/****************************************************************************** * * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * ******************************************************************************/ #ifndef __RTL_WLAN_BITDEF_H__ #define __RTL_WLAN_BITDEF_H__ #include "halmac_hw_cfg.h" #define CPU_OPT_WIDTH 0x1F #if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME BIT(31) #define BIT_SHIFT_GTAB_ID 28 #define BIT_MASK_GTAB_ID 0x7 #define BIT_GTAB_ID(x) (((x) & BIT_MASK_GTAB_ID) << BIT_SHIFT_GTAB_ID) #define BITS_GTAB_ID (BIT_MASK_GTAB_ID << BIT_SHIFT_GTAB_ID) #define BIT_CLEAR_GTAB_ID(x) ((x) & (~BITS_GTAB_ID)) #define BIT_GET_GTAB_ID(x) (((x) >> BIT_SHIFT_GTAB_ID) & BIT_MASK_GTAB_ID) #define BIT_SET_GTAB_ID(x, v) (BIT_CLEAR_GTAB_ID(x) | BIT_GTAB_ID(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) #define BIT_MULRW BIT(27) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) #define BIT_CPRST BIT(23) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) #define BIT_SHIFT_COUNTER_BASE 16 #define BIT_MASK_COUNTER_BASE 0x1fff #define BIT_COUNTER_BASE(x) \ (((x) & BIT_MASK_COUNTER_BASE) << BIT_SHIFT_COUNTER_BASE) #define BITS_COUNTER_BASE (BIT_MASK_COUNTER_BASE << BIT_SHIFT_COUNTER_BASE) #define BIT_CLEAR_COUNTER_BASE(x) ((x) & (~BITS_COUNTER_BASE)) #define BIT_GET_COUNTER_BASE(x) \ (((x) >> BIT_SHIFT_COUNTER_BASE) & BIT_MASK_COUNTER_BASE) #define BIT_SET_COUNTER_BASE(x, v) \ (BIT_CLEAR_COUNTER_BASE(x) | BIT_COUNTER_BASE(v)) #define BIT_SHIFT_AGG_VALUE2 16 #define BIT_MASK_AGG_VALUE2 0x7f #define BIT_AGG_VALUE2(x) (((x) & BIT_MASK_AGG_VALUE2) << BIT_SHIFT_AGG_VALUE2) #define BITS_AGG_VALUE2 (BIT_MASK_AGG_VALUE2 << BIT_SHIFT_AGG_VALUE2) #define BIT_CLEAR_AGG_VALUE2(x) ((x) & (~BITS_AGG_VALUE2)) #define BIT_GET_AGG_VALUE2(x) \ (((x) >> BIT_SHIFT_AGG_VALUE2) & BIT_MASK_AGG_VALUE2) #define BIT_SET_AGG_VALUE2(x, v) (BIT_CLEAR_AGG_VALUE2(x) | BIT_AGG_VALUE2(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1 BIT(15) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) #define BIT_SHIFT_XTAL_DRV_RF1 13 #define BIT_MASK_XTAL_DRV_RF1 0x3 #define BIT_XTAL_DRV_RF1(x) \ (((x) & BIT_MASK_XTAL_DRV_RF1) << BIT_SHIFT_XTAL_DRV_RF1) #define BITS_XTAL_DRV_RF1 (BIT_MASK_XTAL_DRV_RF1 << BIT_SHIFT_XTAL_DRV_RF1) #define BIT_CLEAR_XTAL_DRV_RF1(x) ((x) & (~BITS_XTAL_DRV_RF1)) #define BIT_GET_XTAL_DRV_RF1(x) \ (((x) >> BIT_SHIFT_XTAL_DRV_RF1) & BIT_MASK_XTAL_DRV_RF1) #define BIT_SET_XTAL_DRV_RF1(x, v) \ (BIT_CLEAR_XTAL_DRV_RF1(x) | BIT_XTAL_DRV_RF1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) #define BIT_ATIMEND BIT(12) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) #define BIT_SHIFT_GTAB_ID_V1 12 #define BIT_MASK_GTAB_ID_V1 0x7 #define BIT_GTAB_ID_V1(x) (((x) & BIT_MASK_GTAB_ID_V1) << BIT_SHIFT_GTAB_ID_V1) #define BITS_GTAB_ID_V1 (BIT_MASK_GTAB_ID_V1 << BIT_SHIFT_GTAB_ID_V1) #define BIT_CLEAR_GTAB_ID_V1(x) ((x) & (~BITS_GTAB_ID_V1)) #define BIT_GET_GTAB_ID_V1(x) \ (((x) >> BIT_SHIFT_GTAB_ID_V1) & BIT_MASK_GTAB_ID_V1) #define BIT_SET_GTAB_ID_V1(x, v) (BIT_CLEAR_GTAB_ID_V1(x) | BIT_GTAB_ID_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) #define BIT_SHIFT_WATCH_DOG_RECORD_V1 10 #define BIT_MASK_WATCH_DOG_RECORD_V1 0x3fff #define BIT_WATCH_DOG_RECORD_V1(x) \ (((x) & BIT_MASK_WATCH_DOG_RECORD_V1) << BIT_SHIFT_WATCH_DOG_RECORD_V1) #define BITS_WATCH_DOG_RECORD_V1 \ (BIT_MASK_WATCH_DOG_RECORD_V1 << BIT_SHIFT_WATCH_DOG_RECORD_V1) #define BIT_CLEAR_WATCH_DOG_RECORD_V1(x) ((x) & (~BITS_WATCH_DOG_RECORD_V1)) #define BIT_GET_WATCH_DOG_RECORD_V1(x) \ (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1) & BIT_MASK_WATCH_DOG_RECORD_V1) #define BIT_SET_WATCH_DOG_RECORD_V1(x, v) \ (BIT_CLEAR_WATCH_DOG_RECORD_V1(x) | BIT_WATCH_DOG_RECORD_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) #define BIT_R_8051_SPD BIT(9) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) #define BIT_EN_RTS_REQ BIT(9) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) #define BIT_R_IO_TIMEOUT_FLAG_V1 BIT(9) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) #define BIT_EN_EDCA_REQ BIT(8) #define BIT_SHIFT_AGG_VALUE1 8 #define BIT_MASK_AGG_VALUE1 0x7f #define BIT_AGG_VALUE1(x) (((x) & BIT_MASK_AGG_VALUE1) << BIT_SHIFT_AGG_VALUE1) #define BITS_AGG_VALUE1 (BIT_MASK_AGG_VALUE1 << BIT_SHIFT_AGG_VALUE1) #define BIT_CLEAR_AGG_VALUE1(x) ((x) & (~BITS_AGG_VALUE1)) #define BIT_GET_AGG_VALUE1(x) \ (((x) >> BIT_SHIFT_AGG_VALUE1) & BIT_MASK_AGG_VALUE1) #define BIT_SET_AGG_VALUE1(x, v) (BIT_CLEAR_AGG_VALUE1(x) | BIT_AGG_VALUE1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) #define BIT_EN_WATCH_DOG_V1 BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) #define BIT_DIS_TXDMA_PRE BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) #define BIT_RAM_DL_SEL BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) #define BIT_EN_PTCL_REQ BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) #define BIT_DIS_RXDMA_PRE BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) #define BIT_WINTINI_RDY BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) #define BIT_EN_SCH_REQ BIT(6) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) #define BIT_CLR_HGQ_REQ_BLOCK BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) #define BIT_TXFLAG_EXIT_L1_EN BIT(2) #endif #if (HALMAC_8881A_SUPPORT) #define BIT_AFE_MBIAS BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) #define BIT_MCUFWDL_EN BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) #define BIT_SHIFT_AGG_VALUE0 0 #define BIT_MASK_AGG_VALUE0 0x7f #define BIT_AGG_VALUE0(x) (((x) & BIT_MASK_AGG_VALUE0) << BIT_SHIFT_AGG_VALUE0) #define BITS_AGG_VALUE0 (BIT_MASK_AGG_VALUE0 << BIT_SHIFT_AGG_VALUE0) #define BIT_CLEAR_AGG_VALUE0(x) ((x) & (~BITS_AGG_VALUE0)) #define BIT_GET_AGG_VALUE0(x) \ (((x) >> BIT_SHIFT_AGG_VALUE0) & BIT_MASK_AGG_VALUE0) #define BIT_SET_AGG_VALUE0(x, v) (BIT_CLEAR_AGG_VALUE0(x) | BIT_AGG_VALUE0(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT) #define BIT_SHIFT_MDIO_REG_ADDR 0 #define BIT_MASK_MDIO_REG_ADDR 0x1f #define BIT_MDIO_REG_ADDR(x) \ (((x) & BIT_MASK_MDIO_REG_ADDR) << BIT_SHIFT_MDIO_REG_ADDR) #define BITS_MDIO_REG_ADDR (BIT_MASK_MDIO_REG_ADDR << BIT_SHIFT_MDIO_REG_ADDR) #define BIT_CLEAR_MDIO_REG_ADDR(x) ((x) & (~BITS_MDIO_REG_ADDR)) #define BIT_GET_MDIO_REG_ADDR(x) \ (((x) >> BIT_SHIFT_MDIO_REG_ADDR) & BIT_MASK_MDIO_REG_ADDR) #define BIT_SET_MDIO_REG_ADDR(x, v) \ (BIT_CLEAR_MDIO_REG_ADDR(x) | BIT_MDIO_REG_ADDR(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8822B_SUPPORT) #define BIT_ISO_MD2PP BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ #define BIT_SHIFT_SDIO_INT_TIMEOUT 16 #define BIT_MASK_SDIO_INT_TIMEOUT 0xffff #define BIT_SDIO_INT_TIMEOUT(x) \ (((x) & BIT_MASK_SDIO_INT_TIMEOUT) << BIT_SHIFT_SDIO_INT_TIMEOUT) #define BITS_SDIO_INT_TIMEOUT \ (BIT_MASK_SDIO_INT_TIMEOUT << BIT_SHIFT_SDIO_INT_TIMEOUT) #define BIT_CLEAR_SDIO_INT_TIMEOUT(x) ((x) & (~BITS_SDIO_INT_TIMEOUT)) #define BIT_GET_SDIO_INT_TIMEOUT(x) \ (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT) & BIT_MASK_SDIO_INT_TIMEOUT) #define BIT_SET_SDIO_INT_TIMEOUT(x, v) \ (BIT_CLEAR_SDIO_INT_TIMEOUT(x) | BIT_SDIO_INT_TIMEOUT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_PWC_EV12V BIT(15) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_PWC_EBCOEB BIT(15) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ #define BIT_IO_ERR_STATUS BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_PWC_EV25V BIT(14) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ #define BIT_CMD53_W_MIX BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_PA33V_EN BIT(13) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ #define BIT_CMD53_TX_FORMAT BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_PA12V_EN BIT(12) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_PC_A15V BIT(12) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ #define BIT_CMD53_R_TIMEOUT_MASK BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_UA33V_EN BIT(11) #define BIT_UA12V_EN BIT(10) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_ISO_AFE_OUTPUT_SIGNAL BIT(10) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ #define BIT_SHIFT_CMD53_R_TIMEOUT_UNIT 10 #define BIT_MASK_CMD53_R_TIMEOUT_UNIT 0x3 #define BIT_CMD53_R_TIMEOUT_UNIT(x) \ (((x) & BIT_MASK_CMD53_R_TIMEOUT_UNIT) \ << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT) #define BITS_CMD53_R_TIMEOUT_UNIT \ (BIT_MASK_CMD53_R_TIMEOUT_UNIT << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT) #define BIT_CLEAR_CMD53_R_TIMEOUT_UNIT(x) ((x) & (~BITS_CMD53_R_TIMEOUT_UNIT)) #define BIT_GET_CMD53_R_TIMEOUT_UNIT(x) \ (((x) >> BIT_SHIFT_CMD53_R_TIMEOUT_UNIT) & \ BIT_MASK_CMD53_R_TIMEOUT_UNIT) #define BIT_SET_CMD53_R_TIMEOUT_UNIT(x, v) \ (BIT_CLEAR_CMD53_R_TIMEOUT_UNIT(x) | BIT_CMD53_R_TIMEOUT_UNIT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_ISO_RFDIO BIT(9) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ #define BIT_REPLY_ERRCRC_IN_DATA BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_ISO_EB2CORE BIT(8) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ #define BIT_EN_CMD53_OVERLAP BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_ISO_DIOE BIT(7) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ #define BIT_REPLY_ERR_IN_R5 BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_ISO_DIOP BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_ISO_WLPON2PP BIT(6) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ #define BIT_R18A_EN BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_ISO_IP2MAC_WA2PP BIT(5) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ #define BIT_SDIO_CMD_FORCE_VLD BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_ISO_PD2CORE BIT(4) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ #define BIT_INIT_CMD_EN BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_ISO_PA2PCIE BIT(3) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ #define BIT_EN_32K_TRANS BIT(3) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ #define BIT_RXINT_READ_MASK_DIS BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_ISO_UD2CORE BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ #define BIT_EN_RXDMA_MASK_INT BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_ISO_HD2CORE BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_ISO_UA2USB BIT(1) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ #define BIT_EN_MASK_TIMER BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ #define BIT_ISO_WD2PP BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ #define BIT_CMD_ERR_STOP_INT_EN BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ #define BIT_FEN_MREGEN BIT(15) #define BIT_FEN_HWPDN BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ #define BIT_EN_25_1 BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ #define BIT_FEN_ELDR BIT(12) #define BIT_FEN_DCORE BIT(11) #define BIT_FEN_CPUEN BIT(10) #define BIT_FEN_DIOE BIT(9) #define BIT_FEN_PCIED BIT(8) #define BIT_FEN_PPLL BIT(7) #define BIT_FEN_PCIEA BIT(6) #define BIT_FEN_DIO_PCIE BIT(5) #define BIT_FEN_USBD BIT(4) #define BIT_FEN_UPLL BIT(3) #define BIT_FEN_USBA BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ #define BIT_FEN_BB_GLB_RSTN BIT(1) #define BIT_FEN_BBRSTB BIT(0) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_SOP_EABM BIT(31) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_SKP_ALD BIT(31) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_SOP_ACKF BIT(30) #define BIT_SOP_ERCK BIT(29) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_SOP_ESWR BIT(28) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_SOP_AFEP BIT(28) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_SOP_PWMM BIT(27) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_SOP_EPWM BIT(27) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_SOP_EECK BIT(26) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_ROP_ENXT BIT(25) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_SOP_ANA_CLK_DIVISION_2 BIT(25) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_SOP_EXTL BIT(24) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_CHIPOFF_EN BIT(23) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_SYM_OP_RING_12M BIT(22) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_DIS_USB3_SUS_ALD BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_ROP_SWPR BIT(21) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_DIS_HW_LPLDM BIT(20) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_SOP_ALD BIT(20) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_OPT_SWRST_WLMCU BIT(19) #define BIT_RDY_SYSPWR BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_EN_WLON BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_APDM_HPDN BIT(15) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_HSUS BIT(14) #define BIT_PDN_SEL BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_AFSM_PCIE_SUS_EN BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_AFSM_WLSUS_EN BIT(11) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_APFM_SWLPS BIT(10) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_APFM_SWLPS_EN BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_APFM_OFFMAC BIT(9) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_HW_AUTO_CTRL_EXT_SWR BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_APFN_ONMAC BIT(8) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_USE_INTERNAL_SWR_AND_LDO BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_CHIP_PDN_EN BIT(7) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_BT_SUSEN BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_RDY_MACDIS BIT(6) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_PD_RF BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_RING_CLK_12M_EN BIT(4) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_ENPDN BIT(4) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_CMD11_VOL_SWITCH (Offset 0x10250004) */ #define BIT_SHIFT_CMD11_SEQ_END_DELAY 4 #define BIT_MASK_CMD11_SEQ_END_DELAY 0xf #define BIT_CMD11_SEQ_END_DELAY(x) \ (((x) & BIT_MASK_CMD11_SEQ_END_DELAY) << BIT_SHIFT_CMD11_SEQ_END_DELAY) #define BITS_CMD11_SEQ_END_DELAY \ (BIT_MASK_CMD11_SEQ_END_DELAY << BIT_SHIFT_CMD11_SEQ_END_DELAY) #define BIT_CLEAR_CMD11_SEQ_END_DELAY(x) ((x) & (~BITS_CMD11_SEQ_END_DELAY)) #define BIT_GET_CMD11_SEQ_END_DELAY(x) \ (((x) >> BIT_SHIFT_CMD11_SEQ_END_DELAY) & BIT_MASK_CMD11_SEQ_END_DELAY) #define BIT_SET_CMD11_SEQ_END_DELAY(x, v) \ (BIT_CLEAR_CMD11_SEQ_END_DELAY(x) | BIT_CMD11_SEQ_END_DELAY(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_PFM_WOWL BIT(3) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_SW_WAKE BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_PFM_LDKP BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_WL_HCI_ALD BIT(1) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_PFM_ALDN BIT(1) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_ANA_CLK_DIVISION_2 BIT(1) #define BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL 1 #define BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL 0x7 #define BIT_CMD11_SEQ_SAMPLE_INTERVAL(x) \ (((x) & BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL) \ << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL) #define BITS_CMD11_SEQ_SAMPLE_INTERVAL \ (BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL \ << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL) #define BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL(x) \ ((x) & (~BITS_CMD11_SEQ_SAMPLE_INTERVAL)) #define BIT_GET_CMD11_SEQ_SAMPLE_INTERVAL(x) \ (((x) >> BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL) & \ BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL) #define BIT_SET_CMD11_SEQ_SAMPLE_INTERVAL(x, v) \ (BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL(x) | \ BIT_CMD11_SEQ_SAMPLE_INTERVAL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ #define BIT_PFM_LDALL BIT(0) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_CMD11_VOL_SWITCH (Offset 0x10250004) */ #define BIT_CMD11_SEQ_EN BIT(0) /* 2 REG_SDIO_DRIVING (Offset 0x10250006) */ #define BIT_SHIFT_SDIO_DRV_TYPE_D 12 #define BIT_MASK_SDIO_DRV_TYPE_D 0xf #define BIT_SDIO_DRV_TYPE_D(x) \ (((x) & BIT_MASK_SDIO_DRV_TYPE_D) << BIT_SHIFT_SDIO_DRV_TYPE_D) #define BITS_SDIO_DRV_TYPE_D \ (BIT_MASK_SDIO_DRV_TYPE_D << BIT_SHIFT_SDIO_DRV_TYPE_D) #define BIT_CLEAR_SDIO_DRV_TYPE_D(x) ((x) & (~BITS_SDIO_DRV_TYPE_D)) #define BIT_GET_SDIO_DRV_TYPE_D(x) \ (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_D) & BIT_MASK_SDIO_DRV_TYPE_D) #define BIT_SET_SDIO_DRV_TYPE_D(x, v) \ (BIT_CLEAR_SDIO_DRV_TYPE_D(x) | BIT_SDIO_DRV_TYPE_D(v)) #define BIT_SHIFT_SDIO_DRV_TYPE_C 8 #define BIT_MASK_SDIO_DRV_TYPE_C 0xf #define BIT_SDIO_DRV_TYPE_C(x) \ (((x) & BIT_MASK_SDIO_DRV_TYPE_C) << BIT_SHIFT_SDIO_DRV_TYPE_C) #define BITS_SDIO_DRV_TYPE_C \ (BIT_MASK_SDIO_DRV_TYPE_C << BIT_SHIFT_SDIO_DRV_TYPE_C) #define BIT_CLEAR_SDIO_DRV_TYPE_C(x) ((x) & (~BITS_SDIO_DRV_TYPE_C)) #define BIT_GET_SDIO_DRV_TYPE_C(x) \ (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_C) & BIT_MASK_SDIO_DRV_TYPE_C) #define BIT_SET_SDIO_DRV_TYPE_C(x, v) \ (BIT_CLEAR_SDIO_DRV_TYPE_C(x) | BIT_SDIO_DRV_TYPE_C(v)) #define BIT_SHIFT_SDIO_DRV_TYPE_B 4 #define BIT_MASK_SDIO_DRV_TYPE_B 0xf #define BIT_SDIO_DRV_TYPE_B(x) \ (((x) & BIT_MASK_SDIO_DRV_TYPE_B) << BIT_SHIFT_SDIO_DRV_TYPE_B) #define BITS_SDIO_DRV_TYPE_B \ (BIT_MASK_SDIO_DRV_TYPE_B << BIT_SHIFT_SDIO_DRV_TYPE_B) #define BIT_CLEAR_SDIO_DRV_TYPE_B(x) ((x) & (~BITS_SDIO_DRV_TYPE_B)) #define BIT_GET_SDIO_DRV_TYPE_B(x) \ (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_B) & BIT_MASK_SDIO_DRV_TYPE_B) #define BIT_SET_SDIO_DRV_TYPE_B(x, v) \ (BIT_CLEAR_SDIO_DRV_TYPE_B(x) | BIT_SDIO_DRV_TYPE_B(v)) #define BIT_SHIFT_SDIO_DRV_TYPE_A 0 #define BIT_MASK_SDIO_DRV_TYPE_A 0xf #define BIT_SDIO_DRV_TYPE_A(x) \ (((x) & BIT_MASK_SDIO_DRV_TYPE_A) << BIT_SHIFT_SDIO_DRV_TYPE_A) #define BITS_SDIO_DRV_TYPE_A \ (BIT_MASK_SDIO_DRV_TYPE_A << BIT_SHIFT_SDIO_DRV_TYPE_A) #define BIT_CLEAR_SDIO_DRV_TYPE_A(x) ((x) & (~BITS_SDIO_DRV_TYPE_A)) #define BIT_GET_SDIO_DRV_TYPE_A(x) \ (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_A) & BIT_MASK_SDIO_DRV_TYPE_A) #define BIT_SET_SDIO_DRV_TYPE_A(x, v) \ (BIT_CLEAR_SDIO_DRV_TYPE_A(x) | BIT_SDIO_DRV_TYPE_A(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_CPHY_LDO_CL_EN BIT(19) #define BIT_CPHY_LDO_OK BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_LDO_DUMMY BIT(15) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_ANA_CLK_EN BIT(15) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_DATA_CPU_CLK_EN BIT(15) #define BIT_DATA_CPU_PWC BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_CPU_CLK_EN BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_SYMREG_CLK_EN BIT(13) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_RING_CLK_EN BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_HCI_CLK_EN BIT(12) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_SYS_CLK_EN BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_MAC_CLK_EN BIT(11) #define BIT_SEC_CLK_EN BIT(10) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_CTRL_SPS_PWM_FREQ BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_PHY_SSC_RSTB BIT(9) #define BIT_EXT_32K_EN BIT(8) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_EXT32K_EN BIT(8) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_DISABLE_OPEN_SPS_LDO BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_WL_CLK_TEST BIT(7) #define BIT_OP_SPS_PWM_EN BIT(6) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_SHIFT_MAC_CLK_SEL_V1 6 #define BIT_MASK_MAC_CLK_SEL_V1 0x3 #define BIT_MAC_CLK_SEL_V1(x) \ (((x) & BIT_MASK_MAC_CLK_SEL_V1) << BIT_SHIFT_MAC_CLK_SEL_V1) #define BITS_MAC_CLK_SEL_V1 \ (BIT_MASK_MAC_CLK_SEL_V1 << BIT_SHIFT_MAC_CLK_SEL_V1) #define BIT_CLEAR_MAC_CLK_SEL_V1(x) ((x) & (~BITS_MAC_CLK_SEL_V1)) #define BIT_GET_MAC_CLK_SEL_V1(x) \ (((x) >> BIT_SHIFT_MAC_CLK_SEL_V1) & BIT_MASK_MAC_CLK_SEL_V1) #define BIT_SET_MAC_CLK_SEL_V1(x, v) \ (BIT_CLEAR_MAC_CLK_SEL_V1(x) | BIT_MAC_CLK_SEL_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_LOADER_CLK_EN BIT(5) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_POW_PC_LDO3 BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_MACSLP BIT(4) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_POW_PC_LDO2 BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_WAKEPAD_EN BIT(3) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_ENB_LDO_DIODE_L BIT(3) #define BIT_POW_PC_LDO1 BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_ROMD16V_EN BIT(2) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_AFE_BGEN_PCIE_OP BIT(2) #define BIT_POW_PC_LDO0 BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_CKANA8M_EN BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_CKANA12M_EN BIT(1) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_ANA8M_EN BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_CNTD16V_EN BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ #define BIT_POW_POWER_CUT BIT(0) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_MONITOR (Offset 0x10250008) */ #define BIT_SHIFT_SDIO_INT_START 0 #define BIT_MASK_SDIO_INT_START 0xffffffffL #define BIT_SDIO_INT_START(x) \ (((x) & BIT_MASK_SDIO_INT_START) << BIT_SHIFT_SDIO_INT_START) #define BITS_SDIO_INT_START \ (BIT_MASK_SDIO_INT_START << BIT_SHIFT_SDIO_INT_START) #define BIT_CLEAR_SDIO_INT_START(x) ((x) & (~BITS_SDIO_INT_START)) #define BIT_GET_SDIO_INT_START(x) \ (((x) >> BIT_SHIFT_SDIO_INT_START) & BIT_MASK_SDIO_INT_START) #define BIT_SET_SDIO_INT_START(x, v) \ (BIT_CLEAR_SDIO_INT_START(x) | BIT_SDIO_INT_START(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ #define BIT_SHIFT_VPDIDX 8 #define BIT_MASK_VPDIDX 0xff #define BIT_VPDIDX(x) (((x) & BIT_MASK_VPDIDX) << BIT_SHIFT_VPDIDX) #define BITS_VPDIDX (BIT_MASK_VPDIDX << BIT_SHIFT_VPDIDX) #define BIT_CLEAR_VPDIDX(x) ((x) & (~BITS_VPDIDX)) #define BIT_GET_VPDIDX(x) (((x) >> BIT_SHIFT_VPDIDX) & BIT_MASK_VPDIDX) #define BIT_SET_VPDIDX(x, v) (BIT_CLEAR_VPDIDX(x) | BIT_VPDIDX(v)) #define BIT_SHIFT_EEM1_0 6 #define BIT_MASK_EEM1_0 0x3 #define BIT_EEM1_0(x) (((x) & BIT_MASK_EEM1_0) << BIT_SHIFT_EEM1_0) #define BITS_EEM1_0 (BIT_MASK_EEM1_0 << BIT_SHIFT_EEM1_0) #define BIT_CLEAR_EEM1_0(x) ((x) & (~BITS_EEM1_0)) #define BIT_GET_EEM1_0(x) (((x) >> BIT_SHIFT_EEM1_0) & BIT_MASK_EEM1_0) #define BIT_SET_EEM1_0(x, v) (BIT_CLEAR_EEM1_0(x) | BIT_EEM1_0(v)) #define BIT_AUTOLOAD_SUS BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ #define BIT_EERPOMSEL BIT(4) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ #define BIT_EEPROMSEL BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ #define BIT_EECS_V1 BIT(3) #define BIT_EESK_V1 BIT(2) #define BIT_EEDI_V1 BIT(1) #define BIT_EEDO_V1 BIT(0) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_MONITOR_2 (Offset 0x1025000C) */ #define BIT_CMD53_WT_EN BIT(23) #define BIT_SHIFT_SDIO_CLK_MONITOR 21 #define BIT_MASK_SDIO_CLK_MONITOR 0x3 #define BIT_SDIO_CLK_MONITOR(x) \ (((x) & BIT_MASK_SDIO_CLK_MONITOR) << BIT_SHIFT_SDIO_CLK_MONITOR) #define BITS_SDIO_CLK_MONITOR \ (BIT_MASK_SDIO_CLK_MONITOR << BIT_SHIFT_SDIO_CLK_MONITOR) #define BIT_CLEAR_SDIO_CLK_MONITOR(x) ((x) & (~BITS_SDIO_CLK_MONITOR)) #define BIT_GET_SDIO_CLK_MONITOR(x) \ (((x) >> BIT_SHIFT_SDIO_CLK_MONITOR) & BIT_MASK_SDIO_CLK_MONITOR) #define BIT_SET_SDIO_CLK_MONITOR(x, v) \ (BIT_CLEAR_SDIO_CLK_MONITOR(x) | BIT_SDIO_CLK_MONITOR(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_EE_VPD (Offset 0x000C) */ #define BIT_SHIFT_VPD_DATA 0 #define BIT_MASK_VPD_DATA 0xffffffffL #define BIT_VPD_DATA(x) (((x) & BIT_MASK_VPD_DATA) << BIT_SHIFT_VPD_DATA) #define BITS_VPD_DATA (BIT_MASK_VPD_DATA << BIT_SHIFT_VPD_DATA) #define BIT_CLEAR_VPD_DATA(x) ((x) & (~BITS_VPD_DATA)) #define BIT_GET_VPD_DATA(x) (((x) >> BIT_SHIFT_VPD_DATA) & BIT_MASK_VPD_DATA) #define BIT_SET_VPD_DATA(x, v) (BIT_CLEAR_VPD_DATA(x) | BIT_VPD_DATA(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_EE_VPD (Offset 0x000C) */ #define BIT_SHIFT_VDP_DATA 0 #define BIT_MASK_VDP_DATA 0xffffffffL #define BIT_VDP_DATA(x) (((x) & BIT_MASK_VDP_DATA) << BIT_SHIFT_VDP_DATA) #define BITS_VDP_DATA (BIT_MASK_VDP_DATA << BIT_SHIFT_VDP_DATA) #define BIT_CLEAR_VDP_DATA(x) ((x) & (~BITS_VDP_DATA)) #define BIT_GET_VDP_DATA(x) (((x) >> BIT_SHIFT_VDP_DATA) & BIT_MASK_VDP_DATA) #define BIT_SET_VDP_DATA(x, v) (BIT_CLEAR_VDP_DATA(x) | BIT_VDP_DATA(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_MONITOR_2 (Offset 0x1025000C) */ #define BIT_SHIFT_SDIO_CLK_CNT 0 #define BIT_MASK_SDIO_CLK_CNT 0x1fffff #define BIT_SDIO_CLK_CNT(x) \ (((x) & BIT_MASK_SDIO_CLK_CNT) << BIT_SHIFT_SDIO_CLK_CNT) #define BITS_SDIO_CLK_CNT (BIT_MASK_SDIO_CLK_CNT << BIT_SHIFT_SDIO_CLK_CNT) #define BIT_CLEAR_SDIO_CLK_CNT(x) ((x) & (~BITS_SDIO_CLK_CNT)) #define BIT_GET_SDIO_CLK_CNT(x) \ (((x) >> BIT_SHIFT_SDIO_CLK_CNT) & BIT_MASK_SDIO_CLK_CNT) #define BIT_SET_SDIO_CLK_CNT(x, v) \ (BIT_CLEAR_SDIO_CLK_CNT(x) | BIT_SDIO_CLK_CNT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SW18_C2_BIT0 BIT(31) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_C2_L_BIT0 BIT(31) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SHIFT_R1_L1_V1 30 #define BIT_MASK_R1_L1_V1 0x3 #define BIT_R1_L1_V1(x) (((x) & BIT_MASK_R1_L1_V1) << BIT_SHIFT_R1_L1_V1) #define BITS_R1_L1_V1 (BIT_MASK_R1_L1_V1 << BIT_SHIFT_R1_L1_V1) #define BIT_CLEAR_R1_L1_V1(x) ((x) & (~BITS_R1_L1_V1)) #define BIT_GET_R1_L1_V1(x) (((x) >> BIT_SHIFT_R1_L1_V1) & BIT_MASK_R1_L1_V1) #define BIT_SET_R1_L1_V1(x, v) (BIT_CLEAR_R1_L1_V1(x) | BIT_R1_L1_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SHIFT_SW18_C1 29 #define BIT_MASK_SW18_C1 0x3 #define BIT_SW18_C1(x) (((x) & BIT_MASK_SW18_C1) << BIT_SHIFT_SW18_C1) #define BITS_SW18_C1 (BIT_MASK_SW18_C1 << BIT_SHIFT_SW18_C1) #define BIT_CLEAR_SW18_C1(x) ((x) & (~BITS_SW18_C1)) #define BIT_GET_SW18_C1(x) (((x) >> BIT_SHIFT_SW18_C1) & BIT_MASK_SW18_C1) #define BIT_SET_SW18_C1(x, v) (BIT_CLEAR_SW18_C1(x) | BIT_SW18_C1(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SHIFT_C1_L 29 #define BIT_MASK_C1_L 0x3 #define BIT_C1_L(x) (((x) & BIT_MASK_C1_L) << BIT_SHIFT_C1_L) #define BITS_C1_L (BIT_MASK_C1_L << BIT_SHIFT_C1_L) #define BIT_CLEAR_C1_L(x) ((x) & (~BITS_C1_L)) #define BIT_GET_C1_L(x) (((x) >> BIT_SHIFT_C1_L) & BIT_MASK_C1_L) #define BIT_SET_C1_L(x, v) (BIT_CLEAR_C1_L(x) | BIT_C1_L(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SHIFT_C3_L1_V1 28 #define BIT_MASK_C3_L1_V1 0x3 #define BIT_C3_L1_V1(x) (((x) & BIT_MASK_C3_L1_V1) << BIT_SHIFT_C3_L1_V1) #define BITS_C3_L1_V1 (BIT_MASK_C3_L1_V1 << BIT_SHIFT_C3_L1_V1) #define BIT_CLEAR_C3_L1_V1(x) ((x) & (~BITS_C3_L1_V1)) #define BIT_GET_C3_L1_V1(x) (((x) >> BIT_SHIFT_C3_L1_V1) & BIT_MASK_C3_L1_V1) #define BIT_SET_C3_L1_V1(x, v) (BIT_CLEAR_C3_L1_V1(x) | BIT_C3_L1_V1(v)) #define BIT_SHIFT_C2_L1_V1 26 #define BIT_MASK_C2_L1_V1 0x3 #define BIT_C2_L1_V1(x) (((x) & BIT_MASK_C2_L1_V1) << BIT_SHIFT_C2_L1_V1) #define BITS_C2_L1_V1 (BIT_MASK_C2_L1_V1 << BIT_SHIFT_C2_L1_V1) #define BIT_CLEAR_C2_L1_V1(x) ((x) & (~BITS_C2_L1_V1)) #define BIT_GET_C2_L1_V1(x) (((x) >> BIT_SHIFT_C2_L1_V1) & BIT_MASK_C2_L1_V1) #define BIT_SET_C2_L1_V1(x, v) (BIT_CLEAR_C2_L1_V1(x) | BIT_C2_L1_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SHIFT_REG_FREQ_L 25 #define BIT_MASK_REG_FREQ_L 0x7 #define BIT_REG_FREQ_L(x) (((x) & BIT_MASK_REG_FREQ_L) << BIT_SHIFT_REG_FREQ_L) #define BITS_REG_FREQ_L (BIT_MASK_REG_FREQ_L << BIT_SHIFT_REG_FREQ_L) #define BIT_CLEAR_REG_FREQ_L(x) ((x) & (~BITS_REG_FREQ_L)) #define BIT_GET_REG_FREQ_L(x) \ (((x) >> BIT_SHIFT_REG_FREQ_L) & BIT_MASK_REG_FREQ_L) #define BIT_SET_REG_FREQ_L(x, v) (BIT_CLEAR_REG_FREQ_L(x) | BIT_REG_FREQ_L(v)) #define BIT_REG_EN_DUTY BIT(24) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SHIFT_C1_L1_V1 24 #define BIT_MASK_C1_L1_V1 0x3 #define BIT_C1_L1_V1(x) (((x) & BIT_MASK_C1_L1_V1) << BIT_SHIFT_C1_L1_V1) #define BITS_C1_L1_V1 (BIT_MASK_C1_L1_V1 << BIT_SHIFT_C1_L1_V1) #define BIT_CLEAR_C1_L1_V1(x) ((x) & (~BITS_C1_L1_V1)) #define BIT_GET_C1_L1_V1(x) (((x) >> BIT_SHIFT_C1_L1_V1) & BIT_MASK_C1_L1_V1) #define BIT_SET_C1_L1_V1(x, v) (BIT_CLEAR_C1_L1_V1(x) | BIT_C1_L1_V1(v)) #define BIT_REG_TYPE_L_V3 BIT(23) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SHIFT_REG_MODE 22 #define BIT_MASK_REG_MODE 0x3 #define BIT_REG_MODE(x) (((x) & BIT_MASK_REG_MODE) << BIT_SHIFT_REG_MODE) #define BITS_REG_MODE (BIT_MASK_REG_MODE << BIT_SHIFT_REG_MODE) #define BIT_CLEAR_REG_MODE(x) ((x) & (~BITS_REG_MODE)) #define BIT_GET_REG_MODE(x) (((x) >> BIT_SHIFT_REG_MODE) & BIT_MASK_REG_MODE) #define BIT_SET_REG_MODE(x, v) (BIT_CLEAR_REG_MODE(x) | BIT_REG_MODE(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_FPWM_L1_V1 BIT(22) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_REG_EN_SP BIT(21) #define BIT_REG_AUTO_L BIT(20) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SW18_SELD_BIT0 BIT(19) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SHIFT_V15ADJ_L1 19 #define BIT_MASK_V15ADJ_L1 0x7 #define BIT_V15ADJ_L1(x) (((x) & BIT_MASK_V15ADJ_L1) << BIT_SHIFT_V15ADJ_L1) #define BITS_V15ADJ_L1 (BIT_MASK_V15ADJ_L1 << BIT_SHIFT_V15ADJ_L1) #define BIT_CLEAR_V15ADJ_L1(x) ((x) & (~BITS_V15ADJ_L1)) #define BIT_GET_V15ADJ_L1(x) (((x) >> BIT_SHIFT_V15ADJ_L1) & BIT_MASK_V15ADJ_L1) #define BIT_SET_V15ADJ_L1(x, v) (BIT_CLEAR_V15ADJ_L1(x) | BIT_V15ADJ_L1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SW18_POWOCP BIT(18) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SHIFT_IN_L1 16 #define BIT_MASK_IN_L1 0x7 #define BIT_IN_L1(x) (((x) & BIT_MASK_IN_L1) << BIT_SHIFT_IN_L1) #define BITS_IN_L1 (BIT_MASK_IN_L1 << BIT_SHIFT_IN_L1) #define BIT_CLEAR_IN_L1(x) ((x) & (~BITS_IN_L1)) #define BIT_GET_IN_L1(x) (((x) >> BIT_SHIFT_IN_L1) & BIT_MASK_IN_L1) #define BIT_SET_IN_L1(x, v) (BIT_CLEAR_IN_L1(x) | BIT_IN_L1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SHIFT_SW18_OCP 15 #define BIT_MASK_SW18_OCP 0x7 #define BIT_SW18_OCP(x) (((x) & BIT_MASK_SW18_OCP) << BIT_SHIFT_SW18_OCP) #define BITS_SW18_OCP (BIT_MASK_SW18_OCP << BIT_SHIFT_SW18_OCP) #define BIT_CLEAR_SW18_OCP(x) ((x) & (~BITS_SW18_OCP)) #define BIT_GET_SW18_OCP(x) (((x) >> BIT_SHIFT_SW18_OCP) & BIT_MASK_SW18_OCP) #define BIT_SET_SW18_OCP(x, v) (BIT_CLEAR_SW18_OCP(x) | BIT_SW18_OCP(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SHIFT_OCP_L1 15 #define BIT_MASK_OCP_L1 0x7 #define BIT_OCP_L1(x) (((x) & BIT_MASK_OCP_L1) << BIT_SHIFT_OCP_L1) #define BITS_OCP_L1 (BIT_MASK_OCP_L1 << BIT_SHIFT_OCP_L1) #define BIT_CLEAR_OCP_L1(x) ((x) & (~BITS_OCP_L1)) #define BIT_GET_OCP_L1(x) (((x) >> BIT_SHIFT_OCP_L1) & BIT_MASK_OCP_L1) #define BIT_SET_OCP_L1(x, v) (BIT_CLEAR_OCP_L1(x) | BIT_OCP_L1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SHIFT_STD_L1 14 #define BIT_MASK_STD_L1 0x3 #define BIT_STD_L1(x) (((x) & BIT_MASK_STD_L1) << BIT_SHIFT_STD_L1) #define BITS_STD_L1 (BIT_MASK_STD_L1 << BIT_SHIFT_STD_L1) #define BIT_CLEAR_STD_L1(x) ((x) & (~BITS_STD_L1)) #define BIT_GET_STD_L1(x) (((x) >> BIT_SHIFT_STD_L1) & BIT_MASK_STD_L1) #define BIT_SET_STD_L1(x, v) (BIT_CLEAR_STD_L1(x) | BIT_STD_L1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SHIFT_CF_L_BIT0_TO_1 13 #define BIT_MASK_CF_L_BIT0_TO_1 0x3 #define BIT_CF_L_BIT0_TO_1(x) \ (((x) & BIT_MASK_CF_L_BIT0_TO_1) << BIT_SHIFT_CF_L_BIT0_TO_1) #define BITS_CF_L_BIT0_TO_1 \ (BIT_MASK_CF_L_BIT0_TO_1 << BIT_SHIFT_CF_L_BIT0_TO_1) #define BIT_CLEAR_CF_L_BIT0_TO_1(x) ((x) & (~BITS_CF_L_BIT0_TO_1)) #define BIT_GET_CF_L_BIT0_TO_1(x) \ (((x) >> BIT_SHIFT_CF_L_BIT0_TO_1) & BIT_MASK_CF_L_BIT0_TO_1) #define BIT_SET_CF_L_BIT0_TO_1(x, v) \ (BIT_CLEAR_CF_L_BIT0_TO_1(x) | BIT_CF_L_BIT0_TO_1(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SHIFT_CF_L 13 #define BIT_MASK_CF_L 0x3 #define BIT_CF_L(x) (((x) & BIT_MASK_CF_L) << BIT_SHIFT_CF_L) #define BITS_CF_L (BIT_MASK_CF_L << BIT_SHIFT_CF_L) #define BIT_CLEAR_CF_L(x) ((x) & (~BITS_CF_L)) #define BIT_GET_CF_L(x) (((x) >> BIT_SHIFT_CF_L) & BIT_MASK_CF_L) #define BIT_SET_CF_L(x, v) (BIT_CLEAR_CF_L(x) | BIT_CF_L(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SW18_FPWM BIT(11) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SHIFT_VOL_L1 10 #define BIT_MASK_VOL_L1 0xf #define BIT_VOL_L1(x) (((x) & BIT_MASK_VOL_L1) << BIT_SHIFT_VOL_L1) #define BITS_VOL_L1 (BIT_MASK_VOL_L1 << BIT_SHIFT_VOL_L1) #define BIT_CLEAR_VOL_L1(x) ((x) & (~BITS_VOL_L1)) #define BIT_GET_VOL_L1(x) (((x) >> BIT_SHIFT_VOL_L1) & BIT_MASK_VOL_L1) #define BIT_SET_VOL_L1(x, v) (BIT_CLEAR_VOL_L1(x) | BIT_VOL_L1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_SW18_SWEN BIT(9) #define BIT_SW18_LDEN BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_MAC_ID_EN BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_WL_CTRL_XTAL_CADJ BIT(6) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_LDO11_EN BIT(6) #define BIT_AFE_P3_PC BIT(5) #define BIT_AFE_P2_PC BIT(4) #define BIT_AFE_P1_PC BIT(3) #define BIT_AFE_P0_PC BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ #define BIT_AFE_BGEN BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_POW_ZCD_L BIT(31) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_IO_READY_SIGNAL_ERR_MSK BIT(31) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_CRCERR_MSK BIT(31) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_ENABLE_ZCDOUT_L BIT(30) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_TX_CRC__MSK BIT(30) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_HSISR3_IND_MSK BIT(30) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_AUTOZCD_L BIT(30) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_HSISR2_IND_MSK BIT(29) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_REG_DELAY 28 #define BIT_MASK_REG_DELAY 0x3 #define BIT_REG_DELAY(x) (((x) & BIT_MASK_REG_DELAY) << BIT_SHIFT_REG_DELAY) #define BITS_REG_DELAY (BIT_MASK_REG_DELAY << BIT_SHIFT_REG_DELAY) #define BIT_CLEAR_REG_DELAY(x) ((x) & (~BITS_REG_DELAY)) #define BIT_GET_REG_DELAY(x) (((x) >> BIT_SHIFT_REG_DELAY) & BIT_MASK_REG_DELAY) #define BIT_SET_REG_DELAY(x, v) (BIT_CLEAR_REG_DELAY(x) | BIT_REG_DELAY(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_HEISR_IND_MSK BIT(28) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_CTWEND_MSK BIT(27) #define BIT_SDIO_ATIMEND_E_MSK BIT(26) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_ATIMEND_MSK BIT(25) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIIO_ATIMEND_MSK BIT(25) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_SW18_V15ADJ 24 #define BIT_MASK_SW18_V15ADJ 0x7 #define BIT_SW18_V15ADJ(x) \ (((x) & BIT_MASK_SW18_V15ADJ) << BIT_SHIFT_SW18_V15ADJ) #define BITS_SW18_V15ADJ (BIT_MASK_SW18_V15ADJ << BIT_SHIFT_SW18_V15ADJ) #define BIT_CLEAR_SW18_V15ADJ(x) ((x) & (~BITS_SW18_V15ADJ)) #define BIT_GET_SW18_V15ADJ(x) \ (((x) >> BIT_SHIFT_SW18_V15ADJ) & BIT_MASK_SW18_V15ADJ) #define BIT_SET_SW18_V15ADJ(x, v) \ (BIT_CLEAR_SW18_V15ADJ(x) | BIT_SW18_V15ADJ(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_OCPINT_MSK BIT(24) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_OCPSL BIT(24) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_V15ADJ_L1_V1 24 #define BIT_MASK_V15ADJ_L1_V1 0x7 #define BIT_V15ADJ_L1_V1(x) \ (((x) & BIT_MASK_V15ADJ_L1_V1) << BIT_SHIFT_V15ADJ_L1_V1) #define BITS_V15ADJ_L1_V1 (BIT_MASK_V15ADJ_L1_V1 << BIT_SHIFT_V15ADJ_L1_V1) #define BIT_CLEAR_V15ADJ_L1_V1(x) ((x) & (~BITS_V15ADJ_L1_V1)) #define BIT_GET_V15ADJ_L1_V1(x) \ (((x) >> BIT_SHIFT_V15ADJ_L1_V1) & BIT_MASK_V15ADJ_L1_V1) #define BIT_SET_V15ADJ_L1_V1(x, v) \ (BIT_CLEAR_V15ADJ_L1_V1(x) | BIT_V15ADJ_L1_V1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_PSTIMEOUT_MSK BIT(23) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_REG_LDOF_L_V1 BIT(23) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_GTINT4_MSK BIT(22) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_PARSW_DUMMY BIT(22) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_GTINT3_MSK BIT(21) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_CLAMP_MAX_DUTY BIT(21) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_SW18_VOL 20 #define BIT_MASK_SW18_VOL 0xf #define BIT_SW18_VOL(x) (((x) & BIT_MASK_SW18_VOL) << BIT_SHIFT_SW18_VOL) #define BITS_SW18_VOL (BIT_MASK_SW18_VOL << BIT_SHIFT_SW18_VOL) #define BIT_CLEAR_SW18_VOL(x) ((x) & (~BITS_SW18_VOL)) #define BIT_GET_SW18_VOL(x) (((x) >> BIT_SHIFT_SW18_VOL) & BIT_MASK_SW18_VOL) #define BIT_SET_SW18_VOL(x, v) (BIT_CLEAR_SW18_VOL(x) | BIT_SW18_VOL(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_HSISR_IND_MSK BIT(20) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_VOL_L1_V1 20 #define BIT_MASK_VOL_L1_V1 0xf #define BIT_VOL_L1_V1(x) (((x) & BIT_MASK_VOL_L1_V1) << BIT_SHIFT_VOL_L1_V1) #define BITS_VOL_L1_V1 (BIT_MASK_VOL_L1_V1 << BIT_SHIFT_VOL_L1_V1) #define BIT_CLEAR_VOL_L1_V1(x) ((x) & (~BITS_VOL_L1_V1)) #define BIT_GET_VOL_L1_V1(x) (((x) >> BIT_SHIFT_VOL_L1_V1) & BIT_MASK_VOL_L1_V1) #define BIT_SET_VOL_L1_V1(x, v) (BIT_CLEAR_VOL_L1_V1(x) | BIT_VOL_L1_V1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_CPWM2_MSK BIT(19) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_TBOX_L1_V1 19 #define BIT_MASK_TBOX_L1_V1 0x3 #define BIT_TBOX_L1_V1(x) (((x) & BIT_MASK_TBOX_L1_V1) << BIT_SHIFT_TBOX_L1_V1) #define BITS_TBOX_L1_V1 (BIT_MASK_TBOX_L1_V1 << BIT_SHIFT_TBOX_L1_V1) #define BIT_CLEAR_TBOX_L1_V1(x) ((x) & (~BITS_TBOX_L1_V1)) #define BIT_GET_TBOX_L1_V1(x) \ (((x) >> BIT_SHIFT_TBOX_L1_V1) & BIT_MASK_TBOX_L1_V1) #define BIT_SET_TBOX_L1_V1(x, v) (BIT_CLEAR_TBOX_L1_V1(x) | BIT_TBOX_L1_V1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_CPWM1_MSK BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_SW18_IN 17 #define BIT_MASK_SW18_IN 0x7 #define BIT_SW18_IN(x) (((x) & BIT_MASK_SW18_IN) << BIT_SHIFT_SW18_IN) #define BITS_SW18_IN (BIT_MASK_SW18_IN << BIT_SHIFT_SW18_IN) #define BIT_CLEAR_SW18_IN(x) ((x) & (~BITS_SW18_IN)) #define BIT_GET_SW18_IN(x) (((x) >> BIT_SHIFT_SW18_IN) & BIT_MASK_SW18_IN) #define BIT_SET_SW18_IN(x, v) (BIT_CLEAR_SW18_IN(x) | BIT_SW18_IN(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_C2HCMD_INT_MSK BIT(17) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_REG_DELAY_V3 17 #define BIT_MASK_REG_DELAY_V3 0x3 #define BIT_REG_DELAY_V3(x) \ (((x) & BIT_MASK_REG_DELAY_V3) << BIT_SHIFT_REG_DELAY_V3) #define BITS_REG_DELAY_V3 (BIT_MASK_REG_DELAY_V3 << BIT_SHIFT_REG_DELAY_V3) #define BIT_CLEAR_REG_DELAY_V3(x) ((x) & (~BITS_REG_DELAY_V3)) #define BIT_GET_REG_DELAY_V3(x) \ (((x) >> BIT_SHIFT_REG_DELAY_V3) & BIT_MASK_REG_DELAY_V3) #define BIT_SET_REG_DELAY_V3(x, v) \ (BIT_CLEAR_REG_DELAY_V3(x) | BIT_REG_DELAY_V3(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_IN_L1_V1 17 #define BIT_MASK_IN_L1_V1 0x7 #define BIT_IN_L1_V1(x) (((x) & BIT_MASK_IN_L1_V1) << BIT_SHIFT_IN_L1_V1) #define BITS_IN_L1_V1 (BIT_MASK_IN_L1_V1 << BIT_SHIFT_IN_L1_V1) #define BIT_CLEAR_IN_L1_V1(x) ((x) & (~BITS_IN_L1_V1)) #define BIT_GET_IN_L1_V1(x) (((x) >> BIT_SHIFT_IN_L1_V1) & BIT_MASK_IN_L1_V1) #define BIT_SET_IN_L1_V1(x, v) (BIT_CLEAR_IN_L1_V1(x) | BIT_IN_L1_V1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_BCNERLY_INT_MSK BIT(16) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_REG_CLAMP_D_L_V2 BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_SW18_TBOX 15 #define BIT_MASK_SW18_TBOX 0x3 #define BIT_SW18_TBOX(x) (((x) & BIT_MASK_SW18_TBOX) << BIT_SHIFT_SW18_TBOX) #define BITS_SW18_TBOX (BIT_MASK_SW18_TBOX << BIT_SHIFT_SW18_TBOX) #define BIT_CLEAR_SW18_TBOX(x) ((x) & (~BITS_SW18_TBOX)) #define BIT_GET_SW18_TBOX(x) (((x) >> BIT_SHIFT_SW18_TBOX) & BIT_MASK_SW18_TBOX) #define BIT_SET_SW18_TBOX(x, v) (BIT_CLEAR_SW18_TBOX(x) | BIT_SW18_TBOX(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_REG_BYPASS_L_V3 BIT(15) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_TBOX_L1 15 #define BIT_MASK_TBOX_L1 0x3 #define BIT_TBOX_L1(x) (((x) & BIT_MASK_TBOX_L1) << BIT_SHIFT_TBOX_L1) #define BITS_TBOX_L1 (BIT_MASK_TBOX_L1 << BIT_SHIFT_TBOX_L1) #define BIT_CLEAR_TBOX_L1(x) ((x) & (~BITS_TBOX_L1)) #define BIT_GET_TBOX_L1(x) (((x) >> BIT_SHIFT_TBOX_L1) & BIT_MASK_TBOX_L1) #define BIT_SET_TBOX_L1(x, v) (BIT_CLEAR_TBOX_L1(x) | BIT_TBOX_L1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_ENABLE_ZCDOUT_L_V3 BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SW18_SEL BIT(13) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_POW_ZCD_L_V3 BIT(13) #define BIT_AREN_L1_V1 BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_SW18_STD 11 #define BIT_MASK_SW18_STD 0x3 #define BIT_SW18_STD(x) (((x) & BIT_MASK_SW18_STD) << BIT_SHIFT_SW18_STD) #define BITS_SW18_STD (BIT_MASK_SW18_STD << BIT_SHIFT_SW18_STD) #define BIT_CLEAR_SW18_STD(x) ((x) & (~BITS_SW18_STD)) #define BIT_GET_SW18_STD(x) (((x) >> BIT_SHIFT_SW18_STD) & BIT_MASK_SW18_STD) #define BIT_SET_SW18_STD(x, v) (BIT_CLEAR_SW18_STD(x) | BIT_SW18_STD(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SW18_SD BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SW18_AREN BIT(9) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_OCP_V3 9 #define BIT_MASK_OCP_V3 0x7 #define BIT_OCP_V3(x) (((x) & BIT_MASK_OCP_V3) << BIT_SHIFT_OCP_V3) #define BITS_OCP_V3 (BIT_MASK_OCP_V3 << BIT_SHIFT_OCP_V3) #define BIT_CLEAR_OCP_V3(x) ((x) & (~BITS_OCP_V3)) #define BIT_GET_OCP_V3(x) (((x) >> BIT_SHIFT_OCP_V3) & BIT_MASK_OCP_V3) #define BIT_SET_OCP_V3(x, v) (BIT_CLEAR_OCP_V3(x) | BIT_OCP_V3(v)) #define BIT_POWOCP_V3 BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_SW18_R3 7 #define BIT_MASK_SW18_R3 0x3 #define BIT_SW18_R3(x) (((x) & BIT_MASK_SW18_R3) << BIT_SHIFT_SW18_R3) #define BITS_SW18_R3 (BIT_MASK_SW18_R3 << BIT_SHIFT_SW18_R3) #define BIT_CLEAR_SW18_R3(x) ((x) & (~BITS_SW18_R3)) #define BIT_GET_SW18_R3(x) (((x) >> BIT_SHIFT_SW18_R3) & BIT_MASK_SW18_R3) #define BIT_SET_SW18_R3(x, v) (BIT_CLEAR_SW18_R3(x) | BIT_SW18_R3(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_TXBCNERR_MSK BIT(7) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_R3_L 7 #define BIT_MASK_R3_L 0x3 #define BIT_R3_L(x) (((x) & BIT_MASK_R3_L) << BIT_SHIFT_R3_L) #define BITS_R3_L (BIT_MASK_R3_L << BIT_SHIFT_R3_L) #define BIT_CLEAR_R3_L(x) ((x) & (~BITS_R3_L)) #define BIT_GET_R3_L(x) (((x) >> BIT_SHIFT_R3_L) & BIT_MASK_R3_L) #define BIT_SET_R3_L(x, v) (BIT_CLEAR_R3_L(x) | BIT_R3_L(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_TXBCNOK_MSK BIT(6) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_CF_L_V3 6 #define BIT_MASK_CF_L_V3 0x3 #define BIT_CF_L_V3(x) (((x) & BIT_MASK_CF_L_V3) << BIT_SHIFT_CF_L_V3) #define BITS_CF_L_V3 (BIT_MASK_CF_L_V3 << BIT_SHIFT_CF_L_V3) #define BIT_CLEAR_CF_L_V3(x) ((x) & (~BITS_CF_L_V3)) #define BIT_GET_CF_L_V3(x) (((x) >> BIT_SHIFT_CF_L_V3) & BIT_MASK_CF_L_V3) #define BIT_SET_CF_L_V3(x, v) (BIT_CLEAR_CF_L_V3(x) | BIT_CF_L_V3(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_SW18_R2 5 #define BIT_MASK_SW18_R2 0x3 #define BIT_SW18_R2(x) (((x) & BIT_MASK_SW18_R2) << BIT_SHIFT_SW18_R2) #define BITS_SW18_R2 (BIT_MASK_SW18_R2 << BIT_SHIFT_SW18_R2) #define BIT_CLEAR_SW18_R2(x) ((x) & (~BITS_SW18_R2)) #define BIT_GET_SW18_R2(x) (((x) >> BIT_SHIFT_SW18_R2) & BIT_MASK_SW18_R2) #define BIT_SET_SW18_R2(x, v) (BIT_CLEAR_SW18_R2(x) | BIT_SW18_R2(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_RXFOVW_MSK BIT(5) #define BIT_SDIO_TXFOVW_MSK BIT(4) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_CFC_L_BIT0_TO_1_V1 4 #define BIT_MASK_CFC_L_BIT0_TO_1_V1 0x3 #define BIT_CFC_L_BIT0_TO_1_V1(x) \ (((x) & BIT_MASK_CFC_L_BIT0_TO_1_V1) << BIT_SHIFT_CFC_L_BIT0_TO_1_V1) #define BITS_CFC_L_BIT0_TO_1_V1 \ (BIT_MASK_CFC_L_BIT0_TO_1_V1 << BIT_SHIFT_CFC_L_BIT0_TO_1_V1) #define BIT_CLEAR_CFC_L_BIT0_TO_1_V1(x) ((x) & (~BITS_CFC_L_BIT0_TO_1_V1)) #define BIT_GET_CFC_L_BIT0_TO_1_V1(x) \ (((x) >> BIT_SHIFT_CFC_L_BIT0_TO_1_V1) & BIT_MASK_CFC_L_BIT0_TO_1_V1) #define BIT_SET_CFC_L_BIT0_TO_1_V1(x, v) \ (BIT_CLEAR_CFC_L_BIT0_TO_1_V1(x) | BIT_CFC_L_BIT0_TO_1_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_SW18_R1 3 #define BIT_MASK_SW18_R1 0x3 #define BIT_SW18_R1(x) (((x) & BIT_MASK_SW18_R1) << BIT_SHIFT_SW18_R1) #define BITS_SW18_R1 (BIT_MASK_SW18_R1 << BIT_SHIFT_SW18_R1) #define BIT_CLEAR_SW18_R1(x) ((x) & (~BITS_SW18_R1)) #define BIT_GET_SW18_R1(x) (((x) >> BIT_SHIFT_SW18_R1) & BIT_MASK_SW18_R1) #define BIT_SET_SW18_R1(x, v) (BIT_CLEAR_SW18_R1(x) | BIT_SW18_R1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_RXERR_MSK BIT(3) #define BIT_SDIO_TXERR_MSK BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_R3_L1_V1 2 #define BIT_MASK_R3_L1_V1 0x3 #define BIT_R3_L1_V1(x) (((x) & BIT_MASK_R3_L1_V1) << BIT_SHIFT_R3_L1_V1) #define BITS_R3_L1_V1 (BIT_MASK_R3_L1_V1 << BIT_SHIFT_R3_L1_V1) #define BIT_CLEAR_R3_L1_V1(x) ((x) & (~BITS_R3_L1_V1)) #define BIT_GET_R3_L1_V1(x) (((x) >> BIT_SHIFT_R3_L1_V1) & BIT_MASK_R3_L1_V1) #define BIT_SET_R3_L1_V1(x, v) (BIT_CLEAR_R3_L1_V1(x) | BIT_R3_L1_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_SW18_C3 1 #define BIT_MASK_SW18_C3 0x3 #define BIT_SW18_C3(x) (((x) & BIT_MASK_SW18_C3) << BIT_SHIFT_SW18_C3) #define BITS_SW18_C3 (BIT_MASK_SW18_C3 << BIT_SHIFT_SW18_C3) #define BIT_CLEAR_SW18_C3(x) ((x) & (~BITS_SW18_C3)) #define BIT_GET_SW18_C3(x) (((x) >> BIT_SHIFT_SW18_C3) & BIT_MASK_SW18_C3) #define BIT_SET_SW18_C3(x, v) (BIT_CLEAR_SW18_C3(x) | BIT_SW18_C3(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_SDIO_AVAL_MSK BIT(1) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_C3_L_C3 1 #define BIT_MASK_C3_L_C3 0x3 #define BIT_C3_L_C3(x) (((x) & BIT_MASK_C3_L_C3) << BIT_SHIFT_C3_L_C3) #define BITS_C3_L_C3 (BIT_MASK_C3_L_C3 << BIT_SHIFT_C3_L_C3) #define BIT_CLEAR_C3_L_C3(x) ((x) & (~BITS_C3_L_C3)) #define BIT_GET_C3_L_C3(x) (((x) >> BIT_SHIFT_C3_L_C3) & BIT_MASK_C3_L_C3) #define BIT_SET_C3_L_C3(x, v) (BIT_CLEAR_C3_L_C3(x) | BIT_C3_L_C3(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SW18_C2_BIT1 BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ #define BIT_RX_REQUEST_MSK BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_SHIFT_R2_L1_V1 0 #define BIT_MASK_R2_L1_V1 0x3 #define BIT_R2_L1_V1(x) (((x) & BIT_MASK_R2_L1_V1) << BIT_SHIFT_R2_L1_V1) #define BITS_R2_L1_V1 (BIT_MASK_R2_L1_V1 << BIT_SHIFT_R2_L1_V1) #define BIT_CLEAR_R2_L1_V1(x) ((x) & (~BITS_R2_L1_V1)) #define BIT_GET_R2_L1_V1(x) (((x) >> BIT_SHIFT_R2_L1_V1) & BIT_MASK_R2_L1_V1) #define BIT_SET_R2_L1_V1(x, v) (BIT_CLEAR_R2_L1_V1(x) | BIT_R2_L1_V1(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ #define BIT_C2_L_BIT1 BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ #define BIT_SPS18_OCP_DIS BIT(31) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ #define BIT_IO_READY_SIGNAL_ERR BIT(31) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ #define BIT_SDIO_CRCERR BIT(31) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ #define BIT_TX_CRC BIT(30) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ #define BIT_SDIO_HSISR3_IND BIT(30) #define BIT_SDIO_HSISR2_IND BIT(29) #define BIT_SDIO_HEISR_IND BIT(28) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ #define BIT_SDIO_CTWEND BIT(27) #define BIT_SDIO_ATIMEND_E BIT(26) #define BIT_SDIO_ATIMEND BIT(25) #define BIT_SDIO_OCPINT BIT(24) #define BIT_SDIO_PSTIMEOUT BIT(23) #define BIT_SDIO_GTINT4 BIT(22) #define BIT_SDIO_GTINT3 BIT(21) #define BIT_SDIO_HSISR_IND BIT(20) #define BIT_SDIO_CPWM2 BIT(19) #define BIT_SDIO_CPWM1 BIT(18) #define BIT_SDIO_C2HCMD_INT BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ #define BIT_SHIFT_SPS18_OCP_TH 16 #define BIT_MASK_SPS18_OCP_TH 0x7fff #define BIT_SPS18_OCP_TH(x) \ (((x) & BIT_MASK_SPS18_OCP_TH) << BIT_SHIFT_SPS18_OCP_TH) #define BITS_SPS18_OCP_TH (BIT_MASK_SPS18_OCP_TH << BIT_SHIFT_SPS18_OCP_TH) #define BIT_CLEAR_SPS18_OCP_TH(x) ((x) & (~BITS_SPS18_OCP_TH)) #define BIT_GET_SPS18_OCP_TH(x) \ (((x) >> BIT_SHIFT_SPS18_OCP_TH) & BIT_MASK_SPS18_OCP_TH) #define BIT_SET_SPS18_OCP_TH(x, v) \ (BIT_CLEAR_SPS18_OCP_TH(x) | BIT_SPS18_OCP_TH(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ #define BIT_SDIO_BCNERLY_INT BIT(16) #define BIT_SDIO_TXBCNERR BIT(7) #define BIT_SDIO_TXBCNOK BIT(6) #define BIT_SDIO_RXFOVW BIT(5) #define BIT_SDIO_TXFOVW BIT(4) #define BIT_SDIO_RXERR BIT(3) #define BIT_SDIO_TXERR BIT(2) #define BIT_SDIO_AVAL BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ #define BIT_SHIFT_OCP_WINDOW 0 #define BIT_MASK_OCP_WINDOW 0xffff #define BIT_OCP_WINDOW(x) (((x) & BIT_MASK_OCP_WINDOW) << BIT_SHIFT_OCP_WINDOW) #define BITS_OCP_WINDOW (BIT_MASK_OCP_WINDOW << BIT_SHIFT_OCP_WINDOW) #define BIT_CLEAR_OCP_WINDOW(x) ((x) & (~BITS_OCP_WINDOW)) #define BIT_GET_OCP_WINDOW(x) \ (((x) >> BIT_SHIFT_OCP_WINDOW) & BIT_MASK_OCP_WINDOW) #define BIT_SET_OCP_WINDOW(x, v) (BIT_CLEAR_OCP_WINDOW(x) | BIT_OCP_WINDOW(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ #define BIT_RX_REQUEST BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ #define BIT_HREG_DBG BIT(23) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ #define BIT_SHIFT_HREG_DBG_V1 12 #define BIT_MASK_HREG_DBG_V1 0xfff #define BIT_HREG_DBG_V1(x) \ (((x) & BIT_MASK_HREG_DBG_V1) << BIT_SHIFT_HREG_DBG_V1) #define BITS_HREG_DBG_V1 (BIT_MASK_HREG_DBG_V1 << BIT_SHIFT_HREG_DBG_V1) #define BIT_CLEAR_HREG_DBG_V1(x) ((x) & (~BITS_HREG_DBG_V1)) #define BIT_GET_HREG_DBG_V1(x) \ (((x) >> BIT_SHIFT_HREG_DBG_V1) & BIT_MASK_HREG_DBG_V1) #define BIT_SET_HREG_DBG_V1(x, v) \ (BIT_CLEAR_HREG_DBG_V1(x) | BIT_HREG_DBG_V1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ #define BIT_MCU_RST BIT(11) #define BIT_WLOCK_90 BIT(10) #define BIT_WLOCK_70 BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ #define BIT_WLMCUIOIF BIT(8) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ #define BIT_WLOCK_78 BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ #define BIT_LOCK_ALL_EN BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ #define BIT_R_DIS_PRST BIT(6) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ #define BIT_R_DIS_PRST_1 BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ #define BIT_WLOCK_1C_B6 BIT(5) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ #define BIT_R_DIS_PRST_0 BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ #define BIT_WLOCK_40 BIT(4) #define BIT_WLOCK_08 BIT(3) #define BIT_WLOCK_04 BIT(2) #define BIT_WLOCK_00 BIT(1) #define BIT_WLOCK_ALL BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_RX_REQ_LEN (Offset 0x1025001C) */ #define BIT_SHIFT_RX_REQ_LEN_V1 0 #define BIT_MASK_RX_REQ_LEN_V1 0x3ffff #define BIT_RX_REQ_LEN_V1(x) \ (((x) & BIT_MASK_RX_REQ_LEN_V1) << BIT_SHIFT_RX_REQ_LEN_V1) #define BITS_RX_REQ_LEN_V1 (BIT_MASK_RX_REQ_LEN_V1 << BIT_SHIFT_RX_REQ_LEN_V1) #define BIT_CLEAR_RX_REQ_LEN_V1(x) ((x) & (~BITS_RX_REQ_LEN_V1)) #define BIT_GET_RX_REQ_LEN_V1(x) \ (((x) >> BIT_SHIFT_RX_REQ_LEN_V1) & BIT_MASK_RX_REQ_LEN_V1) #define BIT_SET_RX_REQ_LEN_V1(x, v) \ (BIT_CLEAR_RX_REQ_LEN_V1(x) | BIT_RX_REQ_LEN_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RF_CTRL (Offset 0x001F) */ #define BIT_RF_SDMRSTB BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RF0_CTRL (Offset 0x001F) */ #define BIT_RF0_SDMRSTB BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RF_CTRL (Offset 0x001F) */ #define BIT_RF_RSTB BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RF0_CTRL (Offset 0x001F) */ #define BIT_RF0_RSTB BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RF_CTRL (Offset 0x001F) */ #define BIT_RF_EN BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RF0_CTRL (Offset 0x001F) */ #define BIT_RF0_EN BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_FREE_TXPG_SEQ_V1 (Offset 0x1025001F) */ #define BIT_SHIFT_FREE_TXPG_SEQ 0 #define BIT_MASK_FREE_TXPG_SEQ 0xff #define BIT_FREE_TXPG_SEQ(x) \ (((x) & BIT_MASK_FREE_TXPG_SEQ) << BIT_SHIFT_FREE_TXPG_SEQ) #define BITS_FREE_TXPG_SEQ (BIT_MASK_FREE_TXPG_SEQ << BIT_SHIFT_FREE_TXPG_SEQ) #define BIT_CLEAR_FREE_TXPG_SEQ(x) ((x) & (~BITS_FREE_TXPG_SEQ)) #define BIT_GET_FREE_TXPG_SEQ(x) \ (((x) >> BIT_SHIFT_FREE_TXPG_SEQ) & BIT_MASK_FREE_TXPG_SEQ) #define BIT_SET_FREE_TXPG_SEQ(x, v) \ (BIT_CLEAR_FREE_TXPG_SEQ(x) | BIT_FREE_TXPG_SEQ(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_LPLDH12_RSV1 BIT(31) #define BIT_LPLDH12_RSV0 BIT(30) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_SHIFT_LPLDH12_RSV 29 #define BIT_MASK_LPLDH12_RSV 0x7 #define BIT_LPLDH12_RSV(x) \ (((x) & BIT_MASK_LPLDH12_RSV) << BIT_SHIFT_LPLDH12_RSV) #define BITS_LPLDH12_RSV (BIT_MASK_LPLDH12_RSV << BIT_SHIFT_LPLDH12_RSV) #define BIT_CLEAR_LPLDH12_RSV(x) ((x) & (~BITS_LPLDH12_RSV)) #define BIT_GET_LPLDH12_RSV(x) \ (((x) >> BIT_SHIFT_LPLDH12_RSV) & BIT_MASK_LPLDH12_RSV) #define BIT_SET_LPLDH12_RSV(x, v) \ (BIT_CLEAR_LPLDH12_RSV(x) | BIT_LPLDH12_RSV(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_LPLDH12_SLP BIT(28) #define BIT_SHIFT_LPLDH12_VADJ 24 #define BIT_MASK_LPLDH12_VADJ 0xf #define BIT_LPLDH12_VADJ(x) \ (((x) & BIT_MASK_LPLDH12_VADJ) << BIT_SHIFT_LPLDH12_VADJ) #define BITS_LPLDH12_VADJ (BIT_MASK_LPLDH12_VADJ << BIT_SHIFT_LPLDH12_VADJ) #define BIT_CLEAR_LPLDH12_VADJ(x) ((x) & (~BITS_LPLDH12_VADJ)) #define BIT_GET_LPLDH12_VADJ(x) \ (((x) >> BIT_SHIFT_LPLDH12_VADJ) & BIT_MASK_LPLDH12_VADJ) #define BIT_SET_LPLDH12_VADJ(x, v) \ (BIT_CLEAR_LPLDH12_VADJ(x) | BIT_LPLDH12_VADJ(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_PCIE_CALIB_EN BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_LDH12_EN BIT(16) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */ #define BIT_SHIFT_MID_FREEPG_V1 16 #define BIT_MASK_MID_FREEPG_V1 0xfff #define BIT_MID_FREEPG_V1(x) \ (((x) & BIT_MASK_MID_FREEPG_V1) << BIT_SHIFT_MID_FREEPG_V1) #define BITS_MID_FREEPG_V1 (BIT_MASK_MID_FREEPG_V1 << BIT_SHIFT_MID_FREEPG_V1) #define BIT_CLEAR_MID_FREEPG_V1(x) ((x) & (~BITS_MID_FREEPG_V1)) #define BIT_GET_MID_FREEPG_V1(x) \ (((x) >> BIT_SHIFT_MID_FREEPG_V1) & BIT_MASK_MID_FREEPG_V1) #define BIT_SET_MID_FREEPG_V1(x, v) \ (BIT_CLEAR_MID_FREEPG_V1(x) | BIT_MID_FREEPG_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_WLBBOFF_BIG_PWC_EN BIT(14) #define BIT_WLBBOFF_SMALL_PWC_EN BIT(13) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_POW_REGU_P3 BIT(12) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_WLMACOFF_BIG_PWC_EN BIT(12) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_POW_REGU_P2 BIT(11) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_WLPON_PWC_EN BIT(11) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_POW_REGU_P1 BIT(10) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_R_SYM_WLBBOFF1_P4_EN BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_LDOV12W_EN BIT(8) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_SHIFT_ANAPAR_RFC2 8 #define BIT_MASK_ANAPAR_RFC2 0xff #define BIT_ANAPAR_RFC2(x) \ (((x) & BIT_MASK_ANAPAR_RFC2) << BIT_SHIFT_ANAPAR_RFC2) #define BITS_ANAPAR_RFC2 (BIT_MASK_ANAPAR_RFC2 << BIT_SHIFT_ANAPAR_RFC2) #define BIT_CLEAR_ANAPAR_RFC2(x) ((x) & (~BITS_ANAPAR_RFC2)) #define BIT_GET_ANAPAR_RFC2(x) \ (((x) >> BIT_SHIFT_ANAPAR_RFC2) & BIT_MASK_ANAPAR_RFC2) #define BIT_SET_ANAPAR_RFC2(x, v) \ (BIT_CLEAR_ANAPAR_RFC2(x) | BIT_ANAPAR_RFC2(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_R_SYM_WLBBOFF1_P3_EN BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_EX_XTAL_DRV_DIGI BIT(7) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_R_SYM_WLBBOFF1_P2_EN BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_EX_XTAL_DRV_USB BIT(6) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_R_SYM_WLBBOFF1_P1_EN BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_EX_XTAL_DRV_AFE BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_SHIFT_LDA12_VOADJ 4 #define BIT_MASK_LDA12_VOADJ 0xf #define BIT_LDA12_VOADJ(x) \ (((x) & BIT_MASK_LDA12_VOADJ) << BIT_SHIFT_LDA12_VOADJ) #define BITS_LDA12_VOADJ (BIT_MASK_LDA12_VOADJ << BIT_SHIFT_LDA12_VOADJ) #define BIT_CLEAR_LDA12_VOADJ(x) ((x) & (~BITS_LDA12_VOADJ)) #define BIT_GET_LDA12_VOADJ(x) \ (((x) >> BIT_SHIFT_LDA12_VOADJ) & BIT_MASK_LDA12_VOADJ) #define BIT_SET_LDA12_VOADJ(x, v) \ (BIT_CLEAR_LDA12_VOADJ(x) | BIT_LDA12_VOADJ(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_EX_XTAL_DRV_RF2 BIT(4) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_R_SYM_WLBBOFF_P4_EN BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_REG_VOS BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_EX_XTAL_DRV_RF1 BIT(3) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_R_SYM_WLBBOFF_P3_EN BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_POW_REGU_P0 BIT(2) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_R_SYM_WLBBOFF_P2_EN BIT(2) #define BIT_R_SYM_WLBBOFF_P1_EN BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_LDA12_EN BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_POW_PLL_LDO BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */ #define BIT_SHIFT_HIQ_FREEPG_V1 0 #define BIT_MASK_HIQ_FREEPG_V1 0xfff #define BIT_HIQ_FREEPG_V1(x) \ (((x) & BIT_MASK_HIQ_FREEPG_V1) << BIT_SHIFT_HIQ_FREEPG_V1) #define BITS_HIQ_FREEPG_V1 (BIT_MASK_HIQ_FREEPG_V1 << BIT_SHIFT_HIQ_FREEPG_V1) #define BIT_CLEAR_HIQ_FREEPG_V1(x) ((x) & (~BITS_HIQ_FREEPG_V1)) #define BIT_GET_HIQ_FREEPG_V1(x) \ (((x) >> BIT_SHIFT_HIQ_FREEPG_V1) & BIT_MASK_HIQ_FREEPG_V1) #define BIT_SET_HIQ_FREEPG_V1(x, v) \ (BIT_CLEAR_HIQ_FREEPG_V1(x) | BIT_HIQ_FREEPG_V1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_SHIFT_ANAPAR_RFC1 0 #define BIT_MASK_ANAPAR_RFC1 0xff #define BIT_ANAPAR_RFC1(x) \ (((x) & BIT_MASK_ANAPAR_RFC1) << BIT_SHIFT_ANAPAR_RFC1) #define BITS_ANAPAR_RFC1 (BIT_MASK_ANAPAR_RFC1 << BIT_SHIFT_ANAPAR_RFC1) #define BIT_CLEAR_ANAPAR_RFC1(x) ((x) & (~BITS_ANAPAR_RFC1)) #define BIT_GET_ANAPAR_RFC1(x) \ (((x) >> BIT_SHIFT_ANAPAR_RFC1) & BIT_MASK_ANAPAR_RFC1) #define BIT_SET_ANAPAR_RFC1(x, v) \ (BIT_CLEAR_ANAPAR_RFC1(x) | BIT_ANAPAR_RFC1(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ #define BIT_R_SYM_WLBBOFF_EN BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_AGPIO_GPE BIT(31) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XQSEL_V3 BIT(31) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_REG_CC 30 #define BIT_MASK_REG_CC 0x3 #define BIT_REG_CC(x) (((x) & BIT_MASK_REG_CC) << BIT_SHIFT_REG_CC) #define BITS_REG_CC (BIT_MASK_REG_CC << BIT_SHIFT_REG_CC) #define BIT_CLEAR_REG_CC(x) ((x) & (~BITS_REG_CC)) #define BIT_GET_REG_CC(x) (((x) >> BIT_SHIFT_REG_CC) & BIT_MASK_REG_CC) #define BIT_SET_REG_CC(x, v) (BIT_CLEAR_REG_CC(x) | BIT_REG_CC(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_CKDELAY_AFE_V1 BIT(30) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_CKDLY_DIG BIT(28) #define BIT_CKDLY_USB BIT(27) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_GPIO_V1 27 #define BIT_MASK_XTAL_GPIO_V1 0x7 #define BIT_XTAL_GPIO_V1(x) \ (((x) & BIT_MASK_XTAL_GPIO_V1) << BIT_SHIFT_XTAL_GPIO_V1) #define BITS_XTAL_GPIO_V1 (BIT_MASK_XTAL_GPIO_V1 << BIT_SHIFT_XTAL_GPIO_V1) #define BIT_CLEAR_XTAL_GPIO_V1(x) ((x) & (~BITS_XTAL_GPIO_V1)) #define BIT_GET_XTAL_GPIO_V1(x) \ (((x) >> BIT_SHIFT_XTAL_GPIO_V1) & BIT_MASK_XTAL_GPIO_V1) #define BIT_SET_XTAL_GPIO_V1(x, v) \ (BIT_CLEAR_XTAL_GPIO_V1(x) | BIT_XTAL_GPIO_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_CKDLY_AFE BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_CAP_XI 25 #define BIT_MASK_XTAL_CAP_XI 0x3f #define BIT_XTAL_CAP_XI(x) \ (((x) & BIT_MASK_XTAL_CAP_XI) << BIT_SHIFT_XTAL_CAP_XI) #define BITS_XTAL_CAP_XI (BIT_MASK_XTAL_CAP_XI << BIT_SHIFT_XTAL_CAP_XI) #define BIT_CLEAR_XTAL_CAP_XI(x) ((x) & (~BITS_XTAL_CAP_XI)) #define BIT_GET_XTAL_CAP_XI(x) \ (((x) >> BIT_SHIFT_XTAL_CAP_XI) & BIT_MASK_XTAL_CAP_XI) #define BIT_SET_XTAL_CAP_XI(x, v) \ (BIT_CLEAR_XTAL_CAP_XI(x) | BIT_XTAL_CAP_XI(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_DIG_DRV_1_TO_0 25 #define BIT_MASK_XTAL_DIG_DRV_1_TO_0 0x3 #define BIT_XTAL_DIG_DRV_1_TO_0(x) \ (((x) & BIT_MASK_XTAL_DIG_DRV_1_TO_0) << BIT_SHIFT_XTAL_DIG_DRV_1_TO_0) #define BITS_XTAL_DIG_DRV_1_TO_0 \ (BIT_MASK_XTAL_DIG_DRV_1_TO_0 << BIT_SHIFT_XTAL_DIG_DRV_1_TO_0) #define BIT_CLEAR_XTAL_DIG_DRV_1_TO_0(x) ((x) & (~BITS_XTAL_DIG_DRV_1_TO_0)) #define BIT_GET_XTAL_DIG_DRV_1_TO_0(x) \ (((x) >> BIT_SHIFT_XTAL_DIG_DRV_1_TO_0) & BIT_MASK_XTAL_DIG_DRV_1_TO_0) #define BIT_SET_XTAL_DIG_DRV_1_TO_0(x, v) \ (BIT_CLEAR_XTAL_DIG_DRV_1_TO_0(x) | BIT_XTAL_DIG_DRV_1_TO_0(v)) #define BIT_XTAL_GDIG BIT(24) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_GPIO 23 #define BIT_MASK_XTAL_GPIO 0x7 #define BIT_XTAL_GPIO(x) (((x) & BIT_MASK_XTAL_GPIO) << BIT_SHIFT_XTAL_GPIO) #define BITS_XTAL_GPIO (BIT_MASK_XTAL_GPIO << BIT_SHIFT_XTAL_GPIO) #define BIT_CLEAR_XTAL_GPIO(x) ((x) & (~BITS_XTAL_GPIO)) #define BIT_GET_XTAL_GPIO(x) (((x) >> BIT_SHIFT_XTAL_GPIO) & BIT_MASK_XTAL_GPIO) #define BIT_SET_XTAL_GPIO(x, v) (BIT_CLEAR_XTAL_GPIO(x) | BIT_XTAL_GPIO(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_DRV_DIGI 23 #define BIT_MASK_XTAL_DRV_DIGI 0x3 #define BIT_XTAL_DRV_DIGI(x) \ (((x) & BIT_MASK_XTAL_DRV_DIGI) << BIT_SHIFT_XTAL_DRV_DIGI) #define BITS_XTAL_DRV_DIGI (BIT_MASK_XTAL_DRV_DIGI << BIT_SHIFT_XTAL_DRV_DIGI) #define BIT_CLEAR_XTAL_DRV_DIGI(x) ((x) & (~BITS_XTAL_DRV_DIGI)) #define BIT_GET_XTAL_DRV_DIGI(x) \ (((x) >> BIT_SHIFT_XTAL_DRV_DIGI) & BIT_MASK_XTAL_DRV_DIGI) #define BIT_SET_XTAL_DRV_DIGI(x, v) \ (BIT_CLEAR_XTAL_DRV_DIGI(x) | BIT_XTAL_DRV_DIGI(v)) #define BIT_XTAL_DRV_USB_BIT1 BIT(22) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XTAL_DRV_RF_LATCH_V2 BIT(22) #endif #if (HALMAC_8814A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0 22 #define BIT_MASK_XTAL_RDRV_RF2_1_TO_0 0x3 #define BIT_XTAL_RDRV_RF2_1_TO_0(x) \ (((x) & BIT_MASK_XTAL_RDRV_RF2_1_TO_0) \ << BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0) #define BITS_XTAL_RDRV_RF2_1_TO_0 \ (BIT_MASK_XTAL_RDRV_RF2_1_TO_0 << BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0) #define BIT_CLEAR_XTAL_RDRV_RF2_1_TO_0(x) ((x) & (~BITS_XTAL_RDRV_RF2_1_TO_0)) #define BIT_GET_XTAL_RDRV_RF2_1_TO_0(x) \ (((x) >> BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0) & \ BIT_MASK_XTAL_RDRV_RF2_1_TO_0) #define BIT_SET_XTAL_RDRV_RF2_1_TO_0(x, v) \ (BIT_CLEAR_XTAL_RDRV_RF2_1_TO_0(x) | BIT_XTAL_RDRV_RF2_1_TO_0(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XTAL_GMN_4 BIT(21) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_MAC_CLK_SEL 20 #define BIT_MASK_MAC_CLK_SEL 0x3 #define BIT_MAC_CLK_SEL(x) \ (((x) & BIT_MASK_MAC_CLK_SEL) << BIT_SHIFT_MAC_CLK_SEL) #define BITS_MAC_CLK_SEL (BIT_MASK_MAC_CLK_SEL << BIT_SHIFT_MAC_CLK_SEL) #define BIT_CLEAR_MAC_CLK_SEL(x) ((x) & (~BITS_MAC_CLK_SEL)) #define BIT_GET_MAC_CLK_SEL(x) \ (((x) >> BIT_SHIFT_MAC_CLK_SEL) & BIT_MASK_MAC_CLK_SEL) #define BIT_SET_MAC_CLK_SEL(x, v) \ (BIT_CLEAR_MAC_CLK_SEL(x) | BIT_MAC_CLK_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XTAL_DRV_USB_BIT0 BIT(19) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_RDRV_1_TO_0 19 #define BIT_MASK_XTAL_RDRV_1_TO_0 0x3 #define BIT_XTAL_RDRV_1_TO_0(x) \ (((x) & BIT_MASK_XTAL_RDRV_1_TO_0) << BIT_SHIFT_XTAL_RDRV_1_TO_0) #define BITS_XTAL_RDRV_1_TO_0 \ (BIT_MASK_XTAL_RDRV_1_TO_0 << BIT_SHIFT_XTAL_RDRV_1_TO_0) #define BIT_CLEAR_XTAL_RDRV_1_TO_0(x) ((x) & (~BITS_XTAL_RDRV_1_TO_0)) #define BIT_GET_XTAL_RDRV_1_TO_0(x) \ (((x) >> BIT_SHIFT_XTAL_RDRV_1_TO_0) & BIT_MASK_XTAL_RDRV_1_TO_0) #define BIT_SET_XTAL_RDRV_1_TO_0(x, v) \ (BIT_CLEAR_XTAL_RDRV_1_TO_0(x) | BIT_XTAL_RDRV_1_TO_0(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_DIG_DRV 18 #define BIT_MASK_XTAL_DIG_DRV 0x3 #define BIT_XTAL_DIG_DRV(x) \ (((x) & BIT_MASK_XTAL_DIG_DRV) << BIT_SHIFT_XTAL_DIG_DRV) #define BITS_XTAL_DIG_DRV (BIT_MASK_XTAL_DIG_DRV << BIT_SHIFT_XTAL_DIG_DRV) #define BIT_CLEAR_XTAL_DIG_DRV(x) ((x) & (~BITS_XTAL_DIG_DRV)) #define BIT_GET_XTAL_DIG_DRV(x) \ (((x) >> BIT_SHIFT_XTAL_DIG_DRV) & BIT_MASK_XTAL_DIG_DRV) #define BIT_SET_XTAL_DIG_DRV(x, v) \ (BIT_CLEAR_XTAL_DIG_DRV(x) | BIT_XTAL_DIG_DRV(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XTAL_GMP_4 BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XTAL_GATE_DIG BIT(17) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_DRV_AFE 17 #define BIT_MASK_XTAL_DRV_AFE 0x3 #define BIT_XTAL_DRV_AFE(x) \ (((x) & BIT_MASK_XTAL_DRV_AFE) << BIT_SHIFT_XTAL_DRV_AFE) #define BITS_XTAL_DRV_AFE (BIT_MASK_XTAL_DRV_AFE << BIT_SHIFT_XTAL_DRV_AFE) #define BIT_CLEAR_XTAL_DRV_AFE(x) ((x) & (~BITS_XTAL_DRV_AFE)) #define BIT_GET_XTAL_DRV_AFE(x) \ (((x) >> BIT_SHIFT_XTAL_DRV_AFE) & BIT_MASK_XTAL_DRV_AFE) #define BIT_SET_XTAL_DRV_AFE(x, v) \ (BIT_CLEAR_XTAL_DRV_AFE(x) | BIT_XTAL_DRV_AFE(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */ #define BIT_SHIFT_PUB_FREEPG_V1 16 #define BIT_MASK_PUB_FREEPG_V1 0xfff #define BIT_PUB_FREEPG_V1(x) \ (((x) & BIT_MASK_PUB_FREEPG_V1) << BIT_SHIFT_PUB_FREEPG_V1) #define BITS_PUB_FREEPG_V1 (BIT_MASK_PUB_FREEPG_V1 << BIT_SHIFT_PUB_FREEPG_V1) #define BIT_CLEAR_PUB_FREEPG_V1(x) ((x) & (~BITS_PUB_FREEPG_V1)) #define BIT_GET_PUB_FREEPG_V1(x) \ (((x) >> BIT_SHIFT_PUB_FREEPG_V1) & BIT_MASK_PUB_FREEPG_V1) #define BIT_SET_PUB_FREEPG_V1(x, v) \ (BIT_CLEAR_PUB_FREEPG_V1(x) | BIT_PUB_FREEPG_V1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_ADRV_1_TO_0 16 #define BIT_MASK_XTAL_ADRV_1_TO_0 0x3 #define BIT_XTAL_ADRV_1_TO_0(x) \ (((x) & BIT_MASK_XTAL_ADRV_1_TO_0) << BIT_SHIFT_XTAL_ADRV_1_TO_0) #define BITS_XTAL_ADRV_1_TO_0 \ (BIT_MASK_XTAL_ADRV_1_TO_0 << BIT_SHIFT_XTAL_ADRV_1_TO_0) #define BIT_CLEAR_XTAL_ADRV_1_TO_0(x) ((x) & (~BITS_XTAL_ADRV_1_TO_0)) #define BIT_GET_XTAL_ADRV_1_TO_0(x) \ (((x) >> BIT_SHIFT_XTAL_ADRV_1_TO_0) & BIT_MASK_XTAL_ADRV_1_TO_0) #define BIT_SET_XTAL_ADRV_1_TO_0(x, v) \ (BIT_CLEAR_XTAL_ADRV_1_TO_0(x) | BIT_XTAL_ADRV_1_TO_0(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_RF_DRV 15 #define BIT_MASK_XTAL_RF_DRV 0x3 #define BIT_XTAL_RF_DRV(x) \ (((x) & BIT_MASK_XTAL_RF_DRV) << BIT_SHIFT_XTAL_RF_DRV) #define BITS_XTAL_RF_DRV (BIT_MASK_XTAL_RF_DRV << BIT_SHIFT_XTAL_RF_DRV) #define BIT_CLEAR_XTAL_RF_DRV(x) ((x) & (~BITS_XTAL_RF_DRV)) #define BIT_GET_XTAL_RF_DRV(x) \ (((x) >> BIT_SHIFT_XTAL_RF_DRV) & BIT_MASK_XTAL_RF_DRV) #define BIT_SET_XTAL_RF_DRV(x, v) \ (BIT_CLEAR_XTAL_RF_DRV(x) | BIT_XTAL_RF_DRV(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_DRV_RF2 15 #define BIT_MASK_XTAL_DRV_RF2 0x3 #define BIT_XTAL_DRV_RF2(x) \ (((x) & BIT_MASK_XTAL_DRV_RF2) << BIT_SHIFT_XTAL_DRV_RF2) #define BITS_XTAL_DRV_RF2 (BIT_MASK_XTAL_DRV_RF2 << BIT_SHIFT_XTAL_DRV_RF2) #define BIT_CLEAR_XTAL_DRV_RF2(x) ((x) & (~BITS_XTAL_DRV_RF2)) #define BIT_GET_XTAL_DRV_RF2(x) \ (((x) >> BIT_SHIFT_XTAL_DRV_RF2) & BIT_MASK_XTAL_DRV_RF2) #define BIT_SET_XTAL_DRV_RF2(x, v) \ (BIT_CLEAR_XTAL_DRV_RF2(x) | BIT_XTAL_DRV_RF2(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XTAL_GAFE BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XTAL_RF_GATE BIT(14) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_DDRV_1_TO_0 13 #define BIT_MASK_XTAL_DDRV_1_TO_0 0x3 #define BIT_XTAL_DDRV_1_TO_0(x) \ (((x) & BIT_MASK_XTAL_DDRV_1_TO_0) << BIT_SHIFT_XTAL_DDRV_1_TO_0) #define BITS_XTAL_DDRV_1_TO_0 \ (BIT_MASK_XTAL_DDRV_1_TO_0 << BIT_SHIFT_XTAL_DDRV_1_TO_0) #define BIT_CLEAR_XTAL_DDRV_1_TO_0(x) ((x) & (~BITS_XTAL_DDRV_1_TO_0)) #define BIT_GET_XTAL_DDRV_1_TO_0(x) \ (((x) >> BIT_SHIFT_XTAL_DDRV_1_TO_0) & BIT_MASK_XTAL_DDRV_1_TO_0) #define BIT_SET_XTAL_DDRV_1_TO_0(x, v) \ (BIT_CLEAR_XTAL_DDRV_1_TO_0(x) | BIT_XTAL_DDRV_1_TO_0(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_AFE_DRV 12 #define BIT_MASK_XTAL_AFE_DRV 0x3 #define BIT_XTAL_AFE_DRV(x) \ (((x) & BIT_MASK_XTAL_AFE_DRV) << BIT_SHIFT_XTAL_AFE_DRV) #define BITS_XTAL_AFE_DRV (BIT_MASK_XTAL_AFE_DRV << BIT_SHIFT_XTAL_AFE_DRV) #define BIT_CLEAR_XTAL_AFE_DRV(x) ((x) & (~BITS_XTAL_AFE_DRV)) #define BIT_GET_XTAL_AFE_DRV(x) \ (((x) >> BIT_SHIFT_XTAL_AFE_DRV) & BIT_MASK_XTAL_AFE_DRV) #define BIT_SET_XTAL_AFE_DRV(x, v) \ (BIT_CLEAR_XTAL_AFE_DRV(x) | BIT_XTAL_AFE_DRV(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XTAL_DELAY_DIGI BIT(12) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XTAL_GUSB BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XTAL_GATE_AFE BIT(11) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XTAL_DELAY_USB BIT(11) #define BIT_XTAL_DELAY_AFE BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_USB_DRV 9 #define BIT_MASK_XTAL_USB_DRV 0x3 #define BIT_XTAL_USB_DRV(x) \ (((x) & BIT_MASK_XTAL_USB_DRV) << BIT_SHIFT_XTAL_USB_DRV) #define BITS_XTAL_USB_DRV (BIT_MASK_XTAL_USB_DRV << BIT_SHIFT_XTAL_USB_DRV) #define BIT_CLEAR_XTAL_USB_DRV(x) ((x) & (~BITS_XTAL_USB_DRV)) #define BIT_GET_XTAL_USB_DRV(x) \ (((x) >> BIT_SHIFT_XTAL_USB_DRV) & BIT_MASK_XTAL_USB_DRV) #define BIT_SET_XTAL_USB_DRV(x, v) \ (BIT_CLEAR_XTAL_USB_DRV(x) | BIT_XTAL_USB_DRV(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XTAL_LP_V1 BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XTAL_GATE_USB BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XTAL_GM_SEP_V1 BIT(8) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_GMN_3_TO_0 8 #define BIT_MASK_XTAL_GMN_3_TO_0 0xf #define BIT_XTAL_GMN_3_TO_0(x) \ (((x) & BIT_MASK_XTAL_GMN_3_TO_0) << BIT_SHIFT_XTAL_GMN_3_TO_0) #define BITS_XTAL_GMN_3_TO_0 \ (BIT_MASK_XTAL_GMN_3_TO_0 << BIT_SHIFT_XTAL_GMN_3_TO_0) #define BIT_CLEAR_XTAL_GMN_3_TO_0(x) ((x) & (~BITS_XTAL_GMN_3_TO_0)) #define BIT_GET_XTAL_GMN_3_TO_0(x) \ (((x) >> BIT_SHIFT_XTAL_GMN_3_TO_0) & BIT_MASK_XTAL_GMN_3_TO_0) #define BIT_SET_XTAL_GMN_3_TO_0(x, v) \ (BIT_CLEAR_XTAL_GMN_3_TO_0(x) | BIT_XTAL_GMN_3_TO_0(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XTAL_LDO_VREF_V1 BIT(7) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_LDO_VREF 7 #define BIT_MASK_XTAL_LDO_VREF 0x7 #define BIT_XTAL_LDO_VREF(x) \ (((x) & BIT_MASK_XTAL_LDO_VREF) << BIT_SHIFT_XTAL_LDO_VREF) #define BITS_XTAL_LDO_VREF (BIT_MASK_XTAL_LDO_VREF << BIT_SHIFT_XTAL_LDO_VREF) #define BIT_CLEAR_XTAL_LDO_VREF(x) ((x) & (~BITS_XTAL_LDO_VREF)) #define BIT_GET_XTAL_LDO_VREF(x) \ (((x) >> BIT_SHIFT_XTAL_LDO_VREF) & BIT_MASK_XTAL_LDO_VREF) #define BIT_SET_XTAL_LDO_VREF(x, v) \ (BIT_CLEAR_XTAL_LDO_VREF(x) | BIT_XTAL_LDO_VREF(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XTAL_XQSEL_RF BIT(6) #define BIT_XTAL_XQSEL BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_GMP 4 #define BIT_MASK_XTAL_GMP 0xf #define BIT_XTAL_GMP(x) (((x) & BIT_MASK_XTAL_GMP) << BIT_SHIFT_XTAL_GMP) #define BITS_XTAL_GMP (BIT_MASK_XTAL_GMP << BIT_SHIFT_XTAL_GMP) #define BIT_CLEAR_XTAL_GMP(x) ((x) & (~BITS_XTAL_GMP)) #define BIT_GET_XTAL_GMP(x) (((x) >> BIT_SHIFT_XTAL_GMP) & BIT_MASK_XTAL_GMP) #define BIT_SET_XTAL_GMP(x, v) (BIT_CLEAR_XTAL_GMP(x) | BIT_XTAL_GMP(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_GMP_3_TO_0 4 #define BIT_MASK_XTAL_GMP_3_TO_0 0xf #define BIT_XTAL_GMP_3_TO_0(x) \ (((x) & BIT_MASK_XTAL_GMP_3_TO_0) << BIT_SHIFT_XTAL_GMP_3_TO_0) #define BITS_XTAL_GMP_3_TO_0 \ (BIT_MASK_XTAL_GMP_3_TO_0 << BIT_SHIFT_XTAL_GMP_3_TO_0) #define BIT_CLEAR_XTAL_GMP_3_TO_0(x) ((x) & (~BITS_XTAL_GMP_3_TO_0)) #define BIT_GET_XTAL_GMP_3_TO_0(x) \ (((x) >> BIT_SHIFT_XTAL_GMP_3_TO_0) & BIT_MASK_XTAL_GMP_3_TO_0) #define BIT_SET_XTAL_GMP_3_TO_0(x, v) \ (BIT_CLEAR_XTAL_GMP_3_TO_0(x) | BIT_XTAL_GMP_3_TO_0(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_GMN_V1 3 #define BIT_MASK_XTAL_GMN_V1 0x3 #define BIT_XTAL_GMN_V1(x) \ (((x) & BIT_MASK_XTAL_GMN_V1) << BIT_SHIFT_XTAL_GMN_V1) #define BITS_XTAL_GMN_V1 (BIT_MASK_XTAL_GMN_V1 << BIT_SHIFT_XTAL_GMN_V1) #define BIT_CLEAR_XTAL_GMN_V1(x) ((x) & (~BITS_XTAL_GMN_V1)) #define BIT_GET_XTAL_GMN_V1(x) \ (((x) >> BIT_SHIFT_XTAL_GMN_V1) & BIT_MASK_XTAL_GMN_V1) #define BIT_SET_XTAL_GMN_V1(x, v) \ (BIT_CLEAR_XTAL_GMN_V1(x) | BIT_XTAL_GMN_V1(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_GMN_V2 3 #define BIT_MASK_XTAL_GMN_V2 0x3 #define BIT_XTAL_GMN_V2(x) \ (((x) & BIT_MASK_XTAL_GMN_V2) << BIT_SHIFT_XTAL_GMN_V2) #define BITS_XTAL_GMN_V2 (BIT_MASK_XTAL_GMN_V2 << BIT_SHIFT_XTAL_GMN_V2) #define BIT_CLEAR_XTAL_GMN_V2(x) ((x) & (~BITS_XTAL_GMN_V2)) #define BIT_GET_XTAL_GMN_V2(x) \ (((x) >> BIT_SHIFT_XTAL_GMN_V2) & BIT_MASK_XTAL_GMN_V2) #define BIT_SET_XTAL_GMN_V2(x, v) \ (BIT_CLEAR_XTAL_GMN_V2(x) | BIT_XTAL_GMN_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_LDO_VCM 2 #define BIT_MASK_XTAL_LDO_VCM 0x3 #define BIT_XTAL_LDO_VCM(x) \ (((x) & BIT_MASK_XTAL_LDO_VCM) << BIT_SHIFT_XTAL_LDO_VCM) #define BITS_XTAL_LDO_VCM (BIT_MASK_XTAL_LDO_VCM << BIT_SHIFT_XTAL_LDO_VCM) #define BIT_CLEAR_XTAL_LDO_VCM(x) ((x) & (~BITS_XTAL_LDO_VCM)) #define BIT_GET_XTAL_LDO_VCM(x) \ (((x) >> BIT_SHIFT_XTAL_LDO_VCM) & BIT_MASK_XTAL_LDO_VCM) #define BIT_SET_XTAL_LDO_VCM(x, v) \ (BIT_CLEAR_XTAL_LDO_VCM(x) | BIT_XTAL_LDO_VCM(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_DRV_LDO_VCM_1_TO_0 2 #define BIT_MASK_DRV_LDO_VCM_1_TO_0 0x3 #define BIT_DRV_LDO_VCM_1_TO_0(x) \ (((x) & BIT_MASK_DRV_LDO_VCM_1_TO_0) << BIT_SHIFT_DRV_LDO_VCM_1_TO_0) #define BITS_DRV_LDO_VCM_1_TO_0 \ (BIT_MASK_DRV_LDO_VCM_1_TO_0 << BIT_SHIFT_DRV_LDO_VCM_1_TO_0) #define BIT_CLEAR_DRV_LDO_VCM_1_TO_0(x) ((x) & (~BITS_DRV_LDO_VCM_1_TO_0)) #define BIT_GET_DRV_LDO_VCM_1_TO_0(x) \ (((x) >> BIT_SHIFT_DRV_LDO_VCM_1_TO_0) & BIT_MASK_DRV_LDO_VCM_1_TO_0) #define BIT_SET_DRV_LDO_VCM_1_TO_0(x, v) \ (BIT_CLEAR_DRV_LDO_VCM_1_TO_0(x) | BIT_DRV_LDO_VCM_1_TO_0(v)) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XTAL_DUMMY BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_GMP_V1 1 #define BIT_MASK_XTAL_GMP_V1 0x3 #define BIT_XTAL_GMP_V1(x) \ (((x) & BIT_MASK_XTAL_GMP_V1) << BIT_SHIFT_XTAL_GMP_V1) #define BITS_XTAL_GMP_V1 (BIT_MASK_XTAL_GMP_V1 << BIT_SHIFT_XTAL_GMP_V1) #define BIT_CLEAR_XTAL_GMP_V1(x) ((x) & (~BITS_XTAL_GMP_V1)) #define BIT_GET_XTAL_GMP_V1(x) \ (((x) >> BIT_SHIFT_XTAL_GMP_V1) & BIT_MASK_XTAL_GMP_V1) #define BIT_SET_XTAL_GMP_V1(x, v) \ (BIT_CLEAR_XTAL_GMP_V1(x) | BIT_XTAL_GMP_V1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XQSEL_RF_INITIAL_V1 BIT(1) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_SHIFT_XTAL_GMP_V2 1 #define BIT_MASK_XTAL_GMP_V2 0x3 #define BIT_XTAL_GMP_V2(x) \ (((x) & BIT_MASK_XTAL_GMP_V2) << BIT_SHIFT_XTAL_GMP_V2) #define BITS_XTAL_GMP_V2 (BIT_MASK_XTAL_GMP_V2 << BIT_SHIFT_XTAL_GMP_V2) #define BIT_CLEAR_XTAL_GMP_V2(x) ((x) & (~BITS_XTAL_GMP_V2)) #define BIT_GET_XTAL_GMP_V2(x) \ (((x) >> BIT_SHIFT_XTAL_GMP_V2) & BIT_MASK_XTAL_GMP_V2) #define BIT_SET_XTAL_GMP_V2(x, v) \ (BIT_CLEAR_XTAL_GMP_V2(x) | BIT_XTAL_GMP_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ #define BIT_XTAL_EN BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */ #define BIT_SHIFT_LOW_FREEPG_V1 0 #define BIT_MASK_LOW_FREEPG_V1 0xfff #define BIT_LOW_FREEPG_V1(x) \ (((x) & BIT_MASK_LOW_FREEPG_V1) << BIT_SHIFT_LOW_FREEPG_V1) #define BITS_LOW_FREEPG_V1 (BIT_MASK_LOW_FREEPG_V1 << BIT_SHIFT_LOW_FREEPG_V1) #define BIT_CLEAR_LOW_FREEPG_V1(x) ((x) & (~BITS_LOW_FREEPG_V1)) #define BIT_GET_LOW_FREEPG_V1(x) \ (((x) >> BIT_SHIFT_LOW_FREEPG_V1) & BIT_MASK_LOW_FREEPG_V1) #define BIT_SET_LOW_FREEPG_V1(x, v) \ (BIT_CLEAR_LOW_FREEPG_V1(x) | BIT_LOW_FREEPG_V1(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_REG_C3_V4 30 #define BIT_MASK_REG_C3_V4 0x3 #define BIT_REG_C3_V4(x) (((x) & BIT_MASK_REG_C3_V4) << BIT_SHIFT_REG_C3_V4) #define BITS_REG_C3_V4 (BIT_MASK_REG_C3_V4 << BIT_SHIFT_REG_C3_V4) #define BIT_CLEAR_REG_C3_V4(x) ((x) & (~BITS_REG_C3_V4)) #define BIT_GET_REG_C3_V4(x) (((x) >> BIT_SHIFT_REG_C3_V4) & BIT_MASK_REG_C3_V4) #define BIT_SET_REG_C3_V4(x, v) (BIT_CLEAR_REG_C3_V4(x) | BIT_REG_C3_V4(v)) #define BIT_REG_CP_BIT1 BIT(29) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_XTAL_GMN 28 #define BIT_MASK_XTAL_GMN 0xf #define BIT_XTAL_GMN(x) (((x) & BIT_MASK_XTAL_GMN) << BIT_SHIFT_XTAL_GMN) #define BITS_XTAL_GMN (BIT_MASK_XTAL_GMN << BIT_SHIFT_XTAL_GMN) #define BIT_CLEAR_XTAL_GMN(x) ((x) & (~BITS_XTAL_GMN)) #define BIT_GET_XTAL_GMN(x) (((x) >> BIT_SHIFT_XTAL_GMN) & BIT_MASK_XTAL_GMN) #define BIT_SET_XTAL_GMN(x, v) (BIT_CLEAR_XTAL_GMN(x) | BIT_XTAL_GMN(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_IOOFFSET_3_TO_0 28 #define BIT_MASK_IOOFFSET_3_TO_0 0xf #define BIT_IOOFFSET_3_TO_0(x) \ (((x) & BIT_MASK_IOOFFSET_3_TO_0) << BIT_SHIFT_IOOFFSET_3_TO_0) #define BITS_IOOFFSET_3_TO_0 \ (BIT_MASK_IOOFFSET_3_TO_0 << BIT_SHIFT_IOOFFSET_3_TO_0) #define BIT_CLEAR_IOOFFSET_3_TO_0(x) ((x) & (~BITS_IOOFFSET_3_TO_0)) #define BIT_GET_IOOFFSET_3_TO_0(x) \ (((x) >> BIT_SHIFT_IOOFFSET_3_TO_0) & BIT_MASK_IOOFFSET_3_TO_0) #define BIT_SET_IOOFFSET_3_TO_0(x, v) \ (BIT_CLEAR_IOOFFSET_3_TO_0(x) | BIT_IOOFFSET_3_TO_0(v)) #define BIT_REG_FREF_SEL_BIT3_V1 BIT(27) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_REG_VO_AD 26 #define BIT_MASK_REG_VO_AD 0x3 #define BIT_REG_VO_AD(x) (((x) & BIT_MASK_REG_VO_AD) << BIT_SHIFT_REG_VO_AD) #define BITS_REG_VO_AD (BIT_MASK_REG_VO_AD << BIT_SHIFT_REG_VO_AD) #define BIT_CLEAR_REG_VO_AD(x) ((x) & (~BITS_REG_VO_AD)) #define BIT_GET_REG_VO_AD(x) (((x) >> BIT_SHIFT_REG_VO_AD) & BIT_MASK_REG_VO_AD) #define BIT_SET_REG_VO_AD(x, v) (BIT_CLEAR_REG_VO_AD(x) | BIT_REG_VO_AD(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_RS_SET_V2 26 #define BIT_MASK_RS_SET_V2 0x7 #define BIT_RS_SET_V2(x) (((x) & BIT_MASK_RS_SET_V2) << BIT_SHIFT_RS_SET_V2) #define BITS_RS_SET_V2 (BIT_MASK_RS_SET_V2 << BIT_SHIFT_RS_SET_V2) #define BIT_CLEAR_RS_SET_V2(x) ((x) & (~BITS_RS_SET_V2)) #define BIT_GET_RS_SET_V2(x) (((x) >> BIT_SHIFT_RS_SET_V2) & BIT_MASK_RS_SET_V2) #define BIT_SET_RS_SET_V2(x, v) (BIT_CLEAR_RS_SET_V2(x) | BIT_RS_SET_V2(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_REG_RS_V4 26 #define BIT_MASK_REG_RS_V4 0x7 #define BIT_REG_RS_V4(x) (((x) & BIT_MASK_REG_RS_V4) << BIT_SHIFT_REG_RS_V4) #define BITS_REG_RS_V4 (BIT_MASK_REG_RS_V4 << BIT_SHIFT_REG_RS_V4) #define BIT_CLEAR_REG_RS_V4(x) ((x) & (~BITS_REG_RS_V4)) #define BIT_GET_REG_RS_V4(x) (((x) >> BIT_SHIFT_REG_RS_V4) & BIT_MASK_REG_RS_V4) #define BIT_SET_REG_RS_V4(x, v) (BIT_CLEAR_REG_RS_V4(x) | BIT_REG_RS_V4(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_V12ADJ_V1 25 #define BIT_MASK_V12ADJ_V1 0x3 #define BIT_V12ADJ_V1(x) (((x) & BIT_MASK_V12ADJ_V1) << BIT_SHIFT_V12ADJ_V1) #define BITS_V12ADJ_V1 (BIT_MASK_V12ADJ_V1 << BIT_SHIFT_V12ADJ_V1) #define BIT_CLEAR_V12ADJ_V1(x) ((x) & (~BITS_V12ADJ_V1)) #define BIT_GET_V12ADJ_V1(x) (((x) >> BIT_SHIFT_V12ADJ_V1) & BIT_MASK_V12ADJ_V1) #define BIT_SET_V12ADJ_V1(x, v) (BIT_CLEAR_V12ADJ_V1(x) | BIT_V12ADJ_V1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ #define BIT_SHIFT_NOAC_OQT_FREEPG_V1 24 #define BIT_MASK_NOAC_OQT_FREEPG_V1 0xff #define BIT_NOAC_OQT_FREEPG_V1(x) \ (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1) << BIT_SHIFT_NOAC_OQT_FREEPG_V1) #define BITS_NOAC_OQT_FREEPG_V1 \ (BIT_MASK_NOAC_OQT_FREEPG_V1 << BIT_SHIFT_NOAC_OQT_FREEPG_V1) #define BIT_CLEAR_NOAC_OQT_FREEPG_V1(x) ((x) & (~BITS_NOAC_OQT_FREEPG_V1)) #define BIT_GET_NOAC_OQT_FREEPG_V1(x) \ (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1) & BIT_MASK_NOAC_OQT_FREEPG_V1) #define BIT_SET_NOAC_OQT_FREEPG_V1(x, v) \ (BIT_CLEAR_NOAC_OQT_FREEPG_V1(x) | BIT_NOAC_OQT_FREEPG_V1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_PS_EN BIT(24) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_REG__CS 24 #define BIT_MASK_REG__CS 0x3 #define BIT_REG__CS(x) (((x) & BIT_MASK_REG__CS) << BIT_SHIFT_REG__CS) #define BITS_REG__CS (BIT_MASK_REG__CS << BIT_SHIFT_REG__CS) #define BIT_CLEAR_REG__CS(x) ((x) & (~BITS_REG__CS)) #define BIT_GET_REG__CS(x) (((x) >> BIT_SHIFT_REG__CS) & BIT_MASK_REG__CS) #define BIT_SET_REG__CS(x, v) (BIT_CLEAR_REG__CS(x) | BIT_REG__CS(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_EN_CK320M_V1 BIT(23) #define BIT_AGPIO BIT(22) #define BIT_REG_EDGE_SEL_V1 BIT(21) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_REG_CP_OFFSET 21 #define BIT_MASK_REG_CP_OFFSET 0x7 #define BIT_REG_CP_OFFSET(x) \ (((x) & BIT_MASK_REG_CP_OFFSET) << BIT_SHIFT_REG_CP_OFFSET) #define BITS_REG_CP_OFFSET (BIT_MASK_REG_CP_OFFSET << BIT_SHIFT_REG_CP_OFFSET) #define BIT_CLEAR_REG_CP_OFFSET(x) ((x) & (~BITS_REG_CP_OFFSET)) #define BIT_GET_REG_CP_OFFSET(x) \ (((x) >> BIT_SHIFT_REG_CP_OFFSET) & BIT_MASK_REG_CP_OFFSET) #define BIT_SET_REG_CP_OFFSET(x, v) \ (BIT_CLEAR_REG_CP_OFFSET(x) | BIT_REG_CP_OFFSET(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_REG_VCO_BIAS_0 BIT(20) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_CP_BIAS_V2 18 #define BIT_MASK_CP_BIAS_V2 0x7 #define BIT_CP_BIAS_V2(x) (((x) & BIT_MASK_CP_BIAS_V2) << BIT_SHIFT_CP_BIAS_V2) #define BITS_CP_BIAS_V2 (BIT_MASK_CP_BIAS_V2 << BIT_SHIFT_CP_BIAS_V2) #define BIT_CLEAR_CP_BIAS_V2(x) ((x) & (~BITS_CP_BIAS_V2)) #define BIT_GET_CP_BIAS_V2(x) \ (((x) >> BIT_SHIFT_CP_BIAS_V2) & BIT_MASK_CP_BIAS_V2) #define BIT_SET_CP_BIAS_V2(x, v) (BIT_CLEAR_CP_BIAS_V2(x) | BIT_CP_BIAS_V2(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_CP_BIAS 18 #define BIT_MASK_CP_BIAS 0x7 #define BIT_CP_BIAS(x) (((x) & BIT_MASK_CP_BIAS) << BIT_SHIFT_CP_BIAS) #define BITS_CP_BIAS (BIT_MASK_CP_BIAS << BIT_SHIFT_CP_BIAS) #define BIT_CLEAR_CP_BIAS(x) ((x) & (~BITS_CP_BIAS)) #define BIT_GET_CP_BIAS(x) (((x) >> BIT_SHIFT_CP_BIAS) & BIT_MASK_CP_BIAS) #define BIT_SET_CP_BIAS(x, v) (BIT_CLEAR_CP_BIAS(x) | BIT_CP_BIAS(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1 17 #define BIT_MASK_REG_PLLBIAS_2_TO_0_V1 0x7 #define BIT_REG_PLLBIAS_2_TO_0_V1(x) \ (((x) & BIT_MASK_REG_PLLBIAS_2_TO_0_V1) \ << BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1) #define BITS_REG_PLLBIAS_2_TO_0_V1 \ (BIT_MASK_REG_PLLBIAS_2_TO_0_V1 << BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1) #define BIT_CLEAR_REG_PLLBIAS_2_TO_0_V1(x) ((x) & (~BITS_REG_PLLBIAS_2_TO_0_V1)) #define BIT_GET_REG_PLLBIAS_2_TO_0_V1(x) \ (((x) >> BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1) & \ BIT_MASK_REG_PLLBIAS_2_TO_0_V1) #define BIT_SET_REG_PLLBIAS_2_TO_0_V1(x, v) \ (BIT_CLEAR_REG_PLLBIAS_2_TO_0_V1(x) | BIT_REG_PLLBIAS_2_TO_0_V1(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_REG_IDOUBLE_V2 BIT(17) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_FREF_SEL BIT(16) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_REG_IDOUBLE_V1 BIT(16) #define BIT_SHIFT_AC_OQT__FREEPG_V1 16 #define BIT_MASK_AC_OQT__FREEPG_V1 0xff #define BIT_AC_OQT__FREEPG_V1(x) \ (((x) & BIT_MASK_AC_OQT__FREEPG_V1) << BIT_SHIFT_AC_OQT__FREEPG_V1) #define BITS_AC_OQT__FREEPG_V1 \ (BIT_MASK_AC_OQT__FREEPG_V1 << BIT_SHIFT_AC_OQT__FREEPG_V1) #define BIT_CLEAR_AC_OQT__FREEPG_V1(x) ((x) & (~BITS_AC_OQT__FREEPG_V1)) #define BIT_GET_AC_OQT__FREEPG_V1(x) \ (((x) >> BIT_SHIFT_AC_OQT__FREEPG_V1) & BIT_MASK_AC_OQT__FREEPG_V1) #define BIT_SET_AC_OQT__FREEPG_V1(x, v) \ (BIT_CLEAR_AC_OQT__FREEPG_V1(x) | BIT_AC_OQT__FREEPG_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ #define BIT_SHIFT_AC_OQT_FREEPG_V1 16 #define BIT_MASK_AC_OQT_FREEPG_V1 0xff #define BIT_AC_OQT_FREEPG_V1(x) \ (((x) & BIT_MASK_AC_OQT_FREEPG_V1) << BIT_SHIFT_AC_OQT_FREEPG_V1) #define BITS_AC_OQT_FREEPG_V1 \ (BIT_MASK_AC_OQT_FREEPG_V1 << BIT_SHIFT_AC_OQT_FREEPG_V1) #define BIT_CLEAR_AC_OQT_FREEPG_V1(x) ((x) & (~BITS_AC_OQT_FREEPG_V1)) #define BIT_GET_AC_OQT_FREEPG_V1(x) \ (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1) & BIT_MASK_AC_OQT_FREEPG_V1) #define BIT_SET_AC_OQT_FREEPG_V1(x, v) \ (BIT_CLEAR_AC_OQT_FREEPG_V1(x) | BIT_AC_OQT_FREEPG_V1(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_EN_SYN BIT(16) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_REG_KVCO_V1 BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_APLL_320_GATEB BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_MCCO_V2 14 #define BIT_MASK_MCCO_V2 0x3 #define BIT_MCCO_V2(x) (((x) & BIT_MASK_MCCO_V2) << BIT_SHIFT_MCCO_V2) #define BITS_MCCO_V2 (BIT_MASK_MCCO_V2 << BIT_SHIFT_MCCO_V2) #define BIT_CLEAR_MCCO_V2(x) ((x) & (~BITS_MCCO_V2)) #define BIT_GET_MCCO_V2(x) (((x) >> BIT_SHIFT_MCCO_V2) & BIT_MASK_MCCO_V2) #define BIT_SET_MCCO_V2(x, v) (BIT_CLEAR_MCCO_V2(x) | BIT_MCCO_V2(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_REG_VCO_BIAS_1_V1 BIT(14) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_MCCO 14 #define BIT_MASK_MCCO 0x3 #define BIT_MCCO(x) (((x) & BIT_MASK_MCCO) << BIT_SHIFT_MCCO) #define BITS_MCCO (BIT_MASK_MCCO << BIT_SHIFT_MCCO) #define BIT_CLEAR_MCCO(x) ((x) & (~BITS_MCCO)) #define BIT_GET_MCCO(x) (((x) >> BIT_SHIFT_MCCO) & BIT_MASK_MCCO) #define BIT_SET_MCCO(x, v) (BIT_CLEAR_MCCO(x) | BIT_MCCO(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_REG_DOGB_V1 BIT(13) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_CK320_EN 12 #define BIT_MASK_CK320_EN 0x3 #define BIT_CK320_EN(x) (((x) & BIT_MASK_CK320_EN) << BIT_SHIFT_CK320_EN) #define BITS_CK320_EN (BIT_MASK_CK320_EN << BIT_SHIFT_CK320_EN) #define BIT_CLEAR_CK320_EN(x) ((x) & (~BITS_CK320_EN)) #define BIT_GET_CK320_EN(x) (((x) >> BIT_SHIFT_CK320_EN) & BIT_MASK_CK320_EN) #define BIT_SET_CK320_EN(x, v) (BIT_CLEAR_CK320_EN(x) | BIT_CK320_EN(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_REG_LDO_SEL 12 #define BIT_MASK_REG_LDO_SEL 0x3 #define BIT_REG_LDO_SEL(x) \ (((x) & BIT_MASK_REG_LDO_SEL) << BIT_SHIFT_REG_LDO_SEL) #define BITS_REG_LDO_SEL (BIT_MASK_REG_LDO_SEL << BIT_SHIFT_REG_LDO_SEL) #define BIT_CLEAR_REG_LDO_SEL(x) ((x) & (~BITS_REG_LDO_SEL)) #define BIT_GET_REG_LDO_SEL(x) \ (((x) >> BIT_SHIFT_REG_LDO_SEL) & BIT_MASK_REG_LDO_SEL) #define BIT_SET_REG_LDO_SEL(x, v) \ (BIT_CLEAR_REG_LDO_SEL(x) | BIT_REG_LDO_SEL(v)) #define BIT_REG_KVCO_V2 BIT(10) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_AGPIO_GPO BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_APLL_BIAS 8 #define BIT_MASK_APLL_BIAS 0x7 #define BIT_APLL_BIAS(x) (((x) & BIT_MASK_APLL_BIAS) << BIT_SHIFT_APLL_BIAS) #define BITS_APLL_BIAS (BIT_MASK_APLL_BIAS << BIT_SHIFT_APLL_BIAS) #define BIT_CLEAR_APLL_BIAS(x) ((x) & (~BITS_APLL_BIAS)) #define BIT_GET_APLL_BIAS(x) (((x) >> BIT_SHIFT_APLL_BIAS) & BIT_MASK_APLL_BIAS) #define BIT_SET_APLL_BIAS(x, v) (BIT_CLEAR_APLL_BIAS(x) | BIT_APLL_BIAS(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_AGPIO_DRV 7 #define BIT_MASK_AGPIO_DRV 0x3 #define BIT_AGPIO_DRV(x) (((x) & BIT_MASK_AGPIO_DRV) << BIT_SHIFT_AGPIO_DRV) #define BITS_AGPIO_DRV (BIT_MASK_AGPIO_DRV << BIT_SHIFT_AGPIO_DRV) #define BIT_CLEAR_AGPIO_DRV(x) ((x) & (~BITS_AGPIO_DRV)) #define BIT_GET_AGPIO_DRV(x) (((x) >> BIT_SHIFT_AGPIO_DRV) & BIT_MASK_AGPIO_DRV) #define BIT_SET_AGPIO_DRV(x, v) (BIT_CLEAR_AGPIO_DRV(x) | BIT_AGPIO_DRV(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_REG_V15_3_TO_0_V1 7 #define BIT_MASK_REG_V15_3_TO_0_V1 0xf #define BIT_REG_V15_3_TO_0_V1(x) \ (((x) & BIT_MASK_REG_V15_3_TO_0_V1) << BIT_SHIFT_REG_V15_3_TO_0_V1) #define BITS_REG_V15_3_TO_0_V1 \ (BIT_MASK_REG_V15_3_TO_0_V1 << BIT_SHIFT_REG_V15_3_TO_0_V1) #define BIT_CLEAR_REG_V15_3_TO_0_V1(x) ((x) & (~BITS_REG_V15_3_TO_0_V1)) #define BIT_GET_REG_V15_3_TO_0_V1(x) \ (((x) >> BIT_SHIFT_REG_V15_3_TO_0_V1) & BIT_MASK_REG_V15_3_TO_0_V1) #define BIT_SET_REG_V15_3_TO_0_V1(x, v) \ (BIT_CLEAR_REG_V15_3_TO_0_V1(x) | BIT_REG_V15_3_TO_0_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_APLL_KVCO BIT(6) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_REG_SEL_LDO_PC BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_APLL_WDOGB BIT(4) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_REG_CC_1_TO_0_V1 4 #define BIT_MASK_REG_CC_1_TO_0_V1 0x3 #define BIT_REG_CC_1_TO_0_V1(x) \ (((x) & BIT_MASK_REG_CC_1_TO_0_V1) << BIT_SHIFT_REG_CC_1_TO_0_V1) #define BITS_REG_CC_1_TO_0_V1 \ (BIT_MASK_REG_CC_1_TO_0_V1 << BIT_SHIFT_REG_CC_1_TO_0_V1) #define BIT_CLEAR_REG_CC_1_TO_0_V1(x) ((x) & (~BITS_REG_CC_1_TO_0_V1)) #define BIT_GET_REG_CC_1_TO_0_V1(x) \ (((x) >> BIT_SHIFT_REG_CC_1_TO_0_V1) & BIT_MASK_REG_CC_1_TO_0_V1) #define BIT_SET_REG_CC_1_TO_0_V1(x, v) \ (BIT_CLEAR_REG_CC_1_TO_0_V1(x) | BIT_REG_CC_1_TO_0_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_APLL_EDGE_SEL BIT(3) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_CKDELAY_USB_V1 BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_APLL_FREF_SEL_BIT0 BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_CKDELAY_DIG_V1 BIT(2) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_POW_MAC (Offset 0x0028) */ #define BIT_POW_LDO15 BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_SHIFT_XTAL_CAP_XO 1 #define BIT_MASK_XTAL_CAP_XO 0x3f #define BIT_XTAL_CAP_XO(x) \ (((x) & BIT_MASK_XTAL_CAP_XO) << BIT_SHIFT_XTAL_CAP_XO) #define BITS_XTAL_CAP_XO (BIT_MASK_XTAL_CAP_XO << BIT_SHIFT_XTAL_CAP_XO) #define BIT_CLEAR_XTAL_CAP_XO(x) ((x) & (~BITS_XTAL_CAP_XO)) #define BIT_GET_XTAL_CAP_XO(x) \ (((x) >> BIT_SHIFT_XTAL_CAP_XO) & BIT_MASK_XTAL_CAP_XO) #define BIT_SET_XTAL_CAP_XO(x, v) \ (BIT_CLEAR_XTAL_CAP_XO(x) | BIT_XTAL_CAP_XO(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_MPLL_EN BIT(1) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_POW_MAC (Offset 0x0028) */ #define BIT_POW_SW BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_APLL_EN BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ #define BIT_POW_PLL BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ #define BIT_SHIFT_EXQ__FREEPG_V1 0 #define BIT_MASK_EXQ__FREEPG_V1 0xfff #define BIT_EXQ__FREEPG_V1(x) \ (((x) & BIT_MASK_EXQ__FREEPG_V1) << BIT_SHIFT_EXQ__FREEPG_V1) #define BITS_EXQ__FREEPG_V1 \ (BIT_MASK_EXQ__FREEPG_V1 << BIT_SHIFT_EXQ__FREEPG_V1) #define BIT_CLEAR_EXQ__FREEPG_V1(x) ((x) & (~BITS_EXQ__FREEPG_V1)) #define BIT_GET_EXQ__FREEPG_V1(x) \ (((x) >> BIT_SHIFT_EXQ__FREEPG_V1) & BIT_MASK_EXQ__FREEPG_V1) #define BIT_SET_EXQ__FREEPG_V1(x, v) \ (BIT_CLEAR_EXQ__FREEPG_V1(x) | BIT_EXQ__FREEPG_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ #define BIT_SHIFT_EXQ_FREEPG_V1 0 #define BIT_MASK_EXQ_FREEPG_V1 0xfff #define BIT_EXQ_FREEPG_V1(x) \ (((x) & BIT_MASK_EXQ_FREEPG_V1) << BIT_SHIFT_EXQ_FREEPG_V1) #define BITS_EXQ_FREEPG_V1 (BIT_MASK_EXQ_FREEPG_V1 << BIT_SHIFT_EXQ_FREEPG_V1) #define BIT_CLEAR_EXQ_FREEPG_V1(x) ((x) & (~BITS_EXQ_FREEPG_V1)) #define BIT_GET_EXQ_FREEPG_V1(x) \ (((x) >> BIT_SHIFT_EXQ_FREEPG_V1) & BIT_MASK_EXQ_FREEPG_V1) #define BIT_SET_EXQ_FREEPG_V1(x, v) \ (BIT_CLEAR_EXQ_FREEPG_V1(x) | BIT_EXQ_FREEPG_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_POW_MAC (Offset 0x0028) */ #define BIT_POW_LDO14 BIT(0) /* 2 REG_ANAPARLDO_POW_MAC (Offset 0x0029) */ #define BIT_LDOE25_POW_L BIT(0) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_POW_MAC (Offset 0x002A) */ #define BIT_REG_STANDBY_L BIT(19) #define BIT_PD_REGU_L BIT(18) #define BIT_EN_PC_BT_L BIT(17) #define BIT_SHIFT_REG_LDOADJ_L 13 #define BIT_MASK_REG_LDOADJ_L 0xf #define BIT_REG_LDOADJ_L(x) \ (((x) & BIT_MASK_REG_LDOADJ_L) << BIT_SHIFT_REG_LDOADJ_L) #define BITS_REG_LDOADJ_L (BIT_MASK_REG_LDOADJ_L << BIT_SHIFT_REG_LDOADJ_L) #define BIT_CLEAR_REG_LDOADJ_L(x) ((x) & (~BITS_REG_LDOADJ_L)) #define BIT_GET_REG_LDOADJ_L(x) \ (((x) >> BIT_SHIFT_REG_LDOADJ_L) & BIT_MASK_REG_LDOADJ_L) #define BIT_SET_REG_LDOADJ_L(x, v) \ (BIT_CLEAR_REG_LDOADJ_L(x) | BIT_REG_LDOADJ_L(v)) #define BIT_CK12M_EN BIT(11) #define BIT_CK12M_SEL BIT(10) #define BIT_EN_25_L BIT(9) #define BIT_EN_SLEEP BIT(8) #define BIT_DUMMY_V4 BIT(7) #define BIT_DUMMY_V3 BIT(6) #define BIT_DUMMY_V2 BIT(5) #define BIT_DUMMY_V1 BIT(4) #define BIT_SHIFT_LDOH12_V12ADJ_L 4 #define BIT_MASK_LDOH12_V12ADJ_L 0xf #define BIT_LDOH12_V12ADJ_L(x) \ (((x) & BIT_MASK_LDOH12_V12ADJ_L) << BIT_SHIFT_LDOH12_V12ADJ_L) #define BITS_LDOH12_V12ADJ_L \ (BIT_MASK_LDOH12_V12ADJ_L << BIT_SHIFT_LDOH12_V12ADJ_L) #define BIT_CLEAR_LDOH12_V12ADJ_L(x) ((x) & (~BITS_LDOH12_V12ADJ_L)) #define BIT_GET_LDOH12_V12ADJ_L(x) \ (((x) >> BIT_SHIFT_LDOH12_V12ADJ_L) & BIT_MASK_LDOH12_V12ADJ_L) #define BIT_SET_LDOH12_V12ADJ_L(x, v) \ (BIT_CLEAR_LDOH12_V12ADJ_L(x) | BIT_LDOH12_V12ADJ_L(v)) #define BIT_POW_PC_LDO_PORT1 BIT(3) #define BIT_POW_PC_LDO_PORT0 BIT(2) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_POW_MAC (Offset 0x002A) */ #define BIT_POW_PLL_V1 BIT(1) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_POW_MAC (Offset 0x002A) */ #define BIT_POW_POWER_CUT_POW_LDO BIT(0) #define BIT_SHIFT_LDOE25_V12ADJ_L_V1 0 #define BIT_MASK_LDOE25_V12ADJ_L_V1 0xf #define BIT_LDOE25_V12ADJ_L_V1(x) \ (((x) & BIT_MASK_LDOE25_V12ADJ_L_V1) << BIT_SHIFT_LDOE25_V12ADJ_L_V1) #define BITS_LDOE25_V12ADJ_L_V1 \ (BIT_MASK_LDOE25_V12ADJ_L_V1 << BIT_SHIFT_LDOE25_V12ADJ_L_V1) #define BIT_CLEAR_LDOE25_V12ADJ_L_V1(x) ((x) & (~BITS_LDOE25_V12ADJ_L_V1)) #define BIT_GET_LDOE25_V12ADJ_L_V1(x) \ (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_V1) & BIT_MASK_LDOE25_V12ADJ_L_V1) #define BIT_SET_LDOE25_V12ADJ_L_V1(x, v) \ (BIT_CLEAR_LDOE25_V12ADJ_L_V1(x) | BIT_LDOE25_V12ADJ_L_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_POW_XTAL (Offset 0x002B) */ #define BIT_PSTIMER_2 BIT(31) #define BIT_PSTIMER_1 BIT(30) #define BIT_PSTIMER_0 BIT(29) #define BIT_TXDMA_START_INT BIT(23) #define BIT_TXDMA_STOP_INT BIT(22) #define BIT_HISR7_IND BIT(21) #define BIT_HISR6_IND BIT(19) #define BIT_HISR5_IND BIT(18) #define BIT_HISR4_IND BIT(17) #define BIT_HISR3_IND BIT(14) #define BIT_HISR2_IND BIT(13) #define BIT_POW_XTAL BIT(1) #define BIT_POW_BG BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_XTAL_RF2_DRV 30 #define BIT_MASK_XTAL_RF2_DRV 0x3 #define BIT_XTAL_RF2_DRV(x) \ (((x) & BIT_MASK_XTAL_RF2_DRV) << BIT_SHIFT_XTAL_RF2_DRV) #define BITS_XTAL_RF2_DRV (BIT_MASK_XTAL_RF2_DRV << BIT_SHIFT_XTAL_RF2_DRV) #define BIT_CLEAR_XTAL_RF2_DRV(x) ((x) & (~BITS_XTAL_RF2_DRV)) #define BIT_GET_XTAL_RF2_DRV(x) \ (((x) >> BIT_SHIFT_XTAL_RF2_DRV) & BIT_MASK_XTAL_RF2_DRV) #define BIT_SET_XTAL_RF2_DRV(x, v) \ (BIT_CLEAR_XTAL_RF2_DRV(x) | BIT_XTAL_RF2_DRV(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_REG_REF_SEL_V3 BIT(30) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_XTAL_GMN_BIT4 BIT(29) #define BIT_XTAL_GMP_BIT4 BIT(28) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_XQSEL BIT(27) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_REG_FREF_SEL_2_TO_0 27 #define BIT_MASK_REG_FREF_SEL_2_TO_0 0x7 #define BIT_REG_FREF_SEL_2_TO_0(x) \ (((x) & BIT_MASK_REG_FREF_SEL_2_TO_0) << BIT_SHIFT_REG_FREF_SEL_2_TO_0) #define BITS_REG_FREF_SEL_2_TO_0 \ (BIT_MASK_REG_FREF_SEL_2_TO_0 << BIT_SHIFT_REG_FREF_SEL_2_TO_0) #define BIT_CLEAR_REG_FREF_SEL_2_TO_0(x) ((x) & (~BITS_REG_FREF_SEL_2_TO_0)) #define BIT_GET_REG_FREF_SEL_2_TO_0(x) \ (((x) >> BIT_SHIFT_REG_FREF_SEL_2_TO_0) & BIT_MASK_REG_FREF_SEL_2_TO_0) #define BIT_SET_REG_FREF_SEL_2_TO_0(x, v) \ (BIT_CLEAR_REG_FREF_SEL_2_TO_0(x) | BIT_REG_FREF_SEL_2_TO_0(v)) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_XQSEL_BIT0 BIT(27) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_APLL_DUMMY BIT(26) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1 21 #define BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1 0x3f #define BIT_XTAL_CADJ_XOUT_5_TO_0_V1(x) \ (((x) & BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1) \ << BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1) #define BITS_XTAL_CADJ_XOUT_5_TO_0_V1 \ (BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1 \ << BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1) #define BIT_CLEAR_XTAL_CADJ_XOUT_5_TO_0_V1(x) \ ((x) & (~BITS_XTAL_CADJ_XOUT_5_TO_0_V1)) #define BIT_GET_XTAL_CADJ_XOUT_5_TO_0_V1(x) \ (((x) >> BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1) & \ BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1) #define BIT_SET_XTAL_CADJ_XOUT_5_TO_0_V1(x, v) \ (BIT_CLEAR_XTAL_CADJ_XOUT_5_TO_0_V1(x) | \ BIT_XTAL_CADJ_XOUT_5_TO_0_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_XTAL_CADJ_XOUT 18 #define BIT_MASK_XTAL_CADJ_XOUT 0x3f #define BIT_XTAL_CADJ_XOUT(x) \ (((x) & BIT_MASK_XTAL_CADJ_XOUT) << BIT_SHIFT_XTAL_CADJ_XOUT) #define BITS_XTAL_CADJ_XOUT \ (BIT_MASK_XTAL_CADJ_XOUT << BIT_SHIFT_XTAL_CADJ_XOUT) #define BIT_CLEAR_XTAL_CADJ_XOUT(x) ((x) & (~BITS_XTAL_CADJ_XOUT)) #define BIT_GET_XTAL_CADJ_XOUT(x) \ (((x) >> BIT_SHIFT_XTAL_CADJ_XOUT) & BIT_MASK_XTAL_CADJ_XOUT) #define BIT_SET_XTAL_CADJ_XOUT(x, v) \ (BIT_CLEAR_XTAL_CADJ_XOUT(x) | BIT_XTAL_CADJ_XOUT(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_XTAL_CADJ_XIN_V2 15 #define BIT_MASK_XTAL_CADJ_XIN_V2 0x3f #define BIT_XTAL_CADJ_XIN_V2(x) \ (((x) & BIT_MASK_XTAL_CADJ_XIN_V2) << BIT_SHIFT_XTAL_CADJ_XIN_V2) #define BITS_XTAL_CADJ_XIN_V2 \ (BIT_MASK_XTAL_CADJ_XIN_V2 << BIT_SHIFT_XTAL_CADJ_XIN_V2) #define BIT_CLEAR_XTAL_CADJ_XIN_V2(x) ((x) & (~BITS_XTAL_CADJ_XIN_V2)) #define BIT_GET_XTAL_CADJ_XIN_V2(x) \ (((x) >> BIT_SHIFT_XTAL_CADJ_XIN_V2) & BIT_MASK_XTAL_CADJ_XIN_V2) #define BIT_SET_XTAL_CADJ_XIN_V2(x, v) \ (BIT_CLEAR_XTAL_CADJ_XIN_V2(x) | BIT_XTAL_CADJ_XIN_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_XTAL_CADJ_XIN 12 #define BIT_MASK_XTAL_CADJ_XIN 0x3f #define BIT_XTAL_CADJ_XIN(x) \ (((x) & BIT_MASK_XTAL_CADJ_XIN) << BIT_SHIFT_XTAL_CADJ_XIN) #define BITS_XTAL_CADJ_XIN (BIT_MASK_XTAL_CADJ_XIN << BIT_SHIFT_XTAL_CADJ_XIN) #define BIT_CLEAR_XTAL_CADJ_XIN(x) ((x) & (~BITS_XTAL_CADJ_XIN)) #define BIT_GET_XTAL_CADJ_XIN(x) \ (((x) >> BIT_SHIFT_XTAL_CADJ_XIN) & BIT_MASK_XTAL_CADJ_XIN) #define BIT_SET_XTAL_CADJ_XIN(x, v) \ (BIT_CLEAR_XTAL_CADJ_XIN(x) | BIT_XTAL_CADJ_XIN(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_REG_RS_V3 12 #define BIT_MASK_REG_RS_V3 0x7 #define BIT_REG_RS_V3(x) (((x) & BIT_MASK_REG_RS_V3) << BIT_SHIFT_REG_RS_V3) #define BITS_REG_RS_V3 (BIT_MASK_REG_RS_V3 << BIT_SHIFT_REG_RS_V3) #define BIT_CLEAR_REG_RS_V3(x) ((x) & (~BITS_REG_RS_V3)) #define BIT_GET_REG_RS_V3(x) (((x) >> BIT_SHIFT_REG_RS_V3) & BIT_MASK_REG_RS_V3) #define BIT_SET_REG_RS_V3(x, v) (BIT_CLEAR_REG_RS_V3(x) | BIT_REG_RS_V3(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ #define BIT_SDIO_BCNQ_EMPTY BIT(11) #define BIT_SDIO_HQQ_EMPTY BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_REG_RS 9 #define BIT_MASK_REG_RS 0x7 #define BIT_REG_RS(x) (((x) & BIT_MASK_REG_RS) << BIT_SHIFT_REG_RS) #define BITS_REG_RS (BIT_MASK_REG_RS << BIT_SHIFT_REG_RS) #define BIT_CLEAR_REG_RS(x) ((x) & (~BITS_REG_RS)) #define BIT_GET_REG_RS(x) (((x) >> BIT_SHIFT_REG_RS) & BIT_MASK_REG_RS) #define BIT_SET_REG_RS(x, v) (BIT_CLEAR_REG_RS(x) | BIT_REG_RS(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_REG_R3_V3 9 #define BIT_MASK_REG_R3_V3 0x7 #define BIT_REG_R3_V3(x) (((x) & BIT_MASK_REG_R3_V3) << BIT_SHIFT_REG_R3_V3) #define BITS_REG_R3_V3 (BIT_MASK_REG_R3_V3 << BIT_SHIFT_REG_R3_V3) #define BIT_CLEAR_REG_R3_V3(x) ((x) & (~BITS_REG_R3_V3)) #define BIT_GET_REG_R3_V3(x) (((x) >> BIT_SHIFT_REG_R3_V3) & BIT_MASK_REG_R3_V3) #define BIT_SET_REG_R3_V3(x, v) (BIT_CLEAR_REG_R3_V3(x) | BIT_REG_R3_V3(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ #define BIT_SDIO_MQQ_EMPTY BIT(9) #define BIT_SDIO_MGQ_CPU_EMPTY BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_PS_V2 7 #define BIT_MASK_PS_V2 0x7 #define BIT_PS_V2(x) (((x) & BIT_MASK_PS_V2) << BIT_SHIFT_PS_V2) #define BITS_PS_V2 (BIT_MASK_PS_V2 << BIT_SHIFT_PS_V2) #define BIT_CLEAR_PS_V2(x) ((x) & (~BITS_PS_V2)) #define BIT_GET_PS_V2(x) (((x) >> BIT_SHIFT_PS_V2) & BIT_MASK_PS_V2) #define BIT_SET_PS_V2(x, v) (BIT_CLEAR_PS_V2(x) | BIT_PS_V2(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_REG_CS_V3 7 #define BIT_MASK_REG_CS_V3 0x3 #define BIT_REG_CS_V3(x) (((x) & BIT_MASK_REG_CS_V3) << BIT_SHIFT_REG_CS_V3) #define BITS_REG_CS_V3 (BIT_MASK_REG_CS_V3 << BIT_SHIFT_REG_CS_V3) #define BIT_CLEAR_REG_CS_V3(x) ((x) & (~BITS_REG_CS_V3)) #define BIT_GET_REG_CS_V3(x) (((x) >> BIT_SHIFT_REG_CS_V3) & BIT_MASK_REG_CS_V3) #define BIT_SET_REG_CS_V3(x, v) (BIT_CLEAR_REG_CS_V3(x) | BIT_REG_CS_V3(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_PS 7 #define BIT_MASK_PS 0x7 #define BIT_PS(x) (((x) & BIT_MASK_PS) << BIT_SHIFT_PS) #define BITS_PS (BIT_MASK_PS << BIT_SHIFT_PS) #define BIT_CLEAR_PS(x) ((x) & (~BITS_PS)) #define BIT_GET_PS(x) (((x) >> BIT_SHIFT_PS) & BIT_MASK_PS) #define BIT_SET_PS(x, v) (BIT_CLEAR_PS(x) | BIT_PS(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ #define BIT_SDIO_AC7Q_EMPTY BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_REG_R3 6 #define BIT_MASK_REG_R3 0x7 #define BIT_REG_R3(x) (((x) & BIT_MASK_REG_R3) << BIT_SHIFT_REG_R3) #define BITS_REG_R3 (BIT_MASK_REG_R3 << BIT_SHIFT_REG_R3) #define BIT_CLEAR_REG_R3(x) ((x) & (~BITS_REG_R3)) #define BIT_GET_REG_R3(x) (((x) >> BIT_SHIFT_REG_R3) & BIT_MASK_REG_R3) #define BIT_SET_REG_R3(x, v) (BIT_CLEAR_REG_R3(x) | BIT_REG_R3(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_PSEN BIT(6) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ #define BIT_SDIO_AC6Q_EMPTY BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_DOGENB BIT(5) #endif #if (HALMAC_8814A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_REG_CP_V3 5 #define BIT_MASK_REG_CP_V3 0x3 #define BIT_REG_CP_V3(x) (((x) & BIT_MASK_REG_CP_V3) << BIT_SHIFT_REG_CP_V3) #define BITS_REG_CP_V3 (BIT_MASK_REG_CP_V3 << BIT_SHIFT_REG_CP_V3) #define BIT_CLEAR_REG_CP_V3(x) ((x) & (~BITS_REG_CP_V3)) #define BIT_GET_REG_CP_V3(x) (((x) >> BIT_SHIFT_REG_CP_V3) & BIT_MASK_REG_CP_V3) #define BIT_SET_REG_CP_V3(x, v) (BIT_CLEAR_REG_CP_V3(x) | BIT_REG_CP_V3(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ #define BIT_SDIO_AC5Q_EMPTY BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_REG_CS 4 #define BIT_MASK_REG_CS 0x3 #define BIT_REG_CS(x) (((x) & BIT_MASK_REG_CS) << BIT_SHIFT_REG_CS) #define BITS_REG_CS (BIT_MASK_REG_CS << BIT_SHIFT_REG_CS) #define BIT_CLEAR_REG_CS(x) ((x) & (~BITS_REG_CS)) #define BIT_GET_REG_CS(x) (((x) >> BIT_SHIFT_REG_CS) & BIT_MASK_REG_CS) #define BIT_SET_REG_CS(x, v) (BIT_CLEAR_REG_CS(x) | BIT_REG_CS(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_REG_MBIAS BIT(4) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ #define BIT_SDIO_AC4Q_EMPTY BIT(4) #endif #if (HALMAC_8814A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_REG_C3_V3 3 #define BIT_MASK_REG_C3_V3 0x3 #define BIT_REG_C3_V3(x) (((x) & BIT_MASK_REG_C3_V3) << BIT_SHIFT_REG_C3_V3) #define BITS_REG_C3_V3 (BIT_MASK_REG_C3_V3 << BIT_SHIFT_REG_C3_V3) #define BIT_CLEAR_REG_C3_V3(x) ((x) & (~BITS_REG_C3_V3)) #define BIT_GET_REG_C3_V3(x) (((x) >> BIT_SHIFT_REG_C3_V3) & BIT_MASK_REG_C3_V3) #define BIT_SET_REG_C3_V3(x, v) (BIT_CLEAR_REG_C3_V3(x) | BIT_REG_C3_V3(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ #define BIT_SDIO_AC3Q_EMPTY BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_REG_CP 2 #define BIT_MASK_REG_CP 0x3 #define BIT_REG_CP(x) (((x) & BIT_MASK_REG_CP) << BIT_SHIFT_REG_CP) #define BITS_REG_CP (BIT_MASK_REG_CP << BIT_SHIFT_REG_CP) #define BIT_CLEAR_REG_CP(x) ((x) & (~BITS_REG_CP)) #define BIT_GET_REG_CP(x) (((x) >> BIT_SHIFT_REG_CP) & BIT_MASK_REG_CP) #define BIT_SET_REG_CP(x, v) (BIT_CLEAR_REG_CP(x) | BIT_REG_CP(v)) #endif #if (HALMAC_8814A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_REG_320_SEL_V3 BIT(2) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ #define BIT_SDIO_AC2Q_EMPTY BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_EN_SYN_V1 BIT(1) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_REG_R3_V4 1 #define BIT_MASK_REG_R3_V4 0x7 #define BIT_REG_R3_V4(x) (((x) & BIT_MASK_REG_R3_V4) << BIT_SHIFT_REG_R3_V4) #define BITS_REG_R3_V4 (BIT_MASK_REG_R3_V4 << BIT_SHIFT_REG_R3_V4) #define BIT_CLEAR_REG_R3_V4(x) ((x) & (~BITS_REG_R3_V4)) #define BIT_GET_REG_R3_V4(x) (((x) >> BIT_SHIFT_REG_R3_V4) & BIT_MASK_REG_R3_V4) #define BIT_SET_REG_R3_V4(x, v) (BIT_CLEAR_REG_R3_V4(x) | BIT_REG_R3_V4(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ #define BIT_SDIO_AC1Q_EMPTY BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_SHIFT_REG_C3 0 #define BIT_MASK_REG_C3 0x3 #define BIT_REG_C3(x) (((x) & BIT_MASK_REG_C3) << BIT_SHIFT_REG_C3) #define BITS_REG_C3 (BIT_MASK_REG_C3 << BIT_SHIFT_REG_C3) #define BIT_CLEAR_REG_C3(x) ((x) & (~BITS_REG_C3)) #define BIT_GET_REG_C3(x) (((x) >> BIT_SHIFT_REG_C3) & BIT_MASK_REG_C3) #define BIT_SET_REG_C3(x, v) (BIT_CLEAR_REG_C3(x) | BIT_REG_C3(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_IOOFFSET_BIT4 BIT(0) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ #define BIT_REG_CP_BIT0 BIT(0) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ #define BIT_SDIO_AC0Q_EMPTY BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ #define BIT_EF_FLAG BIT(31) #define BIT_SHIFT_EF_PGPD 28 #define BIT_MASK_EF_PGPD 0x7 #define BIT_EF_PGPD(x) (((x) & BIT_MASK_EF_PGPD) << BIT_SHIFT_EF_PGPD) #define BITS_EF_PGPD (BIT_MASK_EF_PGPD << BIT_SHIFT_EF_PGPD) #define BIT_CLEAR_EF_PGPD(x) ((x) & (~BITS_EF_PGPD)) #define BIT_GET_EF_PGPD(x) (((x) >> BIT_SHIFT_EF_PGPD) & BIT_MASK_EF_PGPD) #define BIT_SET_EF_PGPD(x, v) (BIT_CLEAR_EF_PGPD(x) | BIT_EF_PGPD(v)) #define BIT_SHIFT_EF_RDT 24 #define BIT_MASK_EF_RDT 0xf #define BIT_EF_RDT(x) (((x) & BIT_MASK_EF_RDT) << BIT_SHIFT_EF_RDT) #define BITS_EF_RDT (BIT_MASK_EF_RDT << BIT_SHIFT_EF_RDT) #define BIT_CLEAR_EF_RDT(x) ((x) & (~BITS_EF_RDT)) #define BIT_GET_EF_RDT(x) (((x) >> BIT_SHIFT_EF_RDT) & BIT_MASK_EF_RDT) #define BIT_SET_EF_RDT(x, v) (BIT_CLEAR_EF_RDT(x) | BIT_EF_RDT(v)) #define BIT_SHIFT_EF_PGTS 20 #define BIT_MASK_EF_PGTS 0xf #define BIT_EF_PGTS(x) (((x) & BIT_MASK_EF_PGTS) << BIT_SHIFT_EF_PGTS) #define BITS_EF_PGTS (BIT_MASK_EF_PGTS << BIT_SHIFT_EF_PGTS) #define BIT_CLEAR_EF_PGTS(x) ((x) & (~BITS_EF_PGTS)) #define BIT_GET_EF_PGTS(x) (((x) >> BIT_SHIFT_EF_PGTS) & BIT_MASK_EF_PGTS) #define BIT_SET_EF_PGTS(x, v) (BIT_CLEAR_EF_PGTS(x) | BIT_EF_PGTS(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ #define BIT_EF_PDWN BIT(19) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ #define BIT_EF_ALDEN BIT(18) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */ #define BIT_SHIFT_HTSFR1 16 #define BIT_MASK_HTSFR1 0xffff #define BIT_HTSFR1(x) (((x) & BIT_MASK_HTSFR1) << BIT_SHIFT_HTSFR1) #define BITS_HTSFR1 (BIT_MASK_HTSFR1 << BIT_SHIFT_HTSFR1) #define BIT_CLEAR_HTSFR1(x) ((x) & (~BITS_HTSFR1)) #define BIT_GET_HTSFR1(x) (((x) >> BIT_SHIFT_HTSFR1) & BIT_MASK_HTSFR1) #define BIT_SET_HTSFR1(x, v) (BIT_CLEAR_HTSFR1(x) | BIT_HTSFR1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ #define BIT_SHIFT_EF_ADDR 8 #define BIT_MASK_EF_ADDR 0x3ff #define BIT_EF_ADDR(x) (((x) & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) #define BITS_EF_ADDR (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR) #define BIT_CLEAR_EF_ADDR(x) ((x) & (~BITS_EF_ADDR)) #define BIT_GET_EF_ADDR(x) (((x) >> BIT_SHIFT_EF_ADDR) & BIT_MASK_EF_ADDR) #define BIT_SET_EF_ADDR(x, v) (BIT_CLEAR_EF_ADDR(x) | BIT_EF_ADDR(v)) #define BIT_SHIFT_EF_DATA 0 #define BIT_MASK_EF_DATA 0xff #define BIT_EF_DATA(x) (((x) & BIT_MASK_EF_DATA) << BIT_SHIFT_EF_DATA) #define BITS_EF_DATA (BIT_MASK_EF_DATA << BIT_SHIFT_EF_DATA) #define BIT_CLEAR_EF_DATA(x) ((x) & (~BITS_EF_DATA)) #define BIT_GET_EF_DATA(x) (((x) >> BIT_SHIFT_EF_DATA) & BIT_MASK_EF_DATA) #define BIT_SET_EF_DATA(x, v) (BIT_CLEAR_EF_DATA(x) | BIT_EF_DATA(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */ #define BIT_SHIFT_HTSFR0 0 #define BIT_MASK_HTSFR0 0xffff #define BIT_HTSFR0(x) (((x) & BIT_MASK_HTSFR0) << BIT_SHIFT_HTSFR0) #define BITS_HTSFR0 (BIT_MASK_HTSFR0 << BIT_SHIFT_HTSFR0) #define BIT_CLEAR_HTSFR0(x) ((x) & (~BITS_HTSFR0)) #define BIT_GET_HTSFR0(x) (((x) >> BIT_SHIFT_HTSFR0) & BIT_MASK_HTSFR0) #define BIT_SET_HTSFR0(x, v) (BIT_CLEAR_HTSFR0(x) | BIT_HTSFR0(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ #define BIT_LDOE25_EN BIT(31) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ #define BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2 28 #define BIT_MASK_LDOE25_VADJ_BIT0_TO_2 0x7 #define BIT_LDOE25_VADJ_BIT0_TO_2(x) \ (((x) & BIT_MASK_LDOE25_VADJ_BIT0_TO_2) \ << BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2) #define BITS_LDOE25_VADJ_BIT0_TO_2 \ (BIT_MASK_LDOE25_VADJ_BIT0_TO_2 << BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2) #define BIT_CLEAR_LDOE25_VADJ_BIT0_TO_2(x) ((x) & (~BITS_LDOE25_VADJ_BIT0_TO_2)) #define BIT_GET_LDOE25_VADJ_BIT0_TO_2(x) \ (((x) >> BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2) & \ BIT_MASK_LDOE25_VADJ_BIT0_TO_2) #define BIT_SET_LDOE25_VADJ_BIT0_TO_2(x, v) \ (BIT_CLEAR_LDOE25_VADJ_BIT0_TO_2(x) | BIT_LDOE25_VADJ_BIT0_TO_2(v)) #define BIT_LDOE25_VADJ_BIT3 BIT(27) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ #define BIT_SHIFT_LDOE25_V12ADJ_L 27 #define BIT_MASK_LDOE25_V12ADJ_L 0xf #define BIT_LDOE25_V12ADJ_L(x) \ (((x) & BIT_MASK_LDOE25_V12ADJ_L) << BIT_SHIFT_LDOE25_V12ADJ_L) #define BITS_LDOE25_V12ADJ_L \ (BIT_MASK_LDOE25_V12ADJ_L << BIT_SHIFT_LDOE25_V12ADJ_L) #define BIT_CLEAR_LDOE25_V12ADJ_L(x) ((x) & (~BITS_LDOE25_V12ADJ_L)) #define BIT_GET_LDOE25_V12ADJ_L(x) \ (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L) & BIT_MASK_LDOE25_V12ADJ_L) #define BIT_SET_LDOE25_V12ADJ_L(x, v) \ (BIT_CLEAR_LDOE25_V12ADJ_L(x) | BIT_LDOE25_V12ADJ_L(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ #define BIT_SHIFT_LDOE25_VADJ_3_TO_0 27 #define BIT_MASK_LDOE25_VADJ_3_TO_0 0xf #define BIT_LDOE25_VADJ_3_TO_0(x) \ (((x) & BIT_MASK_LDOE25_VADJ_3_TO_0) << BIT_SHIFT_LDOE25_VADJ_3_TO_0) #define BITS_LDOE25_VADJ_3_TO_0 \ (BIT_MASK_LDOE25_VADJ_3_TO_0 << BIT_SHIFT_LDOE25_VADJ_3_TO_0) #define BIT_CLEAR_LDOE25_VADJ_3_TO_0(x) ((x) & (~BITS_LDOE25_VADJ_3_TO_0)) #define BIT_GET_LDOE25_VADJ_3_TO_0(x) \ (((x) >> BIT_SHIFT_LDOE25_VADJ_3_TO_0) & BIT_MASK_LDOE25_VADJ_3_TO_0) #define BIT_SET_LDOE25_VADJ_3_TO_0(x, v) \ (BIT_CLEAR_LDOE25_VADJ_3_TO_0(x) | BIT_LDOE25_VADJ_3_TO_0(v)) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ #define BIT_EFCRES_SEL BIT(26) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ #define BIT_EF_CSER BIT(26) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ #define BIT_EF_CRES_SEL BIT(26) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ #define BIT_SHIFT_EF_SCAN_START 16 #define BIT_MASK_EF_SCAN_START 0x1ff #define BIT_EF_SCAN_START(x) \ (((x) & BIT_MASK_EF_SCAN_START) << BIT_SHIFT_EF_SCAN_START) #define BITS_EF_SCAN_START (BIT_MASK_EF_SCAN_START << BIT_SHIFT_EF_SCAN_START) #define BIT_CLEAR_EF_SCAN_START(x) ((x) & (~BITS_EF_SCAN_START)) #define BIT_GET_EF_SCAN_START(x) \ (((x) >> BIT_SHIFT_EF_SCAN_START) & BIT_MASK_EF_SCAN_START) #define BIT_SET_EF_SCAN_START(x, v) \ (BIT_CLEAR_EF_SCAN_START(x) | BIT_EF_SCAN_START(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ #define BIT_SHIFT_EF_SCAN_START_V1 16 #define BIT_MASK_EF_SCAN_START_V1 0x3ff #define BIT_EF_SCAN_START_V1(x) \ (((x) & BIT_MASK_EF_SCAN_START_V1) << BIT_SHIFT_EF_SCAN_START_V1) #define BITS_EF_SCAN_START_V1 \ (BIT_MASK_EF_SCAN_START_V1 << BIT_SHIFT_EF_SCAN_START_V1) #define BIT_CLEAR_EF_SCAN_START_V1(x) ((x) & (~BITS_EF_SCAN_START_V1)) #define BIT_GET_EF_SCAN_START_V1(x) \ (((x) >> BIT_SHIFT_EF_SCAN_START_V1) & BIT_MASK_EF_SCAN_START_V1) #define BIT_SET_EF_SCAN_START_V1(x, v) \ (BIT_CLEAR_EF_SCAN_START_V1(x) | BIT_EF_SCAN_START_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ #define BIT_SHIFT_EF_SCAN_END 12 #define BIT_MASK_EF_SCAN_END 0xf #define BIT_EF_SCAN_END(x) \ (((x) & BIT_MASK_EF_SCAN_END) << BIT_SHIFT_EF_SCAN_END) #define BITS_EF_SCAN_END (BIT_MASK_EF_SCAN_END << BIT_SHIFT_EF_SCAN_END) #define BIT_CLEAR_EF_SCAN_END(x) ((x) & (~BITS_EF_SCAN_END)) #define BIT_GET_EF_SCAN_END(x) \ (((x) >> BIT_SHIFT_EF_SCAN_END) & BIT_MASK_EF_SCAN_END) #define BIT_SET_EF_SCAN_END(x, v) \ (BIT_CLEAR_EF_SCAN_END(x) | BIT_EF_SCAN_END(v)) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ #define BIT_EF_FORCE_PGMEN BIT(11) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ #define BIT_SCAN_EN BIT(11) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ #define BIT_EF_PD_DIS BIT(11) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ #define BIT_SW_PG_EN BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ #define BIT_SHIFT_EF_CELL_SEL 8 #define BIT_MASK_EF_CELL_SEL 0x3 #define BIT_EF_CELL_SEL(x) \ (((x) & BIT_MASK_EF_CELL_SEL) << BIT_SHIFT_EF_CELL_SEL) #define BITS_EF_CELL_SEL (BIT_MASK_EF_CELL_SEL << BIT_SHIFT_EF_CELL_SEL) #define BIT_CLEAR_EF_CELL_SEL(x) ((x) & (~BITS_EF_CELL_SEL)) #define BIT_GET_EF_CELL_SEL(x) \ (((x) >> BIT_SHIFT_EF_CELL_SEL) & BIT_MASK_EF_CELL_SEL) #define BIT_SET_EF_CELL_SEL(x, v) \ (BIT_CLEAR_EF_CELL_SEL(x) | BIT_EF_CELL_SEL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ #define BIT_EF_TRPT BIT(7) #define BIT_SHIFT_EF_TTHD 0 #define BIT_MASK_EF_TTHD 0x7f #define BIT_EF_TTHD(x) (((x) & BIT_MASK_EF_TTHD) << BIT_SHIFT_EF_TTHD) #define BITS_EF_TTHD (BIT_MASK_EF_TTHD << BIT_SHIFT_EF_TTHD) #define BIT_CLEAR_EF_TTHD(x) ((x) & (~BITS_EF_TTHD)) #define BIT_GET_EF_TTHD(x) (((x) >> BIT_SHIFT_EF_TTHD) & BIT_MASK_EF_TTHD) #define BIT_SET_EF_TTHD(x, v) (BIT_CLEAR_EF_TTHD(x) | BIT_EF_TTHD(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SHIFT_AFE_USB_CURRENT_SEL 26 #define BIT_MASK_AFE_USB_CURRENT_SEL 0x7 #define BIT_AFE_USB_CURRENT_SEL(x) \ (((x) & BIT_MASK_AFE_USB_CURRENT_SEL) << BIT_SHIFT_AFE_USB_CURRENT_SEL) #define BITS_AFE_USB_CURRENT_SEL \ (BIT_MASK_AFE_USB_CURRENT_SEL << BIT_SHIFT_AFE_USB_CURRENT_SEL) #define BIT_CLEAR_AFE_USB_CURRENT_SEL(x) ((x) & (~BITS_AFE_USB_CURRENT_SEL)) #define BIT_GET_AFE_USB_CURRENT_SEL(x) \ (((x) >> BIT_SHIFT_AFE_USB_CURRENT_SEL) & BIT_MASK_AFE_USB_CURRENT_SEL) #define BIT_SET_AFE_USB_CURRENT_SEL(x, v) \ (BIT_CLEAR_AFE_USB_CURRENT_SEL(x) | BIT_AFE_USB_CURRENT_SEL(v)) #define BIT_SHIFT_AFE_USB_PATH_SEL 24 #define BIT_MASK_AFE_USB_PATH_SEL 0x3 #define BIT_AFE_USB_PATH_SEL(x) \ (((x) & BIT_MASK_AFE_USB_PATH_SEL) << BIT_SHIFT_AFE_USB_PATH_SEL) #define BITS_AFE_USB_PATH_SEL \ (BIT_MASK_AFE_USB_PATH_SEL << BIT_SHIFT_AFE_USB_PATH_SEL) #define BIT_CLEAR_AFE_USB_PATH_SEL(x) ((x) & (~BITS_AFE_USB_PATH_SEL)) #define BIT_GET_AFE_USB_PATH_SEL(x) \ (((x) >> BIT_SHIFT_AFE_USB_PATH_SEL) & BIT_MASK_AFE_USB_PATH_SEL) #define BIT_SET_AFE_USB_PATH_SEL(x, v) \ (BIT_CLEAR_AFE_USB_PATH_SEL(x) | BIT_AFE_USB_PATH_SEL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SHIFT_DBG_SEL_V1 16 #define BIT_MASK_DBG_SEL_V1 0xff #define BIT_DBG_SEL_V1(x) (((x) & BIT_MASK_DBG_SEL_V1) << BIT_SHIFT_DBG_SEL_V1) #define BITS_DBG_SEL_V1 (BIT_MASK_DBG_SEL_V1 << BIT_SHIFT_DBG_SEL_V1) #define BIT_CLEAR_DBG_SEL_V1(x) ((x) & (~BITS_DBG_SEL_V1)) #define BIT_GET_DBG_SEL_V1(x) \ (((x) >> BIT_SHIFT_DBG_SEL_V1) & BIT_MASK_DBG_SEL_V1) #define BIT_SET_DBG_SEL_V1(x, v) (BIT_CLEAR_DBG_SEL_V1(x) | BIT_DBG_SEL_V1(v)) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_CLK_REQ_INPUT BIT(15) #define BIT_USB_XTAL_CLK_SEL BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SHIFT_DBG_SEL_BYTE 14 #define BIT_MASK_DBG_SEL_BYTE 0x3 #define BIT_DBG_SEL_BYTE(x) \ (((x) & BIT_MASK_DBG_SEL_BYTE) << BIT_SHIFT_DBG_SEL_BYTE) #define BITS_DBG_SEL_BYTE (BIT_MASK_DBG_SEL_BYTE << BIT_SHIFT_DBG_SEL_BYTE) #define BIT_CLEAR_DBG_SEL_BYTE(x) ((x) & (~BITS_DBG_SEL_BYTE)) #define BIT_GET_DBG_SEL_BYTE(x) \ (((x) >> BIT_SHIFT_DBG_SEL_BYTE) & BIT_MASK_DBG_SEL_BYTE) #define BIT_SET_DBG_SEL_BYTE(x, v) \ (BIT_CLEAR_DBG_SEL_BYTE(x) | BIT_DBG_SEL_BYTE(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_USB_REG_XTAL_SEL BIT(14) #define BIT_SYSON_BTIO1POW_PAD_E2 BIT(13) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SHIFT_SYSON_SPS0_STD_L1 12 #define BIT_MASK_SYSON_SPS0_STD_L1 0x3 #define BIT_SYSON_SPS0_STD_L1(x) \ (((x) & BIT_MASK_SYSON_SPS0_STD_L1) << BIT_SHIFT_SYSON_SPS0_STD_L1) #define BITS_SYSON_SPS0_STD_L1 \ (BIT_MASK_SYSON_SPS0_STD_L1 << BIT_SHIFT_SYSON_SPS0_STD_L1) #define BIT_CLEAR_SYSON_SPS0_STD_L1(x) ((x) & (~BITS_SYSON_SPS0_STD_L1)) #define BIT_GET_SYSON_SPS0_STD_L1(x) \ (((x) >> BIT_SHIFT_SYSON_SPS0_STD_L1) & BIT_MASK_SYSON_SPS0_STD_L1) #define BIT_SET_SYSON_SPS0_STD_L1(x, v) \ (BIT_CLEAR_SYSON_SPS0_STD_L1(x) | BIT_SYSON_SPS0_STD_L1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SHIFT_STD_L1_V1 12 #define BIT_MASK_STD_L1_V1 0x3 #define BIT_STD_L1_V1(x) (((x) & BIT_MASK_STD_L1_V1) << BIT_SHIFT_STD_L1_V1) #define BITS_STD_L1_V1 (BIT_MASK_STD_L1_V1 << BIT_SHIFT_STD_L1_V1) #define BIT_CLEAR_STD_L1_V1(x) ((x) & (~BITS_STD_L1_V1)) #define BIT_GET_STD_L1_V1(x) (((x) >> BIT_SHIFT_STD_L1_V1) & BIT_MASK_STD_L1_V1) #define BIT_SET_STD_L1_V1(x, v) (BIT_CLEAR_STD_L1_V1(x) | BIT_STD_L1_V1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SYSON_BTIOPOW_PAD_E2 BIT(12) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SHIFT_SYSON_LDOA12V_WT 12 #define BIT_MASK_SYSON_LDOA12V_WT 0x3 #define BIT_SYSON_LDOA12V_WT(x) \ (((x) & BIT_MASK_SYSON_LDOA12V_WT) << BIT_SHIFT_SYSON_LDOA12V_WT) #define BITS_SYSON_LDOA12V_WT \ (BIT_MASK_SYSON_LDOA12V_WT << BIT_SHIFT_SYSON_LDOA12V_WT) #define BIT_CLEAR_SYSON_LDOA12V_WT(x) ((x) & (~BITS_SYSON_LDOA12V_WT)) #define BIT_GET_SYSON_LDOA12V_WT(x) \ (((x) >> BIT_SHIFT_SYSON_LDOA12V_WT) & BIT_MASK_SYSON_LDOA12V_WT) #define BIT_SET_SYSON_LDOA12V_WT(x, v) \ (BIT_CLEAR_SYSON_LDOA12V_WT(x) | BIT_SYSON_LDOA12V_WT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SYSON_DBG_PAD_E2 BIT(11) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SYSON_SDIOPOW_PAD_E2 BIT(11) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SYSON_LED_PAD_E2 BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SYSON_GPEE_PAD_E2 BIT(9) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SYSON_GPEE_PAD_E2_V33 BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SYSON_PCI_PAD_E2 BIT(8) #define BIT_SHIFT_MATCH_CNT 8 #define BIT_MASK_MATCH_CNT 0xff #define BIT_MATCH_CNT(x) (((x) & BIT_MASK_MATCH_CNT) << BIT_SHIFT_MATCH_CNT) #define BITS_MATCH_CNT (BIT_MASK_MATCH_CNT << BIT_SHIFT_MATCH_CNT) #define BIT_CLEAR_MATCH_CNT(x) ((x) & (~BITS_MATCH_CNT)) #define BIT_GET_MATCH_CNT(x) (((x) >> BIT_SHIFT_MATCH_CNT) & BIT_MASK_MATCH_CNT) #define BIT_SET_MATCH_CNT(x, v) (BIT_CLEAR_MATCH_CNT(x) | BIT_MATCH_CNT(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_AUTO_SW_LDO_VOL_EN BIT(7) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HCPWM1_V2 (Offset 0x10250038) */ #define BIT_TOGGLE BIT(7) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_AUTO_SW_LDO_VOL_EN_V1 BIT(6) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_ADJ_LDO_VOLT BIT(6) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SHIFT_SYSON_LDOHCI12_WT 6 #define BIT_MASK_SYSON_LDOHCI12_WT 0x3 #define BIT_SYSON_LDOHCI12_WT(x) \ (((x) & BIT_MASK_SYSON_LDOHCI12_WT) << BIT_SHIFT_SYSON_LDOHCI12_WT) #define BITS_SYSON_LDOHCI12_WT \ (BIT_MASK_SYSON_LDOHCI12_WT << BIT_SHIFT_SYSON_LDOHCI12_WT) #define BIT_CLEAR_SYSON_LDOHCI12_WT(x) ((x) & (~BITS_SYSON_LDOHCI12_WT)) #define BIT_GET_SYSON_LDOHCI12_WT(x) \ (((x) >> BIT_SHIFT_SYSON_LDOHCI12_WT) & BIT_MASK_SYSON_LDOHCI12_WT) #define BIT_SET_SYSON_LDOHCI12_WT(x, v) \ (BIT_CLEAR_SYSON_LDOHCI12_WT(x) | BIT_SYSON_LDOHCI12_WT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SHIFT_SYSON_SPS0WWV_WT 4 #define BIT_MASK_SYSON_SPS0WWV_WT 0x3 #define BIT_SYSON_SPS0WWV_WT(x) \ (((x) & BIT_MASK_SYSON_SPS0WWV_WT) << BIT_SHIFT_SYSON_SPS0WWV_WT) #define BITS_SYSON_SPS0WWV_WT \ (BIT_MASK_SYSON_SPS0WWV_WT << BIT_SHIFT_SYSON_SPS0WWV_WT) #define BIT_CLEAR_SYSON_SPS0WWV_WT(x) ((x) & (~BITS_SYSON_SPS0WWV_WT)) #define BIT_GET_SYSON_SPS0WWV_WT(x) \ (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT) & BIT_MASK_SYSON_SPS0WWV_WT) #define BIT_SET_SYSON_SPS0WWV_WT(x, v) \ (BIT_CLEAR_SYSON_SPS0WWV_WT(x) | BIT_SYSON_SPS0WWV_WT(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SHIFT_SYSON_SPS0SPS_WT 4 #define BIT_MASK_SYSON_SPS0SPS_WT 0x3 #define BIT_SYSON_SPS0SPS_WT(x) \ (((x) & BIT_MASK_SYSON_SPS0SPS_WT) << BIT_SHIFT_SYSON_SPS0SPS_WT) #define BITS_SYSON_SPS0SPS_WT \ (BIT_MASK_SYSON_SPS0SPS_WT << BIT_SHIFT_SYSON_SPS0SPS_WT) #define BIT_CLEAR_SYSON_SPS0SPS_WT(x) ((x) & (~BITS_SYSON_SPS0SPS_WT)) #define BIT_GET_SYSON_SPS0SPS_WT(x) \ (((x) >> BIT_SHIFT_SYSON_SPS0SPS_WT) & BIT_MASK_SYSON_SPS0SPS_WT) #define BIT_SET_SYSON_SPS0SPS_WT(x, v) \ (BIT_CLEAR_SYSON_SPS0SPS_WT(x) | BIT_SYSON_SPS0SPS_WT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SHIFT_SYSON_SPS0LDO_WT 2 #define BIT_MASK_SYSON_SPS0LDO_WT 0x3 #define BIT_SYSON_SPS0LDO_WT(x) \ (((x) & BIT_MASK_SYSON_SPS0LDO_WT) << BIT_SHIFT_SYSON_SPS0LDO_WT) #define BITS_SYSON_SPS0LDO_WT \ (BIT_MASK_SYSON_SPS0LDO_WT << BIT_SHIFT_SYSON_SPS0LDO_WT) #define BIT_CLEAR_SYSON_SPS0LDO_WT(x) ((x) & (~BITS_SYSON_SPS0LDO_WT)) #define BIT_GET_SYSON_SPS0LDO_WT(x) \ (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT) & BIT_MASK_SYSON_SPS0LDO_WT) #define BIT_SET_SYSON_SPS0LDO_WT(x, v) \ (BIT_CLEAR_SYSON_SPS0LDO_WT(x) | BIT_SYSON_SPS0LDO_WT(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SHIFT_SYSON_SPS11VLDO_WT 2 #define BIT_MASK_SYSON_SPS11VLDO_WT 0x3 #define BIT_SYSON_SPS11VLDO_WT(x) \ (((x) & BIT_MASK_SYSON_SPS11VLDO_WT) << BIT_SHIFT_SYSON_SPS11VLDO_WT) #define BITS_SYSON_SPS11VLDO_WT \ (BIT_MASK_SYSON_SPS11VLDO_WT << BIT_SHIFT_SYSON_SPS11VLDO_WT) #define BIT_CLEAR_SYSON_SPS11VLDO_WT(x) ((x) & (~BITS_SYSON_SPS11VLDO_WT)) #define BIT_GET_SYSON_SPS11VLDO_WT(x) \ (((x) >> BIT_SHIFT_SYSON_SPS11VLDO_WT) & BIT_MASK_SYSON_SPS11VLDO_WT) #define BIT_SET_SYSON_SPS11VLDO_WT(x, v) \ (BIT_CLEAR_SYSON_SPS11VLDO_WT(x) | BIT_SYSON_SPS11VLDO_WT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ #define BIT_SHIFT_SYSON_RCLK_SCALE 0 #define BIT_MASK_SYSON_RCLK_SCALE 0x3 #define BIT_SYSON_RCLK_SCALE(x) \ (((x) & BIT_MASK_SYSON_RCLK_SCALE) << BIT_SHIFT_SYSON_RCLK_SCALE) #define BITS_SYSON_RCLK_SCALE \ (BIT_MASK_SYSON_RCLK_SCALE << BIT_SHIFT_SYSON_RCLK_SCALE) #define BIT_CLEAR_SYSON_RCLK_SCALE(x) ((x) & (~BITS_SYSON_RCLK_SCALE)) #define BIT_GET_SYSON_RCLK_SCALE(x) \ (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE) & BIT_MASK_SYSON_RCLK_SCALE) #define BIT_SET_SYSON_RCLK_SCALE(x, v) \ (BIT_CLEAR_SYSON_RCLK_SCALE(x) | BIT_SYSON_RCLK_SCALE(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HCPWM1_V2 (Offset 0x10250038) */ #define BIT_CUR_PS BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_CAL_TIMER (Offset 0x003C) */ #define BIT_SHIFT_CAL_SCAL 0 #define BIT_MASK_CAL_SCAL 0xff #define BIT_CAL_SCAL(x) (((x) & BIT_MASK_CAL_SCAL) << BIT_SHIFT_CAL_SCAL) #define BITS_CAL_SCAL (BIT_MASK_CAL_SCAL << BIT_SHIFT_CAL_SCAL) #define BIT_CLEAR_CAL_SCAL(x) ((x) & (~BITS_CAL_SCAL)) #define BIT_GET_CAL_SCAL(x) (((x) >> BIT_SHIFT_CAL_SCAL) & BIT_MASK_CAL_SCAL) #define BIT_SET_CAL_SCAL(x, v) (BIT_CLEAR_CAL_SCAL(x) | BIT_CAL_SCAL(v)) /* 2 REG_ACLK_MON (Offset 0x003E) */ #define BIT_SHIFT_RCLK_MON 5 #define BIT_MASK_RCLK_MON 0x7ff #define BIT_RCLK_MON(x) (((x) & BIT_MASK_RCLK_MON) << BIT_SHIFT_RCLK_MON) #define BITS_RCLK_MON (BIT_MASK_RCLK_MON << BIT_SHIFT_RCLK_MON) #define BIT_CLEAR_RCLK_MON(x) ((x) & (~BITS_RCLK_MON)) #define BIT_GET_RCLK_MON(x) (((x) >> BIT_SHIFT_RCLK_MON) & BIT_MASK_RCLK_MON) #define BIT_SET_RCLK_MON(x, v) (BIT_CLEAR_RCLK_MON(x) | BIT_RCLK_MON(v)) #define BIT_CAL_EN BIT(4) #define BIT_SHIFT_DPSTU 2 #define BIT_MASK_DPSTU 0x3 #define BIT_DPSTU(x) (((x) & BIT_MASK_DPSTU) << BIT_SHIFT_DPSTU) #define BITS_DPSTU (BIT_MASK_DPSTU << BIT_SHIFT_DPSTU) #define BIT_CLEAR_DPSTU(x) ((x) & (~BITS_DPSTU)) #define BIT_GET_DPSTU(x) (((x) >> BIT_SHIFT_DPSTU) & BIT_MASK_DPSTU) #define BIT_SET_DPSTU(x, v) (BIT_CLEAR_DPSTU(x) | BIT_DPSTU(v)) #define BIT_SUS_16X BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_ACLK_MON (Offset 0x003E) */ #define BIT_RSM_EN BIT(0) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG_2 (Offset 0x003F) */ #define BIT_SOUT_GPIO8 BIT(7) #define BIT_SOUT_GPIO5 BIT(6) #define BIT_RFE_CTRL_5_GPIO14_V1 BIT(5) #define BIT_RFE_CTRL_10_GPIO13_V1 BIT(4) #define BIT_RFE_CTRL_11_GPIO4_V1 BIT(3) #define BIT_RFE_CTRL_5_GPIO14 BIT(2) #define BIT_RFE_CTRL_10_GPIO13 BIT(1) #define BIT_RFE_CTRL_11_GPIO4 BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_PAD_D_PAPE_2G_E BIT(31) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_RFE_CTRL_3_GPIO12 BIT(31) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_PAD_D_PAPE_5G_E BIT(30) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_BT_RFE_CTRL_5_GPIO12 BIT(30) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_PAD_D_TRSW_E BIT(29) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_S0_TRSW_GPIO12 BIT(29) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_SIC_LOWEST_PRIORITY BIT(28) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_PAD_D_TRSWB_E BIT(28) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_RFE_CTRL_9_GPIO13 BIT(28) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_PAD_D_PAPE_2G_O BIT(27) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_RFE_CTRL_9_GPIO12 BIT(27) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_PAD_D_PAPE_5G_O BIT(26) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_RFE_CTRL_8_GPIO4 BIT(26) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_PAD_D_TRSW_O BIT(25) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_BT_RFE_CTRL_1_GPIO13 BIT(25) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_SHIFT_PIN_USECASE 24 #define BIT_MASK_PIN_USECASE 0xf #define BIT_PIN_USECASE(x) \ (((x) & BIT_MASK_PIN_USECASE) << BIT_SHIFT_PIN_USECASE) #define BITS_PIN_USECASE (BIT_MASK_PIN_USECASE << BIT_SHIFT_PIN_USECASE) #define BIT_CLEAR_PIN_USECASE(x) ((x) & (~BITS_PIN_USECASE)) #define BIT_GET_PIN_USECASE(x) \ (((x) >> BIT_SHIFT_PIN_USECASE) & BIT_MASK_PIN_USECASE) #define BIT_SET_PIN_USECASE(x, v) \ (BIT_CLEAR_PIN_USECASE(x) | BIT_PIN_USECASE(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_PAD_D_TRSWB_O BIT(24) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_EN_DATACPU_GPIO2 BIT(24) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_BT_RFE_CTRL_1_GPIO12 BIT(24) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_EN_A_ANTSEL BIT(23) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_EN_DATACPU_GPIO BIT(23) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_BT_RFE_CTRL_0_GPIO4 BIT(23) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_EN_A_ANTSELB BIT(22) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_EN_DATACPU_UART BIT(22) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_ANTSW_GPIO13 BIT(22) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_EN_D_PAPE_2G BIT(21) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_DATACPU_FSPI_EN BIT(21) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_ANTSW_GPIO12 BIT(21) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ #define BIT_INDIRECT_REG_RDY BIT(20) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_EN_D_PAPE_5G BIT(20) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_EN_GPIO8_UART_OUT BIT(20) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_ANTSWB_GPIO4 BIT(20) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_FSPI_EN BIT(19) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ #define BIT_INDIRECT_REG_R BIT(19) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_WL_RTS_EXT_32K_SEL BIT(18) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ #define BIT_INDIRECT_REG_W BIT(18) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_CKOUT33_EN BIT(17) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_XTAL_OUT_EN BIT(17) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_WLBT_DPDT_SEL_EN BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_WLGP_SPI_EN BIT(16) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ #define BIT_SHIFT_INDIRECT_REG_SIZE 16 #define BIT_MASK_INDIRECT_REG_SIZE 0x3 #define BIT_INDIRECT_REG_SIZE(x) \ (((x) & BIT_MASK_INDIRECT_REG_SIZE) << BIT_SHIFT_INDIRECT_REG_SIZE) #define BITS_INDIRECT_REG_SIZE \ (BIT_MASK_INDIRECT_REG_SIZE << BIT_SHIFT_INDIRECT_REG_SIZE) #define BIT_CLEAR_INDIRECT_REG_SIZE(x) ((x) & (~BITS_INDIRECT_REG_SIZE)) #define BIT_GET_INDIRECT_REG_SIZE(x) \ (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE) & BIT_MASK_INDIRECT_REG_SIZE) #define BIT_SET_INDIRECT_REG_SIZE(x, v) \ (BIT_CLEAR_INDIRECT_REG_SIZE(x) | BIT_INDIRECT_REG_SIZE(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_WLBT_LNAON_SEL_EN BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_SIC_LBK BIT(15) #define BIT_ENHTP BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_WLPHY_DBG_EN BIT(13) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_SIC_23 BIT(13) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_BT_AOD_GPIO3 BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_ENSIC BIT(12) #define BIT_SIC_SWRST BIT(11) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_PO_WIFI_PTA_PINS BIT(10) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_ENPMAC BIT(10) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_ENBTCMD BIT(9) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_BTCOEX_MBOX_EN BIT(9) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_BTCMD_OUT_EN BIT(9) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_PO_BT_PTA_PINS BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_ENUART BIT(8) #define BIT_SHIFT_BTMODE 6 #define BIT_MASK_BTMODE 0x3 #define BIT_BTMODE(x) (((x) & BIT_MASK_BTMODE) << BIT_SHIFT_BTMODE) #define BITS_BTMODE (BIT_MASK_BTMODE << BIT_SHIFT_BTMODE) #define BIT_CLEAR_BTMODE(x) ((x) & (~BITS_BTMODE)) #define BIT_GET_BTMODE(x) (((x) >> BIT_SHIFT_BTMODE) & BIT_MASK_BTMODE) #define BIT_SET_BTMODE(x, v) (BIT_CLEAR_BTMODE(x) | BIT_BTMODE(v)) #define BIT_ENBT BIT(5) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_GEN1GEN2_SWITCH BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_EROM_EN BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_WLRFE_6_7_EN BIT(3) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_EN_D_TRSW BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_WLRFE_4_5_EN BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_EN_D_TRSWB BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ #define BIT_SHIFT_GPIOSEL 0 #define BIT_MASK_GPIOSEL 0x3 #define BIT_GPIOSEL(x) (((x) & BIT_MASK_GPIOSEL) << BIT_SHIFT_GPIOSEL) #define BITS_GPIOSEL (BIT_MASK_GPIOSEL << BIT_SHIFT_GPIOSEL) #define BIT_CLEAR_GPIOSEL(x) ((x) & (~BITS_GPIOSEL)) #define BIT_GET_GPIOSEL(x) (((x) >> BIT_SHIFT_GPIOSEL) & BIT_MASK_GPIOSEL) #define BIT_SET_GPIOSEL(x, v) (BIT_CLEAR_GPIOSEL(x) | BIT_GPIOSEL(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ #define BIT_SHIFT_INDIRECT_REG_ADDR 0 #define BIT_MASK_INDIRECT_REG_ADDR 0xffff #define BIT_INDIRECT_REG_ADDR(x) \ (((x) & BIT_MASK_INDIRECT_REG_ADDR) << BIT_SHIFT_INDIRECT_REG_ADDR) #define BITS_INDIRECT_REG_ADDR \ (BIT_MASK_INDIRECT_REG_ADDR << BIT_SHIFT_INDIRECT_REG_ADDR) #define BIT_CLEAR_INDIRECT_REG_ADDR(x) ((x) & (~BITS_INDIRECT_REG_ADDR)) #define BIT_GET_INDIRECT_REG_ADDR(x) \ (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR) & BIT_MASK_INDIRECT_REG_ADDR) #define BIT_SET_INDIRECT_REG_ADDR(x, v) \ (BIT_CLEAR_INDIRECT_REG_ADDR(x) | BIT_INDIRECT_REG_ADDR(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_PIN_CTRL (Offset 0x0044) */ #define BIT_SHIFT_GPIO_MOD_7_TO_0 24 #define BIT_MASK_GPIO_MOD_7_TO_0 0xff #define BIT_GPIO_MOD_7_TO_0(x) \ (((x) & BIT_MASK_GPIO_MOD_7_TO_0) << BIT_SHIFT_GPIO_MOD_7_TO_0) #define BITS_GPIO_MOD_7_TO_0 \ (BIT_MASK_GPIO_MOD_7_TO_0 << BIT_SHIFT_GPIO_MOD_7_TO_0) #define BIT_CLEAR_GPIO_MOD_7_TO_0(x) ((x) & (~BITS_GPIO_MOD_7_TO_0)) #define BIT_GET_GPIO_MOD_7_TO_0(x) \ (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0) & BIT_MASK_GPIO_MOD_7_TO_0) #define BIT_SET_GPIO_MOD_7_TO_0(x, v) \ (BIT_CLEAR_GPIO_MOD_7_TO_0(x) | BIT_GPIO_MOD_7_TO_0(v)) #define BIT_SHIFT_GPIO_IO_SEL_7_TO_0 16 #define BIT_MASK_GPIO_IO_SEL_7_TO_0 0xff #define BIT_GPIO_IO_SEL_7_TO_0(x) \ (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0) #define BITS_GPIO_IO_SEL_7_TO_0 \ (BIT_MASK_GPIO_IO_SEL_7_TO_0 << BIT_SHIFT_GPIO_IO_SEL_7_TO_0) #define BIT_CLEAR_GPIO_IO_SEL_7_TO_0(x) ((x) & (~BITS_GPIO_IO_SEL_7_TO_0)) #define BIT_GET_GPIO_IO_SEL_7_TO_0(x) \ (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0) & BIT_MASK_GPIO_IO_SEL_7_TO_0) #define BIT_SET_GPIO_IO_SEL_7_TO_0(x, v) \ (BIT_CLEAR_GPIO_IO_SEL_7_TO_0(x) | BIT_GPIO_IO_SEL_7_TO_0(v)) #define BIT_SHIFT_GPIO_OUT_7_TO_0 8 #define BIT_MASK_GPIO_OUT_7_TO_0 0xff #define BIT_GPIO_OUT_7_TO_0(x) \ (((x) & BIT_MASK_GPIO_OUT_7_TO_0) << BIT_SHIFT_GPIO_OUT_7_TO_0) #define BITS_GPIO_OUT_7_TO_0 \ (BIT_MASK_GPIO_OUT_7_TO_0 << BIT_SHIFT_GPIO_OUT_7_TO_0) #define BIT_CLEAR_GPIO_OUT_7_TO_0(x) ((x) & (~BITS_GPIO_OUT_7_TO_0)) #define BIT_GET_GPIO_OUT_7_TO_0(x) \ (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0) & BIT_MASK_GPIO_OUT_7_TO_0) #define BIT_SET_GPIO_OUT_7_TO_0(x, v) \ (BIT_CLEAR_GPIO_OUT_7_TO_0(x) | BIT_GPIO_OUT_7_TO_0(v)) #define BIT_SHIFT_GPIO_IN_7_TO_0 0 #define BIT_MASK_GPIO_IN_7_TO_0 0xff #define BIT_GPIO_IN_7_TO_0(x) \ (((x) & BIT_MASK_GPIO_IN_7_TO_0) << BIT_SHIFT_GPIO_IN_7_TO_0) #define BITS_GPIO_IN_7_TO_0 \ (BIT_MASK_GPIO_IN_7_TO_0 << BIT_SHIFT_GPIO_IN_7_TO_0) #define BIT_CLEAR_GPIO_IN_7_TO_0(x) ((x) & (~BITS_GPIO_IN_7_TO_0)) #define BIT_GET_GPIO_IN_7_TO_0(x) \ (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0) & BIT_MASK_GPIO_IN_7_TO_0) #define BIT_SET_GPIO_IN_7_TO_0(x, v) \ (BIT_CLEAR_GPIO_IN_7_TO_0(x) | BIT_GPIO_IN_7_TO_0(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_INDIRECT_REG_DATA (Offset 0x10250044) */ #define BIT_SHIFT_INDIRECT_REG_DATA 0 #define BIT_MASK_INDIRECT_REG_DATA 0xffffffffL #define BIT_INDIRECT_REG_DATA(x) \ (((x) & BIT_MASK_INDIRECT_REG_DATA) << BIT_SHIFT_INDIRECT_REG_DATA) #define BITS_INDIRECT_REG_DATA \ (BIT_MASK_INDIRECT_REG_DATA << BIT_SHIFT_INDIRECT_REG_DATA) #define BIT_CLEAR_INDIRECT_REG_DATA(x) ((x) & (~BITS_INDIRECT_REG_DATA)) #define BIT_GET_INDIRECT_REG_DATA(x) \ (((x) >> BIT_SHIFT_INDIRECT_REG_DATA) & BIT_MASK_INDIRECT_REG_DATA) #define BIT_SET_INDIRECT_REG_DATA(x, v) \ (BIT_CLEAR_INDIRECT_REG_DATA(x) | BIT_INDIRECT_REG_DATA(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ #define BIT_SHIFT_MUXDBG_SEL 30 #define BIT_MASK_MUXDBG_SEL 0x3 #define BIT_MUXDBG_SEL(x) (((x) & BIT_MASK_MUXDBG_SEL) << BIT_SHIFT_MUXDBG_SEL) #define BITS_MUXDBG_SEL (BIT_MASK_MUXDBG_SEL << BIT_SHIFT_MUXDBG_SEL) #define BIT_CLEAR_MUXDBG_SEL(x) ((x) & (~BITS_MUXDBG_SEL)) #define BIT_GET_MUXDBG_SEL(x) \ (((x) >> BIT_SHIFT_MUXDBG_SEL) & BIT_MASK_MUXDBG_SEL) #define BIT_SET_MUXDBG_SEL(x, v) (BIT_CLEAR_MUXDBG_SEL(x) | BIT_MUXDBG_SEL(v)) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ #define BIT_SHIFT_MUXDBG_SEL2 28 #define BIT_MASK_MUXDBG_SEL2 0x3 #define BIT_MUXDBG_SEL2(x) \ (((x) & BIT_MASK_MUXDBG_SEL2) << BIT_SHIFT_MUXDBG_SEL2) #define BITS_MUXDBG_SEL2 (BIT_MASK_MUXDBG_SEL2 << BIT_SHIFT_MUXDBG_SEL2) #define BIT_CLEAR_MUXDBG_SEL2(x) ((x) & (~BITS_MUXDBG_SEL2)) #define BIT_GET_MUXDBG_SEL2(x) \ (((x) >> BIT_SHIFT_MUXDBG_SEL2) & BIT_MASK_MUXDBG_SEL2) #define BIT_SET_MUXDBG_SEL2(x, v) \ (BIT_CLEAR_MUXDBG_SEL2(x) | BIT_MUXDBG_SEL2(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ #define BIT_GPIO_EXT_EN BIT(20) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ #define BIT_EXTWOL1_SEL BIT(19) #define BIT_EXTWOL1_EN BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ #define BIT_EXTWOL0_SEL BIT(17) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ #define BIT_EXTWOL_SEL BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ #define BIT_EXTWOL0_EN BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ #define BIT_EXTWOL_EN BIT(16) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ #define BIT_SHIFT_GPIO_EXT_WOL_V1 16 #define BIT_MASK_GPIO_EXT_WOL_V1 0xf #define BIT_GPIO_EXT_WOL_V1(x) \ (((x) & BIT_MASK_GPIO_EXT_WOL_V1) << BIT_SHIFT_GPIO_EXT_WOL_V1) #define BITS_GPIO_EXT_WOL_V1 \ (BIT_MASK_GPIO_EXT_WOL_V1 << BIT_SHIFT_GPIO_EXT_WOL_V1) #define BIT_CLEAR_GPIO_EXT_WOL_V1(x) ((x) & (~BITS_GPIO_EXT_WOL_V1)) #define BIT_GET_GPIO_EXT_WOL_V1(x) \ (((x) >> BIT_SHIFT_GPIO_EXT_WOL_V1) & BIT_MASK_GPIO_EXT_WOL_V1) #define BIT_SET_GPIO_EXT_WOL_V1(x, v) \ (BIT_CLEAR_GPIO_EXT_WOL_V1(x) | BIT_GPIO_EXT_WOL_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_INTM (Offset 0x0048) */ #define BIT_GPIOF_INT_MD BIT(15) #define BIT_GPIOE_INT_MD BIT(14) #define BIT_GPIOD_INT_MD BIT(13) #define BIT_GPIOC_INT_MD BIT(12) #define BIT_GPIOB_INT_MD BIT(11) #define BIT_GPIOA_INT_MD BIT(10) #define BIT_GPIO9_INT_MD BIT(9) #define BIT_GPIO8_INT_MD BIT(8) #define BIT_GPIO7_INT_MD BIT(7) #define BIT_GPIO6_INT_MD BIT(6) #define BIT_GPIO5_INT_MD BIT(5) #define BIT_GPIO4_INT_MD BIT(4) #define BIT_GPIO3_INT_MD BIT(3) #define BIT_GPIO2_INT_MD BIT(2) #define BIT_GPIO1_INT_MD BIT(1) #define BIT_GPIO0_INT_MD BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_PAD_ANTSEL_I BIT(31) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_MAILBOX_1WIRE_GPIO_CFG BIT(31) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_ANT_SEL7_EN BIT(30) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_PAD_ANTSELB_I BIT(30) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_BT_RF_GPIO_CFG BIT(30) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_ANT_SEL46_EN BIT(29) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_PAD_D_PAPE_2G_I BIT(29) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_BT_SDIO_INT_GPIO_CFG BIT(29) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_ANT_SEL3_EN BIT(28) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_PAD_D_PAPE_5G_I BIT(28) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_MAILBOX_3WIRE_GPIO_CFG BIT(28) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_TRSW_SEL_EN BIT(27) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_PAD_D_TRSW_I BIT(27) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_GPIO3_WL_CTRL_EN BIT(27) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_WLBT_PAPE_SEL_EN BIT(27) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_PAPE1_SEL_EN BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_LNAON_SEL_EN BIT(26) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_PAD_D_TRSWB_I BIT(26) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_PAPE0_SEL_EN BIT(25) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_PAPE_SEL_EN BIT(25) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_DWH_EN BIT(25) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_ANTSEL2_EN BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_DPDT_WLBT_SEL BIT(24) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_DHW_EN BIT(24) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_RFE_ANT_EXT_SEL BIT(24) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_ANTSEL_EN BIT(23) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_DPDT_SEL_EN BIT(23) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_GPIO13_14_WL_CTRL_EN BIT(22) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_LED2DIS_V1 BIT(22) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_TRXIQ_DBG_EN BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_LED2DIS BIT(21) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_LED2EN BIT(21) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_LED2PL BIT(20) #define BIT_LED2SV BIT(19) #define BIT_SHIFT_LED2CM 16 #define BIT_MASK_LED2CM 0x7 #define BIT_LED2CM(x) (((x) & BIT_MASK_LED2CM) << BIT_SHIFT_LED2CM) #define BITS_LED2CM (BIT_MASK_LED2CM << BIT_SHIFT_LED2CM) #define BIT_CLEAR_LED2CM(x) ((x) & (~BITS_LED2CM)) #define BIT_GET_LED2CM(x) (((x) >> BIT_SHIFT_LED2CM) & BIT_MASK_LED2CM) #define BIT_SET_LED2CM(x, v) (BIT_CLEAR_LED2CM(x) | BIT_LED2CM(v)) #define BIT_LED1DIS BIT(15) #define BIT_LED1PL BIT(12) #define BIT_LED1SV BIT(11) #define BIT_SHIFT_LED1CM 8 #define BIT_MASK_LED1CM 0x7 #define BIT_LED1CM(x) (((x) & BIT_MASK_LED1CM) << BIT_SHIFT_LED1CM) #define BITS_LED1CM (BIT_MASK_LED1CM << BIT_SHIFT_LED1CM) #define BIT_CLEAR_LED1CM(x) ((x) & (~BITS_LED1CM)) #define BIT_GET_LED1CM(x) (((x) >> BIT_SHIFT_LED1CM) & BIT_MASK_LED1CM) #define BIT_SET_LED1CM(x, v) (BIT_CLEAR_LED1CM(x) | BIT_LED1CM(v)) #define BIT_LED0DIS BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_SHIFT_AFE_LDO_SWR_CHECK 5 #define BIT_MASK_AFE_LDO_SWR_CHECK 0x3 #define BIT_AFE_LDO_SWR_CHECK(x) \ (((x) & BIT_MASK_AFE_LDO_SWR_CHECK) << BIT_SHIFT_AFE_LDO_SWR_CHECK) #define BITS_AFE_LDO_SWR_CHECK \ (BIT_MASK_AFE_LDO_SWR_CHECK << BIT_SHIFT_AFE_LDO_SWR_CHECK) #define BIT_CLEAR_AFE_LDO_SWR_CHECK(x) ((x) & (~BITS_AFE_LDO_SWR_CHECK)) #define BIT_GET_AFE_LDO_SWR_CHECK(x) \ (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK) & BIT_MASK_AFE_LDO_SWR_CHECK) #define BIT_SET_AFE_LDO_SWR_CHECK(x, v) \ (BIT_CLEAR_AFE_LDO_SWR_CHECK(x) | BIT_AFE_LDO_SWR_CHECK(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ #define BIT_LED0PL BIT(4) #define BIT_LED0SV BIT(3) #define BIT_SHIFT_LED0CM 0 #define BIT_MASK_LED0CM 0x7 #define BIT_LED0CM(x) (((x) & BIT_MASK_LED0CM) << BIT_SHIFT_LED0CM) #define BITS_LED0CM (BIT_MASK_LED0CM << BIT_SHIFT_LED0CM) #define BIT_CLEAR_LED0CM(x) ((x) & (~BITS_LED0CM)) #define BIT_GET_LED0CM(x) (((x) >> BIT_SHIFT_LED0CM) & BIT_MASK_LED0CM) #define BIT_SET_LED0CM(x, v) (BIT_CLEAR_LED0CM(x) | BIT_LED0CM(v)) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_PDNINT_EN BIT(31) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_NFC_INT_PAD_EN BIT(30) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_SPS_OCP_INT_EN BIT(29) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_SW_SPS_OCP_INT_EN BIT(29) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_PWMERR_INT_EN BIT(28) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_PWM_HW_ERR_EN BIT(28) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIOF_INT_EN BIT(27) #define BIT_FS_GPIOE_INT_EN BIT(26) #define BIT_FS_GPIOD_INT_EN BIT(25) #define BIT_FS_GPIOC_INT_EN BIT(24) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_ACT2RECOVERY_INT_EN BIT(24) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIOB_INT_EN BIT(23) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_PCIE_GEN12_SWITCH_EN BIT(23) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIOA_INT_EN BIT(22) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_HCI_SUS_EN_V1 BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO9_INT_EN BIT(21) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_HCI_RES_EN_V1 BIT(21) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO8_INT_EN BIT(20) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_HCI_RESET_EN_V1 BIT(20) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO7_INT_EN BIT(19) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_32K_LEAVE_SETTING_EN BIT(19) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO6_INT_EN BIT(18) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_32K_ENTER_SETTING_EN BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO5_INT_EN BIT(17) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_SIE_LPM_RSM_EN_V1 BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO4_INT_EN BIT(16) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_SIE_LPM_ACT_EN_V1 BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO3_INT_EN BIT(15) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIOF_INT_EN_V1 BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO2_INT_EN BIT(14) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIOE_INT_EN_V1 BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO1_INT_EN BIT(13) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIOD_INT_EN_V1 BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO0_INT_EN BIT(12) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIOC_INT_EN_V1 BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_HCI_SUS_EN BIT(11) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIOB_INT_EN_V1 BIT(11) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_HCI_RES_EN BIT(10) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIOA_INT_EN_V1 BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_HCI_RESET_EN BIT(9) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO9_INT_EN_V1 BIT(9) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_AXI_EXCEPT_FINT_EN BIT(8) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO8_INT_EN_V1 BIT(8) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_USB_SCSI_CMD_EN BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_BTON_STS_UPDATE_MSK_EN BIT(7) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO7_INT_EN_V1 BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_ACT2RECOVERY_INT_EN_V1 BIT(6) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO6_INT_EN_V1 BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_TRPC_TO_INT_EN BIT(5) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO5_INT_EN_V1 BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_RPC_O_T_INT_EN BIT(4) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO4_INT_EN_V1 BIT(4) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_HCI_TXDMA_REQ_HIMR BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_32K_LEAVE_SETTING_MAK BIT(3) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO3_INT_EN_V1 BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_32K_ENTER_SETTING_MAK BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO2_INT_EN_V1 BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_USB_LPMRSM_MSK BIT(1) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO1_INT_EN_V1 BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_USB_LPMINT_MSK BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ #define BIT_FS_GPIO0_INT_EN_V1 BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_PDNINT BIT(31) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_SPS_OCP_INT BIT(29) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_SW_SPS_OCP_INT BIT(29) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_PWMERR_INT BIT(28) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_PWM_HW_ERR BIT(28) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIOF_INT BIT(27) #define BIT_FS_GPIOE_INT BIT(26) #define BIT_FS_GPIOD_INT BIT(25) #define BIT_FS_GPIOC_INT BIT(24) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_ACT2RECOVERY_INT BIT(24) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIOB_INT BIT(23) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_PCIE_GEN12_SWITCH BIT(23) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIOA_INT BIT(22) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_HCI_SUS_V1 BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO9_INT BIT(21) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_HCI_RES_V1 BIT(21) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO8_INT BIT(20) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_HCI_RESET_V1 BIT(20) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO7_INT BIT(19) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_32K_LEAVE_SETTING BIT(19) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO6_INT BIT(18) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_32K_ENTER_SETTING BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO5_INT BIT(17) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_SIE_LPM_RSM_V1 BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO4_INT BIT(16) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_SIE_LPM_ACT_V1 BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO3_INT BIT(15) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIOF_INT_V1 BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO2_INT BIT(14) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIOE_INT_V1 BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO1_INT BIT(13) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIOD_INT_V1 BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO0_INT BIT(12) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIOC_INT_V1 BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_HCI_SUS_INT BIT(11) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIOB_INT_V1 BIT(11) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_HCI_RES_INT BIT(10) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIOA_INT_V1 BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_HCI_RESET_INT BIT(9) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO9_INT_V1 BIT(9) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_AXI_EXCEPT_FINT BIT(8) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO8_INT_V1 BIT(8) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_USB_SCSI_CMD_INT BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_BTON_STS_UPDATE_INT BIT(7) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO7_INT_V1 BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_ACT2RECOVERY_INT_V1 BIT(6) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO6_INT_V1 BIT(6) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_ACT2RECOVERY BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_TRPC_TO_INT_INT BIT(5) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO5_INT_V1 BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_RPC_O_T_INT_INT BIT(4) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO4_INT_V1 BIT(4) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_HCI_TXDMA_REQ_HISR BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_32K_LEAVE_SETTING_INT BIT(3) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO3_INT_V1 BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_32K_ENTER_SETTING_INT BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO2_INT_V1 BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_USB_LPMRSM_INT BIT(1) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO1_INT_V1 BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_USB_LPMINT_INT BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ #define BIT_FS_GPIO0_INT_V1 BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ #define BIT_GPIOF_INT_EN BIT(31) #define BIT_GPIOE_INT_EN BIT(30) #define BIT_GPIOD_INT_EN BIT(29) #define BIT_GPIOC_INT_EN BIT(28) #define BIT_GPIOB_INT_EN BIT(27) #define BIT_GPIOA_INT_EN BIT(26) #define BIT_GPIO9_INT_EN BIT(25) #define BIT_GPIO8_INT_EN BIT(24) #define BIT_GPIO7_INT_EN BIT(23) #define BIT_GPIO6_INT_EN BIT(22) #define BIT_GPIO5_INT_EN BIT(21) #define BIT_GPIO4_INT_EN BIT(20) #define BIT_GPIO3_INT_EN BIT(19) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ #define BIT_GPIO2_INT_EN BIT(18) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ #define BIT_GPIO2_INT_EN_V1 BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ #define BIT_GPIO1_INT_EN BIT(17) #define BIT_GPIO0_INT_EN BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ #define BIT_AXI_EXCEPT_HINT_EN BIT(9) #define BIT_PDNINT_EN_V2 BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ #define BIT_PDNINT_EN BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ #define BIT_PDNINT_EN_V1 BIT(7) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ #define BIT_PDN_INT_EN BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ #define BIT_RON_INT_EN BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ #define BIT_RON_INT_EN_V1 BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ #define BIT_SPS_OCP_INT_EN BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ #define BIT_SPS_OCP_INT_EN_V1 BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ #define BIT_GPIO15_0_INT_EN BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ #define BIT_GPIO15_0_INT_EN_V1 BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ #define BIT_GPIOF_INT BIT(31) #define BIT_GPIOE_INT BIT(30) #define BIT_GPIOD_INT BIT(29) #define BIT_GPIOC_INT BIT(28) #define BIT_GPIOB_INT BIT(27) #define BIT_GPIOA_INT BIT(26) #define BIT_GPIO9_INT BIT(25) #define BIT_GPIO8_INT BIT(24) #define BIT_GPIO7_INT BIT(23) #define BIT_GPIO6_INT BIT(22) #define BIT_GPIO5_INT BIT(21) #define BIT_GPIO4_INT BIT(20) #define BIT_GPIO3_INT BIT(19) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ #define BIT_GPIO2_INT BIT(18) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ #define BIT_GPIO2_INT_V1 BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ #define BIT_GPIO1_INT BIT(17) #define BIT_GPIO0_INT BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ #define BIT_AXI_EXCEPT_HINT BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ #define BIT_PDNINT BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ #define BIT_PDNINT_V1 BIT(7) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ #define BIT_PDN_INT BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ #define BIT_RON_INT BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ #define BIT_RON_INT_V1 BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ #define BIT_SPS_OCP_INT BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ #define BIT_SPS_OCP_INT_V1 BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ #define BIT_GPIO15_0_INT BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ #define BIT_GPIO15_0_INT_V1 BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_EXT_CTRL (Offset 0x0060) */ #define BIT_SHIFT_GPIO_MOD_15_TO_8 24 #define BIT_MASK_GPIO_MOD_15_TO_8 0xff #define BIT_GPIO_MOD_15_TO_8(x) \ (((x) & BIT_MASK_GPIO_MOD_15_TO_8) << BIT_SHIFT_GPIO_MOD_15_TO_8) #define BITS_GPIO_MOD_15_TO_8 \ (BIT_MASK_GPIO_MOD_15_TO_8 << BIT_SHIFT_GPIO_MOD_15_TO_8) #define BIT_CLEAR_GPIO_MOD_15_TO_8(x) ((x) & (~BITS_GPIO_MOD_15_TO_8)) #define BIT_GET_GPIO_MOD_15_TO_8(x) \ (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8) & BIT_MASK_GPIO_MOD_15_TO_8) #define BIT_SET_GPIO_MOD_15_TO_8(x, v) \ (BIT_CLEAR_GPIO_MOD_15_TO_8(x) | BIT_GPIO_MOD_15_TO_8(v)) #define BIT_SHIFT_GPIO_IO_SEL_15_TO_8 16 #define BIT_MASK_GPIO_IO_SEL_15_TO_8 0xff #define BIT_GPIO_IO_SEL_15_TO_8(x) \ (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8) #define BITS_GPIO_IO_SEL_15_TO_8 \ (BIT_MASK_GPIO_IO_SEL_15_TO_8 << BIT_SHIFT_GPIO_IO_SEL_15_TO_8) #define BIT_CLEAR_GPIO_IO_SEL_15_TO_8(x) ((x) & (~BITS_GPIO_IO_SEL_15_TO_8)) #define BIT_GET_GPIO_IO_SEL_15_TO_8(x) \ (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8) & BIT_MASK_GPIO_IO_SEL_15_TO_8) #define BIT_SET_GPIO_IO_SEL_15_TO_8(x, v) \ (BIT_CLEAR_GPIO_IO_SEL_15_TO_8(x) | BIT_GPIO_IO_SEL_15_TO_8(v)) #define BIT_SHIFT_GPIO_OUT_15_TO_8 8 #define BIT_MASK_GPIO_OUT_15_TO_8 0xff #define BIT_GPIO_OUT_15_TO_8(x) \ (((x) & BIT_MASK_GPIO_OUT_15_TO_8) << BIT_SHIFT_GPIO_OUT_15_TO_8) #define BITS_GPIO_OUT_15_TO_8 \ (BIT_MASK_GPIO_OUT_15_TO_8 << BIT_SHIFT_GPIO_OUT_15_TO_8) #define BIT_CLEAR_GPIO_OUT_15_TO_8(x) ((x) & (~BITS_GPIO_OUT_15_TO_8)) #define BIT_GET_GPIO_OUT_15_TO_8(x) \ (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8) & BIT_MASK_GPIO_OUT_15_TO_8) #define BIT_SET_GPIO_OUT_15_TO_8(x, v) \ (BIT_CLEAR_GPIO_OUT_15_TO_8(x) | BIT_GPIO_OUT_15_TO_8(v)) #define BIT_SHIFT_GPIO_IN_15_TO_8 0 #define BIT_MASK_GPIO_IN_15_TO_8 0xff #define BIT_GPIO_IN_15_TO_8(x) \ (((x) & BIT_MASK_GPIO_IN_15_TO_8) << BIT_SHIFT_GPIO_IN_15_TO_8) #define BITS_GPIO_IN_15_TO_8 \ (BIT_MASK_GPIO_IN_15_TO_8 << BIT_SHIFT_GPIO_IN_15_TO_8) #define BIT_CLEAR_GPIO_IN_15_TO_8(x) ((x) & (~BITS_GPIO_IN_15_TO_8)) #define BIT_GET_GPIO_IN_15_TO_8(x) \ (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8) & BIT_MASK_GPIO_IN_15_TO_8) #define BIT_SET_GPIO_IN_15_TO_8(x, v) \ (BIT_CLEAR_GPIO_IN_15_TO_8(x) | BIT_GPIO_IN_15_TO_8(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_H2C (Offset 0x10250060) */ #define BIT_SHIFT_SDIO_H2C_MSG 0 #define BIT_MASK_SDIO_H2C_MSG 0xffffffffL #define BIT_SDIO_H2C_MSG(x) \ (((x) & BIT_MASK_SDIO_H2C_MSG) << BIT_SHIFT_SDIO_H2C_MSG) #define BITS_SDIO_H2C_MSG (BIT_MASK_SDIO_H2C_MSG << BIT_SHIFT_SDIO_H2C_MSG) #define BIT_CLEAR_SDIO_H2C_MSG(x) ((x) & (~BITS_SDIO_H2C_MSG)) #define BIT_GET_SDIO_H2C_MSG(x) \ (((x) >> BIT_SHIFT_SDIO_H2C_MSG) & BIT_MASK_SDIO_H2C_MSG) #define BIT_SET_SDIO_H2C_MSG(x, v) \ (BIT_CLEAR_SDIO_H2C_MSG(x) | BIT_SDIO_H2C_MSG(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_DATA_CPU_JTAG BIT(30) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_PAPE_WLBT_SEL BIT(29) #define BIT_LNAON_WLBT_SEL BIT(28) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_BDEN BIT(28) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_BT_BQB_GPIO_SEL BIT(27) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_BTGP_GPG3_FEN BIT(26) #define BIT_BTGP_GPG2_FEN BIT(25) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_BTGP_JTAG_EN BIT(24) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_BB2PP_ISO BIT(24) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_XTAL_CLK_EXTARNAL_EN BIT(23) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_BTBRI_UART_EN BIT(22) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_BTGP_UART0_EN BIT(22) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_BTGP_UART1_EN BIT(21) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_BTCOEX_PU BIT(21) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_BTGP_SPI_EN BIT(20) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_EEPROM_SEL_PD BIT(20) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_BTGP_GPIO_E2 BIT(19) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_TST_MOD_PD BIT(19) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_BTGP_GPIO_EN BIT(18) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_BOOT_FLUSH_PD BIT(18) #define BIT_USB_XTAL_SEL1_PD BIT(17) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_SHIFT_BTGP_GPIO_SL 16 #define BIT_MASK_BTGP_GPIO_SL 0x3 #define BIT_BTGP_GPIO_SL(x) \ (((x) & BIT_MASK_BTGP_GPIO_SL) << BIT_SHIFT_BTGP_GPIO_SL) #define BITS_BTGP_GPIO_SL (BIT_MASK_BTGP_GPIO_SL << BIT_SHIFT_BTGP_GPIO_SL) #define BIT_CLEAR_BTGP_GPIO_SL(x) ((x) & (~BITS_BTGP_GPIO_SL)) #define BIT_GET_BTGP_GPIO_SL(x) \ (((x) >> BIT_SHIFT_BTGP_GPIO_SL) & BIT_MASK_BTGP_GPIO_SL) #define BIT_SET_BTGP_GPIO_SL(x, v) \ (BIT_CLEAR_BTGP_GPIO_SL(x) | BIT_BTGP_GPIO_SL(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_USB_XTAL_SEL0_PD BIT(16) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_HST_WKE_DEV_SL BIT(15) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_BTSUSB_PL BIT(15) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_WL_JTAG BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_PAD_SDIO_SR BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_GPIO14_OUTPUT_PL BIT(13) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_SW_DEVWHOST_POLARITY BIT(13) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_GPIO15_OUTPUT_PL BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_HOST_WAKE_PAD_PULL_EN BIT(12) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_HOST_WAKE_DEV_PLL_EN BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_HOST_WAKE_PAD_SL BIT(11) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_HOST_WAKE_DEV_POLARITY BIT(11) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_PAD_TRSW_SR BIT(10) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_PAD_LNAON_SR BIT(10) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_PAD_TRSW_E2 BIT(9) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_PAD_LNAON_E2 BIT(9) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_A_ANTSEL_SR BIT(9) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_SW_TRSW_P_SEL_DATA BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_SW_LNAON_G_SEL_DATA BIT(8) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_A_ANTSEL_E2 BIT(8) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_SW_TRSW_N_SEL_DATA BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_SW_LNAON_A_SEL_DATA BIT(7) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_D_PAPE_2G_SR BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_PAD_PAPE_SR BIT(6) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_D_PAPE_5G_SR BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_PAD_PAPE_E2 BIT(5) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_D_TRSW_SR BIT(5) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_SW_PAPE_1_SEL_DATA BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_SW_PAPE_G_SEL_DATA BIT(4) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_D_TRSWB_SR BIT(4) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_SW_PAPE_0_SEL_DATA BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_SW_PAPE_A_SEL_DATA BIT(3) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_D_PAPE_2G_E2 BIT(3) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_SW_ANTSEL_2_SEL_DATA BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_PAD_DPDT_SR BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_D_PAPE_5G_E2 BIT(2) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_SW_ANTSEL_N_SEL_DATA BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_PAD_DPDT_PAD_E2 BIT(1) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_D_TRSW_E2 BIT(1) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_PAD_DPDT_E2 BIT(1) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_SW_ANTSEL_P_SEL_DATA BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_SW_DPDT_SEL_DATA BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ #define BIT_D_TRSWB_E2 BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_C2H (Offset 0x10250064) */ #define BIT_SHIFT_SDIO_C2H_MSG 0 #define BIT_MASK_SDIO_C2H_MSG 0xffffffffL #define BIT_SDIO_C2H_MSG(x) \ (((x) & BIT_MASK_SDIO_C2H_MSG) << BIT_SHIFT_SDIO_C2H_MSG) #define BITS_SDIO_C2H_MSG (BIT_MASK_SDIO_C2H_MSG << BIT_SHIFT_SDIO_C2H_MSG) #define BIT_CLEAR_SDIO_C2H_MSG(x) ((x) & (~BITS_SDIO_C2H_MSG)) #define BIT_GET_SDIO_C2H_MSG(x) \ (((x) >> BIT_SHIFT_SDIO_C2H_MSG) & BIT_MASK_SDIO_C2H_MSG) #define BIT_SET_SDIO_C2H_MSG(x, v) \ (BIT_CLEAR_SDIO_C2H_MSG(x) | BIT_SDIO_C2H_MSG(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_ISO_BD2PP BIT(31) #define BIT_LDOV12B_EN BIT(30) #define BIT_CKEN_BTGPS BIT(29) #define BIT_FEN_BTGPS BIT(28) #define BIT_BTCPU_BOOTSEL BIT(27) #define BIT_SPI_SPEEDUP BIT(26) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_BT_SUS BIT(25) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_BT_LDO_MODE BIT(25) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_DEVWAKE_PAD_TYPE_SEL BIT(24) #define BIT_CLKREQ_PAD_TYPE_SEL BIT(23) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_CKSL_BZSLP BIT(23) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_EN_CPL_TIMEOUT_PS BIT(22) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_BT_WAKE_HST_EN BIT(22) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_ISO_BTPON2PP BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_REG_TXDMA_FAIL_PS BIT(21) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_WAKE_BT_EN BIT(21) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_BTCOEX_CMD BIT(21) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_EN_BT BIT(20) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_BT_UART_INTF BIT(20) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_EN_HWENTR_L1 BIT(19) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_BT_SUSN_EN BIT(19) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_BT_HWROF_EN BIT(19) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_S3_RF_HW_EN BIT(19) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_EN_ADV_CLKGATE BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_BT_FUNC_EN BIT(18) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_S2_RF_HW_EN BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_BT_HWPDN_SL BIT(17) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_S1_RF_HW_EN BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_BT_DISN_EN BIT(16) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_S0_RF_HW_EN BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_BT_PDN_PULL_EN BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_WL_PDN_PULL_EN BIT(14) #define BIT_EXTERNAL_REQUEST_PL BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_GPIO0_2_3_PULL_LOW_EN BIT(12) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_ISO_BA2PP BIT(11) #define BIT_BT_AFE_LDO_EN BIT(10) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_PDN_PIN_SEL BIT(10) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_GPIO11_PULL_LOW_EN BIT(9) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_BT_AFE_PLL_EN BIT(9) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_GPIO4_PULL_LOW_EN BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_BT_DIG_CLK_EN BIT(8) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_BT_WAKE_HST_SL BIT(7) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_ASSERT_SPS_EN BIT(7) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_UART_BRIDGE BIT(7) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_WAKE_BT_SL BIT(6) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_MASK_CHIPEN BIT(6) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_OSC32K_CTRL_SEL BIT(6) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_WLAN_32K_SEL BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_WL_DRV_EXIST_IDX BIT(5) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_ASSERT_RF_EN BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_DOP_EHPAD BIT(4) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_BIT_DOP_EHPAD BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_WL_HWROF_EN BIT(3) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_SDIO_PAD_SHUTDOWNB BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_WL_FUNC_EN BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_SDIO_CLK_SMT BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ #define BIT_WL_HWPDN_SL BIT(1) #define BIT_WL_HWPDN_EN BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SDM_DEBUG (Offset 0x006C) */ #define BIT_SHIFT_F0N 23 #define BIT_MASK_F0N 0x7 #define BIT_F0N(x) (((x) & BIT_MASK_F0N) << BIT_SHIFT_F0N) #define BITS_F0N (BIT_MASK_F0N << BIT_SHIFT_F0N) #define BIT_CLEAR_F0N(x) ((x) & (~BITS_F0N)) #define BIT_GET_F0N(x) (((x) >> BIT_SHIFT_F0N) & BIT_MASK_F0N) #define BIT_SET_F0N(x, v) (BIT_CLEAR_F0N(x) | BIT_F0N(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SDM_DEBUG (Offset 0x006C) */ #define BIT_BT_WAKE_DEV_EN_V1 BIT(19) #define BIT_BT_WAKE_HST_EN_V1 BIT(18) #define BIT_BT_WAKE_HST_PL_V1 BIT(17) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GSSR (Offset 0x006C) */ #define BIT_SHIFT_GPIO_15_TO_0_VAL 16 #define BIT_MASK_GPIO_15_TO_0_VAL 0xffff #define BIT_GPIO_15_TO_0_VAL(x) \ (((x) & BIT_MASK_GPIO_15_TO_0_VAL) << BIT_SHIFT_GPIO_15_TO_0_VAL) #define BITS_GPIO_15_TO_0_VAL \ (BIT_MASK_GPIO_15_TO_0_VAL << BIT_SHIFT_GPIO_15_TO_0_VAL) #define BIT_CLEAR_GPIO_15_TO_0_VAL(x) ((x) & (~BITS_GPIO_15_TO_0_VAL)) #define BIT_GET_GPIO_15_TO_0_VAL(x) \ (((x) >> BIT_SHIFT_GPIO_15_TO_0_VAL) & BIT_MASK_GPIO_15_TO_0_VAL) #define BIT_SET_GPIO_15_TO_0_VAL(x, v) \ (BIT_CLEAR_GPIO_15_TO_0_VAL(x) | BIT_GPIO_15_TO_0_VAL(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SDM_DEBUG (Offset 0x006C) */ #define BIT_BT_CLKREQ_EN_V1 BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SDM_DEBUG (Offset 0x006C) */ #define BIT_SHIFT_F0F 10 #define BIT_MASK_F0F 0x1fff #define BIT_F0F(x) (((x) & BIT_MASK_F0F) << BIT_SHIFT_F0F) #define BITS_F0F (BIT_MASK_F0F << BIT_SHIFT_F0F) #define BIT_CLEAR_F0F(x) ((x) & (~BITS_F0F)) #define BIT_GET_F0F(x) (((x) >> BIT_SHIFT_F0F) & BIT_MASK_F0F) #define BIT_SET_F0F(x, v) (BIT_CLEAR_F0F(x) | BIT_F0F(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDM_DEBUG (Offset 0x006C) */ #define BIT_GPIO_IE_V18 BIT(10) #define BIT_PCIE_IE_V18 BIT(9) #define BIT_UART_IE_V18 BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SDM_DEBUG (Offset 0x006C) */ #define BIT_SHIFT_DIVN 4 #define BIT_MASK_DIVN 0x3f #define BIT_DIVN(x) (((x) & BIT_MASK_DIVN) << BIT_SHIFT_DIVN) #define BITS_DIVN (BIT_MASK_DIVN << BIT_SHIFT_DIVN) #define BIT_CLEAR_DIVN(x) ((x) & (~BITS_DIVN)) #define BIT_GET_DIVN(x) (((x) >> BIT_SHIFT_DIVN) & BIT_MASK_DIVN) #define BIT_SET_DIVN(x, v) (BIT_CLEAR_DIVN(x) | BIT_DIVN(v)) #define BIT_SHIFT_BB_DBG_SEL_AFE_SDM 0 #define BIT_MASK_BB_DBG_SEL_AFE_SDM 0xf #define BIT_BB_DBG_SEL_AFE_SDM(x) \ (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM) #define BITS_BB_DBG_SEL_AFE_SDM \ (BIT_MASK_BB_DBG_SEL_AFE_SDM << BIT_SHIFT_BB_DBG_SEL_AFE_SDM) #define BIT_CLEAR_BB_DBG_SEL_AFE_SDM(x) ((x) & (~BITS_BB_DBG_SEL_AFE_SDM)) #define BIT_GET_BB_DBG_SEL_AFE_SDM(x) \ (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM) & BIT_MASK_BB_DBG_SEL_AFE_SDM) #define BIT_SET_BB_DBG_SEL_AFE_SDM(x, v) \ (BIT_CLEAR_BB_DBG_SEL_AFE_SDM(x) | BIT_BB_DBG_SEL_AFE_SDM(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDM_DEBUG (Offset 0x006C) */ #define BIT_SHIFT_WLCLK_PHASE 0 #define BIT_MASK_WLCLK_PHASE 0x1f #define BIT_WLCLK_PHASE(x) \ (((x) & BIT_MASK_WLCLK_PHASE) << BIT_SHIFT_WLCLK_PHASE) #define BITS_WLCLK_PHASE (BIT_MASK_WLCLK_PHASE << BIT_SHIFT_WLCLK_PHASE) #define BIT_CLEAR_WLCLK_PHASE(x) ((x) & (~BITS_WLCLK_PHASE)) #define BIT_GET_WLCLK_PHASE(x) \ (((x) >> BIT_SHIFT_WLCLK_PHASE) & BIT_MASK_WLCLK_PHASE) #define BIT_SET_WLCLK_PHASE(x, v) \ (BIT_CLEAR_WLCLK_PHASE(x) | BIT_WLCLK_PHASE(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GSSR (Offset 0x006C) */ #define BIT_SHIFT_GPIO_15_TO_0_EN 0 #define BIT_MASK_GPIO_15_TO_0_EN 0xffff #define BIT_GPIO_15_TO_0_EN(x) \ (((x) & BIT_MASK_GPIO_15_TO_0_EN) << BIT_SHIFT_GPIO_15_TO_0_EN) #define BITS_GPIO_15_TO_0_EN \ (BIT_MASK_GPIO_15_TO_0_EN << BIT_SHIFT_GPIO_15_TO_0_EN) #define BIT_CLEAR_GPIO_15_TO_0_EN(x) ((x) & (~BITS_GPIO_15_TO_0_EN)) #define BIT_GET_GPIO_15_TO_0_EN(x) \ (((x) >> BIT_SHIFT_GPIO_15_TO_0_EN) & BIT_MASK_GPIO_15_TO_0_EN) #define BIT_SET_GPIO_15_TO_0_EN(x, v) \ (BIT_CLEAR_GPIO_15_TO_0_EN(x) | BIT_GPIO_15_TO_0_EN(v)) /* 2 REG_SYS_CLKR (Offset 0x0070) */ #define BIT_BBRSTB_STANDBY_V1 BIT(28) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_DBG_GNT_WL_BT BIT(27) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ #define BIT_AFE_PORT3_ISO BIT(27) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_LTE_MUX_CTRL_PATH BIT(26) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ #define BIT_AFE_PORT2_ISO BIT(26) #define BIT_AFE_PORT1_ISO BIT(25) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_LTE_COEX_UART BIT(25) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ #define BIT_AFE_PORT0_ISO BIT(24) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_3W_LTE_WL_GPIO BIT(24) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ #define BIT_USB_PWR_OFF_SEL BIT(23) #define BIT_USB_HOST_PWR_OFF_EN_V1 BIT(22) #define BIT_SYM_LPS_BLOCK_EN_V1 BIT(21) #define BIT_USB_LPM_ACT_EN_V1 BIT(20) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_SDIO_INT_POLARITY BIT(19) #define BIT_SDIO_INT BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_SDIO_OFF_EN BIT(17) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ #define BIT_SDIO_OFF_EN_V1 BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_SDIO_ON_EN BIT(16) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ #define BIT_SDIO_ON_EN_V1 BIT(16) #define BIT_DIS_U3MB_INU2 BIT(13) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_PCIE_FORCE_PWR_NGAT BIT(13) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ #define BIT_USB3_MDIO_EN BIT(12) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_PCIE_CALIB_EN_V1 BIT(12) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ #define BIT_USB3_BG_EN BIT(11) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_PAGE3_AUXCLK_GATE BIT(11) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ #define BIT_USB3_MB_EN BIT(10) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_PCIE_WAIT_TIMEOUT_EVENT BIT(10) #define BIT_PCIE_WAIT_TIME BIT(9) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ #define BIT_SHIFT_USB3_CK_MD 8 #define BIT_MASK_USB3_CK_MD 0x3 #define BIT_USB3_CK_MD(x) (((x) & BIT_MASK_USB3_CK_MD) << BIT_SHIFT_USB3_CK_MD) #define BITS_USB3_CK_MD (BIT_MASK_USB3_CK_MD << BIT_SHIFT_USB3_CK_MD) #define BIT_CLEAR_USB3_CK_MD(x) ((x) & (~BITS_USB3_CK_MD)) #define BIT_GET_USB3_CK_MD(x) \ (((x) >> BIT_SHIFT_USB3_CK_MD) & BIT_MASK_USB3_CK_MD) #define BIT_SET_USB3_CK_MD(x, v) (BIT_CLEAR_USB3_CK_MD(x) | BIT_USB3_CK_MD(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_MPCIE_REFCLK_XTAL_SEL BIT(8) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ #define BIT_USB3_CKBUF BIT(7) #define BIT_USB3_IBX_EN BIT(6) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_BT_CLKREQ_EN BIT(6) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ #define BIT_U3_MB_MASK BIT(5) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_BT_CTRL_USB_PWR_BACKDOOR BIT(5) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ #define BIT_U3_BG_MASK BIT(4) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_SHIFT_USB_CKREF_CML_R 4 #define BIT_MASK_USB_CKREF_CML_R 0x3 #define BIT_USB_CKREF_CML_R(x) \ (((x) & BIT_MASK_USB_CKREF_CML_R) << BIT_SHIFT_USB_CKREF_CML_R) #define BITS_USB_CKREF_CML_R \ (BIT_MASK_USB_CKREF_CML_R << BIT_SHIFT_USB_CKREF_CML_R) #define BIT_CLEAR_USB_CKREF_CML_R(x) ((x) & (~BITS_USB_CKREF_CML_R)) #define BIT_GET_USB_CKREF_CML_R(x) \ (((x) >> BIT_SHIFT_USB_CKREF_CML_R) & BIT_MASK_USB_CKREF_CML_R) #define BIT_SET_USB_CKREF_CML_R(x, v) \ (BIT_CLEAR_USB_CKREF_CML_R(x) | BIT_USB_CKREF_CML_R(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_USB_D_STATE_HOLD BIT(4) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ #define BIT_DIS_USB3_MB_POLLING BIT(3) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_REG_FORCE_DP BIT(3) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ #define BIT_PDN_MASK BIT(2) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_SHIFT_USB_CKREF_D2S_I 2 #define BIT_MASK_USB_CKREF_D2S_I 0x3 #define BIT_USB_CKREF_D2S_I(x) \ (((x) & BIT_MASK_USB_CKREF_D2S_I) << BIT_SHIFT_USB_CKREF_D2S_I) #define BITS_USB_CKREF_D2S_I \ (BIT_MASK_USB_CKREF_D2S_I << BIT_SHIFT_USB_CKREF_D2S_I) #define BIT_CLEAR_USB_CKREF_D2S_I(x) ((x) & (~BITS_USB_CKREF_D2S_I)) #define BIT_GET_USB_CKREF_D2S_I(x) \ (((x) >> BIT_SHIFT_USB_CKREF_D2S_I) & BIT_MASK_USB_CKREF_D2S_I) #define BIT_SET_USB_CKREF_D2S_I(x, v) \ (BIT_CLEAR_USB_CKREF_D2S_I(x) | BIT_USB_CKREF_D2S_I(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_REG_DP_MODE BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ #define BIT_NO_PDN_CHIPOFF BIT(1) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_RES_USB_MASS_STORAGE_DESC BIT(1) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ #define BIT_PDN_HCOUNT BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_USB_WAIT_TIME BIT(0) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ #define BIT_SHIFT_SI_AUTHORIZATION 0 #define BIT_MASK_SI_AUTHORIZATION 0xff #define BIT_SI_AUTHORIZATION(x) \ (((x) & BIT_MASK_SI_AUTHORIZATION) << BIT_SHIFT_SI_AUTHORIZATION) #define BITS_SI_AUTHORIZATION \ (BIT_MASK_SI_AUTHORIZATION << BIT_SHIFT_SI_AUTHORIZATION) #define BIT_CLEAR_SI_AUTHORIZATION(x) ((x) & (~BITS_SI_AUTHORIZATION)) #define BIT_GET_SI_AUTHORIZATION(x) \ (((x) >> BIT_SHIFT_SI_AUTHORIZATION) & BIT_MASK_SI_AUTHORIZATION) #define BIT_SET_SI_AUTHORIZATION(x, v) \ (BIT_CLEAR_SI_AUTHORIZATION(x) | BIT_SI_AUTHORIZATION(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_SHIFT_TSFT_SEL 29 #define BIT_MASK_TSFT_SEL 0x7 #define BIT_TSFT_SEL(x) (((x) & BIT_MASK_TSFT_SEL) << BIT_SHIFT_TSFT_SEL) #define BITS_TSFT_SEL (BIT_MASK_TSFT_SEL << BIT_SHIFT_TSFT_SEL) #define BIT_CLEAR_TSFT_SEL(x) ((x) & (~BITS_TSFT_SEL)) #define BIT_GET_TSFT_SEL(x) (((x) >> BIT_SHIFT_TSFT_SEL) & BIT_MASK_TSFT_SEL) #define BIT_SET_TSFT_SEL(x, v) (BIT_CLEAR_TSFT_SEL(x) | BIT_TSFT_SEL(v)) #endif #if (HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_SHIFT_XTAL_SEL_0_V1 28 #define BIT_MASK_XTAL_SEL_0_V1 0xf #define BIT_XTAL_SEL_0_V1(x) \ (((x) & BIT_MASK_XTAL_SEL_0_V1) << BIT_SHIFT_XTAL_SEL_0_V1) #define BITS_XTAL_SEL_0_V1 (BIT_MASK_XTAL_SEL_0_V1 << BIT_SHIFT_XTAL_SEL_0_V1) #define BIT_CLEAR_XTAL_SEL_0_V1(x) ((x) & (~BITS_XTAL_SEL_0_V1)) #define BIT_GET_XTAL_SEL_0_V1(x) \ (((x) >> BIT_SHIFT_XTAL_SEL_0_V1) & BIT_MASK_XTAL_SEL_0_V1) #define BIT_SET_XTAL_SEL_0_V1(x, v) \ (BIT_CLEAR_XTAL_SEL_0_V1(x) | BIT_XTAL_SEL_0_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_TSFT_BAND_SEL BIT(28) #endif #if (HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_ISO_RFC2RF_3 BIT(27) #define BIT_ISO_RFC2RF_2 BIT(26) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_SHIFT_RPWM 24 #define BIT_MASK_RPWM 0xff #define BIT_RPWM(x) (((x) & BIT_MASK_RPWM) << BIT_SHIFT_RPWM) #define BITS_RPWM (BIT_MASK_RPWM << BIT_SHIFT_RPWM) #define BIT_CLEAR_RPWM(x) ((x) & (~BITS_RPWM)) #define BIT_GET_RPWM(x) (((x) >> BIT_SHIFT_RPWM) & BIT_MASK_RPWM) #define BIT_SET_RPWM(x, v) (BIT_CLEAR_RPWM(x) | BIT_RPWM(v)) #define BIT_ROM_DLEN BIT(19) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_SDIO_PAD_E5 BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_SHIFT_ROM_PGE 16 #define BIT_MASK_ROM_PGE 0x7 #define BIT_ROM_PGE(x) (((x) & BIT_MASK_ROM_PGE) << BIT_SHIFT_ROM_PGE) #define BITS_ROM_PGE (BIT_MASK_ROM_PGE << BIT_SHIFT_ROM_PGE) #define BIT_CLEAR_ROM_PGE(x) ((x) & (~BITS_ROM_PGE)) #define BIT_GET_ROM_PGE(x) (((x) >> BIT_SHIFT_ROM_PGE) & BIT_MASK_ROM_PGE) #define BIT_SET_ROM_PGE(x, v) (BIT_CLEAR_ROM_PGE(x) | BIT_ROM_PGE(v)) #endif #if (HALMAC_8814A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_R_FORCE_CLK_U3 BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_USB_HOST_PWR_OFF_EN BIT(12) #endif #if (HALMAC_8814A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_R_USB2_AUTOLOAD BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_SYM_LPS_BLOCK_EN BIT(11) #endif #if (HALMAC_8814A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_FORCE_U2CK BIT(11) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_USB_LPM_ACT_EN BIT(10) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_FORCE_CLK BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_USB_LPM_NY BIT(9) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_U2_FORCE BIT(9) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_IBX_EN_VALUE BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_USB_SUS_DIS BIT(8) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_U3_FORCE BIT(8) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_IB_EN_VALUE BIT(8) #define BIT_EN_LW_PWR BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_SHIFT_SDIO_PAD_E 5 #define BIT_MASK_SDIO_PAD_E 0x7 #define BIT_SDIO_PAD_E(x) (((x) & BIT_MASK_SDIO_PAD_E) << BIT_SHIFT_SDIO_PAD_E) #define BITS_SDIO_PAD_E (BIT_MASK_SDIO_PAD_E << BIT_SHIFT_SDIO_PAD_E) #define BIT_CLEAR_SDIO_PAD_E(x) ((x) & (~BITS_SDIO_PAD_E)) #define BIT_GET_SDIO_PAD_E(x) \ (((x) >> BIT_SHIFT_SDIO_PAD_E) & BIT_MASK_SDIO_PAD_E) #define BIT_SET_SDIO_PAD_E(x, v) (BIT_CLEAR_SDIO_PAD_E(x) | BIT_SDIO_PAD_E(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_EN_REGU BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_USB_LPPLL_EN BIT(4) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_SDIO_H3L1 BIT(4) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_FORCED_IB_EN BIT(4) #define BIT_EN_PC BIT(4) #define BIT_USB1_1_USB2_0_DECISION BIT(3) #define BIT_EN_REGBG BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_ROP_SW15 BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_SHIFT_USB23_SW_MODE 2 #define BIT_MASK_USB23_SW_MODE 0x3 #define BIT_USB23_SW_MODE(x) \ (((x) & BIT_MASK_USB23_SW_MODE) << BIT_SHIFT_USB23_SW_MODE) #define BITS_USB23_SW_MODE (BIT_MASK_USB23_SW_MODE << BIT_SHIFT_USB23_SW_MODE) #define BIT_CLEAR_USB23_SW_MODE(x) ((x) & (~BITS_USB23_SW_MODE)) #define BIT_GET_USB23_SW_MODE(x) \ (((x) >> BIT_SHIFT_USB23_SW_MODE) & BIT_MASK_USB23_SW_MODE) #define BIT_SET_USB23_SW_MODE(x, v) \ (BIT_CLEAR_USB23_SW_MODE(x) | BIT_USB23_SW_MODE(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_REG_BG_LPF BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_PCI_CKRDY_OPT BIT(1) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_PCLK_VLD_SEL BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_PCI_VAUX_EN BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_VAUX_EN BIT(0) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ #define BIT_SHIFT_REG_BG 0 #define BIT_MASK_REG_BG 0x3 #define BIT_REG_BG(x) (((x) & BIT_MASK_REG_BG) << BIT_SHIFT_REG_BG) #define BITS_REG_BG (BIT_MASK_REG_BG << BIT_SHIFT_REG_BG) #define BIT_CLEAR_REG_BG(x) ((x) & (~BITS_REG_BG)) #define BIT_GET_REG_BG(x) (((x) >> BIT_SHIFT_REG_BG) & BIT_MASK_REG_BG) #define BIT_SET_REG_BG(x, v) (BIT_CLEAR_REG_BG(x) | BIT_REG_BG(v)) #define BIT_SHIFT_REG_VADJ 0 #define BIT_MASK_REG_VADJ 0xf #define BIT_REG_VADJ(x) (((x) & BIT_MASK_REG_VADJ) << BIT_SHIFT_REG_VADJ) #define BITS_REG_VADJ (BIT_MASK_REG_VADJ << BIT_SHIFT_REG_VADJ) #define BIT_CLEAR_REG_VADJ(x) ((x) & (~BITS_REG_VADJ)) #define BIT_GET_REG_VADJ(x) (((x) >> BIT_SHIFT_REG_VADJ) & BIT_MASK_REG_VADJ) #define BIT_SET_REG_VADJ(x, v) (BIT_CLEAR_REG_VADJ(x) | BIT_REG_VADJ(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ #define BIT_SDM_ORDER BIT(30) #define BIT_XTAL_DRV_RF_LATCH_V1 BIT(29) #define BIT_XTAL_VDD_SEL_V1 BIT(28) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_XTAL_DRV_RF_LATCH BIT(27) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ #define BIT_XQSEL_RF_AWAKE_V1 BIT(27) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_XTAL_VDD_SEL BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_RF1_SDMRSTB BIT(26) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ #define BIT_GATED_XTAL_OK0_V1 BIT(26) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_XQSEL_RF BIT(25) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_RF1_RSTB BIT(25) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_XQSEL_RF_AWAKE BIT(25) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_XQSEL_RF_INITIAL BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_RF1_EN BIT(24) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_XQSEL_BIT1 BIT(24) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_REG_VREF_SEL BIT(23) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_DITHER_SDM_BIT3 BIT(23) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ #define BIT_SHIFT_F0N_2_TO_0 23 #define BIT_MASK_F0N_2_TO_0 0x7 #define BIT_F0N_2_TO_0(x) (((x) & BIT_MASK_F0N_2_TO_0) << BIT_SHIFT_F0N_2_TO_0) #define BITS_F0N_2_TO_0 (BIT_MASK_F0N_2_TO_0 << BIT_SHIFT_F0N_2_TO_0) #define BIT_CLEAR_F0N_2_TO_0(x) ((x) & (~BITS_F0N_2_TO_0)) #define BIT_GET_F0N_2_TO_0(x) \ (((x) >> BIT_SHIFT_F0N_2_TO_0) & BIT_MASK_F0N_2_TO_0) #define BIT_SET_F0N_2_TO_0(x, v) (BIT_CLEAR_F0N_2_TO_0(x) | BIT_F0N_2_TO_0(v)) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_REG_LPFEN BIT(22) #define BIT_REG_KVCO BIT(21) #define BIT_XTAL_DRV_AGPIO_BIT1 BIT(20) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_SHIFT_XTAL_LDO 20 #define BIT_MASK_XTAL_LDO 0x7 #define BIT_XTAL_LDO(x) (((x) & BIT_MASK_XTAL_LDO) << BIT_SHIFT_XTAL_LDO) #define BITS_XTAL_LDO (BIT_MASK_XTAL_LDO << BIT_SHIFT_XTAL_LDO) #define BIT_CLEAR_XTAL_LDO(x) ((x) & (~BITS_XTAL_LDO)) #define BIT_GET_XTAL_LDO(x) (((x) >> BIT_SHIFT_XTAL_LDO) & BIT_MASK_XTAL_LDO) #define BIT_SET_XTAL_LDO(x, v) (BIT_CLEAR_XTAL_LDO(x) | BIT_XTAL_LDO(v)) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_XTAL_DRV_AGPIO_BIT0 BIT(19) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_XTAL_GRF2 BIT(18) #define BIT_REG_REF_SEL BIT(17) #define BIT_REG_320_SEL BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_ADC_CK_SYNC_EN BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_EN_SYM BIT(15) #define BIT_SHIFT_IOFFSET 10 #define BIT_MASK_IOFFSET 0x1f #define BIT_IOFFSET(x) (((x) & BIT_MASK_IOFFSET) << BIT_SHIFT_IOFFSET) #define BITS_IOFFSET (BIT_MASK_IOFFSET << BIT_SHIFT_IOFFSET) #define BIT_CLEAR_IOFFSET(x) ((x) & (~BITS_IOFFSET)) #define BIT_GET_IOFFSET(x) (((x) >> BIT_SHIFT_IOFFSET) & BIT_MASK_IOFFSET) #define BIT_SET_IOFFSET(x, v) (BIT_CLEAR_IOFFSET(x) | BIT_IOFFSET(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_RF2_SDMRSTB BIT(10) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ #define BIT_SHIFT_F0F_12_TO_0 10 #define BIT_MASK_F0F_12_TO_0 0x1fff #define BIT_F0F_12_TO_0(x) \ (((x) & BIT_MASK_F0F_12_TO_0) << BIT_SHIFT_F0F_12_TO_0) #define BITS_F0F_12_TO_0 (BIT_MASK_F0F_12_TO_0 << BIT_SHIFT_F0F_12_TO_0) #define BIT_CLEAR_F0F_12_TO_0(x) ((x) & (~BITS_F0F_12_TO_0)) #define BIT_GET_F0F_12_TO_0(x) \ (((x) >> BIT_SHIFT_F0F_12_TO_0) & BIT_MASK_F0F_12_TO_0) #define BIT_SET_F0F_12_TO_0(x, v) \ (BIT_CLEAR_F0F_12_TO_0(x) | BIT_F0F_12_TO_0(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_RF2_RSTB BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1 8 #define BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1 0x3 #define BIT_APLL_FREF_SEL_BIT_2_TO_1(x) \ (((x) & BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1) \ << BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1) #define BITS_APLL_FREF_SEL_BIT_2_TO_1 \ (BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1 \ << BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1) #define BIT_CLEAR_APLL_FREF_SEL_BIT_2_TO_1(x) \ ((x) & (~BITS_APLL_FREF_SEL_BIT_2_TO_1)) #define BIT_GET_APLL_FREF_SEL_BIT_2_TO_1(x) \ (((x) >> BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1) & \ BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1) #define BIT_SET_APLL_FREF_SEL_BIT_2_TO_1(x, v) \ (BIT_CLEAR_APLL_FREF_SEL_BIT_2_TO_1(x) | \ BIT_APLL_FREF_SEL_BIT_2_TO_1(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_RF2_EN BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_APLL_FREF_SEL_BIT3 BIT(7) #define BIT_SHIFT_APLL_LDO_V12ADJ 5 #define BIT_MASK_APLL_LDO_V12ADJ 0x3 #define BIT_APLL_LDO_V12ADJ(x) \ (((x) & BIT_MASK_APLL_LDO_V12ADJ) << BIT_SHIFT_APLL_LDO_V12ADJ) #define BITS_APLL_LDO_V12ADJ \ (BIT_MASK_APLL_LDO_V12ADJ << BIT_SHIFT_APLL_LDO_V12ADJ) #define BIT_CLEAR_APLL_LDO_V12ADJ(x) ((x) & (~BITS_APLL_LDO_V12ADJ)) #define BIT_GET_APLL_LDO_V12ADJ(x) \ (((x) >> BIT_SHIFT_APLL_LDO_V12ADJ) & BIT_MASK_APLL_LDO_V12ADJ) #define BIT_SET_APLL_LDO_V12ADJ(x, v) \ (BIT_CLEAR_APLL_LDO_V12ADJ(x) | BIT_APLL_LDO_V12ADJ(v)) #define BIT_APLL_160_GATEB BIT(4) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ #define BIT_SHIFT_DIVN_5_TO_0 4 #define BIT_MASK_DIVN_5_TO_0 0x3f #define BIT_DIVN_5_TO_0(x) \ (((x) & BIT_MASK_DIVN_5_TO_0) << BIT_SHIFT_DIVN_5_TO_0) #define BITS_DIVN_5_TO_0 (BIT_MASK_DIVN_5_TO_0 << BIT_SHIFT_DIVN_5_TO_0) #define BIT_CLEAR_DIVN_5_TO_0(x) ((x) & (~BITS_DIVN_5_TO_0)) #define BIT_GET_DIVN_5_TO_0(x) \ (((x) >> BIT_SHIFT_DIVN_5_TO_0) & BIT_MASK_DIVN_5_TO_0) #define BIT_SET_DIVN_5_TO_0(x, v) \ (BIT_CLEAR_DIVN_5_TO_0(x) | BIT_DIVN_5_TO_0(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_AFE_DUMMY BIT(3) #define BIT_REG_IDOUBLE BIT(2) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_RF3_SDMRSTB BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_REG_VCO_BIAS_BIT0 BIT(1) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_RF3_RSTB BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_REG_VCO_BIAS_BIT1 BIT(0) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ #define BIT_RF3_EN BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ #define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0 0 #define BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0 0xf #define BIT_BB_DBG_SEL_AFE_SDM_3_TO_0(x) \ (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0) \ << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0) #define BITS_BB_DBG_SEL_AFE_SDM_3_TO_0 \ (BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0 \ << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0) #define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_3_TO_0(x) \ ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_3_TO_0)) #define BIT_GET_BB_DBG_SEL_AFE_SDM_3_TO_0(x) \ (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0) & \ BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0) #define BIT_SET_BB_DBG_SEL_AFE_SDM_3_TO_0(x, v) \ (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_3_TO_0(x) | \ BIT_BB_DBG_SEL_AFE_SDM_3_TO_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_EXT_SWR_CTRL_EN BIT(31) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_REF_FREF_EDGE BIT(29) #define BIT_REG_VREF_SEL_V1 BIT(28) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_ZCD_HW_AUTO_EN BIT(27) #define BIT_ZCD_REGSEL BIT(26) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_SHIFT_REG_CP_OFFSET_4_TO_0 23 #define BIT_MASK_REG_CP_OFFSET_4_TO_0 0x1f #define BIT_REG_CP_OFFSET_4_TO_0(x) \ (((x) & BIT_MASK_REG_CP_OFFSET_4_TO_0) \ << BIT_SHIFT_REG_CP_OFFSET_4_TO_0) #define BITS_REG_CP_OFFSET_4_TO_0 \ (BIT_MASK_REG_CP_OFFSET_4_TO_0 << BIT_SHIFT_REG_CP_OFFSET_4_TO_0) #define BIT_CLEAR_REG_CP_OFFSET_4_TO_0(x) ((x) & (~BITS_REG_CP_OFFSET_4_TO_0)) #define BIT_GET_REG_CP_OFFSET_4_TO_0(x) \ (((x) >> BIT_SHIFT_REG_CP_OFFSET_4_TO_0) & \ BIT_MASK_REG_CP_OFFSET_4_TO_0) #define BIT_SET_REG_CP_OFFSET_4_TO_0(x, v) \ (BIT_CLEAR_REG_CP_OFFSET_4_TO_0(x) | BIT_REG_CP_OFFSET_4_TO_0(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_SHIFT_AUTO_ZCD_IN_CODE 21 #define BIT_MASK_AUTO_ZCD_IN_CODE 0x1f #define BIT_AUTO_ZCD_IN_CODE(x) \ (((x) & BIT_MASK_AUTO_ZCD_IN_CODE) << BIT_SHIFT_AUTO_ZCD_IN_CODE) #define BITS_AUTO_ZCD_IN_CODE \ (BIT_MASK_AUTO_ZCD_IN_CODE << BIT_SHIFT_AUTO_ZCD_IN_CODE) #define BIT_CLEAR_AUTO_ZCD_IN_CODE(x) ((x) & (~BITS_AUTO_ZCD_IN_CODE)) #define BIT_GET_AUTO_ZCD_IN_CODE(x) \ (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE) & BIT_MASK_AUTO_ZCD_IN_CODE) #define BIT_SET_AUTO_ZCD_IN_CODE(x, v) \ (BIT_CLEAR_AUTO_ZCD_IN_CODE(x) | BIT_AUTO_ZCD_IN_CODE(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_SHIFT_REG_RS_SET_2_TO_0 20 #define BIT_MASK_REG_RS_SET_2_TO_0 0x7 #define BIT_REG_RS_SET_2_TO_0(x) \ (((x) & BIT_MASK_REG_RS_SET_2_TO_0) << BIT_SHIFT_REG_RS_SET_2_TO_0) #define BITS_REG_RS_SET_2_TO_0 \ (BIT_MASK_REG_RS_SET_2_TO_0 << BIT_SHIFT_REG_RS_SET_2_TO_0) #define BIT_CLEAR_REG_RS_SET_2_TO_0(x) ((x) & (~BITS_REG_RS_SET_2_TO_0)) #define BIT_GET_REG_RS_SET_2_TO_0(x) \ (((x) >> BIT_SHIFT_REG_RS_SET_2_TO_0) & BIT_MASK_REG_RS_SET_2_TO_0) #define BIT_SET_REG_RS_SET_2_TO_0(x, v) \ (BIT_CLEAR_REG_RS_SET_2_TO_0(x) | BIT_REG_RS_SET_2_TO_0(v)) #define BIT_SHIFT_REG_CS_SET_1_TO_0 18 #define BIT_MASK_REG_CS_SET_1_TO_0 0x3 #define BIT_REG_CS_SET_1_TO_0(x) \ (((x) & BIT_MASK_REG_CS_SET_1_TO_0) << BIT_SHIFT_REG_CS_SET_1_TO_0) #define BITS_REG_CS_SET_1_TO_0 \ (BIT_MASK_REG_CS_SET_1_TO_0 << BIT_SHIFT_REG_CS_SET_1_TO_0) #define BIT_CLEAR_REG_CS_SET_1_TO_0(x) ((x) & (~BITS_REG_CS_SET_1_TO_0)) #define BIT_GET_REG_CS_SET_1_TO_0(x) \ (((x) >> BIT_SHIFT_REG_CS_SET_1_TO_0) & BIT_MASK_REG_CS_SET_1_TO_0) #define BIT_SET_REG_CS_SET_1_TO_0(x, v) \ (BIT_CLEAR_REG_CS_SET_1_TO_0(x) | BIT_REG_CS_SET_1_TO_0(v)) #define BIT_SHIFT_REG_CP_SET_1_TO_0 16 #define BIT_MASK_REG_CP_SET_1_TO_0 0x3 #define BIT_REG_CP_SET_1_TO_0(x) \ (((x) & BIT_MASK_REG_CP_SET_1_TO_0) << BIT_SHIFT_REG_CP_SET_1_TO_0) #define BITS_REG_CP_SET_1_TO_0 \ (BIT_MASK_REG_CP_SET_1_TO_0 << BIT_SHIFT_REG_CP_SET_1_TO_0) #define BIT_CLEAR_REG_CP_SET_1_TO_0(x) ((x) & (~BITS_REG_CP_SET_1_TO_0)) #define BIT_GET_REG_CP_SET_1_TO_0(x) \ (((x) >> BIT_SHIFT_REG_CP_SET_1_TO_0) & BIT_MASK_REG_CP_SET_1_TO_0) #define BIT_SET_REG_CP_SET_1_TO_0(x, v) \ (BIT_CLEAR_REG_CP_SET_1_TO_0(x) | BIT_REG_CP_SET_1_TO_0(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_SHIFT_ZCD_CODE_IN_L 16 #define BIT_MASK_ZCD_CODE_IN_L 0x1f #define BIT_ZCD_CODE_IN_L(x) \ (((x) & BIT_MASK_ZCD_CODE_IN_L) << BIT_SHIFT_ZCD_CODE_IN_L) #define BITS_ZCD_CODE_IN_L (BIT_MASK_ZCD_CODE_IN_L << BIT_SHIFT_ZCD_CODE_IN_L) #define BIT_CLEAR_ZCD_CODE_IN_L(x) ((x) & (~BITS_ZCD_CODE_IN_L)) #define BIT_GET_ZCD_CODE_IN_L(x) \ (((x) >> BIT_SHIFT_ZCD_CODE_IN_L) & BIT_MASK_ZCD_CODE_IN_L) #define BIT_SET_ZCD_CODE_IN_L(x, v) \ (BIT_CLEAR_ZCD_CODE_IN_L(x) | BIT_ZCD_CODE_IN_L(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_LPFEN BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_SHIFT_LDO_HV5_DUMMY 14 #define BIT_MASK_LDO_HV5_DUMMY 0x3 #define BIT_LDO_HV5_DUMMY(x) \ (((x) & BIT_MASK_LDO_HV5_DUMMY) << BIT_SHIFT_LDO_HV5_DUMMY) #define BITS_LDO_HV5_DUMMY (BIT_MASK_LDO_HV5_DUMMY << BIT_SHIFT_LDO_HV5_DUMMY) #define BIT_CLEAR_LDO_HV5_DUMMY(x) ((x) & (~BITS_LDO_HV5_DUMMY)) #define BIT_GET_LDO_HV5_DUMMY(x) \ (((x) >> BIT_SHIFT_LDO_HV5_DUMMY) & BIT_MASK_LDO_HV5_DUMMY) #define BIT_SET_LDO_HV5_DUMMY(x, v) \ (BIT_CLEAR_LDO_HV5_DUMMY(x) | BIT_LDO_HV5_DUMMY(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_REG_DOGENB BIT(14) #define BIT_REG_TEST_EN BIT(13) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_SHIFT_REG_VTUNE33 12 #define BIT_MASK_REG_VTUNE33 0x3 #define BIT_REG_VTUNE33(x) \ (((x) & BIT_MASK_REG_VTUNE33) << BIT_SHIFT_REG_VTUNE33) #define BITS_REG_VTUNE33 (BIT_MASK_REG_VTUNE33 << BIT_SHIFT_REG_VTUNE33) #define BIT_CLEAR_REG_VTUNE33(x) ((x) & (~BITS_REG_VTUNE33)) #define BIT_GET_REG_VTUNE33(x) \ (((x) >> BIT_SHIFT_REG_VTUNE33) & BIT_MASK_REG_VTUNE33) #define BIT_SET_REG_VTUNE33(x, v) \ (BIT_CLEAR_REG_VTUNE33(x) | BIT_REG_VTUNE33(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1 12 #define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1 0x3 #define BIT_REG_VTUNE33_BIT0_TO_BIT1(x) \ (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) \ << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) #define BITS_REG_VTUNE33_BIT0_TO_BIT1 \ (BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1 \ << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) #define BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1(x) \ ((x) & (~BITS_REG_VTUNE33_BIT0_TO_BIT1)) #define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1(x) \ (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) & \ BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) #define BIT_SET_REG_VTUNE33_BIT0_TO_BIT1(x, v) \ (BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1(x) | \ BIT_REG_VTUNE33_BIT0_TO_BIT1(v)) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_SHIFT_REG_STANDBY33 10 #define BIT_MASK_REG_STANDBY33 0x3 #define BIT_REG_STANDBY33(x) \ (((x) & BIT_MASK_REG_STANDBY33) << BIT_SHIFT_REG_STANDBY33) #define BITS_REG_STANDBY33 (BIT_MASK_REG_STANDBY33 << BIT_SHIFT_REG_STANDBY33) #define BIT_CLEAR_REG_STANDBY33(x) ((x) & (~BITS_REG_STANDBY33)) #define BIT_GET_REG_STANDBY33(x) \ (((x) >> BIT_SHIFT_REG_STANDBY33) & BIT_MASK_REG_STANDBY33) #define BIT_SET_REG_STANDBY33(x, v) \ (BIT_CLEAR_REG_STANDBY33(x) | BIT_REG_STANDBY33(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1 10 #define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1 0x3 #define BIT_REG_STANDBY33_BIT0_TO_BIT1(x) \ (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) \ << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) #define BITS_REG_STANDBY33_BIT0_TO_BIT1 \ (BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1 \ << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) #define BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1(x) \ ((x) & (~BITS_REG_STANDBY33_BIT0_TO_BIT1)) #define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1(x) \ (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) & \ BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) #define BIT_SET_REG_STANDBY33_BIT0_TO_BIT1(x, v) \ (BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1(x) | \ BIT_REG_STANDBY33_BIT0_TO_BIT1(v)) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_SHIFT_REG_LOAD33 8 #define BIT_MASK_REG_LOAD33 0x3 #define BIT_REG_LOAD33(x) (((x) & BIT_MASK_REG_LOAD33) << BIT_SHIFT_REG_LOAD33) #define BITS_REG_LOAD33 (BIT_MASK_REG_LOAD33 << BIT_SHIFT_REG_LOAD33) #define BIT_CLEAR_REG_LOAD33(x) ((x) & (~BITS_REG_LOAD33)) #define BIT_GET_REG_LOAD33(x) \ (((x) >> BIT_SHIFT_REG_LOAD33) & BIT_MASK_REG_LOAD33) #define BIT_SET_REG_LOAD33(x, v) (BIT_CLEAR_REG_LOAD33(x) | BIT_REG_LOAD33(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_SHIFT_REG_DIV_SEL 8 #define BIT_MASK_REG_DIV_SEL 0x1f #define BIT_REG_DIV_SEL(x) \ (((x) & BIT_MASK_REG_DIV_SEL) << BIT_SHIFT_REG_DIV_SEL) #define BITS_REG_DIV_SEL (BIT_MASK_REG_DIV_SEL << BIT_SHIFT_REG_DIV_SEL) #define BIT_CLEAR_REG_DIV_SEL(x) ((x) & (~BITS_REG_DIV_SEL)) #define BIT_GET_REG_DIV_SEL(x) \ (((x) >> BIT_SHIFT_REG_DIV_SEL) & BIT_MASK_REG_DIV_SEL) #define BIT_SET_REG_DIV_SEL(x, v) \ (BIT_CLEAR_REG_DIV_SEL(x) | BIT_REG_DIV_SEL(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1 8 #define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 0x3 #define BIT_REG_LOAD33_BIT0_TO_BIT1(x) \ (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) \ << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) #define BITS_REG_LOAD33_BIT0_TO_BIT1 \ (BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) #define BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1(x) \ ((x) & (~BITS_REG_LOAD33_BIT0_TO_BIT1)) #define BIT_GET_REG_LOAD33_BIT0_TO_BIT1(x) \ (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) & \ BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) #define BIT_SET_REG_LOAD33_BIT0_TO_BIT1(x, v) \ (BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1(x) | BIT_REG_LOAD33_BIT0_TO_BIT1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_REG_BYPASS_L BIT(7) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_EN_CK200M BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_REG_LDOF_L BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_REG_OCPS_L BIT(5) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_SHIFT_REG_KVCO_200M_1_TO_0 5 #define BIT_MASK_REG_KVCO_200M_1_TO_0 0x3 #define BIT_REG_KVCO_200M_1_TO_0(x) \ (((x) & BIT_MASK_REG_KVCO_200M_1_TO_0) \ << BIT_SHIFT_REG_KVCO_200M_1_TO_0) #define BITS_REG_KVCO_200M_1_TO_0 \ (BIT_MASK_REG_KVCO_200M_1_TO_0 << BIT_SHIFT_REG_KVCO_200M_1_TO_0) #define BIT_CLEAR_REG_KVCO_200M_1_TO_0(x) ((x) & (~BITS_REG_KVCO_200M_1_TO_0)) #define BIT_GET_REG_KVCO_200M_1_TO_0(x) \ (((x) >> BIT_SHIFT_REG_KVCO_200M_1_TO_0) & \ BIT_MASK_REG_KVCO_200M_1_TO_0) #define BIT_SET_REG_KVCO_200M_1_TO_0(x, v) \ (BIT_CLEAR_REG_KVCO_200M_1_TO_0(x) | BIT_REG_KVCO_200M_1_TO_0(v)) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_REG_TYPE_L_V1 BIT(5) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_ARENB_L BIT(3) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0 2 #define BIT_MASK_REG_CP_BIAS_200M_2_TO_0 0x7 #define BIT_REG_CP_BIAS_200M_2_TO_0(x) \ (((x) & BIT_MASK_REG_CP_BIAS_200M_2_TO_0) \ << BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0) #define BITS_REG_CP_BIAS_200M_2_TO_0 \ (BIT_MASK_REG_CP_BIAS_200M_2_TO_0 << BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0) #define BIT_CLEAR_REG_CP_BIAS_200M_2_TO_0(x) \ ((x) & (~BITS_REG_CP_BIAS_200M_2_TO_0)) #define BIT_GET_REG_CP_BIAS_200M_2_TO_0(x) \ (((x) >> BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0) & \ BIT_MASK_REG_CP_BIAS_200M_2_TO_0) #define BIT_SET_REG_CP_BIAS_200M_2_TO_0(x, v) \ (BIT_CLEAR_REG_CP_BIAS_200M_2_TO_0(x) | BIT_REG_CP_BIAS_200M_2_TO_0(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_SHIFT_CFC_L_BIT_1_TO_0 1 #define BIT_MASK_CFC_L_BIT_1_TO_0 0x3 #define BIT_CFC_L_BIT_1_TO_0(x) \ (((x) & BIT_MASK_CFC_L_BIT_1_TO_0) << BIT_SHIFT_CFC_L_BIT_1_TO_0) #define BITS_CFC_L_BIT_1_TO_0 \ (BIT_MASK_CFC_L_BIT_1_TO_0 << BIT_SHIFT_CFC_L_BIT_1_TO_0) #define BIT_CLEAR_CFC_L_BIT_1_TO_0(x) ((x) & (~BITS_CFC_L_BIT_1_TO_0)) #define BIT_GET_CFC_L_BIT_1_TO_0(x) \ (((x) >> BIT_SHIFT_CFC_L_BIT_1_TO_0) & BIT_MASK_CFC_L_BIT_1_TO_0) #define BIT_SET_CFC_L_BIT_1_TO_0(x, v) \ (BIT_CLEAR_CFC_L_BIT_1_TO_0(x) | BIT_CFC_L_BIT_1_TO_0(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_SHIFT_CFC_L 1 #define BIT_MASK_CFC_L 0x3 #define BIT_CFC_L(x) (((x) & BIT_MASK_CFC_L) << BIT_SHIFT_CFC_L) #define BITS_CFC_L (BIT_MASK_CFC_L << BIT_SHIFT_CFC_L) #define BIT_CLEAR_CFC_L(x) ((x) & (~BITS_CFC_L)) #define BIT_GET_CFC_L(x) (((x) >> BIT_SHIFT_CFC_L) & BIT_MASK_CFC_L) #define BIT_SET_CFC_L(x, v) (BIT_CLEAR_CFC_L(x) | BIT_CFC_L(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_REG_TYPE_L BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_XCK_OUT_EN BIT(0) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ #define BIT_REG_OCPS_L_V1 BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_ANA_PORT_EN BIT(22) #define BIT_MAC_PORT_EN BIT(21) #define BIT_BOOT_FSPI_EN BIT(20) #define BIT_FW_INIT_RDY BIT(15) #define BIT_FW_DW_RDY BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_8051FW_CTRL (Offset 0x0080) */ #define BIT_FWDL_RSVDPAGE_RDY BIT(12) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_SHIFT_CPU_CLK_SEL 12 #define BIT_MASK_CPU_CLK_SEL 0x3 #define BIT_CPU_CLK_SEL(x) \ (((x) & BIT_MASK_CPU_CLK_SEL) << BIT_SHIFT_CPU_CLK_SEL) #define BITS_CPU_CLK_SEL (BIT_MASK_CPU_CLK_SEL << BIT_SHIFT_CPU_CLK_SEL) #define BIT_CLEAR_CPU_CLK_SEL(x) ((x) & (~BITS_CPU_CLK_SEL)) #define BIT_GET_CPU_CLK_SEL(x) \ (((x) >> BIT_SHIFT_CPU_CLK_SEL) & BIT_MASK_CPU_CLK_SEL) #define BIT_SET_CPU_CLK_SEL(x, v) \ (BIT_CLEAR_CPU_CLK_SEL(x) | BIT_CPU_CLK_SEL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_8051FW_CTRL (Offset 0x0080) */ #define BIT_R_8051_ROMDLFW_EN BIT(11) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_CCLK_CHG_MASK BIT(11) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_8051FW_CTRL (Offset 0x0080) */ #define BIT_R_8051_INIT_RDY BIT(10) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_FW_INIT_RDY_V1 BIT(10) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_EMEM__TXBUF_CHKSUM_OK BIT(10) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_EMEM_TXBUF_CHKSUM_OK BIT(10) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_EMEM_TXBUF_DW_RDY BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_8051FW_CTRL (Offset 0x0080) */ #define BIT_R_8051_GAT BIT(8) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_MCU_CLK_EN BIT(8) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_EMEM_CHKSUM_OK BIT(8) #define BIT_EMEM_DW_OK BIT(7) #define BIT_DMEM_CHKSUM_OK BIT(6) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HRPWM1 (Offset 0x10250080) */ #define BIT_ACK BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_8051FW_CTRL (Offset 0x0080) */ #define BIT_RFINI_RDY BIT(5) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_RF_INIT_RDY BIT(5) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_DMEM_DW_OK BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_8051FW_CTRL (Offset 0x0080) */ #define BIT_BBINI_RDY BIT(4) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_BB_INIT_RDY BIT(4) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_IMEM_CHKSUM_OK BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_8051FW_CTRL (Offset 0x0080) */ #define BIT_MACINI_RDY BIT(3) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_MAC_INIT_RDY BIT(3) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_IMEM_DW_OK BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_8051FW_CTRL (Offset 0x0080) */ #define BIT_FWDL_CHK_RPT BIT(2) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_IMEM_BOOT_LOAD_CHKSUM_OK BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_8051FW_CTRL (Offset 0x0080) */ #define BIT_MCUFWDL_RDY BIT(1) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_MCU_FWDL_RDY BIT(1) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_IMEM_BOOT_LOAD_DW_OK BIT(1) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ #define BIT_MCU_FWDL_EN BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HRPWM1 (Offset 0x10250080) */ #define BIT_REQ_PS BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MCU_TST_CFG (Offset 0x0084) */ #define BIT_SHIFT_LBKTST 0 #define BIT_MASK_LBKTST 0xffff #define BIT_LBKTST(x) (((x) & BIT_MASK_LBKTST) << BIT_SHIFT_LBKTST) #define BITS_LBKTST (BIT_MASK_LBKTST << BIT_SHIFT_LBKTST) #define BIT_CLEAR_LBKTST(x) ((x) & (~BITS_LBKTST)) #define BIT_GET_LBKTST(x) (((x) >> BIT_SHIFT_LBKTST) & BIT_MASK_LBKTST) #define BIT_SET_LBKTST(x, v) (BIT_CLEAR_LBKTST(x) | BIT_LBKTST(v)) #endif #if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_MCU_TST_CFG (Offset 0x0084) */ #define BIT_SHIFT_C2H_MSG 0 #define BIT_MASK_C2H_MSG 0xffff #define BIT_C2H_MSG(x) (((x) & BIT_MASK_C2H_MSG) << BIT_SHIFT_C2H_MSG) #define BITS_C2H_MSG (BIT_MASK_C2H_MSG << BIT_SHIFT_C2H_MSG) #define BIT_CLEAR_C2H_MSG(x) ((x) & (~BITS_C2H_MSG)) #define BIT_GET_C2H_MSG(x) (((x) >> BIT_SHIFT_C2H_MSG) & BIT_MASK_C2H_MSG) #define BIT_SET_C2H_MSG(x, v) (BIT_CLEAR_C2H_MSG(x) | BIT_C2H_MSG(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_BUS_CTRL (Offset 0x10250085) */ #define BIT_INT_MASK_DIS BIT(4) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_BUS_CTRL (Offset 0x10250085) */ #define BIT_PAD_CLK_XHGE_EN BIT(3) #define BIT_INTER_CLK_EN BIT(2) #define BIT_EN_RPT_TXCRC BIT(1) #define BIT_DIS_RXDMA_STS BIT(0) /* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */ #define BIT_INTR_CTRL BIT(4) #define BIT_SDIO_VOLTAGE BIT(3) #define BIT_BYPASS_INIT BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */ #define BIT_HCI_RESUME_RDY BIT(1) #define BIT_HCI_SUS_REQ BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HMEBOX_E0_E1 (Offset 0x0088) */ #define BIT_SHIFT_HOST_MSG_E1 16 #define BIT_MASK_HOST_MSG_E1 0xffff #define BIT_HOST_MSG_E1(x) \ (((x) & BIT_MASK_HOST_MSG_E1) << BIT_SHIFT_HOST_MSG_E1) #define BITS_HOST_MSG_E1 (BIT_MASK_HOST_MSG_E1 << BIT_SHIFT_HOST_MSG_E1) #define BIT_CLEAR_HOST_MSG_E1(x) ((x) & (~BITS_HOST_MSG_E1)) #define BIT_GET_HOST_MSG_E1(x) \ (((x) >> BIT_SHIFT_HOST_MSG_E1) & BIT_MASK_HOST_MSG_E1) #define BIT_SET_HOST_MSG_E1(x, v) \ (BIT_CLEAR_HOST_MSG_E1(x) | BIT_HOST_MSG_E1(v)) #define BIT_SHIFT_HOST_MSG_E0 0 #define BIT_MASK_HOST_MSG_E0 0xffff #define BIT_HOST_MSG_E0(x) \ (((x) & BIT_MASK_HOST_MSG_E0) << BIT_SHIFT_HOST_MSG_E0) #define BITS_HOST_MSG_E0 (BIT_MASK_HOST_MSG_E0 << BIT_SHIFT_HOST_MSG_E0) #define BIT_CLEAR_HOST_MSG_E0(x) ((x) & (~BITS_HOST_MSG_E0)) #define BIT_GET_HOST_MSG_E0(x) \ (((x) >> BIT_SHIFT_HOST_MSG_E0) & BIT_MASK_HOST_MSG_E0) #define BIT_SET_HOST_MSG_E0(x, v) \ (BIT_CLEAR_HOST_MSG_E0(x) | BIT_HOST_MSG_E0(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_RESPONSE_TIMER (Offset 0x10250088) */ #define BIT_SHIFT_CMDIN_2RESP_TIMER 0 #define BIT_MASK_CMDIN_2RESP_TIMER 0xffff #define BIT_CMDIN_2RESP_TIMER(x) \ (((x) & BIT_MASK_CMDIN_2RESP_TIMER) << BIT_SHIFT_CMDIN_2RESP_TIMER) #define BITS_CMDIN_2RESP_TIMER \ (BIT_MASK_CMDIN_2RESP_TIMER << BIT_SHIFT_CMDIN_2RESP_TIMER) #define BIT_CLEAR_CMDIN_2RESP_TIMER(x) ((x) & (~BITS_CMDIN_2RESP_TIMER)) #define BIT_GET_CMDIN_2RESP_TIMER(x) \ (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER) & BIT_MASK_CMDIN_2RESP_TIMER) #define BIT_SET_CMDIN_2RESP_TIMER(x, v) \ (BIT_CLEAR_CMDIN_2RESP_TIMER(x) | BIT_CMDIN_2RESP_TIMER(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SDIO_CMD_CRC (Offset 0x1025008A) */ #define BIT_SHIFT_SDIO_CMD_CRC 1 #define BIT_MASK_SDIO_CMD_CRC 0x7f #define BIT_SDIO_CMD_CRC(x) \ (((x) & BIT_MASK_SDIO_CMD_CRC) << BIT_SHIFT_SDIO_CMD_CRC) #define BITS_SDIO_CMD_CRC (BIT_MASK_SDIO_CMD_CRC << BIT_SHIFT_SDIO_CMD_CRC) #define BIT_CLEAR_SDIO_CMD_CRC(x) ((x) & (~BITS_SDIO_CMD_CRC)) #define BIT_GET_SDIO_CMD_CRC(x) \ (((x) >> BIT_SHIFT_SDIO_CMD_CRC) & BIT_MASK_SDIO_CMD_CRC) #define BIT_SET_SDIO_CMD_CRC(x, v) \ (BIT_CLEAR_SDIO_CMD_CRC(x) | BIT_SDIO_CMD_CRC(v)) #define BIT_SDIO_CMD_E_BIT BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_CMD_CRC (Offset 0x1025008A) */ #define BIT_SHIFT_SDIO_CMD_CRC_V1 0 #define BIT_MASK_SDIO_CMD_CRC_V1 0xff #define BIT_SDIO_CMD_CRC_V1(x) \ (((x) & BIT_MASK_SDIO_CMD_CRC_V1) << BIT_SHIFT_SDIO_CMD_CRC_V1) #define BITS_SDIO_CMD_CRC_V1 \ (BIT_MASK_SDIO_CMD_CRC_V1 << BIT_SHIFT_SDIO_CMD_CRC_V1) #define BIT_CLEAR_SDIO_CMD_CRC_V1(x) ((x) & (~BITS_SDIO_CMD_CRC_V1)) #define BIT_GET_SDIO_CMD_CRC_V1(x) \ (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1) & BIT_MASK_SDIO_CMD_CRC_V1) #define BIT_SET_SDIO_CMD_CRC_V1(x, v) \ (BIT_CLEAR_SDIO_CMD_CRC_V1(x) | BIT_SDIO_CMD_CRC_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HMEBOX_E2_E3 (Offset 0x008C) */ #define BIT_SHIFT_HOST_MSG_E3 16 #define BIT_MASK_HOST_MSG_E3 0xffff #define BIT_HOST_MSG_E3(x) \ (((x) & BIT_MASK_HOST_MSG_E3) << BIT_SHIFT_HOST_MSG_E3) #define BITS_HOST_MSG_E3 (BIT_MASK_HOST_MSG_E3 << BIT_SHIFT_HOST_MSG_E3) #define BIT_CLEAR_HOST_MSG_E3(x) ((x) & (~BITS_HOST_MSG_E3)) #define BIT_GET_HOST_MSG_E3(x) \ (((x) >> BIT_SHIFT_HOST_MSG_E3) & BIT_MASK_HOST_MSG_E3) #define BIT_SET_HOST_MSG_E3(x, v) \ (BIT_CLEAR_HOST_MSG_E3(x) | BIT_HOST_MSG_E3(v)) #define BIT_SHIFT_HOST_MSG_E2 0 #define BIT_MASK_HOST_MSG_E2 0xffff #define BIT_HOST_MSG_E2(x) \ (((x) & BIT_MASK_HOST_MSG_E2) << BIT_SHIFT_HOST_MSG_E2) #define BITS_HOST_MSG_E2 (BIT_MASK_HOST_MSG_E2 << BIT_SHIFT_HOST_MSG_E2) #define BIT_CLEAR_HOST_MSG_E2(x) ((x) & (~BITS_HOST_MSG_E2)) #define BIT_GET_HOST_MSG_E2(x) \ (((x) >> BIT_SHIFT_HOST_MSG_E2) & BIT_MASK_HOST_MSG_E2) #define BIT_SET_HOST_MSG_E2(x, v) \ (BIT_CLEAR_HOST_MSG_E2(x) | BIT_HOST_MSG_E2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_WLLPSOP_EABM BIT(31) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_WLLPSOP_ACKF BIT(30) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_TXFIFO_TH_INT BIT(30) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_WLLPSOP_DLDM BIT(29) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_WLLPSOP_AFEP BIT(29) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_WLLPSOP_ESWR BIT(28) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_LPS_DIS_SW BIT(28) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_WLLPSOP_PWMM BIT(27) #define BIT_WLLPSOP_EECK BIT(26) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_WLLPSOP_ELDO BIT(25) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_WLLPSOP_WLMACOFF BIT(25) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_WLLPSOP_EXTAL BIT(24) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_LPS_BB_REG_EN BIT(23) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_WL_SYNPON_VOLTSPDN BIT(23) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_LPS_BB_PWR_EN BIT(22) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_WLLPSOP_WLBBOFF BIT(22) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_LPS_BB_GLB_EN BIT(21) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_WLLPSOP_WLMEM_DS BIT(21) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_WLLPSOP_LDO_WAIT_TIME BIT(20) #define BIT_WLLPSOP_ANA_CLK_DIVISION_2 BIT(19) #define BIT_AFE_BCN BIT(18) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_SUS_DIS_SW BIT(15) #define BIT_SUS_SKP_PAGE0_ALD BIT(14) #define BIT_SUS_LDO_SLEEP BIT(13) #define BIT_PFM_EN_ZCD BIT(12) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_SHIFT_LPLDH12_VADJ_STEP_DN 12 #define BIT_MASK_LPLDH12_VADJ_STEP_DN 0xf #define BIT_LPLDH12_VADJ_STEP_DN(x) \ (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN) \ << BIT_SHIFT_LPLDH12_VADJ_STEP_DN) #define BITS_LPLDH12_VADJ_STEP_DN \ (BIT_MASK_LPLDH12_VADJ_STEP_DN << BIT_SHIFT_LPLDH12_VADJ_STEP_DN) #define BIT_CLEAR_LPLDH12_VADJ_STEP_DN(x) ((x) & (~BITS_LPLDH12_VADJ_STEP_DN)) #define BIT_GET_LPLDH12_VADJ_STEP_DN(x) \ (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN) & \ BIT_MASK_LPLDH12_VADJ_STEP_DN) #define BIT_SET_LPLDH12_VADJ_STEP_DN(x, v) \ (BIT_CLEAR_LPLDH12_VADJ_STEP_DN(x) | BIT_LPLDH12_VADJ_STEP_DN(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_KEEP_RFC_EN BIT(11) #define BIT_MACON_NO_RFCISO_RELEASE BIT(10) #define BIT_MACON_NO_AFEPORT_PWR BIT(9) #define BIT_MACON_NO_CPU_EN BIT(8) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_SHIFT_V15ADJ_L1_STEP_DN 8 #define BIT_MASK_V15ADJ_L1_STEP_DN 0x7 #define BIT_V15ADJ_L1_STEP_DN(x) \ (((x) & BIT_MASK_V15ADJ_L1_STEP_DN) << BIT_SHIFT_V15ADJ_L1_STEP_DN) #define BITS_V15ADJ_L1_STEP_DN \ (BIT_MASK_V15ADJ_L1_STEP_DN << BIT_SHIFT_V15ADJ_L1_STEP_DN) #define BIT_CLEAR_V15ADJ_L1_STEP_DN(x) ((x) & (~BITS_V15ADJ_L1_STEP_DN)) #define BIT_GET_V15ADJ_L1_STEP_DN(x) \ (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN) & BIT_MASK_V15ADJ_L1_STEP_DN) #define BIT_SET_V15ADJ_L1_STEP_DN(x, v) \ (BIT_CLEAR_V15ADJ_L1_STEP_DN(x) | BIT_V15ADJ_L1_STEP_DN(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_SHIFT_V15ADJ_L1_STEP_DN_V1 8 #define BIT_MASK_V15ADJ_L1_STEP_DN_V1 0xf #define BIT_V15ADJ_L1_STEP_DN_V1(x) \ (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_V1) \ << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1) #define BITS_V15ADJ_L1_STEP_DN_V1 \ (BIT_MASK_V15ADJ_L1_STEP_DN_V1 << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1) #define BIT_CLEAR_V15ADJ_L1_STEP_DN_V1(x) ((x) & (~BITS_V15ADJ_L1_STEP_DN_V1)) #define BIT_GET_V15ADJ_L1_STEP_DN_V1(x) \ (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_V1) & \ BIT_MASK_V15ADJ_L1_STEP_DN_V1) #define BIT_SET_V15ADJ_L1_STEP_DN_V1(x, v) \ (BIT_CLEAR_V15ADJ_L1_STEP_DN_V1(x) | BIT_V15ADJ_L1_STEP_DN_V1(v)) #define BIT_FORCE_LEAVE_LPS BIT(3) #define BIT_SW_AFE_MODE BIT(2) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_REGU_32K_CLK_EN BIT(1) #define BIT_DRV_WLAN_INT_CLR BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ #define BIT_WL_LPS_EN BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HSISR (Offset 0x10250090) */ #define BIT_DRV_WLAN_INT BIT(0) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HSIMR (Offset 0x10250091) */ #define BIT_HISR_MASK BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ #define BIT_BB_DBG_SEL_AFE_SDM_V3 BIT(31) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ #define BIT_BB_DBG_SEL_AFE_SDM_BIT0 BIT(31) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ #define BIT_ORDER_SDM BIT(30) #define BIT_RFE_SEL_SDM BIT(29) #define BIT_SHIFT_REF_SEL 25 #define BIT_MASK_REF_SEL 0xf #define BIT_REF_SEL(x) (((x) & BIT_MASK_REF_SEL) << BIT_SHIFT_REF_SEL) #define BITS_REF_SEL (BIT_MASK_REF_SEL << BIT_SHIFT_REF_SEL) #define BIT_CLEAR_REF_SEL(x) ((x) & (~BITS_REF_SEL)) #define BIT_GET_REF_SEL(x) (((x) >> BIT_SHIFT_REF_SEL) & BIT_MASK_REF_SEL) #define BIT_SET_REF_SEL(x, v) (BIT_CLEAR_REF_SEL(x) | BIT_REF_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ #define BIT_SHIFT_F0F_SDM_V2 12 #define BIT_MASK_F0F_SDM_V2 0x1fff #define BIT_F0F_SDM_V2(x) (((x) & BIT_MASK_F0F_SDM_V2) << BIT_SHIFT_F0F_SDM_V2) #define BITS_F0F_SDM_V2 (BIT_MASK_F0F_SDM_V2 << BIT_SHIFT_F0F_SDM_V2) #define BIT_CLEAR_F0F_SDM_V2(x) ((x) & (~BITS_F0F_SDM_V2)) #define BIT_GET_F0F_SDM_V2(x) \ (((x) >> BIT_SHIFT_F0F_SDM_V2) & BIT_MASK_F0F_SDM_V2) #define BIT_SET_F0F_SDM_V2(x, v) (BIT_CLEAR_F0F_SDM_V2(x) | BIT_F0F_SDM_V2(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ #define BIT_SHIFT_F0F_SDM 12 #define BIT_MASK_F0F_SDM 0x1fff #define BIT_F0F_SDM(x) (((x) & BIT_MASK_F0F_SDM) << BIT_SHIFT_F0F_SDM) #define BITS_F0F_SDM (BIT_MASK_F0F_SDM << BIT_SHIFT_F0F_SDM) #define BIT_CLEAR_F0F_SDM(x) ((x) & (~BITS_F0F_SDM)) #define BIT_GET_F0F_SDM(x) (((x) >> BIT_SHIFT_F0F_SDM) & BIT_MASK_F0F_SDM) #define BIT_SET_F0F_SDM(x, v) (BIT_CLEAR_F0F_SDM(x) | BIT_F0F_SDM(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ #define BIT_SHIFT_F0N_SDM_V2 9 #define BIT_MASK_F0N_SDM_V2 0x7 #define BIT_F0N_SDM_V2(x) (((x) & BIT_MASK_F0N_SDM_V2) << BIT_SHIFT_F0N_SDM_V2) #define BITS_F0N_SDM_V2 (BIT_MASK_F0N_SDM_V2 << BIT_SHIFT_F0N_SDM_V2) #define BIT_CLEAR_F0N_SDM_V2(x) ((x) & (~BITS_F0N_SDM_V2)) #define BIT_GET_F0N_SDM_V2(x) \ (((x) >> BIT_SHIFT_F0N_SDM_V2) & BIT_MASK_F0N_SDM_V2) #define BIT_SET_F0N_SDM_V2(x, v) (BIT_CLEAR_F0N_SDM_V2(x) | BIT_F0N_SDM_V2(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ #define BIT_SHIFT_F0N_SDM 9 #define BIT_MASK_F0N_SDM 0x7 #define BIT_F0N_SDM(x) (((x) & BIT_MASK_F0N_SDM) << BIT_SHIFT_F0N_SDM) #define BITS_F0N_SDM (BIT_MASK_F0N_SDM << BIT_SHIFT_F0N_SDM) #define BIT_CLEAR_F0N_SDM(x) ((x) & (~BITS_F0N_SDM)) #define BIT_GET_F0N_SDM(x) (((x) >> BIT_SHIFT_F0N_SDM) & BIT_MASK_F0N_SDM) #define BIT_SET_F0N_SDM(x, v) (BIT_CLEAR_F0N_SDM(x) | BIT_F0N_SDM(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ #define BIT_SHIFT_DIVN_SDM_V2 3 #define BIT_MASK_DIVN_SDM_V2 0x3f #define BIT_DIVN_SDM_V2(x) \ (((x) & BIT_MASK_DIVN_SDM_V2) << BIT_SHIFT_DIVN_SDM_V2) #define BITS_DIVN_SDM_V2 (BIT_MASK_DIVN_SDM_V2 << BIT_SHIFT_DIVN_SDM_V2) #define BIT_CLEAR_DIVN_SDM_V2(x) ((x) & (~BITS_DIVN_SDM_V2)) #define BIT_GET_DIVN_SDM_V2(x) \ (((x) >> BIT_SHIFT_DIVN_SDM_V2) & BIT_MASK_DIVN_SDM_V2) #define BIT_SET_DIVN_SDM_V2(x, v) \ (BIT_CLEAR_DIVN_SDM_V2(x) | BIT_DIVN_SDM_V2(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ #define BIT_SHIFT_DIVN_SDM 3 #define BIT_MASK_DIVN_SDM 0x3f #define BIT_DIVN_SDM(x) (((x) & BIT_MASK_DIVN_SDM) << BIT_SHIFT_DIVN_SDM) #define BITS_DIVN_SDM (BIT_MASK_DIVN_SDM << BIT_SHIFT_DIVN_SDM) #define BIT_CLEAR_DIVN_SDM(x) ((x) & (~BITS_DIVN_SDM)) #define BIT_GET_DIVN_SDM(x) (((x) >> BIT_SHIFT_DIVN_SDM) & BIT_MASK_DIVN_SDM) #define BIT_SET_DIVN_SDM(x, v) (BIT_CLEAR_DIVN_SDM(x) | BIT_DIVN_SDM(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ #define BIT_SHIFT_DITHER_SDM_V2 0 #define BIT_MASK_DITHER_SDM_V2 0x7 #define BIT_DITHER_SDM_V2(x) \ (((x) & BIT_MASK_DITHER_SDM_V2) << BIT_SHIFT_DITHER_SDM_V2) #define BITS_DITHER_SDM_V2 (BIT_MASK_DITHER_SDM_V2 << BIT_SHIFT_DITHER_SDM_V2) #define BIT_CLEAR_DITHER_SDM_V2(x) ((x) & (~BITS_DITHER_SDM_V2)) #define BIT_GET_DITHER_SDM_V2(x) \ (((x) >> BIT_SHIFT_DITHER_SDM_V2) & BIT_MASK_DITHER_SDM_V2) #define BIT_SET_DITHER_SDM_V2(x, v) \ (BIT_CLEAR_DITHER_SDM_V2(x) | BIT_DITHER_SDM_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_DEBOUNCE_CTRL (Offset 0x0098) */ #define BIT_WLGP_DBC1EN BIT(15) #define BIT_SHIFT_WLGP_DBC1 8 #define BIT_MASK_WLGP_DBC1 0xf #define BIT_WLGP_DBC1(x) (((x) & BIT_MASK_WLGP_DBC1) << BIT_SHIFT_WLGP_DBC1) #define BITS_WLGP_DBC1 (BIT_MASK_WLGP_DBC1 << BIT_SHIFT_WLGP_DBC1) #define BIT_CLEAR_WLGP_DBC1(x) ((x) & (~BITS_WLGP_DBC1)) #define BIT_GET_WLGP_DBC1(x) (((x) >> BIT_SHIFT_WLGP_DBC1) & BIT_MASK_WLGP_DBC1) #define BIT_SET_WLGP_DBC1(x, v) (BIT_CLEAR_WLGP_DBC1(x) | BIT_WLGP_DBC1(v)) #define BIT_WLGP_DBC0EN BIT(7) #define BIT_SHIFT_WLGP_DBC0 0 #define BIT_MASK_WLGP_DBC0 0xf #define BIT_WLGP_DBC0(x) (((x) & BIT_MASK_WLGP_DBC0) << BIT_SHIFT_WLGP_DBC0) #define BITS_WLGP_DBC0 (BIT_MASK_WLGP_DBC0 << BIT_SHIFT_WLGP_DBC0) #define BIT_CLEAR_WLGP_DBC0(x) ((x) & (~BITS_WLGP_DBC0)) #define BIT_GET_WLGP_DBC0(x) (((x) >> BIT_SHIFT_WLGP_DBC0) & BIT_MASK_WLGP_DBC0) #define BIT_SET_WLGP_DBC0(x, v) (BIT_CLEAR_WLGP_DBC0(x) | BIT_WLGP_DBC0(v)) /* 2 REG_RPWM2 (Offset 0x009C) */ #define BIT_SHIFT_RPWM2 16 #define BIT_MASK_RPWM2 0xffff #define BIT_RPWM2(x) (((x) & BIT_MASK_RPWM2) << BIT_SHIFT_RPWM2) #define BITS_RPWM2 (BIT_MASK_RPWM2 << BIT_SHIFT_RPWM2) #define BIT_CLEAR_RPWM2(x) ((x) & (~BITS_RPWM2)) #define BIT_GET_RPWM2(x) (((x) >> BIT_SHIFT_RPWM2) & BIT_MASK_RPWM2) #define BIT_SET_RPWM2(x, v) (BIT_CLEAR_RPWM2(x) | BIT_RPWM2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYSON_FSM_MON (Offset 0x00A0) */ #define BIT_SHIFT_FSM_MON_SEL 24 #define BIT_MASK_FSM_MON_SEL 0x7 #define BIT_FSM_MON_SEL(x) \ (((x) & BIT_MASK_FSM_MON_SEL) << BIT_SHIFT_FSM_MON_SEL) #define BITS_FSM_MON_SEL (BIT_MASK_FSM_MON_SEL << BIT_SHIFT_FSM_MON_SEL) #define BIT_CLEAR_FSM_MON_SEL(x) ((x) & (~BITS_FSM_MON_SEL)) #define BIT_GET_FSM_MON_SEL(x) \ (((x) >> BIT_SHIFT_FSM_MON_SEL) & BIT_MASK_FSM_MON_SEL) #define BIT_SET_FSM_MON_SEL(x, v) \ (BIT_CLEAR_FSM_MON_SEL(x) | BIT_FSM_MON_SEL(v)) #define BIT_DOP_ELDO BIT(23) #define BIT_FSM_MON_UPD BIT(15) #define BIT_SHIFT_FSM_PAR 0 #define BIT_MASK_FSM_PAR 0x7fff #define BIT_FSM_PAR(x) (((x) & BIT_MASK_FSM_PAR) << BIT_SHIFT_FSM_PAR) #define BITS_FSM_PAR (BIT_MASK_FSM_PAR << BIT_SHIFT_FSM_PAR) #define BIT_CLEAR_FSM_PAR(x) ((x) & (~BITS_FSM_PAR)) #define BIT_GET_FSM_PAR(x) (((x) >> BIT_SHIFT_FSM_PAR) & BIT_MASK_FSM_PAR) #define BIT_SET_FSM_PAR(x, v) (BIT_CLEAR_FSM_PAR(x) | BIT_FSM_PAR(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL6 (Offset 0x00A4) */ #define BIT_SHIFT_TSFT_SEL_V1 0 #define BIT_MASK_TSFT_SEL_V1 0x7 #define BIT_TSFT_SEL_V1(x) \ (((x) & BIT_MASK_TSFT_SEL_V1) << BIT_SHIFT_TSFT_SEL_V1) #define BITS_TSFT_SEL_V1 (BIT_MASK_TSFT_SEL_V1 << BIT_SHIFT_TSFT_SEL_V1) #define BIT_CLEAR_TSFT_SEL_V1(x) ((x) & (~BITS_TSFT_SEL_V1)) #define BIT_GET_TSFT_SEL_V1(x) \ (((x) >> BIT_SHIFT_TSFT_SEL_V1) & BIT_MASK_TSFT_SEL_V1) #define BIT_SET_TSFT_SEL_V1(x, v) \ (BIT_CLEAR_TSFT_SEL_V1(x) | BIT_TSFT_SEL_V1(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL6 (Offset 0x00A4) */ #define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1 0 #define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1 0x7 #define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \ (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) \ << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) #define BITS_BB_DBG_SEL_AFE_SDM_BIT3_1 \ (BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1 \ << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) #define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \ ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_BIT3_1)) #define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \ (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) & \ BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) #define BIT_SET_BB_DBG_SEL_AFE_SDM_BIT3_1(x, v) \ (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1(x) | \ BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */ #define BIT_BT_INT_EN BIT(31) #define BIT_SHIFT_RD_WR_WIFI_BT_INFO 16 #define BIT_MASK_RD_WR_WIFI_BT_INFO 0x7fff #define BIT_RD_WR_WIFI_BT_INFO(x) \ (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO) << BIT_SHIFT_RD_WR_WIFI_BT_INFO) #define BITS_RD_WR_WIFI_BT_INFO \ (BIT_MASK_RD_WR_WIFI_BT_INFO << BIT_SHIFT_RD_WR_WIFI_BT_INFO) #define BIT_CLEAR_RD_WR_WIFI_BT_INFO(x) ((x) & (~BITS_RD_WR_WIFI_BT_INFO)) #define BIT_GET_RD_WR_WIFI_BT_INFO(x) \ (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO) & BIT_MASK_RD_WR_WIFI_BT_INFO) #define BIT_SET_RD_WR_WIFI_BT_INFO(x, v) \ (BIT_CLEAR_RD_WR_WIFI_BT_INFO(x) | BIT_RD_WR_WIFI_BT_INFO(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */ #define BIT_PMC_WR_OVF BIT(8) #define BIT_SHIFT_WLPMC_ERRINT 0 #define BIT_MASK_WLPMC_ERRINT 0xff #define BIT_WLPMC_ERRINT(x) \ (((x) & BIT_MASK_WLPMC_ERRINT) << BIT_SHIFT_WLPMC_ERRINT) #define BITS_WLPMC_ERRINT (BIT_MASK_WLPMC_ERRINT << BIT_SHIFT_WLPMC_ERRINT) #define BIT_CLEAR_WLPMC_ERRINT(x) ((x) & (~BITS_WLPMC_ERRINT)) #define BIT_GET_WLPMC_ERRINT(x) \ (((x) >> BIT_SHIFT_WLPMC_ERRINT) & BIT_MASK_WLPMC_ERRINT) #define BIT_SET_WLPMC_ERRINT(x, v) \ (BIT_CLEAR_WLPMC_ERRINT(x) | BIT_WLPMC_ERRINT(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ #define BIT_SHIFT_SEL_V 30 #define BIT_MASK_SEL_V 0x3 #define BIT_SEL_V(x) (((x) & BIT_MASK_SEL_V) << BIT_SHIFT_SEL_V) #define BITS_SEL_V (BIT_MASK_SEL_V << BIT_SHIFT_SEL_V) #define BIT_CLEAR_SEL_V(x) ((x) & (~BITS_SEL_V)) #define BIT_GET_SEL_V(x) (((x) >> BIT_SHIFT_SEL_V) & BIT_MASK_SEL_V) #define BIT_SET_SEL_V(x, v) (BIT_CLEAR_SEL_V(x) | BIT_SEL_V(v)) #define BIT_SEL_LDO_PC BIT(29) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ #define BIT_SHIFT_CK_MON_SEL_V2 26 #define BIT_MASK_CK_MON_SEL_V2 0x7 #define BIT_CK_MON_SEL_V2(x) \ (((x) & BIT_MASK_CK_MON_SEL_V2) << BIT_SHIFT_CK_MON_SEL_V2) #define BITS_CK_MON_SEL_V2 (BIT_MASK_CK_MON_SEL_V2 << BIT_SHIFT_CK_MON_SEL_V2) #define BIT_CLEAR_CK_MON_SEL_V2(x) ((x) & (~BITS_CK_MON_SEL_V2)) #define BIT_GET_CK_MON_SEL_V2(x) \ (((x) >> BIT_SHIFT_CK_MON_SEL_V2) & BIT_MASK_CK_MON_SEL_V2) #define BIT_SET_CK_MON_SEL_V2(x, v) \ (BIT_CLEAR_CK_MON_SEL_V2(x) | BIT_CK_MON_SEL_V2(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ #define BIT_SHIFT_CK_MON_SEL 26 #define BIT_MASK_CK_MON_SEL 0x7 #define BIT_CK_MON_SEL(x) (((x) & BIT_MASK_CK_MON_SEL) << BIT_SHIFT_CK_MON_SEL) #define BITS_CK_MON_SEL (BIT_MASK_CK_MON_SEL << BIT_SHIFT_CK_MON_SEL) #define BIT_CLEAR_CK_MON_SEL(x) ((x) & (~BITS_CK_MON_SEL)) #define BIT_GET_CK_MON_SEL(x) \ (((x) >> BIT_SHIFT_CK_MON_SEL) & BIT_MASK_CK_MON_SEL) #define BIT_SET_CK_MON_SEL(x, v) (BIT_CLEAR_CK_MON_SEL(x) | BIT_CK_MON_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ #define BIT_CK_MON_EN BIT(25) #define BIT_FREF_EDGE BIT(24) #define BIT_CK320M_EN BIT(23) #define BIT_CK_5M_EN BIT(22) #define BIT_TESTEN BIT(21) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_TIMEOUT_INTERRUPT2_MASK BIT(31) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_PSTIMER_2_MSK BIT(31) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_TIMEOUT_INTERRUTP1_MASK BIT(30) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_PSTIMER_1_MSK BIT(30) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_PSTIMEOUT_MSK BIT(29) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_PSTIMER_0_MSK BIT(29) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_GTINT4_MSK BIT(28) #define BIT_GTINT4 BIT(28) #define BIT_GTINT3_MSK BIT(27) #define BIT_GTINT3 BIT(27) #define BIT_TXBCN0ERR_MSK BIT(26) #define BIT_TXBCN0ERR BIT(26) #define BIT_TXBCN0OK_MSK BIT(25) #define BIT_TXBCN0OK BIT(25) #define BIT_TSF_BIT32_TOGGLE_MSK BIT(24) #define BIT_TSF_BIT32_TOGGLE BIT(24) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_TXDMA_START_INT_MSK BIT(23) #define BIT_TXDMA_STOP_INT_MSK BIT(22) #define BIT_HISR7_IND_MSK BIT(21) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_BCNDMAINT0_MSK BIT(20) #define BIT_BCNDMAINT0 BIT(20) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_HISR6_IND_MSK BIT(19) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_HISR5_MSK BIT(18) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_HISR5_IND_MSK BIT(18) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_HISR4_MSK BIT(17) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_HISR4_IND_MSK BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_BCNDERR0_MSK BIT(16) #define BIT_BCNDERR0 BIT(16) #define BIT_HSISR_IND_ON_INT_MSK BIT(15) #define BIT_HSISR_IND_ON_INT BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_BCNDMAINT_E_MSK BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_HISR3_IND_INT_MSK BIT(14) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_HISR3_IND_MSK BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_HISR2_IND_INT_MSK BIT(13) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_HISR2_IND_MSK BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_CTWEND_MSK BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_HISR1_IND_MSK BIT(11) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_HISR1_IND_INT_MSK BIT(11) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_C2HCMD_MSK BIT(10) #define BIT_C2HCMD BIT(10) #define BIT_CPWM2_MSK BIT(9) #define BIT_CPWM2 BIT(9) #define BIT_CPWM_MSK BIT(8) #define BIT_CPWM BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_HIGHDOK_MSK BIT(7) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_TXDMAOK_CHANNEL15_MSK BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_MGTDOK_MSK BIT(6) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_TXDMAOK_CHANNEL14_MSK BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_BKDOK_MSK BIT(5) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_TXDMAOK_CHANNEL3_MSK BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_BEDOK_MSK BIT(4) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_TXDMAOK_CHANNEL2_MSK BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_VIDOK_MSK BIT(3) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_TXDMAOK_CHANNEL1_MSK BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_VODOK_MSK BIT(2) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_TXDMAOK_CHANNEL0_MSK BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ #define BIT_RDU_MSK BIT(1) #define BIT_RDU BIT(1) #define BIT_RXOK_MSK BIT(0) #define BIT_RXOK BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HISR0 (Offset 0x00B4) */ #define BIT_PSTIMEOUT2 BIT(31) #define BIT_PSTIMEOUT1 BIT(30) #define BIT_PSTIMEOUT BIT(29) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HISR0 (Offset 0x00B4) */ #define BIT_HISR5_IND_INT BIT(18) #define BIT_HISR4_IND_INT BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HISR0 (Offset 0x00B4) */ #define BIT_BCNDMAINT_E BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HISR0 (Offset 0x00B4) */ #define BIT_HISR3_IND_INT BIT(14) #define BIT_HISR2_IND_INT BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HISR0 (Offset 0x00B4) */ #define BIT_CTWEND BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HISR0 (Offset 0x00B4) */ #define BIT_HISR1_IND_INT BIT(11) #define BIT_HIGHDOK BIT(7) #define BIT_MGTDOK BIT(6) #define BIT_BKDOK BIT(5) #define BIT_BEDOK BIT(4) #define BIT_VIDOK BIT(3) #define BIT_VODOK BIT(2) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_PRETXERR_HANDLE_MSK BIT(31) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_PRE_TX_ERR_INT_MSK BIT(31) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_BTON_STS_UPDATE_INT BIT(29) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_BTON_STS_UPDATE_MSK BIT(29) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_BTON_STS_UPDATE_MASK BIT(29) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_MCU_ERR_MASK BIT(28) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_BCNDMAINT7 BIT(27) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_BCNDMAINT7_MSK BIT(27) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_BCNDMAINT7__MSK BIT(27) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_BCNDMAINT6 BIT(26) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_BCNDMAINT6_MSK BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_BCNDMAINT6__MSK BIT(26) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_BCNDMAINT5 BIT(25) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_BCNDMAINT5_MSK BIT(25) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_BCNDMAINT5__MSK BIT(25) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_BCNDMAINT4 BIT(24) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_BCNDMAINT4_MSK BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_BCNDMAINT4__MSK BIT(24) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_BCNDMAINT3_MSK BIT(23) #define BIT_BCNDMAINT3 BIT(23) #define BIT_BCNDMAINT2_MSK BIT(22) #define BIT_BCNDMAINT2 BIT(22) #define BIT_BCNDMAINT1_MSK BIT(21) #define BIT_BCNDMAINT1 BIT(21) #define BIT_BCNDERR7_MSK BIT(20) #define BIT_BCNDERR7 BIT(20) #define BIT_BCNDERR6_MSK BIT(19) #define BIT_BCNDERR6 BIT(19) #define BIT_BCNDERR5_MSK BIT(18) #define BIT_BCNDERR5 BIT(18) #define BIT_BCNDERR4_MSK BIT(17) #define BIT_BCNDERR4 BIT(17) #define BIT_BCNDERR3_MSK BIT(16) #define BIT_BCNDERR3 BIT(16) #define BIT_BCNDERR2_MSK BIT(15) #define BIT_BCNDERR2 BIT(15) #define BIT_BCNDERR1_MSK BIT(14) #define BIT_BCNDERR1 BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_ATIMEND_E_MSK BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_ATIMEND_MSK BIT(12) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_ATIMEND__MSK BIT(12) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_ATIMEND_E_V1_MSK BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_TXERR_MSK BIT(11) #define BIT_TXERR_INT BIT(11) #define BIT_RXERR_MSK BIT(10) #define BIT_RXERR_INT BIT(10) #define BIT_TXFOVW_MSK BIT(9) #define BIT_TXFOVW BIT(9) #define BIT_FOVW_MSK BIT(8) #define BIT_FOVW BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_LD_B12V_EN_V1 BIT(7) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_CPU_MGQ_EARLY_INT_MSK BIT(6) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_CPU_MGQ_TXDONE_MSK BIT(5) #define BIT_CPU_MGQ_TXDONE BIT(5) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_PSTIMER_5_MSK BIT(4) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_PS_TIMER_C_MSK BIT(4) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_PSTIMER_4_MSK BIT(3) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_PS_TIMER_B_MSK BIT(3) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_PSTIMER_3_MSK BIT(2) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_PS_TIMER_A_MSK BIT(2) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_CPUMGQ_TX_TIMER_MSK BIT(1) #define BIT_CPUMGQ_TX_TIMER BIT(1) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ #define BIT_BB_STOPRX_INT_MSK BIT(0) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HISR1 (Offset 0x00BC) */ #define BIT_PRETXERR_HANDLE_INT BIT(31) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HISR1 (Offset 0x00BC) */ #define BIT_MCU_ERR BIT(28) #define BIT_ATIMEND_E BIT(13) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_HISR1 (Offset 0x00BC) */ #define BIT_ATIMEND_E_V1_INT BIT(12) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HISR1 (Offset 0x00BC) */ #define BIT_PS_TIMER_C BIT(4) #define BIT_PS_TIMER_B BIT(3) #define BIT_PS_TIMER_A BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */ #define BIT_HR_FF_OVF BIT(6) #define BIT_HR_FF_UDN BIT(5) #define BIT_TXDMA_BUSY_ERR BIT(4) #define BIT_TXDMA_VLD_ERR BIT(3) #define BIT_QSEL_UNKNOWN_ERR BIT(2) #define BIT_QSEL_MIS_ERR BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DBG_PORT_SEL (Offset 0x00C0) */ #define BIT_SHIFT_DEBUG_ST 0 #define BIT_MASK_DEBUG_ST 0xffffffffL #define BIT_DEBUG_ST(x) (((x) & BIT_MASK_DEBUG_ST) << BIT_SHIFT_DEBUG_ST) #define BITS_DEBUG_ST (BIT_MASK_DEBUG_ST << BIT_SHIFT_DEBUG_ST) #define BIT_CLEAR_DEBUG_ST(x) ((x) & (~BITS_DEBUG_ST)) #define BIT_GET_DEBUG_ST(x) (((x) >> BIT_SHIFT_DEBUG_ST) & BIT_MASK_DEBUG_ST) #define BIT_SET_DEBUG_ST(x, v) (BIT_CLEAR_DEBUG_ST(x) | BIT_DEBUG_ST(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */ #define BIT_SDIO_OVERRD_ERR BIT(0) #define BIT_SHIFT_SDIO_DATA_REPLY_TIME 0 #define BIT_MASK_SDIO_DATA_REPLY_TIME 0x7 #define BIT_SDIO_DATA_REPLY_TIME(x) \ (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME) \ << BIT_SHIFT_SDIO_DATA_REPLY_TIME) #define BITS_SDIO_DATA_REPLY_TIME \ (BIT_MASK_SDIO_DATA_REPLY_TIME << BIT_SHIFT_SDIO_DATA_REPLY_TIME) #define BIT_CLEAR_SDIO_DATA_REPLY_TIME(x) ((x) & (~BITS_SDIO_DATA_REPLY_TIME)) #define BIT_GET_SDIO_DATA_REPLY_TIME(x) \ (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME) & \ BIT_MASK_SDIO_DATA_REPLY_TIME) #define BIT_SET_SDIO_DATA_REPLY_TIME(x, v) \ (BIT_CLEAR_SDIO_DATA_REPLY_TIME(x) | BIT_SDIO_DATA_REPLY_TIME(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_DIOERR_RPT (Offset 0x102500C0) */ #define BIT_SDIO_PAGE_ERR BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_CMD_ERRCNT (Offset 0x102500C2) */ #define BIT_SHIFT_CMD_CRC_ERR_CNT 0 #define BIT_MASK_CMD_CRC_ERR_CNT 0xff #define BIT_CMD_CRC_ERR_CNT(x) \ (((x) & BIT_MASK_CMD_CRC_ERR_CNT) << BIT_SHIFT_CMD_CRC_ERR_CNT) #define BITS_CMD_CRC_ERR_CNT \ (BIT_MASK_CMD_CRC_ERR_CNT << BIT_SHIFT_CMD_CRC_ERR_CNT) #define BIT_CLEAR_CMD_CRC_ERR_CNT(x) ((x) & (~BITS_CMD_CRC_ERR_CNT)) #define BIT_GET_CMD_CRC_ERR_CNT(x) \ (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT) & BIT_MASK_CMD_CRC_ERR_CNT) #define BIT_SET_CMD_CRC_ERR_CNT(x, v) \ (BIT_CLEAR_CMD_CRC_ERR_CNT(x) | BIT_CMD_CRC_ERR_CNT(v)) /* 2 REG_SDIO_DATA_ERRCNT (Offset 0x102500C3) */ #define BIT_SHIFT_DATA_CRC_ERR_CNT 0 #define BIT_MASK_DATA_CRC_ERR_CNT 0xff #define BIT_DATA_CRC_ERR_CNT(x) \ (((x) & BIT_MASK_DATA_CRC_ERR_CNT) << BIT_SHIFT_DATA_CRC_ERR_CNT) #define BITS_DATA_CRC_ERR_CNT \ (BIT_MASK_DATA_CRC_ERR_CNT << BIT_SHIFT_DATA_CRC_ERR_CNT) #define BIT_CLEAR_DATA_CRC_ERR_CNT(x) ((x) & (~BITS_DATA_CRC_ERR_CNT)) #define BIT_GET_DATA_CRC_ERR_CNT(x) \ (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT) & BIT_MASK_DATA_CRC_ERR_CNT) #define BIT_SET_DATA_CRC_ERR_CNT(x, v) \ (BIT_CLEAR_DATA_CRC_ERR_CNT(x) | BIT_DATA_CRC_ERR_CNT(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_MAC_SOP BIT(25) #define BIT_LDO11_ST_EXT BIT(24) #define BIT_ANTSELB_S2 BIT(23) #define BIT_ANTSELB_S1 BIT(22) #define BIT_ANTSEL_S3 BIT(21) #define BIT_ANTSEL_S2 BIT(20) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_USB3_USB2_TRANSITION BIT(20) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_ANTSEL_S1 BIT(19) #define BIT_FCSN_PU BIT(18) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_SHIFT_USB23_SW_MODE_V1 18 #define BIT_MASK_USB23_SW_MODE_V1 0x3 #define BIT_USB23_SW_MODE_V1(x) \ (((x) & BIT_MASK_USB23_SW_MODE_V1) << BIT_SHIFT_USB23_SW_MODE_V1) #define BITS_USB23_SW_MODE_V1 \ (BIT_MASK_USB23_SW_MODE_V1 << BIT_SHIFT_USB23_SW_MODE_V1) #define BIT_CLEAR_USB23_SW_MODE_V1(x) ((x) & (~BITS_USB23_SW_MODE_V1)) #define BIT_GET_USB23_SW_MODE_V1(x) \ (((x) >> BIT_SHIFT_USB23_SW_MODE_V1) & BIT_MASK_USB23_SW_MODE_V1) #define BIT_SET_USB23_SW_MODE_V1(x, v) \ (BIT_CLEAR_USB23_SW_MODE_V1(x) | BIT_USB23_SW_MODE_V1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_KEEP_PAD BIT(17) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_NO_PDN_CHIPOFF_V1 BIT(17) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_PAD_ALD_SKP BIT(16) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_RSM_EN_V1 BIT(16) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_PAD_A_ANTSEL_E BIT(11) #define BIT_PAD_A_ANTSELB_E BIT(10) #define BIT_PAD_A_ANTSEL_O BIT(9) #define BIT_PAD_A_ANTSELB_O BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_LD_B12V_EN BIT(7) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_B15V_EN BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_EESK_IOSEL BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_EECS_IOSEL_V1 BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_EESK_DATA_O BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_EECS_DATA_O_V1 BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_EESK_DATA_I BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_EECS_DATA_I_V1 BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_EECS_IOSEL BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_EESK_IOSEL_V1 BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_EECS_DATA_O BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_EESK_DATA_O_V1 BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_EECS_DATA_I BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ #define BIT_EESK_DATA_I_V1 BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_CMD_ERR_CONTENT (Offset 0x102500C4) */ #define BIT_SHIFT_SDIO_CMD_ERR_CONTENT 0 #define BIT_MASK_SDIO_CMD_ERR_CONTENT 0xffffffffffL #define BIT_SDIO_CMD_ERR_CONTENT(x) \ (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT) \ << BIT_SHIFT_SDIO_CMD_ERR_CONTENT) #define BITS_SDIO_CMD_ERR_CONTENT \ (BIT_MASK_SDIO_CMD_ERR_CONTENT << BIT_SHIFT_SDIO_CMD_ERR_CONTENT) #define BIT_CLEAR_SDIO_CMD_ERR_CONTENT(x) ((x) & (~BITS_SDIO_CMD_ERR_CONTENT)) #define BIT_GET_SDIO_CMD_ERR_CONTENT(x) \ (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT) & \ BIT_MASK_SDIO_CMD_ERR_CONTENT) #define BIT_SET_SDIO_CMD_ERR_CONTENT(x, v) \ (BIT_CLEAR_SDIO_CMD_ERR_CONTENT(x) | BIT_SDIO_CMD_ERR_CONTENT(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_MEM_RMC (Offset 0x00C8) */ #define BIT_MEM_RMV_SIGN BIT(31) #define BIT_MEM_RMV_2PRF1 BIT(29) #define BIT_MEM_RMV_2PRF0 BIT(28) #define BIT_MEM_RMV_1PRF1 BIT(27) #define BIT_MEM_RMV_1PRF0 BIT(26) #define BIT_MEM_RMV_1PSR BIT(25) #define BIT_MEM_RMV_ROM BIT(24) #define BIT_SHIFT_MEM_RME_WL_V2 4 #define BIT_MASK_MEM_RME_WL_V2 0x3f #define BIT_MEM_RME_WL_V2(x) \ (((x) & BIT_MASK_MEM_RME_WL_V2) << BIT_SHIFT_MEM_RME_WL_V2) #define BITS_MEM_RME_WL_V2 (BIT_MASK_MEM_RME_WL_V2 << BIT_SHIFT_MEM_RME_WL_V2) #define BIT_CLEAR_MEM_RME_WL_V2(x) ((x) & (~BITS_MEM_RME_WL_V2)) #define BIT_GET_MEM_RME_WL_V2(x) \ (((x) >> BIT_SHIFT_MEM_RME_WL_V2) & BIT_MASK_MEM_RME_WL_V2) #define BIT_SET_MEM_RME_WL_V2(x, v) \ (BIT_CLEAR_MEM_RME_WL_V2(x) | BIT_MEM_RME_WL_V2(v)) #define BIT_SHIFT_MEM_RME_HCI_V2 0 #define BIT_MASK_MEM_RME_HCI_V2 0x1f #define BIT_MEM_RME_HCI_V2(x) \ (((x) & BIT_MASK_MEM_RME_HCI_V2) << BIT_SHIFT_MEM_RME_HCI_V2) #define BITS_MEM_RME_HCI_V2 \ (BIT_MASK_MEM_RME_HCI_V2 << BIT_SHIFT_MEM_RME_HCI_V2) #define BIT_CLEAR_MEM_RME_HCI_V2(x) ((x) & (~BITS_MEM_RME_HCI_V2)) #define BIT_GET_MEM_RME_HCI_V2(x) \ (((x) >> BIT_SHIFT_MEM_RME_HCI_V2) & BIT_MASK_MEM_RME_HCI_V2) #define BIT_SET_MEM_RME_HCI_V2(x, v) \ (BIT_CLEAR_MEM_RME_HCI_V2(x) | BIT_MEM_RME_HCI_V2(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_CRC_ERR_IDX (Offset 0x102500C9) */ #define BIT_D3_CRC_ERR BIT(4) #define BIT_D2_CRC_ERR BIT(3) #define BIT_D1_CRC_ERR BIT(2) #define BIT_D0_CRC_ERR BIT(1) #define BIT_CMD_CRC_ERR BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_DATA_CRC (Offset 0x102500CA) */ #define BIT_SHIFT_SDIO_DATA_CRC 0 #define BIT_MASK_SDIO_DATA_CRC 0xffff #define BIT_SDIO_DATA_CRC(x) \ (((x) & BIT_MASK_SDIO_DATA_CRC) << BIT_SHIFT_SDIO_DATA_CRC) #define BITS_SDIO_DATA_CRC (BIT_MASK_SDIO_DATA_CRC << BIT_SHIFT_SDIO_DATA_CRC) #define BIT_CLEAR_SDIO_DATA_CRC(x) ((x) & (~BITS_SDIO_DATA_CRC)) #define BIT_GET_SDIO_DATA_CRC(x) \ (((x) >> BIT_SHIFT_SDIO_DATA_CRC) & BIT_MASK_SDIO_DATA_CRC) #define BIT_SET_SDIO_DATA_CRC(x, v) \ (BIT_CLEAR_SDIO_DATA_CRC(x) | BIT_SDIO_DATA_CRC(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ #define BIT_SHIFT_EFUSE_BURN_GNT 24 #define BIT_MASK_EFUSE_BURN_GNT 0xff #define BIT_EFUSE_BURN_GNT(x) \ (((x) & BIT_MASK_EFUSE_BURN_GNT) << BIT_SHIFT_EFUSE_BURN_GNT) #define BITS_EFUSE_BURN_GNT \ (BIT_MASK_EFUSE_BURN_GNT << BIT_SHIFT_EFUSE_BURN_GNT) #define BIT_CLEAR_EFUSE_BURN_GNT(x) ((x) & (~BITS_EFUSE_BURN_GNT)) #define BIT_GET_EFUSE_BURN_GNT(x) \ (((x) >> BIT_SHIFT_EFUSE_BURN_GNT) & BIT_MASK_EFUSE_BURN_GNT) #define BIT_SET_EFUSE_BURN_GNT(x, v) \ (BIT_CLEAR_EFUSE_BURN_GNT(x) | BIT_EFUSE_BURN_GNT(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ #define BIT_SHIFT_EFUSE_PG_PWD 24 #define BIT_MASK_EFUSE_PG_PWD 0xff #define BIT_EFUSE_PG_PWD(x) \ (((x) & BIT_MASK_EFUSE_PG_PWD) << BIT_SHIFT_EFUSE_PG_PWD) #define BITS_EFUSE_PG_PWD (BIT_MASK_EFUSE_PG_PWD << BIT_SHIFT_EFUSE_PG_PWD) #define BIT_CLEAR_EFUSE_PG_PWD(x) ((x) & (~BITS_EFUSE_PG_PWD)) #define BIT_GET_EFUSE_PG_PWD(x) \ (((x) >> BIT_SHIFT_EFUSE_PG_PWD) & BIT_MASK_EFUSE_PG_PWD) #define BIT_SET_EFUSE_PG_PWD(x, v) \ (BIT_CLEAR_EFUSE_PG_PWD(x) | BIT_EFUSE_PG_PWD(v)) #define BIT_DBG_READ_EN BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ #define BIT_STOP_WL_PMC BIT(9) #define BIT_STOP_SYM_PMC BIT(8) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ #define BIT_SHIFT_EDATA1_V1 8 #define BIT_MASK_EDATA1_V1 0xff #define BIT_EDATA1_V1(x) (((x) & BIT_MASK_EDATA1_V1) << BIT_SHIFT_EDATA1_V1) #define BITS_EDATA1_V1 (BIT_MASK_EDATA1_V1 << BIT_SHIFT_EDATA1_V1) #define BIT_CLEAR_EDATA1_V1(x) ((x) & (~BITS_EDATA1_V1)) #define BIT_GET_EDATA1_V1(x) (((x) >> BIT_SHIFT_EDATA1_V1) & BIT_MASK_EDATA1_V1) #define BIT_SET_EDATA1_V1(x, v) (BIT_CLEAR_EDATA1_V1(x) | BIT_EDATA1_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ #define BIT_BT_ACCESS_WL_PAGE0 BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ #define BIT_REG_RST_WLPMC BIT(5) #define BIT_REG_RST_PD12N BIT(4) #define BIT_SYSON_DIS_WLREG_WRMSK BIT(3) #define BIT_SYSON_DIS_PMCREG_WRMSK BIT(2) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TRANS_FIFO_STATUS (Offset 0x102500CC) */ #define BIT_TRANS_FIFO_UNDERFLOW BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ #define BIT_SHIFT_SYSON_REG_ARB 0 #define BIT_MASK_SYSON_REG_ARB 0x3 #define BIT_SYSON_REG_ARB(x) \ (((x) & BIT_MASK_SYSON_REG_ARB) << BIT_SHIFT_SYSON_REG_ARB) #define BITS_SYSON_REG_ARB (BIT_MASK_SYSON_REG_ARB << BIT_SHIFT_SYSON_REG_ARB) #define BIT_CLEAR_SYSON_REG_ARB(x) ((x) & (~BITS_SYSON_REG_ARB)) #define BIT_GET_SYSON_REG_ARB(x) \ (((x) >> BIT_SHIFT_SYSON_REG_ARB) & BIT_MASK_SYSON_REG_ARB) #define BIT_SET_SYSON_REG_ARB(x, v) \ (BIT_CLEAR_SYSON_REG_ARB(x) | BIT_SYSON_REG_ARB(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ #define BIT_SHIFT_EDATA0_V1 0 #define BIT_MASK_EDATA0_V1 0xff #define BIT_EDATA0_V1(x) (((x) & BIT_MASK_EDATA0_V1) << BIT_SHIFT_EDATA0_V1) #define BITS_EDATA0_V1 (BIT_MASK_EDATA0_V1 << BIT_SHIFT_EDATA0_V1) #define BIT_CLEAR_EDATA0_V1(x) ((x) & (~BITS_EDATA0_V1)) #define BIT_GET_EDATA0_V1(x) (((x) >> BIT_SHIFT_EDATA0_V1) & BIT_MASK_EDATA0_V1) #define BIT_SET_EDATA0_V1(x, v) (BIT_CLEAR_EDATA0_V1(x) | BIT_EDATA0_V1(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TRANS_FIFO_STATUS (Offset 0x102500CC) */ #define BIT_TRANS_FIFO_OVERFLOW BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ #define BIT_LD_RQPN BIT(31) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ #define BIT_SCAN_PLL_BYPASS BIT(30) #define BIT_DRF_BIST_FAIL_V1 BIT(28) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ #define BIT_BIST_USB_DIS BIT(27) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ #define BIT_DRF_BIST_READY_V1 BIT(27) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ #define BIT_BIST_PCI_DIS BIT(26) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ #define BIT_BIST_FAIL_V1 BIT(26) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ #define BIT_BIST_BT_DIS BIT(25) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ #define BIT_BIST_READY_V1 BIT(25) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ #define BIT_BIST_WL_DIS BIT(24) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ #define BIT_BIST_START_PAUSE_V1 BIT(24) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ #define BIT_SHIFT_BIST_RPT_SEL 16 #define BIT_MASK_BIST_RPT_SEL 0xf #define BIT_BIST_RPT_SEL(x) \ (((x) & BIT_MASK_BIST_RPT_SEL) << BIT_SHIFT_BIST_RPT_SEL) #define BITS_BIST_RPT_SEL (BIT_MASK_BIST_RPT_SEL << BIT_SHIFT_BIST_RPT_SEL) #define BIT_CLEAR_BIST_RPT_SEL(x) ((x) & (~BITS_BIST_RPT_SEL)) #define BIT_GET_BIST_RPT_SEL(x) \ (((x) >> BIT_SHIFT_BIST_RPT_SEL) & BIT_MASK_BIST_RPT_SEL) #define BIT_SET_BIST_RPT_SEL(x, v) \ (BIT_CLEAR_BIST_RPT_SEL(x) | BIT_BIST_RPT_SEL(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ #define BIT_SHIFT_MBIST_RSTNI 8 #define BIT_MASK_MBIST_RSTNI 0x3ff #define BIT_MBIST_RSTNI(x) \ (((x) & BIT_MASK_MBIST_RSTNI) << BIT_SHIFT_MBIST_RSTNI) #define BITS_MBIST_RSTNI (BIT_MASK_MBIST_RSTNI << BIT_SHIFT_MBIST_RSTNI) #define BIT_CLEAR_MBIST_RSTNI(x) ((x) & (~BITS_MBIST_RSTNI)) #define BIT_GET_MBIST_RSTNI(x) \ (((x) >> BIT_SHIFT_MBIST_RSTNI) & BIT_MASK_MBIST_RSTNI) #define BIT_SET_MBIST_RSTNI(x, v) \ (BIT_CLEAR_MBIST_RSTNI(x) | BIT_MBIST_RSTNI(v)) #define BIT_BIST_RESUME_PS_V1 BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ #define BIT_BIST_RESUME_PS BIT(4) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ #define BIT_BIST_RESUME_V1 BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ #define BIT_BIST_RESUME BIT(3) #define BIT_BIST_NORMAL BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ #define BIT_SHIFT_BIST_MODE 2 #define BIT_MASK_BIST_MODE 0x3 #define BIT_BIST_MODE(x) (((x) & BIT_MASK_BIST_MODE) << BIT_SHIFT_BIST_MODE) #define BITS_BIST_MODE (BIT_MASK_BIST_MODE << BIT_SHIFT_BIST_MODE) #define BIT_CLEAR_BIST_MODE(x) ((x) & (~BITS_BIST_MODE)) #define BIT_GET_BIST_MODE(x) (((x) >> BIT_SHIFT_BIST_MODE) & BIT_MASK_BIST_MODE) #define BIT_SET_BIST_MODE(x, v) (BIT_CLEAR_BIST_MODE(x) | BIT_BIST_MODE(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ #define BIT_BIST_RSTN BIT(1) #define BIT_BIST_CLK_EN BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_BIST_RPT (Offset 0x00D4) */ #define BIT_SHIFT_MBIST_REPORT 0 #define BIT_MASK_MBIST_REPORT 0xffffffffL #define BIT_MBIST_REPORT(x) \ (((x) & BIT_MASK_MBIST_REPORT) << BIT_SHIFT_MBIST_REPORT) #define BITS_MBIST_REPORT (BIT_MASK_MBIST_REPORT << BIT_SHIFT_MBIST_REPORT) #define BIT_CLEAR_MBIST_REPORT(x) ((x) & (~BITS_MBIST_REPORT)) #define BIT_GET_MBIST_REPORT(x) \ (((x) >> BIT_SHIFT_MBIST_REPORT) & BIT_MASK_MBIST_REPORT) #define BIT_SET_MBIST_REPORT(x, v) \ (BIT_CLEAR_MBIST_REPORT(x) | BIT_MBIST_REPORT(v)) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ #define BIT_RMV_SIGN BIT(31) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ #define BIT_UMEM_RME BIT(31) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ #define BIT_RMV_2PRF1 BIT(29) #define BIT_RMV_2PRF0 BIT(28) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ #define BIT_SHIFT_BT_SPRAM 28 #define BIT_MASK_BT_SPRAM 0x3 #define BIT_BT_SPRAM(x) (((x) & BIT_MASK_BT_SPRAM) << BIT_SHIFT_BT_SPRAM) #define BITS_BT_SPRAM (BIT_MASK_BT_SPRAM << BIT_SHIFT_BT_SPRAM) #define BIT_CLEAR_BT_SPRAM(x) ((x) & (~BITS_BT_SPRAM)) #define BIT_GET_BT_SPRAM(x) (((x) >> BIT_SHIFT_BT_SPRAM) & BIT_MASK_BT_SPRAM) #define BIT_SET_BT_SPRAM(x, v) (BIT_CLEAR_BT_SPRAM(x) | BIT_BT_SPRAM(v)) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ #define BIT_RMV_1PRF1 BIT(27) #define BIT_RMV_1PRF0 BIT(26) #define BIT_RMV_1PSR BIT(25) #define BIT_RMV_ROM BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ #define BIT_SHIFT_BT_ROM 24 #define BIT_MASK_BT_ROM 0xf #define BIT_BT_ROM(x) (((x) & BIT_MASK_BT_ROM) << BIT_SHIFT_BT_ROM) #define BITS_BT_ROM (BIT_MASK_BT_ROM << BIT_SHIFT_BT_ROM) #define BIT_CLEAR_BT_ROM(x) ((x) & (~BITS_BT_ROM)) #define BIT_GET_BT_ROM(x) (((x) >> BIT_SHIFT_BT_ROM) & BIT_MASK_BT_ROM) #define BIT_SET_BT_ROM(x, v) (BIT_CLEAR_BT_ROM(x) | BIT_BT_ROM(v)) #define BIT_SHIFT_PCI_DPRAM 10 #define BIT_MASK_PCI_DPRAM 0x3 #define BIT_PCI_DPRAM(x) (((x) & BIT_MASK_PCI_DPRAM) << BIT_SHIFT_PCI_DPRAM) #define BITS_PCI_DPRAM (BIT_MASK_PCI_DPRAM << BIT_SHIFT_PCI_DPRAM) #define BIT_CLEAR_PCI_DPRAM(x) ((x) & (~BITS_PCI_DPRAM)) #define BIT_GET_PCI_DPRAM(x) (((x) >> BIT_SHIFT_PCI_DPRAM) & BIT_MASK_PCI_DPRAM) #define BIT_SET_PCI_DPRAM(x, v) (BIT_CLEAR_PCI_DPRAM(x) | BIT_PCI_DPRAM(v)) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ #define BIT_SHIFT_MEM_RME_BT 8 #define BIT_MASK_MEM_RME_BT 0xf #define BIT_MEM_RME_BT(x) (((x) & BIT_MASK_MEM_RME_BT) << BIT_SHIFT_MEM_RME_BT) #define BITS_MEM_RME_BT (BIT_MASK_MEM_RME_BT << BIT_SHIFT_MEM_RME_BT) #define BIT_CLEAR_MEM_RME_BT(x) ((x) & (~BITS_MEM_RME_BT)) #define BIT_GET_MEM_RME_BT(x) \ (((x) >> BIT_SHIFT_MEM_RME_BT) & BIT_MASK_MEM_RME_BT) #define BIT_SET_MEM_RME_BT(x, v) (BIT_CLEAR_MEM_RME_BT(x) | BIT_MEM_RME_BT(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ #define BIT_SHIFT_PCI_SPRAM 8 #define BIT_MASK_PCI_SPRAM 0x3 #define BIT_PCI_SPRAM(x) (((x) & BIT_MASK_PCI_SPRAM) << BIT_SHIFT_PCI_SPRAM) #define BITS_PCI_SPRAM (BIT_MASK_PCI_SPRAM << BIT_SHIFT_PCI_SPRAM) #define BIT_CLEAR_PCI_SPRAM(x) ((x) & (~BITS_PCI_SPRAM)) #define BIT_GET_PCI_SPRAM(x) (((x) >> BIT_SHIFT_PCI_SPRAM) & BIT_MASK_PCI_SPRAM) #define BIT_SET_PCI_SPRAM(x, v) (BIT_CLEAR_PCI_SPRAM(x) | BIT_PCI_SPRAM(v)) #define BIT_SHIFT_USB_SPRAM 6 #define BIT_MASK_USB_SPRAM 0x3 #define BIT_USB_SPRAM(x) (((x) & BIT_MASK_USB_SPRAM) << BIT_SHIFT_USB_SPRAM) #define BITS_USB_SPRAM (BIT_MASK_USB_SPRAM << BIT_SHIFT_USB_SPRAM) #define BIT_CLEAR_USB_SPRAM(x) ((x) & (~BITS_USB_SPRAM)) #define BIT_GET_USB_SPRAM(x) (((x) >> BIT_SHIFT_USB_SPRAM) & BIT_MASK_USB_SPRAM) #define BIT_SET_USB_SPRAM(x, v) (BIT_CLEAR_USB_SPRAM(x) | BIT_USB_SPRAM(v)) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ #define BIT_SHIFT_MEM_RME_WL 4 #define BIT_MASK_MEM_RME_WL 0xf #define BIT_MEM_RME_WL(x) (((x) & BIT_MASK_MEM_RME_WL) << BIT_SHIFT_MEM_RME_WL) #define BITS_MEM_RME_WL (BIT_MASK_MEM_RME_WL << BIT_SHIFT_MEM_RME_WL) #define BIT_CLEAR_MEM_RME_WL(x) ((x) & (~BITS_MEM_RME_WL)) #define BIT_GET_MEM_RME_WL(x) \ (((x) >> BIT_SHIFT_MEM_RME_WL) & BIT_MASK_MEM_RME_WL) #define BIT_SET_MEM_RME_WL(x, v) (BIT_CLEAR_MEM_RME_WL(x) | BIT_MEM_RME_WL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ #define BIT_SHIFT_USB_SPRF 4 #define BIT_MASK_USB_SPRF 0x3 #define BIT_USB_SPRF(x) (((x) & BIT_MASK_USB_SPRF) << BIT_SHIFT_USB_SPRF) #define BITS_USB_SPRF (BIT_MASK_USB_SPRF << BIT_SHIFT_USB_SPRF) #define BIT_CLEAR_USB_SPRF(x) ((x) & (~BITS_USB_SPRF)) #define BIT_GET_USB_SPRF(x) (((x) >> BIT_SHIFT_USB_SPRF) & BIT_MASK_USB_SPRF) #define BIT_SET_USB_SPRF(x, v) (BIT_CLEAR_USB_SPRF(x) | BIT_USB_SPRF(v)) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ #define BIT_SHIFT_MEM_RME_HCI 0 #define BIT_MASK_MEM_RME_HCI 0xf #define BIT_MEM_RME_HCI(x) \ (((x) & BIT_MASK_MEM_RME_HCI) << BIT_SHIFT_MEM_RME_HCI) #define BITS_MEM_RME_HCI (BIT_MASK_MEM_RME_HCI << BIT_SHIFT_MEM_RME_HCI) #define BIT_CLEAR_MEM_RME_HCI(x) ((x) & (~BITS_MEM_RME_HCI)) #define BIT_GET_MEM_RME_HCI(x) \ (((x) >> BIT_SHIFT_MEM_RME_HCI) & BIT_MASK_MEM_RME_HCI) #define BIT_SET_MEM_RME_HCI(x, v) \ (BIT_CLEAR_MEM_RME_HCI(x) | BIT_MEM_RME_HCI(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ #define BIT_SHIFT_MCU_ROM 0 #define BIT_MASK_MCU_ROM 0xf #define BIT_MCU_ROM(x) (((x) & BIT_MASK_MCU_ROM) << BIT_SHIFT_MCU_ROM) #define BITS_MCU_ROM (BIT_MASK_MCU_ROM << BIT_SHIFT_MCU_ROM) #define BIT_CLEAR_MCU_ROM(x) ((x) & (~BITS_MCU_ROM)) #define BIT_GET_MCU_ROM(x) (((x) >> BIT_SHIFT_MCU_ROM) & BIT_MASK_MCU_ROM) #define BIT_SET_MCU_ROM(x, v) (BIT_CLEAR_MCU_ROM(x) | BIT_MCU_ROM(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ #define BIT_SHIFT_BIST_ROM 0 #define BIT_MASK_BIST_ROM 0xffffffffL #define BIT_BIST_ROM(x) (((x) & BIT_MASK_BIST_ROM) << BIT_SHIFT_BIST_ROM) #define BITS_BIST_ROM (BIT_MASK_BIST_ROM << BIT_SHIFT_BIST_ROM) #define BIT_CLEAR_BIST_ROM(x) ((x) & (~BITS_BIST_ROM)) #define BIT_GET_BIST_ROM(x) (((x) >> BIT_SHIFT_BIST_ROM) & BIT_MASK_BIST_ROM) #define BIT_SET_BIST_ROM(x, v) (BIT_CLEAR_BIST_ROM(x) | BIT_BIST_ROM(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ #define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4 26 #define BIT_MASK_BB_DBG_SEL_AFE_SDM_V4 0x7 #define BIT_BB_DBG_SEL_AFE_SDM_V4(x) \ (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4) \ << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4) #define BITS_BB_DBG_SEL_AFE_SDM_V4 \ (BIT_MASK_BB_DBG_SEL_AFE_SDM_V4 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4) #define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4(x) ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_V4)) #define BIT_GET_BB_DBG_SEL_AFE_SDM_V4(x) \ (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4) & \ BIT_MASK_BB_DBG_SEL_AFE_SDM_V4) #define BIT_SET_BB_DBG_SEL_AFE_SDM_V4(x, v) \ (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4(x) | BIT_BB_DBG_SEL_AFE_SDM_V4(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ #define BIT_SYN_AGPIO BIT(20) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SYN_RFC_CTRL (Offset 0x00DC) */ #define BIT_SHIFT_SYN_RF1_CTRL 8 #define BIT_MASK_SYN_RF1_CTRL 0xff #define BIT_SYN_RF1_CTRL(x) \ (((x) & BIT_MASK_SYN_RF1_CTRL) << BIT_SHIFT_SYN_RF1_CTRL) #define BITS_SYN_RF1_CTRL (BIT_MASK_SYN_RF1_CTRL << BIT_SHIFT_SYN_RF1_CTRL) #define BIT_CLEAR_SYN_RF1_CTRL(x) ((x) & (~BITS_SYN_RF1_CTRL)) #define BIT_GET_SYN_RF1_CTRL(x) \ (((x) >> BIT_SHIFT_SYN_RF1_CTRL) & BIT_MASK_SYN_RF1_CTRL) #define BIT_SET_SYN_RF1_CTRL(x, v) \ (BIT_CLEAR_SYN_RF1_CTRL(x) | BIT_SYN_RF1_CTRL(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ #define BIT_XTAL_LP BIT(4) #define BIT_XTAL_GM_SEP BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ #define BIT_SHIFT_XTAL_SEL_TOK_V2 0 #define BIT_MASK_XTAL_SEL_TOK_V2 0x7 #define BIT_XTAL_SEL_TOK_V2(x) \ (((x) & BIT_MASK_XTAL_SEL_TOK_V2) << BIT_SHIFT_XTAL_SEL_TOK_V2) #define BITS_XTAL_SEL_TOK_V2 \ (BIT_MASK_XTAL_SEL_TOK_V2 << BIT_SHIFT_XTAL_SEL_TOK_V2) #define BIT_CLEAR_XTAL_SEL_TOK_V2(x) ((x) & (~BITS_XTAL_SEL_TOK_V2)) #define BIT_GET_XTAL_SEL_TOK_V2(x) \ (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V2) & BIT_MASK_XTAL_SEL_TOK_V2) #define BIT_SET_XTAL_SEL_TOK_V2(x, v) \ (BIT_CLEAR_XTAL_SEL_TOK_V2(x) | BIT_XTAL_SEL_TOK_V2(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WLAN_DBG (Offset 0x00DC) */ #define BIT_SHIFT_WLAN_DBG 0 #define BIT_MASK_WLAN_DBG 0xffffffffL #define BIT_WLAN_DBG(x) (((x) & BIT_MASK_WLAN_DBG) << BIT_SHIFT_WLAN_DBG) #define BITS_WLAN_DBG (BIT_MASK_WLAN_DBG << BIT_SHIFT_WLAN_DBG) #define BIT_CLEAR_WLAN_DBG(x) ((x) & (~BITS_WLAN_DBG)) #define BIT_GET_WLAN_DBG(x) (((x) >> BIT_SHIFT_WLAN_DBG) & BIT_MASK_WLAN_DBG) #define BIT_SET_WLAN_DBG(x, v) (BIT_CLEAR_WLAN_DBG(x) | BIT_WLAN_DBG(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SYN_RFC_CTRL (Offset 0x00DC) */ #define BIT_SHIFT_SYN_RF0_CTRL 0 #define BIT_MASK_SYN_RF0_CTRL 0xff #define BIT_SYN_RF0_CTRL(x) \ (((x) & BIT_MASK_SYN_RF0_CTRL) << BIT_SHIFT_SYN_RF0_CTRL) #define BITS_SYN_RF0_CTRL (BIT_MASK_SYN_RF0_CTRL << BIT_SHIFT_SYN_RF0_CTRL) #define BIT_CLEAR_SYN_RF0_CTRL(x) ((x) & (~BITS_SYN_RF0_CTRL)) #define BIT_GET_SYN_RF0_CTRL(x) \ (((x) >> BIT_SHIFT_SYN_RF0_CTRL) & BIT_MASK_SYN_RF0_CTRL) #define BIT_SET_SYN_RF0_CTRL(x, v) \ (BIT_CLEAR_SYN_RF0_CTRL(x) | BIT_SYN_RF0_CTRL(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ #define BIT_SHIFT_XTAL_SEL_TOK 0 #define BIT_MASK_XTAL_SEL_TOK 0x7 #define BIT_XTAL_SEL_TOK(x) \ (((x) & BIT_MASK_XTAL_SEL_TOK) << BIT_SHIFT_XTAL_SEL_TOK) #define BITS_XTAL_SEL_TOK (BIT_MASK_XTAL_SEL_TOK << BIT_SHIFT_XTAL_SEL_TOK) #define BIT_CLEAR_XTAL_SEL_TOK(x) ((x) & (~BITS_XTAL_SEL_TOK)) #define BIT_GET_XTAL_SEL_TOK(x) \ (((x) >> BIT_SHIFT_XTAL_SEL_TOK) & BIT_MASK_XTAL_SEL_TOK) #define BIT_SET_XTAL_SEL_TOK(x, v) \ (BIT_CLEAR_XTAL_SEL_TOK(x) | BIT_XTAL_SEL_TOK(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ #define BIT_RD_SEL BIT(31) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ #define BIT_CPU_REG_SEL BIT(31) #define BIT_USB3_REG_SEL BIT(30) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ #define BIT_USB_SIE_INTF_WE_V1 BIT(30) #define BIT_USB_SIE_INTF_BYIOREG_V1 BIT(29) #define BIT_USB_SIE_SELECT BIT(28) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ #define BIT_USB_SIE_INTF_WE BIT(25) #define BIT_USB_SIE_INTF_BYIOREG BIT(24) #define BIT_SHIFT_USB_SIE_INTF_ADDR 16 #define BIT_MASK_USB_SIE_INTF_ADDR 0xff #define BIT_USB_SIE_INTF_ADDR(x) \ (((x) & BIT_MASK_USB_SIE_INTF_ADDR) << BIT_SHIFT_USB_SIE_INTF_ADDR) #define BITS_USB_SIE_INTF_ADDR \ (BIT_MASK_USB_SIE_INTF_ADDR << BIT_SHIFT_USB_SIE_INTF_ADDR) #define BIT_CLEAR_USB_SIE_INTF_ADDR(x) ((x) & (~BITS_USB_SIE_INTF_ADDR)) #define BIT_GET_USB_SIE_INTF_ADDR(x) \ (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR) & BIT_MASK_USB_SIE_INTF_ADDR) #define BIT_SET_USB_SIE_INTF_ADDR(x, v) \ (BIT_CLEAR_USB_SIE_INTF_ADDR(x) | BIT_USB_SIE_INTF_ADDR(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ #define BIT_SHIFT_USB_SIE_INTF_ADDR_V1 16 #define BIT_MASK_USB_SIE_INTF_ADDR_V1 0x1ff #define BIT_USB_SIE_INTF_ADDR_V1(x) \ (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1) \ << BIT_SHIFT_USB_SIE_INTF_ADDR_V1) #define BITS_USB_SIE_INTF_ADDR_V1 \ (BIT_MASK_USB_SIE_INTF_ADDR_V1 << BIT_SHIFT_USB_SIE_INTF_ADDR_V1) #define BIT_CLEAR_USB_SIE_INTF_ADDR_V1(x) ((x) & (~BITS_USB_SIE_INTF_ADDR_V1)) #define BIT_GET_USB_SIE_INTF_ADDR_V1(x) \ (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1) & \ BIT_MASK_USB_SIE_INTF_ADDR_V1) #define BIT_SET_USB_SIE_INTF_ADDR_V1(x, v) \ (BIT_CLEAR_USB_SIE_INTF_ADDR_V1(x) | BIT_USB_SIE_INTF_ADDR_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ #define BIT_SHIFT_USB_SIE_INTF_RD 8 #define BIT_MASK_USB_SIE_INTF_RD 0xff #define BIT_USB_SIE_INTF_RD(x) \ (((x) & BIT_MASK_USB_SIE_INTF_RD) << BIT_SHIFT_USB_SIE_INTF_RD) #define BITS_USB_SIE_INTF_RD \ (BIT_MASK_USB_SIE_INTF_RD << BIT_SHIFT_USB_SIE_INTF_RD) #define BIT_CLEAR_USB_SIE_INTF_RD(x) ((x) & (~BITS_USB_SIE_INTF_RD)) #define BIT_GET_USB_SIE_INTF_RD(x) \ (((x) >> BIT_SHIFT_USB_SIE_INTF_RD) & BIT_MASK_USB_SIE_INTF_RD) #define BIT_SET_USB_SIE_INTF_RD(x, v) \ (BIT_CLEAR_USB_SIE_INTF_RD(x) | BIT_USB_SIE_INTF_RD(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ #define BIT_SHIFT_NPQ_AVAL_PG 8 #define BIT_MASK_NPQ_AVAL_PG 0xff #define BIT_NPQ_AVAL_PG(x) \ (((x) & BIT_MASK_NPQ_AVAL_PG) << BIT_SHIFT_NPQ_AVAL_PG) #define BITS_NPQ_AVAL_PG (BIT_MASK_NPQ_AVAL_PG << BIT_SHIFT_NPQ_AVAL_PG) #define BIT_CLEAR_NPQ_AVAL_PG(x) ((x) & (~BITS_NPQ_AVAL_PG)) #define BIT_GET_NPQ_AVAL_PG(x) \ (((x) >> BIT_SHIFT_NPQ_AVAL_PG) & BIT_MASK_NPQ_AVAL_PG) #define BIT_SET_NPQ_AVAL_PG(x, v) \ (BIT_CLEAR_NPQ_AVAL_PG(x) | BIT_NPQ_AVAL_PG(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ #define BIT_SHIFT_USB_SIE_INTF_WD 0 #define BIT_MASK_USB_SIE_INTF_WD 0xff #define BIT_USB_SIE_INTF_WD(x) \ (((x) & BIT_MASK_USB_SIE_INTF_WD) << BIT_SHIFT_USB_SIE_INTF_WD) #define BITS_USB_SIE_INTF_WD \ (BIT_MASK_USB_SIE_INTF_WD << BIT_SHIFT_USB_SIE_INTF_WD) #define BIT_CLEAR_USB_SIE_INTF_WD(x) ((x) & (~BITS_USB_SIE_INTF_WD)) #define BIT_GET_USB_SIE_INTF_WD(x) \ (((x) >> BIT_SHIFT_USB_SIE_INTF_WD) & BIT_MASK_USB_SIE_INTF_WD) #define BIT_SET_USB_SIE_INTF_WD(x, v) \ (BIT_CLEAR_USB_SIE_INTF_WD(x) | BIT_USB_SIE_INTF_WD(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ #define BIT_PCIE_MIO_EXIT_L1 BIT(19) #define BIT_PCIE_MIO_EXT BIT(18) #define BIT_PCIE_MIO_ACK BIT(17) #define BIT_PCIE_MIO_IOREG BIT(16) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ #define BIT_SHIFT_PCIE_MIO_ADDR_PAGE 16 #define BIT_MASK_PCIE_MIO_ADDR_PAGE 0x3 #define BIT_PCIE_MIO_ADDR_PAGE(x) \ (((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE) << BIT_SHIFT_PCIE_MIO_ADDR_PAGE) #define BITS_PCIE_MIO_ADDR_PAGE \ (BIT_MASK_PCIE_MIO_ADDR_PAGE << BIT_SHIFT_PCIE_MIO_ADDR_PAGE) #define BIT_CLEAR_PCIE_MIO_ADDR_PAGE(x) ((x) & (~BITS_PCIE_MIO_ADDR_PAGE)) #define BIT_GET_PCIE_MIO_ADDR_PAGE(x) \ (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE) & BIT_MASK_PCIE_MIO_ADDR_PAGE) #define BIT_SET_PCIE_MIO_ADDR_PAGE(x, v) \ (BIT_CLEAR_PCIE_MIO_ADDR_PAGE(x) | BIT_PCIE_MIO_ADDR_PAGE(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ #define BIT_PCIE_MIO_BYIOREG BIT(13) #define BIT_PCIE_MIO_RE BIT(12) #define BIT_SHIFT_PCIE_MIO_WE 8 #define BIT_MASK_PCIE_MIO_WE 0xf #define BIT_PCIE_MIO_WE(x) \ (((x) & BIT_MASK_PCIE_MIO_WE) << BIT_SHIFT_PCIE_MIO_WE) #define BITS_PCIE_MIO_WE (BIT_MASK_PCIE_MIO_WE << BIT_SHIFT_PCIE_MIO_WE) #define BIT_CLEAR_PCIE_MIO_WE(x) ((x) & (~BITS_PCIE_MIO_WE)) #define BIT_GET_PCIE_MIO_WE(x) \ (((x) >> BIT_SHIFT_PCIE_MIO_WE) & BIT_MASK_PCIE_MIO_WE) #define BIT_SET_PCIE_MIO_WE(x, v) \ (BIT_CLEAR_PCIE_MIO_WE(x) | BIT_PCIE_MIO_WE(v)) #define BIT_SHIFT_PCIE_MIO_ADDR 0 #define BIT_MASK_PCIE_MIO_ADDR 0xff #define BIT_PCIE_MIO_ADDR(x) \ (((x) & BIT_MASK_PCIE_MIO_ADDR) << BIT_SHIFT_PCIE_MIO_ADDR) #define BITS_PCIE_MIO_ADDR (BIT_MASK_PCIE_MIO_ADDR << BIT_SHIFT_PCIE_MIO_ADDR) #define BIT_CLEAR_PCIE_MIO_ADDR(x) ((x) & (~BITS_PCIE_MIO_ADDR)) #define BIT_GET_PCIE_MIO_ADDR(x) \ (((x) >> BIT_SHIFT_PCIE_MIO_ADDR) & BIT_MASK_PCIE_MIO_ADDR) #define BIT_SET_PCIE_MIO_ADDR(x, v) \ (BIT_CLEAR_PCIE_MIO_ADDR(x) | BIT_PCIE_MIO_ADDR(v)) /* 2 REG_PCIE_MIO_INTD (Offset 0x00E8) */ #define BIT_SHIFT_PCIE_MIO_DATA 0 #define BIT_MASK_PCIE_MIO_DATA 0xffffffffL #define BIT_PCIE_MIO_DATA(x) \ (((x) & BIT_MASK_PCIE_MIO_DATA) << BIT_SHIFT_PCIE_MIO_DATA) #define BITS_PCIE_MIO_DATA (BIT_MASK_PCIE_MIO_DATA << BIT_SHIFT_PCIE_MIO_DATA) #define BIT_CLEAR_PCIE_MIO_DATA(x) ((x) & (~BITS_PCIE_MIO_DATA)) #define BIT_GET_PCIE_MIO_DATA(x) \ (((x) >> BIT_SHIFT_PCIE_MIO_DATA) & BIT_MASK_PCIE_MIO_DATA) #define BIT_SET_PCIE_MIO_DATA(x, v) \ (BIT_CLEAR_PCIE_MIO_DATA(x) | BIT_PCIE_MIO_DATA(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HPON_FSM (Offset 0x00EC) */ #define BIT_SUSPEND_V1 BIT(31) #define BIT_FSM_RESUME_V1 BIT(30) #define BIT_HOST_RESUME_SYNC_V1 BIT(29) #define BIT_CHIP_PDNB_V1 BIT(28) #define BIT_SHIFT_FSM_SUSPEND_V1 25 #define BIT_MASK_FSM_SUSPEND_V1 0x7 #define BIT_FSM_SUSPEND_V1(x) \ (((x) & BIT_MASK_FSM_SUSPEND_V1) << BIT_SHIFT_FSM_SUSPEND_V1) #define BITS_FSM_SUSPEND_V1 \ (BIT_MASK_FSM_SUSPEND_V1 << BIT_SHIFT_FSM_SUSPEND_V1) #define BIT_CLEAR_FSM_SUSPEND_V1(x) ((x) & (~BITS_FSM_SUSPEND_V1)) #define BIT_GET_FSM_SUSPEND_V1(x) \ (((x) >> BIT_SHIFT_FSM_SUSPEND_V1) & BIT_MASK_FSM_SUSPEND_V1) #define BIT_SET_FSM_SUSPEND_V1(x, v) \ (BIT_CLEAR_FSM_SUSPEND_V1(x) | BIT_FSM_SUSPEND_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_WLRF1 (Offset 0x00EC) */ #define BIT_SHIFT_XTAL_SEL 25 #define BIT_MASK_XTAL_SEL 0x3 #define BIT_XTAL_SEL(x) (((x) & BIT_MASK_XTAL_SEL) << BIT_SHIFT_XTAL_SEL) #define BITS_XTAL_SEL (BIT_MASK_XTAL_SEL << BIT_SHIFT_XTAL_SEL) #define BIT_CLEAR_XTAL_SEL(x) ((x) & (~BITS_XTAL_SEL)) #define BIT_GET_XTAL_SEL(x) (((x) >> BIT_SHIFT_XTAL_SEL) & BIT_MASK_XTAL_SEL) #define BIT_SET_XTAL_SEL(x, v) (BIT_CLEAR_XTAL_SEL(x) | BIT_XTAL_SEL(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HPON_FSM (Offset 0x00EC) */ #define BIT_PMC_ALD_V1 BIT(24) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_WLRF1 (Offset 0x00EC) */ #define BIT_SHIFT_WLRF1_CTRL 24 #define BIT_MASK_WLRF1_CTRL 0xff #define BIT_WLRF1_CTRL(x) (((x) & BIT_MASK_WLRF1_CTRL) << BIT_SHIFT_WLRF1_CTRL) #define BITS_WLRF1_CTRL (BIT_MASK_WLRF1_CTRL << BIT_SHIFT_WLRF1_CTRL) #define BIT_CLEAR_WLRF1_CTRL(x) ((x) & (~BITS_WLRF1_CTRL)) #define BIT_GET_WLRF1_CTRL(x) \ (((x) >> BIT_SHIFT_WLRF1_CTRL) & BIT_MASK_WLRF1_CTRL) #define BIT_SET_WLRF1_CTRL(x, v) (BIT_CLEAR_WLRF1_CTRL(x) | BIT_WLRF1_CTRL(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HPON_FSM (Offset 0x00EC) */ #define BIT_SHIFT_HCI_SEL_1 22 #define BIT_MASK_HCI_SEL_1 0x3 #define BIT_HCI_SEL_1(x) (((x) & BIT_MASK_HCI_SEL_1) << BIT_SHIFT_HCI_SEL_1) #define BITS_HCI_SEL_1 (BIT_MASK_HCI_SEL_1 << BIT_SHIFT_HCI_SEL_1) #define BIT_CLEAR_HCI_SEL_1(x) ((x) & (~BITS_HCI_SEL_1)) #define BIT_GET_HCI_SEL_1(x) (((x) >> BIT_SHIFT_HCI_SEL_1) & BIT_MASK_HCI_SEL_1) #define BIT_SET_HCI_SEL_1(x, v) (BIT_CLEAR_HCI_SEL_1(x) | BIT_HCI_SEL_1(v)) #define BIT_LOAD_DONE_V1 BIT(21) #define BIT_CNT_MATCH BIT(20) #define BIT_TIMEUP_V1 BIT(19) #define BIT_SPS_12V_VLD BIT(18) #define BIT_PCIERST_V1 BIT(17) #define BIT_HOST_CLK_VLD BIT(16) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_WLRF1 (Offset 0x00EC) */ #define BIT_SHIFT_WLRF2_CTRL 16 #define BIT_MASK_WLRF2_CTRL 0xff #define BIT_WLRF2_CTRL(x) (((x) & BIT_MASK_WLRF2_CTRL) << BIT_SHIFT_WLRF2_CTRL) #define BITS_WLRF2_CTRL (BIT_MASK_WLRF2_CTRL << BIT_SHIFT_WLRF2_CTRL) #define BIT_CLEAR_WLRF2_CTRL(x) ((x) & (~BITS_WLRF2_CTRL)) #define BIT_GET_WLRF2_CTRL(x) \ (((x) >> BIT_SHIFT_WLRF2_CTRL) & BIT_MASK_WLRF2_CTRL) #define BIT_SET_WLRF2_CTRL(x, v) (BIT_CLEAR_WLRF2_CTRL(x) | BIT_WLRF2_CTRL(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HPON_FSM (Offset 0x00EC) */ #define BIT_PMC_WR_V1 BIT(15) #define BIT_PMC_DATA_V1 BIT(14) #define BIT_SHIFT_PMC_ADDR_V1 8 #define BIT_MASK_PMC_ADDR_V1 0x3f #define BIT_PMC_ADDR_V1(x) \ (((x) & BIT_MASK_PMC_ADDR_V1) << BIT_SHIFT_PMC_ADDR_V1) #define BITS_PMC_ADDR_V1 (BIT_MASK_PMC_ADDR_V1 << BIT_SHIFT_PMC_ADDR_V1) #define BIT_CLEAR_PMC_ADDR_V1(x) ((x) & (~BITS_PMC_ADDR_V1)) #define BIT_GET_PMC_ADDR_V1(x) \ (((x) >> BIT_SHIFT_PMC_ADDR_V1) & BIT_MASK_PMC_ADDR_V1) #define BIT_SET_PMC_ADDR_V1(x, v) \ (BIT_CLEAR_PMC_ADDR_V1(x) | BIT_PMC_ADDR_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_WLRF1 (Offset 0x00EC) */ #define BIT_SHIFT_WLRF3_CTRL 8 #define BIT_MASK_WLRF3_CTRL 0xff #define BIT_WLRF3_CTRL(x) (((x) & BIT_MASK_WLRF3_CTRL) << BIT_SHIFT_WLRF3_CTRL) #define BITS_WLRF3_CTRL (BIT_MASK_WLRF3_CTRL << BIT_SHIFT_WLRF3_CTRL) #define BIT_CLEAR_WLRF3_CTRL(x) ((x) & (~BITS_WLRF3_CTRL)) #define BIT_GET_WLRF3_CTRL(x) \ (((x) >> BIT_SHIFT_WLRF3_CTRL) & BIT_MASK_WLRF3_CTRL) #define BIT_SET_WLRF3_CTRL(x, v) (BIT_CLEAR_WLRF3_CTRL(x) | BIT_WLRF3_CTRL(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HPON_FSM (Offset 0x00EC) */ #define BIT_PMC_COUNT_EN_V1 BIT(7) #define BIT_SHIFT_FSM_STATE_V1 0 #define BIT_MASK_FSM_STATE_V1 0x7f #define BIT_FSM_STATE_V1(x) \ (((x) & BIT_MASK_FSM_STATE_V1) << BIT_SHIFT_FSM_STATE_V1) #define BITS_FSM_STATE_V1 (BIT_MASK_FSM_STATE_V1 << BIT_SHIFT_FSM_STATE_V1) #define BIT_CLEAR_FSM_STATE_V1(x) ((x) & (~BITS_FSM_STATE_V1)) #define BIT_GET_FSM_STATE_V1(x) \ (((x) >> BIT_SHIFT_FSM_STATE_V1) & BIT_MASK_FSM_STATE_V1) #define BIT_SET_FSM_STATE_V1(x, v) \ (BIT_CLEAR_FSM_STATE_V1(x) | BIT_FSM_STATE_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_SHIFT_TRP_ICFG 28 #define BIT_MASK_TRP_ICFG 0xf #define BIT_TRP_ICFG(x) (((x) & BIT_MASK_TRP_ICFG) << BIT_SHIFT_TRP_ICFG) #define BITS_TRP_ICFG (BIT_MASK_TRP_ICFG << BIT_SHIFT_TRP_ICFG) #define BIT_CLEAR_TRP_ICFG(x) ((x) & (~BITS_TRP_ICFG)) #define BIT_GET_TRP_ICFG(x) (((x) >> BIT_SHIFT_TRP_ICFG) & BIT_MASK_TRP_ICFG) #define BIT_SET_TRP_ICFG(x, v) (BIT_CLEAR_TRP_ICFG(x) | BIT_TRP_ICFG(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_RF_TYPE_ID BIT(27) #define BIT_BD_HCI_SEL BIT(26) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_SHIFT_BD_HCI_SEL_V1 26 #define BIT_MASK_BD_HCI_SEL_V1 0x3 #define BIT_BD_HCI_SEL_V1(x) \ (((x) & BIT_MASK_BD_HCI_SEL_V1) << BIT_SHIFT_BD_HCI_SEL_V1) #define BITS_BD_HCI_SEL_V1 (BIT_MASK_BD_HCI_SEL_V1 << BIT_SHIFT_BD_HCI_SEL_V1) #define BIT_CLEAR_BD_HCI_SEL_V1(x) ((x) & (~BITS_BD_HCI_SEL_V1)) #define BIT_GET_BD_HCI_SEL_V1(x) \ (((x) >> BIT_SHIFT_BD_HCI_SEL_V1) & BIT_MASK_BD_HCI_SEL_V1) #define BIT_SET_BD_HCI_SEL_V1(x, v) \ (BIT_CLEAR_BD_HCI_SEL_V1(x) | BIT_BD_HCI_SEL_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_BD_PKG_SEL BIT(25) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_SPSLDO_SEL BIT(24) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_LDO_SPS_SEL BIT(24) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_INTERNAL_EXTERNAL_SWR BIT(24) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_RTL_ID BIT(23) #define BIT_PAD_HWPD_IDN BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_TESTMODE BIT(20) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_SHIFT_PSC_TESTCFG 20 #define BIT_MASK_PSC_TESTCFG 0x3 #define BIT_PSC_TESTCFG(x) \ (((x) & BIT_MASK_PSC_TESTCFG) << BIT_SHIFT_PSC_TESTCFG) #define BITS_PSC_TESTCFG (BIT_MASK_PSC_TESTCFG << BIT_SHIFT_PSC_TESTCFG) #define BIT_CLEAR_PSC_TESTCFG(x) ((x) & (~BITS_PSC_TESTCFG)) #define BIT_GET_PSC_TESTCFG(x) \ (((x) >> BIT_SHIFT_PSC_TESTCFG) & BIT_MASK_PSC_TESTCFG) #define BIT_SET_PSC_TESTCFG(x, v) \ (BIT_CLEAR_PSC_TESTCFG(x) | BIT_PSC_TESTCFG(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_SHIFT_VENDOR_ID 16 #define BIT_MASK_VENDOR_ID 0xf #define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID) #define BITS_VENDOR_ID (BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID) #define BIT_CLEAR_VENDOR_ID(x) ((x) & (~BITS_VENDOR_ID)) #define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID) #define BIT_SET_VENDOR_ID(x, v) (BIT_CLEAR_VENDOR_ID(x) | BIT_VENDOR_ID(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_SHIFT_CHIP_VER_V2 16 #define BIT_MASK_CHIP_VER_V2 0xf #define BIT_CHIP_VER_V2(x) \ (((x) & BIT_MASK_CHIP_VER_V2) << BIT_SHIFT_CHIP_VER_V2) #define BITS_CHIP_VER_V2 (BIT_MASK_CHIP_VER_V2 << BIT_SHIFT_CHIP_VER_V2) #define BIT_CLEAR_CHIP_VER_V2(x) ((x) & (~BITS_CHIP_VER_V2)) #define BIT_GET_CHIP_VER_V2(x) \ (((x) >> BIT_SHIFT_CHIP_VER_V2) & BIT_MASK_CHIP_VER_V2) #define BIT_SET_CHIP_VER_V2(x, v) \ (BIT_CLEAR_CHIP_VER_V2(x) | BIT_CHIP_VER_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_SHIFT_CHIP_VER 12 #define BIT_MASK_CHIP_VER 0xf #define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER) #define BITS_CHIP_VER (BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER) #define BIT_CLEAR_CHIP_VER(x) ((x) & (~BITS_CHIP_VER)) #define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER) #define BIT_SET_CHIP_VER(x, v) (BIT_CLEAR_CHIP_VER(x) | BIT_CHIP_VER(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_IC_MACPHY_MODE BIT(11) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_BD_MAC3 BIT(11) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_BD_MAC1 BIT(10) #define BIT_BD_MAC2 BIT(9) #define BIT_SIC_IDLE BIT(8) #define BIT_SW_OFFLOAD_EN BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_OCP_SHUTDN BIT(6) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_OCP_SHUTDN_1 BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_V15_VLD BIT(5) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_V12_VLD BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_PCIRSTB BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_PCLK_VLD BIT(3) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_PCLK_VLD_1 BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_UCLK_VLD BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_ACLK_VLD BIT(1) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_M200CLK_VLD_V1 BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ #define BIT_XCLK_VLD BIT(0) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_SHIFT_RF_RL_ID 28 #define BIT_MASK_RF_RL_ID 0xf #define BIT_RF_RL_ID(x) (((x) & BIT_MASK_RF_RL_ID) << BIT_SHIFT_RF_RL_ID) #define BITS_RF_RL_ID (BIT_MASK_RF_RL_ID << BIT_SHIFT_RF_RL_ID) #define BIT_CLEAR_RF_RL_ID(x) ((x) & (~BITS_RF_RL_ID)) #define BIT_GET_RF_RL_ID(x) (((x) >> BIT_SHIFT_RF_RL_ID) & BIT_MASK_RF_RL_ID) #define BIT_SET_RF_RL_ID(x, v) (BIT_CLEAR_RF_RL_ID(x) | BIT_RF_RL_ID(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_U3_CLK_VLD BIT(27) #define BIT_PRST_VLD_V1 BIT(26) #define BIT_PDN BIT(25) #define BIT_OCP_SHUTDN_V1 BIT(24) #define BIT_PCLK_VLD_V1 BIT(23) #define BIT_U2_CLK_VLD BIT(22) #define BIT_PLL_CLK_VLD BIT(21) #define BIT_XCK_VLD BIT(20) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_HPHY_ICFG BIT(19) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_CK200M_VLD BIT(19) #define BIT_BTEN_TRAP BIT(18) #define BIT_PKG_EN_V1 BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_SHIFT_SEL_0XC0 16 #define BIT_MASK_SEL_0XC0 0x3 #define BIT_SEL_0XC0(x) (((x) & BIT_MASK_SEL_0XC0) << BIT_SHIFT_SEL_0XC0) #define BITS_SEL_0XC0 (BIT_MASK_SEL_0XC0 << BIT_SHIFT_SEL_0XC0) #define BIT_CLEAR_SEL_0XC0(x) ((x) & (~BITS_SEL_0XC0)) #define BIT_GET_SEL_0XC0(x) (((x) >> BIT_SHIFT_SEL_0XC0) & BIT_MASK_SEL_0XC0) #define BIT_SET_SEL_0XC0(x, v) (BIT_CLEAR_SEL_0XC0(x) | BIT_SEL_0XC0(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_TRAP_LDO_SPS_V1 BIT(16) #define BIT_MACRDY BIT(15) #define BIT_12V_VLD BIT(14) #define BIT_U3PHY_RST BIT(13) #define BIT_USB2_SEL_V1 BIT(12) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_SHIFT_HCI_SEL_V4 12 #define BIT_MASK_HCI_SEL_V4 0x3 #define BIT_HCI_SEL_V4(x) (((x) & BIT_MASK_HCI_SEL_V4) << BIT_SHIFT_HCI_SEL_V4) #define BITS_HCI_SEL_V4 (BIT_MASK_HCI_SEL_V4 << BIT_SHIFT_HCI_SEL_V4) #define BIT_CLEAR_HCI_SEL_V4(x) ((x) & (~BITS_HCI_SEL_V4)) #define BIT_GET_HCI_SEL_V4(x) \ (((x) >> BIT_SHIFT_HCI_SEL_V4) & BIT_MASK_HCI_SEL_V4) #define BIT_SET_HCI_SEL_V4(x, v) (BIT_CLEAR_HCI_SEL_V4(x) | BIT_HCI_SEL_V4(v)) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_SHIFT_HCI_SEL_V3 12 #define BIT_MASK_HCI_SEL_V3 0x7 #define BIT_HCI_SEL_V3(x) (((x) & BIT_MASK_HCI_SEL_V3) << BIT_SHIFT_HCI_SEL_V3) #define BITS_HCI_SEL_V3 (BIT_MASK_HCI_SEL_V3 << BIT_SHIFT_HCI_SEL_V3) #define BIT_CLEAR_HCI_SEL_V3(x) ((x) & (~BITS_HCI_SEL_V3)) #define BIT_GET_HCI_SEL_V3(x) \ (((x) >> BIT_SHIFT_HCI_SEL_V3) & BIT_MASK_HCI_SEL_V3) #define BIT_SET_HCI_SEL_V3(x, v) (BIT_CLEAR_HCI_SEL_V3(x) | BIT_HCI_SEL_V3(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_USB_OPERATION_MODE BIT(10) #define BIT_BT_PDN BIT(9) #define BIT_AUTO_WLPON BIT(8) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_SHIFT_TRAP_ICFG 8 #define BIT_MASK_TRAP_ICFG 0xf #define BIT_TRAP_ICFG(x) (((x) & BIT_MASK_TRAP_ICFG) << BIT_SHIFT_TRAP_ICFG) #define BITS_TRAP_ICFG (BIT_MASK_TRAP_ICFG << BIT_SHIFT_TRAP_ICFG) #define BIT_CLEAR_TRAP_ICFG(x) ((x) & (~BITS_TRAP_ICFG)) #define BIT_GET_TRAP_ICFG(x) (((x) >> BIT_SHIFT_TRAP_ICFG) & BIT_MASK_TRAP_ICFG) #define BIT_SET_TRAP_ICFG(x, v) (BIT_CLEAR_TRAP_ICFG(x) | BIT_TRAP_ICFG(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_WL_MODE BIT(7) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_WLAN_ID BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_PKG_SEL_HCI BIT(6) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_ALDN BIT(6) #define BIT_BTCOEX_CMDEN BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_SHIFT_HCI_SEL 4 #define BIT_MASK_HCI_SEL 0x3 #define BIT_HCI_SEL(x) (((x) & BIT_MASK_HCI_SEL) << BIT_SHIFT_HCI_SEL) #define BITS_HCI_SEL (BIT_MASK_HCI_SEL << BIT_SHIFT_HCI_SEL) #define BIT_CLEAR_HCI_SEL(x) ((x) & (~BITS_HCI_SEL)) #define BIT_GET_HCI_SEL(x) (((x) >> BIT_SHIFT_HCI_SEL) & BIT_MASK_HCI_SEL) #define BIT_SET_HCI_SEL(x, v) (BIT_CLEAR_HCI_SEL(x) | BIT_HCI_SEL(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_BT_EN BIT(4) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_SHIFT_PAD_HCI_SEL_V2 3 #define BIT_MASK_PAD_HCI_SEL_V2 0x3 #define BIT_PAD_HCI_SEL_V2(x) \ (((x) & BIT_MASK_PAD_HCI_SEL_V2) << BIT_SHIFT_PAD_HCI_SEL_V2) #define BITS_PAD_HCI_SEL_V2 \ (BIT_MASK_PAD_HCI_SEL_V2 << BIT_SHIFT_PAD_HCI_SEL_V2) #define BIT_CLEAR_PAD_HCI_SEL_V2(x) ((x) & (~BITS_PAD_HCI_SEL_V2)) #define BIT_GET_PAD_HCI_SEL_V2(x) \ (((x) >> BIT_SHIFT_PAD_HCI_SEL_V2) & BIT_MASK_PAD_HCI_SEL_V2) #define BIT_SET_PAD_HCI_SEL_V2(x, v) \ (BIT_CLEAR_PAD_HCI_SEL_V2(x) | BIT_PAD_HCI_SEL_V2(v)) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_SHIFT_PAD_HCI_SEL_V1 3 #define BIT_MASK_PAD_HCI_SEL_V1 0x7 #define BIT_PAD_HCI_SEL_V1(x) \ (((x) & BIT_MASK_PAD_HCI_SEL_V1) << BIT_SHIFT_PAD_HCI_SEL_V1) #define BITS_PAD_HCI_SEL_V1 \ (BIT_MASK_PAD_HCI_SEL_V1 << BIT_SHIFT_PAD_HCI_SEL_V1) #define BIT_CLEAR_PAD_HCI_SEL_V1(x) ((x) & (~BITS_PAD_HCI_SEL_V1)) #define BIT_GET_PAD_HCI_SEL_V1(x) \ (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1) & BIT_MASK_PAD_HCI_SEL_V1) #define BIT_SET_PAD_HCI_SEL_V1(x, v) \ (BIT_CLEAR_PAD_HCI_SEL_V1(x) | BIT_PAD_HCI_SEL_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_SHIFT_PAD_HCI_SEL 2 #define BIT_MASK_PAD_HCI_SEL 0x3 #define BIT_PAD_HCI_SEL(x) \ (((x) & BIT_MASK_PAD_HCI_SEL) << BIT_SHIFT_PAD_HCI_SEL) #define BITS_PAD_HCI_SEL (BIT_MASK_PAD_HCI_SEL << BIT_SHIFT_PAD_HCI_SEL) #define BIT_CLEAR_PAD_HCI_SEL(x) ((x) & (~BITS_PAD_HCI_SEL)) #define BIT_GET_PAD_HCI_SEL(x) \ (((x) >> BIT_SHIFT_PAD_HCI_SEL) & BIT_MASK_PAD_HCI_SEL) #define BIT_SET_PAD_HCI_SEL(x, v) \ (BIT_CLEAR_PAD_HCI_SEL(x) | BIT_PAD_HCI_SEL(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_SHIFT_HCI_SEL_V2 2 #define BIT_MASK_HCI_SEL_V2 0x3 #define BIT_HCI_SEL_V2(x) (((x) & BIT_MASK_HCI_SEL_V2) << BIT_SHIFT_HCI_SEL_V2) #define BITS_HCI_SEL_V2 (BIT_MASK_HCI_SEL_V2 << BIT_SHIFT_HCI_SEL_V2) #define BIT_CLEAR_HCI_SEL_V2(x) ((x) & (~BITS_HCI_SEL_V2)) #define BIT_GET_HCI_SEL_V2(x) \ (((x) >> BIT_SHIFT_HCI_SEL_V2) & BIT_MASK_HCI_SEL_V2) #define BIT_SET_HCI_SEL_V2(x, v) (BIT_CLEAR_HCI_SEL_V2(x) | BIT_HCI_SEL_V2(v)) #define BIT_TST_MOD_SEL BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_SHIFT_EFS_HCI_SEL 0 #define BIT_MASK_EFS_HCI_SEL 0x3 #define BIT_EFS_HCI_SEL(x) \ (((x) & BIT_MASK_EFS_HCI_SEL) << BIT_SHIFT_EFS_HCI_SEL) #define BITS_EFS_HCI_SEL (BIT_MASK_EFS_HCI_SEL << BIT_SHIFT_EFS_HCI_SEL) #define BIT_CLEAR_EFS_HCI_SEL(x) ((x) & (~BITS_EFS_HCI_SEL)) #define BIT_GET_EFS_HCI_SEL(x) \ (((x) >> BIT_SHIFT_EFS_HCI_SEL) & BIT_MASK_EFS_HCI_SEL) #define BIT_SET_EFS_HCI_SEL(x, v) \ (BIT_CLEAR_EFS_HCI_SEL(x) | BIT_EFS_HCI_SEL(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_PAD_HWPDB BIT(0) #endif #if (HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ #define BIT_SHIFT_EFS_HCI_SEL_V1 0 #define BIT_MASK_EFS_HCI_SEL_V1 0x7 #define BIT_EFS_HCI_SEL_V1(x) \ (((x) & BIT_MASK_EFS_HCI_SEL_V1) << BIT_SHIFT_EFS_HCI_SEL_V1) #define BITS_EFS_HCI_SEL_V1 \ (BIT_MASK_EFS_HCI_SEL_V1 << BIT_SHIFT_EFS_HCI_SEL_V1) #define BIT_CLEAR_EFS_HCI_SEL_V1(x) ((x) & (~BITS_EFS_HCI_SEL_V1)) #define BIT_GET_EFS_HCI_SEL_V1(x) \ (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1) & BIT_MASK_EFS_HCI_SEL_V1) #define BIT_SET_EFS_HCI_SEL_V1(x, v) \ (BIT_CLEAR_EFS_HCI_SEL_V1(x) | BIT_EFS_HCI_SEL_V1(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SYS_STATUS2 (Offset 0x00F8) */ #define BIT_HIOE_ON_TIMEOUT BIT(23) #define BIT_SIC_ON_TIMEOUT BIT(22) #define BIT_CPU_ON_TIMEOUT BIT(21) #define BIT_HCI_ON_TIMEOUT BIT(20) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_STATUS2 (Offset 0x00F8) */ #define BIT_SIO_ALDN BIT(19) #define BIT_USB_ALDN BIT(18) #define BIT_PCI_ALDN BIT(17) #define BIT_SYS_ALDN BIT(16) #define BIT_SHIFT_EPVID1 8 #define BIT_MASK_EPVID1 0xff #define BIT_EPVID1(x) (((x) & BIT_MASK_EPVID1) << BIT_SHIFT_EPVID1) #define BITS_EPVID1 (BIT_MASK_EPVID1 << BIT_SHIFT_EPVID1) #define BIT_CLEAR_EPVID1(x) ((x) & (~BITS_EPVID1)) #define BIT_GET_EPVID1(x) (((x) >> BIT_SHIFT_EPVID1) & BIT_MASK_EPVID1) #define BIT_SET_EPVID1(x, v) (BIT_CLEAR_EPVID1(x) | BIT_EPVID1(v)) #define BIT_SHIFT_EPVID0 0 #define BIT_MASK_EPVID0 0xff #define BIT_EPVID0(x) (((x) & BIT_MASK_EPVID0) << BIT_SHIFT_EPVID0) #define BITS_EPVID0 (BIT_MASK_EPVID0 << BIT_SHIFT_EPVID0) #define BIT_CLEAR_EPVID0(x) ((x) & (~BITS_EPVID0)) #define BIT_GET_EPVID0(x) (((x) >> BIT_SHIFT_EPVID0) & BIT_MASK_EPVID0) #define BIT_SET_EPVID0(x, v) (BIT_CLEAR_EPVID0(x) | BIT_EPVID0(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ #define BIT_USB2_SEL_1 BIT(31) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ #define BIT_USB2_SEL BIT(31) #define BIT_FEN_WLMAC_OFF BIT(31) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ #define BIT_USB3PHY_RST BIT(30) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ #define BIT_U3PHY_RST_V1 BIT(30) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ #define BIT_U3_TERM_DET BIT(29) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ #define BIT_U3_TERM_DETECT BIT(29) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ #define BIT_USB23_DBG_SEL BIT(24) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ #define BIT_HCI_SEL_EMBEDDED BIT(8) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ #define BIT_ISO_BB2PP BIT(7) #define BIT_ISO_DENG2PP BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ #define BIT_SHIFT_HW_ID 0 #define BIT_MASK_HW_ID 0xff #define BIT_HW_ID(x) (((x) & BIT_MASK_HW_ID) << BIT_SHIFT_HW_ID) #define BITS_HW_ID (BIT_MASK_HW_ID << BIT_SHIFT_HW_ID) #define BIT_CLEAR_HW_ID(x) ((x) & (~BITS_HW_ID)) #define BIT_GET_HW_ID(x) (((x) >> BIT_SHIFT_HW_ID) & BIT_MASK_HW_ID) #define BIT_SET_HW_ID(x, v) (BIT_CLEAR_HW_ID(x) | BIT_HW_ID(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ #define BIT_SHIFT_CHIPID 0 #define BIT_MASK_CHIPID 0xff #define BIT_CHIPID(x) (((x) & BIT_MASK_CHIPID) << BIT_SHIFT_CHIPID) #define BITS_CHIPID (BIT_MASK_CHIPID << BIT_SHIFT_CHIPID) #define BIT_CLEAR_CHIPID(x) ((x) & (~BITS_CHIPID)) #define BIT_GET_CHIPID(x) (((x) >> BIT_SHIFT_CHIPID) & BIT_MASK_CHIPID) #define BIT_SET_CHIPID(x, v) (BIT_CLEAR_CHIPID(x) | BIT_CHIPID(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_CR (Offset 0x0100) */ #define BIT_MACIO_TIMEOUT_EN BIT(29) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_CR (Offset 0x0100) */ #define BIT_SHIFT_LBMODE 24 #define BIT_MASK_LBMODE 0x1f #define BIT_LBMODE(x) (((x) & BIT_MASK_LBMODE) << BIT_SHIFT_LBMODE) #define BITS_LBMODE (BIT_MASK_LBMODE << BIT_SHIFT_LBMODE) #define BIT_CLEAR_LBMODE(x) ((x) & (~BITS_LBMODE)) #define BIT_GET_LBMODE(x) (((x) >> BIT_SHIFT_LBMODE) & BIT_MASK_LBMODE) #define BIT_SET_LBMODE(x, v) (BIT_CLEAR_LBMODE(x) | BIT_LBMODE(v)) #define BIT_SHIFT_NETYPE1 18 #define BIT_MASK_NETYPE1 0x3 #define BIT_NETYPE1(x) (((x) & BIT_MASK_NETYPE1) << BIT_SHIFT_NETYPE1) #define BITS_NETYPE1 (BIT_MASK_NETYPE1 << BIT_SHIFT_NETYPE1) #define BIT_CLEAR_NETYPE1(x) ((x) & (~BITS_NETYPE1)) #define BIT_GET_NETYPE1(x) (((x) >> BIT_SHIFT_NETYPE1) & BIT_MASK_NETYPE1) #define BIT_SET_NETYPE1(x, v) (BIT_CLEAR_NETYPE1(x) | BIT_NETYPE1(v)) #define BIT_SHIFT_NETYPE0 16 #define BIT_MASK_NETYPE0 0x3 #define BIT_NETYPE0(x) (((x) & BIT_MASK_NETYPE0) << BIT_SHIFT_NETYPE0) #define BITS_NETYPE0 (BIT_MASK_NETYPE0 << BIT_SHIFT_NETYPE0) #define BIT_CLEAR_NETYPE0(x) ((x) & (~BITS_NETYPE0)) #define BIT_GET_NETYPE0(x) (((x) >> BIT_SHIFT_NETYPE0) & BIT_MASK_NETYPE0) #define BIT_SET_NETYPE0(x, v) (BIT_CLEAR_NETYPE0(x) | BIT_NETYPE0(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_CR (Offset 0x0100) */ #define BIT_STAT_FUNC_RST BIT(13) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CR (Offset 0x0100) */ #define BIT_COUNTER_STS_EN BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CR (Offset 0x0100) */ #define BIT_PTA_I2C_MBOX_EN BIT(12) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CR (Offset 0x0100) */ #define BIT_I2C_MAILBOX_EN BIT(12) #define BIT_SHCUT_EN BIT(11) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_CR (Offset 0x0100) */ #define BIT_32K_CAL_TMR_EN BIT(10) #define BIT_MAC_SEC_EN BIT(9) #define BIT_ENSWBCN BIT(8) #define BIT_MACRXEN BIT(7) #define BIT_MACTXEN BIT(6) #define BIT_SCHEDULE_EN BIT(5) #define BIT_PROTOCOL_EN BIT(4) #define BIT_RXDMA_EN BIT(3) #define BIT_TXDMA_EN BIT(2) #define BIT_HCI_RXDMA_EN BIT(1) #define BIT_HCI_TXDMA_EN BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PG_SIZE (Offset 0x0104) */ #define BIT_SHIFT_DBG_FIFO_SEL 16 #define BIT_MASK_DBG_FIFO_SEL 0xff #define BIT_DBG_FIFO_SEL(x) \ (((x) & BIT_MASK_DBG_FIFO_SEL) << BIT_SHIFT_DBG_FIFO_SEL) #define BITS_DBG_FIFO_SEL (BIT_MASK_DBG_FIFO_SEL << BIT_SHIFT_DBG_FIFO_SEL) #define BIT_CLEAR_DBG_FIFO_SEL(x) ((x) & (~BITS_DBG_FIFO_SEL)) #define BIT_GET_DBG_FIFO_SEL(x) \ (((x) >> BIT_SHIFT_DBG_FIFO_SEL) & BIT_MASK_DBG_FIFO_SEL) #define BIT_SET_DBG_FIFO_SEL(x, v) \ (BIT_CLEAR_DBG_FIFO_SEL(x) | BIT_DBG_FIFO_SEL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PKT_BUFF_ACCESS_CTRL (Offset 0x0106) */ #define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL 0 #define BIT_MASK_PKT_BUFF_ACCESS_CTRL 0xff #define BIT_PKT_BUFF_ACCESS_CTRL(x) \ (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL) \ << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) #define BITS_PKT_BUFF_ACCESS_CTRL \ (BIT_MASK_PKT_BUFF_ACCESS_CTRL << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) #define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL(x) ((x) & (~BITS_PKT_BUFF_ACCESS_CTRL)) #define BIT_GET_PKT_BUFF_ACCESS_CTRL(x) \ (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) & \ BIT_MASK_PKT_BUFF_ACCESS_CTRL) #define BIT_SET_PKT_BUFF_ACCESS_CTRL(x, v) \ (BIT_CLEAR_PKT_BUFF_ACCESS_CTRL(x) | BIT_PKT_BUFF_ACCESS_CTRL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TSF_CLK_STATE (Offset 0x0108) */ #define BIT_TSF_CLK_IDX BIT(15) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TSF_CLK_STATE (Offset 0x0108) */ #define BIT_TSF_CLK_STABLE BIT(15) #define BIT_SHIFT_I2C_M_BUS_GNT_FW 4 #define BIT_MASK_I2C_M_BUS_GNT_FW 0x7 #define BIT_I2C_M_BUS_GNT_FW(x) \ (((x) & BIT_MASK_I2C_M_BUS_GNT_FW) << BIT_SHIFT_I2C_M_BUS_GNT_FW) #define BITS_I2C_M_BUS_GNT_FW \ (BIT_MASK_I2C_M_BUS_GNT_FW << BIT_SHIFT_I2C_M_BUS_GNT_FW) #define BIT_CLEAR_I2C_M_BUS_GNT_FW(x) ((x) & (~BITS_I2C_M_BUS_GNT_FW)) #define BIT_GET_I2C_M_BUS_GNT_FW(x) \ (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW) & BIT_MASK_I2C_M_BUS_GNT_FW) #define BIT_SET_I2C_M_BUS_GNT_FW(x, v) \ (BIT_CLEAR_I2C_M_BUS_GNT_FW(x) | BIT_I2C_M_BUS_GNT_FW(v)) #define BIT_I2C_M_GNT_FW BIT(3) #define BIT_SHIFT_I2C_M_SPEED 1 #define BIT_MASK_I2C_M_SPEED 0x3 #define BIT_I2C_M_SPEED(x) \ (((x) & BIT_MASK_I2C_M_SPEED) << BIT_SHIFT_I2C_M_SPEED) #define BITS_I2C_M_SPEED (BIT_MASK_I2C_M_SPEED << BIT_SHIFT_I2C_M_SPEED) #define BIT_CLEAR_I2C_M_SPEED(x) ((x) & (~BITS_I2C_M_SPEED)) #define BIT_GET_I2C_M_SPEED(x) \ (((x) >> BIT_SHIFT_I2C_M_SPEED) & BIT_MASK_I2C_M_SPEED) #define BIT_SET_I2C_M_SPEED(x, v) \ (BIT_CLEAR_I2C_M_SPEED(x) | BIT_I2C_M_SPEED(v)) #define BIT_I2C_M_UNLOCK BIT(0) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ #define BIT_CSI_BW_EN BIT(31) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ #define BIT_SHIFT_TXDMA_HIQ_MAP_V1 19 #define BIT_MASK_TXDMA_HIQ_MAP_V1 0x7 #define BIT_TXDMA_HIQ_MAP_V1(x) \ (((x) & BIT_MASK_TXDMA_HIQ_MAP_V1) << BIT_SHIFT_TXDMA_HIQ_MAP_V1) #define BITS_TXDMA_HIQ_MAP_V1 \ (BIT_MASK_TXDMA_HIQ_MAP_V1 << BIT_SHIFT_TXDMA_HIQ_MAP_V1) #define BIT_CLEAR_TXDMA_HIQ_MAP_V1(x) ((x) & (~BITS_TXDMA_HIQ_MAP_V1)) #define BIT_GET_TXDMA_HIQ_MAP_V1(x) \ (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_V1) & BIT_MASK_TXDMA_HIQ_MAP_V1) #define BIT_SET_TXDMA_HIQ_MAP_V1(x, v) \ (BIT_CLEAR_TXDMA_HIQ_MAP_V1(x) | BIT_TXDMA_HIQ_MAP_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ #define BIT_SHIFT_TXDMA_CMQ_MAP 16 #define BIT_MASK_TXDMA_CMQ_MAP 0x3 #define BIT_TXDMA_CMQ_MAP(x) \ (((x) & BIT_MASK_TXDMA_CMQ_MAP) << BIT_SHIFT_TXDMA_CMQ_MAP) #define BITS_TXDMA_CMQ_MAP (BIT_MASK_TXDMA_CMQ_MAP << BIT_SHIFT_TXDMA_CMQ_MAP) #define BIT_CLEAR_TXDMA_CMQ_MAP(x) ((x) & (~BITS_TXDMA_CMQ_MAP)) #define BIT_GET_TXDMA_CMQ_MAP(x) \ (((x) >> BIT_SHIFT_TXDMA_CMQ_MAP) & BIT_MASK_TXDMA_CMQ_MAP) #define BIT_SET_TXDMA_CMQ_MAP(x, v) \ (BIT_CLEAR_TXDMA_CMQ_MAP(x) | BIT_TXDMA_CMQ_MAP(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ #define BIT_SHIFT_TXDMA_MGQ_MAP_V1 16 #define BIT_MASK_TXDMA_MGQ_MAP_V1 0x7 #define BIT_TXDMA_MGQ_MAP_V1(x) \ (((x) & BIT_MASK_TXDMA_MGQ_MAP_V1) << BIT_SHIFT_TXDMA_MGQ_MAP_V1) #define BITS_TXDMA_MGQ_MAP_V1 \ (BIT_MASK_TXDMA_MGQ_MAP_V1 << BIT_SHIFT_TXDMA_MGQ_MAP_V1) #define BIT_CLEAR_TXDMA_MGQ_MAP_V1(x) ((x) & (~BITS_TXDMA_MGQ_MAP_V1)) #define BIT_GET_TXDMA_MGQ_MAP_V1(x) \ (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_V1) & BIT_MASK_TXDMA_MGQ_MAP_V1) #define BIT_SET_TXDMA_MGQ_MAP_V1(x, v) \ (BIT_CLEAR_TXDMA_MGQ_MAP_V1(x) | BIT_TXDMA_MGQ_MAP_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ #define BIT_SHIFT_TXDMA_H2C_MAP 16 #define BIT_MASK_TXDMA_H2C_MAP 0x3 #define BIT_TXDMA_H2C_MAP(x) \ (((x) & BIT_MASK_TXDMA_H2C_MAP) << BIT_SHIFT_TXDMA_H2C_MAP) #define BITS_TXDMA_H2C_MAP (BIT_MASK_TXDMA_H2C_MAP << BIT_SHIFT_TXDMA_H2C_MAP) #define BIT_CLEAR_TXDMA_H2C_MAP(x) ((x) & (~BITS_TXDMA_H2C_MAP)) #define BIT_GET_TXDMA_H2C_MAP(x) \ (((x) >> BIT_SHIFT_TXDMA_H2C_MAP) & BIT_MASK_TXDMA_H2C_MAP) #define BIT_SET_TXDMA_H2C_MAP(x, v) \ (BIT_CLEAR_TXDMA_H2C_MAP(x) | BIT_TXDMA_H2C_MAP(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ #define BIT_SHIFT_TXDMA_HIQ_MAP 14 #define BIT_MASK_TXDMA_HIQ_MAP 0x3 #define BIT_TXDMA_HIQ_MAP(x) \ (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP) #define BITS_TXDMA_HIQ_MAP (BIT_MASK_TXDMA_HIQ_MAP << BIT_SHIFT_TXDMA_HIQ_MAP) #define BIT_CLEAR_TXDMA_HIQ_MAP(x) ((x) & (~BITS_TXDMA_HIQ_MAP)) #define BIT_GET_TXDMA_HIQ_MAP(x) \ (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP) & BIT_MASK_TXDMA_HIQ_MAP) #define BIT_SET_TXDMA_HIQ_MAP(x, v) \ (BIT_CLEAR_TXDMA_HIQ_MAP(x) | BIT_TXDMA_HIQ_MAP(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ #define BIT_SHIFT_TXDMA_BKQ_MAP_V1 13 #define BIT_MASK_TXDMA_BKQ_MAP_V1 0x7 #define BIT_TXDMA_BKQ_MAP_V1(x) \ (((x) & BIT_MASK_TXDMA_BKQ_MAP_V1) << BIT_SHIFT_TXDMA_BKQ_MAP_V1) #define BITS_TXDMA_BKQ_MAP_V1 \ (BIT_MASK_TXDMA_BKQ_MAP_V1 << BIT_SHIFT_TXDMA_BKQ_MAP_V1) #define BIT_CLEAR_TXDMA_BKQ_MAP_V1(x) ((x) & (~BITS_TXDMA_BKQ_MAP_V1)) #define BIT_GET_TXDMA_BKQ_MAP_V1(x) \ (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_V1) & BIT_MASK_TXDMA_BKQ_MAP_V1) #define BIT_SET_TXDMA_BKQ_MAP_V1(x, v) \ (BIT_CLEAR_TXDMA_BKQ_MAP_V1(x) | BIT_TXDMA_BKQ_MAP_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ #define BIT_SHIFT_TXDMA_MGQ_MAP 12 #define BIT_MASK_TXDMA_MGQ_MAP 0x3 #define BIT_TXDMA_MGQ_MAP(x) \ (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP) #define BITS_TXDMA_MGQ_MAP (BIT_MASK_TXDMA_MGQ_MAP << BIT_SHIFT_TXDMA_MGQ_MAP) #define BIT_CLEAR_TXDMA_MGQ_MAP(x) ((x) & (~BITS_TXDMA_MGQ_MAP)) #define BIT_GET_TXDMA_MGQ_MAP(x) \ (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP) & BIT_MASK_TXDMA_MGQ_MAP) #define BIT_SET_TXDMA_MGQ_MAP(x, v) \ (BIT_CLEAR_TXDMA_MGQ_MAP(x) | BIT_TXDMA_MGQ_MAP(v)) #define BIT_SHIFT_TXDMA_BKQ_MAP 10 #define BIT_MASK_TXDMA_BKQ_MAP 0x3 #define BIT_TXDMA_BKQ_MAP(x) \ (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP) #define BITS_TXDMA_BKQ_MAP (BIT_MASK_TXDMA_BKQ_MAP << BIT_SHIFT_TXDMA_BKQ_MAP) #define BIT_CLEAR_TXDMA_BKQ_MAP(x) ((x) & (~BITS_TXDMA_BKQ_MAP)) #define BIT_GET_TXDMA_BKQ_MAP(x) \ (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP) & BIT_MASK_TXDMA_BKQ_MAP) #define BIT_SET_TXDMA_BKQ_MAP(x, v) \ (BIT_CLEAR_TXDMA_BKQ_MAP(x) | BIT_TXDMA_BKQ_MAP(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ #define BIT_SHIFT_TXDMA_BEQ_MAP_V1 10 #define BIT_MASK_TXDMA_BEQ_MAP_V1 0x7 #define BIT_TXDMA_BEQ_MAP_V1(x) \ (((x) & BIT_MASK_TXDMA_BEQ_MAP_V1) << BIT_SHIFT_TXDMA_BEQ_MAP_V1) #define BITS_TXDMA_BEQ_MAP_V1 \ (BIT_MASK_TXDMA_BEQ_MAP_V1 << BIT_SHIFT_TXDMA_BEQ_MAP_V1) #define BIT_CLEAR_TXDMA_BEQ_MAP_V1(x) ((x) & (~BITS_TXDMA_BEQ_MAP_V1)) #define BIT_GET_TXDMA_BEQ_MAP_V1(x) \ (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_V1) & BIT_MASK_TXDMA_BEQ_MAP_V1) #define BIT_SET_TXDMA_BEQ_MAP_V1(x, v) \ (BIT_CLEAR_TXDMA_BEQ_MAP_V1(x) | BIT_TXDMA_BEQ_MAP_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ #define BIT_SHIFT_TXDMA_BEQ_MAP 8 #define BIT_MASK_TXDMA_BEQ_MAP 0x3 #define BIT_TXDMA_BEQ_MAP(x) \ (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP) #define BITS_TXDMA_BEQ_MAP (BIT_MASK_TXDMA_BEQ_MAP << BIT_SHIFT_TXDMA_BEQ_MAP) #define BIT_CLEAR_TXDMA_BEQ_MAP(x) ((x) & (~BITS_TXDMA_BEQ_MAP)) #define BIT_GET_TXDMA_BEQ_MAP(x) \ (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP) & BIT_MASK_TXDMA_BEQ_MAP) #define BIT_SET_TXDMA_BEQ_MAP(x, v) \ (BIT_CLEAR_TXDMA_BEQ_MAP(x) | BIT_TXDMA_BEQ_MAP(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ #define BIT_SHIFT_TXDMA_VIQ_MAP_V1 7 #define BIT_MASK_TXDMA_VIQ_MAP_V1 0x7 #define BIT_TXDMA_VIQ_MAP_V1(x) \ (((x) & BIT_MASK_TXDMA_VIQ_MAP_V1) << BIT_SHIFT_TXDMA_VIQ_MAP_V1) #define BITS_TXDMA_VIQ_MAP_V1 \ (BIT_MASK_TXDMA_VIQ_MAP_V1 << BIT_SHIFT_TXDMA_VIQ_MAP_V1) #define BIT_CLEAR_TXDMA_VIQ_MAP_V1(x) ((x) & (~BITS_TXDMA_VIQ_MAP_V1)) #define BIT_GET_TXDMA_VIQ_MAP_V1(x) \ (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_V1) & BIT_MASK_TXDMA_VIQ_MAP_V1) #define BIT_SET_TXDMA_VIQ_MAP_V1(x, v) \ (BIT_CLEAR_TXDMA_VIQ_MAP_V1(x) | BIT_TXDMA_VIQ_MAP_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ #define BIT_SHIFT_TXDMA_VIQ_MAP 6 #define BIT_MASK_TXDMA_VIQ_MAP 0x3 #define BIT_TXDMA_VIQ_MAP(x) \ (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP) #define BITS_TXDMA_VIQ_MAP (BIT_MASK_TXDMA_VIQ_MAP << BIT_SHIFT_TXDMA_VIQ_MAP) #define BIT_CLEAR_TXDMA_VIQ_MAP(x) ((x) & (~BITS_TXDMA_VIQ_MAP)) #define BIT_GET_TXDMA_VIQ_MAP(x) \ (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP) & BIT_MASK_TXDMA_VIQ_MAP) #define BIT_SET_TXDMA_VIQ_MAP(x, v) \ (BIT_CLEAR_TXDMA_VIQ_MAP(x) | BIT_TXDMA_VIQ_MAP(v)) #define BIT_SHIFT_TXDMA_VOQ_MAP 4 #define BIT_MASK_TXDMA_VOQ_MAP 0x3 #define BIT_TXDMA_VOQ_MAP(x) \ (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP) #define BITS_TXDMA_VOQ_MAP (BIT_MASK_TXDMA_VOQ_MAP << BIT_SHIFT_TXDMA_VOQ_MAP) #define BIT_CLEAR_TXDMA_VOQ_MAP(x) ((x) & (~BITS_TXDMA_VOQ_MAP)) #define BIT_GET_TXDMA_VOQ_MAP(x) \ (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP) & BIT_MASK_TXDMA_VOQ_MAP) #define BIT_SET_TXDMA_VOQ_MAP(x, v) \ (BIT_CLEAR_TXDMA_VOQ_MAP(x) | BIT_TXDMA_VOQ_MAP(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ #define BIT_SHIFT_TXDMA_VOQ_MAP_V1 4 #define BIT_MASK_TXDMA_VOQ_MAP_V1 0x7 #define BIT_TXDMA_VOQ_MAP_V1(x) \ (((x) & BIT_MASK_TXDMA_VOQ_MAP_V1) << BIT_SHIFT_TXDMA_VOQ_MAP_V1) #define BITS_TXDMA_VOQ_MAP_V1 \ (BIT_MASK_TXDMA_VOQ_MAP_V1 << BIT_SHIFT_TXDMA_VOQ_MAP_V1) #define BIT_CLEAR_TXDMA_VOQ_MAP_V1(x) ((x) & (~BITS_TXDMA_VOQ_MAP_V1)) #define BIT_GET_TXDMA_VOQ_MAP_V1(x) \ (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_V1) & BIT_MASK_TXDMA_VOQ_MAP_V1) #define BIT_SET_TXDMA_VOQ_MAP_V1(x, v) \ (BIT_CLEAR_TXDMA_VOQ_MAP_V1(x) | BIT_TXDMA_VOQ_MAP_V1(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ #define BIT_TXDMA_BW_EN BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ #define BIT_RXDMA_AGG_EN BIT(2) #define BIT_RXSHFT_EN BIT(1) #define BIT_RXDMA_ARBBW_EN BIT(0) #endif #if (HALMAC_8814A_SUPPORT) /* 2 REG_TRXFF_BNDY (Offset 0x0114) */ #define BIT_SHIFT_RXFFOVFL_RSV_V1 28 #define BIT_MASK_RXFFOVFL_RSV_V1 0xf #define BIT_RXFFOVFL_RSV_V1(x) \ (((x) & BIT_MASK_RXFFOVFL_RSV_V1) << BIT_SHIFT_RXFFOVFL_RSV_V1) #define BITS_RXFFOVFL_RSV_V1 \ (BIT_MASK_RXFFOVFL_RSV_V1 << BIT_SHIFT_RXFFOVFL_RSV_V1) #define BIT_CLEAR_RXFFOVFL_RSV_V1(x) ((x) & (~BITS_RXFFOVFL_RSV_V1)) #define BIT_GET_RXFFOVFL_RSV_V1(x) \ (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V1) & BIT_MASK_RXFFOVFL_RSV_V1) #define BIT_SET_RXFFOVFL_RSV_V1(x, v) \ (BIT_CLEAR_RXFFOVFL_RSV_V1(x) | BIT_RXFFOVFL_RSV_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TRXFF_BNDY (Offset 0x0114) */ #define BIT_SHIFT_RXFF0_BNDY 16 #define BIT_MASK_RXFF0_BNDY 0xffff #define BIT_RXFF0_BNDY(x) (((x) & BIT_MASK_RXFF0_BNDY) << BIT_SHIFT_RXFF0_BNDY) #define BITS_RXFF0_BNDY (BIT_MASK_RXFF0_BNDY << BIT_SHIFT_RXFF0_BNDY) #define BIT_CLEAR_RXFF0_BNDY(x) ((x) & (~BITS_RXFF0_BNDY)) #define BIT_GET_RXFF0_BNDY(x) \ (((x) >> BIT_SHIFT_RXFF0_BNDY) & BIT_MASK_RXFF0_BNDY) #define BIT_SET_RXFF0_BNDY(x, v) (BIT_CLEAR_RXFF0_BNDY(x) | BIT_RXFF0_BNDY(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TRXFF_BNDY (Offset 0x0114) */ #define BIT_SHIFT_FWFFOVFL_RSV 16 #define BIT_MASK_FWFFOVFL_RSV 0xf #define BIT_FWFFOVFL_RSV(x) \ (((x) & BIT_MASK_FWFFOVFL_RSV) << BIT_SHIFT_FWFFOVFL_RSV) #define BITS_FWFFOVFL_RSV (BIT_MASK_FWFFOVFL_RSV << BIT_SHIFT_FWFFOVFL_RSV) #define BIT_CLEAR_FWFFOVFL_RSV(x) ((x) & (~BITS_FWFFOVFL_RSV)) #define BIT_GET_FWFFOVFL_RSV(x) \ (((x) >> BIT_SHIFT_FWFFOVFL_RSV) & BIT_MASK_FWFFOVFL_RSV) #define BIT_SET_FWFFOVFL_RSV(x, v) \ (BIT_CLEAR_FWFFOVFL_RSV(x) | BIT_FWFFOVFL_RSV(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TRXFF_BNDY (Offset 0x0114) */ #define BIT_SHIFT_RXFFOVFL_RSV 8 #define BIT_MASK_RXFFOVFL_RSV 0xf #define BIT_RXFFOVFL_RSV(x) \ (((x) & BIT_MASK_RXFFOVFL_RSV) << BIT_SHIFT_RXFFOVFL_RSV) #define BITS_RXFFOVFL_RSV (BIT_MASK_RXFFOVFL_RSV << BIT_SHIFT_RXFFOVFL_RSV) #define BIT_CLEAR_RXFFOVFL_RSV(x) ((x) & (~BITS_RXFFOVFL_RSV)) #define BIT_GET_RXFFOVFL_RSV(x) \ (((x) >> BIT_SHIFT_RXFFOVFL_RSV) & BIT_MASK_RXFFOVFL_RSV) #define BIT_SET_RXFFOVFL_RSV(x, v) \ (BIT_CLEAR_RXFFOVFL_RSV(x) | BIT_RXFFOVFL_RSV(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_TRXFF_BNDY (Offset 0x0114) */ #define BIT_SHIFT_RXFFOVFL_RSV_V2 8 #define BIT_MASK_RXFFOVFL_RSV_V2 0xf #define BIT_RXFFOVFL_RSV_V2(x) \ (((x) & BIT_MASK_RXFFOVFL_RSV_V2) << BIT_SHIFT_RXFFOVFL_RSV_V2) #define BITS_RXFFOVFL_RSV_V2 \ (BIT_MASK_RXFFOVFL_RSV_V2 << BIT_SHIFT_RXFFOVFL_RSV_V2) #define BIT_CLEAR_RXFFOVFL_RSV_V2(x) ((x) & (~BITS_RXFFOVFL_RSV_V2)) #define BIT_GET_RXFFOVFL_RSV_V2(x) \ (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2) & BIT_MASK_RXFFOVFL_RSV_V2) #define BIT_SET_RXFFOVFL_RSV_V2(x, v) \ (BIT_CLEAR_RXFFOVFL_RSV_V2(x) | BIT_RXFFOVFL_RSV_V2(v)) #endif #if (HALMAC_8814A_SUPPORT) /* 2 REG_TRXFF_BNDY (Offset 0x0114) */ #define BIT_SHIFT_RXFF0_BNDY_V1 8 #define BIT_MASK_RXFF0_BNDY_V1 0x3ffff #define BIT_RXFF0_BNDY_V1(x) \ (((x) & BIT_MASK_RXFF0_BNDY_V1) << BIT_SHIFT_RXFF0_BNDY_V1) #define BITS_RXFF0_BNDY_V1 (BIT_MASK_RXFF0_BNDY_V1 << BIT_SHIFT_RXFF0_BNDY_V1) #define BIT_CLEAR_RXFF0_BNDY_V1(x) ((x) & (~BITS_RXFF0_BNDY_V1)) #define BIT_GET_RXFF0_BNDY_V1(x) \ (((x) >> BIT_SHIFT_RXFF0_BNDY_V1) & BIT_MASK_RXFF0_BNDY_V1) #define BIT_SET_RXFF0_BNDY_V1(x, v) \ (BIT_CLEAR_RXFF0_BNDY_V1(x) | BIT_RXFF0_BNDY_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TRXFF_BNDY (Offset 0x0114) */ #define BIT_SHIFT_TXPKTBUF_PGBNDY 0 #define BIT_MASK_TXPKTBUF_PGBNDY 0xff #define BIT_TXPKTBUF_PGBNDY(x) \ (((x) & BIT_MASK_TXPKTBUF_PGBNDY) << BIT_SHIFT_TXPKTBUF_PGBNDY) #define BITS_TXPKTBUF_PGBNDY \ (BIT_MASK_TXPKTBUF_PGBNDY << BIT_SHIFT_TXPKTBUF_PGBNDY) #define BIT_CLEAR_TXPKTBUF_PGBNDY(x) ((x) & (~BITS_TXPKTBUF_PGBNDY)) #define BIT_GET_TXPKTBUF_PGBNDY(x) \ (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY) & BIT_MASK_TXPKTBUF_PGBNDY) #define BIT_SET_TXPKTBUF_PGBNDY(x, v) \ (BIT_CLEAR_TXPKTBUF_PGBNDY(x) | BIT_TXPKTBUF_PGBNDY(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_TRXFF_BNDY (Offset 0x0114) */ #define BIT_SHIFT_RXFF0_BNDY_V2 0 #define BIT_MASK_RXFF0_BNDY_V2 0x3ffff #define BIT_RXFF0_BNDY_V2(x) \ (((x) & BIT_MASK_RXFF0_BNDY_V2) << BIT_SHIFT_RXFF0_BNDY_V2) #define BITS_RXFF0_BNDY_V2 (BIT_MASK_RXFF0_BNDY_V2 << BIT_SHIFT_RXFF0_BNDY_V2) #define BIT_CLEAR_RXFF0_BNDY_V2(x) ((x) & (~BITS_RXFF0_BNDY_V2)) #define BIT_GET_RXFF0_BNDY_V2(x) \ (((x) >> BIT_SHIFT_RXFF0_BNDY_V2) & BIT_MASK_RXFF0_BNDY_V2) #define BIT_SET_RXFF0_BNDY_V2(x, v) \ (BIT_CLEAR_RXFF0_BNDY_V2(x) | BIT_RXFF0_BNDY_V2(v)) #define BIT_SHIFT_RXFF0_RDPTR_V2 0 #define BIT_MASK_RXFF0_RDPTR_V2 0x3ffff #define BIT_RXFF0_RDPTR_V2(x) \ (((x) & BIT_MASK_RXFF0_RDPTR_V2) << BIT_SHIFT_RXFF0_RDPTR_V2) #define BITS_RXFF0_RDPTR_V2 \ (BIT_MASK_RXFF0_RDPTR_V2 << BIT_SHIFT_RXFF0_RDPTR_V2) #define BIT_CLEAR_RXFF0_RDPTR_V2(x) ((x) & (~BITS_RXFF0_RDPTR_V2)) #define BIT_GET_RXFF0_RDPTR_V2(x) \ (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2) & BIT_MASK_RXFF0_RDPTR_V2) #define BIT_SET_RXFF0_RDPTR_V2(x, v) \ (BIT_CLEAR_RXFF0_RDPTR_V2(x) | BIT_RXFF0_RDPTR_V2(v)) #define BIT_SHIFT_RXFF0_WTPTR_V2 0 #define BIT_MASK_RXFF0_WTPTR_V2 0x3ffff #define BIT_RXFF0_WTPTR_V2(x) \ (((x) & BIT_MASK_RXFF0_WTPTR_V2) << BIT_SHIFT_RXFF0_WTPTR_V2) #define BITS_RXFF0_WTPTR_V2 \ (BIT_MASK_RXFF0_WTPTR_V2 << BIT_SHIFT_RXFF0_WTPTR_V2) #define BIT_CLEAR_RXFF0_WTPTR_V2(x) ((x) & (~BITS_RXFF0_WTPTR_V2)) #define BIT_GET_RXFF0_WTPTR_V2(x) \ (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2) & BIT_MASK_RXFF0_WTPTR_V2) #define BIT_SET_RXFF0_WTPTR_V2(x, v) \ (BIT_CLEAR_RXFF0_WTPTR_V2(x) | BIT_RXFF0_WTPTR_V2(v)) #endif #if (HALMAC_8814A_SUPPORT) /* 2 REG_FF_STATUS (Offset 0x0118) */ #define BIT_SHIFT_RXFF0_RDPTR_V1 13 #define BIT_MASK_RXFF0_RDPTR_V1 0x3ffff #define BIT_RXFF0_RDPTR_V1(x) \ (((x) & BIT_MASK_RXFF0_RDPTR_V1) << BIT_SHIFT_RXFF0_RDPTR_V1) #define BITS_RXFF0_RDPTR_V1 \ (BIT_MASK_RXFF0_RDPTR_V1 << BIT_SHIFT_RXFF0_RDPTR_V1) #define BIT_CLEAR_RXFF0_RDPTR_V1(x) ((x) & (~BITS_RXFF0_RDPTR_V1)) #define BIT_GET_RXFF0_RDPTR_V1(x) \ (((x) >> BIT_SHIFT_RXFF0_RDPTR_V1) & BIT_MASK_RXFF0_RDPTR_V1) #define BIT_SET_RXFF0_RDPTR_V1(x, v) \ (BIT_CLEAR_RXFF0_RDPTR_V1(x) | BIT_RXFF0_RDPTR_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PTA_I2C_MBOX (Offset 0x0118) */ #define BIT_SHIFT_I2C_M_STATUS 8 #define BIT_MASK_I2C_M_STATUS 0xf #define BIT_I2C_M_STATUS(x) \ (((x) & BIT_MASK_I2C_M_STATUS) << BIT_SHIFT_I2C_M_STATUS) #define BITS_I2C_M_STATUS (BIT_MASK_I2C_M_STATUS << BIT_SHIFT_I2C_M_STATUS) #define BIT_CLEAR_I2C_M_STATUS(x) ((x) & (~BITS_I2C_M_STATUS)) #define BIT_GET_I2C_M_STATUS(x) \ (((x) >> BIT_SHIFT_I2C_M_STATUS) & BIT_MASK_I2C_M_STATUS) #define BIT_SET_I2C_M_STATUS(x, v) \ (BIT_CLEAR_I2C_M_STATUS(x) | BIT_I2C_M_STATUS(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PTA_I2C_MBOX (Offset 0x0118) */ #define BIT_SHIFT_I2C_M_BUS_GNT 4 #define BIT_MASK_I2C_M_BUS_GNT 0x7 #define BIT_I2C_M_BUS_GNT(x) \ (((x) & BIT_MASK_I2C_M_BUS_GNT) << BIT_SHIFT_I2C_M_BUS_GNT) #define BITS_I2C_M_BUS_GNT (BIT_MASK_I2C_M_BUS_GNT << BIT_SHIFT_I2C_M_BUS_GNT) #define BIT_CLEAR_I2C_M_BUS_GNT(x) ((x) & (~BITS_I2C_M_BUS_GNT)) #define BIT_GET_I2C_M_BUS_GNT(x) \ (((x) >> BIT_SHIFT_I2C_M_BUS_GNT) & BIT_MASK_I2C_M_BUS_GNT) #define BIT_SET_I2C_M_BUS_GNT(x, v) \ (BIT_CLEAR_I2C_M_BUS_GNT(x) | BIT_I2C_M_BUS_GNT(v)) #define BIT_I2C_GNT_FW BIT(3) #define BIT_SHIFT_I2C_DATA_RATE 1 #define BIT_MASK_I2C_DATA_RATE 0x3 #define BIT_I2C_DATA_RATE(x) \ (((x) & BIT_MASK_I2C_DATA_RATE) << BIT_SHIFT_I2C_DATA_RATE) #define BITS_I2C_DATA_RATE (BIT_MASK_I2C_DATA_RATE << BIT_SHIFT_I2C_DATA_RATE) #define BIT_CLEAR_I2C_DATA_RATE(x) ((x) & (~BITS_I2C_DATA_RATE)) #define BIT_GET_I2C_DATA_RATE(x) \ (((x) >> BIT_SHIFT_I2C_DATA_RATE) & BIT_MASK_I2C_DATA_RATE) #define BIT_SET_I2C_DATA_RATE(x, v) \ (BIT_CLEAR_I2C_DATA_RATE(x) | BIT_I2C_DATA_RATE(v)) #define BIT_I2C_SW_CONTROL_UNLOCK BIT(0) #endif #if (HALMAC_8814A_SUPPORT) /* 2 REG_FF_STATUS (Offset 0x0118) */ #define BIT_SHIFT_RXFF0_WTPTR_V1 0 #define BIT_MASK_RXFF0_WTPTR_V1 0x3ffff #define BIT_RXFF0_WTPTR_V1(x) \ (((x) & BIT_MASK_RXFF0_WTPTR_V1) << BIT_SHIFT_RXFF0_WTPTR_V1) #define BITS_RXFF0_WTPTR_V1 \ (BIT_MASK_RXFF0_WTPTR_V1 << BIT_SHIFT_RXFF0_WTPTR_V1) #define BIT_CLEAR_RXFF0_WTPTR_V1(x) ((x) & (~BITS_RXFF0_WTPTR_V1)) #define BIT_GET_RXFF0_WTPTR_V1(x) \ (((x) >> BIT_SHIFT_RXFF0_WTPTR_V1) & BIT_MASK_RXFF0_WTPTR_V1) #define BIT_SET_RXFF0_WTPTR_V1(x, v) \ (BIT_CLEAR_RXFF0_WTPTR_V1(x) | BIT_RXFF0_WTPTR_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXFF_PTR (Offset 0x011C) */ #define BIT_SHIFT_RXFF0_RDPTR 16 #define BIT_MASK_RXFF0_RDPTR 0xffff #define BIT_RXFF0_RDPTR(x) \ (((x) & BIT_MASK_RXFF0_RDPTR) << BIT_SHIFT_RXFF0_RDPTR) #define BITS_RXFF0_RDPTR (BIT_MASK_RXFF0_RDPTR << BIT_SHIFT_RXFF0_RDPTR) #define BIT_CLEAR_RXFF0_RDPTR(x) ((x) & (~BITS_RXFF0_RDPTR)) #define BIT_GET_RXFF0_RDPTR(x) \ (((x) >> BIT_SHIFT_RXFF0_RDPTR) & BIT_MASK_RXFF0_RDPTR) #define BIT_SET_RXFF0_RDPTR(x, v) \ (BIT_CLEAR_RXFF0_RDPTR(x) | BIT_RXFF0_RDPTR(v)) #define BIT_SHIFT_RXFF0_WTPTR 0 #define BIT_MASK_RXFF0_WTPTR 0xffff #define BIT_RXFF0_WTPTR(x) \ (((x) & BIT_MASK_RXFF0_WTPTR) << BIT_SHIFT_RXFF0_WTPTR) #define BITS_RXFF0_WTPTR (BIT_MASK_RXFF0_WTPTR << BIT_SHIFT_RXFF0_WTPTR) #define BIT_CLEAR_RXFF0_WTPTR(x) ((x) & (~BITS_RXFF0_WTPTR)) #define BIT_GET_RXFF0_WTPTR(x) \ (((x) >> BIT_SHIFT_RXFF0_WTPTR) & BIT_MASK_RXFF0_WTPTR) #define BIT_SET_RXFF0_WTPTR(x, v) \ (BIT_CLEAR_RXFF0_WTPTR(x) | BIT_RXFF0_WTPTR(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT_EN BIT(31) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_FS_SW_PLL_LEAVE_32K_INT_EN BIT(31) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_FWFF_FULL_INT_EN BIT(30) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_FS_FWFF_FULL_INT_EN BIT(30) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_BB_STOP_RX_INT_EN BIT(29) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_FS_BB_STOP_RX_INT_EN BIT(29) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_FS_RXDMA2_DONE_INT_EN BIT(28) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_FS_RXDONE3_INT_EN BIT(27) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_FS_RXDONE2_INT_EN BIT(26) #define BIT_FS_RX_BCN_P4_INT_EN BIT(25) #define BIT_FS_RX_BCN_P3_INT_EN BIT(24) #define BIT_FS_RX_BCN_P2_INT_EN BIT(23) #define BIT_FS_RX_BCN_P1_INT_EN BIT(22) #define BIT_FS_RX_BCN_P0_INT_EN BIT(21) #define BIT_FS_RX_UMD0_INT_EN BIT(20) #define BIT_FS_RX_UMD1_INT_EN BIT(19) #define BIT_FS_RX_BMD0_INT_EN BIT(18) #define BIT_FS_RX_BMD1_INT_EN BIT(17) #define BIT_FS_RXDONE_INT_EN BIT(16) #define BIT_FS_WWLAN_INT_EN BIT(15) #define BIT_FS_SOUND_DONE_INT_EN BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_FS_LP_STBY_INT_EN BIT(13) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_FS_TRL_MTR_INT_EN BIT(12) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_FS_BF1_PRETO_INT_EN BIT(11) #define BIT_FS_BF0_PRETO_INT_EN BIT(10) #define BIT_FS_PTCL_RELEASE_MACID_INT_EN BIT(9) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_PRETXERR_HANDLE_FSIMR BIT(8) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_PRETX_ERRHLD_INT_EN BIT(8) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_FS_PRETX_ERRHLD_INT_EN BIT(8) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_FS_GTRD_INT_EN BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_FS_LTE_COEX_EN BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_FS_WLACTOFF_INT_EN BIT(5) #define BIT_FS_WLACTON_INT_EN BIT(4) #define BIT_FS_BTCMD_INT_EN BIT(3) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_FEIMR (Offset 0x0120) */ #define BIT_REG_MAILBOX_TO_I2C_INT BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FEIMR (Offset 0x0120) */ #define BIT_TRPC_TO_INT_EN BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_FS_TRPC_TO_INT_EN_V1 BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FEIMR (Offset 0x0120) */ #define BIT_BIT_RPC_O_T_INT_EN BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE1IMR (Offset 0x0120) */ #define BIT_FS_RPC_O_T_INT_EN_V1 BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT BIT(31) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_FS_SW_PLL_LEAVE_32K_INT BIT(31) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_FWFF_FULL_INT BIT(30) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_FS_FS_FWFF_FULL_INT BIT(30) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_BB_STOP_RX_INT BIT(29) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_FS_BB_STOP_RX_INT BIT(29) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_FS_RXDMA2_DONE_INT BIT(28) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_FS_RXDONE3_INT BIT(27) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_FS_RXDONE3_INT_INT BIT(27) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_FS_RXDONE2_INT BIT(26) #define BIT_FS_RX_BCN_P4_INT BIT(25) #define BIT_FS_RX_BCN_P3_INT BIT(24) #define BIT_FS_RX_BCN_P2_INT BIT(23) #define BIT_FS_RX_BCN_P1_INT BIT(22) #define BIT_FS_RX_BCN_P0_INT BIT(21) #define BIT_FS_RX_UMD0_INT BIT(20) #define BIT_FS_RX_UMD1_INT BIT(19) #define BIT_FS_RX_BMD0_INT BIT(18) #define BIT_FS_RX_BMD1_INT BIT(17) #define BIT_FS_RXDONE_INT BIT(16) #define BIT_FS_WWLAN_INT BIT(15) #define BIT_FS_SOUND_DONE_INT BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_FS_LP_STBY_INT BIT(13) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_FS_TRL_MTR_INT BIT(12) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_FS_BF1_PRETO_INT BIT(11) #define BIT_FS_BF0_PRETO_INT BIT(10) #define BIT_FS_PTCL_RELEASE_MACID_INT BIT(9) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_PRETXERR_HANDLE_FSISR BIT(8) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_PRETX_ERRHLD_INT BIT(8) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_FS_PRETX_ERRHLD_INT BIT(8) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_SND_RDY_INT BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_FS_LTE_COEX_INT BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_FS_WLACTOFF_INT BIT(5) #define BIT_FS_WLACTON_INT BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_FS_BCN_RX_INT_INT BIT(3) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_BT_CMD_INT BIT(3) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_FEISR (Offset 0x0124) */ #define BIT_MAILBOX_TO_I2C BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_FS_MAILBOX_TO_I2C_INT BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FEISR (Offset 0x0124) */ #define BIT_TRPC_TO_INT BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_FS_TRPC_TO_INT BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FEISR (Offset 0x0124) */ #define BIT_RPC_O_T_INT BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE1ISR (Offset 0x0124) */ #define BIT_FS_RPC_O_T_INT BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_CPWM (Offset 0x012C) */ #define BIT_CPWM_TOGGLING BIT(31) #define BIT_SHIFT_CPWM_MOD 24 #define BIT_MASK_CPWM_MOD 0x7f #define BIT_CPWM_MOD(x) (((x) & BIT_MASK_CPWM_MOD) << BIT_SHIFT_CPWM_MOD) #define BITS_CPWM_MOD (BIT_MASK_CPWM_MOD << BIT_SHIFT_CPWM_MOD) #define BIT_CLEAR_CPWM_MOD(x) ((x) & (~BITS_CPWM_MOD)) #define BIT_GET_CPWM_MOD(x) (((x) >> BIT_SHIFT_CPWM_MOD) & BIT_MASK_CPWM_MOD) #define BIT_SET_CPWM_MOD(x, v) (BIT_CLEAR_CPWM_MOD(x) | BIT_CPWM_MOD(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXBCNOK_MB7_INT_EN BIT(31) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_SOUND_DONE_MSK BIT(30) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXBCNOK_MB6_INT_EN BIT(30) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_TRY_DONE_MSK BIT(29) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXBCNOK_MB5_INT_EN BIT(29) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_TXRPT_CNT_FULL_MSK BIT(28) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXBCNOK_MB4_INT_EN BIT(28) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_WLACTOFF_INT_EN BIT(27) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXBCNOK_MB3_INT_EN BIT(27) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_WLACTON_INT_EN BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXBCNOK_MB2_INT_EN BIT(26) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_TXPKTIN_INT_EN BIT(25) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXBCNOK_MB1_INT_EN BIT(25) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_TXBCNOK_MSK BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXBCNOK_MB0_INT_EN BIT(24) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_TXBCNERR_MSK BIT(23) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXBCNERR_MB7_INT_EN BIT(23) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_RX_UMD0_EN BIT(22) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXBCNERR_MB6_INT_EN BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_RX_UMD1_EN BIT(21) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXBCNERR_MB5_INT_EN BIT(21) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_RX_BMD0_EN BIT(20) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXBCNERR_MB4_INT_EN BIT(20) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_RX_BMD1_EN BIT(19) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXBCNERR_MB3_INT_EN BIT(19) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_BCN_RX_INT_EN BIT(18) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXBCNERR_MB2_INT_EN BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_TBTTINT_MSK BIT(17) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXBCNERR_MB1_INT_EN BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_BCNERLY_MSK BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXBCNERR_MB0_INT_EN BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_BCNDMA7_MSK BIT(15) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_CPUMGN_POLLED_PKT_DONE_INT_EN BIT(15) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_CPU_MGQ_TXDONE_INT_EN BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_BCNDMA6_MSK BIT(14) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_SIFS_OVERSPEC_INT_EN BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_BCNDMA5_MSK BIT(13) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_BCNDMA4_MSK BIT(12) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_MGNTQFF_TO_INT_EN BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_BCNDMA3_MSK BIT(11) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_DDMA1_LP_INT_ENBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_EN BIT(11) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_CPUMGQ_ERR_INT_EN BIT(11) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_DDMA1_LP_INT_EN BIT(11) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_BCNDMA2_MSK BIT(10) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_DDMA1_HP_INT_EN BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_BCNDMA1_MSK BIT(9) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_DDMA0_LP_INT_EN BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_BCNDMA0_MSK BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_DDMA0_HP_INT_EN BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_LP_STBY_MSK BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TRXRPT_INT_EN BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_CTWENDINT_MSK BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_C2H_W_READY_INT_EN BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_HRCV_MSK BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_HRCV_INT_EN BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_H2CCMD_MSK BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_H2CCMD_INT_EN BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_RXDONE_MSK BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXPKTIN_INT_EN BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_ERRORHDL_MSK BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_ERRORHDL_INT_EN BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_TXCCX_MSK_FW BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXCCX_INT_EN BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_TXCLOSE_MSK BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWIMR (Offset 0x0130) */ #define BIT_FS_TXCLOSE_INT_EN BIT(0) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXBCNOK_MB7_INT BIT(31) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_SOUND_DONE_INT BIT(30) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXBCNOK_MB6_INT BIT(30) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_TRY_DONE_INT BIT(29) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXBCNOK_MB5_INT BIT(29) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_TXRPT_CNT_FULL_INT BIT(28) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXBCNOK_MB4_INT BIT(28) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_WLACTOFF_INT BIT(27) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXBCNOK_MB3_INT BIT(27) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_WLACTON_INT BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXBCNOK_MB2_INT BIT(26) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_TXPKTIN_INT BIT(25) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXBCNOK_MB1_INT BIT(25) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_TXBCNOK_INT BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXBCNOK_MB0_INT BIT(24) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_TXBCNERR_INT BIT(23) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXBCNERR_MB7_INT BIT(23) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_RX_UMD0_INT BIT(22) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXBCNERR_MB6_INT BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_RX_UMD1_INT BIT(21) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXBCNERR_MB5_INT BIT(21) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_RX_BMD0_INT BIT(20) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXBCNERR_MB4_INT BIT(20) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_RX_BMD1_INT BIT(19) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXBCNERR_MB3_INT BIT(19) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_BCN_RX_INT_INT BIT(18) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXBCNERR_MB2_INT BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_TBTTINT_INT BIT(17) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXBCNERR_MB1_INT BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_BCNERLY_INT BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXBCNERR_MB0_INT BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_BCNDMA7_INT BIT(15) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_CPUMGN_POLLED_PKT_DONE_INT BIT(15) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_CPU_MGQ_TXDONE_INT BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_BCNDMA6_INT BIT(14) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_SIFS_OVERSPEC_INT BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_BCNDMA5_INT BIT(13) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_MGNTQ_RPTR_RELEASE_INT BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_BCNDMA4_INT BIT(12) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_MGNTQFF_TO_INT BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_BCNDMA3_INT BIT(11) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_DDMA1_LP_INTBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT BIT(11) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_CPUMGQ_ERR_INT BIT(11) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_DDMA1_LP_INT BIT(11) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_BCNDMA2_INT BIT(10) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_DDMA1_HP_INT BIT(10) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FWCMD_PKTIN_INT BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_BCNDMA1_INT BIT(9) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_DDMA0_LP_INT BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_BCNDMA0_INT BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_DDMA0_HP_INT BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_LP_STBY_INT BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TRXRPT_INT BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_CTWENDINT_INT BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_C2H_W_READY_INT BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_HRCV_INT BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_HRCV_INT BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_H2CCMD_INT BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_H2CCMD_INT BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_RXDONE_INT BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXPKTIN_INT BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_ERRORHDL_INT BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_ERRORHDL_INT BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_TXCCX_INT BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXCCX_INT BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_TXCLOSE_INT BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWISR (Offset 0x0134) */ #define BIT_FS_TXCLOSE_INT BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_GTINT6_MSK BIT(31) #define BIT_TX_NULL1_INT_MSK BIT(30) #define BIT_TX_NULL0_INT_MSK BIT(29) #define BIT_MTI_BCNIVLEAR_INT_MSK BIT(28) #define BIT_ATIMINT_MSK BIT(27) #define BIT_WWLAN_INT_EN BIT(26) #define BIT_C2H_W_READY_EN BIT(25) #define BIT_TRL_MTR_EN BIT(24) #define BIT_CLR_PS_STATUS_MSK BIT(23) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_PS_TIMER_C_EARLY_INT_EN BIT(23) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_RETRIEVE_BUFFERED_MSK BIT(22) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_PS_TIMER_B_EARLY_INT_EN BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_RPWMINT2_MSK BIT(21) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_PS_TIMER_A_EARLY_INT_EN BIT(21) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_TSF_BIT32_TOGGLE_MSK_V1 BIT(20) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN BIT(20) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_TRIGGER_PKT_MSK BIT(19) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_PS_TIMER_C_INT_EN BIT(19) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FW_BTCMD_INTMSK BIT(18) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_PS_TIMER_B_INT_EN BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_P2P_RFOFF_INTMSK BIT(17) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_PS_TIMER_A_INT_EN BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_P2P_RFON_INTMSK BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_CPUMGQ_TX_TIMER_INT_EN BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_TXBCN1ERR_MSK BIT(15) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FS_PS_TIMEOUT2_EN BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_TXBCN1OK_MSK BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FS_PS_TIMEOUT1_EN BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FT_ATIMEND_EMSK BIT(13) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FS_PS_TIMEOUT0_EN BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_BCNDMAINT_EMSK BIT(12) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FS_GTINT12_EN BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_GTINT5_MSK BIT(11) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FS_GTINT11_EN BIT(11) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_EOSP_INT_MSK BIT(10) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FS_GTINT10_EN BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_RX_BCN_E_MSK BIT(9) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FS_GTINT9_EN BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_RPWM_INT_EN BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FS_GTINT8_EN BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_PSTIMER_MSK BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FS_GTINT7_EN BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_TIMEOUT1_MSK BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FS_GTINT6_EN BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_TIMEOUT0_MSK BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FS_GTINT5_EN BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FT_GTINT4_MSK BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FS_GTINT4_EN BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FT_GTINT3_MSK BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FS_GTINT3_EN BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_GTINT2_MSK BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FS_GTINT2_EN BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_GTINT1_MSK BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FS_GTINT1_EN BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_GTINT0_MSK BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTIMR (Offset 0x0138) */ #define BIT_FS_GTINT0_EN BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_GT6INT BIT(31) #define BIT_TX_NULL1_INT BIT(30) #define BIT_TX_NULL0_INT BIT(29) #define BIT_MTI_BCNIVLEAR_INT BIT(28) #define BIT_ATIM_INT BIT(27) #define BIT_WWLAN_INT BIT(26) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PS_TIMER_5_EARLY__INT BIT(26) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_C2H_W_READY BIT(25) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PS_TIMER_4_EARLY__INT BIT(25) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_TRL_MTR_INT BIT(24) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PS_TIMER_3_EARLY__INT BIT(24) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_CLR_PS_STATUS BIT(23) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PS_TIMER_C_EARLY__INT BIT(23) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PS_TIMER_2_EARLY__INT BIT(23) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_RETRIEVE_BUFFERED_INT BIT(22) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PS_TIMER_B_EARLY__INT BIT(22) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PS_TIMER_1_EARLY__INT BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_RPWM2INT BIT(21) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PS_TIMER_A_EARLY__INT BIT(21) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PS_TIMER_0_EARLY__INT BIT(21) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_TSF_BIT32_TOGGLE_INT_V1 BIT(20) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_CPUMGQ_TX_TIMER_EARLY_INT BIT(20) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_TRIGGER_PKT BIT(19) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PS_TIMER_C_INT BIT(19) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PS_TIMER_5_INT BIT(19) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FW_BTCMD_INT BIT(18) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PS_TIMER_B_INT BIT(18) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PS_TIMER_4_INT BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_P2P_RFOFF_INT BIT(17) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PS_TIMER_A_INT BIT(17) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PS_TIMER_3_INT BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_P2P_RFON_INT BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_CPUMGQ_TX_TIMER_INT BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_TX_BCN1ERR_INT BIT(15) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FS_PS_TIMEOUT2_INT BIT(15) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PS_TIMER_2_INT BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_TX_BCN1OK_INT BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FS_PS_TIMEOUT1_INT BIT(14) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PS_TIMER_1_INT BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FT_ATIMEND_E BIT(13) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FS_PS_TIMEOUT0_INT BIT(13) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PS_TIMER_0_INT BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_BCNDMAINT_E_V1 BIT(12) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FS_GTINT12_INT BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_GT5INT BIT(11) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FS_GTINT11_INT BIT(11) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_EOSP_INT BIT(10) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FS_GTINT10_INT BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_RX_BCN_E_INT BIT(9) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FS_GTINT9_INT BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_RPWMINT BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FS_GTINT8_INT BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_PSTIMER_INT BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FS_GTINT7_INT BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_TIMEOUT1_INT BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FS_GTINT6_INT BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_TIMEOUT0_INT BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FS_GTINT5_INT BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FT_GT4INT BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FS_GTINT4_INT BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FT_GT3INT BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FS_GTINT3_INT BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_GT2INT BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FS_GTINT2_INT BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_GT1INT BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FS_GTINT1_INT BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_GT0INT BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTISR (Offset 0x013C) */ #define BIT_FS_GTINT0_INT BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ #define BIT_SHIFT_PKTBUF_WRITE_EN 24 #define BIT_MASK_PKTBUF_WRITE_EN 0xff #define BIT_PKTBUF_WRITE_EN(x) \ (((x) & BIT_MASK_PKTBUF_WRITE_EN) << BIT_SHIFT_PKTBUF_WRITE_EN) #define BITS_PKTBUF_WRITE_EN \ (BIT_MASK_PKTBUF_WRITE_EN << BIT_SHIFT_PKTBUF_WRITE_EN) #define BIT_CLEAR_PKTBUF_WRITE_EN(x) ((x) & (~BITS_PKTBUF_WRITE_EN)) #define BIT_GET_PKTBUF_WRITE_EN(x) \ (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN) & BIT_MASK_PKTBUF_WRITE_EN) #define BIT_SET_PKTBUF_WRITE_EN(x, v) \ (BIT_CLEAR_PKTBUF_WRITE_EN(x) | BIT_PKTBUF_WRITE_EN(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ #define BIT_TXPKT_BUF_READ_EN BIT(23) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ #define BIT_TXRPTBUF_DBG BIT(23) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ #define BIT_TXRPT_BUF_READ_EN BIT(20) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ #define BIT_TXPKTBUF_DBG_V2 BIT(20) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ #define BIT_RXPKT_BUF_READ_EN BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ #define BIT_RXPKTBUF_DBG BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ #define BIT_SHIFT_PKTBUF_ADDR 0 #define BIT_MASK_PKTBUF_ADDR 0x1fff #define BIT_PKTBUF_ADDR(x) \ (((x) & BIT_MASK_PKTBUF_ADDR) << BIT_SHIFT_PKTBUF_ADDR) #define BITS_PKTBUF_ADDR (BIT_MASK_PKTBUF_ADDR << BIT_SHIFT_PKTBUF_ADDR) #define BIT_CLEAR_PKTBUF_ADDR(x) ((x) & (~BITS_PKTBUF_ADDR)) #define BIT_GET_PKTBUF_ADDR(x) \ (((x) >> BIT_SHIFT_PKTBUF_ADDR) & BIT_MASK_PKTBUF_ADDR) #define BIT_SET_PKTBUF_ADDR(x, v) \ (BIT_CLEAR_PKTBUF_ADDR(x) | BIT_PKTBUF_ADDR(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ #define BIT_SHIFT_PKTBUF_DBG_ADDR 0 #define BIT_MASK_PKTBUF_DBG_ADDR 0x1fff #define BIT_PKTBUF_DBG_ADDR(x) \ (((x) & BIT_MASK_PKTBUF_DBG_ADDR) << BIT_SHIFT_PKTBUF_DBG_ADDR) #define BITS_PKTBUF_DBG_ADDR \ (BIT_MASK_PKTBUF_DBG_ADDR << BIT_SHIFT_PKTBUF_DBG_ADDR) #define BIT_CLEAR_PKTBUF_DBG_ADDR(x) ((x) & (~BITS_PKTBUF_DBG_ADDR)) #define BIT_GET_PKTBUF_DBG_ADDR(x) \ (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR) & BIT_MASK_PKTBUF_DBG_ADDR) #define BIT_SET_PKTBUF_DBG_ADDR(x, v) \ (BIT_CLEAR_PKTBUF_DBG_ADDR(x) | BIT_PKTBUF_DBG_ADDR(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PKTBUF_DBG_DATA_L (Offset 0x0144) */ #define BIT_SHIFT_PKTBUF_DBG_DATA_L 0 #define BIT_MASK_PKTBUF_DBG_DATA_L 0xffffffffL #define BIT_PKTBUF_DBG_DATA_L(x) \ (((x) & BIT_MASK_PKTBUF_DBG_DATA_L) << BIT_SHIFT_PKTBUF_DBG_DATA_L) #define BITS_PKTBUF_DBG_DATA_L \ (BIT_MASK_PKTBUF_DBG_DATA_L << BIT_SHIFT_PKTBUF_DBG_DATA_L) #define BIT_CLEAR_PKTBUF_DBG_DATA_L(x) ((x) & (~BITS_PKTBUF_DBG_DATA_L)) #define BIT_GET_PKTBUF_DBG_DATA_L(x) \ (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L) & BIT_MASK_PKTBUF_DBG_DATA_L) #define BIT_SET_PKTBUF_DBG_DATA_L(x, v) \ (BIT_CLEAR_PKTBUF_DBG_DATA_L(x) | BIT_PKTBUF_DBG_DATA_L(v)) /* 2 REG_PKTBUF_DBG_DATA_H (Offset 0x0148) */ #define BIT_SHIFT_PKTBUF_DBG_DATA_H 0 #define BIT_MASK_PKTBUF_DBG_DATA_H 0xffffffffL #define BIT_PKTBUF_DBG_DATA_H(x) \ (((x) & BIT_MASK_PKTBUF_DBG_DATA_H) << BIT_SHIFT_PKTBUF_DBG_DATA_H) #define BITS_PKTBUF_DBG_DATA_H \ (BIT_MASK_PKTBUF_DBG_DATA_H << BIT_SHIFT_PKTBUF_DBG_DATA_H) #define BIT_CLEAR_PKTBUF_DBG_DATA_H(x) ((x) & (~BITS_PKTBUF_DBG_DATA_H)) #define BIT_GET_PKTBUF_DBG_DATA_H(x) \ (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H) & BIT_MASK_PKTBUF_DBG_DATA_H) #define BIT_SET_PKTBUF_DBG_DATA_H(x, v) \ (BIT_CLEAR_PKTBUF_DBG_DATA_H(x) | BIT_PKTBUF_DBG_DATA_H(v)) /* 2 REG_CPWM2 (Offset 0x014C) */ #define BIT_SHIFT_L0S_TO_RCVY_NUM 16 #define BIT_MASK_L0S_TO_RCVY_NUM 0xff #define BIT_L0S_TO_RCVY_NUM(x) \ (((x) & BIT_MASK_L0S_TO_RCVY_NUM) << BIT_SHIFT_L0S_TO_RCVY_NUM) #define BITS_L0S_TO_RCVY_NUM \ (BIT_MASK_L0S_TO_RCVY_NUM << BIT_SHIFT_L0S_TO_RCVY_NUM) #define BIT_CLEAR_L0S_TO_RCVY_NUM(x) ((x) & (~BITS_L0S_TO_RCVY_NUM)) #define BIT_GET_L0S_TO_RCVY_NUM(x) \ (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM) & BIT_MASK_L0S_TO_RCVY_NUM) #define BIT_SET_L0S_TO_RCVY_NUM(x, v) \ (BIT_CLEAR_L0S_TO_RCVY_NUM(x) | BIT_L0S_TO_RCVY_NUM(v)) #define BIT_CPWM2_TOGGLING BIT(15) #define BIT_SHIFT_CPWM2_MOD 0 #define BIT_MASK_CPWM2_MOD 0x7fff #define BIT_CPWM2_MOD(x) (((x) & BIT_MASK_CPWM2_MOD) << BIT_SHIFT_CPWM2_MOD) #define BITS_CPWM2_MOD (BIT_MASK_CPWM2_MOD << BIT_SHIFT_CPWM2_MOD) #define BIT_CLEAR_CPWM2_MOD(x) ((x) & (~BITS_CPWM2_MOD)) #define BIT_GET_CPWM2_MOD(x) (((x) >> BIT_SHIFT_CPWM2_MOD) & BIT_MASK_CPWM2_MOD) #define BIT_SET_CPWM2_MOD(x, v) (BIT_CLEAR_CPWM2_MOD(x) | BIT_CPWM2_MOD(v)) /* 2 REG_TC0_CTRL (Offset 0x0150) */ #define BIT_TC0INT_EN BIT(26) #define BIT_TC0MODE BIT(25) #define BIT_TC0EN BIT(24) #define BIT_SHIFT_TC0DATA 0 #define BIT_MASK_TC0DATA 0xffffff #define BIT_TC0DATA(x) (((x) & BIT_MASK_TC0DATA) << BIT_SHIFT_TC0DATA) #define BITS_TC0DATA (BIT_MASK_TC0DATA << BIT_SHIFT_TC0DATA) #define BIT_CLEAR_TC0DATA(x) ((x) & (~BITS_TC0DATA)) #define BIT_GET_TC0DATA(x) (((x) >> BIT_SHIFT_TC0DATA) & BIT_MASK_TC0DATA) #define BIT_SET_TC0DATA(x, v) (BIT_CLEAR_TC0DATA(x) | BIT_TC0DATA(v)) /* 2 REG_TC1_CTRL (Offset 0x0154) */ #define BIT_TC1INT_EN BIT(26) #define BIT_TC1MODE BIT(25) #define BIT_TC1EN BIT(24) #define BIT_SHIFT_TC1DATA 0 #define BIT_MASK_TC1DATA 0xffffff #define BIT_TC1DATA(x) (((x) & BIT_MASK_TC1DATA) << BIT_SHIFT_TC1DATA) #define BITS_TC1DATA (BIT_MASK_TC1DATA << BIT_SHIFT_TC1DATA) #define BIT_CLEAR_TC1DATA(x) ((x) & (~BITS_TC1DATA)) #define BIT_GET_TC1DATA(x) (((x) >> BIT_SHIFT_TC1DATA) & BIT_MASK_TC1DATA) #define BIT_SET_TC1DATA(x, v) (BIT_CLEAR_TC1DATA(x) | BIT_TC1DATA(v)) /* 2 REG_TC2_CTRL (Offset 0x0158) */ #define BIT_TC2INT_EN BIT(26) #define BIT_TC2MODE BIT(25) #define BIT_TC2EN BIT(24) #define BIT_SHIFT_TC2DATA 0 #define BIT_MASK_TC2DATA 0xffffff #define BIT_TC2DATA(x) (((x) & BIT_MASK_TC2DATA) << BIT_SHIFT_TC2DATA) #define BITS_TC2DATA (BIT_MASK_TC2DATA << BIT_SHIFT_TC2DATA) #define BIT_CLEAR_TC2DATA(x) ((x) & (~BITS_TC2DATA)) #define BIT_GET_TC2DATA(x) (((x) >> BIT_SHIFT_TC2DATA) & BIT_MASK_TC2DATA) #define BIT_SET_TC2DATA(x, v) (BIT_CLEAR_TC2DATA(x) | BIT_TC2DATA(v)) /* 2 REG_TC3_CTRL (Offset 0x015C) */ #define BIT_TC3INT_EN BIT(26) #define BIT_TC3MODE BIT(25) #define BIT_TC3EN BIT(24) #define BIT_SHIFT_TC3DATA 0 #define BIT_MASK_TC3DATA 0xffffff #define BIT_TC3DATA(x) (((x) & BIT_MASK_TC3DATA) << BIT_SHIFT_TC3DATA) #define BITS_TC3DATA (BIT_MASK_TC3DATA << BIT_SHIFT_TC3DATA) #define BIT_CLEAR_TC3DATA(x) ((x) & (~BITS_TC3DATA)) #define BIT_GET_TC3DATA(x) (((x) >> BIT_SHIFT_TC3DATA) & BIT_MASK_TC3DATA) #define BIT_SET_TC3DATA(x, v) (BIT_CLEAR_TC3DATA(x) | BIT_TC3DATA(v)) /* 2 REG_TC4_CTRL (Offset 0x0160) */ #define BIT_TC4INT_EN BIT(26) #define BIT_TC4MODE BIT(25) #define BIT_TC4EN BIT(24) #define BIT_SHIFT_TC4DATA 0 #define BIT_MASK_TC4DATA 0xffffff #define BIT_TC4DATA(x) (((x) & BIT_MASK_TC4DATA) << BIT_SHIFT_TC4DATA) #define BITS_TC4DATA (BIT_MASK_TC4DATA << BIT_SHIFT_TC4DATA) #define BIT_CLEAR_TC4DATA(x) ((x) & (~BITS_TC4DATA)) #define BIT_GET_TC4DATA(x) (((x) >> BIT_SHIFT_TC4DATA) & BIT_MASK_TC4DATA) #define BIT_SET_TC4DATA(x, v) (BIT_CLEAR_TC4DATA(x) | BIT_TC4DATA(v)) /* 2 REG_TCUNIT_BASE (Offset 0x0164) */ #define BIT_SHIFT_TCUNIT_BASE 0 #define BIT_MASK_TCUNIT_BASE 0x3fff #define BIT_TCUNIT_BASE(x) \ (((x) & BIT_MASK_TCUNIT_BASE) << BIT_SHIFT_TCUNIT_BASE) #define BITS_TCUNIT_BASE (BIT_MASK_TCUNIT_BASE << BIT_SHIFT_TCUNIT_BASE) #define BIT_CLEAR_TCUNIT_BASE(x) ((x) & (~BITS_TCUNIT_BASE)) #define BIT_GET_TCUNIT_BASE(x) \ (((x) >> BIT_SHIFT_TCUNIT_BASE) & BIT_MASK_TCUNIT_BASE) #define BIT_SET_TCUNIT_BASE(x, v) \ (BIT_CLEAR_TCUNIT_BASE(x) | BIT_TCUNIT_BASE(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TC5_CTRL (Offset 0x0168) */ #define BIT_TC50INT_EN BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TC5_CTRL (Offset 0x0168) */ #define BIT_TC5INT_EN BIT(26) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TC5_CTRL (Offset 0x0168) */ #define BIT_TC5MODE BIT(25) #define BIT_TC5EN BIT(24) #define BIT_SHIFT_TC5DATA 0 #define BIT_MASK_TC5DATA 0xffffff #define BIT_TC5DATA(x) (((x) & BIT_MASK_TC5DATA) << BIT_SHIFT_TC5DATA) #define BITS_TC5DATA (BIT_MASK_TC5DATA << BIT_SHIFT_TC5DATA) #define BIT_CLEAR_TC5DATA(x) ((x) & (~BITS_TC5DATA)) #define BIT_GET_TC5DATA(x) (((x) >> BIT_SHIFT_TC5DATA) & BIT_MASK_TC5DATA) #define BIT_SET_TC5DATA(x, v) (BIT_CLEAR_TC5DATA(x) | BIT_TC5DATA(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TC6_CTRL (Offset 0x016C) */ #define BIT_TC60INT_EN BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TC6_CTRL (Offset 0x016C) */ #define BIT_TC6INT_EN BIT(26) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TC6_CTRL (Offset 0x016C) */ #define BIT_TC6MODE BIT(25) #define BIT_TC6EN BIT(24) #define BIT_SHIFT_TC6DATA 0 #define BIT_MASK_TC6DATA 0xffffff #define BIT_TC6DATA(x) (((x) & BIT_MASK_TC6DATA) << BIT_SHIFT_TC6DATA) #define BITS_TC6DATA (BIT_MASK_TC6DATA << BIT_SHIFT_TC6DATA) #define BIT_CLEAR_TC6DATA(x) ((x) & (~BITS_TC6DATA)) #define BIT_GET_TC6DATA(x) (((x) >> BIT_SHIFT_TC6DATA) & BIT_MASK_TC6DATA) #define BIT_SET_TC6DATA(x, v) (BIT_CLEAR_TC6DATA(x) | BIT_TC6DATA(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_FAIL (Offset 0x0170) */ #define BIT_SHIFT_8051_MBIST_FAIL 26 #define BIT_MASK_8051_MBIST_FAIL 0x7 #define BIT_8051_MBIST_FAIL(x) \ (((x) & BIT_MASK_8051_MBIST_FAIL) << BIT_SHIFT_8051_MBIST_FAIL) #define BITS_8051_MBIST_FAIL \ (BIT_MASK_8051_MBIST_FAIL << BIT_SHIFT_8051_MBIST_FAIL) #define BIT_CLEAR_8051_MBIST_FAIL(x) ((x) & (~BITS_8051_MBIST_FAIL)) #define BIT_GET_8051_MBIST_FAIL(x) \ (((x) >> BIT_SHIFT_8051_MBIST_FAIL) & BIT_MASK_8051_MBIST_FAIL) #define BIT_SET_8051_MBIST_FAIL(x, v) \ (BIT_CLEAR_8051_MBIST_FAIL(x) | BIT_8051_MBIST_FAIL(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MBIST_DRF_FAIL (Offset 0x0170) */ #define BIT_SHIFT_8051_MBIST_DRF_FAIL 26 #define BIT_MASK_8051_MBIST_DRF_FAIL 0x3f #define BIT_8051_MBIST_DRF_FAIL(x) \ (((x) & BIT_MASK_8051_MBIST_DRF_FAIL) << BIT_SHIFT_8051_MBIST_DRF_FAIL) #define BITS_8051_MBIST_DRF_FAIL \ (BIT_MASK_8051_MBIST_DRF_FAIL << BIT_SHIFT_8051_MBIST_DRF_FAIL) #define BIT_CLEAR_8051_MBIST_DRF_FAIL(x) ((x) & (~BITS_8051_MBIST_DRF_FAIL)) #define BIT_GET_8051_MBIST_DRF_FAIL(x) \ (((x) >> BIT_SHIFT_8051_MBIST_DRF_FAIL) & BIT_MASK_8051_MBIST_DRF_FAIL) #define BIT_SET_8051_MBIST_DRF_FAIL(x, v) \ (BIT_CLEAR_8051_MBIST_DRF_FAIL(x) | BIT_8051_MBIST_DRF_FAIL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_FAIL (Offset 0x0170) */ #define BIT_SHIFT_USB_MBIST_FAIL 24 #define BIT_MASK_USB_MBIST_FAIL 0x3 #define BIT_USB_MBIST_FAIL(x) \ (((x) & BIT_MASK_USB_MBIST_FAIL) << BIT_SHIFT_USB_MBIST_FAIL) #define BITS_USB_MBIST_FAIL \ (BIT_MASK_USB_MBIST_FAIL << BIT_SHIFT_USB_MBIST_FAIL) #define BIT_CLEAR_USB_MBIST_FAIL(x) ((x) & (~BITS_USB_MBIST_FAIL)) #define BIT_GET_USB_MBIST_FAIL(x) \ (((x) >> BIT_SHIFT_USB_MBIST_FAIL) & BIT_MASK_USB_MBIST_FAIL) #define BIT_SET_USB_MBIST_FAIL(x, v) \ (BIT_CLEAR_USB_MBIST_FAIL(x) | BIT_USB_MBIST_FAIL(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MBIST_DRF_FAIL (Offset 0x0170) */ #define BIT_SHIFT_USB_MBIST_DRF_FAIL 24 #define BIT_MASK_USB_MBIST_DRF_FAIL 0x3 #define BIT_USB_MBIST_DRF_FAIL(x) \ (((x) & BIT_MASK_USB_MBIST_DRF_FAIL) << BIT_SHIFT_USB_MBIST_DRF_FAIL) #define BITS_USB_MBIST_DRF_FAIL \ (BIT_MASK_USB_MBIST_DRF_FAIL << BIT_SHIFT_USB_MBIST_DRF_FAIL) #define BIT_CLEAR_USB_MBIST_DRF_FAIL(x) ((x) & (~BITS_USB_MBIST_DRF_FAIL)) #define BIT_GET_USB_MBIST_DRF_FAIL(x) \ (((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL) & BIT_MASK_USB_MBIST_DRF_FAIL) #define BIT_SET_USB_MBIST_DRF_FAIL(x, v) \ (BIT_CLEAR_USB_MBIST_DRF_FAIL(x) | BIT_USB_MBIST_DRF_FAIL(v)) #define BIT_SHIFT_PCIE_MBIST_DRF_FAIL 18 #define BIT_MASK_PCIE_MBIST_DRF_FAIL 0x3f #define BIT_PCIE_MBIST_DRF_FAIL(x) \ (((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL) << BIT_SHIFT_PCIE_MBIST_DRF_FAIL) #define BITS_PCIE_MBIST_DRF_FAIL \ (BIT_MASK_PCIE_MBIST_DRF_FAIL << BIT_SHIFT_PCIE_MBIST_DRF_FAIL) #define BIT_CLEAR_PCIE_MBIST_DRF_FAIL(x) ((x) & (~BITS_PCIE_MBIST_DRF_FAIL)) #define BIT_GET_PCIE_MBIST_DRF_FAIL(x) \ (((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL) & BIT_MASK_PCIE_MBIST_DRF_FAIL) #define BIT_SET_PCIE_MBIST_DRF_FAIL(x, v) \ (BIT_CLEAR_PCIE_MBIST_DRF_FAIL(x) | BIT_PCIE_MBIST_DRF_FAIL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_FAIL (Offset 0x0170) */ #define BIT_SHIFT_PCIE_MBIST_FAIL 16 #define BIT_MASK_PCIE_MBIST_FAIL 0x3f #define BIT_PCIE_MBIST_FAIL(x) \ (((x) & BIT_MASK_PCIE_MBIST_FAIL) << BIT_SHIFT_PCIE_MBIST_FAIL) #define BITS_PCIE_MBIST_FAIL \ (BIT_MASK_PCIE_MBIST_FAIL << BIT_SHIFT_PCIE_MBIST_FAIL) #define BIT_CLEAR_PCIE_MBIST_FAIL(x) ((x) & (~BITS_PCIE_MBIST_FAIL)) #define BIT_GET_PCIE_MBIST_FAIL(x) \ (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL) & BIT_MASK_PCIE_MBIST_FAIL) #define BIT_SET_PCIE_MBIST_FAIL(x, v) \ (BIT_CLEAR_PCIE_MBIST_FAIL(x) | BIT_PCIE_MBIST_FAIL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_FAIL (Offset 0x0170) */ #define BIT_SHIFT_MAC_MBIST_FAIL 0 #define BIT_MASK_MAC_MBIST_FAIL 0xfff #define BIT_MAC_MBIST_FAIL(x) \ (((x) & BIT_MASK_MAC_MBIST_FAIL) << BIT_SHIFT_MAC_MBIST_FAIL) #define BITS_MAC_MBIST_FAIL \ (BIT_MASK_MAC_MBIST_FAIL << BIT_SHIFT_MAC_MBIST_FAIL) #define BIT_CLEAR_MAC_MBIST_FAIL(x) ((x) & (~BITS_MAC_MBIST_FAIL)) #define BIT_GET_MAC_MBIST_FAIL(x) \ (((x) >> BIT_SHIFT_MAC_MBIST_FAIL) & BIT_MASK_MAC_MBIST_FAIL) #define BIT_SET_MAC_MBIST_FAIL(x, v) \ (BIT_CLEAR_MAC_MBIST_FAIL(x) | BIT_MAC_MBIST_FAIL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_MBIST_FAIL (Offset 0x0170) */ #define BIT_SHIFT_MAC_MBIST_FAIL_DRF 0 #define BIT_MASK_MAC_MBIST_FAIL_DRF 0x3ffff #define BIT_MAC_MBIST_FAIL_DRF(x) \ (((x) & BIT_MASK_MAC_MBIST_FAIL_DRF) << BIT_SHIFT_MAC_MBIST_FAIL_DRF) #define BITS_MAC_MBIST_FAIL_DRF \ (BIT_MASK_MAC_MBIST_FAIL_DRF << BIT_SHIFT_MAC_MBIST_FAIL_DRF) #define BIT_CLEAR_MAC_MBIST_FAIL_DRF(x) ((x) & (~BITS_MAC_MBIST_FAIL_DRF)) #define BIT_GET_MAC_MBIST_FAIL_DRF(x) \ (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_DRF) & BIT_MASK_MAC_MBIST_FAIL_DRF) #define BIT_SET_MAC_MBIST_FAIL_DRF(x, v) \ (BIT_CLEAR_MAC_MBIST_FAIL_DRF(x) | BIT_MAC_MBIST_FAIL_DRF(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MBIST_DRF_FAIL (Offset 0x0170) */ #define BIT_SHIFT_MAC_MBIST_DRF_FAIL 0 #define BIT_MASK_MAC_MBIST_DRF_FAIL 0x3ffff #define BIT_MAC_MBIST_DRF_FAIL(x) \ (((x) & BIT_MASK_MAC_MBIST_DRF_FAIL) << BIT_SHIFT_MAC_MBIST_DRF_FAIL) #define BITS_MAC_MBIST_DRF_FAIL \ (BIT_MASK_MAC_MBIST_DRF_FAIL << BIT_SHIFT_MAC_MBIST_DRF_FAIL) #define BIT_CLEAR_MAC_MBIST_DRF_FAIL(x) ((x) & (~BITS_MAC_MBIST_DRF_FAIL)) #define BIT_GET_MAC_MBIST_DRF_FAIL(x) \ (((x) >> BIT_SHIFT_MAC_MBIST_DRF_FAIL) & BIT_MASK_MAC_MBIST_DRF_FAIL) #define BIT_SET_MAC_MBIST_DRF_FAIL(x, v) \ (BIT_CLEAR_MAC_MBIST_DRF_FAIL(x) | BIT_MAC_MBIST_DRF_FAIL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ #define BIT_SHIFT_8051_MBIST_START_PAUSE 26 #define BIT_MASK_8051_MBIST_START_PAUSE 0x7 #define BIT_8051_MBIST_START_PAUSE(x) \ (((x) & BIT_MASK_8051_MBIST_START_PAUSE) \ << BIT_SHIFT_8051_MBIST_START_PAUSE) #define BITS_8051_MBIST_START_PAUSE \ (BIT_MASK_8051_MBIST_START_PAUSE << BIT_SHIFT_8051_MBIST_START_PAUSE) #define BIT_CLEAR_8051_MBIST_START_PAUSE(x) \ ((x) & (~BITS_8051_MBIST_START_PAUSE)) #define BIT_GET_8051_MBIST_START_PAUSE(x) \ (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE) & \ BIT_MASK_8051_MBIST_START_PAUSE) #define BIT_SET_8051_MBIST_START_PAUSE(x, v) \ (BIT_CLEAR_8051_MBIST_START_PAUSE(x) | BIT_8051_MBIST_START_PAUSE(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ #define BIT_SHIFT_8051_MBIST_START_PAUSE_V1 26 #define BIT_MASK_8051_MBIST_START_PAUSE_V1 0x3f #define BIT_8051_MBIST_START_PAUSE_V1(x) \ (((x) & BIT_MASK_8051_MBIST_START_PAUSE_V1) \ << BIT_SHIFT_8051_MBIST_START_PAUSE_V1) #define BITS_8051_MBIST_START_PAUSE_V1 \ (BIT_MASK_8051_MBIST_START_PAUSE_V1 \ << BIT_SHIFT_8051_MBIST_START_PAUSE_V1) #define BIT_CLEAR_8051_MBIST_START_PAUSE_V1(x) \ ((x) & (~BITS_8051_MBIST_START_PAUSE_V1)) #define BIT_GET_8051_MBIST_START_PAUSE_V1(x) \ (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_V1) & \ BIT_MASK_8051_MBIST_START_PAUSE_V1) #define BIT_SET_8051_MBIST_START_PAUSE_V1(x, v) \ (BIT_CLEAR_8051_MBIST_START_PAUSE_V1(x) | \ BIT_8051_MBIST_START_PAUSE_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ #define BIT_SHIFT_USB_MBIST_START_PAUSE 24 #define BIT_MASK_USB_MBIST_START_PAUSE 0x3 #define BIT_USB_MBIST_START_PAUSE(x) \ (((x) & BIT_MASK_USB_MBIST_START_PAUSE) \ << BIT_SHIFT_USB_MBIST_START_PAUSE) #define BITS_USB_MBIST_START_PAUSE \ (BIT_MASK_USB_MBIST_START_PAUSE << BIT_SHIFT_USB_MBIST_START_PAUSE) #define BIT_CLEAR_USB_MBIST_START_PAUSE(x) ((x) & (~BITS_USB_MBIST_START_PAUSE)) #define BIT_GET_USB_MBIST_START_PAUSE(x) \ (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE) & \ BIT_MASK_USB_MBIST_START_PAUSE) #define BIT_SET_USB_MBIST_START_PAUSE(x, v) \ (BIT_CLEAR_USB_MBIST_START_PAUSE(x) | BIT_USB_MBIST_START_PAUSE(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ #define BIT_SHIFT_USB_MBIST_START_PAUSE_V1 24 #define BIT_MASK_USB_MBIST_START_PAUSE_V1 0x3 #define BIT_USB_MBIST_START_PAUSE_V1(x) \ (((x) & BIT_MASK_USB_MBIST_START_PAUSE_V1) \ << BIT_SHIFT_USB_MBIST_START_PAUSE_V1) #define BITS_USB_MBIST_START_PAUSE_V1 \ (BIT_MASK_USB_MBIST_START_PAUSE_V1 \ << BIT_SHIFT_USB_MBIST_START_PAUSE_V1) #define BIT_CLEAR_USB_MBIST_START_PAUSE_V1(x) \ ((x) & (~BITS_USB_MBIST_START_PAUSE_V1)) #define BIT_GET_USB_MBIST_START_PAUSE_V1(x) \ (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V1) & \ BIT_MASK_USB_MBIST_START_PAUSE_V1) #define BIT_SET_USB_MBIST_START_PAUSE_V1(x, v) \ (BIT_CLEAR_USB_MBIST_START_PAUSE_V1(x) | \ BIT_USB_MBIST_START_PAUSE_V1(v)) #define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1 18 #define BIT_MASK_PCIE_MBIST_START_PAUSE_V1 0x3f #define BIT_PCIE_MBIST_START_PAUSE_V1(x) \ (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V1) \ << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1) #define BITS_PCIE_MBIST_START_PAUSE_V1 \ (BIT_MASK_PCIE_MBIST_START_PAUSE_V1 \ << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1) #define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1(x) \ ((x) & (~BITS_PCIE_MBIST_START_PAUSE_V1)) #define BIT_GET_PCIE_MBIST_START_PAUSE_V1(x) \ (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1) & \ BIT_MASK_PCIE_MBIST_START_PAUSE_V1) #define BIT_SET_PCIE_MBIST_START_PAUSE_V1(x, v) \ (BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1(x) | \ BIT_PCIE_MBIST_START_PAUSE_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ #define BIT_SHIFT_PCIE_MBIST_START_PAUSE 16 #define BIT_MASK_PCIE_MBIST_START_PAUSE 0x3f #define BIT_PCIE_MBIST_START_PAUSE(x) \ (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE) \ << BIT_SHIFT_PCIE_MBIST_START_PAUSE) #define BITS_PCIE_MBIST_START_PAUSE \ (BIT_MASK_PCIE_MBIST_START_PAUSE << BIT_SHIFT_PCIE_MBIST_START_PAUSE) #define BIT_CLEAR_PCIE_MBIST_START_PAUSE(x) \ ((x) & (~BITS_PCIE_MBIST_START_PAUSE)) #define BIT_GET_PCIE_MBIST_START_PAUSE(x) \ (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE) & \ BIT_MASK_PCIE_MBIST_START_PAUSE) #define BIT_SET_PCIE_MBIST_START_PAUSE(x, v) \ (BIT_CLEAR_PCIE_MBIST_START_PAUSE(x) | BIT_PCIE_MBIST_START_PAUSE(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ #define BIT_SHIFT_MAC_MBIST_START_PAUSE 0 #define BIT_MASK_MAC_MBIST_START_PAUSE 0xfff #define BIT_MAC_MBIST_START_PAUSE(x) \ (((x) & BIT_MASK_MAC_MBIST_START_PAUSE) \ << BIT_SHIFT_MAC_MBIST_START_PAUSE) #define BITS_MAC_MBIST_START_PAUSE \ (BIT_MASK_MAC_MBIST_START_PAUSE << BIT_SHIFT_MAC_MBIST_START_PAUSE) #define BIT_CLEAR_MAC_MBIST_START_PAUSE(x) ((x) & (~BITS_MAC_MBIST_START_PAUSE)) #define BIT_GET_MAC_MBIST_START_PAUSE(x) \ (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE) & \ BIT_MASK_MAC_MBIST_START_PAUSE) #define BIT_SET_MAC_MBIST_START_PAUSE(x, v) \ (BIT_CLEAR_MAC_MBIST_START_PAUSE(x) | BIT_MAC_MBIST_START_PAUSE(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ #define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1 0 #define BIT_MASK_MAC_MBIST_START_PAUSE_V1 0x3ffff #define BIT_MAC_MBIST_START_PAUSE_V1(x) \ (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1) \ << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1) #define BITS_MAC_MBIST_START_PAUSE_V1 \ (BIT_MASK_MAC_MBIST_START_PAUSE_V1 \ << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1) #define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1(x) \ ((x) & (~BITS_MAC_MBIST_START_PAUSE_V1)) #define BIT_GET_MAC_MBIST_START_PAUSE_V1(x) \ (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1) & \ BIT_MASK_MAC_MBIST_START_PAUSE_V1) #define BIT_SET_MAC_MBIST_START_PAUSE_V1(x, v) \ (BIT_CLEAR_MAC_MBIST_START_PAUSE_V1(x) | \ BIT_MAC_MBIST_START_PAUSE_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_DONE (Offset 0x0178) */ #define BIT_SHIFT_8051_MBIST_DONE 26 #define BIT_MASK_8051_MBIST_DONE 0x7 #define BIT_8051_MBIST_DONE(x) \ (((x) & BIT_MASK_8051_MBIST_DONE) << BIT_SHIFT_8051_MBIST_DONE) #define BITS_8051_MBIST_DONE \ (BIT_MASK_8051_MBIST_DONE << BIT_SHIFT_8051_MBIST_DONE) #define BIT_CLEAR_8051_MBIST_DONE(x) ((x) & (~BITS_8051_MBIST_DONE)) #define BIT_GET_8051_MBIST_DONE(x) \ (((x) >> BIT_SHIFT_8051_MBIST_DONE) & BIT_MASK_8051_MBIST_DONE) #define BIT_SET_8051_MBIST_DONE(x, v) \ (BIT_CLEAR_8051_MBIST_DONE(x) | BIT_8051_MBIST_DONE(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MBIST_DONE (Offset 0x0178) */ #define BIT_SHIFT_8051_MBIST_DONE_V1 26 #define BIT_MASK_8051_MBIST_DONE_V1 0x3f #define BIT_8051_MBIST_DONE_V1(x) \ (((x) & BIT_MASK_8051_MBIST_DONE_V1) << BIT_SHIFT_8051_MBIST_DONE_V1) #define BITS_8051_MBIST_DONE_V1 \ (BIT_MASK_8051_MBIST_DONE_V1 << BIT_SHIFT_8051_MBIST_DONE_V1) #define BIT_CLEAR_8051_MBIST_DONE_V1(x) ((x) & (~BITS_8051_MBIST_DONE_V1)) #define BIT_GET_8051_MBIST_DONE_V1(x) \ (((x) >> BIT_SHIFT_8051_MBIST_DONE_V1) & BIT_MASK_8051_MBIST_DONE_V1) #define BIT_SET_8051_MBIST_DONE_V1(x, v) \ (BIT_CLEAR_8051_MBIST_DONE_V1(x) | BIT_8051_MBIST_DONE_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_DONE (Offset 0x0178) */ #define BIT_SHIFT_USB_MBIST_DONE 24 #define BIT_MASK_USB_MBIST_DONE 0x3 #define BIT_USB_MBIST_DONE(x) \ (((x) & BIT_MASK_USB_MBIST_DONE) << BIT_SHIFT_USB_MBIST_DONE) #define BITS_USB_MBIST_DONE \ (BIT_MASK_USB_MBIST_DONE << BIT_SHIFT_USB_MBIST_DONE) #define BIT_CLEAR_USB_MBIST_DONE(x) ((x) & (~BITS_USB_MBIST_DONE)) #define BIT_GET_USB_MBIST_DONE(x) \ (((x) >> BIT_SHIFT_USB_MBIST_DONE) & BIT_MASK_USB_MBIST_DONE) #define BIT_SET_USB_MBIST_DONE(x, v) \ (BIT_CLEAR_USB_MBIST_DONE(x) | BIT_USB_MBIST_DONE(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MBIST_DONE (Offset 0x0178) */ #define BIT_SHIFT_USB_MBIST_DONE_V1 24 #define BIT_MASK_USB_MBIST_DONE_V1 0x3 #define BIT_USB_MBIST_DONE_V1(x) \ (((x) & BIT_MASK_USB_MBIST_DONE_V1) << BIT_SHIFT_USB_MBIST_DONE_V1) #define BITS_USB_MBIST_DONE_V1 \ (BIT_MASK_USB_MBIST_DONE_V1 << BIT_SHIFT_USB_MBIST_DONE_V1) #define BIT_CLEAR_USB_MBIST_DONE_V1(x) ((x) & (~BITS_USB_MBIST_DONE_V1)) #define BIT_GET_USB_MBIST_DONE_V1(x) \ (((x) >> BIT_SHIFT_USB_MBIST_DONE_V1) & BIT_MASK_USB_MBIST_DONE_V1) #define BIT_SET_USB_MBIST_DONE_V1(x, v) \ (BIT_CLEAR_USB_MBIST_DONE_V1(x) | BIT_USB_MBIST_DONE_V1(v)) #define BIT_SHIFT_PCIE_MBIST_DONE_V1 18 #define BIT_MASK_PCIE_MBIST_DONE_V1 0x3f #define BIT_PCIE_MBIST_DONE_V1(x) \ (((x) & BIT_MASK_PCIE_MBIST_DONE_V1) << BIT_SHIFT_PCIE_MBIST_DONE_V1) #define BITS_PCIE_MBIST_DONE_V1 \ (BIT_MASK_PCIE_MBIST_DONE_V1 << BIT_SHIFT_PCIE_MBIST_DONE_V1) #define BIT_CLEAR_PCIE_MBIST_DONE_V1(x) ((x) & (~BITS_PCIE_MBIST_DONE_V1)) #define BIT_GET_PCIE_MBIST_DONE_V1(x) \ (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V1) & BIT_MASK_PCIE_MBIST_DONE_V1) #define BIT_SET_PCIE_MBIST_DONE_V1(x, v) \ (BIT_CLEAR_PCIE_MBIST_DONE_V1(x) | BIT_PCIE_MBIST_DONE_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_DONE (Offset 0x0178) */ #define BIT_SHIFT_PCIE_MBIST_DONE 16 #define BIT_MASK_PCIE_MBIST_DONE 0x3f #define BIT_PCIE_MBIST_DONE(x) \ (((x) & BIT_MASK_PCIE_MBIST_DONE) << BIT_SHIFT_PCIE_MBIST_DONE) #define BITS_PCIE_MBIST_DONE \ (BIT_MASK_PCIE_MBIST_DONE << BIT_SHIFT_PCIE_MBIST_DONE) #define BIT_CLEAR_PCIE_MBIST_DONE(x) ((x) & (~BITS_PCIE_MBIST_DONE)) #define BIT_GET_PCIE_MBIST_DONE(x) \ (((x) >> BIT_SHIFT_PCIE_MBIST_DONE) & BIT_MASK_PCIE_MBIST_DONE) #define BIT_SET_PCIE_MBIST_DONE(x, v) \ (BIT_CLEAR_PCIE_MBIST_DONE(x) | BIT_PCIE_MBIST_DONE(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_DONE (Offset 0x0178) */ #define BIT_SHIFT_MAC_MBIST_DONE 0 #define BIT_MASK_MAC_MBIST_DONE 0xfff #define BIT_MAC_MBIST_DONE(x) \ (((x) & BIT_MASK_MAC_MBIST_DONE) << BIT_SHIFT_MAC_MBIST_DONE) #define BITS_MAC_MBIST_DONE \ (BIT_MASK_MAC_MBIST_DONE << BIT_SHIFT_MAC_MBIST_DONE) #define BIT_CLEAR_MAC_MBIST_DONE(x) ((x) & (~BITS_MAC_MBIST_DONE)) #define BIT_GET_MAC_MBIST_DONE(x) \ (((x) >> BIT_SHIFT_MAC_MBIST_DONE) & BIT_MASK_MAC_MBIST_DONE) #define BIT_SET_MAC_MBIST_DONE(x, v) \ (BIT_CLEAR_MAC_MBIST_DONE(x) | BIT_MAC_MBIST_DONE(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MBIST_DONE (Offset 0x0178) */ #define BIT_SHIFT_MAC_MBIST_DONE_V1 0 #define BIT_MASK_MAC_MBIST_DONE_V1 0x3ffff #define BIT_MAC_MBIST_DONE_V1(x) \ (((x) & BIT_MASK_MAC_MBIST_DONE_V1) << BIT_SHIFT_MAC_MBIST_DONE_V1) #define BITS_MAC_MBIST_DONE_V1 \ (BIT_MASK_MAC_MBIST_DONE_V1 << BIT_SHIFT_MAC_MBIST_DONE_V1) #define BIT_CLEAR_MAC_MBIST_DONE_V1(x) ((x) & (~BITS_MAC_MBIST_DONE_V1)) #define BIT_GET_MAC_MBIST_DONE_V1(x) \ (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1) & BIT_MASK_MAC_MBIST_DONE_V1) #define BIT_SET_MAC_MBIST_DONE_V1(x, v) \ (BIT_CLEAR_MAC_MBIST_DONE_V1(x) | BIT_MAC_MBIST_DONE_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIST_ROM_CRC_DATA (Offset 0x017C) */ #define BIT_SHIFT_MBIST_ROM_CRC_DATA 0 #define BIT_MASK_MBIST_ROM_CRC_DATA 0xffffffffL #define BIT_MBIST_ROM_CRC_DATA(x) \ (((x) & BIT_MASK_MBIST_ROM_CRC_DATA) << BIT_SHIFT_MBIST_ROM_CRC_DATA) #define BITS_MBIST_ROM_CRC_DATA \ (BIT_MASK_MBIST_ROM_CRC_DATA << BIT_SHIFT_MBIST_ROM_CRC_DATA) #define BIT_CLEAR_MBIST_ROM_CRC_DATA(x) ((x) & (~BITS_MBIST_ROM_CRC_DATA)) #define BIT_GET_MBIST_ROM_CRC_DATA(x) \ (((x) >> BIT_SHIFT_MBIST_ROM_CRC_DATA) & BIT_MASK_MBIST_ROM_CRC_DATA) #define BIT_SET_MBIST_ROM_CRC_DATA(x, v) \ (BIT_CLEAR_MBIST_ROM_CRC_DATA(x) | BIT_MBIST_ROM_CRC_DATA(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_MBIST_FAIL_NRML (Offset 0x017C) */ #define BIT_SHIFT_MBIST_FAIL_NRML_V1 0 #define BIT_MASK_MBIST_FAIL_NRML_V1 0x3ffff #define BIT_MBIST_FAIL_NRML_V1(x) \ (((x) & BIT_MASK_MBIST_FAIL_NRML_V1) << BIT_SHIFT_MBIST_FAIL_NRML_V1) #define BITS_MBIST_FAIL_NRML_V1 \ (BIT_MASK_MBIST_FAIL_NRML_V1 << BIT_SHIFT_MBIST_FAIL_NRML_V1) #define BIT_CLEAR_MBIST_FAIL_NRML_V1(x) ((x) & (~BITS_MBIST_FAIL_NRML_V1)) #define BIT_GET_MBIST_FAIL_NRML_V1(x) \ (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_V1) & BIT_MASK_MBIST_FAIL_NRML_V1) #define BIT_SET_MBIST_FAIL_NRML_V1(x, v) \ (BIT_CLEAR_MBIST_FAIL_NRML_V1(x) | BIT_MBIST_FAIL_NRML_V1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MBIST_FAIL_NRML (Offset 0x017C) */ #define BIT_SHIFT_MBIST_FAIL_NRML 0 #define BIT_MASK_MBIST_FAIL_NRML 0xffffffffL #define BIT_MBIST_FAIL_NRML(x) \ (((x) & BIT_MASK_MBIST_FAIL_NRML) << BIT_SHIFT_MBIST_FAIL_NRML) #define BITS_MBIST_FAIL_NRML \ (BIT_MASK_MBIST_FAIL_NRML << BIT_SHIFT_MBIST_FAIL_NRML) #define BIT_CLEAR_MBIST_FAIL_NRML(x) ((x) & (~BITS_MBIST_FAIL_NRML)) #define BIT_GET_MBIST_FAIL_NRML(x) \ (((x) >> BIT_SHIFT_MBIST_FAIL_NRML) & BIT_MASK_MBIST_FAIL_NRML) #define BIT_SET_MBIST_FAIL_NRML(x, v) \ (BIT_CLEAR_MBIST_FAIL_NRML(x) | BIT_MBIST_FAIL_NRML(v)) #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD 0xffffffffffffffffffffffffffffffffL #define BIT_R_WMAC_IPV6_MYIPAD(x) \ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD) #define BITS_R_WMAC_IPV6_MYIPAD \ (BIT_MASK_R_WMAC_IPV6_MYIPAD << BIT_SHIFT_R_WMAC_IPV6_MYIPAD) #define BIT_CLEAR_R_WMAC_IPV6_MYIPAD(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD)) #define BIT_GET_R_WMAC_IPV6_MYIPAD(x) \ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD) & BIT_MASK_R_WMAC_IPV6_MYIPAD) #define BIT_SET_R_WMAC_IPV6_MYIPAD(x, v) \ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD(x) | BIT_R_WMAC_IPV6_MYIPAD(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MBIST_READ_BIST_RPT (Offset 0x017C) */ #define BIT_SHIFT_MBIST_READ_BIST_RPT 0 #define BIT_MASK_MBIST_READ_BIST_RPT 0xffffffffL #define BIT_MBIST_READ_BIST_RPT(x) \ (((x) & BIT_MASK_MBIST_READ_BIST_RPT) << BIT_SHIFT_MBIST_READ_BIST_RPT) #define BITS_MBIST_READ_BIST_RPT \ (BIT_MASK_MBIST_READ_BIST_RPT << BIT_SHIFT_MBIST_READ_BIST_RPT) #define BIT_CLEAR_MBIST_READ_BIST_RPT(x) ((x) & (~BITS_MBIST_READ_BIST_RPT)) #define BIT_GET_MBIST_READ_BIST_RPT(x) \ (((x) >> BIT_SHIFT_MBIST_READ_BIST_RPT) & BIT_MASK_MBIST_READ_BIST_RPT) #define BIT_SET_MBIST_READ_BIST_RPT(x, v) \ (BIT_CLEAR_MBIST_READ_BIST_RPT(x) | BIT_MBIST_READ_BIST_RPT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_AES_DECRPT_DATA (Offset 0x0180) */ #define BIT_SHIFT_IPS_CFG_ADDR 0 #define BIT_MASK_IPS_CFG_ADDR 0xff #define BIT_IPS_CFG_ADDR(x) \ (((x) & BIT_MASK_IPS_CFG_ADDR) << BIT_SHIFT_IPS_CFG_ADDR) #define BITS_IPS_CFG_ADDR (BIT_MASK_IPS_CFG_ADDR << BIT_SHIFT_IPS_CFG_ADDR) #define BIT_CLEAR_IPS_CFG_ADDR(x) ((x) & (~BITS_IPS_CFG_ADDR)) #define BIT_GET_IPS_CFG_ADDR(x) \ (((x) >> BIT_SHIFT_IPS_CFG_ADDR) & BIT_MASK_IPS_CFG_ADDR) #define BIT_SET_IPS_CFG_ADDR(x, v) \ (BIT_CLEAR_IPS_CFG_ADDR(x) | BIT_IPS_CFG_ADDR(v)) /* 2 REG_AES_DECRPT_CFG (Offset 0x0184) */ #define BIT_SHIFT_IPS_CFG_DATA 0 #define BIT_MASK_IPS_CFG_DATA 0xffffffffL #define BIT_IPS_CFG_DATA(x) \ (((x) & BIT_MASK_IPS_CFG_DATA) << BIT_SHIFT_IPS_CFG_DATA) #define BITS_IPS_CFG_DATA (BIT_MASK_IPS_CFG_DATA << BIT_SHIFT_IPS_CFG_DATA) #define BIT_CLEAR_IPS_CFG_DATA(x) ((x) & (~BITS_IPS_CFG_DATA)) #define BIT_GET_IPS_CFG_DATA(x) \ (((x) >> BIT_SHIFT_IPS_CFG_DATA) & BIT_MASK_IPS_CFG_DATA) #define BIT_SET_IPS_CFG_DATA(x, v) \ (BIT_CLEAR_IPS_CFG_DATA(x) | BIT_IPS_CFG_DATA(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_HIOE_CTRL (Offset 0x0188) */ #define BIT_HIOE_CFG_FILE_LOC_SEL BIT(31) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIOE_CTRL (Offset 0x0188) */ #define BIT_HIOE_WRITE_REQ BIT(30) #define BIT_HIOE_READ_REQ BIT(29) #define BIT_INST_FORMAT_ERR BIT(25) #define BIT_OP_TIMEOUT_ERR BIT(24) #define BIT_SHIFT_HIOE_OP_TIMEOUT 16 #define BIT_MASK_HIOE_OP_TIMEOUT 0xff #define BIT_HIOE_OP_TIMEOUT(x) \ (((x) & BIT_MASK_HIOE_OP_TIMEOUT) << BIT_SHIFT_HIOE_OP_TIMEOUT) #define BITS_HIOE_OP_TIMEOUT \ (BIT_MASK_HIOE_OP_TIMEOUT << BIT_SHIFT_HIOE_OP_TIMEOUT) #define BIT_CLEAR_HIOE_OP_TIMEOUT(x) ((x) & (~BITS_HIOE_OP_TIMEOUT)) #define BIT_GET_HIOE_OP_TIMEOUT(x) \ (((x) >> BIT_SHIFT_HIOE_OP_TIMEOUT) & BIT_MASK_HIOE_OP_TIMEOUT) #define BIT_SET_HIOE_OP_TIMEOUT(x, v) \ (BIT_CLEAR_HIOE_OP_TIMEOUT(x) | BIT_HIOE_OP_TIMEOUT(v)) #define BIT_SHIFT_BITDATA_CHECKSUM 0 #define BIT_MASK_BITDATA_CHECKSUM 0xffff #define BIT_BITDATA_CHECKSUM(x) \ (((x) & BIT_MASK_BITDATA_CHECKSUM) << BIT_SHIFT_BITDATA_CHECKSUM) #define BITS_BITDATA_CHECKSUM \ (BIT_MASK_BITDATA_CHECKSUM << BIT_SHIFT_BITDATA_CHECKSUM) #define BIT_CLEAR_BITDATA_CHECKSUM(x) ((x) & (~BITS_BITDATA_CHECKSUM)) #define BIT_GET_BITDATA_CHECKSUM(x) \ (((x) >> BIT_SHIFT_BITDATA_CHECKSUM) & BIT_MASK_BITDATA_CHECKSUM) #define BIT_SET_BITDATA_CHECKSUM(x, v) \ (BIT_CLEAR_BITDATA_CHECKSUM(x) | BIT_BITDATA_CHECKSUM(v)) /* 2 REG_HIOE_CFG_FILE (Offset 0x018C) */ #define BIT_SHIFT_TXBF_END_ADDR 16 #define BIT_MASK_TXBF_END_ADDR 0xffff #define BIT_TXBF_END_ADDR(x) \ (((x) & BIT_MASK_TXBF_END_ADDR) << BIT_SHIFT_TXBF_END_ADDR) #define BITS_TXBF_END_ADDR (BIT_MASK_TXBF_END_ADDR << BIT_SHIFT_TXBF_END_ADDR) #define BIT_CLEAR_TXBF_END_ADDR(x) ((x) & (~BITS_TXBF_END_ADDR)) #define BIT_GET_TXBF_END_ADDR(x) \ (((x) >> BIT_SHIFT_TXBF_END_ADDR) & BIT_MASK_TXBF_END_ADDR) #define BIT_SET_TXBF_END_ADDR(x, v) \ (BIT_CLEAR_TXBF_END_ADDR(x) | BIT_TXBF_END_ADDR(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_MACCLKFRQ (Offset 0x018C) */ #define BIT_SHIFT_MACCLK_FREQ_LOW32 0 #define BIT_MASK_MACCLK_FREQ_LOW32 0xffffffffL #define BIT_MACCLK_FREQ_LOW32(x) \ (((x) & BIT_MASK_MACCLK_FREQ_LOW32) << BIT_SHIFT_MACCLK_FREQ_LOW32) #define BITS_MACCLK_FREQ_LOW32 \ (BIT_MASK_MACCLK_FREQ_LOW32 << BIT_SHIFT_MACCLK_FREQ_LOW32) #define BIT_CLEAR_MACCLK_FREQ_LOW32(x) ((x) & (~BITS_MACCLK_FREQ_LOW32)) #define BIT_GET_MACCLK_FREQ_LOW32(x) \ (((x) >> BIT_SHIFT_MACCLK_FREQ_LOW32) & BIT_MASK_MACCLK_FREQ_LOW32) #define BIT_SET_MACCLK_FREQ_LOW32(x, v) \ (BIT_CLEAR_MACCLK_FREQ_LOW32(x) | BIT_MACCLK_FREQ_LOW32(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIOE_CFG_FILE (Offset 0x018C) */ #define BIT_SHIFT_TXBF_STR_ADDR 0 #define BIT_MASK_TXBF_STR_ADDR 0xffff #define BIT_TXBF_STR_ADDR(x) \ (((x) & BIT_MASK_TXBF_STR_ADDR) << BIT_SHIFT_TXBF_STR_ADDR) #define BITS_TXBF_STR_ADDR (BIT_MASK_TXBF_STR_ADDR << BIT_SHIFT_TXBF_STR_ADDR) #define BIT_CLEAR_TXBF_STR_ADDR(x) ((x) & (~BITS_TXBF_STR_ADDR)) #define BIT_GET_TXBF_STR_ADDR(x) \ (((x) >> BIT_SHIFT_TXBF_STR_ADDR) & BIT_MASK_TXBF_STR_ADDR) #define BIT_SET_TXBF_STR_ADDR(x, v) \ (BIT_CLEAR_TXBF_STR_ADDR(x) | BIT_TXBF_STR_ADDR(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TMETER (Offset 0x0190) */ #define BIT_TEMP_VALID BIT(31) #define BIT_SHIFT_TEMP_VALUE 24 #define BIT_MASK_TEMP_VALUE 0x3f #define BIT_TEMP_VALUE(x) (((x) & BIT_MASK_TEMP_VALUE) << BIT_SHIFT_TEMP_VALUE) #define BITS_TEMP_VALUE (BIT_MASK_TEMP_VALUE << BIT_SHIFT_TEMP_VALUE) #define BIT_CLEAR_TEMP_VALUE(x) ((x) & (~BITS_TEMP_VALUE)) #define BIT_GET_TEMP_VALUE(x) \ (((x) >> BIT_SHIFT_TEMP_VALUE) & BIT_MASK_TEMP_VALUE) #define BIT_SET_TEMP_VALUE(x, v) (BIT_CLEAR_TEMP_VALUE(x) | BIT_TEMP_VALUE(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_TMETER (Offset 0x0190) */ #define BIT_SHIFT_NCO_OUTCLK_FREQ 12 #define BIT_MASK_NCO_OUTCLK_FREQ 0xfffff #define BIT_NCO_OUTCLK_FREQ(x) \ (((x) & BIT_MASK_NCO_OUTCLK_FREQ) << BIT_SHIFT_NCO_OUTCLK_FREQ) #define BITS_NCO_OUTCLK_FREQ \ (BIT_MASK_NCO_OUTCLK_FREQ << BIT_SHIFT_NCO_OUTCLK_FREQ) #define BIT_CLEAR_NCO_OUTCLK_FREQ(x) ((x) & (~BITS_NCO_OUTCLK_FREQ)) #define BIT_GET_NCO_OUTCLK_FREQ(x) \ (((x) >> BIT_SHIFT_NCO_OUTCLK_FREQ) & BIT_MASK_NCO_OUTCLK_FREQ) #define BIT_SET_NCO_OUTCLK_FREQ(x, v) \ (BIT_CLEAR_NCO_OUTCLK_FREQ(x) | BIT_NCO_OUTCLK_FREQ(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TMETER (Offset 0x0190) */ #define BIT_SHIFT_REG_TMETER_TIMER 8 #define BIT_MASK_REG_TMETER_TIMER 0xfff #define BIT_REG_TMETER_TIMER(x) \ (((x) & BIT_MASK_REG_TMETER_TIMER) << BIT_SHIFT_REG_TMETER_TIMER) #define BITS_REG_TMETER_TIMER \ (BIT_MASK_REG_TMETER_TIMER << BIT_SHIFT_REG_TMETER_TIMER) #define BIT_CLEAR_REG_TMETER_TIMER(x) ((x) & (~BITS_REG_TMETER_TIMER)) #define BIT_GET_REG_TMETER_TIMER(x) \ (((x) >> BIT_SHIFT_REG_TMETER_TIMER) & BIT_MASK_REG_TMETER_TIMER) #define BIT_SET_REG_TMETER_TIMER(x, v) \ (BIT_CLEAR_REG_TMETER_TIMER(x) | BIT_REG_TMETER_TIMER(v)) #define BIT_SHIFT_REG_TEMP_DELTA 2 #define BIT_MASK_REG_TEMP_DELTA 0x3f #define BIT_REG_TEMP_DELTA(x) \ (((x) & BIT_MASK_REG_TEMP_DELTA) << BIT_SHIFT_REG_TEMP_DELTA) #define BITS_REG_TEMP_DELTA \ (BIT_MASK_REG_TEMP_DELTA << BIT_SHIFT_REG_TEMP_DELTA) #define BIT_CLEAR_REG_TEMP_DELTA(x) ((x) & (~BITS_REG_TEMP_DELTA)) #define BIT_GET_REG_TEMP_DELTA(x) \ (((x) >> BIT_SHIFT_REG_TEMP_DELTA) & BIT_MASK_REG_TEMP_DELTA) #define BIT_SET_REG_TEMP_DELTA(x, v) \ (BIT_CLEAR_REG_TEMP_DELTA(x) | BIT_REG_TEMP_DELTA(v)) #define BIT_REG_TMETER_EN BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_TMETER (Offset 0x0190) */ #define BIT_SHIFT_MACCLK_FREQ_HIGH10 0 #define BIT_MASK_MACCLK_FREQ_HIGH10 0x3ff #define BIT_MACCLK_FREQ_HIGH10(x) \ (((x) & BIT_MASK_MACCLK_FREQ_HIGH10) << BIT_SHIFT_MACCLK_FREQ_HIGH10) #define BITS_MACCLK_FREQ_HIGH10 \ (BIT_MASK_MACCLK_FREQ_HIGH10 << BIT_SHIFT_MACCLK_FREQ_HIGH10) #define BIT_CLEAR_MACCLK_FREQ_HIGH10(x) ((x) & (~BITS_MACCLK_FREQ_HIGH10)) #define BIT_GET_MACCLK_FREQ_HIGH10(x) \ (((x) >> BIT_SHIFT_MACCLK_FREQ_HIGH10) & BIT_MASK_MACCLK_FREQ_HIGH10) #define BIT_SET_MACCLK_FREQ_HIGH10(x, v) \ (BIT_CLEAR_MACCLK_FREQ_HIGH10(x) | BIT_MACCLK_FREQ_HIGH10(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ #define BIT_SHIFT_OSC_32K_CLKGEN_0 16 #define BIT_MASK_OSC_32K_CLKGEN_0 0xffff #define BIT_OSC_32K_CLKGEN_0(x) \ (((x) & BIT_MASK_OSC_32K_CLKGEN_0) << BIT_SHIFT_OSC_32K_CLKGEN_0) #define BITS_OSC_32K_CLKGEN_0 \ (BIT_MASK_OSC_32K_CLKGEN_0 << BIT_SHIFT_OSC_32K_CLKGEN_0) #define BIT_CLEAR_OSC_32K_CLKGEN_0(x) ((x) & (~BITS_OSC_32K_CLKGEN_0)) #define BIT_GET_OSC_32K_CLKGEN_0(x) \ (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0) & BIT_MASK_OSC_32K_CLKGEN_0) #define BIT_SET_OSC_32K_CLKGEN_0(x, v) \ (BIT_CLEAR_OSC_32K_CLKGEN_0(x) | BIT_OSC_32K_CLKGEN_0(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ #define BIT_32K_CLK_OUT_RDY BIT(12) #define BIT_SHIFT_MONITOR_CYCLE_LOG2 8 #define BIT_MASK_MONITOR_CYCLE_LOG2 0xf #define BIT_MONITOR_CYCLE_LOG2(x) \ (((x) & BIT_MASK_MONITOR_CYCLE_LOG2) << BIT_SHIFT_MONITOR_CYCLE_LOG2) #define BITS_MONITOR_CYCLE_LOG2 \ (BIT_MASK_MONITOR_CYCLE_LOG2 << BIT_SHIFT_MONITOR_CYCLE_LOG2) #define BIT_CLEAR_MONITOR_CYCLE_LOG2(x) ((x) & (~BITS_MONITOR_CYCLE_LOG2)) #define BIT_GET_MONITOR_CYCLE_LOG2(x) \ (((x) >> BIT_SHIFT_MONITOR_CYCLE_LOG2) & BIT_MASK_MONITOR_CYCLE_LOG2) #define BIT_SET_MONITOR_CYCLE_LOG2(x, v) \ (BIT_CLEAR_MONITOR_CYCLE_LOG2(x) | BIT_MONITOR_CYCLE_LOG2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ #define BIT_SHIFT_OSC_32K_RES_COMP 4 #define BIT_MASK_OSC_32K_RES_COMP 0x3 #define BIT_OSC_32K_RES_COMP(x) \ (((x) & BIT_MASK_OSC_32K_RES_COMP) << BIT_SHIFT_OSC_32K_RES_COMP) #define BITS_OSC_32K_RES_COMP \ (BIT_MASK_OSC_32K_RES_COMP << BIT_SHIFT_OSC_32K_RES_COMP) #define BIT_CLEAR_OSC_32K_RES_COMP(x) ((x) & (~BITS_OSC_32K_RES_COMP)) #define BIT_GET_OSC_32K_RES_COMP(x) \ (((x) >> BIT_SHIFT_OSC_32K_RES_COMP) & BIT_MASK_OSC_32K_RES_COMP) #define BIT_SET_OSC_32K_RES_COMP(x, v) \ (BIT_CLEAR_OSC_32K_RES_COMP(x) | BIT_OSC_32K_RES_COMP(v)) #define BIT_OSC_32K_OUT_SEL BIT(3) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ #define BIT_ISO_WL_2_OSC_32K BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ #define BIT_POW_CKGEN BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ #define BIT_CAL_32K_REG_WR BIT(31) #define BIT_CAL_32K_DBG_SEL BIT(22) #define BIT_SHIFT_CAL_32K_REG_ADDR 16 #define BIT_MASK_CAL_32K_REG_ADDR 0x3f #define BIT_CAL_32K_REG_ADDR(x) \ (((x) & BIT_MASK_CAL_32K_REG_ADDR) << BIT_SHIFT_CAL_32K_REG_ADDR) #define BITS_CAL_32K_REG_ADDR \ (BIT_MASK_CAL_32K_REG_ADDR << BIT_SHIFT_CAL_32K_REG_ADDR) #define BIT_CLEAR_CAL_32K_REG_ADDR(x) ((x) & (~BITS_CAL_32K_REG_ADDR)) #define BIT_GET_CAL_32K_REG_ADDR(x) \ (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR) & BIT_MASK_CAL_32K_REG_ADDR) #define BIT_SET_CAL_32K_REG_ADDR(x, v) \ (BIT_CLEAR_CAL_32K_REG_ADDR(x) | BIT_CAL_32K_REG_ADDR(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ #define BIT_SHIFT_FREQVALUE_UNREGCLK 8 #define BIT_MASK_FREQVALUE_UNREGCLK 0xffffff #define BIT_FREQVALUE_UNREGCLK(x) \ (((x) & BIT_MASK_FREQVALUE_UNREGCLK) << BIT_SHIFT_FREQVALUE_UNREGCLK) #define BITS_FREQVALUE_UNREGCLK \ (BIT_MASK_FREQVALUE_UNREGCLK << BIT_SHIFT_FREQVALUE_UNREGCLK) #define BIT_CLEAR_FREQVALUE_UNREGCLK(x) ((x) & (~BITS_FREQVALUE_UNREGCLK)) #define BIT_GET_FREQVALUE_UNREGCLK(x) \ (((x) >> BIT_SHIFT_FREQVALUE_UNREGCLK) & BIT_MASK_FREQVALUE_UNREGCLK) #define BIT_SET_FREQVALUE_UNREGCLK(x, v) \ (BIT_CLEAR_FREQVALUE_UNREGCLK(x) | BIT_FREQVALUE_UNREGCLK(v)) #define BIT_CAL32K_DBGMOD BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ #define BIT_SHIFT_CAL_32K_REG_DATA 0 #define BIT_MASK_CAL_32K_REG_DATA 0xffff #define BIT_CAL_32K_REG_DATA(x) \ (((x) & BIT_MASK_CAL_32K_REG_DATA) << BIT_SHIFT_CAL_32K_REG_DATA) #define BITS_CAL_32K_REG_DATA \ (BIT_MASK_CAL_32K_REG_DATA << BIT_SHIFT_CAL_32K_REG_DATA) #define BIT_CLEAR_CAL_32K_REG_DATA(x) ((x) & (~BITS_CAL_32K_REG_DATA)) #define BIT_GET_CAL_32K_REG_DATA(x) \ (((x) >> BIT_SHIFT_CAL_32K_REG_DATA) & BIT_MASK_CAL_32K_REG_DATA) #define BIT_SET_CAL_32K_REG_DATA(x, v) \ (BIT_CLEAR_CAL_32K_REG_DATA(x) | BIT_CAL_32K_REG_DATA(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ #define BIT_SHIFT_NCO_THRS 0 #define BIT_MASK_NCO_THRS 0x7f #define BIT_NCO_THRS(x) (((x) & BIT_MASK_NCO_THRS) << BIT_SHIFT_NCO_THRS) #define BITS_NCO_THRS (BIT_MASK_NCO_THRS << BIT_SHIFT_NCO_THRS) #define BIT_CLEAR_NCO_THRS(x) ((x) & (~BITS_NCO_THRS)) #define BIT_GET_NCO_THRS(x) (((x) >> BIT_SHIFT_NCO_THRS) & BIT_MASK_NCO_THRS) #define BIT_SET_NCO_THRS(x, v) (BIT_CLEAR_NCO_THRS(x) | BIT_NCO_THRS(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_C2HEVT (Offset 0x01A0) */ #define BIT_SHIFT_C2HEVT_MSG 0 #define BIT_MASK_C2HEVT_MSG 0xffffffffffffffffffffffffffffffffL #define BIT_C2HEVT_MSG(x) (((x) & BIT_MASK_C2HEVT_MSG) << BIT_SHIFT_C2HEVT_MSG) #define BITS_C2HEVT_MSG (BIT_MASK_C2HEVT_MSG << BIT_SHIFT_C2HEVT_MSG) #define BIT_CLEAR_C2HEVT_MSG(x) ((x) & (~BITS_C2HEVT_MSG)) #define BIT_GET_C2HEVT_MSG(x) \ (((x) >> BIT_SHIFT_C2HEVT_MSG) & BIT_MASK_C2HEVT_MSG) #define BIT_SET_C2HEVT_MSG(x, v) (BIT_CLEAR_C2HEVT_MSG(x) | BIT_C2HEVT_MSG(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_C2HEVT (Offset 0x01A0) */ #define BIT_SHIFT_C2HEVT_MSG_V1 0 #define BIT_MASK_C2HEVT_MSG_V1 0xffffffffL #define BIT_C2HEVT_MSG_V1(x) \ (((x) & BIT_MASK_C2HEVT_MSG_V1) << BIT_SHIFT_C2HEVT_MSG_V1) #define BITS_C2HEVT_MSG_V1 (BIT_MASK_C2HEVT_MSG_V1 << BIT_SHIFT_C2HEVT_MSG_V1) #define BIT_CLEAR_C2HEVT_MSG_V1(x) ((x) & (~BITS_C2HEVT_MSG_V1)) #define BIT_GET_C2HEVT_MSG_V1(x) \ (((x) >> BIT_SHIFT_C2HEVT_MSG_V1) & BIT_MASK_C2HEVT_MSG_V1) #define BIT_SET_C2HEVT_MSG_V1(x, v) \ (BIT_CLEAR_C2HEVT_MSG_V1(x) | BIT_C2HEVT_MSG_V1(v)) /* 2 REG_C2HEVT_1 (Offset 0x01A4) */ #define BIT_SHIFT_C2HEVT_MSG_1 0 #define BIT_MASK_C2HEVT_MSG_1 0xffffffffL #define BIT_C2HEVT_MSG_1(x) \ (((x) & BIT_MASK_C2HEVT_MSG_1) << BIT_SHIFT_C2HEVT_MSG_1) #define BITS_C2HEVT_MSG_1 (BIT_MASK_C2HEVT_MSG_1 << BIT_SHIFT_C2HEVT_MSG_1) #define BIT_CLEAR_C2HEVT_MSG_1(x) ((x) & (~BITS_C2HEVT_MSG_1)) #define BIT_GET_C2HEVT_MSG_1(x) \ (((x) >> BIT_SHIFT_C2HEVT_MSG_1) & BIT_MASK_C2HEVT_MSG_1) #define BIT_SET_C2HEVT_MSG_1(x, v) \ (BIT_CLEAR_C2HEVT_MSG_1(x) | BIT_C2HEVT_MSG_1(v)) /* 2 REG_C2HEVT_2 (Offset 0x01A8) */ #define BIT_SHIFT_C2HEVT_MSG_2 0 #define BIT_MASK_C2HEVT_MSG_2 0xffffffffL #define BIT_C2HEVT_MSG_2(x) \ (((x) & BIT_MASK_C2HEVT_MSG_2) << BIT_SHIFT_C2HEVT_MSG_2) #define BITS_C2HEVT_MSG_2 (BIT_MASK_C2HEVT_MSG_2 << BIT_SHIFT_C2HEVT_MSG_2) #define BIT_CLEAR_C2HEVT_MSG_2(x) ((x) & (~BITS_C2HEVT_MSG_2)) #define BIT_GET_C2HEVT_MSG_2(x) \ (((x) >> BIT_SHIFT_C2HEVT_MSG_2) & BIT_MASK_C2HEVT_MSG_2) #define BIT_SET_C2HEVT_MSG_2(x, v) \ (BIT_CLEAR_C2HEVT_MSG_2(x) | BIT_C2HEVT_MSG_2(v)) /* 2 REG_C2HEVT_3 (Offset 0x01AC) */ #define BIT_SHIFT_C2HEVT_MSG_3 0 #define BIT_MASK_C2HEVT_MSG_3 0xffffffffL #define BIT_C2HEVT_MSG_3(x) \ (((x) & BIT_MASK_C2HEVT_MSG_3) << BIT_SHIFT_C2HEVT_MSG_3) #define BITS_C2HEVT_MSG_3 (BIT_MASK_C2HEVT_MSG_3 << BIT_SHIFT_C2HEVT_MSG_3) #define BIT_CLEAR_C2HEVT_MSG_3(x) ((x) & (~BITS_C2HEVT_MSG_3)) #define BIT_GET_C2HEVT_MSG_3(x) \ (((x) >> BIT_SHIFT_C2HEVT_MSG_3) & BIT_MASK_C2HEVT_MSG_3) #define BIT_SET_C2HEVT_MSG_3(x, v) \ (BIT_CLEAR_C2HEVT_MSG_3(x) | BIT_C2HEVT_MSG_3(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TC7_CTRL (Offset 0x01B0) */ #define BIT_TC7INT_EN BIT(26) #define BIT_TC7MODE BIT(25) #define BIT_TC7EN BIT(24) #define BIT_SHIFT_TC7DATA 0 #define BIT_MASK_TC7DATA 0xffffff #define BIT_TC7DATA(x) (((x) & BIT_MASK_TC7DATA) << BIT_SHIFT_TC7DATA) #define BITS_TC7DATA (BIT_MASK_TC7DATA << BIT_SHIFT_TC7DATA) #define BIT_CLEAR_TC7DATA(x) ((x) & (~BITS_TC7DATA)) #define BIT_GET_TC7DATA(x) (((x) >> BIT_SHIFT_TC7DATA) & BIT_MASK_TC7DATA) #define BIT_SET_TC7DATA(x, v) (BIT_CLEAR_TC7DATA(x) | BIT_TC7DATA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_RXDESC_BUFF_RPTR (Offset 0x01B0) */ #define BIT_SHIFT_RXDESC_BUFF_RPTR 0 #define BIT_MASK_RXDESC_BUFF_RPTR 0xffffffffL #define BIT_RXDESC_BUFF_RPTR(x) \ (((x) & BIT_MASK_RXDESC_BUFF_RPTR) << BIT_SHIFT_RXDESC_BUFF_RPTR) #define BITS_RXDESC_BUFF_RPTR \ (BIT_MASK_RXDESC_BUFF_RPTR << BIT_SHIFT_RXDESC_BUFF_RPTR) #define BIT_CLEAR_RXDESC_BUFF_RPTR(x) ((x) & (~BITS_RXDESC_BUFF_RPTR)) #define BIT_GET_RXDESC_BUFF_RPTR(x) \ (((x) >> BIT_SHIFT_RXDESC_BUFF_RPTR) & BIT_MASK_RXDESC_BUFF_RPTR) #define BIT_SET_RXDESC_BUFF_RPTR(x, v) \ (BIT_CLEAR_RXDESC_BUFF_RPTR(x) | BIT_RXDESC_BUFF_RPTR(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TC8_CTRL (Offset 0x01B4) */ #define BIT_TC8INT_EN BIT(26) #define BIT_TC8MODE BIT(25) #define BIT_TC8EN BIT(24) #define BIT_SHIFT_TC8DATA 0 #define BIT_MASK_TC8DATA 0xffffff #define BIT_TC8DATA(x) (((x) & BIT_MASK_TC8DATA) << BIT_SHIFT_TC8DATA) #define BITS_TC8DATA (BIT_MASK_TC8DATA << BIT_SHIFT_TC8DATA) #define BIT_CLEAR_TC8DATA(x) ((x) & (~BITS_TC8DATA)) #define BIT_GET_TC8DATA(x) (((x) >> BIT_SHIFT_TC8DATA) & BIT_MASK_TC8DATA) #define BIT_SET_TC8DATA(x, v) (BIT_CLEAR_TC8DATA(x) | BIT_TC8DATA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_RXDESC_BUFF_WPTR (Offset 0x01B4) */ #define BIT_SHIFT_RXDESC_BUFF_WPTR 0 #define BIT_MASK_RXDESC_BUFF_WPTR 0xffffffffL #define BIT_RXDESC_BUFF_WPTR(x) \ (((x) & BIT_MASK_RXDESC_BUFF_WPTR) << BIT_SHIFT_RXDESC_BUFF_WPTR) #define BITS_RXDESC_BUFF_WPTR \ (BIT_MASK_RXDESC_BUFF_WPTR << BIT_SHIFT_RXDESC_BUFF_WPTR) #define BIT_CLEAR_RXDESC_BUFF_WPTR(x) ((x) & (~BITS_RXDESC_BUFF_WPTR)) #define BIT_GET_RXDESC_BUFF_WPTR(x) \ (((x) >> BIT_SHIFT_RXDESC_BUFF_WPTR) & BIT_MASK_RXDESC_BUFF_WPTR) #define BIT_SET_RXDESC_BUFF_WPTR(x, v) \ (BIT_CLEAR_RXDESC_BUFF_WPTR(x) | BIT_RXDESC_BUFF_WPTR(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SW_DEFINED_PAGE1 (Offset 0x01B8) */ #define BIT_SHIFT_SW_DEFINED_PAGE1 0 #define BIT_MASK_SW_DEFINED_PAGE1 0xffffffffffffffffL #define BIT_SW_DEFINED_PAGE1(x) \ (((x) & BIT_MASK_SW_DEFINED_PAGE1) << BIT_SHIFT_SW_DEFINED_PAGE1) #define BITS_SW_DEFINED_PAGE1 \ (BIT_MASK_SW_DEFINED_PAGE1 << BIT_SHIFT_SW_DEFINED_PAGE1) #define BIT_CLEAR_SW_DEFINED_PAGE1(x) ((x) & (~BITS_SW_DEFINED_PAGE1)) #define BIT_GET_SW_DEFINED_PAGE1(x) \ (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1) & BIT_MASK_SW_DEFINED_PAGE1) #define BIT_SET_SW_DEFINED_PAGE1(x, v) \ (BIT_CLEAR_SW_DEFINED_PAGE1(x) | BIT_SW_DEFINED_PAGE1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SW_DEFINED_PAGE1 (Offset 0x01B8) */ #define BIT_SHIFT_SW_DEFINED_PAGE1_V1 0 #define BIT_MASK_SW_DEFINED_PAGE1_V1 0xffffffffL #define BIT_SW_DEFINED_PAGE1_V1(x) \ (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1) << BIT_SHIFT_SW_DEFINED_PAGE1_V1) #define BITS_SW_DEFINED_PAGE1_V1 \ (BIT_MASK_SW_DEFINED_PAGE1_V1 << BIT_SHIFT_SW_DEFINED_PAGE1_V1) #define BIT_CLEAR_SW_DEFINED_PAGE1_V1(x) ((x) & (~BITS_SW_DEFINED_PAGE1_V1)) #define BIT_GET_SW_DEFINED_PAGE1_V1(x) \ (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1) & BIT_MASK_SW_DEFINED_PAGE1_V1) #define BIT_SET_SW_DEFINED_PAGE1_V1(x, v) \ (BIT_CLEAR_SW_DEFINED_PAGE1_V1(x) | BIT_SW_DEFINED_PAGE1_V1(v)) /* 2 REG_SW_DEFINED_PAGE2 (Offset 0x01BC) */ #define BIT_SHIFT_SW_DEFINED_PAGE2 0 #define BIT_MASK_SW_DEFINED_PAGE2 0xffffffffL #define BIT_SW_DEFINED_PAGE2(x) \ (((x) & BIT_MASK_SW_DEFINED_PAGE2) << BIT_SHIFT_SW_DEFINED_PAGE2) #define BITS_SW_DEFINED_PAGE2 \ (BIT_MASK_SW_DEFINED_PAGE2 << BIT_SHIFT_SW_DEFINED_PAGE2) #define BIT_CLEAR_SW_DEFINED_PAGE2(x) ((x) & (~BITS_SW_DEFINED_PAGE2)) #define BIT_GET_SW_DEFINED_PAGE2(x) \ (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2) & BIT_MASK_SW_DEFINED_PAGE2) #define BIT_SET_SW_DEFINED_PAGE2(x, v) \ (BIT_CLEAR_SW_DEFINED_PAGE2(x) | BIT_SW_DEFINED_PAGE2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MCUTST_I (Offset 0x01C0) */ #define BIT_SHIFT_MCUDMSG_I 0 #define BIT_MASK_MCUDMSG_I 0xffffffffL #define BIT_MCUDMSG_I(x) (((x) & BIT_MASK_MCUDMSG_I) << BIT_SHIFT_MCUDMSG_I) #define BITS_MCUDMSG_I (BIT_MASK_MCUDMSG_I << BIT_SHIFT_MCUDMSG_I) #define BIT_CLEAR_MCUDMSG_I(x) ((x) & (~BITS_MCUDMSG_I)) #define BIT_GET_MCUDMSG_I(x) (((x) >> BIT_SHIFT_MCUDMSG_I) & BIT_MASK_MCUDMSG_I) #define BIT_SET_MCUDMSG_I(x, v) (BIT_CLEAR_MCUDMSG_I(x) | BIT_MCUDMSG_I(v)) /* 2 REG_MCUTST_II (Offset 0x01C4) */ #define BIT_SHIFT_MCUDMSG_II 0 #define BIT_MASK_MCUDMSG_II 0xffffffffL #define BIT_MCUDMSG_II(x) (((x) & BIT_MASK_MCUDMSG_II) << BIT_SHIFT_MCUDMSG_II) #define BITS_MCUDMSG_II (BIT_MASK_MCUDMSG_II << BIT_SHIFT_MCUDMSG_II) #define BIT_CLEAR_MCUDMSG_II(x) ((x) & (~BITS_MCUDMSG_II)) #define BIT_GET_MCUDMSG_II(x) \ (((x) >> BIT_SHIFT_MCUDMSG_II) & BIT_MASK_MCUDMSG_II) #define BIT_SET_MCUDMSG_II(x, v) (BIT_CLEAR_MCUDMSG_II(x) | BIT_MCUDMSG_II(v)) /* 2 REG_FMETHR (Offset 0x01C8) */ #define BIT_FMSG_INT BIT(31) #define BIT_SHIFT_FW_MSG 0 #define BIT_MASK_FW_MSG 0xffffffffL #define BIT_FW_MSG(x) (((x) & BIT_MASK_FW_MSG) << BIT_SHIFT_FW_MSG) #define BITS_FW_MSG (BIT_MASK_FW_MSG << BIT_SHIFT_FW_MSG) #define BIT_CLEAR_FW_MSG(x) ((x) & (~BITS_FW_MSG)) #define BIT_GET_FW_MSG(x) (((x) >> BIT_SHIFT_FW_MSG) & BIT_MASK_FW_MSG) #define BIT_SET_FW_MSG(x, v) (BIT_CLEAR_FW_MSG(x) | BIT_FW_MSG(v)) /* 2 REG_HMETFR (Offset 0x01CC) */ #define BIT_SHIFT_HRCV_MSG 24 #define BIT_MASK_HRCV_MSG 0xff #define BIT_HRCV_MSG(x) (((x) & BIT_MASK_HRCV_MSG) << BIT_SHIFT_HRCV_MSG) #define BITS_HRCV_MSG (BIT_MASK_HRCV_MSG << BIT_SHIFT_HRCV_MSG) #define BIT_CLEAR_HRCV_MSG(x) ((x) & (~BITS_HRCV_MSG)) #define BIT_GET_HRCV_MSG(x) (((x) >> BIT_SHIFT_HRCV_MSG) & BIT_MASK_HRCV_MSG) #define BIT_SET_HRCV_MSG(x, v) (BIT_CLEAR_HRCV_MSG(x) | BIT_HRCV_MSG(v)) #define BIT_INT_BOX3 BIT(3) #define BIT_INT_BOX2 BIT(2) #define BIT_INT_BOX1 BIT(1) #define BIT_INT_BOX0 BIT(0) /* 2 REG_HMEBOX0 (Offset 0x01D0) */ #define BIT_SHIFT_HOST_MSG_0 0 #define BIT_MASK_HOST_MSG_0 0xffffffffL #define BIT_HOST_MSG_0(x) (((x) & BIT_MASK_HOST_MSG_0) << BIT_SHIFT_HOST_MSG_0) #define BITS_HOST_MSG_0 (BIT_MASK_HOST_MSG_0 << BIT_SHIFT_HOST_MSG_0) #define BIT_CLEAR_HOST_MSG_0(x) ((x) & (~BITS_HOST_MSG_0)) #define BIT_GET_HOST_MSG_0(x) \ (((x) >> BIT_SHIFT_HOST_MSG_0) & BIT_MASK_HOST_MSG_0) #define BIT_SET_HOST_MSG_0(x, v) (BIT_CLEAR_HOST_MSG_0(x) | BIT_HOST_MSG_0(v)) /* 2 REG_HMEBOX1 (Offset 0x01D4) */ #define BIT_SHIFT_HOST_MSG_1 0 #define BIT_MASK_HOST_MSG_1 0xffffffffL #define BIT_HOST_MSG_1(x) (((x) & BIT_MASK_HOST_MSG_1) << BIT_SHIFT_HOST_MSG_1) #define BITS_HOST_MSG_1 (BIT_MASK_HOST_MSG_1 << BIT_SHIFT_HOST_MSG_1) #define BIT_CLEAR_HOST_MSG_1(x) ((x) & (~BITS_HOST_MSG_1)) #define BIT_GET_HOST_MSG_1(x) \ (((x) >> BIT_SHIFT_HOST_MSG_1) & BIT_MASK_HOST_MSG_1) #define BIT_SET_HOST_MSG_1(x, v) (BIT_CLEAR_HOST_MSG_1(x) | BIT_HOST_MSG_1(v)) /* 2 REG_HMEBOX2 (Offset 0x01D8) */ #define BIT_SHIFT_HOST_MSG_2 0 #define BIT_MASK_HOST_MSG_2 0xffffffffL #define BIT_HOST_MSG_2(x) (((x) & BIT_MASK_HOST_MSG_2) << BIT_SHIFT_HOST_MSG_2) #define BITS_HOST_MSG_2 (BIT_MASK_HOST_MSG_2 << BIT_SHIFT_HOST_MSG_2) #define BIT_CLEAR_HOST_MSG_2(x) ((x) & (~BITS_HOST_MSG_2)) #define BIT_GET_HOST_MSG_2(x) \ (((x) >> BIT_SHIFT_HOST_MSG_2) & BIT_MASK_HOST_MSG_2) #define BIT_SET_HOST_MSG_2(x, v) (BIT_CLEAR_HOST_MSG_2(x) | BIT_HOST_MSG_2(v)) /* 2 REG_HMEBOX3 (Offset 0x01DC) */ #define BIT_SHIFT_HOST_MSG_3 0 #define BIT_MASK_HOST_MSG_3 0xffffffffL #define BIT_HOST_MSG_3(x) (((x) & BIT_MASK_HOST_MSG_3) << BIT_SHIFT_HOST_MSG_3) #define BITS_HOST_MSG_3 (BIT_MASK_HOST_MSG_3 << BIT_SHIFT_HOST_MSG_3) #define BIT_CLEAR_HOST_MSG_3(x) ((x) & (~BITS_HOST_MSG_3)) #define BIT_GET_HOST_MSG_3(x) \ (((x) >> BIT_SHIFT_HOST_MSG_3) & BIT_MASK_HOST_MSG_3) #define BIT_SET_HOST_MSG_3(x, v) (BIT_CLEAR_HOST_MSG_3(x) | BIT_HOST_MSG_3(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_LLT_INIT (Offset 0x01E0) */ #define BIT_SHIFT_LLTE_RWM 30 #define BIT_MASK_LLTE_RWM 0x3 #define BIT_LLTE_RWM(x) (((x) & BIT_MASK_LLTE_RWM) << BIT_SHIFT_LLTE_RWM) #define BITS_LLTE_RWM (BIT_MASK_LLTE_RWM << BIT_SHIFT_LLTE_RWM) #define BIT_CLEAR_LLTE_RWM(x) ((x) & (~BITS_LLTE_RWM)) #define BIT_GET_LLTE_RWM(x) (((x) >> BIT_SHIFT_LLTE_RWM) & BIT_MASK_LLTE_RWM) #define BIT_SET_LLTE_RWM(x, v) (BIT_CLEAR_LLTE_RWM(x) | BIT_LLTE_RWM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_RXDESC_BUFF_BNDY (Offset 0x01E0) */ #define BIT_FW_FIFO_PTR_RST BIT(18) #define BIT_PHY_FIFO_PTR_RST BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LLT_INIT (Offset 0x01E0) */ #define BIT_SHIFT_LLTINI_PDATA 16 #define BIT_MASK_LLTINI_PDATA 0xff #define BIT_LLTINI_PDATA(x) \ (((x) & BIT_MASK_LLTINI_PDATA) << BIT_SHIFT_LLTINI_PDATA) #define BITS_LLTINI_PDATA (BIT_MASK_LLTINI_PDATA << BIT_SHIFT_LLTINI_PDATA) #define BIT_CLEAR_LLTINI_PDATA(x) ((x) & (~BITS_LLTINI_PDATA)) #define BIT_GET_LLTINI_PDATA(x) \ (((x) >> BIT_SHIFT_LLTINI_PDATA) & BIT_MASK_LLTINI_PDATA) #define BIT_SET_LLTINI_PDATA(x, v) \ (BIT_CLEAR_LLTINI_PDATA(x) | BIT_LLTINI_PDATA(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LLT_INIT (Offset 0x01E0) */ #define BIT_SHIFT_LLTINI_PDATA_V1 16 #define BIT_MASK_LLTINI_PDATA_V1 0xfff #define BIT_LLTINI_PDATA_V1(x) \ (((x) & BIT_MASK_LLTINI_PDATA_V1) << BIT_SHIFT_LLTINI_PDATA_V1) #define BITS_LLTINI_PDATA_V1 \ (BIT_MASK_LLTINI_PDATA_V1 << BIT_SHIFT_LLTINI_PDATA_V1) #define BIT_CLEAR_LLTINI_PDATA_V1(x) ((x) & (~BITS_LLTINI_PDATA_V1)) #define BIT_GET_LLTINI_PDATA_V1(x) \ (((x) >> BIT_SHIFT_LLTINI_PDATA_V1) & BIT_MASK_LLTINI_PDATA_V1) #define BIT_SET_LLTINI_PDATA_V1(x, v) \ (BIT_CLEAR_LLTINI_PDATA_V1(x) | BIT_LLTINI_PDATA_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LLT_INIT (Offset 0x01E0) */ #define BIT_SHIFT_LLTINI_ADDR 8 #define BIT_MASK_LLTINI_ADDR 0xff #define BIT_LLTINI_ADDR(x) \ (((x) & BIT_MASK_LLTINI_ADDR) << BIT_SHIFT_LLTINI_ADDR) #define BITS_LLTINI_ADDR (BIT_MASK_LLTINI_ADDR << BIT_SHIFT_LLTINI_ADDR) #define BIT_CLEAR_LLTINI_ADDR(x) ((x) & (~BITS_LLTINI_ADDR)) #define BIT_GET_LLTINI_ADDR(x) \ (((x) >> BIT_SHIFT_LLTINI_ADDR) & BIT_MASK_LLTINI_ADDR) #define BIT_SET_LLTINI_ADDR(x, v) \ (BIT_CLEAR_LLTINI_ADDR(x) | BIT_LLTINI_ADDR(v)) #define BIT_SHIFT_LLTINI_HDATA 0 #define BIT_MASK_LLTINI_HDATA 0xff #define BIT_LLTINI_HDATA(x) \ (((x) & BIT_MASK_LLTINI_HDATA) << BIT_SHIFT_LLTINI_HDATA) #define BITS_LLTINI_HDATA (BIT_MASK_LLTINI_HDATA << BIT_SHIFT_LLTINI_HDATA) #define BIT_CLEAR_LLTINI_HDATA(x) ((x) & (~BITS_LLTINI_HDATA)) #define BIT_GET_LLTINI_HDATA(x) \ (((x) >> BIT_SHIFT_LLTINI_HDATA) & BIT_MASK_LLTINI_HDATA) #define BIT_SET_LLTINI_HDATA(x, v) \ (BIT_CLEAR_LLTINI_HDATA(x) | BIT_LLTINI_HDATA(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LLT_INIT (Offset 0x01E0) */ #define BIT_SHIFT_LLTINI_HDATA_V1 0 #define BIT_MASK_LLTINI_HDATA_V1 0xfff #define BIT_LLTINI_HDATA_V1(x) \ (((x) & BIT_MASK_LLTINI_HDATA_V1) << BIT_SHIFT_LLTINI_HDATA_V1) #define BITS_LLTINI_HDATA_V1 \ (BIT_MASK_LLTINI_HDATA_V1 << BIT_SHIFT_LLTINI_HDATA_V1) #define BIT_CLEAR_LLTINI_HDATA_V1(x) ((x) & (~BITS_LLTINI_HDATA_V1)) #define BIT_GET_LLTINI_HDATA_V1(x) \ (((x) >> BIT_SHIFT_LLTINI_HDATA_V1) & BIT_MASK_LLTINI_HDATA_V1) #define BIT_SET_LLTINI_HDATA_V1(x, v) \ (BIT_CLEAR_LLTINI_HDATA_V1(x) | BIT_LLTINI_HDATA_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_RXDESC_BUFF_BNDY (Offset 0x01E0) */ #define BIT_SHIFT_RXDESC_BUFF_BNDY 0 #define BIT_MASK_RXDESC_BUFF_BNDY 0xffffffffL #define BIT_RXDESC_BUFF_BNDY(x) \ (((x) & BIT_MASK_RXDESC_BUFF_BNDY) << BIT_SHIFT_RXDESC_BUFF_BNDY) #define BITS_RXDESC_BUFF_BNDY \ (BIT_MASK_RXDESC_BUFF_BNDY << BIT_SHIFT_RXDESC_BUFF_BNDY) #define BIT_CLEAR_RXDESC_BUFF_BNDY(x) ((x) & (~BITS_RXDESC_BUFF_BNDY)) #define BIT_GET_RXDESC_BUFF_BNDY(x) \ (((x) >> BIT_SHIFT_RXDESC_BUFF_BNDY) & BIT_MASK_RXDESC_BUFF_BNDY) #define BIT_SET_RXDESC_BUFF_BNDY(x, v) \ (BIT_CLEAR_RXDESC_BUFF_BNDY(x) | BIT_RXDESC_BUFF_BNDY(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_GENTST (Offset 0x01E4) */ #define BIT_SHIFT_GENTST 0 #define BIT_MASK_GENTST 0xffffffffL #define BIT_GENTST(x) (((x) & BIT_MASK_GENTST) << BIT_SHIFT_GENTST) #define BITS_GENTST (BIT_MASK_GENTST << BIT_SHIFT_GENTST) #define BIT_CLEAR_GENTST(x) ((x) & (~BITS_GENTST)) #define BIT_GET_GENTST(x) (((x) >> BIT_SHIFT_GENTST) & BIT_MASK_GENTST) #define BIT_SET_GENTST(x, v) (BIT_CLEAR_GENTST(x) | BIT_GENTST(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LLT_INIT_ADDR (Offset 0x01E4) */ #define BIT_SHIFT_LLTINI_ADDR_V1 0 #define BIT_MASK_LLTINI_ADDR_V1 0xfff #define BIT_LLTINI_ADDR_V1(x) \ (((x) & BIT_MASK_LLTINI_ADDR_V1) << BIT_SHIFT_LLTINI_ADDR_V1) #define BITS_LLTINI_ADDR_V1 \ (BIT_MASK_LLTINI_ADDR_V1 << BIT_SHIFT_LLTINI_ADDR_V1) #define BIT_CLEAR_LLTINI_ADDR_V1(x) ((x) & (~BITS_LLTINI_ADDR_V1)) #define BIT_GET_LLTINI_ADDR_V1(x) \ (((x) >> BIT_SHIFT_LLTINI_ADDR_V1) & BIT_MASK_LLTINI_ADDR_V1) #define BIT_SET_LLTINI_ADDR_V1(x, v) \ (BIT_CLEAR_LLTINI_ADDR_V1(x) | BIT_LLTINI_ADDR_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ #define BIT_SHIFT_BB_WRITE_READ 30 #define BIT_MASK_BB_WRITE_READ 0x3 #define BIT_BB_WRITE_READ(x) \ (((x) & BIT_MASK_BB_WRITE_READ) << BIT_SHIFT_BB_WRITE_READ) #define BITS_BB_WRITE_READ (BIT_MASK_BB_WRITE_READ << BIT_SHIFT_BB_WRITE_READ) #define BIT_CLEAR_BB_WRITE_READ(x) ((x) & (~BITS_BB_WRITE_READ)) #define BIT_GET_BB_WRITE_READ(x) \ (((x) >> BIT_SHIFT_BB_WRITE_READ) & BIT_MASK_BB_WRITE_READ) #define BIT_SET_BB_WRITE_READ(x, v) \ (BIT_CLEAR_BB_WRITE_READ(x) | BIT_BB_WRITE_READ(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ #define BIT_SHIFT_BB_WRITE_EN_V1 16 #define BIT_MASK_BB_WRITE_EN_V1 0xf #define BIT_BB_WRITE_EN_V1(x) \ (((x) & BIT_MASK_BB_WRITE_EN_V1) << BIT_SHIFT_BB_WRITE_EN_V1) #define BITS_BB_WRITE_EN_V1 \ (BIT_MASK_BB_WRITE_EN_V1 << BIT_SHIFT_BB_WRITE_EN_V1) #define BIT_CLEAR_BB_WRITE_EN_V1(x) ((x) & (~BITS_BB_WRITE_EN_V1)) #define BIT_GET_BB_WRITE_EN_V1(x) \ (((x) >> BIT_SHIFT_BB_WRITE_EN_V1) & BIT_MASK_BB_WRITE_EN_V1) #define BIT_SET_BB_WRITE_EN_V1(x, v) \ (BIT_CLEAR_BB_WRITE_EN_V1(x) | BIT_BB_WRITE_EN_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ #define BIT_SHIFT_BB_WRITE_EN 12 #define BIT_MASK_BB_WRITE_EN 0xf #define BIT_BB_WRITE_EN(x) \ (((x) & BIT_MASK_BB_WRITE_EN) << BIT_SHIFT_BB_WRITE_EN) #define BITS_BB_WRITE_EN (BIT_MASK_BB_WRITE_EN << BIT_SHIFT_BB_WRITE_EN) #define BIT_CLEAR_BB_WRITE_EN(x) ((x) & (~BITS_BB_WRITE_EN)) #define BIT_GET_BB_WRITE_EN(x) \ (((x) >> BIT_SHIFT_BB_WRITE_EN) & BIT_MASK_BB_WRITE_EN) #define BIT_SET_BB_WRITE_EN(x, v) \ (BIT_CLEAR_BB_WRITE_EN(x) | BIT_BB_WRITE_EN(v)) #define BIT_SHIFT_BB_ADDR 2 #define BIT_MASK_BB_ADDR 0x1ff #define BIT_BB_ADDR(x) (((x) & BIT_MASK_BB_ADDR) << BIT_SHIFT_BB_ADDR) #define BITS_BB_ADDR (BIT_MASK_BB_ADDR << BIT_SHIFT_BB_ADDR) #define BIT_CLEAR_BB_ADDR(x) ((x) & (~BITS_BB_ADDR)) #define BIT_GET_BB_ADDR(x) (((x) >> BIT_SHIFT_BB_ADDR) & BIT_MASK_BB_ADDR) #define BIT_SET_BB_ADDR(x, v) (BIT_CLEAR_BB_ADDR(x) | BIT_BB_ADDR(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ #define BIT_SHIFT_BB_ADDR_V1 2 #define BIT_MASK_BB_ADDR_V1 0xfff #define BIT_BB_ADDR_V1(x) (((x) & BIT_MASK_BB_ADDR_V1) << BIT_SHIFT_BB_ADDR_V1) #define BITS_BB_ADDR_V1 (BIT_MASK_BB_ADDR_V1 << BIT_SHIFT_BB_ADDR_V1) #define BIT_CLEAR_BB_ADDR_V1(x) ((x) & (~BITS_BB_ADDR_V1)) #define BIT_GET_BB_ADDR_V1(x) \ (((x) >> BIT_SHIFT_BB_ADDR_V1) & BIT_MASK_BB_ADDR_V1) #define BIT_SET_BB_ADDR_V1(x, v) (BIT_CLEAR_BB_ADDR_V1(x) | BIT_BB_ADDR_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ #define BIT_BB_ERRACC BIT(0) /* 2 REG_BB_ACCESS_DATA (Offset 0x01EC) */ #define BIT_SHIFT_BB_DATA 0 #define BIT_MASK_BB_DATA 0xffffffffL #define BIT_BB_DATA(x) (((x) & BIT_MASK_BB_DATA) << BIT_SHIFT_BB_DATA) #define BITS_BB_DATA (BIT_MASK_BB_DATA << BIT_SHIFT_BB_DATA) #define BIT_CLEAR_BB_DATA(x) ((x) & (~BITS_BB_DATA)) #define BIT_GET_BB_DATA(x) (((x) >> BIT_SHIFT_BB_DATA) & BIT_MASK_BB_DATA) #define BIT_SET_BB_DATA(x, v) (BIT_CLEAR_BB_DATA(x) | BIT_BB_DATA(v)) /* 2 REG_HMEBOX_E0 (Offset 0x01F0) */ #define BIT_SHIFT_HMEBOX_E0 0 #define BIT_MASK_HMEBOX_E0 0xffffffffL #define BIT_HMEBOX_E0(x) (((x) & BIT_MASK_HMEBOX_E0) << BIT_SHIFT_HMEBOX_E0) #define BITS_HMEBOX_E0 (BIT_MASK_HMEBOX_E0 << BIT_SHIFT_HMEBOX_E0) #define BIT_CLEAR_HMEBOX_E0(x) ((x) & (~BITS_HMEBOX_E0)) #define BIT_GET_HMEBOX_E0(x) (((x) >> BIT_SHIFT_HMEBOX_E0) & BIT_MASK_HMEBOX_E0) #define BIT_SET_HMEBOX_E0(x, v) (BIT_CLEAR_HMEBOX_E0(x) | BIT_HMEBOX_E0(v)) /* 2 REG_HMEBOX_E1 (Offset 0x01F4) */ #define BIT_SHIFT_HMEBOX_E1 0 #define BIT_MASK_HMEBOX_E1 0xffffffffL #define BIT_HMEBOX_E1(x) (((x) & BIT_MASK_HMEBOX_E1) << BIT_SHIFT_HMEBOX_E1) #define BITS_HMEBOX_E1 (BIT_MASK_HMEBOX_E1 << BIT_SHIFT_HMEBOX_E1) #define BIT_CLEAR_HMEBOX_E1(x) ((x) & (~BITS_HMEBOX_E1)) #define BIT_GET_HMEBOX_E1(x) (((x) >> BIT_SHIFT_HMEBOX_E1) & BIT_MASK_HMEBOX_E1) #define BIT_SET_HMEBOX_E1(x, v) (BIT_CLEAR_HMEBOX_E1(x) | BIT_HMEBOX_E1(v)) /* 2 REG_HMEBOX_E2 (Offset 0x01F8) */ #define BIT_SHIFT_HMEBOX_E2 0 #define BIT_MASK_HMEBOX_E2 0xffffffffL #define BIT_HMEBOX_E2(x) (((x) & BIT_MASK_HMEBOX_E2) << BIT_SHIFT_HMEBOX_E2) #define BITS_HMEBOX_E2 (BIT_MASK_HMEBOX_E2 << BIT_SHIFT_HMEBOX_E2) #define BIT_CLEAR_HMEBOX_E2(x) ((x) & (~BITS_HMEBOX_E2)) #define BIT_GET_HMEBOX_E2(x) (((x) >> BIT_SHIFT_HMEBOX_E2) & BIT_MASK_HMEBOX_E2) #define BIT_SET_HMEBOX_E2(x, v) (BIT_CLEAR_HMEBOX_E2(x) | BIT_HMEBOX_E2(v)) /* 2 REG_HMEBOX_E3 (Offset 0x01FC) */ #define BIT_SHIFT_HMEBOX_E3 0 #define BIT_MASK_HMEBOX_E3 0xffffffffL #define BIT_HMEBOX_E3(x) (((x) & BIT_MASK_HMEBOX_E3) << BIT_SHIFT_HMEBOX_E3) #define BITS_HMEBOX_E3 (BIT_MASK_HMEBOX_E3 << BIT_SHIFT_HMEBOX_E3) #define BIT_CLEAR_HMEBOX_E3(x) ((x) & (~BITS_HMEBOX_E3)) #define BIT_GET_HMEBOX_E3(x) (((x) >> BIT_SHIFT_HMEBOX_E3) & BIT_MASK_HMEBOX_E3) #define BIT_SET_HMEBOX_E3(x, v) (BIT_CLEAR_HMEBOX_E3(x) | BIT_HMEBOX_E3(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_BCN_CTRL_0 (Offset 0x0200) */ #define BIT_BCN1_VALID BIT(31) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RQPN_CTRL_HLPQ (Offset 0x0200) */ #define BIT_EPQ_PUBLIC_DIS BIT(27) #define BIT_NPQ_PUBLIC_DIS BIT(26) #define BIT_LPQ_PUBLIC_DIS BIT(25) #define BIT_HPQ_PUBLIC_DIS BIT(24) #define BIT_SHIFT_PUBQ 16 #define BIT_MASK_PUBQ 0xff #define BIT_PUBQ(x) (((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ) #define BITS_PUBQ (BIT_MASK_PUBQ << BIT_SHIFT_PUBQ) #define BIT_CLEAR_PUBQ(x) ((x) & (~BITS_PUBQ)) #define BIT_GET_PUBQ(x) (((x) >> BIT_SHIFT_PUBQ) & BIT_MASK_PUBQ) #define BIT_SET_PUBQ(x, v) (BIT_CLEAR_PUBQ(x) | BIT_PUBQ(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */ #define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1 16 #define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1 0xff #define BIT_TX_OQT_HE_FREE_SPACE_V1(x) \ (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1) \ << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) #define BITS_TX_OQT_HE_FREE_SPACE_V1 \ (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1 << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) #define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1(x) \ ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1)) #define BIT_GET_TX_OQT_HE_FREE_SPACE_V1(x) \ (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) & \ BIT_MASK_TX_OQT_HE_FREE_SPACE_V1) #define BIT_SET_TX_OQT_HE_FREE_SPACE_V1(x, v) \ (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1(x) | BIT_TX_OQT_HE_FREE_SPACE_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_BCN_CTRL_0 (Offset 0x0200) */ #define BIT_SHIFT_BCN1_HEAD 16 #define BIT_MASK_BCN1_HEAD 0xfff #define BIT_BCN1_HEAD(x) (((x) & BIT_MASK_BCN1_HEAD) << BIT_SHIFT_BCN1_HEAD) #define BITS_BCN1_HEAD (BIT_MASK_BCN1_HEAD << BIT_SHIFT_BCN1_HEAD) #define BIT_CLEAR_BCN1_HEAD(x) ((x) & (~BITS_BCN1_HEAD)) #define BIT_GET_BCN1_HEAD(x) (((x) >> BIT_SHIFT_BCN1_HEAD) & BIT_MASK_BCN1_HEAD) #define BIT_SET_BCN1_HEAD(x, v) (BIT_CLEAR_BCN1_HEAD(x) | BIT_BCN1_HEAD(v)) #define BIT_BCN0_VALID BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RQPN_CTRL_HLPQ (Offset 0x0200) */ #define BIT_SHIFT_LPQ 8 #define BIT_MASK_LPQ 0xff #define BIT_LPQ(x) (((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ) #define BITS_LPQ (BIT_MASK_LPQ << BIT_SHIFT_LPQ) #define BIT_CLEAR_LPQ(x) ((x) & (~BITS_LPQ)) #define BIT_GET_LPQ(x) (((x) >> BIT_SHIFT_LPQ) & BIT_MASK_LPQ) #define BIT_SET_LPQ(x, v) (BIT_CLEAR_LPQ(x) | BIT_LPQ(v)) #define BIT_SHIFT_HPQ 0 #define BIT_MASK_HPQ 0xff #define BIT_HPQ(x) (((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ) #define BITS_HPQ (BIT_MASK_HPQ << BIT_SHIFT_HPQ) #define BIT_CLEAR_HPQ(x) ((x) & (~BITS_HPQ)) #define BIT_GET_HPQ(x) (((x) >> BIT_SHIFT_HPQ) & BIT_MASK_HPQ) #define BIT_SET_HPQ(x, v) (BIT_CLEAR_HPQ(x) | BIT_HPQ(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */ #define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1 0 #define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1 0xff #define BIT_TX_OQT_NL_FREE_SPACE_V1(x) \ (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1) \ << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) #define BITS_TX_OQT_NL_FREE_SPACE_V1 \ (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1 << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) #define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1(x) \ ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1)) #define BIT_GET_TX_OQT_NL_FREE_SPACE_V1(x) \ (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) & \ BIT_MASK_TX_OQT_NL_FREE_SPACE_V1) #define BIT_SET_TX_OQT_NL_FREE_SPACE_V1(x, v) \ (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1(x) | BIT_TX_OQT_NL_FREE_SPACE_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_BCN_CTRL_0 (Offset 0x0200) */ #define BIT_SHIFT_BCN0_HEAD 0 #define BIT_MASK_BCN0_HEAD 0xfff #define BIT_BCN0_HEAD(x) (((x) & BIT_MASK_BCN0_HEAD) << BIT_SHIFT_BCN0_HEAD) #define BITS_BCN0_HEAD (BIT_MASK_BCN0_HEAD << BIT_SHIFT_BCN0_HEAD) #define BIT_CLEAR_BCN0_HEAD(x) ((x) & (~BITS_BCN0_HEAD)) #define BIT_GET_BCN0_HEAD(x) (((x) >> BIT_SHIFT_BCN0_HEAD) & BIT_MASK_BCN0_HEAD) #define BIT_SET_BCN0_HEAD(x, v) (BIT_CLEAR_BCN0_HEAD(x) | BIT_BCN0_HEAD(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ #define BIT_BCN_VALID_1_V1 BIT(31) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_BCN_CTRL_1 (Offset 0x0204) */ #define BIT_BCN3_VALID BIT(31) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */ #define BIT_SHIFT_TXPKTNUM 24 #define BIT_MASK_TXPKTNUM 0xff #define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM) #define BITS_TXPKTNUM (BIT_MASK_TXPKTNUM << BIT_SHIFT_TXPKTNUM) #define BIT_CLEAR_TXPKTNUM(x) ((x) & (~BITS_TXPKTNUM)) #define BIT_GET_TXPKTNUM(x) (((x) >> BIT_SHIFT_TXPKTNUM) & BIT_MASK_TXPKTNUM) #define BIT_SET_TXPKTNUM(x, v) (BIT_CLEAR_TXPKTNUM(x) | BIT_TXPKTNUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_BCN_CTRL_1 (Offset 0x0204) */ #define BIT_SHIFT_R_BCN_HEAD_SEL_V1 20 #define BIT_MASK_R_BCN_HEAD_SEL_V1 0x7 #define BIT_R_BCN_HEAD_SEL_V1(x) \ (((x) & BIT_MASK_R_BCN_HEAD_SEL_V1) << BIT_SHIFT_R_BCN_HEAD_SEL_V1) #define BITS_R_BCN_HEAD_SEL_V1 \ (BIT_MASK_R_BCN_HEAD_SEL_V1 << BIT_SHIFT_R_BCN_HEAD_SEL_V1) #define BIT_CLEAR_R_BCN_HEAD_SEL_V1(x) ((x) & (~BITS_R_BCN_HEAD_SEL_V1)) #define BIT_GET_R_BCN_HEAD_SEL_V1(x) \ (((x) >> BIT_SHIFT_R_BCN_HEAD_SEL_V1) & BIT_MASK_R_BCN_HEAD_SEL_V1) #define BIT_SET_R_BCN_HEAD_SEL_V1(x, v) \ (BIT_CLEAR_R_BCN_HEAD_SEL_V1(x) | BIT_R_BCN_HEAD_SEL_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */ #define BIT_SHIFT_PUBQ_AVAL_PG 16 #define BIT_MASK_PUBQ_AVAL_PG 0xff #define BIT_PUBQ_AVAL_PG(x) \ (((x) & BIT_MASK_PUBQ_AVAL_PG) << BIT_SHIFT_PUBQ_AVAL_PG) #define BITS_PUBQ_AVAL_PG (BIT_MASK_PUBQ_AVAL_PG << BIT_SHIFT_PUBQ_AVAL_PG) #define BIT_CLEAR_PUBQ_AVAL_PG(x) ((x) & (~BITS_PUBQ_AVAL_PG)) #define BIT_GET_PUBQ_AVAL_PG(x) \ (((x) >> BIT_SHIFT_PUBQ_AVAL_PG) & BIT_MASK_PUBQ_AVAL_PG) #define BIT_SET_PUBQ_AVAL_PG(x, v) \ (BIT_CLEAR_PUBQ_AVAL_PG(x) | BIT_PUBQ_AVAL_PG(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ #define BIT_SHIFT_BCN_HEAD_1_V1 16 #define BIT_MASK_BCN_HEAD_1_V1 0xfff #define BIT_BCN_HEAD_1_V1(x) \ (((x) & BIT_MASK_BCN_HEAD_1_V1) << BIT_SHIFT_BCN_HEAD_1_V1) #define BITS_BCN_HEAD_1_V1 (BIT_MASK_BCN_HEAD_1_V1 << BIT_SHIFT_BCN_HEAD_1_V1) #define BIT_CLEAR_BCN_HEAD_1_V1(x) ((x) & (~BITS_BCN_HEAD_1_V1)) #define BIT_GET_BCN_HEAD_1_V1(x) \ (((x) >> BIT_SHIFT_BCN_HEAD_1_V1) & BIT_MASK_BCN_HEAD_1_V1) #define BIT_SET_BCN_HEAD_1_V1(x, v) \ (BIT_CLEAR_BCN_HEAD_1_V1(x) | BIT_BCN_HEAD_1_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_BCN_CTRL_1 (Offset 0x0204) */ #define BIT_SHIFT_BCN3_HEAD 16 #define BIT_MASK_BCN3_HEAD 0xfff #define BIT_BCN3_HEAD(x) (((x) & BIT_MASK_BCN3_HEAD) << BIT_SHIFT_BCN3_HEAD) #define BITS_BCN3_HEAD (BIT_MASK_BCN3_HEAD << BIT_SHIFT_BCN3_HEAD) #define BIT_CLEAR_BCN3_HEAD(x) ((x) & (~BITS_BCN3_HEAD)) #define BIT_GET_BCN3_HEAD(x) (((x) >> BIT_SHIFT_BCN3_HEAD) & BIT_MASK_BCN3_HEAD) #define BIT_SET_BCN3_HEAD(x, v) (BIT_CLEAR_BCN3_HEAD(x) | BIT_BCN3_HEAD(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ #define BIT_BCN_VALID_V1 BIT(15) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_BCN_CTRL_1 (Offset 0x0204) */ #define BIT_BCN2_VALID BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */ #define BIT_SHIFT_LPQ_AVAL_PG 8 #define BIT_MASK_LPQ_AVAL_PG 0xff #define BIT_LPQ_AVAL_PG(x) \ (((x) & BIT_MASK_LPQ_AVAL_PG) << BIT_SHIFT_LPQ_AVAL_PG) #define BITS_LPQ_AVAL_PG (BIT_MASK_LPQ_AVAL_PG << BIT_SHIFT_LPQ_AVAL_PG) #define BIT_CLEAR_LPQ_AVAL_PG(x) ((x) & (~BITS_LPQ_AVAL_PG)) #define BIT_GET_LPQ_AVAL_PG(x) \ (((x) >> BIT_SHIFT_LPQ_AVAL_PG) & BIT_MASK_LPQ_AVAL_PG) #define BIT_SET_LPQ_AVAL_PG(x, v) \ (BIT_CLEAR_LPQ_AVAL_PG(x) | BIT_LPQ_AVAL_PG(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_BCN_CTRL_1 (Offset 0x0204) */ #define BIT_TDE_ERROR_STOP BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */ #define BIT_SHIFT_HPQ_AVAL_PG 0 #define BIT_MASK_HPQ_AVAL_PG 0xff #define BIT_HPQ_AVAL_PG(x) \ (((x) & BIT_MASK_HPQ_AVAL_PG) << BIT_SHIFT_HPQ_AVAL_PG) #define BITS_HPQ_AVAL_PG (BIT_MASK_HPQ_AVAL_PG << BIT_SHIFT_HPQ_AVAL_PG) #define BIT_CLEAR_HPQ_AVAL_PG(x) ((x) & (~BITS_HPQ_AVAL_PG)) #define BIT_GET_HPQ_AVAL_PG(x) \ (((x) >> BIT_SHIFT_HPQ_AVAL_PG) & BIT_MASK_HPQ_AVAL_PG) #define BIT_SET_HPQ_AVAL_PG(x, v) \ (BIT_CLEAR_HPQ_AVAL_PG(x) | BIT_HPQ_AVAL_PG(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ #define BIT_SHIFT_BCN_HEAD_V1 0 #define BIT_MASK_BCN_HEAD_V1 0xfff #define BIT_BCN_HEAD_V1(x) \ (((x) & BIT_MASK_BCN_HEAD_V1) << BIT_SHIFT_BCN_HEAD_V1) #define BITS_BCN_HEAD_V1 (BIT_MASK_BCN_HEAD_V1 << BIT_SHIFT_BCN_HEAD_V1) #define BIT_CLEAR_BCN_HEAD_V1(x) ((x) & (~BITS_BCN_HEAD_V1)) #define BIT_GET_BCN_HEAD_V1(x) \ (((x) >> BIT_SHIFT_BCN_HEAD_V1) & BIT_MASK_BCN_HEAD_V1) #define BIT_SET_BCN_HEAD_V1(x, v) \ (BIT_CLEAR_BCN_HEAD_V1(x) | BIT_BCN_HEAD_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_BCN_CTRL_1 (Offset 0x0204) */ #define BIT_SHIFT_BCN2_HEAD 0 #define BIT_MASK_BCN2_HEAD 0xfff #define BIT_BCN2_HEAD(x) (((x) & BIT_MASK_BCN2_HEAD) << BIT_SHIFT_BCN2_HEAD) #define BITS_BCN2_HEAD (BIT_MASK_BCN2_HEAD << BIT_SHIFT_BCN2_HEAD) #define BIT_CLEAR_BCN2_HEAD(x) ((x) & (~BITS_BCN2_HEAD)) #define BIT_GET_BCN2_HEAD(x) (((x) >> BIT_SHIFT_BCN2_HEAD) & BIT_MASK_BCN2_HEAD) #define BIT_SET_BCN2_HEAD(x, v) (BIT_CLEAR_BCN2_HEAD(x) | BIT_BCN2_HEAD(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DWBCN0_CTRL (Offset 0x0208) */ #define BIT_SHIFT_LLT_FREE_PAGE 24 #define BIT_MASK_LLT_FREE_PAGE 0xff #define BIT_LLT_FREE_PAGE(x) \ (((x) & BIT_MASK_LLT_FREE_PAGE) << BIT_SHIFT_LLT_FREE_PAGE) #define BITS_LLT_FREE_PAGE (BIT_MASK_LLT_FREE_PAGE << BIT_SHIFT_LLT_FREE_PAGE) #define BIT_CLEAR_LLT_FREE_PAGE(x) ((x) & (~BITS_LLT_FREE_PAGE)) #define BIT_GET_LLT_FREE_PAGE(x) \ (((x) >> BIT_SHIFT_LLT_FREE_PAGE) & BIT_MASK_LLT_FREE_PAGE) #define BIT_SET_LLT_FREE_PAGE(x, v) \ (BIT_CLEAR_LLT_FREE_PAGE(x) | BIT_LLT_FREE_PAGE(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ #define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 24 #define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 0xff #define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) \ (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) \ << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) #define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 \ (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 \ << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) #define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) \ ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1)) #define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) \ (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) & \ BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) #define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x, v) \ (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) | \ BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ #define BIT_SHIFT_MAX_TX_PKT_V1 24 #define BIT_MASK_MAX_TX_PKT_V1 0xff #define BIT_MAX_TX_PKT_V1(x) \ (((x) & BIT_MASK_MAX_TX_PKT_V1) << BIT_SHIFT_MAX_TX_PKT_V1) #define BITS_MAX_TX_PKT_V1 (BIT_MASK_MAX_TX_PKT_V1 << BIT_SHIFT_MAX_TX_PKT_V1) #define BIT_CLEAR_MAX_TX_PKT_V1(x) ((x) & (~BITS_MAX_TX_PKT_V1)) #define BIT_GET_MAX_TX_PKT_V1(x) \ (((x) >> BIT_SHIFT_MAX_TX_PKT_V1) & BIT_MASK_MAX_TX_PKT_V1) #define BIT_SET_MAX_TX_PKT_V1(x, v) \ (BIT_CLEAR_MAX_TX_PKT_V1(x) | BIT_MAX_TX_PKT_V1(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ #define BIT_TDE_ERROR_STOP_V1 BIT(23) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DWBCN0_CTRL (Offset 0x0208) */ #define BIT_BCN_VALID BIT(16) #define BIT_SHIFT_BCN_HEAD 8 #define BIT_MASK_BCN_HEAD 0xff #define BIT_BCN_HEAD(x) (((x) & BIT_MASK_BCN_HEAD) << BIT_SHIFT_BCN_HEAD) #define BITS_BCN_HEAD (BIT_MASK_BCN_HEAD << BIT_SHIFT_BCN_HEAD) #define BIT_CLEAR_BCN_HEAD(x) ((x) & (~BITS_BCN_HEAD)) #define BIT_GET_BCN_HEAD(x) (((x) >> BIT_SHIFT_BCN_HEAD) & BIT_MASK_BCN_HEAD) #define BIT_SET_BCN_HEAD(x, v) (BIT_CLEAR_BCN_HEAD(x) | BIT_BCN_HEAD(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ #define BIT_SHIFT_LLT_FREE_PAGE_V1 8 #define BIT_MASK_LLT_FREE_PAGE_V1 0xffff #define BIT_LLT_FREE_PAGE_V1(x) \ (((x) & BIT_MASK_LLT_FREE_PAGE_V1) << BIT_SHIFT_LLT_FREE_PAGE_V1) #define BITS_LLT_FREE_PAGE_V1 \ (BIT_MASK_LLT_FREE_PAGE_V1 << BIT_SHIFT_LLT_FREE_PAGE_V1) #define BIT_CLEAR_LLT_FREE_PAGE_V1(x) ((x) & (~BITS_LLT_FREE_PAGE_V1)) #define BIT_GET_LLT_FREE_PAGE_V1(x) \ (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1) & BIT_MASK_LLT_FREE_PAGE_V1) #define BIT_SET_LLT_FREE_PAGE_V1(x, v) \ (BIT_CLEAR_LLT_FREE_PAGE_V1(x) | BIT_LLT_FREE_PAGE_V1(v)) #endif #if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ #define BIT_SHIFT_LLT_FREE_PAGE_V2 8 #define BIT_MASK_LLT_FREE_PAGE_V2 0xfff #define BIT_LLT_FREE_PAGE_V2(x) \ (((x) & BIT_MASK_LLT_FREE_PAGE_V2) << BIT_SHIFT_LLT_FREE_PAGE_V2) #define BITS_LLT_FREE_PAGE_V2 \ (BIT_MASK_LLT_FREE_PAGE_V2 << BIT_SHIFT_LLT_FREE_PAGE_V2) #define BIT_CLEAR_LLT_FREE_PAGE_V2(x) ((x) & (~BITS_LLT_FREE_PAGE_V2)) #define BIT_GET_LLT_FREE_PAGE_V2(x) \ (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2) & BIT_MASK_LLT_FREE_PAGE_V2) #define BIT_SET_LLT_FREE_PAGE_V2(x, v) \ (BIT_CLEAR_LLT_FREE_PAGE_V2(x) | BIT_LLT_FREE_PAGE_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_DWBCN0_CTRL (Offset 0x0208) */ #define BIT_SHIFT_BLK_DESC_NUM 4 #define BIT_MASK_BLK_DESC_NUM 0xf #define BIT_BLK_DESC_NUM(x) \ (((x) & BIT_MASK_BLK_DESC_NUM) << BIT_SHIFT_BLK_DESC_NUM) #define BITS_BLK_DESC_NUM (BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM) #define BIT_CLEAR_BLK_DESC_NUM(x) ((x) & (~BITS_BLK_DESC_NUM)) #define BIT_GET_BLK_DESC_NUM(x) \ (((x) >> BIT_SHIFT_BLK_DESC_NUM) & BIT_MASK_BLK_DESC_NUM) #define BIT_SET_BLK_DESC_NUM(x, v) \ (BIT_CLEAR_BLK_DESC_NUM(x) | BIT_BLK_DESC_NUM(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ #define BIT_R_BCN_HEAD_SEL BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ #define BIT_R_EN_BCN_SW_HEAD_SEL BIT(2) #define BIT_LLT_DBG_SEL BIT(1) #define BIT_AUTO_INIT_LLT_V1 BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ #define BIT_EM_CHKSUM_FIN BIT(31) #define BIT_EMN_PCIE_DMA_MOD BIT(30) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ #define BIT_EN_TXQUE_CLR BIT(29) #define BIT_EN_PCIE_FIFO_MODE BIT(28) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ #define BIT_SHIFT_PG_UNDER_TH 16 #define BIT_MASK_PG_UNDER_TH 0xff #define BIT_PG_UNDER_TH(x) \ (((x) & BIT_MASK_PG_UNDER_TH) << BIT_SHIFT_PG_UNDER_TH) #define BITS_PG_UNDER_TH (BIT_MASK_PG_UNDER_TH << BIT_SHIFT_PG_UNDER_TH) #define BIT_CLEAR_PG_UNDER_TH(x) ((x) & (~BITS_PG_UNDER_TH)) #define BIT_GET_PG_UNDER_TH(x) \ (((x) >> BIT_SHIFT_PG_UNDER_TH) & BIT_MASK_PG_UNDER_TH) #define BIT_SET_PG_UNDER_TH(x, v) \ (BIT_CLEAR_PG_UNDER_TH(x) | BIT_PG_UNDER_TH(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ #define BIT_SHIFT_PG_UNDER_TH_V1 16 #define BIT_MASK_PG_UNDER_TH_V1 0xfff #define BIT_PG_UNDER_TH_V1(x) \ (((x) & BIT_MASK_PG_UNDER_TH_V1) << BIT_SHIFT_PG_UNDER_TH_V1) #define BITS_PG_UNDER_TH_V1 \ (BIT_MASK_PG_UNDER_TH_V1 << BIT_SHIFT_PG_UNDER_TH_V1) #define BIT_CLEAR_PG_UNDER_TH_V1(x) ((x) & (~BITS_PG_UNDER_TH_V1)) #define BIT_GET_PG_UNDER_TH_V1(x) \ (((x) >> BIT_SHIFT_PG_UNDER_TH_V1) & BIT_MASK_PG_UNDER_TH_V1) #define BIT_SET_PG_UNDER_TH_V1(x, v) \ (BIT_CLEAR_PG_UNDER_TH_V1(x) | BIT_PG_UNDER_TH_V1(v)) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ #define BIT_EN_RESET_RESTORE_H2C BIT(15) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ #define BIT_R_EN_RESET_RESTORE_H2C BIT(15) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ #define BIT_RESTORE_H2C_ADDRESS BIT(15) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ #define BIT_SDIO_TDE_FINISH BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ #define BIT_SDIO_TXDESC_CHKSUM_EN BIT(13) #define BIT_RST_RDPTR BIT(12) #define BIT_RST_WRPTR BIT(11) #define BIT_CHK_PG_TH_EN BIT(10) #define BIT_DROP_DATA_EN BIT(9) #define BIT_CHECK_OFFSET_EN BIT(8) #define BIT_SHIFT_CHECK_OFFSET 0 #define BIT_MASK_CHECK_OFFSET 0xff #define BIT_CHECK_OFFSET(x) \ (((x) & BIT_MASK_CHECK_OFFSET) << BIT_SHIFT_CHECK_OFFSET) #define BITS_CHECK_OFFSET (BIT_MASK_CHECK_OFFSET << BIT_SHIFT_CHECK_OFFSET) #define BIT_CLEAR_CHECK_OFFSET(x) ((x) & (~BITS_CHECK_OFFSET)) #define BIT_GET_CHECK_OFFSET(x) \ (((x) >> BIT_SHIFT_CHECK_OFFSET) & BIT_MASK_CHECK_OFFSET) #define BIT_SET_CHECK_OFFSET(x, v) \ (BIT_CLEAR_CHECK_OFFSET(x) | BIT_CHECK_OFFSET(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_AMSDU_PKT_SIZE_ERR BIT(31) #define BIT_AMSDU_EN_ERR BIT(30) #define BIT_CHKSUM_AMSDU_EN_ERR BIT(29) #define BIT_TXPKTBF_REQ_ERR BIT(28) #define BIT_OQT_UDN_16 BIT(27) #define BIT_OQT_OVF_16 BIT(26) #define BIT_OQT_UDN_14_15 BIT(25) #define BIT_OQT_OVF_14_15 BIT(24) #define BIT_OQT_UDN_13 BIT(23) #define BIT_OQT_OVF_13 BIT(22) #define BIT_OQT_UDN_12 BIT(21) #define BIT_OQT_OVF_12 BIT(20) #define BIT_OQT_UDN_8_11 BIT(19) #define BIT_OQT_OVF_8_11 BIT(18) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_TXPKTBUF_REQ_ERR BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_HI_OQT_UDN BIT(17) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_OQT_UDN_4_7 BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_HI_OQT_OVF BIT(16) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_OQT_OVF_4_7 BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_PAYLOAD_CHKSUM_ERR BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_RX_CLOSE_EN BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_PAYLOAD_UDN BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_STOP_BCNQ BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_PAYLOAD_OVF BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_STOP_MGQ BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_DSC_CHKSUM_FAIL BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_STOP_VOQ BIT(12) #define BIT_UNKNOWN_QSEL BIT(11) #define BIT_STOP_VIQ BIT(11) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_EP_QSEL_DIFF BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_STOP_BEQ BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_TX_OFFS_UNMATCH BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_STOP_BKQ BIT(9) #define BIT_TXOQT_UDN BIT(8) #define BIT_STOP_RXQ BIT(8) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_TXOQT_UDN_0_3 BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_TXOQT_OVF BIT(7) #define BIT_STOP_HI7Q BIT(7) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_TXOQT_OVF_0_3 BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_TXDMA_SFF_UDN BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_STOP_HI6Q BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_TXDMA_SFF_OVF BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_STOP_HI5Q BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_LLT_NULL_PG BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_STOP_HI4Q BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_PAGE_UDN BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_STOP_HI3Q BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_PAGE_OVF BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_STOP_HI2Q BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_TXFF_PG_UDN BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_STOP_HI1Q BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_TXFF_PG_OVF BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ #define BIT_STOP_HI0Q BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RQPN_NPQ (Offset 0x0214) */ #define BIT_SHIFT_EXQ_AVAL_PG 24 #define BIT_MASK_EXQ_AVAL_PG 0xff #define BIT_EXQ_AVAL_PG(x) \ (((x) & BIT_MASK_EXQ_AVAL_PG) << BIT_SHIFT_EXQ_AVAL_PG) #define BITS_EXQ_AVAL_PG (BIT_MASK_EXQ_AVAL_PG << BIT_SHIFT_EXQ_AVAL_PG) #define BIT_CLEAR_EXQ_AVAL_PG(x) ((x) & (~BITS_EXQ_AVAL_PG)) #define BIT_GET_EXQ_AVAL_PG(x) \ (((x) >> BIT_SHIFT_EXQ_AVAL_PG) & BIT_MASK_EXQ_AVAL_PG) #define BIT_SET_EXQ_AVAL_PG(x, v) \ (BIT_CLEAR_EXQ_AVAL_PG(x) | BIT_EXQ_AVAL_PG(v)) #define BIT_SHIFT_EXQ 16 #define BIT_MASK_EXQ 0xff #define BIT_EXQ(x) (((x) & BIT_MASK_EXQ) << BIT_SHIFT_EXQ) #define BITS_EXQ (BIT_MASK_EXQ << BIT_SHIFT_EXQ) #define BIT_CLEAR_EXQ(x) ((x) & (~BITS_EXQ)) #define BIT_GET_EXQ(x) (((x) >> BIT_SHIFT_EXQ) & BIT_MASK_EXQ) #define BIT_SET_EXQ(x, v) (BIT_CLEAR_EXQ(x) | BIT_EXQ(v)) #define BIT_SHIFT_NPQ 0 #define BIT_MASK_NPQ 0xff #define BIT_NPQ(x) (((x) & BIT_MASK_NPQ) << BIT_SHIFT_NPQ) #define BITS_NPQ (BIT_MASK_NPQ << BIT_SHIFT_NPQ) #define BIT_CLEAR_NPQ(x) ((x) & (~BITS_NPQ)) #define BIT_GET_NPQ(x) (((x) >> BIT_SHIFT_NPQ) & BIT_MASK_NPQ) #define BIT_SET_NPQ(x, v) (BIT_CLEAR_NPQ(x) | BIT_NPQ(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TQPNT1 (Offset 0x0218) */ #define BIT_HPQ_INT_EN BIT(31) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TQPNT1 (Offset 0x0218) */ #define BIT_SHIFT_NPQ_HIGH_TH 24 #define BIT_MASK_NPQ_HIGH_TH 0xff #define BIT_NPQ_HIGH_TH(x) \ (((x) & BIT_MASK_NPQ_HIGH_TH) << BIT_SHIFT_NPQ_HIGH_TH) #define BITS_NPQ_HIGH_TH (BIT_MASK_NPQ_HIGH_TH << BIT_SHIFT_NPQ_HIGH_TH) #define BIT_CLEAR_NPQ_HIGH_TH(x) ((x) & (~BITS_NPQ_HIGH_TH)) #define BIT_GET_NPQ_HIGH_TH(x) \ (((x) >> BIT_SHIFT_NPQ_HIGH_TH) & BIT_MASK_NPQ_HIGH_TH) #define BIT_SET_NPQ_HIGH_TH(x, v) \ (BIT_CLEAR_NPQ_HIGH_TH(x) | BIT_NPQ_HIGH_TH(v)) #define BIT_SHIFT_NPQ_LOW_TH 16 #define BIT_MASK_NPQ_LOW_TH 0xff #define BIT_NPQ_LOW_TH(x) (((x) & BIT_MASK_NPQ_LOW_TH) << BIT_SHIFT_NPQ_LOW_TH) #define BITS_NPQ_LOW_TH (BIT_MASK_NPQ_LOW_TH << BIT_SHIFT_NPQ_LOW_TH) #define BIT_CLEAR_NPQ_LOW_TH(x) ((x) & (~BITS_NPQ_LOW_TH)) #define BIT_GET_NPQ_LOW_TH(x) \ (((x) >> BIT_SHIFT_NPQ_LOW_TH) & BIT_MASK_NPQ_LOW_TH) #define BIT_SET_NPQ_LOW_TH(x, v) (BIT_CLEAR_NPQ_LOW_TH(x) | BIT_NPQ_LOW_TH(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_TQPNT1 (Offset 0x0218) */ #define BIT_SHIFT_HPQ_HIGH_TH_V1 16 #define BIT_MASK_HPQ_HIGH_TH_V1 0xfff #define BIT_HPQ_HIGH_TH_V1(x) \ (((x) & BIT_MASK_HPQ_HIGH_TH_V1) << BIT_SHIFT_HPQ_HIGH_TH_V1) #define BITS_HPQ_HIGH_TH_V1 \ (BIT_MASK_HPQ_HIGH_TH_V1 << BIT_SHIFT_HPQ_HIGH_TH_V1) #define BIT_CLEAR_HPQ_HIGH_TH_V1(x) ((x) & (~BITS_HPQ_HIGH_TH_V1)) #define BIT_GET_HPQ_HIGH_TH_V1(x) \ (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1) & BIT_MASK_HPQ_HIGH_TH_V1) #define BIT_SET_HPQ_HIGH_TH_V1(x, v) \ (BIT_CLEAR_HPQ_HIGH_TH_V1(x) | BIT_HPQ_HIGH_TH_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DMA_RQPN_INFO_PUB (Offset 0x0218) */ #define BIT_SHIFT_PUB_AVAL_PG 16 #define BIT_MASK_PUB_AVAL_PG 0xfff #define BIT_PUB_AVAL_PG(x) \ (((x) & BIT_MASK_PUB_AVAL_PG) << BIT_SHIFT_PUB_AVAL_PG) #define BITS_PUB_AVAL_PG (BIT_MASK_PUB_AVAL_PG << BIT_SHIFT_PUB_AVAL_PG) #define BIT_CLEAR_PUB_AVAL_PG(x) ((x) & (~BITS_PUB_AVAL_PG)) #define BIT_GET_PUB_AVAL_PG(x) \ (((x) >> BIT_SHIFT_PUB_AVAL_PG) & BIT_MASK_PUB_AVAL_PG) #define BIT_SET_PUB_AVAL_PG(x, v) \ (BIT_CLEAR_PUB_AVAL_PG(x) | BIT_PUB_AVAL_PG(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TQPNT1 (Offset 0x0218) */ #define BIT_SHIFT_HPQ_HIGH_TH 8 #define BIT_MASK_HPQ_HIGH_TH 0xff #define BIT_HPQ_HIGH_TH(x) \ (((x) & BIT_MASK_HPQ_HIGH_TH) << BIT_SHIFT_HPQ_HIGH_TH) #define BITS_HPQ_HIGH_TH (BIT_MASK_HPQ_HIGH_TH << BIT_SHIFT_HPQ_HIGH_TH) #define BIT_CLEAR_HPQ_HIGH_TH(x) ((x) & (~BITS_HPQ_HIGH_TH)) #define BIT_GET_HPQ_HIGH_TH(x) \ (((x) >> BIT_SHIFT_HPQ_HIGH_TH) & BIT_MASK_HPQ_HIGH_TH) #define BIT_SET_HPQ_HIGH_TH(x, v) \ (BIT_CLEAR_HPQ_HIGH_TH(x) | BIT_HPQ_HIGH_TH(v)) #define BIT_SHIFT_HPQ_LOW_TH 0 #define BIT_MASK_HPQ_LOW_TH 0xff #define BIT_HPQ_LOW_TH(x) (((x) & BIT_MASK_HPQ_LOW_TH) << BIT_SHIFT_HPQ_LOW_TH) #define BITS_HPQ_LOW_TH (BIT_MASK_HPQ_LOW_TH << BIT_SHIFT_HPQ_LOW_TH) #define BIT_CLEAR_HPQ_LOW_TH(x) ((x) & (~BITS_HPQ_LOW_TH)) #define BIT_GET_HPQ_LOW_TH(x) \ (((x) >> BIT_SHIFT_HPQ_LOW_TH) & BIT_MASK_HPQ_LOW_TH) #define BIT_SET_HPQ_LOW_TH(x, v) (BIT_CLEAR_HPQ_LOW_TH(x) | BIT_HPQ_LOW_TH(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_TQPNT1 (Offset 0x0218) */ #define BIT_SHIFT_HPQ_LOW_TH_V1 0 #define BIT_MASK_HPQ_LOW_TH_V1 0xfff #define BIT_HPQ_LOW_TH_V1(x) \ (((x) & BIT_MASK_HPQ_LOW_TH_V1) << BIT_SHIFT_HPQ_LOW_TH_V1) #define BITS_HPQ_LOW_TH_V1 (BIT_MASK_HPQ_LOW_TH_V1 << BIT_SHIFT_HPQ_LOW_TH_V1) #define BIT_CLEAR_HPQ_LOW_TH_V1(x) ((x) & (~BITS_HPQ_LOW_TH_V1)) #define BIT_GET_HPQ_LOW_TH_V1(x) \ (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1) & BIT_MASK_HPQ_LOW_TH_V1) #define BIT_SET_HPQ_LOW_TH_V1(x, v) \ (BIT_CLEAR_HPQ_LOW_TH_V1(x) | BIT_HPQ_LOW_TH_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DMA_RQPN_INFO_PUB (Offset 0x0218) */ #define BIT_SHIFT_PUB_RSVD_PG 0 #define BIT_MASK_PUB_RSVD_PG 0xfff #define BIT_PUB_RSVD_PG(x) \ (((x) & BIT_MASK_PUB_RSVD_PG) << BIT_SHIFT_PUB_RSVD_PG) #define BITS_PUB_RSVD_PG (BIT_MASK_PUB_RSVD_PG << BIT_SHIFT_PUB_RSVD_PG) #define BIT_CLEAR_PUB_RSVD_PG(x) ((x) & (~BITS_PUB_RSVD_PG)) #define BIT_GET_PUB_RSVD_PG(x) \ (((x) >> BIT_SHIFT_PUB_RSVD_PG) & BIT_MASK_PUB_RSVD_PG) #define BIT_SET_PUB_RSVD_PG(x, v) \ (BIT_CLEAR_PUB_RSVD_PG(x) | BIT_PUB_RSVD_PG(v)) /* 2 REG_RQPN_CTRL_2_V1 (Offset 0x021C) */ #define BIT_LD_RQPN_V1 BIT(31) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TQPNT2 (Offset 0x021C) */ #define BIT_NPQ_INT_EN BIT(31) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TQPNT2 (Offset 0x021C) */ #define BIT_SHIFT_EXQ_HIGH_TH 24 #define BIT_MASK_EXQ_HIGH_TH 0xff #define BIT_EXQ_HIGH_TH(x) \ (((x) & BIT_MASK_EXQ_HIGH_TH) << BIT_SHIFT_EXQ_HIGH_TH) #define BITS_EXQ_HIGH_TH (BIT_MASK_EXQ_HIGH_TH << BIT_SHIFT_EXQ_HIGH_TH) #define BIT_CLEAR_EXQ_HIGH_TH(x) ((x) & (~BITS_EXQ_HIGH_TH)) #define BIT_GET_EXQ_HIGH_TH(x) \ (((x) >> BIT_SHIFT_EXQ_HIGH_TH) & BIT_MASK_EXQ_HIGH_TH) #define BIT_SET_EXQ_HIGH_TH(x, v) \ (BIT_CLEAR_EXQ_HIGH_TH(x) | BIT_EXQ_HIGH_TH(v)) #define BIT_SHIFT_EXQ_LOW_TH 16 #define BIT_MASK_EXQ_LOW_TH 0xff #define BIT_EXQ_LOW_TH(x) (((x) & BIT_MASK_EXQ_LOW_TH) << BIT_SHIFT_EXQ_LOW_TH) #define BITS_EXQ_LOW_TH (BIT_MASK_EXQ_LOW_TH << BIT_SHIFT_EXQ_LOW_TH) #define BIT_CLEAR_EXQ_LOW_TH(x) ((x) & (~BITS_EXQ_LOW_TH)) #define BIT_GET_EXQ_LOW_TH(x) \ (((x) >> BIT_SHIFT_EXQ_LOW_TH) & BIT_MASK_EXQ_LOW_TH) #define BIT_SET_EXQ_LOW_TH(x, v) (BIT_CLEAR_EXQ_LOW_TH(x) | BIT_EXQ_LOW_TH(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_TQPNT2 (Offset 0x021C) */ #define BIT_SHIFT_NPQ_HIGH_TH_V1 16 #define BIT_MASK_NPQ_HIGH_TH_V1 0xfff #define BIT_NPQ_HIGH_TH_V1(x) \ (((x) & BIT_MASK_NPQ_HIGH_TH_V1) << BIT_SHIFT_NPQ_HIGH_TH_V1) #define BITS_NPQ_HIGH_TH_V1 \ (BIT_MASK_NPQ_HIGH_TH_V1 << BIT_SHIFT_NPQ_HIGH_TH_V1) #define BIT_CLEAR_NPQ_HIGH_TH_V1(x) ((x) & (~BITS_NPQ_HIGH_TH_V1)) #define BIT_GET_NPQ_HIGH_TH_V1(x) \ (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1) & BIT_MASK_NPQ_HIGH_TH_V1) #define BIT_SET_NPQ_HIGH_TH_V1(x, v) \ (BIT_CLEAR_NPQ_HIGH_TH_V1(x) | BIT_NPQ_HIGH_TH_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_RQPN_CTRL_2_V1 (Offset 0x021C) */ #define BIT_CH16_PUBLIC_DIS BIT(16) #define BIT_CH15_PUBLIC_DIS BIT(15) #define BIT_CH14_PUBLIC_DIS BIT(14) #define BIT_CH13_PUBLIC_DIS BIT(13) #define BIT_CH12_PUBLIC_DIS BIT(12) #define BIT_CH11_PUBLIC_DIS BIT(11) #define BIT_CH10_PUBLIC_DIS BIT(10) #define BIT_CH9_PUBLIC_DIS BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TQPNT2 (Offset 0x021C) */ #define BIT_SHIFT_LPQ_HIGH_TH 8 #define BIT_MASK_LPQ_HIGH_TH 0xff #define BIT_LPQ_HIGH_TH(x) \ (((x) & BIT_MASK_LPQ_HIGH_TH) << BIT_SHIFT_LPQ_HIGH_TH) #define BITS_LPQ_HIGH_TH (BIT_MASK_LPQ_HIGH_TH << BIT_SHIFT_LPQ_HIGH_TH) #define BIT_CLEAR_LPQ_HIGH_TH(x) ((x) & (~BITS_LPQ_HIGH_TH)) #define BIT_GET_LPQ_HIGH_TH(x) \ (((x) >> BIT_SHIFT_LPQ_HIGH_TH) & BIT_MASK_LPQ_HIGH_TH) #define BIT_SET_LPQ_HIGH_TH(x, v) \ (BIT_CLEAR_LPQ_HIGH_TH(x) | BIT_LPQ_HIGH_TH(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_RQPN_CTRL_2_V1 (Offset 0x021C) */ #define BIT_CH8_PUBLIC_DIS BIT(8) #define BIT_CH7_PUBLIC_DIS BIT(7) #define BIT_CH6_PUBLIC_DIS BIT(6) #define BIT_CH5_PUBLIC_DIS BIT(5) #define BIT_CH4_PUBLIC_DIS BIT(4) #define BIT_CH3_PUBLIC_DIS BIT(3) #define BIT_CH2_PUBLIC_DIS BIT(2) #define BIT_CH1_PUBLIC_DIS BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TQPNT2 (Offset 0x021C) */ #define BIT_SHIFT_LPQ_LOW_TH 0 #define BIT_MASK_LPQ_LOW_TH 0xff #define BIT_LPQ_LOW_TH(x) (((x) & BIT_MASK_LPQ_LOW_TH) << BIT_SHIFT_LPQ_LOW_TH) #define BITS_LPQ_LOW_TH (BIT_MASK_LPQ_LOW_TH << BIT_SHIFT_LPQ_LOW_TH) #define BIT_CLEAR_LPQ_LOW_TH(x) ((x) & (~BITS_LPQ_LOW_TH)) #define BIT_GET_LPQ_LOW_TH(x) \ (((x) >> BIT_SHIFT_LPQ_LOW_TH) & BIT_MASK_LPQ_LOW_TH) #define BIT_SET_LPQ_LOW_TH(x, v) (BIT_CLEAR_LPQ_LOW_TH(x) | BIT_LPQ_LOW_TH(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_TQPNT2 (Offset 0x021C) */ #define BIT_SHIFT_NPQ_LOW_TH_V1 0 #define BIT_MASK_NPQ_LOW_TH_V1 0xfff #define BIT_NPQ_LOW_TH_V1(x) \ (((x) & BIT_MASK_NPQ_LOW_TH_V1) << BIT_SHIFT_NPQ_LOW_TH_V1) #define BITS_NPQ_LOW_TH_V1 (BIT_MASK_NPQ_LOW_TH_V1 << BIT_SHIFT_NPQ_LOW_TH_V1) #define BIT_CLEAR_NPQ_LOW_TH_V1(x) ((x) & (~BITS_NPQ_LOW_TH_V1)) #define BIT_GET_NPQ_LOW_TH_V1(x) \ (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1) & BIT_MASK_NPQ_LOW_TH_V1) #define BIT_SET_NPQ_LOW_TH_V1(x, v) \ (BIT_CLEAR_NPQ_LOW_TH_V1(x) | BIT_NPQ_LOW_TH_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_RQPN_CTRL_2_V1 (Offset 0x021C) */ #define BIT_CH0_PUBLIC_DIS BIT(0) /* 2 REG_BCN_CTRL_2 (Offset 0x0220) */ #define BIT_BCN0_EXT_VALID BIT(31) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TQPNT3 (Offset 0x0220) */ #define BIT_LPQ_INT_EN BIT(31) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_TQPNT3 (Offset 0x0220) */ #define BIT_SHIFT_LPQ_HIGH_TH_V1 16 #define BIT_MASK_LPQ_HIGH_TH_V1 0xfff #define BIT_LPQ_HIGH_TH_V1(x) \ (((x) & BIT_MASK_LPQ_HIGH_TH_V1) << BIT_SHIFT_LPQ_HIGH_TH_V1) #define BITS_LPQ_HIGH_TH_V1 \ (BIT_MASK_LPQ_HIGH_TH_V1 << BIT_SHIFT_LPQ_HIGH_TH_V1) #define BIT_CLEAR_LPQ_HIGH_TH_V1(x) ((x) & (~BITS_LPQ_HIGH_TH_V1)) #define BIT_GET_LPQ_HIGH_TH_V1(x) \ (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1) & BIT_MASK_LPQ_HIGH_TH_V1) #define BIT_SET_LPQ_HIGH_TH_V1(x, v) \ (BIT_CLEAR_LPQ_HIGH_TH_V1(x) | BIT_LPQ_HIGH_TH_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_BCN_CTRL_2 (Offset 0x0220) */ #define BIT_SHIFT_BCN0_EXT_HEAD 16 #define BIT_MASK_BCN0_EXT_HEAD 0xfff #define BIT_BCN0_EXT_HEAD(x) \ (((x) & BIT_MASK_BCN0_EXT_HEAD) << BIT_SHIFT_BCN0_EXT_HEAD) #define BITS_BCN0_EXT_HEAD (BIT_MASK_BCN0_EXT_HEAD << BIT_SHIFT_BCN0_EXT_HEAD) #define BIT_CLEAR_BCN0_EXT_HEAD(x) ((x) & (~BITS_BCN0_EXT_HEAD)) #define BIT_GET_BCN0_EXT_HEAD(x) \ (((x) >> BIT_SHIFT_BCN0_EXT_HEAD) & BIT_MASK_BCN0_EXT_HEAD) #define BIT_SET_BCN0_EXT_HEAD(x, v) \ (BIT_CLEAR_BCN0_EXT_HEAD(x) | BIT_BCN0_EXT_HEAD(v)) #define BIT_SHIFT_TXPKTNUM_CH4_7 16 #define BIT_MASK_TXPKTNUM_CH4_7 0xfff #define BIT_TXPKTNUM_CH4_7(x) \ (((x) & BIT_MASK_TXPKTNUM_CH4_7) << BIT_SHIFT_TXPKTNUM_CH4_7) #define BITS_TXPKTNUM_CH4_7 \ (BIT_MASK_TXPKTNUM_CH4_7 << BIT_SHIFT_TXPKTNUM_CH4_7) #define BIT_CLEAR_TXPKTNUM_CH4_7(x) ((x) & (~BITS_TXPKTNUM_CH4_7)) #define BIT_GET_TXPKTNUM_CH4_7(x) \ (((x) >> BIT_SHIFT_TXPKTNUM_CH4_7) & BIT_MASK_TXPKTNUM_CH4_7) #define BIT_SET_TXPKTNUM_CH4_7(x, v) \ (BIT_CLEAR_TXPKTNUM_CH4_7(x) | BIT_TXPKTNUM_CH4_7(v)) #define BIT_SHIFT_TXPKTNUM_CH12 16 #define BIT_MASK_TXPKTNUM_CH12 0xfff #define BIT_TXPKTNUM_CH12(x) \ (((x) & BIT_MASK_TXPKTNUM_CH12) << BIT_SHIFT_TXPKTNUM_CH12) #define BITS_TXPKTNUM_CH12 (BIT_MASK_TXPKTNUM_CH12 << BIT_SHIFT_TXPKTNUM_CH12) #define BIT_CLEAR_TXPKTNUM_CH12(x) ((x) & (~BITS_TXPKTNUM_CH12)) #define BIT_GET_TXPKTNUM_CH12(x) \ (((x) >> BIT_SHIFT_TXPKTNUM_CH12) & BIT_MASK_TXPKTNUM_CH12) #define BIT_SET_TXPKTNUM_CH12(x, v) \ (BIT_CLEAR_TXPKTNUM_CH12(x) | BIT_TXPKTNUM_CH12(v)) #define BIT_SHIFT_TXPKTNUM_CH14_15 16 #define BIT_MASK_TXPKTNUM_CH14_15 0xfff #define BIT_TXPKTNUM_CH14_15(x) \ (((x) & BIT_MASK_TXPKTNUM_CH14_15) << BIT_SHIFT_TXPKTNUM_CH14_15) #define BITS_TXPKTNUM_CH14_15 \ (BIT_MASK_TXPKTNUM_CH14_15 << BIT_SHIFT_TXPKTNUM_CH14_15) #define BIT_CLEAR_TXPKTNUM_CH14_15(x) ((x) & (~BITS_TXPKTNUM_CH14_15)) #define BIT_GET_TXPKTNUM_CH14_15(x) \ (((x) >> BIT_SHIFT_TXPKTNUM_CH14_15) & BIT_MASK_TXPKTNUM_CH14_15) #define BIT_SET_TXPKTNUM_CH14_15(x, v) \ (BIT_CLEAR_TXPKTNUM_CH14_15(x) | BIT_TXPKTNUM_CH14_15(v)) #define BIT_BCN4_VALID BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TDE_DEBUG (Offset 0x0220) */ #define BIT_SHIFT_TDE_DEBUG 0 #define BIT_MASK_TDE_DEBUG 0xffffffffL #define BIT_TDE_DEBUG(x) (((x) & BIT_MASK_TDE_DEBUG) << BIT_SHIFT_TDE_DEBUG) #define BITS_TDE_DEBUG (BIT_MASK_TDE_DEBUG << BIT_SHIFT_TDE_DEBUG) #define BIT_CLEAR_TDE_DEBUG(x) ((x) & (~BITS_TDE_DEBUG)) #define BIT_GET_TDE_DEBUG(x) (((x) >> BIT_SHIFT_TDE_DEBUG) & BIT_MASK_TDE_DEBUG) #define BIT_SET_TDE_DEBUG(x, v) (BIT_CLEAR_TDE_DEBUG(x) | BIT_TDE_DEBUG(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_TQPNT3 (Offset 0x0220) */ #define BIT_SHIFT_LPQ_LOW_TH_V1 0 #define BIT_MASK_LPQ_LOW_TH_V1 0xfff #define BIT_LPQ_LOW_TH_V1(x) \ (((x) & BIT_MASK_LPQ_LOW_TH_V1) << BIT_SHIFT_LPQ_LOW_TH_V1) #define BITS_LPQ_LOW_TH_V1 (BIT_MASK_LPQ_LOW_TH_V1 << BIT_SHIFT_LPQ_LOW_TH_V1) #define BIT_CLEAR_LPQ_LOW_TH_V1(x) ((x) & (~BITS_LPQ_LOW_TH_V1)) #define BIT_GET_LPQ_LOW_TH_V1(x) \ (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1) & BIT_MASK_LPQ_LOW_TH_V1) #define BIT_SET_LPQ_LOW_TH_V1(x, v) \ (BIT_CLEAR_LPQ_LOW_TH_V1(x) | BIT_LPQ_LOW_TH_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_BCN_CTRL_2 (Offset 0x0220) */ #define BIT_SHIFT_BCN4_HEAD 0 #define BIT_MASK_BCN4_HEAD 0xfff #define BIT_BCN4_HEAD(x) (((x) & BIT_MASK_BCN4_HEAD) << BIT_SHIFT_BCN4_HEAD) #define BITS_BCN4_HEAD (BIT_MASK_BCN4_HEAD << BIT_SHIFT_BCN4_HEAD) #define BIT_CLEAR_BCN4_HEAD(x) ((x) & (~BITS_BCN4_HEAD)) #define BIT_GET_BCN4_HEAD(x) (((x) >> BIT_SHIFT_BCN4_HEAD) & BIT_MASK_BCN4_HEAD) #define BIT_SET_BCN4_HEAD(x, v) (BIT_CLEAR_BCN4_HEAD(x) | BIT_BCN4_HEAD(v)) #define BIT_SHIFT_TXPKTNUM_CH0_3 0 #define BIT_MASK_TXPKTNUM_CH0_3 0xfff #define BIT_TXPKTNUM_CH0_3(x) \ (((x) & BIT_MASK_TXPKTNUM_CH0_3) << BIT_SHIFT_TXPKTNUM_CH0_3) #define BITS_TXPKTNUM_CH0_3 \ (BIT_MASK_TXPKTNUM_CH0_3 << BIT_SHIFT_TXPKTNUM_CH0_3) #define BIT_CLEAR_TXPKTNUM_CH0_3(x) ((x) & (~BITS_TXPKTNUM_CH0_3)) #define BIT_GET_TXPKTNUM_CH0_3(x) \ (((x) >> BIT_SHIFT_TXPKTNUM_CH0_3) & BIT_MASK_TXPKTNUM_CH0_3) #define BIT_SET_TXPKTNUM_CH0_3(x, v) \ (BIT_CLEAR_TXPKTNUM_CH0_3(x) | BIT_TXPKTNUM_CH0_3(v)) #define BIT_SHIFT_TXPKTNUM_CH8_11 0 #define BIT_MASK_TXPKTNUM_CH8_11 0xfff #define BIT_TXPKTNUM_CH8_11(x) \ (((x) & BIT_MASK_TXPKTNUM_CH8_11) << BIT_SHIFT_TXPKTNUM_CH8_11) #define BITS_TXPKTNUM_CH8_11 \ (BIT_MASK_TXPKTNUM_CH8_11 << BIT_SHIFT_TXPKTNUM_CH8_11) #define BIT_CLEAR_TXPKTNUM_CH8_11(x) ((x) & (~BITS_TXPKTNUM_CH8_11)) #define BIT_GET_TXPKTNUM_CH8_11(x) \ (((x) >> BIT_SHIFT_TXPKTNUM_CH8_11) & BIT_MASK_TXPKTNUM_CH8_11) #define BIT_SET_TXPKTNUM_CH8_11(x, v) \ (BIT_CLEAR_TXPKTNUM_CH8_11(x) | BIT_TXPKTNUM_CH8_11(v)) #define BIT_SHIFT_TXPKTNUM_CH13 0 #define BIT_MASK_TXPKTNUM_CH13 0xfff #define BIT_TXPKTNUM_CH13(x) \ (((x) & BIT_MASK_TXPKTNUM_CH13) << BIT_SHIFT_TXPKTNUM_CH13) #define BITS_TXPKTNUM_CH13 (BIT_MASK_TXPKTNUM_CH13 << BIT_SHIFT_TXPKTNUM_CH13) #define BIT_CLEAR_TXPKTNUM_CH13(x) ((x) & (~BITS_TXPKTNUM_CH13)) #define BIT_GET_TXPKTNUM_CH13(x) \ (((x) >> BIT_SHIFT_TXPKTNUM_CH13) & BIT_MASK_TXPKTNUM_CH13) #define BIT_SET_TXPKTNUM_CH13(x, v) \ (BIT_CLEAR_TXPKTNUM_CH13(x) | BIT_TXPKTNUM_CH13(v)) #define BIT_SHIFT_TXPKTNUM_CH16 0 #define BIT_MASK_TXPKTNUM_CH16 0xfff #define BIT_TXPKTNUM_CH16(x) \ (((x) & BIT_MASK_TXPKTNUM_CH16) << BIT_SHIFT_TXPKTNUM_CH16) #define BITS_TXPKTNUM_CH16 (BIT_MASK_TXPKTNUM_CH16 << BIT_SHIFT_TXPKTNUM_CH16) #define BIT_CLEAR_TXPKTNUM_CH16(x) ((x) & (~BITS_TXPKTNUM_CH16)) #define BIT_GET_TXPKTNUM_CH16(x) \ (((x) >> BIT_SHIFT_TXPKTNUM_CH16) & BIT_MASK_TXPKTNUM_CH16) #define BIT_SET_TXPKTNUM_CH16(x, v) \ (BIT_CLEAR_TXPKTNUM_CH16(x) | BIT_TXPKTNUM_CH16(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TQPNT4 (Offset 0x0224) */ #define BIT_EXQ_INT_EN BIT(31) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AUTO_LLT (Offset 0x0224) */ #define BIT_SHIFT_TXPKTNUM_V1 24 #define BIT_MASK_TXPKTNUM_V1 0xff #define BIT_TXPKTNUM_V1(x) \ (((x) & BIT_MASK_TXPKTNUM_V1) << BIT_SHIFT_TXPKTNUM_V1) #define BITS_TXPKTNUM_V1 (BIT_MASK_TXPKTNUM_V1 << BIT_SHIFT_TXPKTNUM_V1) #define BIT_CLEAR_TXPKTNUM_V1(x) ((x) & (~BITS_TXPKTNUM_V1)) #define BIT_GET_TXPKTNUM_V1(x) \ (((x) >> BIT_SHIFT_TXPKTNUM_V1) & BIT_MASK_TXPKTNUM_V1) #define BIT_SET_TXPKTNUM_V1(x, v) \ (BIT_CLEAR_TXPKTNUM_V1(x) | BIT_TXPKTNUM_V1(v)) #define BIT_TDE_DBG_SEL BIT(23) #define BIT_AUTO_INIT_LLT BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_TQPNT4 (Offset 0x0224) */ #define BIT_SHIFT_EXQ_HIGH_TH_V1 16 #define BIT_MASK_EXQ_HIGH_TH_V1 0xfff #define BIT_EXQ_HIGH_TH_V1(x) \ (((x) & BIT_MASK_EXQ_HIGH_TH_V1) << BIT_SHIFT_EXQ_HIGH_TH_V1) #define BITS_EXQ_HIGH_TH_V1 \ (BIT_MASK_EXQ_HIGH_TH_V1 << BIT_SHIFT_EXQ_HIGH_TH_V1) #define BIT_CLEAR_EXQ_HIGH_TH_V1(x) ((x) & (~BITS_EXQ_HIGH_TH_V1)) #define BIT_GET_EXQ_HIGH_TH_V1(x) \ (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1) & BIT_MASK_EXQ_HIGH_TH_V1) #define BIT_SET_EXQ_HIGH_TH_V1(x, v) \ (BIT_CLEAR_EXQ_HIGH_TH_V1(x) | BIT_EXQ_HIGH_TH_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AUTO_LLT (Offset 0x0224) */ #define BIT_SHIFT_TX_OQT_HE_FREE_SPACE 8 #define BIT_MASK_TX_OQT_HE_FREE_SPACE 0xff #define BIT_TX_OQT_HE_FREE_SPACE(x) \ (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE) \ << BIT_SHIFT_TX_OQT_HE_FREE_SPACE) #define BITS_TX_OQT_HE_FREE_SPACE \ (BIT_MASK_TX_OQT_HE_FREE_SPACE << BIT_SHIFT_TX_OQT_HE_FREE_SPACE) #define BIT_CLEAR_TX_OQT_HE_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_HE_FREE_SPACE)) #define BIT_GET_TX_OQT_HE_FREE_SPACE(x) \ (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE) & \ BIT_MASK_TX_OQT_HE_FREE_SPACE) #define BIT_SET_TX_OQT_HE_FREE_SPACE(x, v) \ (BIT_CLEAR_TX_OQT_HE_FREE_SPACE(x) | BIT_TX_OQT_HE_FREE_SPACE(v)) #define BIT_SHIFT_TX_OQT_NL_FREE_SPACE 0 #define BIT_MASK_TX_OQT_NL_FREE_SPACE 0xff #define BIT_TX_OQT_NL_FREE_SPACE(x) \ (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE) \ << BIT_SHIFT_TX_OQT_NL_FREE_SPACE) #define BITS_TX_OQT_NL_FREE_SPACE \ (BIT_MASK_TX_OQT_NL_FREE_SPACE << BIT_SHIFT_TX_OQT_NL_FREE_SPACE) #define BIT_CLEAR_TX_OQT_NL_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_NL_FREE_SPACE)) #define BIT_GET_TX_OQT_NL_FREE_SPACE(x) \ (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE) & \ BIT_MASK_TX_OQT_NL_FREE_SPACE) #define BIT_SET_TX_OQT_NL_FREE_SPACE(x, v) \ (BIT_CLEAR_TX_OQT_NL_FREE_SPACE(x) | BIT_TX_OQT_NL_FREE_SPACE(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_TQPNT4 (Offset 0x0224) */ #define BIT_SHIFT_EXQ_LOW_TH_V1 0 #define BIT_MASK_EXQ_LOW_TH_V1 0xfff #define BIT_EXQ_LOW_TH_V1(x) \ (((x) & BIT_MASK_EXQ_LOW_TH_V1) << BIT_SHIFT_EXQ_LOW_TH_V1) #define BITS_EXQ_LOW_TH_V1 (BIT_MASK_EXQ_LOW_TH_V1 << BIT_SHIFT_EXQ_LOW_TH_V1) #define BIT_CLEAR_EXQ_LOW_TH_V1(x) ((x) & (~BITS_EXQ_LOW_TH_V1)) #define BIT_GET_EXQ_LOW_TH_V1(x) \ (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1) & BIT_MASK_EXQ_LOW_TH_V1) #define BIT_SET_EXQ_LOW_TH_V1(x, v) \ (BIT_CLEAR_EXQ_LOW_TH_V1(x) | BIT_EXQ_LOW_TH_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DWBCN1_CTRL (Offset 0x0228) */ #define BIT_SW_BCN_SEL BIT(20) #define BIT_SW_BCN_SEL_EN BIT(17) #define BIT_BCN_VALID_1 BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ #define BIT_SHIFT_TXPKTNUM_H 16 #define BIT_MASK_TXPKTNUM_H 0xffff #define BIT_TXPKTNUM_H(x) (((x) & BIT_MASK_TXPKTNUM_H) << BIT_SHIFT_TXPKTNUM_H) #define BITS_TXPKTNUM_H (BIT_MASK_TXPKTNUM_H << BIT_SHIFT_TXPKTNUM_H) #define BIT_CLEAR_TXPKTNUM_H(x) ((x) & (~BITS_TXPKTNUM_H)) #define BIT_GET_TXPKTNUM_H(x) \ (((x) >> BIT_SHIFT_TXPKTNUM_H) & BIT_MASK_TXPKTNUM_H) #define BIT_SET_TXPKTNUM_H(x, v) (BIT_CLEAR_TXPKTNUM_H(x) | BIT_TXPKTNUM_H(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ #define BIT_SHIFT_TXPKTNUM_H_V2 16 #define BIT_MASK_TXPKTNUM_H_V2 0xfff #define BIT_TXPKTNUM_H_V2(x) \ (((x) & BIT_MASK_TXPKTNUM_H_V2) << BIT_SHIFT_TXPKTNUM_H_V2) #define BITS_TXPKTNUM_H_V2 (BIT_MASK_TXPKTNUM_H_V2 << BIT_SHIFT_TXPKTNUM_H_V2) #define BIT_CLEAR_TXPKTNUM_H_V2(x) ((x) & (~BITS_TXPKTNUM_H_V2)) #define BIT_GET_TXPKTNUM_H_V2(x) \ (((x) >> BIT_SHIFT_TXPKTNUM_H_V2) & BIT_MASK_TXPKTNUM_H_V2) #define BIT_SET_TXPKTNUM_H_V2(x, v) \ (BIT_CLEAR_TXPKTNUM_H_V2(x) | BIT_TXPKTNUM_H_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DWBCN1_CTRL (Offset 0x0228) */ #define BIT_SHIFT_BCN_HEAD_1 8 #define BIT_MASK_BCN_HEAD_1 0xff #define BIT_BCN_HEAD_1(x) (((x) & BIT_MASK_BCN_HEAD_1) << BIT_SHIFT_BCN_HEAD_1) #define BITS_BCN_HEAD_1 (BIT_MASK_BCN_HEAD_1 << BIT_SHIFT_BCN_HEAD_1) #define BIT_CLEAR_BCN_HEAD_1(x) ((x) & (~BITS_BCN_HEAD_1)) #define BIT_GET_BCN_HEAD_1(x) \ (((x) >> BIT_SHIFT_BCN_HEAD_1) & BIT_MASK_BCN_HEAD_1) #define BIT_SET_BCN_HEAD_1(x, v) (BIT_CLEAR_BCN_HEAD_1(x) | BIT_BCN_HEAD_1(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ #define BIT_RST_PGSUB_CNT BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DWBCN1_CTRL (Offset 0x0228) */ #define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO 0 #define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO 0xff #define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO(x) \ (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO) \ << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO) #define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO \ (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO \ << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO) #define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO(x) \ ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO)) #define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO(x) \ (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO) & \ BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO) #define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO(x, v) \ (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO(x) | \ BIT_MAX_TX_PKT_FOR_USB_AND_SDIO(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ #define BIT_SHIFT_TXPKTNUM_H_V1 0 #define BIT_MASK_TXPKTNUM_H_V1 0xffff #define BIT_TXPKTNUM_H_V1(x) \ (((x) & BIT_MASK_TXPKTNUM_H_V1) << BIT_SHIFT_TXPKTNUM_H_V1) #define BITS_TXPKTNUM_H_V1 (BIT_MASK_TXPKTNUM_H_V1 << BIT_SHIFT_TXPKTNUM_H_V1) #define BIT_CLEAR_TXPKTNUM_H_V1(x) ((x) & (~BITS_TXPKTNUM_H_V1)) #define BIT_GET_TXPKTNUM_H_V1(x) \ (((x) >> BIT_SHIFT_TXPKTNUM_H_V1) & BIT_MASK_TXPKTNUM_H_V1) #define BIT_SET_TXPKTNUM_H_V1(x, v) \ (BIT_CLEAR_TXPKTNUM_H_V1(x) | BIT_TXPKTNUM_H_V1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ #define BIT_SHIFT_TXPKTNUM_V2 0 #define BIT_MASK_TXPKTNUM_V2 0xffff #define BIT_TXPKTNUM_V2(x) \ (((x) & BIT_MASK_TXPKTNUM_V2) << BIT_SHIFT_TXPKTNUM_V2) #define BITS_TXPKTNUM_V2 (BIT_MASK_TXPKTNUM_V2 << BIT_SHIFT_TXPKTNUM_V2) #define BIT_CLEAR_TXPKTNUM_V2(x) ((x) & (~BITS_TXPKTNUM_V2)) #define BIT_GET_TXPKTNUM_V2(x) \ (((x) >> BIT_SHIFT_TXPKTNUM_V2) & BIT_MASK_TXPKTNUM_V2) #define BIT_SET_TXPKTNUM_V2(x, v) \ (BIT_CLEAR_TXPKTNUM_V2(x) | BIT_TXPKTNUM_V2(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ #define BIT_SHIFT_TXPKTNUM_V3 0 #define BIT_MASK_TXPKTNUM_V3 0xfff #define BIT_TXPKTNUM_V3(x) \ (((x) & BIT_MASK_TXPKTNUM_V3) << BIT_SHIFT_TXPKTNUM_V3) #define BITS_TXPKTNUM_V3 (BIT_MASK_TXPKTNUM_V3 << BIT_SHIFT_TXPKTNUM_V3) #define BIT_CLEAR_TXPKTNUM_V3(x) ((x) & (~BITS_TXPKTNUM_V3)) #define BIT_GET_TXPKTNUM_V3(x) \ (((x) >> BIT_SHIFT_TXPKTNUM_V3) & BIT_MASK_TXPKTNUM_V3) #define BIT_SET_TXPKTNUM_V3(x, v) \ (BIT_CLEAR_TXPKTNUM_V3(x) | BIT_TXPKTNUM_V3(v)) #define BIT_PGSUB_CNT_EN BIT(0) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */ #define BIT_EX2Q_PUBLIC_DIS_V1 BIT(21) #define BIT_EX1Q_PUBLIC_DIS_V1 BIT(20) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */ #define BIT_EXQ_PUBLIC_DIS_V1 BIT(19) #define BIT_NPQ_PUBLIC_DIS_V1 BIT(18) #define BIT_LPQ_PUBLIC_DIS_V1 BIT(17) #define BIT_HPQ_PUBLIC_DIS_V1 BIT(16) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */ #define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN BIT(15) #define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE 0 #define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE 0xfff #define BIT_SDIO_TXAGG_ALIGN_SIZE(x) \ (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE) \ << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE) #define BITS_SDIO_TXAGG_ALIGN_SIZE \ (BIT_MASK_SDIO_TXAGG_ALIGN_SIZE << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE) #define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE(x) ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE)) #define BIT_GET_SDIO_TXAGG_ALIGN_SIZE(x) \ (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE) & \ BIT_MASK_SDIO_TXAGG_ALIGN_SIZE) #define BIT_SET_SDIO_TXAGG_ALIGN_SIZE(x, v) \ (BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE(x) | BIT_SDIO_TXAGG_ALIGN_SIZE(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FIFOPAGE_INFO_1 (Offset 0x0230) */ #define BIT_SHIFT_HPQ_AVAL_PG_V1 16 #define BIT_MASK_HPQ_AVAL_PG_V1 0xfff #define BIT_HPQ_AVAL_PG_V1(x) \ (((x) & BIT_MASK_HPQ_AVAL_PG_V1) << BIT_SHIFT_HPQ_AVAL_PG_V1) #define BITS_HPQ_AVAL_PG_V1 \ (BIT_MASK_HPQ_AVAL_PG_V1 << BIT_SHIFT_HPQ_AVAL_PG_V1) #define BIT_CLEAR_HPQ_AVAL_PG_V1(x) ((x) & (~BITS_HPQ_AVAL_PG_V1)) #define BIT_GET_HPQ_AVAL_PG_V1(x) \ (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1) & BIT_MASK_HPQ_AVAL_PG_V1) #define BIT_SET_HPQ_AVAL_PG_V1(x, v) \ (BIT_CLEAR_HPQ_AVAL_PG_V1(x) | BIT_HPQ_AVAL_PG_V1(v)) #define BIT_SHIFT_HPQ_V1 0 #define BIT_MASK_HPQ_V1 0xfff #define BIT_HPQ_V1(x) (((x) & BIT_MASK_HPQ_V1) << BIT_SHIFT_HPQ_V1) #define BITS_HPQ_V1 (BIT_MASK_HPQ_V1 << BIT_SHIFT_HPQ_V1) #define BIT_CLEAR_HPQ_V1(x) ((x) & (~BITS_HPQ_V1)) #define BIT_GET_HPQ_V1(x) (((x) >> BIT_SHIFT_HPQ_V1) & BIT_MASK_HPQ_V1) #define BIT_SET_HPQ_V1(x, v) (BIT_CLEAR_HPQ_V1(x) | BIT_HPQ_V1(v)) /* 2 REG_FIFOPAGE_INFO_2 (Offset 0x0234) */ #define BIT_SHIFT_LPQ_AVAL_PG_V1 16 #define BIT_MASK_LPQ_AVAL_PG_V1 0xfff #define BIT_LPQ_AVAL_PG_V1(x) \ (((x) & BIT_MASK_LPQ_AVAL_PG_V1) << BIT_SHIFT_LPQ_AVAL_PG_V1) #define BITS_LPQ_AVAL_PG_V1 \ (BIT_MASK_LPQ_AVAL_PG_V1 << BIT_SHIFT_LPQ_AVAL_PG_V1) #define BIT_CLEAR_LPQ_AVAL_PG_V1(x) ((x) & (~BITS_LPQ_AVAL_PG_V1)) #define BIT_GET_LPQ_AVAL_PG_V1(x) \ (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1) & BIT_MASK_LPQ_AVAL_PG_V1) #define BIT_SET_LPQ_AVAL_PG_V1(x, v) \ (BIT_CLEAR_LPQ_AVAL_PG_V1(x) | BIT_LPQ_AVAL_PG_V1(v)) #define BIT_SHIFT_LPQ_V1 0 #define BIT_MASK_LPQ_V1 0xfff #define BIT_LPQ_V1(x) (((x) & BIT_MASK_LPQ_V1) << BIT_SHIFT_LPQ_V1) #define BITS_LPQ_V1 (BIT_MASK_LPQ_V1 << BIT_SHIFT_LPQ_V1) #define BIT_CLEAR_LPQ_V1(x) ((x) & (~BITS_LPQ_V1)) #define BIT_GET_LPQ_V1(x) (((x) >> BIT_SHIFT_LPQ_V1) & BIT_MASK_LPQ_V1) #define BIT_SET_LPQ_V1(x, v) (BIT_CLEAR_LPQ_V1(x) | BIT_LPQ_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */ #define BIT_SHIFT_NPQ_AVAL_PG_V1 16 #define BIT_MASK_NPQ_AVAL_PG_V1 0xfff #define BIT_NPQ_AVAL_PG_V1(x) \ (((x) & BIT_MASK_NPQ_AVAL_PG_V1) << BIT_SHIFT_NPQ_AVAL_PG_V1) #define BITS_NPQ_AVAL_PG_V1 \ (BIT_MASK_NPQ_AVAL_PG_V1 << BIT_SHIFT_NPQ_AVAL_PG_V1) #define BIT_CLEAR_NPQ_AVAL_PG_V1(x) ((x) & (~BITS_NPQ_AVAL_PG_V1)) #define BIT_GET_NPQ_AVAL_PG_V1(x) \ (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1) & BIT_MASK_NPQ_AVAL_PG_V1) #define BIT_SET_NPQ_AVAL_PG_V1(x, v) \ (BIT_CLEAR_NPQ_AVAL_PG_V1(x) | BIT_NPQ_AVAL_PG_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */ #define BIT_SHIFT_NPQ_V1 0 #define BIT_MASK_NPQ_V1 0xfff #define BIT_NPQ_V1(x) (((x) & BIT_MASK_NPQ_V1) << BIT_SHIFT_NPQ_V1) #define BITS_NPQ_V1 (BIT_MASK_NPQ_V1 << BIT_SHIFT_NPQ_V1) #define BIT_CLEAR_NPQ_V1(x) ((x) & (~BITS_NPQ_V1)) #define BIT_GET_NPQ_V1(x) (((x) >> BIT_SHIFT_NPQ_V1) & BIT_MASK_NPQ_V1) #define BIT_SET_NPQ_V1(x, v) (BIT_CLEAR_NPQ_V1(x) | BIT_NPQ_V1(v)) /* 2 REG_FIFOPAGE_INFO_4 (Offset 0x023C) */ #define BIT_SHIFT_EXQ_AVAL_PG_V1 16 #define BIT_MASK_EXQ_AVAL_PG_V1 0xfff #define BIT_EXQ_AVAL_PG_V1(x) \ (((x) & BIT_MASK_EXQ_AVAL_PG_V1) << BIT_SHIFT_EXQ_AVAL_PG_V1) #define BITS_EXQ_AVAL_PG_V1 \ (BIT_MASK_EXQ_AVAL_PG_V1 << BIT_SHIFT_EXQ_AVAL_PG_V1) #define BIT_CLEAR_EXQ_AVAL_PG_V1(x) ((x) & (~BITS_EXQ_AVAL_PG_V1)) #define BIT_GET_EXQ_AVAL_PG_V1(x) \ (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1) & BIT_MASK_EXQ_AVAL_PG_V1) #define BIT_SET_EXQ_AVAL_PG_V1(x, v) \ (BIT_CLEAR_EXQ_AVAL_PG_V1(x) | BIT_EXQ_AVAL_PG_V1(v)) #define BIT_SHIFT_EXQ_V1 0 #define BIT_MASK_EXQ_V1 0xfff #define BIT_EXQ_V1(x) (((x) & BIT_MASK_EXQ_V1) << BIT_SHIFT_EXQ_V1) #define BITS_EXQ_V1 (BIT_MASK_EXQ_V1 << BIT_SHIFT_EXQ_V1) #define BIT_CLEAR_EXQ_V1(x) ((x) & (~BITS_EXQ_V1)) #define BIT_GET_EXQ_V1(x) (((x) >> BIT_SHIFT_EXQ_V1) & BIT_MASK_EXQ_V1) #define BIT_SET_EXQ_V1(x, v) (BIT_CLEAR_EXQ_V1(x) | BIT_EXQ_V1(v)) /* 2 REG_FIFOPAGE_INFO_5 (Offset 0x0240) */ #define BIT_SHIFT_PUBQ_AVAL_PG_V1 16 #define BIT_MASK_PUBQ_AVAL_PG_V1 0xfff #define BIT_PUBQ_AVAL_PG_V1(x) \ (((x) & BIT_MASK_PUBQ_AVAL_PG_V1) << BIT_SHIFT_PUBQ_AVAL_PG_V1) #define BITS_PUBQ_AVAL_PG_V1 \ (BIT_MASK_PUBQ_AVAL_PG_V1 << BIT_SHIFT_PUBQ_AVAL_PG_V1) #define BIT_CLEAR_PUBQ_AVAL_PG_V1(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1)) #define BIT_GET_PUBQ_AVAL_PG_V1(x) \ (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1) & BIT_MASK_PUBQ_AVAL_PG_V1) #define BIT_SET_PUBQ_AVAL_PG_V1(x, v) \ (BIT_CLEAR_PUBQ_AVAL_PG_V1(x) | BIT_PUBQ_AVAL_PG_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TX_AGG_ALIGN (Offset 0x0240) */ #define BIT_SHIFT_HW_FLOW_CTL_EN 16 #define BIT_MASK_HW_FLOW_CTL_EN 0xffff #define BIT_HW_FLOW_CTL_EN(x) \ (((x) & BIT_MASK_HW_FLOW_CTL_EN) << BIT_SHIFT_HW_FLOW_CTL_EN) #define BITS_HW_FLOW_CTL_EN \ (BIT_MASK_HW_FLOW_CTL_EN << BIT_SHIFT_HW_FLOW_CTL_EN) #define BIT_CLEAR_HW_FLOW_CTL_EN(x) ((x) & (~BITS_HW_FLOW_CTL_EN)) #define BIT_GET_HW_FLOW_CTL_EN(x) \ (((x) >> BIT_SHIFT_HW_FLOW_CTL_EN) & BIT_MASK_HW_FLOW_CTL_EN) #define BIT_SET_HW_FLOW_CTL_EN(x, v) \ (BIT_CLEAR_HW_FLOW_CTL_EN(x) | BIT_HW_FLOW_CTL_EN(v)) #define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_V1 BIT(15) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FIFOPAGE_INFO_5 (Offset 0x0240) */ #define BIT_SHIFT_PUBQ_V1 0 #define BIT_MASK_PUBQ_V1 0xfff #define BIT_PUBQ_V1(x) (((x) & BIT_MASK_PUBQ_V1) << BIT_SHIFT_PUBQ_V1) #define BITS_PUBQ_V1 (BIT_MASK_PUBQ_V1 << BIT_SHIFT_PUBQ_V1) #define BIT_CLEAR_PUBQ_V1(x) ((x) & (~BITS_PUBQ_V1)) #define BIT_GET_PUBQ_V1(x) (((x) >> BIT_SHIFT_PUBQ_V1) & BIT_MASK_PUBQ_V1) #define BIT_SET_PUBQ_V1(x, v) (BIT_CLEAR_PUBQ_V1(x) | BIT_PUBQ_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TX_AGG_ALIGN (Offset 0x0240) */ #define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1 0 #define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1 0xfff #define BIT_SDIO_TXAGG_ALIGN_SIZE_V1(x) \ (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1) \ << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1) #define BITS_SDIO_TXAGG_ALIGN_SIZE_V1 \ (BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1 \ << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1) #define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1(x) \ ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_V1)) #define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_V1(x) \ (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1) & \ BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1) #define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_V1(x, v) \ (BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1(x) | \ BIT_SDIO_TXAGG_ALIGN_SIZE_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_H2C_HEAD (Offset 0x0244) */ #define BIT_SHIFT_H2C_HEAD 0 #define BIT_MASK_H2C_HEAD 0x3ffff #define BIT_H2C_HEAD(x) (((x) & BIT_MASK_H2C_HEAD) << BIT_SHIFT_H2C_HEAD) #define BITS_H2C_HEAD (BIT_MASK_H2C_HEAD << BIT_SHIFT_H2C_HEAD) #define BIT_CLEAR_H2C_HEAD(x) ((x) & (~BITS_H2C_HEAD)) #define BIT_GET_H2C_HEAD(x) (((x) >> BIT_SHIFT_H2C_HEAD) & BIT_MASK_H2C_HEAD) #define BIT_SET_H2C_HEAD(x, v) (BIT_CLEAR_H2C_HEAD(x) | BIT_H2C_HEAD(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_H2C_HEAD (Offset 0x0244) */ #define BIT_SHIFT_H2C_HEAD_V1 0 #define BIT_MASK_H2C_HEAD_V1 0x7ffff #define BIT_H2C_HEAD_V1(x) \ (((x) & BIT_MASK_H2C_HEAD_V1) << BIT_SHIFT_H2C_HEAD_V1) #define BITS_H2C_HEAD_V1 (BIT_MASK_H2C_HEAD_V1 << BIT_SHIFT_H2C_HEAD_V1) #define BIT_CLEAR_H2C_HEAD_V1(x) ((x) & (~BITS_H2C_HEAD_V1)) #define BIT_GET_H2C_HEAD_V1(x) \ (((x) >> BIT_SHIFT_H2C_HEAD_V1) & BIT_MASK_H2C_HEAD_V1) #define BIT_SET_H2C_HEAD_V1(x, v) \ (BIT_CLEAR_H2C_HEAD_V1(x) | BIT_H2C_HEAD_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_H2C_TAIL (Offset 0x0248) */ #define BIT_SHIFT_H2C_TAIL 0 #define BIT_MASK_H2C_TAIL 0x3ffff #define BIT_H2C_TAIL(x) (((x) & BIT_MASK_H2C_TAIL) << BIT_SHIFT_H2C_TAIL) #define BITS_H2C_TAIL (BIT_MASK_H2C_TAIL << BIT_SHIFT_H2C_TAIL) #define BIT_CLEAR_H2C_TAIL(x) ((x) & (~BITS_H2C_TAIL)) #define BIT_GET_H2C_TAIL(x) (((x) >> BIT_SHIFT_H2C_TAIL) & BIT_MASK_H2C_TAIL) #define BIT_SET_H2C_TAIL(x, v) (BIT_CLEAR_H2C_TAIL(x) | BIT_H2C_TAIL(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_H2C_TAIL (Offset 0x0248) */ #define BIT_SHIFT_H2C_TAIL_V1 0 #define BIT_MASK_H2C_TAIL_V1 0x7ffff #define BIT_H2C_TAIL_V1(x) \ (((x) & BIT_MASK_H2C_TAIL_V1) << BIT_SHIFT_H2C_TAIL_V1) #define BITS_H2C_TAIL_V1 (BIT_MASK_H2C_TAIL_V1 << BIT_SHIFT_H2C_TAIL_V1) #define BIT_CLEAR_H2C_TAIL_V1(x) ((x) & (~BITS_H2C_TAIL_V1)) #define BIT_GET_H2C_TAIL_V1(x) \ (((x) >> BIT_SHIFT_H2C_TAIL_V1) & BIT_MASK_H2C_TAIL_V1) #define BIT_SET_H2C_TAIL_V1(x, v) \ (BIT_CLEAR_H2C_TAIL_V1(x) | BIT_H2C_TAIL_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_H2C_READ_ADDR (Offset 0x024C) */ #define BIT_SHIFT_H2C_READ_ADDR 0 #define BIT_MASK_H2C_READ_ADDR 0x3ffff #define BIT_H2C_READ_ADDR(x) \ (((x) & BIT_MASK_H2C_READ_ADDR) << BIT_SHIFT_H2C_READ_ADDR) #define BITS_H2C_READ_ADDR (BIT_MASK_H2C_READ_ADDR << BIT_SHIFT_H2C_READ_ADDR) #define BIT_CLEAR_H2C_READ_ADDR(x) ((x) & (~BITS_H2C_READ_ADDR)) #define BIT_GET_H2C_READ_ADDR(x) \ (((x) >> BIT_SHIFT_H2C_READ_ADDR) & BIT_MASK_H2C_READ_ADDR) #define BIT_SET_H2C_READ_ADDR(x, v) \ (BIT_CLEAR_H2C_READ_ADDR(x) | BIT_H2C_READ_ADDR(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_H2C_READ_ADDR (Offset 0x024C) */ #define BIT_SHIFT_H2C_READ_ADDR_V1 0 #define BIT_MASK_H2C_READ_ADDR_V1 0x7ffff #define BIT_H2C_READ_ADDR_V1(x) \ (((x) & BIT_MASK_H2C_READ_ADDR_V1) << BIT_SHIFT_H2C_READ_ADDR_V1) #define BITS_H2C_READ_ADDR_V1 \ (BIT_MASK_H2C_READ_ADDR_V1 << BIT_SHIFT_H2C_READ_ADDR_V1) #define BIT_CLEAR_H2C_READ_ADDR_V1(x) ((x) & (~BITS_H2C_READ_ADDR_V1)) #define BIT_GET_H2C_READ_ADDR_V1(x) \ (((x) >> BIT_SHIFT_H2C_READ_ADDR_V1) & BIT_MASK_H2C_READ_ADDR_V1) #define BIT_SET_H2C_READ_ADDR_V1(x, v) \ (BIT_CLEAR_H2C_READ_ADDR_V1(x) | BIT_H2C_READ_ADDR_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_H2C_WR_ADDR (Offset 0x0250) */ #define BIT_SHIFT_H2C_WR_ADDR 0 #define BIT_MASK_H2C_WR_ADDR 0x3ffff #define BIT_H2C_WR_ADDR(x) \ (((x) & BIT_MASK_H2C_WR_ADDR) << BIT_SHIFT_H2C_WR_ADDR) #define BITS_H2C_WR_ADDR (BIT_MASK_H2C_WR_ADDR << BIT_SHIFT_H2C_WR_ADDR) #define BIT_CLEAR_H2C_WR_ADDR(x) ((x) & (~BITS_H2C_WR_ADDR)) #define BIT_GET_H2C_WR_ADDR(x) \ (((x) >> BIT_SHIFT_H2C_WR_ADDR) & BIT_MASK_H2C_WR_ADDR) #define BIT_SET_H2C_WR_ADDR(x, v) \ (BIT_CLEAR_H2C_WR_ADDR(x) | BIT_H2C_WR_ADDR(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_H2C_WR_ADDR (Offset 0x0250) */ #define BIT_SHIFT_H2C_WR_ADDR_V1 0 #define BIT_MASK_H2C_WR_ADDR_V1 0x7ffff #define BIT_H2C_WR_ADDR_V1(x) \ (((x) & BIT_MASK_H2C_WR_ADDR_V1) << BIT_SHIFT_H2C_WR_ADDR_V1) #define BITS_H2C_WR_ADDR_V1 \ (BIT_MASK_H2C_WR_ADDR_V1 << BIT_SHIFT_H2C_WR_ADDR_V1) #define BIT_CLEAR_H2C_WR_ADDR_V1(x) ((x) & (~BITS_H2C_WR_ADDR_V1)) #define BIT_GET_H2C_WR_ADDR_V1(x) \ (((x) >> BIT_SHIFT_H2C_WR_ADDR_V1) & BIT_MASK_H2C_WR_ADDR_V1) #define BIT_SET_H2C_WR_ADDR_V1(x, v) \ (BIT_CLEAR_H2C_WR_ADDR_V1(x) | BIT_H2C_WR_ADDR_V1(v)) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_H2C_INFO (Offset 0x0254) */ #define BIT_SHIFT_VI_PUB_LIMIT 16 #define BIT_MASK_VI_PUB_LIMIT 0xfff #define BIT_VI_PUB_LIMIT(x) \ (((x) & BIT_MASK_VI_PUB_LIMIT) << BIT_SHIFT_VI_PUB_LIMIT) #define BITS_VI_PUB_LIMIT (BIT_MASK_VI_PUB_LIMIT << BIT_SHIFT_VI_PUB_LIMIT) #define BIT_CLEAR_VI_PUB_LIMIT(x) ((x) & (~BITS_VI_PUB_LIMIT)) #define BIT_GET_VI_PUB_LIMIT(x) \ (((x) >> BIT_SHIFT_VI_PUB_LIMIT) & BIT_MASK_VI_PUB_LIMIT) #define BIT_SET_VI_PUB_LIMIT(x, v) \ (BIT_CLEAR_VI_PUB_LIMIT(x) | BIT_VI_PUB_LIMIT(v)) #define BIT_SHIFT_BK_PUB_LIMIT 16 #define BIT_MASK_BK_PUB_LIMIT 0xfff #define BIT_BK_PUB_LIMIT(x) \ (((x) & BIT_MASK_BK_PUB_LIMIT) << BIT_SHIFT_BK_PUB_LIMIT) #define BITS_BK_PUB_LIMIT (BIT_MASK_BK_PUB_LIMIT << BIT_SHIFT_BK_PUB_LIMIT) #define BIT_CLEAR_BK_PUB_LIMIT(x) ((x) & (~BITS_BK_PUB_LIMIT)) #define BIT_GET_BK_PUB_LIMIT(x) \ (((x) >> BIT_SHIFT_BK_PUB_LIMIT) & BIT_MASK_BK_PUB_LIMIT) #define BIT_SET_BK_PUB_LIMIT(x, v) \ (BIT_CLEAR_BK_PUB_LIMIT(x) | BIT_BK_PUB_LIMIT(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_H2C_INFO (Offset 0x0254) */ #define BIT_EX2Q_EN_PUBLIC_LIMIT BIT(13) #define BIT_EX1Q_EN_PUBLIC_LIMIT BIT(12) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_H2C_INFO (Offset 0x0254) */ #define BIT_EXQ_EN_PUBLIC_LIMIT BIT(11) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_H2C_INFO (Offset 0x0254) */ #define BIT_EQ_EN_PUBLIC_LIMIT BIT(11) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_H2C_INFO (Offset 0x0254) */ #define BIT_NPQ_EN_PUBLIC_LIMIT BIT(10) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_H2C_INFO (Offset 0x0254) */ #define BIT_NQ_EN_PUBLIC_LIMIT BIT(10) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_H2C_INFO (Offset 0x0254) */ #define BIT_LPQ_EN_PUBLIC_LIMIT BIT(9) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_H2C_INFO (Offset 0x0254) */ #define BIT_LQ_EN_PUBLIC_LIMIT BIT(9) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_H2C_INFO (Offset 0x0254) */ #define BIT_HPQ_EN_PUBLIC_LIMIT BIT(8) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_H2C_INFO (Offset 0x0254) */ #define BIT_HQ_EN_PUBLIC_LIMIT BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_H2C_INFO (Offset 0x0254) */ #define BIT_H2C_SPACE_VLD BIT(3) #define BIT_H2C_WR_ADDR_RST BIT(2) #define BIT_SHIFT_H2C_LEN_SEL 0 #define BIT_MASK_H2C_LEN_SEL 0x3 #define BIT_H2C_LEN_SEL(x) \ (((x) & BIT_MASK_H2C_LEN_SEL) << BIT_SHIFT_H2C_LEN_SEL) #define BITS_H2C_LEN_SEL (BIT_MASK_H2C_LEN_SEL << BIT_SHIFT_H2C_LEN_SEL) #define BIT_CLEAR_H2C_LEN_SEL(x) ((x) & (~BITS_H2C_LEN_SEL)) #define BIT_GET_H2C_LEN_SEL(x) \ (((x) >> BIT_SHIFT_H2C_LEN_SEL) & BIT_MASK_H2C_LEN_SEL) #define BIT_SET_H2C_LEN_SEL(x, v) \ (BIT_CLEAR_H2C_LEN_SEL(x) | BIT_H2C_LEN_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_H2C_INFO (Offset 0x0254) */ #define BIT_SHIFT_VO_PUB_LIMIT 0 #define BIT_MASK_VO_PUB_LIMIT 0xfff #define BIT_VO_PUB_LIMIT(x) \ (((x) & BIT_MASK_VO_PUB_LIMIT) << BIT_SHIFT_VO_PUB_LIMIT) #define BITS_VO_PUB_LIMIT (BIT_MASK_VO_PUB_LIMIT << BIT_SHIFT_VO_PUB_LIMIT) #define BIT_CLEAR_VO_PUB_LIMIT(x) ((x) & (~BITS_VO_PUB_LIMIT)) #define BIT_GET_VO_PUB_LIMIT(x) \ (((x) >> BIT_SHIFT_VO_PUB_LIMIT) & BIT_MASK_VO_PUB_LIMIT) #define BIT_SET_VO_PUB_LIMIT(x, v) \ (BIT_CLEAR_VO_PUB_LIMIT(x) | BIT_VO_PUB_LIMIT(v)) #define BIT_SHIFT_BE_PUB_LIMIT 0 #define BIT_MASK_BE_PUB_LIMIT 0xfff #define BIT_BE_PUB_LIMIT(x) \ (((x) & BIT_MASK_BE_PUB_LIMIT) << BIT_SHIFT_BE_PUB_LIMIT) #define BITS_BE_PUB_LIMIT (BIT_MASK_BE_PUB_LIMIT << BIT_SHIFT_BE_PUB_LIMIT) #define BIT_CLEAR_BE_PUB_LIMIT(x) ((x) & (~BITS_BE_PUB_LIMIT)) #define BIT_GET_BE_PUB_LIMIT(x) \ (((x) >> BIT_SHIFT_BE_PUB_LIMIT) & BIT_MASK_BE_PUB_LIMIT) #define BIT_SET_BE_PUB_LIMIT(x, v) \ (BIT_CLEAR_BE_PUB_LIMIT(x) | BIT_BE_PUB_LIMIT(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DMA_OQT_0 (Offset 0x0260) */ #define BIT_SHIFT_TX_OQT_12_FREE_SPACE 24 #define BIT_MASK_TX_OQT_12_FREE_SPACE 0xff #define BIT_TX_OQT_12_FREE_SPACE(x) \ (((x) & BIT_MASK_TX_OQT_12_FREE_SPACE) \ << BIT_SHIFT_TX_OQT_12_FREE_SPACE) #define BITS_TX_OQT_12_FREE_SPACE \ (BIT_MASK_TX_OQT_12_FREE_SPACE << BIT_SHIFT_TX_OQT_12_FREE_SPACE) #define BIT_CLEAR_TX_OQT_12_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_12_FREE_SPACE)) #define BIT_GET_TX_OQT_12_FREE_SPACE(x) \ (((x) >> BIT_SHIFT_TX_OQT_12_FREE_SPACE) & \ BIT_MASK_TX_OQT_12_FREE_SPACE) #define BIT_SET_TX_OQT_12_FREE_SPACE(x, v) \ (BIT_CLEAR_TX_OQT_12_FREE_SPACE(x) | BIT_TX_OQT_12_FREE_SPACE(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_TQPNT5 (Offset 0x0260) */ #define BIT_SHIFT_EX1Q_HIGH_TH_V1 16 #define BIT_MASK_EX1Q_HIGH_TH_V1 0xfff #define BIT_EX1Q_HIGH_TH_V1(x) \ (((x) & BIT_MASK_EX1Q_HIGH_TH_V1) << BIT_SHIFT_EX1Q_HIGH_TH_V1) #define BITS_EX1Q_HIGH_TH_V1 \ (BIT_MASK_EX1Q_HIGH_TH_V1 << BIT_SHIFT_EX1Q_HIGH_TH_V1) #define BIT_CLEAR_EX1Q_HIGH_TH_V1(x) ((x) & (~BITS_EX1Q_HIGH_TH_V1)) #define BIT_GET_EX1Q_HIGH_TH_V1(x) \ (((x) >> BIT_SHIFT_EX1Q_HIGH_TH_V1) & BIT_MASK_EX1Q_HIGH_TH_V1) #define BIT_SET_EX1Q_HIGH_TH_V1(x, v) \ (BIT_CLEAR_EX1Q_HIGH_TH_V1(x) | BIT_EX1Q_HIGH_TH_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DMA_OQT_0 (Offset 0x0260) */ #define BIT_SHIFT_TX_OQT_8_11_FREE_SPACE 16 #define BIT_MASK_TX_OQT_8_11_FREE_SPACE 0xff #define BIT_TX_OQT_8_11_FREE_SPACE(x) \ (((x) & BIT_MASK_TX_OQT_8_11_FREE_SPACE) \ << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE) #define BITS_TX_OQT_8_11_FREE_SPACE \ (BIT_MASK_TX_OQT_8_11_FREE_SPACE << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE) #define BIT_CLEAR_TX_OQT_8_11_FREE_SPACE(x) \ ((x) & (~BITS_TX_OQT_8_11_FREE_SPACE)) #define BIT_GET_TX_OQT_8_11_FREE_SPACE(x) \ (((x) >> BIT_SHIFT_TX_OQT_8_11_FREE_SPACE) & \ BIT_MASK_TX_OQT_8_11_FREE_SPACE) #define BIT_SET_TX_OQT_8_11_FREE_SPACE(x, v) \ (BIT_CLEAR_TX_OQT_8_11_FREE_SPACE(x) | BIT_TX_OQT_8_11_FREE_SPACE(v)) #define BIT_SHIFT_TX_OQT_16_FREE_SPACE 16 #define BIT_MASK_TX_OQT_16_FREE_SPACE 0xff #define BIT_TX_OQT_16_FREE_SPACE(x) \ (((x) & BIT_MASK_TX_OQT_16_FREE_SPACE) \ << BIT_SHIFT_TX_OQT_16_FREE_SPACE) #define BITS_TX_OQT_16_FREE_SPACE \ (BIT_MASK_TX_OQT_16_FREE_SPACE << BIT_SHIFT_TX_OQT_16_FREE_SPACE) #define BIT_CLEAR_TX_OQT_16_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_16_FREE_SPACE)) #define BIT_GET_TX_OQT_16_FREE_SPACE(x) \ (((x) >> BIT_SHIFT_TX_OQT_16_FREE_SPACE) & \ BIT_MASK_TX_OQT_16_FREE_SPACE) #define BIT_SET_TX_OQT_16_FREE_SPACE(x, v) \ (BIT_CLEAR_TX_OQT_16_FREE_SPACE(x) | BIT_TX_OQT_16_FREE_SPACE(v)) #define BIT_SHIFT_TX_OQT_4_7_FREE_SPACE 8 #define BIT_MASK_TX_OQT_4_7_FREE_SPACE 0xff #define BIT_TX_OQT_4_7_FREE_SPACE(x) \ (((x) & BIT_MASK_TX_OQT_4_7_FREE_SPACE) \ << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE) #define BITS_TX_OQT_4_7_FREE_SPACE \ (BIT_MASK_TX_OQT_4_7_FREE_SPACE << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE) #define BIT_CLEAR_TX_OQT_4_7_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_4_7_FREE_SPACE)) #define BIT_GET_TX_OQT_4_7_FREE_SPACE(x) \ (((x) >> BIT_SHIFT_TX_OQT_4_7_FREE_SPACE) & \ BIT_MASK_TX_OQT_4_7_FREE_SPACE) #define BIT_SET_TX_OQT_4_7_FREE_SPACE(x, v) \ (BIT_CLEAR_TX_OQT_4_7_FREE_SPACE(x) | BIT_TX_OQT_4_7_FREE_SPACE(v)) #define BIT_SHIFT_TX_OQT_14_15_FREE_SPACE 8 #define BIT_MASK_TX_OQT_14_15_FREE_SPACE 0xff #define BIT_TX_OQT_14_15_FREE_SPACE(x) \ (((x) & BIT_MASK_TX_OQT_14_15_FREE_SPACE) \ << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE) #define BITS_TX_OQT_14_15_FREE_SPACE \ (BIT_MASK_TX_OQT_14_15_FREE_SPACE << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE) #define BIT_CLEAR_TX_OQT_14_15_FREE_SPACE(x) \ ((x) & (~BITS_TX_OQT_14_15_FREE_SPACE)) #define BIT_GET_TX_OQT_14_15_FREE_SPACE(x) \ (((x) >> BIT_SHIFT_TX_OQT_14_15_FREE_SPACE) & \ BIT_MASK_TX_OQT_14_15_FREE_SPACE) #define BIT_SET_TX_OQT_14_15_FREE_SPACE(x, v) \ (BIT_CLEAR_TX_OQT_14_15_FREE_SPACE(x) | BIT_TX_OQT_14_15_FREE_SPACE(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_TQPNT5 (Offset 0x0260) */ #define BIT_SHIFT_EX1Q_LOW_TH_V1 0 #define BIT_MASK_EX1Q_LOW_TH_V1 0xfff #define BIT_EX1Q_LOW_TH_V1(x) \ (((x) & BIT_MASK_EX1Q_LOW_TH_V1) << BIT_SHIFT_EX1Q_LOW_TH_V1) #define BITS_EX1Q_LOW_TH_V1 \ (BIT_MASK_EX1Q_LOW_TH_V1 << BIT_SHIFT_EX1Q_LOW_TH_V1) #define BIT_CLEAR_EX1Q_LOW_TH_V1(x) ((x) & (~BITS_EX1Q_LOW_TH_V1)) #define BIT_GET_EX1Q_LOW_TH_V1(x) \ (((x) >> BIT_SHIFT_EX1Q_LOW_TH_V1) & BIT_MASK_EX1Q_LOW_TH_V1) #define BIT_SET_EX1Q_LOW_TH_V1(x, v) \ (BIT_CLEAR_EX1Q_LOW_TH_V1(x) | BIT_EX1Q_LOW_TH_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DMA_OQT_0 (Offset 0x0260) */ #define BIT_SHIFT_TX_OQT_0_3_FREE_SPACE 0 #define BIT_MASK_TX_OQT_0_3_FREE_SPACE 0xff #define BIT_TX_OQT_0_3_FREE_SPACE(x) \ (((x) & BIT_MASK_TX_OQT_0_3_FREE_SPACE) \ << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE) #define BITS_TX_OQT_0_3_FREE_SPACE \ (BIT_MASK_TX_OQT_0_3_FREE_SPACE << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE) #define BIT_CLEAR_TX_OQT_0_3_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_0_3_FREE_SPACE)) #define BIT_GET_TX_OQT_0_3_FREE_SPACE(x) \ (((x) >> BIT_SHIFT_TX_OQT_0_3_FREE_SPACE) & \ BIT_MASK_TX_OQT_0_3_FREE_SPACE) #define BIT_SET_TX_OQT_0_3_FREE_SPACE(x, v) \ (BIT_CLEAR_TX_OQT_0_3_FREE_SPACE(x) | BIT_TX_OQT_0_3_FREE_SPACE(v)) #define BIT_SHIFT_TX_OQT_13_FREE_SPACE 0 #define BIT_MASK_TX_OQT_13_FREE_SPACE 0xff #define BIT_TX_OQT_13_FREE_SPACE(x) \ (((x) & BIT_MASK_TX_OQT_13_FREE_SPACE) \ << BIT_SHIFT_TX_OQT_13_FREE_SPACE) #define BITS_TX_OQT_13_FREE_SPACE \ (BIT_MASK_TX_OQT_13_FREE_SPACE << BIT_SHIFT_TX_OQT_13_FREE_SPACE) #define BIT_CLEAR_TX_OQT_13_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_13_FREE_SPACE)) #define BIT_GET_TX_OQT_13_FREE_SPACE(x) \ (((x) >> BIT_SHIFT_TX_OQT_13_FREE_SPACE) & \ BIT_MASK_TX_OQT_13_FREE_SPACE) #define BIT_SET_TX_OQT_13_FREE_SPACE(x, v) \ (BIT_CLEAR_TX_OQT_13_FREE_SPACE(x) | BIT_TX_OQT_13_FREE_SPACE(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_TQPNT6 (Offset 0x0264) */ #define BIT_SHIFT_EX2Q_HIGH_TH_V1 16 #define BIT_MASK_EX2Q_HIGH_TH_V1 0xfff #define BIT_EX2Q_HIGH_TH_V1(x) \ (((x) & BIT_MASK_EX2Q_HIGH_TH_V1) << BIT_SHIFT_EX2Q_HIGH_TH_V1) #define BITS_EX2Q_HIGH_TH_V1 \ (BIT_MASK_EX2Q_HIGH_TH_V1 << BIT_SHIFT_EX2Q_HIGH_TH_V1) #define BIT_CLEAR_EX2Q_HIGH_TH_V1(x) ((x) & (~BITS_EX2Q_HIGH_TH_V1)) #define BIT_GET_EX2Q_HIGH_TH_V1(x) \ (((x) >> BIT_SHIFT_EX2Q_HIGH_TH_V1) & BIT_MASK_EX2Q_HIGH_TH_V1) #define BIT_SET_EX2Q_HIGH_TH_V1(x, v) \ (BIT_CLEAR_EX2Q_HIGH_TH_V1(x) | BIT_EX2Q_HIGH_TH_V1(v)) #define BIT_SHIFT_EX2Q_LOW_TH_V1 0 #define BIT_MASK_EX2Q_LOW_TH_V1 0xfff #define BIT_EX2Q_LOW_TH_V1(x) \ (((x) & BIT_MASK_EX2Q_LOW_TH_V1) << BIT_SHIFT_EX2Q_LOW_TH_V1) #define BITS_EX2Q_LOW_TH_V1 \ (BIT_MASK_EX2Q_LOW_TH_V1 << BIT_SHIFT_EX2Q_LOW_TH_V1) #define BIT_CLEAR_EX2Q_LOW_TH_V1(x) ((x) & (~BITS_EX2Q_LOW_TH_V1)) #define BIT_GET_EX2Q_LOW_TH_V1(x) \ (((x) >> BIT_SHIFT_EX2Q_LOW_TH_V1) & BIT_MASK_EX2Q_LOW_TH_V1) #define BIT_SET_EX2Q_LOW_TH_V1(x, v) \ (BIT_CLEAR_EX2Q_LOW_TH_V1(x) | BIT_EX2Q_LOW_TH_V1(v)) /* 2 REG_FIFOPAGE_INFO_6 (Offset 0x0268) */ #define BIT_SHIFT_EX1Q_AVAL_PG_V1 16 #define BIT_MASK_EX1Q_AVAL_PG_V1 0xfff #define BIT_EX1Q_AVAL_PG_V1(x) \ (((x) & BIT_MASK_EX1Q_AVAL_PG_V1) << BIT_SHIFT_EX1Q_AVAL_PG_V1) #define BITS_EX1Q_AVAL_PG_V1 \ (BIT_MASK_EX1Q_AVAL_PG_V1 << BIT_SHIFT_EX1Q_AVAL_PG_V1) #define BIT_CLEAR_EX1Q_AVAL_PG_V1(x) ((x) & (~BITS_EX1Q_AVAL_PG_V1)) #define BIT_GET_EX1Q_AVAL_PG_V1(x) \ (((x) >> BIT_SHIFT_EX1Q_AVAL_PG_V1) & BIT_MASK_EX1Q_AVAL_PG_V1) #define BIT_SET_EX1Q_AVAL_PG_V1(x, v) \ (BIT_CLEAR_EX1Q_AVAL_PG_V1(x) | BIT_EX1Q_AVAL_PG_V1(v)) #define BIT_SHIFT_EX1Q_V1 0 #define BIT_MASK_EX1Q_V1 0xfff #define BIT_EX1Q_V1(x) (((x) & BIT_MASK_EX1Q_V1) << BIT_SHIFT_EX1Q_V1) #define BITS_EX1Q_V1 (BIT_MASK_EX1Q_V1 << BIT_SHIFT_EX1Q_V1) #define BIT_CLEAR_EX1Q_V1(x) ((x) & (~BITS_EX1Q_V1)) #define BIT_GET_EX1Q_V1(x) (((x) >> BIT_SHIFT_EX1Q_V1) & BIT_MASK_EX1Q_V1) #define BIT_SET_EX1Q_V1(x, v) (BIT_CLEAR_EX1Q_V1(x) | BIT_EX1Q_V1(v)) /* 2 REG_FIFOPAGE_INFO_7 (Offset 0x026C) */ #define BIT_SHIFT_EX2Q_AVAL_PG_V1 16 #define BIT_MASK_EX2Q_AVAL_PG_V1 0xfff #define BIT_EX2Q_AVAL_PG_V1(x) \ (((x) & BIT_MASK_EX2Q_AVAL_PG_V1) << BIT_SHIFT_EX2Q_AVAL_PG_V1) #define BITS_EX2Q_AVAL_PG_V1 \ (BIT_MASK_EX2Q_AVAL_PG_V1 << BIT_SHIFT_EX2Q_AVAL_PG_V1) #define BIT_CLEAR_EX2Q_AVAL_PG_V1(x) ((x) & (~BITS_EX2Q_AVAL_PG_V1)) #define BIT_GET_EX2Q_AVAL_PG_V1(x) \ (((x) >> BIT_SHIFT_EX2Q_AVAL_PG_V1) & BIT_MASK_EX2Q_AVAL_PG_V1) #define BIT_SET_EX2Q_AVAL_PG_V1(x, v) \ (BIT_CLEAR_EX2Q_AVAL_PG_V1(x) | BIT_EX2Q_AVAL_PG_V1(v)) #define BIT_SHIFT_EX2Q_V1 0 #define BIT_MASK_EX2Q_V1 0xfff #define BIT_EX2Q_V1(x) (((x) & BIT_MASK_EX2Q_V1) << BIT_SHIFT_EX2Q_V1) #define BITS_EX2Q_V1 (BIT_MASK_EX2Q_V1 << BIT_SHIFT_EX2Q_V1) #define BIT_CLEAR_EX2Q_V1(x) ((x) & (~BITS_EX2Q_V1)) #define BIT_GET_EX2Q_V1(x) (((x) >> BIT_SHIFT_EX2Q_V1) & BIT_MASK_EX2Q_V1) #define BIT_SET_EX2Q_V1(x, v) (BIT_CLEAR_EX2Q_V1(x) | BIT_EX2Q_V1(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_PGSUB_H (Offset 0x0270) */ #define BIT_SHIFT_HPQ_PGSUB_CNT 0 #define BIT_MASK_HPQ_PGSUB_CNT 0xffffffffL #define BIT_HPQ_PGSUB_CNT(x) \ (((x) & BIT_MASK_HPQ_PGSUB_CNT) << BIT_SHIFT_HPQ_PGSUB_CNT) #define BITS_HPQ_PGSUB_CNT (BIT_MASK_HPQ_PGSUB_CNT << BIT_SHIFT_HPQ_PGSUB_CNT) #define BIT_CLEAR_HPQ_PGSUB_CNT(x) ((x) & (~BITS_HPQ_PGSUB_CNT)) #define BIT_GET_HPQ_PGSUB_CNT(x) \ (((x) >> BIT_SHIFT_HPQ_PGSUB_CNT) & BIT_MASK_HPQ_PGSUB_CNT) #define BIT_SET_HPQ_PGSUB_CNT(x, v) \ (BIT_CLEAR_HPQ_PGSUB_CNT(x) | BIT_HPQ_PGSUB_CNT(v)) /* 2 REG_PGSUB_N (Offset 0x0274) */ #define BIT_SHIFT_NPQ_PGSUB_CNT 0 #define BIT_MASK_NPQ_PGSUB_CNT 0xffffffffL #define BIT_NPQ_PGSUB_CNT(x) \ (((x) & BIT_MASK_NPQ_PGSUB_CNT) << BIT_SHIFT_NPQ_PGSUB_CNT) #define BITS_NPQ_PGSUB_CNT (BIT_MASK_NPQ_PGSUB_CNT << BIT_SHIFT_NPQ_PGSUB_CNT) #define BIT_CLEAR_NPQ_PGSUB_CNT(x) ((x) & (~BITS_NPQ_PGSUB_CNT)) #define BIT_GET_NPQ_PGSUB_CNT(x) \ (((x) >> BIT_SHIFT_NPQ_PGSUB_CNT) & BIT_MASK_NPQ_PGSUB_CNT) #define BIT_SET_NPQ_PGSUB_CNT(x, v) \ (BIT_CLEAR_NPQ_PGSUB_CNT(x) | BIT_NPQ_PGSUB_CNT(v)) /* 2 REG_PGSUB_L (Offset 0x0278) */ #define BIT_SHIFT_LPQ_PGSUB_CNT 0 #define BIT_MASK_LPQ_PGSUB_CNT 0xffffffffL #define BIT_LPQ_PGSUB_CNT(x) \ (((x) & BIT_MASK_LPQ_PGSUB_CNT) << BIT_SHIFT_LPQ_PGSUB_CNT) #define BITS_LPQ_PGSUB_CNT (BIT_MASK_LPQ_PGSUB_CNT << BIT_SHIFT_LPQ_PGSUB_CNT) #define BIT_CLEAR_LPQ_PGSUB_CNT(x) ((x) & (~BITS_LPQ_PGSUB_CNT)) #define BIT_GET_LPQ_PGSUB_CNT(x) \ (((x) >> BIT_SHIFT_LPQ_PGSUB_CNT) & BIT_MASK_LPQ_PGSUB_CNT) #define BIT_SET_LPQ_PGSUB_CNT(x, v) \ (BIT_CLEAR_LPQ_PGSUB_CNT(x) | BIT_LPQ_PGSUB_CNT(v)) /* 2 REG_PGSUB_E (Offset 0x027C) */ #define BIT_SHIFT_EPQ_PGSUB_CNT 0 #define BIT_MASK_EPQ_PGSUB_CNT 0xffffffffL #define BIT_EPQ_PGSUB_CNT(x) \ (((x) & BIT_MASK_EPQ_PGSUB_CNT) << BIT_SHIFT_EPQ_PGSUB_CNT) #define BITS_EPQ_PGSUB_CNT (BIT_MASK_EPQ_PGSUB_CNT << BIT_SHIFT_EPQ_PGSUB_CNT) #define BIT_CLEAR_EPQ_PGSUB_CNT(x) ((x) & (~BITS_EPQ_PGSUB_CNT)) #define BIT_GET_EPQ_PGSUB_CNT(x) \ (((x) >> BIT_SHIFT_EPQ_PGSUB_CNT) & BIT_MASK_EPQ_PGSUB_CNT) #define BIT_SET_EPQ_PGSUB_CNT(x, v) \ (BIT_CLEAR_EPQ_PGSUB_CNT(x) | BIT_EPQ_PGSUB_CNT(v)) #define BIT_SHIFT_FWFF_PKT_STR_ADDR_V2 0 #define BIT_MASK_FWFF_PKT_STR_ADDR_V2 0x3fff #define BIT_FWFF_PKT_STR_ADDR_V2(x) \ (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V2) \ << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2) #define BITS_FWFF_PKT_STR_ADDR_V2 \ (BIT_MASK_FWFF_PKT_STR_ADDR_V2 << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2) #define BIT_CLEAR_FWFF_PKT_STR_ADDR_V2(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR_V2)) #define BIT_GET_FWFF_PKT_STR_ADDR_V2(x) \ (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V2) & \ BIT_MASK_FWFF_PKT_STR_ADDR_V2) #define BIT_SET_FWFF_PKT_STR_ADDR_V2(x, v) \ (BIT_CLEAR_FWFF_PKT_STR_ADDR_V2(x) | BIT_FWFF_PKT_STR_ADDR_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ #define BIT_USB_RXDMA_AGG_EN BIT(31) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ #define BIT_DMA_STORE_MODE BIT(31) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ #define BIT_RXDMA_AGG_OLD_MOD_V1 BIT(31) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ #define BIT_DMA_STORE BIT(31) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ #define BIT_EN_FW_ADD BIT(30) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ #define BIT_EN_PRE_CALC BIT(29) #define BIT_RXAGG_SW_EN BIT(28) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ #define BIT_RXAGG_SW_TRIG BIT(27) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ #define BIT_SHIFT_RXDMA_AGG_OLD_MOD 24 #define BIT_MASK_RXDMA_AGG_OLD_MOD 0xff #define BIT_RXDMA_AGG_OLD_MOD(x) \ (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD) << BIT_SHIFT_RXDMA_AGG_OLD_MOD) #define BITS_RXDMA_AGG_OLD_MOD \ (BIT_MASK_RXDMA_AGG_OLD_MOD << BIT_SHIFT_RXDMA_AGG_OLD_MOD) #define BIT_CLEAR_RXDMA_AGG_OLD_MOD(x) ((x) & (~BITS_RXDMA_AGG_OLD_MOD)) #define BIT_GET_RXDMA_AGG_OLD_MOD(x) \ (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD) & BIT_MASK_RXDMA_AGG_OLD_MOD) #define BIT_SET_RXDMA_AGG_OLD_MOD(x, v) \ (BIT_CLEAR_RXDMA_AGG_OLD_MOD(x) | BIT_RXDMA_AGG_OLD_MOD(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ #define BIT_SHIFT_PKT_NUM_WOL 16 #define BIT_MASK_PKT_NUM_WOL 0xff #define BIT_PKT_NUM_WOL(x) \ (((x) & BIT_MASK_PKT_NUM_WOL) << BIT_SHIFT_PKT_NUM_WOL) #define BITS_PKT_NUM_WOL (BIT_MASK_PKT_NUM_WOL << BIT_SHIFT_PKT_NUM_WOL) #define BIT_CLEAR_PKT_NUM_WOL(x) ((x) & (~BITS_PKT_NUM_WOL)) #define BIT_GET_PKT_NUM_WOL(x) \ (((x) >> BIT_SHIFT_PKT_NUM_WOL) & BIT_MASK_PKT_NUM_WOL) #define BIT_SET_PKT_NUM_WOL(x, v) \ (BIT_CLEAR_PKT_NUM_WOL(x) | BIT_PKT_NUM_WOL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ #define BIT_SHIFT_DMA_AGG_TO_V1 8 #define BIT_MASK_DMA_AGG_TO_V1 0xff #define BIT_DMA_AGG_TO_V1(x) \ (((x) & BIT_MASK_DMA_AGG_TO_V1) << BIT_SHIFT_DMA_AGG_TO_V1) #define BITS_DMA_AGG_TO_V1 (BIT_MASK_DMA_AGG_TO_V1 << BIT_SHIFT_DMA_AGG_TO_V1) #define BIT_CLEAR_DMA_AGG_TO_V1(x) ((x) & (~BITS_DMA_AGG_TO_V1)) #define BIT_GET_DMA_AGG_TO_V1(x) \ (((x) >> BIT_SHIFT_DMA_AGG_TO_V1) & BIT_MASK_DMA_AGG_TO_V1) #define BIT_SET_DMA_AGG_TO_V1(x, v) \ (BIT_CLEAR_DMA_AGG_TO_V1(x) | BIT_DMA_AGG_TO_V1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ #define BIT_SHIFT_DMA_AGG_TO 8 #define BIT_MASK_DMA_AGG_TO 0xf #define BIT_DMA_AGG_TO(x) (((x) & BIT_MASK_DMA_AGG_TO) << BIT_SHIFT_DMA_AGG_TO) #define BITS_DMA_AGG_TO (BIT_MASK_DMA_AGG_TO << BIT_SHIFT_DMA_AGG_TO) #define BIT_CLEAR_DMA_AGG_TO(x) ((x) & (~BITS_DMA_AGG_TO)) #define BIT_GET_DMA_AGG_TO(x) \ (((x) >> BIT_SHIFT_DMA_AGG_TO) & BIT_MASK_DMA_AGG_TO) #define BIT_SET_DMA_AGG_TO(x, v) (BIT_CLEAR_DMA_AGG_TO(x) | BIT_DMA_AGG_TO(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ #define BIT_SHIFT_RXDMA_AGG_PG_TH_V1 0 #define BIT_MASK_RXDMA_AGG_PG_TH_V1 0xf #define BIT_RXDMA_AGG_PG_TH_V1(x) \ (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1) #define BITS_RXDMA_AGG_PG_TH_V1 \ (BIT_MASK_RXDMA_AGG_PG_TH_V1 << BIT_SHIFT_RXDMA_AGG_PG_TH_V1) #define BIT_CLEAR_RXDMA_AGG_PG_TH_V1(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_V1)) #define BIT_GET_RXDMA_AGG_PG_TH_V1(x) \ (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1) & BIT_MASK_RXDMA_AGG_PG_TH_V1) #define BIT_SET_RXDMA_AGG_PG_TH_V1(x, v) \ (BIT_CLEAR_RXDMA_AGG_PG_TH_V1(x) | BIT_RXDMA_AGG_PG_TH_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ #define BIT_SHIFT_RXDMA_AGG_PG_TH 0 #define BIT_MASK_RXDMA_AGG_PG_TH 0xff #define BIT_RXDMA_AGG_PG_TH(x) \ (((x) & BIT_MASK_RXDMA_AGG_PG_TH) << BIT_SHIFT_RXDMA_AGG_PG_TH) #define BITS_RXDMA_AGG_PG_TH \ (BIT_MASK_RXDMA_AGG_PG_TH << BIT_SHIFT_RXDMA_AGG_PG_TH) #define BIT_CLEAR_RXDMA_AGG_PG_TH(x) ((x) & (~BITS_RXDMA_AGG_PG_TH)) #define BIT_GET_RXDMA_AGG_PG_TH(x) \ (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH) & BIT_MASK_RXDMA_AGG_PG_TH) #define BIT_SET_RXDMA_AGG_PG_TH(x, v) \ (BIT_CLEAR_RXDMA_AGG_PG_TH(x) | BIT_RXDMA_AGG_PG_TH(v)) #endif #if (HALMAC_8814AMP_SUPPORT) /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ #define BIT_SHIFT_RXDMA_AGG_PG_TH_V2 0 #define BIT_MASK_RXDMA_AGG_PG_TH_V2 0xff #define BIT_RXDMA_AGG_PG_TH_V2(x) \ (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V2) << BIT_SHIFT_RXDMA_AGG_PG_TH_V2) #define BITS_RXDMA_AGG_PG_TH_V2 \ (BIT_MASK_RXDMA_AGG_PG_TH_V2 << BIT_SHIFT_RXDMA_AGG_PG_TH_V2) #define BIT_CLEAR_RXDMA_AGG_PG_TH_V2(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_V2)) #define BIT_GET_RXDMA_AGG_PG_TH_V2(x) \ (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V2) & BIT_MASK_RXDMA_AGG_PG_TH_V2) #define BIT_SET_RXDMA_AGG_PG_TH_V2(x, v) \ (BIT_CLEAR_RXDMA_AGG_PG_TH_V2(x) | BIT_RXDMA_AGG_PG_TH_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXPKT_NUM (Offset 0x0284) */ #define BIT_SHIFT_RXPKT_NUM 24 #define BIT_MASK_RXPKT_NUM 0xff #define BIT_RXPKT_NUM(x) (((x) & BIT_MASK_RXPKT_NUM) << BIT_SHIFT_RXPKT_NUM) #define BITS_RXPKT_NUM (BIT_MASK_RXPKT_NUM << BIT_SHIFT_RXPKT_NUM) #define BIT_CLEAR_RXPKT_NUM(x) ((x) & (~BITS_RXPKT_NUM)) #define BIT_GET_RXPKT_NUM(x) (((x) >> BIT_SHIFT_RXPKT_NUM) & BIT_MASK_RXPKT_NUM) #define BIT_SET_RXPKT_NUM(x, v) (BIT_CLEAR_RXPKT_NUM(x) | BIT_RXPKT_NUM(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_RXPKT_NUM (Offset 0x0284) */ #define BIT_SHIFT_FW_UPD_RDPTR19_TO_16 20 #define BIT_MASK_FW_UPD_RDPTR19_TO_16 0xf #define BIT_FW_UPD_RDPTR19_TO_16(x) \ (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16) \ << BIT_SHIFT_FW_UPD_RDPTR19_TO_16) #define BITS_FW_UPD_RDPTR19_TO_16 \ (BIT_MASK_FW_UPD_RDPTR19_TO_16 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16) #define BIT_CLEAR_FW_UPD_RDPTR19_TO_16(x) ((x) & (~BITS_FW_UPD_RDPTR19_TO_16)) #define BIT_GET_FW_UPD_RDPTR19_TO_16(x) \ (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16) & \ BIT_MASK_FW_UPD_RDPTR19_TO_16) #define BIT_SET_FW_UPD_RDPTR19_TO_16(x, v) \ (BIT_CLEAR_FW_UPD_RDPTR19_TO_16(x) | BIT_FW_UPD_RDPTR19_TO_16(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RXPKT_NUM (Offset 0x0284) */ #define BIT_RXDMA_REQ BIT(19) #define BIT_RW_RELEASE_EN BIT(18) #define BIT_RXDMA_IDLE BIT(17) #define BIT_RXPKT_RELEASE_POLL BIT(16) #define BIT_SHIFT_FW_UPD_RDPTR 0 #define BIT_MASK_FW_UPD_RDPTR 0xffff #define BIT_FW_UPD_RDPTR(x) \ (((x) & BIT_MASK_FW_UPD_RDPTR) << BIT_SHIFT_FW_UPD_RDPTR) #define BITS_FW_UPD_RDPTR (BIT_MASK_FW_UPD_RDPTR << BIT_SHIFT_FW_UPD_RDPTR) #define BIT_CLEAR_FW_UPD_RDPTR(x) ((x) & (~BITS_FW_UPD_RDPTR)) #define BIT_GET_FW_UPD_RDPTR(x) \ (((x) >> BIT_SHIFT_FW_UPD_RDPTR) & BIT_MASK_FW_UPD_RDPTR) #define BIT_SET_FW_UPD_RDPTR(x, v) \ (BIT_CLEAR_FW_UPD_RDPTR(x) | BIT_FW_UPD_RDPTR(v)) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_RXDMA_STATUS (Offset 0x0288) */ #define BIT_FC2H_PKT_OVERFLOW BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RXDMA_STATUS (Offset 0x0288) */ #define BIT_C2H_PKT_OVF BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXDMA_STATUS (Offset 0x0288) */ #define BIT_AGG_CFG_ISSUE BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXDMA_STATUS (Offset 0x0288) */ #define BIT_AGG_CONFGI_ISSUE BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RXDMA_STATUS (Offset 0x0288) */ #define BIT_FW_POLL_ISSUE BIT(5) #define BIT_RX_DATA_UDN BIT(4) #define BIT_RX_SFF_UDN BIT(3) #define BIT_RX_SFF_OVF BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXDMA_STATUS (Offset 0x0288) */ #define BIT_USB_REQ_LEN_OVF BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RXDMA_STATUS (Offset 0x0288) */ #define BIT_RXPKT_OVF BIT(0) /* 2 REG_RXDMA_DPR (Offset 0x028C) */ #define BIT_SHIFT_RDE_DEBUG 0 #define BIT_MASK_RDE_DEBUG 0xffffffffL #define BIT_RDE_DEBUG(x) (((x) & BIT_MASK_RDE_DEBUG) << BIT_SHIFT_RDE_DEBUG) #define BITS_RDE_DEBUG (BIT_MASK_RDE_DEBUG << BIT_SHIFT_RDE_DEBUG) #define BIT_CLEAR_RDE_DEBUG(x) ((x) & (~BITS_RDE_DEBUG)) #define BIT_GET_RDE_DEBUG(x) (((x) >> BIT_SHIFT_RDE_DEBUG) & BIT_MASK_RDE_DEBUG) #define BIT_SET_RDE_DEBUG(x, v) (BIT_CLEAR_RDE_DEBUG(x) | BIT_RDE_DEBUG(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_RXDMA_MODE (Offset 0x0290) */ #define BIT_SHIFT_PKTNUM_TH_V2 24 #define BIT_MASK_PKTNUM_TH_V2 0x1f #define BIT_PKTNUM_TH_V2(x) \ (((x) & BIT_MASK_PKTNUM_TH_V2) << BIT_SHIFT_PKTNUM_TH_V2) #define BITS_PKTNUM_TH_V2 (BIT_MASK_PKTNUM_TH_V2 << BIT_SHIFT_PKTNUM_TH_V2) #define BIT_CLEAR_PKTNUM_TH_V2(x) ((x) & (~BITS_PKTNUM_TH_V2)) #define BIT_GET_PKTNUM_TH_V2(x) \ (((x) >> BIT_SHIFT_PKTNUM_TH_V2) & BIT_MASK_PKTNUM_TH_V2) #define BIT_SET_PKTNUM_TH_V2(x, v) \ (BIT_CLEAR_PKTNUM_TH_V2(x) | BIT_PKTNUM_TH_V2(v)) #define BIT_TXBA_BREAK_USBAGG BIT(23) #define BIT_SHIFT_PKTLEN_PARA 16 #define BIT_MASK_PKTLEN_PARA 0x7 #define BIT_PKTLEN_PARA(x) \ (((x) & BIT_MASK_PKTLEN_PARA) << BIT_SHIFT_PKTLEN_PARA) #define BITS_PKTLEN_PARA (BIT_MASK_PKTLEN_PARA << BIT_SHIFT_PKTLEN_PARA) #define BIT_CLEAR_PKTLEN_PARA(x) ((x) & (~BITS_PKTLEN_PARA)) #define BIT_GET_PKTLEN_PARA(x) \ (((x) >> BIT_SHIFT_PKTLEN_PARA) & BIT_MASK_PKTLEN_PARA) #define BIT_SET_PKTLEN_PARA(x, v) \ (BIT_CLEAR_PKTLEN_PARA(x) | BIT_PKTLEN_PARA(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_RXDMA_MODE (Offset 0x0290) */ #define BIT_EN_SDIO_FAIL BIT(9) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_RXDMA_MODE (Offset 0x0290) */ #define BIT_GRAYCODE_SYNC_WITH_BIN BIT(8) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_RXDMA_MODE (Offset 0x0290) */ #define BIT_RXDMA_DBD_SEL BIT(7) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXDMA_MODE (Offset 0x0290) */ #define BIT_RX_DBG_SEL BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXDMA_MODE (Offset 0x0290) */ #define BIT_EN_SPD BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RXDMA_MODE (Offset 0x0290) */ #define BIT_SHIFT_BURST_SIZE 4 #define BIT_MASK_BURST_SIZE 0x3 #define BIT_BURST_SIZE(x) (((x) & BIT_MASK_BURST_SIZE) << BIT_SHIFT_BURST_SIZE) #define BITS_BURST_SIZE (BIT_MASK_BURST_SIZE << BIT_SHIFT_BURST_SIZE) #define BIT_CLEAR_BURST_SIZE(x) ((x) & (~BITS_BURST_SIZE)) #define BIT_GET_BURST_SIZE(x) \ (((x) >> BIT_SHIFT_BURST_SIZE) & BIT_MASK_BURST_SIZE) #define BIT_SET_BURST_SIZE(x, v) (BIT_CLEAR_BURST_SIZE(x) | BIT_BURST_SIZE(v)) #define BIT_SHIFT_BURST_CNT 2 #define BIT_MASK_BURST_CNT 0x3 #define BIT_BURST_CNT(x) (((x) & BIT_MASK_BURST_CNT) << BIT_SHIFT_BURST_CNT) #define BITS_BURST_CNT (BIT_MASK_BURST_CNT << BIT_SHIFT_BURST_CNT) #define BIT_CLEAR_BURST_CNT(x) ((x) & (~BITS_BURST_CNT)) #define BIT_GET_BURST_CNT(x) (((x) >> BIT_SHIFT_BURST_CNT) & BIT_MASK_BURST_CNT) #define BIT_SET_BURST_CNT(x, v) (BIT_CLEAR_BURST_CNT(x) | BIT_BURST_CNT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXDMA_MODE (Offset 0x0290) */ #define BIT_DAM_MODE BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXDMA_MODE (Offset 0x0290) */ #define BIT_DMA_MODE BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_C2H_PKT (Offset 0x0294) */ #define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19 24 #define BIT_MASK_R_C2H_STR_ADDR_16_TO_19 0xf #define BIT_R_C2H_STR_ADDR_16_TO_19(x) \ (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19) \ << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) #define BITS_R_C2H_STR_ADDR_16_TO_19 \ (BIT_MASK_R_C2H_STR_ADDR_16_TO_19 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) #define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19(x) \ ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19)) #define BIT_GET_R_C2H_STR_ADDR_16_TO_19(x) \ (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) & \ BIT_MASK_R_C2H_STR_ADDR_16_TO_19) #define BIT_SET_R_C2H_STR_ADDR_16_TO_19(x, v) \ (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19(x) | BIT_R_C2H_STR_ADDR_16_TO_19(v)) #define BIT_SHIFT_MDIO_PHY_ADDR 24 #define BIT_MASK_MDIO_PHY_ADDR 0x1f #define BIT_MDIO_PHY_ADDR(x) \ (((x) & BIT_MASK_MDIO_PHY_ADDR) << BIT_SHIFT_MDIO_PHY_ADDR) #define BITS_MDIO_PHY_ADDR (BIT_MASK_MDIO_PHY_ADDR << BIT_SHIFT_MDIO_PHY_ADDR) #define BIT_CLEAR_MDIO_PHY_ADDR(x) ((x) & (~BITS_MDIO_PHY_ADDR)) #define BIT_GET_MDIO_PHY_ADDR(x) \ (((x) >> BIT_SHIFT_MDIO_PHY_ADDR) & BIT_MASK_MDIO_PHY_ADDR) #define BIT_SET_MDIO_PHY_ADDR(x, v) \ (BIT_CLEAR_MDIO_PHY_ADDR(x) | BIT_MDIO_PHY_ADDR(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_C2H_PKT (Offset 0x0294) */ #define BIT_R_C2H_PKT_REQ BIT(16) #define BIT_SHIFT_R_C2H_STR_ADDR 0 #define BIT_MASK_R_C2H_STR_ADDR 0xffff #define BIT_R_C2H_STR_ADDR(x) \ (((x) & BIT_MASK_R_C2H_STR_ADDR) << BIT_SHIFT_R_C2H_STR_ADDR) #define BITS_R_C2H_STR_ADDR \ (BIT_MASK_R_C2H_STR_ADDR << BIT_SHIFT_R_C2H_STR_ADDR) #define BIT_CLEAR_R_C2H_STR_ADDR(x) ((x) & (~BITS_R_C2H_STR_ADDR)) #define BIT_GET_R_C2H_STR_ADDR(x) \ (((x) >> BIT_SHIFT_R_C2H_STR_ADDR) & BIT_MASK_R_C2H_STR_ADDR) #define BIT_SET_R_C2H_STR_ADDR(x, v) \ (BIT_CLEAR_R_C2H_STR_ADDR(x) | BIT_R_C2H_STR_ADDR(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWFF_C2H (Offset 0x0298) */ #define BIT_SHIFT_C2H_DMA_ADDR 0 #define BIT_MASK_C2H_DMA_ADDR 0x3ffff #define BIT_C2H_DMA_ADDR(x) \ (((x) & BIT_MASK_C2H_DMA_ADDR) << BIT_SHIFT_C2H_DMA_ADDR) #define BITS_C2H_DMA_ADDR (BIT_MASK_C2H_DMA_ADDR << BIT_SHIFT_C2H_DMA_ADDR) #define BIT_CLEAR_C2H_DMA_ADDR(x) ((x) & (~BITS_C2H_DMA_ADDR)) #define BIT_GET_C2H_DMA_ADDR(x) \ (((x) >> BIT_SHIFT_C2H_DMA_ADDR) & BIT_MASK_C2H_DMA_ADDR) #define BIT_SET_C2H_DMA_ADDR(x, v) \ (BIT_CLEAR_C2H_DMA_ADDR(x) | BIT_C2H_DMA_ADDR(v)) /* 2 REG_FWFF_CTRL (Offset 0x029C) */ #define BIT_FWFF_DMAPKT_REQ BIT(31) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FWFF_CTRL (Offset 0x029C) */ #define BIT_SHIFT_FWFF_DMA_PKT_NUM 16 #define BIT_MASK_FWFF_DMA_PKT_NUM 0xff #define BIT_FWFF_DMA_PKT_NUM(x) \ (((x) & BIT_MASK_FWFF_DMA_PKT_NUM) << BIT_SHIFT_FWFF_DMA_PKT_NUM) #define BITS_FWFF_DMA_PKT_NUM \ (BIT_MASK_FWFF_DMA_PKT_NUM << BIT_SHIFT_FWFF_DMA_PKT_NUM) #define BIT_CLEAR_FWFF_DMA_PKT_NUM(x) ((x) & (~BITS_FWFF_DMA_PKT_NUM)) #define BIT_GET_FWFF_DMA_PKT_NUM(x) \ (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM) & BIT_MASK_FWFF_DMA_PKT_NUM) #define BIT_SET_FWFF_DMA_PKT_NUM(x, v) \ (BIT_CLEAR_FWFF_DMA_PKT_NUM(x) | BIT_FWFF_DMA_PKT_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FWFF_CTRL (Offset 0x029C) */ #define BIT_SHIFT_FWFF_DMA_PKT_NUM_V1 16 #define BIT_MASK_FWFF_DMA_PKT_NUM_V1 0x7fff #define BIT_FWFF_DMA_PKT_NUM_V1(x) \ (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_V1) << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1) #define BITS_FWFF_DMA_PKT_NUM_V1 \ (BIT_MASK_FWFF_DMA_PKT_NUM_V1 << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1) #define BIT_CLEAR_FWFF_DMA_PKT_NUM_V1(x) ((x) & (~BITS_FWFF_DMA_PKT_NUM_V1)) #define BIT_GET_FWFF_DMA_PKT_NUM_V1(x) \ (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_V1) & BIT_MASK_FWFF_DMA_PKT_NUM_V1) #define BIT_SET_FWFF_DMA_PKT_NUM_V1(x, v) \ (BIT_CLEAR_FWFF_DMA_PKT_NUM_V1(x) | BIT_FWFF_DMA_PKT_NUM_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWFF_CTRL (Offset 0x029C) */ #define BIT_SHIFT_FWFF_STR_ADDR 0 #define BIT_MASK_FWFF_STR_ADDR 0xffff #define BIT_FWFF_STR_ADDR(x) \ (((x) & BIT_MASK_FWFF_STR_ADDR) << BIT_SHIFT_FWFF_STR_ADDR) #define BITS_FWFF_STR_ADDR (BIT_MASK_FWFF_STR_ADDR << BIT_SHIFT_FWFF_STR_ADDR) #define BIT_CLEAR_FWFF_STR_ADDR(x) ((x) & (~BITS_FWFF_STR_ADDR)) #define BIT_GET_FWFF_STR_ADDR(x) \ (((x) >> BIT_SHIFT_FWFF_STR_ADDR) & BIT_MASK_FWFF_STR_ADDR) #define BIT_SET_FWFF_STR_ADDR(x, v) \ (BIT_CLEAR_FWFF_STR_ADDR(x) | BIT_FWFF_STR_ADDR(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ #define BIT_SHIFT_FWFF_PKT_QUEUED 16 #define BIT_MASK_FWFF_PKT_QUEUED 0xff #define BIT_FWFF_PKT_QUEUED(x) \ (((x) & BIT_MASK_FWFF_PKT_QUEUED) << BIT_SHIFT_FWFF_PKT_QUEUED) #define BITS_FWFF_PKT_QUEUED \ (BIT_MASK_FWFF_PKT_QUEUED << BIT_SHIFT_FWFF_PKT_QUEUED) #define BIT_CLEAR_FWFF_PKT_QUEUED(x) ((x) & (~BITS_FWFF_PKT_QUEUED)) #define BIT_GET_FWFF_PKT_QUEUED(x) \ (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED) & BIT_MASK_FWFF_PKT_QUEUED) #define BIT_SET_FWFF_PKT_QUEUED(x, v) \ (BIT_CLEAR_FWFF_PKT_QUEUED(x) | BIT_FWFF_PKT_QUEUED(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ #define BIT_SHIFT_FWFF_PKT_READ_ADDR 16 #define BIT_MASK_FWFF_PKT_READ_ADDR 0xffff #define BIT_FWFF_PKT_READ_ADDR(x) \ (((x) & BIT_MASK_FWFF_PKT_READ_ADDR) << BIT_SHIFT_FWFF_PKT_READ_ADDR) #define BITS_FWFF_PKT_READ_ADDR \ (BIT_MASK_FWFF_PKT_READ_ADDR << BIT_SHIFT_FWFF_PKT_READ_ADDR) #define BIT_CLEAR_FWFF_PKT_READ_ADDR(x) ((x) & (~BITS_FWFF_PKT_READ_ADDR)) #define BIT_GET_FWFF_PKT_READ_ADDR(x) \ (((x) >> BIT_SHIFT_FWFF_PKT_READ_ADDR) & BIT_MASK_FWFF_PKT_READ_ADDR) #define BIT_SET_FWFF_PKT_READ_ADDR(x, v) \ (BIT_CLEAR_FWFF_PKT_READ_ADDR(x) | BIT_FWFF_PKT_READ_ADDR(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ #define BIT_ECRC_EN_V1 BIT(7) #define BIT_MDIO_RFLAG_V1 BIT(6) #define BIT_MDIO_WFLAG_V1 BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ #define BIT_SHIFT_FWFF_PKT_STR_ADDR 0 #define BIT_MASK_FWFF_PKT_STR_ADDR 0xffff #define BIT_FWFF_PKT_STR_ADDR(x) \ (((x) & BIT_MASK_FWFF_PKT_STR_ADDR) << BIT_SHIFT_FWFF_PKT_STR_ADDR) #define BITS_FWFF_PKT_STR_ADDR \ (BIT_MASK_FWFF_PKT_STR_ADDR << BIT_SHIFT_FWFF_PKT_STR_ADDR) #define BIT_CLEAR_FWFF_PKT_STR_ADDR(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR)) #define BIT_GET_FWFF_PKT_STR_ADDR(x) \ (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR) & BIT_MASK_FWFF_PKT_STR_ADDR) #define BIT_SET_FWFF_PKT_STR_ADDR(x, v) \ (BIT_CLEAR_FWFF_PKT_STR_ADDR(x) | BIT_FWFF_PKT_STR_ADDR(v)) #endif #if (HALMAC_8814AMP_SUPPORT) /* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ #define BIT_SHIFT_FWFF_PKT_STR_ADDR_V1 0 #define BIT_MASK_FWFF_PKT_STR_ADDR_V1 0x7ff #define BIT_FWFF_PKT_STR_ADDR_V1(x) \ (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V1) \ << BIT_SHIFT_FWFF_PKT_STR_ADDR_V1) #define BITS_FWFF_PKT_STR_ADDR_V1 \ (BIT_MASK_FWFF_PKT_STR_ADDR_V1 << BIT_SHIFT_FWFF_PKT_STR_ADDR_V1) #define BIT_CLEAR_FWFF_PKT_STR_ADDR_V1(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR_V1)) #define BIT_GET_FWFF_PKT_STR_ADDR_V1(x) \ (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V1) & \ BIT_MASK_FWFF_PKT_STR_ADDR_V1) #define BIT_SET_FWFF_PKT_STR_ADDR_V1(x, v) \ (BIT_CLEAR_FWFF_PKT_STR_ADDR_V1(x) | BIT_FWFF_PKT_STR_ADDR_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ #define BIT_SHIFT_FWFF_PKT_WRITE_ADDR 0 #define BIT_MASK_FWFF_PKT_WRITE_ADDR 0xffff #define BIT_FWFF_PKT_WRITE_ADDR(x) \ (((x) & BIT_MASK_FWFF_PKT_WRITE_ADDR) << BIT_SHIFT_FWFF_PKT_WRITE_ADDR) #define BITS_FWFF_PKT_WRITE_ADDR \ (BIT_MASK_FWFF_PKT_WRITE_ADDR << BIT_SHIFT_FWFF_PKT_WRITE_ADDR) #define BIT_CLEAR_FWFF_PKT_WRITE_ADDR(x) ((x) & (~BITS_FWFF_PKT_WRITE_ADDR)) #define BIT_GET_FWFF_PKT_WRITE_ADDR(x) \ (((x) >> BIT_SHIFT_FWFF_PKT_WRITE_ADDR) & BIT_MASK_FWFF_PKT_WRITE_ADDR) #define BIT_SET_FWFF_PKT_WRITE_ADDR(x, v) \ (BIT_CLEAR_FWFF_PKT_WRITE_ADDR(x) | BIT_FWFF_PKT_WRITE_ADDR(v)) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_FC2H_INFO (Offset 0x02A4) */ #define BIT_FC2H_PKT_REQ BIT(16) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_FC2H_INFO (Offset 0x02A4) */ #define BIT_FC2H_DMAPKT_REQ BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FC2H_INFO (Offset 0x02A4) */ #define BIT_SHIFT_FC2H_STR_ADDR 0 #define BIT_MASK_FC2H_STR_ADDR 0xffff #define BIT_FC2H_STR_ADDR(x) \ (((x) & BIT_MASK_FC2H_STR_ADDR) << BIT_SHIFT_FC2H_STR_ADDR) #define BITS_FC2H_STR_ADDR (BIT_MASK_FC2H_STR_ADDR << BIT_SHIFT_FC2H_STR_ADDR) #define BIT_CLEAR_FC2H_STR_ADDR(x) ((x) & (~BITS_FC2H_STR_ADDR)) #define BIT_GET_FC2H_STR_ADDR(x) \ (((x) >> BIT_SHIFT_FC2H_STR_ADDR) & BIT_MASK_FC2H_STR_ADDR) #define BIT_SET_FC2H_STR_ADDR(x, v) \ (BIT_CLEAR_FC2H_STR_ADDR(x) | BIT_FC2H_STR_ADDR(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FWFF_PKT_INFO2 (Offset 0x02A4) */ #define BIT_SHIFT_FWFF_PKT_QUEUED_V1 0 #define BIT_MASK_FWFF_PKT_QUEUED_V1 0xffff #define BIT_FWFF_PKT_QUEUED_V1(x) \ (((x) & BIT_MASK_FWFF_PKT_QUEUED_V1) << BIT_SHIFT_FWFF_PKT_QUEUED_V1) #define BITS_FWFF_PKT_QUEUED_V1 \ (BIT_MASK_FWFF_PKT_QUEUED_V1 << BIT_SHIFT_FWFF_PKT_QUEUED_V1) #define BIT_CLEAR_FWFF_PKT_QUEUED_V1(x) ((x) & (~BITS_FWFF_PKT_QUEUED_V1)) #define BIT_GET_FWFF_PKT_QUEUED_V1(x) \ (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_V1) & BIT_MASK_FWFF_PKT_QUEUED_V1) #define BIT_SET_FWFF_PKT_QUEUED_V1(x, v) \ (BIT_CLEAR_FWFF_PKT_QUEUED_V1(x) | BIT_FWFF_PKT_QUEUED_V1(v)) #define BIT_SHIFT_FW_UPD_RXDES_RD_PTR 0 #define BIT_MASK_FW_UPD_RXDES_RD_PTR 0x3ffff #define BIT_FW_UPD_RXDES_RD_PTR(x) \ (((x) & BIT_MASK_FW_UPD_RXDES_RD_PTR) << BIT_SHIFT_FW_UPD_RXDES_RD_PTR) #define BITS_FW_UPD_RXDES_RD_PTR \ (BIT_MASK_FW_UPD_RXDES_RD_PTR << BIT_SHIFT_FW_UPD_RXDES_RD_PTR) #define BIT_CLEAR_FW_UPD_RXDES_RD_PTR(x) ((x) & (~BITS_FW_UPD_RXDES_RD_PTR)) #define BIT_GET_FW_UPD_RXDES_RD_PTR(x) \ (((x) >> BIT_SHIFT_FW_UPD_RXDES_RD_PTR) & BIT_MASK_FW_UPD_RXDES_RD_PTR) #define BIT_SET_FW_UPD_RXDES_RD_PTR(x, v) \ (BIT_CLEAR_FW_UPD_RXDES_RD_PTR(x) | BIT_FW_UPD_RXDES_RD_PTR(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXPKTNUM (Offset 0x02B0) */ #define BIT_SHIFT_PKT_NUM_WOL_V1 16 #define BIT_MASK_PKT_NUM_WOL_V1 0xffff #define BIT_PKT_NUM_WOL_V1(x) \ (((x) & BIT_MASK_PKT_NUM_WOL_V1) << BIT_SHIFT_PKT_NUM_WOL_V1) #define BITS_PKT_NUM_WOL_V1 \ (BIT_MASK_PKT_NUM_WOL_V1 << BIT_SHIFT_PKT_NUM_WOL_V1) #define BIT_CLEAR_PKT_NUM_WOL_V1(x) ((x) & (~BITS_PKT_NUM_WOL_V1)) #define BIT_GET_PKT_NUM_WOL_V1(x) \ (((x) >> BIT_SHIFT_PKT_NUM_WOL_V1) & BIT_MASK_PKT_NUM_WOL_V1) #define BIT_SET_PKT_NUM_WOL_V1(x, v) \ (BIT_CLEAR_PKT_NUM_WOL_V1(x) | BIT_PKT_NUM_WOL_V1(v)) #define BIT_SHIFT_RXPKT_NUM_V1 0 #define BIT_MASK_RXPKT_NUM_V1 0xffff #define BIT_RXPKT_NUM_V1(x) \ (((x) & BIT_MASK_RXPKT_NUM_V1) << BIT_SHIFT_RXPKT_NUM_V1) #define BITS_RXPKT_NUM_V1 (BIT_MASK_RXPKT_NUM_V1 << BIT_SHIFT_RXPKT_NUM_V1) #define BIT_CLEAR_RXPKT_NUM_V1(x) ((x) & (~BITS_RXPKT_NUM_V1)) #define BIT_GET_RXPKT_NUM_V1(x) \ (((x) >> BIT_SHIFT_RXPKT_NUM_V1) & BIT_MASK_RXPKT_NUM_V1) #define BIT_SET_RXPKT_NUM_V1(x, v) \ (BIT_CLEAR_RXPKT_NUM_V1(x) | BIT_RXPKT_NUM_V1(v)) #define BIT_SHIFT_RXPKT_NUM_TH 0 #define BIT_MASK_RXPKT_NUM_TH 0xff #define BIT_RXPKT_NUM_TH(x) \ (((x) & BIT_MASK_RXPKT_NUM_TH) << BIT_SHIFT_RXPKT_NUM_TH) #define BITS_RXPKT_NUM_TH (BIT_MASK_RXPKT_NUM_TH << BIT_SHIFT_RXPKT_NUM_TH) #define BIT_CLEAR_RXPKT_NUM_TH(x) ((x) & (~BITS_RXPKT_NUM_TH)) #define BIT_GET_RXPKT_NUM_TH(x) \ (((x) >> BIT_SHIFT_RXPKT_NUM_TH) & BIT_MASK_RXPKT_NUM_TH) #define BIT_SET_RXPKT_NUM_TH(x, v) \ (BIT_CLEAR_RXPKT_NUM_TH(x) | BIT_RXPKT_NUM_TH(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_FW_MSG1 (Offset 0x02E0) */ #define BIT_SHIFT_FW_MSG_REG1 0 #define BIT_MASK_FW_MSG_REG1 0xffffffffL #define BIT_FW_MSG_REG1(x) \ (((x) & BIT_MASK_FW_MSG_REG1) << BIT_SHIFT_FW_MSG_REG1) #define BITS_FW_MSG_REG1 (BIT_MASK_FW_MSG_REG1 << BIT_SHIFT_FW_MSG_REG1) #define BIT_CLEAR_FW_MSG_REG1(x) ((x) & (~BITS_FW_MSG_REG1)) #define BIT_GET_FW_MSG_REG1(x) \ (((x) >> BIT_SHIFT_FW_MSG_REG1) & BIT_MASK_FW_MSG_REG1) #define BIT_SET_FW_MSG_REG1(x, v) \ (BIT_CLEAR_FW_MSG_REG1(x) | BIT_FW_MSG_REG1(v)) /* 2 REG_FW_MSG2 (Offset 0x02E4) */ #define BIT_SHIFT_FW_MSG_REG2 0 #define BIT_MASK_FW_MSG_REG2 0xffffffffL #define BIT_FW_MSG_REG2(x) \ (((x) & BIT_MASK_FW_MSG_REG2) << BIT_SHIFT_FW_MSG_REG2) #define BITS_FW_MSG_REG2 (BIT_MASK_FW_MSG_REG2 << BIT_SHIFT_FW_MSG_REG2) #define BIT_CLEAR_FW_MSG_REG2(x) ((x) & (~BITS_FW_MSG_REG2)) #define BIT_GET_FW_MSG_REG2(x) \ (((x) >> BIT_SHIFT_FW_MSG_REG2) & BIT_MASK_FW_MSG_REG2) #define BIT_SET_FW_MSG_REG2(x, v) \ (BIT_CLEAR_FW_MSG_REG2(x) | BIT_FW_MSG_REG2(v)) /* 2 REG_FW_MSG3 (Offset 0x02E8) */ #define BIT_SHIFT_FW_MSG_REG3 0 #define BIT_MASK_FW_MSG_REG3 0xffffffffL #define BIT_FW_MSG_REG3(x) \ (((x) & BIT_MASK_FW_MSG_REG3) << BIT_SHIFT_FW_MSG_REG3) #define BITS_FW_MSG_REG3 (BIT_MASK_FW_MSG_REG3 << BIT_SHIFT_FW_MSG_REG3) #define BIT_CLEAR_FW_MSG_REG3(x) ((x) & (~BITS_FW_MSG_REG3)) #define BIT_GET_FW_MSG_REG3(x) \ (((x) >> BIT_SHIFT_FW_MSG_REG3) & BIT_MASK_FW_MSG_REG3) #define BIT_SET_FW_MSG_REG3(x, v) \ (BIT_CLEAR_FW_MSG_REG3(x) | BIT_FW_MSG_REG3(v)) /* 2 REG_FW_MSG4 (Offset 0x02EC) */ #define BIT_SHIFT_FW_MSG_REG4 0 #define BIT_MASK_FW_MSG_REG4 0xffffffffL #define BIT_FW_MSG_REG4(x) \ (((x) & BIT_MASK_FW_MSG_REG4) << BIT_SHIFT_FW_MSG_REG4) #define BITS_FW_MSG_REG4 (BIT_MASK_FW_MSG_REG4 << BIT_SHIFT_FW_MSG_REG4) #define BIT_CLEAR_FW_MSG_REG4(x) ((x) & (~BITS_FW_MSG_REG4)) #define BIT_GET_FW_MSG_REG4(x) \ (((x) >> BIT_SHIFT_FW_MSG_REG4) & BIT_MASK_FW_MSG_REG4) #define BIT_SET_FW_MSG_REG4(x, v) \ (BIT_CLEAR_FW_MSG_REG4(x) | BIT_FW_MSG_REG4(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_PCIE_CTRL (Offset 0x0300) */ #define BIT_PCIEIO_PERSTB_SEL BIT(31) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HCI_CTRL (Offset 0x0300) */ #define BIT_HCIIO_PERSTB_SEL BIT(31) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_PCIE_CTRL (Offset 0x0300) */ #define BIT_SHIFT_PCIE_MAX_RXDMA 28 #define BIT_MASK_PCIE_MAX_RXDMA 0x7 #define BIT_PCIE_MAX_RXDMA(x) \ (((x) & BIT_MASK_PCIE_MAX_RXDMA) << BIT_SHIFT_PCIE_MAX_RXDMA) #define BITS_PCIE_MAX_RXDMA \ (BIT_MASK_PCIE_MAX_RXDMA << BIT_SHIFT_PCIE_MAX_RXDMA) #define BIT_CLEAR_PCIE_MAX_RXDMA(x) ((x) & (~BITS_PCIE_MAX_RXDMA)) #define BIT_GET_PCIE_MAX_RXDMA(x) \ (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA) & BIT_MASK_PCIE_MAX_RXDMA) #define BIT_SET_PCIE_MAX_RXDMA(x, v) \ (BIT_CLEAR_PCIE_MAX_RXDMA(x) | BIT_PCIE_MAX_RXDMA(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HCI_CTRL (Offset 0x0300) */ #define BIT_SHIFT_HCI_MAX_RXDMA 28 #define BIT_MASK_HCI_MAX_RXDMA 0x7 #define BIT_HCI_MAX_RXDMA(x) \ (((x) & BIT_MASK_HCI_MAX_RXDMA) << BIT_SHIFT_HCI_MAX_RXDMA) #define BITS_HCI_MAX_RXDMA (BIT_MASK_HCI_MAX_RXDMA << BIT_SHIFT_HCI_MAX_RXDMA) #define BIT_CLEAR_HCI_MAX_RXDMA(x) ((x) & (~BITS_HCI_MAX_RXDMA)) #define BIT_GET_HCI_MAX_RXDMA(x) \ (((x) >> BIT_SHIFT_HCI_MAX_RXDMA) & BIT_MASK_HCI_MAX_RXDMA) #define BIT_SET_HCI_MAX_RXDMA(x, v) \ (BIT_CLEAR_HCI_MAX_RXDMA(x) | BIT_HCI_MAX_RXDMA(v)) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_LX_CTRL1 (Offset 0x0300) */ #define BIT_RX_LIT_EDN_SEL BIT(27) #define BIT_TX_LIT_EDN_SEL BIT(26) #define BIT_WT_LIT_EDN BIT(25) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_PCIE_CTRL (Offset 0x0300) */ #define BIT_SHIFT_PCIE_MAX_TXDMA 24 #define BIT_MASK_PCIE_MAX_TXDMA 0x7 #define BIT_PCIE_MAX_TXDMA(x) \ (((x) & BIT_MASK_PCIE_MAX_TXDMA) << BIT_SHIFT_PCIE_MAX_TXDMA) #define BITS_PCIE_MAX_TXDMA \ (BIT_MASK_PCIE_MAX_TXDMA << BIT_SHIFT_PCIE_MAX_TXDMA) #define BIT_CLEAR_PCIE_MAX_TXDMA(x) ((x) & (~BITS_PCIE_MAX_TXDMA)) #define BIT_GET_PCIE_MAX_TXDMA(x) \ (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA) & BIT_MASK_PCIE_MAX_TXDMA) #define BIT_SET_PCIE_MAX_TXDMA(x, v) \ (BIT_CLEAR_PCIE_MAX_TXDMA(x) | BIT_PCIE_MAX_TXDMA(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HCI_CTRL (Offset 0x0300) */ #define BIT_SHIFT_HCI_MAX_TXDMA 24 #define BIT_MASK_HCI_MAX_TXDMA 0x7 #define BIT_HCI_MAX_TXDMA(x) \ (((x) & BIT_MASK_HCI_MAX_TXDMA) << BIT_SHIFT_HCI_MAX_TXDMA) #define BITS_HCI_MAX_TXDMA (BIT_MASK_HCI_MAX_TXDMA << BIT_SHIFT_HCI_MAX_TXDMA) #define BIT_CLEAR_HCI_MAX_TXDMA(x) ((x) & (~BITS_HCI_MAX_TXDMA)) #define BIT_GET_HCI_MAX_TXDMA(x) \ (((x) >> BIT_SHIFT_HCI_MAX_TXDMA) & BIT_MASK_HCI_MAX_TXDMA) #define BIT_SET_HCI_MAX_TXDMA(x, v) \ (BIT_CLEAR_HCI_MAX_TXDMA(x) | BIT_HCI_MAX_TXDMA(v)) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_LX_CTRL1 (Offset 0x0300) */ #define BIT_RD_LITT_EDN BIT(24) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PCIE_CTRL (Offset 0x0300) */ #define BIT_PWR_SCALE_START_PS BIT(23) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_PCIE_CTRL (Offset 0x0300) */ #define BIT_PCIE_RST_TRXDMA_INTF BIT(20) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HCI_CTRL (Offset 0x0300) */ #define BIT_HCI_RST_TRXDMA_INTF BIT(20) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_LX_CTRL1 (Offset 0x0300) */ #define BIT_SHIFT_MAX_RXDMA 20 #define BIT_MASK_MAX_RXDMA 0x7 #define BIT_MAX_RXDMA(x) (((x) & BIT_MASK_MAX_RXDMA) << BIT_SHIFT_MAX_RXDMA) #define BITS_MAX_RXDMA (BIT_MASK_MAX_RXDMA << BIT_SHIFT_MAX_RXDMA) #define BIT_CLEAR_MAX_RXDMA(x) ((x) & (~BITS_MAX_RXDMA)) #define BIT_GET_MAX_RXDMA(x) (((x) >> BIT_SHIFT_MAX_RXDMA) & BIT_MASK_MAX_RXDMA) #define BIT_SET_MAX_RXDMA(x, v) (BIT_CLEAR_MAX_RXDMA(x) | BIT_MAX_RXDMA(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_PCIE_CTRL (Offset 0x0300) */ #define BIT_PCIE_EN_SWENT_L23 BIT(17) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HCI_CTRL (Offset 0x0300) */ #define BIT_HCI_EN_SWENT_L23 BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_PCIE_CTRL (Offset 0x0300) */ #define BIT_PCIE_EN_HWEXT_L1 BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HCI_CTRL (Offset 0x0300) */ #define BIT_HCI_EN_HWEXT_L1 BIT(16) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_LX_CTRL1 (Offset 0x0300) */ #define BIT_SHIFT_MAX_TXDMA 16 #define BIT_MASK_MAX_TXDMA 0x7 #define BIT_MAX_TXDMA(x) (((x) & BIT_MASK_MAX_TXDMA) << BIT_SHIFT_MAX_TXDMA) #define BITS_MAX_TXDMA (BIT_MASK_MAX_TXDMA << BIT_SHIFT_MAX_TXDMA) #define BIT_CLEAR_MAX_TXDMA(x) ((x) & (~BITS_MAX_TXDMA)) #define BIT_GET_MAX_TXDMA(x) (((x) >> BIT_SHIFT_MAX_TXDMA) & BIT_MASK_MAX_TXDMA) #define BIT_SET_MAX_TXDMA(x, v) (BIT_CLEAR_MAX_TXDMA(x) | BIT_MAX_TXDMA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PCIE_CTRL (Offset 0x0300) */ #define BIT_STOP_P0_MPRT_BCNQ4 BIT(6) #define BIT_STOP_P0_MPRT_BCNQ3 BIT(4) #define BIT_STOP_P0_MPRT_BCNQ2 BIT(2) #define BIT_STOP_P0_MPRT_BCNQ1 BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_INT_MIG (Offset 0x0304) */ #define BIT_SHIFT_TXTTIMER_MATCH_NUM 28 #define BIT_MASK_TXTTIMER_MATCH_NUM 0xf #define BIT_TXTTIMER_MATCH_NUM(x) \ (((x) & BIT_MASK_TXTTIMER_MATCH_NUM) << BIT_SHIFT_TXTTIMER_MATCH_NUM) #define BITS_TXTTIMER_MATCH_NUM \ (BIT_MASK_TXTTIMER_MATCH_NUM << BIT_SHIFT_TXTTIMER_MATCH_NUM) #define BIT_CLEAR_TXTTIMER_MATCH_NUM(x) ((x) & (~BITS_TXTTIMER_MATCH_NUM)) #define BIT_GET_TXTTIMER_MATCH_NUM(x) \ (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM) & BIT_MASK_TXTTIMER_MATCH_NUM) #define BIT_SET_TXTTIMER_MATCH_NUM(x, v) \ (BIT_CLEAR_TXTTIMER_MATCH_NUM(x) | BIT_TXTTIMER_MATCH_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH_CTRL (Offset 0x0304) */ #define BIT_STOP_P0HIQ19 BIT(27) #define BIT_STOP_P0HIQ18 BIT(26) #define BIT_STOP_P0HIQ17 BIT(25) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_INT_MIG (Offset 0x0304) */ #define BIT_SHIFT_TXPKT_NUM_MATCH 24 #define BIT_MASK_TXPKT_NUM_MATCH 0xf #define BIT_TXPKT_NUM_MATCH(x) \ (((x) & BIT_MASK_TXPKT_NUM_MATCH) << BIT_SHIFT_TXPKT_NUM_MATCH) #define BITS_TXPKT_NUM_MATCH \ (BIT_MASK_TXPKT_NUM_MATCH << BIT_SHIFT_TXPKT_NUM_MATCH) #define BIT_CLEAR_TXPKT_NUM_MATCH(x) ((x) & (~BITS_TXPKT_NUM_MATCH)) #define BIT_GET_TXPKT_NUM_MATCH(x) \ (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH) & BIT_MASK_TXPKT_NUM_MATCH) #define BIT_SET_TXPKT_NUM_MATCH(x, v) \ (BIT_CLEAR_TXPKT_NUM_MATCH(x) | BIT_TXPKT_NUM_MATCH(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH_CTRL (Offset 0x0304) */ #define BIT_STOP_P0HIQ16 BIT(24) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_INT_MIG (Offset 0x0304) */ #define BIT_SHIFT_TRXCOUNTER_MATCH 24 #define BIT_MASK_TRXCOUNTER_MATCH 0xff #define BIT_TRXCOUNTER_MATCH(x) \ (((x) & BIT_MASK_TRXCOUNTER_MATCH) << BIT_SHIFT_TRXCOUNTER_MATCH) #define BITS_TRXCOUNTER_MATCH \ (BIT_MASK_TRXCOUNTER_MATCH << BIT_SHIFT_TRXCOUNTER_MATCH) #define BIT_CLEAR_TRXCOUNTER_MATCH(x) ((x) & (~BITS_TRXCOUNTER_MATCH)) #define BIT_GET_TRXCOUNTER_MATCH(x) \ (((x) >> BIT_SHIFT_TRXCOUNTER_MATCH) & BIT_MASK_TRXCOUNTER_MATCH) #define BIT_SET_TRXCOUNTER_MATCH(x, v) \ (BIT_CLEAR_TRXCOUNTER_MATCH(x) | BIT_TRXCOUNTER_MATCH(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH_CTRL (Offset 0x0304) */ #define BIT_RX_CLOSE_EN_V1 BIT(21) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_INT_MIG (Offset 0x0304) */ #define BIT_SHIFT_RXTTIMER_MATCH_NUM 20 #define BIT_MASK_RXTTIMER_MATCH_NUM 0xf #define BIT_RXTTIMER_MATCH_NUM(x) \ (((x) & BIT_MASK_RXTTIMER_MATCH_NUM) << BIT_SHIFT_RXTTIMER_MATCH_NUM) #define BITS_RXTTIMER_MATCH_NUM \ (BIT_MASK_RXTTIMER_MATCH_NUM << BIT_SHIFT_RXTTIMER_MATCH_NUM) #define BIT_CLEAR_RXTTIMER_MATCH_NUM(x) ((x) & (~BITS_RXTTIMER_MATCH_NUM)) #define BIT_GET_RXTTIMER_MATCH_NUM(x) \ (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM) & BIT_MASK_RXTTIMER_MATCH_NUM) #define BIT_SET_RXTTIMER_MATCH_NUM(x, v) \ (BIT_CLEAR_RXTTIMER_MATCH_NUM(x) | BIT_RXTTIMER_MATCH_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH_CTRL (Offset 0x0304) */ #define BIT_STOP_FWCMDQ BIT(20) #define BIT_STOP_P0BCNQ BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_INT_MIG (Offset 0x0304) */ #define BIT_SHIFT_RXPKT_NUM_MATCH 16 #define BIT_MASK_RXPKT_NUM_MATCH 0xf #define BIT_RXPKT_NUM_MATCH(x) \ (((x) & BIT_MASK_RXPKT_NUM_MATCH) << BIT_SHIFT_RXPKT_NUM_MATCH) #define BITS_RXPKT_NUM_MATCH \ (BIT_MASK_RXPKT_NUM_MATCH << BIT_SHIFT_RXPKT_NUM_MATCH) #define BIT_CLEAR_RXPKT_NUM_MATCH(x) ((x) & (~BITS_RXPKT_NUM_MATCH)) #define BIT_GET_RXPKT_NUM_MATCH(x) \ (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH) & BIT_MASK_RXPKT_NUM_MATCH) #define BIT_SET_RXPKT_NUM_MATCH(x, v) \ (BIT_CLEAR_RXPKT_NUM_MATCH(x) | BIT_RXPKT_NUM_MATCH(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH_CTRL (Offset 0x0304) */ #define BIT_STOP_P0MGQ BIT(16) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_INT_MIG (Offset 0x0304) */ #define BIT_SHIFT_TRXTIMER_MATCH 16 #define BIT_MASK_TRXTIMER_MATCH 0xff #define BIT_TRXTIMER_MATCH(x) \ (((x) & BIT_MASK_TRXTIMER_MATCH) << BIT_SHIFT_TRXTIMER_MATCH) #define BITS_TRXTIMER_MATCH \ (BIT_MASK_TRXTIMER_MATCH << BIT_SHIFT_TRXTIMER_MATCH) #define BIT_CLEAR_TRXTIMER_MATCH(x) ((x) & (~BITS_TRXTIMER_MATCH)) #define BIT_GET_TRXTIMER_MATCH(x) \ (((x) >> BIT_SHIFT_TRXTIMER_MATCH) & BIT_MASK_TRXTIMER_MATCH) #define BIT_SET_TRXTIMER_MATCH(x, v) \ (BIT_CLEAR_TRXTIMER_MATCH(x) | BIT_TRXTIMER_MATCH(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH_CTRL (Offset 0x0304) */ #define BIT_STOP_ACH13 BIT(15) #define BIT_STOP_ACH12 BIT(14) #define BIT_STOP_ACH11 BIT(13) #define BIT_STOP_ACH10 BIT(12) #define BIT_STOP_ACH9 BIT(11) #define BIT_STOP_ACH8 BIT(10) #define BIT_STOP_ACH7 BIT(9) #define BIT_STOP_ACH6 BIT(8) #define BIT_STOP_ACH5 BIT(7) #define BIT_STOP_ACH4 BIT(6) #define BIT_STOP_ACH3 BIT(5) #define BIT_STOP_ACH2 BIT(4) #define BIT_STOP_ACH1 BIT(3) #define BIT_STOP_ACH0 BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_INT_MIG (Offset 0x0304) */ #define BIT_SHIFT_MIGRATE_TIMER 0 #define BIT_MASK_MIGRATE_TIMER 0xffff #define BIT_MIGRATE_TIMER(x) \ (((x) & BIT_MASK_MIGRATE_TIMER) << BIT_SHIFT_MIGRATE_TIMER) #define BITS_MIGRATE_TIMER (BIT_MASK_MIGRATE_TIMER << BIT_SHIFT_MIGRATE_TIMER) #define BIT_CLEAR_MIGRATE_TIMER(x) ((x) & (~BITS_MIGRATE_TIMER)) #define BIT_GET_MIGRATE_TIMER(x) \ (((x) >> BIT_SHIFT_MIGRATE_TIMER) & BIT_MASK_MIGRATE_TIMER) #define BIT_SET_MIGRATE_TIMER(x, v) \ (BIT_CLEAR_MIGRATE_TIMER(x) | BIT_MIGRATE_TIMER(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH_CTRL (Offset 0x0304) */ #define BIT_STOP_P0RX BIT(0) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_INT_MIG (Offset 0x0304) */ #define BIT_SHIFT_TRXTIMER_UNIT 0 #define BIT_MASK_TRXTIMER_UNIT 0x3 #define BIT_TRXTIMER_UNIT(x) \ (((x) & BIT_MASK_TRXTIMER_UNIT) << BIT_SHIFT_TRXTIMER_UNIT) #define BITS_TRXTIMER_UNIT (BIT_MASK_TRXTIMER_UNIT << BIT_SHIFT_TRXTIMER_UNIT) #define BIT_CLEAR_TRXTIMER_UNIT(x) ((x) & (~BITS_TRXTIMER_UNIT)) #define BIT_GET_TRXTIMER_UNIT(x) \ (((x) >> BIT_SHIFT_TRXTIMER_UNIT) & BIT_MASK_TRXTIMER_UNIT) #define BIT_SET_TRXTIMER_UNIT(x, v) \ (BIT_CLEAR_TRXTIMER_UNIT(x) | BIT_TRXTIMER_UNIT(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIQ_CTRL (Offset 0x0308) */ #define BIT_STOP_P0HIQ15 BIT(15) #define BIT_STOP_P0HIQ14 BIT(14) #define BIT_STOP_P0HIQ13 BIT(13) #define BIT_STOP_P0HIQ12 BIT(12) #define BIT_STOP_P0HIQ11 BIT(11) #define BIT_STOP_P0HIQ10 BIT(10) #define BIT_STOP_P0HIQ9 BIT(9) #define BIT_STOP_P0HIQ8 BIT(8) #define BIT_STOP_P0HIQ7 BIT(7) #define BIT_STOP_P0HIQ6 BIT(6) #define BIT_STOP_P0HIQ5 BIT(5) #define BIT_STOP_P0HIQ4 BIT(4) #define BIT_STOP_P0HIQ3 BIT(3) #define BIT_STOP_P0HIQ2 BIT(2) #define BIT_STOP_P0HIQ1 BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BCNQ_TXBD_DESA (Offset 0x0308) */ #define BIT_SHIFT_BCNQ_TXBD_DESA 0 #define BIT_MASK_BCNQ_TXBD_DESA 0xffffffffffffffffL #define BIT_BCNQ_TXBD_DESA(x) \ (((x) & BIT_MASK_BCNQ_TXBD_DESA) << BIT_SHIFT_BCNQ_TXBD_DESA) #define BITS_BCNQ_TXBD_DESA \ (BIT_MASK_BCNQ_TXBD_DESA << BIT_SHIFT_BCNQ_TXBD_DESA) #define BIT_CLEAR_BCNQ_TXBD_DESA(x) ((x) & (~BITS_BCNQ_TXBD_DESA)) #define BIT_GET_BCNQ_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA) & BIT_MASK_BCNQ_TXBD_DESA) #define BIT_SET_BCNQ_TXBD_DESA(x, v) \ (BIT_CLEAR_BCNQ_TXBD_DESA(x) | BIT_BCNQ_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIQ_CTRL (Offset 0x0308) */ #define BIT_STOP_P0HIQ0 BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MGQ_TXBD_DESA (Offset 0x0310) */ #define BIT_SHIFT_MGQ_TXBD_DESA 0 #define BIT_MASK_MGQ_TXBD_DESA 0xffffffffffffffffL #define BIT_MGQ_TXBD_DESA(x) \ (((x) & BIT_MASK_MGQ_TXBD_DESA) << BIT_SHIFT_MGQ_TXBD_DESA) #define BITS_MGQ_TXBD_DESA (BIT_MASK_MGQ_TXBD_DESA << BIT_SHIFT_MGQ_TXBD_DESA) #define BIT_CLEAR_MGQ_TXBD_DESA(x) ((x) & (~BITS_MGQ_TXBD_DESA)) #define BIT_GET_MGQ_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_MGQ_TXBD_DESA) & BIT_MASK_MGQ_TXBD_DESA) #define BIT_SET_MGQ_TXBD_DESA(x, v) \ (BIT_CLEAR_MGQ_TXBD_DESA(x) | BIT_MGQ_TXBD_DESA(v)) /* 2 REG_VOQ_TXBD_DESA (Offset 0x0318) */ #define BIT_SHIFT_VOQ_TXBD_DESA 0 #define BIT_MASK_VOQ_TXBD_DESA 0xffffffffffffffffL #define BIT_VOQ_TXBD_DESA(x) \ (((x) & BIT_MASK_VOQ_TXBD_DESA) << BIT_SHIFT_VOQ_TXBD_DESA) #define BITS_VOQ_TXBD_DESA (BIT_MASK_VOQ_TXBD_DESA << BIT_SHIFT_VOQ_TXBD_DESA) #define BIT_CLEAR_VOQ_TXBD_DESA(x) ((x) & (~BITS_VOQ_TXBD_DESA)) #define BIT_GET_VOQ_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_VOQ_TXBD_DESA) & BIT_MASK_VOQ_TXBD_DESA) #define BIT_SET_VOQ_TXBD_DESA(x, v) \ (BIT_CLEAR_VOQ_TXBD_DESA(x) | BIT_VOQ_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH0_TXBD_DESA_L (Offset 0x0318) */ #define BIT_SHIFT_ACH0_TXBD_DESA_L 0 #define BIT_MASK_ACH0_TXBD_DESA_L 0xffffffffL #define BIT_ACH0_TXBD_DESA_L(x) \ (((x) & BIT_MASK_ACH0_TXBD_DESA_L) << BIT_SHIFT_ACH0_TXBD_DESA_L) #define BITS_ACH0_TXBD_DESA_L \ (BIT_MASK_ACH0_TXBD_DESA_L << BIT_SHIFT_ACH0_TXBD_DESA_L) #define BIT_CLEAR_ACH0_TXBD_DESA_L(x) ((x) & (~BITS_ACH0_TXBD_DESA_L)) #define BIT_GET_ACH0_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_ACH0_TXBD_DESA_L) & BIT_MASK_ACH0_TXBD_DESA_L) #define BIT_SET_ACH0_TXBD_DESA_L(x, v) \ (BIT_CLEAR_ACH0_TXBD_DESA_L(x) | BIT_ACH0_TXBD_DESA_L(v)) /* 2 REG_ACH0_TXBD_DESA_H (Offset 0x031C) */ #define BIT_SHIFT_ACH0_TXBD_DESA_H 0 #define BIT_MASK_ACH0_TXBD_DESA_H 0xffffffffL #define BIT_ACH0_TXBD_DESA_H(x) \ (((x) & BIT_MASK_ACH0_TXBD_DESA_H) << BIT_SHIFT_ACH0_TXBD_DESA_H) #define BITS_ACH0_TXBD_DESA_H \ (BIT_MASK_ACH0_TXBD_DESA_H << BIT_SHIFT_ACH0_TXBD_DESA_H) #define BIT_CLEAR_ACH0_TXBD_DESA_H(x) ((x) & (~BITS_ACH0_TXBD_DESA_H)) #define BIT_GET_ACH0_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_ACH0_TXBD_DESA_H) & BIT_MASK_ACH0_TXBD_DESA_H) #define BIT_SET_ACH0_TXBD_DESA_H(x, v) \ (BIT_CLEAR_ACH0_TXBD_DESA_H(x) | BIT_ACH0_TXBD_DESA_H(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_VIQ_TXBD_DESA (Offset 0x0320) */ #define BIT_SHIFT_VIQ_TXBD_DESA 0 #define BIT_MASK_VIQ_TXBD_DESA 0xffffffffffffffffL #define BIT_VIQ_TXBD_DESA(x) \ (((x) & BIT_MASK_VIQ_TXBD_DESA) << BIT_SHIFT_VIQ_TXBD_DESA) #define BITS_VIQ_TXBD_DESA (BIT_MASK_VIQ_TXBD_DESA << BIT_SHIFT_VIQ_TXBD_DESA) #define BIT_CLEAR_VIQ_TXBD_DESA(x) ((x) & (~BITS_VIQ_TXBD_DESA)) #define BIT_GET_VIQ_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_VIQ_TXBD_DESA) & BIT_MASK_VIQ_TXBD_DESA) #define BIT_SET_VIQ_TXBD_DESA(x, v) \ (BIT_CLEAR_VIQ_TXBD_DESA(x) | BIT_VIQ_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH1_TXBD_DESA_L (Offset 0x0320) */ #define BIT_SHIFT_ACH1_TXBD_DESA_L 0 #define BIT_MASK_ACH1_TXBD_DESA_L 0xffffffffL #define BIT_ACH1_TXBD_DESA_L(x) \ (((x) & BIT_MASK_ACH1_TXBD_DESA_L) << BIT_SHIFT_ACH1_TXBD_DESA_L) #define BITS_ACH1_TXBD_DESA_L \ (BIT_MASK_ACH1_TXBD_DESA_L << BIT_SHIFT_ACH1_TXBD_DESA_L) #define BIT_CLEAR_ACH1_TXBD_DESA_L(x) ((x) & (~BITS_ACH1_TXBD_DESA_L)) #define BIT_GET_ACH1_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_ACH1_TXBD_DESA_L) & BIT_MASK_ACH1_TXBD_DESA_L) #define BIT_SET_ACH1_TXBD_DESA_L(x, v) \ (BIT_CLEAR_ACH1_TXBD_DESA_L(x) | BIT_ACH1_TXBD_DESA_L(v)) /* 2 REG_ACH1_TXBD_DESA_H (Offset 0x0324) */ #define BIT_SHIFT_ACH1_TXBD_DESA_H 0 #define BIT_MASK_ACH1_TXBD_DESA_H 0xffffffffL #define BIT_ACH1_TXBD_DESA_H(x) \ (((x) & BIT_MASK_ACH1_TXBD_DESA_H) << BIT_SHIFT_ACH1_TXBD_DESA_H) #define BITS_ACH1_TXBD_DESA_H \ (BIT_MASK_ACH1_TXBD_DESA_H << BIT_SHIFT_ACH1_TXBD_DESA_H) #define BIT_CLEAR_ACH1_TXBD_DESA_H(x) ((x) & (~BITS_ACH1_TXBD_DESA_H)) #define BIT_GET_ACH1_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_ACH1_TXBD_DESA_H) & BIT_MASK_ACH1_TXBD_DESA_H) #define BIT_SET_ACH1_TXBD_DESA_H(x, v) \ (BIT_CLEAR_ACH1_TXBD_DESA_H(x) | BIT_ACH1_TXBD_DESA_H(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BEQ_TXBD_DESA (Offset 0x0328) */ #define BIT_SHIFT_BEQ_TXBD_DESA 0 #define BIT_MASK_BEQ_TXBD_DESA 0xffffffffffffffffL #define BIT_BEQ_TXBD_DESA(x) \ (((x) & BIT_MASK_BEQ_TXBD_DESA) << BIT_SHIFT_BEQ_TXBD_DESA) #define BITS_BEQ_TXBD_DESA (BIT_MASK_BEQ_TXBD_DESA << BIT_SHIFT_BEQ_TXBD_DESA) #define BIT_CLEAR_BEQ_TXBD_DESA(x) ((x) & (~BITS_BEQ_TXBD_DESA)) #define BIT_GET_BEQ_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_BEQ_TXBD_DESA) & BIT_MASK_BEQ_TXBD_DESA) #define BIT_SET_BEQ_TXBD_DESA(x, v) \ (BIT_CLEAR_BEQ_TXBD_DESA(x) | BIT_BEQ_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH2_TXBD_DESA_L (Offset 0x0328) */ #define BIT_SHIFT_ACH2_TXBD_DESA_L 0 #define BIT_MASK_ACH2_TXBD_DESA_L 0xffffffffL #define BIT_ACH2_TXBD_DESA_L(x) \ (((x) & BIT_MASK_ACH2_TXBD_DESA_L) << BIT_SHIFT_ACH2_TXBD_DESA_L) #define BITS_ACH2_TXBD_DESA_L \ (BIT_MASK_ACH2_TXBD_DESA_L << BIT_SHIFT_ACH2_TXBD_DESA_L) #define BIT_CLEAR_ACH2_TXBD_DESA_L(x) ((x) & (~BITS_ACH2_TXBD_DESA_L)) #define BIT_GET_ACH2_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_ACH2_TXBD_DESA_L) & BIT_MASK_ACH2_TXBD_DESA_L) #define BIT_SET_ACH2_TXBD_DESA_L(x, v) \ (BIT_CLEAR_ACH2_TXBD_DESA_L(x) | BIT_ACH2_TXBD_DESA_L(v)) /* 2 REG_ACH2_TXBD_DESA_H (Offset 0x032C) */ #define BIT_SHIFT_ACH2_TXBD_DESA_H 0 #define BIT_MASK_ACH2_TXBD_DESA_H 0xffffffffL #define BIT_ACH2_TXBD_DESA_H(x) \ (((x) & BIT_MASK_ACH2_TXBD_DESA_H) << BIT_SHIFT_ACH2_TXBD_DESA_H) #define BITS_ACH2_TXBD_DESA_H \ (BIT_MASK_ACH2_TXBD_DESA_H << BIT_SHIFT_ACH2_TXBD_DESA_H) #define BIT_CLEAR_ACH2_TXBD_DESA_H(x) ((x) & (~BITS_ACH2_TXBD_DESA_H)) #define BIT_GET_ACH2_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_ACH2_TXBD_DESA_H) & BIT_MASK_ACH2_TXBD_DESA_H) #define BIT_SET_ACH2_TXBD_DESA_H(x, v) \ (BIT_CLEAR_ACH2_TXBD_DESA_H(x) | BIT_ACH2_TXBD_DESA_H(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BKQ_TXBD_DESA (Offset 0x0330) */ #define BIT_SHIFT_BKQ_TXBD_DESA 0 #define BIT_MASK_BKQ_TXBD_DESA 0xffffffffffffffffL #define BIT_BKQ_TXBD_DESA(x) \ (((x) & BIT_MASK_BKQ_TXBD_DESA) << BIT_SHIFT_BKQ_TXBD_DESA) #define BITS_BKQ_TXBD_DESA (BIT_MASK_BKQ_TXBD_DESA << BIT_SHIFT_BKQ_TXBD_DESA) #define BIT_CLEAR_BKQ_TXBD_DESA(x) ((x) & (~BITS_BKQ_TXBD_DESA)) #define BIT_GET_BKQ_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_BKQ_TXBD_DESA) & BIT_MASK_BKQ_TXBD_DESA) #define BIT_SET_BKQ_TXBD_DESA(x, v) \ (BIT_CLEAR_BKQ_TXBD_DESA(x) | BIT_BKQ_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH3_TXBD_DESA_L (Offset 0x0330) */ #define BIT_SHIFT_ACH3_TXBD_DESA_L 0 #define BIT_MASK_ACH3_TXBD_DESA_L 0xffffffffL #define BIT_ACH3_TXBD_DESA_L(x) \ (((x) & BIT_MASK_ACH3_TXBD_DESA_L) << BIT_SHIFT_ACH3_TXBD_DESA_L) #define BITS_ACH3_TXBD_DESA_L \ (BIT_MASK_ACH3_TXBD_DESA_L << BIT_SHIFT_ACH3_TXBD_DESA_L) #define BIT_CLEAR_ACH3_TXBD_DESA_L(x) ((x) & (~BITS_ACH3_TXBD_DESA_L)) #define BIT_GET_ACH3_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_ACH3_TXBD_DESA_L) & BIT_MASK_ACH3_TXBD_DESA_L) #define BIT_SET_ACH3_TXBD_DESA_L(x, v) \ (BIT_CLEAR_ACH3_TXBD_DESA_L(x) | BIT_ACH3_TXBD_DESA_L(v)) /* 2 REG_ACH3_TXBD_DESA_H (Offset 0x0334) */ #define BIT_SHIFT_ACH3_TXBD_DESA_H 0 #define BIT_MASK_ACH3_TXBD_DESA_H 0xffffffffL #define BIT_ACH3_TXBD_DESA_H(x) \ (((x) & BIT_MASK_ACH3_TXBD_DESA_H) << BIT_SHIFT_ACH3_TXBD_DESA_H) #define BITS_ACH3_TXBD_DESA_H \ (BIT_MASK_ACH3_TXBD_DESA_H << BIT_SHIFT_ACH3_TXBD_DESA_H) #define BIT_CLEAR_ACH3_TXBD_DESA_H(x) ((x) & (~BITS_ACH3_TXBD_DESA_H)) #define BIT_GET_ACH3_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_ACH3_TXBD_DESA_H) & BIT_MASK_ACH3_TXBD_DESA_H) #define BIT_SET_ACH3_TXBD_DESA_H(x, v) \ (BIT_CLEAR_ACH3_TXBD_DESA_H(x) | BIT_ACH3_TXBD_DESA_H(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXQ_RXBD_DESA (Offset 0x0338) */ #define BIT_SHIFT_RXQ_RXBD_DESA 0 #define BIT_MASK_RXQ_RXBD_DESA 0xffffffffffffffffL #define BIT_RXQ_RXBD_DESA(x) \ (((x) & BIT_MASK_RXQ_RXBD_DESA) << BIT_SHIFT_RXQ_RXBD_DESA) #define BITS_RXQ_RXBD_DESA (BIT_MASK_RXQ_RXBD_DESA << BIT_SHIFT_RXQ_RXBD_DESA) #define BIT_CLEAR_RXQ_RXBD_DESA(x) ((x) & (~BITS_RXQ_RXBD_DESA)) #define BIT_GET_RXQ_RXBD_DESA(x) \ (((x) >> BIT_SHIFT_RXQ_RXBD_DESA) & BIT_MASK_RXQ_RXBD_DESA) #define BIT_SET_RXQ_RXBD_DESA(x, v) \ (BIT_CLEAR_RXQ_RXBD_DESA(x) | BIT_RXQ_RXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0RXQ_RXBD_DESA_L (Offset 0x0338) */ #define BIT_SHIFT_P0RXQ_RXBD_DESA_L 0 #define BIT_MASK_P0RXQ_RXBD_DESA_L 0xffffffffL #define BIT_P0RXQ_RXBD_DESA_L(x) \ (((x) & BIT_MASK_P0RXQ_RXBD_DESA_L) << BIT_SHIFT_P0RXQ_RXBD_DESA_L) #define BITS_P0RXQ_RXBD_DESA_L \ (BIT_MASK_P0RXQ_RXBD_DESA_L << BIT_SHIFT_P0RXQ_RXBD_DESA_L) #define BIT_CLEAR_P0RXQ_RXBD_DESA_L(x) ((x) & (~BITS_P0RXQ_RXBD_DESA_L)) #define BIT_GET_P0RXQ_RXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_L) & BIT_MASK_P0RXQ_RXBD_DESA_L) #define BIT_SET_P0RXQ_RXBD_DESA_L(x, v) \ (BIT_CLEAR_P0RXQ_RXBD_DESA_L(x) | BIT_P0RXQ_RXBD_DESA_L(v)) /* 2 REG_P0RXQ_RXBD_DESA_H (Offset 0x033C) */ #define BIT_SHIFT_P0RXQ_RXBD_DESA_H 0 #define BIT_MASK_P0RXQ_RXBD_DESA_H 0xffffffffL #define BIT_P0RXQ_RXBD_DESA_H(x) \ (((x) & BIT_MASK_P0RXQ_RXBD_DESA_H) << BIT_SHIFT_P0RXQ_RXBD_DESA_H) #define BITS_P0RXQ_RXBD_DESA_H \ (BIT_MASK_P0RXQ_RXBD_DESA_H << BIT_SHIFT_P0RXQ_RXBD_DESA_H) #define BIT_CLEAR_P0RXQ_RXBD_DESA_H(x) ((x) & (~BITS_P0RXQ_RXBD_DESA_H)) #define BIT_GET_P0RXQ_RXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_H) & BIT_MASK_P0RXQ_RXBD_DESA_H) #define BIT_SET_P0RXQ_RXBD_DESA_H(x, v) \ (BIT_CLEAR_P0RXQ_RXBD_DESA_H(x) | BIT_P0RXQ_RXBD_DESA_H(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI0Q_TXBD_DESA (Offset 0x0340) */ #define BIT_SHIFT_HI0Q_TXBD_DESA 0 #define BIT_MASK_HI0Q_TXBD_DESA 0xffffffffffffffffL #define BIT_HI0Q_TXBD_DESA(x) \ (((x) & BIT_MASK_HI0Q_TXBD_DESA) << BIT_SHIFT_HI0Q_TXBD_DESA) #define BITS_HI0Q_TXBD_DESA \ (BIT_MASK_HI0Q_TXBD_DESA << BIT_SHIFT_HI0Q_TXBD_DESA) #define BIT_CLEAR_HI0Q_TXBD_DESA(x) ((x) & (~BITS_HI0Q_TXBD_DESA)) #define BIT_GET_HI0Q_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA) & BIT_MASK_HI0Q_TXBD_DESA) #define BIT_SET_HI0Q_TXBD_DESA(x, v) \ (BIT_CLEAR_HI0Q_TXBD_DESA(x) | BIT_HI0Q_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0BCNQ_TXBD_DESA_L (Offset 0x0340) */ #define BIT_SHIFT_P0BCNQ_TXBD_DESA_L 0 #define BIT_MASK_P0BCNQ_TXBD_DESA_L 0xffffffffL #define BIT_P0BCNQ_TXBD_DESA_L(x) \ (((x) & BIT_MASK_P0BCNQ_TXBD_DESA_L) << BIT_SHIFT_P0BCNQ_TXBD_DESA_L) #define BITS_P0BCNQ_TXBD_DESA_L \ (BIT_MASK_P0BCNQ_TXBD_DESA_L << BIT_SHIFT_P0BCNQ_TXBD_DESA_L) #define BIT_CLEAR_P0BCNQ_TXBD_DESA_L(x) ((x) & (~BITS_P0BCNQ_TXBD_DESA_L)) #define BIT_GET_P0BCNQ_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_L) & BIT_MASK_P0BCNQ_TXBD_DESA_L) #define BIT_SET_P0BCNQ_TXBD_DESA_L(x, v) \ (BIT_CLEAR_P0BCNQ_TXBD_DESA_L(x) | BIT_P0BCNQ_TXBD_DESA_L(v)) /* 2 REG_P0BCNQ_TXBD_DESA_H (Offset 0x0344) */ #define BIT_SHIFT_P0BCNQ_TXBD_DESA_H 0 #define BIT_MASK_P0BCNQ_TXBD_DESA_H 0xffffffffL #define BIT_P0BCNQ_TXBD_DESA_H(x) \ (((x) & BIT_MASK_P0BCNQ_TXBD_DESA_H) << BIT_SHIFT_P0BCNQ_TXBD_DESA_H) #define BITS_P0BCNQ_TXBD_DESA_H \ (BIT_MASK_P0BCNQ_TXBD_DESA_H << BIT_SHIFT_P0BCNQ_TXBD_DESA_H) #define BIT_CLEAR_P0BCNQ_TXBD_DESA_H(x) ((x) & (~BITS_P0BCNQ_TXBD_DESA_H)) #define BIT_GET_P0BCNQ_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_H) & BIT_MASK_P0BCNQ_TXBD_DESA_H) #define BIT_SET_P0BCNQ_TXBD_DESA_H(x, v) \ (BIT_CLEAR_P0BCNQ_TXBD_DESA_H(x) | BIT_P0BCNQ_TXBD_DESA_H(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI1Q_TXBD_DESA (Offset 0x0348) */ #define BIT_SHIFT_HI1Q_TXBD_DESA 0 #define BIT_MASK_HI1Q_TXBD_DESA 0xffffffffffffffffL #define BIT_HI1Q_TXBD_DESA(x) \ (((x) & BIT_MASK_HI1Q_TXBD_DESA) << BIT_SHIFT_HI1Q_TXBD_DESA) #define BITS_HI1Q_TXBD_DESA \ (BIT_MASK_HI1Q_TXBD_DESA << BIT_SHIFT_HI1Q_TXBD_DESA) #define BIT_CLEAR_HI1Q_TXBD_DESA(x) ((x) & (~BITS_HI1Q_TXBD_DESA)) #define BIT_GET_HI1Q_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA) & BIT_MASK_HI1Q_TXBD_DESA) #define BIT_SET_HI1Q_TXBD_DESA(x, v) \ (BIT_CLEAR_HI1Q_TXBD_DESA(x) | BIT_HI1Q_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FWCMDQ_TXBD_DESA_L (Offset 0x0348) */ #define BIT_SHIFT_FWCMDQ_TXBD_DESA_L 0 #define BIT_MASK_FWCMDQ_TXBD_DESA_L 0xffffffffL #define BIT_FWCMDQ_TXBD_DESA_L(x) \ (((x) & BIT_MASK_FWCMDQ_TXBD_DESA_L) << BIT_SHIFT_FWCMDQ_TXBD_DESA_L) #define BITS_FWCMDQ_TXBD_DESA_L \ (BIT_MASK_FWCMDQ_TXBD_DESA_L << BIT_SHIFT_FWCMDQ_TXBD_DESA_L) #define BIT_CLEAR_FWCMDQ_TXBD_DESA_L(x) ((x) & (~BITS_FWCMDQ_TXBD_DESA_L)) #define BIT_GET_FWCMDQ_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_L) & BIT_MASK_FWCMDQ_TXBD_DESA_L) #define BIT_SET_FWCMDQ_TXBD_DESA_L(x, v) \ (BIT_CLEAR_FWCMDQ_TXBD_DESA_L(x) | BIT_FWCMDQ_TXBD_DESA_L(v)) /* 2 REG_FWCMDQ_TXBD_DESA_H (Offset 0x034C) */ #define BIT_SHIFT_FWCMDQ_TXBD_DESA_H 0 #define BIT_MASK_FWCMDQ_TXBD_DESA_H 0xffffffffL #define BIT_FWCMDQ_TXBD_DESA_H(x) \ (((x) & BIT_MASK_FWCMDQ_TXBD_DESA_H) << BIT_SHIFT_FWCMDQ_TXBD_DESA_H) #define BITS_FWCMDQ_TXBD_DESA_H \ (BIT_MASK_FWCMDQ_TXBD_DESA_H << BIT_SHIFT_FWCMDQ_TXBD_DESA_H) #define BIT_CLEAR_FWCMDQ_TXBD_DESA_H(x) ((x) & (~BITS_FWCMDQ_TXBD_DESA_H)) #define BIT_GET_FWCMDQ_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_H) & BIT_MASK_FWCMDQ_TXBD_DESA_H) #define BIT_SET_FWCMDQ_TXBD_DESA_H(x, v) \ (BIT_CLEAR_FWCMDQ_TXBD_DESA_H(x) | BIT_FWCMDQ_TXBD_DESA_H(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI2Q_TXBD_DESA (Offset 0x0350) */ #define BIT_SHIFT_HI2Q_TXBD_DESA 0 #define BIT_MASK_HI2Q_TXBD_DESA 0xffffffffffffffffL #define BIT_HI2Q_TXBD_DESA(x) \ (((x) & BIT_MASK_HI2Q_TXBD_DESA) << BIT_SHIFT_HI2Q_TXBD_DESA) #define BITS_HI2Q_TXBD_DESA \ (BIT_MASK_HI2Q_TXBD_DESA << BIT_SHIFT_HI2Q_TXBD_DESA) #define BIT_CLEAR_HI2Q_TXBD_DESA(x) ((x) & (~BITS_HI2Q_TXBD_DESA)) #define BIT_GET_HI2Q_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA) & BIT_MASK_HI2Q_TXBD_DESA) #define BIT_SET_HI2Q_TXBD_DESA(x, v) \ (BIT_CLEAR_HI2Q_TXBD_DESA(x) | BIT_HI2Q_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PCIE_HRPWM1_HCPWM1_DCPU (Offset 0x0354) */ #define BIT_SHIFT_PCIE_HCPWM1_DCPU 16 #define BIT_MASK_PCIE_HCPWM1_DCPU 0xff #define BIT_PCIE_HCPWM1_DCPU(x) \ (((x) & BIT_MASK_PCIE_HCPWM1_DCPU) << BIT_SHIFT_PCIE_HCPWM1_DCPU) #define BITS_PCIE_HCPWM1_DCPU \ (BIT_MASK_PCIE_HCPWM1_DCPU << BIT_SHIFT_PCIE_HCPWM1_DCPU) #define BIT_CLEAR_PCIE_HCPWM1_DCPU(x) ((x) & (~BITS_PCIE_HCPWM1_DCPU)) #define BIT_GET_PCIE_HCPWM1_DCPU(x) \ (((x) >> BIT_SHIFT_PCIE_HCPWM1_DCPU) & BIT_MASK_PCIE_HCPWM1_DCPU) #define BIT_SET_PCIE_HCPWM1_DCPU(x, v) \ (BIT_CLEAR_PCIE_HCPWM1_DCPU(x) | BIT_PCIE_HCPWM1_DCPU(v)) #define BIT_SHIFT_PCIE_HRPWM1_DCPU 8 #define BIT_MASK_PCIE_HRPWM1_DCPU 0xff #define BIT_PCIE_HRPWM1_DCPU(x) \ (((x) & BIT_MASK_PCIE_HRPWM1_DCPU) << BIT_SHIFT_PCIE_HRPWM1_DCPU) #define BITS_PCIE_HRPWM1_DCPU \ (BIT_MASK_PCIE_HRPWM1_DCPU << BIT_SHIFT_PCIE_HRPWM1_DCPU) #define BIT_CLEAR_PCIE_HRPWM1_DCPU(x) ((x) & (~BITS_PCIE_HRPWM1_DCPU)) #define BIT_GET_PCIE_HRPWM1_DCPU(x) \ (((x) >> BIT_SHIFT_PCIE_HRPWM1_DCPU) & BIT_MASK_PCIE_HRPWM1_DCPU) #define BIT_SET_PCIE_HRPWM1_DCPU(x, v) \ (BIT_CLEAR_PCIE_HRPWM1_DCPU(x) | BIT_PCIE_HRPWM1_DCPU(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI3Q_TXBD_DESA (Offset 0x0358) */ #define BIT_SHIFT_HI3Q_TXBD_DESA 0 #define BIT_MASK_HI3Q_TXBD_DESA 0xffffffffffffffffL #define BIT_HI3Q_TXBD_DESA(x) \ (((x) & BIT_MASK_HI3Q_TXBD_DESA) << BIT_SHIFT_HI3Q_TXBD_DESA) #define BITS_HI3Q_TXBD_DESA \ (BIT_MASK_HI3Q_TXBD_DESA << BIT_SHIFT_HI3Q_TXBD_DESA) #define BIT_CLEAR_HI3Q_TXBD_DESA(x) ((x) & (~BITS_HI3Q_TXBD_DESA)) #define BIT_GET_HI3Q_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA) & BIT_MASK_HI3Q_TXBD_DESA) #define BIT_SET_HI3Q_TXBD_DESA(x, v) \ (BIT_CLEAR_HI3Q_TXBD_DESA(x) | BIT_HI3Q_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_L (Offset 0x0358) */ #define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L 0 #define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L 0xffffffffL #define BIT_P0_MPRT_BCNQ_TXBD_DESA_L(x) \ (((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L) \ << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L) #define BITS_P0_MPRT_BCNQ_TXBD_DESA_L \ (BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L \ << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L) #define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L(x) \ ((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_L)) #define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L) & \ BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L) #define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_L(x, v) \ (BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L(x) | \ BIT_P0_MPRT_BCNQ_TXBD_DESA_L(v)) /* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_H (Offset 0x035C) */ #define BIT_CLR_P0HI15Q_HW_IDX BIT(29) #define BIT_CLR_P0HI14Q_HW_IDX BIT(28) #define BIT_CLR_P0HI13Q_HW_IDX BIT(27) #define BIT_CLR_P0HI12Q_HW_IDX BIT(26) #define BIT_CLR_P0HI11Q_HW_IDX BIT(25) #define BIT_CLR_P0HI10Q_HW_IDX BIT(24) #define BIT_CLR_P0HI9Q_HW_IDX BIT(23) #define BIT_CLR_P0HI8Q_HW_IDX BIT(22) #define BIT_CLR_ACH7_HW_IDX BIT(21) #define BIT_CLR_ACH13_HW_IDX BIT(21) #define BIT_CLR_ACH6_HW_IDX BIT(20) #define BIT_CLR_ACH12_HW_IDX BIT(20) #define BIT_CLR_ACH5_HW_IDX BIT(19) #define BIT_CLR_ACH11_HW_IDX BIT(19) #define BIT_CLR_ACH4_HW_IDX BIT(18) #define BIT_CLR_ACH10_HW_IDX BIT(18) #define BIT_CLR_ACH9_HW_IDX BIT(17) #define BIT_CLR_ACH8_HW_IDX BIT(16) #define BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE 13 #define BIT_MASK_P0_MPRT_BCNQ_DESC_MODE 0x3 #define BIT_P0_MPRT_BCNQ_DESC_MODE(x) \ (((x) & BIT_MASK_P0_MPRT_BCNQ_DESC_MODE) \ << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE) #define BITS_P0_MPRT_BCNQ_DESC_MODE \ (BIT_MASK_P0_MPRT_BCNQ_DESC_MODE << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE) #define BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE(x) \ ((x) & (~BITS_P0_MPRT_BCNQ_DESC_MODE)) #define BIT_GET_P0_MPRT_BCNQ_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE) & \ BIT_MASK_P0_MPRT_BCNQ_DESC_MODE) #define BIT_SET_P0_MPRT_BCNQ_DESC_MODE(x, v) \ (BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE(x) | BIT_P0_MPRT_BCNQ_DESC_MODE(v)) #define BIT_CLR_P0HI15Q_HOST_IDX BIT(13) #define BIT_CLR_P0HI14Q_HOST_IDX BIT(12) #define BIT_PCIE_P0MPRT_BCNQ4_FLAG BIT(11) #define BIT_CLR_P0HI13Q_HOST_IDX BIT(11) #define BIT_PCIE_P0MPRT_BCNQ3_FLAG BIT(10) #define BIT_CLR_P0HI12Q_HOST_IDX BIT(10) #define BIT_PCIE_P0MPRT_BCNQ2_FLAG BIT(9) #define BIT_CLR_P0HI11Q_HOST_IDX BIT(9) #define BIT_PCIE_P0MPRT_BCNQ1_FLAG BIT(8) #define BIT_CLR_P0HI10Q_HOST_IDX BIT(8) #define BIT_CLR_P0HI9Q_HOST_IDX BIT(7) #define BIT_CLR_P0HI8Q_HOST_IDX BIT(6) #define BIT_CLR_ACH7_HOST_IDX BIT(5) #define BIT_CLR_ACH13_HOST_IDX BIT(5) #define BIT_CLR_ACH6_HOST_IDX BIT(4) #define BIT_CLR_ACH12_HOST_IDX BIT(4) #define BIT_CLR_ACH5_HOST_IDX BIT(3) #define BIT_CLR_ACH11_HOST_IDX BIT(3) #define BIT_CLR_ACH4_HOST_IDX BIT(2) #define BIT_CLR_ACH10_HOST_IDX BIT(2) #define BIT_EPHY_CAL_DONE BIT(1) #define BIT_CLR_ACH9_HOST_IDX BIT(1) #define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H 0 #define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H 0xffffffffL #define BIT_P0_MPRT_BCNQ_TXBD_DESA_H(x) \ (((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H) \ << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H) #define BITS_P0_MPRT_BCNQ_TXBD_DESA_H \ (BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H \ << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H) #define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H(x) \ ((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_H)) #define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H) & \ BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H) #define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_H(x, v) \ (BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H(x) | \ BIT_P0_MPRT_BCNQ_TXBD_DESA_H(v)) #define BIT_RESET_APHY BIT(0) #define BIT_CLR_ACH8_HOST_IDX BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI4Q_TXBD_DESA (Offset 0x0360) */ #define BIT_SHIFT_HI4Q_TXBD_DESA 0 #define BIT_MASK_HI4Q_TXBD_DESA 0xffffffffffffffffL #define BIT_HI4Q_TXBD_DESA(x) \ (((x) & BIT_MASK_HI4Q_TXBD_DESA) << BIT_SHIFT_HI4Q_TXBD_DESA) #define BITS_HI4Q_TXBD_DESA \ (BIT_MASK_HI4Q_TXBD_DESA << BIT_SHIFT_HI4Q_TXBD_DESA) #define BIT_CLEAR_HI4Q_TXBD_DESA(x) ((x) & (~BITS_HI4Q_TXBD_DESA)) #define BIT_GET_HI4Q_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA) & BIT_MASK_HI4Q_TXBD_DESA) #define BIT_SET_HI4Q_TXBD_DESA(x, v) \ (BIT_CLEAR_HI4Q_TXBD_DESA(x) | BIT_HI4Q_TXBD_DESA(v)) /* 2 REG_HI5Q_TXBD_DESA (Offset 0x0368) */ #define BIT_SHIFT_HI5Q_TXBD_DESA 0 #define BIT_MASK_HI5Q_TXBD_DESA 0xffffffffffffffffL #define BIT_HI5Q_TXBD_DESA(x) \ (((x) & BIT_MASK_HI5Q_TXBD_DESA) << BIT_SHIFT_HI5Q_TXBD_DESA) #define BITS_HI5Q_TXBD_DESA \ (BIT_MASK_HI5Q_TXBD_DESA << BIT_SHIFT_HI5Q_TXBD_DESA) #define BIT_CLEAR_HI5Q_TXBD_DESA(x) ((x) & (~BITS_HI5Q_TXBD_DESA)) #define BIT_GET_HI5Q_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA) & BIT_MASK_HI5Q_TXBD_DESA) #define BIT_SET_HI5Q_TXBD_DESA(x, v) \ (BIT_CLEAR_HI5Q_TXBD_DESA(x) | BIT_HI5Q_TXBD_DESA(v)) /* 2 REG_HI6Q_TXBD_DESA (Offset 0x0370) */ #define BIT_SHIFT_HI6Q_TXBD_DESA 0 #define BIT_MASK_HI6Q_TXBD_DESA 0xffffffffffffffffL #define BIT_HI6Q_TXBD_DESA(x) \ (((x) & BIT_MASK_HI6Q_TXBD_DESA) << BIT_SHIFT_HI6Q_TXBD_DESA) #define BITS_HI6Q_TXBD_DESA \ (BIT_MASK_HI6Q_TXBD_DESA << BIT_SHIFT_HI6Q_TXBD_DESA) #define BIT_CLEAR_HI6Q_TXBD_DESA(x) ((x) & (~BITS_HI6Q_TXBD_DESA)) #define BIT_GET_HI6Q_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA) & BIT_MASK_HI6Q_TXBD_DESA) #define BIT_SET_HI6Q_TXBD_DESA(x, v) \ (BIT_CLEAR_HI6Q_TXBD_DESA(x) | BIT_HI6Q_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0MGQ_RXQ_TXRXBD_NUM (Offset 0x0378) */ #define BIT_SYS_32_64_V1 BIT(31) #define BIT_SHIFT_P0BCNQ_DESC_MODE 29 #define BIT_MASK_P0BCNQ_DESC_MODE 0x3 #define BIT_P0BCNQ_DESC_MODE(x) \ (((x) & BIT_MASK_P0BCNQ_DESC_MODE) << BIT_SHIFT_P0BCNQ_DESC_MODE) #define BITS_P0BCNQ_DESC_MODE \ (BIT_MASK_P0BCNQ_DESC_MODE << BIT_SHIFT_P0BCNQ_DESC_MODE) #define BIT_CLEAR_P0BCNQ_DESC_MODE(x) ((x) & (~BITS_P0BCNQ_DESC_MODE)) #define BIT_GET_P0BCNQ_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0BCNQ_DESC_MODE) & BIT_MASK_P0BCNQ_DESC_MODE) #define BIT_SET_P0BCNQ_DESC_MODE(x, v) \ (BIT_CLEAR_P0BCNQ_DESC_MODE(x) | BIT_P0BCNQ_DESC_MODE(v)) #define BIT_PCIE_P0BCNQ_FLAG BIT(28) #define BIT_SHIFT_P0RXQ_DESC_NUM 16 #define BIT_MASK_P0RXQ_DESC_NUM 0xfff #define BIT_P0RXQ_DESC_NUM(x) \ (((x) & BIT_MASK_P0RXQ_DESC_NUM) << BIT_SHIFT_P0RXQ_DESC_NUM) #define BITS_P0RXQ_DESC_NUM \ (BIT_MASK_P0RXQ_DESC_NUM << BIT_SHIFT_P0RXQ_DESC_NUM) #define BIT_CLEAR_P0RXQ_DESC_NUM(x) ((x) & (~BITS_P0RXQ_DESC_NUM)) #define BIT_GET_P0RXQ_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0RXQ_DESC_NUM) & BIT_MASK_P0RXQ_DESC_NUM) #define BIT_SET_P0RXQ_DESC_NUM(x, v) \ (BIT_CLEAR_P0RXQ_DESC_NUM(x) | BIT_P0RXQ_DESC_NUM(v)) #define BIT_PCIE_P0MGQ_FLAG BIT(14) #define BIT_SHIFT_P0MGQ_DESC_MODE 12 #define BIT_MASK_P0MGQ_DESC_MODE 0x3 #define BIT_P0MGQ_DESC_MODE(x) \ (((x) & BIT_MASK_P0MGQ_DESC_MODE) << BIT_SHIFT_P0MGQ_DESC_MODE) #define BITS_P0MGQ_DESC_MODE \ (BIT_MASK_P0MGQ_DESC_MODE << BIT_SHIFT_P0MGQ_DESC_MODE) #define BIT_CLEAR_P0MGQ_DESC_MODE(x) ((x) & (~BITS_P0MGQ_DESC_MODE)) #define BIT_GET_P0MGQ_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0MGQ_DESC_MODE) & BIT_MASK_P0MGQ_DESC_MODE) #define BIT_SET_P0MGQ_DESC_MODE(x, v) \ (BIT_CLEAR_P0MGQ_DESC_MODE(x) | BIT_P0MGQ_DESC_MODE(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI7Q_TXBD_DESA (Offset 0x0378) */ #define BIT_SHIFT_HI7Q_TXBD_DESA 0 #define BIT_MASK_HI7Q_TXBD_DESA 0xffffffffffffffffL #define BIT_HI7Q_TXBD_DESA(x) \ (((x) & BIT_MASK_HI7Q_TXBD_DESA) << BIT_SHIFT_HI7Q_TXBD_DESA) #define BITS_HI7Q_TXBD_DESA \ (BIT_MASK_HI7Q_TXBD_DESA << BIT_SHIFT_HI7Q_TXBD_DESA) #define BIT_CLEAR_HI7Q_TXBD_DESA(x) ((x) & (~BITS_HI7Q_TXBD_DESA)) #define BIT_GET_HI7Q_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA) & BIT_MASK_HI7Q_TXBD_DESA) #define BIT_SET_HI7Q_TXBD_DESA(x, v) \ (BIT_CLEAR_HI7Q_TXBD_DESA(x) | BIT_HI7Q_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0MGQ_RXQ_TXRXBD_NUM (Offset 0x0378) */ #define BIT_SHIFT_P0MGQ_DESC_NUM 0 #define BIT_MASK_P0MGQ_DESC_NUM 0xfff #define BIT_P0MGQ_DESC_NUM(x) \ (((x) & BIT_MASK_P0MGQ_DESC_NUM) << BIT_SHIFT_P0MGQ_DESC_NUM) #define BITS_P0MGQ_DESC_NUM \ (BIT_MASK_P0MGQ_DESC_NUM << BIT_SHIFT_P0MGQ_DESC_NUM) #define BIT_CLEAR_P0MGQ_DESC_NUM(x) ((x) & (~BITS_P0MGQ_DESC_NUM)) #define BIT_GET_P0MGQ_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0MGQ_DESC_NUM) & BIT_MASK_P0MGQ_DESC_NUM) #define BIT_SET_P0MGQ_DESC_NUM(x, v) \ (BIT_CLEAR_P0MGQ_DESC_NUM(x) | BIT_P0MGQ_DESC_NUM(v)) /* 2 REG_CHNL_DMA_CFG (Offset 0x037C) */ #define BIT_TXHCI_EN BIT(26) #define BIT_TXHCI_IDLE BIT(25) #define BIT_DMA_PRI_EN BIT(24) #define BIT_PCIE_FWCMDQ_FLAG BIT(14) #define BIT_SHIFT_FWCMDQ_DESC_MODE 12 #define BIT_MASK_FWCMDQ_DESC_MODE 0x3 #define BIT_FWCMDQ_DESC_MODE(x) \ (((x) & BIT_MASK_FWCMDQ_DESC_MODE) << BIT_SHIFT_FWCMDQ_DESC_MODE) #define BITS_FWCMDQ_DESC_MODE \ (BIT_MASK_FWCMDQ_DESC_MODE << BIT_SHIFT_FWCMDQ_DESC_MODE) #define BIT_CLEAR_FWCMDQ_DESC_MODE(x) ((x) & (~BITS_FWCMDQ_DESC_MODE)) #define BIT_GET_FWCMDQ_DESC_MODE(x) \ (((x) >> BIT_SHIFT_FWCMDQ_DESC_MODE) & BIT_MASK_FWCMDQ_DESC_MODE) #define BIT_SET_FWCMDQ_DESC_MODE(x, v) \ (BIT_CLEAR_FWCMDQ_DESC_MODE(x) | BIT_FWCMDQ_DESC_MODE(v)) #define BIT_SHIFT_FWCMDQ_DESC_NUM 0 #define BIT_MASK_FWCMDQ_DESC_NUM 0xfff #define BIT_FWCMDQ_DESC_NUM(x) \ (((x) & BIT_MASK_FWCMDQ_DESC_NUM) << BIT_SHIFT_FWCMDQ_DESC_NUM) #define BITS_FWCMDQ_DESC_NUM \ (BIT_MASK_FWCMDQ_DESC_NUM << BIT_SHIFT_FWCMDQ_DESC_NUM) #define BIT_CLEAR_FWCMDQ_DESC_NUM(x) ((x) & (~BITS_FWCMDQ_DESC_NUM)) #define BIT_GET_FWCMDQ_DESC_NUM(x) \ (((x) >> BIT_SHIFT_FWCMDQ_DESC_NUM) & BIT_MASK_FWCMDQ_DESC_NUM) #define BIT_SET_FWCMDQ_DESC_NUM(x, v) \ (BIT_CLEAR_FWCMDQ_DESC_NUM(x) | BIT_FWCMDQ_DESC_NUM(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ #define BIT_PCIE_MGQ_FLAG BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ #define BIT_HCI_MGQ_FLAG BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ #define BIT_SHIFT_MGQ_DESC_MODE 12 #define BIT_MASK_MGQ_DESC_MODE 0x3 #define BIT_MGQ_DESC_MODE(x) \ (((x) & BIT_MASK_MGQ_DESC_MODE) << BIT_SHIFT_MGQ_DESC_MODE) #define BITS_MGQ_DESC_MODE (BIT_MASK_MGQ_DESC_MODE << BIT_SHIFT_MGQ_DESC_MODE) #define BIT_CLEAR_MGQ_DESC_MODE(x) ((x) & (~BITS_MGQ_DESC_MODE)) #define BIT_GET_MGQ_DESC_MODE(x) \ (((x) >> BIT_SHIFT_MGQ_DESC_MODE) & BIT_MASK_MGQ_DESC_MODE) #define BIT_SET_MGQ_DESC_MODE(x, v) \ (BIT_CLEAR_MGQ_DESC_MODE(x) | BIT_MGQ_DESC_MODE(v)) #define BIT_SHIFT_MGQ_DESC_NUM 0 #define BIT_MASK_MGQ_DESC_NUM 0xfff #define BIT_MGQ_DESC_NUM(x) \ (((x) & BIT_MASK_MGQ_DESC_NUM) << BIT_SHIFT_MGQ_DESC_NUM) #define BITS_MGQ_DESC_NUM (BIT_MASK_MGQ_DESC_NUM << BIT_SHIFT_MGQ_DESC_NUM) #define BIT_CLEAR_MGQ_DESC_NUM(x) ((x) & (~BITS_MGQ_DESC_NUM)) #define BIT_GET_MGQ_DESC_NUM(x) \ (((x) >> BIT_SHIFT_MGQ_DESC_NUM) & BIT_MASK_MGQ_DESC_NUM) #define BIT_SET_MGQ_DESC_NUM(x, v) \ (BIT_CLEAR_MGQ_DESC_NUM(x) | BIT_MGQ_DESC_NUM(v)) /* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ #define BIT_SYS_32_64 BIT(15) #define BIT_SHIFT_BCNQ_DESC_MODE 13 #define BIT_MASK_BCNQ_DESC_MODE 0x3 #define BIT_BCNQ_DESC_MODE(x) \ (((x) & BIT_MASK_BCNQ_DESC_MODE) << BIT_SHIFT_BCNQ_DESC_MODE) #define BITS_BCNQ_DESC_MODE \ (BIT_MASK_BCNQ_DESC_MODE << BIT_SHIFT_BCNQ_DESC_MODE) #define BIT_CLEAR_BCNQ_DESC_MODE(x) ((x) & (~BITS_BCNQ_DESC_MODE)) #define BIT_GET_BCNQ_DESC_MODE(x) \ (((x) >> BIT_SHIFT_BCNQ_DESC_MODE) & BIT_MASK_BCNQ_DESC_MODE) #define BIT_SET_BCNQ_DESC_MODE(x, v) \ (BIT_CLEAR_BCNQ_DESC_MODE(x) | BIT_BCNQ_DESC_MODE(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ #define BIT_PCIE_BCNQ_FLAG BIT(12) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ #define BIT_HCI_BCNQ_FLAG BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ #define BIT_SHIFT_RXQ_DESC_NUM 0 #define BIT_MASK_RXQ_DESC_NUM 0xfff #define BIT_RXQ_DESC_NUM(x) \ (((x) & BIT_MASK_RXQ_DESC_NUM) << BIT_SHIFT_RXQ_DESC_NUM) #define BITS_RXQ_DESC_NUM (BIT_MASK_RXQ_DESC_NUM << BIT_SHIFT_RXQ_DESC_NUM) #define BIT_CLEAR_RXQ_DESC_NUM(x) ((x) & (~BITS_RXQ_DESC_NUM)) #define BIT_GET_RXQ_DESC_NUM(x) \ (((x) >> BIT_SHIFT_RXQ_DESC_NUM) & BIT_MASK_RXQ_DESC_NUM) #define BIT_SET_RXQ_DESC_NUM(x, v) \ (BIT_CLEAR_RXQ_DESC_NUM(x) | BIT_RXQ_DESC_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH0_ACH1_TXBD_NUM (Offset 0x0384) */ #define BIT_PCIE_ACH1_FLAG_V1 BIT(30) #define BIT_SHIFT_ACH1_DESC_MODE_V1 28 #define BIT_MASK_ACH1_DESC_MODE_V1 0x3 #define BIT_ACH1_DESC_MODE_V1(x) \ (((x) & BIT_MASK_ACH1_DESC_MODE_V1) << BIT_SHIFT_ACH1_DESC_MODE_V1) #define BITS_ACH1_DESC_MODE_V1 \ (BIT_MASK_ACH1_DESC_MODE_V1 << BIT_SHIFT_ACH1_DESC_MODE_V1) #define BIT_CLEAR_ACH1_DESC_MODE_V1(x) ((x) & (~BITS_ACH1_DESC_MODE_V1)) #define BIT_GET_ACH1_DESC_MODE_V1(x) \ (((x) >> BIT_SHIFT_ACH1_DESC_MODE_V1) & BIT_MASK_ACH1_DESC_MODE_V1) #define BIT_SET_ACH1_DESC_MODE_V1(x, v) \ (BIT_CLEAR_ACH1_DESC_MODE_V1(x) | BIT_ACH1_DESC_MODE_V1(v)) #define BIT_SHIFT_ACH1_DESC_NUM_V1 16 #define BIT_MASK_ACH1_DESC_NUM_V1 0xfff #define BIT_ACH1_DESC_NUM_V1(x) \ (((x) & BIT_MASK_ACH1_DESC_NUM_V1) << BIT_SHIFT_ACH1_DESC_NUM_V1) #define BITS_ACH1_DESC_NUM_V1 \ (BIT_MASK_ACH1_DESC_NUM_V1 << BIT_SHIFT_ACH1_DESC_NUM_V1) #define BIT_CLEAR_ACH1_DESC_NUM_V1(x) ((x) & (~BITS_ACH1_DESC_NUM_V1)) #define BIT_GET_ACH1_DESC_NUM_V1(x) \ (((x) >> BIT_SHIFT_ACH1_DESC_NUM_V1) & BIT_MASK_ACH1_DESC_NUM_V1) #define BIT_SET_ACH1_DESC_NUM_V1(x, v) \ (BIT_CLEAR_ACH1_DESC_NUM_V1(x) | BIT_ACH1_DESC_NUM_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ #define BIT_PCIE_VOQ_FLAG BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ #define BIT_HCI_VOQ_FLAG BIT(14) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH0_ACH1_TXBD_NUM (Offset 0x0384) */ #define BIT_PCIE_ACH0_FLAG BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ #define BIT_SHIFT_VOQ_DESC_MODE 12 #define BIT_MASK_VOQ_DESC_MODE 0x3 #define BIT_VOQ_DESC_MODE(x) \ (((x) & BIT_MASK_VOQ_DESC_MODE) << BIT_SHIFT_VOQ_DESC_MODE) #define BITS_VOQ_DESC_MODE (BIT_MASK_VOQ_DESC_MODE << BIT_SHIFT_VOQ_DESC_MODE) #define BIT_CLEAR_VOQ_DESC_MODE(x) ((x) & (~BITS_VOQ_DESC_MODE)) #define BIT_GET_VOQ_DESC_MODE(x) \ (((x) >> BIT_SHIFT_VOQ_DESC_MODE) & BIT_MASK_VOQ_DESC_MODE) #define BIT_SET_VOQ_DESC_MODE(x, v) \ (BIT_CLEAR_VOQ_DESC_MODE(x) | BIT_VOQ_DESC_MODE(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH0_ACH1_TXBD_NUM (Offset 0x0384) */ #define BIT_SHIFT_ACH0_DESC_MODE 12 #define BIT_MASK_ACH0_DESC_MODE 0x3 #define BIT_ACH0_DESC_MODE(x) \ (((x) & BIT_MASK_ACH0_DESC_MODE) << BIT_SHIFT_ACH0_DESC_MODE) #define BITS_ACH0_DESC_MODE \ (BIT_MASK_ACH0_DESC_MODE << BIT_SHIFT_ACH0_DESC_MODE) #define BIT_CLEAR_ACH0_DESC_MODE(x) ((x) & (~BITS_ACH0_DESC_MODE)) #define BIT_GET_ACH0_DESC_MODE(x) \ (((x) >> BIT_SHIFT_ACH0_DESC_MODE) & BIT_MASK_ACH0_DESC_MODE) #define BIT_SET_ACH0_DESC_MODE(x, v) \ (BIT_CLEAR_ACH0_DESC_MODE(x) | BIT_ACH0_DESC_MODE(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ #define BIT_SHIFT_VOQ_DESC_NUM 0 #define BIT_MASK_VOQ_DESC_NUM 0xfff #define BIT_VOQ_DESC_NUM(x) \ (((x) & BIT_MASK_VOQ_DESC_NUM) << BIT_SHIFT_VOQ_DESC_NUM) #define BITS_VOQ_DESC_NUM (BIT_MASK_VOQ_DESC_NUM << BIT_SHIFT_VOQ_DESC_NUM) #define BIT_CLEAR_VOQ_DESC_NUM(x) ((x) & (~BITS_VOQ_DESC_NUM)) #define BIT_GET_VOQ_DESC_NUM(x) \ (((x) >> BIT_SHIFT_VOQ_DESC_NUM) & BIT_MASK_VOQ_DESC_NUM) #define BIT_SET_VOQ_DESC_NUM(x, v) \ (BIT_CLEAR_VOQ_DESC_NUM(x) | BIT_VOQ_DESC_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH0_ACH1_TXBD_NUM (Offset 0x0384) */ #define BIT_SHIFT_ACH0_DESC_NUM 0 #define BIT_MASK_ACH0_DESC_NUM 0xfff #define BIT_ACH0_DESC_NUM(x) \ (((x) & BIT_MASK_ACH0_DESC_NUM) << BIT_SHIFT_ACH0_DESC_NUM) #define BITS_ACH0_DESC_NUM (BIT_MASK_ACH0_DESC_NUM << BIT_SHIFT_ACH0_DESC_NUM) #define BIT_CLEAR_ACH0_DESC_NUM(x) ((x) & (~BITS_ACH0_DESC_NUM)) #define BIT_GET_ACH0_DESC_NUM(x) \ (((x) >> BIT_SHIFT_ACH0_DESC_NUM) & BIT_MASK_ACH0_DESC_NUM) #define BIT_SET_ACH0_DESC_NUM(x, v) \ (BIT_CLEAR_ACH0_DESC_NUM(x) | BIT_ACH0_DESC_NUM(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ #define BIT_PCIE_VIQ_FLAG BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ #define BIT_HCI_VIQ_FLAG BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ #define BIT_SHIFT_VIQ_DESC_MODE 12 #define BIT_MASK_VIQ_DESC_MODE 0x3 #define BIT_VIQ_DESC_MODE(x) \ (((x) & BIT_MASK_VIQ_DESC_MODE) << BIT_SHIFT_VIQ_DESC_MODE) #define BITS_VIQ_DESC_MODE (BIT_MASK_VIQ_DESC_MODE << BIT_SHIFT_VIQ_DESC_MODE) #define BIT_CLEAR_VIQ_DESC_MODE(x) ((x) & (~BITS_VIQ_DESC_MODE)) #define BIT_GET_VIQ_DESC_MODE(x) \ (((x) >> BIT_SHIFT_VIQ_DESC_MODE) & BIT_MASK_VIQ_DESC_MODE) #define BIT_SET_VIQ_DESC_MODE(x, v) \ (BIT_CLEAR_VIQ_DESC_MODE(x) | BIT_VIQ_DESC_MODE(v)) #define BIT_SHIFT_VIQ_DESC_NUM 0 #define BIT_MASK_VIQ_DESC_NUM 0xfff #define BIT_VIQ_DESC_NUM(x) \ (((x) & BIT_MASK_VIQ_DESC_NUM) << BIT_SHIFT_VIQ_DESC_NUM) #define BITS_VIQ_DESC_NUM (BIT_MASK_VIQ_DESC_NUM << BIT_SHIFT_VIQ_DESC_NUM) #define BIT_CLEAR_VIQ_DESC_NUM(x) ((x) & (~BITS_VIQ_DESC_NUM)) #define BIT_GET_VIQ_DESC_NUM(x) \ (((x) >> BIT_SHIFT_VIQ_DESC_NUM) & BIT_MASK_VIQ_DESC_NUM) #define BIT_SET_VIQ_DESC_NUM(x, v) \ (BIT_CLEAR_VIQ_DESC_NUM(x) | BIT_VIQ_DESC_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH2_ACH3_TXBD_NUM (Offset 0x0388) */ #define BIT_PCIE_ACH3_FLAG_V1 BIT(30) #define BIT_SHIFT_ACH3_DESC_MODE_V1 28 #define BIT_MASK_ACH3_DESC_MODE_V1 0x3 #define BIT_ACH3_DESC_MODE_V1(x) \ (((x) & BIT_MASK_ACH3_DESC_MODE_V1) << BIT_SHIFT_ACH3_DESC_MODE_V1) #define BITS_ACH3_DESC_MODE_V1 \ (BIT_MASK_ACH3_DESC_MODE_V1 << BIT_SHIFT_ACH3_DESC_MODE_V1) #define BIT_CLEAR_ACH3_DESC_MODE_V1(x) ((x) & (~BITS_ACH3_DESC_MODE_V1)) #define BIT_GET_ACH3_DESC_MODE_V1(x) \ (((x) >> BIT_SHIFT_ACH3_DESC_MODE_V1) & BIT_MASK_ACH3_DESC_MODE_V1) #define BIT_SET_ACH3_DESC_MODE_V1(x, v) \ (BIT_CLEAR_ACH3_DESC_MODE_V1(x) | BIT_ACH3_DESC_MODE_V1(v)) #define BIT_SHIFT_ACH3_DESC_NUM_V1 16 #define BIT_MASK_ACH3_DESC_NUM_V1 0xfff #define BIT_ACH3_DESC_NUM_V1(x) \ (((x) & BIT_MASK_ACH3_DESC_NUM_V1) << BIT_SHIFT_ACH3_DESC_NUM_V1) #define BITS_ACH3_DESC_NUM_V1 \ (BIT_MASK_ACH3_DESC_NUM_V1 << BIT_SHIFT_ACH3_DESC_NUM_V1) #define BIT_CLEAR_ACH3_DESC_NUM_V1(x) ((x) & (~BITS_ACH3_DESC_NUM_V1)) #define BIT_GET_ACH3_DESC_NUM_V1(x) \ (((x) >> BIT_SHIFT_ACH3_DESC_NUM_V1) & BIT_MASK_ACH3_DESC_NUM_V1) #define BIT_SET_ACH3_DESC_NUM_V1(x, v) \ (BIT_CLEAR_ACH3_DESC_NUM_V1(x) | BIT_ACH3_DESC_NUM_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ #define BIT_PCIE_BEQ_FLAG BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ #define BIT_HCI_BEQ_FLAG BIT(14) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH2_ACH3_TXBD_NUM (Offset 0x0388) */ #define BIT_PCIE_ACH2_FLAG BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ #define BIT_SHIFT_BEQ_DESC_MODE 12 #define BIT_MASK_BEQ_DESC_MODE 0x3 #define BIT_BEQ_DESC_MODE(x) \ (((x) & BIT_MASK_BEQ_DESC_MODE) << BIT_SHIFT_BEQ_DESC_MODE) #define BITS_BEQ_DESC_MODE (BIT_MASK_BEQ_DESC_MODE << BIT_SHIFT_BEQ_DESC_MODE) #define BIT_CLEAR_BEQ_DESC_MODE(x) ((x) & (~BITS_BEQ_DESC_MODE)) #define BIT_GET_BEQ_DESC_MODE(x) \ (((x) >> BIT_SHIFT_BEQ_DESC_MODE) & BIT_MASK_BEQ_DESC_MODE) #define BIT_SET_BEQ_DESC_MODE(x, v) \ (BIT_CLEAR_BEQ_DESC_MODE(x) | BIT_BEQ_DESC_MODE(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH2_ACH3_TXBD_NUM (Offset 0x0388) */ #define BIT_SHIFT_ACH2_DESC_MODE 12 #define BIT_MASK_ACH2_DESC_MODE 0x3 #define BIT_ACH2_DESC_MODE(x) \ (((x) & BIT_MASK_ACH2_DESC_MODE) << BIT_SHIFT_ACH2_DESC_MODE) #define BITS_ACH2_DESC_MODE \ (BIT_MASK_ACH2_DESC_MODE << BIT_SHIFT_ACH2_DESC_MODE) #define BIT_CLEAR_ACH2_DESC_MODE(x) ((x) & (~BITS_ACH2_DESC_MODE)) #define BIT_GET_ACH2_DESC_MODE(x) \ (((x) >> BIT_SHIFT_ACH2_DESC_MODE) & BIT_MASK_ACH2_DESC_MODE) #define BIT_SET_ACH2_DESC_MODE(x, v) \ (BIT_CLEAR_ACH2_DESC_MODE(x) | BIT_ACH2_DESC_MODE(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ #define BIT_SHIFT_BEQ_DESC_NUM 0 #define BIT_MASK_BEQ_DESC_NUM 0xfff #define BIT_BEQ_DESC_NUM(x) \ (((x) & BIT_MASK_BEQ_DESC_NUM) << BIT_SHIFT_BEQ_DESC_NUM) #define BITS_BEQ_DESC_NUM (BIT_MASK_BEQ_DESC_NUM << BIT_SHIFT_BEQ_DESC_NUM) #define BIT_CLEAR_BEQ_DESC_NUM(x) ((x) & (~BITS_BEQ_DESC_NUM)) #define BIT_GET_BEQ_DESC_NUM(x) \ (((x) >> BIT_SHIFT_BEQ_DESC_NUM) & BIT_MASK_BEQ_DESC_NUM) #define BIT_SET_BEQ_DESC_NUM(x, v) \ (BIT_CLEAR_BEQ_DESC_NUM(x) | BIT_BEQ_DESC_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH2_ACH3_TXBD_NUM (Offset 0x0388) */ #define BIT_SHIFT_ACH2_DESC_NUM 0 #define BIT_MASK_ACH2_DESC_NUM 0xfff #define BIT_ACH2_DESC_NUM(x) \ (((x) & BIT_MASK_ACH2_DESC_NUM) << BIT_SHIFT_ACH2_DESC_NUM) #define BITS_ACH2_DESC_NUM (BIT_MASK_ACH2_DESC_NUM << BIT_SHIFT_ACH2_DESC_NUM) #define BIT_CLEAR_ACH2_DESC_NUM(x) ((x) & (~BITS_ACH2_DESC_NUM)) #define BIT_GET_ACH2_DESC_NUM(x) \ (((x) >> BIT_SHIFT_ACH2_DESC_NUM) & BIT_MASK_ACH2_DESC_NUM) #define BIT_SET_ACH2_DESC_NUM(x, v) \ (BIT_CLEAR_ACH2_DESC_NUM(x) | BIT_ACH2_DESC_NUM(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ #define BIT_PCIE_BKQ_FLAG BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ #define BIT_HCI_BKQ_FLAG BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ #define BIT_SHIFT_BKQ_DESC_MODE 12 #define BIT_MASK_BKQ_DESC_MODE 0x3 #define BIT_BKQ_DESC_MODE(x) \ (((x) & BIT_MASK_BKQ_DESC_MODE) << BIT_SHIFT_BKQ_DESC_MODE) #define BITS_BKQ_DESC_MODE (BIT_MASK_BKQ_DESC_MODE << BIT_SHIFT_BKQ_DESC_MODE) #define BIT_CLEAR_BKQ_DESC_MODE(x) ((x) & (~BITS_BKQ_DESC_MODE)) #define BIT_GET_BKQ_DESC_MODE(x) \ (((x) >> BIT_SHIFT_BKQ_DESC_MODE) & BIT_MASK_BKQ_DESC_MODE) #define BIT_SET_BKQ_DESC_MODE(x, v) \ (BIT_CLEAR_BKQ_DESC_MODE(x) | BIT_BKQ_DESC_MODE(v)) #define BIT_SHIFT_BKQ_DESC_NUM 0 #define BIT_MASK_BKQ_DESC_NUM 0xfff #define BIT_BKQ_DESC_NUM(x) \ (((x) & BIT_MASK_BKQ_DESC_NUM) << BIT_SHIFT_BKQ_DESC_NUM) #define BITS_BKQ_DESC_NUM (BIT_MASK_BKQ_DESC_NUM << BIT_SHIFT_BKQ_DESC_NUM) #define BIT_CLEAR_BKQ_DESC_NUM(x) ((x) & (~BITS_BKQ_DESC_NUM)) #define BIT_GET_BKQ_DESC_NUM(x) \ (((x) >> BIT_SHIFT_BKQ_DESC_NUM) & BIT_MASK_BKQ_DESC_NUM) #define BIT_SET_BKQ_DESC_NUM(x, v) \ (BIT_CLEAR_BKQ_DESC_NUM(x) | BIT_BKQ_DESC_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI0Q_HI1Q_TXBD_NUM (Offset 0x038C) */ #define BIT_P0HI1Q_FLAG BIT(30) #define BIT_SHIFT_P0HI1Q_DESC_MODE 28 #define BIT_MASK_P0HI1Q_DESC_MODE 0x3 #define BIT_P0HI1Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI1Q_DESC_MODE) << BIT_SHIFT_P0HI1Q_DESC_MODE) #define BITS_P0HI1Q_DESC_MODE \ (BIT_MASK_P0HI1Q_DESC_MODE << BIT_SHIFT_P0HI1Q_DESC_MODE) #define BIT_CLEAR_P0HI1Q_DESC_MODE(x) ((x) & (~BITS_P0HI1Q_DESC_MODE)) #define BIT_GET_P0HI1Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI1Q_DESC_MODE) & BIT_MASK_P0HI1Q_DESC_MODE) #define BIT_SET_P0HI1Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI1Q_DESC_MODE(x) | BIT_P0HI1Q_DESC_MODE(v)) #define BIT_SHIFT_P0HI1Q_DESC_NUM 16 #define BIT_MASK_P0HI1Q_DESC_NUM 0xfff #define BIT_P0HI1Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI1Q_DESC_NUM) << BIT_SHIFT_P0HI1Q_DESC_NUM) #define BITS_P0HI1Q_DESC_NUM \ (BIT_MASK_P0HI1Q_DESC_NUM << BIT_SHIFT_P0HI1Q_DESC_NUM) #define BIT_CLEAR_P0HI1Q_DESC_NUM(x) ((x) & (~BITS_P0HI1Q_DESC_NUM)) #define BIT_GET_P0HI1Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI1Q_DESC_NUM) & BIT_MASK_P0HI1Q_DESC_NUM) #define BIT_SET_P0HI1Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI1Q_DESC_NUM(x) | BIT_P0HI1Q_DESC_NUM(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI0Q_TXBD_NUM (Offset 0x038C) */ #define BIT_HI0Q_FLAG BIT(14) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI0Q_HI1Q_TXBD_NUM (Offset 0x038C) */ #define BIT_P0HI0Q_FLAG BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI0Q_TXBD_NUM (Offset 0x038C) */ #define BIT_SHIFT_HI0Q_DESC_MODE 12 #define BIT_MASK_HI0Q_DESC_MODE 0x3 #define BIT_HI0Q_DESC_MODE(x) \ (((x) & BIT_MASK_HI0Q_DESC_MODE) << BIT_SHIFT_HI0Q_DESC_MODE) #define BITS_HI0Q_DESC_MODE \ (BIT_MASK_HI0Q_DESC_MODE << BIT_SHIFT_HI0Q_DESC_MODE) #define BIT_CLEAR_HI0Q_DESC_MODE(x) ((x) & (~BITS_HI0Q_DESC_MODE)) #define BIT_GET_HI0Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_HI0Q_DESC_MODE) & BIT_MASK_HI0Q_DESC_MODE) #define BIT_SET_HI0Q_DESC_MODE(x, v) \ (BIT_CLEAR_HI0Q_DESC_MODE(x) | BIT_HI0Q_DESC_MODE(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI0Q_HI1Q_TXBD_NUM (Offset 0x038C) */ #define BIT_SHIFT_P0HI0Q_DESC_MODE 12 #define BIT_MASK_P0HI0Q_DESC_MODE 0x3 #define BIT_P0HI0Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI0Q_DESC_MODE) << BIT_SHIFT_P0HI0Q_DESC_MODE) #define BITS_P0HI0Q_DESC_MODE \ (BIT_MASK_P0HI0Q_DESC_MODE << BIT_SHIFT_P0HI0Q_DESC_MODE) #define BIT_CLEAR_P0HI0Q_DESC_MODE(x) ((x) & (~BITS_P0HI0Q_DESC_MODE)) #define BIT_GET_P0HI0Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI0Q_DESC_MODE) & BIT_MASK_P0HI0Q_DESC_MODE) #define BIT_SET_P0HI0Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI0Q_DESC_MODE(x) | BIT_P0HI0Q_DESC_MODE(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI0Q_TXBD_NUM (Offset 0x038C) */ #define BIT_SHIFT_HI0Q_DESC_NUM 0 #define BIT_MASK_HI0Q_DESC_NUM 0xfff #define BIT_HI0Q_DESC_NUM(x) \ (((x) & BIT_MASK_HI0Q_DESC_NUM) << BIT_SHIFT_HI0Q_DESC_NUM) #define BITS_HI0Q_DESC_NUM (BIT_MASK_HI0Q_DESC_NUM << BIT_SHIFT_HI0Q_DESC_NUM) #define BIT_CLEAR_HI0Q_DESC_NUM(x) ((x) & (~BITS_HI0Q_DESC_NUM)) #define BIT_GET_HI0Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_HI0Q_DESC_NUM) & BIT_MASK_HI0Q_DESC_NUM) #define BIT_SET_HI0Q_DESC_NUM(x, v) \ (BIT_CLEAR_HI0Q_DESC_NUM(x) | BIT_HI0Q_DESC_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI0Q_HI1Q_TXBD_NUM (Offset 0x038C) */ #define BIT_SHIFT_P0HI0Q_DESC_NUM 0 #define BIT_MASK_P0HI0Q_DESC_NUM 0xfff #define BIT_P0HI0Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI0Q_DESC_NUM) << BIT_SHIFT_P0HI0Q_DESC_NUM) #define BITS_P0HI0Q_DESC_NUM \ (BIT_MASK_P0HI0Q_DESC_NUM << BIT_SHIFT_P0HI0Q_DESC_NUM) #define BIT_CLEAR_P0HI0Q_DESC_NUM(x) ((x) & (~BITS_P0HI0Q_DESC_NUM)) #define BIT_GET_P0HI0Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI0Q_DESC_NUM) & BIT_MASK_P0HI0Q_DESC_NUM) #define BIT_SET_P0HI0Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI0Q_DESC_NUM(x) | BIT_P0HI0Q_DESC_NUM(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI1Q_TXBD_NUM (Offset 0x038E) */ #define BIT_HI1Q_FLAG BIT(14) #define BIT_SHIFT_HI1Q_DESC_MODE 12 #define BIT_MASK_HI1Q_DESC_MODE 0x3 #define BIT_HI1Q_DESC_MODE(x) \ (((x) & BIT_MASK_HI1Q_DESC_MODE) << BIT_SHIFT_HI1Q_DESC_MODE) #define BITS_HI1Q_DESC_MODE \ (BIT_MASK_HI1Q_DESC_MODE << BIT_SHIFT_HI1Q_DESC_MODE) #define BIT_CLEAR_HI1Q_DESC_MODE(x) ((x) & (~BITS_HI1Q_DESC_MODE)) #define BIT_GET_HI1Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_HI1Q_DESC_MODE) & BIT_MASK_HI1Q_DESC_MODE) #define BIT_SET_HI1Q_DESC_MODE(x, v) \ (BIT_CLEAR_HI1Q_DESC_MODE(x) | BIT_HI1Q_DESC_MODE(v)) #define BIT_SHIFT_HI1Q_DESC_NUM 0 #define BIT_MASK_HI1Q_DESC_NUM 0xfff #define BIT_HI1Q_DESC_NUM(x) \ (((x) & BIT_MASK_HI1Q_DESC_NUM) << BIT_SHIFT_HI1Q_DESC_NUM) #define BITS_HI1Q_DESC_NUM (BIT_MASK_HI1Q_DESC_NUM << BIT_SHIFT_HI1Q_DESC_NUM) #define BIT_CLEAR_HI1Q_DESC_NUM(x) ((x) & (~BITS_HI1Q_DESC_NUM)) #define BIT_GET_HI1Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_HI1Q_DESC_NUM) & BIT_MASK_HI1Q_DESC_NUM) #define BIT_SET_HI1Q_DESC_NUM(x, v) \ (BIT_CLEAR_HI1Q_DESC_NUM(x) | BIT_HI1Q_DESC_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI2Q_HI3Q_TXBD_NUM (Offset 0x0390) */ #define BIT_P0HI3Q_FLAG BIT(30) #define BIT_SHIFT_P0HI3Q_DESC_MODE 28 #define BIT_MASK_P0HI3Q_DESC_MODE 0x3 #define BIT_P0HI3Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI3Q_DESC_MODE) << BIT_SHIFT_P0HI3Q_DESC_MODE) #define BITS_P0HI3Q_DESC_MODE \ (BIT_MASK_P0HI3Q_DESC_MODE << BIT_SHIFT_P0HI3Q_DESC_MODE) #define BIT_CLEAR_P0HI3Q_DESC_MODE(x) ((x) & (~BITS_P0HI3Q_DESC_MODE)) #define BIT_GET_P0HI3Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI3Q_DESC_MODE) & BIT_MASK_P0HI3Q_DESC_MODE) #define BIT_SET_P0HI3Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI3Q_DESC_MODE(x) | BIT_P0HI3Q_DESC_MODE(v)) #define BIT_SHIFT_P0HI3Q_DESC_NUM 16 #define BIT_MASK_P0HI3Q_DESC_NUM 0xfff #define BIT_P0HI3Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI3Q_DESC_NUM) << BIT_SHIFT_P0HI3Q_DESC_NUM) #define BITS_P0HI3Q_DESC_NUM \ (BIT_MASK_P0HI3Q_DESC_NUM << BIT_SHIFT_P0HI3Q_DESC_NUM) #define BIT_CLEAR_P0HI3Q_DESC_NUM(x) ((x) & (~BITS_P0HI3Q_DESC_NUM)) #define BIT_GET_P0HI3Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI3Q_DESC_NUM) & BIT_MASK_P0HI3Q_DESC_NUM) #define BIT_SET_P0HI3Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI3Q_DESC_NUM(x) | BIT_P0HI3Q_DESC_NUM(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI2Q_TXBD_NUM (Offset 0x0390) */ #define BIT_HI2Q_FLAG BIT(14) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI2Q_HI3Q_TXBD_NUM (Offset 0x0390) */ #define BIT_P0HI2Q_FLAG BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI2Q_TXBD_NUM (Offset 0x0390) */ #define BIT_SHIFT_HI2Q_DESC_MODE 12 #define BIT_MASK_HI2Q_DESC_MODE 0x3 #define BIT_HI2Q_DESC_MODE(x) \ (((x) & BIT_MASK_HI2Q_DESC_MODE) << BIT_SHIFT_HI2Q_DESC_MODE) #define BITS_HI2Q_DESC_MODE \ (BIT_MASK_HI2Q_DESC_MODE << BIT_SHIFT_HI2Q_DESC_MODE) #define BIT_CLEAR_HI2Q_DESC_MODE(x) ((x) & (~BITS_HI2Q_DESC_MODE)) #define BIT_GET_HI2Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_HI2Q_DESC_MODE) & BIT_MASK_HI2Q_DESC_MODE) #define BIT_SET_HI2Q_DESC_MODE(x, v) \ (BIT_CLEAR_HI2Q_DESC_MODE(x) | BIT_HI2Q_DESC_MODE(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI2Q_HI3Q_TXBD_NUM (Offset 0x0390) */ #define BIT_SHIFT_P0HI2Q_DESC_MODE 12 #define BIT_MASK_P0HI2Q_DESC_MODE 0x3 #define BIT_P0HI2Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI2Q_DESC_MODE) << BIT_SHIFT_P0HI2Q_DESC_MODE) #define BITS_P0HI2Q_DESC_MODE \ (BIT_MASK_P0HI2Q_DESC_MODE << BIT_SHIFT_P0HI2Q_DESC_MODE) #define BIT_CLEAR_P0HI2Q_DESC_MODE(x) ((x) & (~BITS_P0HI2Q_DESC_MODE)) #define BIT_GET_P0HI2Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI2Q_DESC_MODE) & BIT_MASK_P0HI2Q_DESC_MODE) #define BIT_SET_P0HI2Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI2Q_DESC_MODE(x) | BIT_P0HI2Q_DESC_MODE(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI2Q_TXBD_NUM (Offset 0x0390) */ #define BIT_SHIFT_HI2Q_DESC_NUM 0 #define BIT_MASK_HI2Q_DESC_NUM 0xfff #define BIT_HI2Q_DESC_NUM(x) \ (((x) & BIT_MASK_HI2Q_DESC_NUM) << BIT_SHIFT_HI2Q_DESC_NUM) #define BITS_HI2Q_DESC_NUM (BIT_MASK_HI2Q_DESC_NUM << BIT_SHIFT_HI2Q_DESC_NUM) #define BIT_CLEAR_HI2Q_DESC_NUM(x) ((x) & (~BITS_HI2Q_DESC_NUM)) #define BIT_GET_HI2Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_HI2Q_DESC_NUM) & BIT_MASK_HI2Q_DESC_NUM) #define BIT_SET_HI2Q_DESC_NUM(x, v) \ (BIT_CLEAR_HI2Q_DESC_NUM(x) | BIT_HI2Q_DESC_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI2Q_HI3Q_TXBD_NUM (Offset 0x0390) */ #define BIT_SHIFT_P0HI2Q_DESC_NUM 0 #define BIT_MASK_P0HI2Q_DESC_NUM 0xfff #define BIT_P0HI2Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI2Q_DESC_NUM) << BIT_SHIFT_P0HI2Q_DESC_NUM) #define BITS_P0HI2Q_DESC_NUM \ (BIT_MASK_P0HI2Q_DESC_NUM << BIT_SHIFT_P0HI2Q_DESC_NUM) #define BIT_CLEAR_P0HI2Q_DESC_NUM(x) ((x) & (~BITS_P0HI2Q_DESC_NUM)) #define BIT_GET_P0HI2Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI2Q_DESC_NUM) & BIT_MASK_P0HI2Q_DESC_NUM) #define BIT_SET_P0HI2Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI2Q_DESC_NUM(x) | BIT_P0HI2Q_DESC_NUM(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI3Q_TXBD_NUM (Offset 0x0392) */ #define BIT_HI3Q_FLAG BIT(14) #define BIT_SHIFT_HI3Q_DESC_MODE 12 #define BIT_MASK_HI3Q_DESC_MODE 0x3 #define BIT_HI3Q_DESC_MODE(x) \ (((x) & BIT_MASK_HI3Q_DESC_MODE) << BIT_SHIFT_HI3Q_DESC_MODE) #define BITS_HI3Q_DESC_MODE \ (BIT_MASK_HI3Q_DESC_MODE << BIT_SHIFT_HI3Q_DESC_MODE) #define BIT_CLEAR_HI3Q_DESC_MODE(x) ((x) & (~BITS_HI3Q_DESC_MODE)) #define BIT_GET_HI3Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_HI3Q_DESC_MODE) & BIT_MASK_HI3Q_DESC_MODE) #define BIT_SET_HI3Q_DESC_MODE(x, v) \ (BIT_CLEAR_HI3Q_DESC_MODE(x) | BIT_HI3Q_DESC_MODE(v)) #define BIT_SHIFT_HI3Q_DESC_NUM 0 #define BIT_MASK_HI3Q_DESC_NUM 0xfff #define BIT_HI3Q_DESC_NUM(x) \ (((x) & BIT_MASK_HI3Q_DESC_NUM) << BIT_SHIFT_HI3Q_DESC_NUM) #define BITS_HI3Q_DESC_NUM (BIT_MASK_HI3Q_DESC_NUM << BIT_SHIFT_HI3Q_DESC_NUM) #define BIT_CLEAR_HI3Q_DESC_NUM(x) ((x) & (~BITS_HI3Q_DESC_NUM)) #define BIT_GET_HI3Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_HI3Q_DESC_NUM) & BIT_MASK_HI3Q_DESC_NUM) #define BIT_SET_HI3Q_DESC_NUM(x, v) \ (BIT_CLEAR_HI3Q_DESC_NUM(x) | BIT_HI3Q_DESC_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI4Q_HI5Q_TXBD_NUM (Offset 0x0394) */ #define BIT_P0HI5Q_FLAG BIT(30) #define BIT_SHIFT_P0HI5Q_DESC_MODE 28 #define BIT_MASK_P0HI5Q_DESC_MODE 0x3 #define BIT_P0HI5Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI5Q_DESC_MODE) << BIT_SHIFT_P0HI5Q_DESC_MODE) #define BITS_P0HI5Q_DESC_MODE \ (BIT_MASK_P0HI5Q_DESC_MODE << BIT_SHIFT_P0HI5Q_DESC_MODE) #define BIT_CLEAR_P0HI5Q_DESC_MODE(x) ((x) & (~BITS_P0HI5Q_DESC_MODE)) #define BIT_GET_P0HI5Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI5Q_DESC_MODE) & BIT_MASK_P0HI5Q_DESC_MODE) #define BIT_SET_P0HI5Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI5Q_DESC_MODE(x) | BIT_P0HI5Q_DESC_MODE(v)) #define BIT_SHIFT_P0HI5Q_DESC_NUM 16 #define BIT_MASK_P0HI5Q_DESC_NUM 0xfff #define BIT_P0HI5Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI5Q_DESC_NUM) << BIT_SHIFT_P0HI5Q_DESC_NUM) #define BITS_P0HI5Q_DESC_NUM \ (BIT_MASK_P0HI5Q_DESC_NUM << BIT_SHIFT_P0HI5Q_DESC_NUM) #define BIT_CLEAR_P0HI5Q_DESC_NUM(x) ((x) & (~BITS_P0HI5Q_DESC_NUM)) #define BIT_GET_P0HI5Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI5Q_DESC_NUM) & BIT_MASK_P0HI5Q_DESC_NUM) #define BIT_SET_P0HI5Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI5Q_DESC_NUM(x) | BIT_P0HI5Q_DESC_NUM(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI4Q_TXBD_NUM (Offset 0x0394) */ #define BIT_HI4Q_FLAG BIT(14) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI4Q_HI5Q_TXBD_NUM (Offset 0x0394) */ #define BIT_P0HI4Q_FLAG BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI4Q_TXBD_NUM (Offset 0x0394) */ #define BIT_SHIFT_HI4Q_DESC_MODE 12 #define BIT_MASK_HI4Q_DESC_MODE 0x3 #define BIT_HI4Q_DESC_MODE(x) \ (((x) & BIT_MASK_HI4Q_DESC_MODE) << BIT_SHIFT_HI4Q_DESC_MODE) #define BITS_HI4Q_DESC_MODE \ (BIT_MASK_HI4Q_DESC_MODE << BIT_SHIFT_HI4Q_DESC_MODE) #define BIT_CLEAR_HI4Q_DESC_MODE(x) ((x) & (~BITS_HI4Q_DESC_MODE)) #define BIT_GET_HI4Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_HI4Q_DESC_MODE) & BIT_MASK_HI4Q_DESC_MODE) #define BIT_SET_HI4Q_DESC_MODE(x, v) \ (BIT_CLEAR_HI4Q_DESC_MODE(x) | BIT_HI4Q_DESC_MODE(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI4Q_HI5Q_TXBD_NUM (Offset 0x0394) */ #define BIT_SHIFT_P0HI4Q_DESC_MODE 12 #define BIT_MASK_P0HI4Q_DESC_MODE 0x3 #define BIT_P0HI4Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI4Q_DESC_MODE) << BIT_SHIFT_P0HI4Q_DESC_MODE) #define BITS_P0HI4Q_DESC_MODE \ (BIT_MASK_P0HI4Q_DESC_MODE << BIT_SHIFT_P0HI4Q_DESC_MODE) #define BIT_CLEAR_P0HI4Q_DESC_MODE(x) ((x) & (~BITS_P0HI4Q_DESC_MODE)) #define BIT_GET_P0HI4Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI4Q_DESC_MODE) & BIT_MASK_P0HI4Q_DESC_MODE) #define BIT_SET_P0HI4Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI4Q_DESC_MODE(x) | BIT_P0HI4Q_DESC_MODE(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI4Q_TXBD_NUM (Offset 0x0394) */ #define BIT_SHIFT_HI4Q_DESC_NUM 0 #define BIT_MASK_HI4Q_DESC_NUM 0xfff #define BIT_HI4Q_DESC_NUM(x) \ (((x) & BIT_MASK_HI4Q_DESC_NUM) << BIT_SHIFT_HI4Q_DESC_NUM) #define BITS_HI4Q_DESC_NUM (BIT_MASK_HI4Q_DESC_NUM << BIT_SHIFT_HI4Q_DESC_NUM) #define BIT_CLEAR_HI4Q_DESC_NUM(x) ((x) & (~BITS_HI4Q_DESC_NUM)) #define BIT_GET_HI4Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_HI4Q_DESC_NUM) & BIT_MASK_HI4Q_DESC_NUM) #define BIT_SET_HI4Q_DESC_NUM(x, v) \ (BIT_CLEAR_HI4Q_DESC_NUM(x) | BIT_HI4Q_DESC_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI4Q_HI5Q_TXBD_NUM (Offset 0x0394) */ #define BIT_SHIFT_P0HI4Q_DESC_NUM 0 #define BIT_MASK_P0HI4Q_DESC_NUM 0xfff #define BIT_P0HI4Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI4Q_DESC_NUM) << BIT_SHIFT_P0HI4Q_DESC_NUM) #define BITS_P0HI4Q_DESC_NUM \ (BIT_MASK_P0HI4Q_DESC_NUM << BIT_SHIFT_P0HI4Q_DESC_NUM) #define BIT_CLEAR_P0HI4Q_DESC_NUM(x) ((x) & (~BITS_P0HI4Q_DESC_NUM)) #define BIT_GET_P0HI4Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI4Q_DESC_NUM) & BIT_MASK_P0HI4Q_DESC_NUM) #define BIT_SET_P0HI4Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI4Q_DESC_NUM(x) | BIT_P0HI4Q_DESC_NUM(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI5Q_TXBD_NUM (Offset 0x0396) */ #define BIT_HI5Q_FLAG BIT(14) #define BIT_SHIFT_HI5Q_DESC_MODE 12 #define BIT_MASK_HI5Q_DESC_MODE 0x3 #define BIT_HI5Q_DESC_MODE(x) \ (((x) & BIT_MASK_HI5Q_DESC_MODE) << BIT_SHIFT_HI5Q_DESC_MODE) #define BITS_HI5Q_DESC_MODE \ (BIT_MASK_HI5Q_DESC_MODE << BIT_SHIFT_HI5Q_DESC_MODE) #define BIT_CLEAR_HI5Q_DESC_MODE(x) ((x) & (~BITS_HI5Q_DESC_MODE)) #define BIT_GET_HI5Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_HI5Q_DESC_MODE) & BIT_MASK_HI5Q_DESC_MODE) #define BIT_SET_HI5Q_DESC_MODE(x, v) \ (BIT_CLEAR_HI5Q_DESC_MODE(x) | BIT_HI5Q_DESC_MODE(v)) #define BIT_SHIFT_HI5Q_DESC_NUM 0 #define BIT_MASK_HI5Q_DESC_NUM 0xfff #define BIT_HI5Q_DESC_NUM(x) \ (((x) & BIT_MASK_HI5Q_DESC_NUM) << BIT_SHIFT_HI5Q_DESC_NUM) #define BITS_HI5Q_DESC_NUM (BIT_MASK_HI5Q_DESC_NUM << BIT_SHIFT_HI5Q_DESC_NUM) #define BIT_CLEAR_HI5Q_DESC_NUM(x) ((x) & (~BITS_HI5Q_DESC_NUM)) #define BIT_GET_HI5Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_HI5Q_DESC_NUM) & BIT_MASK_HI5Q_DESC_NUM) #define BIT_SET_HI5Q_DESC_NUM(x, v) \ (BIT_CLEAR_HI5Q_DESC_NUM(x) | BIT_HI5Q_DESC_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI6Q_HI7Q_TXBD_NUM (Offset 0x0398) */ #define BIT_P0HI7Q_FLAG BIT(30) #define BIT_CLR_FWCMDQ_HW_IDX BIT(30) #define BIT_CLR_P0HI7Q_HW_IDX BIT(29) #define BIT_SHIFT_P0HI7Q_DESC_MODE 28 #define BIT_MASK_P0HI7Q_DESC_MODE 0x3 #define BIT_P0HI7Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI7Q_DESC_MODE) << BIT_SHIFT_P0HI7Q_DESC_MODE) #define BITS_P0HI7Q_DESC_MODE \ (BIT_MASK_P0HI7Q_DESC_MODE << BIT_SHIFT_P0HI7Q_DESC_MODE) #define BIT_CLEAR_P0HI7Q_DESC_MODE(x) ((x) & (~BITS_P0HI7Q_DESC_MODE)) #define BIT_GET_P0HI7Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI7Q_DESC_MODE) & BIT_MASK_P0HI7Q_DESC_MODE) #define BIT_SET_P0HI7Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI7Q_DESC_MODE(x) | BIT_P0HI7Q_DESC_MODE(v)) #define BIT_CLR_P0HI6Q_HW_IDX BIT(28) #define BIT_CLR_P0HI5Q_HW_IDX BIT(27) #define BIT_CLR_P0HI4Q_HW_IDX BIT(26) #define BIT_CLR_P0HI3Q_HW_IDX BIT(25) #define BIT_CLR_P0HI2Q_HW_IDX BIT(24) #define BIT_CLR_P0HI1Q_HW_IDX BIT(23) #define BIT_CLR_P0HI0Q_HW_IDX BIT(22) #define BIT_CLR_ACH3_HW_IDX BIT(21) #define BIT_CLR_ACH2_HW_IDX BIT(20) #define BIT_CLR_ACH1_HW_IDX BIT(19) #define BIT_CLR_ACH0_HW_IDX BIT(18) #define BIT_CLR_P0MGQ_HW_IDX BIT(17) #define BIT_SHIFT_P0HI7Q_DESC_NUM 16 #define BIT_MASK_P0HI7Q_DESC_NUM 0xfff #define BIT_P0HI7Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI7Q_DESC_NUM) << BIT_SHIFT_P0HI7Q_DESC_NUM) #define BITS_P0HI7Q_DESC_NUM \ (BIT_MASK_P0HI7Q_DESC_NUM << BIT_SHIFT_P0HI7Q_DESC_NUM) #define BIT_CLEAR_P0HI7Q_DESC_NUM(x) ((x) & (~BITS_P0HI7Q_DESC_NUM)) #define BIT_GET_P0HI7Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI7Q_DESC_NUM) & BIT_MASK_P0HI7Q_DESC_NUM) #define BIT_SET_P0HI7Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI7Q_DESC_NUM(x) | BIT_P0HI7Q_DESC_NUM(v)) #define BIT_CLR_P0RXQ_HW_IDX BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI6Q_TXBD_NUM (Offset 0x0398) */ #define BIT_HI6Q_FLAG BIT(14) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI6Q_HI7Q_TXBD_NUM (Offset 0x0398) */ #define BIT_P0HI6Q_FLAG BIT(14) #define BIT_CLR_PFWCMDQ_HOST_IDX BIT(14) #define BIT_CLR_P0HI7Q_HOST_IDX BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI6Q_TXBD_NUM (Offset 0x0398) */ #define BIT_SHIFT_HI6Q_DESC_MODE 12 #define BIT_MASK_HI6Q_DESC_MODE 0x3 #define BIT_HI6Q_DESC_MODE(x) \ (((x) & BIT_MASK_HI6Q_DESC_MODE) << BIT_SHIFT_HI6Q_DESC_MODE) #define BITS_HI6Q_DESC_MODE \ (BIT_MASK_HI6Q_DESC_MODE << BIT_SHIFT_HI6Q_DESC_MODE) #define BIT_CLEAR_HI6Q_DESC_MODE(x) ((x) & (~BITS_HI6Q_DESC_MODE)) #define BIT_GET_HI6Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_HI6Q_DESC_MODE) & BIT_MASK_HI6Q_DESC_MODE) #define BIT_SET_HI6Q_DESC_MODE(x, v) \ (BIT_CLEAR_HI6Q_DESC_MODE(x) | BIT_HI6Q_DESC_MODE(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI6Q_HI7Q_TXBD_NUM (Offset 0x0398) */ #define BIT_SHIFT_P0HI6Q_DESC_MODE 12 #define BIT_MASK_P0HI6Q_DESC_MODE 0x3 #define BIT_P0HI6Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI6Q_DESC_MODE) << BIT_SHIFT_P0HI6Q_DESC_MODE) #define BITS_P0HI6Q_DESC_MODE \ (BIT_MASK_P0HI6Q_DESC_MODE << BIT_SHIFT_P0HI6Q_DESC_MODE) #define BIT_CLEAR_P0HI6Q_DESC_MODE(x) ((x) & (~BITS_P0HI6Q_DESC_MODE)) #define BIT_GET_P0HI6Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI6Q_DESC_MODE) & BIT_MASK_P0HI6Q_DESC_MODE) #define BIT_SET_P0HI6Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI6Q_DESC_MODE(x) | BIT_P0HI6Q_DESC_MODE(v)) #define BIT_CLR_P0HI6Q_HOST_IDX BIT(12) #define BIT_CLR_P0HI5Q_HOST_IDX BIT(11) #define BIT_CLR_P0HI4Q_HOST_IDX BIT(10) #define BIT_CLR_P0HI3Q_HOST_IDX BIT(9) #define BIT_CLR_P0HI2Q_HOST_IDX BIT(8) #define BIT_CLR_P0HI1Q_HOST_IDX BIT(7) #define BIT_CLR_P0HI0Q_HOST_IDX BIT(6) #define BIT_CLR_ACH3_HOST_IDX BIT(5) #define BIT_CLR_ACH2_HOST_IDX BIT(4) #define BIT_CLR_ACH1_HOST_IDX BIT(3) #define BIT_CLR_ACH0_HOST_IDX BIT(2) #define BIT_CLR_P0MGQ_HOST_IDX BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI6Q_TXBD_NUM (Offset 0x0398) */ #define BIT_SHIFT_HI6Q_DESC_NUM 0 #define BIT_MASK_HI6Q_DESC_NUM 0xfff #define BIT_HI6Q_DESC_NUM(x) \ (((x) & BIT_MASK_HI6Q_DESC_NUM) << BIT_SHIFT_HI6Q_DESC_NUM) #define BITS_HI6Q_DESC_NUM (BIT_MASK_HI6Q_DESC_NUM << BIT_SHIFT_HI6Q_DESC_NUM) #define BIT_CLEAR_HI6Q_DESC_NUM(x) ((x) & (~BITS_HI6Q_DESC_NUM)) #define BIT_GET_HI6Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_HI6Q_DESC_NUM) & BIT_MASK_HI6Q_DESC_NUM) #define BIT_SET_HI6Q_DESC_NUM(x, v) \ (BIT_CLEAR_HI6Q_DESC_NUM(x) | BIT_HI6Q_DESC_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI6Q_HI7Q_TXBD_NUM (Offset 0x0398) */ #define BIT_SHIFT_P0HI6Q_DESC_NUM 0 #define BIT_MASK_P0HI6Q_DESC_NUM 0xfff #define BIT_P0HI6Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI6Q_DESC_NUM) << BIT_SHIFT_P0HI6Q_DESC_NUM) #define BITS_P0HI6Q_DESC_NUM \ (BIT_MASK_P0HI6Q_DESC_NUM << BIT_SHIFT_P0HI6Q_DESC_NUM) #define BIT_CLEAR_P0HI6Q_DESC_NUM(x) ((x) & (~BITS_P0HI6Q_DESC_NUM)) #define BIT_GET_P0HI6Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI6Q_DESC_NUM) & BIT_MASK_P0HI6Q_DESC_NUM) #define BIT_SET_P0HI6Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI6Q_DESC_NUM(x) | BIT_P0HI6Q_DESC_NUM(v)) #define BIT_CLR_P0RXQ_HOST_IDX BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI7Q_TXBD_NUM (Offset 0x039A) */ #define BIT_HI7Q_FLAG BIT(14) #define BIT_SHIFT_HI7Q_DESC_MODE 12 #define BIT_MASK_HI7Q_DESC_MODE 0x3 #define BIT_HI7Q_DESC_MODE(x) \ (((x) & BIT_MASK_HI7Q_DESC_MODE) << BIT_SHIFT_HI7Q_DESC_MODE) #define BITS_HI7Q_DESC_MODE \ (BIT_MASK_HI7Q_DESC_MODE << BIT_SHIFT_HI7Q_DESC_MODE) #define BIT_CLEAR_HI7Q_DESC_MODE(x) ((x) & (~BITS_HI7Q_DESC_MODE)) #define BIT_GET_HI7Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_HI7Q_DESC_MODE) & BIT_MASK_HI7Q_DESC_MODE) #define BIT_SET_HI7Q_DESC_MODE(x, v) \ (BIT_CLEAR_HI7Q_DESC_MODE(x) | BIT_HI7Q_DESC_MODE(v)) #define BIT_SHIFT_HI7Q_DESC_NUM 0 #define BIT_MASK_HI7Q_DESC_NUM 0xfff #define BIT_HI7Q_DESC_NUM(x) \ (((x) & BIT_MASK_HI7Q_DESC_NUM) << BIT_SHIFT_HI7Q_DESC_NUM) #define BITS_HI7Q_DESC_NUM (BIT_MASK_HI7Q_DESC_NUM << BIT_SHIFT_HI7Q_DESC_NUM) #define BIT_CLEAR_HI7Q_DESC_NUM(x) ((x) & (~BITS_HI7Q_DESC_NUM)) #define BIT_GET_HI7Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_HI7Q_DESC_NUM) & BIT_MASK_HI7Q_DESC_NUM) #define BIT_SET_HI7Q_DESC_NUM(x, v) \ (BIT_CLEAR_HI7Q_DESC_NUM(x) | BIT_HI7Q_DESC_NUM(v)) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_HI7Q_HW_IDX BIT(29) #define BIT_CLR_HI6Q_HW_IDX BIT(28) #define BIT_CLR_HI5Q_HW_IDX BIT(27) #define BIT_CLR_HI4Q_HW_IDX BIT(26) #define BIT_CLR_HI3Q_HW_IDX BIT(25) #define BIT_CLR_HI2Q_HW_IDX BIT(24) #define BIT_CLR_HI1Q_HW_IDX BIT(23) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_BCN7DOK BIT(23) #define BIT_BCN7DOKM BIT(23) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_HI0Q_HW_IDX BIT(22) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_BCN6DOK BIT(22) #define BIT_BCN6DOKM BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_BKQ_HW_IDX BIT(21) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_BCN5DOK BIT(21) #define BIT_BCN5DOKM BIT(21) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_BEQ_HW_IDX BIT(20) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_BCN4DOK BIT(20) #define BIT_BCN4DOKM BIT(20) #define BIT_RX_OVER_RD_ERR BIT(20) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_VIQ_HW_IDX BIT(19) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_BCN3DOK BIT(19) #define BIT_BCN3DOKM BIT(19) #define BIT_RXDMA_STUCK BIT(19) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_VOQ_HW_IDX BIT(18) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_BCN2DOK BIT(18) #define BIT_BCN2DOKM BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_MGQ_HW_IDX BIT(17) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_BCN1DOK BIT(17) #define BIT_BCN1DOKM BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TSFTIMER_HCI (Offset 0x039C) */ #define BIT_SHIFT_TSFT2_HCI 16 #define BIT_MASK_TSFT2_HCI 0xffff #define BIT_TSFT2_HCI(x) (((x) & BIT_MASK_TSFT2_HCI) << BIT_SHIFT_TSFT2_HCI) #define BITS_TSFT2_HCI (BIT_MASK_TSFT2_HCI << BIT_SHIFT_TSFT2_HCI) #define BIT_CLEAR_TSFT2_HCI(x) ((x) & (~BITS_TSFT2_HCI)) #define BIT_GET_TSFT2_HCI(x) (((x) >> BIT_SHIFT_TSFT2_HCI) & BIT_MASK_TSFT2_HCI) #define BIT_SET_TSFT2_HCI(x, v) (BIT_CLEAR_TSFT2_HCI(x) | BIT_TSFT2_HCI(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_RXQ_HW_IDX BIT(16) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_BCN0DOK BIT(16) #define BIT_BCN0DOKM BIT(16) #define BIT_SHIFT_RX_STATE 16 #define BIT_MASK_RX_STATE 0x7 #define BIT_RX_STATE(x) (((x) & BIT_MASK_RX_STATE) << BIT_SHIFT_RX_STATE) #define BITS_RX_STATE (BIT_MASK_RX_STATE << BIT_SHIFT_RX_STATE) #define BIT_CLEAR_RX_STATE(x) ((x) & (~BITS_RX_STATE)) #define BIT_GET_RX_STATE(x) (((x) >> BIT_SHIFT_RX_STATE) & BIT_MASK_RX_STATE) #define BIT_SET_RX_STATE(x, v) (BIT_CLEAR_RX_STATE(x) | BIT_RX_STATE(v)) #define BIT_SRST_TX BIT(15) #define BIT_M7DOK BIT(15) #define BIT_M7DOKM BIT(15) #define BIT_TDE_NO_IDLE BIT(15) #define BIT_SRST_RX BIT(14) #define BIT_M6DOK BIT(14) #define BIT_M6DOKM BIT(14) #define BIT_TXDMA_STUCK BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_HI7Q_HOST_IDX BIT(13) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_M5DOK BIT(13) #define BIT_M5DOKM BIT(13) #define BIT_TDE_FULL_ERR BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_HI6Q_HOST_IDX BIT(12) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_M4DOK BIT(12) #define BIT_M4DOKM BIT(12) #define BIT_HD_SIZE_ERR BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_HI5Q_HOST_IDX BIT(11) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_M3DOK BIT(11) #define BIT_M3DOKM BIT(11) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_HI4Q_HOST_IDX BIT(10) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_M2DOK BIT(10) #define BIT_M2DOKM BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_HI3Q_HOST_IDX BIT(9) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_M1DOK BIT(9) #define BIT_M1DOKM BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_HI2Q_HOST_IDX BIT(8) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_M0DOK BIT(8) #define BIT_M0DOKM BIT(8) #define BIT_SHIFT_TX_STATE 8 #define BIT_MASK_TX_STATE 0xf #define BIT_TX_STATE(x) (((x) & BIT_MASK_TX_STATE) << BIT_SHIFT_TX_STATE) #define BITS_TX_STATE (BIT_MASK_TX_STATE << BIT_SHIFT_TX_STATE) #define BIT_CLEAR_TX_STATE(x) ((x) & (~BITS_TX_STATE)) #define BIT_GET_TX_STATE(x) (((x) >> BIT_SHIFT_TX_STATE) & BIT_MASK_TX_STATE) #define BIT_SET_TX_STATE(x, v) (BIT_CLEAR_TX_STATE(x) | BIT_TX_STATE(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_HI1Q_HOST_IDX BIT(7) #define BIT_CLR_HI0Q_HOST_IDX BIT(6) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_MGQDOK BIT(6) #define BIT_MGQDOKM BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_BKQ_HOST_IDX BIT(5) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_BKQDOK BIT(5) #define BIT_BKQDOKM BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_BEQ_HOST_IDX BIT(4) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_SHIFT_HPS_CLKR 4 #define BIT_MASK_HPS_CLKR 0x3 #define BIT_HPS_CLKR(x) (((x) & BIT_MASK_HPS_CLKR) << BIT_SHIFT_HPS_CLKR) #define BITS_HPS_CLKR (BIT_MASK_HPS_CLKR << BIT_SHIFT_HPS_CLKR) #define BIT_CLEAR_HPS_CLKR(x) ((x) & (~BITS_HPS_CLKR)) #define BIT_GET_HPS_CLKR(x) (((x) >> BIT_SHIFT_HPS_CLKR) & BIT_MASK_HPS_CLKR) #define BIT_SET_HPS_CLKR(x, v) (BIT_CLEAR_HPS_CLKR(x) | BIT_HPS_CLKR(v)) #define BIT_BEQDOK BIT(4) #define BIT_BEQDOKM BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_VIQ_HOST_IDX BIT(3) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_LX_INT BIT(3) #define BIT_VIQDOK BIT(3) #define BIT_VIQDOKM BIT(3) #define BIT_MST_BUSY BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_VOQ_HOST_IDX BIT(2) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_VOQDOK BIT(2) #define BIT_VOQDOKM BIT(2) #define BIT_SLV_BUSY BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_MGQ_HOST_IDX BIT(1) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_RDUM BIT(1) #define BIT_RXDES_UNAVAIL BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TSFTIMER_HCI (Offset 0x039C) */ #define BIT_SHIFT_TSFT1_HCI 0 #define BIT_MASK_TSFT1_HCI 0xffff #define BIT_TSFT1_HCI(x) (((x) & BIT_MASK_TSFT1_HCI) << BIT_SHIFT_TSFT1_HCI) #define BITS_TSFT1_HCI (BIT_MASK_TSFT1_HCI << BIT_SHIFT_TSFT1_HCI) #define BIT_CLEAR_TSFT1_HCI(x) ((x) & (~BITS_TSFT1_HCI)) #define BIT_GET_TSFT1_HCI(x) (((x) >> BIT_SHIFT_TSFT1_HCI) & BIT_MASK_TSFT1_HCI) #define BIT_SET_TSFT1_HCI(x, v) (BIT_CLEAR_TSFT1_HCI(x) | BIT_TSFT1_HCI(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_CLR_RXQ_HOST_IDX BIT(0) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ #define BIT_RXDOK BIT(0) #define BIT_RXDOKM BIT(0) #define BIT_EN_DBG_STUCK BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_VOQ_TXBD_IDX (Offset 0x03A0) */ #define BIT_SHIFT_VOQ_HW_IDX 16 #define BIT_MASK_VOQ_HW_IDX 0xfff #define BIT_VOQ_HW_IDX(x) (((x) & BIT_MASK_VOQ_HW_IDX) << BIT_SHIFT_VOQ_HW_IDX) #define BITS_VOQ_HW_IDX (BIT_MASK_VOQ_HW_IDX << BIT_SHIFT_VOQ_HW_IDX) #define BIT_CLEAR_VOQ_HW_IDX(x) ((x) & (~BITS_VOQ_HW_IDX)) #define BIT_GET_VOQ_HW_IDX(x) \ (((x) >> BIT_SHIFT_VOQ_HW_IDX) & BIT_MASK_VOQ_HW_IDX) #define BIT_SET_VOQ_HW_IDX(x, v) (BIT_CLEAR_VOQ_HW_IDX(x) | BIT_VOQ_HW_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH0_TXBD_IDX (Offset 0x03A0) */ #define BIT_SHIFT_ACH0_HW_IDX 16 #define BIT_MASK_ACH0_HW_IDX 0xfff #define BIT_ACH0_HW_IDX(x) \ (((x) & BIT_MASK_ACH0_HW_IDX) << BIT_SHIFT_ACH0_HW_IDX) #define BITS_ACH0_HW_IDX (BIT_MASK_ACH0_HW_IDX << BIT_SHIFT_ACH0_HW_IDX) #define BIT_CLEAR_ACH0_HW_IDX(x) ((x) & (~BITS_ACH0_HW_IDX)) #define BIT_GET_ACH0_HW_IDX(x) \ (((x) >> BIT_SHIFT_ACH0_HW_IDX) & BIT_MASK_ACH0_HW_IDX) #define BIT_SET_ACH0_HW_IDX(x, v) \ (BIT_CLEAR_ACH0_HW_IDX(x) | BIT_ACH0_HW_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_VOQ_TXBD_IDX (Offset 0x03A0) */ #define BIT_SHIFT_VOQ_HOST_IDX 0 #define BIT_MASK_VOQ_HOST_IDX 0xfff #define BIT_VOQ_HOST_IDX(x) \ (((x) & BIT_MASK_VOQ_HOST_IDX) << BIT_SHIFT_VOQ_HOST_IDX) #define BITS_VOQ_HOST_IDX (BIT_MASK_VOQ_HOST_IDX << BIT_SHIFT_VOQ_HOST_IDX) #define BIT_CLEAR_VOQ_HOST_IDX(x) ((x) & (~BITS_VOQ_HOST_IDX)) #define BIT_GET_VOQ_HOST_IDX(x) \ (((x) >> BIT_SHIFT_VOQ_HOST_IDX) & BIT_MASK_VOQ_HOST_IDX) #define BIT_SET_VOQ_HOST_IDX(x, v) \ (BIT_CLEAR_VOQ_HOST_IDX(x) | BIT_VOQ_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH0_TXBD_IDX (Offset 0x03A0) */ #define BIT_SHIFT_ACH0_HOST_IDX 0 #define BIT_MASK_ACH0_HOST_IDX 0xfff #define BIT_ACH0_HOST_IDX(x) \ (((x) & BIT_MASK_ACH0_HOST_IDX) << BIT_SHIFT_ACH0_HOST_IDX) #define BITS_ACH0_HOST_IDX (BIT_MASK_ACH0_HOST_IDX << BIT_SHIFT_ACH0_HOST_IDX) #define BIT_CLEAR_ACH0_HOST_IDX(x) ((x) & (~BITS_ACH0_HOST_IDX)) #define BIT_GET_ACH0_HOST_IDX(x) \ (((x) >> BIT_SHIFT_ACH0_HOST_IDX) & BIT_MASK_ACH0_HOST_IDX) #define BIT_SET_ACH0_HOST_IDX(x, v) \ (BIT_CLEAR_ACH0_HOST_IDX(x) | BIT_ACH0_HOST_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_VIQ_TXBD_IDX (Offset 0x03A4) */ #define BIT_SHIFT_VIQ_HW_IDX 16 #define BIT_MASK_VIQ_HW_IDX 0xfff #define BIT_VIQ_HW_IDX(x) (((x) & BIT_MASK_VIQ_HW_IDX) << BIT_SHIFT_VIQ_HW_IDX) #define BITS_VIQ_HW_IDX (BIT_MASK_VIQ_HW_IDX << BIT_SHIFT_VIQ_HW_IDX) #define BIT_CLEAR_VIQ_HW_IDX(x) ((x) & (~BITS_VIQ_HW_IDX)) #define BIT_GET_VIQ_HW_IDX(x) \ (((x) >> BIT_SHIFT_VIQ_HW_IDX) & BIT_MASK_VIQ_HW_IDX) #define BIT_SET_VIQ_HW_IDX(x, v) (BIT_CLEAR_VIQ_HW_IDX(x) | BIT_VIQ_HW_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH1_TXBD_IDX (Offset 0x03A4) */ #define BIT_SHIFT_ACH1_HW_IDX 16 #define BIT_MASK_ACH1_HW_IDX 0xfff #define BIT_ACH1_HW_IDX(x) \ (((x) & BIT_MASK_ACH1_HW_IDX) << BIT_SHIFT_ACH1_HW_IDX) #define BITS_ACH1_HW_IDX (BIT_MASK_ACH1_HW_IDX << BIT_SHIFT_ACH1_HW_IDX) #define BIT_CLEAR_ACH1_HW_IDX(x) ((x) & (~BITS_ACH1_HW_IDX)) #define BIT_GET_ACH1_HW_IDX(x) \ (((x) >> BIT_SHIFT_ACH1_HW_IDX) & BIT_MASK_ACH1_HW_IDX) #define BIT_SET_ACH1_HW_IDX(x, v) \ (BIT_CLEAR_ACH1_HW_IDX(x) | BIT_ACH1_HW_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_VIQ_TXBD_IDX (Offset 0x03A4) */ #define BIT_SHIFT_VIQ_HOST_IDX 0 #define BIT_MASK_VIQ_HOST_IDX 0xfff #define BIT_VIQ_HOST_IDX(x) \ (((x) & BIT_MASK_VIQ_HOST_IDX) << BIT_SHIFT_VIQ_HOST_IDX) #define BITS_VIQ_HOST_IDX (BIT_MASK_VIQ_HOST_IDX << BIT_SHIFT_VIQ_HOST_IDX) #define BIT_CLEAR_VIQ_HOST_IDX(x) ((x) & (~BITS_VIQ_HOST_IDX)) #define BIT_GET_VIQ_HOST_IDX(x) \ (((x) >> BIT_SHIFT_VIQ_HOST_IDX) & BIT_MASK_VIQ_HOST_IDX) #define BIT_SET_VIQ_HOST_IDX(x, v) \ (BIT_CLEAR_VIQ_HOST_IDX(x) | BIT_VIQ_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH1_TXBD_IDX (Offset 0x03A4) */ #define BIT_SHIFT_ACH1_HOST_IDX 0 #define BIT_MASK_ACH1_HOST_IDX 0xfff #define BIT_ACH1_HOST_IDX(x) \ (((x) & BIT_MASK_ACH1_HOST_IDX) << BIT_SHIFT_ACH1_HOST_IDX) #define BITS_ACH1_HOST_IDX (BIT_MASK_ACH1_HOST_IDX << BIT_SHIFT_ACH1_HOST_IDX) #define BIT_CLEAR_ACH1_HOST_IDX(x) ((x) & (~BITS_ACH1_HOST_IDX)) #define BIT_GET_ACH1_HOST_IDX(x) \ (((x) >> BIT_SHIFT_ACH1_HOST_IDX) & BIT_MASK_ACH1_HOST_IDX) #define BIT_SET_ACH1_HOST_IDX(x, v) \ (BIT_CLEAR_ACH1_HOST_IDX(x) | BIT_ACH1_HOST_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BEQ_TXBD_IDX (Offset 0x03A8) */ #define BIT_SHIFT_BEQ_HW_IDX 16 #define BIT_MASK_BEQ_HW_IDX 0xfff #define BIT_BEQ_HW_IDX(x) (((x) & BIT_MASK_BEQ_HW_IDX) << BIT_SHIFT_BEQ_HW_IDX) #define BITS_BEQ_HW_IDX (BIT_MASK_BEQ_HW_IDX << BIT_SHIFT_BEQ_HW_IDX) #define BIT_CLEAR_BEQ_HW_IDX(x) ((x) & (~BITS_BEQ_HW_IDX)) #define BIT_GET_BEQ_HW_IDX(x) \ (((x) >> BIT_SHIFT_BEQ_HW_IDX) & BIT_MASK_BEQ_HW_IDX) #define BIT_SET_BEQ_HW_IDX(x, v) (BIT_CLEAR_BEQ_HW_IDX(x) | BIT_BEQ_HW_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH2_TXBD_IDX (Offset 0x03A8) */ #define BIT_SHIFT_ACH2_HW_IDX 16 #define BIT_MASK_ACH2_HW_IDX 0xfff #define BIT_ACH2_HW_IDX(x) \ (((x) & BIT_MASK_ACH2_HW_IDX) << BIT_SHIFT_ACH2_HW_IDX) #define BITS_ACH2_HW_IDX (BIT_MASK_ACH2_HW_IDX << BIT_SHIFT_ACH2_HW_IDX) #define BIT_CLEAR_ACH2_HW_IDX(x) ((x) & (~BITS_ACH2_HW_IDX)) #define BIT_GET_ACH2_HW_IDX(x) \ (((x) >> BIT_SHIFT_ACH2_HW_IDX) & BIT_MASK_ACH2_HW_IDX) #define BIT_SET_ACH2_HW_IDX(x, v) \ (BIT_CLEAR_ACH2_HW_IDX(x) | BIT_ACH2_HW_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BEQ_TXBD_IDX (Offset 0x03A8) */ #define BIT_SHIFT_BEQ_HOST_IDX 0 #define BIT_MASK_BEQ_HOST_IDX 0xfff #define BIT_BEQ_HOST_IDX(x) \ (((x) & BIT_MASK_BEQ_HOST_IDX) << BIT_SHIFT_BEQ_HOST_IDX) #define BITS_BEQ_HOST_IDX (BIT_MASK_BEQ_HOST_IDX << BIT_SHIFT_BEQ_HOST_IDX) #define BIT_CLEAR_BEQ_HOST_IDX(x) ((x) & (~BITS_BEQ_HOST_IDX)) #define BIT_GET_BEQ_HOST_IDX(x) \ (((x) >> BIT_SHIFT_BEQ_HOST_IDX) & BIT_MASK_BEQ_HOST_IDX) #define BIT_SET_BEQ_HOST_IDX(x, v) \ (BIT_CLEAR_BEQ_HOST_IDX(x) | BIT_BEQ_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH2_TXBD_IDX (Offset 0x03A8) */ #define BIT_SHIFT_ACH2_HOST_IDX 0 #define BIT_MASK_ACH2_HOST_IDX 0xfff #define BIT_ACH2_HOST_IDX(x) \ (((x) & BIT_MASK_ACH2_HOST_IDX) << BIT_SHIFT_ACH2_HOST_IDX) #define BITS_ACH2_HOST_IDX (BIT_MASK_ACH2_HOST_IDX << BIT_SHIFT_ACH2_HOST_IDX) #define BIT_CLEAR_ACH2_HOST_IDX(x) ((x) & (~BITS_ACH2_HOST_IDX)) #define BIT_GET_ACH2_HOST_IDX(x) \ (((x) >> BIT_SHIFT_ACH2_HOST_IDX) & BIT_MASK_ACH2_HOST_IDX) #define BIT_SET_ACH2_HOST_IDX(x, v) \ (BIT_CLEAR_ACH2_HOST_IDX(x) | BIT_ACH2_HOST_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BKQ_TXBD_IDX (Offset 0x03AC) */ #define BIT_SHIFT_BKQ_HW_IDX 16 #define BIT_MASK_BKQ_HW_IDX 0xfff #define BIT_BKQ_HW_IDX(x) (((x) & BIT_MASK_BKQ_HW_IDX) << BIT_SHIFT_BKQ_HW_IDX) #define BITS_BKQ_HW_IDX (BIT_MASK_BKQ_HW_IDX << BIT_SHIFT_BKQ_HW_IDX) #define BIT_CLEAR_BKQ_HW_IDX(x) ((x) & (~BITS_BKQ_HW_IDX)) #define BIT_GET_BKQ_HW_IDX(x) \ (((x) >> BIT_SHIFT_BKQ_HW_IDX) & BIT_MASK_BKQ_HW_IDX) #define BIT_SET_BKQ_HW_IDX(x, v) (BIT_CLEAR_BKQ_HW_IDX(x) | BIT_BKQ_HW_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH3_TXBD_IDX (Offset 0x03AC) */ #define BIT_SHIFT_ACH3_HW_IDX 16 #define BIT_MASK_ACH3_HW_IDX 0xfff #define BIT_ACH3_HW_IDX(x) \ (((x) & BIT_MASK_ACH3_HW_IDX) << BIT_SHIFT_ACH3_HW_IDX) #define BITS_ACH3_HW_IDX (BIT_MASK_ACH3_HW_IDX << BIT_SHIFT_ACH3_HW_IDX) #define BIT_CLEAR_ACH3_HW_IDX(x) ((x) & (~BITS_ACH3_HW_IDX)) #define BIT_GET_ACH3_HW_IDX(x) \ (((x) >> BIT_SHIFT_ACH3_HW_IDX) & BIT_MASK_ACH3_HW_IDX) #define BIT_SET_ACH3_HW_IDX(x, v) \ (BIT_CLEAR_ACH3_HW_IDX(x) | BIT_ACH3_HW_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BKQ_TXBD_IDX (Offset 0x03AC) */ #define BIT_SHIFT_BKQ_HOST_IDX 0 #define BIT_MASK_BKQ_HOST_IDX 0xfff #define BIT_BKQ_HOST_IDX(x) \ (((x) & BIT_MASK_BKQ_HOST_IDX) << BIT_SHIFT_BKQ_HOST_IDX) #define BITS_BKQ_HOST_IDX (BIT_MASK_BKQ_HOST_IDX << BIT_SHIFT_BKQ_HOST_IDX) #define BIT_CLEAR_BKQ_HOST_IDX(x) ((x) & (~BITS_BKQ_HOST_IDX)) #define BIT_GET_BKQ_HOST_IDX(x) \ (((x) >> BIT_SHIFT_BKQ_HOST_IDX) & BIT_MASK_BKQ_HOST_IDX) #define BIT_SET_BKQ_HOST_IDX(x, v) \ (BIT_CLEAR_BKQ_HOST_IDX(x) | BIT_BKQ_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH3_TXBD_IDX (Offset 0x03AC) */ #define BIT_SHIFT_ACH3_HOST_IDX 0 #define BIT_MASK_ACH3_HOST_IDX 0xfff #define BIT_ACH3_HOST_IDX(x) \ (((x) & BIT_MASK_ACH3_HOST_IDX) << BIT_SHIFT_ACH3_HOST_IDX) #define BITS_ACH3_HOST_IDX (BIT_MASK_ACH3_HOST_IDX << BIT_SHIFT_ACH3_HOST_IDX) #define BIT_CLEAR_ACH3_HOST_IDX(x) ((x) & (~BITS_ACH3_HOST_IDX)) #define BIT_GET_ACH3_HOST_IDX(x) \ (((x) >> BIT_SHIFT_ACH3_HOST_IDX) & BIT_MASK_ACH3_HOST_IDX) #define BIT_SET_ACH3_HOST_IDX(x, v) \ (BIT_CLEAR_ACH3_HOST_IDX(x) | BIT_ACH3_HOST_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MGQ_TXBD_IDX (Offset 0x03B0) */ #define BIT_SHIFT_MGQ_HW_IDX 16 #define BIT_MASK_MGQ_HW_IDX 0xfff #define BIT_MGQ_HW_IDX(x) (((x) & BIT_MASK_MGQ_HW_IDX) << BIT_SHIFT_MGQ_HW_IDX) #define BITS_MGQ_HW_IDX (BIT_MASK_MGQ_HW_IDX << BIT_SHIFT_MGQ_HW_IDX) #define BIT_CLEAR_MGQ_HW_IDX(x) ((x) & (~BITS_MGQ_HW_IDX)) #define BIT_GET_MGQ_HW_IDX(x) \ (((x) >> BIT_SHIFT_MGQ_HW_IDX) & BIT_MASK_MGQ_HW_IDX) #define BIT_SET_MGQ_HW_IDX(x, v) (BIT_CLEAR_MGQ_HW_IDX(x) | BIT_MGQ_HW_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0MGQ_TXBD_IDX (Offset 0x03B0) */ #define BIT_SHIFT_P0MGQ_HW_IDX 16 #define BIT_MASK_P0MGQ_HW_IDX 0xfff #define BIT_P0MGQ_HW_IDX(x) \ (((x) & BIT_MASK_P0MGQ_HW_IDX) << BIT_SHIFT_P0MGQ_HW_IDX) #define BITS_P0MGQ_HW_IDX (BIT_MASK_P0MGQ_HW_IDX << BIT_SHIFT_P0MGQ_HW_IDX) #define BIT_CLEAR_P0MGQ_HW_IDX(x) ((x) & (~BITS_P0MGQ_HW_IDX)) #define BIT_GET_P0MGQ_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0MGQ_HW_IDX) & BIT_MASK_P0MGQ_HW_IDX) #define BIT_SET_P0MGQ_HW_IDX(x, v) \ (BIT_CLEAR_P0MGQ_HW_IDX(x) | BIT_P0MGQ_HW_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MGQ_TXBD_IDX (Offset 0x03B0) */ #define BIT_SHIFT_MGQ_HOST_IDX 0 #define BIT_MASK_MGQ_HOST_IDX 0xfff #define BIT_MGQ_HOST_IDX(x) \ (((x) & BIT_MASK_MGQ_HOST_IDX) << BIT_SHIFT_MGQ_HOST_IDX) #define BITS_MGQ_HOST_IDX (BIT_MASK_MGQ_HOST_IDX << BIT_SHIFT_MGQ_HOST_IDX) #define BIT_CLEAR_MGQ_HOST_IDX(x) ((x) & (~BITS_MGQ_HOST_IDX)) #define BIT_GET_MGQ_HOST_IDX(x) \ (((x) >> BIT_SHIFT_MGQ_HOST_IDX) & BIT_MASK_MGQ_HOST_IDX) #define BIT_SET_MGQ_HOST_IDX(x, v) \ (BIT_CLEAR_MGQ_HOST_IDX(x) | BIT_MGQ_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0MGQ_TXBD_IDX (Offset 0x03B0) */ #define BIT_SHIFT_P0MGQ_HOST_IDX 0 #define BIT_MASK_P0MGQ_HOST_IDX 0xfff #define BIT_P0MGQ_HOST_IDX(x) \ (((x) & BIT_MASK_P0MGQ_HOST_IDX) << BIT_SHIFT_P0MGQ_HOST_IDX) #define BITS_P0MGQ_HOST_IDX \ (BIT_MASK_P0MGQ_HOST_IDX << BIT_SHIFT_P0MGQ_HOST_IDX) #define BIT_CLEAR_P0MGQ_HOST_IDX(x) ((x) & (~BITS_P0MGQ_HOST_IDX)) #define BIT_GET_P0MGQ_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0MGQ_HOST_IDX) & BIT_MASK_P0MGQ_HOST_IDX) #define BIT_SET_P0MGQ_HOST_IDX(x, v) \ (BIT_CLEAR_P0MGQ_HOST_IDX(x) | BIT_P0MGQ_HOST_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXQ_RXBD_IDX (Offset 0x03B4) */ #define BIT_SHIFT_RXQ_HW_IDX 16 #define BIT_MASK_RXQ_HW_IDX 0xfff #define BIT_RXQ_HW_IDX(x) (((x) & BIT_MASK_RXQ_HW_IDX) << BIT_SHIFT_RXQ_HW_IDX) #define BITS_RXQ_HW_IDX (BIT_MASK_RXQ_HW_IDX << BIT_SHIFT_RXQ_HW_IDX) #define BIT_CLEAR_RXQ_HW_IDX(x) ((x) & (~BITS_RXQ_HW_IDX)) #define BIT_GET_RXQ_HW_IDX(x) \ (((x) >> BIT_SHIFT_RXQ_HW_IDX) & BIT_MASK_RXQ_HW_IDX) #define BIT_SET_RXQ_HW_IDX(x, v) (BIT_CLEAR_RXQ_HW_IDX(x) | BIT_RXQ_HW_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0RXQ_RXBD_IDX (Offset 0x03B4) */ #define BIT_SHIFT_P0RXQ_HW_IDX 16 #define BIT_MASK_P0RXQ_HW_IDX 0xfff #define BIT_P0RXQ_HW_IDX(x) \ (((x) & BIT_MASK_P0RXQ_HW_IDX) << BIT_SHIFT_P0RXQ_HW_IDX) #define BITS_P0RXQ_HW_IDX (BIT_MASK_P0RXQ_HW_IDX << BIT_SHIFT_P0RXQ_HW_IDX) #define BIT_CLEAR_P0RXQ_HW_IDX(x) ((x) & (~BITS_P0RXQ_HW_IDX)) #define BIT_GET_P0RXQ_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0RXQ_HW_IDX) & BIT_MASK_P0RXQ_HW_IDX) #define BIT_SET_P0RXQ_HW_IDX(x, v) \ (BIT_CLEAR_P0RXQ_HW_IDX(x) | BIT_P0RXQ_HW_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RXQ_RXBD_IDX (Offset 0x03B4) */ #define BIT_SHIFT_RXQ_HOST_IDX 0 #define BIT_MASK_RXQ_HOST_IDX 0xfff #define BIT_RXQ_HOST_IDX(x) \ (((x) & BIT_MASK_RXQ_HOST_IDX) << BIT_SHIFT_RXQ_HOST_IDX) #define BITS_RXQ_HOST_IDX (BIT_MASK_RXQ_HOST_IDX << BIT_SHIFT_RXQ_HOST_IDX) #define BIT_CLEAR_RXQ_HOST_IDX(x) ((x) & (~BITS_RXQ_HOST_IDX)) #define BIT_GET_RXQ_HOST_IDX(x) \ (((x) >> BIT_SHIFT_RXQ_HOST_IDX) & BIT_MASK_RXQ_HOST_IDX) #define BIT_SET_RXQ_HOST_IDX(x, v) \ (BIT_CLEAR_RXQ_HOST_IDX(x) | BIT_RXQ_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0RXQ_RXBD_IDX (Offset 0x03B4) */ #define BIT_SHIFT_P0RXQ_HOST_IDX 0 #define BIT_MASK_P0RXQ_HOST_IDX 0xfff #define BIT_P0RXQ_HOST_IDX(x) \ (((x) & BIT_MASK_P0RXQ_HOST_IDX) << BIT_SHIFT_P0RXQ_HOST_IDX) #define BITS_P0RXQ_HOST_IDX \ (BIT_MASK_P0RXQ_HOST_IDX << BIT_SHIFT_P0RXQ_HOST_IDX) #define BIT_CLEAR_P0RXQ_HOST_IDX(x) ((x) & (~BITS_P0RXQ_HOST_IDX)) #define BIT_GET_P0RXQ_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0RXQ_HOST_IDX) & BIT_MASK_P0RXQ_HOST_IDX) #define BIT_SET_P0RXQ_HOST_IDX(x, v) \ (BIT_CLEAR_P0RXQ_HOST_IDX(x) | BIT_P0RXQ_HOST_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI0Q_TXBD_IDX (Offset 0x03B8) */ #define BIT_SHIFT_HI0Q_HW_IDX 16 #define BIT_MASK_HI0Q_HW_IDX 0xfff #define BIT_HI0Q_HW_IDX(x) \ (((x) & BIT_MASK_HI0Q_HW_IDX) << BIT_SHIFT_HI0Q_HW_IDX) #define BITS_HI0Q_HW_IDX (BIT_MASK_HI0Q_HW_IDX << BIT_SHIFT_HI0Q_HW_IDX) #define BIT_CLEAR_HI0Q_HW_IDX(x) ((x) & (~BITS_HI0Q_HW_IDX)) #define BIT_GET_HI0Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_HI0Q_HW_IDX) & BIT_MASK_HI0Q_HW_IDX) #define BIT_SET_HI0Q_HW_IDX(x, v) \ (BIT_CLEAR_HI0Q_HW_IDX(x) | BIT_HI0Q_HW_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI0Q_TXBD_IDX (Offset 0x03B8) */ #define BIT_SHIFT_P0HI0Q_HW_IDX 16 #define BIT_MASK_P0HI0Q_HW_IDX 0xfff #define BIT_P0HI0Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI0Q_HW_IDX) << BIT_SHIFT_P0HI0Q_HW_IDX) #define BITS_P0HI0Q_HW_IDX (BIT_MASK_P0HI0Q_HW_IDX << BIT_SHIFT_P0HI0Q_HW_IDX) #define BIT_CLEAR_P0HI0Q_HW_IDX(x) ((x) & (~BITS_P0HI0Q_HW_IDX)) #define BIT_GET_P0HI0Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI0Q_HW_IDX) & BIT_MASK_P0HI0Q_HW_IDX) #define BIT_SET_P0HI0Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI0Q_HW_IDX(x) | BIT_P0HI0Q_HW_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI0Q_TXBD_IDX (Offset 0x03B8) */ #define BIT_SHIFT_HI0Q_HOST_IDX 0 #define BIT_MASK_HI0Q_HOST_IDX 0xfff #define BIT_HI0Q_HOST_IDX(x) \ (((x) & BIT_MASK_HI0Q_HOST_IDX) << BIT_SHIFT_HI0Q_HOST_IDX) #define BITS_HI0Q_HOST_IDX (BIT_MASK_HI0Q_HOST_IDX << BIT_SHIFT_HI0Q_HOST_IDX) #define BIT_CLEAR_HI0Q_HOST_IDX(x) ((x) & (~BITS_HI0Q_HOST_IDX)) #define BIT_GET_HI0Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_HI0Q_HOST_IDX) & BIT_MASK_HI0Q_HOST_IDX) #define BIT_SET_HI0Q_HOST_IDX(x, v) \ (BIT_CLEAR_HI0Q_HOST_IDX(x) | BIT_HI0Q_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI0Q_TXBD_IDX (Offset 0x03B8) */ #define BIT_SHIFT_P0HI0Q_HOST_IDX 0 #define BIT_MASK_P0HI0Q_HOST_IDX 0xfff #define BIT_P0HI0Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI0Q_HOST_IDX) << BIT_SHIFT_P0HI0Q_HOST_IDX) #define BITS_P0HI0Q_HOST_IDX \ (BIT_MASK_P0HI0Q_HOST_IDX << BIT_SHIFT_P0HI0Q_HOST_IDX) #define BIT_CLEAR_P0HI0Q_HOST_IDX(x) ((x) & (~BITS_P0HI0Q_HOST_IDX)) #define BIT_GET_P0HI0Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI0Q_HOST_IDX) & BIT_MASK_P0HI0Q_HOST_IDX) #define BIT_SET_P0HI0Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI0Q_HOST_IDX(x) | BIT_P0HI0Q_HOST_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI1Q_TXBD_IDX (Offset 0x03BC) */ #define BIT_SHIFT_HI1Q_HW_IDX 16 #define BIT_MASK_HI1Q_HW_IDX 0xfff #define BIT_HI1Q_HW_IDX(x) \ (((x) & BIT_MASK_HI1Q_HW_IDX) << BIT_SHIFT_HI1Q_HW_IDX) #define BITS_HI1Q_HW_IDX (BIT_MASK_HI1Q_HW_IDX << BIT_SHIFT_HI1Q_HW_IDX) #define BIT_CLEAR_HI1Q_HW_IDX(x) ((x) & (~BITS_HI1Q_HW_IDX)) #define BIT_GET_HI1Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_HI1Q_HW_IDX) & BIT_MASK_HI1Q_HW_IDX) #define BIT_SET_HI1Q_HW_IDX(x, v) \ (BIT_CLEAR_HI1Q_HW_IDX(x) | BIT_HI1Q_HW_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI1Q_TXBD_IDX (Offset 0x03BC) */ #define BIT_SHIFT_P0HI1Q_HW_IDX 16 #define BIT_MASK_P0HI1Q_HW_IDX 0xfff #define BIT_P0HI1Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI1Q_HW_IDX) << BIT_SHIFT_P0HI1Q_HW_IDX) #define BITS_P0HI1Q_HW_IDX (BIT_MASK_P0HI1Q_HW_IDX << BIT_SHIFT_P0HI1Q_HW_IDX) #define BIT_CLEAR_P0HI1Q_HW_IDX(x) ((x) & (~BITS_P0HI1Q_HW_IDX)) #define BIT_GET_P0HI1Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI1Q_HW_IDX) & BIT_MASK_P0HI1Q_HW_IDX) #define BIT_SET_P0HI1Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI1Q_HW_IDX(x) | BIT_P0HI1Q_HW_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI1Q_TXBD_IDX (Offset 0x03BC) */ #define BIT_SHIFT_HI1Q_HOST_IDX 0 #define BIT_MASK_HI1Q_HOST_IDX 0xfff #define BIT_HI1Q_HOST_IDX(x) \ (((x) & BIT_MASK_HI1Q_HOST_IDX) << BIT_SHIFT_HI1Q_HOST_IDX) #define BITS_HI1Q_HOST_IDX (BIT_MASK_HI1Q_HOST_IDX << BIT_SHIFT_HI1Q_HOST_IDX) #define BIT_CLEAR_HI1Q_HOST_IDX(x) ((x) & (~BITS_HI1Q_HOST_IDX)) #define BIT_GET_HI1Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_HI1Q_HOST_IDX) & BIT_MASK_HI1Q_HOST_IDX) #define BIT_SET_HI1Q_HOST_IDX(x, v) \ (BIT_CLEAR_HI1Q_HOST_IDX(x) | BIT_HI1Q_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI1Q_TXBD_IDX (Offset 0x03BC) */ #define BIT_SHIFT_P0HI1Q_HOST_IDX 0 #define BIT_MASK_P0HI1Q_HOST_IDX 0xfff #define BIT_P0HI1Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI1Q_HOST_IDX) << BIT_SHIFT_P0HI1Q_HOST_IDX) #define BITS_P0HI1Q_HOST_IDX \ (BIT_MASK_P0HI1Q_HOST_IDX << BIT_SHIFT_P0HI1Q_HOST_IDX) #define BIT_CLEAR_P0HI1Q_HOST_IDX(x) ((x) & (~BITS_P0HI1Q_HOST_IDX)) #define BIT_GET_P0HI1Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI1Q_HOST_IDX) & BIT_MASK_P0HI1Q_HOST_IDX) #define BIT_SET_P0HI1Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI1Q_HOST_IDX(x) | BIT_P0HI1Q_HOST_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI2Q_TXBD_IDX (Offset 0x03C0) */ #define BIT_SHIFT_HI2Q_HW_IDX 16 #define BIT_MASK_HI2Q_HW_IDX 0xfff #define BIT_HI2Q_HW_IDX(x) \ (((x) & BIT_MASK_HI2Q_HW_IDX) << BIT_SHIFT_HI2Q_HW_IDX) #define BITS_HI2Q_HW_IDX (BIT_MASK_HI2Q_HW_IDX << BIT_SHIFT_HI2Q_HW_IDX) #define BIT_CLEAR_HI2Q_HW_IDX(x) ((x) & (~BITS_HI2Q_HW_IDX)) #define BIT_GET_HI2Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_HI2Q_HW_IDX) & BIT_MASK_HI2Q_HW_IDX) #define BIT_SET_HI2Q_HW_IDX(x, v) \ (BIT_CLEAR_HI2Q_HW_IDX(x) | BIT_HI2Q_HW_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI2Q_TXBD_IDX (Offset 0x03C0) */ #define BIT_SHIFT_P0HI2Q_HW_IDX 16 #define BIT_MASK_P0HI2Q_HW_IDX 0xfff #define BIT_P0HI2Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI2Q_HW_IDX) << BIT_SHIFT_P0HI2Q_HW_IDX) #define BITS_P0HI2Q_HW_IDX (BIT_MASK_P0HI2Q_HW_IDX << BIT_SHIFT_P0HI2Q_HW_IDX) #define BIT_CLEAR_P0HI2Q_HW_IDX(x) ((x) & (~BITS_P0HI2Q_HW_IDX)) #define BIT_GET_P0HI2Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI2Q_HW_IDX) & BIT_MASK_P0HI2Q_HW_IDX) #define BIT_SET_P0HI2Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI2Q_HW_IDX(x) | BIT_P0HI2Q_HW_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI2Q_TXBD_IDX (Offset 0x03C0) */ #define BIT_SHIFT_HI2Q_HOST_IDX 0 #define BIT_MASK_HI2Q_HOST_IDX 0xfff #define BIT_HI2Q_HOST_IDX(x) \ (((x) & BIT_MASK_HI2Q_HOST_IDX) << BIT_SHIFT_HI2Q_HOST_IDX) #define BITS_HI2Q_HOST_IDX (BIT_MASK_HI2Q_HOST_IDX << BIT_SHIFT_HI2Q_HOST_IDX) #define BIT_CLEAR_HI2Q_HOST_IDX(x) ((x) & (~BITS_HI2Q_HOST_IDX)) #define BIT_GET_HI2Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_HI2Q_HOST_IDX) & BIT_MASK_HI2Q_HOST_IDX) #define BIT_SET_HI2Q_HOST_IDX(x, v) \ (BIT_CLEAR_HI2Q_HOST_IDX(x) | BIT_HI2Q_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI2Q_TXBD_IDX (Offset 0x03C0) */ #define BIT_SHIFT_P0HI2Q_HOST_IDX 0 #define BIT_MASK_P0HI2Q_HOST_IDX 0xfff #define BIT_P0HI2Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI2Q_HOST_IDX) << BIT_SHIFT_P0HI2Q_HOST_IDX) #define BITS_P0HI2Q_HOST_IDX \ (BIT_MASK_P0HI2Q_HOST_IDX << BIT_SHIFT_P0HI2Q_HOST_IDX) #define BIT_CLEAR_P0HI2Q_HOST_IDX(x) ((x) & (~BITS_P0HI2Q_HOST_IDX)) #define BIT_GET_P0HI2Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI2Q_HOST_IDX) & BIT_MASK_P0HI2Q_HOST_IDX) #define BIT_SET_P0HI2Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI2Q_HOST_IDX(x) | BIT_P0HI2Q_HOST_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI3Q_TXBD_IDX (Offset 0x03C4) */ #define BIT_SHIFT_HI3Q_HW_IDX 16 #define BIT_MASK_HI3Q_HW_IDX 0xfff #define BIT_HI3Q_HW_IDX(x) \ (((x) & BIT_MASK_HI3Q_HW_IDX) << BIT_SHIFT_HI3Q_HW_IDX) #define BITS_HI3Q_HW_IDX (BIT_MASK_HI3Q_HW_IDX << BIT_SHIFT_HI3Q_HW_IDX) #define BIT_CLEAR_HI3Q_HW_IDX(x) ((x) & (~BITS_HI3Q_HW_IDX)) #define BIT_GET_HI3Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_HI3Q_HW_IDX) & BIT_MASK_HI3Q_HW_IDX) #define BIT_SET_HI3Q_HW_IDX(x, v) \ (BIT_CLEAR_HI3Q_HW_IDX(x) | BIT_HI3Q_HW_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI3Q_TXBD_IDX (Offset 0x03C4) */ #define BIT_SHIFT_P0HI3Q_HW_IDX 16 #define BIT_MASK_P0HI3Q_HW_IDX 0xfff #define BIT_P0HI3Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI3Q_HW_IDX) << BIT_SHIFT_P0HI3Q_HW_IDX) #define BITS_P0HI3Q_HW_IDX (BIT_MASK_P0HI3Q_HW_IDX << BIT_SHIFT_P0HI3Q_HW_IDX) #define BIT_CLEAR_P0HI3Q_HW_IDX(x) ((x) & (~BITS_P0HI3Q_HW_IDX)) #define BIT_GET_P0HI3Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI3Q_HW_IDX) & BIT_MASK_P0HI3Q_HW_IDX) #define BIT_SET_P0HI3Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI3Q_HW_IDX(x) | BIT_P0HI3Q_HW_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI3Q_TXBD_IDX (Offset 0x03C4) */ #define BIT_SHIFT_HI3Q_HOST_IDX 0 #define BIT_MASK_HI3Q_HOST_IDX 0xfff #define BIT_HI3Q_HOST_IDX(x) \ (((x) & BIT_MASK_HI3Q_HOST_IDX) << BIT_SHIFT_HI3Q_HOST_IDX) #define BITS_HI3Q_HOST_IDX (BIT_MASK_HI3Q_HOST_IDX << BIT_SHIFT_HI3Q_HOST_IDX) #define BIT_CLEAR_HI3Q_HOST_IDX(x) ((x) & (~BITS_HI3Q_HOST_IDX)) #define BIT_GET_HI3Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_HI3Q_HOST_IDX) & BIT_MASK_HI3Q_HOST_IDX) #define BIT_SET_HI3Q_HOST_IDX(x, v) \ (BIT_CLEAR_HI3Q_HOST_IDX(x) | BIT_HI3Q_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI3Q_TXBD_IDX (Offset 0x03C4) */ #define BIT_SHIFT_P0HI3Q_HOST_IDX 0 #define BIT_MASK_P0HI3Q_HOST_IDX 0xfff #define BIT_P0HI3Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI3Q_HOST_IDX) << BIT_SHIFT_P0HI3Q_HOST_IDX) #define BITS_P0HI3Q_HOST_IDX \ (BIT_MASK_P0HI3Q_HOST_IDX << BIT_SHIFT_P0HI3Q_HOST_IDX) #define BIT_CLEAR_P0HI3Q_HOST_IDX(x) ((x) & (~BITS_P0HI3Q_HOST_IDX)) #define BIT_GET_P0HI3Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI3Q_HOST_IDX) & BIT_MASK_P0HI3Q_HOST_IDX) #define BIT_SET_P0HI3Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI3Q_HOST_IDX(x) | BIT_P0HI3Q_HOST_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI4Q_TXBD_IDX (Offset 0x03C8) */ #define BIT_SHIFT_HI4Q_HW_IDX 16 #define BIT_MASK_HI4Q_HW_IDX 0xfff #define BIT_HI4Q_HW_IDX(x) \ (((x) & BIT_MASK_HI4Q_HW_IDX) << BIT_SHIFT_HI4Q_HW_IDX) #define BITS_HI4Q_HW_IDX (BIT_MASK_HI4Q_HW_IDX << BIT_SHIFT_HI4Q_HW_IDX) #define BIT_CLEAR_HI4Q_HW_IDX(x) ((x) & (~BITS_HI4Q_HW_IDX)) #define BIT_GET_HI4Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_HI4Q_HW_IDX) & BIT_MASK_HI4Q_HW_IDX) #define BIT_SET_HI4Q_HW_IDX(x, v) \ (BIT_CLEAR_HI4Q_HW_IDX(x) | BIT_HI4Q_HW_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI4Q_TXBD_IDX (Offset 0x03C8) */ #define BIT_SHIFT_P0HI4Q_HW_IDX 16 #define BIT_MASK_P0HI4Q_HW_IDX 0xfff #define BIT_P0HI4Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI4Q_HW_IDX) << BIT_SHIFT_P0HI4Q_HW_IDX) #define BITS_P0HI4Q_HW_IDX (BIT_MASK_P0HI4Q_HW_IDX << BIT_SHIFT_P0HI4Q_HW_IDX) #define BIT_CLEAR_P0HI4Q_HW_IDX(x) ((x) & (~BITS_P0HI4Q_HW_IDX)) #define BIT_GET_P0HI4Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI4Q_HW_IDX) & BIT_MASK_P0HI4Q_HW_IDX) #define BIT_SET_P0HI4Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI4Q_HW_IDX(x) | BIT_P0HI4Q_HW_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI4Q_TXBD_IDX (Offset 0x03C8) */ #define BIT_SHIFT_HI4Q_HOST_IDX 0 #define BIT_MASK_HI4Q_HOST_IDX 0xfff #define BIT_HI4Q_HOST_IDX(x) \ (((x) & BIT_MASK_HI4Q_HOST_IDX) << BIT_SHIFT_HI4Q_HOST_IDX) #define BITS_HI4Q_HOST_IDX (BIT_MASK_HI4Q_HOST_IDX << BIT_SHIFT_HI4Q_HOST_IDX) #define BIT_CLEAR_HI4Q_HOST_IDX(x) ((x) & (~BITS_HI4Q_HOST_IDX)) #define BIT_GET_HI4Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_HI4Q_HOST_IDX) & BIT_MASK_HI4Q_HOST_IDX) #define BIT_SET_HI4Q_HOST_IDX(x, v) \ (BIT_CLEAR_HI4Q_HOST_IDX(x) | BIT_HI4Q_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI4Q_TXBD_IDX (Offset 0x03C8) */ #define BIT_SHIFT_P0HI4Q_HOST_IDX 0 #define BIT_MASK_P0HI4Q_HOST_IDX 0xfff #define BIT_P0HI4Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI4Q_HOST_IDX) << BIT_SHIFT_P0HI4Q_HOST_IDX) #define BITS_P0HI4Q_HOST_IDX \ (BIT_MASK_P0HI4Q_HOST_IDX << BIT_SHIFT_P0HI4Q_HOST_IDX) #define BIT_CLEAR_P0HI4Q_HOST_IDX(x) ((x) & (~BITS_P0HI4Q_HOST_IDX)) #define BIT_GET_P0HI4Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI4Q_HOST_IDX) & BIT_MASK_P0HI4Q_HOST_IDX) #define BIT_SET_P0HI4Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI4Q_HOST_IDX(x) | BIT_P0HI4Q_HOST_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI5Q_TXBD_IDX (Offset 0x03CC) */ #define BIT_SHIFT_HI5Q_HW_IDX 16 #define BIT_MASK_HI5Q_HW_IDX 0xfff #define BIT_HI5Q_HW_IDX(x) \ (((x) & BIT_MASK_HI5Q_HW_IDX) << BIT_SHIFT_HI5Q_HW_IDX) #define BITS_HI5Q_HW_IDX (BIT_MASK_HI5Q_HW_IDX << BIT_SHIFT_HI5Q_HW_IDX) #define BIT_CLEAR_HI5Q_HW_IDX(x) ((x) & (~BITS_HI5Q_HW_IDX)) #define BIT_GET_HI5Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_HI5Q_HW_IDX) & BIT_MASK_HI5Q_HW_IDX) #define BIT_SET_HI5Q_HW_IDX(x, v) \ (BIT_CLEAR_HI5Q_HW_IDX(x) | BIT_HI5Q_HW_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI5Q_TXBD_IDX (Offset 0x03CC) */ #define BIT_SHIFT_P0HI5Q_HW_IDX 16 #define BIT_MASK_P0HI5Q_HW_IDX 0xfff #define BIT_P0HI5Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI5Q_HW_IDX) << BIT_SHIFT_P0HI5Q_HW_IDX) #define BITS_P0HI5Q_HW_IDX (BIT_MASK_P0HI5Q_HW_IDX << BIT_SHIFT_P0HI5Q_HW_IDX) #define BIT_CLEAR_P0HI5Q_HW_IDX(x) ((x) & (~BITS_P0HI5Q_HW_IDX)) #define BIT_GET_P0HI5Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI5Q_HW_IDX) & BIT_MASK_P0HI5Q_HW_IDX) #define BIT_SET_P0HI5Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI5Q_HW_IDX(x) | BIT_P0HI5Q_HW_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI5Q_TXBD_IDX (Offset 0x03CC) */ #define BIT_SHIFT_HI5Q_HOST_IDX 0 #define BIT_MASK_HI5Q_HOST_IDX 0xfff #define BIT_HI5Q_HOST_IDX(x) \ (((x) & BIT_MASK_HI5Q_HOST_IDX) << BIT_SHIFT_HI5Q_HOST_IDX) #define BITS_HI5Q_HOST_IDX (BIT_MASK_HI5Q_HOST_IDX << BIT_SHIFT_HI5Q_HOST_IDX) #define BIT_CLEAR_HI5Q_HOST_IDX(x) ((x) & (~BITS_HI5Q_HOST_IDX)) #define BIT_GET_HI5Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_HI5Q_HOST_IDX) & BIT_MASK_HI5Q_HOST_IDX) #define BIT_SET_HI5Q_HOST_IDX(x, v) \ (BIT_CLEAR_HI5Q_HOST_IDX(x) | BIT_HI5Q_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI5Q_TXBD_IDX (Offset 0x03CC) */ #define BIT_SHIFT_P0HI5Q_HOST_IDX 0 #define BIT_MASK_P0HI5Q_HOST_IDX 0xfff #define BIT_P0HI5Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI5Q_HOST_IDX) << BIT_SHIFT_P0HI5Q_HOST_IDX) #define BITS_P0HI5Q_HOST_IDX \ (BIT_MASK_P0HI5Q_HOST_IDX << BIT_SHIFT_P0HI5Q_HOST_IDX) #define BIT_CLEAR_P0HI5Q_HOST_IDX(x) ((x) & (~BITS_P0HI5Q_HOST_IDX)) #define BIT_GET_P0HI5Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI5Q_HOST_IDX) & BIT_MASK_P0HI5Q_HOST_IDX) #define BIT_SET_P0HI5Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI5Q_HOST_IDX(x) | BIT_P0HI5Q_HOST_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI6Q_TXBD_IDX (Offset 0x03D0) */ #define BIT_SHIFT_HI6Q_HW_IDX 16 #define BIT_MASK_HI6Q_HW_IDX 0xfff #define BIT_HI6Q_HW_IDX(x) \ (((x) & BIT_MASK_HI6Q_HW_IDX) << BIT_SHIFT_HI6Q_HW_IDX) #define BITS_HI6Q_HW_IDX (BIT_MASK_HI6Q_HW_IDX << BIT_SHIFT_HI6Q_HW_IDX) #define BIT_CLEAR_HI6Q_HW_IDX(x) ((x) & (~BITS_HI6Q_HW_IDX)) #define BIT_GET_HI6Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_HI6Q_HW_IDX) & BIT_MASK_HI6Q_HW_IDX) #define BIT_SET_HI6Q_HW_IDX(x, v) \ (BIT_CLEAR_HI6Q_HW_IDX(x) | BIT_HI6Q_HW_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI6Q_TXBD_IDX (Offset 0x03D0) */ #define BIT_SHIFT_P0HI6Q_HW_IDX 16 #define BIT_MASK_P0HI6Q_HW_IDX 0xfff #define BIT_P0HI6Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI6Q_HW_IDX) << BIT_SHIFT_P0HI6Q_HW_IDX) #define BITS_P0HI6Q_HW_IDX (BIT_MASK_P0HI6Q_HW_IDX << BIT_SHIFT_P0HI6Q_HW_IDX) #define BIT_CLEAR_P0HI6Q_HW_IDX(x) ((x) & (~BITS_P0HI6Q_HW_IDX)) #define BIT_GET_P0HI6Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI6Q_HW_IDX) & BIT_MASK_P0HI6Q_HW_IDX) #define BIT_SET_P0HI6Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI6Q_HW_IDX(x) | BIT_P0HI6Q_HW_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI6Q_TXBD_IDX (Offset 0x03D0) */ #define BIT_SHIFT_HI6Q_HOST_IDX 0 #define BIT_MASK_HI6Q_HOST_IDX 0xfff #define BIT_HI6Q_HOST_IDX(x) \ (((x) & BIT_MASK_HI6Q_HOST_IDX) << BIT_SHIFT_HI6Q_HOST_IDX) #define BITS_HI6Q_HOST_IDX (BIT_MASK_HI6Q_HOST_IDX << BIT_SHIFT_HI6Q_HOST_IDX) #define BIT_CLEAR_HI6Q_HOST_IDX(x) ((x) & (~BITS_HI6Q_HOST_IDX)) #define BIT_GET_HI6Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_HI6Q_HOST_IDX) & BIT_MASK_HI6Q_HOST_IDX) #define BIT_SET_HI6Q_HOST_IDX(x, v) \ (BIT_CLEAR_HI6Q_HOST_IDX(x) | BIT_HI6Q_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI6Q_TXBD_IDX (Offset 0x03D0) */ #define BIT_SHIFT_P0HI6Q_HOST_IDX 0 #define BIT_MASK_P0HI6Q_HOST_IDX 0xfff #define BIT_P0HI6Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI6Q_HOST_IDX) << BIT_SHIFT_P0HI6Q_HOST_IDX) #define BITS_P0HI6Q_HOST_IDX \ (BIT_MASK_P0HI6Q_HOST_IDX << BIT_SHIFT_P0HI6Q_HOST_IDX) #define BIT_CLEAR_P0HI6Q_HOST_IDX(x) ((x) & (~BITS_P0HI6Q_HOST_IDX)) #define BIT_GET_P0HI6Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI6Q_HOST_IDX) & BIT_MASK_P0HI6Q_HOST_IDX) #define BIT_SET_P0HI6Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI6Q_HOST_IDX(x) | BIT_P0HI6Q_HOST_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI7Q_TXBD_IDX (Offset 0x03D4) */ #define BIT_SHIFT_HI7Q_HW_IDX 16 #define BIT_MASK_HI7Q_HW_IDX 0xfff #define BIT_HI7Q_HW_IDX(x) \ (((x) & BIT_MASK_HI7Q_HW_IDX) << BIT_SHIFT_HI7Q_HW_IDX) #define BITS_HI7Q_HW_IDX (BIT_MASK_HI7Q_HW_IDX << BIT_SHIFT_HI7Q_HW_IDX) #define BIT_CLEAR_HI7Q_HW_IDX(x) ((x) & (~BITS_HI7Q_HW_IDX)) #define BIT_GET_HI7Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_HI7Q_HW_IDX) & BIT_MASK_HI7Q_HW_IDX) #define BIT_SET_HI7Q_HW_IDX(x, v) \ (BIT_CLEAR_HI7Q_HW_IDX(x) | BIT_HI7Q_HW_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI7Q_TXBD_IDX (Offset 0x03D4) */ #define BIT_SHIFT_P0HI7Q_HW_IDX 16 #define BIT_MASK_P0HI7Q_HW_IDX 0xfff #define BIT_P0HI7Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI7Q_HW_IDX) << BIT_SHIFT_P0HI7Q_HW_IDX) #define BITS_P0HI7Q_HW_IDX (BIT_MASK_P0HI7Q_HW_IDX << BIT_SHIFT_P0HI7Q_HW_IDX) #define BIT_CLEAR_P0HI7Q_HW_IDX(x) ((x) & (~BITS_P0HI7Q_HW_IDX)) #define BIT_GET_P0HI7Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI7Q_HW_IDX) & BIT_MASK_P0HI7Q_HW_IDX) #define BIT_SET_P0HI7Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI7Q_HW_IDX(x) | BIT_P0HI7Q_HW_IDX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HI7Q_TXBD_IDX (Offset 0x03D4) */ #define BIT_SHIFT_HI7Q_HOST_IDX 0 #define BIT_MASK_HI7Q_HOST_IDX 0xfff #define BIT_HI7Q_HOST_IDX(x) \ (((x) & BIT_MASK_HI7Q_HOST_IDX) << BIT_SHIFT_HI7Q_HOST_IDX) #define BITS_HI7Q_HOST_IDX (BIT_MASK_HI7Q_HOST_IDX << BIT_SHIFT_HI7Q_HOST_IDX) #define BIT_CLEAR_HI7Q_HOST_IDX(x) ((x) & (~BITS_HI7Q_HOST_IDX)) #define BIT_GET_HI7Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_HI7Q_HOST_IDX) & BIT_MASK_HI7Q_HOST_IDX) #define BIT_SET_HI7Q_HOST_IDX(x, v) \ (BIT_CLEAR_HI7Q_HOST_IDX(x) | BIT_HI7Q_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI7Q_TXBD_IDX (Offset 0x03D4) */ #define BIT_SHIFT_P0HI7Q_HOST_IDX 0 #define BIT_MASK_P0HI7Q_HOST_IDX 0xfff #define BIT_P0HI7Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI7Q_HOST_IDX) << BIT_SHIFT_P0HI7Q_HOST_IDX) #define BITS_P0HI7Q_HOST_IDX \ (BIT_MASK_P0HI7Q_HOST_IDX << BIT_SHIFT_P0HI7Q_HOST_IDX) #define BIT_CLEAR_P0HI7Q_HOST_IDX(x) ((x) & (~BITS_P0HI7Q_HOST_IDX)) #define BIT_GET_P0HI7Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI7Q_HOST_IDX) & BIT_MASK_P0HI7Q_HOST_IDX) #define BIT_SET_P0HI7Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI7Q_HOST_IDX(x) | BIT_P0HI7Q_HOST_IDX(v)) /* 2 REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1 (Offset 0x03D8) */ #define BIT_DIS_TXDMA_PRE_V1 BIT(31) #define BIT_DIS_RXDMA_PRE_V1 BIT(30) #define BIT_SHIFT_HPS_CLKR_PCIE_V1 28 #define BIT_MASK_HPS_CLKR_PCIE_V1 0x3 #define BIT_HPS_CLKR_PCIE_V1(x) \ (((x) & BIT_MASK_HPS_CLKR_PCIE_V1) << BIT_SHIFT_HPS_CLKR_PCIE_V1) #define BITS_HPS_CLKR_PCIE_V1 \ (BIT_MASK_HPS_CLKR_PCIE_V1 << BIT_SHIFT_HPS_CLKR_PCIE_V1) #define BIT_CLEAR_HPS_CLKR_PCIE_V1(x) ((x) & (~BITS_HPS_CLKR_PCIE_V1)) #define BIT_GET_HPS_CLKR_PCIE_V1(x) \ (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_V1) & BIT_MASK_HPS_CLKR_PCIE_V1) #define BIT_SET_HPS_CLKR_PCIE_V1(x, v) \ (BIT_CLEAR_HPS_CLKR_PCIE_V1(x) | BIT_HPS_CLKR_PCIE_V1(v)) #define BIT_PCIE_INT_V1 BIT(27) #define BIT_TXFLAG_EXIT_L1_EN_V1 BIT(26) #define BIT_EN_RXDMA_ALIGN_V2 BIT(25) #define BIT_EN_TXDMA_ALIGN_V2 BIT(24) #define BIT_SHIFT_PCIE_HCPWM_V1 16 #define BIT_MASK_PCIE_HCPWM_V1 0xff #define BIT_PCIE_HCPWM_V1(x) \ (((x) & BIT_MASK_PCIE_HCPWM_V1) << BIT_SHIFT_PCIE_HCPWM_V1) #define BITS_PCIE_HCPWM_V1 (BIT_MASK_PCIE_HCPWM_V1 << BIT_SHIFT_PCIE_HCPWM_V1) #define BIT_CLEAR_PCIE_HCPWM_V1(x) ((x) & (~BITS_PCIE_HCPWM_V1)) #define BIT_GET_PCIE_HCPWM_V1(x) \ (((x) >> BIT_SHIFT_PCIE_HCPWM_V1) & BIT_MASK_PCIE_HCPWM_V1) #define BIT_SET_PCIE_HCPWM_V1(x, v) \ (BIT_CLEAR_PCIE_HCPWM_V1(x) | BIT_PCIE_HCPWM_V1(v)) #define BIT_SHIFT_PCIE_HRPWM_V1 8 #define BIT_MASK_PCIE_HRPWM_V1 0xff #define BIT_PCIE_HRPWM_V1(x) \ (((x) & BIT_MASK_PCIE_HRPWM_V1) << BIT_SHIFT_PCIE_HRPWM_V1) #define BITS_PCIE_HRPWM_V1 (BIT_MASK_PCIE_HRPWM_V1 << BIT_SHIFT_PCIE_HRPWM_V1) #define BIT_CLEAR_PCIE_HRPWM_V1(x) ((x) & (~BITS_PCIE_HRPWM_V1)) #define BIT_GET_PCIE_HRPWM_V1(x) \ (((x) >> BIT_SHIFT_PCIE_HRPWM_V1) & BIT_MASK_PCIE_HRPWM_V1) #define BIT_SET_PCIE_HRPWM_V1(x, v) \ (BIT_CLEAR_PCIE_HRPWM_V1(x) | BIT_PCIE_HRPWM_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DBG_SEL_V1 (Offset 0x03D8) */ #define BIT_SHIFT_DBG_SEL 0 #define BIT_MASK_DBG_SEL 0xff #define BIT_DBG_SEL(x) (((x) & BIT_MASK_DBG_SEL) << BIT_SHIFT_DBG_SEL) #define BITS_DBG_SEL (BIT_MASK_DBG_SEL << BIT_SHIFT_DBG_SEL) #define BIT_CLEAR_DBG_SEL(x) ((x) & (~BITS_DBG_SEL)) #define BIT_GET_DBG_SEL(x) (((x) >> BIT_SHIFT_DBG_SEL) & BIT_MASK_DBG_SEL) #define BIT_SET_DBG_SEL(x, v) (BIT_CLEAR_DBG_SEL(x) | BIT_DBG_SEL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PCIE_HRPWM1_V1 (Offset 0x03D9) */ #define BIT_SHIFT_PCIE_HRPWM 0 #define BIT_MASK_PCIE_HRPWM 0xff #define BIT_PCIE_HRPWM(x) (((x) & BIT_MASK_PCIE_HRPWM) << BIT_SHIFT_PCIE_HRPWM) #define BITS_PCIE_HRPWM (BIT_MASK_PCIE_HRPWM << BIT_SHIFT_PCIE_HRPWM) #define BIT_CLEAR_PCIE_HRPWM(x) ((x) & (~BITS_PCIE_HRPWM)) #define BIT_GET_PCIE_HRPWM(x) \ (((x) >> BIT_SHIFT_PCIE_HRPWM) & BIT_MASK_PCIE_HRPWM) #define BIT_SET_PCIE_HRPWM(x, v) (BIT_CLEAR_PCIE_HRPWM(x) | BIT_PCIE_HRPWM(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HCI_HRPWM1_V1 (Offset 0x03D9) */ #define BIT_SHIFT_HCI_HRPWM 0 #define BIT_MASK_HCI_HRPWM 0xff #define BIT_HCI_HRPWM(x) (((x) & BIT_MASK_HCI_HRPWM) << BIT_SHIFT_HCI_HRPWM) #define BITS_HCI_HRPWM (BIT_MASK_HCI_HRPWM << BIT_SHIFT_HCI_HRPWM) #define BIT_CLEAR_HCI_HRPWM(x) ((x) & (~BITS_HCI_HRPWM)) #define BIT_GET_HCI_HRPWM(x) (((x) >> BIT_SHIFT_HCI_HRPWM) & BIT_MASK_HCI_HRPWM) #define BIT_SET_HCI_HRPWM(x, v) (BIT_CLEAR_HCI_HRPWM(x) | BIT_HCI_HRPWM(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PCIE_HCPWM1_V1 (Offset 0x03DA) */ #define BIT_SHIFT_PCIE_HCPWM 0 #define BIT_MASK_PCIE_HCPWM 0xff #define BIT_PCIE_HCPWM(x) (((x) & BIT_MASK_PCIE_HCPWM) << BIT_SHIFT_PCIE_HCPWM) #define BITS_PCIE_HCPWM (BIT_MASK_PCIE_HCPWM << BIT_SHIFT_PCIE_HCPWM) #define BIT_CLEAR_PCIE_HCPWM(x) ((x) & (~BITS_PCIE_HCPWM)) #define BIT_GET_PCIE_HCPWM(x) \ (((x) >> BIT_SHIFT_PCIE_HCPWM) & BIT_MASK_PCIE_HCPWM) #define BIT_SET_PCIE_HCPWM(x, v) (BIT_CLEAR_PCIE_HCPWM(x) | BIT_PCIE_HCPWM(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HCI_HCPWM1_V1 (Offset 0x03DA) */ #define BIT_SHIFT_HCI_HCPWM 0 #define BIT_MASK_HCI_HCPWM 0xff #define BIT_HCI_HCPWM(x) (((x) & BIT_MASK_HCI_HCPWM) << BIT_SHIFT_HCI_HCPWM) #define BITS_HCI_HCPWM (BIT_MASK_HCI_HCPWM << BIT_SHIFT_HCI_HCPWM) #define BIT_CLEAR_HCI_HCPWM(x) ((x) & (~BITS_HCI_HCPWM)) #define BIT_GET_HCI_HCPWM(x) (((x) >> BIT_SHIFT_HCI_HCPWM) & BIT_MASK_HCI_HCPWM) #define BIT_SET_HCI_HCPWM(x, v) (BIT_CLEAR_HCI_HCPWM(x) | BIT_HCI_HCPWM(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ #define BIT_SHIFT_HPS_CLKR_PCIE 4 #define BIT_MASK_HPS_CLKR_PCIE 0x3 #define BIT_HPS_CLKR_PCIE(x) \ (((x) & BIT_MASK_HPS_CLKR_PCIE) << BIT_SHIFT_HPS_CLKR_PCIE) #define BITS_HPS_CLKR_PCIE (BIT_MASK_HPS_CLKR_PCIE << BIT_SHIFT_HPS_CLKR_PCIE) #define BIT_CLEAR_HPS_CLKR_PCIE(x) ((x) & (~BITS_HPS_CLKR_PCIE)) #define BIT_GET_HPS_CLKR_PCIE(x) \ (((x) >> BIT_SHIFT_HPS_CLKR_PCIE) & BIT_MASK_HPS_CLKR_PCIE) #define BIT_SET_HPS_CLKR_PCIE(x, v) \ (BIT_CLEAR_HPS_CLKR_PCIE(x) | BIT_HPS_CLKR_PCIE(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HCI_CTRL2 (Offset 0x03DB) */ #define BIT_SHIFT_HPS_CLKR_HCI 4 #define BIT_MASK_HPS_CLKR_HCI 0x3 #define BIT_HPS_CLKR_HCI(x) \ (((x) & BIT_MASK_HPS_CLKR_HCI) << BIT_SHIFT_HPS_CLKR_HCI) #define BITS_HPS_CLKR_HCI (BIT_MASK_HPS_CLKR_HCI << BIT_SHIFT_HPS_CLKR_HCI) #define BIT_CLEAR_HPS_CLKR_HCI(x) ((x) & (~BITS_HPS_CLKR_HCI)) #define BIT_GET_HPS_CLKR_HCI(x) \ (((x) >> BIT_SHIFT_HPS_CLKR_HCI) & BIT_MASK_HPS_CLKR_HCI) #define BIT_SET_HPS_CLKR_HCI(x, v) \ (BIT_CLEAR_HPS_CLKR_HCI(x) | BIT_HPS_CLKR_HCI(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ #define BIT_PCIE_INT BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HCI_CTRL2 (Offset 0x03DB) */ #define BIT_HCI_INT BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ #define BIT_EN_RXDMA_ALIGN BIT(1) #define BIT_EN_TXDMA_ALIGN BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PCIE_HRPWM2_HCPWM2_V1 (Offset 0x03DC) */ #define BIT_SHIFT_PCIE_HCPWM2_V1 16 #define BIT_MASK_PCIE_HCPWM2_V1 0xffff #define BIT_PCIE_HCPWM2_V1(x) \ (((x) & BIT_MASK_PCIE_HCPWM2_V1) << BIT_SHIFT_PCIE_HCPWM2_V1) #define BITS_PCIE_HCPWM2_V1 \ (BIT_MASK_PCIE_HCPWM2_V1 << BIT_SHIFT_PCIE_HCPWM2_V1) #define BIT_CLEAR_PCIE_HCPWM2_V1(x) ((x) & (~BITS_PCIE_HCPWM2_V1)) #define BIT_GET_PCIE_HCPWM2_V1(x) \ (((x) >> BIT_SHIFT_PCIE_HCPWM2_V1) & BIT_MASK_PCIE_HCPWM2_V1) #define BIT_SET_PCIE_HCPWM2_V1(x, v) \ (BIT_CLEAR_PCIE_HCPWM2_V1(x) | BIT_PCIE_HCPWM2_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PCIE_HRPWM2_V1 (Offset 0x03DC) */ #define BIT_SHIFT_PCIE_HRPWM2 0 #define BIT_MASK_PCIE_HRPWM2 0xffff #define BIT_PCIE_HRPWM2(x) \ (((x) & BIT_MASK_PCIE_HRPWM2) << BIT_SHIFT_PCIE_HRPWM2) #define BITS_PCIE_HRPWM2 (BIT_MASK_PCIE_HRPWM2 << BIT_SHIFT_PCIE_HRPWM2) #define BIT_CLEAR_PCIE_HRPWM2(x) ((x) & (~BITS_PCIE_HRPWM2)) #define BIT_GET_PCIE_HRPWM2(x) \ (((x) >> BIT_SHIFT_PCIE_HRPWM2) & BIT_MASK_PCIE_HRPWM2) #define BIT_SET_PCIE_HRPWM2(x, v) \ (BIT_CLEAR_PCIE_HRPWM2(x) | BIT_PCIE_HRPWM2(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HCI_HRPWM2_V1 (Offset 0x03DC) */ #define BIT_SHIFT_HCI_HRPWM2 0 #define BIT_MASK_HCI_HRPWM2 0xffff #define BIT_HCI_HRPWM2(x) (((x) & BIT_MASK_HCI_HRPWM2) << BIT_SHIFT_HCI_HRPWM2) #define BITS_HCI_HRPWM2 (BIT_MASK_HCI_HRPWM2 << BIT_SHIFT_HCI_HRPWM2) #define BIT_CLEAR_HCI_HRPWM2(x) ((x) & (~BITS_HCI_HRPWM2)) #define BIT_GET_HCI_HRPWM2(x) \ (((x) >> BIT_SHIFT_HCI_HRPWM2) & BIT_MASK_HCI_HRPWM2) #define BIT_SET_HCI_HRPWM2(x, v) (BIT_CLEAR_HCI_HRPWM2(x) | BIT_HCI_HRPWM2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PCIE_HCPWM2_V1 (Offset 0x03DE) */ #define BIT_SHIFT_PCIE_HCPWM2 0 #define BIT_MASK_PCIE_HCPWM2 0xffff #define BIT_PCIE_HCPWM2(x) \ (((x) & BIT_MASK_PCIE_HCPWM2) << BIT_SHIFT_PCIE_HCPWM2) #define BITS_PCIE_HCPWM2 (BIT_MASK_PCIE_HCPWM2 << BIT_SHIFT_PCIE_HCPWM2) #define BIT_CLEAR_PCIE_HCPWM2(x) ((x) & (~BITS_PCIE_HCPWM2)) #define BIT_GET_PCIE_HCPWM2(x) \ (((x) >> BIT_SHIFT_PCIE_HCPWM2) & BIT_MASK_PCIE_HCPWM2) #define BIT_SET_PCIE_HCPWM2(x, v) \ (BIT_CLEAR_PCIE_HCPWM2(x) | BIT_PCIE_HCPWM2(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HCI_HCPWM2_V1 (Offset 0x03DE) */ #define BIT_SHIFT_HCI_HCPWM2 0 #define BIT_MASK_HCI_HCPWM2 0xffff #define BIT_HCI_HCPWM2(x) (((x) & BIT_MASK_HCI_HCPWM2) << BIT_SHIFT_HCI_HCPWM2) #define BITS_HCI_HCPWM2 (BIT_MASK_HCI_HCPWM2 << BIT_SHIFT_HCI_HCPWM2) #define BIT_CLEAR_HCI_HCPWM2(x) ((x) & (~BITS_HCI_HCPWM2)) #define BIT_GET_HCI_HCPWM2(x) \ (((x) >> BIT_SHIFT_HCI_HCPWM2) & BIT_MASK_HCI_HCPWM2) #define BIT_SET_HCI_HCPWM2(x, v) (BIT_CLEAR_HCI_HCPWM2(x) | BIT_HCI_HCPWM2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PCIE_H2C_MSG_V1 (Offset 0x03E0) */ #define BIT_AC7Q_EMPTY BIT(7) #define BIT_AC6Q_EMPTY BIT(6) #define BIT_AC5Q_EMPTY BIT(5) #define BIT_AC4Q_EMPTY BIT(4) #define BIT_AC3Q_EMPTY BIT(3) #define BIT_AC2Q_EMPTY BIT(2) #define BIT_AC1Q_EMPTY BIT(1) #define BIT_SHIFT_DRV2FW_INFO 0 #define BIT_MASK_DRV2FW_INFO 0xffffffffL #define BIT_DRV2FW_INFO(x) \ (((x) & BIT_MASK_DRV2FW_INFO) << BIT_SHIFT_DRV2FW_INFO) #define BITS_DRV2FW_INFO (BIT_MASK_DRV2FW_INFO << BIT_SHIFT_DRV2FW_INFO) #define BIT_CLEAR_DRV2FW_INFO(x) ((x) & (~BITS_DRV2FW_INFO)) #define BIT_GET_DRV2FW_INFO(x) \ (((x) >> BIT_SHIFT_DRV2FW_INFO) & BIT_MASK_DRV2FW_INFO) #define BIT_SET_DRV2FW_INFO(x, v) \ (BIT_CLEAR_DRV2FW_INFO(x) | BIT_DRV2FW_INFO(v)) #define BIT_AC0Q_EMPTY BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PCIE_C2H_MSG_V1 (Offset 0x03E4) */ #define BIT_SHIFT_HCI_PCIE_C2H_MSG 0 #define BIT_MASK_HCI_PCIE_C2H_MSG 0xffffffffL #define BIT_HCI_PCIE_C2H_MSG(x) \ (((x) & BIT_MASK_HCI_PCIE_C2H_MSG) << BIT_SHIFT_HCI_PCIE_C2H_MSG) #define BITS_HCI_PCIE_C2H_MSG \ (BIT_MASK_HCI_PCIE_C2H_MSG << BIT_SHIFT_HCI_PCIE_C2H_MSG) #define BIT_CLEAR_HCI_PCIE_C2H_MSG(x) ((x) & (~BITS_HCI_PCIE_C2H_MSG)) #define BIT_GET_HCI_PCIE_C2H_MSG(x) \ (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG) & BIT_MASK_HCI_PCIE_C2H_MSG) #define BIT_SET_HCI_PCIE_C2H_MSG(x, v) \ (BIT_CLEAR_HCI_PCIE_C2H_MSG(x) | BIT_HCI_PCIE_C2H_MSG(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HCI_C2H_MSG_V1 (Offset 0x03E4) */ #define BIT_SHIFT_HCI_C2H_MSG 0 #define BIT_MASK_HCI_C2H_MSG 0xffffffffL #define BIT_HCI_C2H_MSG(x) \ (((x) & BIT_MASK_HCI_C2H_MSG) << BIT_SHIFT_HCI_C2H_MSG) #define BITS_HCI_C2H_MSG (BIT_MASK_HCI_C2H_MSG << BIT_SHIFT_HCI_C2H_MSG) #define BIT_CLEAR_HCI_C2H_MSG(x) ((x) & (~BITS_HCI_C2H_MSG)) #define BIT_GET_HCI_C2H_MSG(x) \ (((x) >> BIT_SHIFT_HCI_C2H_MSG) & BIT_MASK_HCI_C2H_MSG) #define BIT_SET_HCI_C2H_MSG(x, v) \ (BIT_CLEAR_HCI_C2H_MSG(x) | BIT_HCI_C2H_MSG(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DBI_WDATA_V1 (Offset 0x03E8) */ #define BIT_SHIFT_DBI_WDATA 0 #define BIT_MASK_DBI_WDATA 0xffffffffL #define BIT_DBI_WDATA(x) (((x) & BIT_MASK_DBI_WDATA) << BIT_SHIFT_DBI_WDATA) #define BITS_DBI_WDATA (BIT_MASK_DBI_WDATA << BIT_SHIFT_DBI_WDATA) #define BIT_CLEAR_DBI_WDATA(x) ((x) & (~BITS_DBI_WDATA)) #define BIT_GET_DBI_WDATA(x) (((x) >> BIT_SHIFT_DBI_WDATA) & BIT_MASK_DBI_WDATA) #define BIT_SET_DBI_WDATA(x, v) (BIT_CLEAR_DBI_WDATA(x) | BIT_DBI_WDATA(v)) /* 2 REG_DBI_RDATA_V1 (Offset 0x03EC) */ #define BIT_SHIFT_DBI_RDATA 0 #define BIT_MASK_DBI_RDATA 0xffffffffL #define BIT_DBI_RDATA(x) (((x) & BIT_MASK_DBI_RDATA) << BIT_SHIFT_DBI_RDATA) #define BITS_DBI_RDATA (BIT_MASK_DBI_RDATA << BIT_SHIFT_DBI_RDATA) #define BIT_CLEAR_DBI_RDATA(x) ((x) & (~BITS_DBI_RDATA)) #define BIT_GET_DBI_RDATA(x) (((x) >> BIT_SHIFT_DBI_RDATA) & BIT_MASK_DBI_RDATA) #define BIT_SET_DBI_RDATA(x, v) (BIT_CLEAR_DBI_RDATA(x) | BIT_DBI_RDATA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DBI_FLAG_V1 (Offset 0x03F0) */ #define BIT_SHIFT_LOOPBACK_DBG_SEL 28 #define BIT_MASK_LOOPBACK_DBG_SEL 0xf #define BIT_LOOPBACK_DBG_SEL(x) \ (((x) & BIT_MASK_LOOPBACK_DBG_SEL) << BIT_SHIFT_LOOPBACK_DBG_SEL) #define BITS_LOOPBACK_DBG_SEL \ (BIT_MASK_LOOPBACK_DBG_SEL << BIT_SHIFT_LOOPBACK_DBG_SEL) #define BIT_CLEAR_LOOPBACK_DBG_SEL(x) ((x) & (~BITS_LOOPBACK_DBG_SEL)) #define BIT_GET_LOOPBACK_DBG_SEL(x) \ (((x) >> BIT_SHIFT_LOOPBACK_DBG_SEL) & BIT_MASK_LOOPBACK_DBG_SEL) #define BIT_SET_LOOPBACK_DBG_SEL(x, v) \ (BIT_CLEAR_LOOPBACK_DBG_SEL(x) | BIT_LOOPBACK_DBG_SEL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DBI_FLAG_V1 (Offset 0x03F0) */ #define BIT_EN_STUCK_DBG BIT(26) #define BIT_RX_STUCK BIT(25) #define BIT_TX_STUCK BIT(24) #define BIT_DBI_RFLAG BIT(17) #define BIT_DBI_WFLAG BIT(16) #define BIT_SHIFT_DBI_WREN 12 #define BIT_MASK_DBI_WREN 0xf #define BIT_DBI_WREN(x) (((x) & BIT_MASK_DBI_WREN) << BIT_SHIFT_DBI_WREN) #define BITS_DBI_WREN (BIT_MASK_DBI_WREN << BIT_SHIFT_DBI_WREN) #define BIT_CLEAR_DBI_WREN(x) ((x) & (~BITS_DBI_WREN)) #define BIT_GET_DBI_WREN(x) (((x) >> BIT_SHIFT_DBI_WREN) & BIT_MASK_DBI_WREN) #define BIT_SET_DBI_WREN(x, v) (BIT_CLEAR_DBI_WREN(x) | BIT_DBI_WREN(v)) #define BIT_SHIFT_DBI_ADDR 0 #define BIT_MASK_DBI_ADDR 0xfff #define BIT_DBI_ADDR(x) (((x) & BIT_MASK_DBI_ADDR) << BIT_SHIFT_DBI_ADDR) #define BITS_DBI_ADDR (BIT_MASK_DBI_ADDR << BIT_SHIFT_DBI_ADDR) #define BIT_CLEAR_DBI_ADDR(x) ((x) & (~BITS_DBI_ADDR)) #define BIT_GET_DBI_ADDR(x) (((x) >> BIT_SHIFT_DBI_ADDR) & BIT_MASK_DBI_ADDR) #define BIT_SET_DBI_ADDR(x, v) (BIT_CLEAR_DBI_ADDR(x) | BIT_DBI_ADDR(v)) /* 2 REG_MDIO_V1 (Offset 0x03F4) */ #define BIT_SHIFT_MDIO_RDATA 16 #define BIT_MASK_MDIO_RDATA 0xffff #define BIT_MDIO_RDATA(x) (((x) & BIT_MASK_MDIO_RDATA) << BIT_SHIFT_MDIO_RDATA) #define BITS_MDIO_RDATA (BIT_MASK_MDIO_RDATA << BIT_SHIFT_MDIO_RDATA) #define BIT_CLEAR_MDIO_RDATA(x) ((x) & (~BITS_MDIO_RDATA)) #define BIT_GET_MDIO_RDATA(x) \ (((x) >> BIT_SHIFT_MDIO_RDATA) & BIT_MASK_MDIO_RDATA) #define BIT_SET_MDIO_RDATA(x, v) (BIT_CLEAR_MDIO_RDATA(x) | BIT_MDIO_RDATA(v)) #define BIT_SHIFT_MDIO_WDATA 0 #define BIT_MASK_MDIO_WDATA 0xffff #define BIT_MDIO_WDATA(x) (((x) & BIT_MASK_MDIO_WDATA) << BIT_SHIFT_MDIO_WDATA) #define BITS_MDIO_WDATA (BIT_MASK_MDIO_WDATA << BIT_SHIFT_MDIO_WDATA) #define BIT_CLEAR_MDIO_WDATA(x) ((x) & (~BITS_MDIO_WDATA)) #define BIT_GET_MDIO_WDATA(x) \ (((x) >> BIT_SHIFT_MDIO_WDATA) & BIT_MASK_MDIO_WDATA) #define BIT_SET_MDIO_WDATA(x, v) (BIT_CLEAR_MDIO_WDATA(x) | BIT_MDIO_WDATA(v)) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_BUS_MIX_CFG (Offset 0x03F8) */ #define BIT_SHIFT_DELAY_TIME 24 #define BIT_MASK_DELAY_TIME 0xff #define BIT_DELAY_TIME(x) (((x) & BIT_MASK_DELAY_TIME) << BIT_SHIFT_DELAY_TIME) #define BITS_DELAY_TIME (BIT_MASK_DELAY_TIME << BIT_SHIFT_DELAY_TIME) #define BIT_CLEAR_DELAY_TIME(x) ((x) & (~BITS_DELAY_TIME)) #define BIT_GET_DELAY_TIME(x) \ (((x) >> BIT_SHIFT_DELAY_TIME) & BIT_MASK_DELAY_TIME) #define BIT_SET_DELAY_TIME(x, v) (BIT_CLEAR_DELAY_TIME(x) | BIT_DELAY_TIME(v)) #define BIT_RX_TIMER_DELAY_EN BIT(17) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */ #define BIT_EN_WATCH_DOG BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_MDIO2_V1 (Offset 0x03F8) */ #define BIT_ECRC_EN BIT(7) #define BIT_MDIO_RFLAG BIT(6) #define BIT_MDIO_WFLAG BIT(5) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_MDIO2_V1 (Offset 0x03F8) */ #define BIT_SHIFT_MDIO_ADDR 0 #define BIT_MASK_MDIO_ADDR 0x1f #define BIT_MDIO_ADDR(x) (((x) & BIT_MASK_MDIO_ADDR) << BIT_SHIFT_MDIO_ADDR) #define BITS_MDIO_ADDR (BIT_MASK_MDIO_ADDR << BIT_SHIFT_MDIO_ADDR) #define BIT_CLEAR_MDIO_ADDR(x) ((x) & (~BITS_MDIO_ADDR)) #define BIT_GET_MDIO_ADDR(x) (((x) >> BIT_SHIFT_MDIO_ADDR) & BIT_MASK_MDIO_ADDR) #define BIT_SET_MDIO_ADDR(x, v) (BIT_CLEAR_MDIO_ADDR(x) | BIT_MDIO_ADDR(v)) #define BIT_SHIFT_TXFAIL_DROPCNT 0 #define BIT_MASK_TXFAIL_DROPCNT 0xffff #define BIT_TXFAIL_DROPCNT(x) \ (((x) & BIT_MASK_TXFAIL_DROPCNT) << BIT_SHIFT_TXFAIL_DROPCNT) #define BITS_TXFAIL_DROPCNT \ (BIT_MASK_TXFAIL_DROPCNT << BIT_SHIFT_TXFAIL_DROPCNT) #define BIT_CLEAR_TXFAIL_DROPCNT(x) ((x) & (~BITS_TXFAIL_DROPCNT)) #define BIT_GET_TXFAIL_DROPCNT(x) \ (((x) >> BIT_SHIFT_TXFAIL_DROPCNT) & BIT_MASK_TXFAIL_DROPCNT) #define BIT_SET_TXFAIL_DROPCNT(x, v) \ (BIT_CLEAR_TXFAIL_DROPCNT(x) | BIT_TXFAIL_DROPCNT(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */ #define BIT_SHIFT_MDIO_REG_ADDR_V1 0 #define BIT_MASK_MDIO_REG_ADDR_V1 0x1f #define BIT_MDIO_REG_ADDR_V1(x) \ (((x) & BIT_MASK_MDIO_REG_ADDR_V1) << BIT_SHIFT_MDIO_REG_ADDR_V1) #define BITS_MDIO_REG_ADDR_V1 \ (BIT_MASK_MDIO_REG_ADDR_V1 << BIT_SHIFT_MDIO_REG_ADDR_V1) #define BIT_CLEAR_MDIO_REG_ADDR_V1(x) ((x) & (~BITS_MDIO_REG_ADDR_V1)) #define BIT_GET_MDIO_REG_ADDR_V1(x) \ (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1) & BIT_MASK_MDIO_REG_ADDR_V1) #define BIT_SET_MDIO_REG_ADDR_V1(x, v) \ (BIT_CLEAR_MDIO_REG_ADDR_V1(x) | BIT_MDIO_REG_ADDR_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_RXRST_BACKDOOR BIT(31) #define BIT_TXRST_BACKDOOR BIT(30) #define BIT_RXIDX_RSTB BIT(29) #define BIT_TXIDX_RSTB BIT(28) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_SHIFT_WATCH_DOG_TIMER 28 #define BIT_MASK_WATCH_DOG_TIMER 0xf #define BIT_WATCH_DOG_TIMER(x) \ (((x) & BIT_MASK_WATCH_DOG_TIMER) << BIT_SHIFT_WATCH_DOG_TIMER) #define BITS_WATCH_DOG_TIMER \ (BIT_MASK_WATCH_DOG_TIMER << BIT_SHIFT_WATCH_DOG_TIMER) #define BIT_CLEAR_WATCH_DOG_TIMER(x) ((x) & (~BITS_WATCH_DOG_TIMER)) #define BIT_GET_WATCH_DOG_TIMER(x) \ (((x) >> BIT_SHIFT_WATCH_DOG_TIMER) & BIT_MASK_WATCH_DOG_TIMER) #define BIT_SET_WATCH_DOG_TIMER(x, v) \ (BIT_CLEAR_WATCH_DOG_TIMER(x) | BIT_WATCH_DOG_TIMER(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_DROP_NEXT_RXPKT BIT(27) #define BIT_SHORT_CORE_RST_SEL BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_EXCEPT_RESUME_EN BIT(25) #define BIT_EXCEPT_RESUME_FLAG BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_ALIGN_MTU BIT(23) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_EN_ALIGN_MTU BIT(23) #endif #if (HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_EARLY_TAG_RETURN BIT(22) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_SHIFT_LATENCY_CONTROL 21 #define BIT_MASK_LATENCY_CONTROL 0x3 #define BIT_LATENCY_CONTROL(x) \ (((x) & BIT_MASK_LATENCY_CONTROL) << BIT_SHIFT_LATENCY_CONTROL) #define BITS_LATENCY_CONTROL \ (BIT_MASK_LATENCY_CONTROL << BIT_SHIFT_LATENCY_CONTROL) #define BIT_CLEAR_LATENCY_CONTROL(x) ((x) & (~BITS_LATENCY_CONTROL)) #define BIT_GET_LATENCY_CONTROL(x) \ (((x) >> BIT_SHIFT_LATENCY_CONTROL) & BIT_MASK_LATENCY_CONTROL) #define BIT_SET_LATENCY_CONTROL(x, v) \ (BIT_CLEAR_LATENCY_CONTROL(x) | BIT_LATENCY_CONTROL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_HOST_GEN2_SUPPORT BIT(20) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_SHIFT_TXDMA_ERR_FLAG 16 #define BIT_MASK_TXDMA_ERR_FLAG 0xf #define BIT_TXDMA_ERR_FLAG(x) \ (((x) & BIT_MASK_TXDMA_ERR_FLAG) << BIT_SHIFT_TXDMA_ERR_FLAG) #define BITS_TXDMA_ERR_FLAG \ (BIT_MASK_TXDMA_ERR_FLAG << BIT_SHIFT_TXDMA_ERR_FLAG) #define BIT_CLEAR_TXDMA_ERR_FLAG(x) ((x) & (~BITS_TXDMA_ERR_FLAG)) #define BIT_GET_TXDMA_ERR_FLAG(x) \ (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG) & BIT_MASK_TXDMA_ERR_FLAG) #define BIT_SET_TXDMA_ERR_FLAG(x, v) \ (BIT_CLEAR_TXDMA_ERR_FLAG(x) | BIT_TXDMA_ERR_FLAG(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_SHIFT_TXDMA_ERR_FLAG_V1 15 #define BIT_MASK_TXDMA_ERR_FLAG_V1 0x1f #define BIT_TXDMA_ERR_FLAG_V1(x) \ (((x) & BIT_MASK_TXDMA_ERR_FLAG_V1) << BIT_SHIFT_TXDMA_ERR_FLAG_V1) #define BITS_TXDMA_ERR_FLAG_V1 \ (BIT_MASK_TXDMA_ERR_FLAG_V1 << BIT_SHIFT_TXDMA_ERR_FLAG_V1) #define BIT_CLEAR_TXDMA_ERR_FLAG_V1(x) ((x) & (~BITS_TXDMA_ERR_FLAG_V1)) #define BIT_GET_TXDMA_ERR_FLAG_V1(x) \ (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_V1) & BIT_MASK_TXDMA_ERR_FLAG_V1) #define BIT_SET_TXDMA_ERR_FLAG_V1(x, v) \ (BIT_CLEAR_TXDMA_ERR_FLAG_V1(x) | BIT_TXDMA_ERR_FLAG_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_SHIFT_EARLY_MODE_SEL 12 #define BIT_MASK_EARLY_MODE_SEL 0xf #define BIT_EARLY_MODE_SEL(x) \ (((x) & BIT_MASK_EARLY_MODE_SEL) << BIT_SHIFT_EARLY_MODE_SEL) #define BITS_EARLY_MODE_SEL \ (BIT_MASK_EARLY_MODE_SEL << BIT_SHIFT_EARLY_MODE_SEL) #define BIT_CLEAR_EARLY_MODE_SEL(x) ((x) & (~BITS_EARLY_MODE_SEL)) #define BIT_GET_EARLY_MODE_SEL(x) \ (((x) >> BIT_SHIFT_EARLY_MODE_SEL) & BIT_MASK_EARLY_MODE_SEL) #define BIT_SET_EARLY_MODE_SEL(x, v) \ (BIT_CLEAR_EARLY_MODE_SEL(x) | BIT_EARLY_MODE_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_EPHY_RX50_EN BIT(11) #define BIT_SHIFT_MSI_TIMEOUT_ID_V1 8 #define BIT_MASK_MSI_TIMEOUT_ID_V1 0x7 #define BIT_MSI_TIMEOUT_ID_V1(x) \ (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1) << BIT_SHIFT_MSI_TIMEOUT_ID_V1) #define BITS_MSI_TIMEOUT_ID_V1 \ (BIT_MASK_MSI_TIMEOUT_ID_V1 << BIT_SHIFT_MSI_TIMEOUT_ID_V1) #define BIT_CLEAR_MSI_TIMEOUT_ID_V1(x) ((x) & (~BITS_MSI_TIMEOUT_ID_V1)) #define BIT_GET_MSI_TIMEOUT_ID_V1(x) \ (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1) & BIT_MASK_MSI_TIMEOUT_ID_V1) #define BIT_SET_MSI_TIMEOUT_ID_V1(x, v) \ (BIT_CLEAR_MSI_TIMEOUT_ID_V1(x) | BIT_MSI_TIMEOUT_ID_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_SHIFT_RXDMA_ERR_CNT 8 #define BIT_MASK_RXDMA_ERR_CNT 0xff #define BIT_RXDMA_ERR_CNT(x) \ (((x) & BIT_MASK_RXDMA_ERR_CNT) << BIT_SHIFT_RXDMA_ERR_CNT) #define BITS_RXDMA_ERR_CNT (BIT_MASK_RXDMA_ERR_CNT << BIT_SHIFT_RXDMA_ERR_CNT) #define BIT_CLEAR_RXDMA_ERR_CNT(x) ((x) & (~BITS_RXDMA_ERR_CNT)) #define BIT_GET_RXDMA_ERR_CNT(x) \ (((x) >> BIT_SHIFT_RXDMA_ERR_CNT) & BIT_MASK_RXDMA_ERR_CNT) #define BIT_SET_RXDMA_ERR_CNT(x, v) \ (BIT_CLEAR_RXDMA_ERR_CNT(x) | BIT_RXDMA_ERR_CNT(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_RADDR_RD BIT(7) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_TXDMA_ERR_HANDLE_REQ BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_EN_MUL_TAG BIT(6) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_TXDMA_ERROR_PS BIT(6) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_L1OFF_PWR_OFF_EN BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_EN_EARLY_MODE BIT(5) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_EN_TXDMA_STUCK_ERR_HANDLE BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_L0S_LINK_OFF BIT(4) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_EN_TXDMA_RTN_ERR_HANDLE BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_ACT_LINK_OFF BIT(3) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_RXDMA_ERR_HANDLE_REQ BIT(3) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_EN_SLOW_MAC_TX BIT(2) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_RXDMA_ERROR_PS BIT(2) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_EN_SLOW_MAC_RX BIT(1) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ #define BIT_EN_RXDMA_STUCK_ERR_HANDLE BIT(1) #define BIT_EN_SLOW_MAC_HW BIT(0) #define BIT_EN_RXDMA_RTN_ERR_HANDLE BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q0_INFO (Offset 0x0400) */ #define BIT_SHIFT_QUEUEMACID_Q0_V1 25 #define BIT_MASK_QUEUEMACID_Q0_V1 0x7f #define BIT_QUEUEMACID_Q0_V1(x) \ (((x) & BIT_MASK_QUEUEMACID_Q0_V1) << BIT_SHIFT_QUEUEMACID_Q0_V1) #define BITS_QUEUEMACID_Q0_V1 \ (BIT_MASK_QUEUEMACID_Q0_V1 << BIT_SHIFT_QUEUEMACID_Q0_V1) #define BIT_CLEAR_QUEUEMACID_Q0_V1(x) ((x) & (~BITS_QUEUEMACID_Q0_V1)) #define BIT_GET_QUEUEMACID_Q0_V1(x) \ (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1) & BIT_MASK_QUEUEMACID_Q0_V1) #define BIT_SET_QUEUEMACID_Q0_V1(x, v) \ (BIT_CLEAR_QUEUEMACID_Q0_V1(x) | BIT_QUEUEMACID_Q0_V1(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_QUEUE_INFO1 (Offset 0x0400) */ #define BIT_SHIFT_QUEUEMACID 25 #define BIT_MASK_QUEUEMACID 0x7f #define BIT_QUEUEMACID(x) (((x) & BIT_MASK_QUEUEMACID) << BIT_SHIFT_QUEUEMACID) #define BITS_QUEUEMACID (BIT_MASK_QUEUEMACID << BIT_SHIFT_QUEUEMACID) #define BIT_CLEAR_QUEUEMACID(x) ((x) & (~BITS_QUEUEMACID)) #define BIT_GET_QUEUEMACID(x) \ (((x) >> BIT_SHIFT_QUEUEMACID) & BIT_MASK_QUEUEMACID) #define BIT_SET_QUEUEMACID(x, v) (BIT_CLEAR_QUEUEMACID(x) | BIT_QUEUEMACID(v)) #define BIT_DONE BIT(24) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q0_INFO (Offset 0x0400) */ #define BIT_SHIFT_QUEUEAC_Q0_V1 23 #define BIT_MASK_QUEUEAC_Q0_V1 0x3 #define BIT_QUEUEAC_Q0_V1(x) \ (((x) & BIT_MASK_QUEUEAC_Q0_V1) << BIT_SHIFT_QUEUEAC_Q0_V1) #define BITS_QUEUEAC_Q0_V1 (BIT_MASK_QUEUEAC_Q0_V1 << BIT_SHIFT_QUEUEAC_Q0_V1) #define BIT_CLEAR_QUEUEAC_Q0_V1(x) ((x) & (~BITS_QUEUEAC_Q0_V1)) #define BIT_GET_QUEUEAC_Q0_V1(x) \ (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1) & BIT_MASK_QUEUEAC_Q0_V1) #define BIT_SET_QUEUEAC_Q0_V1(x, v) \ (BIT_CLEAR_QUEUEAC_Q0_V1(x) | BIT_QUEUEAC_Q0_V1(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_QUEUE_INFO1 (Offset 0x0400) */ #define BIT_SHIFT_QUEUEAC 23 #define BIT_MASK_QUEUEAC 0x3 #define BIT_QUEUEAC(x) (((x) & BIT_MASK_QUEUEAC) << BIT_SHIFT_QUEUEAC) #define BITS_QUEUEAC (BIT_MASK_QUEUEAC << BIT_SHIFT_QUEUEAC) #define BIT_CLEAR_QUEUEAC(x) ((x) & (~BITS_QUEUEAC)) #define BIT_GET_QUEUEAC(x) (((x) >> BIT_SHIFT_QUEUEAC) & BIT_MASK_QUEUEAC) #define BIT_SET_QUEUEAC(x, v) (BIT_CLEAR_QUEUEAC(x) | BIT_QUEUEAC(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q0_INFO (Offset 0x0400) */ #define BIT_TIDEMPTY_Q0_V1 BIT(22) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_QUEUE_INFO1 (Offset 0x0400) */ #define BIT_TIDEMPTY BIT(22) #define BIT_SHIFT_ACCWBITEN 20 #define BIT_MASK_ACCWBITEN 0xf #define BIT_ACCWBITEN(x) (((x) & BIT_MASK_ACCWBITEN) << BIT_SHIFT_ACCWBITEN) #define BITS_ACCWBITEN (BIT_MASK_ACCWBITEN << BIT_SHIFT_ACCWBITEN) #define BIT_CLEAR_ACCWBITEN(x) ((x) & (~BITS_ACCWBITEN)) #define BIT_GET_ACCWBITEN(x) (((x) >> BIT_SHIFT_ACCWBITEN) & BIT_MASK_ACCWBITEN) #define BIT_SET_ACCWBITEN(x, v) (BIT_CLEAR_ACCWBITEN(x) | BIT_ACCWBITEN(v)) #define BIT_BCNQ_EMPTY_V1 BIT(19) #define BIT_HIQ_EMPTY_V1 BIT(18) #define BIT_MQQ_EMPTY_V1 BIT(17) #define BIT_SHIFT_COL_CNT 16 #define BIT_MASK_COL_CNT 0xf #define BIT_COL_CNT(x) (((x) & BIT_MASK_COL_CNT) << BIT_SHIFT_COL_CNT) #define BITS_COL_CNT (BIT_MASK_COL_CNT << BIT_SHIFT_COL_CNT) #define BIT_CLEAR_COL_CNT(x) ((x) & (~BITS_COL_CNT)) #define BIT_GET_COL_CNT(x) (((x) >> BIT_SHIFT_COL_CNT) & BIT_MASK_COL_CNT) #define BIT_SET_COL_CNT(x, v) (BIT_CLEAR_COL_CNT(x) | BIT_COL_CNT(v)) #define BIT_CPU_MGT_EMPTY BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q0_INFO (Offset 0x0400) */ #define BIT_SHIFT_TAIL_PKT_Q0_V1 15 #define BIT_MASK_TAIL_PKT_Q0_V1 0xff #define BIT_TAIL_PKT_Q0_V1(x) \ (((x) & BIT_MASK_TAIL_PKT_Q0_V1) << BIT_SHIFT_TAIL_PKT_Q0_V1) #define BITS_TAIL_PKT_Q0_V1 \ (BIT_MASK_TAIL_PKT_Q0_V1 << BIT_SHIFT_TAIL_PKT_Q0_V1) #define BIT_CLEAR_TAIL_PKT_Q0_V1(x) ((x) & (~BITS_TAIL_PKT_Q0_V1)) #define BIT_GET_TAIL_PKT_Q0_V1(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V1) & BIT_MASK_TAIL_PKT_Q0_V1) #define BIT_SET_TAIL_PKT_Q0_V1(x, v) \ (BIT_CLEAR_TAIL_PKT_Q0_V1(x) | BIT_TAIL_PKT_Q0_V1(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_QUEUE_INFO1 (Offset 0x0400) */ #define BIT_AC_MACID_NOT_SAME BIT(15) #define BIT_SHIFT_GROUP_TABLE_ID 12 #define BIT_MASK_GROUP_TABLE_ID 0x7 #define BIT_GROUP_TABLE_ID(x) \ (((x) & BIT_MASK_GROUP_TABLE_ID) << BIT_SHIFT_GROUP_TABLE_ID) #define BITS_GROUP_TABLE_ID \ (BIT_MASK_GROUP_TABLE_ID << BIT_SHIFT_GROUP_TABLE_ID) #define BIT_CLEAR_GROUP_TABLE_ID(x) ((x) & (~BITS_GROUP_TABLE_ID)) #define BIT_GET_GROUP_TABLE_ID(x) \ (((x) >> BIT_SHIFT_GROUP_TABLE_ID) & BIT_MASK_GROUP_TABLE_ID) #define BIT_SET_GROUP_TABLE_ID(x, v) \ (BIT_CLEAR_GROUP_TABLE_ID(x) | BIT_GROUP_TABLE_ID(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q0_INFO (Offset 0x0400) */ #define BIT_SHIFT_TAIL_PKT_Q0_V2 11 #define BIT_MASK_TAIL_PKT_Q0_V2 0x7ff #define BIT_TAIL_PKT_Q0_V2(x) \ (((x) & BIT_MASK_TAIL_PKT_Q0_V2) << BIT_SHIFT_TAIL_PKT_Q0_V2) #define BITS_TAIL_PKT_Q0_V2 \ (BIT_MASK_TAIL_PKT_Q0_V2 << BIT_SHIFT_TAIL_PKT_Q0_V2) #define BIT_CLEAR_TAIL_PKT_Q0_V2(x) ((x) & (~BITS_TAIL_PKT_Q0_V2)) #define BIT_GET_TAIL_PKT_Q0_V2(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2) & BIT_MASK_TAIL_PKT_Q0_V2) #define BIT_SET_TAIL_PKT_Q0_V2(x, v) \ (BIT_CLEAR_TAIL_PKT_Q0_V2(x) | BIT_TAIL_PKT_Q0_V2(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_QUEUE_INFO1 (Offset 0x0400) */ #define BIT_SHIFT_TAIL_PKT 11 #define BIT_MASK_TAIL_PKT 0x7ff #define BIT_TAIL_PKT(x) (((x) & BIT_MASK_TAIL_PKT) << BIT_SHIFT_TAIL_PKT) #define BITS_TAIL_PKT (BIT_MASK_TAIL_PKT << BIT_SHIFT_TAIL_PKT) #define BIT_CLEAR_TAIL_PKT(x) ((x) & (~BITS_TAIL_PKT)) #define BIT_GET_TAIL_PKT(x) (((x) >> BIT_SHIFT_TAIL_PKT) & BIT_MASK_TAIL_PKT) #define BIT_SET_TAIL_PKT(x, v) (BIT_CLEAR_TAIL_PKT(x) | BIT_TAIL_PKT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q0_INFO (Offset 0x0400) */ #define BIT_SHIFT_PKT_NUM_Q0_V1 8 #define BIT_MASK_PKT_NUM_Q0_V1 0x7f #define BIT_PKT_NUM_Q0_V1(x) \ (((x) & BIT_MASK_PKT_NUM_Q0_V1) << BIT_SHIFT_PKT_NUM_Q0_V1) #define BITS_PKT_NUM_Q0_V1 (BIT_MASK_PKT_NUM_Q0_V1 << BIT_SHIFT_PKT_NUM_Q0_V1) #define BIT_CLEAR_PKT_NUM_Q0_V1(x) ((x) & (~BITS_PKT_NUM_Q0_V1)) #define BIT_GET_PKT_NUM_Q0_V1(x) \ (((x) >> BIT_SHIFT_PKT_NUM_Q0_V1) & BIT_MASK_PKT_NUM_Q0_V1) #define BIT_SET_PKT_NUM_Q0_V1(x, v) \ (BIT_CLEAR_PKT_NUM_Q0_V1(x) | BIT_PKT_NUM_Q0_V1(v)) #define BIT_SHIFT_HEAD_PKT_Q0 0 #define BIT_MASK_HEAD_PKT_Q0 0xff #define BIT_HEAD_PKT_Q0(x) \ (((x) & BIT_MASK_HEAD_PKT_Q0) << BIT_SHIFT_HEAD_PKT_Q0) #define BITS_HEAD_PKT_Q0 (BIT_MASK_HEAD_PKT_Q0 << BIT_SHIFT_HEAD_PKT_Q0) #define BIT_CLEAR_HEAD_PKT_Q0(x) ((x) & (~BITS_HEAD_PKT_Q0)) #define BIT_GET_HEAD_PKT_Q0(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_Q0) & BIT_MASK_HEAD_PKT_Q0) #define BIT_SET_HEAD_PKT_Q0(x, v) \ (BIT_CLEAR_HEAD_PKT_Q0(x) | BIT_HEAD_PKT_Q0(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q0_INFO (Offset 0x0400) */ #define BIT_SHIFT_HEAD_PKT_Q0_V1 0 #define BIT_MASK_HEAD_PKT_Q0_V1 0x7ff #define BIT_HEAD_PKT_Q0_V1(x) \ (((x) & BIT_MASK_HEAD_PKT_Q0_V1) << BIT_SHIFT_HEAD_PKT_Q0_V1) #define BITS_HEAD_PKT_Q0_V1 \ (BIT_MASK_HEAD_PKT_Q0_V1 << BIT_SHIFT_HEAD_PKT_Q0_V1) #define BIT_CLEAR_HEAD_PKT_Q0_V1(x) ((x) & (~BITS_HEAD_PKT_Q0_V1)) #define BIT_GET_HEAD_PKT_Q0_V1(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1) & BIT_MASK_HEAD_PKT_Q0_V1) #define BIT_SET_HEAD_PKT_Q0_V1(x, v) \ (BIT_CLEAR_HEAD_PKT_Q0_V1(x) | BIT_HEAD_PKT_Q0_V1(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_QUEUE_INFO1 (Offset 0x0400) */ #define BIT_SHIFT_HEAD_PKT 0 #define BIT_MASK_HEAD_PKT 0x7ff #define BIT_HEAD_PKT(x) (((x) & BIT_MASK_HEAD_PKT) << BIT_SHIFT_HEAD_PKT) #define BITS_HEAD_PKT (BIT_MASK_HEAD_PKT << BIT_SHIFT_HEAD_PKT) #define BIT_CLEAR_HEAD_PKT(x) ((x) & (~BITS_HEAD_PKT)) #define BIT_GET_HEAD_PKT(x) (((x) >> BIT_SHIFT_HEAD_PKT) & BIT_MASK_HEAD_PKT) #define BIT_SET_HEAD_PKT(x, v) (BIT_CLEAR_HEAD_PKT(x) | BIT_HEAD_PKT(v)) #define BIT_SHIFT_PKT_NUMBER 0 #define BIT_MASK_PKT_NUMBER 0xfff #define BIT_PKT_NUMBER(x) (((x) & BIT_MASK_PKT_NUMBER) << BIT_SHIFT_PKT_NUMBER) #define BITS_PKT_NUMBER (BIT_MASK_PKT_NUMBER << BIT_SHIFT_PKT_NUMBER) #define BIT_CLEAR_PKT_NUMBER(x) ((x) & (~BITS_PKT_NUMBER)) #define BIT_GET_PKT_NUMBER(x) \ (((x) >> BIT_SHIFT_PKT_NUMBER) & BIT_MASK_PKT_NUMBER) #define BIT_SET_PKT_NUMBER(x, v) (BIT_CLEAR_PKT_NUMBER(x) | BIT_PKT_NUMBER(v)) #define BIT_SHIFT_ACCW 0 #define BIT_MASK_ACCW 0x3ff #define BIT_ACCW(x) (((x) & BIT_MASK_ACCW) << BIT_SHIFT_ACCW) #define BITS_ACCW (BIT_MASK_ACCW << BIT_SHIFT_ACCW) #define BIT_CLEAR_ACCW(x) ((x) & (~BITS_ACCW)) #define BIT_GET_ACCW(x) (((x) >> BIT_SHIFT_ACCW) & BIT_MASK_ACCW) #define BIT_SET_ACCW(x, v) (BIT_CLEAR_ACCW(x) | BIT_ACCW(v)) #define BIT_SHIFT_QINFO_INDEX 0 #define BIT_MASK_QINFO_INDEX 0x1f #define BIT_QINFO_INDEX(x) \ (((x) & BIT_MASK_QINFO_INDEX) << BIT_SHIFT_QINFO_INDEX) #define BITS_QINFO_INDEX (BIT_MASK_QINFO_INDEX << BIT_SHIFT_QINFO_INDEX) #define BIT_CLEAR_QINFO_INDEX(x) ((x) & (~BITS_QINFO_INDEX)) #define BIT_GET_QINFO_INDEX(x) \ (((x) >> BIT_SHIFT_QINFO_INDEX) & BIT_MASK_QINFO_INDEX) #define BIT_SET_QINFO_INDEX(x, v) \ (BIT_CLEAR_QINFO_INDEX(x) | BIT_QINFO_INDEX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_QUEUELIST_INFO0 (Offset 0x0400) */ #define BIT_SHIFT_QINFO0 0 #define BIT_MASK_QINFO0 0xffffffffL #define BIT_QINFO0(x) (((x) & BIT_MASK_QINFO0) << BIT_SHIFT_QINFO0) #define BITS_QINFO0 (BIT_MASK_QINFO0 << BIT_SHIFT_QINFO0) #define BIT_CLEAR_QINFO0(x) ((x) & (~BITS_QINFO0)) #define BIT_GET_QINFO0(x) (((x) >> BIT_SHIFT_QINFO0) & BIT_MASK_QINFO0) #define BIT_SET_QINFO0(x, v) (BIT_CLEAR_QINFO0(x) | BIT_QINFO0(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q1_INFO (Offset 0x0404) */ #define BIT_SHIFT_QUEUEMACID_Q1_V1 25 #define BIT_MASK_QUEUEMACID_Q1_V1 0x7f #define BIT_QUEUEMACID_Q1_V1(x) \ (((x) & BIT_MASK_QUEUEMACID_Q1_V1) << BIT_SHIFT_QUEUEMACID_Q1_V1) #define BITS_QUEUEMACID_Q1_V1 \ (BIT_MASK_QUEUEMACID_Q1_V1 << BIT_SHIFT_QUEUEMACID_Q1_V1) #define BIT_CLEAR_QUEUEMACID_Q1_V1(x) ((x) & (~BITS_QUEUEMACID_Q1_V1)) #define BIT_GET_QUEUEMACID_Q1_V1(x) \ (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1) & BIT_MASK_QUEUEMACID_Q1_V1) #define BIT_SET_QUEUEMACID_Q1_V1(x, v) \ (BIT_CLEAR_QUEUEMACID_Q1_V1(x) | BIT_QUEUEMACID_Q1_V1(v)) #define BIT_SHIFT_QUEUEAC_Q1_V1 23 #define BIT_MASK_QUEUEAC_Q1_V1 0x3 #define BIT_QUEUEAC_Q1_V1(x) \ (((x) & BIT_MASK_QUEUEAC_Q1_V1) << BIT_SHIFT_QUEUEAC_Q1_V1) #define BITS_QUEUEAC_Q1_V1 (BIT_MASK_QUEUEAC_Q1_V1 << BIT_SHIFT_QUEUEAC_Q1_V1) #define BIT_CLEAR_QUEUEAC_Q1_V1(x) ((x) & (~BITS_QUEUEAC_Q1_V1)) #define BIT_GET_QUEUEAC_Q1_V1(x) \ (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1) & BIT_MASK_QUEUEAC_Q1_V1) #define BIT_SET_QUEUEAC_Q1_V1(x, v) \ (BIT_CLEAR_QUEUEAC_Q1_V1(x) | BIT_QUEUEAC_Q1_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q1_INFO (Offset 0x0404) */ #define BIT_TIDEMPTY_Q1_V1 BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q1_INFO (Offset 0x0404) */ #define BIT_SHIFT_TAIL_PKT_Q1_V1 15 #define BIT_MASK_TAIL_PKT_Q1_V1 0xff #define BIT_TAIL_PKT_Q1_V1(x) \ (((x) & BIT_MASK_TAIL_PKT_Q1_V1) << BIT_SHIFT_TAIL_PKT_Q1_V1) #define BITS_TAIL_PKT_Q1_V1 \ (BIT_MASK_TAIL_PKT_Q1_V1 << BIT_SHIFT_TAIL_PKT_Q1_V1) #define BIT_CLEAR_TAIL_PKT_Q1_V1(x) ((x) & (~BITS_TAIL_PKT_Q1_V1)) #define BIT_GET_TAIL_PKT_Q1_V1(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V1) & BIT_MASK_TAIL_PKT_Q1_V1) #define BIT_SET_TAIL_PKT_Q1_V1(x, v) \ (BIT_CLEAR_TAIL_PKT_Q1_V1(x) | BIT_TAIL_PKT_Q1_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q1_INFO (Offset 0x0404) */ #define BIT_SHIFT_TAIL_PKT_Q1_V2 11 #define BIT_MASK_TAIL_PKT_Q1_V2 0x7ff #define BIT_TAIL_PKT_Q1_V2(x) \ (((x) & BIT_MASK_TAIL_PKT_Q1_V2) << BIT_SHIFT_TAIL_PKT_Q1_V2) #define BITS_TAIL_PKT_Q1_V2 \ (BIT_MASK_TAIL_PKT_Q1_V2 << BIT_SHIFT_TAIL_PKT_Q1_V2) #define BIT_CLEAR_TAIL_PKT_Q1_V2(x) ((x) & (~BITS_TAIL_PKT_Q1_V2)) #define BIT_GET_TAIL_PKT_Q1_V2(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2) & BIT_MASK_TAIL_PKT_Q1_V2) #define BIT_SET_TAIL_PKT_Q1_V2(x, v) \ (BIT_CLEAR_TAIL_PKT_Q1_V2(x) | BIT_TAIL_PKT_Q1_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q1_INFO (Offset 0x0404) */ #define BIT_SHIFT_PKT_NUM_Q1_V1 8 #define BIT_MASK_PKT_NUM_Q1_V1 0x7f #define BIT_PKT_NUM_Q1_V1(x) \ (((x) & BIT_MASK_PKT_NUM_Q1_V1) << BIT_SHIFT_PKT_NUM_Q1_V1) #define BITS_PKT_NUM_Q1_V1 (BIT_MASK_PKT_NUM_Q1_V1 << BIT_SHIFT_PKT_NUM_Q1_V1) #define BIT_CLEAR_PKT_NUM_Q1_V1(x) ((x) & (~BITS_PKT_NUM_Q1_V1)) #define BIT_GET_PKT_NUM_Q1_V1(x) \ (((x) >> BIT_SHIFT_PKT_NUM_Q1_V1) & BIT_MASK_PKT_NUM_Q1_V1) #define BIT_SET_PKT_NUM_Q1_V1(x, v) \ (BIT_CLEAR_PKT_NUM_Q1_V1(x) | BIT_PKT_NUM_Q1_V1(v)) #define BIT_SHIFT_HEAD_PKT_Q1 0 #define BIT_MASK_HEAD_PKT_Q1 0xff #define BIT_HEAD_PKT_Q1(x) \ (((x) & BIT_MASK_HEAD_PKT_Q1) << BIT_SHIFT_HEAD_PKT_Q1) #define BITS_HEAD_PKT_Q1 (BIT_MASK_HEAD_PKT_Q1 << BIT_SHIFT_HEAD_PKT_Q1) #define BIT_CLEAR_HEAD_PKT_Q1(x) ((x) & (~BITS_HEAD_PKT_Q1)) #define BIT_GET_HEAD_PKT_Q1(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_Q1) & BIT_MASK_HEAD_PKT_Q1) #define BIT_SET_HEAD_PKT_Q1(x, v) \ (BIT_CLEAR_HEAD_PKT_Q1(x) | BIT_HEAD_PKT_Q1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q1_INFO (Offset 0x0404) */ #define BIT_SHIFT_HEAD_PKT_Q1_V1 0 #define BIT_MASK_HEAD_PKT_Q1_V1 0x7ff #define BIT_HEAD_PKT_Q1_V1(x) \ (((x) & BIT_MASK_HEAD_PKT_Q1_V1) << BIT_SHIFT_HEAD_PKT_Q1_V1) #define BITS_HEAD_PKT_Q1_V1 \ (BIT_MASK_HEAD_PKT_Q1_V1 << BIT_SHIFT_HEAD_PKT_Q1_V1) #define BIT_CLEAR_HEAD_PKT_Q1_V1(x) ((x) & (~BITS_HEAD_PKT_Q1_V1)) #define BIT_GET_HEAD_PKT_Q1_V1(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1) & BIT_MASK_HEAD_PKT_Q1_V1) #define BIT_SET_HEAD_PKT_Q1_V1(x, v) \ (BIT_CLEAR_HEAD_PKT_Q1_V1(x) | BIT_HEAD_PKT_Q1_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_QUEUELIST_INFO1 (Offset 0x0404) */ #define BIT_SHIFT_QINFO1 0 #define BIT_MASK_QINFO1 0xffffffffL #define BIT_QINFO1(x) (((x) & BIT_MASK_QINFO1) << BIT_SHIFT_QINFO1) #define BITS_QINFO1 (BIT_MASK_QINFO1 << BIT_SHIFT_QINFO1) #define BIT_CLEAR_QINFO1(x) ((x) & (~BITS_QINFO1)) #define BIT_GET_QINFO1(x) (((x) >> BIT_SHIFT_QINFO1) & BIT_MASK_QINFO1) #define BIT_SET_QINFO1(x, v) (BIT_CLEAR_QINFO1(x) | BIT_QINFO1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q2_INFO (Offset 0x0408) */ #define BIT_SHIFT_QUEUEMACID_Q2_V1 25 #define BIT_MASK_QUEUEMACID_Q2_V1 0x7f #define BIT_QUEUEMACID_Q2_V1(x) \ (((x) & BIT_MASK_QUEUEMACID_Q2_V1) << BIT_SHIFT_QUEUEMACID_Q2_V1) #define BITS_QUEUEMACID_Q2_V1 \ (BIT_MASK_QUEUEMACID_Q2_V1 << BIT_SHIFT_QUEUEMACID_Q2_V1) #define BIT_CLEAR_QUEUEMACID_Q2_V1(x) ((x) & (~BITS_QUEUEMACID_Q2_V1)) #define BIT_GET_QUEUEMACID_Q2_V1(x) \ (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1) & BIT_MASK_QUEUEMACID_Q2_V1) #define BIT_SET_QUEUEMACID_Q2_V1(x, v) \ (BIT_CLEAR_QUEUEMACID_Q2_V1(x) | BIT_QUEUEMACID_Q2_V1(v)) #define BIT_SHIFT_QUEUEAC_Q2_V1 23 #define BIT_MASK_QUEUEAC_Q2_V1 0x3 #define BIT_QUEUEAC_Q2_V1(x) \ (((x) & BIT_MASK_QUEUEAC_Q2_V1) << BIT_SHIFT_QUEUEAC_Q2_V1) #define BITS_QUEUEAC_Q2_V1 (BIT_MASK_QUEUEAC_Q2_V1 << BIT_SHIFT_QUEUEAC_Q2_V1) #define BIT_CLEAR_QUEUEAC_Q2_V1(x) ((x) & (~BITS_QUEUEAC_Q2_V1)) #define BIT_GET_QUEUEAC_Q2_V1(x) \ (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1) & BIT_MASK_QUEUEAC_Q2_V1) #define BIT_SET_QUEUEAC_Q2_V1(x, v) \ (BIT_CLEAR_QUEUEAC_Q2_V1(x) | BIT_QUEUEAC_Q2_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q2_INFO (Offset 0x0408) */ #define BIT_TIDEMPTY_Q2_V1 BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q2_INFO (Offset 0x0408) */ #define BIT_SHIFT_TAIL_PKT_Q2_V1 15 #define BIT_MASK_TAIL_PKT_Q2_V1 0xff #define BIT_TAIL_PKT_Q2_V1(x) \ (((x) & BIT_MASK_TAIL_PKT_Q2_V1) << BIT_SHIFT_TAIL_PKT_Q2_V1) #define BITS_TAIL_PKT_Q2_V1 \ (BIT_MASK_TAIL_PKT_Q2_V1 << BIT_SHIFT_TAIL_PKT_Q2_V1) #define BIT_CLEAR_TAIL_PKT_Q2_V1(x) ((x) & (~BITS_TAIL_PKT_Q2_V1)) #define BIT_GET_TAIL_PKT_Q2_V1(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V1) & BIT_MASK_TAIL_PKT_Q2_V1) #define BIT_SET_TAIL_PKT_Q2_V1(x, v) \ (BIT_CLEAR_TAIL_PKT_Q2_V1(x) | BIT_TAIL_PKT_Q2_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q2_INFO (Offset 0x0408) */ #define BIT_SHIFT_TAIL_PKT_Q2_V2 11 #define BIT_MASK_TAIL_PKT_Q2_V2 0x7ff #define BIT_TAIL_PKT_Q2_V2(x) \ (((x) & BIT_MASK_TAIL_PKT_Q2_V2) << BIT_SHIFT_TAIL_PKT_Q2_V2) #define BITS_TAIL_PKT_Q2_V2 \ (BIT_MASK_TAIL_PKT_Q2_V2 << BIT_SHIFT_TAIL_PKT_Q2_V2) #define BIT_CLEAR_TAIL_PKT_Q2_V2(x) ((x) & (~BITS_TAIL_PKT_Q2_V2)) #define BIT_GET_TAIL_PKT_Q2_V2(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2) & BIT_MASK_TAIL_PKT_Q2_V2) #define BIT_SET_TAIL_PKT_Q2_V2(x, v) \ (BIT_CLEAR_TAIL_PKT_Q2_V2(x) | BIT_TAIL_PKT_Q2_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q2_INFO (Offset 0x0408) */ #define BIT_SHIFT_PKT_NUM_Q2_V1 8 #define BIT_MASK_PKT_NUM_Q2_V1 0x7f #define BIT_PKT_NUM_Q2_V1(x) \ (((x) & BIT_MASK_PKT_NUM_Q2_V1) << BIT_SHIFT_PKT_NUM_Q2_V1) #define BITS_PKT_NUM_Q2_V1 (BIT_MASK_PKT_NUM_Q2_V1 << BIT_SHIFT_PKT_NUM_Q2_V1) #define BIT_CLEAR_PKT_NUM_Q2_V1(x) ((x) & (~BITS_PKT_NUM_Q2_V1)) #define BIT_GET_PKT_NUM_Q2_V1(x) \ (((x) >> BIT_SHIFT_PKT_NUM_Q2_V1) & BIT_MASK_PKT_NUM_Q2_V1) #define BIT_SET_PKT_NUM_Q2_V1(x, v) \ (BIT_CLEAR_PKT_NUM_Q2_V1(x) | BIT_PKT_NUM_Q2_V1(v)) #define BIT_SHIFT_HEAD_PKT_Q2 0 #define BIT_MASK_HEAD_PKT_Q2 0xff #define BIT_HEAD_PKT_Q2(x) \ (((x) & BIT_MASK_HEAD_PKT_Q2) << BIT_SHIFT_HEAD_PKT_Q2) #define BITS_HEAD_PKT_Q2 (BIT_MASK_HEAD_PKT_Q2 << BIT_SHIFT_HEAD_PKT_Q2) #define BIT_CLEAR_HEAD_PKT_Q2(x) ((x) & (~BITS_HEAD_PKT_Q2)) #define BIT_GET_HEAD_PKT_Q2(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_Q2) & BIT_MASK_HEAD_PKT_Q2) #define BIT_SET_HEAD_PKT_Q2(x, v) \ (BIT_CLEAR_HEAD_PKT_Q2(x) | BIT_HEAD_PKT_Q2(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q2_INFO (Offset 0x0408) */ #define BIT_SHIFT_HEAD_PKT_Q2_V1 0 #define BIT_MASK_HEAD_PKT_Q2_V1 0x7ff #define BIT_HEAD_PKT_Q2_V1(x) \ (((x) & BIT_MASK_HEAD_PKT_Q2_V1) << BIT_SHIFT_HEAD_PKT_Q2_V1) #define BITS_HEAD_PKT_Q2_V1 \ (BIT_MASK_HEAD_PKT_Q2_V1 << BIT_SHIFT_HEAD_PKT_Q2_V1) #define BIT_CLEAR_HEAD_PKT_Q2_V1(x) ((x) & (~BITS_HEAD_PKT_Q2_V1)) #define BIT_GET_HEAD_PKT_Q2_V1(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1) & BIT_MASK_HEAD_PKT_Q2_V1) #define BIT_SET_HEAD_PKT_Q2_V1(x, v) \ (BIT_CLEAR_HEAD_PKT_Q2_V1(x) | BIT_HEAD_PKT_Q2_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_QUEUELIST_INFO2 (Offset 0x0408) */ #define BIT_SHIFT_QINFO2 0 #define BIT_MASK_QINFO2 0xffffffffL #define BIT_QINFO2(x) (((x) & BIT_MASK_QINFO2) << BIT_SHIFT_QINFO2) #define BITS_QINFO2 (BIT_MASK_QINFO2 << BIT_SHIFT_QINFO2) #define BIT_CLEAR_QINFO2(x) ((x) & (~BITS_QINFO2)) #define BIT_GET_QINFO2(x) (((x) >> BIT_SHIFT_QINFO2) & BIT_MASK_QINFO2) #define BIT_SET_QINFO2(x, v) (BIT_CLEAR_QINFO2(x) | BIT_QINFO2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q3_INFO (Offset 0x040C) */ #define BIT_SHIFT_QUEUEMACID_Q3_V1 25 #define BIT_MASK_QUEUEMACID_Q3_V1 0x7f #define BIT_QUEUEMACID_Q3_V1(x) \ (((x) & BIT_MASK_QUEUEMACID_Q3_V1) << BIT_SHIFT_QUEUEMACID_Q3_V1) #define BITS_QUEUEMACID_Q3_V1 \ (BIT_MASK_QUEUEMACID_Q3_V1 << BIT_SHIFT_QUEUEMACID_Q3_V1) #define BIT_CLEAR_QUEUEMACID_Q3_V1(x) ((x) & (~BITS_QUEUEMACID_Q3_V1)) #define BIT_GET_QUEUEMACID_Q3_V1(x) \ (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1) & BIT_MASK_QUEUEMACID_Q3_V1) #define BIT_SET_QUEUEMACID_Q3_V1(x, v) \ (BIT_CLEAR_QUEUEMACID_Q3_V1(x) | BIT_QUEUEMACID_Q3_V1(v)) #define BIT_SHIFT_QUEUEAC_Q3_V1 23 #define BIT_MASK_QUEUEAC_Q3_V1 0x3 #define BIT_QUEUEAC_Q3_V1(x) \ (((x) & BIT_MASK_QUEUEAC_Q3_V1) << BIT_SHIFT_QUEUEAC_Q3_V1) #define BITS_QUEUEAC_Q3_V1 (BIT_MASK_QUEUEAC_Q3_V1 << BIT_SHIFT_QUEUEAC_Q3_V1) #define BIT_CLEAR_QUEUEAC_Q3_V1(x) ((x) & (~BITS_QUEUEAC_Q3_V1)) #define BIT_GET_QUEUEAC_Q3_V1(x) \ (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1) & BIT_MASK_QUEUEAC_Q3_V1) #define BIT_SET_QUEUEAC_Q3_V1(x, v) \ (BIT_CLEAR_QUEUEAC_Q3_V1(x) | BIT_QUEUEAC_Q3_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q3_INFO (Offset 0x040C) */ #define BIT_TIDEMPTY_Q3_V1 BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q3_INFO (Offset 0x040C) */ #define BIT_SHIFT_TAIL_PKT_Q3_V1 15 #define BIT_MASK_TAIL_PKT_Q3_V1 0xff #define BIT_TAIL_PKT_Q3_V1(x) \ (((x) & BIT_MASK_TAIL_PKT_Q3_V1) << BIT_SHIFT_TAIL_PKT_Q3_V1) #define BITS_TAIL_PKT_Q3_V1 \ (BIT_MASK_TAIL_PKT_Q3_V1 << BIT_SHIFT_TAIL_PKT_Q3_V1) #define BIT_CLEAR_TAIL_PKT_Q3_V1(x) ((x) & (~BITS_TAIL_PKT_Q3_V1)) #define BIT_GET_TAIL_PKT_Q3_V1(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V1) & BIT_MASK_TAIL_PKT_Q3_V1) #define BIT_SET_TAIL_PKT_Q3_V1(x, v) \ (BIT_CLEAR_TAIL_PKT_Q3_V1(x) | BIT_TAIL_PKT_Q3_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q3_INFO (Offset 0x040C) */ #define BIT_SHIFT_TAIL_PKT_Q3_V2 11 #define BIT_MASK_TAIL_PKT_Q3_V2 0x7ff #define BIT_TAIL_PKT_Q3_V2(x) \ (((x) & BIT_MASK_TAIL_PKT_Q3_V2) << BIT_SHIFT_TAIL_PKT_Q3_V2) #define BITS_TAIL_PKT_Q3_V2 \ (BIT_MASK_TAIL_PKT_Q3_V2 << BIT_SHIFT_TAIL_PKT_Q3_V2) #define BIT_CLEAR_TAIL_PKT_Q3_V2(x) ((x) & (~BITS_TAIL_PKT_Q3_V2)) #define BIT_GET_TAIL_PKT_Q3_V2(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2) & BIT_MASK_TAIL_PKT_Q3_V2) #define BIT_SET_TAIL_PKT_Q3_V2(x, v) \ (BIT_CLEAR_TAIL_PKT_Q3_V2(x) | BIT_TAIL_PKT_Q3_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q3_INFO (Offset 0x040C) */ #define BIT_SHIFT_PKT_NUM_Q3_V1 8 #define BIT_MASK_PKT_NUM_Q3_V1 0x7f #define BIT_PKT_NUM_Q3_V1(x) \ (((x) & BIT_MASK_PKT_NUM_Q3_V1) << BIT_SHIFT_PKT_NUM_Q3_V1) #define BITS_PKT_NUM_Q3_V1 (BIT_MASK_PKT_NUM_Q3_V1 << BIT_SHIFT_PKT_NUM_Q3_V1) #define BIT_CLEAR_PKT_NUM_Q3_V1(x) ((x) & (~BITS_PKT_NUM_Q3_V1)) #define BIT_GET_PKT_NUM_Q3_V1(x) \ (((x) >> BIT_SHIFT_PKT_NUM_Q3_V1) & BIT_MASK_PKT_NUM_Q3_V1) #define BIT_SET_PKT_NUM_Q3_V1(x, v) \ (BIT_CLEAR_PKT_NUM_Q3_V1(x) | BIT_PKT_NUM_Q3_V1(v)) #define BIT_SHIFT_HEAD_PKT_Q3 0 #define BIT_MASK_HEAD_PKT_Q3 0xff #define BIT_HEAD_PKT_Q3(x) \ (((x) & BIT_MASK_HEAD_PKT_Q3) << BIT_SHIFT_HEAD_PKT_Q3) #define BITS_HEAD_PKT_Q3 (BIT_MASK_HEAD_PKT_Q3 << BIT_SHIFT_HEAD_PKT_Q3) #define BIT_CLEAR_HEAD_PKT_Q3(x) ((x) & (~BITS_HEAD_PKT_Q3)) #define BIT_GET_HEAD_PKT_Q3(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_Q3) & BIT_MASK_HEAD_PKT_Q3) #define BIT_SET_HEAD_PKT_Q3(x, v) \ (BIT_CLEAR_HEAD_PKT_Q3(x) | BIT_HEAD_PKT_Q3(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q3_INFO (Offset 0x040C) */ #define BIT_SHIFT_HEAD_PKT_Q3_V1 0 #define BIT_MASK_HEAD_PKT_Q3_V1 0x7ff #define BIT_HEAD_PKT_Q3_V1(x) \ (((x) & BIT_MASK_HEAD_PKT_Q3_V1) << BIT_SHIFT_HEAD_PKT_Q3_V1) #define BITS_HEAD_PKT_Q3_V1 \ (BIT_MASK_HEAD_PKT_Q3_V1 << BIT_SHIFT_HEAD_PKT_Q3_V1) #define BIT_CLEAR_HEAD_PKT_Q3_V1(x) ((x) & (~BITS_HEAD_PKT_Q3_V1)) #define BIT_GET_HEAD_PKT_Q3_V1(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1) & BIT_MASK_HEAD_PKT_Q3_V1) #define BIT_SET_HEAD_PKT_Q3_V1(x, v) \ (BIT_CLEAR_HEAD_PKT_Q3_V1(x) | BIT_HEAD_PKT_Q3_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_QUEUELIST_INFO3 (Offset 0x040C) */ #define BIT_SHIFT_QINFO3 0 #define BIT_MASK_QINFO3 0xffffffffL #define BIT_QINFO3(x) (((x) & BIT_MASK_QINFO3) << BIT_SHIFT_QINFO3) #define BITS_QINFO3 (BIT_MASK_QINFO3 << BIT_SHIFT_QINFO3) #define BIT_CLEAR_QINFO3(x) ((x) & (~BITS_QINFO3)) #define BIT_GET_QINFO3(x) (((x) >> BIT_SHIFT_QINFO3) & BIT_MASK_QINFO3) #define BIT_SET_QINFO3(x, v) (BIT_CLEAR_QINFO3(x) | BIT_QINFO3(v)) /* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ #define BIT_FWCMDQ_EMPTY BIT(31) #define BIT_MGQ_CPU_EMPTY_V1 BIT(30) #define BIT_BCNQ_EMPTY_EXTP0 BIT(29) #define BIT_BCNQ_EMPTY_PORT4 BIT(28) #define BIT_BCNQ_EMPTY_PORT3 BIT(27) #define BIT_BCNQ_EMPTY_PORT2 BIT(26) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MGQ_INFO (Offset 0x0410) */ #define BIT_SHIFT_QUEUEMACID_MGQ_V1 25 #define BIT_MASK_QUEUEMACID_MGQ_V1 0x7f #define BIT_QUEUEMACID_MGQ_V1(x) \ (((x) & BIT_MASK_QUEUEMACID_MGQ_V1) << BIT_SHIFT_QUEUEMACID_MGQ_V1) #define BITS_QUEUEMACID_MGQ_V1 \ (BIT_MASK_QUEUEMACID_MGQ_V1 << BIT_SHIFT_QUEUEMACID_MGQ_V1) #define BIT_CLEAR_QUEUEMACID_MGQ_V1(x) ((x) & (~BITS_QUEUEMACID_MGQ_V1)) #define BIT_GET_QUEUEMACID_MGQ_V1(x) \ (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1) & BIT_MASK_QUEUEMACID_MGQ_V1) #define BIT_SET_QUEUEMACID_MGQ_V1(x, v) \ (BIT_CLEAR_QUEUEMACID_MGQ_V1(x) | BIT_QUEUEMACID_MGQ_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ #define BIT_BCNQ_EMPTY_PORT1 BIT(25) #define BIT_BCNQ_EMPTY_PORT0 BIT(24) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MGQ_INFO (Offset 0x0410) */ #define BIT_SHIFT_QUEUEAC_MGQ_V1 23 #define BIT_MASK_QUEUEAC_MGQ_V1 0x3 #define BIT_QUEUEAC_MGQ_V1(x) \ (((x) & BIT_MASK_QUEUEAC_MGQ_V1) << BIT_SHIFT_QUEUEAC_MGQ_V1) #define BITS_QUEUEAC_MGQ_V1 \ (BIT_MASK_QUEUEAC_MGQ_V1 << BIT_SHIFT_QUEUEAC_MGQ_V1) #define BIT_CLEAR_QUEUEAC_MGQ_V1(x) ((x) & (~BITS_QUEUEAC_MGQ_V1)) #define BIT_GET_QUEUEAC_MGQ_V1(x) \ (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1) & BIT_MASK_QUEUEAC_MGQ_V1) #define BIT_SET_QUEUEAC_MGQ_V1(x, v) \ (BIT_CLEAR_QUEUEAC_MGQ_V1(x) | BIT_QUEUEAC_MGQ_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ #define BIT_HQQ_EMPTY_V1 BIT(23) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MGQ_INFO (Offset 0x0410) */ #define BIT_TIDEMPTY_MGQ_V1 BIT(22) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ #define BIT_MQQ_EMPTY_V2 BIT(22) #define BIT_S1_EMPTY BIT(21) #define BIT_S0_EMPTY BIT(20) #define BIT_AC19Q_EMPTY BIT(19) #define BIT_AC18Q_EMPTY BIT(18) #define BIT_AC17Q_EMPTY BIT(17) #define BIT_AC16Q_EMPTY BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MGQ_INFO (Offset 0x0410) */ #define BIT_SHIFT_TAIL_PKT_MGQ_V1 15 #define BIT_MASK_TAIL_PKT_MGQ_V1 0xff #define BIT_TAIL_PKT_MGQ_V1(x) \ (((x) & BIT_MASK_TAIL_PKT_MGQ_V1) << BIT_SHIFT_TAIL_PKT_MGQ_V1) #define BITS_TAIL_PKT_MGQ_V1 \ (BIT_MASK_TAIL_PKT_MGQ_V1 << BIT_SHIFT_TAIL_PKT_MGQ_V1) #define BIT_CLEAR_TAIL_PKT_MGQ_V1(x) ((x) & (~BITS_TAIL_PKT_MGQ_V1)) #define BIT_GET_TAIL_PKT_MGQ_V1(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V1) & BIT_MASK_TAIL_PKT_MGQ_V1) #define BIT_SET_TAIL_PKT_MGQ_V1(x, v) \ (BIT_CLEAR_TAIL_PKT_MGQ_V1(x) | BIT_TAIL_PKT_MGQ_V1(v)) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ #define BIT_AC15Q_EMPTY BIT(15) #define BIT_AC14Q_EMPTY BIT(14) #define BIT_AC13Q_EMPTY BIT(13) #define BIT_AC12Q_EMPTY BIT(12) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MGQ_INFO (Offset 0x0410) */ #define BIT_SHIFT_TAIL_PKT_MGQ_V2 11 #define BIT_MASK_TAIL_PKT_MGQ_V2 0x7ff #define BIT_TAIL_PKT_MGQ_V2(x) \ (((x) & BIT_MASK_TAIL_PKT_MGQ_V2) << BIT_SHIFT_TAIL_PKT_MGQ_V2) #define BITS_TAIL_PKT_MGQ_V2 \ (BIT_MASK_TAIL_PKT_MGQ_V2 << BIT_SHIFT_TAIL_PKT_MGQ_V2) #define BIT_CLEAR_TAIL_PKT_MGQ_V2(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2)) #define BIT_GET_TAIL_PKT_MGQ_V2(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2) & BIT_MASK_TAIL_PKT_MGQ_V2) #define BIT_SET_TAIL_PKT_MGQ_V2(x, v) \ (BIT_CLEAR_TAIL_PKT_MGQ_V2(x) | BIT_TAIL_PKT_MGQ_V2(v)) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ #define BIT_AC11Q_EMPTY BIT(11) #define BIT_AC10Q_EMPTY BIT(10) #define BIT_AC9Q_EMPTY BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MGQ_INFO (Offset 0x0410) */ #define BIT_SHIFT_PKT_NUM_MGQ_V1 8 #define BIT_MASK_PKT_NUM_MGQ_V1 0x7f #define BIT_PKT_NUM_MGQ_V1(x) \ (((x) & BIT_MASK_PKT_NUM_MGQ_V1) << BIT_SHIFT_PKT_NUM_MGQ_V1) #define BITS_PKT_NUM_MGQ_V1 \ (BIT_MASK_PKT_NUM_MGQ_V1 << BIT_SHIFT_PKT_NUM_MGQ_V1) #define BIT_CLEAR_PKT_NUM_MGQ_V1(x) ((x) & (~BITS_PKT_NUM_MGQ_V1)) #define BIT_GET_PKT_NUM_MGQ_V1(x) \ (((x) >> BIT_SHIFT_PKT_NUM_MGQ_V1) & BIT_MASK_PKT_NUM_MGQ_V1) #define BIT_SET_PKT_NUM_MGQ_V1(x, v) \ (BIT_CLEAR_PKT_NUM_MGQ_V1(x) | BIT_PKT_NUM_MGQ_V1(v)) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ #define BIT_AC8Q_EMPTY BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MGQ_INFO (Offset 0x0410) */ #define BIT_SHIFT_HEAD_PKT_MGQ 0 #define BIT_MASK_HEAD_PKT_MGQ 0xff #define BIT_HEAD_PKT_MGQ(x) \ (((x) & BIT_MASK_HEAD_PKT_MGQ) << BIT_SHIFT_HEAD_PKT_MGQ) #define BITS_HEAD_PKT_MGQ (BIT_MASK_HEAD_PKT_MGQ << BIT_SHIFT_HEAD_PKT_MGQ) #define BIT_CLEAR_HEAD_PKT_MGQ(x) ((x) & (~BITS_HEAD_PKT_MGQ)) #define BIT_GET_HEAD_PKT_MGQ(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_MGQ) & BIT_MASK_HEAD_PKT_MGQ) #define BIT_SET_HEAD_PKT_MGQ(x, v) \ (BIT_CLEAR_HEAD_PKT_MGQ(x) | BIT_HEAD_PKT_MGQ(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MGQ_INFO (Offset 0x0410) */ #define BIT_SHIFT_HEAD_PKT_MGQ_V1 0 #define BIT_MASK_HEAD_PKT_MGQ_V1 0x7ff #define BIT_HEAD_PKT_MGQ_V1(x) \ (((x) & BIT_MASK_HEAD_PKT_MGQ_V1) << BIT_SHIFT_HEAD_PKT_MGQ_V1) #define BITS_HEAD_PKT_MGQ_V1 \ (BIT_MASK_HEAD_PKT_MGQ_V1 << BIT_SHIFT_HEAD_PKT_MGQ_V1) #define BIT_CLEAR_HEAD_PKT_MGQ_V1(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1)) #define BIT_GET_HEAD_PKT_MGQ_V1(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1) & BIT_MASK_HEAD_PKT_MGQ_V1) #define BIT_SET_HEAD_PKT_MGQ_V1(x, v) \ (BIT_CLEAR_HEAD_PKT_MGQ_V1(x) | BIT_HEAD_PKT_MGQ_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIQ_INFO (Offset 0x0414) */ #define BIT_SHIFT_QUEUEMACID_HIQ_V1 25 #define BIT_MASK_QUEUEMACID_HIQ_V1 0x7f #define BIT_QUEUEMACID_HIQ_V1(x) \ (((x) & BIT_MASK_QUEUEMACID_HIQ_V1) << BIT_SHIFT_QUEUEMACID_HIQ_V1) #define BITS_QUEUEMACID_HIQ_V1 \ (BIT_MASK_QUEUEMACID_HIQ_V1 << BIT_SHIFT_QUEUEMACID_HIQ_V1) #define BIT_CLEAR_QUEUEMACID_HIQ_V1(x) ((x) & (~BITS_QUEUEMACID_HIQ_V1)) #define BIT_GET_QUEUEMACID_HIQ_V1(x) \ (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1) & BIT_MASK_QUEUEMACID_HIQ_V1) #define BIT_SET_QUEUEMACID_HIQ_V1(x, v) \ (BIT_CLEAR_QUEUEMACID_HIQ_V1(x) | BIT_QUEUEMACID_HIQ_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */ #define BIT_SHIFT_QINFO_CTRL 24 #define BIT_MASK_QINFO_CTRL 0x3f #define BIT_QINFO_CTRL(x) (((x) & BIT_MASK_QINFO_CTRL) << BIT_SHIFT_QINFO_CTRL) #define BITS_QINFO_CTRL (BIT_MASK_QINFO_CTRL << BIT_SHIFT_QINFO_CTRL) #define BIT_CLEAR_QINFO_CTRL(x) ((x) & (~BITS_QINFO_CTRL)) #define BIT_GET_QINFO_CTRL(x) \ (((x) >> BIT_SHIFT_QINFO_CTRL) & BIT_MASK_QINFO_CTRL) #define BIT_SET_QINFO_CTRL(x, v) (BIT_CLEAR_QINFO_CTRL(x) | BIT_QINFO_CTRL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIQ_INFO (Offset 0x0414) */ #define BIT_SHIFT_QUEUEAC_HIQ_V1 23 #define BIT_MASK_QUEUEAC_HIQ_V1 0x3 #define BIT_QUEUEAC_HIQ_V1(x) \ (((x) & BIT_MASK_QUEUEAC_HIQ_V1) << BIT_SHIFT_QUEUEAC_HIQ_V1) #define BITS_QUEUEAC_HIQ_V1 \ (BIT_MASK_QUEUEAC_HIQ_V1 << BIT_SHIFT_QUEUEAC_HIQ_V1) #define BIT_CLEAR_QUEUEAC_HIQ_V1(x) ((x) & (~BITS_QUEUEAC_HIQ_V1)) #define BIT_GET_QUEUEAC_HIQ_V1(x) \ (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1) & BIT_MASK_QUEUEAC_HIQ_V1) #define BIT_SET_QUEUEAC_HIQ_V1(x, v) \ (BIT_CLEAR_QUEUEAC_HIQ_V1(x) | BIT_QUEUEAC_HIQ_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIQ_INFO (Offset 0x0414) */ #define BIT_TIDEMPTY_HIQ_V1 BIT(22) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */ #define BIT_SHIFT_QINFO_MODE_BAND 20 #define BIT_MASK_QINFO_MODE_BAND 0x7 #define BIT_QINFO_MODE_BAND(x) \ (((x) & BIT_MASK_QINFO_MODE_BAND) << BIT_SHIFT_QINFO_MODE_BAND) #define BITS_QINFO_MODE_BAND \ (BIT_MASK_QINFO_MODE_BAND << BIT_SHIFT_QINFO_MODE_BAND) #define BIT_CLEAR_QINFO_MODE_BAND(x) ((x) & (~BITS_QINFO_MODE_BAND)) #define BIT_GET_QINFO_MODE_BAND(x) \ (((x) >> BIT_SHIFT_QINFO_MODE_BAND) & BIT_MASK_QINFO_MODE_BAND) #define BIT_SET_QINFO_MODE_BAND(x, v) \ (BIT_CLEAR_QINFO_MODE_BAND(x) | BIT_QINFO_MODE_BAND(v)) #define BIT_ACQ19_ENABLE BIT(19) #define BIT_ACQ18_ENABLE BIT(18) #define BIT_ACQ17_ENABLE BIT(17) #define BIT_ACQ16_ENABLE BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIQ_INFO (Offset 0x0414) */ #define BIT_SHIFT_TAIL_PKT_HIQ_V1 15 #define BIT_MASK_TAIL_PKT_HIQ_V1 0xff #define BIT_TAIL_PKT_HIQ_V1(x) \ (((x) & BIT_MASK_TAIL_PKT_HIQ_V1) << BIT_SHIFT_TAIL_PKT_HIQ_V1) #define BITS_TAIL_PKT_HIQ_V1 \ (BIT_MASK_TAIL_PKT_HIQ_V1 << BIT_SHIFT_TAIL_PKT_HIQ_V1) #define BIT_CLEAR_TAIL_PKT_HIQ_V1(x) ((x) & (~BITS_TAIL_PKT_HIQ_V1)) #define BIT_GET_TAIL_PKT_HIQ_V1(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V1) & BIT_MASK_TAIL_PKT_HIQ_V1) #define BIT_SET_TAIL_PKT_HIQ_V1(x, v) \ (BIT_CLEAR_TAIL_PKT_HIQ_V1(x) | BIT_TAIL_PKT_HIQ_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */ #define BIT_ACQ15_ENABLE BIT(15) #define BIT_ACQ14_ENABLE BIT(14) #define BIT_ACQ13_ENABLE BIT(13) #define BIT_ACQ12_ENABLE BIT(12) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIQ_INFO (Offset 0x0414) */ #define BIT_SHIFT_TAIL_PKT_HIQ_V2 11 #define BIT_MASK_TAIL_PKT_HIQ_V2 0x7ff #define BIT_TAIL_PKT_HIQ_V2(x) \ (((x) & BIT_MASK_TAIL_PKT_HIQ_V2) << BIT_SHIFT_TAIL_PKT_HIQ_V2) #define BITS_TAIL_PKT_HIQ_V2 \ (BIT_MASK_TAIL_PKT_HIQ_V2 << BIT_SHIFT_TAIL_PKT_HIQ_V2) #define BIT_CLEAR_TAIL_PKT_HIQ_V2(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2)) #define BIT_GET_TAIL_PKT_HIQ_V2(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2) & BIT_MASK_TAIL_PKT_HIQ_V2) #define BIT_SET_TAIL_PKT_HIQ_V2(x, v) \ (BIT_CLEAR_TAIL_PKT_HIQ_V2(x) | BIT_TAIL_PKT_HIQ_V2(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */ #define BIT_ACQ11_ENABLE BIT(11) #define BIT_ACQ10_ENABLE BIT(10) #define BIT_ACQ9_ENABLE BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIQ_INFO (Offset 0x0414) */ #define BIT_SHIFT_PKT_NUM_HIQ_V1 8 #define BIT_MASK_PKT_NUM_HIQ_V1 0x7f #define BIT_PKT_NUM_HIQ_V1(x) \ (((x) & BIT_MASK_PKT_NUM_HIQ_V1) << BIT_SHIFT_PKT_NUM_HIQ_V1) #define BITS_PKT_NUM_HIQ_V1 \ (BIT_MASK_PKT_NUM_HIQ_V1 << BIT_SHIFT_PKT_NUM_HIQ_V1) #define BIT_CLEAR_PKT_NUM_HIQ_V1(x) ((x) & (~BITS_PKT_NUM_HIQ_V1)) #define BIT_GET_PKT_NUM_HIQ_V1(x) \ (((x) >> BIT_SHIFT_PKT_NUM_HIQ_V1) & BIT_MASK_PKT_NUM_HIQ_V1) #define BIT_SET_PKT_NUM_HIQ_V1(x, v) \ (BIT_CLEAR_PKT_NUM_HIQ_V1(x) | BIT_PKT_NUM_HIQ_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */ #define BIT_ACQ8_ENABLE BIT(8) #define BIT_ACQ7_ENABLE BIT(7) #define BIT_ACQ6_ENABLE BIT(6) #define BIT_ACQ5_ENABLE BIT(5) #define BIT_ACQ4_ENABLE BIT(4) #define BIT_ACQ3_ENABLE BIT(3) #define BIT_ACQ2_ENABLE BIT(2) #define BIT_ACQ1_ENABLE BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIQ_INFO (Offset 0x0414) */ #define BIT_SHIFT_HEAD_PKT_HIQ 0 #define BIT_MASK_HEAD_PKT_HIQ 0xff #define BIT_HEAD_PKT_HIQ(x) \ (((x) & BIT_MASK_HEAD_PKT_HIQ) << BIT_SHIFT_HEAD_PKT_HIQ) #define BITS_HEAD_PKT_HIQ (BIT_MASK_HEAD_PKT_HIQ << BIT_SHIFT_HEAD_PKT_HIQ) #define BIT_CLEAR_HEAD_PKT_HIQ(x) ((x) & (~BITS_HEAD_PKT_HIQ)) #define BIT_GET_HEAD_PKT_HIQ(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_HIQ) & BIT_MASK_HEAD_PKT_HIQ) #define BIT_SET_HEAD_PKT_HIQ(x, v) \ (BIT_CLEAR_HEAD_PKT_HIQ(x) | BIT_HEAD_PKT_HIQ(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIQ_INFO (Offset 0x0414) */ #define BIT_SHIFT_HEAD_PKT_HIQ_V1 0 #define BIT_MASK_HEAD_PKT_HIQ_V1 0x7ff #define BIT_HEAD_PKT_HIQ_V1(x) \ (((x) & BIT_MASK_HEAD_PKT_HIQ_V1) << BIT_SHIFT_HEAD_PKT_HIQ_V1) #define BITS_HEAD_PKT_HIQ_V1 \ (BIT_MASK_HEAD_PKT_HIQ_V1 << BIT_SHIFT_HEAD_PKT_HIQ_V1) #define BIT_CLEAR_HEAD_PKT_HIQ_V1(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1)) #define BIT_GET_HEAD_PKT_HIQ_V1(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1) & BIT_MASK_HEAD_PKT_HIQ_V1) #define BIT_SET_HEAD_PKT_HIQ_V1(x, v) \ (BIT_CLEAR_HEAD_PKT_HIQ_V1(x) | BIT_HEAD_PKT_HIQ_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */ #define BIT_ACQ0_ENABLE BIT(0) /* 2 REG_BCNQ_BDNY_V2 (Offset 0x0418) */ #define BIT_SHIFT_BCNQ_PGBNDY_WSEL 28 #define BIT_MASK_BCNQ_PGBNDY_WSEL 0x7 #define BIT_BCNQ_PGBNDY_WSEL(x) \ (((x) & BIT_MASK_BCNQ_PGBNDY_WSEL) << BIT_SHIFT_BCNQ_PGBNDY_WSEL) #define BITS_BCNQ_PGBNDY_WSEL \ (BIT_MASK_BCNQ_PGBNDY_WSEL << BIT_SHIFT_BCNQ_PGBNDY_WSEL) #define BIT_CLEAR_BCNQ_PGBNDY_WSEL(x) ((x) & (~BITS_BCNQ_PGBNDY_WSEL)) #define BIT_GET_BCNQ_PGBNDY_WSEL(x) \ (((x) >> BIT_SHIFT_BCNQ_PGBNDY_WSEL) & BIT_MASK_BCNQ_PGBNDY_WSEL) #define BIT_SET_BCNQ_PGBNDY_WSEL(x, v) \ (BIT_CLEAR_BCNQ_PGBNDY_WSEL(x) | BIT_BCNQ_PGBNDY_WSEL(v)) #define BIT_SHIFT_BCNQ_PGBNDY_RCONTENT 12 #define BIT_MASK_BCNQ_PGBNDY_RCONTENT 0xfff #define BIT_BCNQ_PGBNDY_RCONTENT(x) \ (((x) & BIT_MASK_BCNQ_PGBNDY_RCONTENT) \ << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT) #define BITS_BCNQ_PGBNDY_RCONTENT \ (BIT_MASK_BCNQ_PGBNDY_RCONTENT << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT) #define BIT_CLEAR_BCNQ_PGBNDY_RCONTENT(x) ((x) & (~BITS_BCNQ_PGBNDY_RCONTENT)) #define BIT_GET_BCNQ_PGBNDY_RCONTENT(x) \ (((x) >> BIT_SHIFT_BCNQ_PGBNDY_RCONTENT) & \ BIT_MASK_BCNQ_PGBNDY_RCONTENT) #define BIT_SET_BCNQ_PGBNDY_RCONTENT(x, v) \ (BIT_CLEAR_BCNQ_PGBNDY_RCONTENT(x) | BIT_BCNQ_PGBNDY_RCONTENT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BCNQ_INFO (Offset 0x0418) */ #define BIT_SHIFT_PKT_NUM_BCNQ 8 #define BIT_MASK_PKT_NUM_BCNQ 0xff #define BIT_PKT_NUM_BCNQ(x) \ (((x) & BIT_MASK_PKT_NUM_BCNQ) << BIT_SHIFT_PKT_NUM_BCNQ) #define BITS_PKT_NUM_BCNQ (BIT_MASK_PKT_NUM_BCNQ << BIT_SHIFT_PKT_NUM_BCNQ) #define BIT_CLEAR_PKT_NUM_BCNQ(x) ((x) & (~BITS_PKT_NUM_BCNQ)) #define BIT_GET_PKT_NUM_BCNQ(x) \ (((x) >> BIT_SHIFT_PKT_NUM_BCNQ) & BIT_MASK_PKT_NUM_BCNQ) #define BIT_SET_PKT_NUM_BCNQ(x, v) \ (BIT_CLEAR_PKT_NUM_BCNQ(x) | BIT_PKT_NUM_BCNQ(v)) #define BIT_SHIFT_BCNQ_HEAD_PG 0 #define BIT_MASK_BCNQ_HEAD_PG 0xff #define BIT_BCNQ_HEAD_PG(x) \ (((x) & BIT_MASK_BCNQ_HEAD_PG) << BIT_SHIFT_BCNQ_HEAD_PG) #define BITS_BCNQ_HEAD_PG (BIT_MASK_BCNQ_HEAD_PG << BIT_SHIFT_BCNQ_HEAD_PG) #define BIT_CLEAR_BCNQ_HEAD_PG(x) ((x) & (~BITS_BCNQ_HEAD_PG)) #define BIT_GET_BCNQ_HEAD_PG(x) \ (((x) >> BIT_SHIFT_BCNQ_HEAD_PG) & BIT_MASK_BCNQ_HEAD_PG) #define BIT_SET_BCNQ_HEAD_PG(x, v) \ (BIT_CLEAR_BCNQ_HEAD_PG(x) | BIT_BCNQ_HEAD_PG(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BCNQ_INFO (Offset 0x0418) */ #define BIT_SHIFT_BCNQ_HEAD_PG_V1 0 #define BIT_MASK_BCNQ_HEAD_PG_V1 0xfff #define BIT_BCNQ_HEAD_PG_V1(x) \ (((x) & BIT_MASK_BCNQ_HEAD_PG_V1) << BIT_SHIFT_BCNQ_HEAD_PG_V1) #define BITS_BCNQ_HEAD_PG_V1 \ (BIT_MASK_BCNQ_HEAD_PG_V1 << BIT_SHIFT_BCNQ_HEAD_PG_V1) #define BIT_CLEAR_BCNQ_HEAD_PG_V1(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1)) #define BIT_GET_BCNQ_HEAD_PG_V1(x) \ (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1) & BIT_MASK_BCNQ_HEAD_PG_V1) #define BIT_SET_BCNQ_HEAD_PG_V1(x, v) \ (BIT_CLEAR_BCNQ_HEAD_PG_V1(x) | BIT_BCNQ_HEAD_PG_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_BCNQ_BDNY_V2 (Offset 0x0418) */ #define BIT_SHIFT_BCNQ_PGBNDY_WCONTENT 0 #define BIT_MASK_BCNQ_PGBNDY_WCONTENT 0xfff #define BIT_BCNQ_PGBNDY_WCONTENT(x) \ (((x) & BIT_MASK_BCNQ_PGBNDY_WCONTENT) \ << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT) #define BITS_BCNQ_PGBNDY_WCONTENT \ (BIT_MASK_BCNQ_PGBNDY_WCONTENT << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT) #define BIT_CLEAR_BCNQ_PGBNDY_WCONTENT(x) ((x) & (~BITS_BCNQ_PGBNDY_WCONTENT)) #define BIT_GET_BCNQ_PGBNDY_WCONTENT(x) \ (((x) >> BIT_SHIFT_BCNQ_PGBNDY_WCONTENT) & \ BIT_MASK_BCNQ_PGBNDY_WCONTENT) #define BIT_SET_BCNQ_PGBNDY_WCONTENT(x, v) \ (BIT_CLEAR_BCNQ_PGBNDY_WCONTENT(x) | BIT_BCNQ_PGBNDY_WCONTENT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXPKT_EMPTY (Offset 0x041A) */ #define BIT_BCNQ_EMPTY BIT(11) #define BIT_HQQ_EMPTY BIT(10) #define BIT_MQQ_EMPTY BIT(9) #define BIT_MGQ_CPU_EMPTY BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ #define BIT_BCN1_POLL BIT(30) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ #define BIT_CPUMGT_CLR_V1 BIT(30) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ #define BIT_CPUMGT_POLL BIT(29) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ #define BIT_BCN_POLL BIT(28) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ #define BIT_CPUMGT_CLR BIT(27) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ #define BIT_BCN_EXT_POLL BIT(21) #define BIT_BCN4_POLL BIT(20) #define BIT_BCN3_POLL BIT(19) #define BIT_BCN2_POLL BIT(18) #define BIT_BCN1_POLL_V1 BIT(17) #define BIT_BCN_POLL_V1 BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ #define BIT_CPUMGQ_FW_NUM_V1 BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ #define BIT_CPUMGQ_FW_NUM BIT(8) #define BIT_SHIFT_CPUMGQ_HEAD_PG 0 #define BIT_MASK_CPUMGQ_HEAD_PG 0xff #define BIT_CPUMGQ_HEAD_PG(x) \ (((x) & BIT_MASK_CPUMGQ_HEAD_PG) << BIT_SHIFT_CPUMGQ_HEAD_PG) #define BITS_CPUMGQ_HEAD_PG \ (BIT_MASK_CPUMGQ_HEAD_PG << BIT_SHIFT_CPUMGQ_HEAD_PG) #define BIT_CLEAR_CPUMGQ_HEAD_PG(x) ((x) & (~BITS_CPUMGQ_HEAD_PG)) #define BIT_GET_CPUMGQ_HEAD_PG(x) \ (((x) >> BIT_SHIFT_CPUMGQ_HEAD_PG) & BIT_MASK_CPUMGQ_HEAD_PG) #define BIT_SET_CPUMGQ_HEAD_PG(x, v) \ (BIT_CLEAR_CPUMGQ_HEAD_PG(x) | BIT_CPUMGQ_HEAD_PG(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ #define BIT_SHIFT_FW_FREE_TAIL_V1 0 #define BIT_MASK_FW_FREE_TAIL_V1 0xfff #define BIT_FW_FREE_TAIL_V1(x) \ (((x) & BIT_MASK_FW_FREE_TAIL_V1) << BIT_SHIFT_FW_FREE_TAIL_V1) #define BITS_FW_FREE_TAIL_V1 \ (BIT_MASK_FW_FREE_TAIL_V1 << BIT_SHIFT_FW_FREE_TAIL_V1) #define BIT_CLEAR_FW_FREE_TAIL_V1(x) ((x) & (~BITS_FW_FREE_TAIL_V1)) #define BIT_GET_FW_FREE_TAIL_V1(x) \ (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1) & BIT_MASK_FW_FREE_TAIL_V1) #define BIT_SET_FW_FREE_TAIL_V1(x, v) \ (BIT_CLEAR_FW_FREE_TAIL_V1(x) | BIT_FW_FREE_TAIL_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ #define BIT_SHIFT_FREE_TAIL_PAGE 0 #define BIT_MASK_FREE_TAIL_PAGE 0xfff #define BIT_FREE_TAIL_PAGE(x) \ (((x) & BIT_MASK_FREE_TAIL_PAGE) << BIT_SHIFT_FREE_TAIL_PAGE) #define BITS_FREE_TAIL_PAGE \ (BIT_MASK_FREE_TAIL_PAGE << BIT_SHIFT_FREE_TAIL_PAGE) #define BIT_CLEAR_FREE_TAIL_PAGE(x) ((x) & (~BITS_FREE_TAIL_PAGE)) #define BIT_GET_FREE_TAIL_PAGE(x) \ (((x) >> BIT_SHIFT_FREE_TAIL_PAGE) & BIT_MASK_FREE_TAIL_PAGE) #define BIT_SET_FREE_TAIL_PAGE(x, v) \ (BIT_CLEAR_FREE_TAIL_PAGE(x) | BIT_FREE_TAIL_PAGE(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_RTS_LIMIT_IN_OFDM BIT(23) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_EN_BCNQ_DL BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_EN_RD_RESP_NAV_BK BIT(21) #define BIT_EN_WR_FREE_TAIL BIT(20) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_TXRPT_DIS BIT(19) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_NOTXRPT_USERATE_EN BIT(19) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_DIS_TXFAIL_RPT BIT(18) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_FTM_TIMEOUT_BYPASS BIT(16) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_EN_BCNQ_DL5 BIT(13) #define BIT_EN_BCNQ_DL4 BIT(12) #define BIT_EN_BCNQ_DL3 BIT(11) #define BIT_EN_BCNQ_DL2 BIT(10) #define BIT_EN_BCNQ_DL1 BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_SHIFT_EN_QUEUE_RPT 8 #define BIT_MASK_EN_QUEUE_RPT 0xff #define BIT_EN_QUEUE_RPT(x) \ (((x) & BIT_MASK_EN_QUEUE_RPT) << BIT_SHIFT_EN_QUEUE_RPT) #define BITS_EN_QUEUE_RPT (BIT_MASK_EN_QUEUE_RPT << BIT_SHIFT_EN_QUEUE_RPT) #define BIT_CLEAR_EN_QUEUE_RPT(x) ((x) & (~BITS_EN_QUEUE_RPT)) #define BIT_GET_EN_QUEUE_RPT(x) \ (((x) >> BIT_SHIFT_EN_QUEUE_RPT) & BIT_MASK_EN_QUEUE_RPT) #define BIT_SET_EN_QUEUE_RPT(x, v) \ (BIT_CLEAR_EN_QUEUE_RPT(x) | BIT_EN_QUEUE_RPT(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_EN_BCNQ_DL0 BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_EN_RTY_BK BIT(7) #define BIT_EN_USE_INI_RAT BIT(6) #define BIT_EN_RTS_NAV_BK BIT(5) #define BIT_DIS_SSN_CHECK BIT(4) #define BIT_MACID_MATCH_RTS BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_EN_BCN_TRXRPT_V1 BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_R_EN_FTMRPT BIT(1) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_EN_FTMRPT_V1 BIT(1) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_R_EN_FTMRPT_V1 BIT(1) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_EN_FTMACKRPT BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_R_BMC_NAV_PROTECT BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_BMC_NAV_PROTECT BIT(0) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ #define BIT_EN_FTMRPT BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HWSEQ_CTRL (Offset 0x0423) */ #define BIT_HWSEQ_CPUM_EN BIT(7) #define BIT_HWSEQ_BCN_EN BIT(6) #define BIT_HWSEQ_HI_EN BIT(5) #define BIT_HWSEQ_MGT_EN BIT(4) #define BIT_HWSEQ_BK_EN BIT(3) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_DATAFB_SEL (Offset 0x0423) */ #define BIT_R_BROADCAST_RETRY_EN BIT(3) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DATAFB_SEL (Offset 0x0423) */ #define BIT_BROADCAST_RTY_EN BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HWSEQ_CTRL (Offset 0x0423) */ #define BIT_HWSEQ_BE_EN BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_DATAFB_SEL (Offset 0x0423) */ #define BIT__R_EN_RTY_BK_COD BIT(2) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DATAFB_SEL (Offset 0x0423) */ #define BIT_EN_RTY_BK_COD BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HWSEQ_CTRL (Offset 0x0423) */ #define BIT_HWSEQ_VI_EN BIT(1) #define BIT_HWSEQ_VO_EN BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DATAFB_SEL (Offset 0x0423) */ #define BIT_SHIFT__R_DATA_FALLBACK_SEL 0 #define BIT_MASK__R_DATA_FALLBACK_SEL 0x3 #define BIT__R_DATA_FALLBACK_SEL(x) \ (((x) & BIT_MASK__R_DATA_FALLBACK_SEL) \ << BIT_SHIFT__R_DATA_FALLBACK_SEL) #define BITS__R_DATA_FALLBACK_SEL \ (BIT_MASK__R_DATA_FALLBACK_SEL << BIT_SHIFT__R_DATA_FALLBACK_SEL) #define BIT_CLEAR__R_DATA_FALLBACK_SEL(x) ((x) & (~BITS__R_DATA_FALLBACK_SEL)) #define BIT_GET__R_DATA_FALLBACK_SEL(x) \ (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL) & \ BIT_MASK__R_DATA_FALLBACK_SEL) #define BIT_SET__R_DATA_FALLBACK_SEL(x, v) \ (BIT_CLEAR__R_DATA_FALLBACK_SEL(x) | BIT__R_DATA_FALLBACK_SEL(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DATAFB_SEL (Offset 0x0423) */ #define BIT_SHIFT__DATA_FALLBACK_SEL 0 #define BIT_MASK__DATA_FALLBACK_SEL 0x3 #define BIT__DATA_FALLBACK_SEL(x) \ (((x) & BIT_MASK__DATA_FALLBACK_SEL) << BIT_SHIFT__DATA_FALLBACK_SEL) #define BITS__DATA_FALLBACK_SEL \ (BIT_MASK__DATA_FALLBACK_SEL << BIT_SHIFT__DATA_FALLBACK_SEL) #define BIT_CLEAR__DATA_FALLBACK_SEL(x) ((x) & (~BITS__DATA_FALLBACK_SEL)) #define BIT_GET__DATA_FALLBACK_SEL(x) \ (((x) >> BIT_SHIFT__DATA_FALLBACK_SEL) & BIT_MASK__DATA_FALLBACK_SEL) #define BIT_SET__DATA_FALLBACK_SEL(x, v) \ (BIT_CLEAR__DATA_FALLBACK_SEL(x) | BIT__DATA_FALLBACK_SEL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BCNQ_BDNY (Offset 0x0424) */ #define BIT_SHIFT_BCNQ_PGBNDY 0 #define BIT_MASK_BCNQ_PGBNDY 0xff #define BIT_BCNQ_PGBNDY(x) \ (((x) & BIT_MASK_BCNQ_PGBNDY) << BIT_SHIFT_BCNQ_PGBNDY) #define BITS_BCNQ_PGBNDY (BIT_MASK_BCNQ_PGBNDY << BIT_SHIFT_BCNQ_PGBNDY) #define BIT_CLEAR_BCNQ_PGBNDY(x) ((x) & (~BITS_BCNQ_PGBNDY)) #define BIT_GET_BCNQ_PGBNDY(x) \ (((x) >> BIT_SHIFT_BCNQ_PGBNDY) & BIT_MASK_BCNQ_PGBNDY) #define BIT_SET_BCNQ_PGBNDY(x, v) \ (BIT_CLEAR_BCNQ_PGBNDY(x) | BIT_BCNQ_PGBNDY(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_BCNQ_BDNY_V1 (Offset 0x0424) */ #define BIT_SHIFT_BCNQ_PGBNDY_V1 0 #define BIT_MASK_BCNQ_PGBNDY_V1 0xfff #define BIT_BCNQ_PGBNDY_V1(x) \ (((x) & BIT_MASK_BCNQ_PGBNDY_V1) << BIT_SHIFT_BCNQ_PGBNDY_V1) #define BITS_BCNQ_PGBNDY_V1 \ (BIT_MASK_BCNQ_PGBNDY_V1 << BIT_SHIFT_BCNQ_PGBNDY_V1) #define BIT_CLEAR_BCNQ_PGBNDY_V1(x) ((x) & (~BITS_BCNQ_PGBNDY_V1)) #define BIT_GET_BCNQ_PGBNDY_V1(x) \ (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1) & BIT_MASK_BCNQ_PGBNDY_V1) #define BIT_SET_BCNQ_PGBNDY_V1(x, v) \ (BIT_CLEAR_BCNQ_PGBNDY_V1(x) | BIT_BCNQ_PGBNDY_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXBDNY (Offset 0x0424) */ #define BIT_SHIFT_TXBNDY 0 #define BIT_MASK_TXBNDY 0xfff #define BIT_TXBNDY(x) (((x) & BIT_MASK_TXBNDY) << BIT_SHIFT_TXBNDY) #define BITS_TXBNDY (BIT_MASK_TXBNDY << BIT_SHIFT_TXBNDY) #define BIT_CLEAR_TXBNDY(x) ((x) & (~BITS_TXBNDY)) #define BIT_GET_TXBNDY(x) (((x) >> BIT_SHIFT_TXBNDY) & BIT_MASK_TXBNDY) #define BIT_SET_TXBNDY(x, v) (BIT_CLEAR_TXBNDY(x) | BIT_TXBNDY(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MGQ_BDNY (Offset 0x0425) */ #define BIT_SHIFT_MGQ_PGBNDY 0 #define BIT_MASK_MGQ_PGBNDY 0xff #define BIT_MGQ_PGBNDY(x) (((x) & BIT_MASK_MGQ_PGBNDY) << BIT_SHIFT_MGQ_PGBNDY) #define BITS_MGQ_PGBNDY (BIT_MASK_MGQ_PGBNDY << BIT_SHIFT_MGQ_PGBNDY) #define BIT_CLEAR_MGQ_PGBNDY(x) ((x) & (~BITS_MGQ_PGBNDY)) #define BIT_GET_MGQ_PGBNDY(x) \ (((x) >> BIT_SHIFT_MGQ_PGBNDY) & BIT_MASK_MGQ_PGBNDY) #define BIT_SET_MGQ_PGBNDY(x, v) (BIT_CLEAR_MGQ_PGBNDY(x) | BIT_MGQ_PGBNDY(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_LIFETIME_EN (Offset 0x0426) */ #define BIT_BT_INT_CPU BIT(7) #define BIT_BT_INT_PTA BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LIFETIME_EN (Offset 0x0426) */ #define BIT_SPERPT_ENTRY BIT(5) #define BIT_RTYCNT_FB BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_LIFETIME_EN (Offset 0x0426) */ #define BIT_EN_CTRL_RTYBIT BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_LIFETIME_EN (Offset 0x0426) */ #define BIT_LIFETIME_BK_EN BIT(3) #define BIT_LIFETIME_BE_EN BIT(2) #define BIT_LIFETIME_VI_EN BIT(1) #define BIT_LIFETIME_VO_EN BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FW_FREE_TAIL (Offset 0x0427) */ #define BIT_SHIFT_FW_FREE_TAIL 0 #define BIT_MASK_FW_FREE_TAIL 0xff #define BIT_FW_FREE_TAIL(x) \ (((x) & BIT_MASK_FW_FREE_TAIL) << BIT_SHIFT_FW_FREE_TAIL) #define BITS_FW_FREE_TAIL (BIT_MASK_FW_FREE_TAIL << BIT_SHIFT_FW_FREE_TAIL) #define BIT_CLEAR_FW_FREE_TAIL(x) ((x) & (~BITS_FW_FREE_TAIL)) #define BIT_GET_FW_FREE_TAIL(x) \ (((x) >> BIT_SHIFT_FW_FREE_TAIL) & BIT_MASK_FW_FREE_TAIL) #define BIT_SET_FW_FREE_TAIL(x, v) \ (BIT_CLEAR_FW_FREE_TAIL(x) | BIT_FW_FREE_TAIL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SPEC_SIFS (Offset 0x0428) */ #define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL 8 #define BIT_MASK_SPEC_SIFS_OFDM_PTCL 0xff #define BIT_SPEC_SIFS_OFDM_PTCL(x) \ (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) #define BITS_SPEC_SIFS_OFDM_PTCL \ (BIT_MASK_SPEC_SIFS_OFDM_PTCL << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) #define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL(x) ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL)) #define BIT_GET_SPEC_SIFS_OFDM_PTCL(x) \ (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) #define BIT_SET_SPEC_SIFS_OFDM_PTCL(x, v) \ (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL(x) | BIT_SPEC_SIFS_OFDM_PTCL(v)) #define BIT_SHIFT_SPEC_SIFS_CCK_PTCL 0 #define BIT_MASK_SPEC_SIFS_CCK_PTCL 0xff #define BIT_SPEC_SIFS_CCK_PTCL(x) \ (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL) #define BITS_SPEC_SIFS_CCK_PTCL \ (BIT_MASK_SPEC_SIFS_CCK_PTCL << BIT_SHIFT_SPEC_SIFS_CCK_PTCL) #define BIT_CLEAR_SPEC_SIFS_CCK_PTCL(x) ((x) & (~BITS_SPEC_SIFS_CCK_PTCL)) #define BIT_GET_SPEC_SIFS_CCK_PTCL(x) \ (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL) & BIT_MASK_SPEC_SIFS_CCK_PTCL) #define BIT_SET_SPEC_SIFS_CCK_PTCL(x, v) \ (BIT_CLEAR_SPEC_SIFS_CCK_PTCL(x) | BIT_SPEC_SIFS_CCK_PTCL(v)) /* 2 REG_RETRY_LIMIT (Offset 0x042A) */ #define BIT_SHIFT_SRL 8 #define BIT_MASK_SRL 0x3f #define BIT_SRL(x) (((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL) #define BITS_SRL (BIT_MASK_SRL << BIT_SHIFT_SRL) #define BIT_CLEAR_SRL(x) ((x) & (~BITS_SRL)) #define BIT_GET_SRL(x) (((x) >> BIT_SHIFT_SRL) & BIT_MASK_SRL) #define BIT_SET_SRL(x, v) (BIT_CLEAR_SRL(x) | BIT_SRL(v)) #define BIT_SHIFT_LRL 0 #define BIT_MASK_LRL 0x3f #define BIT_LRL(x) (((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL) #define BITS_LRL (BIT_MASK_LRL << BIT_SHIFT_LRL) #define BIT_CLEAR_LRL(x) ((x) & (~BITS_LRL)) #define BIT_GET_LRL(x) (((x) >> BIT_SHIFT_LRL) & BIT_MASK_LRL) #define BIT_SET_LRL(x, v) (BIT_CLEAR_LRL(x) | BIT_LRL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_R_ENABLE_NDPA BIT(31) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_ENABLE_NDPA BIT(31) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_USE_NDPA_PARAMETER BIT(30) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_NDPA_PARA BIT(30) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_R_PROP_TXBF BIT(29) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_PROP_TXBF BIT(29) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_R_EN_NDPA_INT BIT(28) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_EN_NDPA_INT BIT(28) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_R_TXBF1_80M BIT(27) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_TXBF1_80M_160M BIT(27) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_R_TXBF1_40M BIT(26) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_TXBF1_40M BIT(26) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_R_TXBF1_20M BIT(25) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_TXBF1_20M BIT(25) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_SHIFT_R_TXBF1_AID 16 #define BIT_MASK_R_TXBF1_AID 0x1ff #define BIT_R_TXBF1_AID(x) \ (((x) & BIT_MASK_R_TXBF1_AID) << BIT_SHIFT_R_TXBF1_AID) #define BITS_R_TXBF1_AID (BIT_MASK_R_TXBF1_AID << BIT_SHIFT_R_TXBF1_AID) #define BIT_CLEAR_R_TXBF1_AID(x) ((x) & (~BITS_R_TXBF1_AID)) #define BIT_GET_R_TXBF1_AID(x) \ (((x) >> BIT_SHIFT_R_TXBF1_AID) & BIT_MASK_R_TXBF1_AID) #define BIT_SET_R_TXBF1_AID(x, v) \ (BIT_CLEAR_R_TXBF1_AID(x) | BIT_R_TXBF1_AID(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_SHIFT_TXBF1_AID 16 #define BIT_MASK_TXBF1_AID 0x1ff #define BIT_TXBF1_AID(x) (((x) & BIT_MASK_TXBF1_AID) << BIT_SHIFT_TXBF1_AID) #define BITS_TXBF1_AID (BIT_MASK_TXBF1_AID << BIT_SHIFT_TXBF1_AID) #define BIT_CLEAR_TXBF1_AID(x) ((x) & (~BITS_TXBF1_AID)) #define BIT_GET_TXBF1_AID(x) (((x) >> BIT_SHIFT_TXBF1_AID) & BIT_MASK_TXBF1_AID) #define BIT_SET_TXBF1_AID(x, v) (BIT_CLEAR_TXBF1_AID(x) | BIT_TXBF1_AID(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_DIS_NDP_BFEN BIT(15) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_R_TXBCN_NOBLOCK_NDP BIT(14) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_TXBCN_NOBLOCK_NDP BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_R_TXBF0_80M BIT(11) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_TXBF0_80M_160M BIT(11) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_R_TXBF0_40M BIT(10) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_TXBF0_40M BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_R_TXBF0_20M BIT(9) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_TXBF0_20M BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_SHIFT_R_TXBF0_AID 0 #define BIT_MASK_R_TXBF0_AID 0x1ff #define BIT_R_TXBF0_AID(x) \ (((x) & BIT_MASK_R_TXBF0_AID) << BIT_SHIFT_R_TXBF0_AID) #define BITS_R_TXBF0_AID (BIT_MASK_R_TXBF0_AID << BIT_SHIFT_R_TXBF0_AID) #define BIT_CLEAR_R_TXBF0_AID(x) ((x) & (~BITS_R_TXBF0_AID)) #define BIT_GET_R_TXBF0_AID(x) \ (((x) >> BIT_SHIFT_R_TXBF0_AID) & BIT_MASK_R_TXBF0_AID) #define BIT_SET_R_TXBF0_AID(x, v) \ (BIT_CLEAR_R_TXBF0_AID(x) | BIT_R_TXBF0_AID(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXBF_CTRL (Offset 0x042C) */ #define BIT_SHIFT_TXBF0_AID 0 #define BIT_MASK_TXBF0_AID 0x1ff #define BIT_TXBF0_AID(x) (((x) & BIT_MASK_TXBF0_AID) << BIT_SHIFT_TXBF0_AID) #define BITS_TXBF0_AID (BIT_MASK_TXBF0_AID << BIT_SHIFT_TXBF0_AID) #define BIT_CLEAR_TXBF0_AID(x) ((x) & (~BITS_TXBF0_AID)) #define BIT_GET_TXBF0_AID(x) (((x) >> BIT_SHIFT_TXBF0_AID) & BIT_MASK_TXBF0_AID) #define BIT_SET_TXBF0_AID(x, v) (BIT_CLEAR_TXBF0_AID(x) | BIT_TXBF0_AID(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DARFRC (Offset 0x0430) */ #define BIT_SHIFT_DARF_RC8 (56 & CPU_OPT_WIDTH) #define BIT_MASK_DARF_RC8 0x1f #define BIT_DARF_RC8(x) (((x) & BIT_MASK_DARF_RC8) << BIT_SHIFT_DARF_RC8) #define BITS_DARF_RC8 (BIT_MASK_DARF_RC8 << BIT_SHIFT_DARF_RC8) #define BIT_CLEAR_DARF_RC8(x) ((x) & (~BITS_DARF_RC8)) #define BIT_GET_DARF_RC8(x) (((x) >> BIT_SHIFT_DARF_RC8) & BIT_MASK_DARF_RC8) #define BIT_SET_DARF_RC8(x, v) (BIT_CLEAR_DARF_RC8(x) | BIT_DARF_RC8(v)) #define BIT_SHIFT_DARF_RC7 (48 & CPU_OPT_WIDTH) #define BIT_MASK_DARF_RC7 0x1f #define BIT_DARF_RC7(x) (((x) & BIT_MASK_DARF_RC7) << BIT_SHIFT_DARF_RC7) #define BITS_DARF_RC7 (BIT_MASK_DARF_RC7 << BIT_SHIFT_DARF_RC7) #define BIT_CLEAR_DARF_RC7(x) ((x) & (~BITS_DARF_RC7)) #define BIT_GET_DARF_RC7(x) (((x) >> BIT_SHIFT_DARF_RC7) & BIT_MASK_DARF_RC7) #define BIT_SET_DARF_RC7(x, v) (BIT_CLEAR_DARF_RC7(x) | BIT_DARF_RC7(v)) #define BIT_SHIFT_DARF_RC6 (40 & CPU_OPT_WIDTH) #define BIT_MASK_DARF_RC6 0x1f #define BIT_DARF_RC6(x) (((x) & BIT_MASK_DARF_RC6) << BIT_SHIFT_DARF_RC6) #define BITS_DARF_RC6 (BIT_MASK_DARF_RC6 << BIT_SHIFT_DARF_RC6) #define BIT_CLEAR_DARF_RC6(x) ((x) & (~BITS_DARF_RC6)) #define BIT_GET_DARF_RC6(x) (((x) >> BIT_SHIFT_DARF_RC6) & BIT_MASK_DARF_RC6) #define BIT_SET_DARF_RC6(x, v) (BIT_CLEAR_DARF_RC6(x) | BIT_DARF_RC6(v)) #define BIT_SHIFT_DARF_RC5 (32 & CPU_OPT_WIDTH) #define BIT_MASK_DARF_RC5 0x1f #define BIT_DARF_RC5(x) (((x) & BIT_MASK_DARF_RC5) << BIT_SHIFT_DARF_RC5) #define BITS_DARF_RC5 (BIT_MASK_DARF_RC5 << BIT_SHIFT_DARF_RC5) #define BIT_CLEAR_DARF_RC5(x) ((x) & (~BITS_DARF_RC5)) #define BIT_GET_DARF_RC5(x) (((x) >> BIT_SHIFT_DARF_RC5) & BIT_MASK_DARF_RC5) #define BIT_SET_DARF_RC5(x, v) (BIT_CLEAR_DARF_RC5(x) | BIT_DARF_RC5(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_DARFRC (Offset 0x0430) */ #define BIT_SHIFT_DARF_RC4 24 #define BIT_MASK_DARF_RC4 0x1f #define BIT_DARF_RC4(x) (((x) & BIT_MASK_DARF_RC4) << BIT_SHIFT_DARF_RC4) #define BITS_DARF_RC4 (BIT_MASK_DARF_RC4 << BIT_SHIFT_DARF_RC4) #define BIT_CLEAR_DARF_RC4(x) ((x) & (~BITS_DARF_RC4)) #define BIT_GET_DARF_RC4(x) (((x) >> BIT_SHIFT_DARF_RC4) & BIT_MASK_DARF_RC4) #define BIT_SET_DARF_RC4(x, v) (BIT_CLEAR_DARF_RC4(x) | BIT_DARF_RC4(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_DARFRC (Offset 0x0430) */ #define BIT_SHIFT_DARF_RC4_V1 24 #define BIT_MASK_DARF_RC4_V1 0x3f #define BIT_DARF_RC4_V1(x) \ (((x) & BIT_MASK_DARF_RC4_V1) << BIT_SHIFT_DARF_RC4_V1) #define BITS_DARF_RC4_V1 (BIT_MASK_DARF_RC4_V1 << BIT_SHIFT_DARF_RC4_V1) #define BIT_CLEAR_DARF_RC4_V1(x) ((x) & (~BITS_DARF_RC4_V1)) #define BIT_GET_DARF_RC4_V1(x) \ (((x) >> BIT_SHIFT_DARF_RC4_V1) & BIT_MASK_DARF_RC4_V1) #define BIT_SET_DARF_RC4_V1(x, v) \ (BIT_CLEAR_DARF_RC4_V1(x) | BIT_DARF_RC4_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_DARFRC (Offset 0x0430) */ #define BIT_SHIFT_DARF_RC3 16 #define BIT_MASK_DARF_RC3 0x1f #define BIT_DARF_RC3(x) (((x) & BIT_MASK_DARF_RC3) << BIT_SHIFT_DARF_RC3) #define BITS_DARF_RC3 (BIT_MASK_DARF_RC3 << BIT_SHIFT_DARF_RC3) #define BIT_CLEAR_DARF_RC3(x) ((x) & (~BITS_DARF_RC3)) #define BIT_GET_DARF_RC3(x) (((x) >> BIT_SHIFT_DARF_RC3) & BIT_MASK_DARF_RC3) #define BIT_SET_DARF_RC3(x, v) (BIT_CLEAR_DARF_RC3(x) | BIT_DARF_RC3(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_DARFRC (Offset 0x0430) */ #define BIT_SHIFT_DARF_RC3_V1 16 #define BIT_MASK_DARF_RC3_V1 0x3f #define BIT_DARF_RC3_V1(x) \ (((x) & BIT_MASK_DARF_RC3_V1) << BIT_SHIFT_DARF_RC3_V1) #define BITS_DARF_RC3_V1 (BIT_MASK_DARF_RC3_V1 << BIT_SHIFT_DARF_RC3_V1) #define BIT_CLEAR_DARF_RC3_V1(x) ((x) & (~BITS_DARF_RC3_V1)) #define BIT_GET_DARF_RC3_V1(x) \ (((x) >> BIT_SHIFT_DARF_RC3_V1) & BIT_MASK_DARF_RC3_V1) #define BIT_SET_DARF_RC3_V1(x, v) \ (BIT_CLEAR_DARF_RC3_V1(x) | BIT_DARF_RC3_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_DARFRC (Offset 0x0430) */ #define BIT_SHIFT_DARF_RC2 8 #define BIT_MASK_DARF_RC2 0x1f #define BIT_DARF_RC2(x) (((x) & BIT_MASK_DARF_RC2) << BIT_SHIFT_DARF_RC2) #define BITS_DARF_RC2 (BIT_MASK_DARF_RC2 << BIT_SHIFT_DARF_RC2) #define BIT_CLEAR_DARF_RC2(x) ((x) & (~BITS_DARF_RC2)) #define BIT_GET_DARF_RC2(x) (((x) >> BIT_SHIFT_DARF_RC2) & BIT_MASK_DARF_RC2) #define BIT_SET_DARF_RC2(x, v) (BIT_CLEAR_DARF_RC2(x) | BIT_DARF_RC2(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_DARFRC (Offset 0x0430) */ #define BIT_SHIFT_DARF_RC2_V1 8 #define BIT_MASK_DARF_RC2_V1 0x3f #define BIT_DARF_RC2_V1(x) \ (((x) & BIT_MASK_DARF_RC2_V1) << BIT_SHIFT_DARF_RC2_V1) #define BITS_DARF_RC2_V1 (BIT_MASK_DARF_RC2_V1 << BIT_SHIFT_DARF_RC2_V1) #define BIT_CLEAR_DARF_RC2_V1(x) ((x) & (~BITS_DARF_RC2_V1)) #define BIT_GET_DARF_RC2_V1(x) \ (((x) >> BIT_SHIFT_DARF_RC2_V1) & BIT_MASK_DARF_RC2_V1) #define BIT_SET_DARF_RC2_V1(x, v) \ (BIT_CLEAR_DARF_RC2_V1(x) | BIT_DARF_RC2_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_DARFRC (Offset 0x0430) */ #define BIT_SHIFT_DARF_RC1 0 #define BIT_MASK_DARF_RC1 0x1f #define BIT_DARF_RC1(x) (((x) & BIT_MASK_DARF_RC1) << BIT_SHIFT_DARF_RC1) #define BITS_DARF_RC1 (BIT_MASK_DARF_RC1 << BIT_SHIFT_DARF_RC1) #define BIT_CLEAR_DARF_RC1(x) ((x) & (~BITS_DARF_RC1)) #define BIT_GET_DARF_RC1(x) (((x) >> BIT_SHIFT_DARF_RC1) & BIT_MASK_DARF_RC1) #define BIT_SET_DARF_RC1(x, v) (BIT_CLEAR_DARF_RC1(x) | BIT_DARF_RC1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_DARFRC (Offset 0x0430) */ #define BIT_SHIFT_DARF_RC1_V1 0 #define BIT_MASK_DARF_RC1_V1 0x3f #define BIT_DARF_RC1_V1(x) \ (((x) & BIT_MASK_DARF_RC1_V1) << BIT_SHIFT_DARF_RC1_V1) #define BITS_DARF_RC1_V1 (BIT_MASK_DARF_RC1_V1 << BIT_SHIFT_DARF_RC1_V1) #define BIT_CLEAR_DARF_RC1_V1(x) ((x) & (~BITS_DARF_RC1_V1)) #define BIT_GET_DARF_RC1_V1(x) \ (((x) >> BIT_SHIFT_DARF_RC1_V1) & BIT_MASK_DARF_RC1_V1) #define BIT_SET_DARF_RC1_V1(x, v) \ (BIT_CLEAR_DARF_RC1_V1(x) | BIT_DARF_RC1_V1(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DARFRCH (Offset 0x0434) */ #define BIT_SHIFT_DARF_RC8_V1 24 #define BIT_MASK_DARF_RC8_V1 0x1f #define BIT_DARF_RC8_V1(x) \ (((x) & BIT_MASK_DARF_RC8_V1) << BIT_SHIFT_DARF_RC8_V1) #define BITS_DARF_RC8_V1 (BIT_MASK_DARF_RC8_V1 << BIT_SHIFT_DARF_RC8_V1) #define BIT_CLEAR_DARF_RC8_V1(x) ((x) & (~BITS_DARF_RC8_V1)) #define BIT_GET_DARF_RC8_V1(x) \ (((x) >> BIT_SHIFT_DARF_RC8_V1) & BIT_MASK_DARF_RC8_V1) #define BIT_SET_DARF_RC8_V1(x, v) \ (BIT_CLEAR_DARF_RC8_V1(x) | BIT_DARF_RC8_V1(v)) #define BIT_SHIFT_DARF_RC7_V1 16 #define BIT_MASK_DARF_RC7_V1 0x1f #define BIT_DARF_RC7_V1(x) \ (((x) & BIT_MASK_DARF_RC7_V1) << BIT_SHIFT_DARF_RC7_V1) #define BITS_DARF_RC7_V1 (BIT_MASK_DARF_RC7_V1 << BIT_SHIFT_DARF_RC7_V1) #define BIT_CLEAR_DARF_RC7_V1(x) ((x) & (~BITS_DARF_RC7_V1)) #define BIT_GET_DARF_RC7_V1(x) \ (((x) >> BIT_SHIFT_DARF_RC7_V1) & BIT_MASK_DARF_RC7_V1) #define BIT_SET_DARF_RC7_V1(x, v) \ (BIT_CLEAR_DARF_RC7_V1(x) | BIT_DARF_RC7_V1(v)) #define BIT_SHIFT_DARF_RC6_V1 8 #define BIT_MASK_DARF_RC6_V1 0x1f #define BIT_DARF_RC6_V1(x) \ (((x) & BIT_MASK_DARF_RC6_V1) << BIT_SHIFT_DARF_RC6_V1) #define BITS_DARF_RC6_V1 (BIT_MASK_DARF_RC6_V1 << BIT_SHIFT_DARF_RC6_V1) #define BIT_CLEAR_DARF_RC6_V1(x) ((x) & (~BITS_DARF_RC6_V1)) #define BIT_GET_DARF_RC6_V1(x) \ (((x) >> BIT_SHIFT_DARF_RC6_V1) & BIT_MASK_DARF_RC6_V1) #define BIT_SET_DARF_RC6_V1(x, v) \ (BIT_CLEAR_DARF_RC6_V1(x) | BIT_DARF_RC6_V1(v)) #define BIT_SHIFT_DARF_RC5_V1 0 #define BIT_MASK_DARF_RC5_V1 0x1f #define BIT_DARF_RC5_V1(x) \ (((x) & BIT_MASK_DARF_RC5_V1) << BIT_SHIFT_DARF_RC5_V1) #define BITS_DARF_RC5_V1 (BIT_MASK_DARF_RC5_V1 << BIT_SHIFT_DARF_RC5_V1) #define BIT_CLEAR_DARF_RC5_V1(x) ((x) & (~BITS_DARF_RC5_V1)) #define BIT_GET_DARF_RC5_V1(x) \ (((x) >> BIT_SHIFT_DARF_RC5_V1) & BIT_MASK_DARF_RC5_V1) #define BIT_SET_DARF_RC5_V1(x, v) \ (BIT_CLEAR_DARF_RC5_V1(x) | BIT_DARF_RC5_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RARFRC (Offset 0x0438) */ #define BIT_SHIFT_RARF_RC8 (56 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC8 0x1f #define BIT_RARF_RC8(x) (((x) & BIT_MASK_RARF_RC8) << BIT_SHIFT_RARF_RC8) #define BITS_RARF_RC8 (BIT_MASK_RARF_RC8 << BIT_SHIFT_RARF_RC8) #define BIT_CLEAR_RARF_RC8(x) ((x) & (~BITS_RARF_RC8)) #define BIT_GET_RARF_RC8(x) (((x) >> BIT_SHIFT_RARF_RC8) & BIT_MASK_RARF_RC8) #define BIT_SET_RARF_RC8(x, v) (BIT_CLEAR_RARF_RC8(x) | BIT_RARF_RC8(v)) #define BIT_SHIFT_RARF_RC7 (48 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC7 0x1f #define BIT_RARF_RC7(x) (((x) & BIT_MASK_RARF_RC7) << BIT_SHIFT_RARF_RC7) #define BITS_RARF_RC7 (BIT_MASK_RARF_RC7 << BIT_SHIFT_RARF_RC7) #define BIT_CLEAR_RARF_RC7(x) ((x) & (~BITS_RARF_RC7)) #define BIT_GET_RARF_RC7(x) (((x) >> BIT_SHIFT_RARF_RC7) & BIT_MASK_RARF_RC7) #define BIT_SET_RARF_RC7(x, v) (BIT_CLEAR_RARF_RC7(x) | BIT_RARF_RC7(v)) #define BIT_SHIFT_RARF_RC6 (40 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC6 0x1f #define BIT_RARF_RC6(x) (((x) & BIT_MASK_RARF_RC6) << BIT_SHIFT_RARF_RC6) #define BITS_RARF_RC6 (BIT_MASK_RARF_RC6 << BIT_SHIFT_RARF_RC6) #define BIT_CLEAR_RARF_RC6(x) ((x) & (~BITS_RARF_RC6)) #define BIT_GET_RARF_RC6(x) (((x) >> BIT_SHIFT_RARF_RC6) & BIT_MASK_RARF_RC6) #define BIT_SET_RARF_RC6(x, v) (BIT_CLEAR_RARF_RC6(x) | BIT_RARF_RC6(v)) #define BIT_SHIFT_RARF_RC5 (32 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC5 0x1f #define BIT_RARF_RC5(x) (((x) & BIT_MASK_RARF_RC5) << BIT_SHIFT_RARF_RC5) #define BITS_RARF_RC5 (BIT_MASK_RARF_RC5 << BIT_SHIFT_RARF_RC5) #define BIT_CLEAR_RARF_RC5(x) ((x) & (~BITS_RARF_RC5)) #define BIT_GET_RARF_RC5(x) (((x) >> BIT_SHIFT_RARF_RC5) & BIT_MASK_RARF_RC5) #define BIT_SET_RARF_RC5(x, v) (BIT_CLEAR_RARF_RC5(x) | BIT_RARF_RC5(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RARFRC (Offset 0x0438) */ #define BIT_SHIFT_RARF_RC4 24 #define BIT_MASK_RARF_RC4 0x1f #define BIT_RARF_RC4(x) (((x) & BIT_MASK_RARF_RC4) << BIT_SHIFT_RARF_RC4) #define BITS_RARF_RC4 (BIT_MASK_RARF_RC4 << BIT_SHIFT_RARF_RC4) #define BIT_CLEAR_RARF_RC4(x) ((x) & (~BITS_RARF_RC4)) #define BIT_GET_RARF_RC4(x) (((x) >> BIT_SHIFT_RARF_RC4) & BIT_MASK_RARF_RC4) #define BIT_SET_RARF_RC4(x, v) (BIT_CLEAR_RARF_RC4(x) | BIT_RARF_RC4(v)) #define BIT_SHIFT_RARF_RC3 16 #define BIT_MASK_RARF_RC3 0x1f #define BIT_RARF_RC3(x) (((x) & BIT_MASK_RARF_RC3) << BIT_SHIFT_RARF_RC3) #define BITS_RARF_RC3 (BIT_MASK_RARF_RC3 << BIT_SHIFT_RARF_RC3) #define BIT_CLEAR_RARF_RC3(x) ((x) & (~BITS_RARF_RC3)) #define BIT_GET_RARF_RC3(x) (((x) >> BIT_SHIFT_RARF_RC3) & BIT_MASK_RARF_RC3) #define BIT_SET_RARF_RC3(x, v) (BIT_CLEAR_RARF_RC3(x) | BIT_RARF_RC3(v)) #define BIT_SHIFT_RARF_RC2 8 #define BIT_MASK_RARF_RC2 0x1f #define BIT_RARF_RC2(x) (((x) & BIT_MASK_RARF_RC2) << BIT_SHIFT_RARF_RC2) #define BITS_RARF_RC2 (BIT_MASK_RARF_RC2 << BIT_SHIFT_RARF_RC2) #define BIT_CLEAR_RARF_RC2(x) ((x) & (~BITS_RARF_RC2)) #define BIT_GET_RARF_RC2(x) (((x) >> BIT_SHIFT_RARF_RC2) & BIT_MASK_RARF_RC2) #define BIT_SET_RARF_RC2(x, v) (BIT_CLEAR_RARF_RC2(x) | BIT_RARF_RC2(v)) #define BIT_SHIFT_RARF_RC1 0 #define BIT_MASK_RARF_RC1 0x1f #define BIT_RARF_RC1(x) (((x) & BIT_MASK_RARF_RC1) << BIT_SHIFT_RARF_RC1) #define BITS_RARF_RC1 (BIT_MASK_RARF_RC1 << BIT_SHIFT_RARF_RC1) #define BIT_CLEAR_RARF_RC1(x) ((x) & (~BITS_RARF_RC1)) #define BIT_GET_RARF_RC1(x) (((x) >> BIT_SHIFT_RARF_RC1) & BIT_MASK_RARF_RC1) #define BIT_SET_RARF_RC1(x, v) (BIT_CLEAR_RARF_RC1(x) | BIT_RARF_RC1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RARFRCH (Offset 0x043C) */ #define BIT_SHIFT_RARF_RC8_V1 24 #define BIT_MASK_RARF_RC8_V1 0x1f #define BIT_RARF_RC8_V1(x) \ (((x) & BIT_MASK_RARF_RC8_V1) << BIT_SHIFT_RARF_RC8_V1) #define BITS_RARF_RC8_V1 (BIT_MASK_RARF_RC8_V1 << BIT_SHIFT_RARF_RC8_V1) #define BIT_CLEAR_RARF_RC8_V1(x) ((x) & (~BITS_RARF_RC8_V1)) #define BIT_GET_RARF_RC8_V1(x) \ (((x) >> BIT_SHIFT_RARF_RC8_V1) & BIT_MASK_RARF_RC8_V1) #define BIT_SET_RARF_RC8_V1(x, v) \ (BIT_CLEAR_RARF_RC8_V1(x) | BIT_RARF_RC8_V1(v)) #define BIT_SHIFT_RARF_RC7_V1 16 #define BIT_MASK_RARF_RC7_V1 0x1f #define BIT_RARF_RC7_V1(x) \ (((x) & BIT_MASK_RARF_RC7_V1) << BIT_SHIFT_RARF_RC7_V1) #define BITS_RARF_RC7_V1 (BIT_MASK_RARF_RC7_V1 << BIT_SHIFT_RARF_RC7_V1) #define BIT_CLEAR_RARF_RC7_V1(x) ((x) & (~BITS_RARF_RC7_V1)) #define BIT_GET_RARF_RC7_V1(x) \ (((x) >> BIT_SHIFT_RARF_RC7_V1) & BIT_MASK_RARF_RC7_V1) #define BIT_SET_RARF_RC7_V1(x, v) \ (BIT_CLEAR_RARF_RC7_V1(x) | BIT_RARF_RC7_V1(v)) #define BIT_SHIFT_RARF_RC6_V1 8 #define BIT_MASK_RARF_RC6_V1 0x1f #define BIT_RARF_RC6_V1(x) \ (((x) & BIT_MASK_RARF_RC6_V1) << BIT_SHIFT_RARF_RC6_V1) #define BITS_RARF_RC6_V1 (BIT_MASK_RARF_RC6_V1 << BIT_SHIFT_RARF_RC6_V1) #define BIT_CLEAR_RARF_RC6_V1(x) ((x) & (~BITS_RARF_RC6_V1)) #define BIT_GET_RARF_RC6_V1(x) \ (((x) >> BIT_SHIFT_RARF_RC6_V1) & BIT_MASK_RARF_RC6_V1) #define BIT_SET_RARF_RC6_V1(x, v) \ (BIT_CLEAR_RARF_RC6_V1(x) | BIT_RARF_RC6_V1(v)) #define BIT_SHIFT_RARF_RC5_V1 0 #define BIT_MASK_RARF_RC5_V1 0x1f #define BIT_RARF_RC5_V1(x) \ (((x) & BIT_MASK_RARF_RC5_V1) << BIT_SHIFT_RARF_RC5_V1) #define BITS_RARF_RC5_V1 (BIT_MASK_RARF_RC5_V1 << BIT_SHIFT_RARF_RC5_V1) #define BIT_CLEAR_RARF_RC5_V1(x) ((x) & (~BITS_RARF_RC5_V1)) #define BIT_GET_RARF_RC5_V1(x) \ (((x) >> BIT_SHIFT_RARF_RC5_V1) & BIT_MASK_RARF_RC5_V1) #define BIT_SET_RARF_RC5_V1(x, v) \ (BIT_CLEAR_RARF_RC5_V1(x) | BIT_RARF_RC5_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RRSR (Offset 0x0440) */ #define BIT_EN_VHTBW_FALL BIT(31) #define BIT_EN_HTBW_FALL BIT(30) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RRSR (Offset 0x0440) */ #define BIT_SHIFT_RRSR_RSC 21 #define BIT_MASK_RRSR_RSC 0x3 #define BIT_RRSR_RSC(x) (((x) & BIT_MASK_RRSR_RSC) << BIT_SHIFT_RRSR_RSC) #define BITS_RRSR_RSC (BIT_MASK_RRSR_RSC << BIT_SHIFT_RRSR_RSC) #define BIT_CLEAR_RRSR_RSC(x) ((x) & (~BITS_RRSR_RSC)) #define BIT_GET_RRSR_RSC(x) (((x) >> BIT_SHIFT_RRSR_RSC) & BIT_MASK_RRSR_RSC) #define BIT_SET_RRSR_RSC(x, v) (BIT_CLEAR_RRSR_RSC(x) | BIT_RRSR_RSC(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RRSR (Offset 0x0440) */ #define BIT_RRSR_BW BIT(20) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RRSR (Offset 0x0440) */ #define BIT_SHIFT_RRSC_BITMAP 0 #define BIT_MASK_RRSC_BITMAP 0xfffff #define BIT_RRSC_BITMAP(x) \ (((x) & BIT_MASK_RRSC_BITMAP) << BIT_SHIFT_RRSC_BITMAP) #define BITS_RRSC_BITMAP (BIT_MASK_RRSC_BITMAP << BIT_SHIFT_RRSC_BITMAP) #define BIT_CLEAR_RRSC_BITMAP(x) ((x) & (~BITS_RRSC_BITMAP)) #define BIT_GET_RRSC_BITMAP(x) \ (((x) >> BIT_SHIFT_RRSC_BITMAP) & BIT_MASK_RRSC_BITMAP) #define BIT_SET_RRSC_BITMAP(x, v) \ (BIT_CLEAR_RRSC_BITMAP(x) | BIT_RRSC_BITMAP(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_ARFR0 (Offset 0x0444) */ #define BIT_SHIFT_ARFR0_V1 0 #define BIT_MASK_ARFR0_V1 0xffffffffffffffffL #define BIT_ARFR0_V1(x) (((x) & BIT_MASK_ARFR0_V1) << BIT_SHIFT_ARFR0_V1) #define BITS_ARFR0_V1 (BIT_MASK_ARFR0_V1 << BIT_SHIFT_ARFR0_V1) #define BIT_CLEAR_ARFR0_V1(x) ((x) & (~BITS_ARFR0_V1)) #define BIT_GET_ARFR0_V1(x) (((x) >> BIT_SHIFT_ARFR0_V1) & BIT_MASK_ARFR0_V1) #define BIT_SET_ARFR0_V1(x, v) (BIT_CLEAR_ARFR0_V1(x) | BIT_ARFR0_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ARFR0 (Offset 0x0444) */ #define BIT_SHIFT_ARFRL0 0 #define BIT_MASK_ARFRL0 0xffffffffL #define BIT_ARFRL0(x) (((x) & BIT_MASK_ARFRL0) << BIT_SHIFT_ARFRL0) #define BITS_ARFRL0 (BIT_MASK_ARFRL0 << BIT_SHIFT_ARFRL0) #define BIT_CLEAR_ARFRL0(x) ((x) & (~BITS_ARFRL0)) #define BIT_GET_ARFRL0(x) (((x) >> BIT_SHIFT_ARFRL0) & BIT_MASK_ARFRL0) #define BIT_SET_ARFRL0(x, v) (BIT_CLEAR_ARFRL0(x) | BIT_ARFRL0(v)) /* 2 REG_ARFRH0 (Offset 0x0448) */ #define BIT_SHIFT_ARFRH0 0 #define BIT_MASK_ARFRH0 0xffffffffL #define BIT_ARFRH0(x) (((x) & BIT_MASK_ARFRH0) << BIT_SHIFT_ARFRH0) #define BITS_ARFRH0 (BIT_MASK_ARFRH0 << BIT_SHIFT_ARFRH0) #define BIT_CLEAR_ARFRH0(x) ((x) & (~BITS_ARFRH0)) #define BIT_GET_ARFRH0(x) (((x) >> BIT_SHIFT_ARFRH0) & BIT_MASK_ARFRH0) #define BIT_SET_ARFRH0(x, v) (BIT_CLEAR_ARFRH0(x) | BIT_ARFRH0(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_REG_ARFR_WT0 (Offset 0x044C) */ #define BIT_SHIFT_RATE7_WEIGHTING 28 #define BIT_MASK_RATE7_WEIGHTING 0xf #define BIT_RATE7_WEIGHTING(x) \ (((x) & BIT_MASK_RATE7_WEIGHTING) << BIT_SHIFT_RATE7_WEIGHTING) #define BITS_RATE7_WEIGHTING \ (BIT_MASK_RATE7_WEIGHTING << BIT_SHIFT_RATE7_WEIGHTING) #define BIT_CLEAR_RATE7_WEIGHTING(x) ((x) & (~BITS_RATE7_WEIGHTING)) #define BIT_GET_RATE7_WEIGHTING(x) \ (((x) >> BIT_SHIFT_RATE7_WEIGHTING) & BIT_MASK_RATE7_WEIGHTING) #define BIT_SET_RATE7_WEIGHTING(x, v) \ (BIT_CLEAR_RATE7_WEIGHTING(x) | BIT_RATE7_WEIGHTING(v)) #define BIT_SHIFT_RATE6_WEIGHTING 24 #define BIT_MASK_RATE6_WEIGHTING 0xf #define BIT_RATE6_WEIGHTING(x) \ (((x) & BIT_MASK_RATE6_WEIGHTING) << BIT_SHIFT_RATE6_WEIGHTING) #define BITS_RATE6_WEIGHTING \ (BIT_MASK_RATE6_WEIGHTING << BIT_SHIFT_RATE6_WEIGHTING) #define BIT_CLEAR_RATE6_WEIGHTING(x) ((x) & (~BITS_RATE6_WEIGHTING)) #define BIT_GET_RATE6_WEIGHTING(x) \ (((x) >> BIT_SHIFT_RATE6_WEIGHTING) & BIT_MASK_RATE6_WEIGHTING) #define BIT_SET_RATE6_WEIGHTING(x, v) \ (BIT_CLEAR_RATE6_WEIGHTING(x) | BIT_RATE6_WEIGHTING(v)) #define BIT_SHIFT_RATE5_WEIGHTING 20 #define BIT_MASK_RATE5_WEIGHTING 0xf #define BIT_RATE5_WEIGHTING(x) \ (((x) & BIT_MASK_RATE5_WEIGHTING) << BIT_SHIFT_RATE5_WEIGHTING) #define BITS_RATE5_WEIGHTING \ (BIT_MASK_RATE5_WEIGHTING << BIT_SHIFT_RATE5_WEIGHTING) #define BIT_CLEAR_RATE5_WEIGHTING(x) ((x) & (~BITS_RATE5_WEIGHTING)) #define BIT_GET_RATE5_WEIGHTING(x) \ (((x) >> BIT_SHIFT_RATE5_WEIGHTING) & BIT_MASK_RATE5_WEIGHTING) #define BIT_SET_RATE5_WEIGHTING(x, v) \ (BIT_CLEAR_RATE5_WEIGHTING(x) | BIT_RATE5_WEIGHTING(v)) #define BIT_SHIFT_RATE4_WEIGHTING 16 #define BIT_MASK_RATE4_WEIGHTING 0xf #define BIT_RATE4_WEIGHTING(x) \ (((x) & BIT_MASK_RATE4_WEIGHTING) << BIT_SHIFT_RATE4_WEIGHTING) #define BITS_RATE4_WEIGHTING \ (BIT_MASK_RATE4_WEIGHTING << BIT_SHIFT_RATE4_WEIGHTING) #define BIT_CLEAR_RATE4_WEIGHTING(x) ((x) & (~BITS_RATE4_WEIGHTING)) #define BIT_GET_RATE4_WEIGHTING(x) \ (((x) >> BIT_SHIFT_RATE4_WEIGHTING) & BIT_MASK_RATE4_WEIGHTING) #define BIT_SET_RATE4_WEIGHTING(x, v) \ (BIT_CLEAR_RATE4_WEIGHTING(x) | BIT_RATE4_WEIGHTING(v)) #define BIT_SHIFT_RATE3_WEIGHTING 12 #define BIT_MASK_RATE3_WEIGHTING 0xf #define BIT_RATE3_WEIGHTING(x) \ (((x) & BIT_MASK_RATE3_WEIGHTING) << BIT_SHIFT_RATE3_WEIGHTING) #define BITS_RATE3_WEIGHTING \ (BIT_MASK_RATE3_WEIGHTING << BIT_SHIFT_RATE3_WEIGHTING) #define BIT_CLEAR_RATE3_WEIGHTING(x) ((x) & (~BITS_RATE3_WEIGHTING)) #define BIT_GET_RATE3_WEIGHTING(x) \ (((x) >> BIT_SHIFT_RATE3_WEIGHTING) & BIT_MASK_RATE3_WEIGHTING) #define BIT_SET_RATE3_WEIGHTING(x, v) \ (BIT_CLEAR_RATE3_WEIGHTING(x) | BIT_RATE3_WEIGHTING(v)) #define BIT_SHIFT_RATE2_WEIGHTING 8 #define BIT_MASK_RATE2_WEIGHTING 0xf #define BIT_RATE2_WEIGHTING(x) \ (((x) & BIT_MASK_RATE2_WEIGHTING) << BIT_SHIFT_RATE2_WEIGHTING) #define BITS_RATE2_WEIGHTING \ (BIT_MASK_RATE2_WEIGHTING << BIT_SHIFT_RATE2_WEIGHTING) #define BIT_CLEAR_RATE2_WEIGHTING(x) ((x) & (~BITS_RATE2_WEIGHTING)) #define BIT_GET_RATE2_WEIGHTING(x) \ (((x) >> BIT_SHIFT_RATE2_WEIGHTING) & BIT_MASK_RATE2_WEIGHTING) #define BIT_SET_RATE2_WEIGHTING(x, v) \ (BIT_CLEAR_RATE2_WEIGHTING(x) | BIT_RATE2_WEIGHTING(v)) #define BIT_SHIFT_RATE1_WEIGHTING 4 #define BIT_MASK_RATE1_WEIGHTING 0xf #define BIT_RATE1_WEIGHTING(x) \ (((x) & BIT_MASK_RATE1_WEIGHTING) << BIT_SHIFT_RATE1_WEIGHTING) #define BITS_RATE1_WEIGHTING \ (BIT_MASK_RATE1_WEIGHTING << BIT_SHIFT_RATE1_WEIGHTING) #define BIT_CLEAR_RATE1_WEIGHTING(x) ((x) & (~BITS_RATE1_WEIGHTING)) #define BIT_GET_RATE1_WEIGHTING(x) \ (((x) >> BIT_SHIFT_RATE1_WEIGHTING) & BIT_MASK_RATE1_WEIGHTING) #define BIT_SET_RATE1_WEIGHTING(x, v) \ (BIT_CLEAR_RATE1_WEIGHTING(x) | BIT_RATE1_WEIGHTING(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_ARFR1_V1 (Offset 0x044C) */ #define BIT_SHIFT_ARFR1_V1 0 #define BIT_MASK_ARFR1_V1 0xffffffffffffffffL #define BIT_ARFR1_V1(x) (((x) & BIT_MASK_ARFR1_V1) << BIT_SHIFT_ARFR1_V1) #define BITS_ARFR1_V1 (BIT_MASK_ARFR1_V1 << BIT_SHIFT_ARFR1_V1) #define BIT_CLEAR_ARFR1_V1(x) ((x) & (~BITS_ARFR1_V1)) #define BIT_GET_ARFR1_V1(x) (((x) >> BIT_SHIFT_ARFR1_V1) & BIT_MASK_ARFR1_V1) #define BIT_SET_ARFR1_V1(x, v) (BIT_CLEAR_ARFR1_V1(x) | BIT_ARFR1_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_REG_ARFR_WT0 (Offset 0x044C) */ #define BIT_SHIFT_RATE0_WEIGHTING 0 #define BIT_MASK_RATE0_WEIGHTING 0xf #define BIT_RATE0_WEIGHTING(x) \ (((x) & BIT_MASK_RATE0_WEIGHTING) << BIT_SHIFT_RATE0_WEIGHTING) #define BITS_RATE0_WEIGHTING \ (BIT_MASK_RATE0_WEIGHTING << BIT_SHIFT_RATE0_WEIGHTING) #define BIT_CLEAR_RATE0_WEIGHTING(x) ((x) & (~BITS_RATE0_WEIGHTING)) #define BIT_GET_RATE0_WEIGHTING(x) \ (((x) >> BIT_SHIFT_RATE0_WEIGHTING) & BIT_MASK_RATE0_WEIGHTING) #define BIT_SET_RATE0_WEIGHTING(x, v) \ (BIT_CLEAR_RATE0_WEIGHTING(x) | BIT_RATE0_WEIGHTING(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ARFR1_V1 (Offset 0x044C) */ #define BIT_SHIFT_ARFRL1 0 #define BIT_MASK_ARFRL1 0xffffffffL #define BIT_ARFRL1(x) (((x) & BIT_MASK_ARFRL1) << BIT_SHIFT_ARFRL1) #define BITS_ARFRL1 (BIT_MASK_ARFRL1 << BIT_SHIFT_ARFRL1) #define BIT_CLEAR_ARFRL1(x) ((x) & (~BITS_ARFRL1)) #define BIT_GET_ARFRL1(x) (((x) >> BIT_SHIFT_ARFRL1) & BIT_MASK_ARFRL1) #define BIT_SET_ARFRL1(x, v) (BIT_CLEAR_ARFRL1(x) | BIT_ARFRL1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_REG_ARFR_WT1 (Offset 0x0450) */ #define BIT_SHIFT_RATE15_WEIGHTING 28 #define BIT_MASK_RATE15_WEIGHTING 0xf #define BIT_RATE15_WEIGHTING(x) \ (((x) & BIT_MASK_RATE15_WEIGHTING) << BIT_SHIFT_RATE15_WEIGHTING) #define BITS_RATE15_WEIGHTING \ (BIT_MASK_RATE15_WEIGHTING << BIT_SHIFT_RATE15_WEIGHTING) #define BIT_CLEAR_RATE15_WEIGHTING(x) ((x) & (~BITS_RATE15_WEIGHTING)) #define BIT_GET_RATE15_WEIGHTING(x) \ (((x) >> BIT_SHIFT_RATE15_WEIGHTING) & BIT_MASK_RATE15_WEIGHTING) #define BIT_SET_RATE15_WEIGHTING(x, v) \ (BIT_CLEAR_RATE15_WEIGHTING(x) | BIT_RATE15_WEIGHTING(v)) #define BIT_SHIFT_RATE14_WEIGHTING 24 #define BIT_MASK_RATE14_WEIGHTING 0xf #define BIT_RATE14_WEIGHTING(x) \ (((x) & BIT_MASK_RATE14_WEIGHTING) << BIT_SHIFT_RATE14_WEIGHTING) #define BITS_RATE14_WEIGHTING \ (BIT_MASK_RATE14_WEIGHTING << BIT_SHIFT_RATE14_WEIGHTING) #define BIT_CLEAR_RATE14_WEIGHTING(x) ((x) & (~BITS_RATE14_WEIGHTING)) #define BIT_GET_RATE14_WEIGHTING(x) \ (((x) >> BIT_SHIFT_RATE14_WEIGHTING) & BIT_MASK_RATE14_WEIGHTING) #define BIT_SET_RATE14_WEIGHTING(x, v) \ (BIT_CLEAR_RATE14_WEIGHTING(x) | BIT_RATE14_WEIGHTING(v)) #define BIT_SHIFT_RATE13_WEIGHTING 20 #define BIT_MASK_RATE13_WEIGHTING 0xf #define BIT_RATE13_WEIGHTING(x) \ (((x) & BIT_MASK_RATE13_WEIGHTING) << BIT_SHIFT_RATE13_WEIGHTING) #define BITS_RATE13_WEIGHTING \ (BIT_MASK_RATE13_WEIGHTING << BIT_SHIFT_RATE13_WEIGHTING) #define BIT_CLEAR_RATE13_WEIGHTING(x) ((x) & (~BITS_RATE13_WEIGHTING)) #define BIT_GET_RATE13_WEIGHTING(x) \ (((x) >> BIT_SHIFT_RATE13_WEIGHTING) & BIT_MASK_RATE13_WEIGHTING) #define BIT_SET_RATE13_WEIGHTING(x, v) \ (BIT_CLEAR_RATE13_WEIGHTING(x) | BIT_RATE13_WEIGHTING(v)) #define BIT_SHIFT_RATE12_WEIGHTING 16 #define BIT_MASK_RATE12_WEIGHTING 0xf #define BIT_RATE12_WEIGHTING(x) \ (((x) & BIT_MASK_RATE12_WEIGHTING) << BIT_SHIFT_RATE12_WEIGHTING) #define BITS_RATE12_WEIGHTING \ (BIT_MASK_RATE12_WEIGHTING << BIT_SHIFT_RATE12_WEIGHTING) #define BIT_CLEAR_RATE12_WEIGHTING(x) ((x) & (~BITS_RATE12_WEIGHTING)) #define BIT_GET_RATE12_WEIGHTING(x) \ (((x) >> BIT_SHIFT_RATE12_WEIGHTING) & BIT_MASK_RATE12_WEIGHTING) #define BIT_SET_RATE12_WEIGHTING(x, v) \ (BIT_CLEAR_RATE12_WEIGHTING(x) | BIT_RATE12_WEIGHTING(v)) #define BIT_SHIFT_RATE11_WEIGHTING 12 #define BIT_MASK_RATE11_WEIGHTING 0xf #define BIT_RATE11_WEIGHTING(x) \ (((x) & BIT_MASK_RATE11_WEIGHTING) << BIT_SHIFT_RATE11_WEIGHTING) #define BITS_RATE11_WEIGHTING \ (BIT_MASK_RATE11_WEIGHTING << BIT_SHIFT_RATE11_WEIGHTING) #define BIT_CLEAR_RATE11_WEIGHTING(x) ((x) & (~BITS_RATE11_WEIGHTING)) #define BIT_GET_RATE11_WEIGHTING(x) \ (((x) >> BIT_SHIFT_RATE11_WEIGHTING) & BIT_MASK_RATE11_WEIGHTING) #define BIT_SET_RATE11_WEIGHTING(x, v) \ (BIT_CLEAR_RATE11_WEIGHTING(x) | BIT_RATE11_WEIGHTING(v)) #define BIT_SHIFT_RATE10_WEIGHTING 8 #define BIT_MASK_RATE10_WEIGHTING 0xf #define BIT_RATE10_WEIGHTING(x) \ (((x) & BIT_MASK_RATE10_WEIGHTING) << BIT_SHIFT_RATE10_WEIGHTING) #define BITS_RATE10_WEIGHTING \ (BIT_MASK_RATE10_WEIGHTING << BIT_SHIFT_RATE10_WEIGHTING) #define BIT_CLEAR_RATE10_WEIGHTING(x) ((x) & (~BITS_RATE10_WEIGHTING)) #define BIT_GET_RATE10_WEIGHTING(x) \ (((x) >> BIT_SHIFT_RATE10_WEIGHTING) & BIT_MASK_RATE10_WEIGHTING) #define BIT_SET_RATE10_WEIGHTING(x, v) \ (BIT_CLEAR_RATE10_WEIGHTING(x) | BIT_RATE10_WEIGHTING(v)) #define BIT_SHIFT_RATE9_WEIGHTING 4 #define BIT_MASK_RATE9_WEIGHTING 0xf #define BIT_RATE9_WEIGHTING(x) \ (((x) & BIT_MASK_RATE9_WEIGHTING) << BIT_SHIFT_RATE9_WEIGHTING) #define BITS_RATE9_WEIGHTING \ (BIT_MASK_RATE9_WEIGHTING << BIT_SHIFT_RATE9_WEIGHTING) #define BIT_CLEAR_RATE9_WEIGHTING(x) ((x) & (~BITS_RATE9_WEIGHTING)) #define BIT_GET_RATE9_WEIGHTING(x) \ (((x) >> BIT_SHIFT_RATE9_WEIGHTING) & BIT_MASK_RATE9_WEIGHTING) #define BIT_SET_RATE9_WEIGHTING(x, v) \ (BIT_CLEAR_RATE9_WEIGHTING(x) | BIT_RATE9_WEIGHTING(v)) #define BIT_SHIFT_RATE8_WEIGHTING 0 #define BIT_MASK_RATE8_WEIGHTING 0xf #define BIT_RATE8_WEIGHTING(x) \ (((x) & BIT_MASK_RATE8_WEIGHTING) << BIT_SHIFT_RATE8_WEIGHTING) #define BITS_RATE8_WEIGHTING \ (BIT_MASK_RATE8_WEIGHTING << BIT_SHIFT_RATE8_WEIGHTING) #define BIT_CLEAR_RATE8_WEIGHTING(x) ((x) & (~BITS_RATE8_WEIGHTING)) #define BIT_GET_RATE8_WEIGHTING(x) \ (((x) >> BIT_SHIFT_RATE8_WEIGHTING) & BIT_MASK_RATE8_WEIGHTING) #define BIT_SET_RATE8_WEIGHTING(x, v) \ (BIT_CLEAR_RATE8_WEIGHTING(x) | BIT_RATE8_WEIGHTING(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ARFRH1_V1 (Offset 0x0450) */ #define BIT_SHIFT_ARFRH1 0 #define BIT_MASK_ARFRH1 0xffffffffL #define BIT_ARFRH1(x) (((x) & BIT_MASK_ARFRH1) << BIT_SHIFT_ARFRH1) #define BITS_ARFRH1 (BIT_MASK_ARFRH1 << BIT_SHIFT_ARFRH1) #define BIT_CLEAR_ARFRH1(x) ((x) & (~BITS_ARFRH1)) #define BIT_GET_ARFRH1(x) (((x) >> BIT_SHIFT_ARFRH1) & BIT_MASK_ARFRH1) #define BIT_SET_ARFRH1(x, v) (BIT_CLEAR_ARFRH1(x) | BIT_ARFRH1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_CCK_CHECK (Offset 0x0454) */ #define BIT_CHECK_CCK_EN BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CCK_CHECK (Offset 0x0454) */ #define BIT_EN_BCN_PKT_REL BIT(6) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CCK_CHECK (Offset 0x0454) */ #define BIT_EN_BCN_PKT_REL_P0 BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_CCK_CHECK (Offset 0x0454) */ #define BIT_BCN_PORT_SEL BIT(5) #define BIT_MOREDATA_BYPASS BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CCK_CHECK (Offset 0x0454) */ #define BIT_EN_CLR_CMD_REL_BCN_PKT BIT(3) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CCK_CHECK (Offset 0x0454) */ #define BIT_EN_CLR_CMD_REL_BCN_PKT_P0 BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CCK_CHECK (Offset 0x0454) */ #define BIT_R_EN_SET_MOREDATA BIT(2) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CCK_CHECK (Offset 0x0454) */ #define BIT_EN_SET_MOREDATA BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CCK_CHECK (Offset 0x0454) */ #define BIT__R_DIS_CLEAR_MACID_RELEASE BIT(1) #define BIT__R_MACID_RELEASE_EN BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AMPDU_BURST_CTRL (Offset 0x0455) */ #define BIT_AMPDU_BURST_GLOBAL_EN BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_AMPDU_MAX_TIME (Offset 0x0456) */ #define BIT_SHIFT_AMPDU_MAX_TIME 0 #define BIT_MASK_AMPDU_MAX_TIME 0xff #define BIT_AMPDU_MAX_TIME(x) \ (((x) & BIT_MASK_AMPDU_MAX_TIME) << BIT_SHIFT_AMPDU_MAX_TIME) #define BITS_AMPDU_MAX_TIME \ (BIT_MASK_AMPDU_MAX_TIME << BIT_SHIFT_AMPDU_MAX_TIME) #define BIT_CLEAR_AMPDU_MAX_TIME(x) ((x) & (~BITS_AMPDU_MAX_TIME)) #define BIT_GET_AMPDU_MAX_TIME(x) \ (((x) >> BIT_SHIFT_AMPDU_MAX_TIME) & BIT_MASK_AMPDU_MAX_TIME) #define BIT_SET_AMPDU_MAX_TIME(x, v) \ (BIT_CLEAR_AMPDU_MAX_TIME(x) | BIT_AMPDU_MAX_TIME(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_BCNQ1_BDNY_V1 (Offset 0x0456) */ #define BIT_SHIFT_BCNQ1_PGBNDY_V1 0 #define BIT_MASK_BCNQ1_PGBNDY_V1 0xfff #define BIT_BCNQ1_PGBNDY_V1(x) \ (((x) & BIT_MASK_BCNQ1_PGBNDY_V1) << BIT_SHIFT_BCNQ1_PGBNDY_V1) #define BITS_BCNQ1_PGBNDY_V1 \ (BIT_MASK_BCNQ1_PGBNDY_V1 << BIT_SHIFT_BCNQ1_PGBNDY_V1) #define BIT_CLEAR_BCNQ1_PGBNDY_V1(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1)) #define BIT_GET_BCNQ1_PGBNDY_V1(x) \ (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1) & BIT_MASK_BCNQ1_PGBNDY_V1) #define BIT_SET_BCNQ1_PGBNDY_V1(x, v) \ (BIT_CLEAR_BCNQ1_PGBNDY_V1(x) | BIT_BCNQ1_PGBNDY_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TAB_SEL (Offset 0x0456) */ #define BIT_SHIFT_RATE_SEL 0 #define BIT_MASK_RATE_SEL 0xf #define BIT_RATE_SEL(x) (((x) & BIT_MASK_RATE_SEL) << BIT_SHIFT_RATE_SEL) #define BITS_RATE_SEL (BIT_MASK_RATE_SEL << BIT_SHIFT_RATE_SEL) #define BIT_CLEAR_RATE_SEL(x) ((x) & (~BITS_RATE_SEL)) #define BIT_GET_RATE_SEL(x) (((x) >> BIT_SHIFT_RATE_SEL) & BIT_MASK_RATE_SEL) #define BIT_SET_RATE_SEL(x, v) (BIT_CLEAR_RATE_SEL(x) | BIT_RATE_SEL(v)) /* 2 REG_BCN_INVALID_CTRL (Offset 0x0457) */ #define BIT_EN_CLR_CMD_REL_BCN_PKT_P4 BIT(7) #define BIT_EN_BCN_PKT_REL_P4 BIT(6) #define BIT_EN_CLR_CMD_REL_BCN_PKT_P3 BIT(5) #define BIT_EN_BCN_PKT_REL_P3 BIT(4) #define BIT_EN_CLR_CMD_REL_BCN_PKT_P2 BIT(3) #define BIT_EN_BCN_PKT_REL_P2 BIT(2) #define BIT_EN_CLR_CMD_REL_BCN_PKT_P1 BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BCNQ1_BDNY (Offset 0x0457) */ #define BIT_SHIFT_BCNQ1_PGBNDY 0 #define BIT_MASK_BCNQ1_PGBNDY 0xff #define BIT_BCNQ1_PGBNDY(x) \ (((x) & BIT_MASK_BCNQ1_PGBNDY) << BIT_SHIFT_BCNQ1_PGBNDY) #define BITS_BCNQ1_PGBNDY (BIT_MASK_BCNQ1_PGBNDY << BIT_SHIFT_BCNQ1_PGBNDY) #define BIT_CLEAR_BCNQ1_PGBNDY(x) ((x) & (~BITS_BCNQ1_PGBNDY)) #define BIT_GET_BCNQ1_PGBNDY(x) \ (((x) >> BIT_SHIFT_BCNQ1_PGBNDY) & BIT_MASK_BCNQ1_PGBNDY) #define BIT_SET_BCNQ1_PGBNDY(x, v) \ (BIT_CLEAR_BCNQ1_PGBNDY(x) | BIT_BCNQ1_PGBNDY(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_BCN_INVALID_CTRL (Offset 0x0457) */ #define BIT_EN_BCN_PKT_REL_P1 BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AMPDU_MAX_LENGTH (Offset 0x0458) */ #define BIT_SHIFT_AMPDU_MAX_LENGTH 0 #define BIT_MASK_AMPDU_MAX_LENGTH 0xffffffffL #define BIT_AMPDU_MAX_LENGTH(x) \ (((x) & BIT_MASK_AMPDU_MAX_LENGTH) << BIT_SHIFT_AMPDU_MAX_LENGTH) #define BITS_AMPDU_MAX_LENGTH \ (BIT_MASK_AMPDU_MAX_LENGTH << BIT_SHIFT_AMPDU_MAX_LENGTH) #define BIT_CLEAR_AMPDU_MAX_LENGTH(x) ((x) & (~BITS_AMPDU_MAX_LENGTH)) #define BIT_GET_AMPDU_MAX_LENGTH(x) \ (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH) & BIT_MASK_AMPDU_MAX_LENGTH) #define BIT_SET_AMPDU_MAX_LENGTH(x, v) \ (BIT_CLEAR_AMPDU_MAX_LENGTH(x) | BIT_AMPDU_MAX_LENGTH(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_AMPDU_MAX_LENGTH_HT (Offset 0x0458) */ #define BIT_SHIFT_AMPDU_MAX_LENGTH_HT 0 #define BIT_MASK_AMPDU_MAX_LENGTH_HT 0xffff #define BIT_AMPDU_MAX_LENGTH_HT(x) \ (((x) & BIT_MASK_AMPDU_MAX_LENGTH_HT) << BIT_SHIFT_AMPDU_MAX_LENGTH_HT) #define BITS_AMPDU_MAX_LENGTH_HT \ (BIT_MASK_AMPDU_MAX_LENGTH_HT << BIT_SHIFT_AMPDU_MAX_LENGTH_HT) #define BIT_CLEAR_AMPDU_MAX_LENGTH_HT(x) ((x) & (~BITS_AMPDU_MAX_LENGTH_HT)) #define BIT_GET_AMPDU_MAX_LENGTH_HT(x) \ (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_HT) & BIT_MASK_AMPDU_MAX_LENGTH_HT) #define BIT_SET_AMPDU_MAX_LENGTH_HT(x, v) \ (BIT_CLEAR_AMPDU_MAX_LENGTH_HT(x) | BIT_AMPDU_MAX_LENGTH_HT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_ACQ_STOP (Offset 0x045C) */ #define BIT_AC7Q_STOP BIT(7) #define BIT_AC6Q_STOP BIT(6) #define BIT_AC5Q_STOP BIT(5) #define BIT_AC4Q_STOP BIT(4) #define BIT_AC3Q_STOP BIT(3) #define BIT_AC2Q_STOP BIT(2) #define BIT_AC1Q_STOP BIT(1) #define BIT_AC0Q_STOP BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_LBK_BUF_HD (Offset 0x045D) */ #define BIT_SHIFT_WMAC_LBK_BUF_HEAD 0 #define BIT_MASK_WMAC_LBK_BUF_HEAD 0xff #define BIT_WMAC_LBK_BUF_HEAD(x) \ (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD) << BIT_SHIFT_WMAC_LBK_BUF_HEAD) #define BITS_WMAC_LBK_BUF_HEAD \ (BIT_MASK_WMAC_LBK_BUF_HEAD << BIT_SHIFT_WMAC_LBK_BUF_HEAD) #define BIT_CLEAR_WMAC_LBK_BUF_HEAD(x) ((x) & (~BITS_WMAC_LBK_BUF_HEAD)) #define BIT_GET_WMAC_LBK_BUF_HEAD(x) \ (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD) & BIT_MASK_WMAC_LBK_BUF_HEAD) #define BIT_SET_WMAC_LBK_BUF_HEAD(x, v) \ (BIT_CLEAR_WMAC_LBK_BUF_HEAD(x) | BIT_WMAC_LBK_BUF_HEAD(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_NDPA_RATE (Offset 0x045D) */ #define BIT_SHIFT_R_NDPA_RATE_V1 0 #define BIT_MASK_R_NDPA_RATE_V1 0xff #define BIT_R_NDPA_RATE_V1(x) \ (((x) & BIT_MASK_R_NDPA_RATE_V1) << BIT_SHIFT_R_NDPA_RATE_V1) #define BITS_R_NDPA_RATE_V1 \ (BIT_MASK_R_NDPA_RATE_V1 << BIT_SHIFT_R_NDPA_RATE_V1) #define BIT_CLEAR_R_NDPA_RATE_V1(x) ((x) & (~BITS_R_NDPA_RATE_V1)) #define BIT_GET_R_NDPA_RATE_V1(x) \ (((x) >> BIT_SHIFT_R_NDPA_RATE_V1) & BIT_MASK_R_NDPA_RATE_V1) #define BIT_SET_R_NDPA_RATE_V1(x, v) \ (BIT_CLEAR_R_NDPA_RATE_V1(x) | BIT_R_NDPA_RATE_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ #define BIT_R_EN_GNT_BT_AWAKE BIT(3) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ #define BIT_EN_GNT_BT_AWAKE BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ #define BIT_EN_EOF_V1 BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ #define BIT_DIS_OQT_BLOCK BIT(1) #define BIT_SEARCH_QUEUE_EN BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ #define BIT_R_DIS_MACID_RELEASE_RTY BIT(5) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ #define BIT_DIS_MACID_RELEASE_RTY BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ #define BIT_SHIFT_BW_SIGTA 3 #define BIT_MASK_BW_SIGTA 0x3 #define BIT_BW_SIGTA(x) (((x) & BIT_MASK_BW_SIGTA) << BIT_SHIFT_BW_SIGTA) #define BITS_BW_SIGTA (BIT_MASK_BW_SIGTA << BIT_SHIFT_BW_SIGTA) #define BIT_CLEAR_BW_SIGTA(x) ((x) & (~BITS_BW_SIGTA)) #define BIT_GET_BW_SIGTA(x) (((x) >> BIT_SHIFT_BW_SIGTA) & BIT_MASK_BW_SIGTA) #define BIT_SET_BW_SIGTA(x, v) (BIT_CLEAR_BW_SIGTA(x) | BIT_BW_SIGTA(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ #define BIT_SHIFT_R_NDPA_RATE 2 #define BIT_MASK_R_NDPA_RATE 0x3f #define BIT_R_NDPA_RATE(x) \ (((x) & BIT_MASK_R_NDPA_RATE) << BIT_SHIFT_R_NDPA_RATE) #define BITS_R_NDPA_RATE (BIT_MASK_R_NDPA_RATE << BIT_SHIFT_R_NDPA_RATE) #define BIT_CLEAR_R_NDPA_RATE(x) ((x) & (~BITS_R_NDPA_RATE)) #define BIT_GET_R_NDPA_RATE(x) \ (((x) >> BIT_SHIFT_R_NDPA_RATE) & BIT_MASK_R_NDPA_RATE) #define BIT_SET_R_NDPA_RATE(x, v) \ (BIT_CLEAR_R_NDPA_RATE(x) | BIT_R_NDPA_RATE(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ #define BIT_EN_BAR_SIGTA BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ #define BIT_SHIFT_R_NDPA_BW 0 #define BIT_MASK_R_NDPA_BW 0x3 #define BIT_R_NDPA_BW(x) (((x) & BIT_MASK_R_NDPA_BW) << BIT_SHIFT_R_NDPA_BW) #define BITS_R_NDPA_BW (BIT_MASK_R_NDPA_BW << BIT_SHIFT_R_NDPA_BW) #define BIT_CLEAR_R_NDPA_BW(x) ((x) & (~BITS_R_NDPA_BW)) #define BIT_GET_R_NDPA_BW(x) (((x) >> BIT_SHIFT_R_NDPA_BW) & BIT_MASK_R_NDPA_BW) #define BIT_SET_R_NDPA_BW(x, v) (BIT_CLEAR_R_NDPA_BW(x) | BIT_R_NDPA_BW(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ #define BIT_SHIFT_NDPA_BW 0 #define BIT_MASK_NDPA_BW 0x3 #define BIT_NDPA_BW(x) (((x) & BIT_MASK_NDPA_BW) << BIT_SHIFT_NDPA_BW) #define BITS_NDPA_BW (BIT_MASK_NDPA_BW << BIT_SHIFT_NDPA_BW) #define BIT_CLEAR_NDPA_BW(x) ((x) & (~BITS_NDPA_BW)) #define BIT_GET_NDPA_BW(x) (((x) >> BIT_SHIFT_NDPA_BW) & BIT_MASK_NDPA_BW) #define BIT_SET_NDPA_BW(x, v) (BIT_CLEAR_NDPA_BW(x) | BIT_NDPA_BW(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FAST_EDCA_CTRL (Offset 0x0460) */ #define BIT_SHIFT_FAST_EDCA_TO_V1 16 #define BIT_MASK_FAST_EDCA_TO_V1 0xff #define BIT_FAST_EDCA_TO_V1(x) \ (((x) & BIT_MASK_FAST_EDCA_TO_V1) << BIT_SHIFT_FAST_EDCA_TO_V1) #define BITS_FAST_EDCA_TO_V1 \ (BIT_MASK_FAST_EDCA_TO_V1 << BIT_SHIFT_FAST_EDCA_TO_V1) #define BIT_CLEAR_FAST_EDCA_TO_V1(x) ((x) & (~BITS_FAST_EDCA_TO_V1)) #define BIT_GET_FAST_EDCA_TO_V1(x) \ (((x) >> BIT_SHIFT_FAST_EDCA_TO_V1) & BIT_MASK_FAST_EDCA_TO_V1) #define BIT_SET_FAST_EDCA_TO_V1(x, v) \ (BIT_CLEAR_FAST_EDCA_TO_V1(x) | BIT_FAST_EDCA_TO_V1(v)) #define BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH 12 #define BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH 0xf #define BIT_AC3_AC7_FAST_EDCA_PKT_TH(x) \ (((x) & BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH) \ << BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH) #define BITS_AC3_AC7_FAST_EDCA_PKT_TH \ (BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH \ << BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH) #define BIT_CLEAR_AC3_AC7_FAST_EDCA_PKT_TH(x) \ ((x) & (~BITS_AC3_AC7_FAST_EDCA_PKT_TH)) #define BIT_GET_AC3_AC7_FAST_EDCA_PKT_TH(x) \ (((x) >> BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH) & \ BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH) #define BIT_SET_AC3_AC7_FAST_EDCA_PKT_TH(x, v) \ (BIT_CLEAR_AC3_AC7_FAST_EDCA_PKT_TH(x) | \ BIT_AC3_AC7_FAST_EDCA_PKT_TH(v)) #define BIT_SHIFT_AC2_FAST_EDCA_PKT_TH 8 #define BIT_MASK_AC2_FAST_EDCA_PKT_TH 0xf #define BIT_AC2_FAST_EDCA_PKT_TH(x) \ (((x) & BIT_MASK_AC2_FAST_EDCA_PKT_TH) \ << BIT_SHIFT_AC2_FAST_EDCA_PKT_TH) #define BITS_AC2_FAST_EDCA_PKT_TH \ (BIT_MASK_AC2_FAST_EDCA_PKT_TH << BIT_SHIFT_AC2_FAST_EDCA_PKT_TH) #define BIT_CLEAR_AC2_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_AC2_FAST_EDCA_PKT_TH)) #define BIT_GET_AC2_FAST_EDCA_PKT_TH(x) \ (((x) >> BIT_SHIFT_AC2_FAST_EDCA_PKT_TH) & \ BIT_MASK_AC2_FAST_EDCA_PKT_TH) #define BIT_SET_AC2_FAST_EDCA_PKT_TH(x, v) \ (BIT_CLEAR_AC2_FAST_EDCA_PKT_TH(x) | BIT_AC2_FAST_EDCA_PKT_TH(v)) #define BIT_SHIFT_AC1_FAST_EDCA_PKT_TH 4 #define BIT_MASK_AC1_FAST_EDCA_PKT_TH 0xf #define BIT_AC1_FAST_EDCA_PKT_TH(x) \ (((x) & BIT_MASK_AC1_FAST_EDCA_PKT_TH) \ << BIT_SHIFT_AC1_FAST_EDCA_PKT_TH) #define BITS_AC1_FAST_EDCA_PKT_TH \ (BIT_MASK_AC1_FAST_EDCA_PKT_TH << BIT_SHIFT_AC1_FAST_EDCA_PKT_TH) #define BIT_CLEAR_AC1_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_AC1_FAST_EDCA_PKT_TH)) #define BIT_GET_AC1_FAST_EDCA_PKT_TH(x) \ (((x) >> BIT_SHIFT_AC1_FAST_EDCA_PKT_TH) & \ BIT_MASK_AC1_FAST_EDCA_PKT_TH) #define BIT_SET_AC1_FAST_EDCA_PKT_TH(x, v) \ (BIT_CLEAR_AC1_FAST_EDCA_PKT_TH(x) | BIT_AC1_FAST_EDCA_PKT_TH(v)) #define BIT_SHIFT_AC0_FAST_EDCA_PKT_TH 0 #define BIT_MASK_AC0_FAST_EDCA_PKT_TH 0xf #define BIT_AC0_FAST_EDCA_PKT_TH(x) \ (((x) & BIT_MASK_AC0_FAST_EDCA_PKT_TH) \ << BIT_SHIFT_AC0_FAST_EDCA_PKT_TH) #define BITS_AC0_FAST_EDCA_PKT_TH \ (BIT_MASK_AC0_FAST_EDCA_PKT_TH << BIT_SHIFT_AC0_FAST_EDCA_PKT_TH) #define BIT_CLEAR_AC0_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_AC0_FAST_EDCA_PKT_TH)) #define BIT_GET_AC0_FAST_EDCA_PKT_TH(x) \ (((x) >> BIT_SHIFT_AC0_FAST_EDCA_PKT_TH) & \ BIT_MASK_AC0_FAST_EDCA_PKT_TH) #define BIT_SET_AC0_FAST_EDCA_PKT_TH(x, v) \ (BIT_CLEAR_AC0_FAST_EDCA_PKT_TH(x) | BIT_AC0_FAST_EDCA_PKT_TH(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_AMPDU_MAX_LENGTH_VHT (Offset 0x0460) */ #define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT 0 #define BIT_MASK_AMPDU_MAX_LENGTH_VHT 0x3ffff #define BIT_AMPDU_MAX_LENGTH_VHT(x) \ (((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT) \ << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT) #define BITS_AMPDU_MAX_LENGTH_VHT \ (BIT_MASK_AMPDU_MAX_LENGTH_VHT << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT) #define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT(x) ((x) & (~BITS_AMPDU_MAX_LENGTH_VHT)) #define BIT_GET_AMPDU_MAX_LENGTH_VHT(x) \ (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT) & \ BIT_MASK_AMPDU_MAX_LENGTH_VHT) #define BIT_SET_AMPDU_MAX_LENGTH_VHT(x, v) \ (BIT_CLEAR_AMPDU_MAX_LENGTH_VHT(x) | BIT_AMPDU_MAX_LENGTH_VHT(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_AMPDU_MAX_LENGTH_VHT (Offset 0x0460) */ #define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1 0 #define BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1 0xfffff #define BIT_AMPDU_MAX_LENGTH_VHT_V1(x) \ (((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1) \ << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1) #define BITS_AMPDU_MAX_LENGTH_VHT_V1 \ (BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1 << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1) #define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1(x) \ ((x) & (~BITS_AMPDU_MAX_LENGTH_VHT_V1)) #define BIT_GET_AMPDU_MAX_LENGTH_VHT_V1(x) \ (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1) & \ BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1) #define BIT_SET_AMPDU_MAX_LENGTH_VHT_V1(x, v) \ (BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1(x) | BIT_AMPDU_MAX_LENGTH_VHT_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RD_RESP_PKT_TH (Offset 0x0463) */ #define BIT_SHIFT_RD_RESP_PKT_TH 0 #define BIT_MASK_RD_RESP_PKT_TH 0x1f #define BIT_RD_RESP_PKT_TH(x) \ (((x) & BIT_MASK_RD_RESP_PKT_TH) << BIT_SHIFT_RD_RESP_PKT_TH) #define BITS_RD_RESP_PKT_TH \ (BIT_MASK_RD_RESP_PKT_TH << BIT_SHIFT_RD_RESP_PKT_TH) #define BIT_CLEAR_RD_RESP_PKT_TH(x) ((x) & (~BITS_RD_RESP_PKT_TH)) #define BIT_GET_RD_RESP_PKT_TH(x) \ (((x) >> BIT_SHIFT_RD_RESP_PKT_TH) & BIT_MASK_RD_RESP_PKT_TH) #define BIT_SET_RD_RESP_PKT_TH(x, v) \ (BIT_CLEAR_RD_RESP_PKT_TH(x) | BIT_RD_RESP_PKT_TH(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RD_RESP_PKT_TH (Offset 0x0463) */ #define BIT_SHIFT_RD_RESP_PKT_TH_V1 0 #define BIT_MASK_RD_RESP_PKT_TH_V1 0x3f #define BIT_RD_RESP_PKT_TH_V1(x) \ (((x) & BIT_MASK_RD_RESP_PKT_TH_V1) << BIT_SHIFT_RD_RESP_PKT_TH_V1) #define BITS_RD_RESP_PKT_TH_V1 \ (BIT_MASK_RD_RESP_PKT_TH_V1 << BIT_SHIFT_RD_RESP_PKT_TH_V1) #define BIT_CLEAR_RD_RESP_PKT_TH_V1(x) ((x) & (~BITS_RD_RESP_PKT_TH_V1)) #define BIT_GET_RD_RESP_PKT_TH_V1(x) \ (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1) & BIT_MASK_RD_RESP_PKT_TH_V1) #define BIT_SET_RD_RESP_PKT_TH_V1(x, v) \ (BIT_CLEAR_RD_RESP_PKT_TH_V1(x) | BIT_RD_RESP_PKT_TH_V1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CMDQ_INFO (Offset 0x0464) */ #define BIT_SHIFT_QUEUEMACID_CMDQ_V1 25 #define BIT_MASK_QUEUEMACID_CMDQ_V1 0x7f #define BIT_QUEUEMACID_CMDQ_V1(x) \ (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1) << BIT_SHIFT_QUEUEMACID_CMDQ_V1) #define BITS_QUEUEMACID_CMDQ_V1 \ (BIT_MASK_QUEUEMACID_CMDQ_V1 << BIT_SHIFT_QUEUEMACID_CMDQ_V1) #define BIT_CLEAR_QUEUEMACID_CMDQ_V1(x) ((x) & (~BITS_QUEUEMACID_CMDQ_V1)) #define BIT_GET_QUEUEMACID_CMDQ_V1(x) \ (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1) & BIT_MASK_QUEUEMACID_CMDQ_V1) #define BIT_SET_QUEUEMACID_CMDQ_V1(x, v) \ (BIT_CLEAR_QUEUEMACID_CMDQ_V1(x) | BIT_QUEUEMACID_CMDQ_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CMDQ_INFO (Offset 0x0464) */ #define BIT_SHIFT_PKT_NUM_CMDQ_V2 24 #define BIT_MASK_PKT_NUM_CMDQ_V2 0xff #define BIT_PKT_NUM_CMDQ_V2(x) \ (((x) & BIT_MASK_PKT_NUM_CMDQ_V2) << BIT_SHIFT_PKT_NUM_CMDQ_V2) #define BITS_PKT_NUM_CMDQ_V2 \ (BIT_MASK_PKT_NUM_CMDQ_V2 << BIT_SHIFT_PKT_NUM_CMDQ_V2) #define BIT_CLEAR_PKT_NUM_CMDQ_V2(x) ((x) & (~BITS_PKT_NUM_CMDQ_V2)) #define BIT_GET_PKT_NUM_CMDQ_V2(x) \ (((x) >> BIT_SHIFT_PKT_NUM_CMDQ_V2) & BIT_MASK_PKT_NUM_CMDQ_V2) #define BIT_SET_PKT_NUM_CMDQ_V2(x, v) \ (BIT_CLEAR_PKT_NUM_CMDQ_V2(x) | BIT_PKT_NUM_CMDQ_V2(v)) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_CMDQ_INFO (Offset 0x0464) */ #define BIT_SHIFT_PKT_NUM 23 #define BIT_MASK_PKT_NUM 0x1ff #define BIT_PKT_NUM(x) (((x) & BIT_MASK_PKT_NUM) << BIT_SHIFT_PKT_NUM) #define BITS_PKT_NUM (BIT_MASK_PKT_NUM << BIT_SHIFT_PKT_NUM) #define BIT_CLEAR_PKT_NUM(x) ((x) & (~BITS_PKT_NUM)) #define BIT_GET_PKT_NUM(x) (((x) >> BIT_SHIFT_PKT_NUM) & BIT_MASK_PKT_NUM) #define BIT_SET_PKT_NUM(x, v) (BIT_CLEAR_PKT_NUM(x) | BIT_PKT_NUM(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CMDQ_INFO (Offset 0x0464) */ #define BIT_SHIFT_QUEUEAC_CMDQ_V1 23 #define BIT_MASK_QUEUEAC_CMDQ_V1 0x3 #define BIT_QUEUEAC_CMDQ_V1(x) \ (((x) & BIT_MASK_QUEUEAC_CMDQ_V1) << BIT_SHIFT_QUEUEAC_CMDQ_V1) #define BITS_QUEUEAC_CMDQ_V1 \ (BIT_MASK_QUEUEAC_CMDQ_V1 << BIT_SHIFT_QUEUEAC_CMDQ_V1) #define BIT_CLEAR_QUEUEAC_CMDQ_V1(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1)) #define BIT_GET_QUEUEAC_CMDQ_V1(x) \ (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1) & BIT_MASK_QUEUEAC_CMDQ_V1) #define BIT_SET_QUEUEAC_CMDQ_V1(x, v) \ (BIT_CLEAR_QUEUEAC_CMDQ_V1(x) | BIT_QUEUEAC_CMDQ_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CMDQ_INFO (Offset 0x0464) */ #define BIT_TIDEMPTY_CMDQ_V1 BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CMDQ_INFO (Offset 0x0464) */ #define BIT_SHIFT_TAIL_PKT_CMDQ 16 #define BIT_MASK_TAIL_PKT_CMDQ 0xff #define BIT_TAIL_PKT_CMDQ(x) \ (((x) & BIT_MASK_TAIL_PKT_CMDQ) << BIT_SHIFT_TAIL_PKT_CMDQ) #define BITS_TAIL_PKT_CMDQ (BIT_MASK_TAIL_PKT_CMDQ << BIT_SHIFT_TAIL_PKT_CMDQ) #define BIT_CLEAR_TAIL_PKT_CMDQ(x) ((x) & (~BITS_TAIL_PKT_CMDQ)) #define BIT_GET_TAIL_PKT_CMDQ(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ) & BIT_MASK_TAIL_PKT_CMDQ) #define BIT_SET_TAIL_PKT_CMDQ(x, v) \ (BIT_CLEAR_TAIL_PKT_CMDQ(x) | BIT_TAIL_PKT_CMDQ(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_CMDQ_INFO (Offset 0x0464) */ #define BIT_SHIFT_TAIL_PKT_CMDQ_V2 11 #define BIT_MASK_TAIL_PKT_CMDQ_V2 0x7ff #define BIT_TAIL_PKT_CMDQ_V2(x) \ (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2) << BIT_SHIFT_TAIL_PKT_CMDQ_V2) #define BITS_TAIL_PKT_CMDQ_V2 \ (BIT_MASK_TAIL_PKT_CMDQ_V2 << BIT_SHIFT_TAIL_PKT_CMDQ_V2) #define BIT_CLEAR_TAIL_PKT_CMDQ_V2(x) ((x) & (~BITS_TAIL_PKT_CMDQ_V2)) #define BIT_GET_TAIL_PKT_CMDQ_V2(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2) & BIT_MASK_TAIL_PKT_CMDQ_V2) #define BIT_SET_TAIL_PKT_CMDQ_V2(x, v) \ (BIT_CLEAR_TAIL_PKT_CMDQ_V2(x) | BIT_TAIL_PKT_CMDQ_V2(v)) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_NEW_EDCA_CTRL_V1 (Offset 0x0464) */ #define BIT_SHIFT_RANDOM_VALUE_SHIFT 9 #define BIT_MASK_RANDOM_VALUE_SHIFT 0x7 #define BIT_RANDOM_VALUE_SHIFT(x) \ (((x) & BIT_MASK_RANDOM_VALUE_SHIFT) << BIT_SHIFT_RANDOM_VALUE_SHIFT) #define BITS_RANDOM_VALUE_SHIFT \ (BIT_MASK_RANDOM_VALUE_SHIFT << BIT_SHIFT_RANDOM_VALUE_SHIFT) #define BIT_CLEAR_RANDOM_VALUE_SHIFT(x) ((x) & (~BITS_RANDOM_VALUE_SHIFT)) #define BIT_GET_RANDOM_VALUE_SHIFT(x) \ (((x) >> BIT_SHIFT_RANDOM_VALUE_SHIFT) & BIT_MASK_RANDOM_VALUE_SHIFT) #define BIT_SET_RANDOM_VALUE_SHIFT(x, v) \ (BIT_CLEAR_RANDOM_VALUE_SHIFT(x) | BIT_RANDOM_VALUE_SHIFT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CMDQ_INFO (Offset 0x0464) */ #define BIT_SHIFT_PKT_NUM_CMDQ 8 #define BIT_MASK_PKT_NUM_CMDQ 0xff #define BIT_PKT_NUM_CMDQ(x) \ (((x) & BIT_MASK_PKT_NUM_CMDQ) << BIT_SHIFT_PKT_NUM_CMDQ) #define BITS_PKT_NUM_CMDQ (BIT_MASK_PKT_NUM_CMDQ << BIT_SHIFT_PKT_NUM_CMDQ) #define BIT_CLEAR_PKT_NUM_CMDQ(x) ((x) & (~BITS_PKT_NUM_CMDQ)) #define BIT_GET_PKT_NUM_CMDQ(x) \ (((x) >> BIT_SHIFT_PKT_NUM_CMDQ) & BIT_MASK_PKT_NUM_CMDQ) #define BIT_SET_PKT_NUM_CMDQ(x, v) \ (BIT_CLEAR_PKT_NUM_CMDQ(x) | BIT_PKT_NUM_CMDQ(v)) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_NEW_EDCA_CTRL_V1 (Offset 0x0464) */ #define BIT_ENABLE_NEW_EDCA BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CMDQ_INFO (Offset 0x0464) */ #define BIT_SHIFT_HEAD_PKT_CMDQ 0 #define BIT_MASK_HEAD_PKT_CMDQ 0xff #define BIT_HEAD_PKT_CMDQ(x) \ (((x) & BIT_MASK_HEAD_PKT_CMDQ) << BIT_SHIFT_HEAD_PKT_CMDQ) #define BITS_HEAD_PKT_CMDQ (BIT_MASK_HEAD_PKT_CMDQ << BIT_SHIFT_HEAD_PKT_CMDQ) #define BIT_CLEAR_HEAD_PKT_CMDQ(x) ((x) & (~BITS_HEAD_PKT_CMDQ)) #define BIT_GET_HEAD_PKT_CMDQ(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ) & BIT_MASK_HEAD_PKT_CMDQ) #define BIT_SET_HEAD_PKT_CMDQ(x, v) \ (BIT_CLEAR_HEAD_PKT_CMDQ(x) | BIT_HEAD_PKT_CMDQ(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CMDQ_INFO (Offset 0x0464) */ #define BIT_SHIFT_HEAD_PKT_CMDQ_V1 0 #define BIT_MASK_HEAD_PKT_CMDQ_V1 0x7ff #define BIT_HEAD_PKT_CMDQ_V1(x) \ (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1) << BIT_SHIFT_HEAD_PKT_CMDQ_V1) #define BITS_HEAD_PKT_CMDQ_V1 \ (BIT_MASK_HEAD_PKT_CMDQ_V1 << BIT_SHIFT_HEAD_PKT_CMDQ_V1) #define BIT_CLEAR_HEAD_PKT_CMDQ_V1(x) ((x) & (~BITS_HEAD_PKT_CMDQ_V1)) #define BIT_GET_HEAD_PKT_CMDQ_V1(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1) & BIT_MASK_HEAD_PKT_CMDQ_V1) #define BIT_SET_HEAD_PKT_CMDQ_V1(x, v) \ (BIT_CLEAR_HEAD_PKT_CMDQ_V1(x) | BIT_HEAD_PKT_CMDQ_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_NEW_EDCA_CTRL_V1 (Offset 0x0464) */ #define BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER 0 #define BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER 0xff #define BIT_MEDIUM_HAS_IDKE_TRIGGER(x) \ (((x) & BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER) \ << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER) #define BITS_MEDIUM_HAS_IDKE_TRIGGER \ (BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER) #define BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER(x) \ ((x) & (~BITS_MEDIUM_HAS_IDKE_TRIGGER)) #define BIT_GET_MEDIUM_HAS_IDKE_TRIGGER(x) \ (((x) >> BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER) & \ BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER) #define BIT_SET_MEDIUM_HAS_IDKE_TRIGGER(x, v) \ (BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER(x) | BIT_MEDIUM_HAS_IDKE_TRIGGER(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q4_INFO (Offset 0x0468) */ #define BIT_SHIFT_QUEUEMACID_Q4_V1 25 #define BIT_MASK_QUEUEMACID_Q4_V1 0x7f #define BIT_QUEUEMACID_Q4_V1(x) \ (((x) & BIT_MASK_QUEUEMACID_Q4_V1) << BIT_SHIFT_QUEUEMACID_Q4_V1) #define BITS_QUEUEMACID_Q4_V1 \ (BIT_MASK_QUEUEMACID_Q4_V1 << BIT_SHIFT_QUEUEMACID_Q4_V1) #define BIT_CLEAR_QUEUEMACID_Q4_V1(x) ((x) & (~BITS_QUEUEMACID_Q4_V1)) #define BIT_GET_QUEUEMACID_Q4_V1(x) \ (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1) & BIT_MASK_QUEUEMACID_Q4_V1) #define BIT_SET_QUEUEMACID_Q4_V1(x, v) \ (BIT_CLEAR_QUEUEMACID_Q4_V1(x) | BIT_QUEUEMACID_Q4_V1(v)) #define BIT_SHIFT_QUEUEAC_Q4_V1 23 #define BIT_MASK_QUEUEAC_Q4_V1 0x3 #define BIT_QUEUEAC_Q4_V1(x) \ (((x) & BIT_MASK_QUEUEAC_Q4_V1) << BIT_SHIFT_QUEUEAC_Q4_V1) #define BITS_QUEUEAC_Q4_V1 (BIT_MASK_QUEUEAC_Q4_V1 << BIT_SHIFT_QUEUEAC_Q4_V1) #define BIT_CLEAR_QUEUEAC_Q4_V1(x) ((x) & (~BITS_QUEUEAC_Q4_V1)) #define BIT_GET_QUEUEAC_Q4_V1(x) \ (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1) & BIT_MASK_QUEUEAC_Q4_V1) #define BIT_SET_QUEUEAC_Q4_V1(x, v) \ (BIT_CLEAR_QUEUEAC_Q4_V1(x) | BIT_QUEUEAC_Q4_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q4_INFO (Offset 0x0468) */ #define BIT_TIDEMPTY_Q4_V1 BIT(22) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACQ_STOP_V2 (Offset 0x0468) */ #define BIT_AC19Q_STOP BIT(19) #define BIT_AC18Q_STOP BIT(18) #define BIT_AC17Q_STOP BIT(17) #define BIT_AC16Q_STOP BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q4_INFO (Offset 0x0468) */ #define BIT_SHIFT_TAIL_PKT_Q4_V1 15 #define BIT_MASK_TAIL_PKT_Q4_V1 0xff #define BIT_TAIL_PKT_Q4_V1(x) \ (((x) & BIT_MASK_TAIL_PKT_Q4_V1) << BIT_SHIFT_TAIL_PKT_Q4_V1) #define BITS_TAIL_PKT_Q4_V1 \ (BIT_MASK_TAIL_PKT_Q4_V1 << BIT_SHIFT_TAIL_PKT_Q4_V1) #define BIT_CLEAR_TAIL_PKT_Q4_V1(x) ((x) & (~BITS_TAIL_PKT_Q4_V1)) #define BIT_GET_TAIL_PKT_Q4_V1(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V1) & BIT_MASK_TAIL_PKT_Q4_V1) #define BIT_SET_TAIL_PKT_Q4_V1(x, v) \ (BIT_CLEAR_TAIL_PKT_Q4_V1(x) | BIT_TAIL_PKT_Q4_V1(v)) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_ACQ_STOP_V2 (Offset 0x0468) */ #define BIT_AC15Q_STOP BIT(15) #define BIT_AC14Q_STOP BIT(14) #define BIT_AC13Q_STOP BIT(13) #define BIT_AC12Q_STOP BIT(12) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q4_INFO (Offset 0x0468) */ #define BIT_SHIFT_TAIL_PKT_Q4_V2 11 #define BIT_MASK_TAIL_PKT_Q4_V2 0x7ff #define BIT_TAIL_PKT_Q4_V2(x) \ (((x) & BIT_MASK_TAIL_PKT_Q4_V2) << BIT_SHIFT_TAIL_PKT_Q4_V2) #define BITS_TAIL_PKT_Q4_V2 \ (BIT_MASK_TAIL_PKT_Q4_V2 << BIT_SHIFT_TAIL_PKT_Q4_V2) #define BIT_CLEAR_TAIL_PKT_Q4_V2(x) ((x) & (~BITS_TAIL_PKT_Q4_V2)) #define BIT_GET_TAIL_PKT_Q4_V2(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2) & BIT_MASK_TAIL_PKT_Q4_V2) #define BIT_SET_TAIL_PKT_Q4_V2(x, v) \ (BIT_CLEAR_TAIL_PKT_Q4_V2(x) | BIT_TAIL_PKT_Q4_V2(v)) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_ACQ_STOP_V2 (Offset 0x0468) */ #define BIT_AC11Q_STOP BIT(11) #define BIT_AC10Q_STOP BIT(10) #define BIT_AC9Q_STOP BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q4_INFO (Offset 0x0468) */ #define BIT_SHIFT_PKT_NUM_Q4_V1 8 #define BIT_MASK_PKT_NUM_Q4_V1 0x7f #define BIT_PKT_NUM_Q4_V1(x) \ (((x) & BIT_MASK_PKT_NUM_Q4_V1) << BIT_SHIFT_PKT_NUM_Q4_V1) #define BITS_PKT_NUM_Q4_V1 (BIT_MASK_PKT_NUM_Q4_V1 << BIT_SHIFT_PKT_NUM_Q4_V1) #define BIT_CLEAR_PKT_NUM_Q4_V1(x) ((x) & (~BITS_PKT_NUM_Q4_V1)) #define BIT_GET_PKT_NUM_Q4_V1(x) \ (((x) >> BIT_SHIFT_PKT_NUM_Q4_V1) & BIT_MASK_PKT_NUM_Q4_V1) #define BIT_SET_PKT_NUM_Q4_V1(x, v) \ (BIT_CLEAR_PKT_NUM_Q4_V1(x) | BIT_PKT_NUM_Q4_V1(v)) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_ACQ_STOP_V2 (Offset 0x0468) */ #define BIT_AC8Q_STOP BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q4_INFO (Offset 0x0468) */ #define BIT_SHIFT_HEAD_PKT_Q4 0 #define BIT_MASK_HEAD_PKT_Q4 0xff #define BIT_HEAD_PKT_Q4(x) \ (((x) & BIT_MASK_HEAD_PKT_Q4) << BIT_SHIFT_HEAD_PKT_Q4) #define BITS_HEAD_PKT_Q4 (BIT_MASK_HEAD_PKT_Q4 << BIT_SHIFT_HEAD_PKT_Q4) #define BIT_CLEAR_HEAD_PKT_Q4(x) ((x) & (~BITS_HEAD_PKT_Q4)) #define BIT_GET_HEAD_PKT_Q4(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_Q4) & BIT_MASK_HEAD_PKT_Q4) #define BIT_SET_HEAD_PKT_Q4(x, v) \ (BIT_CLEAR_HEAD_PKT_Q4(x) | BIT_HEAD_PKT_Q4(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q4_INFO (Offset 0x0468) */ #define BIT_SHIFT_HEAD_PKT_Q4_V1 0 #define BIT_MASK_HEAD_PKT_Q4_V1 0x7ff #define BIT_HEAD_PKT_Q4_V1(x) \ (((x) & BIT_MASK_HEAD_PKT_Q4_V1) << BIT_SHIFT_HEAD_PKT_Q4_V1) #define BITS_HEAD_PKT_Q4_V1 \ (BIT_MASK_HEAD_PKT_Q4_V1 << BIT_SHIFT_HEAD_PKT_Q4_V1) #define BIT_CLEAR_HEAD_PKT_Q4_V1(x) ((x) & (~BITS_HEAD_PKT_Q4_V1)) #define BIT_GET_HEAD_PKT_Q4_V1(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1) & BIT_MASK_HEAD_PKT_Q4_V1) #define BIT_SET_HEAD_PKT_Q4_V1(x, v) \ (BIT_CLEAR_HEAD_PKT_Q4_V1(x) | BIT_HEAD_PKT_Q4_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q5_INFO (Offset 0x046C) */ #define BIT_SHIFT_QUEUEMACID_Q5_V1 25 #define BIT_MASK_QUEUEMACID_Q5_V1 0x7f #define BIT_QUEUEMACID_Q5_V1(x) \ (((x) & BIT_MASK_QUEUEMACID_Q5_V1) << BIT_SHIFT_QUEUEMACID_Q5_V1) #define BITS_QUEUEMACID_Q5_V1 \ (BIT_MASK_QUEUEMACID_Q5_V1 << BIT_SHIFT_QUEUEMACID_Q5_V1) #define BIT_CLEAR_QUEUEMACID_Q5_V1(x) ((x) & (~BITS_QUEUEMACID_Q5_V1)) #define BIT_GET_QUEUEMACID_Q5_V1(x) \ (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1) & BIT_MASK_QUEUEMACID_Q5_V1) #define BIT_SET_QUEUEMACID_Q5_V1(x, v) \ (BIT_CLEAR_QUEUEMACID_Q5_V1(x) | BIT_QUEUEMACID_Q5_V1(v)) #define BIT_SHIFT_QUEUEAC_Q5_V1 23 #define BIT_MASK_QUEUEAC_Q5_V1 0x3 #define BIT_QUEUEAC_Q5_V1(x) \ (((x) & BIT_MASK_QUEUEAC_Q5_V1) << BIT_SHIFT_QUEUEAC_Q5_V1) #define BITS_QUEUEAC_Q5_V1 (BIT_MASK_QUEUEAC_Q5_V1 << BIT_SHIFT_QUEUEAC_Q5_V1) #define BIT_CLEAR_QUEUEAC_Q5_V1(x) ((x) & (~BITS_QUEUEAC_Q5_V1)) #define BIT_GET_QUEUEAC_Q5_V1(x) \ (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1) & BIT_MASK_QUEUEAC_Q5_V1) #define BIT_SET_QUEUEAC_Q5_V1(x, v) \ (BIT_CLEAR_QUEUEAC_Q5_V1(x) | BIT_QUEUEAC_Q5_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q5_INFO (Offset 0x046C) */ #define BIT_TIDEMPTY_Q5_V1 BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q5_INFO (Offset 0x046C) */ #define BIT_SHIFT_TAIL_PKT_Q5_V1 15 #define BIT_MASK_TAIL_PKT_Q5_V1 0xff #define BIT_TAIL_PKT_Q5_V1(x) \ (((x) & BIT_MASK_TAIL_PKT_Q5_V1) << BIT_SHIFT_TAIL_PKT_Q5_V1) #define BITS_TAIL_PKT_Q5_V1 \ (BIT_MASK_TAIL_PKT_Q5_V1 << BIT_SHIFT_TAIL_PKT_Q5_V1) #define BIT_CLEAR_TAIL_PKT_Q5_V1(x) ((x) & (~BITS_TAIL_PKT_Q5_V1)) #define BIT_GET_TAIL_PKT_Q5_V1(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V1) & BIT_MASK_TAIL_PKT_Q5_V1) #define BIT_SET_TAIL_PKT_Q5_V1(x, v) \ (BIT_CLEAR_TAIL_PKT_Q5_V1(x) | BIT_TAIL_PKT_Q5_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q5_INFO (Offset 0x046C) */ #define BIT_SHIFT_TAIL_PKT_Q5_V2 11 #define BIT_MASK_TAIL_PKT_Q5_V2 0x7ff #define BIT_TAIL_PKT_Q5_V2(x) \ (((x) & BIT_MASK_TAIL_PKT_Q5_V2) << BIT_SHIFT_TAIL_PKT_Q5_V2) #define BITS_TAIL_PKT_Q5_V2 \ (BIT_MASK_TAIL_PKT_Q5_V2 << BIT_SHIFT_TAIL_PKT_Q5_V2) #define BIT_CLEAR_TAIL_PKT_Q5_V2(x) ((x) & (~BITS_TAIL_PKT_Q5_V2)) #define BIT_GET_TAIL_PKT_Q5_V2(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2) & BIT_MASK_TAIL_PKT_Q5_V2) #define BIT_SET_TAIL_PKT_Q5_V2(x, v) \ (BIT_CLEAR_TAIL_PKT_Q5_V2(x) | BIT_TAIL_PKT_Q5_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q5_INFO (Offset 0x046C) */ #define BIT_SHIFT_PKT_NUM_Q5_V1 8 #define BIT_MASK_PKT_NUM_Q5_V1 0x7f #define BIT_PKT_NUM_Q5_V1(x) \ (((x) & BIT_MASK_PKT_NUM_Q5_V1) << BIT_SHIFT_PKT_NUM_Q5_V1) #define BITS_PKT_NUM_Q5_V1 (BIT_MASK_PKT_NUM_Q5_V1 << BIT_SHIFT_PKT_NUM_Q5_V1) #define BIT_CLEAR_PKT_NUM_Q5_V1(x) ((x) & (~BITS_PKT_NUM_Q5_V1)) #define BIT_GET_PKT_NUM_Q5_V1(x) \ (((x) >> BIT_SHIFT_PKT_NUM_Q5_V1) & BIT_MASK_PKT_NUM_Q5_V1) #define BIT_SET_PKT_NUM_Q5_V1(x, v) \ (BIT_CLEAR_PKT_NUM_Q5_V1(x) | BIT_PKT_NUM_Q5_V1(v)) #define BIT_SHIFT_HEAD_PKT_Q5 0 #define BIT_MASK_HEAD_PKT_Q5 0xff #define BIT_HEAD_PKT_Q5(x) \ (((x) & BIT_MASK_HEAD_PKT_Q5) << BIT_SHIFT_HEAD_PKT_Q5) #define BITS_HEAD_PKT_Q5 (BIT_MASK_HEAD_PKT_Q5 << BIT_SHIFT_HEAD_PKT_Q5) #define BIT_CLEAR_HEAD_PKT_Q5(x) ((x) & (~BITS_HEAD_PKT_Q5)) #define BIT_GET_HEAD_PKT_Q5(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_Q5) & BIT_MASK_HEAD_PKT_Q5) #define BIT_SET_HEAD_PKT_Q5(x, v) \ (BIT_CLEAR_HEAD_PKT_Q5(x) | BIT_HEAD_PKT_Q5(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q5_INFO (Offset 0x046C) */ #define BIT_SHIFT_HEAD_PKT_Q5_V1 0 #define BIT_MASK_HEAD_PKT_Q5_V1 0x7ff #define BIT_HEAD_PKT_Q5_V1(x) \ (((x) & BIT_MASK_HEAD_PKT_Q5_V1) << BIT_SHIFT_HEAD_PKT_Q5_V1) #define BITS_HEAD_PKT_Q5_V1 \ (BIT_MASK_HEAD_PKT_Q5_V1 << BIT_SHIFT_HEAD_PKT_Q5_V1) #define BIT_CLEAR_HEAD_PKT_Q5_V1(x) ((x) & (~BITS_HEAD_PKT_Q5_V1)) #define BIT_GET_HEAD_PKT_Q5_V1(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1) & BIT_MASK_HEAD_PKT_Q5_V1) #define BIT_SET_HEAD_PKT_Q5_V1(x, v) \ (BIT_CLEAR_HEAD_PKT_Q5_V1(x) | BIT_HEAD_PKT_Q5_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q6_INFO (Offset 0x0470) */ #define BIT_SHIFT_QUEUEMACID_Q6_V1 25 #define BIT_MASK_QUEUEMACID_Q6_V1 0x7f #define BIT_QUEUEMACID_Q6_V1(x) \ (((x) & BIT_MASK_QUEUEMACID_Q6_V1) << BIT_SHIFT_QUEUEMACID_Q6_V1) #define BITS_QUEUEMACID_Q6_V1 \ (BIT_MASK_QUEUEMACID_Q6_V1 << BIT_SHIFT_QUEUEMACID_Q6_V1) #define BIT_CLEAR_QUEUEMACID_Q6_V1(x) ((x) & (~BITS_QUEUEMACID_Q6_V1)) #define BIT_GET_QUEUEMACID_Q6_V1(x) \ (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1) & BIT_MASK_QUEUEMACID_Q6_V1) #define BIT_SET_QUEUEMACID_Q6_V1(x, v) \ (BIT_CLEAR_QUEUEMACID_Q6_V1(x) | BIT_QUEUEMACID_Q6_V1(v)) #define BIT_SHIFT_QUEUEAC_Q6_V1 23 #define BIT_MASK_QUEUEAC_Q6_V1 0x3 #define BIT_QUEUEAC_Q6_V1(x) \ (((x) & BIT_MASK_QUEUEAC_Q6_V1) << BIT_SHIFT_QUEUEAC_Q6_V1) #define BITS_QUEUEAC_Q6_V1 (BIT_MASK_QUEUEAC_Q6_V1 << BIT_SHIFT_QUEUEAC_Q6_V1) #define BIT_CLEAR_QUEUEAC_Q6_V1(x) ((x) & (~BITS_QUEUEAC_Q6_V1)) #define BIT_GET_QUEUEAC_Q6_V1(x) \ (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1) & BIT_MASK_QUEUEAC_Q6_V1) #define BIT_SET_QUEUEAC_Q6_V1(x, v) \ (BIT_CLEAR_QUEUEAC_Q6_V1(x) | BIT_QUEUEAC_Q6_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q6_INFO (Offset 0x0470) */ #define BIT_TIDEMPTY_Q6_V1 BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q6_INFO (Offset 0x0470) */ #define BIT_SHIFT_TAIL_PKT_Q6_V1 15 #define BIT_MASK_TAIL_PKT_Q6_V1 0xff #define BIT_TAIL_PKT_Q6_V1(x) \ (((x) & BIT_MASK_TAIL_PKT_Q6_V1) << BIT_SHIFT_TAIL_PKT_Q6_V1) #define BITS_TAIL_PKT_Q6_V1 \ (BIT_MASK_TAIL_PKT_Q6_V1 << BIT_SHIFT_TAIL_PKT_Q6_V1) #define BIT_CLEAR_TAIL_PKT_Q6_V1(x) ((x) & (~BITS_TAIL_PKT_Q6_V1)) #define BIT_GET_TAIL_PKT_Q6_V1(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V1) & BIT_MASK_TAIL_PKT_Q6_V1) #define BIT_SET_TAIL_PKT_Q6_V1(x, v) \ (BIT_CLEAR_TAIL_PKT_Q6_V1(x) | BIT_TAIL_PKT_Q6_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q6_INFO (Offset 0x0470) */ #define BIT_SHIFT_TAIL_PKT_Q6_V2 11 #define BIT_MASK_TAIL_PKT_Q6_V2 0x7ff #define BIT_TAIL_PKT_Q6_V2(x) \ (((x) & BIT_MASK_TAIL_PKT_Q6_V2) << BIT_SHIFT_TAIL_PKT_Q6_V2) #define BITS_TAIL_PKT_Q6_V2 \ (BIT_MASK_TAIL_PKT_Q6_V2 << BIT_SHIFT_TAIL_PKT_Q6_V2) #define BIT_CLEAR_TAIL_PKT_Q6_V2(x) ((x) & (~BITS_TAIL_PKT_Q6_V2)) #define BIT_GET_TAIL_PKT_Q6_V2(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2) & BIT_MASK_TAIL_PKT_Q6_V2) #define BIT_SET_TAIL_PKT_Q6_V2(x, v) \ (BIT_CLEAR_TAIL_PKT_Q6_V2(x) | BIT_TAIL_PKT_Q6_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q6_INFO (Offset 0x0470) */ #define BIT_SHIFT_PKT_NUM_Q6_V1 8 #define BIT_MASK_PKT_NUM_Q6_V1 0x7f #define BIT_PKT_NUM_Q6_V1(x) \ (((x) & BIT_MASK_PKT_NUM_Q6_V1) << BIT_SHIFT_PKT_NUM_Q6_V1) #define BITS_PKT_NUM_Q6_V1 (BIT_MASK_PKT_NUM_Q6_V1 << BIT_SHIFT_PKT_NUM_Q6_V1) #define BIT_CLEAR_PKT_NUM_Q6_V1(x) ((x) & (~BITS_PKT_NUM_Q6_V1)) #define BIT_GET_PKT_NUM_Q6_V1(x) \ (((x) >> BIT_SHIFT_PKT_NUM_Q6_V1) & BIT_MASK_PKT_NUM_Q6_V1) #define BIT_SET_PKT_NUM_Q6_V1(x, v) \ (BIT_CLEAR_PKT_NUM_Q6_V1(x) | BIT_PKT_NUM_Q6_V1(v)) #define BIT_SHIFT_HEAD_PKT_Q6 0 #define BIT_MASK_HEAD_PKT_Q6 0xff #define BIT_HEAD_PKT_Q6(x) \ (((x) & BIT_MASK_HEAD_PKT_Q6) << BIT_SHIFT_HEAD_PKT_Q6) #define BITS_HEAD_PKT_Q6 (BIT_MASK_HEAD_PKT_Q6 << BIT_SHIFT_HEAD_PKT_Q6) #define BIT_CLEAR_HEAD_PKT_Q6(x) ((x) & (~BITS_HEAD_PKT_Q6)) #define BIT_GET_HEAD_PKT_Q6(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_Q6) & BIT_MASK_HEAD_PKT_Q6) #define BIT_SET_HEAD_PKT_Q6(x, v) \ (BIT_CLEAR_HEAD_PKT_Q6(x) | BIT_HEAD_PKT_Q6(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q6_INFO (Offset 0x0470) */ #define BIT_SHIFT_HEAD_PKT_Q6_V1 0 #define BIT_MASK_HEAD_PKT_Q6_V1 0x7ff #define BIT_HEAD_PKT_Q6_V1(x) \ (((x) & BIT_MASK_HEAD_PKT_Q6_V1) << BIT_SHIFT_HEAD_PKT_Q6_V1) #define BITS_HEAD_PKT_Q6_V1 \ (BIT_MASK_HEAD_PKT_Q6_V1 << BIT_SHIFT_HEAD_PKT_Q6_V1) #define BIT_CLEAR_HEAD_PKT_Q6_V1(x) ((x) & (~BITS_HEAD_PKT_Q6_V1)) #define BIT_GET_HEAD_PKT_Q6_V1(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1) & BIT_MASK_HEAD_PKT_Q6_V1) #define BIT_SET_HEAD_PKT_Q6_V1(x, v) \ (BIT_CLEAR_HEAD_PKT_Q6_V1(x) | BIT_HEAD_PKT_Q6_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q7_INFO (Offset 0x0474) */ #define BIT_SHIFT_QUEUEMACID_Q7_V1 25 #define BIT_MASK_QUEUEMACID_Q7_V1 0x7f #define BIT_QUEUEMACID_Q7_V1(x) \ (((x) & BIT_MASK_QUEUEMACID_Q7_V1) << BIT_SHIFT_QUEUEMACID_Q7_V1) #define BITS_QUEUEMACID_Q7_V1 \ (BIT_MASK_QUEUEMACID_Q7_V1 << BIT_SHIFT_QUEUEMACID_Q7_V1) #define BIT_CLEAR_QUEUEMACID_Q7_V1(x) ((x) & (~BITS_QUEUEMACID_Q7_V1)) #define BIT_GET_QUEUEMACID_Q7_V1(x) \ (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1) & BIT_MASK_QUEUEMACID_Q7_V1) #define BIT_SET_QUEUEMACID_Q7_V1(x, v) \ (BIT_CLEAR_QUEUEMACID_Q7_V1(x) | BIT_QUEUEMACID_Q7_V1(v)) #define BIT_SHIFT_QUEUEAC_Q7_V1 23 #define BIT_MASK_QUEUEAC_Q7_V1 0x3 #define BIT_QUEUEAC_Q7_V1(x) \ (((x) & BIT_MASK_QUEUEAC_Q7_V1) << BIT_SHIFT_QUEUEAC_Q7_V1) #define BITS_QUEUEAC_Q7_V1 (BIT_MASK_QUEUEAC_Q7_V1 << BIT_SHIFT_QUEUEAC_Q7_V1) #define BIT_CLEAR_QUEUEAC_Q7_V1(x) ((x) & (~BITS_QUEUEAC_Q7_V1)) #define BIT_GET_QUEUEAC_Q7_V1(x) \ (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1) & BIT_MASK_QUEUEAC_Q7_V1) #define BIT_SET_QUEUEAC_Q7_V1(x, v) \ (BIT_CLEAR_QUEUEAC_Q7_V1(x) | BIT_QUEUEAC_Q7_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q7_INFO (Offset 0x0474) */ #define BIT_TIDEMPTY_Q7_V1 BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q7_INFO (Offset 0x0474) */ #define BIT_SHIFT_TAIL_PKT_Q7_V1 15 #define BIT_MASK_TAIL_PKT_Q7_V1 0xff #define BIT_TAIL_PKT_Q7_V1(x) \ (((x) & BIT_MASK_TAIL_PKT_Q7_V1) << BIT_SHIFT_TAIL_PKT_Q7_V1) #define BITS_TAIL_PKT_Q7_V1 \ (BIT_MASK_TAIL_PKT_Q7_V1 << BIT_SHIFT_TAIL_PKT_Q7_V1) #define BIT_CLEAR_TAIL_PKT_Q7_V1(x) ((x) & (~BITS_TAIL_PKT_Q7_V1)) #define BIT_GET_TAIL_PKT_Q7_V1(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V1) & BIT_MASK_TAIL_PKT_Q7_V1) #define BIT_SET_TAIL_PKT_Q7_V1(x, v) \ (BIT_CLEAR_TAIL_PKT_Q7_V1(x) | BIT_TAIL_PKT_Q7_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q7_INFO (Offset 0x0474) */ #define BIT_SHIFT_TAIL_PKT_Q7_V2 11 #define BIT_MASK_TAIL_PKT_Q7_V2 0x7ff #define BIT_TAIL_PKT_Q7_V2(x) \ (((x) & BIT_MASK_TAIL_PKT_Q7_V2) << BIT_SHIFT_TAIL_PKT_Q7_V2) #define BITS_TAIL_PKT_Q7_V2 \ (BIT_MASK_TAIL_PKT_Q7_V2 << BIT_SHIFT_TAIL_PKT_Q7_V2) #define BIT_CLEAR_TAIL_PKT_Q7_V2(x) ((x) & (~BITS_TAIL_PKT_Q7_V2)) #define BIT_GET_TAIL_PKT_Q7_V2(x) \ (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2) & BIT_MASK_TAIL_PKT_Q7_V2) #define BIT_SET_TAIL_PKT_Q7_V2(x, v) \ (BIT_CLEAR_TAIL_PKT_Q7_V2(x) | BIT_TAIL_PKT_Q7_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_Q7_INFO (Offset 0x0474) */ #define BIT_SHIFT_PKT_NUM_Q7_V1 8 #define BIT_MASK_PKT_NUM_Q7_V1 0x7f #define BIT_PKT_NUM_Q7_V1(x) \ (((x) & BIT_MASK_PKT_NUM_Q7_V1) << BIT_SHIFT_PKT_NUM_Q7_V1) #define BITS_PKT_NUM_Q7_V1 (BIT_MASK_PKT_NUM_Q7_V1 << BIT_SHIFT_PKT_NUM_Q7_V1) #define BIT_CLEAR_PKT_NUM_Q7_V1(x) ((x) & (~BITS_PKT_NUM_Q7_V1)) #define BIT_GET_PKT_NUM_Q7_V1(x) \ (((x) >> BIT_SHIFT_PKT_NUM_Q7_V1) & BIT_MASK_PKT_NUM_Q7_V1) #define BIT_SET_PKT_NUM_Q7_V1(x, v) \ (BIT_CLEAR_PKT_NUM_Q7_V1(x) | BIT_PKT_NUM_Q7_V1(v)) #define BIT_SHIFT_HEAD_PKT_Q7 0 #define BIT_MASK_HEAD_PKT_Q7 0xff #define BIT_HEAD_PKT_Q7(x) \ (((x) & BIT_MASK_HEAD_PKT_Q7) << BIT_SHIFT_HEAD_PKT_Q7) #define BITS_HEAD_PKT_Q7 (BIT_MASK_HEAD_PKT_Q7 << BIT_SHIFT_HEAD_PKT_Q7) #define BIT_CLEAR_HEAD_PKT_Q7(x) ((x) & (~BITS_HEAD_PKT_Q7)) #define BIT_GET_HEAD_PKT_Q7(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_Q7) & BIT_MASK_HEAD_PKT_Q7) #define BIT_SET_HEAD_PKT_Q7(x, v) \ (BIT_CLEAR_HEAD_PKT_Q7(x) | BIT_HEAD_PKT_Q7(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q7_INFO (Offset 0x0474) */ #define BIT_SHIFT_HEAD_PKT_Q7_V1 0 #define BIT_MASK_HEAD_PKT_Q7_V1 0x7ff #define BIT_HEAD_PKT_Q7_V1(x) \ (((x) & BIT_MASK_HEAD_PKT_Q7_V1) << BIT_SHIFT_HEAD_PKT_Q7_V1) #define BITS_HEAD_PKT_Q7_V1 \ (BIT_MASK_HEAD_PKT_Q7_V1 << BIT_SHIFT_HEAD_PKT_Q7_V1) #define BIT_CLEAR_HEAD_PKT_Q7_V1(x) ((x) & (~BITS_HEAD_PKT_Q7_V1)) #define BIT_GET_HEAD_PKT_Q7_V1(x) \ (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1) & BIT_MASK_HEAD_PKT_Q7_V1) #define BIT_SET_HEAD_PKT_Q7_V1(x, v) \ (BIT_CLEAR_HEAD_PKT_Q7_V1(x) | BIT_HEAD_PKT_Q7_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_LBK_BUF_HD_V1 (Offset 0x0478) */ #define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1 0 #define BIT_MASK_WMAC_LBK_BUF_HEAD_V1 0xfff #define BIT_WMAC_LBK_BUF_HEAD_V1(x) \ (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1) \ << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) #define BITS_WMAC_LBK_BUF_HEAD_V1 \ (BIT_MASK_WMAC_LBK_BUF_HEAD_V1 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) #define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1(x) ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1)) #define BIT_GET_WMAC_LBK_BUF_HEAD_V1(x) \ (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) & \ BIT_MASK_WMAC_LBK_BUF_HEAD_V1) #define BIT_SET_WMAC_LBK_BUF_HEAD_V1(x, v) \ (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1(x) | BIT_WMAC_LBK_BUF_HEAD_V1(v)) /* 2 REG_MGQ_BDNY_V1 (Offset 0x047A) */ #define BIT_SHIFT_MGQ_PGBNDY_V1 0 #define BIT_MASK_MGQ_PGBNDY_V1 0xfff #define BIT_MGQ_PGBNDY_V1(x) \ (((x) & BIT_MASK_MGQ_PGBNDY_V1) << BIT_SHIFT_MGQ_PGBNDY_V1) #define BITS_MGQ_PGBNDY_V1 (BIT_MASK_MGQ_PGBNDY_V1 << BIT_SHIFT_MGQ_PGBNDY_V1) #define BIT_CLEAR_MGQ_PGBNDY_V1(x) ((x) & (~BITS_MGQ_PGBNDY_V1)) #define BIT_GET_MGQ_PGBNDY_V1(x) \ (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1) & BIT_MASK_MGQ_PGBNDY_V1) #define BIT_SET_MGQ_PGBNDY_V1(x, v) \ (BIT_CLEAR_MGQ_PGBNDY_V1(x) | BIT_MGQ_PGBNDY_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXRPT_CTRL (Offset 0x047C) */ #define BIT_SHIFT_SPC_READ_PTR 24 #define BIT_MASK_SPC_READ_PTR 0xf #define BIT_SPC_READ_PTR(x) \ (((x) & BIT_MASK_SPC_READ_PTR) << BIT_SHIFT_SPC_READ_PTR) #define BITS_SPC_READ_PTR (BIT_MASK_SPC_READ_PTR << BIT_SHIFT_SPC_READ_PTR) #define BIT_CLEAR_SPC_READ_PTR(x) ((x) & (~BITS_SPC_READ_PTR)) #define BIT_GET_SPC_READ_PTR(x) \ (((x) >> BIT_SHIFT_SPC_READ_PTR) & BIT_MASK_SPC_READ_PTR) #define BIT_SET_SPC_READ_PTR(x, v) \ (BIT_CLEAR_SPC_READ_PTR(x) | BIT_SPC_READ_PTR(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXRPT_CTRL (Offset 0x047C) */ #define BIT_SHIFT_TRXRPT_TIMER_TH 24 #define BIT_MASK_TRXRPT_TIMER_TH 0xff #define BIT_TRXRPT_TIMER_TH(x) \ (((x) & BIT_MASK_TRXRPT_TIMER_TH) << BIT_SHIFT_TRXRPT_TIMER_TH) #define BITS_TRXRPT_TIMER_TH \ (BIT_MASK_TRXRPT_TIMER_TH << BIT_SHIFT_TRXRPT_TIMER_TH) #define BIT_CLEAR_TRXRPT_TIMER_TH(x) ((x) & (~BITS_TRXRPT_TIMER_TH)) #define BIT_GET_TRXRPT_TIMER_TH(x) \ (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH) & BIT_MASK_TRXRPT_TIMER_TH) #define BIT_SET_TRXRPT_TIMER_TH(x, v) \ (BIT_CLEAR_TRXRPT_TIMER_TH(x) | BIT_TRXRPT_TIMER_TH(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXRPT_CTRL (Offset 0x047C) */ #define BIT_SHIFT_SPC_WRITE_PTR 16 #define BIT_MASK_SPC_WRITE_PTR 0xf #define BIT_SPC_WRITE_PTR(x) \ (((x) & BIT_MASK_SPC_WRITE_PTR) << BIT_SHIFT_SPC_WRITE_PTR) #define BITS_SPC_WRITE_PTR (BIT_MASK_SPC_WRITE_PTR << BIT_SHIFT_SPC_WRITE_PTR) #define BIT_CLEAR_SPC_WRITE_PTR(x) ((x) & (~BITS_SPC_WRITE_PTR)) #define BIT_GET_SPC_WRITE_PTR(x) \ (((x) >> BIT_SHIFT_SPC_WRITE_PTR) & BIT_MASK_SPC_WRITE_PTR) #define BIT_SET_SPC_WRITE_PTR(x, v) \ (BIT_CLEAR_SPC_WRITE_PTR(x) | BIT_SPC_WRITE_PTR(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXRPT_CTRL (Offset 0x047C) */ #define BIT_SHIFT_TRXRPT_LEN_TH 16 #define BIT_MASK_TRXRPT_LEN_TH 0xff #define BIT_TRXRPT_LEN_TH(x) \ (((x) & BIT_MASK_TRXRPT_LEN_TH) << BIT_SHIFT_TRXRPT_LEN_TH) #define BITS_TRXRPT_LEN_TH (BIT_MASK_TRXRPT_LEN_TH << BIT_SHIFT_TRXRPT_LEN_TH) #define BIT_CLEAR_TRXRPT_LEN_TH(x) ((x) & (~BITS_TRXRPT_LEN_TH)) #define BIT_GET_TRXRPT_LEN_TH(x) \ (((x) >> BIT_SHIFT_TRXRPT_LEN_TH) & BIT_MASK_TRXRPT_LEN_TH) #define BIT_SET_TRXRPT_LEN_TH(x, v) \ (BIT_CLEAR_TRXRPT_LEN_TH(x) | BIT_TRXRPT_LEN_TH(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXRPT_CTRL (Offset 0x047C) */ #define BIT_SHIFT_AC_READ_PTR 8 #define BIT_MASK_AC_READ_PTR 0xf #define BIT_AC_READ_PTR(x) \ (((x) & BIT_MASK_AC_READ_PTR) << BIT_SHIFT_AC_READ_PTR) #define BITS_AC_READ_PTR (BIT_MASK_AC_READ_PTR << BIT_SHIFT_AC_READ_PTR) #define BIT_CLEAR_AC_READ_PTR(x) ((x) & (~BITS_AC_READ_PTR)) #define BIT_GET_AC_READ_PTR(x) \ (((x) >> BIT_SHIFT_AC_READ_PTR) & BIT_MASK_AC_READ_PTR) #define BIT_SET_AC_READ_PTR(x, v) \ (BIT_CLEAR_AC_READ_PTR(x) | BIT_AC_READ_PTR(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXRPT_CTRL (Offset 0x047C) */ #define BIT_SHIFT_TRXRPT_READ_PTR 8 #define BIT_MASK_TRXRPT_READ_PTR 0xff #define BIT_TRXRPT_READ_PTR(x) \ (((x) & BIT_MASK_TRXRPT_READ_PTR) << BIT_SHIFT_TRXRPT_READ_PTR) #define BITS_TRXRPT_READ_PTR \ (BIT_MASK_TRXRPT_READ_PTR << BIT_SHIFT_TRXRPT_READ_PTR) #define BIT_CLEAR_TRXRPT_READ_PTR(x) ((x) & (~BITS_TRXRPT_READ_PTR)) #define BIT_GET_TRXRPT_READ_PTR(x) \ (((x) >> BIT_SHIFT_TRXRPT_READ_PTR) & BIT_MASK_TRXRPT_READ_PTR) #define BIT_SET_TRXRPT_READ_PTR(x, v) \ (BIT_CLEAR_TRXRPT_READ_PTR(x) | BIT_TRXRPT_READ_PTR(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXRPT_CTRL (Offset 0x047C) */ #define BIT_SHIFT_AC_WRITE_PTR 0 #define BIT_MASK_AC_WRITE_PTR 0xf #define BIT_AC_WRITE_PTR(x) \ (((x) & BIT_MASK_AC_WRITE_PTR) << BIT_SHIFT_AC_WRITE_PTR) #define BITS_AC_WRITE_PTR (BIT_MASK_AC_WRITE_PTR << BIT_SHIFT_AC_WRITE_PTR) #define BIT_CLEAR_AC_WRITE_PTR(x) ((x) & (~BITS_AC_WRITE_PTR)) #define BIT_GET_AC_WRITE_PTR(x) \ (((x) >> BIT_SHIFT_AC_WRITE_PTR) & BIT_MASK_AC_WRITE_PTR) #define BIT_SET_AC_WRITE_PTR(x, v) \ (BIT_CLEAR_AC_WRITE_PTR(x) | BIT_AC_WRITE_PTR(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXRPT_CTRL (Offset 0x047C) */ #define BIT_SHIFT_TRXRPT_WRITE_PTR 0 #define BIT_MASK_TRXRPT_WRITE_PTR 0xff #define BIT_TRXRPT_WRITE_PTR(x) \ (((x) & BIT_MASK_TRXRPT_WRITE_PTR) << BIT_SHIFT_TRXRPT_WRITE_PTR) #define BITS_TRXRPT_WRITE_PTR \ (BIT_MASK_TRXRPT_WRITE_PTR << BIT_SHIFT_TRXRPT_WRITE_PTR) #define BIT_CLEAR_TRXRPT_WRITE_PTR(x) ((x) & (~BITS_TRXRPT_WRITE_PTR)) #define BIT_GET_TRXRPT_WRITE_PTR(x) \ (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR) & BIT_MASK_TRXRPT_WRITE_PTR) #define BIT_SET_TRXRPT_WRITE_PTR(x, v) \ (BIT_CLEAR_TRXRPT_WRITE_PTR(x) | BIT_TRXRPT_WRITE_PTR(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_INIRTS_RATE_SEL (Offset 0x0480) */ #define BIT_LEAG_RTS_BW_DUP BIT(5) /* 2 REG_BASIC_CFEND_RATE (Offset 0x0481) */ #define BIT_SHIFT_BASIC_CFEND_RATE 0 #define BIT_MASK_BASIC_CFEND_RATE 0x1f #define BIT_BASIC_CFEND_RATE(x) \ (((x) & BIT_MASK_BASIC_CFEND_RATE) << BIT_SHIFT_BASIC_CFEND_RATE) #define BITS_BASIC_CFEND_RATE \ (BIT_MASK_BASIC_CFEND_RATE << BIT_SHIFT_BASIC_CFEND_RATE) #define BIT_CLEAR_BASIC_CFEND_RATE(x) ((x) & (~BITS_BASIC_CFEND_RATE)) #define BIT_GET_BASIC_CFEND_RATE(x) \ (((x) >> BIT_SHIFT_BASIC_CFEND_RATE) & BIT_MASK_BASIC_CFEND_RATE) #define BIT_SET_BASIC_CFEND_RATE(x, v) \ (BIT_CLEAR_BASIC_CFEND_RATE(x) | BIT_BASIC_CFEND_RATE(v)) /* 2 REG_STBC_CFEND_RATE (Offset 0x0482) */ #define BIT_SHIFT_STBC_CFEND_RATE 0 #define BIT_MASK_STBC_CFEND_RATE 0x1f #define BIT_STBC_CFEND_RATE(x) \ (((x) & BIT_MASK_STBC_CFEND_RATE) << BIT_SHIFT_STBC_CFEND_RATE) #define BITS_STBC_CFEND_RATE \ (BIT_MASK_STBC_CFEND_RATE << BIT_SHIFT_STBC_CFEND_RATE) #define BIT_CLEAR_STBC_CFEND_RATE(x) ((x) & (~BITS_STBC_CFEND_RATE)) #define BIT_GET_STBC_CFEND_RATE(x) \ (((x) >> BIT_SHIFT_STBC_CFEND_RATE) & BIT_MASK_STBC_CFEND_RATE) #define BIT_SET_STBC_CFEND_RATE(x, v) \ (BIT_CLEAR_STBC_CFEND_RATE(x) | BIT_STBC_CFEND_RATE(v)) /* 2 REG_DATA_SC (Offset 0x0483) */ #define BIT_SHIFT_TXSC_40M 4 #define BIT_MASK_TXSC_40M 0xf #define BIT_TXSC_40M(x) (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M) #define BITS_TXSC_40M (BIT_MASK_TXSC_40M << BIT_SHIFT_TXSC_40M) #define BIT_CLEAR_TXSC_40M(x) ((x) & (~BITS_TXSC_40M)) #define BIT_GET_TXSC_40M(x) (((x) >> BIT_SHIFT_TXSC_40M) & BIT_MASK_TXSC_40M) #define BIT_SET_TXSC_40M(x, v) (BIT_CLEAR_TXSC_40M(x) | BIT_TXSC_40M(v)) #define BIT_SHIFT_TXSC_20M 0 #define BIT_MASK_TXSC_20M 0xf #define BIT_TXSC_20M(x) (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M) #define BITS_TXSC_20M (BIT_MASK_TXSC_20M << BIT_SHIFT_TXSC_20M) #define BIT_CLEAR_TXSC_20M(x) ((x) & (~BITS_TXSC_20M)) #define BIT_GET_TXSC_20M(x) (((x) >> BIT_SHIFT_TXSC_20M) & BIT_MASK_TXSC_20M) #define BIT_SET_TXSC_20M(x, v) (BIT_CLEAR_TXSC_20M(x) | BIT_TXSC_20M(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MACID_SLEEP3 (Offset 0x0484) */ #define BIT_SHIFT_MACID127_96_PKTSLEEP 0 #define BIT_MASK_MACID127_96_PKTSLEEP 0xffffffffL #define BIT_MACID127_96_PKTSLEEP(x) \ (((x) & BIT_MASK_MACID127_96_PKTSLEEP) \ << BIT_SHIFT_MACID127_96_PKTSLEEP) #define BITS_MACID127_96_PKTSLEEP \ (BIT_MASK_MACID127_96_PKTSLEEP << BIT_SHIFT_MACID127_96_PKTSLEEP) #define BIT_CLEAR_MACID127_96_PKTSLEEP(x) ((x) & (~BITS_MACID127_96_PKTSLEEP)) #define BIT_GET_MACID127_96_PKTSLEEP(x) \ (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP) & \ BIT_MASK_MACID127_96_PKTSLEEP) #define BIT_SET_MACID127_96_PKTSLEEP(x, v) \ (BIT_CLEAR_MACID127_96_PKTSLEEP(x) | BIT_MACID127_96_PKTSLEEP(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DATA_SC1 (Offset 0x0487) */ #define BIT_SHIFT_TXSC_160M 4 #define BIT_MASK_TXSC_160M 0xf #define BIT_TXSC_160M(x) (((x) & BIT_MASK_TXSC_160M) << BIT_SHIFT_TXSC_160M) #define BITS_TXSC_160M (BIT_MASK_TXSC_160M << BIT_SHIFT_TXSC_160M) #define BIT_CLEAR_TXSC_160M(x) ((x) & (~BITS_TXSC_160M)) #define BIT_GET_TXSC_160M(x) (((x) >> BIT_SHIFT_TXSC_160M) & BIT_MASK_TXSC_160M) #define BIT_SET_TXSC_160M(x, v) (BIT_CLEAR_TXSC_160M(x) | BIT_TXSC_160M(v)) #define BIT_SHIFT_TXSC_80M 0 #define BIT_MASK_TXSC_80M 0xf #define BIT_TXSC_80M(x) (((x) & BIT_MASK_TXSC_80M) << BIT_SHIFT_TXSC_80M) #define BITS_TXSC_80M (BIT_MASK_TXSC_80M << BIT_SHIFT_TXSC_80M) #define BIT_CLEAR_TXSC_80M(x) ((x) & (~BITS_TXSC_80M)) #define BIT_GET_TXSC_80M(x) (((x) >> BIT_SHIFT_TXSC_80M) & BIT_MASK_TXSC_80M) #define BIT_SET_TXSC_80M(x, v) (BIT_CLEAR_TXSC_80M(x) | BIT_TXSC_80M(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MACID_SLEEP1 (Offset 0x0488) */ #define BIT_SHIFT_MACID63_32_PKTSLEEP 0 #define BIT_MASK_MACID63_32_PKTSLEEP 0xffffffffL #define BIT_MACID63_32_PKTSLEEP(x) \ (((x) & BIT_MASK_MACID63_32_PKTSLEEP) << BIT_SHIFT_MACID63_32_PKTSLEEP) #define BITS_MACID63_32_PKTSLEEP \ (BIT_MASK_MACID63_32_PKTSLEEP << BIT_SHIFT_MACID63_32_PKTSLEEP) #define BIT_CLEAR_MACID63_32_PKTSLEEP(x) ((x) & (~BITS_MACID63_32_PKTSLEEP)) #define BIT_GET_MACID63_32_PKTSLEEP(x) \ (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP) & BIT_MASK_MACID63_32_PKTSLEEP) #define BIT_SET_MACID63_32_PKTSLEEP(x, v) \ (BIT_CLEAR_MACID63_32_PKTSLEEP(x) | BIT_MACID63_32_PKTSLEEP(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_ARFR2_V1 (Offset 0x048C) */ #define BIT_SHIFT_ARFR2_V1 0 #define BIT_MASK_ARFR2_V1 0xffffffffffffffffL #define BIT_ARFR2_V1(x) (((x) & BIT_MASK_ARFR2_V1) << BIT_SHIFT_ARFR2_V1) #define BITS_ARFR2_V1 (BIT_MASK_ARFR2_V1 << BIT_SHIFT_ARFR2_V1) #define BIT_CLEAR_ARFR2_V1(x) ((x) & (~BITS_ARFR2_V1)) #define BIT_GET_ARFR2_V1(x) (((x) >> BIT_SHIFT_ARFR2_V1) & BIT_MASK_ARFR2_V1) #define BIT_SET_ARFR2_V1(x, v) (BIT_CLEAR_ARFR2_V1(x) | BIT_ARFR2_V1(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ARFR2_V1 (Offset 0x048C) */ #define BIT_SHIFT_ARFRL2 0 #define BIT_MASK_ARFRL2 0xffffffffL #define BIT_ARFRL2(x) (((x) & BIT_MASK_ARFRL2) << BIT_SHIFT_ARFRL2) #define BITS_ARFRL2 (BIT_MASK_ARFRL2 << BIT_SHIFT_ARFRL2) #define BIT_CLEAR_ARFRL2(x) ((x) & (~BITS_ARFRL2)) #define BIT_GET_ARFRL2(x) (((x) >> BIT_SHIFT_ARFRL2) & BIT_MASK_ARFRL2) #define BIT_SET_ARFRL2(x, v) (BIT_CLEAR_ARFRL2(x) | BIT_ARFRL2(v)) /* 2 REG_ARFRH2_V1 (Offset 0x0490) */ #define BIT_SHIFT_ARFRH2 0 #define BIT_MASK_ARFRH2 0xffffffffL #define BIT_ARFRH2(x) (((x) & BIT_MASK_ARFRH2) << BIT_SHIFT_ARFRH2) #define BITS_ARFRH2 (BIT_MASK_ARFRH2 << BIT_SHIFT_ARFRH2) #define BIT_CLEAR_ARFRH2(x) ((x) & (~BITS_ARFRH2)) #define BIT_GET_ARFRH2(x) (((x) >> BIT_SHIFT_ARFRH2) & BIT_MASK_ARFRH2) #define BIT_SET_ARFRH2(x, v) (BIT_CLEAR_ARFRH2(x) | BIT_ARFRH2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_ARFR3_V1 (Offset 0x0494) */ #define BIT_SHIFT_ARFR3_V1 0 #define BIT_MASK_ARFR3_V1 0xffffffffffffffffL #define BIT_ARFR3_V1(x) (((x) & BIT_MASK_ARFR3_V1) << BIT_SHIFT_ARFR3_V1) #define BITS_ARFR3_V1 (BIT_MASK_ARFR3_V1 << BIT_SHIFT_ARFR3_V1) #define BIT_CLEAR_ARFR3_V1(x) ((x) & (~BITS_ARFR3_V1)) #define BIT_GET_ARFR3_V1(x) (((x) >> BIT_SHIFT_ARFR3_V1) & BIT_MASK_ARFR3_V1) #define BIT_SET_ARFR3_V1(x, v) (BIT_CLEAR_ARFR3_V1(x) | BIT_ARFR3_V1(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ARFR3_V1 (Offset 0x0494) */ #define BIT_SHIFT_ARFRL3 0 #define BIT_MASK_ARFRL3 0xffffffffL #define BIT_ARFRL3(x) (((x) & BIT_MASK_ARFRL3) << BIT_SHIFT_ARFRL3) #define BITS_ARFRL3 (BIT_MASK_ARFRL3 << BIT_SHIFT_ARFRL3) #define BIT_CLEAR_ARFRL3(x) ((x) & (~BITS_ARFRL3)) #define BIT_GET_ARFRL3(x) (((x) >> BIT_SHIFT_ARFRL3) & BIT_MASK_ARFRL3) #define BIT_SET_ARFRL3(x, v) (BIT_CLEAR_ARFRL3(x) | BIT_ARFRL3(v)) /* 2 REG_ARFRH3_V1 (Offset 0x0498) */ #define BIT_SHIFT_ARFRH3 0 #define BIT_MASK_ARFRH3 0xffffffffL #define BIT_ARFRH3(x) (((x) & BIT_MASK_ARFRH3) << BIT_SHIFT_ARFRH3) #define BITS_ARFRH3 (BIT_MASK_ARFRH3 << BIT_SHIFT_ARFRH3) #define BIT_CLEAR_ARFRH3(x) ((x) & (~BITS_ARFRH3)) #define BIT_GET_ARFRH3(x) (((x) >> BIT_SHIFT_ARFRH3) & BIT_MASK_ARFRH3) #define BIT_SET_ARFRH3(x, v) (BIT_CLEAR_ARFRH3(x) | BIT_ARFRH3(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_ARFR4 (Offset 0x049C) */ #define BIT_SHIFT_ARFR4 0 #define BIT_MASK_ARFR4 0xffffffffffffffffL #define BIT_ARFR4(x) (((x) & BIT_MASK_ARFR4) << BIT_SHIFT_ARFR4) #define BITS_ARFR4 (BIT_MASK_ARFR4 << BIT_SHIFT_ARFR4) #define BIT_CLEAR_ARFR4(x) ((x) & (~BITS_ARFR4)) #define BIT_GET_ARFR4(x) (((x) >> BIT_SHIFT_ARFR4) & BIT_MASK_ARFR4) #define BIT_SET_ARFR4(x, v) (BIT_CLEAR_ARFR4(x) | BIT_ARFR4(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ARFR4 (Offset 0x049C) */ #define BIT_SHIFT_ARFRL4 0 #define BIT_MASK_ARFRL4 0xffffffffL #define BIT_ARFRL4(x) (((x) & BIT_MASK_ARFRL4) << BIT_SHIFT_ARFRL4) #define BITS_ARFRL4 (BIT_MASK_ARFRL4 << BIT_SHIFT_ARFRL4) #define BIT_CLEAR_ARFRL4(x) ((x) & (~BITS_ARFRL4)) #define BIT_GET_ARFRL4(x) (((x) >> BIT_SHIFT_ARFRL4) & BIT_MASK_ARFRL4) #define BIT_SET_ARFRL4(x, v) (BIT_CLEAR_ARFRL4(x) | BIT_ARFRL4(v)) /* 2 REG_ARFRH4 (Offset 0x04A0) */ #define BIT_SHIFT_ARFRH4 0 #define BIT_MASK_ARFRH4 0xffffffffL #define BIT_ARFRH4(x) (((x) & BIT_MASK_ARFRH4) << BIT_SHIFT_ARFRH4) #define BITS_ARFRH4 (BIT_MASK_ARFRH4 << BIT_SHIFT_ARFRH4) #define BIT_CLEAR_ARFRH4(x) ((x) & (~BITS_ARFRH4)) #define BIT_GET_ARFRH4(x) (((x) >> BIT_SHIFT_ARFRH4) & BIT_MASK_ARFRH4) #define BIT_SET_ARFRH4(x, v) (BIT_CLEAR_ARFRH4(x) | BIT_ARFRH4(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_ARFR5 (Offset 0x04A4) */ #define BIT_SHIFT_ARFR5 0 #define BIT_MASK_ARFR5 0xffffffffffffffffL #define BIT_ARFR5(x) (((x) & BIT_MASK_ARFR5) << BIT_SHIFT_ARFR5) #define BITS_ARFR5 (BIT_MASK_ARFR5 << BIT_SHIFT_ARFR5) #define BIT_CLEAR_ARFR5(x) ((x) & (~BITS_ARFR5)) #define BIT_GET_ARFR5(x) (((x) >> BIT_SHIFT_ARFR5) & BIT_MASK_ARFR5) #define BIT_SET_ARFR5(x, v) (BIT_CLEAR_ARFR5(x) | BIT_ARFR5(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ARFR5 (Offset 0x04A4) */ #define BIT_SHIFT_ARFRL5 0 #define BIT_MASK_ARFRL5 0xffffffffL #define BIT_ARFRL5(x) (((x) & BIT_MASK_ARFRL5) << BIT_SHIFT_ARFRL5) #define BITS_ARFRL5 (BIT_MASK_ARFRL5 << BIT_SHIFT_ARFRL5) #define BIT_CLEAR_ARFRL5(x) ((x) & (~BITS_ARFRL5)) #define BIT_GET_ARFRL5(x) (((x) >> BIT_SHIFT_ARFRL5) & BIT_MASK_ARFRL5) #define BIT_SET_ARFRL5(x, v) (BIT_CLEAR_ARFRL5(x) | BIT_ARFRL5(v)) /* 2 REG_ARFRH5 (Offset 0x04A8) */ #define BIT_SHIFT_ARFRH5 0 #define BIT_MASK_ARFRH5 0xffffffffL #define BIT_ARFRH5(x) (((x) & BIT_MASK_ARFRH5) << BIT_SHIFT_ARFRH5) #define BITS_ARFRH5 (BIT_MASK_ARFRH5 << BIT_SHIFT_ARFRH5) #define BIT_CLEAR_ARFRH5(x) ((x) & (~BITS_ARFRH5)) #define BIT_GET_ARFRH5(x) (((x) >> BIT_SHIFT_ARFRH5) & BIT_MASK_ARFRH5) #define BIT_SET_ARFRH5(x, v) (BIT_CLEAR_ARFRH5(x) | BIT_ARFRH5(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ #define BIT_RPTFIFO_RPTNUM_OPT BIT(31) #define BIT_SHIFT_MISSED_RPT_NUM 28 #define BIT_MASK_MISSED_RPT_NUM 0x7 #define BIT_MISSED_RPT_NUM(x) \ (((x) & BIT_MASK_MISSED_RPT_NUM) << BIT_SHIFT_MISSED_RPT_NUM) #define BITS_MISSED_RPT_NUM \ (BIT_MASK_MISSED_RPT_NUM << BIT_SHIFT_MISSED_RPT_NUM) #define BIT_CLEAR_MISSED_RPT_NUM(x) ((x) & (~BITS_MISSED_RPT_NUM)) #define BIT_GET_MISSED_RPT_NUM(x) \ (((x) >> BIT_SHIFT_MISSED_RPT_NUM) & BIT_MASK_MISSED_RPT_NUM) #define BIT_SET_MISSED_RPT_NUM(x, v) \ (BIT_CLEAR_MISSED_RPT_NUM(x) | BIT_MISSED_RPT_NUM(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ #define BIT_SHCUT_PARSE_DASA BIT(25) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ #define BIT_SHIFT_LOC_AMPDU_BURST_CTRL 24 #define BIT_MASK_LOC_AMPDU_BURST_CTRL 0xff #define BIT_LOC_AMPDU_BURST_CTRL(x) \ (((x) & BIT_MASK_LOC_AMPDU_BURST_CTRL) \ << BIT_SHIFT_LOC_AMPDU_BURST_CTRL) #define BITS_LOC_AMPDU_BURST_CTRL \ (BIT_MASK_LOC_AMPDU_BURST_CTRL << BIT_SHIFT_LOC_AMPDU_BURST_CTRL) #define BIT_CLEAR_LOC_AMPDU_BURST_CTRL(x) ((x) & (~BITS_LOC_AMPDU_BURST_CTRL)) #define BIT_GET_LOC_AMPDU_BURST_CTRL(x) \ (((x) >> BIT_SHIFT_LOC_AMPDU_BURST_CTRL) & \ BIT_MASK_LOC_AMPDU_BURST_CTRL) #define BIT_SET_LOC_AMPDU_BURST_CTRL(x, v) \ (BIT_CLEAR_LOC_AMPDU_BURST_CTRL(x) | BIT_LOC_AMPDU_BURST_CTRL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ #define BIT_SHCUT_BYPASS BIT(24) #endif #if (HALMAC_8821C_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ #define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET 24 #define BIT_MASK_R_MUTAB_TXRPT_OFFSET 0xff #define BIT_R_MUTAB_TXRPT_OFFSET(x) \ (((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET) \ << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET) #define BITS_R_MUTAB_TXRPT_OFFSET \ (BIT_MASK_R_MUTAB_TXRPT_OFFSET << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET) #define BIT_CLEAR_R_MUTAB_TXRPT_OFFSET(x) ((x) & (~BITS_R_MUTAB_TXRPT_OFFSET)) #define BIT_GET_R_MUTAB_TXRPT_OFFSET(x) \ (((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET) & \ BIT_MASK_R_MUTAB_TXRPT_OFFSET) #define BIT_SET_R_MUTAB_TXRPT_OFFSET(x, v) \ (BIT_CLEAR_R_MUTAB_TXRPT_OFFSET(x) | BIT_R_MUTAB_TXRPT_OFFSET(v)) #endif #if (HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ #define BIT_SHIFT_MACID_MURATE_OFFSET 24 #define BIT_MASK_MACID_MURATE_OFFSET 0xff #define BIT_MACID_MURATE_OFFSET(x) \ (((x) & BIT_MASK_MACID_MURATE_OFFSET) << BIT_SHIFT_MACID_MURATE_OFFSET) #define BITS_MACID_MURATE_OFFSET \ (BIT_MASK_MACID_MURATE_OFFSET << BIT_SHIFT_MACID_MURATE_OFFSET) #define BIT_CLEAR_MACID_MURATE_OFFSET(x) ((x) & (~BITS_MACID_MURATE_OFFSET)) #define BIT_GET_MACID_MURATE_OFFSET(x) \ (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET) & BIT_MASK_MACID_MURATE_OFFSET) #define BIT_SET_MACID_MURATE_OFFSET(x, v) \ (BIT_CLEAR_MACID_MURATE_OFFSET(x) | BIT_MACID_MURATE_OFFSET(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ #define BIT_SHIFT_TXRPT_MISS_COUNT 17 #define BIT_MASK_TXRPT_MISS_COUNT 0x7 #define BIT_TXRPT_MISS_COUNT(x) \ (((x) & BIT_MASK_TXRPT_MISS_COUNT) << BIT_SHIFT_TXRPT_MISS_COUNT) #define BITS_TXRPT_MISS_COUNT \ (BIT_MASK_TXRPT_MISS_COUNT << BIT_SHIFT_TXRPT_MISS_COUNT) #define BIT_CLEAR_TXRPT_MISS_COUNT(x) ((x) & (~BITS_TXRPT_MISS_COUNT)) #define BIT_GET_TXRPT_MISS_COUNT(x) \ (((x) >> BIT_SHIFT_TXRPT_MISS_COUNT) & BIT_MASK_TXRPT_MISS_COUNT) #define BIT_SET_TXRPT_MISS_COUNT(x, v) \ (BIT_CLEAR_TXRPT_MISS_COUNT(x) | BIT_TXRPT_MISS_COUNT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ #define BIT_SHIFT_LOC_BCN_RPT 16 #define BIT_MASK_LOC_BCN_RPT 0xff #define BIT_LOC_BCN_RPT(x) \ (((x) & BIT_MASK_LOC_BCN_RPT) << BIT_SHIFT_LOC_BCN_RPT) #define BITS_LOC_BCN_RPT (BIT_MASK_LOC_BCN_RPT << BIT_SHIFT_LOC_BCN_RPT) #define BIT_CLEAR_LOC_BCN_RPT(x) ((x) & (~BITS_LOC_BCN_RPT)) #define BIT_GET_LOC_BCN_RPT(x) \ (((x) >> BIT_SHIFT_LOC_BCN_RPT) & BIT_MASK_LOC_BCN_RPT) #define BIT_SET_LOC_BCN_RPT(x, v) \ (BIT_CLEAR_LOC_BCN_RPT(x) | BIT_LOC_BCN_RPT(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ #define BIT__R_RPTFIFO_1K BIT(16) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ #define BIT_SHIFT_MACID_SHCUT_OFFSET 16 #define BIT_MASK_MACID_SHCUT_OFFSET 0xff #define BIT_MACID_SHCUT_OFFSET(x) \ (((x) & BIT_MASK_MACID_SHCUT_OFFSET) << BIT_SHIFT_MACID_SHCUT_OFFSET) #define BITS_MACID_SHCUT_OFFSET \ (BIT_MASK_MACID_SHCUT_OFFSET << BIT_SHIFT_MACID_SHCUT_OFFSET) #define BIT_CLEAR_MACID_SHCUT_OFFSET(x) ((x) & (~BITS_MACID_SHCUT_OFFSET)) #define BIT_GET_MACID_SHCUT_OFFSET(x) \ (((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET) & BIT_MASK_MACID_SHCUT_OFFSET) #define BIT_SET_MACID_SHCUT_OFFSET(x, v) \ (BIT_CLEAR_MACID_SHCUT_OFFSET(x) | BIT_MACID_SHCUT_OFFSET(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ #define BIT_SHIFT_MACID_CTRL_OFFSET_V1 16 #define BIT_MASK_MACID_CTRL_OFFSET_V1 0x1ff #define BIT_MACID_CTRL_OFFSET_V1(x) \ (((x) & BIT_MASK_MACID_CTRL_OFFSET_V1) \ << BIT_SHIFT_MACID_CTRL_OFFSET_V1) #define BITS_MACID_CTRL_OFFSET_V1 \ (BIT_MASK_MACID_CTRL_OFFSET_V1 << BIT_SHIFT_MACID_CTRL_OFFSET_V1) #define BIT_CLEAR_MACID_CTRL_OFFSET_V1(x) ((x) & (~BITS_MACID_CTRL_OFFSET_V1)) #define BIT_GET_MACID_CTRL_OFFSET_V1(x) \ (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_V1) & \ BIT_MASK_MACID_CTRL_OFFSET_V1) #define BIT_SET_MACID_CTRL_OFFSET_V1(x, v) \ (BIT_CLEAR_MACID_CTRL_OFFSET_V1(x) | BIT_MACID_CTRL_OFFSET_V1(v)) #endif #if (HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ #define BIT_RPTFIFO_SIZE_OPT BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ #define BIT_SHIFT_LOC_TXRPT 8 #define BIT_MASK_LOC_TXRPT 0xff #define BIT_LOC_TXRPT(x) (((x) & BIT_MASK_LOC_TXRPT) << BIT_SHIFT_LOC_TXRPT) #define BITS_LOC_TXRPT (BIT_MASK_LOC_TXRPT << BIT_SHIFT_LOC_TXRPT) #define BIT_CLEAR_LOC_TXRPT(x) ((x) & (~BITS_LOC_TXRPT)) #define BIT_GET_LOC_TXRPT(x) (((x) >> BIT_SHIFT_LOC_TXRPT) & BIT_MASK_LOC_TXRPT) #define BIT_SET_LOC_TXRPT(x, v) (BIT_CLEAR_LOC_TXRPT(x) | BIT_LOC_TXRPT(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ #define BIT_SHIFT_MACID_CTRL_OFFSET 8 #define BIT_MASK_MACID_CTRL_OFFSET 0xff #define BIT_MACID_CTRL_OFFSET(x) \ (((x) & BIT_MASK_MACID_CTRL_OFFSET) << BIT_SHIFT_MACID_CTRL_OFFSET) #define BITS_MACID_CTRL_OFFSET \ (BIT_MASK_MACID_CTRL_OFFSET << BIT_SHIFT_MACID_CTRL_OFFSET) #define BIT_CLEAR_MACID_CTRL_OFFSET(x) ((x) & (~BITS_MACID_CTRL_OFFSET)) #define BIT_GET_MACID_CTRL_OFFSET(x) \ (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET) & BIT_MASK_MACID_CTRL_OFFSET) #define BIT_SET_MACID_CTRL_OFFSET(x, v) \ (BIT_CLEAR_MACID_CTRL_OFFSET(x) | BIT_MACID_CTRL_OFFSET(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ #define BIT_SHIFT_LOC_SRFF 0 #define BIT_MASK_LOC_SRFF 0xff #define BIT_LOC_SRFF(x) (((x) & BIT_MASK_LOC_SRFF) << BIT_SHIFT_LOC_SRFF) #define BITS_LOC_SRFF (BIT_MASK_LOC_SRFF << BIT_SHIFT_LOC_SRFF) #define BIT_CLEAR_LOC_SRFF(x) ((x) & (~BITS_LOC_SRFF)) #define BIT_GET_LOC_SRFF(x) (((x) >> BIT_SHIFT_LOC_SRFF) & BIT_MASK_LOC_SRFF) #define BIT_SET_LOC_SRFF(x, v) (BIT_CLEAR_LOC_SRFF(x) | BIT_LOC_SRFF(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ #define BIT_SHIFT_AMPDU_TXRPT_OFFSET 0 #define BIT_MASK_AMPDU_TXRPT_OFFSET 0xff #define BIT_AMPDU_TXRPT_OFFSET(x) \ (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET) << BIT_SHIFT_AMPDU_TXRPT_OFFSET) #define BITS_AMPDU_TXRPT_OFFSET \ (BIT_MASK_AMPDU_TXRPT_OFFSET << BIT_SHIFT_AMPDU_TXRPT_OFFSET) #define BIT_CLEAR_AMPDU_TXRPT_OFFSET(x) ((x) & (~BITS_AMPDU_TXRPT_OFFSET)) #define BIT_GET_AMPDU_TXRPT_OFFSET(x) \ (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET) & BIT_MASK_AMPDU_TXRPT_OFFSET) #define BIT_SET_AMPDU_TXRPT_OFFSET(x, v) \ (BIT_CLEAR_AMPDU_TXRPT_OFFSET(x) | BIT_AMPDU_TXRPT_OFFSET(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ #define BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1 0 #define BIT_MASK_AMPDU_TXRPT_OFFSET_V1 0x1ff #define BIT_AMPDU_TXRPT_OFFSET_V1(x) \ (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_V1) \ << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1) #define BITS_AMPDU_TXRPT_OFFSET_V1 \ (BIT_MASK_AMPDU_TXRPT_OFFSET_V1 << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1) #define BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1(x) ((x) & (~BITS_AMPDU_TXRPT_OFFSET_V1)) #define BIT_GET_AMPDU_TXRPT_OFFSET_V1(x) \ (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1) & \ BIT_MASK_AMPDU_TXRPT_OFFSET_V1) #define BIT_SET_AMPDU_TXRPT_OFFSET_V1(x, v) \ (BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1(x) | BIT_AMPDU_TXRPT_OFFSET_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TRYING_CNT_TH (Offset 0x04B0) */ #define BIT_SHIFT_INDEX_15 24 #define BIT_MASK_INDEX_15 0xff #define BIT_INDEX_15(x) (((x) & BIT_MASK_INDEX_15) << BIT_SHIFT_INDEX_15) #define BITS_INDEX_15 (BIT_MASK_INDEX_15 << BIT_SHIFT_INDEX_15) #define BIT_CLEAR_INDEX_15(x) ((x) & (~BITS_INDEX_15)) #define BIT_GET_INDEX_15(x) (((x) >> BIT_SHIFT_INDEX_15) & BIT_MASK_INDEX_15) #define BIT_SET_INDEX_15(x, v) (BIT_CLEAR_INDEX_15(x) | BIT_INDEX_15(v)) #define BIT_SHIFT_INDEX_14 16 #define BIT_MASK_INDEX_14 0xff #define BIT_INDEX_14(x) (((x) & BIT_MASK_INDEX_14) << BIT_SHIFT_INDEX_14) #define BITS_INDEX_14 (BIT_MASK_INDEX_14 << BIT_SHIFT_INDEX_14) #define BIT_CLEAR_INDEX_14(x) ((x) & (~BITS_INDEX_14)) #define BIT_GET_INDEX_14(x) (((x) >> BIT_SHIFT_INDEX_14) & BIT_MASK_INDEX_14) #define BIT_SET_INDEX_14(x, v) (BIT_CLEAR_INDEX_14(x) | BIT_INDEX_14(v)) #define BIT_SHIFT_INDEX_13 8 #define BIT_MASK_INDEX_13 0xff #define BIT_INDEX_13(x) (((x) & BIT_MASK_INDEX_13) << BIT_SHIFT_INDEX_13) #define BITS_INDEX_13 (BIT_MASK_INDEX_13 << BIT_SHIFT_INDEX_13) #define BIT_CLEAR_INDEX_13(x) ((x) & (~BITS_INDEX_13)) #define BIT_GET_INDEX_13(x) (((x) >> BIT_SHIFT_INDEX_13) & BIT_MASK_INDEX_13) #define BIT_SET_INDEX_13(x, v) (BIT_CLEAR_INDEX_13(x) | BIT_INDEX_13(v)) #define BIT_SHIFT_INDEX_12 0 #define BIT_MASK_INDEX_12 0xff #define BIT_INDEX_12(x) (((x) & BIT_MASK_INDEX_12) << BIT_SHIFT_INDEX_12) #define BITS_INDEX_12 (BIT_MASK_INDEX_12 << BIT_SHIFT_INDEX_12) #define BIT_CLEAR_INDEX_12(x) ((x) & (~BITS_INDEX_12)) #define BIT_GET_INDEX_12(x) (((x) >> BIT_SHIFT_INDEX_12) & BIT_MASK_INDEX_12) #define BIT_SET_INDEX_12(x, v) (BIT_CLEAR_INDEX_12(x) | BIT_INDEX_12(v)) #define BIT_SHIFT_RA_TRY_RATE_AGG_LMT 0 #define BIT_MASK_RA_TRY_RATE_AGG_LMT 0x1f #define BIT_RA_TRY_RATE_AGG_LMT(x) \ (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT) #define BITS_RA_TRY_RATE_AGG_LMT \ (BIT_MASK_RA_TRY_RATE_AGG_LMT << BIT_SHIFT_RA_TRY_RATE_AGG_LMT) #define BIT_CLEAR_RA_TRY_RATE_AGG_LMT(x) ((x) & (~BITS_RA_TRY_RATE_AGG_LMT)) #define BIT_GET_RA_TRY_RATE_AGG_LMT(x) \ (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT) & BIT_MASK_RA_TRY_RATE_AGG_LMT) #define BIT_SET_RA_TRY_RATE_AGG_LMT(x, v) \ (BIT_CLEAR_RA_TRY_RATE_AGG_LMT(x) | BIT_RA_TRY_RATE_AGG_LMT(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_POWER_STAGE1 (Offset 0x04B4) */ #define BIT_PTA_WL_PRI_MASK_CPU_MGQ BIT(31) #define BIT_PTA_WL_PRI_MASK_BCNQ BIT(30) #define BIT_PTA_WL_PRI_MASK_HIQ BIT(29) #define BIT_PTA_WL_PRI_MASK_MGQ BIT(28) #define BIT_PTA_WL_PRI_MASK_BK BIT(27) #define BIT_PTA_WL_PRI_MASK_BE BIT(26) #define BIT_PTA_WL_PRI_MASK_VI BIT(25) #define BIT_PTA_WL_PRI_MASK_VO BIT(24) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_POWER_STAGE1 (Offset 0x04B4) */ #define BIT_SHIFT_POWER_STAGE1 0 #define BIT_MASK_POWER_STAGE1 0xffffff #define BIT_POWER_STAGE1(x) \ (((x) & BIT_MASK_POWER_STAGE1) << BIT_SHIFT_POWER_STAGE1) #define BITS_POWER_STAGE1 (BIT_MASK_POWER_STAGE1 << BIT_SHIFT_POWER_STAGE1) #define BIT_CLEAR_POWER_STAGE1(x) ((x) & (~BITS_POWER_STAGE1)) #define BIT_GET_POWER_STAGE1(x) \ (((x) >> BIT_SHIFT_POWER_STAGE1) & BIT_MASK_POWER_STAGE1) #define BIT_SET_POWER_STAGE1(x, v) \ (BIT_CLEAR_POWER_STAGE1(x) | BIT_POWER_STAGE1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ #define BIT__R_CTRL_PKT_POW_ADJ BIT(24) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ #define BIT__CTRL_PKT_POW_ADJ BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ #define BIT_SHIFT_POWER_STAGE2 0 #define BIT_MASK_POWER_STAGE2 0xffffff #define BIT_POWER_STAGE2(x) \ (((x) & BIT_MASK_POWER_STAGE2) << BIT_SHIFT_POWER_STAGE2) #define BITS_POWER_STAGE2 (BIT_MASK_POWER_STAGE2 << BIT_SHIFT_POWER_STAGE2) #define BIT_CLEAR_POWER_STAGE2(x) ((x) & (~BITS_POWER_STAGE2)) #define BIT_GET_POWER_STAGE2(x) \ (((x) >> BIT_SHIFT_POWER_STAGE2) & BIT_MASK_POWER_STAGE2) #define BIT_SET_POWER_STAGE2(x, v) \ (BIT_CLEAR_POWER_STAGE2(x) | BIT_POWER_STAGE2(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ #define BIT_SHIFT_PAD_NUM_THRES 24 #define BIT_MASK_PAD_NUM_THRES 0x3f #define BIT_PAD_NUM_THRES(x) \ (((x) & BIT_MASK_PAD_NUM_THRES) << BIT_SHIFT_PAD_NUM_THRES) #define BITS_PAD_NUM_THRES (BIT_MASK_PAD_NUM_THRES << BIT_SHIFT_PAD_NUM_THRES) #define BIT_CLEAR_PAD_NUM_THRES(x) ((x) & (~BITS_PAD_NUM_THRES)) #define BIT_GET_PAD_NUM_THRES(x) \ (((x) >> BIT_SHIFT_PAD_NUM_THRES) & BIT_MASK_PAD_NUM_THRES) #define BIT_SET_PAD_NUM_THRES(x, v) \ (BIT_CLEAR_PAD_NUM_THRES(x) | BIT_PAD_NUM_THRES(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ #define BIT_R_DMA_THIS_QUEUE_BK BIT(23) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ #define BIT_DMA_THIS_QUEUE_BK BIT(23) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ #define BIT_R_DMA_THIS_QUEUE_BE BIT(22) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ #define BIT_DMA_THIS_QUEUE_BE BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ #define BIT_R_DMA_THIS_QUEUE_VI BIT(21) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ #define BIT_DMA_THIS_QUEUE_VI BIT(21) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ #define BIT_R_DMA_THIS_QUEUE_VO BIT(20) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ #define BIT_DMA_THIS_QUEUE_VO BIT(20) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ #define BIT_SHIFT_R_TOTAL_LEN_TH 8 #define BIT_MASK_R_TOTAL_LEN_TH 0xfff #define BIT_R_TOTAL_LEN_TH(x) \ (((x) & BIT_MASK_R_TOTAL_LEN_TH) << BIT_SHIFT_R_TOTAL_LEN_TH) #define BITS_R_TOTAL_LEN_TH \ (BIT_MASK_R_TOTAL_LEN_TH << BIT_SHIFT_R_TOTAL_LEN_TH) #define BIT_CLEAR_R_TOTAL_LEN_TH(x) ((x) & (~BITS_R_TOTAL_LEN_TH)) #define BIT_GET_R_TOTAL_LEN_TH(x) \ (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH) & BIT_MASK_R_TOTAL_LEN_TH) #define BIT_SET_R_TOTAL_LEN_TH(x, v) \ (BIT_CLEAR_R_TOTAL_LEN_TH(x) | BIT_R_TOTAL_LEN_TH(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ #define BIT_SHIFT_TOTAL_LEN_TH 8 #define BIT_MASK_TOTAL_LEN_TH 0xfff #define BIT_TOTAL_LEN_TH(x) \ (((x) & BIT_MASK_TOTAL_LEN_TH) << BIT_SHIFT_TOTAL_LEN_TH) #define BITS_TOTAL_LEN_TH (BIT_MASK_TOTAL_LEN_TH << BIT_SHIFT_TOTAL_LEN_TH) #define BIT_CLEAR_TOTAL_LEN_TH(x) ((x) & (~BITS_TOTAL_LEN_TH)) #define BIT_GET_TOTAL_LEN_TH(x) \ (((x) >> BIT_SHIFT_TOTAL_LEN_TH) & BIT_MASK_TOTAL_LEN_TH) #define BIT_SET_TOTAL_LEN_TH(x, v) \ (BIT_CLEAR_TOTAL_LEN_TH(x) | BIT_TOTAL_LEN_TH(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ #define BIT_EN_NEW_EARLY BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ #define BIT_PRE_TX_CMD BIT(6) #define BIT_SHIFT_NUM_SCL_EN 4 #define BIT_MASK_NUM_SCL_EN 0x3 #define BIT_NUM_SCL_EN(x) (((x) & BIT_MASK_NUM_SCL_EN) << BIT_SHIFT_NUM_SCL_EN) #define BITS_NUM_SCL_EN (BIT_MASK_NUM_SCL_EN << BIT_SHIFT_NUM_SCL_EN) #define BIT_CLEAR_NUM_SCL_EN(x) ((x) & (~BITS_NUM_SCL_EN)) #define BIT_GET_NUM_SCL_EN(x) \ (((x) >> BIT_SHIFT_NUM_SCL_EN) & BIT_MASK_NUM_SCL_EN) #define BIT_SET_NUM_SCL_EN(x, v) (BIT_CLEAR_NUM_SCL_EN(x) | BIT_NUM_SCL_EN(v)) #define BIT_BK_EN BIT(3) #define BIT_BE_EN BIT(2) #define BIT_VI_EN BIT(1) #define BIT_VO_EN BIT(0) /* 2 REG_PKT_LIFE_TIME (Offset 0x04C0) */ #define BIT_SHIFT_PKT_LIFTIME_BEBK 16 #define BIT_MASK_PKT_LIFTIME_BEBK 0xffff #define BIT_PKT_LIFTIME_BEBK(x) \ (((x) & BIT_MASK_PKT_LIFTIME_BEBK) << BIT_SHIFT_PKT_LIFTIME_BEBK) #define BITS_PKT_LIFTIME_BEBK \ (BIT_MASK_PKT_LIFTIME_BEBK << BIT_SHIFT_PKT_LIFTIME_BEBK) #define BIT_CLEAR_PKT_LIFTIME_BEBK(x) ((x) & (~BITS_PKT_LIFTIME_BEBK)) #define BIT_GET_PKT_LIFTIME_BEBK(x) \ (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK) & BIT_MASK_PKT_LIFTIME_BEBK) #define BIT_SET_PKT_LIFTIME_BEBK(x, v) \ (BIT_CLEAR_PKT_LIFTIME_BEBK(x) | BIT_PKT_LIFTIME_BEBK(v)) #define BIT_SHIFT_PKT_LIFTIME_VOVI 0 #define BIT_MASK_PKT_LIFTIME_VOVI 0xffff #define BIT_PKT_LIFTIME_VOVI(x) \ (((x) & BIT_MASK_PKT_LIFTIME_VOVI) << BIT_SHIFT_PKT_LIFTIME_VOVI) #define BITS_PKT_LIFTIME_VOVI \ (BIT_MASK_PKT_LIFTIME_VOVI << BIT_SHIFT_PKT_LIFTIME_VOVI) #define BIT_CLEAR_PKT_LIFTIME_VOVI(x) ((x) & (~BITS_PKT_LIFTIME_VOVI)) #define BIT_GET_PKT_LIFTIME_VOVI(x) \ (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI) & BIT_MASK_PKT_LIFTIME_VOVI) #define BIT_SET_PKT_LIFTIME_VOVI(x, v) \ (BIT_CLEAR_PKT_LIFTIME_VOVI(x) | BIT_PKT_LIFTIME_VOVI(v)) /* 2 REG_STBC_SETTING (Offset 0x04C4) */ #define BIT_SHIFT_CDEND_TXTIME_L 4 #define BIT_MASK_CDEND_TXTIME_L 0xf #define BIT_CDEND_TXTIME_L(x) \ (((x) & BIT_MASK_CDEND_TXTIME_L) << BIT_SHIFT_CDEND_TXTIME_L) #define BITS_CDEND_TXTIME_L \ (BIT_MASK_CDEND_TXTIME_L << BIT_SHIFT_CDEND_TXTIME_L) #define BIT_CLEAR_CDEND_TXTIME_L(x) ((x) & (~BITS_CDEND_TXTIME_L)) #define BIT_GET_CDEND_TXTIME_L(x) \ (((x) >> BIT_SHIFT_CDEND_TXTIME_L) & BIT_MASK_CDEND_TXTIME_L) #define BIT_SET_CDEND_TXTIME_L(x, v) \ (BIT_CLEAR_CDEND_TXTIME_L(x) | BIT_CDEND_TXTIME_L(v)) #define BIT_SHIFT_NESS 2 #define BIT_MASK_NESS 0x3 #define BIT_NESS(x) (((x) & BIT_MASK_NESS) << BIT_SHIFT_NESS) #define BITS_NESS (BIT_MASK_NESS << BIT_SHIFT_NESS) #define BIT_CLEAR_NESS(x) ((x) & (~BITS_NESS)) #define BIT_GET_NESS(x) (((x) >> BIT_SHIFT_NESS) & BIT_MASK_NESS) #define BIT_SET_NESS(x, v) (BIT_CLEAR_NESS(x) | BIT_NESS(v)) #define BIT_SHIFT_STBC_CFEND 0 #define BIT_MASK_STBC_CFEND 0x3 #define BIT_STBC_CFEND(x) (((x) & BIT_MASK_STBC_CFEND) << BIT_SHIFT_STBC_CFEND) #define BITS_STBC_CFEND (BIT_MASK_STBC_CFEND << BIT_SHIFT_STBC_CFEND) #define BIT_CLEAR_STBC_CFEND(x) ((x) & (~BITS_STBC_CFEND)) #define BIT_GET_STBC_CFEND(x) \ (((x) >> BIT_SHIFT_STBC_CFEND) & BIT_MASK_STBC_CFEND) #define BIT_SET_STBC_CFEND(x, v) (BIT_CLEAR_STBC_CFEND(x) | BIT_STBC_CFEND(v)) /* 2 REG_STBC_SETTING2 (Offset 0x04C5) */ #define BIT_SHIFT_CDEND_TXTIME_H 0 #define BIT_MASK_CDEND_TXTIME_H 0x1f #define BIT_CDEND_TXTIME_H(x) \ (((x) & BIT_MASK_CDEND_TXTIME_H) << BIT_SHIFT_CDEND_TXTIME_H) #define BITS_CDEND_TXTIME_H \ (BIT_MASK_CDEND_TXTIME_H << BIT_SHIFT_CDEND_TXTIME_H) #define BIT_CLEAR_CDEND_TXTIME_H(x) ((x) & (~BITS_CDEND_TXTIME_H)) #define BIT_GET_CDEND_TXTIME_H(x) \ (((x) >> BIT_SHIFT_CDEND_TXTIME_H) & BIT_MASK_CDEND_TXTIME_H) #define BIT_SET_CDEND_TXTIME_H(x, v) \ (BIT_CLEAR_CDEND_TXTIME_H(x) | BIT_CDEND_TXTIME_H(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ #define BIT_FORCE_RND_PRI BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ #define BIT_PTA_EDCCA_EN BIT(5) #define BIT_PTA_WL_TX_EN BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ #define BIT_R_USE_DATA_BW BIT(3) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ #define BIT_USE_DATA_BW BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ #define BIT_TRI_PKT_INT_MODE1 BIT(2) #define BIT_TRI_PKT_INT_MODE0 BIT(1) #define BIT_ACQ_MODE_SEL BIT(0) /* 2 REG_SINGLE_AMPDU_CTRL (Offset 0x04C7) */ #define BIT_EN_SINGLE_APMDU BIT(7) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_PROT_MODE_CTRL (Offset 0x04C8) */ #define BIT_SND_SIFS_TXDATA BIT(31) #define BIT_TX_SND_MATCH_MACID BIT(30) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PROT_MODE_CTRL (Offset 0x04C8) */ #define BIT_SHIFT_RTS_MAX_AGG_NUM 24 #define BIT_MASK_RTS_MAX_AGG_NUM 0x3f #define BIT_RTS_MAX_AGG_NUM(x) \ (((x) & BIT_MASK_RTS_MAX_AGG_NUM) << BIT_SHIFT_RTS_MAX_AGG_NUM) #define BITS_RTS_MAX_AGG_NUM \ (BIT_MASK_RTS_MAX_AGG_NUM << BIT_SHIFT_RTS_MAX_AGG_NUM) #define BIT_CLEAR_RTS_MAX_AGG_NUM(x) ((x) & (~BITS_RTS_MAX_AGG_NUM)) #define BIT_GET_RTS_MAX_AGG_NUM(x) \ (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM) & BIT_MASK_RTS_MAX_AGG_NUM) #define BIT_SET_RTS_MAX_AGG_NUM(x, v) \ (BIT_CLEAR_RTS_MAX_AGG_NUM(x) | BIT_RTS_MAX_AGG_NUM(v)) #define BIT_SHIFT_MAX_AGG_NUM 16 #define BIT_MASK_MAX_AGG_NUM 0x3f #define BIT_MAX_AGG_NUM(x) \ (((x) & BIT_MASK_MAX_AGG_NUM) << BIT_SHIFT_MAX_AGG_NUM) #define BITS_MAX_AGG_NUM (BIT_MASK_MAX_AGG_NUM << BIT_SHIFT_MAX_AGG_NUM) #define BIT_CLEAR_MAX_AGG_NUM(x) ((x) & (~BITS_MAX_AGG_NUM)) #define BIT_GET_MAX_AGG_NUM(x) \ (((x) >> BIT_SHIFT_MAX_AGG_NUM) & BIT_MASK_MAX_AGG_NUM) #define BIT_SET_MAX_AGG_NUM(x, v) \ (BIT_CLEAR_MAX_AGG_NUM(x) | BIT_MAX_AGG_NUM(v)) #define BIT_SHIFT_RTS_TXTIME_TH 8 #define BIT_MASK_RTS_TXTIME_TH 0xff #define BIT_RTS_TXTIME_TH(x) \ (((x) & BIT_MASK_RTS_TXTIME_TH) << BIT_SHIFT_RTS_TXTIME_TH) #define BITS_RTS_TXTIME_TH (BIT_MASK_RTS_TXTIME_TH << BIT_SHIFT_RTS_TXTIME_TH) #define BIT_CLEAR_RTS_TXTIME_TH(x) ((x) & (~BITS_RTS_TXTIME_TH)) #define BIT_GET_RTS_TXTIME_TH(x) \ (((x) >> BIT_SHIFT_RTS_TXTIME_TH) & BIT_MASK_RTS_TXTIME_TH) #define BIT_SET_RTS_TXTIME_TH(x, v) \ (BIT_CLEAR_RTS_TXTIME_TH(x) | BIT_RTS_TXTIME_TH(v)) #define BIT_SHIFT_RTS_LEN_TH 0 #define BIT_MASK_RTS_LEN_TH 0xff #define BIT_RTS_LEN_TH(x) (((x) & BIT_MASK_RTS_LEN_TH) << BIT_SHIFT_RTS_LEN_TH) #define BITS_RTS_LEN_TH (BIT_MASK_RTS_LEN_TH << BIT_SHIFT_RTS_LEN_TH) #define BIT_CLEAR_RTS_LEN_TH(x) ((x) & (~BITS_RTS_LEN_TH)) #define BIT_GET_RTS_LEN_TH(x) \ (((x) >> BIT_SHIFT_RTS_LEN_TH) & BIT_MASK_RTS_LEN_TH) #define BIT_SET_RTS_LEN_TH(x, v) (BIT_CLEAR_RTS_LEN_TH(x) | BIT_RTS_LEN_TH(v)) /* 2 REG_BAR_MODE_CTRL (Offset 0x04CC) */ #define BIT_SHIFT_BAR_RTY_LMT 16 #define BIT_MASK_BAR_RTY_LMT 0x3 #define BIT_BAR_RTY_LMT(x) \ (((x) & BIT_MASK_BAR_RTY_LMT) << BIT_SHIFT_BAR_RTY_LMT) #define BITS_BAR_RTY_LMT (BIT_MASK_BAR_RTY_LMT << BIT_SHIFT_BAR_RTY_LMT) #define BIT_CLEAR_BAR_RTY_LMT(x) ((x) & (~BITS_BAR_RTY_LMT)) #define BIT_GET_BAR_RTY_LMT(x) \ (((x) >> BIT_SHIFT_BAR_RTY_LMT) & BIT_MASK_BAR_RTY_LMT) #define BIT_SET_BAR_RTY_LMT(x, v) \ (BIT_CLEAR_BAR_RTY_LMT(x) | BIT_BAR_RTY_LMT(v)) #define BIT_SHIFT_BAR_PKT_TXTIME_TH 8 #define BIT_MASK_BAR_PKT_TXTIME_TH 0xff #define BIT_BAR_PKT_TXTIME_TH(x) \ (((x) & BIT_MASK_BAR_PKT_TXTIME_TH) << BIT_SHIFT_BAR_PKT_TXTIME_TH) #define BITS_BAR_PKT_TXTIME_TH \ (BIT_MASK_BAR_PKT_TXTIME_TH << BIT_SHIFT_BAR_PKT_TXTIME_TH) #define BIT_CLEAR_BAR_PKT_TXTIME_TH(x) ((x) & (~BITS_BAR_PKT_TXTIME_TH)) #define BIT_GET_BAR_PKT_TXTIME_TH(x) \ (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH) & BIT_MASK_BAR_PKT_TXTIME_TH) #define BIT_SET_BAR_PKT_TXTIME_TH(x, v) \ (BIT_CLEAR_BAR_PKT_TXTIME_TH(x) | BIT_BAR_PKT_TXTIME_TH(v)) #define BIT_BAR_EN_V1 BIT(6) #define BIT_SHIFT_BAR_PKTNUM_TH_V1 0 #define BIT_MASK_BAR_PKTNUM_TH_V1 0x3f #define BIT_BAR_PKTNUM_TH_V1(x) \ (((x) & BIT_MASK_BAR_PKTNUM_TH_V1) << BIT_SHIFT_BAR_PKTNUM_TH_V1) #define BITS_BAR_PKTNUM_TH_V1 \ (BIT_MASK_BAR_PKTNUM_TH_V1 << BIT_SHIFT_BAR_PKTNUM_TH_V1) #define BIT_CLEAR_BAR_PKTNUM_TH_V1(x) ((x) & (~BITS_BAR_PKTNUM_TH_V1)) #define BIT_GET_BAR_PKTNUM_TH_V1(x) \ (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1) & BIT_MASK_BAR_PKTNUM_TH_V1) #define BIT_SET_BAR_PKTNUM_TH_V1(x, v) \ (BIT_CLEAR_BAR_PKTNUM_TH_V1(x) | BIT_BAR_PKTNUM_TH_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RA_TRY_RATE_AGG_LMT (Offset 0x04CF) */ #define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1 0 #define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1 0x3f #define BIT_RA_TRY_RATE_AGG_LMT_V1(x) \ (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1) \ << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) #define BITS_RA_TRY_RATE_AGG_LMT_V1 \ (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) #define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1(x) \ ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1)) #define BIT_GET_RA_TRY_RATE_AGG_LMT_V1(x) \ (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) & \ BIT_MASK_RA_TRY_RATE_AGG_LMT_V1) #define BIT_SET_RA_TRY_RATE_AGG_LMT_V1(x, v) \ (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1(x) | BIT_RA_TRY_RATE_AGG_LMT_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MACID_SLEEP_CTRL (Offset 0x04D0) */ #define BIT_SHIFT_DEBUG_PROTOCOL 24 #define BIT_MASK_DEBUG_PROTOCOL 0xff #define BIT_DEBUG_PROTOCOL(x) \ (((x) & BIT_MASK_DEBUG_PROTOCOL) << BIT_SHIFT_DEBUG_PROTOCOL) #define BITS_DEBUG_PROTOCOL \ (BIT_MASK_DEBUG_PROTOCOL << BIT_SHIFT_DEBUG_PROTOCOL) #define BIT_CLEAR_DEBUG_PROTOCOL(x) ((x) & (~BITS_DEBUG_PROTOCOL)) #define BIT_GET_DEBUG_PROTOCOL(x) \ (((x) >> BIT_SHIFT_DEBUG_PROTOCOL) & BIT_MASK_DEBUG_PROTOCOL) #define BIT_SET_DEBUG_PROTOCOL(x, v) \ (BIT_CLEAR_DEBUG_PROTOCOL(x) | BIT_DEBUG_PROTOCOL(v)) #define BIT_SHIFT_BCNQ_PGBNDY_RSEL 16 #define BIT_MASK_BCNQ_PGBNDY_RSEL 0x7 #define BIT_BCNQ_PGBNDY_RSEL(x) \ (((x) & BIT_MASK_BCNQ_PGBNDY_RSEL) << BIT_SHIFT_BCNQ_PGBNDY_RSEL) #define BITS_BCNQ_PGBNDY_RSEL \ (BIT_MASK_BCNQ_PGBNDY_RSEL << BIT_SHIFT_BCNQ_PGBNDY_RSEL) #define BIT_CLEAR_BCNQ_PGBNDY_RSEL(x) ((x) & (~BITS_BCNQ_PGBNDY_RSEL)) #define BIT_GET_BCNQ_PGBNDY_RSEL(x) \ (((x) >> BIT_SHIFT_BCNQ_PGBNDY_RSEL) & BIT_MASK_BCNQ_PGBNDY_RSEL) #define BIT_SET_BCNQ_PGBNDY_RSEL(x, v) \ (BIT_CLEAR_BCNQ_PGBNDY_RSEL(x) | BIT_BCNQ_PGBNDY_RSEL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MACID_SLEEP2 (Offset 0x04D0) */ #define BIT_SHIFT_MACID95_64PKTSLEEP 0 #define BIT_MASK_MACID95_64PKTSLEEP 0xffffffffL #define BIT_MACID95_64PKTSLEEP(x) \ (((x) & BIT_MASK_MACID95_64PKTSLEEP) << BIT_SHIFT_MACID95_64PKTSLEEP) #define BITS_MACID95_64PKTSLEEP \ (BIT_MASK_MACID95_64PKTSLEEP << BIT_SHIFT_MACID95_64PKTSLEEP) #define BIT_CLEAR_MACID95_64PKTSLEEP(x) ((x) & (~BITS_MACID95_64PKTSLEEP)) #define BIT_GET_MACID95_64PKTSLEEP(x) \ (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP) & BIT_MASK_MACID95_64PKTSLEEP) #define BIT_SET_MACID95_64PKTSLEEP(x, v) \ (BIT_CLEAR_MACID95_64PKTSLEEP(x) | BIT_MACID95_64PKTSLEEP(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MACID_SLEEP_CTRL (Offset 0x04D0) */ #define BIT_SHIFT_MACID_SLEEP_SEL 0 #define BIT_MASK_MACID_SLEEP_SEL 0x7 #define BIT_MACID_SLEEP_SEL(x) \ (((x) & BIT_MASK_MACID_SLEEP_SEL) << BIT_SHIFT_MACID_SLEEP_SEL) #define BITS_MACID_SLEEP_SEL \ (BIT_MASK_MACID_SLEEP_SEL << BIT_SHIFT_MACID_SLEEP_SEL) #define BIT_CLEAR_MACID_SLEEP_SEL(x) ((x) & (~BITS_MACID_SLEEP_SEL)) #define BIT_GET_MACID_SLEEP_SEL(x) \ (((x) >> BIT_SHIFT_MACID_SLEEP_SEL) & BIT_MASK_MACID_SLEEP_SEL) #define BIT_SET_MACID_SLEEP_SEL(x, v) \ (BIT_CLEAR_MACID_SLEEP_SEL(x) | BIT_MACID_SLEEP_SEL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MACID_SLEEP (Offset 0x04D4) */ #define BIT_SHIFT_MACID31_0_PKTSLEEP 0 #define BIT_MASK_MACID31_0_PKTSLEEP 0xffffffffL #define BIT_MACID31_0_PKTSLEEP(x) \ (((x) & BIT_MASK_MACID31_0_PKTSLEEP) << BIT_SHIFT_MACID31_0_PKTSLEEP) #define BITS_MACID31_0_PKTSLEEP \ (BIT_MASK_MACID31_0_PKTSLEEP << BIT_SHIFT_MACID31_0_PKTSLEEP) #define BIT_CLEAR_MACID31_0_PKTSLEEP(x) ((x) & (~BITS_MACID31_0_PKTSLEEP)) #define BIT_GET_MACID31_0_PKTSLEEP(x) \ (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP) & BIT_MASK_MACID31_0_PKTSLEEP) #define BIT_SET_MACID31_0_PKTSLEEP(x, v) \ (BIT_CLEAR_MACID31_0_PKTSLEEP(x) | BIT_MACID31_0_PKTSLEEP(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MACID_SLEEP_INFO (Offset 0x04D4) */ #define BIT_SHIFT_MACID_SLEEP_INFO 0 #define BIT_MASK_MACID_SLEEP_INFO 0xffffffffL #define BIT_MACID_SLEEP_INFO(x) \ (((x) & BIT_MASK_MACID_SLEEP_INFO) << BIT_SHIFT_MACID_SLEEP_INFO) #define BITS_MACID_SLEEP_INFO \ (BIT_MASK_MACID_SLEEP_INFO << BIT_SHIFT_MACID_SLEEP_INFO) #define BIT_CLEAR_MACID_SLEEP_INFO(x) ((x) & (~BITS_MACID_SLEEP_INFO)) #define BIT_GET_MACID_SLEEP_INFO(x) \ (((x) >> BIT_SHIFT_MACID_SLEEP_INFO) & BIT_MASK_MACID_SLEEP_INFO) #define BIT_SET_MACID_SLEEP_INFO(x, v) \ (BIT_CLEAR_MACID_SLEEP_INFO(x) | BIT_MACID_SLEEP_INFO(v)) #define BIT_SHIFT_PTCL_TOTAL_PG_V3 0 #define BIT_MASK_PTCL_TOTAL_PG_V3 0x1fff #define BIT_PTCL_TOTAL_PG_V3(x) \ (((x) & BIT_MASK_PTCL_TOTAL_PG_V3) << BIT_SHIFT_PTCL_TOTAL_PG_V3) #define BITS_PTCL_TOTAL_PG_V3 \ (BIT_MASK_PTCL_TOTAL_PG_V3 << BIT_SHIFT_PTCL_TOTAL_PG_V3) #define BIT_CLEAR_PTCL_TOTAL_PG_V3(x) ((x) & (~BITS_PTCL_TOTAL_PG_V3)) #define BIT_GET_PTCL_TOTAL_PG_V3(x) \ (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V3) & BIT_MASK_PTCL_TOTAL_PG_V3) #define BIT_SET_PTCL_TOTAL_PG_V3(x, v) \ (BIT_CLEAR_PTCL_TOTAL_PG_V3(x) | BIT_PTCL_TOTAL_PG_V3(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HW_SEQ0 (Offset 0x04D8) */ #define BIT_SHIFT_HW_SSN_SEQ0 0 #define BIT_MASK_HW_SSN_SEQ0 0xfff #define BIT_HW_SSN_SEQ0(x) \ (((x) & BIT_MASK_HW_SSN_SEQ0) << BIT_SHIFT_HW_SSN_SEQ0) #define BITS_HW_SSN_SEQ0 (BIT_MASK_HW_SSN_SEQ0 << BIT_SHIFT_HW_SSN_SEQ0) #define BIT_CLEAR_HW_SSN_SEQ0(x) ((x) & (~BITS_HW_SSN_SEQ0)) #define BIT_GET_HW_SSN_SEQ0(x) \ (((x) >> BIT_SHIFT_HW_SSN_SEQ0) & BIT_MASK_HW_SSN_SEQ0) #define BIT_SET_HW_SSN_SEQ0(x, v) \ (BIT_CLEAR_HW_SSN_SEQ0(x) | BIT_HW_SSN_SEQ0(v)) /* 2 REG_HW_SEQ1 (Offset 0x04DA) */ #define BIT_SHIFT_HW_SSN_SEQ1 0 #define BIT_MASK_HW_SSN_SEQ1 0xfff #define BIT_HW_SSN_SEQ1(x) \ (((x) & BIT_MASK_HW_SSN_SEQ1) << BIT_SHIFT_HW_SSN_SEQ1) #define BITS_HW_SSN_SEQ1 (BIT_MASK_HW_SSN_SEQ1 << BIT_SHIFT_HW_SSN_SEQ1) #define BIT_CLEAR_HW_SSN_SEQ1(x) ((x) & (~BITS_HW_SSN_SEQ1)) #define BIT_GET_HW_SSN_SEQ1(x) \ (((x) >> BIT_SHIFT_HW_SSN_SEQ1) & BIT_MASK_HW_SSN_SEQ1) #define BIT_SET_HW_SSN_SEQ1(x, v) \ (BIT_CLEAR_HW_SSN_SEQ1(x) | BIT_HW_SSN_SEQ1(v)) /* 2 REG_HW_SEQ2 (Offset 0x04DC) */ #define BIT_SHIFT_HW_SSN_SEQ2 0 #define BIT_MASK_HW_SSN_SEQ2 0xfff #define BIT_HW_SSN_SEQ2(x) \ (((x) & BIT_MASK_HW_SSN_SEQ2) << BIT_SHIFT_HW_SSN_SEQ2) #define BITS_HW_SSN_SEQ2 (BIT_MASK_HW_SSN_SEQ2 << BIT_SHIFT_HW_SSN_SEQ2) #define BIT_CLEAR_HW_SSN_SEQ2(x) ((x) & (~BITS_HW_SSN_SEQ2)) #define BIT_GET_HW_SSN_SEQ2(x) \ (((x) >> BIT_SHIFT_HW_SSN_SEQ2) & BIT_MASK_HW_SSN_SEQ2) #define BIT_SET_HW_SSN_SEQ2(x, v) \ (BIT_CLEAR_HW_SSN_SEQ2(x) | BIT_HW_SSN_SEQ2(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HW_SEQ3 (Offset 0x04DE) */ #define BIT_SHIFT_CSI_HWSSN_SEL 12 #define BIT_MASK_CSI_HWSSN_SEL 0x3 #define BIT_CSI_HWSSN_SEL(x) \ (((x) & BIT_MASK_CSI_HWSSN_SEL) << BIT_SHIFT_CSI_HWSSN_SEL) #define BITS_CSI_HWSSN_SEL (BIT_MASK_CSI_HWSSN_SEL << BIT_SHIFT_CSI_HWSSN_SEL) #define BIT_CLEAR_CSI_HWSSN_SEL(x) ((x) & (~BITS_CSI_HWSSN_SEL)) #define BIT_GET_CSI_HWSSN_SEL(x) \ (((x) >> BIT_SHIFT_CSI_HWSSN_SEL) & BIT_MASK_CSI_HWSSN_SEL) #define BIT_SET_CSI_HWSSN_SEL(x, v) \ (BIT_CLEAR_CSI_HWSSN_SEL(x) | BIT_CSI_HWSSN_SEL(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HW_SEQ3 (Offset 0x04DE) */ #define BIT_SHIFT_CSI_HWSEQ_SEL 12 #define BIT_MASK_CSI_HWSEQ_SEL 0x3 #define BIT_CSI_HWSEQ_SEL(x) \ (((x) & BIT_MASK_CSI_HWSEQ_SEL) << BIT_SHIFT_CSI_HWSEQ_SEL) #define BITS_CSI_HWSEQ_SEL (BIT_MASK_CSI_HWSEQ_SEL << BIT_SHIFT_CSI_HWSEQ_SEL) #define BIT_CLEAR_CSI_HWSEQ_SEL(x) ((x) & (~BITS_CSI_HWSEQ_SEL)) #define BIT_GET_CSI_HWSEQ_SEL(x) \ (((x) >> BIT_SHIFT_CSI_HWSEQ_SEL) & BIT_MASK_CSI_HWSEQ_SEL) #define BIT_SET_CSI_HWSEQ_SEL(x, v) \ (BIT_CLEAR_CSI_HWSEQ_SEL(x) | BIT_CSI_HWSEQ_SEL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HW_SEQ3 (Offset 0x04DE) */ #define BIT_SHIFT_HW_SSN_SEQ3 0 #define BIT_MASK_HW_SSN_SEQ3 0xfff #define BIT_HW_SSN_SEQ3(x) \ (((x) & BIT_MASK_HW_SSN_SEQ3) << BIT_SHIFT_HW_SSN_SEQ3) #define BITS_HW_SSN_SEQ3 (BIT_MASK_HW_SSN_SEQ3 << BIT_SHIFT_HW_SSN_SEQ3) #define BIT_CLEAR_HW_SSN_SEQ3(x) ((x) & (~BITS_HW_SSN_SEQ3)) #define BIT_GET_HW_SSN_SEQ3(x) \ (((x) >> BIT_SHIFT_HW_SSN_SEQ3) & BIT_MASK_HW_SSN_SEQ3) #define BIT_SET_HW_SSN_SEQ3(x, v) \ (BIT_CLEAR_HW_SSN_SEQ3(x) | BIT_HW_SSN_SEQ3(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_CSI_SEQ (Offset 0x04DE) */ #define BIT_SHIFT_HW_CSI_SEQ 0 #define BIT_MASK_HW_CSI_SEQ 0xfff #define BIT_HW_CSI_SEQ(x) (((x) & BIT_MASK_HW_CSI_SEQ) << BIT_SHIFT_HW_CSI_SEQ) #define BITS_HW_CSI_SEQ (BIT_MASK_HW_CSI_SEQ << BIT_SHIFT_HW_CSI_SEQ) #define BIT_CLEAR_HW_CSI_SEQ(x) ((x) & (~BITS_HW_CSI_SEQ)) #define BIT_GET_HW_CSI_SEQ(x) \ (((x) >> BIT_SHIFT_HW_CSI_SEQ) & BIT_MASK_HW_CSI_SEQ) #define BIT_SET_HW_CSI_SEQ(x, v) (BIT_CLEAR_HW_CSI_SEQ(x) | BIT_HW_CSI_SEQ(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT) /* 2 REG_NULL_PKT_STATUS_V1 (Offset 0x04E0) */ #define BIT_SHIFT_PTCL_TOTAL_PG_V1 2 #define BIT_MASK_PTCL_TOTAL_PG_V1 0x1fff #define BIT_PTCL_TOTAL_PG_V1(x) \ (((x) & BIT_MASK_PTCL_TOTAL_PG_V1) << BIT_SHIFT_PTCL_TOTAL_PG_V1) #define BITS_PTCL_TOTAL_PG_V1 \ (BIT_MASK_PTCL_TOTAL_PG_V1 << BIT_SHIFT_PTCL_TOTAL_PG_V1) #define BIT_CLEAR_PTCL_TOTAL_PG_V1(x) ((x) & (~BITS_PTCL_TOTAL_PG_V1)) #define BIT_GET_PTCL_TOTAL_PG_V1(x) \ (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V1) & BIT_MASK_PTCL_TOTAL_PG_V1) #define BIT_SET_PTCL_TOTAL_PG_V1(x, v) \ (BIT_CLEAR_PTCL_TOTAL_PG_V1(x) | BIT_PTCL_TOTAL_PG_V1(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_NULL_PKT_STATUS_V1 (Offset 0x04E0) */ #define BIT_SHIFT_PTCL_TOTAL_PG_V2 2 #define BIT_MASK_PTCL_TOTAL_PG_V2 0x3fff #define BIT_PTCL_TOTAL_PG_V2(x) \ (((x) & BIT_MASK_PTCL_TOTAL_PG_V2) << BIT_SHIFT_PTCL_TOTAL_PG_V2) #define BITS_PTCL_TOTAL_PG_V2 \ (BIT_MASK_PTCL_TOTAL_PG_V2 << BIT_SHIFT_PTCL_TOTAL_PG_V2) #define BIT_CLEAR_PTCL_TOTAL_PG_V2(x) ((x) & (~BITS_PTCL_TOTAL_PG_V2)) #define BIT_GET_PTCL_TOTAL_PG_V2(x) \ (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2) & BIT_MASK_PTCL_TOTAL_PG_V2) #define BIT_SET_PTCL_TOTAL_PG_V2(x, v) \ (BIT_CLEAR_PTCL_TOTAL_PG_V2(x) | BIT_PTCL_TOTAL_PG_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_NULL_PKT_STATUS (Offset 0x04E0) */ #define BIT_TX_NULL_1 BIT(1) #define BIT_TX_NULL_0 BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ #define BIT_MUARB_SEARCH_ERR BIT(14) #define BIT_MU_BFEN_ERR BIT(12) #define BIT_NDPA_DROPNULL_ERR BIT(11) #define BIT_NDPA_DROPPKT_ERR BIT(10) #define BIT_PTCL_PKYIN_ERR BIT(9) #define BIT_PTCL_QSELCNL_ERR BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ #define BIT_PTCL_RATE_TABLE_INVALID BIT(7) #define BIT_FTM_T2R_ERROR BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ #define BIT_PTCL_ERR0 BIT(5) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ #define BIT_TXTIMEOUT_ERR BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ #define BIT_PTCL_ERR1 BIT(4) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ #define BIT_NULLPAGE_ERR BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ #define BIT_PTCL_ERR2 BIT(3) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ #define BIT_CONTENTION_ERR BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ #define BIT_PTCL_ERR3 BIT(2) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ #define BIT_HEADNULL_ERR BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ #define BIT_PTCL_ERR4 BIT(1) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ #define BIT_OVERFLOW_ERR BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ #define BIT_PTCL_ERR5 BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ #define BIT_QUEUE_INDEX_ERR BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */ #define BIT_CLI3_TX_NULL_1 BIT(7) #define BIT_CLI3_TX_NULL_0 BIT(6) #define BIT_CLI2_TX_NULL_1 BIT(5) #define BIT_CLI2_TX_NULL_0 BIT(4) #define BIT_CLI1_TX_NULL_1 BIT(3) #define BIT_CLI1_TX_NULL_0 BIT(2) #define BIT_CLI0_TX_NULL_1 BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PTCL_PKT_NUM (Offset 0x04E3) */ #define BIT_SHIFT_PTCL_TOTAL_PG 0 #define BIT_MASK_PTCL_TOTAL_PG 0xff #define BIT_PTCL_TOTAL_PG(x) \ (((x) & BIT_MASK_PTCL_TOTAL_PG) << BIT_SHIFT_PTCL_TOTAL_PG) #define BITS_PTCL_TOTAL_PG (BIT_MASK_PTCL_TOTAL_PG << BIT_SHIFT_PTCL_TOTAL_PG) #define BIT_CLEAR_PTCL_TOTAL_PG(x) ((x) & (~BITS_PTCL_TOTAL_PG)) #define BIT_GET_PTCL_TOTAL_PG(x) \ (((x) >> BIT_SHIFT_PTCL_TOTAL_PG) & BIT_MASK_PTCL_TOTAL_PG) #define BIT_SET_PTCL_TOTAL_PG(x, v) \ (BIT_CLEAR_PTCL_TOTAL_PG(x) | BIT_PTCL_TOTAL_PG(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */ #define BIT_CLI0_TX_NULL_0 BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_TRXRPT_MISS_CNT (Offset 0x04E3) */ #define BIT_SHIFT_TRXRPT_MISS_CNT 0 #define BIT_MASK_TRXRPT_MISS_CNT 0x7 #define BIT_TRXRPT_MISS_CNT(x) \ (((x) & BIT_MASK_TRXRPT_MISS_CNT) << BIT_SHIFT_TRXRPT_MISS_CNT) #define BITS_TRXRPT_MISS_CNT \ (BIT_MASK_TRXRPT_MISS_CNT << BIT_SHIFT_TRXRPT_MISS_CNT) #define BIT_CLEAR_TRXRPT_MISS_CNT(x) ((x) & (~BITS_TRXRPT_MISS_CNT)) #define BIT_GET_TRXRPT_MISS_CNT(x) \ (((x) >> BIT_SHIFT_TRXRPT_MISS_CNT) & BIT_MASK_TRXRPT_MISS_CNT) #define BIT_SET_TRXRPT_MISS_CNT(x, v) \ (BIT_CLEAR_TRXRPT_MISS_CNT(x) | BIT_TRXRPT_MISS_CNT(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ #define BIT_MAX_PRETX_AGGR_EN BIT(19) #define BIT_SHIFT_MAX_PRETX_AGGR_TIME 8 #define BIT_MASK_MAX_PRETX_AGGR_TIME 0x7ff #define BIT_MAX_PRETX_AGGR_TIME(x) \ (((x) & BIT_MASK_MAX_PRETX_AGGR_TIME) << BIT_SHIFT_MAX_PRETX_AGGR_TIME) #define BITS_MAX_PRETX_AGGR_TIME \ (BIT_MASK_MAX_PRETX_AGGR_TIME << BIT_SHIFT_MAX_PRETX_AGGR_TIME) #define BIT_CLEAR_MAX_PRETX_AGGR_TIME(x) ((x) & (~BITS_MAX_PRETX_AGGR_TIME)) #define BIT_GET_MAX_PRETX_AGGR_TIME(x) \ (((x) >> BIT_SHIFT_MAX_PRETX_AGGR_TIME) & BIT_MASK_MAX_PRETX_AGGR_TIME) #define BIT_SET_MAX_PRETX_AGGR_TIME(x, v) \ (BIT_CLEAR_MAX_PRETX_AGGR_TIME(x) | BIT_MAX_PRETX_AGGR_TIME(v)) #define BIT_HGQ_DEL_EN BIT(7) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ #define BIT_HIQ_DROP BIT(7) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ #define BIT_MGQ_DEL_EN BIT(6) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ #define BIT_MGQ_DROP BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ #define BIT_VIDEO_JUST_DROP BIT(1) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_NULL_PKT_STATUS_V2 (Offset 0x04E4) */ #define BIT_TX_NULL_1_V1 BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ #define BIT_VIDEO_ENHANCEMENT_FUN_EN BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_NULL_PKT_STATUS_V2 (Offset 0x04E4) */ #define BIT_TX_NULL_0_V1 BIT(0) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_PRECNT_CTRL (Offset 0x04E5) */ #define BIT_EN_PRECNT BIT(11) #define BIT_DATA_FW_STS_FILTER BIT(2) #define BIT_CTRL_FW_STS_FILTER BIT(1) #define BIT_SHIFT_PRECNT_TH 0 #define BIT_MASK_PRECNT_TH 0x7ff #define BIT_PRECNT_TH(x) (((x) & BIT_MASK_PRECNT_TH) << BIT_SHIFT_PRECNT_TH) #define BITS_PRECNT_TH (BIT_MASK_PRECNT_TH << BIT_SHIFT_PRECNT_TH) #define BIT_CLEAR_PRECNT_TH(x) ((x) & (~BITS_PRECNT_TH)) #define BIT_GET_PRECNT_TH(x) (((x) >> BIT_SHIFT_PRECNT_TH) & BIT_MASK_PRECNT_TH) #define BIT_SET_PRECNT_TH(x, v) (BIT_CLEAR_PRECNT_TH(x) | BIT_PRECNT_TH(v)) #define BIT_MGNT_FW_STS_FILTER BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_NULL_PKT_STATUS_EXTEND_V1 (Offset 0x04E7) */ #define BIT_CLI3_TX_NULL_1_V1 BIT(7) #define BIT_CLI3_TX_NULL_0_V1 BIT(6) #define BIT_CLI2_TX_NULL_1_V1 BIT(5) #define BIT_CLI2_TX_NULL_0_V1 BIT(4) #define BIT_CLI1_TX_NULL_1_V1 BIT(3) #define BIT_CLI1_TX_NULL_0_V1 BIT(2) #define BIT_CLI0_TX_NULL_1_V1 BIT(1) #define BIT_CLI0_TX_NULL_0_V1 BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BT_POLLUTE_PKT_CNT (Offset 0x04E8) */ #define BIT_SHIFT_BT_POLLUTE_PKT_CNT 0 #define BIT_MASK_BT_POLLUTE_PKT_CNT 0xffff #define BIT_BT_POLLUTE_PKT_CNT(x) \ (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT) << BIT_SHIFT_BT_POLLUTE_PKT_CNT) #define BITS_BT_POLLUTE_PKT_CNT \ (BIT_MASK_BT_POLLUTE_PKT_CNT << BIT_SHIFT_BT_POLLUTE_PKT_CNT) #define BIT_CLEAR_BT_POLLUTE_PKT_CNT(x) ((x) & (~BITS_BT_POLLUTE_PKT_CNT)) #define BIT_GET_BT_POLLUTE_PKT_CNT(x) \ (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT) & BIT_MASK_BT_POLLUTE_PKT_CNT) #define BIT_SET_BT_POLLUTE_PKT_CNT(x, v) \ (BIT_CLEAR_BT_POLLUTE_PKT_CNT(x) | BIT_BT_POLLUTE_PKT_CNT(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PTCL_DBG (Offset 0x04EC) */ #define BIT_SHIFT_PTCL_DBG 0 #define BIT_MASK_PTCL_DBG 0xffffffffL #define BIT_PTCL_DBG(x) (((x) & BIT_MASK_PTCL_DBG) << BIT_SHIFT_PTCL_DBG) #define BITS_PTCL_DBG (BIT_MASK_PTCL_DBG << BIT_SHIFT_PTCL_DBG) #define BIT_CLEAR_PTCL_DBG(x) ((x) & (~BITS_PTCL_DBG)) #define BIT_GET_PTCL_DBG(x) (((x) >> BIT_SHIFT_PTCL_DBG) & BIT_MASK_PTCL_DBG) #define BIT_SET_PTCL_DBG(x, v) (BIT_CLEAR_PTCL_DBG(x) | BIT_PTCL_DBG(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_DROP_NUM (Offset 0x04EC) */ #define BIT_SHIFT_DROP_PKT_NUM 0 #define BIT_MASK_DROP_PKT_NUM 0xffff #define BIT_DROP_PKT_NUM(x) \ (((x) & BIT_MASK_DROP_PKT_NUM) << BIT_SHIFT_DROP_PKT_NUM) #define BITS_DROP_PKT_NUM (BIT_MASK_DROP_PKT_NUM << BIT_SHIFT_DROP_PKT_NUM) #define BIT_CLEAR_DROP_PKT_NUM(x) ((x) & (~BITS_DROP_PKT_NUM)) #define BIT_GET_DROP_PKT_NUM(x) \ (((x) >> BIT_SHIFT_DROP_PKT_NUM) & BIT_MASK_DROP_PKT_NUM) #define BIT_SET_DROP_PKT_NUM(x, v) \ (BIT_CLEAR_DROP_PKT_NUM(x) | BIT_DROP_PKT_NUM(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PTCL_TX_RPT (Offset 0x04F0) */ #define BIT_SHIFT_AC_TX_RPT_INFO 0 #define BIT_MASK_AC_TX_RPT_INFO 0xffffffffffffffffL #define BIT_AC_TX_RPT_INFO(x) \ (((x) & BIT_MASK_AC_TX_RPT_INFO) << BIT_SHIFT_AC_TX_RPT_INFO) #define BITS_AC_TX_RPT_INFO \ (BIT_MASK_AC_TX_RPT_INFO << BIT_SHIFT_AC_TX_RPT_INFO) #define BIT_CLEAR_AC_TX_RPT_INFO(x) ((x) & (~BITS_AC_TX_RPT_INFO)) #define BIT_GET_AC_TX_RPT_INFO(x) \ (((x) >> BIT_SHIFT_AC_TX_RPT_INFO) & BIT_MASK_AC_TX_RPT_INFO) #define BIT_SET_AC_TX_RPT_INFO(x, v) \ (BIT_CLEAR_AC_TX_RPT_INFO(x) | BIT_AC_TX_RPT_INFO(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_TXOP_EXTRA_CTRL (Offset 0x04F0) */ #define BIT_TXOP_EFFICIENCY_EN BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_BT_POLLUTE_PKTCNT (Offset 0x04F0) */ #define BIT_SHIFT_BT_POLLUTE_PKTCNT 0 #define BIT_MASK_BT_POLLUTE_PKTCNT 0xffff #define BIT_BT_POLLUTE_PKTCNT(x) \ (((x) & BIT_MASK_BT_POLLUTE_PKTCNT) << BIT_SHIFT_BT_POLLUTE_PKTCNT) #define BITS_BT_POLLUTE_PKTCNT \ (BIT_MASK_BT_POLLUTE_PKTCNT << BIT_SHIFT_BT_POLLUTE_PKTCNT) #define BIT_CLEAR_BT_POLLUTE_PKTCNT(x) ((x) & (~BITS_BT_POLLUTE_PKTCNT)) #define BIT_GET_BT_POLLUTE_PKTCNT(x) \ (((x) >> BIT_SHIFT_BT_POLLUTE_PKTCNT) & BIT_MASK_BT_POLLUTE_PKTCNT) #define BIT_SET_BT_POLLUTE_PKTCNT(x, v) \ (BIT_CLEAR_BT_POLLUTE_PKTCNT(x) | BIT_BT_POLLUTE_PKTCNT(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CPUMGQ_TIMER_CTRL2 (Offset 0x04F4) */ #define BIT_SHIFT_TRI_HEAD_ADDR 16 #define BIT_MASK_TRI_HEAD_ADDR 0xfff #define BIT_TRI_HEAD_ADDR(x) \ (((x) & BIT_MASK_TRI_HEAD_ADDR) << BIT_SHIFT_TRI_HEAD_ADDR) #define BITS_TRI_HEAD_ADDR (BIT_MASK_TRI_HEAD_ADDR << BIT_SHIFT_TRI_HEAD_ADDR) #define BIT_CLEAR_TRI_HEAD_ADDR(x) ((x) & (~BITS_TRI_HEAD_ADDR)) #define BIT_GET_TRI_HEAD_ADDR(x) \ (((x) >> BIT_SHIFT_TRI_HEAD_ADDR) & BIT_MASK_TRI_HEAD_ADDR) #define BIT_SET_TRI_HEAD_ADDR(x, v) \ (BIT_CLEAR_TRI_HEAD_ADDR(x) | BIT_TRI_HEAD_ADDR(v)) #define BIT_DROP_TH_EN BIT(8) #define BIT_SHIFT_DROP_TH 0 #define BIT_MASK_DROP_TH 0xff #define BIT_DROP_TH(x) (((x) & BIT_MASK_DROP_TH) << BIT_SHIFT_DROP_TH) #define BITS_DROP_TH (BIT_MASK_DROP_TH << BIT_SHIFT_DROP_TH) #define BIT_CLEAR_DROP_TH(x) ((x) & (~BITS_DROP_TH)) #define BIT_GET_DROP_TH(x) (((x) >> BIT_SHIFT_DROP_TH) & BIT_MASK_DROP_TH) #define BIT_SET_DROP_TH(x, v) (BIT_CLEAR_DROP_TH(x) | BIT_DROP_TH(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PTCL_DBG_OUT (Offset 0x04F8) */ #define BIT_SHIFT_PTCL_DBG_OUT 0 #define BIT_MASK_PTCL_DBG_OUT 0xffffffffL #define BIT_PTCL_DBG_OUT(x) \ (((x) & BIT_MASK_PTCL_DBG_OUT) << BIT_SHIFT_PTCL_DBG_OUT) #define BITS_PTCL_DBG_OUT (BIT_MASK_PTCL_DBG_OUT << BIT_SHIFT_PTCL_DBG_OUT) #define BIT_CLEAR_PTCL_DBG_OUT(x) ((x) & (~BITS_PTCL_DBG_OUT)) #define BIT_GET_PTCL_DBG_OUT(x) \ (((x) >> BIT_SHIFT_PTCL_DBG_OUT) & BIT_MASK_PTCL_DBG_OUT) #define BIT_SET_PTCL_DBG_OUT(x, v) \ (BIT_CLEAR_PTCL_DBG_OUT(x) | BIT_PTCL_DBG_OUT(v)) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ #define BIT_MOREDATA_CTRL2_EN BIT(19) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ #define BIT_MOREDATA_CTRL2_EN_V2 BIT(19) #endif #if (HALMAC_8192E_SUPPORT) /* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ #define BIT_MOREDATA_CTRL1_EN BIT(18) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ #define BIT_MOREDATA_CTRL1_EN_V2 BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ #define BIT_EN_BCN_TRXRPT BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ #define BIT_PKTIN_MOREDATA_REPLACE_ENABLE BIT(16) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_DUMMY_PAGE4_V1 (Offset 0x04FC) */ #define BIT_BCN_EN_EXTHWSEQ BIT(1) #define BIT_BCN_EN_HWSEQ BIT(0) #define BIT_SHIFT_R_MU_STA_GTAB_POSITION 0 #define BIT_MASK_R_MU_STA_GTAB_POSITION 0xffffffffffffffffL #define BIT_R_MU_STA_GTAB_POSITION(x) \ (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION) \ << BIT_SHIFT_R_MU_STA_GTAB_POSITION) #define BITS_R_MU_STA_GTAB_POSITION \ (BIT_MASK_R_MU_STA_GTAB_POSITION << BIT_SHIFT_R_MU_STA_GTAB_POSITION) #define BIT_CLEAR_R_MU_STA_GTAB_POSITION(x) \ ((x) & (~BITS_R_MU_STA_GTAB_POSITION)) #define BIT_GET_R_MU_STA_GTAB_POSITION(x) \ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION) & \ BIT_MASK_R_MU_STA_GTAB_POSITION) #define BIT_SET_R_MU_STA_GTAB_POSITION(x, v) \ (BIT_CLEAR_R_MU_STA_GTAB_POSITION(x) | BIT_R_MU_STA_GTAB_POSITION(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MOREDATA (Offset 0x04FE) */ #define BIT_MOREDATA_CTRL2_EN_V1 BIT(3) #define BIT_MOREDATA_CTRL1_EN_V1 BIT(2) #define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1 BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_EDCA_VO_PARAM (Offset 0x0500) */ #define BIT_SHIFT_TXOPLIMIT 16 #define BIT_MASK_TXOPLIMIT 0x7ff #define BIT_TXOPLIMIT(x) (((x) & BIT_MASK_TXOPLIMIT) << BIT_SHIFT_TXOPLIMIT) #define BITS_TXOPLIMIT (BIT_MASK_TXOPLIMIT << BIT_SHIFT_TXOPLIMIT) #define BIT_CLEAR_TXOPLIMIT(x) ((x) & (~BITS_TXOPLIMIT)) #define BIT_GET_TXOPLIMIT(x) (((x) >> BIT_SHIFT_TXOPLIMIT) & BIT_MASK_TXOPLIMIT) #define BIT_SET_TXOPLIMIT(x, v) (BIT_CLEAR_TXOPLIMIT(x) | BIT_TXOPLIMIT(v)) #define BIT_SHIFT_CW 8 #define BIT_MASK_CW 0xff #define BIT_CW(x) (((x) & BIT_MASK_CW) << BIT_SHIFT_CW) #define BITS_CW (BIT_MASK_CW << BIT_SHIFT_CW) #define BIT_CLEAR_CW(x) ((x) & (~BITS_CW)) #define BIT_GET_CW(x) (((x) >> BIT_SHIFT_CW) & BIT_MASK_CW) #define BIT_SET_CW(x, v) (BIT_CLEAR_CW(x) | BIT_CW(v)) #define BIT_SHIFT_AIFS 0 #define BIT_MASK_AIFS 0xff #define BIT_AIFS(x) (((x) & BIT_MASK_AIFS) << BIT_SHIFT_AIFS) #define BITS_AIFS (BIT_MASK_AIFS << BIT_SHIFT_AIFS) #define BIT_CLEAR_AIFS(x) ((x) & (~BITS_AIFS)) #define BIT_GET_AIFS(x) (((x) >> BIT_SHIFT_AIFS) & BIT_MASK_AIFS) #define BIT_SET_AIFS(x, v) (BIT_CLEAR_AIFS(x) | BIT_AIFS(v)) /* 2 REG_BCNTCFG (Offset 0x0510) */ #define BIT_SHIFT_BCNCW_MAX 12 #define BIT_MASK_BCNCW_MAX 0xf #define BIT_BCNCW_MAX(x) (((x) & BIT_MASK_BCNCW_MAX) << BIT_SHIFT_BCNCW_MAX) #define BITS_BCNCW_MAX (BIT_MASK_BCNCW_MAX << BIT_SHIFT_BCNCW_MAX) #define BIT_CLEAR_BCNCW_MAX(x) ((x) & (~BITS_BCNCW_MAX)) #define BIT_GET_BCNCW_MAX(x) (((x) >> BIT_SHIFT_BCNCW_MAX) & BIT_MASK_BCNCW_MAX) #define BIT_SET_BCNCW_MAX(x, v) (BIT_CLEAR_BCNCW_MAX(x) | BIT_BCNCW_MAX(v)) #define BIT_SHIFT_BCNCW_MIN 8 #define BIT_MASK_BCNCW_MIN 0xf #define BIT_BCNCW_MIN(x) (((x) & BIT_MASK_BCNCW_MIN) << BIT_SHIFT_BCNCW_MIN) #define BITS_BCNCW_MIN (BIT_MASK_BCNCW_MIN << BIT_SHIFT_BCNCW_MIN) #define BIT_CLEAR_BCNCW_MIN(x) ((x) & (~BITS_BCNCW_MIN)) #define BIT_GET_BCNCW_MIN(x) (((x) >> BIT_SHIFT_BCNCW_MIN) & BIT_MASK_BCNCW_MIN) #define BIT_SET_BCNCW_MIN(x, v) (BIT_CLEAR_BCNCW_MIN(x) | BIT_BCNCW_MIN(v)) #define BIT_SHIFT_BCNIFS 0 #define BIT_MASK_BCNIFS 0xff #define BIT_BCNIFS(x) (((x) & BIT_MASK_BCNIFS) << BIT_SHIFT_BCNIFS) #define BITS_BCNIFS (BIT_MASK_BCNIFS << BIT_SHIFT_BCNIFS) #define BIT_CLEAR_BCNIFS(x) ((x) & (~BITS_BCNIFS)) #define BIT_GET_BCNIFS(x) (((x) >> BIT_SHIFT_BCNIFS) & BIT_MASK_BCNIFS) #define BIT_SET_BCNIFS(x, v) (BIT_CLEAR_BCNIFS(x) | BIT_BCNIFS(v)) /* 2 REG_PIFS (Offset 0x0512) */ #define BIT_SHIFT_PIFS 0 #define BIT_MASK_PIFS 0xff #define BIT_PIFS(x) (((x) & BIT_MASK_PIFS) << BIT_SHIFT_PIFS) #define BITS_PIFS (BIT_MASK_PIFS << BIT_SHIFT_PIFS) #define BIT_CLEAR_PIFS(x) ((x) & (~BITS_PIFS)) #define BIT_GET_PIFS(x) (((x) >> BIT_SHIFT_PIFS) & BIT_MASK_PIFS) #define BIT_SET_PIFS(x, v) (BIT_CLEAR_PIFS(x) | BIT_PIFS(v)) /* 2 REG_RDG_PIFS (Offset 0x0513) */ #define BIT_SHIFT_RDG_PIFS 0 #define BIT_MASK_RDG_PIFS 0xff #define BIT_RDG_PIFS(x) (((x) & BIT_MASK_RDG_PIFS) << BIT_SHIFT_RDG_PIFS) #define BITS_RDG_PIFS (BIT_MASK_RDG_PIFS << BIT_SHIFT_RDG_PIFS) #define BIT_CLEAR_RDG_PIFS(x) ((x) & (~BITS_RDG_PIFS)) #define BIT_GET_RDG_PIFS(x) (((x) >> BIT_SHIFT_RDG_PIFS) & BIT_MASK_RDG_PIFS) #define BIT_SET_RDG_PIFS(x, v) (BIT_CLEAR_RDG_PIFS(x) | BIT_RDG_PIFS(v)) /* 2 REG_SIFS (Offset 0x0514) */ #define BIT_SHIFT_SIFS_OFDM_TRX 24 #define BIT_MASK_SIFS_OFDM_TRX 0xff #define BIT_SIFS_OFDM_TRX(x) \ (((x) & BIT_MASK_SIFS_OFDM_TRX) << BIT_SHIFT_SIFS_OFDM_TRX) #define BITS_SIFS_OFDM_TRX (BIT_MASK_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX) #define BIT_CLEAR_SIFS_OFDM_TRX(x) ((x) & (~BITS_SIFS_OFDM_TRX)) #define BIT_GET_SIFS_OFDM_TRX(x) \ (((x) >> BIT_SHIFT_SIFS_OFDM_TRX) & BIT_MASK_SIFS_OFDM_TRX) #define BIT_SET_SIFS_OFDM_TRX(x, v) \ (BIT_CLEAR_SIFS_OFDM_TRX(x) | BIT_SIFS_OFDM_TRX(v)) #define BIT_SHIFT_SIFS_CCK_TRX 16 #define BIT_MASK_SIFS_CCK_TRX 0xff #define BIT_SIFS_CCK_TRX(x) \ (((x) & BIT_MASK_SIFS_CCK_TRX) << BIT_SHIFT_SIFS_CCK_TRX) #define BITS_SIFS_CCK_TRX (BIT_MASK_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) #define BIT_CLEAR_SIFS_CCK_TRX(x) ((x) & (~BITS_SIFS_CCK_TRX)) #define BIT_GET_SIFS_CCK_TRX(x) \ (((x) >> BIT_SHIFT_SIFS_CCK_TRX) & BIT_MASK_SIFS_CCK_TRX) #define BIT_SET_SIFS_CCK_TRX(x, v) \ (BIT_CLEAR_SIFS_CCK_TRX(x) | BIT_SIFS_CCK_TRX(v)) #define BIT_SHIFT_SIFS_OFDM_CTX 8 #define BIT_MASK_SIFS_OFDM_CTX 0xff #define BIT_SIFS_OFDM_CTX(x) \ (((x) & BIT_MASK_SIFS_OFDM_CTX) << BIT_SHIFT_SIFS_OFDM_CTX) #define BITS_SIFS_OFDM_CTX (BIT_MASK_SIFS_OFDM_CTX << BIT_SHIFT_SIFS_OFDM_CTX) #define BIT_CLEAR_SIFS_OFDM_CTX(x) ((x) & (~BITS_SIFS_OFDM_CTX)) #define BIT_GET_SIFS_OFDM_CTX(x) \ (((x) >> BIT_SHIFT_SIFS_OFDM_CTX) & BIT_MASK_SIFS_OFDM_CTX) #define BIT_SET_SIFS_OFDM_CTX(x, v) \ (BIT_CLEAR_SIFS_OFDM_CTX(x) | BIT_SIFS_OFDM_CTX(v)) #define BIT_SHIFT_SIFS_CCK_CTX 0 #define BIT_MASK_SIFS_CCK_CTX 0xff #define BIT_SIFS_CCK_CTX(x) \ (((x) & BIT_MASK_SIFS_CCK_CTX) << BIT_SHIFT_SIFS_CCK_CTX) #define BITS_SIFS_CCK_CTX (BIT_MASK_SIFS_CCK_CTX << BIT_SHIFT_SIFS_CCK_CTX) #define BIT_CLEAR_SIFS_CCK_CTX(x) ((x) & (~BITS_SIFS_CCK_CTX)) #define BIT_GET_SIFS_CCK_CTX(x) \ (((x) >> BIT_SHIFT_SIFS_CCK_CTX) & BIT_MASK_SIFS_CCK_CTX) #define BIT_SET_SIFS_CCK_CTX(x, v) \ (BIT_CLEAR_SIFS_CCK_CTX(x) | BIT_SIFS_CCK_CTX(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TSFTR_SYN_OFFSET (Offset 0x0518) */ #define BIT_SHIFT_TSFTR_SNC_OFFSET 0 #define BIT_MASK_TSFTR_SNC_OFFSET 0xffff #define BIT_TSFTR_SNC_OFFSET(x) \ (((x) & BIT_MASK_TSFTR_SNC_OFFSET) << BIT_SHIFT_TSFTR_SNC_OFFSET) #define BITS_TSFTR_SNC_OFFSET \ (BIT_MASK_TSFTR_SNC_OFFSET << BIT_SHIFT_TSFTR_SNC_OFFSET) #define BIT_CLEAR_TSFTR_SNC_OFFSET(x) ((x) & (~BITS_TSFTR_SNC_OFFSET)) #define BIT_GET_TSFTR_SNC_OFFSET(x) \ (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET) & BIT_MASK_TSFTR_SNC_OFFSET) #define BIT_SET_TSFTR_SNC_OFFSET(x, v) \ (BIT_CLEAR_TSFTR_SNC_OFFSET(x) | BIT_TSFTR_SNC_OFFSET(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_AGGR_BREAK_TIME (Offset 0x051A) */ #define BIT_SHIFT_AGGR_BK_TIME 0 #define BIT_MASK_AGGR_BK_TIME 0xff #define BIT_AGGR_BK_TIME(x) \ (((x) & BIT_MASK_AGGR_BK_TIME) << BIT_SHIFT_AGGR_BK_TIME) #define BITS_AGGR_BK_TIME (BIT_MASK_AGGR_BK_TIME << BIT_SHIFT_AGGR_BK_TIME) #define BIT_CLEAR_AGGR_BK_TIME(x) ((x) & (~BITS_AGGR_BK_TIME)) #define BIT_GET_AGGR_BK_TIME(x) \ (((x) >> BIT_SHIFT_AGGR_BK_TIME) & BIT_MASK_AGGR_BK_TIME) #define BIT_SET_AGGR_BK_TIME(x, v) \ (BIT_CLEAR_AGGR_BK_TIME(x) | BIT_AGGR_BK_TIME(v)) /* 2 REG_SLOT (Offset 0x051B) */ #define BIT_SHIFT_SLOT 0 #define BIT_MASK_SLOT 0xff #define BIT_SLOT(x) (((x) & BIT_MASK_SLOT) << BIT_SHIFT_SLOT) #define BITS_SLOT (BIT_MASK_SLOT << BIT_SHIFT_SLOT) #define BIT_CLEAR_SLOT(x) ((x) & (~BITS_SLOT)) #define BIT_GET_SLOT(x) (((x) >> BIT_SHIFT_SLOT) & BIT_MASK_SLOT) #define BIT_SET_SLOT(x, v) (BIT_CLEAR_SLOT(x) | BIT_SLOT(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_EDCA_CPUMGQ_PARAM (Offset 0x051C) */ #define BIT_SHIFT_CW_V1 8 #define BIT_MASK_CW_V1 0xff #define BIT_CW_V1(x) (((x) & BIT_MASK_CW_V1) << BIT_SHIFT_CW_V1) #define BITS_CW_V1 (BIT_MASK_CW_V1 << BIT_SHIFT_CW_V1) #define BIT_CLEAR_CW_V1(x) ((x) & (~BITS_CW_V1)) #define BIT_GET_CW_V1(x) (((x) >> BIT_SHIFT_CW_V1) & BIT_MASK_CW_V1) #define BIT_SET_CW_V1(x, v) (BIT_CLEAR_CW_V1(x) | BIT_CW_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_NOA_ON_ERLY_TIME (Offset 0x051C) */ #define BIT_SHIFT__NOA_ON_ERLY_TIME 0 #define BIT_MASK__NOA_ON_ERLY_TIME 0xff #define BIT__NOA_ON_ERLY_TIME(x) \ (((x) & BIT_MASK__NOA_ON_ERLY_TIME) << BIT_SHIFT__NOA_ON_ERLY_TIME) #define BITS__NOA_ON_ERLY_TIME \ (BIT_MASK__NOA_ON_ERLY_TIME << BIT_SHIFT__NOA_ON_ERLY_TIME) #define BIT_CLEAR__NOA_ON_ERLY_TIME(x) ((x) & (~BITS__NOA_ON_ERLY_TIME)) #define BIT_GET__NOA_ON_ERLY_TIME(x) \ (((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME) & BIT_MASK__NOA_ON_ERLY_TIME) #define BIT_SET__NOA_ON_ERLY_TIME(x, v) \ (BIT_CLEAR__NOA_ON_ERLY_TIME(x) | BIT__NOA_ON_ERLY_TIME(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_EDCA_CPUMGQ_PARAM (Offset 0x051C) */ #define BIT_SHIFT_AIFS_V1 0 #define BIT_MASK_AIFS_V1 0xff #define BIT_AIFS_V1(x) (((x) & BIT_MASK_AIFS_V1) << BIT_SHIFT_AIFS_V1) #define BITS_AIFS_V1 (BIT_MASK_AIFS_V1 << BIT_SHIFT_AIFS_V1) #define BIT_CLEAR_AIFS_V1(x) ((x) & (~BITS_AIFS_V1)) #define BIT_GET_AIFS_V1(x) (((x) >> BIT_SHIFT_AIFS_V1) & BIT_MASK_AIFS_V1) #define BIT_SET_AIFS_V1(x, v) (BIT_CLEAR_AIFS_V1(x) | BIT_AIFS_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_NOA_OFF_ERLY_TIME (Offset 0x051D) */ #define BIT_SHIFT__NOA_OFF_ERLY_TIME 0 #define BIT_MASK__NOA_OFF_ERLY_TIME 0xff #define BIT__NOA_OFF_ERLY_TIME(x) \ (((x) & BIT_MASK__NOA_OFF_ERLY_TIME) << BIT_SHIFT__NOA_OFF_ERLY_TIME) #define BITS__NOA_OFF_ERLY_TIME \ (BIT_MASK__NOA_OFF_ERLY_TIME << BIT_SHIFT__NOA_OFF_ERLY_TIME) #define BIT_CLEAR__NOA_OFF_ERLY_TIME(x) ((x) & (~BITS__NOA_OFF_ERLY_TIME)) #define BIT_GET__NOA_OFF_ERLY_TIME(x) \ (((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME) & BIT_MASK__NOA_OFF_ERLY_TIME) #define BIT_SET__NOA_OFF_ERLY_TIME(x, v) \ (BIT_CLEAR__NOA_OFF_ERLY_TIME(x) | BIT__NOA_OFF_ERLY_TIME(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CPUMGQ_PAUSE (Offset 0x051E) */ #define BIT_MAC_STOP_CPUMGQ_V1 BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TX_PTCL_CTRL (Offset 0x0520) */ #define BIT_DIS_EDCCA BIT(15) #define BIT_DIS_CCA BIT(14) #define BIT_LSIG_TXOP_TXCMD_NAV BIT(13) #define BIT_SIFS_BK_EN BIT(12) #define BIT_SHIFT_TXQ_NAV_MSK 8 #define BIT_MASK_TXQ_NAV_MSK 0xf #define BIT_TXQ_NAV_MSK(x) \ (((x) & BIT_MASK_TXQ_NAV_MSK) << BIT_SHIFT_TXQ_NAV_MSK) #define BITS_TXQ_NAV_MSK (BIT_MASK_TXQ_NAV_MSK << BIT_SHIFT_TXQ_NAV_MSK) #define BIT_CLEAR_TXQ_NAV_MSK(x) ((x) & (~BITS_TXQ_NAV_MSK)) #define BIT_GET_TXQ_NAV_MSK(x) \ (((x) >> BIT_SHIFT_TXQ_NAV_MSK) & BIT_MASK_TXQ_NAV_MSK) #define BIT_SET_TXQ_NAV_MSK(x, v) \ (BIT_CLEAR_TXQ_NAV_MSK(x) | BIT_TXQ_NAV_MSK(v)) #define BIT_DIS_CW BIT(7) #define BIT_NAV_END_TXOP BIT(6) #define BIT_RDG_END_TXOP BIT(5) #define BIT_AC_INBCN_HOLD BIT(4) #define BIT_MGTQ_TXOP_EN BIT(3) #define BIT_MGTQ_RTSMF_EN BIT(2) #define BIT_HIQ_RTSMF_EN BIT(1) #define BIT_BCN_RTSMF_EN BIT(0) /* 2 REG_TXPAUSE (Offset 0x0522) */ #define BIT_STOP_BCN_HI_MGT BIT(7) #define BIT_MAC_STOPBCNQ BIT(6) #define BIT_MAC_STOPHIQ BIT(5) #define BIT_MAC_STOPMGQ BIT(4) #define BIT_MAC_STOPBK BIT(3) #define BIT_MAC_STOPBE BIT(2) #define BIT_MAC_STOPVI BIT(1) #define BIT_MAC_STOPVO BIT(0) /* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ #define BIT_DIS_BT_CCA BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ #define BIT_DIS_TXREQ_CLR_CPUMGQ BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ #define BIT_DIS_TXREQ_CLR_HI BIT(5) #define BIT_DIS_TXREQ_CLR_MGQ BIT(4) #define BIT_DIS_TXREQ_CLR_VO BIT(3) #define BIT_DIS_TXREQ_CLR_VI BIT(2) #define BIT_DIS_TXREQ_CLR_BE BIT(1) #define BIT_DIS_TXREQ_CLR_BK BIT(0) /* 2 REG_RD_CTRL (Offset 0x0524) */ #define BIT_EN_CLR_TXREQ_INCCA BIT(15) #define BIT_DIS_TX_OVER_BCNQ BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RD_CTRL (Offset 0x0524) */ #define BIT_EN_BCNERR_INCCCA BIT(13) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RD_CTRL (Offset 0x0524) */ #define BIT_EN_BCNERR_INCCA BIT(13) #define BIT_EN_BCNERR_INEDCCA BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RD_CTRL (Offset 0x0524) */ #define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11) #define BIT_DIS_TXOP_CFE BIT(10) #define BIT_DIS_LSIG_CFE BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RD_CTRL (Offset 0x0524) */ #define BIT_DIS_STBC_CFE BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RD_CTRL (Offset 0x0524) */ #define BIT_BKQ_RD_INIT_EN BIT(7) #define BIT_BEQ_RD_INIT_EN BIT(6) #define BIT_VIQ_RD_INIT_EN BIT(5) #define BIT_VOQ_RD_INIT_EN BIT(4) #define BIT_BKQ_RD_RESP_EN BIT(3) #define BIT_BEQ_RD_RESP_EN BIT(2) #define BIT_VIQ_RD_RESP_EN BIT(1) #define BIT_VOQ_RD_RESP_EN BIT(0) /* 2 REG_MBSSID_CTRL (Offset 0x0526) */ #define BIT_MBID_BCNQ7_EN BIT(7) #define BIT_MBID_BCNQ6_EN BIT(6) #define BIT_MBID_BCNQ5_EN BIT(5) #define BIT_MBID_BCNQ4_EN BIT(4) #define BIT_MBID_BCNQ3_EN BIT(3) #define BIT_MBID_BCNQ2_EN BIT(2) #define BIT_MBID_BCNQ1_EN BIT(1) #define BIT_MBID_BCNQ0_EN BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_P2PPS_CTRL (Offset 0x0527) */ #define BIT_P2P_CTW_ALLSTASLEEP BIT(7) #define BIT_P2P_OFF_DISTX_EN BIT(6) #define BIT_PWR_MGT_EN BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_P2PPS_CTRL (Offset 0x0527) */ #define BIT_P2P_BCN_AREA_EN BIT(4) #define BIT_P2P_CTWND_EN BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_P2PPS_CTRL (Offset 0x0527) */ #define BIT_P2P_NOA1_EN BIT(2) #define BIT_P2P_NOA0_EN BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_P2PPS_CTRL (Offset 0x0527) */ #define BIT_P2P_BCN_SEL BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ #define BIT_EN_P2P_CTWND1 BIT(23) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ #define BIT_EN_TBTT_AREA_FOR_BB BIT(23) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ #define BIT_EN_BKF_CLR_TXREQ BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ #define BIT_EN_TSFBIT32_RST_P2P BIT(21) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ #define BIT_EN_BCN_TX_BTCCA BIT(20) #define BIT_DIS_PKT_TX_ATIM BIT(19) #define BIT_DIS_BCN_DIS_CTN BIT(18) #define BIT_EN_NAVEND_RST_TXOP BIT(17) #define BIT_EN_FILTER_CCA BIT(16) #define BIT_SHIFT_CCA_FILTER_THRS 8 #define BIT_MASK_CCA_FILTER_THRS 0xff #define BIT_CCA_FILTER_THRS(x) \ (((x) & BIT_MASK_CCA_FILTER_THRS) << BIT_SHIFT_CCA_FILTER_THRS) #define BITS_CCA_FILTER_THRS \ (BIT_MASK_CCA_FILTER_THRS << BIT_SHIFT_CCA_FILTER_THRS) #define BIT_CLEAR_CCA_FILTER_THRS(x) ((x) & (~BITS_CCA_FILTER_THRS)) #define BIT_GET_CCA_FILTER_THRS(x) \ (((x) >> BIT_SHIFT_CCA_FILTER_THRS) & BIT_MASK_CCA_FILTER_THRS) #define BIT_SET_CCA_FILTER_THRS(x, v) \ (BIT_CLEAR_CCA_FILTER_THRS(x) | BIT_CCA_FILTER_THRS(v)) #define BIT_SHIFT_EDCCA_THRS 0 #define BIT_MASK_EDCCA_THRS 0xff #define BIT_EDCCA_THRS(x) (((x) & BIT_MASK_EDCCA_THRS) << BIT_SHIFT_EDCCA_THRS) #define BITS_EDCCA_THRS (BIT_MASK_EDCCA_THRS << BIT_SHIFT_EDCCA_THRS) #define BIT_CLEAR_EDCCA_THRS(x) ((x) & (~BITS_EDCCA_THRS)) #define BIT_GET_EDCCA_THRS(x) \ (((x) >> BIT_SHIFT_EDCCA_THRS) & BIT_MASK_EDCCA_THRS) #define BIT_SET_EDCCA_THRS(x, v) (BIT_CLEAR_EDCCA_THRS(x) | BIT_EDCCA_THRS(v)) /* 2 REG_P2PPS_SPEC_STATE (Offset 0x052B) */ #define BIT_SPEC_POWER_STATE BIT(7) #define BIT_SPEC_CTWINDOW_ON BIT(6) #define BIT_SPEC_BEACON_AREA_ON BIT(5) #define BIT_SPEC_CTWIN_EARLY_DISTX BIT(4) #define BIT_SPEC_NOA1_OFF_PERIOD BIT(3) #define BIT_SPEC_FORCE_DOZE1 BIT(2) #define BIT_SPEC_NOA0_OFF_PERIOD BIT(1) #define BIT_SPEC_FORCE_DOZE0 BIT(0) #define BIT_SHIFT_TBTT_PROHIBIT_SETUP 0 #define BIT_MASK_TBTT_PROHIBIT_SETUP 0xf #define BIT_TBTT_PROHIBIT_SETUP(x) \ (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP) << BIT_SHIFT_TBTT_PROHIBIT_SETUP) #define BITS_TBTT_PROHIBIT_SETUP \ (BIT_MASK_TBTT_PROHIBIT_SETUP << BIT_SHIFT_TBTT_PROHIBIT_SETUP) #define BIT_CLEAR_TBTT_PROHIBIT_SETUP(x) ((x) & (~BITS_TBTT_PROHIBIT_SETUP)) #define BIT_GET_TBTT_PROHIBIT_SETUP(x) \ (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP) & BIT_MASK_TBTT_PROHIBIT_SETUP) #define BIT_SET_TBTT_PROHIBIT_SETUP(x, v) \ (BIT_CLEAR_TBTT_PROHIBIT_SETUP(x) | BIT_TBTT_PROHIBIT_SETUP(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXOP_LIMIT_CTRL (Offset 0x052C) */ #define BIT_SHIFT_TXOP_TBTT_CNT 24 #define BIT_MASK_TXOP_TBTT_CNT 0xff #define BIT_TXOP_TBTT_CNT(x) \ (((x) & BIT_MASK_TXOP_TBTT_CNT) << BIT_SHIFT_TXOP_TBTT_CNT) #define BITS_TXOP_TBTT_CNT (BIT_MASK_TXOP_TBTT_CNT << BIT_SHIFT_TXOP_TBTT_CNT) #define BIT_CLEAR_TXOP_TBTT_CNT(x) ((x) & (~BITS_TXOP_TBTT_CNT)) #define BIT_GET_TXOP_TBTT_CNT(x) \ (((x) >> BIT_SHIFT_TXOP_TBTT_CNT) & BIT_MASK_TXOP_TBTT_CNT) #define BIT_SET_TXOP_TBTT_CNT(x, v) \ (BIT_CLEAR_TXOP_TBTT_CNT(x) | BIT_TXOP_TBTT_CNT(v)) #define BIT_SHIFT_TXOP_TBTT_CNT_SEL 20 #define BIT_MASK_TXOP_TBTT_CNT_SEL 0xf #define BIT_TXOP_TBTT_CNT_SEL(x) \ (((x) & BIT_MASK_TXOP_TBTT_CNT_SEL) << BIT_SHIFT_TXOP_TBTT_CNT_SEL) #define BITS_TXOP_TBTT_CNT_SEL \ (BIT_MASK_TXOP_TBTT_CNT_SEL << BIT_SHIFT_TXOP_TBTT_CNT_SEL) #define BIT_CLEAR_TXOP_TBTT_CNT_SEL(x) ((x) & (~BITS_TXOP_TBTT_CNT_SEL)) #define BIT_GET_TXOP_TBTT_CNT_SEL(x) \ (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL) & BIT_MASK_TXOP_TBTT_CNT_SEL) #define BIT_SET_TXOP_TBTT_CNT_SEL(x, v) \ (BIT_CLEAR_TXOP_TBTT_CNT_SEL(x) | BIT_TXOP_TBTT_CNT_SEL(v)) #define BIT_SHIFT_TXOP_LMT_EN 16 #define BIT_MASK_TXOP_LMT_EN 0xf #define BIT_TXOP_LMT_EN(x) \ (((x) & BIT_MASK_TXOP_LMT_EN) << BIT_SHIFT_TXOP_LMT_EN) #define BITS_TXOP_LMT_EN (BIT_MASK_TXOP_LMT_EN << BIT_SHIFT_TXOP_LMT_EN) #define BIT_CLEAR_TXOP_LMT_EN(x) ((x) & (~BITS_TXOP_LMT_EN)) #define BIT_GET_TXOP_LMT_EN(x) \ (((x) >> BIT_SHIFT_TXOP_LMT_EN) & BIT_MASK_TXOP_LMT_EN) #define BIT_SET_TXOP_LMT_EN(x, v) \ (BIT_CLEAR_TXOP_LMT_EN(x) | BIT_TXOP_LMT_EN(v)) #define BIT_SHIFT_TXOP_LMT_TX_TIME 8 #define BIT_MASK_TXOP_LMT_TX_TIME 0xff #define BIT_TXOP_LMT_TX_TIME(x) \ (((x) & BIT_MASK_TXOP_LMT_TX_TIME) << BIT_SHIFT_TXOP_LMT_TX_TIME) #define BITS_TXOP_LMT_TX_TIME \ (BIT_MASK_TXOP_LMT_TX_TIME << BIT_SHIFT_TXOP_LMT_TX_TIME) #define BIT_CLEAR_TXOP_LMT_TX_TIME(x) ((x) & (~BITS_TXOP_LMT_TX_TIME)) #define BIT_GET_TXOP_LMT_TX_TIME(x) \ (((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME) & BIT_MASK_TXOP_LMT_TX_TIME) #define BIT_SET_TXOP_LMT_TX_TIME(x, v) \ (BIT_CLEAR_TXOP_LMT_TX_TIME(x) | BIT_TXOP_LMT_TX_TIME(v)) #define BIT_TXOP_CNT_TRIGGER_RESET BIT(7) #define BIT_SHIFT_TXOP_LMT_PKT_NUM 0 #define BIT_MASK_TXOP_LMT_PKT_NUM 0x3f #define BIT_TXOP_LMT_PKT_NUM(x) \ (((x) & BIT_MASK_TXOP_LMT_PKT_NUM) << BIT_SHIFT_TXOP_LMT_PKT_NUM) #define BITS_TXOP_LMT_PKT_NUM \ (BIT_MASK_TXOP_LMT_PKT_NUM << BIT_SHIFT_TXOP_LMT_PKT_NUM) #define BIT_CLEAR_TXOP_LMT_PKT_NUM(x) ((x) & (~BITS_TXOP_LMT_PKT_NUM)) #define BIT_GET_TXOP_LMT_PKT_NUM(x) \ (((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM) & BIT_MASK_TXOP_LMT_PKT_NUM) #define BIT_SET_TXOP_LMT_PKT_NUM(x, v) \ (BIT_CLEAR_TXOP_LMT_PKT_NUM(x) | BIT_TXOP_LMT_PKT_NUM(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_P2PON_DIS_TXTIME (Offset 0x0531) */ #define BIT_SHIFT_P2PON_DIS_TXTIME 0 #define BIT_MASK_P2PON_DIS_TXTIME 0xff #define BIT_P2PON_DIS_TXTIME(x) \ (((x) & BIT_MASK_P2PON_DIS_TXTIME) << BIT_SHIFT_P2PON_DIS_TXTIME) #define BITS_P2PON_DIS_TXTIME \ (BIT_MASK_P2PON_DIS_TXTIME << BIT_SHIFT_P2PON_DIS_TXTIME) #define BIT_CLEAR_P2PON_DIS_TXTIME(x) ((x) & (~BITS_P2PON_DIS_TXTIME)) #define BIT_GET_P2PON_DIS_TXTIME(x) \ (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME) & BIT_MASK_P2PON_DIS_TXTIME) #define BIT_SET_P2PON_DIS_TXTIME(x, v) \ (BIT_CLEAR_P2PON_DIS_TXTIME(x) | BIT_P2PON_DIS_TXTIME(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CCA_TXEN_CNT (Offset 0x0534) */ #define BIT_CCA_TXEN_CNT_SWITCH BIT(17) #define BIT_CCA_TXEN_CNT_EN BIT(16) #define BIT_SHIFT_CCA_TXEN_BIG_CNT 8 #define BIT_MASK_CCA_TXEN_BIG_CNT 0xff #define BIT_CCA_TXEN_BIG_CNT(x) \ (((x) & BIT_MASK_CCA_TXEN_BIG_CNT) << BIT_SHIFT_CCA_TXEN_BIG_CNT) #define BITS_CCA_TXEN_BIG_CNT \ (BIT_MASK_CCA_TXEN_BIG_CNT << BIT_SHIFT_CCA_TXEN_BIG_CNT) #define BIT_CLEAR_CCA_TXEN_BIG_CNT(x) ((x) & (~BITS_CCA_TXEN_BIG_CNT)) #define BIT_GET_CCA_TXEN_BIG_CNT(x) \ (((x) >> BIT_SHIFT_CCA_TXEN_BIG_CNT) & BIT_MASK_CCA_TXEN_BIG_CNT) #define BIT_SET_CCA_TXEN_BIG_CNT(x, v) \ (BIT_CLEAR_CCA_TXEN_BIG_CNT(x) | BIT_CCA_TXEN_BIG_CNT(v)) #define BIT_SHIFT_CCA_TXEN_SMALL_CNT 0 #define BIT_MASK_CCA_TXEN_SMALL_CNT 0xff #define BIT_CCA_TXEN_SMALL_CNT(x) \ (((x) & BIT_MASK_CCA_TXEN_SMALL_CNT) << BIT_SHIFT_CCA_TXEN_SMALL_CNT) #define BITS_CCA_TXEN_SMALL_CNT \ (BIT_MASK_CCA_TXEN_SMALL_CNT << BIT_SHIFT_CCA_TXEN_SMALL_CNT) #define BIT_CLEAR_CCA_TXEN_SMALL_CNT(x) ((x) & (~BITS_CCA_TXEN_SMALL_CNT)) #define BIT_GET_CCA_TXEN_SMALL_CNT(x) \ (((x) >> BIT_SHIFT_CCA_TXEN_SMALL_CNT) & BIT_MASK_CCA_TXEN_SMALL_CNT) #define BIT_SET_CCA_TXEN_SMALL_CNT(x, v) \ (BIT_CLEAR_CCA_TXEN_SMALL_CNT(x) | BIT_CCA_TXEN_SMALL_CNT(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */ #define BIT_SHIFT_BK_QUEUE_THR 24 #define BIT_MASK_BK_QUEUE_THR 0xff #define BIT_BK_QUEUE_THR(x) \ (((x) & BIT_MASK_BK_QUEUE_THR) << BIT_SHIFT_BK_QUEUE_THR) #define BITS_BK_QUEUE_THR (BIT_MASK_BK_QUEUE_THR << BIT_SHIFT_BK_QUEUE_THR) #define BIT_CLEAR_BK_QUEUE_THR(x) ((x) & (~BITS_BK_QUEUE_THR)) #define BIT_GET_BK_QUEUE_THR(x) \ (((x) >> BIT_SHIFT_BK_QUEUE_THR) & BIT_MASK_BK_QUEUE_THR) #define BIT_SET_BK_QUEUE_THR(x, v) \ (BIT_CLEAR_BK_QUEUE_THR(x) | BIT_BK_QUEUE_THR(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MAX_INTER_COLLISION (Offset 0x0538) */ #define BIT_SHIFT_MAX_INTER_COLLISION_BK 24 #define BIT_MASK_MAX_INTER_COLLISION_BK 0xff #define BIT_MAX_INTER_COLLISION_BK(x) \ (((x) & BIT_MASK_MAX_INTER_COLLISION_BK) \ << BIT_SHIFT_MAX_INTER_COLLISION_BK) #define BITS_MAX_INTER_COLLISION_BK \ (BIT_MASK_MAX_INTER_COLLISION_BK << BIT_SHIFT_MAX_INTER_COLLISION_BK) #define BIT_CLEAR_MAX_INTER_COLLISION_BK(x) \ ((x) & (~BITS_MAX_INTER_COLLISION_BK)) #define BIT_GET_MAX_INTER_COLLISION_BK(x) \ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BK) & \ BIT_MASK_MAX_INTER_COLLISION_BK) #define BIT_SET_MAX_INTER_COLLISION_BK(x, v) \ (BIT_CLEAR_MAX_INTER_COLLISION_BK(x) | BIT_MAX_INTER_COLLISION_BK(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */ #define BIT_SHIFT_BE_QUEUE_THR 16 #define BIT_MASK_BE_QUEUE_THR 0xff #define BIT_BE_QUEUE_THR(x) \ (((x) & BIT_MASK_BE_QUEUE_THR) << BIT_SHIFT_BE_QUEUE_THR) #define BITS_BE_QUEUE_THR (BIT_MASK_BE_QUEUE_THR << BIT_SHIFT_BE_QUEUE_THR) #define BIT_CLEAR_BE_QUEUE_THR(x) ((x) & (~BITS_BE_QUEUE_THR)) #define BIT_GET_BE_QUEUE_THR(x) \ (((x) >> BIT_SHIFT_BE_QUEUE_THR) & BIT_MASK_BE_QUEUE_THR) #define BIT_SET_BE_QUEUE_THR(x, v) \ (BIT_CLEAR_BE_QUEUE_THR(x) | BIT_BE_QUEUE_THR(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MAX_INTER_COLLISION (Offset 0x0538) */ #define BIT_SHIFT_MAX_INTER_COLLISION_BE 16 #define BIT_MASK_MAX_INTER_COLLISION_BE 0xff #define BIT_MAX_INTER_COLLISION_BE(x) \ (((x) & BIT_MASK_MAX_INTER_COLLISION_BE) \ << BIT_SHIFT_MAX_INTER_COLLISION_BE) #define BITS_MAX_INTER_COLLISION_BE \ (BIT_MASK_MAX_INTER_COLLISION_BE << BIT_SHIFT_MAX_INTER_COLLISION_BE) #define BIT_CLEAR_MAX_INTER_COLLISION_BE(x) \ ((x) & (~BITS_MAX_INTER_COLLISION_BE)) #define BIT_GET_MAX_INTER_COLLISION_BE(x) \ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BE) & \ BIT_MASK_MAX_INTER_COLLISION_BE) #define BIT_SET_MAX_INTER_COLLISION_BE(x, v) \ (BIT_CLEAR_MAX_INTER_COLLISION_BE(x) | BIT_MAX_INTER_COLLISION_BE(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */ #define BIT_SHIFT_VI_QUEUE_THR 8 #define BIT_MASK_VI_QUEUE_THR 0xff #define BIT_VI_QUEUE_THR(x) \ (((x) & BIT_MASK_VI_QUEUE_THR) << BIT_SHIFT_VI_QUEUE_THR) #define BITS_VI_QUEUE_THR (BIT_MASK_VI_QUEUE_THR << BIT_SHIFT_VI_QUEUE_THR) #define BIT_CLEAR_VI_QUEUE_THR(x) ((x) & (~BITS_VI_QUEUE_THR)) #define BIT_GET_VI_QUEUE_THR(x) \ (((x) >> BIT_SHIFT_VI_QUEUE_THR) & BIT_MASK_VI_QUEUE_THR) #define BIT_SET_VI_QUEUE_THR(x, v) \ (BIT_CLEAR_VI_QUEUE_THR(x) | BIT_VI_QUEUE_THR(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MAX_INTER_COLLISION (Offset 0x0538) */ #define BIT_SHIFT_MAX_INTER_COLLISION_VI 8 #define BIT_MASK_MAX_INTER_COLLISION_VI 0xff #define BIT_MAX_INTER_COLLISION_VI(x) \ (((x) & BIT_MASK_MAX_INTER_COLLISION_VI) \ << BIT_SHIFT_MAX_INTER_COLLISION_VI) #define BITS_MAX_INTER_COLLISION_VI \ (BIT_MASK_MAX_INTER_COLLISION_VI << BIT_SHIFT_MAX_INTER_COLLISION_VI) #define BIT_CLEAR_MAX_INTER_COLLISION_VI(x) \ ((x) & (~BITS_MAX_INTER_COLLISION_VI)) #define BIT_GET_MAX_INTER_COLLISION_VI(x) \ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VI) & \ BIT_MASK_MAX_INTER_COLLISION_VI) #define BIT_SET_MAX_INTER_COLLISION_VI(x, v) \ (BIT_CLEAR_MAX_INTER_COLLISION_VI(x) | BIT_MAX_INTER_COLLISION_VI(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */ #define BIT_SHIFT_VO_QUEUE_THR 0 #define BIT_MASK_VO_QUEUE_THR 0xff #define BIT_VO_QUEUE_THR(x) \ (((x) & BIT_MASK_VO_QUEUE_THR) << BIT_SHIFT_VO_QUEUE_THR) #define BITS_VO_QUEUE_THR (BIT_MASK_VO_QUEUE_THR << BIT_SHIFT_VO_QUEUE_THR) #define BIT_CLEAR_VO_QUEUE_THR(x) ((x) & (~BITS_VO_QUEUE_THR)) #define BIT_GET_VO_QUEUE_THR(x) \ (((x) >> BIT_SHIFT_VO_QUEUE_THR) & BIT_MASK_VO_QUEUE_THR) #define BIT_SET_VO_QUEUE_THR(x, v) \ (BIT_CLEAR_VO_QUEUE_THR(x) | BIT_VO_QUEUE_THR(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MAX_INTER_COLLISION (Offset 0x0538) */ #define BIT_SHIFT_MAX_INTER_COLLISION_VO 0 #define BIT_MASK_MAX_INTER_COLLISION_VO 0xff #define BIT_MAX_INTER_COLLISION_VO(x) \ (((x) & BIT_MASK_MAX_INTER_COLLISION_VO) \ << BIT_SHIFT_MAX_INTER_COLLISION_VO) #define BITS_MAX_INTER_COLLISION_VO \ (BIT_MASK_MAX_INTER_COLLISION_VO << BIT_SHIFT_MAX_INTER_COLLISION_VO) #define BIT_CLEAR_MAX_INTER_COLLISION_VO(x) \ ((x) & (~BITS_MAX_INTER_COLLISION_VO)) #define BIT_GET_MAX_INTER_COLLISION_VO(x) \ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VO) & \ BIT_MASK_MAX_INTER_COLLISION_VO) #define BIT_SET_MAX_INTER_COLLISION_VO(x, v) \ (BIT_CLEAR_MAX_INTER_COLLISION_VO(x) | BIT_MAX_INTER_COLLISION_VO(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ #define BIT_QUEUE_INCOL_EN BIT(16) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */ #define BIT_MAX_INTER_COLLISION_EN BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ #define BIT_SHIFT_BK_TRIGGER_NUM_V1 12 #define BIT_MASK_BK_TRIGGER_NUM_V1 0xf #define BIT_BK_TRIGGER_NUM_V1(x) \ (((x) & BIT_MASK_BK_TRIGGER_NUM_V1) << BIT_SHIFT_BK_TRIGGER_NUM_V1) #define BITS_BK_TRIGGER_NUM_V1 \ (BIT_MASK_BK_TRIGGER_NUM_V1 << BIT_SHIFT_BK_TRIGGER_NUM_V1) #define BIT_CLEAR_BK_TRIGGER_NUM_V1(x) ((x) & (~BITS_BK_TRIGGER_NUM_V1)) #define BIT_GET_BK_TRIGGER_NUM_V1(x) \ (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_V1) & BIT_MASK_BK_TRIGGER_NUM_V1) #define BIT_SET_BK_TRIGGER_NUM_V1(x, v) \ (BIT_CLEAR_BK_TRIGGER_NUM_V1(x) | BIT_BK_TRIGGER_NUM_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */ #define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK 12 #define BIT_MASK_MAX_INTER_COLLISION_CNT_BK 0xf #define BIT_MAX_INTER_COLLISION_CNT_BK(x) \ (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BK) \ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK) #define BITS_MAX_INTER_COLLISION_CNT_BK \ (BIT_MASK_MAX_INTER_COLLISION_CNT_BK \ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK) #define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK(x) \ ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BK)) #define BIT_GET_MAX_INTER_COLLISION_CNT_BK(x) \ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK) & \ BIT_MASK_MAX_INTER_COLLISION_CNT_BK) #define BIT_SET_MAX_INTER_COLLISION_CNT_BK(x, v) \ (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK(x) | \ BIT_MAX_INTER_COLLISION_CNT_BK(v)) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ #define BIT_SHIFT_BE_TRIGGER_NUM 12 #define BIT_MASK_BE_TRIGGER_NUM 0xf #define BIT_BE_TRIGGER_NUM(x) \ (((x) & BIT_MASK_BE_TRIGGER_NUM) << BIT_SHIFT_BE_TRIGGER_NUM) #define BITS_BE_TRIGGER_NUM \ (BIT_MASK_BE_TRIGGER_NUM << BIT_SHIFT_BE_TRIGGER_NUM) #define BIT_CLEAR_BE_TRIGGER_NUM(x) ((x) & (~BITS_BE_TRIGGER_NUM)) #define BIT_GET_BE_TRIGGER_NUM(x) \ (((x) >> BIT_SHIFT_BE_TRIGGER_NUM) & BIT_MASK_BE_TRIGGER_NUM) #define BIT_SET_BE_TRIGGER_NUM(x, v) \ (BIT_CLEAR_BE_TRIGGER_NUM(x) | BIT_BE_TRIGGER_NUM(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ #define BIT_SHIFT_BE_TRIGGER_NUM_V1 8 #define BIT_MASK_BE_TRIGGER_NUM_V1 0xf #define BIT_BE_TRIGGER_NUM_V1(x) \ (((x) & BIT_MASK_BE_TRIGGER_NUM_V1) << BIT_SHIFT_BE_TRIGGER_NUM_V1) #define BITS_BE_TRIGGER_NUM_V1 \ (BIT_MASK_BE_TRIGGER_NUM_V1 << BIT_SHIFT_BE_TRIGGER_NUM_V1) #define BIT_CLEAR_BE_TRIGGER_NUM_V1(x) ((x) & (~BITS_BE_TRIGGER_NUM_V1)) #define BIT_GET_BE_TRIGGER_NUM_V1(x) \ (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_V1) & BIT_MASK_BE_TRIGGER_NUM_V1) #define BIT_SET_BE_TRIGGER_NUM_V1(x, v) \ (BIT_CLEAR_BE_TRIGGER_NUM_V1(x) | BIT_BE_TRIGGER_NUM_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */ #define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE 8 #define BIT_MASK_MAX_INTER_COLLISION_CNT_BE 0xf #define BIT_MAX_INTER_COLLISION_CNT_BE(x) \ (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BE) \ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE) #define BITS_MAX_INTER_COLLISION_CNT_BE \ (BIT_MASK_MAX_INTER_COLLISION_CNT_BE \ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE) #define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE(x) \ ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BE)) #define BIT_GET_MAX_INTER_COLLISION_CNT_BE(x) \ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE) & \ BIT_MASK_MAX_INTER_COLLISION_CNT_BE) #define BIT_SET_MAX_INTER_COLLISION_CNT_BE(x, v) \ (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE(x) | \ BIT_MAX_INTER_COLLISION_CNT_BE(v)) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ #define BIT_SHIFT_BK_TRIGGER_NUM 8 #define BIT_MASK_BK_TRIGGER_NUM 0xf #define BIT_BK_TRIGGER_NUM(x) \ (((x) & BIT_MASK_BK_TRIGGER_NUM) << BIT_SHIFT_BK_TRIGGER_NUM) #define BITS_BK_TRIGGER_NUM \ (BIT_MASK_BK_TRIGGER_NUM << BIT_SHIFT_BK_TRIGGER_NUM) #define BIT_CLEAR_BK_TRIGGER_NUM(x) ((x) & (~BITS_BK_TRIGGER_NUM)) #define BIT_GET_BK_TRIGGER_NUM(x) \ (((x) >> BIT_SHIFT_BK_TRIGGER_NUM) & BIT_MASK_BK_TRIGGER_NUM) #define BIT_SET_BK_TRIGGER_NUM(x, v) \ (BIT_CLEAR_BK_TRIGGER_NUM(x) | BIT_BK_TRIGGER_NUM(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ #define BIT_SHIFT_VI_TRIGGER_NUM 4 #define BIT_MASK_VI_TRIGGER_NUM 0xf #define BIT_VI_TRIGGER_NUM(x) \ (((x) & BIT_MASK_VI_TRIGGER_NUM) << BIT_SHIFT_VI_TRIGGER_NUM) #define BITS_VI_TRIGGER_NUM \ (BIT_MASK_VI_TRIGGER_NUM << BIT_SHIFT_VI_TRIGGER_NUM) #define BIT_CLEAR_VI_TRIGGER_NUM(x) ((x) & (~BITS_VI_TRIGGER_NUM)) #define BIT_GET_VI_TRIGGER_NUM(x) \ (((x) >> BIT_SHIFT_VI_TRIGGER_NUM) & BIT_MASK_VI_TRIGGER_NUM) #define BIT_SET_VI_TRIGGER_NUM(x, v) \ (BIT_CLEAR_VI_TRIGGER_NUM(x) | BIT_VI_TRIGGER_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */ #define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI 4 #define BIT_MASK_MAX_INTER_COLLISION_CNT_VI 0xf #define BIT_MAX_INTER_COLLISION_CNT_VI(x) \ (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VI) \ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI) #define BITS_MAX_INTER_COLLISION_CNT_VI \ (BIT_MASK_MAX_INTER_COLLISION_CNT_VI \ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI) #define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI(x) \ ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VI)) #define BIT_GET_MAX_INTER_COLLISION_CNT_VI(x) \ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI) & \ BIT_MASK_MAX_INTER_COLLISION_CNT_VI) #define BIT_SET_MAX_INTER_COLLISION_CNT_VI(x, v) \ (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI(x) | \ BIT_MAX_INTER_COLLISION_CNT_VI(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ #define BIT_SHIFT_VO_TRIGGER_NUM 0 #define BIT_MASK_VO_TRIGGER_NUM 0xf #define BIT_VO_TRIGGER_NUM(x) \ (((x) & BIT_MASK_VO_TRIGGER_NUM) << BIT_SHIFT_VO_TRIGGER_NUM) #define BITS_VO_TRIGGER_NUM \ (BIT_MASK_VO_TRIGGER_NUM << BIT_SHIFT_VO_TRIGGER_NUM) #define BIT_CLEAR_VO_TRIGGER_NUM(x) ((x) & (~BITS_VO_TRIGGER_NUM)) #define BIT_GET_VO_TRIGGER_NUM(x) \ (((x) >> BIT_SHIFT_VO_TRIGGER_NUM) & BIT_MASK_VO_TRIGGER_NUM) #define BIT_SET_VO_TRIGGER_NUM(x, v) \ (BIT_CLEAR_VO_TRIGGER_NUM(x) | BIT_VO_TRIGGER_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */ #define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO 0 #define BIT_MASK_MAX_INTER_COLLISION_CNT_VO 0xf #define BIT_MAX_INTER_COLLISION_CNT_VO(x) \ (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VO) \ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO) #define BITS_MAX_INTER_COLLISION_CNT_VO \ (BIT_MASK_MAX_INTER_COLLISION_CNT_VO \ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO) #define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO(x) \ ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VO)) #define BIT_GET_MAX_INTER_COLLISION_CNT_VO(x) \ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO) & \ BIT_MASK_MAX_INTER_COLLISION_CNT_VO) #define BIT_SET_MAX_INTER_COLLISION_CNT_VO(x, v) \ (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO(x) | \ BIT_MAX_INTER_COLLISION_CNT_VO(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */ #define BIT_SHIFT_TBTT_HOLD_TIME_AP 8 #define BIT_MASK_TBTT_HOLD_TIME_AP 0xfff #define BIT_TBTT_HOLD_TIME_AP(x) \ (((x) & BIT_MASK_TBTT_HOLD_TIME_AP) << BIT_SHIFT_TBTT_HOLD_TIME_AP) #define BITS_TBTT_HOLD_TIME_AP \ (BIT_MASK_TBTT_HOLD_TIME_AP << BIT_SHIFT_TBTT_HOLD_TIME_AP) #define BIT_CLEAR_TBTT_HOLD_TIME_AP(x) ((x) & (~BITS_TBTT_HOLD_TIME_AP)) #define BIT_GET_TBTT_HOLD_TIME_AP(x) \ (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP) & BIT_MASK_TBTT_HOLD_TIME_AP) #define BIT_SET_TBTT_HOLD_TIME_AP(x, v) \ (BIT_CLEAR_TBTT_HOLD_TIME_AP(x) | BIT_TBTT_HOLD_TIME_AP(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */ #define BIT_SHIFT_TBTT_HOLD_TIME_INFRA 4 #define BIT_MASK_TBTT_HOLD_TIME_INFRA 0xf #define BIT_TBTT_HOLD_TIME_INFRA(x) \ (((x) & BIT_MASK_TBTT_HOLD_TIME_INFRA) \ << BIT_SHIFT_TBTT_HOLD_TIME_INFRA) #define BITS_TBTT_HOLD_TIME_INFRA \ (BIT_MASK_TBTT_HOLD_TIME_INFRA << BIT_SHIFT_TBTT_HOLD_TIME_INFRA) #define BIT_CLEAR_TBTT_HOLD_TIME_INFRA(x) ((x) & (~BITS_TBTT_HOLD_TIME_INFRA)) #define BIT_GET_TBTT_HOLD_TIME_INFRA(x) \ (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_INFRA) & \ BIT_MASK_TBTT_HOLD_TIME_INFRA) #define BIT_SET_TBTT_HOLD_TIME_INFRA(x, v) \ (BIT_CLEAR_TBTT_HOLD_TIME_INFRA(x) | BIT_TBTT_HOLD_TIME_INFRA(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_P2PPS_STATE (Offset 0x0543) */ #define BIT_POWER_STATE BIT(7) #define BIT_CTWINDOW_ON BIT(6) #define BIT_BEACON_AREA_ON BIT(5) #define BIT_CTWIN_EARLY_DISTX BIT(4) #define BIT_NOA1_OFF_PERIOD BIT(3) #define BIT_FORCE_DOZE1 BIT(2) #define BIT_NOA0_OFF_PERIOD BIT(1) #define BIT_FORCE_DOZE0 BIT(0) /* 2 REG_RD_NAV_NXT (Offset 0x0544) */ #define BIT_SHIFT_RD_NAV_PROT_NXT 0 #define BIT_MASK_RD_NAV_PROT_NXT 0xffff #define BIT_RD_NAV_PROT_NXT(x) \ (((x) & BIT_MASK_RD_NAV_PROT_NXT) << BIT_SHIFT_RD_NAV_PROT_NXT) #define BITS_RD_NAV_PROT_NXT \ (BIT_MASK_RD_NAV_PROT_NXT << BIT_SHIFT_RD_NAV_PROT_NXT) #define BIT_CLEAR_RD_NAV_PROT_NXT(x) ((x) & (~BITS_RD_NAV_PROT_NXT)) #define BIT_GET_RD_NAV_PROT_NXT(x) \ (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT) & BIT_MASK_RD_NAV_PROT_NXT) #define BIT_SET_RD_NAV_PROT_NXT(x, v) \ (BIT_CLEAR_RD_NAV_PROT_NXT(x) | BIT_RD_NAV_PROT_NXT(v)) /* 2 REG_NAV_PROT_LEN (Offset 0x0546) */ #define BIT_DIS_RX_BSSID_FIT BIT(6) #define BIT_DIS_TSF_UDT BIT(4) #define BIT_SHIFT_NAV_PROT_LEN 0 #define BIT_MASK_NAV_PROT_LEN 0xffff #define BIT_NAV_PROT_LEN(x) \ (((x) & BIT_MASK_NAV_PROT_LEN) << BIT_SHIFT_NAV_PROT_LEN) #define BITS_NAV_PROT_LEN (BIT_MASK_NAV_PROT_LEN << BIT_SHIFT_NAV_PROT_LEN) #define BIT_CLEAR_NAV_PROT_LEN(x) ((x) & (~BITS_NAV_PROT_LEN)) #define BIT_GET_NAV_PROT_LEN(x) \ (((x) >> BIT_SHIFT_NAV_PROT_LEN) & BIT_MASK_NAV_PROT_LEN) #define BIT_SET_NAV_PROT_LEN(x, v) \ (BIT_CLEAR_NAV_PROT_LEN(x) | BIT_NAV_PROT_LEN(v)) #define BIT_SHIFT_DRVERLYITV 0 #define BIT_MASK_DRVERLYITV 0xff #define BIT_DRVERLYITV(x) (((x) & BIT_MASK_DRVERLYITV) << BIT_SHIFT_DRVERLYITV) #define BITS_DRVERLYITV (BIT_MASK_DRVERLYITV << BIT_SHIFT_DRVERLYITV) #define BIT_CLEAR_DRVERLYITV(x) ((x) & (~BITS_DRVERLYITV)) #define BIT_GET_DRVERLYITV(x) \ (((x) >> BIT_SHIFT_DRVERLYITV) & BIT_MASK_DRVERLYITV) #define BIT_SET_DRVERLYITV(x, v) (BIT_CLEAR_DRVERLYITV(x) | BIT_DRVERLYITV(v)) #define BIT_SHIFT_BCNDMATIM 0 #define BIT_MASK_BCNDMATIM 0xff #define BIT_BCNDMATIM(x) (((x) & BIT_MASK_BCNDMATIM) << BIT_SHIFT_BCNDMATIM) #define BITS_BCNDMATIM (BIT_MASK_BCNDMATIM << BIT_SHIFT_BCNDMATIM) #define BIT_CLEAR_BCNDMATIM(x) ((x) & (~BITS_BCNDMATIM)) #define BIT_GET_BCNDMATIM(x) (((x) >> BIT_SHIFT_BCNDMATIM) & BIT_MASK_BCNDMATIM) #define BIT_SET_BCNDMATIM(x, v) (BIT_CLEAR_BCNDMATIM(x) | BIT_BCNDMATIM(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FTM_CTRL (Offset 0x0548) */ #define BIT_SHIFT_FTM_TSF_R2T_PORT 22 #define BIT_MASK_FTM_TSF_R2T_PORT 0x7 #define BIT_FTM_TSF_R2T_PORT(x) \ (((x) & BIT_MASK_FTM_TSF_R2T_PORT) << BIT_SHIFT_FTM_TSF_R2T_PORT) #define BITS_FTM_TSF_R2T_PORT \ (BIT_MASK_FTM_TSF_R2T_PORT << BIT_SHIFT_FTM_TSF_R2T_PORT) #define BIT_CLEAR_FTM_TSF_R2T_PORT(x) ((x) & (~BITS_FTM_TSF_R2T_PORT)) #define BIT_GET_FTM_TSF_R2T_PORT(x) \ (((x) >> BIT_SHIFT_FTM_TSF_R2T_PORT) & BIT_MASK_FTM_TSF_R2T_PORT) #define BIT_SET_FTM_TSF_R2T_PORT(x, v) \ (BIT_CLEAR_FTM_TSF_R2T_PORT(x) | BIT_FTM_TSF_R2T_PORT(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTM_PTT (Offset 0x0548) */ #define BIT_SHIFT_FTM_PTT_TSF_R2T_SEL 22 #define BIT_MASK_FTM_PTT_TSF_R2T_SEL 0x7 #define BIT_FTM_PTT_TSF_R2T_SEL(x) \ (((x) & BIT_MASK_FTM_PTT_TSF_R2T_SEL) << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL) #define BITS_FTM_PTT_TSF_R2T_SEL \ (BIT_MASK_FTM_PTT_TSF_R2T_SEL << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL) #define BIT_CLEAR_FTM_PTT_TSF_R2T_SEL(x) ((x) & (~BITS_FTM_PTT_TSF_R2T_SEL)) #define BIT_GET_FTM_PTT_TSF_R2T_SEL(x) \ (((x) >> BIT_SHIFT_FTM_PTT_TSF_R2T_SEL) & BIT_MASK_FTM_PTT_TSF_R2T_SEL) #define BIT_SET_FTM_PTT_TSF_R2T_SEL(x, v) \ (BIT_CLEAR_FTM_PTT_TSF_R2T_SEL(x) | BIT_FTM_PTT_TSF_R2T_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FTM_CTRL (Offset 0x0548) */ #define BIT_SHIFT_FTM_TSF_T2R_PORT 19 #define BIT_MASK_FTM_TSF_T2R_PORT 0x7 #define BIT_FTM_TSF_T2R_PORT(x) \ (((x) & BIT_MASK_FTM_TSF_T2R_PORT) << BIT_SHIFT_FTM_TSF_T2R_PORT) #define BITS_FTM_TSF_T2R_PORT \ (BIT_MASK_FTM_TSF_T2R_PORT << BIT_SHIFT_FTM_TSF_T2R_PORT) #define BIT_CLEAR_FTM_TSF_T2R_PORT(x) ((x) & (~BITS_FTM_TSF_T2R_PORT)) #define BIT_GET_FTM_TSF_T2R_PORT(x) \ (((x) >> BIT_SHIFT_FTM_TSF_T2R_PORT) & BIT_MASK_FTM_TSF_T2R_PORT) #define BIT_SET_FTM_TSF_T2R_PORT(x, v) \ (BIT_CLEAR_FTM_TSF_T2R_PORT(x) | BIT_FTM_TSF_T2R_PORT(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTM_PTT (Offset 0x0548) */ #define BIT_SHIFT_FTM_PTT_TSF_T2R_SEL 19 #define BIT_MASK_FTM_PTT_TSF_T2R_SEL 0x7 #define BIT_FTM_PTT_TSF_T2R_SEL(x) \ (((x) & BIT_MASK_FTM_PTT_TSF_T2R_SEL) << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL) #define BITS_FTM_PTT_TSF_T2R_SEL \ (BIT_MASK_FTM_PTT_TSF_T2R_SEL << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL) #define BIT_CLEAR_FTM_PTT_TSF_T2R_SEL(x) ((x) & (~BITS_FTM_PTT_TSF_T2R_SEL)) #define BIT_GET_FTM_PTT_TSF_T2R_SEL(x) \ (((x) >> BIT_SHIFT_FTM_PTT_TSF_T2R_SEL) & BIT_MASK_FTM_PTT_TSF_T2R_SEL) #define BIT_SET_FTM_PTT_TSF_T2R_SEL(x, v) \ (BIT_CLEAR_FTM_PTT_TSF_T2R_SEL(x) | BIT_FTM_PTT_TSF_T2R_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FTM_CTRL (Offset 0x0548) */ #define BIT_SHIFT_FTM_PTT_PORT 16 #define BIT_MASK_FTM_PTT_PORT 0x7 #define BIT_FTM_PTT_PORT(x) \ (((x) & BIT_MASK_FTM_PTT_PORT) << BIT_SHIFT_FTM_PTT_PORT) #define BITS_FTM_PTT_PORT (BIT_MASK_FTM_PTT_PORT << BIT_SHIFT_FTM_PTT_PORT) #define BIT_CLEAR_FTM_PTT_PORT(x) ((x) & (~BITS_FTM_PTT_PORT)) #define BIT_GET_FTM_PTT_PORT(x) \ (((x) >> BIT_SHIFT_FTM_PTT_PORT) & BIT_MASK_FTM_PTT_PORT) #define BIT_SET_FTM_PTT_PORT(x, v) \ (BIT_CLEAR_FTM_PTT_PORT(x) | BIT_FTM_PTT_PORT(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTM_PTT (Offset 0x0548) */ #define BIT_SHIFT_FTM_PTT_TSF_SEL 16 #define BIT_MASK_FTM_PTT_TSF_SEL 0x7 #define BIT_FTM_PTT_TSF_SEL(x) \ (((x) & BIT_MASK_FTM_PTT_TSF_SEL) << BIT_SHIFT_FTM_PTT_TSF_SEL) #define BITS_FTM_PTT_TSF_SEL \ (BIT_MASK_FTM_PTT_TSF_SEL << BIT_SHIFT_FTM_PTT_TSF_SEL) #define BIT_CLEAR_FTM_PTT_TSF_SEL(x) ((x) & (~BITS_FTM_PTT_TSF_SEL)) #define BIT_GET_FTM_PTT_TSF_SEL(x) \ (((x) >> BIT_SHIFT_FTM_PTT_TSF_SEL) & BIT_MASK_FTM_PTT_TSF_SEL) #define BIT_SET_FTM_PTT_TSF_SEL(x, v) \ (BIT_CLEAR_FTM_PTT_TSF_SEL(x) | BIT_FTM_PTT_TSF_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FTM_CTRL (Offset 0x0548) */ #define BIT_SHIFT_FTM_PTT 0 #define BIT_MASK_FTM_PTT 0xffff #define BIT_FTM_PTT(x) (((x) & BIT_MASK_FTM_PTT) << BIT_SHIFT_FTM_PTT) #define BITS_FTM_PTT (BIT_MASK_FTM_PTT << BIT_SHIFT_FTM_PTT) #define BIT_CLEAR_FTM_PTT(x) ((x) & (~BITS_FTM_PTT)) #define BIT_GET_FTM_PTT(x) (((x) >> BIT_SHIFT_FTM_PTT) & BIT_MASK_FTM_PTT) #define BIT_SET_FTM_PTT(x, v) (BIT_CLEAR_FTM_PTT(x) | BIT_FTM_PTT(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTM_PTT (Offset 0x0548) */ #define BIT_SHIFT_FTM_PTT_VALUE 0 #define BIT_MASK_FTM_PTT_VALUE 0xffff #define BIT_FTM_PTT_VALUE(x) \ (((x) & BIT_MASK_FTM_PTT_VALUE) << BIT_SHIFT_FTM_PTT_VALUE) #define BITS_FTM_PTT_VALUE (BIT_MASK_FTM_PTT_VALUE << BIT_SHIFT_FTM_PTT_VALUE) #define BIT_CLEAR_FTM_PTT_VALUE(x) ((x) & (~BITS_FTM_PTT_VALUE)) #define BIT_GET_FTM_PTT_VALUE(x) \ (((x) >> BIT_SHIFT_FTM_PTT_VALUE) & BIT_MASK_FTM_PTT_VALUE) #define BIT_SET_FTM_PTT_VALUE(x, v) \ (BIT_CLEAR_FTM_PTT_VALUE(x) | BIT_FTM_PTT_VALUE(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FTM_TSF_CNT (Offset 0x054C) */ #define BIT_SHIFT_FTM_TSF_R2T 16 #define BIT_MASK_FTM_TSF_R2T 0xffff #define BIT_FTM_TSF_R2T(x) \ (((x) & BIT_MASK_FTM_TSF_R2T) << BIT_SHIFT_FTM_TSF_R2T) #define BITS_FTM_TSF_R2T (BIT_MASK_FTM_TSF_R2T << BIT_SHIFT_FTM_TSF_R2T) #define BIT_CLEAR_FTM_TSF_R2T(x) ((x) & (~BITS_FTM_TSF_R2T)) #define BIT_GET_FTM_TSF_R2T(x) \ (((x) >> BIT_SHIFT_FTM_TSF_R2T) & BIT_MASK_FTM_TSF_R2T) #define BIT_SET_FTM_TSF_R2T(x, v) \ (BIT_CLEAR_FTM_TSF_R2T(x) | BIT_FTM_TSF_R2T(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTM_TSF (Offset 0x054C) */ #define BIT_SHIFT_FTM_T2_TSF 16 #define BIT_MASK_FTM_T2_TSF 0xffff #define BIT_FTM_T2_TSF(x) (((x) & BIT_MASK_FTM_T2_TSF) << BIT_SHIFT_FTM_T2_TSF) #define BITS_FTM_T2_TSF (BIT_MASK_FTM_T2_TSF << BIT_SHIFT_FTM_T2_TSF) #define BIT_CLEAR_FTM_T2_TSF(x) ((x) & (~BITS_FTM_T2_TSF)) #define BIT_GET_FTM_T2_TSF(x) \ (((x) >> BIT_SHIFT_FTM_T2_TSF) & BIT_MASK_FTM_T2_TSF) #define BIT_SET_FTM_T2_TSF(x, v) (BIT_CLEAR_FTM_T2_TSF(x) | BIT_FTM_T2_TSF(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FTM_TSF_CNT (Offset 0x054C) */ #define BIT_SHIFT_FTM_TSF_T2R 0 #define BIT_MASK_FTM_TSF_T2R 0xffff #define BIT_FTM_TSF_T2R(x) \ (((x) & BIT_MASK_FTM_TSF_T2R) << BIT_SHIFT_FTM_TSF_T2R) #define BITS_FTM_TSF_T2R (BIT_MASK_FTM_TSF_T2R << BIT_SHIFT_FTM_TSF_T2R) #define BIT_CLEAR_FTM_TSF_T2R(x) ((x) & (~BITS_FTM_TSF_T2R)) #define BIT_GET_FTM_TSF_T2R(x) \ (((x) >> BIT_SHIFT_FTM_TSF_T2R) & BIT_MASK_FTM_TSF_T2R) #define BIT_SET_FTM_TSF_T2R(x, v) \ (BIT_CLEAR_FTM_TSF_T2R(x) | BIT_FTM_TSF_T2R(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FTM_TSF (Offset 0x054C) */ #define BIT_SHIFT_FTM_T1_TSF 0 #define BIT_MASK_FTM_T1_TSF 0xffff #define BIT_FTM_T1_TSF(x) (((x) & BIT_MASK_FTM_T1_TSF) << BIT_SHIFT_FTM_T1_TSF) #define BITS_FTM_T1_TSF (BIT_MASK_FTM_T1_TSF << BIT_SHIFT_FTM_T1_TSF) #define BIT_CLEAR_FTM_T1_TSF(x) ((x) & (~BITS_FTM_T1_TSF)) #define BIT_GET_FTM_T1_TSF(x) \ (((x) >> BIT_SHIFT_FTM_T1_TSF) & BIT_MASK_FTM_T1_TSF) #define BIT_SET_FTM_T1_TSF(x, v) (BIT_CLEAR_FTM_T1_TSF(x) | BIT_FTM_T1_TSF(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BCN_CTRL (Offset 0x0550) */ #define BIT_P0_EN_TXBCN_RPT BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BCN_CTRL (Offset 0x0550) */ #define BIT_EN_BCN_FUNCTION BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_BCN_CTRL (Offset 0x0550) */ #define BIT_EN_TXBCN_RPT BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BCN_CTRL (Offset 0x0550) */ #define BIT_P0_EN_RXBCN_RPT BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BCN_CTRL (Offset 0x0550) */ #define BIT_DIS_BCNQ_SUB BIT(1) /* 2 REG_BCN_CTRL1 (Offset 0x0551) */ #define BIT_DIS_RX_BSSID_FIT1 BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ #define BIT_CLI0_DIS_RX_BSSID_FIT BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BCN_CTRL1 (Offset 0x0551) */ #define BIT_DIS_TSF1_UDT BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ #define BIT_CLI0_DIS_TSF_UDT BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BCN_CTRL1 (Offset 0x0551) */ #define BIT_EN_BCN1_FUNCTION BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ #define BIT_CLI0_EN_BCN_FUNCTION BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BCN_CTRL1 (Offset 0x0551) */ #define BIT_EN_TXBCN1_RPT BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ #define BIT_CLI0_EN_RXBCN_RPT BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ #define BIT_CLI0_EN_BCN_RPT BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BCN_CTRL1 (Offset 0x0551) */ #define BIT_DIS_BCNQ1_SUB BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ #define BIT_CLI0_ENP2P_CTWINDOW BIT(1) #define BIT_CLI0_ENP2P_BCNQ_AREA BIT(0) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_MBID_NUM (Offset 0x0552) */ #define BIT_SHIFT_MBID_BCN_NUM_V2 4 #define BIT_MASK_MBID_BCN_NUM_V2 0xf #define BIT_MBID_BCN_NUM_V2(x) \ (((x) & BIT_MASK_MBID_BCN_NUM_V2) << BIT_SHIFT_MBID_BCN_NUM_V2) #define BITS_MBID_BCN_NUM_V2 \ (BIT_MASK_MBID_BCN_NUM_V2 << BIT_SHIFT_MBID_BCN_NUM_V2) #define BIT_CLEAR_MBID_BCN_NUM_V2(x) ((x) & (~BITS_MBID_BCN_NUM_V2)) #define BIT_GET_MBID_BCN_NUM_V2(x) \ (((x) >> BIT_SHIFT_MBID_BCN_NUM_V2) & BIT_MASK_MBID_BCN_NUM_V2) #define BIT_SET_MBID_BCN_NUM_V2(x, v) \ (BIT_CLEAR_MBID_BCN_NUM_V2(x) | BIT_MBID_BCN_NUM_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBID_NUM (Offset 0x0552) */ #define BIT_EN_PRE_DL_BEACON BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBID_NUM (Offset 0x0552) */ #define BIT_SHIFT_MBID_BCN_NUM 0 #define BIT_MASK_MBID_BCN_NUM 0x7 #define BIT_MBID_BCN_NUM(x) \ (((x) & BIT_MASK_MBID_BCN_NUM) << BIT_SHIFT_MBID_BCN_NUM) #define BITS_MBID_BCN_NUM (BIT_MASK_MBID_BCN_NUM << BIT_SHIFT_MBID_BCN_NUM) #define BIT_CLEAR_MBID_BCN_NUM(x) ((x) & (~BITS_MBID_BCN_NUM)) #define BIT_GET_MBID_BCN_NUM(x) \ (((x) >> BIT_SHIFT_MBID_BCN_NUM) & BIT_MASK_MBID_BCN_NUM) #define BIT_SET_MBID_BCN_NUM(x, v) \ (BIT_CLEAR_MBID_BCN_NUM(x) | BIT_MBID_BCN_NUM(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ #define BIT_P2P_PWR_RST1 BIT(6) #define BIT_SCHEDULER_RST BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ #define BIT_FREECNT_RST BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ #define BIT_P2P_PWR_RST0 BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ #define BIT_TSFTR_CLI3_RST BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ #define BIT_TSFTR1_SYNC_EN BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ #define BIT_TSFTR_CLI2_RST BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ #define BIT_TSFTR_SYNC_EN BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ #define BIT_TSFTR_CLI1_RST BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ #define BIT_TSFTR1_RST BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ #define BIT_TSFTR_CLI0_RST BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ #define BIT_TSFTR_RST BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ #define BIT_SHIFT_BCN_TIMER_SEL_FWRD 28 #define BIT_MASK_BCN_TIMER_SEL_FWRD 0x7 #define BIT_BCN_TIMER_SEL_FWRD(x) \ (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD) << BIT_SHIFT_BCN_TIMER_SEL_FWRD) #define BITS_BCN_TIMER_SEL_FWRD \ (BIT_MASK_BCN_TIMER_SEL_FWRD << BIT_SHIFT_BCN_TIMER_SEL_FWRD) #define BIT_CLEAR_BCN_TIMER_SEL_FWRD(x) ((x) & (~BITS_BCN_TIMER_SEL_FWRD)) #define BIT_GET_BCN_TIMER_SEL_FWRD(x) \ (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD) & BIT_MASK_BCN_TIMER_SEL_FWRD) #define BIT_SET_BCN_TIMER_SEL_FWRD(x, v) \ (BIT_CLEAR_BCN_TIMER_SEL_FWRD(x) | BIT_BCN_TIMER_SEL_FWRD(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ #define BIT_SHIFT_BCN_SPACE1 16 #define BIT_MASK_BCN_SPACE1 0xffff #define BIT_BCN_SPACE1(x) (((x) & BIT_MASK_BCN_SPACE1) << BIT_SHIFT_BCN_SPACE1) #define BITS_BCN_SPACE1 (BIT_MASK_BCN_SPACE1 << BIT_SHIFT_BCN_SPACE1) #define BIT_CLEAR_BCN_SPACE1(x) ((x) & (~BITS_BCN_SPACE1)) #define BIT_GET_BCN_SPACE1(x) \ (((x) >> BIT_SHIFT_BCN_SPACE1) & BIT_MASK_BCN_SPACE1) #define BIT_SET_BCN_SPACE1(x, v) (BIT_CLEAR_BCN_SPACE1(x) | BIT_BCN_SPACE1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ #define BIT_SHIFT_BCN_SPACE_CLINT0 16 #define BIT_MASK_BCN_SPACE_CLINT0 0xfff #define BIT_BCN_SPACE_CLINT0(x) \ (((x) & BIT_MASK_BCN_SPACE_CLINT0) << BIT_SHIFT_BCN_SPACE_CLINT0) #define BITS_BCN_SPACE_CLINT0 \ (BIT_MASK_BCN_SPACE_CLINT0 << BIT_SHIFT_BCN_SPACE_CLINT0) #define BIT_CLEAR_BCN_SPACE_CLINT0(x) ((x) & (~BITS_BCN_SPACE_CLINT0)) #define BIT_GET_BCN_SPACE_CLINT0(x) \ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0) & BIT_MASK_BCN_SPACE_CLINT0) #define BIT_SET_BCN_SPACE_CLINT0(x, v) \ (BIT_CLEAR_BCN_SPACE_CLINT0(x) | BIT_BCN_SPACE_CLINT0(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ #define BIT_SHIFT_BCN_SPACE0 0 #define BIT_MASK_BCN_SPACE0 0xffff #define BIT_BCN_SPACE0(x) (((x) & BIT_MASK_BCN_SPACE0) << BIT_SHIFT_BCN_SPACE0) #define BITS_BCN_SPACE0 (BIT_MASK_BCN_SPACE0 << BIT_SHIFT_BCN_SPACE0) #define BIT_CLEAR_BCN_SPACE0(x) ((x) & (~BITS_BCN_SPACE0)) #define BIT_GET_BCN_SPACE0(x) \ (((x) >> BIT_SHIFT_BCN_SPACE0) & BIT_MASK_BCN_SPACE0) #define BIT_SET_BCN_SPACE0(x, v) (BIT_CLEAR_BCN_SPACE0(x) | BIT_BCN_SPACE0(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_ATIMWND (Offset 0x055A) */ #define BIT_SHIFT_ATIMWND 0 #define BIT_MASK_ATIMWND 0xffff #define BIT_ATIMWND(x) (((x) & BIT_MASK_ATIMWND) << BIT_SHIFT_ATIMWND) #define BITS_ATIMWND (BIT_MASK_ATIMWND << BIT_SHIFT_ATIMWND) #define BIT_CLEAR_ATIMWND(x) ((x) & (~BITS_ATIMWND)) #define BIT_GET_ATIMWND(x) (((x) >> BIT_SHIFT_ATIMWND) & BIT_MASK_ATIMWND) #define BIT_SET_ATIMWND(x, v) (BIT_CLEAR_ATIMWND(x) | BIT_ATIMWND(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_ATIMWND (Offset 0x055A) */ #define BIT_SHIFT_ATIMWND0 0 #define BIT_MASK_ATIMWND0 0xffff #define BIT_ATIMWND0(x) (((x) & BIT_MASK_ATIMWND0) << BIT_SHIFT_ATIMWND0) #define BITS_ATIMWND0 (BIT_MASK_ATIMWND0 << BIT_SHIFT_ATIMWND0) #define BIT_CLEAR_ATIMWND0(x) ((x) & (~BITS_ATIMWND0)) #define BIT_GET_ATIMWND0(x) (((x) >> BIT_SHIFT_ATIMWND0) & BIT_MASK_ATIMWND0) #define BIT_SET_ATIMWND0(x, v) (BIT_CLEAR_ATIMWND0(x) | BIT_ATIMWND0(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_USTIME_TSF (Offset 0x055C) */ #define BIT_SHIFT_USTIME_TSF_V1 0 #define BIT_MASK_USTIME_TSF_V1 0xff #define BIT_USTIME_TSF_V1(x) \ (((x) & BIT_MASK_USTIME_TSF_V1) << BIT_SHIFT_USTIME_TSF_V1) #define BITS_USTIME_TSF_V1 (BIT_MASK_USTIME_TSF_V1 << BIT_SHIFT_USTIME_TSF_V1) #define BIT_CLEAR_USTIME_TSF_V1(x) ((x) & (~BITS_USTIME_TSF_V1)) #define BIT_GET_USTIME_TSF_V1(x) \ (((x) >> BIT_SHIFT_USTIME_TSF_V1) & BIT_MASK_USTIME_TSF_V1) #define BIT_SET_USTIME_TSF_V1(x, v) \ (BIT_CLEAR_USTIME_TSF_V1(x) | BIT_USTIME_TSF_V1(v)) /* 2 REG_BCN_MAX_ERR (Offset 0x055D) */ #define BIT_SHIFT_BCN_MAX_ERR 0 #define BIT_MASK_BCN_MAX_ERR 0xff #define BIT_BCN_MAX_ERR(x) \ (((x) & BIT_MASK_BCN_MAX_ERR) << BIT_SHIFT_BCN_MAX_ERR) #define BITS_BCN_MAX_ERR (BIT_MASK_BCN_MAX_ERR << BIT_SHIFT_BCN_MAX_ERR) #define BIT_CLEAR_BCN_MAX_ERR(x) ((x) & (~BITS_BCN_MAX_ERR)) #define BIT_GET_BCN_MAX_ERR(x) \ (((x) >> BIT_SHIFT_BCN_MAX_ERR) & BIT_MASK_BCN_MAX_ERR) #define BIT_SET_BCN_MAX_ERR(x, v) \ (BIT_CLEAR_BCN_MAX_ERR(x) | BIT_BCN_MAX_ERR(v)) /* 2 REG_RXTSF_OFFSET_CCK (Offset 0x055E) */ #define BIT_SHIFT_CCK_RXTSF_OFFSET 0 #define BIT_MASK_CCK_RXTSF_OFFSET 0xff #define BIT_CCK_RXTSF_OFFSET(x) \ (((x) & BIT_MASK_CCK_RXTSF_OFFSET) << BIT_SHIFT_CCK_RXTSF_OFFSET) #define BITS_CCK_RXTSF_OFFSET \ (BIT_MASK_CCK_RXTSF_OFFSET << BIT_SHIFT_CCK_RXTSF_OFFSET) #define BIT_CLEAR_CCK_RXTSF_OFFSET(x) ((x) & (~BITS_CCK_RXTSF_OFFSET)) #define BIT_GET_CCK_RXTSF_OFFSET(x) \ (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET) & BIT_MASK_CCK_RXTSF_OFFSET) #define BIT_SET_CCK_RXTSF_OFFSET(x, v) \ (BIT_CLEAR_CCK_RXTSF_OFFSET(x) | BIT_CCK_RXTSF_OFFSET(v)) /* 2 REG_RXTSF_OFFSET_OFDM (Offset 0x055F) */ #define BIT_SHIFT_OFDM_RXTSF_OFFSET 0 #define BIT_MASK_OFDM_RXTSF_OFFSET 0xff #define BIT_OFDM_RXTSF_OFFSET(x) \ (((x) & BIT_MASK_OFDM_RXTSF_OFFSET) << BIT_SHIFT_OFDM_RXTSF_OFFSET) #define BITS_OFDM_RXTSF_OFFSET \ (BIT_MASK_OFDM_RXTSF_OFFSET << BIT_SHIFT_OFDM_RXTSF_OFFSET) #define BIT_CLEAR_OFDM_RXTSF_OFFSET(x) ((x) & (~BITS_OFDM_RXTSF_OFFSET)) #define BIT_GET_OFDM_RXTSF_OFFSET(x) \ (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET) & BIT_MASK_OFDM_RXTSF_OFFSET) #define BIT_SET_OFDM_RXTSF_OFFSET(x, v) \ (BIT_CLEAR_OFDM_RXTSF_OFFSET(x) | BIT_OFDM_RXTSF_OFFSET(v)) #define BIT_SHIFT_CTWND 0 #define BIT_MASK_CTWND 0xff #define BIT_CTWND(x) (((x) & BIT_MASK_CTWND) << BIT_SHIFT_CTWND) #define BITS_CTWND (BIT_MASK_CTWND << BIT_SHIFT_CTWND) #define BIT_CLEAR_CTWND(x) ((x) & (~BITS_CTWND)) #define BIT_GET_CTWND(x) (((x) >> BIT_SHIFT_CTWND) & BIT_MASK_CTWND) #define BIT_SET_CTWND(x, v) (BIT_CLEAR_CTWND(x) | BIT_CTWND(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TSFTR (Offset 0x0560) */ #define BIT_SHIFT_TSF_TIMER 0 #define BIT_MASK_TSF_TIMER 0xffffffffffffffffL #define BIT_TSF_TIMER(x) (((x) & BIT_MASK_TSF_TIMER) << BIT_SHIFT_TSF_TIMER) #define BITS_TSF_TIMER (BIT_MASK_TSF_TIMER << BIT_SHIFT_TSF_TIMER) #define BIT_CLEAR_TSF_TIMER(x) ((x) & (~BITS_TSF_TIMER)) #define BIT_GET_TSF_TIMER(x) (((x) >> BIT_SHIFT_TSF_TIMER) & BIT_MASK_TSF_TIMER) #define BIT_SET_TSF_TIMER(x, v) (BIT_CLEAR_TSF_TIMER(x) | BIT_TSF_TIMER(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TSFTR (Offset 0x0560) */ #define BIT_SHIFT_TSF_TIMER_V1 0 #define BIT_MASK_TSF_TIMER_V1 0xffffffffL #define BIT_TSF_TIMER_V1(x) \ (((x) & BIT_MASK_TSF_TIMER_V1) << BIT_SHIFT_TSF_TIMER_V1) #define BITS_TSF_TIMER_V1 (BIT_MASK_TSF_TIMER_V1 << BIT_SHIFT_TSF_TIMER_V1) #define BIT_CLEAR_TSF_TIMER_V1(x) ((x) & (~BITS_TSF_TIMER_V1)) #define BIT_GET_TSF_TIMER_V1(x) \ (((x) >> BIT_SHIFT_TSF_TIMER_V1) & BIT_MASK_TSF_TIMER_V1) #define BIT_SET_TSF_TIMER_V1(x, v) \ (BIT_CLEAR_TSF_TIMER_V1(x) | BIT_TSF_TIMER_V1(v)) /* 2 REG_TSFTR_1 (Offset 0x0564) */ #define BIT_SHIFT_TSF_TIMER_V2 0 #define BIT_MASK_TSF_TIMER_V2 0xffffffffL #define BIT_TSF_TIMER_V2(x) \ (((x) & BIT_MASK_TSF_TIMER_V2) << BIT_SHIFT_TSF_TIMER_V2) #define BITS_TSF_TIMER_V2 (BIT_MASK_TSF_TIMER_V2 << BIT_SHIFT_TSF_TIMER_V2) #define BIT_CLEAR_TSF_TIMER_V2(x) ((x) & (~BITS_TSF_TIMER_V2)) #define BIT_GET_TSF_TIMER_V2(x) \ (((x) >> BIT_SHIFT_TSF_TIMER_V2) & BIT_MASK_TSF_TIMER_V2) #define BIT_SET_TSF_TIMER_V2(x, v) \ (BIT_CLEAR_TSF_TIMER_V2(x) | BIT_TSF_TIMER_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TSFTR1 (Offset 0x0568) */ #define BIT_SHIFT_TSF_TIMER1 0 #define BIT_MASK_TSF_TIMER1 0xffffffffffffffffL #define BIT_TSF_TIMER1(x) (((x) & BIT_MASK_TSF_TIMER1) << BIT_SHIFT_TSF_TIMER1) #define BITS_TSF_TIMER1 (BIT_MASK_TSF_TIMER1 << BIT_SHIFT_TSF_TIMER1) #define BIT_CLEAR_TSF_TIMER1(x) ((x) & (~BITS_TSF_TIMER1)) #define BIT_GET_TSF_TIMER1(x) \ (((x) >> BIT_SHIFT_TSF_TIMER1) & BIT_MASK_TSF_TIMER1) #define BIT_SET_TSF_TIMER1(x, v) (BIT_CLEAR_TSF_TIMER1(x) | BIT_TSF_TIMER1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FREERUN_CNT (Offset 0x0568) */ #define BIT_SHIFT_FREERUN_CNT 0 #define BIT_MASK_FREERUN_CNT 0xffffffffffffffffL #define BIT_FREERUN_CNT(x) \ (((x) & BIT_MASK_FREERUN_CNT) << BIT_SHIFT_FREERUN_CNT) #define BITS_FREERUN_CNT (BIT_MASK_FREERUN_CNT << BIT_SHIFT_FREERUN_CNT) #define BIT_CLEAR_FREERUN_CNT(x) ((x) & (~BITS_FREERUN_CNT)) #define BIT_GET_FREERUN_CNT(x) \ (((x) >> BIT_SHIFT_FREERUN_CNT) & BIT_MASK_FREERUN_CNT) #define BIT_SET_FREERUN_CNT(x, v) \ (BIT_CLEAR_FREERUN_CNT(x) | BIT_FREERUN_CNT(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FREERUN_CNT (Offset 0x0568) */ #define BIT_SHIFT_FREERUN_CNT_V1 0 #define BIT_MASK_FREERUN_CNT_V1 0xffffffffL #define BIT_FREERUN_CNT_V1(x) \ (((x) & BIT_MASK_FREERUN_CNT_V1) << BIT_SHIFT_FREERUN_CNT_V1) #define BITS_FREERUN_CNT_V1 \ (BIT_MASK_FREERUN_CNT_V1 << BIT_SHIFT_FREERUN_CNT_V1) #define BIT_CLEAR_FREERUN_CNT_V1(x) ((x) & (~BITS_FREERUN_CNT_V1)) #define BIT_GET_FREERUN_CNT_V1(x) \ (((x) >> BIT_SHIFT_FREERUN_CNT_V1) & BIT_MASK_FREERUN_CNT_V1) #define BIT_SET_FREERUN_CNT_V1(x, v) \ (BIT_CLEAR_FREERUN_CNT_V1(x) | BIT_FREERUN_CNT_V1(v)) /* 2 REG_FREERUN_CNT_1 (Offset 0x056C) */ #define BIT_SHIFT_FREERUN_CNT_V2 0 #define BIT_MASK_FREERUN_CNT_V2 0xffffffffL #define BIT_FREERUN_CNT_V2(x) \ (((x) & BIT_MASK_FREERUN_CNT_V2) << BIT_SHIFT_FREERUN_CNT_V2) #define BITS_FREERUN_CNT_V2 \ (BIT_MASK_FREERUN_CNT_V2 << BIT_SHIFT_FREERUN_CNT_V2) #define BIT_CLEAR_FREERUN_CNT_V2(x) ((x) & (~BITS_FREERUN_CNT_V2)) #define BIT_GET_FREERUN_CNT_V2(x) \ (((x) >> BIT_SHIFT_FREERUN_CNT_V2) & BIT_MASK_FREERUN_CNT_V2) #define BIT_SET_FREERUN_CNT_V2(x, v) \ (BIT_CLEAR_FREERUN_CNT_V2(x) | BIT_FREERUN_CNT_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_ATIMWND1 (Offset 0x0570) */ #define BIT_SHIFT_ATIMWND1 0 #define BIT_MASK_ATIMWND1 0xffff #define BIT_ATIMWND1(x) (((x) & BIT_MASK_ATIMWND1) << BIT_SHIFT_ATIMWND1) #define BITS_ATIMWND1 (BIT_MASK_ATIMWND1 << BIT_SHIFT_ATIMWND1) #define BIT_CLEAR_ATIMWND1(x) ((x) & (~BITS_ATIMWND1)) #define BIT_GET_ATIMWND1(x) (((x) >> BIT_SHIFT_ATIMWND1) & BIT_MASK_ATIMWND1) #define BIT_SET_ATIMWND1(x, v) (BIT_CLEAR_ATIMWND1(x) | BIT_ATIMWND1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_ATIMWND1_V1 (Offset 0x0570) */ #define BIT_SHIFT_ATIMWND1_V1 0 #define BIT_MASK_ATIMWND1_V1 0xff #define BIT_ATIMWND1_V1(x) \ (((x) & BIT_MASK_ATIMWND1_V1) << BIT_SHIFT_ATIMWND1_V1) #define BITS_ATIMWND1_V1 (BIT_MASK_ATIMWND1_V1 << BIT_SHIFT_ATIMWND1_V1) #define BIT_CLEAR_ATIMWND1_V1(x) ((x) & (~BITS_ATIMWND1_V1)) #define BIT_GET_ATIMWND1_V1(x) \ (((x) >> BIT_SHIFT_ATIMWND1_V1) & BIT_MASK_ATIMWND1_V1) #define BIT_SET_ATIMWND1_V1(x, v) \ (BIT_CLEAR_ATIMWND1_V1(x) | BIT_ATIMWND1_V1(v)) /* 2 REG_TBTT_PROHIBIT_INFRA (Offset 0x0571) */ #define BIT_SHIFT_TBTT_PROHIBIT_INFRA 0 #define BIT_MASK_TBTT_PROHIBIT_INFRA 0xff #define BIT_TBTT_PROHIBIT_INFRA(x) \ (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA) << BIT_SHIFT_TBTT_PROHIBIT_INFRA) #define BITS_TBTT_PROHIBIT_INFRA \ (BIT_MASK_TBTT_PROHIBIT_INFRA << BIT_SHIFT_TBTT_PROHIBIT_INFRA) #define BIT_CLEAR_TBTT_PROHIBIT_INFRA(x) ((x) & (~BITS_TBTT_PROHIBIT_INFRA)) #define BIT_GET_TBTT_PROHIBIT_INFRA(x) \ (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA) & BIT_MASK_TBTT_PROHIBIT_INFRA) #define BIT_SET_TBTT_PROHIBIT_INFRA(x, v) \ (BIT_CLEAR_TBTT_PROHIBIT_INFRA(x) | BIT_TBTT_PROHIBIT_INFRA(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_BCNIVLCUNT (Offset 0x0573) */ #define BIT_SHIFT_BCNIVLCUNT 0 #define BIT_MASK_BCNIVLCUNT 0x7f #define BIT_BCNIVLCUNT(x) (((x) & BIT_MASK_BCNIVLCUNT) << BIT_SHIFT_BCNIVLCUNT) #define BITS_BCNIVLCUNT (BIT_MASK_BCNIVLCUNT << BIT_SHIFT_BCNIVLCUNT) #define BIT_CLEAR_BCNIVLCUNT(x) ((x) & (~BITS_BCNIVLCUNT)) #define BIT_GET_BCNIVLCUNT(x) \ (((x) >> BIT_SHIFT_BCNIVLCUNT) & BIT_MASK_BCNIVLCUNT) #define BIT_SET_BCNIVLCUNT(x, v) (BIT_CLEAR_BCNIVLCUNT(x) | BIT_BCNIVLCUNT(v)) /* 2 REG_BCNDROPCTRL (Offset 0x0574) */ #define BIT_BEACON_DROP_EN BIT(7) #define BIT_SHIFT_BEACON_DROP_IVL 0 #define BIT_MASK_BEACON_DROP_IVL 0x7f #define BIT_BEACON_DROP_IVL(x) \ (((x) & BIT_MASK_BEACON_DROP_IVL) << BIT_SHIFT_BEACON_DROP_IVL) #define BITS_BEACON_DROP_IVL \ (BIT_MASK_BEACON_DROP_IVL << BIT_SHIFT_BEACON_DROP_IVL) #define BIT_CLEAR_BEACON_DROP_IVL(x) ((x) & (~BITS_BEACON_DROP_IVL)) #define BIT_GET_BEACON_DROP_IVL(x) \ (((x) >> BIT_SHIFT_BEACON_DROP_IVL) & BIT_MASK_BEACON_DROP_IVL) #define BIT_SET_BEACON_DROP_IVL(x, v) \ (BIT_CLEAR_BEACON_DROP_IVL(x) | BIT_BEACON_DROP_IVL(v)) /* 2 REG_HGQ_TIMEOUT_PERIOD (Offset 0x0575) */ #define BIT_SHIFT_HGQ_TIMEOUT_PERIOD 0 #define BIT_MASK_HGQ_TIMEOUT_PERIOD 0xff #define BIT_HGQ_TIMEOUT_PERIOD(x) \ (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD) #define BITS_HGQ_TIMEOUT_PERIOD \ (BIT_MASK_HGQ_TIMEOUT_PERIOD << BIT_SHIFT_HGQ_TIMEOUT_PERIOD) #define BIT_CLEAR_HGQ_TIMEOUT_PERIOD(x) ((x) & (~BITS_HGQ_TIMEOUT_PERIOD)) #define BIT_GET_HGQ_TIMEOUT_PERIOD(x) \ (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD) & BIT_MASK_HGQ_TIMEOUT_PERIOD) #define BIT_SET_HGQ_TIMEOUT_PERIOD(x, v) \ (BIT_CLEAR_HGQ_TIMEOUT_PERIOD(x) | BIT_HGQ_TIMEOUT_PERIOD(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXCMD_TIMEOUT_PERIOD (Offset 0x0576) */ #define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD 0 #define BIT_MASK_TXCMD_TIMEOUT_PERIOD 0xff #define BIT_TXCMD_TIMEOUT_PERIOD(x) \ (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD) \ << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) #define BITS_TXCMD_TIMEOUT_PERIOD \ (BIT_MASK_TXCMD_TIMEOUT_PERIOD << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) #define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD(x) ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD)) #define BIT_GET_TXCMD_TIMEOUT_PERIOD(x) \ (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) & \ BIT_MASK_TXCMD_TIMEOUT_PERIOD) #define BIT_SET_TXCMD_TIMEOUT_PERIOD(x, v) \ (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD(x) | BIT_TXCMD_TIMEOUT_PERIOD(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_MISC_CTRL (Offset 0x0577) */ #define BIT_DIS_MARK_TSF_US BIT(7) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_MISC_CTRL (Offset 0x0577) */ #define BIT_DIS_MARK_TSF_US_V2 BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_MISC_CTRL (Offset 0x0577) */ #define BIT_EN_TSFAUTO_SYNC BIT(6) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MISC_CTRL (Offset 0x0577) */ #define BIT_AUTO_SYNC_BY_TBTT BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MISC_CTRL (Offset 0x0577) */ #define BIT_DIS_TRX_CAL_BCN BIT(5) #define BIT_DIS_TX_CAL_TBTT BIT(4) #define BIT_EN_FREECNT BIT(3) #define BIT_BCN_AGGRESSION BIT(2) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MISC_CTRL (Offset 0x0577) */ #define BIT_DIS_SECONDARY_CCA_80M BIT(2) #define BIT_DIS_SECONDARY_CCA_40M BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MISC_CTRL (Offset 0x0577) */ #define BIT_SHIFT_DIS_SECONDARY_CCA 0 #define BIT_MASK_DIS_SECONDARY_CCA 0x3 #define BIT_DIS_SECONDARY_CCA(x) \ (((x) & BIT_MASK_DIS_SECONDARY_CCA) << BIT_SHIFT_DIS_SECONDARY_CCA) #define BITS_DIS_SECONDARY_CCA \ (BIT_MASK_DIS_SECONDARY_CCA << BIT_SHIFT_DIS_SECONDARY_CCA) #define BIT_CLEAR_DIS_SECONDARY_CCA(x) ((x) & (~BITS_DIS_SECONDARY_CCA)) #define BIT_GET_DIS_SECONDARY_CCA(x) \ (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA) & BIT_MASK_DIS_SECONDARY_CCA) #define BIT_SET_DIS_SECONDARY_CCA(x, v) \ (BIT_CLEAR_DIS_SECONDARY_CCA(x) | BIT_DIS_SECONDARY_CCA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MISC_CTRL (Offset 0x0577) */ #define BIT_DIS_SECONDARY_CCA_20M BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ #define BIT_CLI1_DIS_RX_BSSID_FIT BIT(6) #define BIT_CLI1_DIS_TSF_UDT BIT(4) #define BIT_CLI1_EN_BCN_FUNCTION BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ #define BIT_CLI1_EN_RXBCN_RPT BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ #define BIT_CLI1_EN_BCN_RPT BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ #define BIT_CLI1_ENP2P_CTWINDOW BIT(1) #define BIT_CLI1_ENP2P_BCNQ_AREA BIT(0) /* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ #define BIT_CLI2_DIS_RX_BSSID_FIT BIT(6) #define BIT_CLI2_DIS_TSF_UDT BIT(4) #define BIT_CLI2_EN_BCN_FUNCTION BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ #define BIT_CLI2_EN_RXBCN_RPT BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ #define BIT_CLI2_EN_BCN_RPT BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ #define BIT_CLI2_ENP2P_CTWINDOW BIT(1) #define BIT_CLI2_ENP2P_BCNQ_AREA BIT(0) /* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ #define BIT_CLI3_DIS_RX_BSSID_FIT BIT(6) #define BIT_CLI3_DIS_TSF_UDT BIT(4) #define BIT_CLI3_EN_BCN_FUNCTION BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ #define BIT_CLI3_EN_RXBCN_RPT BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ #define BIT_CLI3_EN_BCN_RPT BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ #define BIT_CLI3_ENP2P_CTWINDOW BIT(1) #define BIT_CLI3_ENP2P_BCNQ_AREA BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_EXTEND_CTRL (Offset 0x057B) */ #define BIT_EN_TSFBIT32_RST_P2P2 BIT(5) #define BIT_EN_TSFBIT32_RST_P2P1 BIT(4) #define BIT_SHIFT_PORT_SEL 0 #define BIT_MASK_PORT_SEL 0x7 #define BIT_PORT_SEL(x) (((x) & BIT_MASK_PORT_SEL) << BIT_SHIFT_PORT_SEL) #define BITS_PORT_SEL (BIT_MASK_PORT_SEL << BIT_SHIFT_PORT_SEL) #define BIT_CLEAR_PORT_SEL(x) ((x) & (~BITS_PORT_SEL)) #define BIT_GET_PORT_SEL(x) (((x) >> BIT_SHIFT_PORT_SEL) & BIT_MASK_PORT_SEL) #define BIT_SET_PORT_SEL(x, v) (BIT_CLEAR_PORT_SEL(x) | BIT_PORT_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */ #define BIT_P2P1_SPEC_POWER_STATE BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */ #define BIT_P2P1_SPEC_CTWINDOW_ON BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */ #define BIT_P2P1_SPEC_BCN_AREA_ON BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */ #define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX BIT(4) #define BIT_P2P1_SPEC_NOA1_OFF_PERIOD BIT(3) #define BIT_P2P1_SPEC_FORCE_DOZE1 BIT(2) #define BIT_P2P1_SPEC_NOA0_OFF_PERIOD BIT(1) #define BIT_P2P1_SPEC_FORCE_DOZE0 BIT(0) /* 2 REG_P2PPS1_STATE (Offset 0x057D) */ #define BIT_P2P1_POWER_STATE BIT(7) #define BIT_P2P1_CTWINDOW_ON BIT(6) #define BIT_P2P1_BEACON_AREA_ON BIT(5) #define BIT_P2P1_CTWIN_EARLY_DISTX BIT(4) #define BIT_P2P1_NOA1_OFF_PERIOD BIT(3) #define BIT_P2P1_FORCE_DOZE1 BIT(2) #define BIT_P2P1_NOA0_OFF_PERIOD BIT(1) #define BIT_P2P1_FORCE_DOZE0 BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */ #define BIT_P2P2_SPEC_POWER_STATE BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */ #define BIT_P2P2_SPEC_CTWINDOW_ON BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */ #define BIT_P2P2_SPEC_BCN_AREA_ON BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */ #define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX BIT(4) #define BIT_P2P2_SPEC_NOA1_OFF_PERIOD BIT(3) #define BIT_P2P2_SPEC_FORCE_DOZE1 BIT(2) #define BIT_P2P2_SPEC_NOA0_OFF_PERIOD BIT(1) #define BIT_P2P2_SPEC_FORCE_DOZE0 BIT(0) /* 2 REG_P2PPS2_STATE (Offset 0x057F) */ #define BIT_P2P2_POWER_STATE BIT(7) #define BIT_P2P2_CTWINDOW_ON BIT(6) #define BIT_P2P2_BEACON_AREA_ON BIT(5) #define BIT_P2P2_CTWIN_EARLY_DISTX BIT(4) #define BIT_P2P2_NOA1_OFF_PERIOD BIT(3) #define BIT_P2P2_FORCE_DOZE1 BIT(2) #define BIT_P2P2_NOA0_OFF_PERIOD BIT(1) #define BIT_P2P2_FORCE_DOZE0 BIT(0) #define BIT_SHIFT_EARLY_128US 0 #define BIT_MASK_EARLY_128US 0x7 #define BIT_EARLY_128US(x) \ (((x) & BIT_MASK_EARLY_128US) << BIT_SHIFT_EARLY_128US) #define BITS_EARLY_128US (BIT_MASK_EARLY_128US << BIT_SHIFT_EARLY_128US) #define BIT_CLEAR_EARLY_128US(x) ((x) & (~BITS_EARLY_128US)) #define BIT_GET_EARLY_128US(x) \ (((x) >> BIT_SHIFT_EARLY_128US) & BIT_MASK_EARLY_128US) #define BIT_SET_EARLY_128US(x, v) \ (BIT_CLEAR_EARLY_128US(x) | BIT_EARLY_128US(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PS_TIMER (Offset 0x0580) */ #define BIT_SHIFT_PSTIMER 5 #define BIT_MASK_PSTIMER 0x7ffffff #define BIT_PSTIMER(x) (((x) & BIT_MASK_PSTIMER) << BIT_SHIFT_PSTIMER) #define BITS_PSTIMER (BIT_MASK_PSTIMER << BIT_SHIFT_PSTIMER) #define BIT_CLEAR_PSTIMER(x) ((x) & (~BITS_PSTIMER)) #define BIT_GET_PSTIMER(x) (((x) >> BIT_SHIFT_PSTIMER) & BIT_MASK_PSTIMER) #define BIT_SET_PSTIMER(x, v) (BIT_CLEAR_PSTIMER(x) | BIT_PSTIMER(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_PS_TIMER0 (Offset 0x0580) */ #define BIT_SHIFT_PSTIMER0_INT 5 #define BIT_MASK_PSTIMER0_INT 0x7ffffff #define BIT_PSTIMER0_INT(x) \ (((x) & BIT_MASK_PSTIMER0_INT) << BIT_SHIFT_PSTIMER0_INT) #define BITS_PSTIMER0_INT (BIT_MASK_PSTIMER0_INT << BIT_SHIFT_PSTIMER0_INT) #define BIT_CLEAR_PSTIMER0_INT(x) ((x) & (~BITS_PSTIMER0_INT)) #define BIT_GET_PSTIMER0_INT(x) \ (((x) >> BIT_SHIFT_PSTIMER0_INT) & BIT_MASK_PSTIMER0_INT) #define BIT_SET_PSTIMER0_INT(x, v) \ (BIT_CLEAR_PSTIMER0_INT(x) | BIT_PSTIMER0_INT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TIMER0 (Offset 0x0584) */ #define BIT_SHIFT_TIMER0_INT 5 #define BIT_MASK_TIMER0_INT 0x7ffffff #define BIT_TIMER0_INT(x) (((x) & BIT_MASK_TIMER0_INT) << BIT_SHIFT_TIMER0_INT) #define BITS_TIMER0_INT (BIT_MASK_TIMER0_INT << BIT_SHIFT_TIMER0_INT) #define BIT_CLEAR_TIMER0_INT(x) ((x) & (~BITS_TIMER0_INT)) #define BIT_GET_TIMER0_INT(x) \ (((x) >> BIT_SHIFT_TIMER0_INT) & BIT_MASK_TIMER0_INT) #define BIT_SET_TIMER0_INT(x, v) (BIT_CLEAR_TIMER0_INT(x) | BIT_TIMER0_INT(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_PS_TIMER1 (Offset 0x0584) */ #define BIT_SHIFT_PSTIMER1_INT 5 #define BIT_MASK_PSTIMER1_INT 0x7ffffff #define BIT_PSTIMER1_INT(x) \ (((x) & BIT_MASK_PSTIMER1_INT) << BIT_SHIFT_PSTIMER1_INT) #define BITS_PSTIMER1_INT (BIT_MASK_PSTIMER1_INT << BIT_SHIFT_PSTIMER1_INT) #define BIT_CLEAR_PSTIMER1_INT(x) ((x) & (~BITS_PSTIMER1_INT)) #define BIT_GET_PSTIMER1_INT(x) \ (((x) >> BIT_SHIFT_PSTIMER1_INT) & BIT_MASK_PSTIMER1_INT) #define BIT_SET_PSTIMER1_INT(x, v) \ (BIT_CLEAR_PSTIMER1_INT(x) | BIT_PSTIMER1_INT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TIMER1 (Offset 0x0588) */ #define BIT_SHIFT_TIMER1_INT 5 #define BIT_MASK_TIMER1_INT 0x7ffffff #define BIT_TIMER1_INT(x) (((x) & BIT_MASK_TIMER1_INT) << BIT_SHIFT_TIMER1_INT) #define BITS_TIMER1_INT (BIT_MASK_TIMER1_INT << BIT_SHIFT_TIMER1_INT) #define BIT_CLEAR_TIMER1_INT(x) ((x) & (~BITS_TIMER1_INT)) #define BIT_GET_TIMER1_INT(x) \ (((x) >> BIT_SHIFT_TIMER1_INT) & BIT_MASK_TIMER1_INT) #define BIT_SET_TIMER1_INT(x, v) (BIT_CLEAR_TIMER1_INT(x) | BIT_TIMER1_INT(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_PS_TIMER2 (Offset 0x0588) */ #define BIT_SHIFT_PSTIMER2_INT 5 #define BIT_MASK_PSTIMER2_INT 0x7ffffff #define BIT_PSTIMER2_INT(x) \ (((x) & BIT_MASK_PSTIMER2_INT) << BIT_SHIFT_PSTIMER2_INT) #define BITS_PSTIMER2_INT (BIT_MASK_PSTIMER2_INT << BIT_SHIFT_PSTIMER2_INT) #define BIT_CLEAR_PSTIMER2_INT(x) ((x) & (~BITS_PSTIMER2_INT)) #define BIT_GET_PSTIMER2_INT(x) \ (((x) >> BIT_SHIFT_PSTIMER2_INT) & BIT_MASK_PSTIMER2_INT) #define BIT_SET_PSTIMER2_INT(x, v) \ (BIT_CLEAR_PSTIMER2_INT(x) | BIT_PSTIMER2_INT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TBTT_CTN_AREA (Offset 0x058C) */ #define BIT_SHIFT_TBTT_CTN_AREA 0 #define BIT_MASK_TBTT_CTN_AREA 0xff #define BIT_TBTT_CTN_AREA(x) \ (((x) & BIT_MASK_TBTT_CTN_AREA) << BIT_SHIFT_TBTT_CTN_AREA) #define BITS_TBTT_CTN_AREA (BIT_MASK_TBTT_CTN_AREA << BIT_SHIFT_TBTT_CTN_AREA) #define BIT_CLEAR_TBTT_CTN_AREA(x) ((x) & (~BITS_TBTT_CTN_AREA)) #define BIT_GET_TBTT_CTN_AREA(x) \ (((x) >> BIT_SHIFT_TBTT_CTN_AREA) & BIT_MASK_TBTT_CTN_AREA) #define BIT_SET_TBTT_CTN_AREA(x, v) \ (BIT_CLEAR_TBTT_CTN_AREA(x) | BIT_TBTT_CTN_AREA(v)) /* 2 REG_FORCE_BCN_IFS (Offset 0x058E) */ #define BIT_SHIFT_FORCE_BCN_IFS 0 #define BIT_MASK_FORCE_BCN_IFS 0xff #define BIT_FORCE_BCN_IFS(x) \ (((x) & BIT_MASK_FORCE_BCN_IFS) << BIT_SHIFT_FORCE_BCN_IFS) #define BITS_FORCE_BCN_IFS (BIT_MASK_FORCE_BCN_IFS << BIT_SHIFT_FORCE_BCN_IFS) #define BIT_CLEAR_FORCE_BCN_IFS(x) ((x) & (~BITS_FORCE_BCN_IFS)) #define BIT_GET_FORCE_BCN_IFS(x) \ (((x) >> BIT_SHIFT_FORCE_BCN_IFS) & BIT_MASK_FORCE_BCN_IFS) #define BIT_SET_FORCE_BCN_IFS(x, v) \ (BIT_CLEAR_FORCE_BCN_IFS(x) | BIT_FORCE_BCN_IFS(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_TXOP_MIN (Offset 0x0590) */ #define BIT_NAV_BLK_HGQ BIT(15) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXOP_MIN (Offset 0x0590) */ #define BIT_HIQ_NAV_BREAK_EN BIT(15) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_TXOP_MIN (Offset 0x0590) */ #define BIT_NAV_BLK_MGQ BIT(14) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXOP_MIN (Offset 0x0590) */ #define BIT_MGQ_NAV_BREAK_EN BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TXOP_MIN (Offset 0x0590) */ #define BIT_SHIFT_TXOP_MIN 0 #define BIT_MASK_TXOP_MIN 0x3fff #define BIT_TXOP_MIN(x) (((x) & BIT_MASK_TXOP_MIN) << BIT_SHIFT_TXOP_MIN) #define BITS_TXOP_MIN (BIT_MASK_TXOP_MIN << BIT_SHIFT_TXOP_MIN) #define BIT_CLEAR_TXOP_MIN(x) ((x) & (~BITS_TXOP_MIN)) #define BIT_GET_TXOP_MIN(x) (((x) >> BIT_SHIFT_TXOP_MIN) & BIT_MASK_TXOP_MIN) #define BIT_SET_TXOP_MIN(x, v) (BIT_CLEAR_TXOP_MIN(x) | BIT_TXOP_MIN(v)) /* 2 REG_PRE_BKF_TIME (Offset 0x0592) */ #define BIT_SHIFT_PRE_BKF_TIME 0 #define BIT_MASK_PRE_BKF_TIME 0xff #define BIT_PRE_BKF_TIME(x) \ (((x) & BIT_MASK_PRE_BKF_TIME) << BIT_SHIFT_PRE_BKF_TIME) #define BITS_PRE_BKF_TIME (BIT_MASK_PRE_BKF_TIME << BIT_SHIFT_PRE_BKF_TIME) #define BIT_CLEAR_PRE_BKF_TIME(x) ((x) & (~BITS_PRE_BKF_TIME)) #define BIT_GET_PRE_BKF_TIME(x) \ (((x) >> BIT_SHIFT_PRE_BKF_TIME) & BIT_MASK_PRE_BKF_TIME) #define BIT_SET_PRE_BKF_TIME(x, v) \ (BIT_CLEAR_PRE_BKF_TIME(x) | BIT_PRE_BKF_TIME(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ #define BIT_NOPKT_END_RTSMF BIT(7) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ #define BIT_TBTT_RETRY BIT(4) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ #define BIT_TXOP_FAIL_BREAK BIT(3) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ #define BIT_TXFAIL_BREACK_TXOP_EN BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ #define BIT_DTIM_BYPASS BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ #define BIT_RTS_NAV_TXOP BIT(1) #define BIT_NOT_CROSS_TXOP BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_TBTT_INT_SHIFT_CLI0 (Offset 0x0594) */ #define BIT_TBTT_INT_SHIFT_DIR_CLI0 BIT(7) #define BIT_SHIFT_TBTT_INT_SHIFT_CLI0 0 #define BIT_MASK_TBTT_INT_SHIFT_CLI0 0x7f #define BIT_TBTT_INT_SHIFT_CLI0(x) \ (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI0) << BIT_SHIFT_TBTT_INT_SHIFT_CLI0) #define BITS_TBTT_INT_SHIFT_CLI0 \ (BIT_MASK_TBTT_INT_SHIFT_CLI0 << BIT_SHIFT_TBTT_INT_SHIFT_CLI0) #define BIT_CLEAR_TBTT_INT_SHIFT_CLI0(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI0)) #define BIT_GET_TBTT_INT_SHIFT_CLI0(x) \ (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI0) & BIT_MASK_TBTT_INT_SHIFT_CLI0) #define BIT_SET_TBTT_INT_SHIFT_CLI0(x, v) \ (BIT_CLEAR_TBTT_INT_SHIFT_CLI0(x) | BIT_TBTT_INT_SHIFT_CLI0(v)) /* 2 REG_TBTT_INT_SHIFT_CLI1 (Offset 0x0595) */ #define BIT_TBTT_INT_SHIFT_DIR_CLI1 BIT(7) #define BIT_SHIFT_TBTT_INT_SHIFT_CLI1 0 #define BIT_MASK_TBTT_INT_SHIFT_CLI1 0x7f #define BIT_TBTT_INT_SHIFT_CLI1(x) \ (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1) << BIT_SHIFT_TBTT_INT_SHIFT_CLI1) #define BITS_TBTT_INT_SHIFT_CLI1 \ (BIT_MASK_TBTT_INT_SHIFT_CLI1 << BIT_SHIFT_TBTT_INT_SHIFT_CLI1) #define BIT_CLEAR_TBTT_INT_SHIFT_CLI1(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI1)) #define BIT_GET_TBTT_INT_SHIFT_CLI1(x) \ (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1) & BIT_MASK_TBTT_INT_SHIFT_CLI1) #define BIT_SET_TBTT_INT_SHIFT_CLI1(x, v) \ (BIT_CLEAR_TBTT_INT_SHIFT_CLI1(x) | BIT_TBTT_INT_SHIFT_CLI1(v)) /* 2 REG_TBTT_INT_SHIFT_CLI2 (Offset 0x0596) */ #define BIT_TBTT_INT_SHIFT_DIR_CLI2 BIT(7) #define BIT_SHIFT_TBTT_INT_SHIFT_CLI2 0 #define BIT_MASK_TBTT_INT_SHIFT_CLI2 0x7f #define BIT_TBTT_INT_SHIFT_CLI2(x) \ (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2) << BIT_SHIFT_TBTT_INT_SHIFT_CLI2) #define BITS_TBTT_INT_SHIFT_CLI2 \ (BIT_MASK_TBTT_INT_SHIFT_CLI2 << BIT_SHIFT_TBTT_INT_SHIFT_CLI2) #define BIT_CLEAR_TBTT_INT_SHIFT_CLI2(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI2)) #define BIT_GET_TBTT_INT_SHIFT_CLI2(x) \ (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2) & BIT_MASK_TBTT_INT_SHIFT_CLI2) #define BIT_SET_TBTT_INT_SHIFT_CLI2(x, v) \ (BIT_CLEAR_TBTT_INT_SHIFT_CLI2(x) | BIT_TBTT_INT_SHIFT_CLI2(v)) /* 2 REG_TBTT_INT_SHIFT_CLI3 (Offset 0x0597) */ #define BIT_TBTT_INT_SHIFT_DIR_CLI3 BIT(7) #define BIT_SHIFT_TBTT_INT_SHIFT_CLI3 0 #define BIT_MASK_TBTT_INT_SHIFT_CLI3 0x7f #define BIT_TBTT_INT_SHIFT_CLI3(x) \ (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3) << BIT_SHIFT_TBTT_INT_SHIFT_CLI3) #define BITS_TBTT_INT_SHIFT_CLI3 \ (BIT_MASK_TBTT_INT_SHIFT_CLI3 << BIT_SHIFT_TBTT_INT_SHIFT_CLI3) #define BIT_CLEAR_TBTT_INT_SHIFT_CLI3(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI3)) #define BIT_GET_TBTT_INT_SHIFT_CLI3(x) \ (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3) & BIT_MASK_TBTT_INT_SHIFT_CLI3) #define BIT_SET_TBTT_INT_SHIFT_CLI3(x, v) \ (BIT_CLEAR_TBTT_INT_SHIFT_CLI3(x) | BIT_TBTT_INT_SHIFT_CLI3(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_RX_TBTT_SHIFT_V1 (Offset 0x0598) */ #define BIT_RX_TBTT_SHIFT_RW_FLAG_V1 BIT(31) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_TBTT_INT_SHIFT_ENABLE (Offset 0x0598) */ #define BIT_BCNERR_CNT_EN BIT(20) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_RX_TBTT_SHIFT_V1 (Offset 0x0598) */ #define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1 16 #define BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1 0xfff #define BIT_RX_TBTT_SHIFT_OFFSET_V1(x) \ (((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1) \ << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1) #define BITS_RX_TBTT_SHIFT_OFFSET_V1 \ (BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1 << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1) #define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1(x) \ ((x) & (~BITS_RX_TBTT_SHIFT_OFFSET_V1)) #define BIT_GET_RX_TBTT_SHIFT_OFFSET_V1(x) \ (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1) & \ BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1) #define BIT_SET_RX_TBTT_SHIFT_OFFSET_V1(x, v) \ (BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1(x) | BIT_RX_TBTT_SHIFT_OFFSET_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_TBTT_INT_SHIFT_ENABLE (Offset 0x0598) */ #define BIT_CHANGE_POW_BCN_AREA BIT(9) #define BIT_SHIFT_TXPAUSE1 8 #define BIT_MASK_TXPAUSE1 0xff #define BIT_TXPAUSE1(x) (((x) & BIT_MASK_TXPAUSE1) << BIT_SHIFT_TXPAUSE1) #define BITS_TXPAUSE1 (BIT_MASK_TXPAUSE1 << BIT_SHIFT_TXPAUSE1) #define BIT_CLEAR_TXPAUSE1(x) ((x) & (~BITS_TXPAUSE1)) #define BIT_GET_TXPAUSE1(x) (((x) >> BIT_SHIFT_TXPAUSE1) & BIT_MASK_TXPAUSE1) #define BIT_SET_TXPAUSE1(x, v) (BIT_CLEAR_TXPAUSE1(x) | BIT_TXPAUSE1(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_RX_TBTT_SHIFT_V1 (Offset 0x0598) */ #define BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1 8 #define BIT_MASK_RX_TBTT_SHIFT_SEL_V1 0x7 #define BIT_RX_TBTT_SHIFT_SEL_V1(x) \ (((x) & BIT_MASK_RX_TBTT_SHIFT_SEL_V1) \ << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1) #define BITS_RX_TBTT_SHIFT_SEL_V1 \ (BIT_MASK_RX_TBTT_SHIFT_SEL_V1 << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1) #define BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1(x) ((x) & (~BITS_RX_TBTT_SHIFT_SEL_V1)) #define BIT_GET_RX_TBTT_SHIFT_SEL_V1(x) \ (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1) & \ BIT_MASK_RX_TBTT_SHIFT_SEL_V1) #define BIT_SET_RX_TBTT_SHIFT_SEL_V1(x, v) \ (BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1(x) | BIT_RX_TBTT_SHIFT_SEL_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_TBTT_INT_SHIFT_ENABLE (Offset 0x0598) */ #define BIT_EN_TBTT_RTY BIT(1) #define BIT_TBTT_INT_SHIFT_ENABLE BIT(0) #define BIT_SHIFT_BCN_ELY_ADJ 0 #define BIT_MASK_BCN_ELY_ADJ 0xffff #define BIT_BCN_ELY_ADJ(x) \ (((x) & BIT_MASK_BCN_ELY_ADJ) << BIT_SHIFT_BCN_ELY_ADJ) #define BITS_BCN_ELY_ADJ (BIT_MASK_BCN_ELY_ADJ << BIT_SHIFT_BCN_ELY_ADJ) #define BIT_CLEAR_BCN_ELY_ADJ(x) ((x) & (~BITS_BCN_ELY_ADJ)) #define BIT_GET_BCN_ELY_ADJ(x) \ (((x) >> BIT_SHIFT_BCN_ELY_ADJ) & BIT_MASK_BCN_ELY_ADJ) #define BIT_SET_BCN_ELY_ADJ(x, v) \ (BIT_CLEAR_BCN_ELY_ADJ(x) | BIT_BCN_ELY_ADJ(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_ATIMWND2 (Offset 0x05A0) */ #define BIT_SHIFT_ATIMWND2 0 #define BIT_MASK_ATIMWND2 0xff #define BIT_ATIMWND2(x) (((x) & BIT_MASK_ATIMWND2) << BIT_SHIFT_ATIMWND2) #define BITS_ATIMWND2 (BIT_MASK_ATIMWND2 << BIT_SHIFT_ATIMWND2) #define BIT_CLEAR_ATIMWND2(x) ((x) & (~BITS_ATIMWND2)) #define BIT_GET_ATIMWND2(x) (((x) >> BIT_SHIFT_ATIMWND2) & BIT_MASK_ATIMWND2) #define BIT_SET_ATIMWND2(x, v) (BIT_CLEAR_ATIMWND2(x) | BIT_ATIMWND2(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_ATIMWND_GROUP1 (Offset 0x05A0) */ #define BIT_SHIFT_ATIMWND_GROUP1 0 #define BIT_MASK_ATIMWND_GROUP1 0xff #define BIT_ATIMWND_GROUP1(x) \ (((x) & BIT_MASK_ATIMWND_GROUP1) << BIT_SHIFT_ATIMWND_GROUP1) #define BITS_ATIMWND_GROUP1 \ (BIT_MASK_ATIMWND_GROUP1 << BIT_SHIFT_ATIMWND_GROUP1) #define BIT_CLEAR_ATIMWND_GROUP1(x) ((x) & (~BITS_ATIMWND_GROUP1)) #define BIT_GET_ATIMWND_GROUP1(x) \ (((x) >> BIT_SHIFT_ATIMWND_GROUP1) & BIT_MASK_ATIMWND_GROUP1) #define BIT_SET_ATIMWND_GROUP1(x, v) \ (BIT_CLEAR_ATIMWND_GROUP1(x) | BIT_ATIMWND_GROUP1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_ATIMWND3 (Offset 0x05A1) */ #define BIT_SHIFT_ATIMWND3 0 #define BIT_MASK_ATIMWND3 0xff #define BIT_ATIMWND3(x) (((x) & BIT_MASK_ATIMWND3) << BIT_SHIFT_ATIMWND3) #define BITS_ATIMWND3 (BIT_MASK_ATIMWND3 << BIT_SHIFT_ATIMWND3) #define BIT_CLEAR_ATIMWND3(x) ((x) & (~BITS_ATIMWND3)) #define BIT_GET_ATIMWND3(x) (((x) >> BIT_SHIFT_ATIMWND3) & BIT_MASK_ATIMWND3) #define BIT_SET_ATIMWND3(x, v) (BIT_CLEAR_ATIMWND3(x) | BIT_ATIMWND3(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_ATIMWND_GROUP2 (Offset 0x05A1) */ #define BIT_SHIFT_ATIMWND_GROUP2 0 #define BIT_MASK_ATIMWND_GROUP2 0xff #define BIT_ATIMWND_GROUP2(x) \ (((x) & BIT_MASK_ATIMWND_GROUP2) << BIT_SHIFT_ATIMWND_GROUP2) #define BITS_ATIMWND_GROUP2 \ (BIT_MASK_ATIMWND_GROUP2 << BIT_SHIFT_ATIMWND_GROUP2) #define BIT_CLEAR_ATIMWND_GROUP2(x) ((x) & (~BITS_ATIMWND_GROUP2)) #define BIT_GET_ATIMWND_GROUP2(x) \ (((x) >> BIT_SHIFT_ATIMWND_GROUP2) & BIT_MASK_ATIMWND_GROUP2) #define BIT_SET_ATIMWND_GROUP2(x, v) \ (BIT_CLEAR_ATIMWND_GROUP2(x) | BIT_ATIMWND_GROUP2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_ATIMWND4 (Offset 0x05A2) */ #define BIT_SHIFT_ATIMWND4 0 #define BIT_MASK_ATIMWND4 0xff #define BIT_ATIMWND4(x) (((x) & BIT_MASK_ATIMWND4) << BIT_SHIFT_ATIMWND4) #define BITS_ATIMWND4 (BIT_MASK_ATIMWND4 << BIT_SHIFT_ATIMWND4) #define BIT_CLEAR_ATIMWND4(x) ((x) & (~BITS_ATIMWND4)) #define BIT_GET_ATIMWND4(x) (((x) >> BIT_SHIFT_ATIMWND4) & BIT_MASK_ATIMWND4) #define BIT_SET_ATIMWND4(x, v) (BIT_CLEAR_ATIMWND4(x) | BIT_ATIMWND4(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_ATIMWND_GROUP3 (Offset 0x05A2) */ #define BIT_SHIFT_ATIMWND_GROUP3 0 #define BIT_MASK_ATIMWND_GROUP3 0xff #define BIT_ATIMWND_GROUP3(x) \ (((x) & BIT_MASK_ATIMWND_GROUP3) << BIT_SHIFT_ATIMWND_GROUP3) #define BITS_ATIMWND_GROUP3 \ (BIT_MASK_ATIMWND_GROUP3 << BIT_SHIFT_ATIMWND_GROUP3) #define BIT_CLEAR_ATIMWND_GROUP3(x) ((x) & (~BITS_ATIMWND_GROUP3)) #define BIT_GET_ATIMWND_GROUP3(x) \ (((x) >> BIT_SHIFT_ATIMWND_GROUP3) & BIT_MASK_ATIMWND_GROUP3) #define BIT_SET_ATIMWND_GROUP3(x, v) \ (BIT_CLEAR_ATIMWND_GROUP3(x) | BIT_ATIMWND_GROUP3(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_ATIMWND5 (Offset 0x05A3) */ #define BIT_SHIFT_ATIMWND5 0 #define BIT_MASK_ATIMWND5 0xff #define BIT_ATIMWND5(x) (((x) & BIT_MASK_ATIMWND5) << BIT_SHIFT_ATIMWND5) #define BITS_ATIMWND5 (BIT_MASK_ATIMWND5 << BIT_SHIFT_ATIMWND5) #define BIT_CLEAR_ATIMWND5(x) ((x) & (~BITS_ATIMWND5)) #define BIT_GET_ATIMWND5(x) (((x) >> BIT_SHIFT_ATIMWND5) & BIT_MASK_ATIMWND5) #define BIT_SET_ATIMWND5(x, v) (BIT_CLEAR_ATIMWND5(x) | BIT_ATIMWND5(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_ATIMWND_GROUP4 (Offset 0x05A3) */ #define BIT_SHIFT_ATIMWND_GROUP4 0 #define BIT_MASK_ATIMWND_GROUP4 0xff #define BIT_ATIMWND_GROUP4(x) \ (((x) & BIT_MASK_ATIMWND_GROUP4) << BIT_SHIFT_ATIMWND_GROUP4) #define BITS_ATIMWND_GROUP4 \ (BIT_MASK_ATIMWND_GROUP4 << BIT_SHIFT_ATIMWND_GROUP4) #define BIT_CLEAR_ATIMWND_GROUP4(x) ((x) & (~BITS_ATIMWND_GROUP4)) #define BIT_GET_ATIMWND_GROUP4(x) \ (((x) >> BIT_SHIFT_ATIMWND_GROUP4) & BIT_MASK_ATIMWND_GROUP4) #define BIT_SET_ATIMWND_GROUP4(x, v) \ (BIT_CLEAR_ATIMWND_GROUP4(x) | BIT_ATIMWND_GROUP4(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_ATIMWND6 (Offset 0x05A4) */ #define BIT_SHIFT_ATIMWND6 0 #define BIT_MASK_ATIMWND6 0xff #define BIT_ATIMWND6(x) (((x) & BIT_MASK_ATIMWND6) << BIT_SHIFT_ATIMWND6) #define BITS_ATIMWND6 (BIT_MASK_ATIMWND6 << BIT_SHIFT_ATIMWND6) #define BIT_CLEAR_ATIMWND6(x) ((x) & (~BITS_ATIMWND6)) #define BIT_GET_ATIMWND6(x) (((x) >> BIT_SHIFT_ATIMWND6) & BIT_MASK_ATIMWND6) #define BIT_SET_ATIMWND6(x, v) (BIT_CLEAR_ATIMWND6(x) | BIT_ATIMWND6(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_DTIM_COUNT_GROUP1 (Offset 0x05A4) */ #define BIT_SHIFT_DTIM_COUNT_GROUP1 0 #define BIT_MASK_DTIM_COUNT_GROUP1 0xff #define BIT_DTIM_COUNT_GROUP1(x) \ (((x) & BIT_MASK_DTIM_COUNT_GROUP1) << BIT_SHIFT_DTIM_COUNT_GROUP1) #define BITS_DTIM_COUNT_GROUP1 \ (BIT_MASK_DTIM_COUNT_GROUP1 << BIT_SHIFT_DTIM_COUNT_GROUP1) #define BIT_CLEAR_DTIM_COUNT_GROUP1(x) ((x) & (~BITS_DTIM_COUNT_GROUP1)) #define BIT_GET_DTIM_COUNT_GROUP1(x) \ (((x) >> BIT_SHIFT_DTIM_COUNT_GROUP1) & BIT_MASK_DTIM_COUNT_GROUP1) #define BIT_SET_DTIM_COUNT_GROUP1(x, v) \ (BIT_CLEAR_DTIM_COUNT_GROUP1(x) | BIT_DTIM_COUNT_GROUP1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_ATIMWND7 (Offset 0x05A5) */ #define BIT_SHIFT_ATIMWND7 0 #define BIT_MASK_ATIMWND7 0xff #define BIT_ATIMWND7(x) (((x) & BIT_MASK_ATIMWND7) << BIT_SHIFT_ATIMWND7) #define BITS_ATIMWND7 (BIT_MASK_ATIMWND7 << BIT_SHIFT_ATIMWND7) #define BIT_CLEAR_ATIMWND7(x) ((x) & (~BITS_ATIMWND7)) #define BIT_GET_ATIMWND7(x) (((x) >> BIT_SHIFT_ATIMWND7) & BIT_MASK_ATIMWND7) #define BIT_SET_ATIMWND7(x, v) (BIT_CLEAR_ATIMWND7(x) | BIT_ATIMWND7(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_DTIM_COUNT_GROUP2 (Offset 0x05A5) */ #define BIT_SHIFT_DTIM_COUNT_GROUP2 0 #define BIT_MASK_DTIM_COUNT_GROUP2 0xff #define BIT_DTIM_COUNT_GROUP2(x) \ (((x) & BIT_MASK_DTIM_COUNT_GROUP2) << BIT_SHIFT_DTIM_COUNT_GROUP2) #define BITS_DTIM_COUNT_GROUP2 \ (BIT_MASK_DTIM_COUNT_GROUP2 << BIT_SHIFT_DTIM_COUNT_GROUP2) #define BIT_CLEAR_DTIM_COUNT_GROUP2(x) ((x) & (~BITS_DTIM_COUNT_GROUP2)) #define BIT_GET_DTIM_COUNT_GROUP2(x) \ (((x) >> BIT_SHIFT_DTIM_COUNT_GROUP2) & BIT_MASK_DTIM_COUNT_GROUP2) #define BIT_SET_DTIM_COUNT_GROUP2(x, v) \ (BIT_CLEAR_DTIM_COUNT_GROUP2(x) | BIT_DTIM_COUNT_GROUP2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_ATIMUGT (Offset 0x05A6) */ #define BIT_SHIFT_ATIM_URGENT 0 #define BIT_MASK_ATIM_URGENT 0xff #define BIT_ATIM_URGENT(x) \ (((x) & BIT_MASK_ATIM_URGENT) << BIT_SHIFT_ATIM_URGENT) #define BITS_ATIM_URGENT (BIT_MASK_ATIM_URGENT << BIT_SHIFT_ATIM_URGENT) #define BIT_CLEAR_ATIM_URGENT(x) ((x) & (~BITS_ATIM_URGENT)) #define BIT_GET_ATIM_URGENT(x) \ (((x) >> BIT_SHIFT_ATIM_URGENT) & BIT_MASK_ATIM_URGENT) #define BIT_SET_ATIM_URGENT(x, v) \ (BIT_CLEAR_ATIM_URGENT(x) | BIT_ATIM_URGENT(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_DTIM_COUNT_GROUP3 (Offset 0x05A6) */ #define BIT_SHIFT_DTIM_COUNT_GROUP3 0 #define BIT_MASK_DTIM_COUNT_GROUP3 0xff #define BIT_DTIM_COUNT_GROUP3(x) \ (((x) & BIT_MASK_DTIM_COUNT_GROUP3) << BIT_SHIFT_DTIM_COUNT_GROUP3) #define BITS_DTIM_COUNT_GROUP3 \ (BIT_MASK_DTIM_COUNT_GROUP3 << BIT_SHIFT_DTIM_COUNT_GROUP3) #define BIT_CLEAR_DTIM_COUNT_GROUP3(x) ((x) & (~BITS_DTIM_COUNT_GROUP3)) #define BIT_GET_DTIM_COUNT_GROUP3(x) \ (((x) >> BIT_SHIFT_DTIM_COUNT_GROUP3) & BIT_MASK_DTIM_COUNT_GROUP3) #define BIT_SET_DTIM_COUNT_GROUP3(x, v) \ (BIT_CLEAR_DTIM_COUNT_GROUP3(x) | BIT_DTIM_COUNT_GROUP3(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_HIQ_NO_LMT_EN (Offset 0x05A7) */ #define BIT_HIQ_NO_LMT_EN_VAP7 BIT(7) #define BIT_HIQ_NO_LMT_EN_VAP6 BIT(6) #define BIT_HIQ_NO_LMT_EN_VAP5 BIT(5) #define BIT_HIQ_NO_LMT_EN_VAP4 BIT(4) #define BIT_HIQ_NO_LMT_EN_VAP3 BIT(3) #define BIT_HIQ_NO_LMT_EN_VAP2 BIT(2) #define BIT_HIQ_NO_LMT_EN_VAP1 BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIQ_NO_LMT_EN (Offset 0x05A7) */ #define BIT_HIQ_NO_LMT_EN_ROOT BIT(0) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_DTIM_COUNT_GROUP4 (Offset 0x05A7) */ #define BIT_SHIFT_DTIM_COUNT_GROUP4 0 #define BIT_MASK_DTIM_COUNT_GROUP4 0xff #define BIT_DTIM_COUNT_GROUP4(x) \ (((x) & BIT_MASK_DTIM_COUNT_GROUP4) << BIT_SHIFT_DTIM_COUNT_GROUP4) #define BITS_DTIM_COUNT_GROUP4 \ (BIT_MASK_DTIM_COUNT_GROUP4 << BIT_SHIFT_DTIM_COUNT_GROUP4) #define BIT_CLEAR_DTIM_COUNT_GROUP4(x) ((x) & (~BITS_DTIM_COUNT_GROUP4)) #define BIT_GET_DTIM_COUNT_GROUP4(x) \ (((x) >> BIT_SHIFT_DTIM_COUNT_GROUP4) & BIT_MASK_DTIM_COUNT_GROUP4) #define BIT_SET_DTIM_COUNT_GROUP4(x, v) \ (BIT_CLEAR_DTIM_COUNT_GROUP4(x) | BIT_DTIM_COUNT_GROUP4(v)) /* 2 REG_HIQ_NO_LMT_EN_V2 (Offset 0x05A8) */ #define BIT_SHIFT_ATIM_CFG_SEL 24 #define BIT_MASK_ATIM_CFG_SEL 0x3 #define BIT_ATIM_CFG_SEL(x) \ (((x) & BIT_MASK_ATIM_CFG_SEL) << BIT_SHIFT_ATIM_CFG_SEL) #define BITS_ATIM_CFG_SEL (BIT_MASK_ATIM_CFG_SEL << BIT_SHIFT_ATIM_CFG_SEL) #define BIT_CLEAR_ATIM_CFG_SEL(x) ((x) & (~BITS_ATIM_CFG_SEL)) #define BIT_GET_ATIM_CFG_SEL(x) \ (((x) >> BIT_SHIFT_ATIM_CFG_SEL) & BIT_MASK_ATIM_CFG_SEL) #define BIT_SET_ATIM_CFG_SEL(x, v) \ (BIT_CLEAR_ATIM_CFG_SEL(x) | BIT_ATIM_CFG_SEL(v)) #define BIT_SHIFT_DIS_ATIM 16 #define BIT_MASK_DIS_ATIM 0xffff #define BIT_DIS_ATIM(x) (((x) & BIT_MASK_DIS_ATIM) << BIT_SHIFT_DIS_ATIM) #define BITS_DIS_ATIM (BIT_MASK_DIS_ATIM << BIT_SHIFT_DIS_ATIM) #define BIT_CLEAR_DIS_ATIM(x) ((x) & (~BITS_DIS_ATIM)) #define BIT_GET_DIS_ATIM(x) (((x) >> BIT_SHIFT_DIS_ATIM) & BIT_MASK_DIS_ATIM) #define BIT_SET_DIS_ATIM(x, v) (BIT_CLEAR_DIS_ATIM(x) | BIT_DIS_ATIM(v)) #define BIT_SHIFT_ATIM_URGENT_V1 16 #define BIT_MASK_ATIM_URGENT_V1 0xff #define BIT_ATIM_URGENT_V1(x) \ (((x) & BIT_MASK_ATIM_URGENT_V1) << BIT_SHIFT_ATIM_URGENT_V1) #define BITS_ATIM_URGENT_V1 \ (BIT_MASK_ATIM_URGENT_V1 << BIT_SHIFT_ATIM_URGENT_V1) #define BIT_CLEAR_ATIM_URGENT_V1(x) ((x) & (~BITS_ATIM_URGENT_V1)) #define BIT_GET_ATIM_URGENT_V1(x) \ (((x) >> BIT_SHIFT_ATIM_URGENT_V1) & BIT_MASK_ATIM_URGENT_V1) #define BIT_SET_ATIM_URGENT_V1(x, v) \ (BIT_CLEAR_ATIM_URGENT_V1(x) | BIT_ATIM_URGENT_V1(v)) #define BIT_SHIFT_BCNERR_PORT_SEL_V1 16 #define BIT_MASK_BCNERR_PORT_SEL_V1 0xf #define BIT_BCNERR_PORT_SEL_V1(x) \ (((x) & BIT_MASK_BCNERR_PORT_SEL_V1) << BIT_SHIFT_BCNERR_PORT_SEL_V1) #define BITS_BCNERR_PORT_SEL_V1 \ (BIT_MASK_BCNERR_PORT_SEL_V1 << BIT_SHIFT_BCNERR_PORT_SEL_V1) #define BIT_CLEAR_BCNERR_PORT_SEL_V1(x) ((x) & (~BITS_BCNERR_PORT_SEL_V1)) #define BIT_GET_BCNERR_PORT_SEL_V1(x) \ (((x) >> BIT_SHIFT_BCNERR_PORT_SEL_V1) & BIT_MASK_BCNERR_PORT_SEL_V1) #define BIT_SET_BCNERR_PORT_SEL_V1(x, v) \ (BIT_CLEAR_BCNERR_PORT_SEL_V1(x) | BIT_BCNERR_PORT_SEL_V1(v)) #define BIT_DIS_NDPA_NAV_CHK BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DTIM_COUNTER_ROOT (Offset 0x05A8) */ #define BIT_SHIFT_DTIM_COUNT_ROOT 0 #define BIT_MASK_DTIM_COUNT_ROOT 0xff #define BIT_DTIM_COUNT_ROOT(x) \ (((x) & BIT_MASK_DTIM_COUNT_ROOT) << BIT_SHIFT_DTIM_COUNT_ROOT) #define BITS_DTIM_COUNT_ROOT \ (BIT_MASK_DTIM_COUNT_ROOT << BIT_SHIFT_DTIM_COUNT_ROOT) #define BIT_CLEAR_DTIM_COUNT_ROOT(x) ((x) & (~BITS_DTIM_COUNT_ROOT)) #define BIT_GET_DTIM_COUNT_ROOT(x) \ (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT) & BIT_MASK_DTIM_COUNT_ROOT) #define BIT_SET_DTIM_COUNT_ROOT(x, v) \ (BIT_CLEAR_DTIM_COUNT_ROOT(x) | BIT_DTIM_COUNT_ROOT(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HIQ_NO_LMT_EN_V2 (Offset 0x05A8) */ #define BIT_SHIFT_MBID_BCNQ_EN 0 #define BIT_MASK_MBID_BCNQ_EN 0xffff #define BIT_MBID_BCNQ_EN(x) \ (((x) & BIT_MASK_MBID_BCNQ_EN) << BIT_SHIFT_MBID_BCNQ_EN) #define BITS_MBID_BCNQ_EN (BIT_MASK_MBID_BCNQ_EN << BIT_SHIFT_MBID_BCNQ_EN) #define BIT_CLEAR_MBID_BCNQ_EN(x) ((x) & (~BITS_MBID_BCNQ_EN)) #define BIT_GET_MBID_BCNQ_EN(x) \ (((x) >> BIT_SHIFT_MBID_BCNQ_EN) & BIT_MASK_MBID_BCNQ_EN) #define BIT_SET_MBID_BCNQ_EN(x, v) \ (BIT_CLEAR_MBID_BCNQ_EN(x) | BIT_MBID_BCNQ_EN(v)) #define BIT_SHIFT_MHDR_NAV_OFFSET 0 #define BIT_MASK_MHDR_NAV_OFFSET 0xff #define BIT_MHDR_NAV_OFFSET(x) \ (((x) & BIT_MASK_MHDR_NAV_OFFSET) << BIT_SHIFT_MHDR_NAV_OFFSET) #define BITS_MHDR_NAV_OFFSET \ (BIT_MASK_MHDR_NAV_OFFSET << BIT_SHIFT_MHDR_NAV_OFFSET) #define BIT_CLEAR_MHDR_NAV_OFFSET(x) ((x) & (~BITS_MHDR_NAV_OFFSET)) #define BIT_GET_MHDR_NAV_OFFSET(x) \ (((x) >> BIT_SHIFT_MHDR_NAV_OFFSET) & BIT_MASK_MHDR_NAV_OFFSET) #define BIT_SET_MHDR_NAV_OFFSET(x, v) \ (BIT_CLEAR_MHDR_NAV_OFFSET(x) | BIT_MHDR_NAV_OFFSET(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DTIM_COUNTER_VAP1 (Offset 0x05A9) */ #define BIT_SHIFT_DTIM_COUNT_VAP1 0 #define BIT_MASK_DTIM_COUNT_VAP1 0xff #define BIT_DTIM_COUNT_VAP1(x) \ (((x) & BIT_MASK_DTIM_COUNT_VAP1) << BIT_SHIFT_DTIM_COUNT_VAP1) #define BITS_DTIM_COUNT_VAP1 \ (BIT_MASK_DTIM_COUNT_VAP1 << BIT_SHIFT_DTIM_COUNT_VAP1) #define BIT_CLEAR_DTIM_COUNT_VAP1(x) ((x) & (~BITS_DTIM_COUNT_VAP1)) #define BIT_GET_DTIM_COUNT_VAP1(x) \ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1) & BIT_MASK_DTIM_COUNT_VAP1) #define BIT_SET_DTIM_COUNT_VAP1(x, v) \ (BIT_CLEAR_DTIM_COUNT_VAP1(x) | BIT_DTIM_COUNT_VAP1(v)) /* 2 REG_DTIM_COUNTER_VAP2 (Offset 0x05AA) */ #define BIT_SHIFT_DTIM_COUNT_VAP2 0 #define BIT_MASK_DTIM_COUNT_VAP2 0xff #define BIT_DTIM_COUNT_VAP2(x) \ (((x) & BIT_MASK_DTIM_COUNT_VAP2) << BIT_SHIFT_DTIM_COUNT_VAP2) #define BITS_DTIM_COUNT_VAP2 \ (BIT_MASK_DTIM_COUNT_VAP2 << BIT_SHIFT_DTIM_COUNT_VAP2) #define BIT_CLEAR_DTIM_COUNT_VAP2(x) ((x) & (~BITS_DTIM_COUNT_VAP2)) #define BIT_GET_DTIM_COUNT_VAP2(x) \ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2) & BIT_MASK_DTIM_COUNT_VAP2) #define BIT_SET_DTIM_COUNT_VAP2(x, v) \ (BIT_CLEAR_DTIM_COUNT_VAP2(x) | BIT_DTIM_COUNT_VAP2(v)) /* 2 REG_DTIM_COUNTER_VAP3 (Offset 0x05AB) */ #define BIT_SHIFT_DTIM_COUNT_VAP3 0 #define BIT_MASK_DTIM_COUNT_VAP3 0xff #define BIT_DTIM_COUNT_VAP3(x) \ (((x) & BIT_MASK_DTIM_COUNT_VAP3) << BIT_SHIFT_DTIM_COUNT_VAP3) #define BITS_DTIM_COUNT_VAP3 \ (BIT_MASK_DTIM_COUNT_VAP3 << BIT_SHIFT_DTIM_COUNT_VAP3) #define BIT_CLEAR_DTIM_COUNT_VAP3(x) ((x) & (~BITS_DTIM_COUNT_VAP3)) #define BIT_GET_DTIM_COUNT_VAP3(x) \ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3) & BIT_MASK_DTIM_COUNT_VAP3) #define BIT_SET_DTIM_COUNT_VAP3(x, v) \ (BIT_CLEAR_DTIM_COUNT_VAP3(x) | BIT_DTIM_COUNT_VAP3(v)) /* 2 REG_DTIM_COUNTER_VAP4 (Offset 0x05AC) */ #define BIT_SHIFT_DTIM_COUNT_VAP4 0 #define BIT_MASK_DTIM_COUNT_VAP4 0xff #define BIT_DTIM_COUNT_VAP4(x) \ (((x) & BIT_MASK_DTIM_COUNT_VAP4) << BIT_SHIFT_DTIM_COUNT_VAP4) #define BITS_DTIM_COUNT_VAP4 \ (BIT_MASK_DTIM_COUNT_VAP4 << BIT_SHIFT_DTIM_COUNT_VAP4) #define BIT_CLEAR_DTIM_COUNT_VAP4(x) ((x) & (~BITS_DTIM_COUNT_VAP4)) #define BIT_GET_DTIM_COUNT_VAP4(x) \ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4) & BIT_MASK_DTIM_COUNT_VAP4) #define BIT_SET_DTIM_COUNT_VAP4(x, v) \ (BIT_CLEAR_DTIM_COUNT_VAP4(x) | BIT_DTIM_COUNT_VAP4(v)) /* 2 REG_DTIM_COUNTER_VAP5 (Offset 0x05AD) */ #define BIT_SHIFT_DTIM_COUNT_VAP5 0 #define BIT_MASK_DTIM_COUNT_VAP5 0xff #define BIT_DTIM_COUNT_VAP5(x) \ (((x) & BIT_MASK_DTIM_COUNT_VAP5) << BIT_SHIFT_DTIM_COUNT_VAP5) #define BITS_DTIM_COUNT_VAP5 \ (BIT_MASK_DTIM_COUNT_VAP5 << BIT_SHIFT_DTIM_COUNT_VAP5) #define BIT_CLEAR_DTIM_COUNT_VAP5(x) ((x) & (~BITS_DTIM_COUNT_VAP5)) #define BIT_GET_DTIM_COUNT_VAP5(x) \ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5) & BIT_MASK_DTIM_COUNT_VAP5) #define BIT_SET_DTIM_COUNT_VAP5(x, v) \ (BIT_CLEAR_DTIM_COUNT_VAP5(x) | BIT_DTIM_COUNT_VAP5(v)) /* 2 REG_DTIM_COUNTER_VAP6 (Offset 0x05AE) */ #define BIT_SHIFT_DTIM_COUNT_VAP6 0 #define BIT_MASK_DTIM_COUNT_VAP6 0xff #define BIT_DTIM_COUNT_VAP6(x) \ (((x) & BIT_MASK_DTIM_COUNT_VAP6) << BIT_SHIFT_DTIM_COUNT_VAP6) #define BITS_DTIM_COUNT_VAP6 \ (BIT_MASK_DTIM_COUNT_VAP6 << BIT_SHIFT_DTIM_COUNT_VAP6) #define BIT_CLEAR_DTIM_COUNT_VAP6(x) ((x) & (~BITS_DTIM_COUNT_VAP6)) #define BIT_GET_DTIM_COUNT_VAP6(x) \ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6) & BIT_MASK_DTIM_COUNT_VAP6) #define BIT_SET_DTIM_COUNT_VAP6(x, v) \ (BIT_CLEAR_DTIM_COUNT_VAP6(x) | BIT_DTIM_COUNT_VAP6(v)) /* 2 REG_DTIM_COUNTER_VAP7 (Offset 0x05AF) */ #define BIT_SHIFT_DTIM_COUNT_VAP7 0 #define BIT_MASK_DTIM_COUNT_VAP7 0xff #define BIT_DTIM_COUNT_VAP7(x) \ (((x) & BIT_MASK_DTIM_COUNT_VAP7) << BIT_SHIFT_DTIM_COUNT_VAP7) #define BITS_DTIM_COUNT_VAP7 \ (BIT_MASK_DTIM_COUNT_VAP7 << BIT_SHIFT_DTIM_COUNT_VAP7) #define BIT_CLEAR_DTIM_COUNT_VAP7(x) ((x) & (~BITS_DTIM_COUNT_VAP7)) #define BIT_GET_DTIM_COUNT_VAP7(x) \ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7) & BIT_MASK_DTIM_COUNT_VAP7) #define BIT_SET_DTIM_COUNT_VAP7(x, v) \ (BIT_CLEAR_DTIM_COUNT_VAP7(x) | BIT_DTIM_COUNT_VAP7(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DIS_ATIM (Offset 0x05B0) */ #define BIT_DIS_ATIM_VAP7 BIT(7) #define BIT_DIS_ATIM_VAP6 BIT(6) #define BIT_DIS_ATIM_VAP5 BIT(5) #define BIT_DIS_ATIM_VAP4 BIT(4) #define BIT_DIS_ATIM_VAP3 BIT(3) #define BIT_DIS_ATIM_VAP2 BIT(2) #define BIT_DIS_ATIM_VAP1 BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_DIS_ATIM (Offset 0x05B0) */ #define BIT_DIS_ATIM_ROOT BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_EARLY_128US (Offset 0x05B1) */ #define BIT_SHIFT_TSFT_SEL_TIMER1 3 #define BIT_MASK_TSFT_SEL_TIMER1 0x7 #define BIT_TSFT_SEL_TIMER1(x) \ (((x) & BIT_MASK_TSFT_SEL_TIMER1) << BIT_SHIFT_TSFT_SEL_TIMER1) #define BITS_TSFT_SEL_TIMER1 \ (BIT_MASK_TSFT_SEL_TIMER1 << BIT_SHIFT_TSFT_SEL_TIMER1) #define BIT_CLEAR_TSFT_SEL_TIMER1(x) ((x) & (~BITS_TSFT_SEL_TIMER1)) #define BIT_GET_TSFT_SEL_TIMER1(x) \ (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1) & BIT_MASK_TSFT_SEL_TIMER1) #define BIT_SET_TSFT_SEL_TIMER1(x, v) \ (BIT_CLEAR_TSFT_SEL_TIMER1(x) | BIT_TSFT_SEL_TIMER1(v)) /* 2 REG_P2PPS1_CTRL (Offset 0x05B2) */ #define BIT_P2P1_CTW_ALLSTASLEEP BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_P2PPS1_CTRL (Offset 0x05B2) */ #define BIT_P2P1_OFF_DISTX_EN BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_P2PPS1_CTRL (Offset 0x05B2) */ #define BIT_P2P1_PWR_MGT_EN BIT(5) #define BIT_P2P1_NOA1_EN BIT(2) #define BIT_P2P1_NOA0_EN BIT(1) /* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */ #define BIT_P2P2_CTW_ALLSTASLEEP BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */ #define BIT_P2P2_OFF_DISTX_EN BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */ #define BIT_P2P2_PWR_MGT_EN BIT(5) #define BIT_P2P2_NOA1_EN BIT(2) #define BIT_P2P2_NOA0_EN BIT(1) /* 2 REG_TIMER0_SRC_SEL (Offset 0x05B4) */ #define BIT_SHIFT_SYNC_CLI_SEL 4 #define BIT_MASK_SYNC_CLI_SEL 0x7 #define BIT_SYNC_CLI_SEL(x) \ (((x) & BIT_MASK_SYNC_CLI_SEL) << BIT_SHIFT_SYNC_CLI_SEL) #define BITS_SYNC_CLI_SEL (BIT_MASK_SYNC_CLI_SEL << BIT_SHIFT_SYNC_CLI_SEL) #define BIT_CLEAR_SYNC_CLI_SEL(x) ((x) & (~BITS_SYNC_CLI_SEL)) #define BIT_GET_SYNC_CLI_SEL(x) \ (((x) >> BIT_SHIFT_SYNC_CLI_SEL) & BIT_MASK_SYNC_CLI_SEL) #define BIT_SET_SYNC_CLI_SEL(x, v) \ (BIT_CLEAR_SYNC_CLI_SEL(x) | BIT_SYNC_CLI_SEL(v)) #define BIT_SHIFT_TSFT_SEL_TIMER0 0 #define BIT_MASK_TSFT_SEL_TIMER0 0x7 #define BIT_TSFT_SEL_TIMER0(x) \ (((x) & BIT_MASK_TSFT_SEL_TIMER0) << BIT_SHIFT_TSFT_SEL_TIMER0) #define BITS_TSFT_SEL_TIMER0 \ (BIT_MASK_TSFT_SEL_TIMER0 << BIT_SHIFT_TSFT_SEL_TIMER0) #define BIT_CLEAR_TSFT_SEL_TIMER0(x) ((x) & (~BITS_TSFT_SEL_TIMER0)) #define BIT_GET_TSFT_SEL_TIMER0(x) \ (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0) & BIT_MASK_TSFT_SEL_TIMER0) #define BIT_SET_TSFT_SEL_TIMER0(x, v) \ (BIT_CLEAR_TSFT_SEL_TIMER0(x) | BIT_TSFT_SEL_TIMER0(v)) /* 2 REG_NOA_UNIT_SEL (Offset 0x05B5) */ #define BIT_SHIFT_NOA_UNIT2_SEL 8 #define BIT_MASK_NOA_UNIT2_SEL 0x7 #define BIT_NOA_UNIT2_SEL(x) \ (((x) & BIT_MASK_NOA_UNIT2_SEL) << BIT_SHIFT_NOA_UNIT2_SEL) #define BITS_NOA_UNIT2_SEL (BIT_MASK_NOA_UNIT2_SEL << BIT_SHIFT_NOA_UNIT2_SEL) #define BIT_CLEAR_NOA_UNIT2_SEL(x) ((x) & (~BITS_NOA_UNIT2_SEL)) #define BIT_GET_NOA_UNIT2_SEL(x) \ (((x) >> BIT_SHIFT_NOA_UNIT2_SEL) & BIT_MASK_NOA_UNIT2_SEL) #define BIT_SET_NOA_UNIT2_SEL(x, v) \ (BIT_CLEAR_NOA_UNIT2_SEL(x) | BIT_NOA_UNIT2_SEL(v)) #define BIT_SHIFT_NOA_UNIT1_SEL 4 #define BIT_MASK_NOA_UNIT1_SEL 0x7 #define BIT_NOA_UNIT1_SEL(x) \ (((x) & BIT_MASK_NOA_UNIT1_SEL) << BIT_SHIFT_NOA_UNIT1_SEL) #define BITS_NOA_UNIT1_SEL (BIT_MASK_NOA_UNIT1_SEL << BIT_SHIFT_NOA_UNIT1_SEL) #define BIT_CLEAR_NOA_UNIT1_SEL(x) ((x) & (~BITS_NOA_UNIT1_SEL)) #define BIT_GET_NOA_UNIT1_SEL(x) \ (((x) >> BIT_SHIFT_NOA_UNIT1_SEL) & BIT_MASK_NOA_UNIT1_SEL) #define BIT_SET_NOA_UNIT1_SEL(x, v) \ (BIT_CLEAR_NOA_UNIT1_SEL(x) | BIT_NOA_UNIT1_SEL(v)) #define BIT_SHIFT_NOA_UNIT0_SEL 0 #define BIT_MASK_NOA_UNIT0_SEL 0x7 #define BIT_NOA_UNIT0_SEL(x) \ (((x) & BIT_MASK_NOA_UNIT0_SEL) << BIT_SHIFT_NOA_UNIT0_SEL) #define BITS_NOA_UNIT0_SEL (BIT_MASK_NOA_UNIT0_SEL << BIT_SHIFT_NOA_UNIT0_SEL) #define BIT_CLEAR_NOA_UNIT0_SEL(x) ((x) & (~BITS_NOA_UNIT0_SEL)) #define BIT_GET_NOA_UNIT0_SEL(x) \ (((x) >> BIT_SHIFT_NOA_UNIT0_SEL) & BIT_MASK_NOA_UNIT0_SEL) #define BIT_SET_NOA_UNIT0_SEL(x, v) \ (BIT_CLEAR_NOA_UNIT0_SEL(x) | BIT_NOA_UNIT0_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_P2POFF_DIS_TXTIME (Offset 0x05B7) */ #define BIT_SHIFT_P2POFF_DIS_TXTIME 0 #define BIT_MASK_P2POFF_DIS_TXTIME 0xff #define BIT_P2POFF_DIS_TXTIME(x) \ (((x) & BIT_MASK_P2POFF_DIS_TXTIME) << BIT_SHIFT_P2POFF_DIS_TXTIME) #define BITS_P2POFF_DIS_TXTIME \ (BIT_MASK_P2POFF_DIS_TXTIME << BIT_SHIFT_P2POFF_DIS_TXTIME) #define BIT_CLEAR_P2POFF_DIS_TXTIME(x) ((x) & (~BITS_P2POFF_DIS_TXTIME)) #define BIT_GET_P2POFF_DIS_TXTIME(x) \ (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME) & BIT_MASK_P2POFF_DIS_TXTIME) #define BIT_SET_P2POFF_DIS_TXTIME(x, v) \ (BIT_CLEAR_P2POFF_DIS_TXTIME(x) | BIT_P2POFF_DIS_TXTIME(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MBSSID_BCN_SPACE2 (Offset 0x05B8) */ #define BIT_SHIFT_BCN_SPACE_CLINT2 16 #define BIT_MASK_BCN_SPACE_CLINT2 0xfff #define BIT_BCN_SPACE_CLINT2(x) \ (((x) & BIT_MASK_BCN_SPACE_CLINT2) << BIT_SHIFT_BCN_SPACE_CLINT2) #define BITS_BCN_SPACE_CLINT2 \ (BIT_MASK_BCN_SPACE_CLINT2 << BIT_SHIFT_BCN_SPACE_CLINT2) #define BIT_CLEAR_BCN_SPACE_CLINT2(x) ((x) & (~BITS_BCN_SPACE_CLINT2)) #define BIT_GET_BCN_SPACE_CLINT2(x) \ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2) & BIT_MASK_BCN_SPACE_CLINT2) #define BIT_SET_BCN_SPACE_CLINT2(x, v) \ (BIT_CLEAR_BCN_SPACE_CLINT2(x) | BIT_BCN_SPACE_CLINT2(v)) #define BIT_SHIFT_BCN_SPACE_CLINT1 0 #define BIT_MASK_BCN_SPACE_CLINT1 0xfff #define BIT_BCN_SPACE_CLINT1(x) \ (((x) & BIT_MASK_BCN_SPACE_CLINT1) << BIT_SHIFT_BCN_SPACE_CLINT1) #define BITS_BCN_SPACE_CLINT1 \ (BIT_MASK_BCN_SPACE_CLINT1 << BIT_SHIFT_BCN_SPACE_CLINT1) #define BIT_CLEAR_BCN_SPACE_CLINT1(x) ((x) & (~BITS_BCN_SPACE_CLINT1)) #define BIT_GET_BCN_SPACE_CLINT1(x) \ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1) & BIT_MASK_BCN_SPACE_CLINT1) #define BIT_SET_BCN_SPACE_CLINT1(x, v) \ (BIT_CLEAR_BCN_SPACE_CLINT1(x) | BIT_BCN_SPACE_CLINT1(v)) /* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ #define BIT_SHIFT_SUB_BCN_SPACE 16 #define BIT_MASK_SUB_BCN_SPACE 0xff #define BIT_SUB_BCN_SPACE(x) \ (((x) & BIT_MASK_SUB_BCN_SPACE) << BIT_SHIFT_SUB_BCN_SPACE) #define BITS_SUB_BCN_SPACE (BIT_MASK_SUB_BCN_SPACE << BIT_SHIFT_SUB_BCN_SPACE) #define BIT_CLEAR_SUB_BCN_SPACE(x) ((x) & (~BITS_SUB_BCN_SPACE)) #define BIT_GET_SUB_BCN_SPACE(x) \ (((x) >> BIT_SHIFT_SUB_BCN_SPACE) & BIT_MASK_SUB_BCN_SPACE) #define BIT_SET_SUB_BCN_SPACE(x, v) \ (BIT_CLEAR_SUB_BCN_SPACE(x) | BIT_SUB_BCN_SPACE(v)) #define BIT_SHIFT_BCN_SPACE_CLINT3 0 #define BIT_MASK_BCN_SPACE_CLINT3 0xfff #define BIT_BCN_SPACE_CLINT3(x) \ (((x) & BIT_MASK_BCN_SPACE_CLINT3) << BIT_SHIFT_BCN_SPACE_CLINT3) #define BITS_BCN_SPACE_CLINT3 \ (BIT_MASK_BCN_SPACE_CLINT3 << BIT_SHIFT_BCN_SPACE_CLINT3) #define BIT_CLEAR_BCN_SPACE_CLINT3(x) ((x) & (~BITS_BCN_SPACE_CLINT3)) #define BIT_GET_BCN_SPACE_CLINT3(x) \ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3) & BIT_MASK_BCN_SPACE_CLINT3) #define BIT_SET_BCN_SPACE_CLINT3(x, v) \ (BIT_CLEAR_BCN_SPACE_CLINT3(x) | BIT_BCN_SPACE_CLINT3(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_ACMHWCTRL (Offset 0x05C0) */ #define BIT_BEQ_ACM_STATUS BIT(7) #define BIT_VIQ_ACM_STATUS BIT(6) #define BIT_VOQ_ACM_STATUS BIT(5) #define BIT_BEQ_ACM_EN BIT(3) #define BIT_VIQ_ACM_EN BIT(2) #define BIT_VOQ_ACM_EN BIT(1) #define BIT_ACMHWEN BIT(0) /* 2 REG_ACMRSTCTRL (Offset 0x05C1) */ #define BIT_BE_ACM_RESET_USED_TIME BIT(2) #define BIT_VI_ACM_RESET_USED_TIME BIT(1) #define BIT_VO_ACM_RESET_USED_TIME BIT(0) /* 2 REG_ACMAVG (Offset 0x05C2) */ #define BIT_SHIFT_AVGPERIOD 0 #define BIT_MASK_AVGPERIOD 0xffff #define BIT_AVGPERIOD(x) (((x) & BIT_MASK_AVGPERIOD) << BIT_SHIFT_AVGPERIOD) #define BITS_AVGPERIOD (BIT_MASK_AVGPERIOD << BIT_SHIFT_AVGPERIOD) #define BIT_CLEAR_AVGPERIOD(x) ((x) & (~BITS_AVGPERIOD)) #define BIT_GET_AVGPERIOD(x) (((x) >> BIT_SHIFT_AVGPERIOD) & BIT_MASK_AVGPERIOD) #define BIT_SET_AVGPERIOD(x, v) (BIT_CLEAR_AVGPERIOD(x) | BIT_AVGPERIOD(v)) /* 2 REG_VO_ADMTIME (Offset 0x05C4) */ #define BIT_SHIFT_VO_ADMITTED_TIME 0 #define BIT_MASK_VO_ADMITTED_TIME 0xffff #define BIT_VO_ADMITTED_TIME(x) \ (((x) & BIT_MASK_VO_ADMITTED_TIME) << BIT_SHIFT_VO_ADMITTED_TIME) #define BITS_VO_ADMITTED_TIME \ (BIT_MASK_VO_ADMITTED_TIME << BIT_SHIFT_VO_ADMITTED_TIME) #define BIT_CLEAR_VO_ADMITTED_TIME(x) ((x) & (~BITS_VO_ADMITTED_TIME)) #define BIT_GET_VO_ADMITTED_TIME(x) \ (((x) >> BIT_SHIFT_VO_ADMITTED_TIME) & BIT_MASK_VO_ADMITTED_TIME) #define BIT_SET_VO_ADMITTED_TIME(x, v) \ (BIT_CLEAR_VO_ADMITTED_TIME(x) | BIT_VO_ADMITTED_TIME(v)) /* 2 REG_VI_ADMTIME (Offset 0x05C6) */ #define BIT_SHIFT_VI_ADMITTED_TIME 0 #define BIT_MASK_VI_ADMITTED_TIME 0xffff #define BIT_VI_ADMITTED_TIME(x) \ (((x) & BIT_MASK_VI_ADMITTED_TIME) << BIT_SHIFT_VI_ADMITTED_TIME) #define BITS_VI_ADMITTED_TIME \ (BIT_MASK_VI_ADMITTED_TIME << BIT_SHIFT_VI_ADMITTED_TIME) #define BIT_CLEAR_VI_ADMITTED_TIME(x) ((x) & (~BITS_VI_ADMITTED_TIME)) #define BIT_GET_VI_ADMITTED_TIME(x) \ (((x) >> BIT_SHIFT_VI_ADMITTED_TIME) & BIT_MASK_VI_ADMITTED_TIME) #define BIT_SET_VI_ADMITTED_TIME(x, v) \ (BIT_CLEAR_VI_ADMITTED_TIME(x) | BIT_VI_ADMITTED_TIME(v)) /* 2 REG_BE_ADMTIME (Offset 0x05C8) */ #define BIT_SHIFT_BE_ADMITTED_TIME 0 #define BIT_MASK_BE_ADMITTED_TIME 0xffff #define BIT_BE_ADMITTED_TIME(x) \ (((x) & BIT_MASK_BE_ADMITTED_TIME) << BIT_SHIFT_BE_ADMITTED_TIME) #define BITS_BE_ADMITTED_TIME \ (BIT_MASK_BE_ADMITTED_TIME << BIT_SHIFT_BE_ADMITTED_TIME) #define BIT_CLEAR_BE_ADMITTED_TIME(x) ((x) & (~BITS_BE_ADMITTED_TIME)) #define BIT_GET_BE_ADMITTED_TIME(x) \ (((x) >> BIT_SHIFT_BE_ADMITTED_TIME) & BIT_MASK_BE_ADMITTED_TIME) #define BIT_SET_BE_ADMITTED_TIME(x, v) \ (BIT_CLEAR_BE_ADMITTED_TIME(x) | BIT_BE_ADMITTED_TIME(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MAC_HEADER_NAV_OFFSET (Offset 0x05CA) */ #define BIT_SHIFT_MAC_HEADER_NAV_OFFSET 0 #define BIT_MASK_MAC_HEADER_NAV_OFFSET 0xff #define BIT_MAC_HEADER_NAV_OFFSET(x) \ (((x) & BIT_MASK_MAC_HEADER_NAV_OFFSET) \ << BIT_SHIFT_MAC_HEADER_NAV_OFFSET) #define BITS_MAC_HEADER_NAV_OFFSET \ (BIT_MASK_MAC_HEADER_NAV_OFFSET << BIT_SHIFT_MAC_HEADER_NAV_OFFSET) #define BIT_CLEAR_MAC_HEADER_NAV_OFFSET(x) ((x) & (~BITS_MAC_HEADER_NAV_OFFSET)) #define BIT_GET_MAC_HEADER_NAV_OFFSET(x) \ (((x) >> BIT_SHIFT_MAC_HEADER_NAV_OFFSET) & \ BIT_MASK_MAC_HEADER_NAV_OFFSET) #define BIT_SET_MAC_HEADER_NAV_OFFSET(x, v) \ (BIT_CLEAR_MAC_HEADER_NAV_OFFSET(x) | BIT_MAC_HEADER_NAV_OFFSET(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_DIS_NDPA_NAV_CHECK (Offset 0x05CB) */ #define BIT_CHG_POWER_BCN_AREA_V1 BIT(1) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DIS_NDPA_NAV_CHECK (Offset 0x05CB) */ #define BIT_DIS_NDPA_NAV_CHECK BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_EDCA_RANDOM_GEN (Offset 0x05CC) */ #define BIT_SHIFT_RANDOM_GEN 0 #define BIT_MASK_RANDOM_GEN 0xffffff #define BIT_RANDOM_GEN(x) (((x) & BIT_MASK_RANDOM_GEN) << BIT_SHIFT_RANDOM_GEN) #define BITS_RANDOM_GEN (BIT_MASK_RANDOM_GEN << BIT_SHIFT_RANDOM_GEN) #define BIT_CLEAR_RANDOM_GEN(x) ((x) & (~BITS_RANDOM_GEN)) #define BIT_GET_RANDOM_GEN(x) \ (((x) >> BIT_SHIFT_RANDOM_GEN) & BIT_MASK_RANDOM_GEN) #define BIT_SET_RANDOM_GEN(x, v) (BIT_CLEAR_RANDOM_GEN(x) | BIT_RANDOM_GEN(v)) #define BIT_SHIFT_TXCMD_SEG_SEL 0 #define BIT_MASK_TXCMD_SEG_SEL 0xf #define BIT_TXCMD_SEG_SEL(x) \ (((x) & BIT_MASK_TXCMD_SEG_SEL) << BIT_SHIFT_TXCMD_SEG_SEL) #define BITS_TXCMD_SEG_SEL (BIT_MASK_TXCMD_SEG_SEL << BIT_SHIFT_TXCMD_SEG_SEL) #define BIT_CLEAR_TXCMD_SEG_SEL(x) ((x) & (~BITS_TXCMD_SEG_SEL)) #define BIT_GET_TXCMD_SEG_SEL(x) \ (((x) >> BIT_SHIFT_TXCMD_SEG_SEL) & BIT_MASK_TXCMD_SEG_SEL) #define BIT_SET_TXCMD_SEG_SEL(x, v) \ (BIT_CLEAR_TXCMD_SEG_SEL(x) | BIT_TXCMD_SEG_SEL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ #define BIT_NOA_SEL BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ #define BIT_SHIFT_NOA_SEL_V2 4 #define BIT_MASK_NOA_SEL_V2 0x7 #define BIT_NOA_SEL_V2(x) (((x) & BIT_MASK_NOA_SEL_V2) << BIT_SHIFT_NOA_SEL_V2) #define BITS_NOA_SEL_V2 (BIT_MASK_NOA_SEL_V2 << BIT_SHIFT_NOA_SEL_V2) #define BIT_CLEAR_NOA_SEL_V2(x) ((x) & (~BITS_NOA_SEL_V2)) #define BIT_GET_NOA_SEL_V2(x) \ (((x) >> BIT_SHIFT_NOA_SEL_V2) & BIT_MASK_NOA_SEL_V2) #define BIT_SET_NOA_SEL_V2(x, v) (BIT_CLEAR_NOA_SEL_V2(x) | BIT_NOA_SEL_V2(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_32K_CLK_SEL (Offset 0x05D0) */ #define BIT_R_BCNERR_CNT_EN BIT(20) #define BIT_SHIFT_R_BCNERR_PORT_SEL 16 #define BIT_MASK_R_BCNERR_PORT_SEL 0x7 #define BIT_R_BCNERR_PORT_SEL(x) \ (((x) & BIT_MASK_R_BCNERR_PORT_SEL) << BIT_SHIFT_R_BCNERR_PORT_SEL) #define BITS_R_BCNERR_PORT_SEL \ (BIT_MASK_R_BCNERR_PORT_SEL << BIT_SHIFT_R_BCNERR_PORT_SEL) #define BIT_CLEAR_R_BCNERR_PORT_SEL(x) ((x) & (~BITS_R_BCNERR_PORT_SEL)) #define BIT_GET_R_BCNERR_PORT_SEL(x) \ (((x) >> BIT_SHIFT_R_BCNERR_PORT_SEL) & BIT_MASK_R_BCNERR_PORT_SEL) #define BIT_SET_R_BCNERR_PORT_SEL(x, v) \ (BIT_CLEAR_R_BCNERR_PORT_SEL(x) | BIT_R_BCNERR_PORT_SEL(v)) #define BIT_SHIFT_R_TXPAUSE1 8 #define BIT_MASK_R_TXPAUSE1 0xff #define BIT_R_TXPAUSE1(x) (((x) & BIT_MASK_R_TXPAUSE1) << BIT_SHIFT_R_TXPAUSE1) #define BITS_R_TXPAUSE1 (BIT_MASK_R_TXPAUSE1 << BIT_SHIFT_R_TXPAUSE1) #define BIT_CLEAR_R_TXPAUSE1(x) ((x) & (~BITS_R_TXPAUSE1)) #define BIT_GET_R_TXPAUSE1(x) \ (((x) >> BIT_SHIFT_R_TXPAUSE1) & BIT_MASK_R_TXPAUSE1) #define BIT_SET_R_TXPAUSE1(x, v) (BIT_CLEAR_R_TXPAUSE1(x) | BIT_R_TXPAUSE1(v)) #define BIT_SLEEP_32K_EN_V1 BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_EARLYINT_ADJUST (Offset 0x05D4) */ #define BIT_SHIFT_RXBCN_TIMER 16 #define BIT_MASK_RXBCN_TIMER 0xffff #define BIT_RXBCN_TIMER(x) \ (((x) & BIT_MASK_RXBCN_TIMER) << BIT_SHIFT_RXBCN_TIMER) #define BITS_RXBCN_TIMER (BIT_MASK_RXBCN_TIMER << BIT_SHIFT_RXBCN_TIMER) #define BIT_CLEAR_RXBCN_TIMER(x) ((x) & (~BITS_RXBCN_TIMER)) #define BIT_GET_RXBCN_TIMER(x) \ (((x) >> BIT_SHIFT_RXBCN_TIMER) & BIT_MASK_RXBCN_TIMER) #define BIT_SET_RXBCN_TIMER(x, v) \ (BIT_CLEAR_RXBCN_TIMER(x) | BIT_RXBCN_TIMER(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_EARLYINT_ADJUST (Offset 0x05D4) */ #define BIT_SHIFT_R_ERLYINTADJ 0 #define BIT_MASK_R_ERLYINTADJ 0xffff #define BIT_R_ERLYINTADJ(x) \ (((x) & BIT_MASK_R_ERLYINTADJ) << BIT_SHIFT_R_ERLYINTADJ) #define BITS_R_ERLYINTADJ (BIT_MASK_R_ERLYINTADJ << BIT_SHIFT_R_ERLYINTADJ) #define BIT_CLEAR_R_ERLYINTADJ(x) ((x) & (~BITS_R_ERLYINTADJ)) #define BIT_GET_R_ERLYINTADJ(x) \ (((x) >> BIT_SHIFT_R_ERLYINTADJ) & BIT_MASK_R_ERLYINTADJ) #define BIT_SET_R_ERLYINTADJ(x, v) \ (BIT_CLEAR_R_ERLYINTADJ(x) | BIT_R_ERLYINTADJ(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BCNERR_CNT (Offset 0x05D8) */ #define BIT_SHIFT_BCNERR_CNT_OTHERS 24 #define BIT_MASK_BCNERR_CNT_OTHERS 0xff #define BIT_BCNERR_CNT_OTHERS(x) \ (((x) & BIT_MASK_BCNERR_CNT_OTHERS) << BIT_SHIFT_BCNERR_CNT_OTHERS) #define BITS_BCNERR_CNT_OTHERS \ (BIT_MASK_BCNERR_CNT_OTHERS << BIT_SHIFT_BCNERR_CNT_OTHERS) #define BIT_CLEAR_BCNERR_CNT_OTHERS(x) ((x) & (~BITS_BCNERR_CNT_OTHERS)) #define BIT_GET_BCNERR_CNT_OTHERS(x) \ (((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS) & BIT_MASK_BCNERR_CNT_OTHERS) #define BIT_SET_BCNERR_CNT_OTHERS(x, v) \ (BIT_CLEAR_BCNERR_CNT_OTHERS(x) | BIT_BCNERR_CNT_OTHERS(v)) #define BIT_SHIFT_BCNERR_CNT_INVALID 16 #define BIT_MASK_BCNERR_CNT_INVALID 0xff #define BIT_BCNERR_CNT_INVALID(x) \ (((x) & BIT_MASK_BCNERR_CNT_INVALID) << BIT_SHIFT_BCNERR_CNT_INVALID) #define BITS_BCNERR_CNT_INVALID \ (BIT_MASK_BCNERR_CNT_INVALID << BIT_SHIFT_BCNERR_CNT_INVALID) #define BIT_CLEAR_BCNERR_CNT_INVALID(x) ((x) & (~BITS_BCNERR_CNT_INVALID)) #define BIT_GET_BCNERR_CNT_INVALID(x) \ (((x) >> BIT_SHIFT_BCNERR_CNT_INVALID) & BIT_MASK_BCNERR_CNT_INVALID) #define BIT_SET_BCNERR_CNT_INVALID(x, v) \ (BIT_CLEAR_BCNERR_CNT_INVALID(x) | BIT_BCNERR_CNT_INVALID(v)) #define BIT_SHIFT_BCNERR_CNT_MAC 8 #define BIT_MASK_BCNERR_CNT_MAC 0xff #define BIT_BCNERR_CNT_MAC(x) \ (((x) & BIT_MASK_BCNERR_CNT_MAC) << BIT_SHIFT_BCNERR_CNT_MAC) #define BITS_BCNERR_CNT_MAC \ (BIT_MASK_BCNERR_CNT_MAC << BIT_SHIFT_BCNERR_CNT_MAC) #define BIT_CLEAR_BCNERR_CNT_MAC(x) ((x) & (~BITS_BCNERR_CNT_MAC)) #define BIT_GET_BCNERR_CNT_MAC(x) \ (((x) >> BIT_SHIFT_BCNERR_CNT_MAC) & BIT_MASK_BCNERR_CNT_MAC) #define BIT_SET_BCNERR_CNT_MAC(x, v) \ (BIT_CLEAR_BCNERR_CNT_MAC(x) | BIT_BCNERR_CNT_MAC(v)) #define BIT_SHIFT_BCNERR_CNT_CCA 0 #define BIT_MASK_BCNERR_CNT_CCA 0xff #define BIT_BCNERR_CNT_CCA(x) \ (((x) & BIT_MASK_BCNERR_CNT_CCA) << BIT_SHIFT_BCNERR_CNT_CCA) #define BITS_BCNERR_CNT_CCA \ (BIT_MASK_BCNERR_CNT_CCA << BIT_SHIFT_BCNERR_CNT_CCA) #define BIT_CLEAR_BCNERR_CNT_CCA(x) ((x) & (~BITS_BCNERR_CNT_CCA)) #define BIT_GET_BCNERR_CNT_CCA(x) \ (((x) >> BIT_SHIFT_BCNERR_CNT_CCA) & BIT_MASK_BCNERR_CNT_CCA) #define BIT_SET_BCNERR_CNT_CCA(x, v) \ (BIT_CLEAR_BCNERR_CNT_CCA(x) | BIT_BCNERR_CNT_CCA(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_NOA_PARAM (Offset 0x05E0) */ #define BIT_SHIFT_NOA_COUNT (96 & CPU_OPT_WIDTH) #define BIT_MASK_NOA_COUNT 0xff #define BIT_NOA_COUNT(x) (((x) & BIT_MASK_NOA_COUNT) << BIT_SHIFT_NOA_COUNT) #define BITS_NOA_COUNT (BIT_MASK_NOA_COUNT << BIT_SHIFT_NOA_COUNT) #define BIT_CLEAR_NOA_COUNT(x) ((x) & (~BITS_NOA_COUNT)) #define BIT_GET_NOA_COUNT(x) (((x) >> BIT_SHIFT_NOA_COUNT) & BIT_MASK_NOA_COUNT) #define BIT_SET_NOA_COUNT(x, v) (BIT_CLEAR_NOA_COUNT(x) | BIT_NOA_COUNT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_NOA_PARAM (Offset 0x05E0) */ #define BIT_SHIFT_NOA_DURATION 0 #define BIT_MASK_NOA_DURATION 0xffffffffL #define BIT_NOA_DURATION(x) \ (((x) & BIT_MASK_NOA_DURATION) << BIT_SHIFT_NOA_DURATION) #define BITS_NOA_DURATION (BIT_MASK_NOA_DURATION << BIT_SHIFT_NOA_DURATION) #define BIT_CLEAR_NOA_DURATION(x) ((x) & (~BITS_NOA_DURATION)) #define BIT_GET_NOA_DURATION(x) \ (((x) >> BIT_SHIFT_NOA_DURATION) & BIT_MASK_NOA_DURATION) #define BIT_SET_NOA_DURATION(x, v) \ (BIT_CLEAR_NOA_DURATION(x) | BIT_NOA_DURATION(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_NOA_PARAM (Offset 0x05E0) */ #define BIT_SHIFT_NOA_DURATION_V1 0 #define BIT_MASK_NOA_DURATION_V1 0xffffffffL #define BIT_NOA_DURATION_V1(x) \ (((x) & BIT_MASK_NOA_DURATION_V1) << BIT_SHIFT_NOA_DURATION_V1) #define BITS_NOA_DURATION_V1 \ (BIT_MASK_NOA_DURATION_V1 << BIT_SHIFT_NOA_DURATION_V1) #define BIT_CLEAR_NOA_DURATION_V1(x) ((x) & (~BITS_NOA_DURATION_V1)) #define BIT_GET_NOA_DURATION_V1(x) \ (((x) >> BIT_SHIFT_NOA_DURATION_V1) & BIT_MASK_NOA_DURATION_V1) #define BIT_SET_NOA_DURATION_V1(x, v) \ (BIT_CLEAR_NOA_DURATION_V1(x) | BIT_NOA_DURATION_V1(v)) /* 2 REG_NOA_PARAM_1 (Offset 0x05E4) */ #define BIT_SHIFT_NOA_INTERVAL_V1 0 #define BIT_MASK_NOA_INTERVAL_V1 0xffffffffL #define BIT_NOA_INTERVAL_V1(x) \ (((x) & BIT_MASK_NOA_INTERVAL_V1) << BIT_SHIFT_NOA_INTERVAL_V1) #define BITS_NOA_INTERVAL_V1 \ (BIT_MASK_NOA_INTERVAL_V1 << BIT_SHIFT_NOA_INTERVAL_V1) #define BIT_CLEAR_NOA_INTERVAL_V1(x) ((x) & (~BITS_NOA_INTERVAL_V1)) #define BIT_GET_NOA_INTERVAL_V1(x) \ (((x) >> BIT_SHIFT_NOA_INTERVAL_V1) & BIT_MASK_NOA_INTERVAL_V1) #define BIT_SET_NOA_INTERVAL_V1(x, v) \ (BIT_CLEAR_NOA_INTERVAL_V1(x) | BIT_NOA_INTERVAL_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MU_DBG_INFO (Offset 0x05E8) */ #define BIT_SHIFT_MU_DBG_INFO 0 #define BIT_MASK_MU_DBG_INFO 0xffffffffL #define BIT_MU_DBG_INFO(x) \ (((x) & BIT_MASK_MU_DBG_INFO) << BIT_SHIFT_MU_DBG_INFO) #define BITS_MU_DBG_INFO (BIT_MASK_MU_DBG_INFO << BIT_SHIFT_MU_DBG_INFO) #define BIT_CLEAR_MU_DBG_INFO(x) ((x) & (~BITS_MU_DBG_INFO)) #define BIT_GET_MU_DBG_INFO(x) \ (((x) >> BIT_SHIFT_MU_DBG_INFO) & BIT_MASK_MU_DBG_INFO) #define BIT_SET_MU_DBG_INFO(x, v) \ (BIT_CLEAR_MU_DBG_INFO(x) | BIT_MU_DBG_INFO(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_NOA_PARAM_2 (Offset 0x05E8) */ #define BIT_SHIFT_NOA_START_TIME_V1 0 #define BIT_MASK_NOA_START_TIME_V1 0xffffffffL #define BIT_NOA_START_TIME_V1(x) \ (((x) & BIT_MASK_NOA_START_TIME_V1) << BIT_SHIFT_NOA_START_TIME_V1) #define BITS_NOA_START_TIME_V1 \ (BIT_MASK_NOA_START_TIME_V1 << BIT_SHIFT_NOA_START_TIME_V1) #define BIT_CLEAR_NOA_START_TIME_V1(x) ((x) & (~BITS_NOA_START_TIME_V1)) #define BIT_GET_NOA_START_TIME_V1(x) \ (((x) >> BIT_SHIFT_NOA_START_TIME_V1) & BIT_MASK_NOA_START_TIME_V1) #define BIT_SET_NOA_START_TIME_V1(x, v) \ (BIT_CLEAR_NOA_START_TIME_V1(x) | BIT_NOA_START_TIME_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MU_DBG_INFO_1 (Offset 0x05EC) */ #define BIT_SHIFT_MU_DBG_INFO_1 0 #define BIT_MASK_MU_DBG_INFO_1 0xffffffffL #define BIT_MU_DBG_INFO_1(x) \ (((x) & BIT_MASK_MU_DBG_INFO_1) << BIT_SHIFT_MU_DBG_INFO_1) #define BITS_MU_DBG_INFO_1 (BIT_MASK_MU_DBG_INFO_1 << BIT_SHIFT_MU_DBG_INFO_1) #define BIT_CLEAR_MU_DBG_INFO_1(x) ((x) & (~BITS_MU_DBG_INFO_1)) #define BIT_GET_MU_DBG_INFO_1(x) \ (((x) >> BIT_SHIFT_MU_DBG_INFO_1) & BIT_MASK_MU_DBG_INFO_1) #define BIT_SET_MU_DBG_INFO_1(x, v) \ (BIT_CLEAR_MU_DBG_INFO_1(x) | BIT_MU_DBG_INFO_1(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_NOA_PARAM_3 (Offset 0x05EC) */ #define BIT_SHIFT_NOA_COUNT_V1 0 #define BIT_MASK_NOA_COUNT_V1 0xffffffffL #define BIT_NOA_COUNT_V1(x) \ (((x) & BIT_MASK_NOA_COUNT_V1) << BIT_SHIFT_NOA_COUNT_V1) #define BITS_NOA_COUNT_V1 (BIT_MASK_NOA_COUNT_V1 << BIT_SHIFT_NOA_COUNT_V1) #define BIT_CLEAR_NOA_COUNT_V1(x) ((x) & (~BITS_NOA_COUNT_V1)) #define BIT_GET_NOA_COUNT_V1(x) \ (((x) >> BIT_SHIFT_NOA_COUNT_V1) & BIT_MASK_NOA_COUNT_V1) #define BIT_SET_NOA_COUNT_V1(x, v) \ (BIT_CLEAR_NOA_COUNT_V1(x) | BIT_NOA_COUNT_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_NOA_SUBIE (Offset 0x05ED) */ #define BIT_MORE_NOA_DESC BIT(19) #define BIT_NOA_DESC1_VALID BIT(18) #define BIT_NOA_DESC0_VALID BIT(17) #define BIT_NOA_HEAD_VALID BIT(16) #define BIT_NOA_OPP_PS BIT(15) #define BIT_SHIFT_NOA_CTW 8 #define BIT_MASK_NOA_CTW 0x7f #define BIT_NOA_CTW(x) (((x) & BIT_MASK_NOA_CTW) << BIT_SHIFT_NOA_CTW) #define BITS_NOA_CTW (BIT_MASK_NOA_CTW << BIT_SHIFT_NOA_CTW) #define BIT_CLEAR_NOA_CTW(x) ((x) & (~BITS_NOA_CTW)) #define BIT_GET_NOA_CTW(x) (((x) >> BIT_SHIFT_NOA_CTW) & BIT_MASK_NOA_CTW) #define BIT_SET_NOA_CTW(x, v) (BIT_CLEAR_NOA_CTW(x) | BIT_NOA_CTW(v)) #define BIT_SHIFT_NOA_INDEX 0 #define BIT_MASK_NOA_INDEX 0xff #define BIT_NOA_INDEX(x) (((x) & BIT_MASK_NOA_INDEX) << BIT_SHIFT_NOA_INDEX) #define BITS_NOA_INDEX (BIT_MASK_NOA_INDEX << BIT_SHIFT_NOA_INDEX) #define BIT_CLEAR_NOA_INDEX(x) ((x) & (~BITS_NOA_INDEX)) #define BIT_GET_NOA_INDEX(x) (((x) >> BIT_SHIFT_NOA_INDEX) & BIT_MASK_NOA_INDEX) #define BIT_SET_NOA_INDEX(x, v) (BIT_CLEAR_NOA_INDEX(x) | BIT_NOA_INDEX(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_P2P_RST (Offset 0x05F0) */ #define BIT_P2P2_PWR_RST1 BIT(5) #define BIT_P2P2_PWR_RST0 BIT(4) #define BIT_P2P1_PWR_RST1 BIT(3) #define BIT_P2P1_PWR_RST0 BIT(2) #define BIT_P2P_PWR_RST1_V1 BIT(1) #define BIT_P2P_PWR_RST0_V1 BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SCH_DBG_SEL (Offset 0x05F0) */ #define BIT_SHIFT_SCH_DBG_SEL 0 #define BIT_MASK_SCH_DBG_SEL 0xff #define BIT_SCH_DBG_SEL(x) \ (((x) & BIT_MASK_SCH_DBG_SEL) << BIT_SHIFT_SCH_DBG_SEL) #define BITS_SCH_DBG_SEL (BIT_MASK_SCH_DBG_SEL << BIT_SHIFT_SCH_DBG_SEL) #define BIT_CLEAR_SCH_DBG_SEL(x) ((x) & (~BITS_SCH_DBG_SEL)) #define BIT_GET_SCH_DBG_SEL(x) \ (((x) >> BIT_SHIFT_SCH_DBG_SEL) & BIT_MASK_SCH_DBG_SEL) #define BIT_SET_SCH_DBG_SEL(x, v) \ (BIT_CLEAR_SCH_DBG_SEL(x) | BIT_SCH_DBG_SEL(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ #define BIT_MAC_STOP_CPUMGQ BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ #define BIT_SYNC_TSF_NOW BIT(2) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ #define BIT_SYNC_CLI_ONCE_RIGHT_NOW BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT) /* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ #define BIT_SYNC_CLI BIT(1) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ #define BIT_SYNC_CLI_ONCE_BY_TBTT BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ #define BIT_SCHEDULER_RST_V1 BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MU_DBG_ERR_FLAG (Offset 0x05F2) */ #define BIT_BCN_PORTID_ERR BIT(2) #define BIT_SHIFT_MU_DBG_ERR_FLAG 0 #define BIT_MASK_MU_DBG_ERR_FLAG 0x3 #define BIT_MU_DBG_ERR_FLAG(x) \ (((x) & BIT_MASK_MU_DBG_ERR_FLAG) << BIT_SHIFT_MU_DBG_ERR_FLAG) #define BITS_MU_DBG_ERR_FLAG \ (BIT_MASK_MU_DBG_ERR_FLAG << BIT_SHIFT_MU_DBG_ERR_FLAG) #define BIT_CLEAR_MU_DBG_ERR_FLAG(x) ((x) & (~BITS_MU_DBG_ERR_FLAG)) #define BIT_GET_MU_DBG_ERR_FLAG(x) \ (((x) >> BIT_SHIFT_MU_DBG_ERR_FLAG) & BIT_MASK_MU_DBG_ERR_FLAG) #define BIT_SET_MU_DBG_ERR_FLAG(x, v) \ (BIT_CLEAR_MU_DBG_ERR_FLAG(x) | BIT_MU_DBG_ERR_FLAG(v)) /* 2 REG_TX_ERR_RECOVERY_RST (Offset 0x05F3) */ #define BIT_SHIFT_ERR_RECOVER_CNT 4 #define BIT_MASK_ERR_RECOVER_CNT 0xf #define BIT_ERR_RECOVER_CNT(x) \ (((x) & BIT_MASK_ERR_RECOVER_CNT) << BIT_SHIFT_ERR_RECOVER_CNT) #define BITS_ERR_RECOVER_CNT \ (BIT_MASK_ERR_RECOVER_CNT << BIT_SHIFT_ERR_RECOVER_CNT) #define BIT_CLEAR_ERR_RECOVER_CNT(x) ((x) & (~BITS_ERR_RECOVER_CNT)) #define BIT_GET_ERR_RECOVER_CNT(x) \ (((x) >> BIT_SHIFT_ERR_RECOVER_CNT) & BIT_MASK_ERR_RECOVER_CNT) #define BIT_SET_ERR_RECOVER_CNT(x, v) \ (BIT_CLEAR_ERR_RECOVER_CNT(x) | BIT_ERR_RECOVER_CNT(v)) #define BIT_RX_HANG_ERR BIT(2) #define BIT_TX_HANG_ERR BIT(1) #define BIT_TX_ERR_RECOVERY_RST BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SCH_DBG_VALUE (Offset 0x05F4) */ #define BIT_SHIFT_SCH_DBG_VALUE 0 #define BIT_MASK_SCH_DBG_VALUE 0xffffffffL #define BIT_SCH_DBG_VALUE(x) \ (((x) & BIT_MASK_SCH_DBG_VALUE) << BIT_SHIFT_SCH_DBG_VALUE) #define BITS_SCH_DBG_VALUE (BIT_MASK_SCH_DBG_VALUE << BIT_SHIFT_SCH_DBG_VALUE) #define BIT_CLEAR_SCH_DBG_VALUE(x) ((x) & (~BITS_SCH_DBG_VALUE)) #define BIT_GET_SCH_DBG_VALUE(x) \ (((x) >> BIT_SHIFT_SCH_DBG_VALUE) & BIT_MASK_SCH_DBG_VALUE) #define BIT_SET_SCH_DBG_VALUE(x, v) \ (BIT_CLEAR_SCH_DBG_VALUE(x) | BIT_SCH_DBG_VALUE(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SCH_TXCMD (Offset 0x05F8) */ #define BIT_SHIFT_SCH_TXCMD 0 #define BIT_MASK_SCH_TXCMD 0xffffffffL #define BIT_SCH_TXCMD(x) (((x) & BIT_MASK_SCH_TXCMD) << BIT_SHIFT_SCH_TXCMD) #define BITS_SCH_TXCMD (BIT_MASK_SCH_TXCMD << BIT_SHIFT_SCH_TXCMD) #define BIT_CLEAR_SCH_TXCMD(x) ((x) & (~BITS_SCH_TXCMD)) #define BIT_GET_SCH_TXCMD(x) (((x) >> BIT_SHIFT_SCH_TXCMD) & BIT_MASK_SCH_TXCMD) #define BIT_SET_SCH_TXCMD(x, v) (BIT_CLEAR_SCH_TXCMD(x) | BIT_SCH_TXCMD(v)) #endif #if (HALMAC_8821C_SUPPORT) /* 2 REG_PAGE5_DUMMY (Offset 0x05FC) */ #define BIT_ECO_TXOP_BREAK_FORCE_CFEND BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WMAC_CR (Offset 0x0600) */ #define BIT_APSDOFF_STATUS BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT) /* 2 REG_WMAC_CR (Offset 0x0600) */ #define BIT_APSDOFF BIT(6) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WMAC_CR (Offset 0x0600) */ #define BIT_STANDBY_STATUS BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_CR (Offset 0x0600) */ #define BIT_IC_MACPHY_M BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ #define BIT_FWEN BIT(7) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ #define BIT_FWRX_EN BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ #define BIT_PHYSTS_PKT_CTRL BIT(6) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ #define BIT_FWFULL_TO_RXFF_EN BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ #define BIT_APPHDR_MIDSRCH_FAIL BIT(4) #define BIT_FWPARSING_EN BIT(3) #define BIT_SHIFT_APPEND_MHDR_LEN 0 #define BIT_MASK_APPEND_MHDR_LEN 0x7 #define BIT_APPEND_MHDR_LEN(x) \ (((x) & BIT_MASK_APPEND_MHDR_LEN) << BIT_SHIFT_APPEND_MHDR_LEN) #define BITS_APPEND_MHDR_LEN \ (BIT_MASK_APPEND_MHDR_LEN << BIT_SHIFT_APPEND_MHDR_LEN) #define BIT_CLEAR_APPEND_MHDR_LEN(x) ((x) & (~BITS_APPEND_MHDR_LEN)) #define BIT_GET_APPEND_MHDR_LEN(x) \ (((x) >> BIT_SHIFT_APPEND_MHDR_LEN) & BIT_MASK_APPEND_MHDR_LEN) #define BIT_SET_APPEND_MHDR_LEN(x, v) \ (BIT_CLEAR_APPEND_MHDR_LEN(x) | BIT_APPEND_MHDR_LEN(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_BWOPMODE (Offset 0x0603) */ #define BIT_WMAC_20MHZBW BIT(2) #define BIT_WMAC_M11J BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_WMAC_EN_RTS_ADDR BIT(31) #define BIT_WMAC_DISABLE_CCK BIT(30) #define BIT_WMAC_RAW_LEN BIT(29) #define BIT_WMAC_NOTX_IN_RXNDP BIT(28) #define BIT_WMAC_EN_EOF BIT(27) #define BIT_WMAC_BF_SEL BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_WMAC_ANTMODE_SEL BIT(25) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_WMAC_TCRPWRMGT_HWCTL BIT(24) #endif #if (HALMAC_8814A_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_RXLEN_SEL BIT(24) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_WMAC_TCRPWRMGT_HWCTL_EN BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_WMAC_SMOOTH_VAL BIT(23) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_WMAC_EN_SCRAM_INC BIT(22) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_UNDERFLOWEN_CMPLEN_SEL BIT(21) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_SHIFT_TSFT_CMP 20 #define BIT_MASK_TSFT_CMP 0xf #define BIT_TSFT_CMP(x) (((x) & BIT_MASK_TSFT_CMP) << BIT_SHIFT_TSFT_CMP) #define BITS_TSFT_CMP (BIT_MASK_TSFT_CMP << BIT_SHIFT_TSFT_CMP) #define BIT_CLEAR_TSFT_CMP(x) ((x) & (~BITS_TSFT_CMP)) #define BIT_GET_TSFT_CMP(x) (((x) >> BIT_SHIFT_TSFT_CMP) & BIT_MASK_TSFT_CMP) #define BIT_SET_TSFT_CMP(x, v) (BIT_CLEAR_TSFT_CMP(x) | BIT_TSFT_CMP(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_FETCH_MPDU_AFTER_WSEC_RDY BIT(20) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_WMAC_TCR_EN_20MST BIT(19) #define BIT_WMAC_DIS_SIGTA BIT(18) #define BIT_WMAC_DIS_A2B0 BIT(17) #define BIT_WMAC_MSK_SIGBCRC BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_WMAC_TCR_ERRSTEN_3 BIT(15) #define BIT_WMAC_TCR_ERRSTEN_2 BIT(14) #define BIT_WMAC_TCR_ERRSTEN_1 BIT(13) #define BIT_WMAC_TCR_ERRSTEN_0 BIT(12) #define BIT_WMAC_TCR_TXSK_PERPKT BIT(11) #define BIT_ICV BIT(10) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_CFEND_FORMAT BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_CRC BIT(8) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_PWRBIT_OW_EN BIT(7) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_WMAC_TCRPWRMGT_HWDATA_EN BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_PWR_ST BIT(6) #define BIT_WMAC_TCR_UPD_TIMIE BIT(5) #define BIT_WMAC_TCR_UPD_HGQMD BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_VHTSIGA1_TXPS BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_PAD_SEL BIT(2) #define BIT_DIS_GCLK BIT(1) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_TSFRST BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_R_WMAC_TCR_LSIG BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TCR (Offset 0x0604) */ #define BIT_WMAC_TCRPWRMGT_HWACT_EN BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ #define BIT_APP_FCS BIT(31) #define BIT_APP_MIC BIT(30) #define BIT_APP_ICV BIT(29) #define BIT_APP_PHYSTS BIT(28) #define BIT_APP_BASSN BIT(27) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ #define BIT_VHT_DACK BIT(26) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ #define BIT_TCPOFLD_EN BIT(25) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ #define BIT_ENMBID BIT(24) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ #define BIT_ENADDRCAM BIT(24) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ #define BIT_LSIGEN BIT(23) #define BIT_MFBEN BIT(22) #define BIT_DISCHKPPDLLEN BIT(21) #define BIT_PKTCTL_DLEN BIT(20) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ #define BIT_DISGCLK BIT(19) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ #define BIT_TIM_PARSER_EN BIT(18) #define BIT_BC_MD_EN BIT(17) #define BIT_UC_MD_EN BIT(16) #define BIT_RXSK_PERPKT BIT(15) #define BIT_HTC_LOC_CTRL BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ #define BIT_AMF BIT(13) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ #define BIT_CHK_PREVTCA2 BIT(13) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ #define BIT_ACK_WITH_CBSSID_DATA_OPTION BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ #define BIT_ACF BIT(12) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ #define BIT_RPFM_CAM_ENABLE BIT(12) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ #define BIT_ADF BIT(11) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ #define BIT_TA_BCN BIT(11) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RCR (Offset 0x0608) */ #define BIT_DISDECMYPKT BIT(10) #define BIT_AICV BIT(9) #define BIT_ACRC32 BIT(8) #define BIT_CBSSID_BCN BIT(7) #define BIT_CBSSID_DATA BIT(6) #define BIT_APWRMGT BIT(5) #define BIT_ADD3 BIT(4) #define BIT_AB BIT(3) #define BIT_AM BIT(2) #define BIT_APM BIT(1) #define BIT_AAP BIT(0) /* 2 REG_RX_PKT_LIMIT (Offset 0x060C) */ #define BIT_SHIFT_RXPKTLMT 0 #define BIT_MASK_RXPKTLMT 0x3f #define BIT_RXPKTLMT(x) (((x) & BIT_MASK_RXPKTLMT) << BIT_SHIFT_RXPKTLMT) #define BITS_RXPKTLMT (BIT_MASK_RXPKTLMT << BIT_SHIFT_RXPKTLMT) #define BIT_CLEAR_RXPKTLMT(x) ((x) & (~BITS_RXPKTLMT)) #define BIT_GET_RXPKTLMT(x) (((x) >> BIT_SHIFT_RXPKTLMT) & BIT_MASK_RXPKTLMT) #define BIT_SET_RXPKTLMT(x, v) (BIT_CLEAR_RXPKTLMT(x) | BIT_RXPKTLMT(v)) /* 2 REG_RX_DLK_TIME (Offset 0x060D) */ #define BIT_SHIFT_RX_DLK_TIME 0 #define BIT_MASK_RX_DLK_TIME 0xff #define BIT_RX_DLK_TIME(x) \ (((x) & BIT_MASK_RX_DLK_TIME) << BIT_SHIFT_RX_DLK_TIME) #define BITS_RX_DLK_TIME (BIT_MASK_RX_DLK_TIME << BIT_SHIFT_RX_DLK_TIME) #define BIT_CLEAR_RX_DLK_TIME(x) ((x) & (~BITS_RX_DLK_TIME)) #define BIT_GET_RX_DLK_TIME(x) \ (((x) >> BIT_SHIFT_RX_DLK_TIME) & BIT_MASK_RX_DLK_TIME) #define BIT_SET_RX_DLK_TIME(x, v) \ (BIT_CLEAR_RX_DLK_TIME(x) | BIT_RX_DLK_TIME(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ #define BIT_APP_PHYSTS_PER_SUBMPDU BIT(7) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ #define BIT_PHYSTS_PER_PKT_MODE BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ #define BIT_APP_MH_SHIFT_VAL BIT(6) #define BIT_WMAC_ENSHIFT BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ #define BIT_SHIFT_DRVINFO_SZ 0 #define BIT_MASK_DRVINFO_SZ 0xff #define BIT_DRVINFO_SZ(x) (((x) & BIT_MASK_DRVINFO_SZ) << BIT_SHIFT_DRVINFO_SZ) #define BITS_DRVINFO_SZ (BIT_MASK_DRVINFO_SZ << BIT_SHIFT_DRVINFO_SZ) #define BIT_CLEAR_DRVINFO_SZ(x) ((x) & (~BITS_DRVINFO_SZ)) #define BIT_GET_DRVINFO_SZ(x) \ (((x) >> BIT_SHIFT_DRVINFO_SZ) & BIT_MASK_DRVINFO_SZ) #define BIT_SET_DRVINFO_SZ(x, v) (BIT_CLEAR_DRVINFO_SZ(x) | BIT_DRVINFO_SZ(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ #define BIT_SHIFT_DRVINFO_SZ_V1 0 #define BIT_MASK_DRVINFO_SZ_V1 0xf #define BIT_DRVINFO_SZ_V1(x) \ (((x) & BIT_MASK_DRVINFO_SZ_V1) << BIT_SHIFT_DRVINFO_SZ_V1) #define BITS_DRVINFO_SZ_V1 (BIT_MASK_DRVINFO_SZ_V1 << BIT_SHIFT_DRVINFO_SZ_V1) #define BIT_CLEAR_DRVINFO_SZ_V1(x) ((x) & (~BITS_DRVINFO_SZ_V1)) #define BIT_GET_DRVINFO_SZ_V1(x) \ (((x) >> BIT_SHIFT_DRVINFO_SZ_V1) & BIT_MASK_DRVINFO_SZ_V1) #define BIT_SET_DRVINFO_SZ_V1(x, v) \ (BIT_CLEAR_DRVINFO_SZ_V1(x) | BIT_DRVINFO_SZ_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MACID (Offset 0x0610) */ #define BIT_SHIFT_MACID 0 #define BIT_MASK_MACID 0xffffffffffffL #define BIT_MACID(x) (((x) & BIT_MASK_MACID) << BIT_SHIFT_MACID) #define BITS_MACID (BIT_MASK_MACID << BIT_SHIFT_MACID) #define BIT_CLEAR_MACID(x) ((x) & (~BITS_MACID)) #define BIT_GET_MACID(x) (((x) >> BIT_SHIFT_MACID) & BIT_MASK_MACID) #define BIT_SET_MACID(x, v) (BIT_CLEAR_MACID(x) | BIT_MACID(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MACID (Offset 0x0610) */ #define BIT_SHIFT_MACID_V1 0 #define BIT_MASK_MACID_V1 0xffffffffL #define BIT_MACID_V1(x) (((x) & BIT_MASK_MACID_V1) << BIT_SHIFT_MACID_V1) #define BITS_MACID_V1 (BIT_MASK_MACID_V1 << BIT_SHIFT_MACID_V1) #define BIT_CLEAR_MACID_V1(x) ((x) & (~BITS_MACID_V1)) #define BIT_GET_MACID_V1(x) (((x) >> BIT_SHIFT_MACID_V1) & BIT_MASK_MACID_V1) #define BIT_SET_MACID_V1(x, v) (BIT_CLEAR_MACID_V1(x) | BIT_MACID_V1(v)) /* 2 REG_MACID_H (Offset 0x0614) */ #define BIT_SHIFT_MACID_H_V1 0 #define BIT_MASK_MACID_H_V1 0xffff #define BIT_MACID_H_V1(x) (((x) & BIT_MASK_MACID_H_V1) << BIT_SHIFT_MACID_H_V1) #define BITS_MACID_H_V1 (BIT_MASK_MACID_H_V1 << BIT_SHIFT_MACID_H_V1) #define BIT_CLEAR_MACID_H_V1(x) ((x) & (~BITS_MACID_H_V1)) #define BIT_GET_MACID_H_V1(x) \ (((x) >> BIT_SHIFT_MACID_H_V1) & BIT_MASK_MACID_H_V1) #define BIT_SET_MACID_H_V1(x, v) (BIT_CLEAR_MACID_H_V1(x) | BIT_MACID_H_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_BSSID (Offset 0x0618) */ #define BIT_SHIFT_BSSID 0 #define BIT_MASK_BSSID 0xffffffffffffL #define BIT_BSSID(x) (((x) & BIT_MASK_BSSID) << BIT_SHIFT_BSSID) #define BITS_BSSID (BIT_MASK_BSSID << BIT_SHIFT_BSSID) #define BIT_CLEAR_BSSID(x) ((x) & (~BITS_BSSID)) #define BIT_GET_BSSID(x) (((x) >> BIT_SHIFT_BSSID) & BIT_MASK_BSSID) #define BIT_SET_BSSID(x, v) (BIT_CLEAR_BSSID(x) | BIT_BSSID(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BSSID (Offset 0x0618) */ #define BIT_SHIFT_BSSID_V1 0 #define BIT_MASK_BSSID_V1 0xffffffffL #define BIT_BSSID_V1(x) (((x) & BIT_MASK_BSSID_V1) << BIT_SHIFT_BSSID_V1) #define BITS_BSSID_V1 (BIT_MASK_BSSID_V1 << BIT_SHIFT_BSSID_V1) #define BIT_CLEAR_BSSID_V1(x) ((x) & (~BITS_BSSID_V1)) #define BIT_GET_BSSID_V1(x) (((x) >> BIT_SHIFT_BSSID_V1) & BIT_MASK_BSSID_V1) #define BIT_SET_BSSID_V1(x, v) (BIT_CLEAR_BSSID_V1(x) | BIT_BSSID_V1(v)) #define BIT_SHIFT_BSSID_H_V1 0 #define BIT_MASK_BSSID_H_V1 0xffff #define BIT_BSSID_H_V1(x) (((x) & BIT_MASK_BSSID_H_V1) << BIT_SHIFT_BSSID_H_V1) #define BITS_BSSID_H_V1 (BIT_MASK_BSSID_H_V1 << BIT_SHIFT_BSSID_H_V1) #define BIT_CLEAR_BSSID_H_V1(x) ((x) & (~BITS_BSSID_H_V1)) #define BIT_GET_BSSID_H_V1(x) \ (((x) >> BIT_SHIFT_BSSID_H_V1) & BIT_MASK_BSSID_H_V1) #define BIT_SET_BSSID_H_V1(x, v) (BIT_CLEAR_BSSID_H_V1(x) | BIT_BSSID_H_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MAR (Offset 0x0620) */ #define BIT_SHIFT_MAR 0 #define BIT_MASK_MAR 0xffffffffffffffffL #define BIT_MAR(x) (((x) & BIT_MASK_MAR) << BIT_SHIFT_MAR) #define BITS_MAR (BIT_MASK_MAR << BIT_SHIFT_MAR) #define BIT_CLEAR_MAR(x) ((x) & (~BITS_MAR)) #define BIT_GET_MAR(x) (((x) >> BIT_SHIFT_MAR) & BIT_MASK_MAR) #define BIT_SET_MAR(x, v) (BIT_CLEAR_MAR(x) | BIT_MAR(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MAR (Offset 0x0620) */ #define BIT_SHIFT_MAR_V1 0 #define BIT_MASK_MAR_V1 0xffffffffL #define BIT_MAR_V1(x) (((x) & BIT_MASK_MAR_V1) << BIT_SHIFT_MAR_V1) #define BITS_MAR_V1 (BIT_MASK_MAR_V1 << BIT_SHIFT_MAR_V1) #define BIT_CLEAR_MAR_V1(x) ((x) & (~BITS_MAR_V1)) #define BIT_GET_MAR_V1(x) (((x) >> BIT_SHIFT_MAR_V1) & BIT_MASK_MAR_V1) #define BIT_SET_MAR_V1(x, v) (BIT_CLEAR_MAR_V1(x) | BIT_MAR_V1(v)) /* 2 REG_MAR_H (Offset 0x0624) */ #define BIT_SHIFT_MAR_H_V1 0 #define BIT_MASK_MAR_H_V1 0xffffffffL #define BIT_MAR_H_V1(x) (((x) & BIT_MASK_MAR_H_V1) << BIT_SHIFT_MAR_H_V1) #define BITS_MAR_H_V1 (BIT_MASK_MAR_H_V1 << BIT_SHIFT_MAR_H_V1) #define BIT_CLEAR_MAR_H_V1(x) ((x) & (~BITS_MAR_H_V1)) #define BIT_GET_MAR_H_V1(x) (((x) >> BIT_SHIFT_MAR_H_V1) & BIT_MASK_MAR_H_V1) #define BIT_SET_MAR_H_V1(x, v) (BIT_CLEAR_MAR_H_V1(x) | BIT_MAR_H_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIDCAMCFG_1 (Offset 0x0628) */ #define BIT_SHIFT_MBIDCAM_RWDATA_L 0 #define BIT_MASK_MBIDCAM_RWDATA_L 0xffffffffL #define BIT_MBIDCAM_RWDATA_L(x) \ (((x) & BIT_MASK_MBIDCAM_RWDATA_L) << BIT_SHIFT_MBIDCAM_RWDATA_L) #define BITS_MBIDCAM_RWDATA_L \ (BIT_MASK_MBIDCAM_RWDATA_L << BIT_SHIFT_MBIDCAM_RWDATA_L) #define BIT_CLEAR_MBIDCAM_RWDATA_L(x) ((x) & (~BITS_MBIDCAM_RWDATA_L)) #define BIT_GET_MBIDCAM_RWDATA_L(x) \ (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L) & BIT_MASK_MBIDCAM_RWDATA_L) #define BIT_SET_MBIDCAM_RWDATA_L(x, v) \ (BIT_CLEAR_MBIDCAM_RWDATA_L(x) | BIT_MBIDCAM_RWDATA_L(v)) /* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ #define BIT_MBIDCAM_POLL BIT(31) #define BIT_MBIDCAM_WT_EN BIT(30) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ #define BIT_SHIFT_MBIDCAM_ADDR 24 #define BIT_MASK_MBIDCAM_ADDR 0x1f #define BIT_MBIDCAM_ADDR(x) \ (((x) & BIT_MASK_MBIDCAM_ADDR) << BIT_SHIFT_MBIDCAM_ADDR) #define BITS_MBIDCAM_ADDR (BIT_MASK_MBIDCAM_ADDR << BIT_SHIFT_MBIDCAM_ADDR) #define BIT_CLEAR_MBIDCAM_ADDR(x) ((x) & (~BITS_MBIDCAM_ADDR)) #define BIT_GET_MBIDCAM_ADDR(x) \ (((x) >> BIT_SHIFT_MBIDCAM_ADDR) & BIT_MASK_MBIDCAM_ADDR) #define BIT_SET_MBIDCAM_ADDR(x, v) \ (BIT_CLEAR_MBIDCAM_ADDR(x) | BIT_MBIDCAM_ADDR(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ #define BIT_SHIFT_MBIDCAM_ADDR_V1 24 #define BIT_MASK_MBIDCAM_ADDR_V1 0x3f #define BIT_MBIDCAM_ADDR_V1(x) \ (((x) & BIT_MASK_MBIDCAM_ADDR_V1) << BIT_SHIFT_MBIDCAM_ADDR_V1) #define BITS_MBIDCAM_ADDR_V1 \ (BIT_MASK_MBIDCAM_ADDR_V1 << BIT_SHIFT_MBIDCAM_ADDR_V1) #define BIT_CLEAR_MBIDCAM_ADDR_V1(x) ((x) & (~BITS_MBIDCAM_ADDR_V1)) #define BIT_GET_MBIDCAM_ADDR_V1(x) \ (((x) >> BIT_SHIFT_MBIDCAM_ADDR_V1) & BIT_MASK_MBIDCAM_ADDR_V1) #define BIT_SET_MBIDCAM_ADDR_V1(x, v) \ (BIT_CLEAR_MBIDCAM_ADDR_V1(x) | BIT_MBIDCAM_ADDR_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ #define BIT_MBIDCAM_VALID BIT(23) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ #define BIT_SHIFT_MBIDCAM_ADDR_V2 23 #define BIT_MASK_MBIDCAM_ADDR_V2 0x7f #define BIT_MBIDCAM_ADDR_V2(x) \ (((x) & BIT_MASK_MBIDCAM_ADDR_V2) << BIT_SHIFT_MBIDCAM_ADDR_V2) #define BITS_MBIDCAM_ADDR_V2 \ (BIT_MASK_MBIDCAM_ADDR_V2 << BIT_SHIFT_MBIDCAM_ADDR_V2) #define BIT_CLEAR_MBIDCAM_ADDR_V2(x) ((x) & (~BITS_MBIDCAM_ADDR_V2)) #define BIT_GET_MBIDCAM_ADDR_V2(x) \ (((x) >> BIT_SHIFT_MBIDCAM_ADDR_V2) & BIT_MASK_MBIDCAM_ADDR_V2) #define BIT_SET_MBIDCAM_ADDR_V2(x, v) \ (BIT_CLEAR_MBIDCAM_ADDR_V2(x) | BIT_MBIDCAM_ADDR_V2(v)) #define BIT_MBIDCAM_RST BIT(19) #define BIT_MBIDCAM_VALID_V1 BIT(18) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ #define BIT_LSIC_TXOP_EN BIT(17) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ #define BIT_CTS_EN BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ #define BIT_REPEAT_MODE_EN BIT(16) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_WMAC_DEBUG_SEL (Offset 0x062C) */ #define BIT_SHIFT_WMAC_ARB_DBG_SEL 3 #define BIT_MASK_WMAC_ARB_DBG_SEL 0x3 #define BIT_WMAC_ARB_DBG_SEL(x) \ (((x) & BIT_MASK_WMAC_ARB_DBG_SEL) << BIT_SHIFT_WMAC_ARB_DBG_SEL) #define BITS_WMAC_ARB_DBG_SEL \ (BIT_MASK_WMAC_ARB_DBG_SEL << BIT_SHIFT_WMAC_ARB_DBG_SEL) #define BIT_CLEAR_WMAC_ARB_DBG_SEL(x) ((x) & (~BITS_WMAC_ARB_DBG_SEL)) #define BIT_GET_WMAC_ARB_DBG_SEL(x) \ (((x) >> BIT_SHIFT_WMAC_ARB_DBG_SEL) & BIT_MASK_WMAC_ARB_DBG_SEL) #define BIT_SET_WMAC_ARB_DBG_SEL(x, v) \ (BIT_CLEAR_WMAC_ARB_DBG_SEL(x) | BIT_WMAC_ARB_DBG_SEL(v)) #define BIT_WMAC_EXT_DBG_SEL BIT(2) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ #define BIT_SHIFT_MBIDCAM_RWDATA_H 0 #define BIT_MASK_MBIDCAM_RWDATA_H 0xffff #define BIT_MBIDCAM_RWDATA_H(x) \ (((x) & BIT_MASK_MBIDCAM_RWDATA_H) << BIT_SHIFT_MBIDCAM_RWDATA_H) #define BITS_MBIDCAM_RWDATA_H \ (BIT_MASK_MBIDCAM_RWDATA_H << BIT_SHIFT_MBIDCAM_RWDATA_H) #define BIT_CLEAR_MBIDCAM_RWDATA_H(x) ((x) & (~BITS_MBIDCAM_RWDATA_H)) #define BIT_GET_MBIDCAM_RWDATA_H(x) \ (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H) & BIT_MASK_MBIDCAM_RWDATA_H) #define BIT_SET_MBIDCAM_RWDATA_H(x, v) \ (BIT_CLEAR_MBIDCAM_RWDATA_H(x) | BIT_MBIDCAM_RWDATA_H(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_WMAC_DEBUG_SEL (Offset 0x062C) */ #define BIT_SHIFT_WMAC_MU_DBGSEL_V1 0 #define BIT_MASK_WMAC_MU_DBGSEL_V1 0x3 #define BIT_WMAC_MU_DBGSEL_V1(x) \ (((x) & BIT_MASK_WMAC_MU_DBGSEL_V1) << BIT_SHIFT_WMAC_MU_DBGSEL_V1) #define BITS_WMAC_MU_DBGSEL_V1 \ (BIT_MASK_WMAC_MU_DBGSEL_V1 << BIT_SHIFT_WMAC_MU_DBGSEL_V1) #define BIT_CLEAR_WMAC_MU_DBGSEL_V1(x) ((x) & (~BITS_WMAC_MU_DBGSEL_V1)) #define BIT_GET_WMAC_MU_DBGSEL_V1(x) \ (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_V1) & BIT_MASK_WMAC_MU_DBGSEL_V1) #define BIT_SET_WMAC_MU_DBGSEL_V1(x, v) \ (BIT_CLEAR_WMAC_MU_DBGSEL_V1(x) | BIT_WMAC_MU_DBGSEL_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MCU_TEST_1 (Offset 0x0630) */ #define BIT_SHIFT_MCU_RSVD 0 #define BIT_MASK_MCU_RSVD 0xffffffffL #define BIT_MCU_RSVD(x) (((x) & BIT_MASK_MCU_RSVD) << BIT_SHIFT_MCU_RSVD) #define BITS_MCU_RSVD (BIT_MASK_MCU_RSVD << BIT_SHIFT_MCU_RSVD) #define BIT_CLEAR_MCU_RSVD(x) ((x) & (~BITS_MCU_RSVD)) #define BIT_GET_MCU_RSVD(x) (((x) >> BIT_SHIFT_MCU_RSVD) & BIT_MASK_MCU_RSVD) #define BIT_SET_MCU_RSVD(x, v) (BIT_CLEAR_MCU_RSVD(x) | BIT_MCU_RSVD(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_TCR_TSFT_OFS (Offset 0x0630) */ #define BIT_SHIFT_WMAC_TCR_TSFT_OFS 0 #define BIT_MASK_WMAC_TCR_TSFT_OFS 0xffff #define BIT_WMAC_TCR_TSFT_OFS(x) \ (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS) << BIT_SHIFT_WMAC_TCR_TSFT_OFS) #define BITS_WMAC_TCR_TSFT_OFS \ (BIT_MASK_WMAC_TCR_TSFT_OFS << BIT_SHIFT_WMAC_TCR_TSFT_OFS) #define BIT_CLEAR_WMAC_TCR_TSFT_OFS(x) ((x) & (~BITS_WMAC_TCR_TSFT_OFS)) #define BIT_GET_WMAC_TCR_TSFT_OFS(x) \ (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS) & BIT_MASK_WMAC_TCR_TSFT_OFS) #define BIT_SET_WMAC_TCR_TSFT_OFS(x, v) \ (BIT_CLEAR_WMAC_TCR_TSFT_OFS(x) | BIT_WMAC_TCR_TSFT_OFS(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_UDF_THSD (Offset 0x0632) */ #define BIT_UDF_THSD_V1 BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_UDF_THSD (Offset 0x0632) */ #define BIT_SHIFT_UDF_THSD 0 #define BIT_MASK_UDF_THSD 0xff #define BIT_UDF_THSD(x) (((x) & BIT_MASK_UDF_THSD) << BIT_SHIFT_UDF_THSD) #define BITS_UDF_THSD (BIT_MASK_UDF_THSD << BIT_SHIFT_UDF_THSD) #define BIT_CLEAR_UDF_THSD(x) ((x) & (~BITS_UDF_THSD)) #define BIT_GET_UDF_THSD(x) (((x) >> BIT_SHIFT_UDF_THSD) & BIT_MASK_UDF_THSD) #define BIT_SET_UDF_THSD(x, v) (BIT_CLEAR_UDF_THSD(x) | BIT_UDF_THSD(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_UDF_THSD (Offset 0x0632) */ #define BIT_SHIFT_UDF_THSD_VALUE 0 #define BIT_MASK_UDF_THSD_VALUE 0x7f #define BIT_UDF_THSD_VALUE(x) \ (((x) & BIT_MASK_UDF_THSD_VALUE) << BIT_SHIFT_UDF_THSD_VALUE) #define BITS_UDF_THSD_VALUE \ (BIT_MASK_UDF_THSD_VALUE << BIT_SHIFT_UDF_THSD_VALUE) #define BIT_CLEAR_UDF_THSD_VALUE(x) ((x) & (~BITS_UDF_THSD_VALUE)) #define BIT_GET_UDF_THSD_VALUE(x) \ (((x) >> BIT_SHIFT_UDF_THSD_VALUE) & BIT_MASK_UDF_THSD_VALUE) #define BIT_SET_UDF_THSD_VALUE(x, v) \ (BIT_CLEAR_UDF_THSD_VALUE(x) | BIT_UDF_THSD_VALUE(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ZLD_NUM (Offset 0x0633) */ #define BIT_SHIFT_ZLD_NUM 0 #define BIT_MASK_ZLD_NUM 0xff #define BIT_ZLD_NUM(x) (((x) & BIT_MASK_ZLD_NUM) << BIT_SHIFT_ZLD_NUM) #define BITS_ZLD_NUM (BIT_MASK_ZLD_NUM << BIT_SHIFT_ZLD_NUM) #define BIT_CLEAR_ZLD_NUM(x) ((x) & (~BITS_ZLD_NUM)) #define BIT_GET_ZLD_NUM(x) (((x) >> BIT_SHIFT_ZLD_NUM) & BIT_MASK_ZLD_NUM) #define BIT_SET_ZLD_NUM(x, v) (BIT_CLEAR_ZLD_NUM(x) | BIT_ZLD_NUM(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MCU_TEST_2 (Offset 0x0634) */ #define BIT_SHIFT_MCU_RSVD_2 0 #define BIT_MASK_MCU_RSVD_2 0xffffffffL #define BIT_MCU_RSVD_2(x) (((x) & BIT_MASK_MCU_RSVD_2) << BIT_SHIFT_MCU_RSVD_2) #define BITS_MCU_RSVD_2 (BIT_MASK_MCU_RSVD_2 << BIT_SHIFT_MCU_RSVD_2) #define BIT_CLEAR_MCU_RSVD_2(x) ((x) & (~BITS_MCU_RSVD_2)) #define BIT_GET_MCU_RSVD_2(x) \ (((x) >> BIT_SHIFT_MCU_RSVD_2) & BIT_MASK_MCU_RSVD_2) #define BIT_SET_MCU_RSVD_2(x, v) (BIT_CLEAR_MCU_RSVD_2(x) | BIT_MCU_RSVD_2(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_STMP_THSD (Offset 0x0634) */ #define BIT_SHIFT_STMP_THSD 0 #define BIT_MASK_STMP_THSD 0xff #define BIT_STMP_THSD(x) (((x) & BIT_MASK_STMP_THSD) << BIT_SHIFT_STMP_THSD) #define BITS_STMP_THSD (BIT_MASK_STMP_THSD << BIT_SHIFT_STMP_THSD) #define BIT_CLEAR_STMP_THSD(x) ((x) & (~BITS_STMP_THSD)) #define BIT_GET_STMP_THSD(x) (((x) >> BIT_SHIFT_STMP_THSD) & BIT_MASK_STMP_THSD) #define BIT_SET_STMP_THSD(x, v) (BIT_CLEAR_STMP_THSD(x) | BIT_STMP_THSD(v)) /* 2 REG_WMAC_TXTIMEOUT (Offset 0x0635) */ #define BIT_SHIFT_WMAC_TXTIMEOUT 0 #define BIT_MASK_WMAC_TXTIMEOUT 0xff #define BIT_WMAC_TXTIMEOUT(x) \ (((x) & BIT_MASK_WMAC_TXTIMEOUT) << BIT_SHIFT_WMAC_TXTIMEOUT) #define BITS_WMAC_TXTIMEOUT \ (BIT_MASK_WMAC_TXTIMEOUT << BIT_SHIFT_WMAC_TXTIMEOUT) #define BIT_CLEAR_WMAC_TXTIMEOUT(x) ((x) & (~BITS_WMAC_TXTIMEOUT)) #define BIT_GET_WMAC_TXTIMEOUT(x) \ (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT) & BIT_MASK_WMAC_TXTIMEOUT) #define BIT_SET_WMAC_TXTIMEOUT(x, v) \ (BIT_CLEAR_WMAC_TXTIMEOUT(x) | BIT_WMAC_TXTIMEOUT(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_MCU_TEST_2_V1 (Offset 0x0636) */ #define BIT_SHIFT_MCU_RSVD_2_V1 0 #define BIT_MASK_MCU_RSVD_2_V1 0xffff #define BIT_MCU_RSVD_2_V1(x) \ (((x) & BIT_MASK_MCU_RSVD_2_V1) << BIT_SHIFT_MCU_RSVD_2_V1) #define BITS_MCU_RSVD_2_V1 (BIT_MASK_MCU_RSVD_2_V1 << BIT_SHIFT_MCU_RSVD_2_V1) #define BIT_CLEAR_MCU_RSVD_2_V1(x) ((x) & (~BITS_MCU_RSVD_2_V1)) #define BIT_GET_MCU_RSVD_2_V1(x) \ (((x) >> BIT_SHIFT_MCU_RSVD_2_V1) & BIT_MASK_MCU_RSVD_2_V1) #define BIT_SET_MCU_RSVD_2_V1(x, v) \ (BIT_CLEAR_MCU_RSVD_2_V1(x) | BIT_MCU_RSVD_2_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_USTIME_EDCA (Offset 0x0638) */ #define BIT_SHIFT_USTIME_EDCA 0 #define BIT_MASK_USTIME_EDCA 0xff #define BIT_USTIME_EDCA(x) \ (((x) & BIT_MASK_USTIME_EDCA) << BIT_SHIFT_USTIME_EDCA) #define BITS_USTIME_EDCA (BIT_MASK_USTIME_EDCA << BIT_SHIFT_USTIME_EDCA) #define BIT_CLEAR_USTIME_EDCA(x) ((x) & (~BITS_USTIME_EDCA)) #define BIT_GET_USTIME_EDCA(x) \ (((x) >> BIT_SHIFT_USTIME_EDCA) & BIT_MASK_USTIME_EDCA) #define BIT_SET_USTIME_EDCA(x, v) \ (BIT_CLEAR_USTIME_EDCA(x) | BIT_USTIME_EDCA(v)) #endif #if (HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_USTIME_EDCA (Offset 0x0638) */ #define BIT_SHIFT_USTIME_EDCA_V1 0 #define BIT_MASK_USTIME_EDCA_V1 0x1ff #define BIT_USTIME_EDCA_V1(x) \ (((x) & BIT_MASK_USTIME_EDCA_V1) << BIT_SHIFT_USTIME_EDCA_V1) #define BITS_USTIME_EDCA_V1 \ (BIT_MASK_USTIME_EDCA_V1 << BIT_SHIFT_USTIME_EDCA_V1) #define BIT_CLEAR_USTIME_EDCA_V1(x) ((x) & (~BITS_USTIME_EDCA_V1)) #define BIT_GET_USTIME_EDCA_V1(x) \ (((x) >> BIT_SHIFT_USTIME_EDCA_V1) & BIT_MASK_USTIME_EDCA_V1) #define BIT_SET_USTIME_EDCA_V1(x, v) \ (BIT_CLEAR_USTIME_EDCA_V1(x) | BIT_USTIME_EDCA_V1(v)) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_ACKTO_CCK (Offset 0x0639) */ #define BIT_SHIFT_ACKTO_CCK 0 #define BIT_MASK_ACKTO_CCK 0xff #define BIT_ACKTO_CCK(x) (((x) & BIT_MASK_ACKTO_CCK) << BIT_SHIFT_ACKTO_CCK) #define BITS_ACKTO_CCK (BIT_MASK_ACKTO_CCK << BIT_SHIFT_ACKTO_CCK) #define BIT_CLEAR_ACKTO_CCK(x) ((x) & (~BITS_ACKTO_CCK)) #define BIT_GET_ACKTO_CCK(x) (((x) >> BIT_SHIFT_ACKTO_CCK) & BIT_MASK_ACKTO_CCK) #define BIT_SET_ACKTO_CCK(x, v) (BIT_CLEAR_ACKTO_CCK(x) | BIT_ACKTO_CCK(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MAC_SPEC_SIFS (Offset 0x063A) */ #define BIT_SHIFT_SPEC_SIFS_OFDM 8 #define BIT_MASK_SPEC_SIFS_OFDM 0xff #define BIT_SPEC_SIFS_OFDM(x) \ (((x) & BIT_MASK_SPEC_SIFS_OFDM) << BIT_SHIFT_SPEC_SIFS_OFDM) #define BITS_SPEC_SIFS_OFDM \ (BIT_MASK_SPEC_SIFS_OFDM << BIT_SHIFT_SPEC_SIFS_OFDM) #define BIT_CLEAR_SPEC_SIFS_OFDM(x) ((x) & (~BITS_SPEC_SIFS_OFDM)) #define BIT_GET_SPEC_SIFS_OFDM(x) \ (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM) & BIT_MASK_SPEC_SIFS_OFDM) #define BIT_SET_SPEC_SIFS_OFDM(x, v) \ (BIT_CLEAR_SPEC_SIFS_OFDM(x) | BIT_SPEC_SIFS_OFDM(v)) #define BIT_SHIFT_SPEC_SIFS_CCK 0 #define BIT_MASK_SPEC_SIFS_CCK 0xff #define BIT_SPEC_SIFS_CCK(x) \ (((x) & BIT_MASK_SPEC_SIFS_CCK) << BIT_SHIFT_SPEC_SIFS_CCK) #define BITS_SPEC_SIFS_CCK (BIT_MASK_SPEC_SIFS_CCK << BIT_SHIFT_SPEC_SIFS_CCK) #define BIT_CLEAR_SPEC_SIFS_CCK(x) ((x) & (~BITS_SPEC_SIFS_CCK)) #define BIT_GET_SPEC_SIFS_CCK(x) \ (((x) >> BIT_SHIFT_SPEC_SIFS_CCK) & BIT_MASK_SPEC_SIFS_CCK) #define BIT_SET_SPEC_SIFS_CCK(x, v) \ (BIT_CLEAR_SPEC_SIFS_CCK(x) | BIT_SPEC_SIFS_CCK(v)) /* 2 REG_RESP_SIFS_CCK (Offset 0x063C) */ #define BIT_SHIFT_SIFS_R2T_CCK 8 #define BIT_MASK_SIFS_R2T_CCK 0xff #define BIT_SIFS_R2T_CCK(x) \ (((x) & BIT_MASK_SIFS_R2T_CCK) << BIT_SHIFT_SIFS_R2T_CCK) #define BITS_SIFS_R2T_CCK (BIT_MASK_SIFS_R2T_CCK << BIT_SHIFT_SIFS_R2T_CCK) #define BIT_CLEAR_SIFS_R2T_CCK(x) ((x) & (~BITS_SIFS_R2T_CCK)) #define BIT_GET_SIFS_R2T_CCK(x) \ (((x) >> BIT_SHIFT_SIFS_R2T_CCK) & BIT_MASK_SIFS_R2T_CCK) #define BIT_SET_SIFS_R2T_CCK(x, v) \ (BIT_CLEAR_SIFS_R2T_CCK(x) | BIT_SIFS_R2T_CCK(v)) #define BIT_SHIFT_SIFS_T2T_CCK 0 #define BIT_MASK_SIFS_T2T_CCK 0xff #define BIT_SIFS_T2T_CCK(x) \ (((x) & BIT_MASK_SIFS_T2T_CCK) << BIT_SHIFT_SIFS_T2T_CCK) #define BITS_SIFS_T2T_CCK (BIT_MASK_SIFS_T2T_CCK << BIT_SHIFT_SIFS_T2T_CCK) #define BIT_CLEAR_SIFS_T2T_CCK(x) ((x) & (~BITS_SIFS_T2T_CCK)) #define BIT_GET_SIFS_T2T_CCK(x) \ (((x) >> BIT_SHIFT_SIFS_T2T_CCK) & BIT_MASK_SIFS_T2T_CCK) #define BIT_SET_SIFS_T2T_CCK(x, v) \ (BIT_CLEAR_SIFS_T2T_CCK(x) | BIT_SIFS_T2T_CCK(v)) /* 2 REG_RESP_SIFS_OFDM (Offset 0x063E) */ #define BIT_SHIFT_SIFS_R2T_OFDM 8 #define BIT_MASK_SIFS_R2T_OFDM 0xff #define BIT_SIFS_R2T_OFDM(x) \ (((x) & BIT_MASK_SIFS_R2T_OFDM) << BIT_SHIFT_SIFS_R2T_OFDM) #define BITS_SIFS_R2T_OFDM (BIT_MASK_SIFS_R2T_OFDM << BIT_SHIFT_SIFS_R2T_OFDM) #define BIT_CLEAR_SIFS_R2T_OFDM(x) ((x) & (~BITS_SIFS_R2T_OFDM)) #define BIT_GET_SIFS_R2T_OFDM(x) \ (((x) >> BIT_SHIFT_SIFS_R2T_OFDM) & BIT_MASK_SIFS_R2T_OFDM) #define BIT_SET_SIFS_R2T_OFDM(x, v) \ (BIT_CLEAR_SIFS_R2T_OFDM(x) | BIT_SIFS_R2T_OFDM(v)) #define BIT_SHIFT_SIFS_T2T_OFDM 0 #define BIT_MASK_SIFS_T2T_OFDM 0xff #define BIT_SIFS_T2T_OFDM(x) \ (((x) & BIT_MASK_SIFS_T2T_OFDM) << BIT_SHIFT_SIFS_T2T_OFDM) #define BITS_SIFS_T2T_OFDM (BIT_MASK_SIFS_T2T_OFDM << BIT_SHIFT_SIFS_T2T_OFDM) #define BIT_CLEAR_SIFS_T2T_OFDM(x) ((x) & (~BITS_SIFS_T2T_OFDM)) #define BIT_GET_SIFS_T2T_OFDM(x) \ (((x) >> BIT_SHIFT_SIFS_T2T_OFDM) & BIT_MASK_SIFS_T2T_OFDM) #define BIT_SET_SIFS_T2T_OFDM(x, v) \ (BIT_CLEAR_SIFS_T2T_OFDM(x) | BIT_SIFS_T2T_OFDM(v)) /* 2 REG_ACKTO (Offset 0x0640) */ #define BIT_SHIFT_ACKTO 0 #define BIT_MASK_ACKTO 0xff #define BIT_ACKTO(x) (((x) & BIT_MASK_ACKTO) << BIT_SHIFT_ACKTO) #define BITS_ACKTO (BIT_MASK_ACKTO << BIT_SHIFT_ACKTO) #define BIT_CLEAR_ACKTO(x) ((x) & (~BITS_ACKTO)) #define BIT_GET_ACKTO(x) (((x) >> BIT_SHIFT_ACKTO) & BIT_MASK_ACKTO) #define BIT_SET_ACKTO(x, v) (BIT_CLEAR_ACKTO(x) | BIT_ACKTO(v)) /* 2 REG_CTS2TO (Offset 0x0641) */ #define BIT_SHIFT_CTS2TO 0 #define BIT_MASK_CTS2TO 0xff #define BIT_CTS2TO(x) (((x) & BIT_MASK_CTS2TO) << BIT_SHIFT_CTS2TO) #define BITS_CTS2TO (BIT_MASK_CTS2TO << BIT_SHIFT_CTS2TO) #define BIT_CLEAR_CTS2TO(x) ((x) & (~BITS_CTS2TO)) #define BIT_GET_CTS2TO(x) (((x) >> BIT_SHIFT_CTS2TO) & BIT_MASK_CTS2TO) #define BIT_SET_CTS2TO(x, v) (BIT_CLEAR_CTS2TO(x) | BIT_CTS2TO(v)) /* 2 REG_EIFS (Offset 0x0642) */ #define BIT_SHIFT_EIFS 0 #define BIT_MASK_EIFS 0xffff #define BIT_EIFS(x) (((x) & BIT_MASK_EIFS) << BIT_SHIFT_EIFS) #define BITS_EIFS (BIT_MASK_EIFS << BIT_SHIFT_EIFS) #define BIT_CLEAR_EIFS(x) ((x) & (~BITS_EIFS)) #define BIT_GET_EIFS(x) (((x) >> BIT_SHIFT_EIFS) & BIT_MASK_EIFS) #define BIT_SET_EIFS(x, v) (BIT_CLEAR_EIFS(x) | BIT_EIFS(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RPFM_MAP0 (Offset 0x0644) */ #define BIT_MGT_RPFM15EN BIT(15) #define BIT_MGT_RPFM14EN BIT(14) #define BIT_MGT_RPFM13EN BIT(13) #define BIT_MGT_RPFM12EN BIT(12) #define BIT_MGT_RPFM11EN BIT(11) #define BIT_MGT_RPFM10EN BIT(10) #define BIT_MGT_RPFM9EN BIT(9) #define BIT_MGT_RPFM8EN BIT(8) #define BIT_MGT_RPFM7EN BIT(7) #define BIT_MGT_RPFM6EN BIT(6) #define BIT_MGT_RPFM5EN BIT(5) #define BIT_MGT_RPFM4EN BIT(4) #define BIT_MGT_RPFM3EN BIT(3) #define BIT_MGT_RPFM2EN BIT(2) #define BIT_MGT_RPFM1EN BIT(1) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_RPFM_MAP0 (Offset 0x0644) */ #define BIT_SHIFT_RPFM_MAP0 0 #define BIT_MASK_RPFM_MAP0 0xffff #define BIT_RPFM_MAP0(x) (((x) & BIT_MASK_RPFM_MAP0) << BIT_SHIFT_RPFM_MAP0) #define BITS_RPFM_MAP0 (BIT_MASK_RPFM_MAP0 << BIT_SHIFT_RPFM_MAP0) #define BIT_CLEAR_RPFM_MAP0(x) ((x) & (~BITS_RPFM_MAP0)) #define BIT_GET_RPFM_MAP0(x) (((x) >> BIT_SHIFT_RPFM_MAP0) & BIT_MASK_RPFM_MAP0) #define BIT_SET_RPFM_MAP0(x, v) (BIT_CLEAR_RPFM_MAP0(x) | BIT_RPFM_MAP0(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RPFM_MAP0 (Offset 0x0644) */ #define BIT_MGT_RPFM0EN BIT(0) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_RPFM_MAP1 (Offset 0x0646) */ #define BIT_SHIFT_RPFM_MAP1 0 #define BIT_MASK_RPFM_MAP1 0xffff #define BIT_RPFM_MAP1(x) (((x) & BIT_MASK_RPFM_MAP1) << BIT_SHIFT_RPFM_MAP1) #define BITS_RPFM_MAP1 (BIT_MASK_RPFM_MAP1 << BIT_SHIFT_RPFM_MAP1) #define BIT_CLEAR_RPFM_MAP1(x) ((x) & (~BITS_RPFM_MAP1)) #define BIT_GET_RPFM_MAP1(x) (((x) >> BIT_SHIFT_RPFM_MAP1) & BIT_MASK_RPFM_MAP1) #define BIT_SET_RPFM_MAP1(x, v) (BIT_CLEAR_RPFM_MAP1(x) | BIT_RPFM_MAP1(v)) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */ #define BIT_RPFM_CAM_POLLING BIT(31) #define BIT_RPFM_CAM_CLR BIT(30) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */ #define BIT_RPFM_CAM_WR BIT(16) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */ #define BIT_RPFM_CAM_WE BIT(16) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */ #define BIT_SHIFT_RPFM_CAM_ADDR 0 #define BIT_MASK_RPFM_CAM_ADDR 0x7f #define BIT_RPFM_CAM_ADDR(x) \ (((x) & BIT_MASK_RPFM_CAM_ADDR) << BIT_SHIFT_RPFM_CAM_ADDR) #define BITS_RPFM_CAM_ADDR (BIT_MASK_RPFM_CAM_ADDR << BIT_SHIFT_RPFM_CAM_ADDR) #define BIT_CLEAR_RPFM_CAM_ADDR(x) ((x) & (~BITS_RPFM_CAM_ADDR)) #define BIT_GET_RPFM_CAM_ADDR(x) \ (((x) >> BIT_SHIFT_RPFM_CAM_ADDR) & BIT_MASK_RPFM_CAM_ADDR) #define BIT_SET_RPFM_CAM_ADDR(x, v) \ (BIT_CLEAR_RPFM_CAM_ADDR(x) | BIT_RPFM_CAM_ADDR(v)) /* 2 REG_RPFM_CAM_RWD (Offset 0x064C) */ #define BIT_SHIFT_RPFM_CAM_RWD 0 #define BIT_MASK_RPFM_CAM_RWD 0xffffffffL #define BIT_RPFM_CAM_RWD(x) \ (((x) & BIT_MASK_RPFM_CAM_RWD) << BIT_SHIFT_RPFM_CAM_RWD) #define BITS_RPFM_CAM_RWD (BIT_MASK_RPFM_CAM_RWD << BIT_SHIFT_RPFM_CAM_RWD) #define BIT_CLEAR_RPFM_CAM_RWD(x) ((x) & (~BITS_RPFM_CAM_RWD)) #define BIT_GET_RPFM_CAM_RWD(x) \ (((x) >> BIT_SHIFT_RPFM_CAM_RWD) & BIT_MASK_RPFM_CAM_RWD) #define BIT_SET_RPFM_CAM_RWD(x, v) \ (BIT_CLEAR_RPFM_CAM_RWD(x) | BIT_RPFM_CAM_RWD(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_NAV_CTRL (Offset 0x0650) */ #define BIT_SHIFT_NAV_UPPER 16 #define BIT_MASK_NAV_UPPER 0xff #define BIT_NAV_UPPER(x) (((x) & BIT_MASK_NAV_UPPER) << BIT_SHIFT_NAV_UPPER) #define BITS_NAV_UPPER (BIT_MASK_NAV_UPPER << BIT_SHIFT_NAV_UPPER) #define BIT_CLEAR_NAV_UPPER(x) ((x) & (~BITS_NAV_UPPER)) #define BIT_GET_NAV_UPPER(x) (((x) >> BIT_SHIFT_NAV_UPPER) & BIT_MASK_NAV_UPPER) #define BIT_SET_NAV_UPPER(x, v) (BIT_CLEAR_NAV_UPPER(x) | BIT_NAV_UPPER(v)) #define BIT_SHIFT_RXMYRTS_NAV 8 #define BIT_MASK_RXMYRTS_NAV 0xf #define BIT_RXMYRTS_NAV(x) \ (((x) & BIT_MASK_RXMYRTS_NAV) << BIT_SHIFT_RXMYRTS_NAV) #define BITS_RXMYRTS_NAV (BIT_MASK_RXMYRTS_NAV << BIT_SHIFT_RXMYRTS_NAV) #define BIT_CLEAR_RXMYRTS_NAV(x) ((x) & (~BITS_RXMYRTS_NAV)) #define BIT_GET_RXMYRTS_NAV(x) \ (((x) >> BIT_SHIFT_RXMYRTS_NAV) & BIT_MASK_RXMYRTS_NAV) #define BIT_SET_RXMYRTS_NAV(x, v) \ (BIT_CLEAR_RXMYRTS_NAV(x) | BIT_RXMYRTS_NAV(v)) #define BIT_SHIFT_RTSRST 0 #define BIT_MASK_RTSRST 0xff #define BIT_RTSRST(x) (((x) & BIT_MASK_RTSRST) << BIT_SHIFT_RTSRST) #define BITS_RTSRST (BIT_MASK_RTSRST << BIT_SHIFT_RTSRST) #define BIT_CLEAR_RTSRST(x) ((x) & (~BITS_RTSRST)) #define BIT_GET_RTSRST(x) (((x) >> BIT_SHIFT_RTSRST) & BIT_MASK_RTSRST) #define BIT_SET_RTSRST(x, v) (BIT_CLEAR_RTSRST(x) | BIT_RTSRST(v)) /* 2 REG_BACAMCMD (Offset 0x0654) */ #define BIT_BACAM_POLL BIT(31) #define BIT_BACAM_RST BIT(17) #define BIT_BACAM_RW BIT(16) #define BIT_SHIFT_TXSBM 14 #define BIT_MASK_TXSBM 0x3 #define BIT_TXSBM(x) (((x) & BIT_MASK_TXSBM) << BIT_SHIFT_TXSBM) #define BITS_TXSBM (BIT_MASK_TXSBM << BIT_SHIFT_TXSBM) #define BIT_CLEAR_TXSBM(x) ((x) & (~BITS_TXSBM)) #define BIT_GET_TXSBM(x) (((x) >> BIT_SHIFT_TXSBM) & BIT_MASK_TXSBM) #define BIT_SET_TXSBM(x, v) (BIT_CLEAR_TXSBM(x) | BIT_TXSBM(v)) #define BIT_SHIFT_BACAM_ADDR 0 #define BIT_MASK_BACAM_ADDR 0x3f #define BIT_BACAM_ADDR(x) (((x) & BIT_MASK_BACAM_ADDR) << BIT_SHIFT_BACAM_ADDR) #define BITS_BACAM_ADDR (BIT_MASK_BACAM_ADDR << BIT_SHIFT_BACAM_ADDR) #define BIT_CLEAR_BACAM_ADDR(x) ((x) & (~BITS_BACAM_ADDR)) #define BIT_GET_BACAM_ADDR(x) \ (((x) >> BIT_SHIFT_BACAM_ADDR) & BIT_MASK_BACAM_ADDR) #define BIT_SET_BACAM_ADDR(x, v) (BIT_CLEAR_BACAM_ADDR(x) | BIT_BACAM_ADDR(v)) /* 2 REG_BACAMCONTENT (Offset 0x0658) */ #define BIT_SHIFT_BA_CONTENT_L 0 #define BIT_MASK_BA_CONTENT_L 0xffffffffL #define BIT_BA_CONTENT_L(x) \ (((x) & BIT_MASK_BA_CONTENT_L) << BIT_SHIFT_BA_CONTENT_L) #define BITS_BA_CONTENT_L (BIT_MASK_BA_CONTENT_L << BIT_SHIFT_BA_CONTENT_L) #define BIT_CLEAR_BA_CONTENT_L(x) ((x) & (~BITS_BA_CONTENT_L)) #define BIT_GET_BA_CONTENT_L(x) \ (((x) >> BIT_SHIFT_BA_CONTENT_L) & BIT_MASK_BA_CONTENT_L) #define BIT_SET_BA_CONTENT_L(x, v) \ (BIT_CLEAR_BA_CONTENT_L(x) | BIT_BA_CONTENT_L(v)) /* 2 REG_LBDLY (Offset 0x0660) */ #define BIT_SHIFT_LBDLY 0 #define BIT_MASK_LBDLY 0x1f #define BIT_LBDLY(x) (((x) & BIT_MASK_LBDLY) << BIT_SHIFT_LBDLY) #define BITS_LBDLY (BIT_MASK_LBDLY << BIT_SHIFT_LBDLY) #define BIT_CLEAR_LBDLY(x) ((x) & (~BITS_LBDLY)) #define BIT_GET_LBDLY(x) (((x) >> BIT_SHIFT_LBDLY) & BIT_MASK_LBDLY) #define BIT_SET_LBDLY(x, v) (BIT_CLEAR_LBDLY(x) | BIT_LBDLY(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */ #define BIT_SHIFT_BITMAP_SSNBK_COUNTER 2 #define BIT_MASK_BITMAP_SSNBK_COUNTER 0x3f #define BIT_BITMAP_SSNBK_COUNTER(x) \ (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER) \ << BIT_SHIFT_BITMAP_SSNBK_COUNTER) #define BITS_BITMAP_SSNBK_COUNTER \ (BIT_MASK_BITMAP_SSNBK_COUNTER << BIT_SHIFT_BITMAP_SSNBK_COUNTER) #define BIT_CLEAR_BITMAP_SSNBK_COUNTER(x) ((x) & (~BITS_BITMAP_SSNBK_COUNTER)) #define BIT_GET_BITMAP_SSNBK_COUNTER(x) \ (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER) & \ BIT_MASK_BITMAP_SSNBK_COUNTER) #define BIT_SET_BITMAP_SSNBK_COUNTER(x, v) \ (BIT_CLEAR_BITMAP_SSNBK_COUNTER(x) | BIT_BITMAP_SSNBK_COUNTER(v)) #define BIT_BITMAP_EN BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */ #define BIT_WMAC_BACAM_RPMEN BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TX_RX (Offset 0x0662) */ #define BIT_SHIFT_RXPKT_TYPE 2 #define BIT_MASK_RXPKT_TYPE 0x3f #define BIT_RXPKT_TYPE(x) (((x) & BIT_MASK_RXPKT_TYPE) << BIT_SHIFT_RXPKT_TYPE) #define BITS_RXPKT_TYPE (BIT_MASK_RXPKT_TYPE << BIT_SHIFT_RXPKT_TYPE) #define BIT_CLEAR_RXPKT_TYPE(x) ((x) & (~BITS_RXPKT_TYPE)) #define BIT_GET_RXPKT_TYPE(x) \ (((x) >> BIT_SHIFT_RXPKT_TYPE) & BIT_MASK_RXPKT_TYPE) #define BIT_SET_RXPKT_TYPE(x, v) (BIT_CLEAR_RXPKT_TYPE(x) | BIT_RXPKT_TYPE(v)) #define BIT_TXACT_IND BIT(1) #define BIT_RXACT_IND BIT(0) /* 2 REG_WMAC_BITMAP_CTL (Offset 0x0663) */ #define BIT_BITMAP_VO BIT(7) #define BIT_BITMAP_VI BIT(6) #define BIT_BITMAP_BE BIT(5) #define BIT_BITMAP_BK BIT(4) #define BIT_SHIFT_BITMAP_CONDITION 2 #define BIT_MASK_BITMAP_CONDITION 0x3 #define BIT_BITMAP_CONDITION(x) \ (((x) & BIT_MASK_BITMAP_CONDITION) << BIT_SHIFT_BITMAP_CONDITION) #define BITS_BITMAP_CONDITION \ (BIT_MASK_BITMAP_CONDITION << BIT_SHIFT_BITMAP_CONDITION) #define BIT_CLEAR_BITMAP_CONDITION(x) ((x) & (~BITS_BITMAP_CONDITION)) #define BIT_GET_BITMAP_CONDITION(x) \ (((x) >> BIT_SHIFT_BITMAP_CONDITION) & BIT_MASK_BITMAP_CONDITION) #define BIT_SET_BITMAP_CONDITION(x, v) \ (BIT_CLEAR_BITMAP_CONDITION(x) | BIT_BITMAP_CONDITION(v)) #define BIT_BITMAP_SSNBK_COUNTER_CLR BIT(1) #define BIT_BITMAP_FORCE BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ #define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0 28 #define BIT_MASK_RXERR_RPT_SEL_V1_3_0 0xf #define BIT_RXERR_RPT_SEL_V1_3_0(x) \ (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0) \ << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) #define BITS_RXERR_RPT_SEL_V1_3_0 \ (BIT_MASK_RXERR_RPT_SEL_V1_3_0 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) #define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0(x) ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0)) #define BIT_GET_RXERR_RPT_SEL_V1_3_0(x) \ (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) & \ BIT_MASK_RXERR_RPT_SEL_V1_3_0) #define BIT_SET_RXERR_RPT_SEL_V1_3_0(x, v) \ (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0(x) | BIT_RXERR_RPT_SEL_V1_3_0(v)) #endif #if (HALMAC_8881A_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ #define BIT_SHIFT_RXERR_RPT_SEL 28 #define BIT_MASK_RXERR_RPT_SEL 0xf #define BIT_RXERR_RPT_SEL(x) \ (((x) & BIT_MASK_RXERR_RPT_SEL) << BIT_SHIFT_RXERR_RPT_SEL) #define BITS_RXERR_RPT_SEL (BIT_MASK_RXERR_RPT_SEL << BIT_SHIFT_RXERR_RPT_SEL) #define BIT_CLEAR_RXERR_RPT_SEL(x) ((x) & (~BITS_RXERR_RPT_SEL)) #define BIT_GET_RXERR_RPT_SEL(x) \ (((x) >> BIT_SHIFT_RXERR_RPT_SEL) & BIT_MASK_RXERR_RPT_SEL) #define BIT_SET_RXERR_RPT_SEL(x, v) \ (BIT_CLEAR_RXERR_RPT_SEL(x) | BIT_RXERR_RPT_SEL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ #define BIT_RXERR_RPT_RST BIT(27) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ #define BIT_RXERR_RPT_SEL_V1_4 BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ #define BIT_SHIFT_UD_SELECT_BSSID_2_1 24 #define BIT_MASK_UD_SELECT_BSSID_2_1 0x3 #define BIT_UD_SELECT_BSSID_2_1(x) \ (((x) & BIT_MASK_UD_SELECT_BSSID_2_1) << BIT_SHIFT_UD_SELECT_BSSID_2_1) #define BITS_UD_SELECT_BSSID_2_1 \ (BIT_MASK_UD_SELECT_BSSID_2_1 << BIT_SHIFT_UD_SELECT_BSSID_2_1) #define BIT_CLEAR_UD_SELECT_BSSID_2_1(x) ((x) & (~BITS_UD_SELECT_BSSID_2_1)) #define BIT_GET_UD_SELECT_BSSID_2_1(x) \ (((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1) & BIT_MASK_UD_SELECT_BSSID_2_1) #define BIT_SET_UD_SELECT_BSSID_2_1(x, v) \ (BIT_CLEAR_UD_SELECT_BSSID_2_1(x) | BIT_UD_SELECT_BSSID_2_1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ #define BIT_W1S BIT(23) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ #define BIT_UD_SELECT_BSSID BIT(22) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ #define BIT_UD_SELECT_BSSID_0 BIT(22) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RXERR_RPT (Offset 0x0664) */ #define BIT_SHIFT_UD_SUB_TYPE 18 #define BIT_MASK_UD_SUB_TYPE 0xf #define BIT_UD_SUB_TYPE(x) \ (((x) & BIT_MASK_UD_SUB_TYPE) << BIT_SHIFT_UD_SUB_TYPE) #define BITS_UD_SUB_TYPE (BIT_MASK_UD_SUB_TYPE << BIT_SHIFT_UD_SUB_TYPE) #define BIT_CLEAR_UD_SUB_TYPE(x) ((x) & (~BITS_UD_SUB_TYPE)) #define BIT_GET_UD_SUB_TYPE(x) \ (((x) >> BIT_SHIFT_UD_SUB_TYPE) & BIT_MASK_UD_SUB_TYPE) #define BIT_SET_UD_SUB_TYPE(x, v) \ (BIT_CLEAR_UD_SUB_TYPE(x) | BIT_UD_SUB_TYPE(v)) #define BIT_SHIFT_UD_TYPE 16 #define BIT_MASK_UD_TYPE 0x3 #define BIT_UD_TYPE(x) (((x) & BIT_MASK_UD_TYPE) << BIT_SHIFT_UD_TYPE) #define BITS_UD_TYPE (BIT_MASK_UD_TYPE << BIT_SHIFT_UD_TYPE) #define BIT_CLEAR_UD_TYPE(x) ((x) & (~BITS_UD_TYPE)) #define BIT_GET_UD_TYPE(x) (((x) >> BIT_SHIFT_UD_TYPE) & BIT_MASK_UD_TYPE) #define BIT_SET_UD_TYPE(x, v) (BIT_CLEAR_UD_TYPE(x) | BIT_UD_TYPE(v)) #define BIT_SHIFT_RPT_COUNTER 0 #define BIT_MASK_RPT_COUNTER 0xffff #define BIT_RPT_COUNTER(x) \ (((x) & BIT_MASK_RPT_COUNTER) << BIT_SHIFT_RPT_COUNTER) #define BITS_RPT_COUNTER (BIT_MASK_RPT_COUNTER << BIT_SHIFT_RPT_COUNTER) #define BIT_CLEAR_RPT_COUNTER(x) ((x) & (~BITS_RPT_COUNTER)) #define BIT_GET_RPT_COUNTER(x) \ (((x) >> BIT_SHIFT_RPT_COUNTER) & BIT_MASK_RPT_COUNTER) #define BIT_SET_RPT_COUNTER(x, v) \ (BIT_CLEAR_RPT_COUNTER(x) | BIT_RPT_COUNTER(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ #define BIT_RXBA_IGNOREA2 BIT(42) #define BIT_EN_SAVE_ALL_TXOPADDR BIT(41) #define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV BIT(40) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ #define BIT_DIS_TXBA_AMPDUFCSERR BIT(39) #define BIT_DIS_TXBA_RXBARINFULL BIT(38) #define BIT_DIS_TXCFE_INFULL BIT(37) #define BIT_DIS_TXCTS_INFULL BIT(36) #define BIT_EN_TXACKBA_IN_TX_RDG BIT(35) #define BIT_EN_TXACKBA_IN_TXOP BIT(34) #define BIT_EN_TXCTS_IN_RXNAV BIT(33) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ #define BIT_EN_TXCTS_INTXOP BIT(32) #define BIT_BLK_EDCA_BBSLP BIT(31) #define BIT_BLK_EDCA_BBSBY BIT(30) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ #define BIT_ACKTO_BLOCK_SCH_EN BIT(27) #define BIT_EIFS_BLOCK_SCH_EN BIT(26) #define BIT_PLCPCHK_RST_EIFS BIT(25) #define BIT_CCA_RST_EIFS BIT(24) #define BIT_DIS_UPD_MYRXPKTNAV BIT(23) #define BIT_EARLY_TXBA BIT(22) #define BIT_SHIFT_RESP_CHNBUSY 20 #define BIT_MASK_RESP_CHNBUSY 0x3 #define BIT_RESP_CHNBUSY(x) \ (((x) & BIT_MASK_RESP_CHNBUSY) << BIT_SHIFT_RESP_CHNBUSY) #define BITS_RESP_CHNBUSY (BIT_MASK_RESP_CHNBUSY << BIT_SHIFT_RESP_CHNBUSY) #define BIT_CLEAR_RESP_CHNBUSY(x) ((x) & (~BITS_RESP_CHNBUSY)) #define BIT_GET_RESP_CHNBUSY(x) \ (((x) >> BIT_SHIFT_RESP_CHNBUSY) & BIT_MASK_RESP_CHNBUSY) #define BIT_SET_RESP_CHNBUSY(x, v) \ (BIT_CLEAR_RESP_CHNBUSY(x) | BIT_RESP_CHNBUSY(v)) #define BIT_RESP_DCTS_EN BIT(19) #define BIT_RESP_DCFE_EN BIT(18) #define BIT_RESP_SPLCPEN BIT(17) #define BIT_RESP_SGIEN BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ #define BIT_RESP_LDPC_EN BIT(15) #define BIT_DIS_RESP_ACKINCCA BIT(14) #define BIT_DIS_RESP_CTSINCCA BIT(13) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ #define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER 10 #define BIT_MASK_R_WMAC_SECOND_CCA_TIMER 0x7 #define BIT_R_WMAC_SECOND_CCA_TIMER(x) \ (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER) \ << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) #define BITS_R_WMAC_SECOND_CCA_TIMER \ (BIT_MASK_R_WMAC_SECOND_CCA_TIMER << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) #define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER(x) \ ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER)) #define BIT_GET_R_WMAC_SECOND_CCA_TIMER(x) \ (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) & \ BIT_MASK_R_WMAC_SECOND_CCA_TIMER) #define BIT_SET_R_WMAC_SECOND_CCA_TIMER(x, v) \ (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER(x) | BIT_R_WMAC_SECOND_CCA_TIMER(v)) #endif #if (HALMAC_8814AMP_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ #define BIT_SHIFT_SECOND_CCA_CNT 10 #define BIT_MASK_SECOND_CCA_CNT 0x7 #define BIT_SECOND_CCA_CNT(x) \ (((x) & BIT_MASK_SECOND_CCA_CNT) << BIT_SHIFT_SECOND_CCA_CNT) #define BITS_SECOND_CCA_CNT \ (BIT_MASK_SECOND_CCA_CNT << BIT_SHIFT_SECOND_CCA_CNT) #define BIT_CLEAR_SECOND_CCA_CNT(x) ((x) & (~BITS_SECOND_CCA_CNT)) #define BIT_GET_SECOND_CCA_CNT(x) \ (((x) >> BIT_SHIFT_SECOND_CCA_CNT) & BIT_MASK_SECOND_CCA_CNT) #define BIT_SET_SECOND_CCA_CNT(x, v) \ (BIT_CLEAR_SECOND_CCA_CNT(x) | BIT_SECOND_CCA_CNT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ #define BIT_SHIFT_RFMOD 7 #define BIT_MASK_RFMOD 0x3 #define BIT_RFMOD(x) (((x) & BIT_MASK_RFMOD) << BIT_SHIFT_RFMOD) #define BITS_RFMOD (BIT_MASK_RFMOD << BIT_SHIFT_RFMOD) #define BIT_CLEAR_RFMOD(x) ((x) & (~BITS_RFMOD)) #define BIT_GET_RFMOD(x) (((x) >> BIT_SHIFT_RFMOD) & BIT_MASK_RFMOD) #define BIT_SET_RFMOD(x, v) (BIT_CLEAR_RFMOD(x) | BIT_RFMOD(v)) #endif #if (HALMAC_8814AMP_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ #define BIT_SHIFT_RF_MOD 7 #define BIT_MASK_RF_MOD 0x3 #define BIT_RF_MOD(x) (((x) & BIT_MASK_RF_MOD) << BIT_SHIFT_RF_MOD) #define BITS_RF_MOD (BIT_MASK_RF_MOD << BIT_SHIFT_RF_MOD) #define BIT_CLEAR_RF_MOD(x) ((x) & (~BITS_RF_MOD)) #define BIT_GET_RF_MOD(x) (((x) >> BIT_SHIFT_RF_MOD) & BIT_MASK_RF_MOD) #define BIT_SET_RF_MOD(x, v) (BIT_CLEAR_RF_MOD(x) | BIT_RF_MOD(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ #define BIT_SHIFT_RESP_CTS_DYNBW_SEL 5 #define BIT_MASK_RESP_CTS_DYNBW_SEL 0x3 #define BIT_RESP_CTS_DYNBW_SEL(x) \ (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL) << BIT_SHIFT_RESP_CTS_DYNBW_SEL) #define BITS_RESP_CTS_DYNBW_SEL \ (BIT_MASK_RESP_CTS_DYNBW_SEL << BIT_SHIFT_RESP_CTS_DYNBW_SEL) #define BIT_CLEAR_RESP_CTS_DYNBW_SEL(x) ((x) & (~BITS_RESP_CTS_DYNBW_SEL)) #define BIT_GET_RESP_CTS_DYNBW_SEL(x) \ (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL) & BIT_MASK_RESP_CTS_DYNBW_SEL) #define BIT_SET_RESP_CTS_DYNBW_SEL(x, v) \ (BIT_CLEAR_RESP_CTS_DYNBW_SEL(x) | BIT_RESP_CTS_DYNBW_SEL(v)) #endif #if (HALMAC_8814AMP_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ #define BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL 5 #define BIT_MASK_RESP_CTS_BW_DYNBW_SEL 0x3 #define BIT_RESP_CTS_BW_DYNBW_SEL(x) \ (((x) & BIT_MASK_RESP_CTS_BW_DYNBW_SEL) \ << BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL) #define BITS_RESP_CTS_BW_DYNBW_SEL \ (BIT_MASK_RESP_CTS_BW_DYNBW_SEL << BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL) #define BIT_CLEAR_RESP_CTS_BW_DYNBW_SEL(x) ((x) & (~BITS_RESP_CTS_BW_DYNBW_SEL)) #define BIT_GET_RESP_CTS_BW_DYNBW_SEL(x) \ (((x) >> BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL) & \ BIT_MASK_RESP_CTS_BW_DYNBW_SEL) #define BIT_SET_RESP_CTS_BW_DYNBW_SEL(x, v) \ (BIT_CLEAR_RESP_CTS_BW_DYNBW_SEL(x) | BIT_RESP_CTS_BW_DYNBW_SEL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ #define BIT_DLY_TX_WAIT_RXANTSEL BIT(4) #endif #if (HALMAC_8814AMP_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ #define BIT_DELAY_TX_USE_RX_ANTSEL BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ #define BIT_TXRESP_BY_RXANTSEL BIT(3) #endif #if (HALMAC_8814AMP_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ #define BIT_TX_USE_RX_ANTSEL BIT(3) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ #define BIT_RESP_EARLY_TXACK_RWEPTKIP BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ #define BIT_SHIFT_ORIG_DCTS_CHK 0 #define BIT_MASK_ORIG_DCTS_CHK 0x3 #define BIT_ORIG_DCTS_CHK(x) \ (((x) & BIT_MASK_ORIG_DCTS_CHK) << BIT_SHIFT_ORIG_DCTS_CHK) #define BITS_ORIG_DCTS_CHK (BIT_MASK_ORIG_DCTS_CHK << BIT_SHIFT_ORIG_DCTS_CHK) #define BIT_CLEAR_ORIG_DCTS_CHK(x) ((x) & (~BITS_ORIG_DCTS_CHK)) #define BIT_GET_ORIG_DCTS_CHK(x) \ (((x) >> BIT_SHIFT_ORIG_DCTS_CHK) & BIT_MASK_ORIG_DCTS_CHK) #define BIT_SET_ORIG_DCTS_CHK(x, v) \ (BIT_CLEAR_ORIG_DCTS_CHK(x) | BIT_ORIG_DCTS_CHK(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_TRXPTCL_CTL_H (Offset 0x066C) */ #define BIT_RPT_VALID BIT(13) #define BIT_RXBA_IGNOREA2_V1 BIT(10) #define BIT_EN_SAVE_ALL_TXOPADDR_V1 BIT(9) #define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1 BIT(8) #define BIT_DIS_TXBA_AMPDUFCSERR_V1 BIT(7) #define BIT_DIS_TXBA_RXBARINFULL_V1 BIT(6) #define BIT_DIS_TXCFE_INFULL_V1 BIT(5) #define BIT_DIS_TXCTS_INFULL_V1 BIT(4) #define BIT_EN_TXACKBA_IN_TX_RDG_V1 BIT(3) #define BIT_EN_TXACKBA_IN_TXOP_V1 BIT(2) #define BIT_EN_TXCTS_IN_RXNAV_V1 BIT(1) #define BIT_EN_TXCTS_INTXOP_V1 BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CAMCMD (Offset 0x0670) */ #define BIT_SECCAM_POLLING BIT(31) #define BIT_SECCAM_CLR BIT(30) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_CAMCMD (Offset 0x0670) */ #define BIT_MFBCAM_CLR BIT(29) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_CAMCMD (Offset 0x0670) */ #define BIT_SECCAM_WE BIT(16) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CAMCMD (Offset 0x0670) */ #define BIT_SHIFT_SECCAM_ADDR_V1 0 #define BIT_MASK_SECCAM_ADDR_V1 0xff #define BIT_SECCAM_ADDR_V1(x) \ (((x) & BIT_MASK_SECCAM_ADDR_V1) << BIT_SHIFT_SECCAM_ADDR_V1) #define BITS_SECCAM_ADDR_V1 \ (BIT_MASK_SECCAM_ADDR_V1 << BIT_SHIFT_SECCAM_ADDR_V1) #define BIT_CLEAR_SECCAM_ADDR_V1(x) ((x) & (~BITS_SECCAM_ADDR_V1)) #define BIT_GET_SECCAM_ADDR_V1(x) \ (((x) >> BIT_SHIFT_SECCAM_ADDR_V1) & BIT_MASK_SECCAM_ADDR_V1) #define BIT_SET_SECCAM_ADDR_V1(x, v) \ (BIT_CLEAR_SECCAM_ADDR_V1(x) | BIT_SECCAM_ADDR_V1(v)) #define BIT_SHIFT_WKFCAM_NUM 0 #define BIT_MASK_WKFCAM_NUM 0x7f #define BIT_WKFCAM_NUM(x) (((x) & BIT_MASK_WKFCAM_NUM) << BIT_SHIFT_WKFCAM_NUM) #define BITS_WKFCAM_NUM (BIT_MASK_WKFCAM_NUM << BIT_SHIFT_WKFCAM_NUM) #define BIT_CLEAR_WKFCAM_NUM(x) ((x) & (~BITS_WKFCAM_NUM)) #define BIT_GET_WKFCAM_NUM(x) \ (((x) >> BIT_SHIFT_WKFCAM_NUM) & BIT_MASK_WKFCAM_NUM) #define BIT_SET_WKFCAM_NUM(x, v) (BIT_CLEAR_WKFCAM_NUM(x) | BIT_WKFCAM_NUM(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CAMCMD (Offset 0x0670) */ #define BIT_SHIFT_SECCAM_ADDR_V2 0 #define BIT_MASK_SECCAM_ADDR_V2 0x3ff #define BIT_SECCAM_ADDR_V2(x) \ (((x) & BIT_MASK_SECCAM_ADDR_V2) << BIT_SHIFT_SECCAM_ADDR_V2) #define BITS_SECCAM_ADDR_V2 \ (BIT_MASK_SECCAM_ADDR_V2 << BIT_SHIFT_SECCAM_ADDR_V2) #define BIT_CLEAR_SECCAM_ADDR_V2(x) ((x) & (~BITS_SECCAM_ADDR_V2)) #define BIT_GET_SECCAM_ADDR_V2(x) \ (((x) >> BIT_SHIFT_SECCAM_ADDR_V2) & BIT_MASK_SECCAM_ADDR_V2) #define BIT_SET_SECCAM_ADDR_V2(x, v) \ (BIT_CLEAR_SECCAM_ADDR_V2(x) | BIT_SECCAM_ADDR_V2(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_CAMCMD (Offset 0x0670) */ #define BIT_SHIFT_SECCAM_ADDR 0 #define BIT_MASK_SECCAM_ADDR 0xff #define BIT_SECCAM_ADDR(x) \ (((x) & BIT_MASK_SECCAM_ADDR) << BIT_SHIFT_SECCAM_ADDR) #define BITS_SECCAM_ADDR (BIT_MASK_SECCAM_ADDR << BIT_SHIFT_SECCAM_ADDR) #define BIT_CLEAR_SECCAM_ADDR(x) ((x) & (~BITS_SECCAM_ADDR)) #define BIT_GET_SECCAM_ADDR(x) \ (((x) >> BIT_SHIFT_SECCAM_ADDR) & BIT_MASK_SECCAM_ADDR) #define BIT_SET_SECCAM_ADDR(x, v) \ (BIT_CLEAR_SECCAM_ADDR(x) | BIT_SECCAM_ADDR(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_CAMWRITE (Offset 0x0674) */ #define BIT_SHIFT_CAMW_DATA 0 #define BIT_MASK_CAMW_DATA 0xffffffffL #define BIT_CAMW_DATA(x) (((x) & BIT_MASK_CAMW_DATA) << BIT_SHIFT_CAMW_DATA) #define BITS_CAMW_DATA (BIT_MASK_CAMW_DATA << BIT_SHIFT_CAMW_DATA) #define BIT_CLEAR_CAMW_DATA(x) ((x) & (~BITS_CAMW_DATA)) #define BIT_GET_CAMW_DATA(x) (((x) >> BIT_SHIFT_CAMW_DATA) & BIT_MASK_CAMW_DATA) #define BIT_SET_CAMW_DATA(x, v) (BIT_CLEAR_CAMW_DATA(x) | BIT_CAMW_DATA(v)) /* 2 REG_CAMREAD (Offset 0x0678) */ #define BIT_SHIFT_CAMR_DATA 0 #define BIT_MASK_CAMR_DATA 0xffffffffL #define BIT_CAMR_DATA(x) (((x) & BIT_MASK_CAMR_DATA) << BIT_SHIFT_CAMR_DATA) #define BITS_CAMR_DATA (BIT_MASK_CAMR_DATA << BIT_SHIFT_CAMR_DATA) #define BIT_CLEAR_CAMR_DATA(x) ((x) & (~BITS_CAMR_DATA)) #define BIT_GET_CAMR_DATA(x) (((x) >> BIT_SHIFT_CAMR_DATA) & BIT_MASK_CAMR_DATA) #define BIT_SET_CAMR_DATA(x, v) (BIT_CLEAR_CAMR_DATA(x) | BIT_CAMR_DATA(v)) /* 2 REG_CAMDBG (Offset 0x067C) */ #define BIT_SECCAM_INFO BIT(31) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_CAMDBG (Offset 0x067C) */ #define BIT_SEC_KEYFOUND_V1 BIT(19) #define BIT_SHIFT_CAMDBG_SEC_TYPE_V1 16 #define BIT_MASK_CAMDBG_SEC_TYPE_V1 0x7 #define BIT_CAMDBG_SEC_TYPE_V1(x) \ (((x) & BIT_MASK_CAMDBG_SEC_TYPE_V1) << BIT_SHIFT_CAMDBG_SEC_TYPE_V1) #define BITS_CAMDBG_SEC_TYPE_V1 \ (BIT_MASK_CAMDBG_SEC_TYPE_V1 << BIT_SHIFT_CAMDBG_SEC_TYPE_V1) #define BIT_CLEAR_CAMDBG_SEC_TYPE_V1(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_V1)) #define BIT_GET_CAMDBG_SEC_TYPE_V1(x) \ (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_V1) & BIT_MASK_CAMDBG_SEC_TYPE_V1) #define BIT_SET_CAMDBG_SEC_TYPE_V1(x, v) \ (BIT_CLEAR_CAMDBG_SEC_TYPE_V1(x) | BIT_CAMDBG_SEC_TYPE_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CAMDBG (Offset 0x067C) */ #define BIT_SEC_KEYFOUND BIT(15) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_CAMDBG (Offset 0x067C) */ #define BIT_CAMDBG_EXT_SEC_TYPE_V1 BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CAMDBG (Offset 0x067C) */ #define BIT_SHIFT_CAMDBG_SEC_TYPE 12 #define BIT_MASK_CAMDBG_SEC_TYPE 0x7 #define BIT_CAMDBG_SEC_TYPE(x) \ (((x) & BIT_MASK_CAMDBG_SEC_TYPE) << BIT_SHIFT_CAMDBG_SEC_TYPE) #define BITS_CAMDBG_SEC_TYPE \ (BIT_MASK_CAMDBG_SEC_TYPE << BIT_SHIFT_CAMDBG_SEC_TYPE) #define BIT_CLEAR_CAMDBG_SEC_TYPE(x) ((x) & (~BITS_CAMDBG_SEC_TYPE)) #define BIT_GET_CAMDBG_SEC_TYPE(x) \ (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE) & BIT_MASK_CAMDBG_SEC_TYPE) #define BIT_SET_CAMDBG_SEC_TYPE(x, v) \ (BIT_CLEAR_CAMDBG_SEC_TYPE(x) | BIT_CAMDBG_SEC_TYPE(v)) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_CAMDBG (Offset 0x067C) */ #define BIT_CAMDBG_EXT_SEC_TYPE BIT(11) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_CAMDBG (Offset 0x067C) */ #define BIT_CAMDBG_EXT_SECTYPE BIT(11) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_CAMDBG (Offset 0x067C) */ #define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1 7 #define BIT_MASK_CAMDBG_MIC_KEY_IDX_V1 0x7f #define BIT_CAMDBG_MIC_KEY_IDX_V1(x) \ (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_V1) \ << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1) #define BITS_CAMDBG_MIC_KEY_IDX_V1 \ (BIT_MASK_CAMDBG_MIC_KEY_IDX_V1 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1) #define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_V1(x) ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_V1)) #define BIT_GET_CAMDBG_MIC_KEY_IDX_V1(x) \ (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1) & \ BIT_MASK_CAMDBG_MIC_KEY_IDX_V1) #define BIT_SET_CAMDBG_MIC_KEY_IDX_V1(x, v) \ (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_V1(x) | BIT_CAMDBG_MIC_KEY_IDX_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_CAMDBG (Offset 0x067C) */ #define BIT_SHIFT_CAMDBG_MIC_KEY_IDX 5 #define BIT_MASK_CAMDBG_MIC_KEY_IDX 0x1f #define BIT_CAMDBG_MIC_KEY_IDX(x) \ (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX) #define BITS_CAMDBG_MIC_KEY_IDX \ (BIT_MASK_CAMDBG_MIC_KEY_IDX << BIT_SHIFT_CAMDBG_MIC_KEY_IDX) #define BIT_CLEAR_CAMDBG_MIC_KEY_IDX(x) ((x) & (~BITS_CAMDBG_MIC_KEY_IDX)) #define BIT_GET_CAMDBG_MIC_KEY_IDX(x) \ (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX) & BIT_MASK_CAMDBG_MIC_KEY_IDX) #define BIT_SET_CAMDBG_MIC_KEY_IDX(x, v) \ (BIT_CLEAR_CAMDBG_MIC_KEY_IDX(x) | BIT_CAMDBG_MIC_KEY_IDX(v)) #define BIT_SHIFT_CAMDBG_SEC_KEY_IDX 0 #define BIT_MASK_CAMDBG_SEC_KEY_IDX 0x1f #define BIT_CAMDBG_SEC_KEY_IDX(x) \ (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX) #define BITS_CAMDBG_SEC_KEY_IDX \ (BIT_MASK_CAMDBG_SEC_KEY_IDX << BIT_SHIFT_CAMDBG_SEC_KEY_IDX) #define BIT_CLEAR_CAMDBG_SEC_KEY_IDX(x) ((x) & (~BITS_CAMDBG_SEC_KEY_IDX)) #define BIT_GET_CAMDBG_SEC_KEY_IDX(x) \ (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX) & BIT_MASK_CAMDBG_SEC_KEY_IDX) #define BIT_SET_CAMDBG_SEC_KEY_IDX(x, v) \ (BIT_CLEAR_CAMDBG_SEC_KEY_IDX(x) | BIT_CAMDBG_SEC_KEY_IDX(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_CAMDBG (Offset 0x067C) */ #define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1 0 #define BIT_MASK_CAMDBG_SEC_KEY_IDX_V1 0x7f #define BIT_CAMDBG_SEC_KEY_IDX_V1(x) \ (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_V1) \ << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1) #define BITS_CAMDBG_SEC_KEY_IDX_V1 \ (BIT_MASK_CAMDBG_SEC_KEY_IDX_V1 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1) #define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_V1(x) ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_V1)) #define BIT_GET_CAMDBG_SEC_KEY_IDX_V1(x) \ (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1) & \ BIT_MASK_CAMDBG_SEC_KEY_IDX_V1) #define BIT_SET_CAMDBG_SEC_KEY_IDX_V1(x, v) \ (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_V1(x) | BIT_CAMDBG_SEC_KEY_IDX_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SECCFG (Offset 0x0680) */ #define BIT_DIS_GCLK_WAPI BIT(15) #define BIT_DIS_GCLK_AES BIT(14) #define BIT_DIS_GCLK_TKIP BIT(13) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SECCFG (Offset 0x0680) */ #define BIT_AES_SEL_QC_1 BIT(12) #define BIT_AES_SEL_QC_0 BIT(11) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_SECCFG (Offset 0x0680) */ #define BIT_WMAC_CKECK_BMC BIT(9) #endif #if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SECCFG (Offset 0x0680) */ #define BIT_CHK_BMC BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_SECCFG (Offset 0x0680) */ #define BIT_CHK_KEYID BIT(8) #define BIT_RXBCUSEDK BIT(7) #define BIT_TXBCUSEDK BIT(6) #define BIT_NOSKMC BIT(5) #define BIT_SKBYA2 BIT(4) #define BIT_RXDEC BIT(3) #define BIT_TXENC BIT(2) #define BIT_RXUHUSEDK BIT(1) #define BIT_TXUHUSEDK BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXFILTER_CATEGORY_1 (Offset 0x0682) */ #define BIT_SHIFT_RXFILTER_CATEGORY_1 0 #define BIT_MASK_RXFILTER_CATEGORY_1 0xff #define BIT_RXFILTER_CATEGORY_1(x) \ (((x) & BIT_MASK_RXFILTER_CATEGORY_1) << BIT_SHIFT_RXFILTER_CATEGORY_1) #define BITS_RXFILTER_CATEGORY_1 \ (BIT_MASK_RXFILTER_CATEGORY_1 << BIT_SHIFT_RXFILTER_CATEGORY_1) #define BIT_CLEAR_RXFILTER_CATEGORY_1(x) ((x) & (~BITS_RXFILTER_CATEGORY_1)) #define BIT_GET_RXFILTER_CATEGORY_1(x) \ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1) & BIT_MASK_RXFILTER_CATEGORY_1) #define BIT_SET_RXFILTER_CATEGORY_1(x, v) \ (BIT_CLEAR_RXFILTER_CATEGORY_1(x) | BIT_RXFILTER_CATEGORY_1(v)) /* 2 REG_RXFILTER_ACTION_1 (Offset 0x0683) */ #define BIT_SHIFT_RXFILTER_ACTION_1 0 #define BIT_MASK_RXFILTER_ACTION_1 0xff #define BIT_RXFILTER_ACTION_1(x) \ (((x) & BIT_MASK_RXFILTER_ACTION_1) << BIT_SHIFT_RXFILTER_ACTION_1) #define BITS_RXFILTER_ACTION_1 \ (BIT_MASK_RXFILTER_ACTION_1 << BIT_SHIFT_RXFILTER_ACTION_1) #define BIT_CLEAR_RXFILTER_ACTION_1(x) ((x) & (~BITS_RXFILTER_ACTION_1)) #define BIT_GET_RXFILTER_ACTION_1(x) \ (((x) >> BIT_SHIFT_RXFILTER_ACTION_1) & BIT_MASK_RXFILTER_ACTION_1) #define BIT_SET_RXFILTER_ACTION_1(x, v) \ (BIT_CLEAR_RXFILTER_ACTION_1(x) | BIT_RXFILTER_ACTION_1(v)) /* 2 REG_RXFILTER_CATEGORY_2 (Offset 0x0684) */ #define BIT_SHIFT_RXFILTER_CATEGORY_2 0 #define BIT_MASK_RXFILTER_CATEGORY_2 0xff #define BIT_RXFILTER_CATEGORY_2(x) \ (((x) & BIT_MASK_RXFILTER_CATEGORY_2) << BIT_SHIFT_RXFILTER_CATEGORY_2) #define BITS_RXFILTER_CATEGORY_2 \ (BIT_MASK_RXFILTER_CATEGORY_2 << BIT_SHIFT_RXFILTER_CATEGORY_2) #define BIT_CLEAR_RXFILTER_CATEGORY_2(x) ((x) & (~BITS_RXFILTER_CATEGORY_2)) #define BIT_GET_RXFILTER_CATEGORY_2(x) \ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2) & BIT_MASK_RXFILTER_CATEGORY_2) #define BIT_SET_RXFILTER_CATEGORY_2(x, v) \ (BIT_CLEAR_RXFILTER_CATEGORY_2(x) | BIT_RXFILTER_CATEGORY_2(v)) /* 2 REG_RXFILTER_ACTION_2 (Offset 0x0685) */ #define BIT_SHIFT_RXFILTER_ACTION_2 0 #define BIT_MASK_RXFILTER_ACTION_2 0xff #define BIT_RXFILTER_ACTION_2(x) \ (((x) & BIT_MASK_RXFILTER_ACTION_2) << BIT_SHIFT_RXFILTER_ACTION_2) #define BITS_RXFILTER_ACTION_2 \ (BIT_MASK_RXFILTER_ACTION_2 << BIT_SHIFT_RXFILTER_ACTION_2) #define BIT_CLEAR_RXFILTER_ACTION_2(x) ((x) & (~BITS_RXFILTER_ACTION_2)) #define BIT_GET_RXFILTER_ACTION_2(x) \ (((x) >> BIT_SHIFT_RXFILTER_ACTION_2) & BIT_MASK_RXFILTER_ACTION_2) #define BIT_SET_RXFILTER_ACTION_2(x, v) \ (BIT_CLEAR_RXFILTER_ACTION_2(x) | BIT_RXFILTER_ACTION_2(v)) /* 2 REG_RXFILTER_CATEGORY_3 (Offset 0x0686) */ #define BIT_SHIFT_RXFILTER_CATEGORY_3 0 #define BIT_MASK_RXFILTER_CATEGORY_3 0xff #define BIT_RXFILTER_CATEGORY_3(x) \ (((x) & BIT_MASK_RXFILTER_CATEGORY_3) << BIT_SHIFT_RXFILTER_CATEGORY_3) #define BITS_RXFILTER_CATEGORY_3 \ (BIT_MASK_RXFILTER_CATEGORY_3 << BIT_SHIFT_RXFILTER_CATEGORY_3) #define BIT_CLEAR_RXFILTER_CATEGORY_3(x) ((x) & (~BITS_RXFILTER_CATEGORY_3)) #define BIT_GET_RXFILTER_CATEGORY_3(x) \ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3) & BIT_MASK_RXFILTER_CATEGORY_3) #define BIT_SET_RXFILTER_CATEGORY_3(x, v) \ (BIT_CLEAR_RXFILTER_CATEGORY_3(x) | BIT_RXFILTER_CATEGORY_3(v)) /* 2 REG_RXFILTER_ACTION_3 (Offset 0x0687) */ #define BIT_SHIFT_RXFILTER_ACTION_3 0 #define BIT_MASK_RXFILTER_ACTION_3 0xff #define BIT_RXFILTER_ACTION_3(x) \ (((x) & BIT_MASK_RXFILTER_ACTION_3) << BIT_SHIFT_RXFILTER_ACTION_3) #define BITS_RXFILTER_ACTION_3 \ (BIT_MASK_RXFILTER_ACTION_3 << BIT_SHIFT_RXFILTER_ACTION_3) #define BIT_CLEAR_RXFILTER_ACTION_3(x) ((x) & (~BITS_RXFILTER_ACTION_3)) #define BIT_GET_RXFILTER_ACTION_3(x) \ (((x) >> BIT_SHIFT_RXFILTER_ACTION_3) & BIT_MASK_RXFILTER_ACTION_3) #define BIT_SET_RXFILTER_ACTION_3(x, v) \ (BIT_CLEAR_RXFILTER_ACTION_3(x) | BIT_RXFILTER_ACTION_3(v)) /* 2 REG_RXFLTMAP3 (Offset 0x0688) */ #define BIT_MGTFLT15EN_FW BIT(15) #define BIT_MGTFLT14EN_FW BIT(14) #define BIT_MGTFLT13EN_FW BIT(13) #define BIT_MGTFLT12EN_FW BIT(12) #define BIT_MGTFLT11EN_FW BIT(11) #define BIT_MGTFLT10EN_FW BIT(10) #define BIT_MGTFLT9EN_FW BIT(9) #define BIT_MGTFLT8EN_FW BIT(8) #define BIT_MGTFLT7EN_FW BIT(7) #define BIT_MGTFLT6EN_FW BIT(6) #define BIT_MGTFLT5EN_FW BIT(5) #define BIT_MGTFLT4EN_FW BIT(4) #define BIT_MGTFLT3EN_FW BIT(3) #define BIT_MGTFLT2EN_FW BIT(2) #define BIT_MGTFLT1EN_FW BIT(1) #define BIT_MGTFLT0EN_FW BIT(0) /* 2 REG_RXFLTMAP4 (Offset 0x068A) */ #define BIT_CTRLFLT15EN_FW BIT(15) #define BIT_CTRLFLT14EN_FW BIT(14) #define BIT_CTRLFLT13EN_FW BIT(13) #define BIT_CTRLFLT12EN_FW BIT(12) #define BIT_CTRLFLT11EN_FW BIT(11) #define BIT_CTRLFLT10EN_FW BIT(10) #define BIT_CTRLFLT9EN_FW BIT(9) #define BIT_CTRLFLT8EN_FW BIT(8) #define BIT_CTRLFLT7EN_FW BIT(7) #define BIT_CTRLFLT6EN_FW BIT(6) #define BIT_CTRLFLT5EN_FW BIT(5) #define BIT_CTRLFLT4EN_FW BIT(4) #define BIT_CTRLFLT3EN_FW BIT(3) #define BIT_CTRLFLT2EN_FW BIT(2) #define BIT_CTRLFLT1EN_FW BIT(1) #define BIT_CTRLFLT0EN_FW BIT(0) /* 2 REG_RXFLTMAP5 (Offset 0x068C) */ #define BIT_DATAFLT15EN_FW BIT(15) #define BIT_DATAFLT14EN_FW BIT(14) #define BIT_DATAFLT13EN_FW BIT(13) #define BIT_DATAFLT12EN_FW BIT(12) #define BIT_DATAFLT11EN_FW BIT(11) #define BIT_DATAFLT10EN_FW BIT(10) #define BIT_DATAFLT9EN_FW BIT(9) #define BIT_DATAFLT8EN_FW BIT(8) #define BIT_DATAFLT7EN_FW BIT(7) #define BIT_DATAFLT6EN_FW BIT(6) #define BIT_DATAFLT5EN_FW BIT(5) #define BIT_DATAFLT4EN_FW BIT(4) #define BIT_DATAFLT3EN_FW BIT(3) #define BIT_DATAFLT2EN_FW BIT(2) #define BIT_DATAFLT1EN_FW BIT(1) #define BIT_DATAFLT0EN_FW BIT(0) /* 2 REG_RXFLTMAP6 (Offset 0x068E) */ #define BIT_ACTIONFLT15EN_FW BIT(15) #define BIT_ACTIONFLT14EN_FW BIT(14) #define BIT_ACTIONFLT13EN_FW BIT(13) #define BIT_ACTIONFLT12EN_FW BIT(12) #define BIT_ACTIONFLT11EN_FW BIT(11) #define BIT_ACTIONFLT10EN_FW BIT(10) #define BIT_ACTIONFLT9EN_FW BIT(9) #define BIT_ACTIONFLT8EN_FW BIT(8) #define BIT_ACTIONFLT7EN_FW BIT(7) #define BIT_ACTIONFLT6EN_FW BIT(6) #define BIT_ACTIONFLT5EN_FW BIT(5) #define BIT_ACTIONFLT4EN_FW BIT(4) #define BIT_ACTIONFLT3EN_FW BIT(3) #define BIT_ACTIONFLT2EN_FW BIT(2) #define BIT_ACTIONFLT1EN_FW BIT(1) #define BIT_ACTIONFLT0EN_FW BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WOW_CTRL (Offset 0x0690) */ #define BIT_SHIFT_PSF_BSSIDSEL_B2B1 6 #define BIT_MASK_PSF_BSSIDSEL_B2B1 0x3 #define BIT_PSF_BSSIDSEL_B2B1(x) \ (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1) << BIT_SHIFT_PSF_BSSIDSEL_B2B1) #define BITS_PSF_BSSIDSEL_B2B1 \ (BIT_MASK_PSF_BSSIDSEL_B2B1 << BIT_SHIFT_PSF_BSSIDSEL_B2B1) #define BIT_CLEAR_PSF_BSSIDSEL_B2B1(x) ((x) & (~BITS_PSF_BSSIDSEL_B2B1)) #define BIT_GET_PSF_BSSIDSEL_B2B1(x) \ (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1) & BIT_MASK_PSF_BSSIDSEL_B2B1) #define BIT_SET_PSF_BSSIDSEL_B2B1(x, v) \ (BIT_CLEAR_PSF_BSSIDSEL_B2B1(x) | BIT_PSF_BSSIDSEL_B2B1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_WOW_CTRL (Offset 0x0690) */ #define BIT_WOWHCI BIT(5) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_WOW_CTRL (Offset 0x0690) */ #define BIT_PSF_BSSIDSEL BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WOW_CTRL (Offset 0x0690) */ #define BIT_PSF_BSSIDSEL_B0 BIT(4) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_WOW_CTRL (Offset 0x0690) */ #define BIT_UWF BIT(3) #define BIT_MAGIC BIT(2) #define BIT_WOWEN BIT(1) #define BIT_FORCE_WAKEUP BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_NAN_RX_TSF_FILTER (Offset 0x0691) */ #define BIT_CHK_TSF_TA BIT(2) #define BIT_CHK_TSF_CBSSID BIT(1) #define BIT_CHK_TSF_EN BIT(0) /* 2 REG_PS_RX_INFO (Offset 0x0692) */ #define BIT_SHIFT_PORTSEL__PS_RX_INFO 5 #define BIT_MASK_PORTSEL__PS_RX_INFO 0x7 #define BIT_PORTSEL__PS_RX_INFO(x) \ (((x) & BIT_MASK_PORTSEL__PS_RX_INFO) << BIT_SHIFT_PORTSEL__PS_RX_INFO) #define BITS_PORTSEL__PS_RX_INFO \ (BIT_MASK_PORTSEL__PS_RX_INFO << BIT_SHIFT_PORTSEL__PS_RX_INFO) #define BIT_CLEAR_PORTSEL__PS_RX_INFO(x) ((x) & (~BITS_PORTSEL__PS_RX_INFO)) #define BIT_GET_PORTSEL__PS_RX_INFO(x) \ (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO) & BIT_MASK_PORTSEL__PS_RX_INFO) #define BIT_SET_PORTSEL__PS_RX_INFO(x, v) \ (BIT_CLEAR_PORTSEL__PS_RX_INFO(x) | BIT_PORTSEL__PS_RX_INFO(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_PS_RX_INFO (Offset 0x0692) */ #define BIT_RXCTRLIN0 BIT(4) #define BIT_RXMGTIN0 BIT(3) #define BIT_RXDATAIN2 BIT(2) #define BIT_RXDATAIN1 BIT(1) #define BIT_RXDATAIN0 BIT(0) /* 2 REG_WMMPS_UAPSD_TID (Offset 0x0693) */ #define BIT_WMMPS_UAPSD_TID7 BIT(7) #define BIT_WMMPS_UAPSD_TID6 BIT(6) #define BIT_WMMPS_UAPSD_TID5 BIT(5) #define BIT_WMMPS_UAPSD_TID4 BIT(4) #define BIT_WMMPS_UAPSD_TID3 BIT(3) #define BIT_WMMPS_UAPSD_TID2 BIT(2) #define BIT_WMMPS_UAPSD_TID1 BIT(1) #define BIT_WMMPS_UAPSD_TID0 BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LPNAV_CTRL (Offset 0x0694) */ #define BIT_LPNAV_EN BIT(31) #define BIT_SHIFT_LPNAV_EARLY 16 #define BIT_MASK_LPNAV_EARLY 0x7fff #define BIT_LPNAV_EARLY(x) \ (((x) & BIT_MASK_LPNAV_EARLY) << BIT_SHIFT_LPNAV_EARLY) #define BITS_LPNAV_EARLY (BIT_MASK_LPNAV_EARLY << BIT_SHIFT_LPNAV_EARLY) #define BIT_CLEAR_LPNAV_EARLY(x) ((x) & (~BITS_LPNAV_EARLY)) #define BIT_GET_LPNAV_EARLY(x) \ (((x) >> BIT_SHIFT_LPNAV_EARLY) & BIT_MASK_LPNAV_EARLY) #define BIT_SET_LPNAV_EARLY(x, v) \ (BIT_CLEAR_LPNAV_EARLY(x) | BIT_LPNAV_EARLY(v)) #define BIT_SHIFT_LPNAV_TH 0 #define BIT_MASK_LPNAV_TH 0xffff #define BIT_LPNAV_TH(x) (((x) & BIT_MASK_LPNAV_TH) << BIT_SHIFT_LPNAV_TH) #define BITS_LPNAV_TH (BIT_MASK_LPNAV_TH << BIT_SHIFT_LPNAV_TH) #define BIT_CLEAR_LPNAV_TH(x) ((x) & (~BITS_LPNAV_TH)) #define BIT_GET_LPNAV_TH(x) (((x) >> BIT_SHIFT_LPNAV_TH) & BIT_MASK_LPNAV_TH) #define BIT_SET_LPNAV_TH(x, v) (BIT_CLEAR_LPNAV_TH(x) | BIT_LPNAV_TH(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ #define BIT_WKFCAM_POLLING_V1 BIT(31) #define BIT_WKFCAM_CLR_V1 BIT(30) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ #define BIT_WKFCAM_WE BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ #define BIT_SHIFT_WKFCAM_ADDR_V2 8 #define BIT_MASK_WKFCAM_ADDR_V2 0xff #define BIT_WKFCAM_ADDR_V2(x) \ (((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2) #define BITS_WKFCAM_ADDR_V2 \ (BIT_MASK_WKFCAM_ADDR_V2 << BIT_SHIFT_WKFCAM_ADDR_V2) #define BIT_CLEAR_WKFCAM_ADDR_V2(x) ((x) & (~BITS_WKFCAM_ADDR_V2)) #define BIT_GET_WKFCAM_ADDR_V2(x) \ (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2) & BIT_MASK_WKFCAM_ADDR_V2) #define BIT_SET_WKFCAM_ADDR_V2(x, v) \ (BIT_CLEAR_WKFCAM_ADDR_V2(x) | BIT_WKFCAM_ADDR_V2(v)) #define BIT_WMAC_RESP_NONSTA1_DIS BIT(7) #define BIT_SHIFT_WMAC_TXMU_ACKPOLICY 4 #define BIT_MASK_WMAC_TXMU_ACKPOLICY 0x3 #define BIT_WMAC_TXMU_ACKPOLICY(x) \ (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY) #define BITS_WMAC_TXMU_ACKPOLICY \ (BIT_MASK_WMAC_TXMU_ACKPOLICY << BIT_SHIFT_WMAC_TXMU_ACKPOLICY) #define BIT_CLEAR_WMAC_TXMU_ACKPOLICY(x) ((x) & (~BITS_WMAC_TXMU_ACKPOLICY)) #define BIT_GET_WMAC_TXMU_ACKPOLICY(x) \ (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY) & BIT_MASK_WMAC_TXMU_ACKPOLICY) #define BIT_SET_WMAC_TXMU_ACKPOLICY(x, v) \ (BIT_CLEAR_WMAC_TXMU_ACKPOLICY(x) | BIT_WMAC_TXMU_ACKPOLICY(v)) #define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL 1 #define BIT_MASK_WMAC_MU_BFEE_PORT_SEL 0x7 #define BIT_WMAC_MU_BFEE_PORT_SEL(x) \ (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL) \ << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) #define BITS_WMAC_MU_BFEE_PORT_SEL \ (BIT_MASK_WMAC_MU_BFEE_PORT_SEL << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) #define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL(x) ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL)) #define BIT_GET_WMAC_MU_BFEE_PORT_SEL(x) \ (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) & \ BIT_MASK_WMAC_MU_BFEE_PORT_SEL) #define BIT_SET_WMAC_MU_BFEE_PORT_SEL(x, v) \ (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL(x) | BIT_WMAC_MU_BFEE_PORT_SEL(v)) #define BIT_SHIFT_WKFCAM_CAM_NUM_V1 0 #define BIT_MASK_WKFCAM_CAM_NUM_V1 0xff #define BIT_WKFCAM_CAM_NUM_V1(x) \ (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1) << BIT_SHIFT_WKFCAM_CAM_NUM_V1) #define BITS_WKFCAM_CAM_NUM_V1 \ (BIT_MASK_WKFCAM_CAM_NUM_V1 << BIT_SHIFT_WKFCAM_CAM_NUM_V1) #define BIT_CLEAR_WKFCAM_CAM_NUM_V1(x) ((x) & (~BITS_WKFCAM_CAM_NUM_V1)) #define BIT_GET_WKFCAM_CAM_NUM_V1(x) \ (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1) & BIT_MASK_WKFCAM_CAM_NUM_V1) #define BIT_SET_WKFCAM_CAM_NUM_V1(x, v) \ (BIT_CLEAR_WKFCAM_CAM_NUM_V1(x) | BIT_WKFCAM_CAM_NUM_V1(v)) #define BIT_WMAC_MU_BFEE_DIS BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ #define BIT_SHIFT_WKFCAM_ADDR 0 #define BIT_MASK_WKFCAM_ADDR 0x7f #define BIT_WKFCAM_ADDR(x) \ (((x) & BIT_MASK_WKFCAM_ADDR) << BIT_SHIFT_WKFCAM_ADDR) #define BITS_WKFCAM_ADDR (BIT_MASK_WKFCAM_ADDR << BIT_SHIFT_WKFCAM_ADDR) #define BIT_CLEAR_WKFCAM_ADDR(x) ((x) & (~BITS_WKFCAM_ADDR)) #define BIT_GET_WKFCAM_ADDR(x) \ (((x) >> BIT_SHIFT_WKFCAM_ADDR) & BIT_MASK_WKFCAM_ADDR) #define BIT_SET_WKFCAM_ADDR(x, v) \ (BIT_CLEAR_WKFCAM_ADDR(x) | BIT_WKFCAM_ADDR(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WKFMCAM_RWD (Offset 0x069C) */ #define BIT_SHIFT_WKFMCAM_RWD 0 #define BIT_MASK_WKFMCAM_RWD 0xffffffffL #define BIT_WKFMCAM_RWD(x) \ (((x) & BIT_MASK_WKFMCAM_RWD) << BIT_SHIFT_WKFMCAM_RWD) #define BITS_WKFMCAM_RWD (BIT_MASK_WKFMCAM_RWD << BIT_SHIFT_WKFMCAM_RWD) #define BIT_CLEAR_WKFMCAM_RWD(x) ((x) & (~BITS_WKFMCAM_RWD)) #define BIT_GET_WKFMCAM_RWD(x) \ (((x) >> BIT_SHIFT_WKFMCAM_RWD) & BIT_MASK_WKFMCAM_RWD) #define BIT_SET_WKFMCAM_RWD(x, v) \ (BIT_CLEAR_WKFMCAM_RWD(x) | BIT_WKFMCAM_RWD(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ #define BIT_DATAFLT15EN BIT(15) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ #define BIT_MGTFLT15EN BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ #define BIT_DATAFLT14EN BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ #define BIT_MGTFLT14EN BIT(14) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ #define BIT_MGTFLT13EN BIT(13) #define BIT_DATAFLT13EN BIT(13) #define BIT_MGTFLT12EN BIT(12) #define BIT_DATAFLT12EN BIT(12) #define BIT_MGTFLT11EN BIT(11) #define BIT_DATAFLT11EN BIT(11) #define BIT_MGTFLT10EN BIT(10) #define BIT_DATAFLT10EN BIT(10) #define BIT_MGTFLT9EN BIT(9) #define BIT_DATAFLT9EN BIT(9) #define BIT_MGTFLT8EN BIT(8) #define BIT_DATAFLT8EN BIT(8) #define BIT_DATAFLT7EN BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ #define BIT_MGTFLT7EN BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ #define BIT_DATAFLT6EN BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ #define BIT_MGTFLT6EN BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ #define BIT_MGTFLT5EN BIT(5) #define BIT_DATAFLT5EN BIT(5) #define BIT_MGTFLT4EN BIT(4) #define BIT_DATAFLT4EN BIT(4) #define BIT_MGTFLT3EN BIT(3) #define BIT_DATAFLT3EN BIT(3) #define BIT_MGTFLT2EN BIT(2) #define BIT_DATAFLT2EN BIT(2) #define BIT_MGTFLT1EN BIT(1) #define BIT_DATAFLT1EN BIT(1) #define BIT_MGTFLT0EN BIT(0) #define BIT_DATAFLT0EN BIT(0) /* 2 REG_RXFLTMAP1 (Offset 0x06A2) */ #define BIT_CTRLFLT15EN BIT(15) #define BIT_CTRLFLT14EN BIT(14) #define BIT_CTRLFLT13EN BIT(13) #define BIT_CTRLFLT12EN BIT(12) #define BIT_CTRLFLT11EN BIT(11) #define BIT_CTRLFLT10EN BIT(10) #define BIT_CTRLFLT9EN BIT(9) #define BIT_CTRLFLT8EN BIT(8) #define BIT_CTRLFLT7EN BIT(7) #define BIT_CTRLFLT6EN BIT(6) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXFLTMAP1 (Offset 0x06A2) */ #define BIT_CTRLFLT5EN BIT(5) #define BIT_CTRLFLT4EN BIT(4) #define BIT_CTRLFLT3EN BIT(3) #define BIT_CTRLFLT2EN BIT(2) #define BIT_CTRLFLT1EN BIT(1) #define BIT_CTRLFLT0EN BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_BCN_PSR_RPT (Offset 0x06A8) */ #define BIT_SHIFT_DTIM_CNT 24 #define BIT_MASK_DTIM_CNT 0xff #define BIT_DTIM_CNT(x) (((x) & BIT_MASK_DTIM_CNT) << BIT_SHIFT_DTIM_CNT) #define BITS_DTIM_CNT (BIT_MASK_DTIM_CNT << BIT_SHIFT_DTIM_CNT) #define BIT_CLEAR_DTIM_CNT(x) ((x) & (~BITS_DTIM_CNT)) #define BIT_GET_DTIM_CNT(x) (((x) >> BIT_SHIFT_DTIM_CNT) & BIT_MASK_DTIM_CNT) #define BIT_SET_DTIM_CNT(x, v) (BIT_CLEAR_DTIM_CNT(x) | BIT_DTIM_CNT(v)) #define BIT_SHIFT_DTIM_PERIOD 16 #define BIT_MASK_DTIM_PERIOD 0xff #define BIT_DTIM_PERIOD(x) \ (((x) & BIT_MASK_DTIM_PERIOD) << BIT_SHIFT_DTIM_PERIOD) #define BITS_DTIM_PERIOD (BIT_MASK_DTIM_PERIOD << BIT_SHIFT_DTIM_PERIOD) #define BIT_CLEAR_DTIM_PERIOD(x) ((x) & (~BITS_DTIM_PERIOD)) #define BIT_GET_DTIM_PERIOD(x) \ (((x) >> BIT_SHIFT_DTIM_PERIOD) & BIT_MASK_DTIM_PERIOD) #define BIT_SET_DTIM_PERIOD(x, v) \ (BIT_CLEAR_DTIM_PERIOD(x) | BIT_DTIM_PERIOD(v)) #define BIT_DTIM BIT(15) #define BIT_TIM BIT(14) #define BIT_SHIFT_PS_AID_0 0 #define BIT_MASK_PS_AID_0 0x7ff #define BIT_PS_AID_0(x) (((x) & BIT_MASK_PS_AID_0) << BIT_SHIFT_PS_AID_0) #define BITS_PS_AID_0 (BIT_MASK_PS_AID_0 << BIT_SHIFT_PS_AID_0) #define BIT_CLEAR_PS_AID_0(x) ((x) & (~BITS_PS_AID_0)) #define BIT_GET_PS_AID_0(x) (((x) >> BIT_SHIFT_PS_AID_0) & BIT_MASK_PS_AID_0) #define BIT_SET_PS_AID_0(x, v) (BIT_CLEAR_PS_AID_0(x) | BIT_PS_AID_0(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FLC_RPC (Offset 0x06AC) */ #define BIT_SHIFT_FLC_RPC 0 #define BIT_MASK_FLC_RPC 0xff #define BIT_FLC_RPC(x) (((x) & BIT_MASK_FLC_RPC) << BIT_SHIFT_FLC_RPC) #define BITS_FLC_RPC (BIT_MASK_FLC_RPC << BIT_SHIFT_FLC_RPC) #define BIT_CLEAR_FLC_RPC(x) ((x) & (~BITS_FLC_RPC)) #define BIT_GET_FLC_RPC(x) (((x) >> BIT_SHIFT_FLC_RPC) & BIT_MASK_FLC_RPC) #define BIT_SET_FLC_RPC(x, v) (BIT_CLEAR_FLC_RPC(x) | BIT_FLC_RPC(v)) /* 2 REG_FLC_RPCT (Offset 0x06AD) */ #define BIT_SHIFT_FLC_RPCT 0 #define BIT_MASK_FLC_RPCT 0xff #define BIT_FLC_RPCT(x) (((x) & BIT_MASK_FLC_RPCT) << BIT_SHIFT_FLC_RPCT) #define BITS_FLC_RPCT (BIT_MASK_FLC_RPCT << BIT_SHIFT_FLC_RPCT) #define BIT_CLEAR_FLC_RPCT(x) ((x) & (~BITS_FLC_RPCT)) #define BIT_GET_FLC_RPCT(x) (((x) >> BIT_SHIFT_FLC_RPCT) & BIT_MASK_FLC_RPCT) #define BIT_SET_FLC_RPCT(x, v) (BIT_CLEAR_FLC_RPCT(x) | BIT_FLC_RPCT(v)) /* 2 REG_FLC_PTS (Offset 0x06AE) */ #define BIT_CMF BIT(2) #define BIT_CCF BIT(1) #define BIT_CDF BIT(0) /* 2 REG_FLC_TRPC (Offset 0x06AF) */ #define BIT_FLC_RPCT_V1 BIT(7) #define BIT_MODE BIT(6) #define BIT_SHIFT_TRPCD 0 #define BIT_MASK_TRPCD 0x3f #define BIT_TRPCD(x) (((x) & BIT_MASK_TRPCD) << BIT_SHIFT_TRPCD) #define BITS_TRPCD (BIT_MASK_TRPCD << BIT_SHIFT_TRPCD) #define BIT_CLEAR_TRPCD(x) ((x) & (~BITS_TRPCD)) #define BIT_GET_TRPCD(x) (((x) >> BIT_SHIFT_TRPCD) & BIT_MASK_TRPCD) #define BIT_SET_TRPCD(x, v) (BIT_CLEAR_TRPCD(x) | BIT_TRPCD(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXPKTMON_CTRL (Offset 0x06B0) */ #define BIT_SHIFT_RXBKQPKT_SEQ 20 #define BIT_MASK_RXBKQPKT_SEQ 0xf #define BIT_RXBKQPKT_SEQ(x) \ (((x) & BIT_MASK_RXBKQPKT_SEQ) << BIT_SHIFT_RXBKQPKT_SEQ) #define BITS_RXBKQPKT_SEQ (BIT_MASK_RXBKQPKT_SEQ << BIT_SHIFT_RXBKQPKT_SEQ) #define BIT_CLEAR_RXBKQPKT_SEQ(x) ((x) & (~BITS_RXBKQPKT_SEQ)) #define BIT_GET_RXBKQPKT_SEQ(x) \ (((x) >> BIT_SHIFT_RXBKQPKT_SEQ) & BIT_MASK_RXBKQPKT_SEQ) #define BIT_SET_RXBKQPKT_SEQ(x, v) \ (BIT_CLEAR_RXBKQPKT_SEQ(x) | BIT_RXBKQPKT_SEQ(v)) #define BIT_SHIFT_RXBEQPKT_SEQ 16 #define BIT_MASK_RXBEQPKT_SEQ 0xf #define BIT_RXBEQPKT_SEQ(x) \ (((x) & BIT_MASK_RXBEQPKT_SEQ) << BIT_SHIFT_RXBEQPKT_SEQ) #define BITS_RXBEQPKT_SEQ (BIT_MASK_RXBEQPKT_SEQ << BIT_SHIFT_RXBEQPKT_SEQ) #define BIT_CLEAR_RXBEQPKT_SEQ(x) ((x) & (~BITS_RXBEQPKT_SEQ)) #define BIT_GET_RXBEQPKT_SEQ(x) \ (((x) >> BIT_SHIFT_RXBEQPKT_SEQ) & BIT_MASK_RXBEQPKT_SEQ) #define BIT_SET_RXBEQPKT_SEQ(x, v) \ (BIT_CLEAR_RXBEQPKT_SEQ(x) | BIT_RXBEQPKT_SEQ(v)) #define BIT_SHIFT_RXVIQPKT_SEQ 12 #define BIT_MASK_RXVIQPKT_SEQ 0xf #define BIT_RXVIQPKT_SEQ(x) \ (((x) & BIT_MASK_RXVIQPKT_SEQ) << BIT_SHIFT_RXVIQPKT_SEQ) #define BITS_RXVIQPKT_SEQ (BIT_MASK_RXVIQPKT_SEQ << BIT_SHIFT_RXVIQPKT_SEQ) #define BIT_CLEAR_RXVIQPKT_SEQ(x) ((x) & (~BITS_RXVIQPKT_SEQ)) #define BIT_GET_RXVIQPKT_SEQ(x) \ (((x) >> BIT_SHIFT_RXVIQPKT_SEQ) & BIT_MASK_RXVIQPKT_SEQ) #define BIT_SET_RXVIQPKT_SEQ(x, v) \ (BIT_CLEAR_RXVIQPKT_SEQ(x) | BIT_RXVIQPKT_SEQ(v)) #define BIT_SHIFT_RXVOQPKT_SEQ 8 #define BIT_MASK_RXVOQPKT_SEQ 0xf #define BIT_RXVOQPKT_SEQ(x) \ (((x) & BIT_MASK_RXVOQPKT_SEQ) << BIT_SHIFT_RXVOQPKT_SEQ) #define BITS_RXVOQPKT_SEQ (BIT_MASK_RXVOQPKT_SEQ << BIT_SHIFT_RXVOQPKT_SEQ) #define BIT_CLEAR_RXVOQPKT_SEQ(x) ((x) & (~BITS_RXVOQPKT_SEQ)) #define BIT_GET_RXVOQPKT_SEQ(x) \ (((x) >> BIT_SHIFT_RXVOQPKT_SEQ) & BIT_MASK_RXVOQPKT_SEQ) #define BIT_SET_RXVOQPKT_SEQ(x, v) \ (BIT_CLEAR_RXVOQPKT_SEQ(x) | BIT_RXVOQPKT_SEQ(v)) #define BIT_RXBKQPKT_ERR BIT(7) #define BIT_RXBEQPKT_ERR BIT(6) #define BIT_RXVIQPKT_ERR BIT(5) #define BIT_RXVOQPKT_ERR BIT(4) #define BIT_RXDMA_MON_EN BIT(2) #define BIT_RXPKT_MON_RST BIT(1) #define BIT_RXPKT_MON_EN BIT(0) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_STATE_MON (Offset 0x06B4) */ #define BIT_SHIFT_DMA_MON_EN 24 #define BIT_MASK_DMA_MON_EN 0x1f #define BIT_DMA_MON_EN(x) (((x) & BIT_MASK_DMA_MON_EN) << BIT_SHIFT_DMA_MON_EN) #define BITS_DMA_MON_EN (BIT_MASK_DMA_MON_EN << BIT_SHIFT_DMA_MON_EN) #define BIT_CLEAR_DMA_MON_EN(x) ((x) & (~BITS_DMA_MON_EN)) #define BIT_GET_DMA_MON_EN(x) \ (((x) >> BIT_SHIFT_DMA_MON_EN) & BIT_MASK_DMA_MON_EN) #define BIT_SET_DMA_MON_EN(x, v) (BIT_CLEAR_DMA_MON_EN(x) | BIT_DMA_MON_EN(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_STATE_MON (Offset 0x06B4) */ #define BIT_SHIFT_STATE_SEL 24 #define BIT_MASK_STATE_SEL 0x1f #define BIT_STATE_SEL(x) (((x) & BIT_MASK_STATE_SEL) << BIT_SHIFT_STATE_SEL) #define BITS_STATE_SEL (BIT_MASK_STATE_SEL << BIT_SHIFT_STATE_SEL) #define BIT_CLEAR_STATE_SEL(x) ((x) & (~BITS_STATE_SEL)) #define BIT_GET_STATE_SEL(x) (((x) >> BIT_SHIFT_STATE_SEL) & BIT_MASK_STATE_SEL) #define BIT_SET_STATE_SEL(x, v) (BIT_CLEAR_STATE_SEL(x) | BIT_STATE_SEL(v)) #define BIT_SHIFT_STATE_INFO 8 #define BIT_MASK_STATE_INFO 0xff #define BIT_STATE_INFO(x) (((x) & BIT_MASK_STATE_INFO) << BIT_SHIFT_STATE_INFO) #define BITS_STATE_INFO (BIT_MASK_STATE_INFO << BIT_SHIFT_STATE_INFO) #define BIT_CLEAR_STATE_INFO(x) ((x) & (~BITS_STATE_INFO)) #define BIT_GET_STATE_INFO(x) \ (((x) >> BIT_SHIFT_STATE_INFO) & BIT_MASK_STATE_INFO) #define BIT_SET_STATE_INFO(x, v) (BIT_CLEAR_STATE_INFO(x) | BIT_STATE_INFO(v)) #define BIT_UPD_NXT_STATE BIT(7) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_STATE_MON (Offset 0x06B4) */ #define BIT_SHIFT_PKT_MON_EN 0 #define BIT_MASK_PKT_MON_EN 0x7f #define BIT_PKT_MON_EN(x) (((x) & BIT_MASK_PKT_MON_EN) << BIT_SHIFT_PKT_MON_EN) #define BITS_PKT_MON_EN (BIT_MASK_PKT_MON_EN << BIT_SHIFT_PKT_MON_EN) #define BIT_CLEAR_PKT_MON_EN(x) ((x) & (~BITS_PKT_MON_EN)) #define BIT_GET_PKT_MON_EN(x) \ (((x) >> BIT_SHIFT_PKT_MON_EN) & BIT_MASK_PKT_MON_EN) #define BIT_SET_PKT_MON_EN(x, v) (BIT_CLEAR_PKT_MON_EN(x) | BIT_PKT_MON_EN(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_STATE_MON (Offset 0x06B4) */ #define BIT_SHIFT_CUR_STATE 0 #define BIT_MASK_CUR_STATE 0x7f #define BIT_CUR_STATE(x) (((x) & BIT_MASK_CUR_STATE) << BIT_SHIFT_CUR_STATE) #define BITS_CUR_STATE (BIT_MASK_CUR_STATE << BIT_SHIFT_CUR_STATE) #define BIT_CLEAR_CUR_STATE(x) ((x) & (~BITS_CUR_STATE)) #define BIT_GET_CUR_STATE(x) (((x) >> BIT_SHIFT_CUR_STATE) & BIT_MASK_CUR_STATE) #define BIT_SET_CUR_STATE(x, v) (BIT_CLEAR_CUR_STATE(x) | BIT_CUR_STATE(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ERROR_MON (Offset 0x06B8) */ #define BIT_CSIRPT_LEN_BB_MORE_THAN_MAC BIT(23) #define BIT_CSI_CHKSUM_ERROR BIT(22) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_ERROR_MON (Offset 0x06B8) */ #define BIT_BFM_RPTNUM_ERROR BIT(21) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ERROR_MON (Offset 0x06B8) */ #define BIT_MACRX_ERR_5 BIT(21) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_ERROR_MON (Offset 0x06B8) */ #define BIT_BFM_CHECKSUM_ERROR BIT(20) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ERROR_MON (Offset 0x06B8) */ #define BIT_MACRX_ERR_4 BIT(20) #define BIT_MACRX_ERR_3 BIT(19) #define BIT_MACRX_ERR_2 BIT(18) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ERROR_MON (Offset 0x06B8) */ #define BIT_MACRX_ERR_1 BIT(17) #define BIT_MACRX_ERR_0 BIT(16) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_ERROR_MON (Offset 0x06B8) */ #define BIT_PRETX_ERRHDL_EN BIT(15) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ERROR_MON (Offset 0x06B8) */ #define BIT_WMAC_PRETX_ERRHDL_EN BIT(15) #define BIT_MACTX_ERR_5 BIT(5) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ERROR_MON (Offset 0x06B8) */ #define BIT_MACTX_ERR_4 BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ERROR_MON (Offset 0x06B8) */ #define BIT_MACTX_ERR_3 BIT(3) #define BIT_MACTX_ERR_2 BIT(2) #define BIT_MACTX_ERR_1 BIT(1) #define BIT_MACTX_ERR_0 BIT(0) /* 2 REG_SEARCH_MACID (Offset 0x06BC) */ #define BIT_EN_TXRPTBUF_CLK BIT(31) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SEARCH_MACID (Offset 0x06BC) */ #define BIT_SHIFT_INFO_INDEX_OFFSET 16 #define BIT_MASK_INFO_INDEX_OFFSET 0x1fff #define BIT_INFO_INDEX_OFFSET(x) \ (((x) & BIT_MASK_INFO_INDEX_OFFSET) << BIT_SHIFT_INFO_INDEX_OFFSET) #define BITS_INFO_INDEX_OFFSET \ (BIT_MASK_INFO_INDEX_OFFSET << BIT_SHIFT_INFO_INDEX_OFFSET) #define BIT_CLEAR_INFO_INDEX_OFFSET(x) ((x) & (~BITS_INFO_INDEX_OFFSET)) #define BIT_GET_INFO_INDEX_OFFSET(x) \ (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET) & BIT_MASK_INFO_INDEX_OFFSET) #define BIT_SET_INFO_INDEX_OFFSET(x, v) \ (BIT_CLEAR_INFO_INDEX_OFFSET(x) | BIT_INFO_INDEX_OFFSET(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SEARCH_MACID (Offset 0x06BC) */ #define BIT_WMAC_SRCH_FIFOFULL BIT(15) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SEARCH_MACID (Offset 0x06BC) */ #define BIT_DIS_INFOSRCH BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_SEARCH_MACID (Offset 0x06BC) */ #define BIT_DISABLE_B0 BIT(13) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SEARCH_MACID (Offset 0x06BC) */ #define BIT_SHIFT_INFO_ADDR_OFFSET 0 #define BIT_MASK_INFO_ADDR_OFFSET 0x1fff #define BIT_INFO_ADDR_OFFSET(x) \ (((x) & BIT_MASK_INFO_ADDR_OFFSET) << BIT_SHIFT_INFO_ADDR_OFFSET) #define BITS_INFO_ADDR_OFFSET \ (BIT_MASK_INFO_ADDR_OFFSET << BIT_SHIFT_INFO_ADDR_OFFSET) #define BIT_CLEAR_INFO_ADDR_OFFSET(x) ((x) & (~BITS_INFO_ADDR_OFFSET)) #define BIT_GET_INFO_ADDR_OFFSET(x) \ (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET) & BIT_MASK_INFO_ADDR_OFFSET) #define BIT_SET_INFO_ADDR_OFFSET(x, v) \ (BIT_CLEAR_INFO_ADDR_OFFSET(x) | BIT_INFO_ADDR_OFFSET(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_BT_COEX_TABLE (Offset 0x06C0) */ #define BIT_PRI_MASK_RX_RESP BIT(126) #define BIT_PRI_MASK_RXOFDM BIT(125) #define BIT_PRI_MASK_RXCCK BIT(124) #define BIT_PRI_MASK_CCK BIT(108) #define BIT_PRI_MASK_OFDM BIT(107) #define BIT_PRI_MASK_RTY BIT(106) #define BIT_OOB BIT(97) #define BIT_ANT_SEL BIT(96) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_BT_COEX_TABLE (Offset 0x06C0) */ #define BIT_SHIFT_COEX_TABLE_1 0 #define BIT_MASK_COEX_TABLE_1 0xffffffffL #define BIT_COEX_TABLE_1(x) \ (((x) & BIT_MASK_COEX_TABLE_1) << BIT_SHIFT_COEX_TABLE_1) #define BITS_COEX_TABLE_1 (BIT_MASK_COEX_TABLE_1 << BIT_SHIFT_COEX_TABLE_1) #define BIT_CLEAR_COEX_TABLE_1(x) ((x) & (~BITS_COEX_TABLE_1)) #define BIT_GET_COEX_TABLE_1(x) \ (((x) >> BIT_SHIFT_COEX_TABLE_1) & BIT_MASK_COEX_TABLE_1) #define BIT_SET_COEX_TABLE_1(x, v) \ (BIT_CLEAR_COEX_TABLE_1(x) | BIT_COEX_TABLE_1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BT_COEX_TABLE_H (Offset 0x06CC) */ #define BIT_PRI_MASK_RX_RESP_V1 BIT(30) #define BIT_PRI_MASK_RXOFDM_V1 BIT(29) #define BIT_PRI_MASK_RXCCK_V1 BIT(28) #define BIT_PRI_MASK_CCK_V1 BIT(12) #define BIT_PRI_MASK_OFDM_V1 BIT(11) #define BIT_PRI_MASK_RTY_V1 BIT(10) #define BIT_OOB_V1 BIT(1) #define BIT_ANT_SEL_V1 BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXCMD_0 (Offset 0x06D0) */ #define BIT_RXCMD_EN BIT(31) #define BIT_SHIFT_RXCMD_INFO 0 #define BIT_MASK_RXCMD_INFO 0x7fffffffL #define BIT_RXCMD_INFO(x) (((x) & BIT_MASK_RXCMD_INFO) << BIT_SHIFT_RXCMD_INFO) #define BITS_RXCMD_INFO (BIT_MASK_RXCMD_INFO << BIT_SHIFT_RXCMD_INFO) #define BIT_CLEAR_RXCMD_INFO(x) ((x) & (~BITS_RXCMD_INFO)) #define BIT_GET_RXCMD_INFO(x) \ (((x) >> BIT_SHIFT_RXCMD_INFO) & BIT_MASK_RXCMD_INFO) #define BIT_SET_RXCMD_INFO(x, v) (BIT_CLEAR_RXCMD_INFO(x) | BIT_RXCMD_INFO(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_RXCMD_1 (Offset 0x06D4) */ #define BIT_SHIFT_CSI_RADDR_LATCH_V1 24 #define BIT_MASK_CSI_RADDR_LATCH_V1 0x3f #define BIT_CSI_RADDR_LATCH_V1(x) \ (((x) & BIT_MASK_CSI_RADDR_LATCH_V1) << BIT_SHIFT_CSI_RADDR_LATCH_V1) #define BITS_CSI_RADDR_LATCH_V1 \ (BIT_MASK_CSI_RADDR_LATCH_V1 << BIT_SHIFT_CSI_RADDR_LATCH_V1) #define BIT_CLEAR_CSI_RADDR_LATCH_V1(x) ((x) & (~BITS_CSI_RADDR_LATCH_V1)) #define BIT_GET_CSI_RADDR_LATCH_V1(x) \ (((x) >> BIT_SHIFT_CSI_RADDR_LATCH_V1) & BIT_MASK_CSI_RADDR_LATCH_V1) #define BIT_SET_CSI_RADDR_LATCH_V1(x, v) \ (BIT_CLEAR_CSI_RADDR_LATCH_V1(x) | BIT_CSI_RADDR_LATCH_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_RXCMD_1 (Offset 0x06D4) */ #define BIT_SHIFT_CSI_RADDR_LATCH 24 #define BIT_MASK_CSI_RADDR_LATCH 0xff #define BIT_CSI_RADDR_LATCH(x) \ (((x) & BIT_MASK_CSI_RADDR_LATCH) << BIT_SHIFT_CSI_RADDR_LATCH) #define BITS_CSI_RADDR_LATCH \ (BIT_MASK_CSI_RADDR_LATCH << BIT_SHIFT_CSI_RADDR_LATCH) #define BIT_CLEAR_CSI_RADDR_LATCH(x) ((x) & (~BITS_CSI_RADDR_LATCH)) #define BIT_GET_CSI_RADDR_LATCH(x) \ (((x) >> BIT_SHIFT_CSI_RADDR_LATCH) & BIT_MASK_CSI_RADDR_LATCH) #define BIT_SET_CSI_RADDR_LATCH(x, v) \ (BIT_CLEAR_CSI_RADDR_LATCH(x) | BIT_CSI_RADDR_LATCH(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_RXCMD_1 (Offset 0x06D4) */ #define BIT_SHIFT_CSI_WADDR_LATCH_V1 16 #define BIT_MASK_CSI_WADDR_LATCH_V1 0x3f #define BIT_CSI_WADDR_LATCH_V1(x) \ (((x) & BIT_MASK_CSI_WADDR_LATCH_V1) << BIT_SHIFT_CSI_WADDR_LATCH_V1) #define BITS_CSI_WADDR_LATCH_V1 \ (BIT_MASK_CSI_WADDR_LATCH_V1 << BIT_SHIFT_CSI_WADDR_LATCH_V1) #define BIT_CLEAR_CSI_WADDR_LATCH_V1(x) ((x) & (~BITS_CSI_WADDR_LATCH_V1)) #define BIT_GET_CSI_WADDR_LATCH_V1(x) \ (((x) >> BIT_SHIFT_CSI_WADDR_LATCH_V1) & BIT_MASK_CSI_WADDR_LATCH_V1) #define BIT_SET_CSI_WADDR_LATCH_V1(x, v) \ (BIT_CLEAR_CSI_WADDR_LATCH_V1(x) | BIT_CSI_WADDR_LATCH_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_RXCMD_1 (Offset 0x06D4) */ #define BIT_SHIFT_CSI_WADDR_LATCH 16 #define BIT_MASK_CSI_WADDR_LATCH 0xff #define BIT_CSI_WADDR_LATCH(x) \ (((x) & BIT_MASK_CSI_WADDR_LATCH) << BIT_SHIFT_CSI_WADDR_LATCH) #define BITS_CSI_WADDR_LATCH \ (BIT_MASK_CSI_WADDR_LATCH << BIT_SHIFT_CSI_WADDR_LATCH) #define BIT_CLEAR_CSI_WADDR_LATCH(x) ((x) & (~BITS_CSI_WADDR_LATCH)) #define BIT_GET_CSI_WADDR_LATCH(x) \ (((x) >> BIT_SHIFT_CSI_WADDR_LATCH) & BIT_MASK_CSI_WADDR_LATCH) #define BIT_SET_CSI_WADDR_LATCH(x, v) \ (BIT_CLEAR_CSI_WADDR_LATCH(x) | BIT_CSI_WADDR_LATCH(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXCMD_1 (Offset 0x06D4) */ #define BIT_SHIFT_RXCMD_PRD 0 #define BIT_MASK_RXCMD_PRD 0xffff #define BIT_RXCMD_PRD(x) (((x) & BIT_MASK_RXCMD_PRD) << BIT_SHIFT_RXCMD_PRD) #define BITS_RXCMD_PRD (BIT_MASK_RXCMD_PRD << BIT_SHIFT_RXCMD_PRD) #define BIT_CLEAR_RXCMD_PRD(x) ((x) & (~BITS_RXCMD_PRD)) #define BIT_GET_RXCMD_PRD(x) (((x) >> BIT_SHIFT_RXCMD_PRD) & BIT_MASK_RXCMD_PRD) #define BIT_SET_RXCMD_PRD(x, v) (BIT_CLEAR_RXCMD_PRD(x) | BIT_RXCMD_PRD(v)) /* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ #define BIT_SHIFT_WMAC_RESP_MFB 25 #define BIT_MASK_WMAC_RESP_MFB 0x7f #define BIT_WMAC_RESP_MFB(x) \ (((x) & BIT_MASK_WMAC_RESP_MFB) << BIT_SHIFT_WMAC_RESP_MFB) #define BITS_WMAC_RESP_MFB (BIT_MASK_WMAC_RESP_MFB << BIT_SHIFT_WMAC_RESP_MFB) #define BIT_CLEAR_WMAC_RESP_MFB(x) ((x) & (~BITS_WMAC_RESP_MFB)) #define BIT_GET_WMAC_RESP_MFB(x) \ (((x) >> BIT_SHIFT_WMAC_RESP_MFB) & BIT_MASK_WMAC_RESP_MFB) #define BIT_SET_WMAC_RESP_MFB(x, v) \ (BIT_CLEAR_WMAC_RESP_MFB(x) | BIT_WMAC_RESP_MFB(v)) #define BIT_SHIFT_WMAC_ANTINF_SEL 23 #define BIT_MASK_WMAC_ANTINF_SEL 0x3 #define BIT_WMAC_ANTINF_SEL(x) \ (((x) & BIT_MASK_WMAC_ANTINF_SEL) << BIT_SHIFT_WMAC_ANTINF_SEL) #define BITS_WMAC_ANTINF_SEL \ (BIT_MASK_WMAC_ANTINF_SEL << BIT_SHIFT_WMAC_ANTINF_SEL) #define BIT_CLEAR_WMAC_ANTINF_SEL(x) ((x) & (~BITS_WMAC_ANTINF_SEL)) #define BIT_GET_WMAC_ANTINF_SEL(x) \ (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL) & BIT_MASK_WMAC_ANTINF_SEL) #define BIT_SET_WMAC_ANTINF_SEL(x, v) \ (BIT_CLEAR_WMAC_ANTINF_SEL(x) | BIT_WMAC_ANTINF_SEL(v)) #define BIT_SHIFT_WMAC_ANTSEL_SEL 21 #define BIT_MASK_WMAC_ANTSEL_SEL 0x3 #define BIT_WMAC_ANTSEL_SEL(x) \ (((x) & BIT_MASK_WMAC_ANTSEL_SEL) << BIT_SHIFT_WMAC_ANTSEL_SEL) #define BITS_WMAC_ANTSEL_SEL \ (BIT_MASK_WMAC_ANTSEL_SEL << BIT_SHIFT_WMAC_ANTSEL_SEL) #define BIT_CLEAR_WMAC_ANTSEL_SEL(x) ((x) & (~BITS_WMAC_ANTSEL_SEL)) #define BIT_GET_WMAC_ANTSEL_SEL(x) \ (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL) & BIT_MASK_WMAC_ANTSEL_SEL) #define BIT_SET_WMAC_ANTSEL_SEL(x, v) \ (BIT_CLEAR_WMAC_ANTSEL_SEL(x) | BIT_WMAC_ANTSEL_SEL(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ #define BIT_SHIFT_RESP_TXPOWER 18 #define BIT_MASK_RESP_TXPOWER 0x7 #define BIT_RESP_TXPOWER(x) \ (((x) & BIT_MASK_RESP_TXPOWER) << BIT_SHIFT_RESP_TXPOWER) #define BITS_RESP_TXPOWER (BIT_MASK_RESP_TXPOWER << BIT_SHIFT_RESP_TXPOWER) #define BIT_CLEAR_RESP_TXPOWER(x) ((x) & (~BITS_RESP_TXPOWER)) #define BIT_GET_RESP_TXPOWER(x) \ (((x) >> BIT_SHIFT_RESP_TXPOWER) & BIT_MASK_RESP_TXPOWER) #define BIT_SET_RESP_TXPOWER(x, v) \ (BIT_CLEAR_RESP_TXPOWER(x) | BIT_RESP_TXPOWER(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ #define BIT_SHIFT_R_WMAC_RESP_TXPOWER 18 #define BIT_MASK_R_WMAC_RESP_TXPOWER 0x7 #define BIT_R_WMAC_RESP_TXPOWER(x) \ (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER) << BIT_SHIFT_R_WMAC_RESP_TXPOWER) #define BITS_R_WMAC_RESP_TXPOWER \ (BIT_MASK_R_WMAC_RESP_TXPOWER << BIT_SHIFT_R_WMAC_RESP_TXPOWER) #define BIT_CLEAR_R_WMAC_RESP_TXPOWER(x) ((x) & (~BITS_R_WMAC_RESP_TXPOWER)) #define BIT_GET_R_WMAC_RESP_TXPOWER(x) \ (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER) & BIT_MASK_R_WMAC_RESP_TXPOWER) #define BIT_SET_R_WMAC_RESP_TXPOWER(x, v) \ (BIT_CLEAR_R_WMAC_RESP_TXPOWER(x) | BIT_R_WMAC_RESP_TXPOWER(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ #define BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE 18 #define BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE 0x3 #define BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE(x) \ (((x) & BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE) \ << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE) #define BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE \ (BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE \ << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE) #define BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE(x) \ ((x) & (~BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE)) #define BIT_GET_WMAC_RESP_TXPOWER_OFFSET_TYPE(x) \ (((x) >> BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE) & \ BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE) #define BIT_SET_WMAC_RESP_TXPOWER_OFFSET_TYPE(x, v) \ (BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE(x) | \ BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ #define BIT_SHIFT_RESP_TXAGC_B 13 #define BIT_MASK_RESP_TXAGC_B 0x1f #define BIT_RESP_TXAGC_B(x) \ (((x) & BIT_MASK_RESP_TXAGC_B) << BIT_SHIFT_RESP_TXAGC_B) #define BITS_RESP_TXAGC_B (BIT_MASK_RESP_TXAGC_B << BIT_SHIFT_RESP_TXAGC_B) #define BIT_CLEAR_RESP_TXAGC_B(x) ((x) & (~BITS_RESP_TXAGC_B)) #define BIT_GET_RESP_TXAGC_B(x) \ (((x) >> BIT_SHIFT_RESP_TXAGC_B) & BIT_MASK_RESP_TXAGC_B) #define BIT_SET_RESP_TXAGC_B(x, v) \ (BIT_CLEAR_RESP_TXAGC_B(x) | BIT_RESP_TXAGC_B(v)) #define BIT_SHIFT_RESP_TXAGC_A 8 #define BIT_MASK_RESP_TXAGC_A 0x1f #define BIT_RESP_TXAGC_A(x) \ (((x) & BIT_MASK_RESP_TXAGC_A) << BIT_SHIFT_RESP_TXAGC_A) #define BITS_RESP_TXAGC_A (BIT_MASK_RESP_TXAGC_A << BIT_SHIFT_RESP_TXAGC_A) #define BIT_CLEAR_RESP_TXAGC_A(x) ((x) & (~BITS_RESP_TXAGC_A)) #define BIT_GET_RESP_TXAGC_A(x) \ (((x) >> BIT_SHIFT_RESP_TXAGC_A) & BIT_MASK_RESP_TXAGC_A) #define BIT_SET_RESP_TXAGC_A(x, v) \ (BIT_CLEAR_RESP_TXAGC_A(x) | BIT_RESP_TXAGC_A(v)) #define BIT_RESP_ANTSEL_B BIT(7) #define BIT_RESP_ANTSEL_A BIT(6) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ #define BIT_SHIFT_WMAC_RESP_TXANT_V1 6 #define BIT_MASK_WMAC_RESP_TXANT_V1 0xfff #define BIT_WMAC_RESP_TXANT_V1(x) \ (((x) & BIT_MASK_WMAC_RESP_TXANT_V1) << BIT_SHIFT_WMAC_RESP_TXANT_V1) #define BITS_WMAC_RESP_TXANT_V1 \ (BIT_MASK_WMAC_RESP_TXANT_V1 << BIT_SHIFT_WMAC_RESP_TXANT_V1) #define BIT_CLEAR_WMAC_RESP_TXANT_V1(x) ((x) & (~BITS_WMAC_RESP_TXANT_V1)) #define BIT_GET_WMAC_RESP_TXANT_V1(x) \ (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_V1) & BIT_MASK_WMAC_RESP_TXANT_V1) #define BIT_SET_WMAC_RESP_TXANT_V1(x, v) \ (BIT_CLEAR_WMAC_RESP_TXANT_V1(x) | BIT_WMAC_RESP_TXANT_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ #define BIT_SHIFT_RESP_TXANT_CCK 4 #define BIT_MASK_RESP_TXANT_CCK 0x3 #define BIT_RESP_TXANT_CCK(x) \ (((x) & BIT_MASK_RESP_TXANT_CCK) << BIT_SHIFT_RESP_TXANT_CCK) #define BITS_RESP_TXANT_CCK \ (BIT_MASK_RESP_TXANT_CCK << BIT_SHIFT_RESP_TXANT_CCK) #define BIT_CLEAR_RESP_TXANT_CCK(x) ((x) & (~BITS_RESP_TXANT_CCK)) #define BIT_GET_RESP_TXANT_CCK(x) \ (((x) >> BIT_SHIFT_RESP_TXANT_CCK) & BIT_MASK_RESP_TXANT_CCK) #define BIT_SET_RESP_TXANT_CCK(x, v) \ (BIT_CLEAR_RESP_TXANT_CCK(x) | BIT_RESP_TXANT_CCK(v)) #define BIT_SHIFT_RESP_TXANT_L 2 #define BIT_MASK_RESP_TXANT_L 0x3 #define BIT_RESP_TXANT_L(x) \ (((x) & BIT_MASK_RESP_TXANT_L) << BIT_SHIFT_RESP_TXANT_L) #define BITS_RESP_TXANT_L (BIT_MASK_RESP_TXANT_L << BIT_SHIFT_RESP_TXANT_L) #define BIT_CLEAR_RESP_TXANT_L(x) ((x) & (~BITS_RESP_TXANT_L)) #define BIT_GET_RESP_TXANT_L(x) \ (((x) >> BIT_SHIFT_RESP_TXANT_L) & BIT_MASK_RESP_TXANT_L) #define BIT_SET_RESP_TXANT_L(x, v) \ (BIT_CLEAR_RESP_TXANT_L(x) | BIT_RESP_TXANT_L(v)) #define BIT_SHIFT_RESP_TXANT_HT 0 #define BIT_MASK_RESP_TXANT_HT 0x3 #define BIT_RESP_TXANT_HT(x) \ (((x) & BIT_MASK_RESP_TXANT_HT) << BIT_SHIFT_RESP_TXANT_HT) #define BITS_RESP_TXANT_HT (BIT_MASK_RESP_TXANT_HT << BIT_SHIFT_RESP_TXANT_HT) #define BIT_CLEAR_RESP_TXANT_HT(x) ((x) & (~BITS_RESP_TXANT_HT)) #define BIT_GET_RESP_TXANT_HT(x) \ (((x) >> BIT_SHIFT_RESP_TXANT_HT) & BIT_MASK_RESP_TXANT_HT) #define BIT_SET_RESP_TXANT_HT(x, v) \ (BIT_CLEAR_RESP_TXANT_HT(x) | BIT_RESP_TXANT_HT(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ #define BIT_SHIFT_WMAC_RESP_TXANT 0 #define BIT_MASK_WMAC_RESP_TXANT 0x3ffff #define BIT_WMAC_RESP_TXANT(x) \ (((x) & BIT_MASK_WMAC_RESP_TXANT) << BIT_SHIFT_WMAC_RESP_TXANT) #define BITS_WMAC_RESP_TXANT \ (BIT_MASK_WMAC_RESP_TXANT << BIT_SHIFT_WMAC_RESP_TXANT) #define BIT_CLEAR_WMAC_RESP_TXANT(x) ((x) & (~BITS_WMAC_RESP_TXANT)) #define BIT_GET_WMAC_RESP_TXANT(x) \ (((x) >> BIT_SHIFT_WMAC_RESP_TXANT) & BIT_MASK_WMAC_RESP_TXANT) #define BIT_SET_WMAC_RESP_TXANT(x, v) \ (BIT_CLEAR_WMAC_RESP_TXANT(x) | BIT_WMAC_RESP_TXANT(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ #define BIT_CTL_IDLE_CLR_CSI_RPT BIT(31) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ #define BIT_WMAC_USE_NDPARATE BIT(30) #define BIT_SHIFT_WMAC_CSI_RATE 24 #define BIT_MASK_WMAC_CSI_RATE 0x3f #define BIT_WMAC_CSI_RATE(x) \ (((x) & BIT_MASK_WMAC_CSI_RATE) << BIT_SHIFT_WMAC_CSI_RATE) #define BITS_WMAC_CSI_RATE (BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE) #define BIT_CLEAR_WMAC_CSI_RATE(x) ((x) & (~BITS_WMAC_CSI_RATE)) #define BIT_GET_WMAC_CSI_RATE(x) \ (((x) >> BIT_SHIFT_WMAC_CSI_RATE) & BIT_MASK_WMAC_CSI_RATE) #define BIT_SET_WMAC_CSI_RATE(x, v) \ (BIT_CLEAR_WMAC_CSI_RATE(x) | BIT_WMAC_CSI_RATE(v)) #define BIT_SHIFT_WMAC_RESP_TXRATE 16 #define BIT_MASK_WMAC_RESP_TXRATE 0xff #define BIT_WMAC_RESP_TXRATE(x) \ (((x) & BIT_MASK_WMAC_RESP_TXRATE) << BIT_SHIFT_WMAC_RESP_TXRATE) #define BITS_WMAC_RESP_TXRATE \ (BIT_MASK_WMAC_RESP_TXRATE << BIT_SHIFT_WMAC_RESP_TXRATE) #define BIT_CLEAR_WMAC_RESP_TXRATE(x) ((x) & (~BITS_WMAC_RESP_TXRATE)) #define BIT_GET_WMAC_RESP_TXRATE(x) \ (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE) & BIT_MASK_WMAC_RESP_TXRATE) #define BIT_SET_WMAC_RESP_TXRATE(x, v) \ (BIT_CLEAR_WMAC_RESP_TXRATE(x) | BIT_WMAC_RESP_TXRATE(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ #define BIT_WMAC_CSI_RATE_FORCE_EN BIT(15) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ #define BIT_CSI_FORCE_RATE_EN BIT(15) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ #define BIT_SHIFT_WMAC_CSI_RSC_FORCE 13 #define BIT_MASK_WMAC_CSI_RSC_FORCE 0x3 #define BIT_WMAC_CSI_RSC_FORCE(x) \ (((x) & BIT_MASK_WMAC_CSI_RSC_FORCE) << BIT_SHIFT_WMAC_CSI_RSC_FORCE) #define BITS_WMAC_CSI_RSC_FORCE \ (BIT_MASK_WMAC_CSI_RSC_FORCE << BIT_SHIFT_WMAC_CSI_RSC_FORCE) #define BIT_CLEAR_WMAC_CSI_RSC_FORCE(x) ((x) & (~BITS_WMAC_CSI_RSC_FORCE)) #define BIT_GET_WMAC_CSI_RSC_FORCE(x) \ (((x) >> BIT_SHIFT_WMAC_CSI_RSC_FORCE) & BIT_MASK_WMAC_CSI_RSC_FORCE) #define BIT_SET_WMAC_CSI_RSC_FORCE(x, v) \ (BIT_CLEAR_WMAC_CSI_RSC_FORCE(x) | BIT_WMAC_CSI_RSC_FORCE(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ #define BIT_SHIFT_CSI_RSC 13 #define BIT_MASK_CSI_RSC 0x3 #define BIT_CSI_RSC(x) (((x) & BIT_MASK_CSI_RSC) << BIT_SHIFT_CSI_RSC) #define BITS_CSI_RSC (BIT_MASK_CSI_RSC << BIT_SHIFT_CSI_RSC) #define BIT_CLEAR_CSI_RSC(x) ((x) & (~BITS_CSI_RSC)) #define BIT_GET_CSI_RSC(x) (((x) >> BIT_SHIFT_CSI_RSC) & BIT_MASK_CSI_RSC) #define BIT_SET_CSI_RSC(x, v) (BIT_CLEAR_CSI_RSC(x) | BIT_CSI_RSC(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ #define BIT_WMAC_CSI_GID_SEL BIT(12) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ #define BIT_CSI_GID_SEL BIT(12) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ #define BIT_RDCSIMD_FLAG_TRIG_SEL BIT(11) #define BIT_NDPVLD_POS_RST_FFPTR_DIS_V1 BIT(10) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ #define BIT_NDPVLD_PROTECT_RDRDY_DIS BIT(9) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ #define BIT_CSIRD_EMPTY_APPZERO BIT(8) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ #define BIT_RDCSI_EMPTY_APPZERO BIT(8) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ #define BIT_WMC_CSI_RATE_FB_EN BIT(7) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ #define BIT_CSI_RATE_FB_EN BIT(7) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ #define BIT_RXFIFO_WRPTR_WO_CHKSUM BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ #define BIT_BBPSF_MPDUCHKEN BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ #define BIT_BBPSF_MHCHKEN BIT(4) #define BIT_BBPSF_ERRCHKEN BIT(3) #define BIT_SHIFT_BBPSF_ERRTHR 0 #define BIT_MASK_BBPSF_ERRTHR 0x7 #define BIT_BBPSF_ERRTHR(x) \ (((x) & BIT_MASK_BBPSF_ERRTHR) << BIT_SHIFT_BBPSF_ERRTHR) #define BITS_BBPSF_ERRTHR (BIT_MASK_BBPSF_ERRTHR << BIT_SHIFT_BBPSF_ERRTHR) #define BIT_CLEAR_BBPSF_ERRTHR(x) ((x) & (~BITS_BBPSF_ERRTHR)) #define BIT_GET_BBPSF_ERRTHR(x) \ (((x) >> BIT_SHIFT_BBPSF_ERRTHR) & BIT_MASK_BBPSF_ERRTHR) #define BIT_SET_BBPSF_ERRTHR(x, v) \ (BIT_CLEAR_BBPSF_ERRTHR(x) | BIT_BBPSF_ERRTHR(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ #define BIT_NOA_PARSER_EN BIT(15) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ #define BIT_BSSID_SEL BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ #define BIT_SHIFT_BSSID_SEL_V1 12 #define BIT_MASK_BSSID_SEL_V1 0x7 #define BIT_BSSID_SEL_V1(x) \ (((x) & BIT_MASK_BSSID_SEL_V1) << BIT_SHIFT_BSSID_SEL_V1) #define BITS_BSSID_SEL_V1 (BIT_MASK_BSSID_SEL_V1 << BIT_SHIFT_BSSID_SEL_V1) #define BIT_CLEAR_BSSID_SEL_V1(x) ((x) & (~BITS_BSSID_SEL_V1)) #define BIT_GET_BSSID_SEL_V1(x) \ (((x) >> BIT_SHIFT_BSSID_SEL_V1) & BIT_MASK_BSSID_SEL_V1) #define BIT_SET_BSSID_SEL_V1(x, v) \ (BIT_CLEAR_BSSID_SEL_V1(x) | BIT_BSSID_SEL_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ #define BIT_SHIFT_P2P_OUI_TYPE 0 #define BIT_MASK_P2P_OUI_TYPE 0xff #define BIT_P2P_OUI_TYPE(x) \ (((x) & BIT_MASK_P2P_OUI_TYPE) << BIT_SHIFT_P2P_OUI_TYPE) #define BITS_P2P_OUI_TYPE (BIT_MASK_P2P_OUI_TYPE << BIT_SHIFT_P2P_OUI_TYPE) #define BIT_CLEAR_P2P_OUI_TYPE(x) ((x) & (~BITS_P2P_OUI_TYPE)) #define BIT_GET_P2P_OUI_TYPE(x) \ (((x) >> BIT_SHIFT_P2P_OUI_TYPE) & BIT_MASK_P2P_OUI_TYPE) #define BIT_SET_P2P_OUI_TYPE(x, v) \ (BIT_CLEAR_P2P_OUI_TYPE(x) | BIT_P2P_OUI_TYPE(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_ASSOCIATED_BFMER0_INFO (Offset 0x06E4) */ #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0 0 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0 0xffffffffffffL #define BIT_R_WMAC_SOUNDING_RXADD_R0(x) \ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0) \ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) #define BITS_R_WMAC_SOUNDING_RXADD_R0 \ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0 \ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) #define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0(x) \ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0)) #define BIT_GET_R_WMAC_SOUNDING_RXADD_R0(x) \ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) & \ BIT_MASK_R_WMAC_SOUNDING_RXADD_R0) #define BIT_SET_R_WMAC_SOUNDING_RXADD_R0(x, v) \ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0(x) | \ BIT_R_WMAC_SOUNDING_RXADD_R0(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ASSOCIATED_BFMER0_INFO (Offset 0x06E4) */ #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1 0 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1 0xffffffffL #define BIT_R_WMAC_SOUNDING_RXADD_R0_V1(x) \ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1) \ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1) #define BITS_R_WMAC_SOUNDING_RXADD_R0_V1 \ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1 \ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1) #define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1(x) \ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1)) #define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1(x) \ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1) & \ BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1) #define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1(x, v) \ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1(x) | \ BIT_R_WMAC_SOUNDING_RXADD_R0_V1(v)) /* 2 REG_ASSOCIATED_BFMER0_INFO_H (Offset 0x06E8) */ #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1 0 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1 0xffff #define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1(x) \ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1) \ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1) #define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1 \ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1 \ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1) #define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1(x) \ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1)) #define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1(x) \ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1) & \ BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1) #define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1(x, v) \ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1(x) | \ BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_ASSOCIATED_BFMER1_INFO (Offset 0x06EC) */ #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1 0 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1 0xffffffffffffL #define BIT_R_WMAC_SOUNDING_RXADD_R1(x) \ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1) \ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) #define BITS_R_WMAC_SOUNDING_RXADD_R1 \ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1 \ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) #define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1(x) \ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1)) #define BIT_GET_R_WMAC_SOUNDING_RXADD_R1(x) \ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) & \ BIT_MASK_R_WMAC_SOUNDING_RXADD_R1) #define BIT_SET_R_WMAC_SOUNDING_RXADD_R1(x, v) \ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1(x) | \ BIT_R_WMAC_SOUNDING_RXADD_R1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ASSOCIATED_BFMER1_INFO (Offset 0x06EC) */ #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1 0 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1 0xffffffffL #define BIT_R_WMAC_SOUNDING_RXADD_R1_V1(x) \ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1) \ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1) #define BITS_R_WMAC_SOUNDING_RXADD_R1_V1 \ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1 \ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1) #define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1(x) \ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1)) #define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1(x) \ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1) & \ BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1) #define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1(x, v) \ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1(x) | \ BIT_R_WMAC_SOUNDING_RXADD_R1_V1(v)) /* 2 REG_ASSOCIATED_BFMER1_INFO_H (Offset 0x06F0) */ #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1 0 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1 0xffff #define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1(x) \ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1) \ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1) #define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1 \ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1 \ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1) #define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1(x) \ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1)) #define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1(x) \ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1) & \ BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1) #define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1(x, v) \ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1(x) | \ BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_TX_CSI_RPT_PARAM_BW20 (Offset 0x06F4) */ #define BIT_SHIFT_R_WMAC_BFINFO_20M_1 16 #define BIT_MASK_R_WMAC_BFINFO_20M_1 0xfff #define BIT_R_WMAC_BFINFO_20M_1(x) \ (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1) << BIT_SHIFT_R_WMAC_BFINFO_20M_1) #define BITS_R_WMAC_BFINFO_20M_1 \ (BIT_MASK_R_WMAC_BFINFO_20M_1 << BIT_SHIFT_R_WMAC_BFINFO_20M_1) #define BIT_CLEAR_R_WMAC_BFINFO_20M_1(x) ((x) & (~BITS_R_WMAC_BFINFO_20M_1)) #define BIT_GET_R_WMAC_BFINFO_20M_1(x) \ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1) & BIT_MASK_R_WMAC_BFINFO_20M_1) #define BIT_SET_R_WMAC_BFINFO_20M_1(x, v) \ (BIT_CLEAR_R_WMAC_BFINFO_20M_1(x) | BIT_R_WMAC_BFINFO_20M_1(v)) #define BIT_SHIFT_R_WMAC_BFINFO_20M_0 0 #define BIT_MASK_R_WMAC_BFINFO_20M_0 0xfff #define BIT_R_WMAC_BFINFO_20M_0(x) \ (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0) << BIT_SHIFT_R_WMAC_BFINFO_20M_0) #define BITS_R_WMAC_BFINFO_20M_0 \ (BIT_MASK_R_WMAC_BFINFO_20M_0 << BIT_SHIFT_R_WMAC_BFINFO_20M_0) #define BIT_CLEAR_R_WMAC_BFINFO_20M_0(x) ((x) & (~BITS_R_WMAC_BFINFO_20M_0)) #define BIT_GET_R_WMAC_BFINFO_20M_0(x) \ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0) & BIT_MASK_R_WMAC_BFINFO_20M_0) #define BIT_SET_R_WMAC_BFINFO_20M_0(x, v) \ (BIT_CLEAR_R_WMAC_BFINFO_20M_0(x) | BIT_R_WMAC_BFINFO_20M_0(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ #define BIT_SHIFT_R_WMAC_BFINFO_40M_1 13 #define BIT_MASK_R_WMAC_BFINFO_40M_1 0x7fff #define BIT_R_WMAC_BFINFO_40M_1(x) \ (((x) & BIT_MASK_R_WMAC_BFINFO_40M_1) << BIT_SHIFT_R_WMAC_BFINFO_40M_1) #define BITS_R_WMAC_BFINFO_40M_1 \ (BIT_MASK_R_WMAC_BFINFO_40M_1 << BIT_SHIFT_R_WMAC_BFINFO_40M_1) #define BIT_CLEAR_R_WMAC_BFINFO_40M_1(x) ((x) & (~BITS_R_WMAC_BFINFO_40M_1)) #define BIT_GET_R_WMAC_BFINFO_40M_1(x) \ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_40M_1) & BIT_MASK_R_WMAC_BFINFO_40M_1) #define BIT_SET_R_WMAC_BFINFO_40M_1(x, v) \ (BIT_CLEAR_R_WMAC_BFINFO_40M_1(x) | BIT_R_WMAC_BFINFO_40M_1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ #define BIT_SHIFT_WMAC_RESP_ANTD 12 #define BIT_MASK_WMAC_RESP_ANTD 0xf #define BIT_WMAC_RESP_ANTD(x) \ (((x) & BIT_MASK_WMAC_RESP_ANTD) << BIT_SHIFT_WMAC_RESP_ANTD) #define BITS_WMAC_RESP_ANTD \ (BIT_MASK_WMAC_RESP_ANTD << BIT_SHIFT_WMAC_RESP_ANTD) #define BIT_CLEAR_WMAC_RESP_ANTD(x) ((x) & (~BITS_WMAC_RESP_ANTD)) #define BIT_GET_WMAC_RESP_ANTD(x) \ (((x) >> BIT_SHIFT_WMAC_RESP_ANTD) & BIT_MASK_WMAC_RESP_ANTD) #define BIT_SET_WMAC_RESP_ANTD(x, v) \ (BIT_CLEAR_WMAC_RESP_ANTD(x) | BIT_WMAC_RESP_ANTD(v)) #define BIT_SHIFT_WMAC_RESP_ANTC 8 #define BIT_MASK_WMAC_RESP_ANTC 0xf #define BIT_WMAC_RESP_ANTC(x) \ (((x) & BIT_MASK_WMAC_RESP_ANTC) << BIT_SHIFT_WMAC_RESP_ANTC) #define BITS_WMAC_RESP_ANTC \ (BIT_MASK_WMAC_RESP_ANTC << BIT_SHIFT_WMAC_RESP_ANTC) #define BIT_CLEAR_WMAC_RESP_ANTC(x) ((x) & (~BITS_WMAC_RESP_ANTC)) #define BIT_GET_WMAC_RESP_ANTC(x) \ (((x) >> BIT_SHIFT_WMAC_RESP_ANTC) & BIT_MASK_WMAC_RESP_ANTC) #define BIT_SET_WMAC_RESP_ANTC(x, v) \ (BIT_CLEAR_WMAC_RESP_ANTC(x) | BIT_WMAC_RESP_ANTC(v)) #define BIT_SHIFT_WMAC_RESP_ANTB 4 #define BIT_MASK_WMAC_RESP_ANTB 0xf #define BIT_WMAC_RESP_ANTB(x) \ (((x) & BIT_MASK_WMAC_RESP_ANTB) << BIT_SHIFT_WMAC_RESP_ANTB) #define BITS_WMAC_RESP_ANTB \ (BIT_MASK_WMAC_RESP_ANTB << BIT_SHIFT_WMAC_RESP_ANTB) #define BIT_CLEAR_WMAC_RESP_ANTB(x) ((x) & (~BITS_WMAC_RESP_ANTB)) #define BIT_GET_WMAC_RESP_ANTB(x) \ (((x) >> BIT_SHIFT_WMAC_RESP_ANTB) & BIT_MASK_WMAC_RESP_ANTB) #define BIT_SET_WMAC_RESP_ANTB(x, v) \ (BIT_CLEAR_WMAC_RESP_ANTB(x) | BIT_WMAC_RESP_ANTB(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ #define BIT_SHIFT_R_WMAC_BFINFO_40M_0 0 #define BIT_MASK_R_WMAC_BFINFO_40M_0 0xfff #define BIT_R_WMAC_BFINFO_40M_0(x) \ (((x) & BIT_MASK_R_WMAC_BFINFO_40M_0) << BIT_SHIFT_R_WMAC_BFINFO_40M_0) #define BITS_R_WMAC_BFINFO_40M_0 \ (BIT_MASK_R_WMAC_BFINFO_40M_0 << BIT_SHIFT_R_WMAC_BFINFO_40M_0) #define BIT_CLEAR_R_WMAC_BFINFO_40M_0(x) ((x) & (~BITS_R_WMAC_BFINFO_40M_0)) #define BIT_GET_R_WMAC_BFINFO_40M_0(x) \ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_40M_0) & BIT_MASK_R_WMAC_BFINFO_40M_0) #define BIT_SET_R_WMAC_BFINFO_40M_0(x, v) \ (BIT_CLEAR_R_WMAC_BFINFO_40M_0(x) | BIT_R_WMAC_BFINFO_40M_0(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ #define BIT_SHIFT_WMAC_RESP_ANTCD 0 #define BIT_MASK_WMAC_RESP_ANTCD 0xf #define BIT_WMAC_RESP_ANTCD(x) \ (((x) & BIT_MASK_WMAC_RESP_ANTCD) << BIT_SHIFT_WMAC_RESP_ANTCD) #define BITS_WMAC_RESP_ANTCD \ (BIT_MASK_WMAC_RESP_ANTCD << BIT_SHIFT_WMAC_RESP_ANTCD) #define BIT_CLEAR_WMAC_RESP_ANTCD(x) ((x) & (~BITS_WMAC_RESP_ANTCD)) #define BIT_GET_WMAC_RESP_ANTCD(x) \ (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD) & BIT_MASK_WMAC_RESP_ANTCD) #define BIT_SET_WMAC_RESP_ANTCD(x, v) \ (BIT_CLEAR_WMAC_RESP_ANTCD(x) | BIT_WMAC_RESP_ANTCD(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ #define BIT_SHIFT_WMAC_RESP_ANTA 0 #define BIT_MASK_WMAC_RESP_ANTA 0xf #define BIT_WMAC_RESP_ANTA(x) \ (((x) & BIT_MASK_WMAC_RESP_ANTA) << BIT_SHIFT_WMAC_RESP_ANTA) #define BITS_WMAC_RESP_ANTA \ (BIT_MASK_WMAC_RESP_ANTA << BIT_SHIFT_WMAC_RESP_ANTA) #define BIT_CLEAR_WMAC_RESP_ANTA(x) ((x) & (~BITS_WMAC_RESP_ANTA)) #define BIT_GET_WMAC_RESP_ANTA(x) \ (((x) >> BIT_SHIFT_WMAC_RESP_ANTA) & BIT_MASK_WMAC_RESP_ANTA) #define BIT_SET_WMAC_RESP_ANTA(x, v) \ (BIT_CLEAR_WMAC_RESP_ANTA(x) | BIT_WMAC_RESP_ANTA(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_CSI_RRSR_V1 (Offset 0x06FC) */ #define BIT_WMAC_CSI_LDPC_EN BIT(29) #define BIT_WMAC_CSI_STBC_EN BIT(28) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TX_CSI_RPT_PARAM_BW80 (Offset 0x06FC) */ #define BIT_SHIFT_R_WMAC_BFINFO_80M_1 16 #define BIT_MASK_R_WMAC_BFINFO_80M_1 0xfff #define BIT_R_WMAC_BFINFO_80M_1(x) \ (((x) & BIT_MASK_R_WMAC_BFINFO_80M_1) << BIT_SHIFT_R_WMAC_BFINFO_80M_1) #define BITS_R_WMAC_BFINFO_80M_1 \ (BIT_MASK_R_WMAC_BFINFO_80M_1 << BIT_SHIFT_R_WMAC_BFINFO_80M_1) #define BIT_CLEAR_R_WMAC_BFINFO_80M_1(x) ((x) & (~BITS_R_WMAC_BFINFO_80M_1)) #define BIT_GET_R_WMAC_BFINFO_80M_1(x) \ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_80M_1) & BIT_MASK_R_WMAC_BFINFO_80M_1) #define BIT_SET_R_WMAC_BFINFO_80M_1(x, v) \ (BIT_CLEAR_R_WMAC_BFINFO_80M_1(x) | BIT_R_WMAC_BFINFO_80M_1(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_CSI_PTR (Offset 0x06FC) */ #define BIT_SHIFT_CSI_RADDR_LATCH_V2 16 #define BIT_MASK_CSI_RADDR_LATCH_V2 0xffff #define BIT_CSI_RADDR_LATCH_V2(x) \ (((x) & BIT_MASK_CSI_RADDR_LATCH_V2) << BIT_SHIFT_CSI_RADDR_LATCH_V2) #define BITS_CSI_RADDR_LATCH_V2 \ (BIT_MASK_CSI_RADDR_LATCH_V2 << BIT_SHIFT_CSI_RADDR_LATCH_V2) #define BIT_CLEAR_CSI_RADDR_LATCH_V2(x) ((x) & (~BITS_CSI_RADDR_LATCH_V2)) #define BIT_GET_CSI_RADDR_LATCH_V2(x) \ (((x) >> BIT_SHIFT_CSI_RADDR_LATCH_V2) & BIT_MASK_CSI_RADDR_LATCH_V2) #define BIT_SET_CSI_RADDR_LATCH_V2(x, v) \ (BIT_CLEAR_CSI_RADDR_LATCH_V2(x) | BIT_CSI_RADDR_LATCH_V2(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_CSI_RRSR_V1 (Offset 0x06FC) */ #define BIT_SHIFT_WMAC_CSI_RRSC_BITMAP 4 #define BIT_MASK_WMAC_CSI_RRSC_BITMAP 0xffffff #define BIT_WMAC_CSI_RRSC_BITMAP(x) \ (((x) & BIT_MASK_WMAC_CSI_RRSC_BITMAP) \ << BIT_SHIFT_WMAC_CSI_RRSC_BITMAP) #define BITS_WMAC_CSI_RRSC_BITMAP \ (BIT_MASK_WMAC_CSI_RRSC_BITMAP << BIT_SHIFT_WMAC_CSI_RRSC_BITMAP) #define BIT_CLEAR_WMAC_CSI_RRSC_BITMAP(x) ((x) & (~BITS_WMAC_CSI_RRSC_BITMAP)) #define BIT_GET_WMAC_CSI_RRSC_BITMAP(x) \ (((x) >> BIT_SHIFT_WMAC_CSI_RRSC_BITMAP) & \ BIT_MASK_WMAC_CSI_RRSC_BITMAP) #define BIT_SET_WMAC_CSI_RRSC_BITMAP(x, v) \ (BIT_CLEAR_WMAC_CSI_RRSC_BITMAP(x) | BIT_WMAC_CSI_RRSC_BITMAP(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_TX_CSI_RPT_PARAM_BW80 (Offset 0x06FC) */ #define BIT_SHIFT_R_WMAC_BFINFO_80M_0 0 #define BIT_MASK_R_WMAC_BFINFO_80M_0 0xfff #define BIT_R_WMAC_BFINFO_80M_0(x) \ (((x) & BIT_MASK_R_WMAC_BFINFO_80M_0) << BIT_SHIFT_R_WMAC_BFINFO_80M_0) #define BITS_R_WMAC_BFINFO_80M_0 \ (BIT_MASK_R_WMAC_BFINFO_80M_0 << BIT_SHIFT_R_WMAC_BFINFO_80M_0) #define BIT_CLEAR_R_WMAC_BFINFO_80M_0(x) ((x) & (~BITS_R_WMAC_BFINFO_80M_0)) #define BIT_GET_R_WMAC_BFINFO_80M_0(x) \ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_80M_0) & BIT_MASK_R_WMAC_BFINFO_80M_0) #define BIT_SET_R_WMAC_BFINFO_80M_0(x, v) \ (BIT_CLEAR_R_WMAC_BFINFO_80M_0(x) | BIT_R_WMAC_BFINFO_80M_0(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_CSI_RRSR_V1 (Offset 0x06FC) */ #define BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH 0 #define BIT_MASK_WMAC_CSI_OFDM_LEN_TH 0xf #define BIT_WMAC_CSI_OFDM_LEN_TH(x) \ (((x) & BIT_MASK_WMAC_CSI_OFDM_LEN_TH) \ << BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH) #define BITS_WMAC_CSI_OFDM_LEN_TH \ (BIT_MASK_WMAC_CSI_OFDM_LEN_TH << BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH) #define BIT_CLEAR_WMAC_CSI_OFDM_LEN_TH(x) ((x) & (~BITS_WMAC_CSI_OFDM_LEN_TH)) #define BIT_GET_WMAC_CSI_OFDM_LEN_TH(x) \ (((x) >> BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH) & \ BIT_MASK_WMAC_CSI_OFDM_LEN_TH) #define BIT_SET_WMAC_CSI_OFDM_LEN_TH(x, v) \ (BIT_CLEAR_WMAC_CSI_OFDM_LEN_TH(x) | BIT_WMAC_CSI_OFDM_LEN_TH(v)) #define BIT_SHIFT_CSI_PARA_RDY_DLYCNT 0 #define BIT_MASK_CSI_PARA_RDY_DLYCNT 0x1f #define BIT_CSI_PARA_RDY_DLYCNT(x) \ (((x) & BIT_MASK_CSI_PARA_RDY_DLYCNT) << BIT_SHIFT_CSI_PARA_RDY_DLYCNT) #define BITS_CSI_PARA_RDY_DLYCNT \ (BIT_MASK_CSI_PARA_RDY_DLYCNT << BIT_SHIFT_CSI_PARA_RDY_DLYCNT) #define BIT_CLEAR_CSI_PARA_RDY_DLYCNT(x) ((x) & (~BITS_CSI_PARA_RDY_DLYCNT)) #define BIT_GET_CSI_PARA_RDY_DLYCNT(x) \ (((x) >> BIT_SHIFT_CSI_PARA_RDY_DLYCNT) & BIT_MASK_CSI_PARA_RDY_DLYCNT) #define BIT_SET_CSI_PARA_RDY_DLYCNT(x, v) \ (BIT_CLEAR_CSI_PARA_RDY_DLYCNT(x) | BIT_CSI_PARA_RDY_DLYCNT(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_CSI_PTR (Offset 0x06FC) */ #define BIT_SHIFT_CSI_WADDR_LATCH_V2 0 #define BIT_MASK_CSI_WADDR_LATCH_V2 0xffff #define BIT_CSI_WADDR_LATCH_V2(x) \ (((x) & BIT_MASK_CSI_WADDR_LATCH_V2) << BIT_SHIFT_CSI_WADDR_LATCH_V2) #define BITS_CSI_WADDR_LATCH_V2 \ (BIT_MASK_CSI_WADDR_LATCH_V2 << BIT_SHIFT_CSI_WADDR_LATCH_V2) #define BIT_CLEAR_CSI_WADDR_LATCH_V2(x) ((x) & (~BITS_CSI_WADDR_LATCH_V2)) #define BIT_GET_CSI_WADDR_LATCH_V2(x) \ (((x) >> BIT_SHIFT_CSI_WADDR_LATCH_V2) & BIT_MASK_CSI_WADDR_LATCH_V2) #define BIT_SET_CSI_WADDR_LATCH_V2(x, v) \ (BIT_CLEAR_CSI_WADDR_LATCH_V2(x) | BIT_CSI_WADDR_LATCH_V2(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8881A_SUPPORT) /* 2 REG_MACID1 (Offset 0x0700) */ #define BIT_SHIFT_MACID1 0 #define BIT_MASK_MACID1 0xffffffffffffL #define BIT_MACID1(x) (((x) & BIT_MASK_MACID1) << BIT_SHIFT_MACID1) #define BITS_MACID1 (BIT_MASK_MACID1 << BIT_SHIFT_MACID1) #define BIT_CLEAR_MACID1(x) ((x) & (~BITS_MACID1)) #define BIT_GET_MACID1(x) (((x) >> BIT_SHIFT_MACID1) & BIT_MASK_MACID1) #define BIT_SET_MACID1(x, v) (BIT_CLEAR_MACID1(x) | BIT_MACID1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MACID1 (Offset 0x0700) */ #define BIT_SHIFT_MACID1_0 0 #define BIT_MASK_MACID1_0 0xffffffffL #define BIT_MACID1_0(x) (((x) & BIT_MASK_MACID1_0) << BIT_SHIFT_MACID1_0) #define BITS_MACID1_0 (BIT_MASK_MACID1_0 << BIT_SHIFT_MACID1_0) #define BIT_CLEAR_MACID1_0(x) ((x) & (~BITS_MACID1_0)) #define BIT_GET_MACID1_0(x) (((x) >> BIT_SHIFT_MACID1_0) & BIT_MASK_MACID1_0) #define BIT_SET_MACID1_0(x, v) (BIT_CLEAR_MACID1_0(x) | BIT_MACID1_0(v)) /* 2 REG_MACID1_1 (Offset 0x0704) */ #define BIT_SHIFT_MACID1_1 0 #define BIT_MASK_MACID1_1 0xffff #define BIT_MACID1_1(x) (((x) & BIT_MASK_MACID1_1) << BIT_SHIFT_MACID1_1) #define BITS_MACID1_1 (BIT_MASK_MACID1_1 << BIT_SHIFT_MACID1_1) #define BIT_CLEAR_MACID1_1(x) ((x) & (~BITS_MACID1_1)) #define BIT_GET_MACID1_1(x) (((x) >> BIT_SHIFT_MACID1_1) & BIT_MASK_MACID1_1) #define BIT_SET_MACID1_1(x, v) (BIT_CLEAR_MACID1_1(x) | BIT_MACID1_1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BSSID1 (Offset 0x0708) */ #define BIT_SHIFT_BSSID1 0 #define BIT_MASK_BSSID1 0xffffffffffffL #define BIT_BSSID1(x) (((x) & BIT_MASK_BSSID1) << BIT_SHIFT_BSSID1) #define BITS_BSSID1 (BIT_MASK_BSSID1 << BIT_SHIFT_BSSID1) #define BIT_CLEAR_BSSID1(x) ((x) & (~BITS_BSSID1)) #define BIT_GET_BSSID1(x) (((x) >> BIT_SHIFT_BSSID1) & BIT_MASK_BSSID1) #define BIT_SET_BSSID1(x, v) (BIT_CLEAR_BSSID1(x) | BIT_BSSID1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BSSID1 (Offset 0x0708) */ #define BIT_SHIFT_BSSID1_0 0 #define BIT_MASK_BSSID1_0 0xffffffffL #define BIT_BSSID1_0(x) (((x) & BIT_MASK_BSSID1_0) << BIT_SHIFT_BSSID1_0) #define BITS_BSSID1_0 (BIT_MASK_BSSID1_0 << BIT_SHIFT_BSSID1_0) #define BIT_CLEAR_BSSID1_0(x) ((x) & (~BITS_BSSID1_0)) #define BIT_GET_BSSID1_0(x) (((x) >> BIT_SHIFT_BSSID1_0) & BIT_MASK_BSSID1_0) #define BIT_SET_BSSID1_0(x, v) (BIT_CLEAR_BSSID1_0(x) | BIT_BSSID1_0(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PCIE_CFG_FORCE_LINK_L (Offset 0x0709) */ #define BIT_PCIE_CFG_FORCE_EN BIT(7) /* 2 REG_PCIE_CFG_FORCE_LINK_H (Offset 0x070A) */ #define BIT_PCIE_CFG_TRXACT_DIS_IDLE_TIMER BIT(6) #define BIT_SHIFT_PCIE_CFG_LINK_STATE 0 #define BIT_MASK_PCIE_CFG_LINK_STATE 0x3f #define BIT_PCIE_CFG_LINK_STATE(x) \ (((x) & BIT_MASK_PCIE_CFG_LINK_STATE) << BIT_SHIFT_PCIE_CFG_LINK_STATE) #define BITS_PCIE_CFG_LINK_STATE \ (BIT_MASK_PCIE_CFG_LINK_STATE << BIT_SHIFT_PCIE_CFG_LINK_STATE) #define BIT_CLEAR_PCIE_CFG_LINK_STATE(x) ((x) & (~BITS_PCIE_CFG_LINK_STATE)) #define BIT_GET_PCIE_CFG_LINK_STATE(x) \ (((x) >> BIT_SHIFT_PCIE_CFG_LINK_STATE) & BIT_MASK_PCIE_CFG_LINK_STATE) #define BIT_SET_PCIE_CFG_LINK_STATE(x, v) \ (BIT_CLEAR_PCIE_CFG_LINK_STATE(x) | BIT_PCIE_CFG_LINK_STATE(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BSSID1_1 (Offset 0x070C) */ #define BIT_SHIFT_BSSID1_1 0 #define BIT_MASK_BSSID1_1 0xffff #define BIT_BSSID1_1(x) (((x) & BIT_MASK_BSSID1_1) << BIT_SHIFT_BSSID1_1) #define BITS_BSSID1_1 (BIT_MASK_BSSID1_1 << BIT_SHIFT_BSSID1_1) #define BIT_CLEAR_BSSID1_1(x) ((x) & (~BITS_BSSID1_1)) #define BIT_GET_BSSID1_1(x) (((x) >> BIT_SHIFT_BSSID1_1) & BIT_MASK_BSSID1_1) #define BIT_SET_BSSID1_1(x, v) (BIT_CLEAR_BSSID1_1(x) | BIT_BSSID1_1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY (Offset 0x070C) */ #define BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY 0 #define BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY 0xff #define BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x) \ (((x) & BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY) \ << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY) #define BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY \ (BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY \ << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY) #define BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x) \ ((x) & (~BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY)) #define BIT_GET_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x) \ (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY) & \ BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY) #define BIT_SET_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x, v) \ (BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x) | \ BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY(v)) /* 2 REG_PCIE_CFG_CX_NFTS (Offset 0x070D) */ #define BIT_SHIFT_PCIE_CFG_CX_NFTS 0 #define BIT_MASK_PCIE_CFG_CX_NFTS 0xff #define BIT_PCIE_CFG_CX_NFTS(x) \ (((x) & BIT_MASK_PCIE_CFG_CX_NFTS) << BIT_SHIFT_PCIE_CFG_CX_NFTS) #define BITS_PCIE_CFG_CX_NFTS \ (BIT_MASK_PCIE_CFG_CX_NFTS << BIT_SHIFT_PCIE_CFG_CX_NFTS) #define BIT_CLEAR_PCIE_CFG_CX_NFTS(x) ((x) & (~BITS_PCIE_CFG_CX_NFTS)) #define BIT_GET_PCIE_CFG_CX_NFTS(x) \ (((x) >> BIT_SHIFT_PCIE_CFG_CX_NFTS) & BIT_MASK_PCIE_CFG_CX_NFTS) #define BIT_SET_PCIE_CFG_CX_NFTS(x, v) \ (BIT_CLEAR_PCIE_CFG_CX_NFTS(x) | BIT_PCIE_CFG_CX_NFTS(v)) /* 2 REG_PCIE_CFG_DEFAULT_ENTR_LATENCY (Offset 0x070F) */ #define BIT_PCIE_CFG_REAL_EN_L0S BIT(7) #define BIT_PCIE_CFG_ENTER_ASPM BIT(6) #define BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY 3 #define BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY 0x7 #define BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x) \ (((x) & BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) \ << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) #define BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY \ (BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY \ << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) #define BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x) \ ((x) & (~BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY)) #define BIT_GET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x) \ (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) & \ BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) #define BIT_SET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x, v) \ (BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x) | \ BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(v)) #define BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY 0 #define BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY 0x7 #define BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x) \ (((x) & BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) \ << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) #define BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY \ (BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY \ << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) #define BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x) \ ((x) & (~BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY)) #define BIT_GET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x) \ (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) & \ BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) #define BIT_SET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x, v) \ (BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x) | \ BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BCN_PSR_RPT1 (Offset 0x0710) */ #define BIT_TXUSER_ID1 BIT(25) #define BIT_SHIFT_DTIM_CNT1 24 #define BIT_MASK_DTIM_CNT1 0xff #define BIT_DTIM_CNT1(x) (((x) & BIT_MASK_DTIM_CNT1) << BIT_SHIFT_DTIM_CNT1) #define BITS_DTIM_CNT1 (BIT_MASK_DTIM_CNT1 << BIT_SHIFT_DTIM_CNT1) #define BIT_CLEAR_DTIM_CNT1(x) ((x) & (~BITS_DTIM_CNT1)) #define BIT_GET_DTIM_CNT1(x) (((x) >> BIT_SHIFT_DTIM_CNT1) & BIT_MASK_DTIM_CNT1) #define BIT_SET_DTIM_CNT1(x, v) (BIT_CLEAR_DTIM_CNT1(x) | BIT_DTIM_CNT1(v)) #define BIT_SHIFT_DTIM_PERIOD1 16 #define BIT_MASK_DTIM_PERIOD1 0xff #define BIT_DTIM_PERIOD1(x) \ (((x) & BIT_MASK_DTIM_PERIOD1) << BIT_SHIFT_DTIM_PERIOD1) #define BITS_DTIM_PERIOD1 (BIT_MASK_DTIM_PERIOD1 << BIT_SHIFT_DTIM_PERIOD1) #define BIT_CLEAR_DTIM_PERIOD1(x) ((x) & (~BITS_DTIM_PERIOD1)) #define BIT_GET_DTIM_PERIOD1(x) \ (((x) >> BIT_SHIFT_DTIM_PERIOD1) & BIT_MASK_DTIM_PERIOD1) #define BIT_SET_DTIM_PERIOD1(x, v) \ (BIT_CLEAR_DTIM_PERIOD1(x) | BIT_DTIM_PERIOD1(v)) #define BIT_SHIFT_AID1 16 #define BIT_MASK_AID1 0x1ff #define BIT_AID1(x) (((x) & BIT_MASK_AID1) << BIT_SHIFT_AID1) #define BITS_AID1 (BIT_MASK_AID1 << BIT_SHIFT_AID1) #define BIT_CLEAR_AID1(x) ((x) & (~BITS_AID1)) #define BIT_GET_AID1(x) (((x) >> BIT_SHIFT_AID1) & BIT_MASK_AID1) #define BIT_SET_AID1(x, v) (BIT_CLEAR_AID1(x) | BIT_AID1(v)) #define BIT_DTIM1 BIT(15) #define BIT_TIM1 BIT(14) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_BCN_PSR_RPT1 (Offset 0x0710) */ #define BIT_BCN_VALID_V2 BIT(13) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BCN_PSR_RPT1 (Offset 0x0710) */ #define BIT_TXUSER_ID0 BIT(9) #define BIT_SHIFT_PS_AID_1 0 #define BIT_MASK_PS_AID_1 0x7ff #define BIT_PS_AID_1(x) (((x) & BIT_MASK_PS_AID_1) << BIT_SHIFT_PS_AID_1) #define BITS_PS_AID_1 (BIT_MASK_PS_AID_1 << BIT_SHIFT_PS_AID_1) #define BIT_CLEAR_PS_AID_1(x) ((x) & (~BITS_PS_AID_1)) #define BIT_GET_PS_AID_1(x) (((x) >> BIT_SHIFT_PS_AID_1) & BIT_MASK_PS_AID_1) #define BIT_SET_PS_AID_1(x, v) (BIT_CLEAR_PS_AID_1(x) | BIT_PS_AID_1(v)) #define BIT_SHIFT_AID0 0 #define BIT_MASK_AID0 0x1ff #define BIT_AID0(x) (((x) & BIT_MASK_AID0) << BIT_SHIFT_AID0) #define BITS_AID0 (BIT_MASK_AID0 << BIT_SHIFT_AID0) #define BIT_CLEAR_AID0(x) ((x) & (~BITS_AID0)) #define BIT_GET_AID0(x) (((x) >> BIT_SHIFT_AID0) & BIT_MASK_AID0) #define BIT_SET_AID0(x, v) (BIT_CLEAR_AID0(x) | BIT_AID0(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PCIE_CFG_L1_MISC_SEL (Offset 0x0711) */ #define BIT_PCIE_CFG_L1_RIDLE_SEL BIT(6) #define BIT_PCIE_CFG_L1_TIMEOUT_SEL BIT(5) #define BIT_PCIE_CFG_L1_EIDLE_SEL BIT(4) #define BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE 0 #define BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE 0xf #define BIT_PCIE_CFG_DEFAULT_LINK_RATE(x) \ (((x) & BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE) \ << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE) #define BITS_PCIE_CFG_DEFAULT_LINK_RATE \ (BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE \ << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE) #define BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE(x) \ ((x) & (~BITS_PCIE_CFG_DEFAULT_LINK_RATE)) #define BIT_GET_PCIE_CFG_DEFAULT_LINK_RATE(x) \ (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE) & \ BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE) #define BIT_SET_PCIE_CFG_DEFAULT_LINK_RATE(x, v) \ (BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE(x) | \ BIT_PCIE_CFG_DEFAULT_LINK_RATE(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_ASSOCIATED_BFMEE_SEL (Offset 0x0714) */ #define BIT_SHIFT_RD_BF_SEL 29 #define BIT_MASK_RD_BF_SEL 0x7 #define BIT_RD_BF_SEL(x) (((x) & BIT_MASK_RD_BF_SEL) << BIT_SHIFT_RD_BF_SEL) #define BITS_RD_BF_SEL (BIT_MASK_RD_BF_SEL << BIT_SHIFT_RD_BF_SEL) #define BIT_CLEAR_RD_BF_SEL(x) ((x) & (~BITS_RD_BF_SEL)) #define BIT_GET_RD_BF_SEL(x) (((x) >> BIT_SHIFT_RD_BF_SEL) & BIT_MASK_RD_BF_SEL) #define BIT_SET_RD_BF_SEL(x, v) (BIT_CLEAR_RD_BF_SEL(x) | BIT_RD_BF_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_SHIFT_NDP_RX_STANDBY_TIMER 24 #define BIT_MASK_NDP_RX_STANDBY_TIMER 0xff #define BIT_NDP_RX_STANDBY_TIMER(x) \ (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER) \ << BIT_SHIFT_NDP_RX_STANDBY_TIMER) #define BITS_NDP_RX_STANDBY_TIMER \ (BIT_MASK_NDP_RX_STANDBY_TIMER << BIT_SHIFT_NDP_RX_STANDBY_TIMER) #define BIT_CLEAR_NDP_RX_STANDBY_TIMER(x) ((x) & (~BITS_NDP_RX_STANDBY_TIMER)) #define BIT_GET_NDP_RX_STANDBY_TIMER(x) \ (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER) & \ BIT_MASK_NDP_RX_STANDBY_TIMER) #define BIT_SET_NDP_RX_STANDBY_TIMER(x, v) \ (BIT_CLEAR_NDP_RX_STANDBY_TIMER(x) | BIT_NDP_RX_STANDBY_TIMER(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_WMAC_CHK_RPTPOLL_A2_DIS BIT(23) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_R_WMAC_CHK_RPTPOLL_A2_DIS BIT(23) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_WMAC_CHK_UCNDPA_A2_DIS BIT(22) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_R_WMAC_CHK_UCNDPA_A2_DIS BIT(22) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_SHIFT_CSI_RPT_OFFSET_HT 16 #define BIT_MASK_CSI_RPT_OFFSET_HT 0xff #define BIT_CSI_RPT_OFFSET_HT(x) \ (((x) & BIT_MASK_CSI_RPT_OFFSET_HT) << BIT_SHIFT_CSI_RPT_OFFSET_HT) #define BITS_CSI_RPT_OFFSET_HT \ (BIT_MASK_CSI_RPT_OFFSET_HT << BIT_SHIFT_CSI_RPT_OFFSET_HT) #define BIT_CLEAR_CSI_RPT_OFFSET_HT(x) ((x) & (~BITS_CSI_RPT_OFFSET_HT)) #define BIT_GET_CSI_RPT_OFFSET_HT(x) \ (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT) & BIT_MASK_CSI_RPT_OFFSET_HT) #define BIT_SET_CSI_RPT_OFFSET_HT(x, v) \ (BIT_CLEAR_CSI_RPT_OFFSET_HT(x) | BIT_CSI_RPT_OFFSET_HT(v)) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_SHIFT_CSI_RPT_OFFSET_HT_V1 16 #define BIT_MASK_CSI_RPT_OFFSET_HT_V1 0x3f #define BIT_CSI_RPT_OFFSET_HT_V1(x) \ (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_V1) \ << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1) #define BITS_CSI_RPT_OFFSET_HT_V1 \ (BIT_MASK_CSI_RPT_OFFSET_HT_V1 << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1) #define BIT_CLEAR_CSI_RPT_OFFSET_HT_V1(x) ((x) & (~BITS_CSI_RPT_OFFSET_HT_V1)) #define BIT_GET_CSI_RPT_OFFSET_HT_V1(x) \ (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_V1) & \ BIT_MASK_CSI_RPT_OFFSET_HT_V1) #define BIT_SET_CSI_RPT_OFFSET_HT_V1(x, v) \ (BIT_CLEAR_CSI_RPT_OFFSET_HT_V1(x) | BIT_CSI_RPT_OFFSET_HT_V1(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_WMAC_OFFSET_RPTPOLL_EN BIT(15) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL BIT(15) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_R_WMAC_OFFSET_RPTPOLL_EN BIT(15) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_WMAC_CSI_CHKSUM_DIS BIT(14) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_R_WMAC_CSI_CHKSUM_DIS BIT(14) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_NDPVLD_POS_RST_FFPTR_DIS BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_SHIFT_CSI_RPT_OFFSET_VHT 8 #define BIT_MASK_CSI_RPT_OFFSET_VHT 0xff #define BIT_CSI_RPT_OFFSET_VHT(x) \ (((x) & BIT_MASK_CSI_RPT_OFFSET_VHT) << BIT_SHIFT_CSI_RPT_OFFSET_VHT) #define BITS_CSI_RPT_OFFSET_VHT \ (BIT_MASK_CSI_RPT_OFFSET_VHT << BIT_SHIFT_CSI_RPT_OFFSET_VHT) #define BIT_CLEAR_CSI_RPT_OFFSET_VHT(x) ((x) & (~BITS_CSI_RPT_OFFSET_VHT)) #define BIT_GET_CSI_RPT_OFFSET_VHT(x) \ (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT) & BIT_MASK_CSI_RPT_OFFSET_VHT) #define BIT_SET_CSI_RPT_OFFSET_VHT(x, v) \ (BIT_CLEAR_CSI_RPT_OFFSET_VHT(x) | BIT_CSI_RPT_OFFSET_VHT(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1 8 #define BIT_MASK_CSI_RPT_OFFSET_VHT_V1 0x3f #define BIT_CSI_RPT_OFFSET_VHT_V1(x) \ (((x) & BIT_MASK_CSI_RPT_OFFSET_VHT_V1) \ << BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1) #define BITS_CSI_RPT_OFFSET_VHT_V1 \ (BIT_MASK_CSI_RPT_OFFSET_VHT_V1 << BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1) #define BIT_CLEAR_CSI_RPT_OFFSET_VHT_V1(x) ((x) & (~BITS_CSI_RPT_OFFSET_VHT_V1)) #define BIT_GET_CSI_RPT_OFFSET_VHT_V1(x) \ (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1) & \ BIT_MASK_CSI_RPT_OFFSET_VHT_V1) #define BIT_SET_CSI_RPT_OFFSET_VHT_V1(x, v) \ (BIT_CLEAR_CSI_RPT_OFFSET_VHT_V1(x) | BIT_CSI_RPT_OFFSET_VHT_V1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_SHIFT_R_WMAC_VHT_CATEGORY 8 #define BIT_MASK_R_WMAC_VHT_CATEGORY 0xff #define BIT_R_WMAC_VHT_CATEGORY(x) \ (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY) << BIT_SHIFT_R_WMAC_VHT_CATEGORY) #define BITS_R_WMAC_VHT_CATEGORY \ (BIT_MASK_R_WMAC_VHT_CATEGORY << BIT_SHIFT_R_WMAC_VHT_CATEGORY) #define BIT_CLEAR_R_WMAC_VHT_CATEGORY(x) ((x) & (~BITS_R_WMAC_VHT_CATEGORY)) #define BIT_GET_R_WMAC_VHT_CATEGORY(x) \ (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY) & BIT_MASK_R_WMAC_VHT_CATEGORY) #define BIT_SET_R_WMAC_VHT_CATEGORY(x, v) \ (BIT_CLEAR_R_WMAC_VHT_CATEGORY(x) | BIT_R_WMAC_VHT_CATEGORY(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1 8 #define BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1 0x3f #define BIT_R_CSI_RPT_OFFSET_VHT_V1(x) \ (((x) & BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1) \ << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1) #define BITS_R_CSI_RPT_OFFSET_VHT_V1 \ (BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1 << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1) #define BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1(x) \ ((x) & (~BITS_R_CSI_RPT_OFFSET_VHT_V1)) #define BIT_GET_R_CSI_RPT_OFFSET_VHT_V1(x) \ (((x) >> BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1) & \ BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1) #define BIT_SET_R_CSI_RPT_OFFSET_VHT_V1(x, v) \ (BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1(x) | BIT_R_CSI_RPT_OFFSET_VHT_V1(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1 8 #define BIT_MASK_R_WMAC_VHT_CATEGORY_V1 0x3f #define BIT_R_WMAC_VHT_CATEGORY_V1(x) \ (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_V1) \ << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1) #define BITS_R_WMAC_VHT_CATEGORY_V1 \ (BIT_MASK_R_WMAC_VHT_CATEGORY_V1 << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1) #define BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1(x) \ ((x) & (~BITS_R_WMAC_VHT_CATEGORY_V1)) #define BIT_GET_R_WMAC_VHT_CATEGORY_V1(x) \ (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1) & \ BIT_MASK_R_WMAC_VHT_CATEGORY_V1) #define BIT_SET_R_WMAC_VHT_CATEGORY_V1(x, v) \ (BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1(x) | BIT_R_WMAC_VHT_CATEGORY_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_R_WMAC_USE_NSTS BIT(7) #define BIT_R_DISABLE_CHECK_VHTSIGB_CRC BIT(6) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF (Offset 0x0718) */ #define BIT_PCIE_CFG_REAL_PTM_ENABLE BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_R_DISABLE_CHECK_VHTSIGA_CRC BIT(5) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF (Offset 0x0718) */ #define BIT_PCIE_CFG_REAL_EN_L1SUB BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ #define BIT_R_WMAC_BFPARAM_SEL BIT(4) #define BIT_R_WMAC_CSISEQ_SEL BIT(3) #define BIT_R_WMAC_CSI_WITHHTC_EN BIT(2) #define BIT_R_WMAC_HT_NDPA_EN BIT(1) #define BIT_R_WMAC_VHT_NDPA_EN BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF (Offset 0x0718) */ #define BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM 0 #define BIT_MASK_PCIE_CFG_MAX_FUNC_NUM 0x7 #define BIT_PCIE_CFG_MAX_FUNC_NUM(x) \ (((x) & BIT_MASK_PCIE_CFG_MAX_FUNC_NUM) \ << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM) #define BITS_PCIE_CFG_MAX_FUNC_NUM \ (BIT_MASK_PCIE_CFG_MAX_FUNC_NUM << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM) #define BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM(x) ((x) & (~BITS_PCIE_CFG_MAX_FUNC_NUM)) #define BIT_GET_PCIE_CFG_MAX_FUNC_NUM(x) \ (((x) >> BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM) & \ BIT_MASK_PCIE_CFG_MAX_FUNC_NUM) #define BIT_SET_PCIE_CFG_MAX_FUNC_NUM(x, v) \ (BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM(x) | BIT_PCIE_CFG_MAX_FUNC_NUM(v)) /* 2 REG_PCIE_CFG_FORCE_CLKREQ_N_PAD (Offset 0x0719) */ #define BIT_PCIE_CFG_REAL_EN_64BITS BIT(5) #define BIT_PCIE_CFG_REAL_EN_CLKREQ BIT(4) #define BIT_PCIE_CFG_REAL_EN_L1 BIT(3) #define BIT_PCIE_CFG_WAKE_N_EN BIT(2) #define BIT_PCIE_CFG_BYPASS_LTR_OPTION BIT(1) #define BIT_PCIE_CFG_FORCE_CLKREQ_N_PAD BIT(0) /* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY (Offset 0x071A) */ #define BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK 0 #define BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK 0xff #define BIT_PCIE_CFG_TIMER_MOD_ACK_NAK(x) \ (((x) & BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK) \ << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK) #define BITS_PCIE_CFG_TIMER_MOD_ACK_NAK \ (BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK \ << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK) #define BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK(x) \ ((x) & (~BITS_PCIE_CFG_TIMER_MOD_ACK_NAK)) #define BIT_GET_PCIE_CFG_TIMER_MOD_ACK_NAK(x) \ (((x) >> BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK) & \ BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK) #define BIT_SET_PCIE_CFG_TIMER_MOD_ACK_NAK(x, v) \ (BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK(x) | \ BIT_PCIE_CFG_TIMER_MOD_ACK_NAK(v)) /* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG (Offset 0x071B) */ #define BIT_PCIE_CFG_BYPASS_L1_SUBSTATE_OPTION BIT(7) #define BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR 5 #define BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR 0x3 #define BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x) \ (((x) & BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR) \ << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR) #define BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR \ (BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR \ << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR) #define BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x) \ ((x) & (~BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR)) #define BIT_GET_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x) \ (((x) >> BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR) & \ BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR) #define BIT_SET_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x, v) \ (BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x) | \ BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR(v)) #define BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER 0 #define BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER 0x1f #define BIT_PCIE_CFG_UPDATE_FREQ_TIMER(x) \ (((x) & BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER) \ << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER) #define BITS_PCIE_CFG_UPDATE_FREQ_TIMER \ (BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER \ << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER) #define BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER(x) \ ((x) & (~BITS_PCIE_CFG_UPDATE_FREQ_TIMER)) #define BIT_GET_PCIE_CFG_UPDATE_FREQ_TIMER(x) \ (((x) >> BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER) & \ BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER) #define BIT_SET_PCIE_CFG_UPDATE_FREQ_TIMER(x, v) \ (BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER(x) | \ BIT_PCIE_CFG_UPDATE_FREQ_TIMER(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */ #define BIT_WRITE_ENABLE BIT(31) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */ #define BIT_WMAC_CHECK_SOUNDING_SEQ BIT(30) #define BIT_ANTTRN_SWITCH BIT(19) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */ #define BIT_WRITE_USERID BIT(12) #define BIT_SHIFT_WRITE_BW 10 #define BIT_MASK_WRITE_BW 0x3 #define BIT_WRITE_BW(x) (((x) & BIT_MASK_WRITE_BW) << BIT_SHIFT_WRITE_BW) #define BITS_WRITE_BW (BIT_MASK_WRITE_BW << BIT_SHIFT_WRITE_BW) #define BIT_CLEAR_WRITE_BW(x) ((x) & (~BITS_WRITE_BW)) #define BIT_GET_WRITE_BW(x) (((x) >> BIT_SHIFT_WRITE_BW) & BIT_MASK_WRITE_BW) #define BIT_SET_WRITE_BW(x, v) (BIT_CLEAR_WRITE_BW(x) | BIT_WRITE_BW(v)) #define BIT_SHIFT_WRITE_CB 8 #define BIT_MASK_WRITE_CB 0x3 #define BIT_WRITE_CB(x) (((x) & BIT_MASK_WRITE_CB) << BIT_SHIFT_WRITE_CB) #define BITS_WRITE_CB (BIT_MASK_WRITE_CB << BIT_SHIFT_WRITE_CB) #define BIT_CLEAR_WRITE_CB(x) ((x) & (~BITS_WRITE_CB)) #define BIT_GET_WRITE_CB(x) (((x) >> BIT_SHIFT_WRITE_CB) & BIT_MASK_WRITE_CB) #define BIT_SET_WRITE_CB(x, v) (BIT_CLEAR_WRITE_CB(x) | BIT_WRITE_CB(v)) #define BIT_SHIFT_WRITE_GROUPING 6 #define BIT_MASK_WRITE_GROUPING 0x3 #define BIT_WRITE_GROUPING(x) \ (((x) & BIT_MASK_WRITE_GROUPING) << BIT_SHIFT_WRITE_GROUPING) #define BITS_WRITE_GROUPING \ (BIT_MASK_WRITE_GROUPING << BIT_SHIFT_WRITE_GROUPING) #define BIT_CLEAR_WRITE_GROUPING(x) ((x) & (~BITS_WRITE_GROUPING)) #define BIT_GET_WRITE_GROUPING(x) \ (((x) >> BIT_SHIFT_WRITE_GROUPING) & BIT_MASK_WRITE_GROUPING) #define BIT_SET_WRITE_GROUPING(x, v) \ (BIT_CLEAR_WRITE_GROUPING(x) | BIT_WRITE_GROUPING(v)) #define BIT_SHIFT_WRITE_NR 3 #define BIT_MASK_WRITE_NR 0x7 #define BIT_WRITE_NR(x) (((x) & BIT_MASK_WRITE_NR) << BIT_SHIFT_WRITE_NR) #define BITS_WRITE_NR (BIT_MASK_WRITE_NR << BIT_SHIFT_WRITE_NR) #define BIT_CLEAR_WRITE_NR(x) ((x) & (~BITS_WRITE_NR)) #define BIT_GET_WRITE_NR(x) (((x) >> BIT_SHIFT_WRITE_NR) & BIT_MASK_WRITE_NR) #define BIT_SET_WRITE_NR(x, v) (BIT_CLEAR_WRITE_NR(x) | BIT_WRITE_NR(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */ #define BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD 1 #define BIT_MASK_VHTHT_MIMO_CTRL_FIELD 0xffffff #define BIT_VHTHT_MIMO_CTRL_FIELD(x) \ (((x) & BIT_MASK_VHTHT_MIMO_CTRL_FIELD) \ << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD) #define BITS_VHTHT_MIMO_CTRL_FIELD \ (BIT_MASK_VHTHT_MIMO_CTRL_FIELD << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD) #define BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD(x) ((x) & (~BITS_VHTHT_MIMO_CTRL_FIELD)) #define BIT_GET_VHTHT_MIMO_CTRL_FIELD(x) \ (((x) >> BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD) & \ BIT_MASK_VHTHT_MIMO_CTRL_FIELD) #define BIT_SET_VHTHT_MIMO_CTRL_FIELD(x, v) \ (BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD(x) | BIT_VHTHT_MIMO_CTRL_FIELD(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */ #define BIT_SHIFT_WRITE_NC 0 #define BIT_MASK_WRITE_NC 0x7 #define BIT_WRITE_NC(x) (((x) & BIT_MASK_WRITE_NC) << BIT_SHIFT_WRITE_NC) #define BITS_WRITE_NC (BIT_MASK_WRITE_NC << BIT_SHIFT_WRITE_NC) #define BIT_CLEAR_WRITE_NC(x) ((x) & (~BITS_WRITE_NC)) #define BIT_GET_WRITE_NC(x) (((x) >> BIT_SHIFT_WRITE_NC) & BIT_MASK_WRITE_NC) #define BIT_SET_WRITE_NC(x, v) (BIT_CLEAR_WRITE_NC(x) | BIT_WRITE_NC(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */ #define BIT_CSI_INTERRUPT_STATUS BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_L (Offset 0x071C) */ #define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L 0 #define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L 0xff #define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L(x) \ (((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L) \ << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L) #define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L \ (BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L \ << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L) #define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L(x) \ ((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L)) #define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_L(x) \ (((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L) & \ BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L) #define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_L(x, v) \ (BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L(x) | \ BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L(v)) /* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_H (Offset 0x071D) */ #define BIT_PCIE_CFG_DISABLE_FC_WATCHDOG_TIMER BIT(7) #define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H 0 #define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H 0x7 #define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H(x) \ (((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H) \ << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H) #define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H \ (BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H \ << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H) #define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H(x) \ ((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H)) #define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_H(x) \ (((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H) & \ BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H) #define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_H(x, v) \ (BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H(x) | \ BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_NS_ARP_CTRL (Offset 0x0720) */ #define BIT_R_WMAC_NSARP_RSPEN BIT(15) #define BIT_R_WMAC_NSARP_RARP BIT(9) #define BIT_R_WMAC_NSARP_RIPV6 BIT(8) #define BIT_SHIFT_R_WMAC_NSARP_MODEN 6 #define BIT_MASK_R_WMAC_NSARP_MODEN 0x3 #define BIT_R_WMAC_NSARP_MODEN(x) \ (((x) & BIT_MASK_R_WMAC_NSARP_MODEN) << BIT_SHIFT_R_WMAC_NSARP_MODEN) #define BITS_R_WMAC_NSARP_MODEN \ (BIT_MASK_R_WMAC_NSARP_MODEN << BIT_SHIFT_R_WMAC_NSARP_MODEN) #define BIT_CLEAR_R_WMAC_NSARP_MODEN(x) ((x) & (~BITS_R_WMAC_NSARP_MODEN)) #define BIT_GET_R_WMAC_NSARP_MODEN(x) \ (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN) & BIT_MASK_R_WMAC_NSARP_MODEN) #define BIT_SET_R_WMAC_NSARP_MODEN(x, v) \ (BIT_CLEAR_R_WMAC_NSARP_MODEN(x) | BIT_R_WMAC_NSARP_MODEN(v)) #define BIT_SHIFT_R_WMAC_NSARP_RSPFTP 4 #define BIT_MASK_R_WMAC_NSARP_RSPFTP 0x3 #define BIT_R_WMAC_NSARP_RSPFTP(x) \ (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP) #define BITS_R_WMAC_NSARP_RSPFTP \ (BIT_MASK_R_WMAC_NSARP_RSPFTP << BIT_SHIFT_R_WMAC_NSARP_RSPFTP) #define BIT_CLEAR_R_WMAC_NSARP_RSPFTP(x) ((x) & (~BITS_R_WMAC_NSARP_RSPFTP)) #define BIT_GET_R_WMAC_NSARP_RSPFTP(x) \ (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP) & BIT_MASK_R_WMAC_NSARP_RSPFTP) #define BIT_SET_R_WMAC_NSARP_RSPFTP(x, v) \ (BIT_CLEAR_R_WMAC_NSARP_RSPFTP(x) | BIT_R_WMAC_NSARP_RSPFTP(v)) #define BIT_SHIFT_R_WMAC_NSARP_RSPSEC 0 #define BIT_MASK_R_WMAC_NSARP_RSPSEC 0xf #define BIT_R_WMAC_NSARP_RSPSEC(x) \ (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC) #define BITS_R_WMAC_NSARP_RSPSEC \ (BIT_MASK_R_WMAC_NSARP_RSPSEC << BIT_SHIFT_R_WMAC_NSARP_RSPSEC) #define BIT_CLEAR_R_WMAC_NSARP_RSPSEC(x) ((x) & (~BITS_R_WMAC_NSARP_RSPSEC)) #define BIT_GET_R_WMAC_NSARP_RSPSEC(x) \ (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC) & BIT_MASK_R_WMAC_NSARP_RSPSEC) #define BIT_SET_R_WMAC_NSARP_RSPSEC(x, v) \ (BIT_CLEAR_R_WMAC_NSARP_RSPSEC(x) | BIT_R_WMAC_NSARP_RSPSEC(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_NS_ARP_INFO (Offset 0x0724) */ #define BIT_REQ_IS_MCNS BIT(23) #define BIT_REQ_IS_UCNS BIT(22) #define BIT_REQ_IS_USNS BIT(21) #define BIT_REQ_IS_ARP BIT(20) #define BIT_EXPRSP_MH_WITHQC BIT(19) #define BIT_SHIFT_EXPRSP_SECTYPE 16 #define BIT_MASK_EXPRSP_SECTYPE 0x7 #define BIT_EXPRSP_SECTYPE(x) \ (((x) & BIT_MASK_EXPRSP_SECTYPE) << BIT_SHIFT_EXPRSP_SECTYPE) #define BITS_EXPRSP_SECTYPE \ (BIT_MASK_EXPRSP_SECTYPE << BIT_SHIFT_EXPRSP_SECTYPE) #define BIT_CLEAR_EXPRSP_SECTYPE(x) ((x) & (~BITS_EXPRSP_SECTYPE)) #define BIT_GET_EXPRSP_SECTYPE(x) \ (((x) >> BIT_SHIFT_EXPRSP_SECTYPE) & BIT_MASK_EXPRSP_SECTYPE) #define BIT_SET_EXPRSP_SECTYPE(x, v) \ (BIT_CLEAR_EXPRSP_SECTYPE(x) | BIT_EXPRSP_SECTYPE(v)) #define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0 8 #define BIT_MASK_EXPRSP_CHKSM_7_TO_0 0xff #define BIT_EXPRSP_CHKSM_7_TO_0(x) \ (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) #define BITS_EXPRSP_CHKSM_7_TO_0 \ (BIT_MASK_EXPRSP_CHKSM_7_TO_0 << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) #define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0(x) ((x) & (~BITS_EXPRSP_CHKSM_7_TO_0)) #define BIT_GET_EXPRSP_CHKSM_7_TO_0(x) \ (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) #define BIT_SET_EXPRSP_CHKSM_7_TO_0(x, v) \ (BIT_CLEAR_EXPRSP_CHKSM_7_TO_0(x) | BIT_EXPRSP_CHKSM_7_TO_0(v)) #define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8 0 #define BIT_MASK_EXPRSP_CHKSM_15_TO_8 0xff #define BIT_EXPRSP_CHKSM_15_TO_8(x) \ (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8) \ << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) #define BITS_EXPRSP_CHKSM_15_TO_8 \ (BIT_MASK_EXPRSP_CHKSM_15_TO_8 << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) #define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8(x) ((x) & (~BITS_EXPRSP_CHKSM_15_TO_8)) #define BIT_GET_EXPRSP_CHKSM_15_TO_8(x) \ (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) & \ BIT_MASK_EXPRSP_CHKSM_15_TO_8) #define BIT_SET_EXPRSP_CHKSM_15_TO_8(x, v) \ (BIT_CLEAR_EXPRSP_CHKSM_15_TO_8(x) | BIT_EXPRSP_CHKSM_15_TO_8(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PCIE_CFG_L1_UNIT_SEL (Offset 0x0724) */ #define BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL 0 #define BIT_MASK_PCIE_CFG_L1_UNIT_SEL 0xff #define BIT_PCIE_CFG_L1_UNIT_SEL(x) \ (((x) & BIT_MASK_PCIE_CFG_L1_UNIT_SEL) \ << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL) #define BITS_PCIE_CFG_L1_UNIT_SEL \ (BIT_MASK_PCIE_CFG_L1_UNIT_SEL << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL) #define BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL(x) ((x) & (~BITS_PCIE_CFG_L1_UNIT_SEL)) #define BIT_GET_PCIE_CFG_L1_UNIT_SEL(x) \ (((x) >> BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL) & \ BIT_MASK_PCIE_CFG_L1_UNIT_SEL) #define BIT_SET_PCIE_CFG_L1_UNIT_SEL(x, v) \ (BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL(x) | BIT_PCIE_CFG_L1_UNIT_SEL(v)) /* 2 REG_PCIE_CFG_MIN_CLKREQ_SEL (Offset 0x0725) */ #define BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL 0 #define BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL 0xf #define BIT_PCIE_CFG_MIN_CLKREQ_SEL(x) \ (((x) & BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL) \ << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL) #define BITS_PCIE_CFG_MIN_CLKREQ_SEL \ (BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL) #define BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL(x) \ ((x) & (~BITS_PCIE_CFG_MIN_CLKREQ_SEL)) #define BIT_GET_PCIE_CFG_MIN_CLKREQ_SEL(x) \ (((x) >> BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL) & \ BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL) #define BIT_SET_PCIE_CFG_MIN_CLKREQ_SEL(x, v) \ (BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL(x) | BIT_PCIE_CFG_MIN_CLKREQ_SEL(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_BEAMFORMING_INFO_NSARP_V1 (Offset 0x0728) */ #define BIT_SHIFT_WMAC_ARPIP 0 #define BIT_MASK_WMAC_ARPIP 0xffffffffL #define BIT_WMAC_ARPIP(x) (((x) & BIT_MASK_WMAC_ARPIP) << BIT_SHIFT_WMAC_ARPIP) #define BITS_WMAC_ARPIP (BIT_MASK_WMAC_ARPIP << BIT_SHIFT_WMAC_ARPIP) #define BIT_CLEAR_WMAC_ARPIP(x) ((x) & (~BITS_WMAC_ARPIP)) #define BIT_GET_WMAC_ARPIP(x) \ (((x) >> BIT_SHIFT_WMAC_ARPIP) & BIT_MASK_WMAC_ARPIP) #define BIT_SET_WMAC_ARPIP(x, v) (BIT_CLEAR_WMAC_ARPIP(x) | BIT_WMAC_ARPIP(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */ #define BIT_SHIFT_UPD_BFMEE_USERID 13 #define BIT_MASK_UPD_BFMEE_USERID 0x7 #define BIT_UPD_BFMEE_USERID(x) \ (((x) & BIT_MASK_UPD_BFMEE_USERID) << BIT_SHIFT_UPD_BFMEE_USERID) #define BITS_UPD_BFMEE_USERID \ (BIT_MASK_UPD_BFMEE_USERID << BIT_SHIFT_UPD_BFMEE_USERID) #define BIT_CLEAR_UPD_BFMEE_USERID(x) ((x) & (~BITS_UPD_BFMEE_USERID)) #define BIT_GET_UPD_BFMEE_USERID(x) \ (((x) >> BIT_SHIFT_UPD_BFMEE_USERID) & BIT_MASK_UPD_BFMEE_USERID) #define BIT_SET_UPD_BFMEE_USERID(x, v) \ (BIT_CLEAR_UPD_BFMEE_USERID(x) | BIT_UPD_BFMEE_USERID(v)) #define BIT_UPD_BFMEE_FBTP BIT(12) #define BIT_SHIFT_UPD_BFMEE_CB 8 #define BIT_MASK_UPD_BFMEE_CB 0x3 #define BIT_UPD_BFMEE_CB(x) \ (((x) & BIT_MASK_UPD_BFMEE_CB) << BIT_SHIFT_UPD_BFMEE_CB) #define BITS_UPD_BFMEE_CB (BIT_MASK_UPD_BFMEE_CB << BIT_SHIFT_UPD_BFMEE_CB) #define BIT_CLEAR_UPD_BFMEE_CB(x) ((x) & (~BITS_UPD_BFMEE_CB)) #define BIT_GET_UPD_BFMEE_CB(x) \ (((x) >> BIT_SHIFT_UPD_BFMEE_CB) & BIT_MASK_UPD_BFMEE_CB) #define BIT_SET_UPD_BFMEE_CB(x, v) \ (BIT_CLEAR_UPD_BFMEE_CB(x) | BIT_UPD_BFMEE_CB(v)) #define BIT_SHIFT_UPD_BFMEE_NG 6 #define BIT_MASK_UPD_BFMEE_NG 0x3 #define BIT_UPD_BFMEE_NG(x) \ (((x) & BIT_MASK_UPD_BFMEE_NG) << BIT_SHIFT_UPD_BFMEE_NG) #define BITS_UPD_BFMEE_NG (BIT_MASK_UPD_BFMEE_NG << BIT_SHIFT_UPD_BFMEE_NG) #define BIT_CLEAR_UPD_BFMEE_NG(x) ((x) & (~BITS_UPD_BFMEE_NG)) #define BIT_GET_UPD_BFMEE_NG(x) \ (((x) >> BIT_SHIFT_UPD_BFMEE_NG) & BIT_MASK_UPD_BFMEE_NG) #define BIT_SET_UPD_BFMEE_NG(x, v) \ (BIT_CLEAR_UPD_BFMEE_NG(x) | BIT_UPD_BFMEE_NG(v)) #define BIT_SHIFT_UPD_BFMEE_NR 3 #define BIT_MASK_UPD_BFMEE_NR 0x7 #define BIT_UPD_BFMEE_NR(x) \ (((x) & BIT_MASK_UPD_BFMEE_NR) << BIT_SHIFT_UPD_BFMEE_NR) #define BITS_UPD_BFMEE_NR (BIT_MASK_UPD_BFMEE_NR << BIT_SHIFT_UPD_BFMEE_NR) #define BIT_CLEAR_UPD_BFMEE_NR(x) ((x) & (~BITS_UPD_BFMEE_NR)) #define BIT_GET_UPD_BFMEE_NR(x) \ (((x) >> BIT_SHIFT_UPD_BFMEE_NR) & BIT_MASK_UPD_BFMEE_NR) #define BIT_SET_UPD_BFMEE_NR(x, v) \ (BIT_CLEAR_UPD_BFMEE_NR(x) | BIT_UPD_BFMEE_NR(v)) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */ #define BIT_SHIFT_BEAMFORMING_INFO 0 #define BIT_MASK_BEAMFORMING_INFO 0xffffffffL #define BIT_BEAMFORMING_INFO(x) \ (((x) & BIT_MASK_BEAMFORMING_INFO) << BIT_SHIFT_BEAMFORMING_INFO) #define BITS_BEAMFORMING_INFO \ (BIT_MASK_BEAMFORMING_INFO << BIT_SHIFT_BEAMFORMING_INFO) #define BIT_CLEAR_BEAMFORMING_INFO(x) ((x) & (~BITS_BEAMFORMING_INFO)) #define BIT_GET_BEAMFORMING_INFO(x) \ (((x) >> BIT_SHIFT_BEAMFORMING_INFO) & BIT_MASK_BEAMFORMING_INFO) #define BIT_SET_BEAMFORMING_INFO(x, v) \ (BIT_CLEAR_BEAMFORMING_INFO(x) | BIT_BEAMFORMING_INFO(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */ #define BIT_SHIFT_UPD_BFMEE_BW 0 #define BIT_MASK_UPD_BFMEE_BW 0xfff #define BIT_UPD_BFMEE_BW(x) \ (((x) & BIT_MASK_UPD_BFMEE_BW) << BIT_SHIFT_UPD_BFMEE_BW) #define BITS_UPD_BFMEE_BW (BIT_MASK_UPD_BFMEE_BW << BIT_SHIFT_UPD_BFMEE_BW) #define BIT_CLEAR_UPD_BFMEE_BW(x) ((x) & (~BITS_UPD_BFMEE_BW)) #define BIT_GET_UPD_BFMEE_BW(x) \ (((x) >> BIT_SHIFT_UPD_BFMEE_BW) & BIT_MASK_UPD_BFMEE_BW) #define BIT_SET_UPD_BFMEE_BW(x, v) \ (BIT_CLEAR_UPD_BFMEE_BW(x) | BIT_UPD_BFMEE_BW(v)) #define BIT_SHIFT_UPD_BFMEE_NC 0 #define BIT_MASK_UPD_BFMEE_NC 0x7 #define BIT_UPD_BFMEE_NC(x) \ (((x) & BIT_MASK_UPD_BFMEE_NC) << BIT_SHIFT_UPD_BFMEE_NC) #define BITS_UPD_BFMEE_NC (BIT_MASK_UPD_BFMEE_NC << BIT_SHIFT_UPD_BFMEE_NC) #define BIT_CLEAR_UPD_BFMEE_NC(x) ((x) & (~BITS_UPD_BFMEE_NC)) #define BIT_GET_UPD_BFMEE_NC(x) \ (((x) >> BIT_SHIFT_UPD_BFMEE_NC) & BIT_MASK_UPD_BFMEE_NC) #define BIT_SET_UPD_BFMEE_NC(x, v) \ (BIT_CLEAR_UPD_BFMEE_NC(x) | BIT_UPD_BFMEE_NC(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_IPV6 (Offset 0x0730) */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_0 0xffffffffL #define BIT_R_WMAC_IPV6_MYIPAD_0(x) \ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0) \ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0) #define BITS_R_WMAC_IPV6_MYIPAD_0 \ (BIT_MASK_R_WMAC_IPV6_MYIPAD_0 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0) #define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0)) #define BIT_GET_R_WMAC_IPV6_MYIPAD_0(x) \ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0) & \ BIT_MASK_R_WMAC_IPV6_MYIPAD_0) #define BIT_SET_R_WMAC_IPV6_MYIPAD_0(x, v) \ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0(x) | BIT_R_WMAC_IPV6_MYIPAD_0(v)) /* 2 REG_IPV6_1 (Offset 0x0734) */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_1 0xffffffffL #define BIT_R_WMAC_IPV6_MYIPAD_1(x) \ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1) \ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1) #define BITS_R_WMAC_IPV6_MYIPAD_1 \ (BIT_MASK_R_WMAC_IPV6_MYIPAD_1 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1) #define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1)) #define BIT_GET_R_WMAC_IPV6_MYIPAD_1(x) \ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1) & \ BIT_MASK_R_WMAC_IPV6_MYIPAD_1) #define BIT_SET_R_WMAC_IPV6_MYIPAD_1(x, v) \ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1(x) | BIT_R_WMAC_IPV6_MYIPAD_1(v)) /* 2 REG_IPV6_2 (Offset 0x0738) */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_2 0xffffffffL #define BIT_R_WMAC_IPV6_MYIPAD_2(x) \ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2) \ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2) #define BITS_R_WMAC_IPV6_MYIPAD_2 \ (BIT_MASK_R_WMAC_IPV6_MYIPAD_2 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2) #define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2)) #define BIT_GET_R_WMAC_IPV6_MYIPAD_2(x) \ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2) & \ BIT_MASK_R_WMAC_IPV6_MYIPAD_2) #define BIT_SET_R_WMAC_IPV6_MYIPAD_2(x, v) \ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2(x) | BIT_R_WMAC_IPV6_MYIPAD_2(v)) /* 2 REG_IPV6_3 (Offset 0x073C) */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_3 0xffffffffL #define BIT_R_WMAC_IPV6_MYIPAD_3(x) \ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3) \ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3) #define BITS_R_WMAC_IPV6_MYIPAD_3 \ (BIT_MASK_R_WMAC_IPV6_MYIPAD_3 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3) #define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3)) #define BIT_GET_R_WMAC_IPV6_MYIPAD_3(x) \ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3) & \ BIT_MASK_R_WMAC_IPV6_MYIPAD_3) #define BIT_SET_R_WMAC_IPV6_MYIPAD_3(x, v) \ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3(x) | BIT_R_WMAC_IPV6_MYIPAD_3(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG (Offset 0x0750) */ #define BIT_SHIFT_R_WMAC_CTX_SUBTYPE 4 #define BIT_MASK_R_WMAC_CTX_SUBTYPE 0xf #define BIT_R_WMAC_CTX_SUBTYPE(x) \ (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE) #define BITS_R_WMAC_CTX_SUBTYPE \ (BIT_MASK_R_WMAC_CTX_SUBTYPE << BIT_SHIFT_R_WMAC_CTX_SUBTYPE) #define BIT_CLEAR_R_WMAC_CTX_SUBTYPE(x) ((x) & (~BITS_R_WMAC_CTX_SUBTYPE)) #define BIT_GET_R_WMAC_CTX_SUBTYPE(x) \ (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE) & BIT_MASK_R_WMAC_CTX_SUBTYPE) #define BIT_SET_R_WMAC_CTX_SUBTYPE(x, v) \ (BIT_CLEAR_R_WMAC_CTX_SUBTYPE(x) | BIT_R_WMAC_CTX_SUBTYPE(v)) #define BIT_SHIFT_R_WMAC_RTX_SUBTYPE 0 #define BIT_MASK_R_WMAC_RTX_SUBTYPE 0xf #define BIT_R_WMAC_RTX_SUBTYPE(x) \ (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE) #define BITS_R_WMAC_RTX_SUBTYPE \ (BIT_MASK_R_WMAC_RTX_SUBTYPE << BIT_SHIFT_R_WMAC_RTX_SUBTYPE) #define BIT_CLEAR_R_WMAC_RTX_SUBTYPE(x) ((x) & (~BITS_R_WMAC_RTX_SUBTYPE)) #define BIT_GET_R_WMAC_RTX_SUBTYPE(x) \ (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE) & BIT_MASK_R_WMAC_RTX_SUBTYPE) #define BIT_SET_R_WMAC_RTX_SUBTYPE(x, v) \ (BIT_CLEAR_R_WMAC_RTX_SUBTYPE(x) | BIT_R_WMAC_RTX_SUBTYPE(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_SWAES_DIO_B63_B32 (Offset 0x0754) */ #define BIT_SHIFT_WMAC_SWAES_DIO_B63_B32 0 #define BIT_MASK_WMAC_SWAES_DIO_B63_B32 0xffffffffL #define BIT_WMAC_SWAES_DIO_B63_B32(x) \ (((x) & BIT_MASK_WMAC_SWAES_DIO_B63_B32) \ << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32) #define BITS_WMAC_SWAES_DIO_B63_B32 \ (BIT_MASK_WMAC_SWAES_DIO_B63_B32 << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32) #define BIT_CLEAR_WMAC_SWAES_DIO_B63_B32(x) \ ((x) & (~BITS_WMAC_SWAES_DIO_B63_B32)) #define BIT_GET_WMAC_SWAES_DIO_B63_B32(x) \ (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B63_B32) & \ BIT_MASK_WMAC_SWAES_DIO_B63_B32) #define BIT_SET_WMAC_SWAES_DIO_B63_B32(x, v) \ (BIT_CLEAR_WMAC_SWAES_DIO_B63_B32(x) | BIT_WMAC_SWAES_DIO_B63_B32(v)) /* 2 REG_WMAC_SWAES_DIO_B95_B64 (Offset 0x0758) */ #define BIT_SHIFT_WMAC_SWAES_DIO_B95_B64 0 #define BIT_MASK_WMAC_SWAES_DIO_B95_B64 0xffffffffL #define BIT_WMAC_SWAES_DIO_B95_B64(x) \ (((x) & BIT_MASK_WMAC_SWAES_DIO_B95_B64) \ << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64) #define BITS_WMAC_SWAES_DIO_B95_B64 \ (BIT_MASK_WMAC_SWAES_DIO_B95_B64 << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64) #define BIT_CLEAR_WMAC_SWAES_DIO_B95_B64(x) \ ((x) & (~BITS_WMAC_SWAES_DIO_B95_B64)) #define BIT_GET_WMAC_SWAES_DIO_B95_B64(x) \ (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B95_B64) & \ BIT_MASK_WMAC_SWAES_DIO_B95_B64) #define BIT_SET_WMAC_SWAES_DIO_B95_B64(x, v) \ (BIT_CLEAR_WMAC_SWAES_DIO_B95_B64(x) | BIT_WMAC_SWAES_DIO_B95_B64(v)) /* 2 REG_WMAC_SWAES_DIO_B127_B96 (Offset 0x075C) */ #define BIT_SHIFT_WMAC_SWAES_DIO_B127_B96 0 #define BIT_MASK_WMAC_SWAES_DIO_B127_B96 0xffffffffL #define BIT_WMAC_SWAES_DIO_B127_B96(x) \ (((x) & BIT_MASK_WMAC_SWAES_DIO_B127_B96) \ << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96) #define BITS_WMAC_SWAES_DIO_B127_B96 \ (BIT_MASK_WMAC_SWAES_DIO_B127_B96 << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96) #define BIT_CLEAR_WMAC_SWAES_DIO_B127_B96(x) \ ((x) & (~BITS_WMAC_SWAES_DIO_B127_B96)) #define BIT_GET_WMAC_SWAES_DIO_B127_B96(x) \ (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B127_B96) & \ BIT_MASK_WMAC_SWAES_DIO_B127_B96) #define BIT_SET_WMAC_SWAES_DIO_B127_B96(x, v) \ (BIT_CLEAR_WMAC_SWAES_DIO_B127_B96(x) | BIT_WMAC_SWAES_DIO_B127_B96(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BT_COEX_V2 (Offset 0x0762) */ #define BIT_GNT_BT_POLARITY BIT(12) #define BIT_GNT_BT_BYPASS_PRIORITY BIT(8) #define BIT_SHIFT_TIMER 0 #define BIT_MASK_TIMER 0xff #define BIT_TIMER(x) (((x) & BIT_MASK_TIMER) << BIT_SHIFT_TIMER) #define BITS_TIMER (BIT_MASK_TIMER << BIT_SHIFT_TIMER) #define BIT_CLEAR_TIMER(x) ((x) & (~BITS_TIMER)) #define BIT_GET_TIMER(x) (((x) >> BIT_SHIFT_TIMER) & BIT_MASK_TIMER) #define BIT_SET_TIMER(x, v) (BIT_CLEAR_TIMER(x) | BIT_TIMER(v)) /* 2 REG_BT_COEX (Offset 0x0764) */ #define BIT_R_GNT_BT_RFC_SW BIT(12) #define BIT_R_GNT_BT_RFC_SW_EN BIT(11) #define BIT_R_GNT_BT_BB_SW BIT(10) #define BIT_R_GNT_BT_BB_SW_EN BIT(9) #define BIT_R_BT_CNT_THREN BIT(8) #define BIT_SHIFT_R_BT_CNT_THR 0 #define BIT_MASK_R_BT_CNT_THR 0xff #define BIT_R_BT_CNT_THR(x) \ (((x) & BIT_MASK_R_BT_CNT_THR) << BIT_SHIFT_R_BT_CNT_THR) #define BITS_R_BT_CNT_THR (BIT_MASK_R_BT_CNT_THR << BIT_SHIFT_R_BT_CNT_THR) #define BIT_CLEAR_R_BT_CNT_THR(x) ((x) & (~BITS_R_BT_CNT_THR)) #define BIT_GET_R_BT_CNT_THR(x) \ (((x) >> BIT_SHIFT_R_BT_CNT_THR) & BIT_MASK_R_BT_CNT_THR) #define BIT_SET_R_BT_CNT_THR(x, v) \ (BIT_CLEAR_R_BT_CNT_THR(x) | BIT_R_BT_CNT_THR(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ #define BIT_WLRX_TER_BY_CTL BIT(43) #define BIT_WLRX_TER_BY_AD BIT(42) #define BIT_ANT_DIVERSITY_SEL BIT(41) #define BIT_ANTSEL_FOR_BT_CTRL_EN BIT(40) #define BIT_WLACT_LOW_GNTWL_EN BIT(34) #define BIT_WLACT_HIGH_GNTBT_EN BIT(33) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ #define BIT_NAV_UPPER_V1 BIT(32) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ #define BIT_SHIFT_RXMYRTS_NAV_V1 8 #define BIT_MASK_RXMYRTS_NAV_V1 0xff #define BIT_RXMYRTS_NAV_V1(x) \ (((x) & BIT_MASK_RXMYRTS_NAV_V1) << BIT_SHIFT_RXMYRTS_NAV_V1) #define BITS_RXMYRTS_NAV_V1 \ (BIT_MASK_RXMYRTS_NAV_V1 << BIT_SHIFT_RXMYRTS_NAV_V1) #define BIT_CLEAR_RXMYRTS_NAV_V1(x) ((x) & (~BITS_RXMYRTS_NAV_V1)) #define BIT_GET_RXMYRTS_NAV_V1(x) \ (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1) & BIT_MASK_RXMYRTS_NAV_V1) #define BIT_SET_RXMYRTS_NAV_V1(x, v) \ (BIT_CLEAR_RXMYRTS_NAV_V1(x) | BIT_RXMYRTS_NAV_V1(v)) #define BIT_SHIFT_RTSRST_V1 0 #define BIT_MASK_RTSRST_V1 0xff #define BIT_RTSRST_V1(x) (((x) & BIT_MASK_RTSRST_V1) << BIT_SHIFT_RTSRST_V1) #define BITS_RTSRST_V1 (BIT_MASK_RTSRST_V1 << BIT_SHIFT_RTSRST_V1) #define BIT_CLEAR_RTSRST_V1(x) ((x) & (~BITS_RTSRST_V1)) #define BIT_GET_RTSRST_V1(x) (((x) >> BIT_SHIFT_RTSRST_V1) & BIT_MASK_RTSRST_V1) #define BIT_SET_RTSRST_V1(x, v) (BIT_CLEAR_RTSRST_V1(x) | BIT_RTSRST_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WLAN_ACT_MASK_CTRL_1 (Offset 0x076C) */ #define BIT_WLRX_TER_BY_CTL_1 BIT(11) #define BIT_WLRX_TER_BY_AD_1 BIT(10) #define BIT_ANT_DIVERSITY_SEL_1 BIT(9) #define BIT_ANTSEL_FOR_BT_CTRL_EN_1 BIT(8) #define BIT_WLACT_LOW_GNTWL_EN_1 BIT(2) #define BIT_WLACT_HIGH_GNTBT_EN_1 BIT(1) #define BIT_NAV_UPPER_1_V1 BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BT_COEX_ENHANCED_INTR_CTRL (Offset 0x076E) */ #define BIT_SHIFT_BT_STAT_DELAY 12 #define BIT_MASK_BT_STAT_DELAY 0xf #define BIT_BT_STAT_DELAY(x) \ (((x) & BIT_MASK_BT_STAT_DELAY) << BIT_SHIFT_BT_STAT_DELAY) #define BITS_BT_STAT_DELAY (BIT_MASK_BT_STAT_DELAY << BIT_SHIFT_BT_STAT_DELAY) #define BIT_CLEAR_BT_STAT_DELAY(x) ((x) & (~BITS_BT_STAT_DELAY)) #define BIT_GET_BT_STAT_DELAY(x) \ (((x) >> BIT_SHIFT_BT_STAT_DELAY) & BIT_MASK_BT_STAT_DELAY) #define BIT_SET_BT_STAT_DELAY(x, v) \ (BIT_CLEAR_BT_STAT_DELAY(x) | BIT_BT_STAT_DELAY(v)) #define BIT_SHIFT_BT_TRX_INIT_DETECT 8 #define BIT_MASK_BT_TRX_INIT_DETECT 0xf #define BIT_BT_TRX_INIT_DETECT(x) \ (((x) & BIT_MASK_BT_TRX_INIT_DETECT) << BIT_SHIFT_BT_TRX_INIT_DETECT) #define BITS_BT_TRX_INIT_DETECT \ (BIT_MASK_BT_TRX_INIT_DETECT << BIT_SHIFT_BT_TRX_INIT_DETECT) #define BIT_CLEAR_BT_TRX_INIT_DETECT(x) ((x) & (~BITS_BT_TRX_INIT_DETECT)) #define BIT_GET_BT_TRX_INIT_DETECT(x) \ (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT) & BIT_MASK_BT_TRX_INIT_DETECT) #define BIT_SET_BT_TRX_INIT_DETECT(x, v) \ (BIT_CLEAR_BT_TRX_INIT_DETECT(x) | BIT_BT_TRX_INIT_DETECT(v)) #define BIT_SHIFT_BT_PRI_DETECT_TO 4 #define BIT_MASK_BT_PRI_DETECT_TO 0xf #define BIT_BT_PRI_DETECT_TO(x) \ (((x) & BIT_MASK_BT_PRI_DETECT_TO) << BIT_SHIFT_BT_PRI_DETECT_TO) #define BITS_BT_PRI_DETECT_TO \ (BIT_MASK_BT_PRI_DETECT_TO << BIT_SHIFT_BT_PRI_DETECT_TO) #define BIT_CLEAR_BT_PRI_DETECT_TO(x) ((x) & (~BITS_BT_PRI_DETECT_TO)) #define BIT_GET_BT_PRI_DETECT_TO(x) \ (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO) & BIT_MASK_BT_PRI_DETECT_TO) #define BIT_SET_BT_PRI_DETECT_TO(x, v) \ (BIT_CLEAR_BT_PRI_DETECT_TO(x) | BIT_BT_PRI_DETECT_TO(v)) #define BIT_R_GRANTALL_WLMASK BIT(3) #define BIT_STATIS_BT_EN BIT(2) #define BIT_WL_ACT_MASK_ENABLE BIT(1) #define BIT_ENHANCED_BT BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */ #define BIT_SHIFT_STATIS_BT_LO_RX (48 & CPU_OPT_WIDTH) #define BIT_MASK_STATIS_BT_LO_RX 0xffff #define BIT_STATIS_BT_LO_RX(x) \ (((x) & BIT_MASK_STATIS_BT_LO_RX) << BIT_SHIFT_STATIS_BT_LO_RX) #define BITS_STATIS_BT_LO_RX \ (BIT_MASK_STATIS_BT_LO_RX << BIT_SHIFT_STATIS_BT_LO_RX) #define BIT_CLEAR_STATIS_BT_LO_RX(x) ((x) & (~BITS_STATIS_BT_LO_RX)) #define BIT_GET_STATIS_BT_LO_RX(x) \ (((x) >> BIT_SHIFT_STATIS_BT_LO_RX) & BIT_MASK_STATIS_BT_LO_RX) #define BIT_SET_STATIS_BT_LO_RX(x, v) \ (BIT_CLEAR_STATIS_BT_LO_RX(x) | BIT_STATIS_BT_LO_RX(v)) #define BIT_SHIFT_STATIS_BT_LO_TX (32 & CPU_OPT_WIDTH) #define BIT_MASK_STATIS_BT_LO_TX 0xffff #define BIT_STATIS_BT_LO_TX(x) \ (((x) & BIT_MASK_STATIS_BT_LO_TX) << BIT_SHIFT_STATIS_BT_LO_TX) #define BITS_STATIS_BT_LO_TX \ (BIT_MASK_STATIS_BT_LO_TX << BIT_SHIFT_STATIS_BT_LO_TX) #define BIT_CLEAR_STATIS_BT_LO_TX(x) ((x) & (~BITS_STATIS_BT_LO_TX)) #define BIT_GET_STATIS_BT_LO_TX(x) \ (((x) >> BIT_SHIFT_STATIS_BT_LO_TX) & BIT_MASK_STATIS_BT_LO_TX) #define BIT_SET_STATIS_BT_LO_TX(x, v) \ (BIT_CLEAR_STATIS_BT_LO_TX(x) | BIT_STATIS_BT_LO_TX(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */ #define BIT_SHIFT_STATIS_BT_HI_RX 16 #define BIT_MASK_STATIS_BT_HI_RX 0xffff #define BIT_STATIS_BT_HI_RX(x) \ (((x) & BIT_MASK_STATIS_BT_HI_RX) << BIT_SHIFT_STATIS_BT_HI_RX) #define BITS_STATIS_BT_HI_RX \ (BIT_MASK_STATIS_BT_HI_RX << BIT_SHIFT_STATIS_BT_HI_RX) #define BIT_CLEAR_STATIS_BT_HI_RX(x) ((x) & (~BITS_STATIS_BT_HI_RX)) #define BIT_GET_STATIS_BT_HI_RX(x) \ (((x) >> BIT_SHIFT_STATIS_BT_HI_RX) & BIT_MASK_STATIS_BT_HI_RX) #define BIT_SET_STATIS_BT_HI_RX(x, v) \ (BIT_CLEAR_STATIS_BT_HI_RX(x) | BIT_STATIS_BT_HI_RX(v)) #define BIT_SHIFT_STATIS_BT_HI_TX 0 #define BIT_MASK_STATIS_BT_HI_TX 0xffff #define BIT_STATIS_BT_HI_TX(x) \ (((x) & BIT_MASK_STATIS_BT_HI_TX) << BIT_SHIFT_STATIS_BT_HI_TX) #define BITS_STATIS_BT_HI_TX \ (BIT_MASK_STATIS_BT_HI_TX << BIT_SHIFT_STATIS_BT_HI_TX) #define BIT_CLEAR_STATIS_BT_HI_TX(x) ((x) & (~BITS_STATIS_BT_HI_TX)) #define BIT_GET_STATIS_BT_HI_TX(x) \ (((x) >> BIT_SHIFT_STATIS_BT_HI_TX) & BIT_MASK_STATIS_BT_HI_TX) #define BIT_SET_STATIS_BT_HI_TX(x, v) \ (BIT_CLEAR_STATIS_BT_HI_TX(x) | BIT_STATIS_BT_HI_TX(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BT_ACT_STATISTICS_1 (Offset 0x0774) */ #define BIT_SHIFT_STATIS_BT_LO_RX_1 16 #define BIT_MASK_STATIS_BT_LO_RX_1 0xffff #define BIT_STATIS_BT_LO_RX_1(x) \ (((x) & BIT_MASK_STATIS_BT_LO_RX_1) << BIT_SHIFT_STATIS_BT_LO_RX_1) #define BITS_STATIS_BT_LO_RX_1 \ (BIT_MASK_STATIS_BT_LO_RX_1 << BIT_SHIFT_STATIS_BT_LO_RX_1) #define BIT_CLEAR_STATIS_BT_LO_RX_1(x) ((x) & (~BITS_STATIS_BT_LO_RX_1)) #define BIT_GET_STATIS_BT_LO_RX_1(x) \ (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1) & BIT_MASK_STATIS_BT_LO_RX_1) #define BIT_SET_STATIS_BT_LO_RX_1(x, v) \ (BIT_CLEAR_STATIS_BT_LO_RX_1(x) | BIT_STATIS_BT_LO_RX_1(v)) #define BIT_SHIFT_STATIS_BT_LO_TX_1 0 #define BIT_MASK_STATIS_BT_LO_TX_1 0xffff #define BIT_STATIS_BT_LO_TX_1(x) \ (((x) & BIT_MASK_STATIS_BT_LO_TX_1) << BIT_SHIFT_STATIS_BT_LO_TX_1) #define BITS_STATIS_BT_LO_TX_1 \ (BIT_MASK_STATIS_BT_LO_TX_1 << BIT_SHIFT_STATIS_BT_LO_TX_1) #define BIT_CLEAR_STATIS_BT_LO_TX_1(x) ((x) & (~BITS_STATIS_BT_LO_TX_1)) #define BIT_GET_STATIS_BT_LO_TX_1(x) \ (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1) & BIT_MASK_STATIS_BT_LO_TX_1) #define BIT_SET_STATIS_BT_LO_TX_1(x, v) \ (BIT_CLEAR_STATIS_BT_LO_TX_1(x) | BIT_STATIS_BT_LO_TX_1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BT_STATISTICS_CONTROL_REGISTER (Offset 0x0778) */ #define BIT_SHIFT_R_BT_CMD_RPT 16 #define BIT_MASK_R_BT_CMD_RPT 0xffff #define BIT_R_BT_CMD_RPT(x) \ (((x) & BIT_MASK_R_BT_CMD_RPT) << BIT_SHIFT_R_BT_CMD_RPT) #define BITS_R_BT_CMD_RPT (BIT_MASK_R_BT_CMD_RPT << BIT_SHIFT_R_BT_CMD_RPT) #define BIT_CLEAR_R_BT_CMD_RPT(x) ((x) & (~BITS_R_BT_CMD_RPT)) #define BIT_GET_R_BT_CMD_RPT(x) \ (((x) >> BIT_SHIFT_R_BT_CMD_RPT) & BIT_MASK_R_BT_CMD_RPT) #define BIT_SET_R_BT_CMD_RPT(x, v) \ (BIT_CLEAR_R_BT_CMD_RPT(x) | BIT_R_BT_CMD_RPT(v)) #define BIT_SHIFT_R_RPT_FROM_BT 8 #define BIT_MASK_R_RPT_FROM_BT 0xff #define BIT_R_RPT_FROM_BT(x) \ (((x) & BIT_MASK_R_RPT_FROM_BT) << BIT_SHIFT_R_RPT_FROM_BT) #define BITS_R_RPT_FROM_BT (BIT_MASK_R_RPT_FROM_BT << BIT_SHIFT_R_RPT_FROM_BT) #define BIT_CLEAR_R_RPT_FROM_BT(x) ((x) & (~BITS_R_RPT_FROM_BT)) #define BIT_GET_R_RPT_FROM_BT(x) \ (((x) >> BIT_SHIFT_R_RPT_FROM_BT) & BIT_MASK_R_RPT_FROM_BT) #define BIT_SET_R_RPT_FROM_BT(x, v) \ (BIT_CLEAR_R_RPT_FROM_BT(x) | BIT_R_RPT_FROM_BT(v)) #define BIT_SHIFT_BT_HID_ISR_SET 6 #define BIT_MASK_BT_HID_ISR_SET 0x3 #define BIT_BT_HID_ISR_SET(x) \ (((x) & BIT_MASK_BT_HID_ISR_SET) << BIT_SHIFT_BT_HID_ISR_SET) #define BITS_BT_HID_ISR_SET \ (BIT_MASK_BT_HID_ISR_SET << BIT_SHIFT_BT_HID_ISR_SET) #define BIT_CLEAR_BT_HID_ISR_SET(x) ((x) & (~BITS_BT_HID_ISR_SET)) #define BIT_GET_BT_HID_ISR_SET(x) \ (((x) >> BIT_SHIFT_BT_HID_ISR_SET) & BIT_MASK_BT_HID_ISR_SET) #define BIT_SET_BT_HID_ISR_SET(x, v) \ (BIT_CLEAR_BT_HID_ISR_SET(x) | BIT_BT_HID_ISR_SET(v)) #define BIT_TDMA_BT_START_NOTIFY BIT(5) #define BIT_ENABLE_TDMA_FW_MODE BIT(4) #define BIT_ENABLE_PTA_TDMA_MODE BIT(3) #define BIT_ENABLE_COEXIST_TAB_IN_TDMA BIT(2) #define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1) #define BIT_RTK_BT_ENABLE BIT(0) /* 2 REG_BT_STATUS_REPORT_REGISTER (Offset 0x077C) */ #define BIT_SHIFT_BT_PROFILE 24 #define BIT_MASK_BT_PROFILE 0xff #define BIT_BT_PROFILE(x) (((x) & BIT_MASK_BT_PROFILE) << BIT_SHIFT_BT_PROFILE) #define BITS_BT_PROFILE (BIT_MASK_BT_PROFILE << BIT_SHIFT_BT_PROFILE) #define BIT_CLEAR_BT_PROFILE(x) ((x) & (~BITS_BT_PROFILE)) #define BIT_GET_BT_PROFILE(x) \ (((x) >> BIT_SHIFT_BT_PROFILE) & BIT_MASK_BT_PROFILE) #define BIT_SET_BT_PROFILE(x, v) (BIT_CLEAR_BT_PROFILE(x) | BIT_BT_PROFILE(v)) #define BIT_SHIFT_BT_POWER 16 #define BIT_MASK_BT_POWER 0xff #define BIT_BT_POWER(x) (((x) & BIT_MASK_BT_POWER) << BIT_SHIFT_BT_POWER) #define BITS_BT_POWER (BIT_MASK_BT_POWER << BIT_SHIFT_BT_POWER) #define BIT_CLEAR_BT_POWER(x) ((x) & (~BITS_BT_POWER)) #define BIT_GET_BT_POWER(x) (((x) >> BIT_SHIFT_BT_POWER) & BIT_MASK_BT_POWER) #define BIT_SET_BT_POWER(x, v) (BIT_CLEAR_BT_POWER(x) | BIT_BT_POWER(v)) #define BIT_SHIFT_BT_PREDECT_STATUS 8 #define BIT_MASK_BT_PREDECT_STATUS 0xff #define BIT_BT_PREDECT_STATUS(x) \ (((x) & BIT_MASK_BT_PREDECT_STATUS) << BIT_SHIFT_BT_PREDECT_STATUS) #define BITS_BT_PREDECT_STATUS \ (BIT_MASK_BT_PREDECT_STATUS << BIT_SHIFT_BT_PREDECT_STATUS) #define BIT_CLEAR_BT_PREDECT_STATUS(x) ((x) & (~BITS_BT_PREDECT_STATUS)) #define BIT_GET_BT_PREDECT_STATUS(x) \ (((x) >> BIT_SHIFT_BT_PREDECT_STATUS) & BIT_MASK_BT_PREDECT_STATUS) #define BIT_SET_BT_PREDECT_STATUS(x, v) \ (BIT_CLEAR_BT_PREDECT_STATUS(x) | BIT_BT_PREDECT_STATUS(v)) #define BIT_SHIFT_BT_CMD_INFO 0 #define BIT_MASK_BT_CMD_INFO 0xff #define BIT_BT_CMD_INFO(x) \ (((x) & BIT_MASK_BT_CMD_INFO) << BIT_SHIFT_BT_CMD_INFO) #define BITS_BT_CMD_INFO (BIT_MASK_BT_CMD_INFO << BIT_SHIFT_BT_CMD_INFO) #define BIT_CLEAR_BT_CMD_INFO(x) ((x) & (~BITS_BT_CMD_INFO)) #define BIT_GET_BT_CMD_INFO(x) \ (((x) >> BIT_SHIFT_BT_CMD_INFO) & BIT_MASK_BT_CMD_INFO) #define BIT_SET_BT_CMD_INFO(x, v) \ (BIT_CLEAR_BT_CMD_INFO(x) | BIT_BT_CMD_INFO(v)) /* 2 REG_BT_INTERRUPT_CONTROL_REGISTER (Offset 0x0780) */ #define BIT_EN_MAC_NULL_PKT_NOTIFY BIT(31) #define BIT_EN_WLAN_RPT_AND_BT_QUERY BIT(30) #define BIT_EN_BT_STSTUS_RPT BIT(29) #define BIT_EN_BT_POWER BIT(28) #define BIT_EN_BT_CHANNEL BIT(27) #define BIT_EN_BT_SLOT_CHANGE BIT(26) #define BIT_EN_BT_PROFILE_OR_HID BIT(25) #define BIT_WLAN_RPT_NOTIFY BIT(24) #define BIT_SHIFT_WLAN_RPT_DATA 16 #define BIT_MASK_WLAN_RPT_DATA 0xff #define BIT_WLAN_RPT_DATA(x) \ (((x) & BIT_MASK_WLAN_RPT_DATA) << BIT_SHIFT_WLAN_RPT_DATA) #define BITS_WLAN_RPT_DATA (BIT_MASK_WLAN_RPT_DATA << BIT_SHIFT_WLAN_RPT_DATA) #define BIT_CLEAR_WLAN_RPT_DATA(x) ((x) & (~BITS_WLAN_RPT_DATA)) #define BIT_GET_WLAN_RPT_DATA(x) \ (((x) >> BIT_SHIFT_WLAN_RPT_DATA) & BIT_MASK_WLAN_RPT_DATA) #define BIT_SET_WLAN_RPT_DATA(x, v) \ (BIT_CLEAR_WLAN_RPT_DATA(x) | BIT_WLAN_RPT_DATA(v)) #define BIT_SHIFT_CMD_ID 8 #define BIT_MASK_CMD_ID 0xff #define BIT_CMD_ID(x) (((x) & BIT_MASK_CMD_ID) << BIT_SHIFT_CMD_ID) #define BITS_CMD_ID (BIT_MASK_CMD_ID << BIT_SHIFT_CMD_ID) #define BIT_CLEAR_CMD_ID(x) ((x) & (~BITS_CMD_ID)) #define BIT_GET_CMD_ID(x) (((x) >> BIT_SHIFT_CMD_ID) & BIT_MASK_CMD_ID) #define BIT_SET_CMD_ID(x, v) (BIT_CLEAR_CMD_ID(x) | BIT_CMD_ID(v)) #define BIT_SHIFT_BT_DATA 0 #define BIT_MASK_BT_DATA 0xff #define BIT_BT_DATA(x) (((x) & BIT_MASK_BT_DATA) << BIT_SHIFT_BT_DATA) #define BITS_BT_DATA (BIT_MASK_BT_DATA << BIT_SHIFT_BT_DATA) #define BIT_CLEAR_BT_DATA(x) ((x) & (~BITS_BT_DATA)) #define BIT_GET_BT_DATA(x) (((x) >> BIT_SHIFT_BT_DATA) & BIT_MASK_BT_DATA) #define BIT_SET_BT_DATA(x, v) (BIT_CLEAR_BT_DATA(x) | BIT_BT_DATA(v)) /* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER (Offset 0x0784) */ #define BIT_SHIFT_WLAN_RPT_TO 0 #define BIT_MASK_WLAN_RPT_TO 0xff #define BIT_WLAN_RPT_TO(x) \ (((x) & BIT_MASK_WLAN_RPT_TO) << BIT_SHIFT_WLAN_RPT_TO) #define BITS_WLAN_RPT_TO (BIT_MASK_WLAN_RPT_TO << BIT_SHIFT_WLAN_RPT_TO) #define BIT_CLEAR_WLAN_RPT_TO(x) ((x) & (~BITS_WLAN_RPT_TO)) #define BIT_GET_WLAN_RPT_TO(x) \ (((x) >> BIT_SHIFT_WLAN_RPT_TO) & BIT_MASK_WLAN_RPT_TO) #define BIT_SET_WLAN_RPT_TO(x, v) \ (BIT_CLEAR_WLAN_RPT_TO(x) | BIT_WLAN_RPT_TO(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ #define BIT_SHIFT_ISOLATION_CHK 1 #define BIT_MASK_ISOLATION_CHK 0x7fffffffffffffffffffL #define BIT_ISOLATION_CHK(x) \ (((x) & BIT_MASK_ISOLATION_CHK) << BIT_SHIFT_ISOLATION_CHK) #define BITS_ISOLATION_CHK (BIT_MASK_ISOLATION_CHK << BIT_SHIFT_ISOLATION_CHK) #define BIT_CLEAR_ISOLATION_CHK(x) ((x) & (~BITS_ISOLATION_CHK)) #define BIT_GET_ISOLATION_CHK(x) \ (((x) >> BIT_SHIFT_ISOLATION_CHK) & BIT_MASK_ISOLATION_CHK) #define BIT_SET_ISOLATION_CHK(x, v) \ (BIT_CLEAR_ISOLATION_CHK(x) | BIT_ISOLATION_CHK(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ #define BIT_SHIFT_ISOLATION_CHK_0 1 #define BIT_MASK_ISOLATION_CHK_0 0x7fffff #define BIT_ISOLATION_CHK_0(x) \ (((x) & BIT_MASK_ISOLATION_CHK_0) << BIT_SHIFT_ISOLATION_CHK_0) #define BITS_ISOLATION_CHK_0 \ (BIT_MASK_ISOLATION_CHK_0 << BIT_SHIFT_ISOLATION_CHK_0) #define BIT_CLEAR_ISOLATION_CHK_0(x) ((x) & (~BITS_ISOLATION_CHK_0)) #define BIT_GET_ISOLATION_CHK_0(x) \ (((x) >> BIT_SHIFT_ISOLATION_CHK_0) & BIT_MASK_ISOLATION_CHK_0) #define BIT_SET_ISOLATION_CHK_0(x, v) \ (BIT_CLEAR_ISOLATION_CHK_0(x) | BIT_ISOLATION_CHK_0(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ #define BIT_ISOLATION_EN BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 (Offset 0x0788) */ #define BIT_SHIFT_ISOLATION_CHK_1 0 #define BIT_MASK_ISOLATION_CHK_1 0xffffffffL #define BIT_ISOLATION_CHK_1(x) \ (((x) & BIT_MASK_ISOLATION_CHK_1) << BIT_SHIFT_ISOLATION_CHK_1) #define BITS_ISOLATION_CHK_1 \ (BIT_MASK_ISOLATION_CHK_1 << BIT_SHIFT_ISOLATION_CHK_1) #define BIT_CLEAR_ISOLATION_CHK_1(x) ((x) & (~BITS_ISOLATION_CHK_1)) #define BIT_GET_ISOLATION_CHK_1(x) \ (((x) >> BIT_SHIFT_ISOLATION_CHK_1) & BIT_MASK_ISOLATION_CHK_1) #define BIT_SET_ISOLATION_CHK_1(x, v) \ (BIT_CLEAR_ISOLATION_CHK_1(x) | BIT_ISOLATION_CHK_1(v)) /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 (Offset 0x078C) */ #define BIT_APPEND_MACID_IN_RESP_EN_1 BIT(18) #define BIT_ADDR2_MATCH_EN_1 BIT(17) #define BIT_ANTTRN_EN_1 BIT(16) #define BIT_SHIFT_ISOLATION_CHK_2 0 #define BIT_MASK_ISOLATION_CHK_2 0xffffff #define BIT_ISOLATION_CHK_2(x) \ (((x) & BIT_MASK_ISOLATION_CHK_2) << BIT_SHIFT_ISOLATION_CHK_2) #define BITS_ISOLATION_CHK_2 \ (BIT_MASK_ISOLATION_CHK_2 << BIT_SHIFT_ISOLATION_CHK_2) #define BIT_CLEAR_ISOLATION_CHK_2(x) ((x) & (~BITS_ISOLATION_CHK_2)) #define BIT_GET_ISOLATION_CHK_2(x) \ (((x) >> BIT_SHIFT_ISOLATION_CHK_2) & BIT_MASK_ISOLATION_CHK_2) #define BIT_SET_ISOLATION_CHK_2(x, v) \ (BIT_CLEAR_ISOLATION_CHK_2(x) | BIT_ISOLATION_CHK_2(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BT_INTERRUPT_STATUS_REGISTER (Offset 0x078F) */ #define BIT_BT_HID_ISR BIT(7) #define BIT_BT_QUERY_ISR BIT(6) #define BIT_MAC_NULL_PKT_NOTIFY_ISR BIT(5) #define BIT_WLAN_RPT_ISR BIT(4) #define BIT_BT_POWER_ISR BIT(3) #define BIT_BT_CHANNEL_ISR BIT(2) #define BIT_BT_SLOT_CHANGE_ISR BIT(1) #define BIT_BT_PROFILE_ISR BIT(0) /* 2 REG_BT_TDMA_TIME_REGISTER (Offset 0x0790) */ #define BIT_SHIFT_BT_TIME 6 #define BIT_MASK_BT_TIME 0x3ffffff #define BIT_BT_TIME(x) (((x) & BIT_MASK_BT_TIME) << BIT_SHIFT_BT_TIME) #define BITS_BT_TIME (BIT_MASK_BT_TIME << BIT_SHIFT_BT_TIME) #define BIT_CLEAR_BT_TIME(x) ((x) & (~BITS_BT_TIME)) #define BIT_GET_BT_TIME(x) (((x) >> BIT_SHIFT_BT_TIME) & BIT_MASK_BT_TIME) #define BIT_SET_BT_TIME(x, v) (BIT_CLEAR_BT_TIME(x) | BIT_BT_TIME(v)) #define BIT_SHIFT_BT_RPT_SAMPLE_RATE 0 #define BIT_MASK_BT_RPT_SAMPLE_RATE 0x3f #define BIT_BT_RPT_SAMPLE_RATE(x) \ (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE) << BIT_SHIFT_BT_RPT_SAMPLE_RATE) #define BITS_BT_RPT_SAMPLE_RATE \ (BIT_MASK_BT_RPT_SAMPLE_RATE << BIT_SHIFT_BT_RPT_SAMPLE_RATE) #define BIT_CLEAR_BT_RPT_SAMPLE_RATE(x) ((x) & (~BITS_BT_RPT_SAMPLE_RATE)) #define BIT_GET_BT_RPT_SAMPLE_RATE(x) \ (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE) & BIT_MASK_BT_RPT_SAMPLE_RATE) #define BIT_SET_BT_RPT_SAMPLE_RATE(x, v) \ (BIT_CLEAR_BT_RPT_SAMPLE_RATE(x) | BIT_BT_RPT_SAMPLE_RATE(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */ #define BIT_SHIFT_R_OFDM_LEN 26 #define BIT_MASK_R_OFDM_LEN 0x3f #define BIT_R_OFDM_LEN(x) (((x) & BIT_MASK_R_OFDM_LEN) << BIT_SHIFT_R_OFDM_LEN) #define BITS_R_OFDM_LEN (BIT_MASK_R_OFDM_LEN << BIT_SHIFT_R_OFDM_LEN) #define BIT_CLEAR_R_OFDM_LEN(x) ((x) & (~BITS_R_OFDM_LEN)) #define BIT_GET_R_OFDM_LEN(x) \ (((x) >> BIT_SHIFT_R_OFDM_LEN) & BIT_MASK_R_OFDM_LEN) #define BIT_SET_R_OFDM_LEN(x, v) (BIT_CLEAR_R_OFDM_LEN(x) | BIT_R_OFDM_LEN(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */ #define BIT_SHIFT_BT_EISR_EN 16 #define BIT_MASK_BT_EISR_EN 0xff #define BIT_BT_EISR_EN(x) (((x) & BIT_MASK_BT_EISR_EN) << BIT_SHIFT_BT_EISR_EN) #define BITS_BT_EISR_EN (BIT_MASK_BT_EISR_EN << BIT_SHIFT_BT_EISR_EN) #define BIT_CLEAR_BT_EISR_EN(x) ((x) & (~BITS_BT_EISR_EN)) #define BIT_GET_BT_EISR_EN(x) \ (((x) >> BIT_SHIFT_BT_EISR_EN) & BIT_MASK_BT_EISR_EN) #define BIT_SET_BT_EISR_EN(x, v) (BIT_CLEAR_BT_EISR_EN(x) | BIT_BT_EISR_EN(v)) #define BIT_BT_ACT_FALLING_ISR BIT(10) #define BIT_BT_ACT_RISING_ISR BIT(9) #define BIT_TDMA_TO_ISR BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */ #define BIT_SHIFT_BT_CH 0 #define BIT_MASK_BT_CH 0xff #define BIT_BT_CH(x) (((x) & BIT_MASK_BT_CH) << BIT_SHIFT_BT_CH) #define BITS_BT_CH (BIT_MASK_BT_CH << BIT_SHIFT_BT_CH) #define BIT_CLEAR_BT_CH(x) ((x) & (~BITS_BT_CH)) #define BIT_GET_BT_CH(x) (((x) >> BIT_SHIFT_BT_CH) & BIT_MASK_BT_CH) #define BIT_SET_BT_CH(x, v) (BIT_CLEAR_BT_CH(x) | BIT_BT_CH(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */ #define BIT_SHIFT_BT_CH_V1 0 #define BIT_MASK_BT_CH_V1 0x7f #define BIT_BT_CH_V1(x) (((x) & BIT_MASK_BT_CH_V1) << BIT_SHIFT_BT_CH_V1) #define BITS_BT_CH_V1 (BIT_MASK_BT_CH_V1 << BIT_SHIFT_BT_CH_V1) #define BIT_CLEAR_BT_CH_V1(x) ((x) & (~BITS_BT_CH_V1)) #define BIT_GET_BT_CH_V1(x) (((x) >> BIT_SHIFT_BT_CH_V1) & BIT_MASK_BT_CH_V1) #define BIT_SET_BT_CH_V1(x, v) (BIT_CLEAR_BT_CH_V1(x) | BIT_BT_CH_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_OBFF_CTRL_BASIC (Offset 0x0798) */ #define BIT_OBFF_EN_V1 BIT(31) #define BIT_SHIFT_OBFF_STATE_V1 28 #define BIT_MASK_OBFF_STATE_V1 0x3 #define BIT_OBFF_STATE_V1(x) \ (((x) & BIT_MASK_OBFF_STATE_V1) << BIT_SHIFT_OBFF_STATE_V1) #define BITS_OBFF_STATE_V1 (BIT_MASK_OBFF_STATE_V1 << BIT_SHIFT_OBFF_STATE_V1) #define BIT_CLEAR_OBFF_STATE_V1(x) ((x) & (~BITS_OBFF_STATE_V1)) #define BIT_GET_OBFF_STATE_V1(x) \ (((x) >> BIT_SHIFT_OBFF_STATE_V1) & BIT_MASK_OBFF_STATE_V1) #define BIT_SET_OBFF_STATE_V1(x, v) \ (BIT_CLEAR_OBFF_STATE_V1(x) | BIT_OBFF_STATE_V1(v)) #define BIT_OBFF_ACT_RXDMA_EN BIT(27) #define BIT_OBFF_BLOCK_INT_EN BIT(26) #define BIT_OBFF_AUTOACT_EN BIT(25) #define BIT_OBFF_AUTOIDLE_EN BIT(24) #define BIT_SHIFT_WAKE_MAX_PLS 20 #define BIT_MASK_WAKE_MAX_PLS 0x7 #define BIT_WAKE_MAX_PLS(x) \ (((x) & BIT_MASK_WAKE_MAX_PLS) << BIT_SHIFT_WAKE_MAX_PLS) #define BITS_WAKE_MAX_PLS (BIT_MASK_WAKE_MAX_PLS << BIT_SHIFT_WAKE_MAX_PLS) #define BIT_CLEAR_WAKE_MAX_PLS(x) ((x) & (~BITS_WAKE_MAX_PLS)) #define BIT_GET_WAKE_MAX_PLS(x) \ (((x) >> BIT_SHIFT_WAKE_MAX_PLS) & BIT_MASK_WAKE_MAX_PLS) #define BIT_SET_WAKE_MAX_PLS(x, v) \ (BIT_CLEAR_WAKE_MAX_PLS(x) | BIT_WAKE_MAX_PLS(v)) #define BIT_SHIFT_WAKE_MIN_PLS 16 #define BIT_MASK_WAKE_MIN_PLS 0x7 #define BIT_WAKE_MIN_PLS(x) \ (((x) & BIT_MASK_WAKE_MIN_PLS) << BIT_SHIFT_WAKE_MIN_PLS) #define BITS_WAKE_MIN_PLS (BIT_MASK_WAKE_MIN_PLS << BIT_SHIFT_WAKE_MIN_PLS) #define BIT_CLEAR_WAKE_MIN_PLS(x) ((x) & (~BITS_WAKE_MIN_PLS)) #define BIT_GET_WAKE_MIN_PLS(x) \ (((x) >> BIT_SHIFT_WAKE_MIN_PLS) & BIT_MASK_WAKE_MIN_PLS) #define BIT_SET_WAKE_MIN_PLS(x, v) \ (BIT_CLEAR_WAKE_MIN_PLS(x) | BIT_WAKE_MIN_PLS(v)) #define BIT_SHIFT_WAKE_MAX_F2F 12 #define BIT_MASK_WAKE_MAX_F2F 0x7 #define BIT_WAKE_MAX_F2F(x) \ (((x) & BIT_MASK_WAKE_MAX_F2F) << BIT_SHIFT_WAKE_MAX_F2F) #define BITS_WAKE_MAX_F2F (BIT_MASK_WAKE_MAX_F2F << BIT_SHIFT_WAKE_MAX_F2F) #define BIT_CLEAR_WAKE_MAX_F2F(x) ((x) & (~BITS_WAKE_MAX_F2F)) #define BIT_GET_WAKE_MAX_F2F(x) \ (((x) >> BIT_SHIFT_WAKE_MAX_F2F) & BIT_MASK_WAKE_MAX_F2F) #define BIT_SET_WAKE_MAX_F2F(x, v) \ (BIT_CLEAR_WAKE_MAX_F2F(x) | BIT_WAKE_MAX_F2F(v)) #define BIT_SHIFT_WAKE_MIN_F2F 8 #define BIT_MASK_WAKE_MIN_F2F 0x7 #define BIT_WAKE_MIN_F2F(x) \ (((x) & BIT_MASK_WAKE_MIN_F2F) << BIT_SHIFT_WAKE_MIN_F2F) #define BITS_WAKE_MIN_F2F (BIT_MASK_WAKE_MIN_F2F << BIT_SHIFT_WAKE_MIN_F2F) #define BIT_CLEAR_WAKE_MIN_F2F(x) ((x) & (~BITS_WAKE_MIN_F2F)) #define BIT_GET_WAKE_MIN_F2F(x) \ (((x) >> BIT_SHIFT_WAKE_MIN_F2F) & BIT_MASK_WAKE_MIN_F2F) #define BIT_SET_WAKE_MIN_F2F(x, v) \ (BIT_CLEAR_WAKE_MIN_F2F(x) | BIT_WAKE_MIN_F2F(v)) #define BIT_APP_CPU_ACT_V1 BIT(3) #define BIT_APP_OBFF_V1 BIT(2) #define BIT_APP_IDLE_V1 BIT(1) #define BIT_APP_INIT_V1 BIT(0) /* 2 REG_OBFF_CTRL2_TIMER (Offset 0x079C) */ #define BIT_SHIFT_RX_HIGH_TIMER_IDX 24 #define BIT_MASK_RX_HIGH_TIMER_IDX 0x7 #define BIT_RX_HIGH_TIMER_IDX(x) \ (((x) & BIT_MASK_RX_HIGH_TIMER_IDX) << BIT_SHIFT_RX_HIGH_TIMER_IDX) #define BITS_RX_HIGH_TIMER_IDX \ (BIT_MASK_RX_HIGH_TIMER_IDX << BIT_SHIFT_RX_HIGH_TIMER_IDX) #define BIT_CLEAR_RX_HIGH_TIMER_IDX(x) ((x) & (~BITS_RX_HIGH_TIMER_IDX)) #define BIT_GET_RX_HIGH_TIMER_IDX(x) \ (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX) & BIT_MASK_RX_HIGH_TIMER_IDX) #define BIT_SET_RX_HIGH_TIMER_IDX(x, v) \ (BIT_CLEAR_RX_HIGH_TIMER_IDX(x) | BIT_RX_HIGH_TIMER_IDX(v)) #define BIT_SHIFT_RX_MED_TIMER_IDX 16 #define BIT_MASK_RX_MED_TIMER_IDX 0x7 #define BIT_RX_MED_TIMER_IDX(x) \ (((x) & BIT_MASK_RX_MED_TIMER_IDX) << BIT_SHIFT_RX_MED_TIMER_IDX) #define BITS_RX_MED_TIMER_IDX \ (BIT_MASK_RX_MED_TIMER_IDX << BIT_SHIFT_RX_MED_TIMER_IDX) #define BIT_CLEAR_RX_MED_TIMER_IDX(x) ((x) & (~BITS_RX_MED_TIMER_IDX)) #define BIT_GET_RX_MED_TIMER_IDX(x) \ (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX) & BIT_MASK_RX_MED_TIMER_IDX) #define BIT_SET_RX_MED_TIMER_IDX(x, v) \ (BIT_CLEAR_RX_MED_TIMER_IDX(x) | BIT_RX_MED_TIMER_IDX(v)) #define BIT_SHIFT_RX_LOW_TIMER_IDX 8 #define BIT_MASK_RX_LOW_TIMER_IDX 0x7 #define BIT_RX_LOW_TIMER_IDX(x) \ (((x) & BIT_MASK_RX_LOW_TIMER_IDX) << BIT_SHIFT_RX_LOW_TIMER_IDX) #define BITS_RX_LOW_TIMER_IDX \ (BIT_MASK_RX_LOW_TIMER_IDX << BIT_SHIFT_RX_LOW_TIMER_IDX) #define BIT_CLEAR_RX_LOW_TIMER_IDX(x) ((x) & (~BITS_RX_LOW_TIMER_IDX)) #define BIT_GET_RX_LOW_TIMER_IDX(x) \ (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX) & BIT_MASK_RX_LOW_TIMER_IDX) #define BIT_SET_RX_LOW_TIMER_IDX(x, v) \ (BIT_CLEAR_RX_LOW_TIMER_IDX(x) | BIT_RX_LOW_TIMER_IDX(v)) #define BIT_SHIFT_OBFF_INT_TIMER_IDX 0 #define BIT_MASK_OBFF_INT_TIMER_IDX 0x7 #define BIT_OBFF_INT_TIMER_IDX(x) \ (((x) & BIT_MASK_OBFF_INT_TIMER_IDX) << BIT_SHIFT_OBFF_INT_TIMER_IDX) #define BITS_OBFF_INT_TIMER_IDX \ (BIT_MASK_OBFF_INT_TIMER_IDX << BIT_SHIFT_OBFF_INT_TIMER_IDX) #define BIT_CLEAR_OBFF_INT_TIMER_IDX(x) ((x) & (~BITS_OBFF_INT_TIMER_IDX)) #define BIT_GET_OBFF_INT_TIMER_IDX(x) \ (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX) & BIT_MASK_OBFF_INT_TIMER_IDX) #define BIT_SET_OBFF_INT_TIMER_IDX(x, v) \ (BIT_CLEAR_OBFF_INT_TIMER_IDX(x) | BIT_OBFF_INT_TIMER_IDX(v)) /* 2 REG_LTR_CTRL_BASIC (Offset 0x07A0) */ #define BIT_LTR_EN_V1 BIT(31) #define BIT_LTR_HW_EN_V1 BIT(30) #define BIT_LRT_ACT_CTS_EN BIT(29) #define BIT_LTR_ACT_RXPKT_EN BIT(28) #define BIT_LTR_ACT_RXDMA_EN BIT(27) #define BIT_LTR_IDLE_NO_SNOOP BIT(26) #define BIT_SPDUP_MGTPKT BIT(25) #define BIT_RX_AGG_EN BIT(24) #define BIT_APP_LTR_ACT BIT(23) #define BIT_APP_LTR_IDLE BIT(22) #define BIT_SHIFT_HIGH_RATE_TRIG_SEL 20 #define BIT_MASK_HIGH_RATE_TRIG_SEL 0x3 #define BIT_HIGH_RATE_TRIG_SEL(x) \ (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL) << BIT_SHIFT_HIGH_RATE_TRIG_SEL) #define BITS_HIGH_RATE_TRIG_SEL \ (BIT_MASK_HIGH_RATE_TRIG_SEL << BIT_SHIFT_HIGH_RATE_TRIG_SEL) #define BIT_CLEAR_HIGH_RATE_TRIG_SEL(x) ((x) & (~BITS_HIGH_RATE_TRIG_SEL)) #define BIT_GET_HIGH_RATE_TRIG_SEL(x) \ (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL) & BIT_MASK_HIGH_RATE_TRIG_SEL) #define BIT_SET_HIGH_RATE_TRIG_SEL(x, v) \ (BIT_CLEAR_HIGH_RATE_TRIG_SEL(x) | BIT_HIGH_RATE_TRIG_SEL(v)) #define BIT_SHIFT_MED_RATE_TRIG_SEL 18 #define BIT_MASK_MED_RATE_TRIG_SEL 0x3 #define BIT_MED_RATE_TRIG_SEL(x) \ (((x) & BIT_MASK_MED_RATE_TRIG_SEL) << BIT_SHIFT_MED_RATE_TRIG_SEL) #define BITS_MED_RATE_TRIG_SEL \ (BIT_MASK_MED_RATE_TRIG_SEL << BIT_SHIFT_MED_RATE_TRIG_SEL) #define BIT_CLEAR_MED_RATE_TRIG_SEL(x) ((x) & (~BITS_MED_RATE_TRIG_SEL)) #define BIT_GET_MED_RATE_TRIG_SEL(x) \ (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL) & BIT_MASK_MED_RATE_TRIG_SEL) #define BIT_SET_MED_RATE_TRIG_SEL(x, v) \ (BIT_CLEAR_MED_RATE_TRIG_SEL(x) | BIT_MED_RATE_TRIG_SEL(v)) #define BIT_SHIFT_LOW_RATE_TRIG_SEL 16 #define BIT_MASK_LOW_RATE_TRIG_SEL 0x3 #define BIT_LOW_RATE_TRIG_SEL(x) \ (((x) & BIT_MASK_LOW_RATE_TRIG_SEL) << BIT_SHIFT_LOW_RATE_TRIG_SEL) #define BITS_LOW_RATE_TRIG_SEL \ (BIT_MASK_LOW_RATE_TRIG_SEL << BIT_SHIFT_LOW_RATE_TRIG_SEL) #define BIT_CLEAR_LOW_RATE_TRIG_SEL(x) ((x) & (~BITS_LOW_RATE_TRIG_SEL)) #define BIT_GET_LOW_RATE_TRIG_SEL(x) \ (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL) & BIT_MASK_LOW_RATE_TRIG_SEL) #define BIT_SET_LOW_RATE_TRIG_SEL(x, v) \ (BIT_CLEAR_LOW_RATE_TRIG_SEL(x) | BIT_LOW_RATE_TRIG_SEL(v)) #define BIT_SHIFT_HIGH_RATE_BD_IDX 8 #define BIT_MASK_HIGH_RATE_BD_IDX 0x7f #define BIT_HIGH_RATE_BD_IDX(x) \ (((x) & BIT_MASK_HIGH_RATE_BD_IDX) << BIT_SHIFT_HIGH_RATE_BD_IDX) #define BITS_HIGH_RATE_BD_IDX \ (BIT_MASK_HIGH_RATE_BD_IDX << BIT_SHIFT_HIGH_RATE_BD_IDX) #define BIT_CLEAR_HIGH_RATE_BD_IDX(x) ((x) & (~BITS_HIGH_RATE_BD_IDX)) #define BIT_GET_HIGH_RATE_BD_IDX(x) \ (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX) & BIT_MASK_HIGH_RATE_BD_IDX) #define BIT_SET_HIGH_RATE_BD_IDX(x, v) \ (BIT_CLEAR_HIGH_RATE_BD_IDX(x) | BIT_HIGH_RATE_BD_IDX(v)) #define BIT_SHIFT_LOW_RATE_BD_IDX 0 #define BIT_MASK_LOW_RATE_BD_IDX 0x7f #define BIT_LOW_RATE_BD_IDX(x) \ (((x) & BIT_MASK_LOW_RATE_BD_IDX) << BIT_SHIFT_LOW_RATE_BD_IDX) #define BITS_LOW_RATE_BD_IDX \ (BIT_MASK_LOW_RATE_BD_IDX << BIT_SHIFT_LOW_RATE_BD_IDX) #define BIT_CLEAR_LOW_RATE_BD_IDX(x) ((x) & (~BITS_LOW_RATE_BD_IDX)) #define BIT_GET_LOW_RATE_BD_IDX(x) \ (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX) & BIT_MASK_LOW_RATE_BD_IDX) #define BIT_SET_LOW_RATE_BD_IDX(x, v) \ (BIT_CLEAR_LOW_RATE_BD_IDX(x) | BIT_LOW_RATE_BD_IDX(v)) /* 2 REG_LTR_CTRL2_TIMER_THRESHOLD (Offset 0x07A4) */ #define BIT_SHIFT_RX_EMPTY_TIMER_IDX 24 #define BIT_MASK_RX_EMPTY_TIMER_IDX 0x7 #define BIT_RX_EMPTY_TIMER_IDX(x) \ (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX) << BIT_SHIFT_RX_EMPTY_TIMER_IDX) #define BITS_RX_EMPTY_TIMER_IDX \ (BIT_MASK_RX_EMPTY_TIMER_IDX << BIT_SHIFT_RX_EMPTY_TIMER_IDX) #define BIT_CLEAR_RX_EMPTY_TIMER_IDX(x) ((x) & (~BITS_RX_EMPTY_TIMER_IDX)) #define BIT_GET_RX_EMPTY_TIMER_IDX(x) \ (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX) & BIT_MASK_RX_EMPTY_TIMER_IDX) #define BIT_SET_RX_EMPTY_TIMER_IDX(x, v) \ (BIT_CLEAR_RX_EMPTY_TIMER_IDX(x) | BIT_RX_EMPTY_TIMER_IDX(v)) #define BIT_SHIFT_RX_AFULL_TH_IDX 20 #define BIT_MASK_RX_AFULL_TH_IDX 0x7 #define BIT_RX_AFULL_TH_IDX(x) \ (((x) & BIT_MASK_RX_AFULL_TH_IDX) << BIT_SHIFT_RX_AFULL_TH_IDX) #define BITS_RX_AFULL_TH_IDX \ (BIT_MASK_RX_AFULL_TH_IDX << BIT_SHIFT_RX_AFULL_TH_IDX) #define BIT_CLEAR_RX_AFULL_TH_IDX(x) ((x) & (~BITS_RX_AFULL_TH_IDX)) #define BIT_GET_RX_AFULL_TH_IDX(x) \ (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX) & BIT_MASK_RX_AFULL_TH_IDX) #define BIT_SET_RX_AFULL_TH_IDX(x, v) \ (BIT_CLEAR_RX_AFULL_TH_IDX(x) | BIT_RX_AFULL_TH_IDX(v)) #define BIT_SHIFT_RX_HIGH_TH_IDX 16 #define BIT_MASK_RX_HIGH_TH_IDX 0x7 #define BIT_RX_HIGH_TH_IDX(x) \ (((x) & BIT_MASK_RX_HIGH_TH_IDX) << BIT_SHIFT_RX_HIGH_TH_IDX) #define BITS_RX_HIGH_TH_IDX \ (BIT_MASK_RX_HIGH_TH_IDX << BIT_SHIFT_RX_HIGH_TH_IDX) #define BIT_CLEAR_RX_HIGH_TH_IDX(x) ((x) & (~BITS_RX_HIGH_TH_IDX)) #define BIT_GET_RX_HIGH_TH_IDX(x) \ (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX) & BIT_MASK_RX_HIGH_TH_IDX) #define BIT_SET_RX_HIGH_TH_IDX(x, v) \ (BIT_CLEAR_RX_HIGH_TH_IDX(x) | BIT_RX_HIGH_TH_IDX(v)) #define BIT_SHIFT_RX_MED_TH_IDX 12 #define BIT_MASK_RX_MED_TH_IDX 0x7 #define BIT_RX_MED_TH_IDX(x) \ (((x) & BIT_MASK_RX_MED_TH_IDX) << BIT_SHIFT_RX_MED_TH_IDX) #define BITS_RX_MED_TH_IDX (BIT_MASK_RX_MED_TH_IDX << BIT_SHIFT_RX_MED_TH_IDX) #define BIT_CLEAR_RX_MED_TH_IDX(x) ((x) & (~BITS_RX_MED_TH_IDX)) #define BIT_GET_RX_MED_TH_IDX(x) \ (((x) >> BIT_SHIFT_RX_MED_TH_IDX) & BIT_MASK_RX_MED_TH_IDX) #define BIT_SET_RX_MED_TH_IDX(x, v) \ (BIT_CLEAR_RX_MED_TH_IDX(x) | BIT_RX_MED_TH_IDX(v)) #define BIT_SHIFT_RX_LOW_TH_IDX 8 #define BIT_MASK_RX_LOW_TH_IDX 0x7 #define BIT_RX_LOW_TH_IDX(x) \ (((x) & BIT_MASK_RX_LOW_TH_IDX) << BIT_SHIFT_RX_LOW_TH_IDX) #define BITS_RX_LOW_TH_IDX (BIT_MASK_RX_LOW_TH_IDX << BIT_SHIFT_RX_LOW_TH_IDX) #define BIT_CLEAR_RX_LOW_TH_IDX(x) ((x) & (~BITS_RX_LOW_TH_IDX)) #define BIT_GET_RX_LOW_TH_IDX(x) \ (((x) >> BIT_SHIFT_RX_LOW_TH_IDX) & BIT_MASK_RX_LOW_TH_IDX) #define BIT_SET_RX_LOW_TH_IDX(x, v) \ (BIT_CLEAR_RX_LOW_TH_IDX(x) | BIT_RX_LOW_TH_IDX(v)) #define BIT_SHIFT_LTR_SPACE_IDX 4 #define BIT_MASK_LTR_SPACE_IDX 0x3 #define BIT_LTR_SPACE_IDX(x) \ (((x) & BIT_MASK_LTR_SPACE_IDX) << BIT_SHIFT_LTR_SPACE_IDX) #define BITS_LTR_SPACE_IDX (BIT_MASK_LTR_SPACE_IDX << BIT_SHIFT_LTR_SPACE_IDX) #define BIT_CLEAR_LTR_SPACE_IDX(x) ((x) & (~BITS_LTR_SPACE_IDX)) #define BIT_GET_LTR_SPACE_IDX(x) \ (((x) >> BIT_SHIFT_LTR_SPACE_IDX) & BIT_MASK_LTR_SPACE_IDX) #define BIT_SET_LTR_SPACE_IDX(x, v) \ (BIT_CLEAR_LTR_SPACE_IDX(x) | BIT_LTR_SPACE_IDX(v)) #define BIT_SHIFT_LTR_IDLE_TIMER_IDX 0 #define BIT_MASK_LTR_IDLE_TIMER_IDX 0x7 #define BIT_LTR_IDLE_TIMER_IDX(x) \ (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX) << BIT_SHIFT_LTR_IDLE_TIMER_IDX) #define BITS_LTR_IDLE_TIMER_IDX \ (BIT_MASK_LTR_IDLE_TIMER_IDX << BIT_SHIFT_LTR_IDLE_TIMER_IDX) #define BIT_CLEAR_LTR_IDLE_TIMER_IDX(x) ((x) & (~BITS_LTR_IDLE_TIMER_IDX)) #define BIT_GET_LTR_IDLE_TIMER_IDX(x) \ (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX) & BIT_MASK_LTR_IDLE_TIMER_IDX) #define BIT_SET_LTR_IDLE_TIMER_IDX(x, v) \ (BIT_CLEAR_LTR_IDLE_TIMER_IDX(x) | BIT_LTR_IDLE_TIMER_IDX(v)) /* 2 REG_LTR_IDLE_LATENCY_V1 (Offset 0x07A8) */ #define BIT_SHIFT_LTR_IDLE_L 0 #define BIT_MASK_LTR_IDLE_L 0xffffffffL #define BIT_LTR_IDLE_L(x) (((x) & BIT_MASK_LTR_IDLE_L) << BIT_SHIFT_LTR_IDLE_L) #define BITS_LTR_IDLE_L (BIT_MASK_LTR_IDLE_L << BIT_SHIFT_LTR_IDLE_L) #define BIT_CLEAR_LTR_IDLE_L(x) ((x) & (~BITS_LTR_IDLE_L)) #define BIT_GET_LTR_IDLE_L(x) \ (((x) >> BIT_SHIFT_LTR_IDLE_L) & BIT_MASK_LTR_IDLE_L) #define BIT_SET_LTR_IDLE_L(x, v) (BIT_CLEAR_LTR_IDLE_L(x) | BIT_LTR_IDLE_L(v)) /* 2 REG_LTR_ACTIVE_LATENCY_V1 (Offset 0x07AC) */ #define BIT_SHIFT_LTR_ACT_L 0 #define BIT_MASK_LTR_ACT_L 0xffffffffL #define BIT_LTR_ACT_L(x) (((x) & BIT_MASK_LTR_ACT_L) << BIT_SHIFT_LTR_ACT_L) #define BITS_LTR_ACT_L (BIT_MASK_LTR_ACT_L << BIT_SHIFT_LTR_ACT_L) #define BIT_CLEAR_LTR_ACT_L(x) ((x) & (~BITS_LTR_ACT_L)) #define BIT_GET_LTR_ACT_L(x) (((x) >> BIT_SHIFT_LTR_ACT_L) & BIT_MASK_LTR_ACT_L) #define BIT_SET_LTR_ACT_L(x, v) (BIT_CLEAR_LTR_ACT_L(x) | BIT_LTR_ACT_L(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_LTR_ACTIVE_LATENCY_V1 (Offset 0x07AC) */ #define BIT_SHIFT_ANT_ADDR2_1 0 #define BIT_MASK_ANT_ADDR2_1 0xffffffffL #define BIT_ANT_ADDR2_1(x) \ (((x) & BIT_MASK_ANT_ADDR2_1) << BIT_SHIFT_ANT_ADDR2_1) #define BITS_ANT_ADDR2_1 (BIT_MASK_ANT_ADDR2_1 << BIT_SHIFT_ANT_ADDR2_1) #define BIT_CLEAR_ANT_ADDR2_1(x) ((x) & (~BITS_ANT_ADDR2_1)) #define BIT_GET_ANT_ADDR2_1(x) \ (((x) >> BIT_SHIFT_ANT_ADDR2_1) & BIT_MASK_ANT_ADDR2_1) #define BIT_SET_ANT_ADDR2_1(x, v) \ (BIT_CLEAR_ANT_ADDR2_1(x) | BIT_ANT_ADDR2_1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER (Offset 0x07B0) */ #define BIT_APPEND_MACID_IN_RESP_EN BIT(50) #define BIT_ADDR2_MATCH_EN BIT(49) #define BIT_ANTTRN_EN BIT(48) #define BIT_SHIFT_TRAIN_STA_ADDR 0 #define BIT_MASK_TRAIN_STA_ADDR 0xffffffffffffL #define BIT_TRAIN_STA_ADDR(x) \ (((x) & BIT_MASK_TRAIN_STA_ADDR) << BIT_SHIFT_TRAIN_STA_ADDR) #define BITS_TRAIN_STA_ADDR \ (BIT_MASK_TRAIN_STA_ADDR << BIT_SHIFT_TRAIN_STA_ADDR) #define BIT_CLEAR_TRAIN_STA_ADDR(x) ((x) & (~BITS_TRAIN_STA_ADDR)) #define BIT_GET_TRAIN_STA_ADDR(x) \ (((x) >> BIT_SHIFT_TRAIN_STA_ADDR) & BIT_MASK_TRAIN_STA_ADDR) #define BIT_SET_TRAIN_STA_ADDR(x, v) \ (BIT_CLEAR_TRAIN_STA_ADDR(x) | BIT_TRAIN_STA_ADDR(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER (Offset 0x07B0) */ #define BIT_SHIFT_TRAIN_STA_ADDR_0 0 #define BIT_MASK_TRAIN_STA_ADDR_0 0xffffffffL #define BIT_TRAIN_STA_ADDR_0(x) \ (((x) & BIT_MASK_TRAIN_STA_ADDR_0) << BIT_SHIFT_TRAIN_STA_ADDR_0) #define BITS_TRAIN_STA_ADDR_0 \ (BIT_MASK_TRAIN_STA_ADDR_0 << BIT_SHIFT_TRAIN_STA_ADDR_0) #define BIT_CLEAR_TRAIN_STA_ADDR_0(x) ((x) & (~BITS_TRAIN_STA_ADDR_0)) #define BIT_GET_TRAIN_STA_ADDR_0(x) \ (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0) & BIT_MASK_TRAIN_STA_ADDR_0) #define BIT_SET_TRAIN_STA_ADDR_0(x, v) \ (BIT_CLEAR_TRAIN_STA_ADDR_0(x) | BIT_TRAIN_STA_ADDR_0(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SMART_ANT_CTRL (Offset 0x07B4) */ #define BIT_SHIFT_ANT_ADDR2_2 0 #define BIT_MASK_ANT_ADDR2_2 0xffff #define BIT_ANT_ADDR2_2(x) \ (((x) & BIT_MASK_ANT_ADDR2_2) << BIT_SHIFT_ANT_ADDR2_2) #define BITS_ANT_ADDR2_2 (BIT_MASK_ANT_ADDR2_2 << BIT_SHIFT_ANT_ADDR2_2) #define BIT_CLEAR_ANT_ADDR2_2(x) ((x) & (~BITS_ANT_ADDR2_2)) #define BIT_GET_ANT_ADDR2_2(x) \ (((x) >> BIT_SHIFT_ANT_ADDR2_2) & BIT_MASK_ANT_ADDR2_2) #define BIT_SET_ANT_ADDR2_2(x, v) \ (BIT_CLEAR_ANT_ADDR2_2(x) | BIT_ANT_ADDR2_2(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1 (Offset 0x07B4) */ #define BIT_SHIFT_TRAIN_STA_ADDR_1 0 #define BIT_MASK_TRAIN_STA_ADDR_1 0xffff #define BIT_TRAIN_STA_ADDR_1(x) \ (((x) & BIT_MASK_TRAIN_STA_ADDR_1) << BIT_SHIFT_TRAIN_STA_ADDR_1) #define BITS_TRAIN_STA_ADDR_1 \ (BIT_MASK_TRAIN_STA_ADDR_1 << BIT_SHIFT_TRAIN_STA_ADDR_1) #define BIT_CLEAR_TRAIN_STA_ADDR_1(x) ((x) & (~BITS_TRAIN_STA_ADDR_1)) #define BIT_GET_TRAIN_STA_ADDR_1(x) \ (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1) & BIT_MASK_TRAIN_STA_ADDR_1) #define BIT_SET_TRAIN_STA_ADDR_1(x, v) \ (BIT_CLEAR_TRAIN_STA_ADDR_1(x) | BIT_TRAIN_STA_ADDR_1(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_PKTCNT_RWD (Offset 0x07B8) */ #define BIT_SHIFT_PKTCNT_BSSIDMAP 4 #define BIT_MASK_PKTCNT_BSSIDMAP 0xf #define BIT_PKTCNT_BSSIDMAP(x) \ (((x) & BIT_MASK_PKTCNT_BSSIDMAP) << BIT_SHIFT_PKTCNT_BSSIDMAP) #define BITS_PKTCNT_BSSIDMAP \ (BIT_MASK_PKTCNT_BSSIDMAP << BIT_SHIFT_PKTCNT_BSSIDMAP) #define BIT_CLEAR_PKTCNT_BSSIDMAP(x) ((x) & (~BITS_PKTCNT_BSSIDMAP)) #define BIT_GET_PKTCNT_BSSIDMAP(x) \ (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP) & BIT_MASK_PKTCNT_BSSIDMAP) #define BIT_SET_PKTCNT_BSSIDMAP(x, v) \ (BIT_CLEAR_PKTCNT_BSSIDMAP(x) | BIT_PKTCNT_BSSIDMAP(v)) #define BIT_PKTCNT_CNTRST BIT(1) #define BIT_PKTCNT_CNTEN BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CONTROL_FRAME_REPORT (Offset 0x07B8) */ #define BIT_SHIFT_CONTROL_FRAME_REPORT 0 #define BIT_MASK_CONTROL_FRAME_REPORT 0xffffffffL #define BIT_CONTROL_FRAME_REPORT(x) \ (((x) & BIT_MASK_CONTROL_FRAME_REPORT) \ << BIT_SHIFT_CONTROL_FRAME_REPORT) #define BITS_CONTROL_FRAME_REPORT \ (BIT_MASK_CONTROL_FRAME_REPORT << BIT_SHIFT_CONTROL_FRAME_REPORT) #define BIT_CLEAR_CONTROL_FRAME_REPORT(x) ((x) & (~BITS_CONTROL_FRAME_REPORT)) #define BIT_GET_CONTROL_FRAME_REPORT(x) \ (((x) >> BIT_SHIFT_CONTROL_FRAME_REPORT) & \ BIT_MASK_CONTROL_FRAME_REPORT) #define BIT_SET_CONTROL_FRAME_REPORT(x, v) \ (BIT_CLEAR_CONTROL_FRAME_REPORT(x) | BIT_CONTROL_FRAME_REPORT(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_PKTCNT_CTRL (Offset 0x07BC) */ #define BIT_WMAC_PKTCNT_TRST BIT(9) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CONTROL_FRAME_CNT_CTRL (Offset 0x07BC) */ #define BIT_ALLCNTRST BIT(9) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_PKTCNT_CTRL (Offset 0x07BC) */ #define BIT_WMAC_PKTCNT_FEN BIT(8) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CONTROL_FRAME_CNT_CTRL (Offset 0x07BC) */ #define BIT__ALLCNTEN BIT(8) #define BIT_SHIFT_ADDR 4 #define BIT_MASK_ADDR 0xf #define BIT_ADDR(x) (((x) & BIT_MASK_ADDR) << BIT_SHIFT_ADDR) #define BITS_ADDR (BIT_MASK_ADDR << BIT_SHIFT_ADDR) #define BIT_CLEAR_ADDR(x) ((x) & (~BITS_ADDR)) #define BIT_GET_ADDR(x) (((x) >> BIT_SHIFT_ADDR) & BIT_MASK_ADDR) #define BIT_SET_ADDR(x, v) (BIT_CLEAR_ADDR(x) | BIT_ADDR(v)) #endif #if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WMAC_PKTCNT_CTRL (Offset 0x07BC) */ #define BIT_SHIFT_WMAC_PKTCNT_CFGAD 0 #define BIT_MASK_WMAC_PKTCNT_CFGAD 0xff #define BIT_WMAC_PKTCNT_CFGAD(x) \ (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD) << BIT_SHIFT_WMAC_PKTCNT_CFGAD) #define BITS_WMAC_PKTCNT_CFGAD \ (BIT_MASK_WMAC_PKTCNT_CFGAD << BIT_SHIFT_WMAC_PKTCNT_CFGAD) #define BIT_CLEAR_WMAC_PKTCNT_CFGAD(x) ((x) & (~BITS_WMAC_PKTCNT_CFGAD)) #define BIT_GET_WMAC_PKTCNT_CFGAD(x) \ (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD) & BIT_MASK_WMAC_PKTCNT_CFGAD) #define BIT_SET_WMAC_PKTCNT_CFGAD(x, v) \ (BIT_CLEAR_WMAC_PKTCNT_CFGAD(x) | BIT_WMAC_PKTCNT_CFGAD(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CONTROL_FRAME_CNT_CTRL (Offset 0x07BC) */ #define BIT_SHIFT_CTRL_SEL 0 #define BIT_MASK_CTRL_SEL 0xf #define BIT_CTRL_SEL(x) (((x) & BIT_MASK_CTRL_SEL) << BIT_SHIFT_CTRL_SEL) #define BITS_CTRL_SEL (BIT_MASK_CTRL_SEL << BIT_SHIFT_CTRL_SEL) #define BIT_CLEAR_CTRL_SEL(x) ((x) & (~BITS_CTRL_SEL)) #define BIT_GET_CTRL_SEL(x) (((x) >> BIT_SHIFT_CTRL_SEL) & BIT_MASK_CTRL_SEL) #define BIT_SET_CTRL_SEL(x, v) (BIT_CLEAR_CTRL_SEL(x) | BIT_CTRL_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_IQ_DUMP (Offset 0x07C0) */ #define BIT_SHIFT_R_WMAC_MATCH_REF_MAC (64 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_MATCH_REF_MAC 0xffffffffL #define BIT_R_WMAC_MATCH_REF_MAC(x) \ (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC) \ << BIT_SHIFT_R_WMAC_MATCH_REF_MAC) #define BITS_R_WMAC_MATCH_REF_MAC \ (BIT_MASK_R_WMAC_MATCH_REF_MAC << BIT_SHIFT_R_WMAC_MATCH_REF_MAC) #define BIT_CLEAR_R_WMAC_MATCH_REF_MAC(x) ((x) & (~BITS_R_WMAC_MATCH_REF_MAC)) #define BIT_GET_R_WMAC_MATCH_REF_MAC(x) \ (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC) & \ BIT_MASK_R_WMAC_MATCH_REF_MAC) #define BIT_SET_R_WMAC_MATCH_REF_MAC(x, v) \ (BIT_CLEAR_R_WMAC_MATCH_REF_MAC(x) | BIT_R_WMAC_MATCH_REF_MAC(v)) #define BIT_SHIFT_R_WMAC_RX_FIL_LEN (64 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_RX_FIL_LEN 0xffff #define BIT_R_WMAC_RX_FIL_LEN(x) \ (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN) << BIT_SHIFT_R_WMAC_RX_FIL_LEN) #define BITS_R_WMAC_RX_FIL_LEN \ (BIT_MASK_R_WMAC_RX_FIL_LEN << BIT_SHIFT_R_WMAC_RX_FIL_LEN) #define BIT_CLEAR_R_WMAC_RX_FIL_LEN(x) ((x) & (~BITS_R_WMAC_RX_FIL_LEN)) #define BIT_GET_R_WMAC_RX_FIL_LEN(x) \ (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN) & BIT_MASK_R_WMAC_RX_FIL_LEN) #define BIT_SET_R_WMAC_RX_FIL_LEN(x, v) \ (BIT_CLEAR_R_WMAC_RX_FIL_LEN(x) | BIT_R_WMAC_RX_FIL_LEN(v)) #define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH (56 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_RXFIFO_FULL_TH 0xff #define BIT_R_WMAC_RXFIFO_FULL_TH(x) \ (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH) \ << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) #define BITS_R_WMAC_RXFIFO_FULL_TH \ (BIT_MASK_R_WMAC_RXFIFO_FULL_TH << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) #define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH(x) ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH)) #define BIT_GET_R_WMAC_RXFIFO_FULL_TH(x) \ (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) & \ BIT_MASK_R_WMAC_RXFIFO_FULL_TH) #define BIT_SET_R_WMAC_RXFIFO_FULL_TH(x, v) \ (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH(x) | BIT_R_WMAC_RXFIFO_FULL_TH(v)) #define BIT_R_WMAC_SRCH_TXRPT_TYPE BIT(51) #define BIT_R_WMAC_NDP_RST BIT(50) #define BIT_R_WMAC_POWINT_EN BIT(49) #define BIT_R_WMAC_SRCH_TXRPT_PERPKT BIT(48) #define BIT_R_WMAC_SRCH_TXRPT_MID BIT(47) #define BIT_R_WMAC_PFIN_TOEN BIT(46) #define BIT_R_WMAC_FIL_SECERR BIT(45) #define BIT_R_WMAC_FIL_CTLPKTLEN BIT(44) #define BIT_R_WMAC_FIL_FCTYPE BIT(43) #define BIT_R_WMAC_FIL_FCPROVER BIT(42) #define BIT_R_WMAC_PHYSTS_SNIF BIT(41) #define BIT_R_WMAC_PHYSTS_PLCP BIT(40) #define BIT_R_MAC_TCR_VBONF_RD BIT(39) #define BIT_R_WMAC_TCR_MPAR_NDP BIT(38) #define BIT_R_WMAC_NDP_FILTER BIT(37) #define BIT_R_WMAC_RXLEN_SEL BIT(36) #define BIT_R_WMAC_RXLEN_SEL1 BIT(35) #define BIT_R_OFDM_FILTER BIT(34) #define BIT_R_WMAC_CHK_OFDM_LEN BIT(33) #define BIT_SHIFT_R_WMAC_MASK_LA_MAC (32 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_MASK_LA_MAC 0xffffffffL #define BIT_R_WMAC_MASK_LA_MAC(x) \ (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC) << BIT_SHIFT_R_WMAC_MASK_LA_MAC) #define BITS_R_WMAC_MASK_LA_MAC \ (BIT_MASK_R_WMAC_MASK_LA_MAC << BIT_SHIFT_R_WMAC_MASK_LA_MAC) #define BIT_CLEAR_R_WMAC_MASK_LA_MAC(x) ((x) & (~BITS_R_WMAC_MASK_LA_MAC)) #define BIT_GET_R_WMAC_MASK_LA_MAC(x) \ (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC) & BIT_MASK_R_WMAC_MASK_LA_MAC) #define BIT_SET_R_WMAC_MASK_LA_MAC(x, v) \ (BIT_CLEAR_R_WMAC_MASK_LA_MAC(x) | BIT_R_WMAC_MASK_LA_MAC(v)) #define BIT_R_WMAC_CHK_CCK_LEN BIT(32) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_IQ_DUMP (Offset 0x07C0) */ #define BIT_SHIFT_DUMP_OK_ADDR 16 #define BIT_MASK_DUMP_OK_ADDR 0xffff #define BIT_DUMP_OK_ADDR(x) \ (((x) & BIT_MASK_DUMP_OK_ADDR) << BIT_SHIFT_DUMP_OK_ADDR) #define BITS_DUMP_OK_ADDR (BIT_MASK_DUMP_OK_ADDR << BIT_SHIFT_DUMP_OK_ADDR) #define BIT_CLEAR_DUMP_OK_ADDR(x) ((x) & (~BITS_DUMP_OK_ADDR)) #define BIT_GET_DUMP_OK_ADDR(x) \ (((x) >> BIT_SHIFT_DUMP_OK_ADDR) & BIT_MASK_DUMP_OK_ADDR) #define BIT_SET_DUMP_OK_ADDR(x, v) \ (BIT_CLEAR_DUMP_OK_ADDR(x) | BIT_DUMP_OK_ADDR(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_IQ_DUMP (Offset 0x07C0) */ #define BIT_MACDBG_TRIG_IQDUMP BIT(15) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_IQ_DUMP (Offset 0x07C0) */ #define BIT_SHIFT_R_TRIG_TIME_SEL 8 #define BIT_MASK_R_TRIG_TIME_SEL 0x7f #define BIT_R_TRIG_TIME_SEL(x) \ (((x) & BIT_MASK_R_TRIG_TIME_SEL) << BIT_SHIFT_R_TRIG_TIME_SEL) #define BITS_R_TRIG_TIME_SEL \ (BIT_MASK_R_TRIG_TIME_SEL << BIT_SHIFT_R_TRIG_TIME_SEL) #define BIT_CLEAR_R_TRIG_TIME_SEL(x) ((x) & (~BITS_R_TRIG_TIME_SEL)) #define BIT_GET_R_TRIG_TIME_SEL(x) \ (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL) & BIT_MASK_R_TRIG_TIME_SEL) #define BIT_SET_R_TRIG_TIME_SEL(x, v) \ (BIT_CLEAR_R_TRIG_TIME_SEL(x) | BIT_R_TRIG_TIME_SEL(v)) #define BIT_SHIFT_R_MAC_TRIG_SEL 6 #define BIT_MASK_R_MAC_TRIG_SEL 0x3 #define BIT_R_MAC_TRIG_SEL(x) \ (((x) & BIT_MASK_R_MAC_TRIG_SEL) << BIT_SHIFT_R_MAC_TRIG_SEL) #define BITS_R_MAC_TRIG_SEL \ (BIT_MASK_R_MAC_TRIG_SEL << BIT_SHIFT_R_MAC_TRIG_SEL) #define BIT_CLEAR_R_MAC_TRIG_SEL(x) ((x) & (~BITS_R_MAC_TRIG_SEL)) #define BIT_GET_R_MAC_TRIG_SEL(x) \ (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL) & BIT_MASK_R_MAC_TRIG_SEL) #define BIT_SET_R_MAC_TRIG_SEL(x, v) \ (BIT_CLEAR_R_MAC_TRIG_SEL(x) | BIT_R_MAC_TRIG_SEL(v)) #define BIT_MAC_TRIG_REG BIT(5) #define BIT_SHIFT_R_LEVEL_PULSE_SEL 3 #define BIT_MASK_R_LEVEL_PULSE_SEL 0x3 #define BIT_R_LEVEL_PULSE_SEL(x) \ (((x) & BIT_MASK_R_LEVEL_PULSE_SEL) << BIT_SHIFT_R_LEVEL_PULSE_SEL) #define BITS_R_LEVEL_PULSE_SEL \ (BIT_MASK_R_LEVEL_PULSE_SEL << BIT_SHIFT_R_LEVEL_PULSE_SEL) #define BIT_CLEAR_R_LEVEL_PULSE_SEL(x) ((x) & (~BITS_R_LEVEL_PULSE_SEL)) #define BIT_GET_R_LEVEL_PULSE_SEL(x) \ (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL) & BIT_MASK_R_LEVEL_PULSE_SEL) #define BIT_SET_R_LEVEL_PULSE_SEL(x, v) \ (BIT_CLEAR_R_LEVEL_PULSE_SEL(x) | BIT_R_LEVEL_PULSE_SEL(v)) #define BIT_EN_LA_MAC BIT(2) #define BIT_R_EN_IQDUMP BIT(1) #define BIT_R_IQDATA_DUMP BIT(0) #define BIT_SHIFT_R_CCK_LEN 0 #define BIT_MASK_R_CCK_LEN 0xffff #define BIT_R_CCK_LEN(x) (((x) & BIT_MASK_R_CCK_LEN) << BIT_SHIFT_R_CCK_LEN) #define BITS_R_CCK_LEN (BIT_MASK_R_CCK_LEN << BIT_SHIFT_R_CCK_LEN) #define BIT_CLEAR_R_CCK_LEN(x) ((x) & (~BITS_R_CCK_LEN)) #define BIT_GET_R_CCK_LEN(x) (((x) >> BIT_SHIFT_R_CCK_LEN) & BIT_MASK_R_CCK_LEN) #define BIT_SET_R_CCK_LEN(x, v) (BIT_CLEAR_R_CCK_LEN(x) | BIT_R_CCK_LEN(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_IQ_DUMP_1 (Offset 0x07C4) */ #define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1 0 #define BIT_MASK_R_WMAC_MASK_LA_MAC_1 0xffffffffL #define BIT_R_WMAC_MASK_LA_MAC_1(x) \ (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1) \ << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1) #define BITS_R_WMAC_MASK_LA_MAC_1 \ (BIT_MASK_R_WMAC_MASK_LA_MAC_1 << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1) #define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1(x) ((x) & (~BITS_R_WMAC_MASK_LA_MAC_1)) #define BIT_GET_R_WMAC_MASK_LA_MAC_1(x) \ (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1) & \ BIT_MASK_R_WMAC_MASK_LA_MAC_1) #define BIT_SET_R_WMAC_MASK_LA_MAC_1(x, v) \ (BIT_CLEAR_R_WMAC_MASK_LA_MAC_1(x) | BIT_R_WMAC_MASK_LA_MAC_1(v)) /* 2 REG_IQ_DUMP_2 (Offset 0x07C8) */ #define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2 0 #define BIT_MASK_R_WMAC_MATCH_REF_MAC_2 0xffffffffL #define BIT_R_WMAC_MATCH_REF_MAC_2(x) \ (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2) \ << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2) #define BITS_R_WMAC_MATCH_REF_MAC_2 \ (BIT_MASK_R_WMAC_MATCH_REF_MAC_2 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2) #define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2(x) \ ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2)) #define BIT_GET_R_WMAC_MATCH_REF_MAC_2(x) \ (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2) & \ BIT_MASK_R_WMAC_MATCH_REF_MAC_2) #define BIT_SET_R_WMAC_MATCH_REF_MAC_2(x, v) \ (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2(x) | BIT_R_WMAC_MATCH_REF_MAC_2(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_FTM_CTL (Offset 0x07CC) */ #define BIT_RXFTM_TXACK_SC BIT(6) #define BIT_RXFTM_TXACK_BW BIT(5) #define BIT_RXFTM_EN BIT(3) #define BIT_RXFTMREQ_BYDRV BIT(2) #define BIT_RXFTMREQ_EN BIT(1) #define BIT_FTM_EN BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_IQ_DUMP_EXT (Offset 0x07CF) */ #define BIT_SHIFT_R_TIME_UNIT_SEL 0 #define BIT_MASK_R_TIME_UNIT_SEL 0x7 #define BIT_R_TIME_UNIT_SEL(x) \ (((x) & BIT_MASK_R_TIME_UNIT_SEL) << BIT_SHIFT_R_TIME_UNIT_SEL) #define BITS_R_TIME_UNIT_SEL \ (BIT_MASK_R_TIME_UNIT_SEL << BIT_SHIFT_R_TIME_UNIT_SEL) #define BIT_CLEAR_R_TIME_UNIT_SEL(x) ((x) & (~BITS_R_TIME_UNIT_SEL)) #define BIT_GET_R_TIME_UNIT_SEL(x) \ (((x) >> BIT_SHIFT_R_TIME_UNIT_SEL) & BIT_MASK_R_TIME_UNIT_SEL) #define BIT_SET_R_TIME_UNIT_SEL(x, v) \ (BIT_CLEAR_R_TIME_UNIT_SEL(x) | BIT_R_TIME_UNIT_SEL(v)) #endif #if (HALMAC_8814AMP_SUPPORT) /* 2 REG_OFDM_CCK_LEN_MASK (Offset 0x07D0) */ #define BIT_MICICV_CLR BIT(86) #define BIT_MPDU_RDY_SET BIT(85) #define BIT_CLR_SEC_TYPE BIT(84) #define BIT_NEWPKT_IN BIT(83) #define BIT_FCS_END BIT(82) #define BIT_DEL_MESH_TYPE BIT(81) #define BIT_MASK_MESH_TYPE BIT(80) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_OPTION_FUNCTION (Offset 0x07D0) */ #define BIT_SHIFT_R_OFDM_LEN_V1 16 #define BIT_MASK_R_OFDM_LEN_V1 0xffff #define BIT_R_OFDM_LEN_V1(x) \ (((x) & BIT_MASK_R_OFDM_LEN_V1) << BIT_SHIFT_R_OFDM_LEN_V1) #define BITS_R_OFDM_LEN_V1 (BIT_MASK_R_OFDM_LEN_V1 << BIT_SHIFT_R_OFDM_LEN_V1) #define BIT_CLEAR_R_OFDM_LEN_V1(x) ((x) & (~BITS_R_OFDM_LEN_V1)) #define BIT_GET_R_OFDM_LEN_V1(x) \ (((x) >> BIT_SHIFT_R_OFDM_LEN_V1) & BIT_MASK_R_OFDM_LEN_V1) #define BIT_SET_R_OFDM_LEN_V1(x, v) \ (BIT_CLEAR_R_OFDM_LEN_V1(x) | BIT_R_OFDM_LEN_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_OPTION_FUNCTION_1 (Offset 0x07D4) */ #define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1 24 #define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1 0xff #define BIT_R_WMAC_RXFIFO_FULL_TH_1(x) \ (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1) \ << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) #define BITS_R_WMAC_RXFIFO_FULL_TH_1 \ (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) #define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1(x) \ ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1)) #define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1(x) \ (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) & \ BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1) #define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1(x, v) \ (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1(x) | BIT_R_WMAC_RXFIFO_FULL_TH_1(v)) #define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1 BIT(23) #define BIT_R_WMAC_RXRST_DLY_1 BIT(22) #define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1 BIT(21) #define BIT_R_WMAC_SRCH_TXRPT_UA1_1 BIT(20) #define BIT_R_WMAC_SRCH_TXRPT_TYPE_1 BIT(19) #define BIT_R_WMAC_NDP_RST_1 BIT(18) #define BIT_R_WMAC_POWINT_EN_1 BIT(17) #define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1 BIT(16) #define BIT_R_WMAC_SRCH_TXRPT_MID_1 BIT(15) #define BIT_R_WMAC_PFIN_TOEN_1 BIT(14) #define BIT_R_WMAC_FIL_SECERR_1 BIT(13) #define BIT_R_WMAC_FIL_CTLPKTLEN_1 BIT(12) #define BIT_R_WMAC_FIL_FCTYPE_1 BIT(11) #define BIT_R_WMAC_FIL_FCPROVER_1 BIT(10) #define BIT_R_WMAC_PHYSTS_SNIF_1 BIT(9) #define BIT_R_WMAC_PHYSTS_PLCP_1 BIT(8) #define BIT_R_MAC_TCR_VBONF_RD_1 BIT(7) #define BIT_R_WMAC_TCR_MPAR_NDP_1 BIT(6) #define BIT_R_WMAC_NDP_FILTER_1 BIT(5) #define BIT_R_WMAC_RXLEN_SEL_1 BIT(4) #define BIT_R_WMAC_RXLEN_SEL1_1 BIT(3) #define BIT_R_OFDM_FILTER_1 BIT(2) #define BIT_R_WMAC_CHK_OFDM_LEN_1 BIT(1) #define BIT_R_WMAC_CHK_CCK_LEN_1 BIT(0) /* 2 REG_WMAC_OPTION_FUNCTION_2 (Offset 0x07D8) */ #define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2 0 #define BIT_MASK_R_WMAC_RX_FIL_LEN_2 0xffff #define BIT_R_WMAC_RX_FIL_LEN_2(x) \ (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) #define BITS_R_WMAC_RX_FIL_LEN_2 \ (BIT_MASK_R_WMAC_RX_FIL_LEN_2 << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) #define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2(x) ((x) & (~BITS_R_WMAC_RX_FIL_LEN_2)) #define BIT_GET_R_WMAC_RX_FIL_LEN_2(x) \ (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) & BIT_MASK_R_WMAC_RX_FIL_LEN_2) #define BIT_SET_R_WMAC_RX_FIL_LEN_2(x, v) \ (BIT_CLEAR_R_WMAC_RX_FIL_LEN_2(x) | BIT_R_WMAC_RX_FIL_LEN_2(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ #define BIT_R_WMAC_RXHANG_EN BIT(15) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ #define BIT_RXHANG_EN BIT(15) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ #define BIT_R_WMAC_MHRDDY_LATCH BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ #define BIT_R_MHRDDY_CLR BIT(13) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ #define BIT_R_WMAC_MHRDDY_CLR BIT(13) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ #define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1 BIT(12) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ #define BIT_R_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ #define BIT_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ #define BIT_R_CHK_DELIMIT_LEN BIT(10) #define BIT_R_REAPTER_ADDR_MATCH BIT(9) #define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY BIT(8) #define BIT_R_LATCH_MACHRDY BIT(7) #define BIT_R_WMAC_RXFIL_REND BIT(6) #define BIT_R_WMAC_MPDURDY_CLR BIT(5) #define BIT_R_WMAC_CLRRXSEC BIT(4) #define BIT_R_WMAC_RXFIL_RDEL BIT(3) #define BIT_R_WMAC_RXFIL_FCSE BIT(2) #define BIT_R_WMAC_RXFIL_MESH_DEL BIT(1) #define BIT_R_WMAC_RXFIL_MASKM BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_NDP_SIG (Offset 0x07E0) */ #define BIT_SHIFT_R_WMAC_TXNDP_SIGB 0 #define BIT_MASK_R_WMAC_TXNDP_SIGB 0x1fffff #define BIT_R_WMAC_TXNDP_SIGB(x) \ (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB) << BIT_SHIFT_R_WMAC_TXNDP_SIGB) #define BITS_R_WMAC_TXNDP_SIGB \ (BIT_MASK_R_WMAC_TXNDP_SIGB << BIT_SHIFT_R_WMAC_TXNDP_SIGB) #define BIT_CLEAR_R_WMAC_TXNDP_SIGB(x) ((x) & (~BITS_R_WMAC_TXNDP_SIGB)) #define BIT_GET_R_WMAC_TXNDP_SIGB(x) \ (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB) & BIT_MASK_R_WMAC_TXNDP_SIGB) #define BIT_SET_R_WMAC_TXNDP_SIGB(x, v) \ (BIT_CLEAR_R_WMAC_TXNDP_SIGB(x) | BIT_R_WMAC_TXNDP_SIGB(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */ #define BIT_SHIFT_R_MAC_DEBUG (32 & CPU_OPT_WIDTH) #define BIT_MASK_R_MAC_DEBUG 0xffffffffL #define BIT_R_MAC_DEBUG(x) \ (((x) & BIT_MASK_R_MAC_DEBUG) << BIT_SHIFT_R_MAC_DEBUG) #define BITS_R_MAC_DEBUG (BIT_MASK_R_MAC_DEBUG << BIT_SHIFT_R_MAC_DEBUG) #define BIT_CLEAR_R_MAC_DEBUG(x) ((x) & (~BITS_R_MAC_DEBUG)) #define BIT_GET_R_MAC_DEBUG(x) \ (((x) >> BIT_SHIFT_R_MAC_DEBUG) & BIT_MASK_R_MAC_DEBUG) #define BIT_SET_R_MAC_DEBUG(x, v) \ (BIT_CLEAR_R_MAC_DEBUG(x) | BIT_R_MAC_DEBUG(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */ #define BIT_SHIFT_R_MAC_DBG_SHIFT 8 #define BIT_MASK_R_MAC_DBG_SHIFT 0x7 #define BIT_R_MAC_DBG_SHIFT(x) \ (((x) & BIT_MASK_R_MAC_DBG_SHIFT) << BIT_SHIFT_R_MAC_DBG_SHIFT) #define BITS_R_MAC_DBG_SHIFT \ (BIT_MASK_R_MAC_DBG_SHIFT << BIT_SHIFT_R_MAC_DBG_SHIFT) #define BIT_CLEAR_R_MAC_DBG_SHIFT(x) ((x) & (~BITS_R_MAC_DBG_SHIFT)) #define BIT_GET_R_MAC_DBG_SHIFT(x) \ (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT) & BIT_MASK_R_MAC_DBG_SHIFT) #define BIT_SET_R_MAC_DBG_SHIFT(x, v) \ (BIT_CLEAR_R_MAC_DBG_SHIFT(x) | BIT_R_MAC_DBG_SHIFT(v)) #define BIT_SHIFT_R_MAC_DBG_SEL 0 #define BIT_MASK_R_MAC_DBG_SEL 0x3 #define BIT_R_MAC_DBG_SEL(x) \ (((x) & BIT_MASK_R_MAC_DBG_SEL) << BIT_SHIFT_R_MAC_DBG_SEL) #define BITS_R_MAC_DBG_SEL (BIT_MASK_R_MAC_DBG_SEL << BIT_SHIFT_R_MAC_DBG_SEL) #define BIT_CLEAR_R_MAC_DBG_SEL(x) ((x) & (~BITS_R_MAC_DBG_SEL)) #define BIT_GET_R_MAC_DBG_SEL(x) \ (((x) >> BIT_SHIFT_R_MAC_DBG_SEL) & BIT_MASK_R_MAC_DBG_SEL) #define BIT_SET_R_MAC_DBG_SEL(x, v) \ (BIT_CLEAR_R_MAC_DBG_SEL(x) | BIT_R_MAC_DBG_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SEC_OPT (Offset 0x07E8) */ #define BIT_MASK_IV BIT(18) #define BIT_EIVL_ENDIAN BIT(17) #define BIT_EIVH_ENDIAN BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SEC_OPT (Offset 0x07E8) */ #define BIT_SHIFT_BT_TIME_CNT 0 #define BIT_MASK_BT_TIME_CNT 0xff #define BIT_BT_TIME_CNT(x) \ (((x) & BIT_MASK_BT_TIME_CNT) << BIT_SHIFT_BT_TIME_CNT) #define BITS_BT_TIME_CNT (BIT_MASK_BT_TIME_CNT << BIT_SHIFT_BT_TIME_CNT) #define BIT_CLEAR_BT_TIME_CNT(x) ((x) & (~BITS_BT_TIME_CNT)) #define BIT_GET_BT_TIME_CNT(x) \ (((x) >> BIT_SHIFT_BT_TIME_CNT) & BIT_MASK_BT_TIME_CNT) #define BIT_SET_BT_TIME_CNT(x, v) \ (BIT_CLEAR_BT_TIME_CNT(x) | BIT_BT_TIME_CNT(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1 (Offset 0x07E8) */ #define BIT_SHIFT_R_MAC_DEBUG_1 0 #define BIT_MASK_R_MAC_DEBUG_1 0xffffffffL #define BIT_R_MAC_DEBUG_1(x) \ (((x) & BIT_MASK_R_MAC_DEBUG_1) << BIT_SHIFT_R_MAC_DEBUG_1) #define BITS_R_MAC_DEBUG_1 (BIT_MASK_R_MAC_DEBUG_1 << BIT_SHIFT_R_MAC_DEBUG_1) #define BIT_CLEAR_R_MAC_DEBUG_1(x) ((x) & (~BITS_R_MAC_DEBUG_1)) #define BIT_GET_R_MAC_DEBUG_1(x) \ (((x) >> BIT_SHIFT_R_MAC_DEBUG_1) & BIT_MASK_R_MAC_DEBUG_1) #define BIT_SET_R_MAC_DEBUG_1(x, v) \ (BIT_CLEAR_R_MAC_DEBUG_1(x) | BIT_R_MAC_DEBUG_1(v)) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_WSEC_OPTION (Offset 0x07EC) */ #define BIT_RXDEC_BM_MGNT BIT(22) #define BIT_TXENC_BM_MGNT BIT(21) #define BIT_RXDEC_UNI_MGNT BIT(20) #define BIT_TXENC_UNI_MGNT BIT(19) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_WSEC_OPTION (Offset 0x07EC) */ #define BIT_WMAC_SEC_MASKIV BIT(18) #define BIT_SHIFT_WMAC_SEC_PN_SEL 16 #define BIT_MASK_WMAC_SEC_PN_SEL 0x3 #define BIT_WMAC_SEC_PN_SEL(x) \ (((x) & BIT_MASK_WMAC_SEC_PN_SEL) << BIT_SHIFT_WMAC_SEC_PN_SEL) #define BITS_WMAC_SEC_PN_SEL \ (BIT_MASK_WMAC_SEC_PN_SEL << BIT_SHIFT_WMAC_SEC_PN_SEL) #define BIT_CLEAR_WMAC_SEC_PN_SEL(x) ((x) & (~BITS_WMAC_SEC_PN_SEL)) #define BIT_GET_WMAC_SEC_PN_SEL(x) \ (((x) >> BIT_SHIFT_WMAC_SEC_PN_SEL) & BIT_MASK_WMAC_SEC_PN_SEL) #define BIT_SET_WMAC_SEC_PN_SEL(x, v) \ (BIT_CLEAR_WMAC_SEC_PN_SEL(x) | BIT_WMAC_SEC_PN_SEL(v)) #endif #if (HALMAC_8814AMP_SUPPORT) /* 2 REG_RTS_ADDR0 (Offset 0x07F0) */ #define BIT_SHIFT_RTS_ADDR0 0 #define BIT_MASK_RTS_ADDR0 0xffffffffffffL #define BIT_RTS_ADDR0(x) (((x) & BIT_MASK_RTS_ADDR0) << BIT_SHIFT_RTS_ADDR0) #define BITS_RTS_ADDR0 (BIT_MASK_RTS_ADDR0 << BIT_SHIFT_RTS_ADDR0) #define BIT_CLEAR_RTS_ADDR0(x) ((x) & (~BITS_RTS_ADDR0)) #define BIT_GET_RTS_ADDR0(x) (((x) >> BIT_SHIFT_RTS_ADDR0) & BIT_MASK_RTS_ADDR0) #define BIT_SET_RTS_ADDR0(x, v) (BIT_CLEAR_RTS_ADDR0(x) | BIT_RTS_ADDR0(v)) /* 2 REG_RTS_ADDR1 (Offset 0x07F8) */ #define BIT_SHIFT_RTS_ADDR1 0 #define BIT_MASK_RTS_ADDR1 0xffffffffffffL #define BIT_RTS_ADDR1(x) (((x) & BIT_MASK_RTS_ADDR1) << BIT_SHIFT_RTS_ADDR1) #define BITS_RTS_ADDR1 (BIT_MASK_RTS_ADDR1 << BIT_SHIFT_RTS_ADDR1) #define BIT_CLEAR_RTS_ADDR1(x) ((x) & (~BITS_RTS_ADDR1)) #define BIT_GET_RTS_ADDR1(x) (((x) >> BIT_SHIFT_RTS_ADDR1) & BIT_MASK_RTS_ADDR1) #define BIT_SET_RTS_ADDR1(x, v) (BIT_CLEAR_RTS_ADDR1(x) | BIT_RTS_ADDR1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG__RPFM_MAP1 (Offset 0x07FE) */ #define BIT_DATA_RPFM15EN BIT(15) #define BIT_DATA_RPFM14EN BIT(14) #define BIT_DATA_RPFM13EN BIT(13) #define BIT_DATA_RPFM12EN BIT(12) #define BIT_DATA_RPFM11EN BIT(11) #define BIT_DATA_RPFM10EN BIT(10) #define BIT_DATA_RPFM9EN BIT(9) #define BIT_DATA_RPFM8EN BIT(8) #define BIT_DATA_RPFM7EN BIT(7) #define BIT_DATA_RPFM6EN BIT(6) #define BIT_DATA_RPFM5EN BIT(5) #define BIT_DATA_RPFM4EN BIT(4) #define BIT_DATA_RPFM3EN BIT(3) #define BIT_DATA_RPFM2EN BIT(2) #define BIT_DATA_RPFM1EN BIT(1) #define BIT_DATA_RPFM0EN BIT(0) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CFG3 (Offset 0x1000) */ #define BIT_FEN_BB_GLB_RSTN_V1 BIT(17) #define BIT_FEN_BBRSTB_V1 BIT(16) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_CFG3 (Offset 0x1000) */ #define BIT_PWC_MA33V BIT(15) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CFG3 (Offset 0x1000) */ #define BIT_PWC_EV25V_1 BIT(14) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_CFG3 (Offset 0x1000) */ #define BIT_PWC_MA12V BIT(14) #define BIT_PWC_MD12V BIT(13) #define BIT_PWC_PD12V BIT(12) #define BIT_PWC_UD12V BIT(11) #define BIT_ISO_MA2MD BIT(1) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_OCP_L_0 BIT(31) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_OCP_L BIT(31) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_POWOCP_L BIT(30) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_CF_L_1_0 28 #define BIT_MASK_CF_L_1_0 0x3 #define BIT_CF_L_1_0(x) (((x) & BIT_MASK_CF_L_1_0) << BIT_SHIFT_CF_L_1_0) #define BITS_CF_L_1_0 (BIT_MASK_CF_L_1_0 << BIT_SHIFT_CF_L_1_0) #define BIT_CLEAR_CF_L_1_0(x) ((x) & (~BITS_CF_L_1_0)) #define BIT_GET_CF_L_1_0(x) (((x) >> BIT_SHIFT_CF_L_1_0) & BIT_MASK_CF_L_1_0) #define BIT_SET_CF_L_1_0(x, v) (BIT_CLEAR_CF_L_1_0(x) | BIT_CF_L_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_CF_L_V2 28 #define BIT_MASK_CF_L_V2 0x3 #define BIT_CF_L_V2(x) (((x) & BIT_MASK_CF_L_V2) << BIT_SHIFT_CF_L_V2) #define BITS_CF_L_V2 (BIT_MASK_CF_L_V2 << BIT_SHIFT_CF_L_V2) #define BIT_CLEAR_CF_L_V2(x) ((x) & (~BITS_CF_L_V2)) #define BIT_GET_CF_L_V2(x) (((x) >> BIT_SHIFT_CF_L_V2) & BIT_MASK_CF_L_V2) #define BIT_SET_CF_L_V2(x, v) (BIT_CLEAR_CF_L_V2(x) | BIT_CF_L_V2(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_CFC_L_1_0 26 #define BIT_MASK_CFC_L_1_0 0x3 #define BIT_CFC_L_1_0(x) (((x) & BIT_MASK_CFC_L_1_0) << BIT_SHIFT_CFC_L_1_0) #define BITS_CFC_L_1_0 (BIT_MASK_CFC_L_1_0 << BIT_SHIFT_CFC_L_1_0) #define BIT_CLEAR_CFC_L_1_0(x) ((x) & (~BITS_CFC_L_1_0)) #define BIT_GET_CFC_L_1_0(x) (((x) >> BIT_SHIFT_CFC_L_1_0) & BIT_MASK_CFC_L_1_0) #define BIT_SET_CFC_L_1_0(x, v) (BIT_CLEAR_CFC_L_1_0(x) | BIT_CFC_L_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_CFC_L_V2 26 #define BIT_MASK_CFC_L_V2 0x3 #define BIT_CFC_L_V2(x) (((x) & BIT_MASK_CFC_L_V2) << BIT_SHIFT_CFC_L_V2) #define BITS_CFC_L_V2 (BIT_MASK_CFC_L_V2 << BIT_SHIFT_CFC_L_V2) #define BIT_CLEAR_CFC_L_V2(x) ((x) & (~BITS_CFC_L_V2)) #define BIT_GET_CFC_L_V2(x) (((x) >> BIT_SHIFT_CFC_L_V2) & BIT_MASK_CFC_L_V2) #define BIT_SET_CFC_L_V2(x, v) (BIT_CLEAR_CFC_L_V2(x) | BIT_CFC_L_V2(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_R3_L_1_0 24 #define BIT_MASK_R3_L_1_0 0x3 #define BIT_R3_L_1_0(x) (((x) & BIT_MASK_R3_L_1_0) << BIT_SHIFT_R3_L_1_0) #define BITS_R3_L_1_0 (BIT_MASK_R3_L_1_0 << BIT_SHIFT_R3_L_1_0) #define BIT_CLEAR_R3_L_1_0(x) ((x) & (~BITS_R3_L_1_0)) #define BIT_GET_R3_L_1_0(x) (((x) >> BIT_SHIFT_R3_L_1_0) & BIT_MASK_R3_L_1_0) #define BIT_SET_R3_L_1_0(x, v) (BIT_CLEAR_R3_L_1_0(x) | BIT_R3_L_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_R3_L_V2 24 #define BIT_MASK_R3_L_V2 0x3 #define BIT_R3_L_V2(x) (((x) & BIT_MASK_R3_L_V2) << BIT_SHIFT_R3_L_V2) #define BITS_R3_L_V2 (BIT_MASK_R3_L_V2 << BIT_SHIFT_R3_L_V2) #define BIT_CLEAR_R3_L_V2(x) ((x) & (~BITS_R3_L_V2)) #define BIT_GET_R3_L_V2(x) (((x) >> BIT_SHIFT_R3_L_V2) & BIT_MASK_R3_L_V2) #define BIT_SET_R3_L_V2(x, v) (BIT_CLEAR_R3_L_V2(x) | BIT_R3_L_V2(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_R2_L_1_0 22 #define BIT_MASK_R2_L_1_0 0x3 #define BIT_R2_L_1_0(x) (((x) & BIT_MASK_R2_L_1_0) << BIT_SHIFT_R2_L_1_0) #define BITS_R2_L_1_0 (BIT_MASK_R2_L_1_0 << BIT_SHIFT_R2_L_1_0) #define BIT_CLEAR_R2_L_1_0(x) ((x) & (~BITS_R2_L_1_0)) #define BIT_GET_R2_L_1_0(x) (((x) >> BIT_SHIFT_R2_L_1_0) & BIT_MASK_R2_L_1_0) #define BIT_SET_R2_L_1_0(x, v) (BIT_CLEAR_R2_L_1_0(x) | BIT_R2_L_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_R2_L 22 #define BIT_MASK_R2_L 0x3 #define BIT_R2_L(x) (((x) & BIT_MASK_R2_L) << BIT_SHIFT_R2_L) #define BITS_R2_L (BIT_MASK_R2_L << BIT_SHIFT_R2_L) #define BIT_CLEAR_R2_L(x) ((x) & (~BITS_R2_L)) #define BIT_GET_R2_L(x) (((x) >> BIT_SHIFT_R2_L) & BIT_MASK_R2_L) #define BIT_SET_R2_L(x, v) (BIT_CLEAR_R2_L(x) | BIT_R2_L(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_R1_L_1_0 20 #define BIT_MASK_R1_L_1_0 0x3 #define BIT_R1_L_1_0(x) (((x) & BIT_MASK_R1_L_1_0) << BIT_SHIFT_R1_L_1_0) #define BITS_R1_L_1_0 (BIT_MASK_R1_L_1_0 << BIT_SHIFT_R1_L_1_0) #define BIT_CLEAR_R1_L_1_0(x) ((x) & (~BITS_R1_L_1_0)) #define BIT_GET_R1_L_1_0(x) (((x) >> BIT_SHIFT_R1_L_1_0) & BIT_MASK_R1_L_1_0) #define BIT_SET_R1_L_1_0(x, v) (BIT_CLEAR_R1_L_1_0(x) | BIT_R1_L_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_R1_L 20 #define BIT_MASK_R1_L 0x3 #define BIT_R1_L(x) (((x) & BIT_MASK_R1_L) << BIT_SHIFT_R1_L) #define BITS_R1_L (BIT_MASK_R1_L << BIT_SHIFT_R1_L) #define BIT_CLEAR_R1_L(x) ((x) & (~BITS_R1_L)) #define BIT_GET_R1_L(x) (((x) >> BIT_SHIFT_R1_L) & BIT_MASK_R1_L) #define BIT_SET_R1_L(x, v) (BIT_CLEAR_R1_L(x) | BIT_R1_L(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_C3_L_1_0 18 #define BIT_MASK_C3_L_1_0 0x3 #define BIT_C3_L_1_0(x) (((x) & BIT_MASK_C3_L_1_0) << BIT_SHIFT_C3_L_1_0) #define BITS_C3_L_1_0 (BIT_MASK_C3_L_1_0 << BIT_SHIFT_C3_L_1_0) #define BIT_CLEAR_C3_L_1_0(x) ((x) & (~BITS_C3_L_1_0)) #define BIT_GET_C3_L_1_0(x) (((x) >> BIT_SHIFT_C3_L_1_0) & BIT_MASK_C3_L_1_0) #define BIT_SET_C3_L_1_0(x, v) (BIT_CLEAR_C3_L_1_0(x) | BIT_C3_L_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_C3_L 18 #define BIT_MASK_C3_L 0x3 #define BIT_C3_L(x) (((x) & BIT_MASK_C3_L) << BIT_SHIFT_C3_L) #define BITS_C3_L (BIT_MASK_C3_L << BIT_SHIFT_C3_L) #define BIT_CLEAR_C3_L(x) ((x) & (~BITS_C3_L)) #define BIT_GET_C3_L(x) (((x) >> BIT_SHIFT_C3_L) & BIT_MASK_C3_L) #define BIT_SET_C3_L(x, v) (BIT_CLEAR_C3_L(x) | BIT_C3_L(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_C2_L_1_0 16 #define BIT_MASK_C2_L_1_0 0x3 #define BIT_C2_L_1_0(x) (((x) & BIT_MASK_C2_L_1_0) << BIT_SHIFT_C2_L_1_0) #define BITS_C2_L_1_0 (BIT_MASK_C2_L_1_0 << BIT_SHIFT_C2_L_1_0) #define BIT_CLEAR_C2_L_1_0(x) ((x) & (~BITS_C2_L_1_0)) #define BIT_GET_C2_L_1_0(x) (((x) >> BIT_SHIFT_C2_L_1_0) & BIT_MASK_C2_L_1_0) #define BIT_SET_C2_L_1_0(x, v) (BIT_CLEAR_C2_L_1_0(x) | BIT_C2_L_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_C2_L 16 #define BIT_MASK_C2_L 0x3 #define BIT_C2_L(x) (((x) & BIT_MASK_C2_L) << BIT_SHIFT_C2_L) #define BITS_C2_L (BIT_MASK_C2_L << BIT_SHIFT_C2_L) #define BIT_CLEAR_C2_L(x) ((x) & (~BITS_C2_L)) #define BIT_GET_C2_L(x) (((x) >> BIT_SHIFT_C2_L) & BIT_MASK_C2_L) #define BIT_SET_C2_L(x, v) (BIT_CLEAR_C2_L(x) | BIT_C2_L(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_C1_L_1_0 14 #define BIT_MASK_C1_L_1_0 0x3 #define BIT_C1_L_1_0(x) (((x) & BIT_MASK_C1_L_1_0) << BIT_SHIFT_C1_L_1_0) #define BITS_C1_L_1_0 (BIT_MASK_C1_L_1_0 << BIT_SHIFT_C1_L_1_0) #define BIT_CLEAR_C1_L_1_0(x) ((x) & (~BITS_C1_L_1_0)) #define BIT_GET_C1_L_1_0(x) (((x) >> BIT_SHIFT_C1_L_1_0) & BIT_MASK_C1_L_1_0) #define BIT_SET_C1_L_1_0(x, v) (BIT_CLEAR_C1_L_1_0(x) | BIT_C1_L_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_C1_L_V2 14 #define BIT_MASK_C1_L_V2 0x3 #define BIT_C1_L_V2(x) (((x) & BIT_MASK_C1_L_V2) << BIT_SHIFT_C1_L_V2) #define BITS_C1_L_V2 (BIT_MASK_C1_L_V2 << BIT_SHIFT_C1_L_V2) #define BIT_CLEAR_C1_L_V2(x) ((x) & (~BITS_C1_L_V2)) #define BIT_GET_C1_L_V2(x) (((x) >> BIT_SHIFT_C1_L_V2) & BIT_MASK_C1_L_V2) #define BIT_SET_C1_L_V2(x, v) (BIT_CLEAR_C1_L_V2(x) | BIT_C1_L_V2(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_REG_TYPE_L_V2 BIT(13) #define BIT_REG_PWM_L BIT(12) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_V15ADJ_L_2_0 9 #define BIT_MASK_V15ADJ_L_2_0 0x7 #define BIT_V15ADJ_L_2_0(x) \ (((x) & BIT_MASK_V15ADJ_L_2_0) << BIT_SHIFT_V15ADJ_L_2_0) #define BITS_V15ADJ_L_2_0 (BIT_MASK_V15ADJ_L_2_0 << BIT_SHIFT_V15ADJ_L_2_0) #define BIT_CLEAR_V15ADJ_L_2_0(x) ((x) & (~BITS_V15ADJ_L_2_0)) #define BIT_GET_V15ADJ_L_2_0(x) \ (((x) >> BIT_SHIFT_V15ADJ_L_2_0) & BIT_MASK_V15ADJ_L_2_0) #define BIT_SET_V15ADJ_L_2_0(x, v) \ (BIT_CLEAR_V15ADJ_L_2_0(x) | BIT_V15ADJ_L_2_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_V15ADJ_L 9 #define BIT_MASK_V15ADJ_L 0x7 #define BIT_V15ADJ_L(x) (((x) & BIT_MASK_V15ADJ_L) << BIT_SHIFT_V15ADJ_L) #define BITS_V15ADJ_L (BIT_MASK_V15ADJ_L << BIT_SHIFT_V15ADJ_L) #define BIT_CLEAR_V15ADJ_L(x) ((x) & (~BITS_V15ADJ_L)) #define BIT_GET_V15ADJ_L(x) (((x) >> BIT_SHIFT_V15ADJ_L) & BIT_MASK_V15ADJ_L) #define BIT_SET_V15ADJ_L(x, v) (BIT_CLEAR_V15ADJ_L(x) | BIT_V15ADJ_L(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_IN_L_2_0 6 #define BIT_MASK_IN_L_2_0 0x7 #define BIT_IN_L_2_0(x) (((x) & BIT_MASK_IN_L_2_0) << BIT_SHIFT_IN_L_2_0) #define BITS_IN_L_2_0 (BIT_MASK_IN_L_2_0 << BIT_SHIFT_IN_L_2_0) #define BIT_CLEAR_IN_L_2_0(x) ((x) & (~BITS_IN_L_2_0)) #define BIT_GET_IN_L_2_0(x) (((x) >> BIT_SHIFT_IN_L_2_0) & BIT_MASK_IN_L_2_0) #define BIT_SET_IN_L_2_0(x, v) (BIT_CLEAR_IN_L_2_0(x) | BIT_IN_L_2_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_IN_L 6 #define BIT_MASK_IN_L 0x7 #define BIT_IN_L(x) (((x) & BIT_MASK_IN_L) << BIT_SHIFT_IN_L) #define BITS_IN_L (BIT_MASK_IN_L << BIT_SHIFT_IN_L) #define BIT_CLEAR_IN_L(x) ((x) & (~BITS_IN_L)) #define BIT_GET_IN_L(x) (((x) >> BIT_SHIFT_IN_L) & BIT_MASK_IN_L) #define BIT_SET_IN_L(x, v) (BIT_CLEAR_IN_L(x) | BIT_IN_L(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_STD_L_1_0 4 #define BIT_MASK_STD_L_1_0 0x3 #define BIT_STD_L_1_0(x) (((x) & BIT_MASK_STD_L_1_0) << BIT_SHIFT_STD_L_1_0) #define BITS_STD_L_1_0 (BIT_MASK_STD_L_1_0 << BIT_SHIFT_STD_L_1_0) #define BIT_CLEAR_STD_L_1_0(x) ((x) & (~BITS_STD_L_1_0)) #define BIT_GET_STD_L_1_0(x) (((x) >> BIT_SHIFT_STD_L_1_0) & BIT_MASK_STD_L_1_0) #define BIT_SET_STD_L_1_0(x, v) (BIT_CLEAR_STD_L_1_0(x) | BIT_STD_L_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_STD_L 4 #define BIT_MASK_STD_L 0x3 #define BIT_STD_L(x) (((x) & BIT_MASK_STD_L) << BIT_SHIFT_STD_L) #define BITS_STD_L (BIT_MASK_STD_L << BIT_SHIFT_STD_L) #define BIT_CLEAR_STD_L(x) ((x) & (~BITS_STD_L)) #define BIT_GET_STD_L(x) (((x) >> BIT_SHIFT_STD_L) & BIT_MASK_STD_L) #define BIT_SET_STD_L(x, v) (BIT_CLEAR_STD_L(x) | BIT_STD_L(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_VOL_L_3_0 0 #define BIT_MASK_VOL_L_3_0 0xf #define BIT_VOL_L_3_0(x) (((x) & BIT_MASK_VOL_L_3_0) << BIT_SHIFT_VOL_L_3_0) #define BITS_VOL_L_3_0 (BIT_MASK_VOL_L_3_0 << BIT_SHIFT_VOL_L_3_0) #define BIT_CLEAR_VOL_L_3_0(x) ((x) & (~BITS_VOL_L_3_0)) #define BIT_GET_VOL_L_3_0(x) (((x) >> BIT_SHIFT_VOL_L_3_0) & BIT_MASK_VOL_L_3_0) #define BIT_SET_VOL_L_3_0(x, v) (BIT_CLEAR_VOL_L_3_0(x) | BIT_VOL_L_3_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ #define BIT_SHIFT_VOL_L 0 #define BIT_MASK_VOL_L 0xf #define BIT_VOL_L(x) (((x) & BIT_MASK_VOL_L) << BIT_SHIFT_VOL_L) #define BITS_VOL_L (BIT_MASK_VOL_L << BIT_SHIFT_VOL_L) #define BIT_CLEAR_VOL_L(x) ((x) & (~BITS_VOL_L)) #define BIT_GET_VOL_L(x) (((x) >> BIT_SHIFT_VOL_L) & BIT_MASK_VOL_L) #define BIT_SET_VOL_L(x, v) (BIT_CLEAR_VOL_L(x) | BIT_VOL_L(v)) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_SHIFT_OCP_L_PFM 29 #define BIT_MASK_OCP_L_PFM 0x7 #define BIT_OCP_L_PFM(x) (((x) & BIT_MASK_OCP_L_PFM) << BIT_SHIFT_OCP_L_PFM) #define BITS_OCP_L_PFM (BIT_MASK_OCP_L_PFM << BIT_SHIFT_OCP_L_PFM) #define BIT_CLEAR_OCP_L_PFM(x) ((x) & (~BITS_OCP_L_PFM)) #define BIT_GET_OCP_L_PFM(x) (((x) >> BIT_SHIFT_OCP_L_PFM) & BIT_MASK_OCP_L_PFM) #define BIT_SET_OCP_L_PFM(x, v) (BIT_CLEAR_OCP_L_PFM(x) | BIT_OCP_L_PFM(v)) #define BIT_SHIFT_CFC_L_PFM 27 #define BIT_MASK_CFC_L_PFM 0x3 #define BIT_CFC_L_PFM(x) (((x) & BIT_MASK_CFC_L_PFM) << BIT_SHIFT_CFC_L_PFM) #define BITS_CFC_L_PFM (BIT_MASK_CFC_L_PFM << BIT_SHIFT_CFC_L_PFM) #define BIT_CLEAR_CFC_L_PFM(x) ((x) & (~BITS_CFC_L_PFM)) #define BIT_GET_CFC_L_PFM(x) (((x) >> BIT_SHIFT_CFC_L_PFM) & BIT_MASK_CFC_L_PFM) #define BIT_SET_CFC_L_PFM(x, v) (BIT_CLEAR_CFC_L_PFM(x) | BIT_CFC_L_PFM(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_SHIFT_REG_FREQ_L_V1 20 #define BIT_MASK_REG_FREQ_L_V1 0x7 #define BIT_REG_FREQ_L_V1(x) \ (((x) & BIT_MASK_REG_FREQ_L_V1) << BIT_SHIFT_REG_FREQ_L_V1) #define BITS_REG_FREQ_L_V1 (BIT_MASK_REG_FREQ_L_V1 << BIT_SHIFT_REG_FREQ_L_V1) #define BIT_CLEAR_REG_FREQ_L_V1(x) ((x) & (~BITS_REG_FREQ_L_V1)) #define BIT_GET_REG_FREQ_L_V1(x) \ (((x) >> BIT_SHIFT_REG_FREQ_L_V1) & BIT_MASK_REG_FREQ_L_V1) #define BIT_SET_REG_FREQ_L_V1(x, v) \ (BIT_CLEAR_REG_FREQ_L_V1(x) | BIT_REG_FREQ_L_V1(v)) #define BIT_EN_DUTY BIT(19) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_SHIFT_REG_MOS_HALF 17 #define BIT_MASK_REG_MOS_HALF 0x3 #define BIT_REG_MOS_HALF(x) \ (((x) & BIT_MASK_REG_MOS_HALF) << BIT_SHIFT_REG_MOS_HALF) #define BITS_REG_MOS_HALF (BIT_MASK_REG_MOS_HALF << BIT_SHIFT_REG_MOS_HALF) #define BIT_CLEAR_REG_MOS_HALF(x) ((x) & (~BITS_REG_MOS_HALF)) #define BIT_GET_REG_MOS_HALF(x) \ (((x) >> BIT_SHIFT_REG_MOS_HALF) & BIT_MASK_REG_MOS_HALF) #define BIT_SET_REG_MOS_HALF(x, v) \ (BIT_CLEAR_REG_MOS_HALF(x) | BIT_REG_MOS_HALF(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_SHIFT_REG_MODE_V2 17 #define BIT_MASK_REG_MODE_V2 0x3 #define BIT_REG_MODE_V2(x) \ (((x) & BIT_MASK_REG_MODE_V2) << BIT_SHIFT_REG_MODE_V2) #define BITS_REG_MODE_V2 (BIT_MASK_REG_MODE_V2 << BIT_SHIFT_REG_MODE_V2) #define BIT_CLEAR_REG_MODE_V2(x) ((x) & (~BITS_REG_MODE_V2)) #define BIT_GET_REG_MODE_V2(x) \ (((x) >> BIT_SHIFT_REG_MODE_V2) & BIT_MASK_REG_MODE_V2) #define BIT_SET_REG_MODE_V2(x, v) \ (BIT_CLEAR_REG_MODE_V2(x) | BIT_REG_MODE_V2(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_EN_SP BIT(16) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_REG_AUTO_L_V1 BIT(15) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_REG_AUTO_L_V2 BIT(15) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_REG_LDOF_L_V2 BIT(14) #define BIT_REG_OCPS_L_V2 BIT(13) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_VO15_V1P05_H BIT(12) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_ARENB_L_V1 BIT(11) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_ARENB_L_V2 BIT(11) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_SHIFT_TBOX_L1_1_0 9 #define BIT_MASK_TBOX_L1_1_0 0x3 #define BIT_TBOX_L1_1_0(x) \ (((x) & BIT_MASK_TBOX_L1_1_0) << BIT_SHIFT_TBOX_L1_1_0) #define BITS_TBOX_L1_1_0 (BIT_MASK_TBOX_L1_1_0 << BIT_SHIFT_TBOX_L1_1_0) #define BIT_CLEAR_TBOX_L1_1_0(x) ((x) & (~BITS_TBOX_L1_1_0)) #define BIT_GET_TBOX_L1_1_0(x) \ (((x) >> BIT_SHIFT_TBOX_L1_1_0) & BIT_MASK_TBOX_L1_1_0) #define BIT_SET_TBOX_L1_1_0(x, v) \ (BIT_CLEAR_TBOX_L1_1_0(x) | BIT_TBOX_L1_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_SHIFT_TBOX_L1_V2 9 #define BIT_MASK_TBOX_L1_V2 0x3 #define BIT_TBOX_L1_V2(x) (((x) & BIT_MASK_TBOX_L1_V2) << BIT_SHIFT_TBOX_L1_V2) #define BITS_TBOX_L1_V2 (BIT_MASK_TBOX_L1_V2 << BIT_SHIFT_TBOX_L1_V2) #define BIT_CLEAR_TBOX_L1_V2(x) ((x) & (~BITS_TBOX_L1_V2)) #define BIT_GET_TBOX_L1_V2(x) \ (((x) >> BIT_SHIFT_TBOX_L1_V2) & BIT_MASK_TBOX_L1_V2) #define BIT_SET_TBOX_L1_V2(x, v) (BIT_CLEAR_TBOX_L1_V2(x) | BIT_TBOX_L1_V2(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_SHIFT_REG_DELAY_L_1_0 7 #define BIT_MASK_REG_DELAY_L_1_0 0x3 #define BIT_REG_DELAY_L_1_0(x) \ (((x) & BIT_MASK_REG_DELAY_L_1_0) << BIT_SHIFT_REG_DELAY_L_1_0) #define BITS_REG_DELAY_L_1_0 \ (BIT_MASK_REG_DELAY_L_1_0 << BIT_SHIFT_REG_DELAY_L_1_0) #define BIT_CLEAR_REG_DELAY_L_1_0(x) ((x) & (~BITS_REG_DELAY_L_1_0)) #define BIT_GET_REG_DELAY_L_1_0(x) \ (((x) >> BIT_SHIFT_REG_DELAY_L_1_0) & BIT_MASK_REG_DELAY_L_1_0) #define BIT_SET_REG_DELAY_L_1_0(x, v) \ (BIT_CLEAR_REG_DELAY_L_1_0(x) | BIT_REG_DELAY_L_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_SHIFT_REG_DELAY_L 7 #define BIT_MASK_REG_DELAY_L 0x3 #define BIT_REG_DELAY_L(x) \ (((x) & BIT_MASK_REG_DELAY_L) << BIT_SHIFT_REG_DELAY_L) #define BITS_REG_DELAY_L (BIT_MASK_REG_DELAY_L << BIT_SHIFT_REG_DELAY_L) #define BIT_CLEAR_REG_DELAY_L(x) ((x) & (~BITS_REG_DELAY_L)) #define BIT_GET_REG_DELAY_L(x) \ (((x) >> BIT_SHIFT_REG_DELAY_L) & BIT_MASK_REG_DELAY_L) #define BIT_SET_REG_DELAY_L(x, v) \ (BIT_CLEAR_REG_DELAY_L(x) | BIT_REG_DELAY_L(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_REG_CLAMP_D_L BIT(6) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_REG_BYPASS_L_V1 BIT(5) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_REG_BYPASS_L_V2 BIT(5) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_REG_AUTOZCD_L BIT(4) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_POW_ZCD_L_V1 BIT(3) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_POW_ZCD_L_V2 BIT(3) #define BIT_REG_HALF_L BIT(2) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_SHIFT_OCP_L_2_1 0 #define BIT_MASK_OCP_L_2_1 0x3 #define BIT_OCP_L_2_1(x) (((x) & BIT_MASK_OCP_L_2_1) << BIT_SHIFT_OCP_L_2_1) #define BITS_OCP_L_2_1 (BIT_MASK_OCP_L_2_1 << BIT_SHIFT_OCP_L_2_1) #define BIT_CLEAR_OCP_L_2_1(x) ((x) & (~BITS_OCP_L_2_1)) #define BIT_GET_OCP_L_2_1(x) (((x) >> BIT_SHIFT_OCP_L_2_1) & BIT_MASK_OCP_L_2_1) #define BIT_SET_OCP_L_2_1(x, v) (BIT_CLEAR_OCP_L_2_1(x) | BIT_OCP_L_2_1(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ #define BIT_SHIFT_OCP_L_V2 0 #define BIT_MASK_OCP_L_V2 0x3 #define BIT_OCP_L_V2(x) (((x) & BIT_MASK_OCP_L_V2) << BIT_SHIFT_OCP_L_V2) #define BITS_OCP_L_V2 (BIT_MASK_OCP_L_V2 << BIT_SHIFT_OCP_L_V2) #define BIT_CLEAR_OCP_L_V2(x) ((x) & (~BITS_OCP_L_V2)) #define BIT_GET_OCP_L_V2(x) (((x) >> BIT_SHIFT_OCP_L_V2) & BIT_MASK_OCP_L_V2) #define BIT_SET_OCP_L_V2(x, v) (BIT_CLEAR_OCP_L_V2(x) | BIT_OCP_L_V2(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_SHIFT_LPF_C2_1_0 30 #define BIT_MASK_LPF_C2_1_0 0x3 #define BIT_LPF_C2_1_0(x) (((x) & BIT_MASK_LPF_C2_1_0) << BIT_SHIFT_LPF_C2_1_0) #define BITS_LPF_C2_1_0 (BIT_MASK_LPF_C2_1_0 << BIT_SHIFT_LPF_C2_1_0) #define BIT_CLEAR_LPF_C2_1_0(x) ((x) & (~BITS_LPF_C2_1_0)) #define BIT_GET_LPF_C2_1_0(x) \ (((x) >> BIT_SHIFT_LPF_C2_1_0) & BIT_MASK_LPF_C2_1_0) #define BIT_SET_LPF_C2_1_0(x, v) (BIT_CLEAR_LPF_C2_1_0(x) | BIT_LPF_C2_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_SHIFT_REG_LPF_R3 29 #define BIT_MASK_REG_LPF_R3 0x7 #define BIT_REG_LPF_R3(x) (((x) & BIT_MASK_REG_LPF_R3) << BIT_SHIFT_REG_LPF_R3) #define BITS_REG_LPF_R3 (BIT_MASK_REG_LPF_R3 << BIT_SHIFT_REG_LPF_R3) #define BIT_CLEAR_REG_LPF_R3(x) ((x) & (~BITS_REG_LPF_R3)) #define BIT_GET_REG_LPF_R3(x) \ (((x) >> BIT_SHIFT_REG_LPF_R3) & BIT_MASK_REG_LPF_R3) #define BIT_SET_REG_LPF_R3(x, v) (BIT_CLEAR_REG_LPF_R3(x) | BIT_REG_LPF_R3(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_EN_XTAL_AAC_TRIG BIT(28) #define BIT_EN_XTAL_AAC BIT(27) #define BIT_EN_XTAL_AAC_DIGI BIT(26) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_SHIFT_LPF_C1_5_0 24 #define BIT_MASK_LPF_C1_5_0 0x3f #define BIT_LPF_C1_5_0(x) (((x) & BIT_MASK_LPF_C1_5_0) << BIT_SHIFT_LPF_C1_5_0) #define BITS_LPF_C1_5_0 (BIT_MASK_LPF_C1_5_0 << BIT_SHIFT_LPF_C1_5_0) #define BIT_CLEAR_LPF_C1_5_0(x) ((x) & (~BITS_LPF_C1_5_0)) #define BIT_GET_LPF_C1_5_0(x) \ (((x) >> BIT_SHIFT_LPF_C1_5_0) & BIT_MASK_LPF_C1_5_0) #define BIT_SET_LPF_C1_5_0(x, v) (BIT_CLEAR_LPF_C1_5_0(x) | BIT_LPF_C1_5_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_SHIFT_REG_LPF_R2 24 #define BIT_MASK_REG_LPF_R2 0x1f #define BIT_REG_LPF_R2(x) (((x) & BIT_MASK_REG_LPF_R2) << BIT_SHIFT_REG_LPF_R2) #define BITS_REG_LPF_R2 (BIT_MASK_REG_LPF_R2 << BIT_SHIFT_REG_LPF_R2) #define BIT_CLEAR_REG_LPF_R2(x) ((x) & (~BITS_REG_LPF_R2)) #define BIT_GET_REG_LPF_R2(x) \ (((x) >> BIT_SHIFT_REG_LPF_R2) & BIT_MASK_REG_LPF_R2) #define BIT_SET_REG_LPF_R2(x, v) (BIT_CLEAR_REG_LPF_R2(x) | BIT_REG_LPF_R2(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_LPF_TIEL BIT(23) #define BIT_LPF_TIEH BIT(22) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_SHIFT_REG_LPF_C3 21 #define BIT_MASK_REG_LPF_C3 0x7 #define BIT_REG_LPF_C3(x) (((x) & BIT_MASK_REG_LPF_C3) << BIT_SHIFT_REG_LPF_C3) #define BITS_REG_LPF_C3 (BIT_MASK_REG_LPF_C3 << BIT_SHIFT_REG_LPF_C3) #define BIT_CLEAR_REG_LPF_C3(x) ((x) & (~BITS_REG_LPF_C3)) #define BIT_GET_REG_LPF_C3(x) \ (((x) >> BIT_SHIFT_REG_LPF_C3) & BIT_MASK_REG_LPF_C3) #define BIT_SET_REG_LPF_C3(x, v) (BIT_CLEAR_REG_LPF_C3(x) | BIT_REG_LPF_C3(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_SHIFT_LOCKDET_VREF_L_1_0 20 #define BIT_MASK_LOCKDET_VREF_L_1_0 0x3 #define BIT_LOCKDET_VREF_L_1_0(x) \ (((x) & BIT_MASK_LOCKDET_VREF_L_1_0) << BIT_SHIFT_LOCKDET_VREF_L_1_0) #define BITS_LOCKDET_VREF_L_1_0 \ (BIT_MASK_LOCKDET_VREF_L_1_0 << BIT_SHIFT_LOCKDET_VREF_L_1_0) #define BIT_CLEAR_LOCKDET_VREF_L_1_0(x) ((x) & (~BITS_LOCKDET_VREF_L_1_0)) #define BIT_GET_LOCKDET_VREF_L_1_0(x) \ (((x) >> BIT_SHIFT_LOCKDET_VREF_L_1_0) & BIT_MASK_LOCKDET_VREF_L_1_0) #define BIT_SET_LOCKDET_VREF_L_1_0(x, v) \ (BIT_CLEAR_LOCKDET_VREF_L_1_0(x) | BIT_LOCKDET_VREF_L_1_0(v)) #define BIT_SHIFT_LOCKDET_VREF_H_1_0 18 #define BIT_MASK_LOCKDET_VREF_H_1_0 0x3 #define BIT_LOCKDET_VREF_H_1_0(x) \ (((x) & BIT_MASK_LOCKDET_VREF_H_1_0) << BIT_SHIFT_LOCKDET_VREF_H_1_0) #define BITS_LOCKDET_VREF_H_1_0 \ (BIT_MASK_LOCKDET_VREF_H_1_0 << BIT_SHIFT_LOCKDET_VREF_H_1_0) #define BIT_CLEAR_LOCKDET_VREF_H_1_0(x) ((x) & (~BITS_LOCKDET_VREF_H_1_0)) #define BIT_GET_LOCKDET_VREF_H_1_0(x) \ (((x) >> BIT_SHIFT_LOCKDET_VREF_H_1_0) & BIT_MASK_LOCKDET_VREF_H_1_0) #define BIT_SET_LOCKDET_VREF_H_1_0(x, v) \ (BIT_CLEAR_LOCKDET_VREF_H_1_0(x) | BIT_LOCKDET_VREF_H_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_SHIFT_REG_LPF_C2 18 #define BIT_MASK_REG_LPF_C2 0x7 #define BIT_REG_LPF_C2(x) (((x) & BIT_MASK_REG_LPF_C2) << BIT_SHIFT_REG_LPF_C2) #define BITS_REG_LPF_C2 (BIT_MASK_REG_LPF_C2 << BIT_SHIFT_REG_LPF_C2) #define BIT_CLEAR_REG_LPF_C2(x) ((x) & (~BITS_REG_LPF_C2)) #define BIT_GET_REG_LPF_C2(x) \ (((x) >> BIT_SHIFT_REG_LPF_C2) & BIT_MASK_REG_LPF_C2) #define BIT_SET_REG_LPF_C2(x, v) (BIT_CLEAR_REG_LPF_C2(x) | BIT_REG_LPF_C2(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_SHIFT_LDO_SEL_1_0 16 #define BIT_MASK_LDO_SEL_1_0 0x3 #define BIT_LDO_SEL_1_0(x) \ (((x) & BIT_MASK_LDO_SEL_1_0) << BIT_SHIFT_LDO_SEL_1_0) #define BITS_LDO_SEL_1_0 (BIT_MASK_LDO_SEL_1_0 << BIT_SHIFT_LDO_SEL_1_0) #define BIT_CLEAR_LDO_SEL_1_0(x) ((x) & (~BITS_LDO_SEL_1_0)) #define BIT_GET_LDO_SEL_1_0(x) \ (((x) >> BIT_SHIFT_LDO_SEL_1_0) & BIT_MASK_LDO_SEL_1_0) #define BIT_SET_LDO_SEL_1_0(x, v) \ (BIT_CLEAR_LDO_SEL_1_0(x) | BIT_LDO_SEL_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_SHIFT_REG_LPF_C1 15 #define BIT_MASK_REG_LPF_C1 0x7 #define BIT_REG_LPF_C1(x) (((x) & BIT_MASK_REG_LPF_C1) << BIT_SHIFT_REG_LPF_C1) #define BITS_REG_LPF_C1 (BIT_MASK_REG_LPF_C1 << BIT_SHIFT_REG_LPF_C1) #define BIT_CLEAR_REG_LPF_C1(x) ((x) & (~BITS_REG_LPF_C1)) #define BIT_GET_REG_LPF_C1(x) \ (((x) >> BIT_SHIFT_REG_LPF_C1) & BIT_MASK_REG_LPF_C1) #define BIT_SET_REG_LPF_C1(x, v) (BIT_CLEAR_REG_LPF_C1(x) | BIT_REG_LPF_C1(v)) #define BIT_SHIFT_REG_LDO_SEL_V1 13 #define BIT_MASK_REG_LDO_SEL_V1 0x3 #define BIT_REG_LDO_SEL_V1(x) \ (((x) & BIT_MASK_REG_LDO_SEL_V1) << BIT_SHIFT_REG_LDO_SEL_V1) #define BITS_REG_LDO_SEL_V1 \ (BIT_MASK_REG_LDO_SEL_V1 << BIT_SHIFT_REG_LDO_SEL_V1) #define BIT_CLEAR_REG_LDO_SEL_V1(x) ((x) & (~BITS_REG_LDO_SEL_V1)) #define BIT_GET_REG_LDO_SEL_V1(x) \ (((x) >> BIT_SHIFT_REG_LDO_SEL_V1) & BIT_MASK_REG_LDO_SEL_V1) #define BIT_SET_REG_LDO_SEL_V1(x, v) \ (BIT_CLEAR_REG_LDO_SEL_V1(x) | BIT_REG_LDO_SEL_V1(v)) #define BIT_REG_CP_ICPX2 BIT(12) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_SHIFT_IOFFSET_5_0 10 #define BIT_MASK_IOFFSET_5_0 0x3f #define BIT_IOFFSET_5_0(x) \ (((x) & BIT_MASK_IOFFSET_5_0) << BIT_SHIFT_IOFFSET_5_0) #define BITS_IOFFSET_5_0 (BIT_MASK_IOFFSET_5_0 << BIT_SHIFT_IOFFSET_5_0) #define BIT_CLEAR_IOFFSET_5_0(x) ((x) & (~BITS_IOFFSET_5_0)) #define BIT_GET_IOFFSET_5_0(x) \ (((x) >> BIT_SHIFT_IOFFSET_5_0) & BIT_MASK_IOFFSET_5_0) #define BIT_SET_IOFFSET_5_0(x, v) \ (BIT_CLEAR_IOFFSET_5_0(x) | BIT_IOFFSET_5_0(v)) #define BIT_CP_ICPX2 BIT(9) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_SHIFT_REG_CP_ICP_SEL_FAST 9 #define BIT_MASK_REG_CP_ICP_SEL_FAST 0x7 #define BIT_REG_CP_ICP_SEL_FAST(x) \ (((x) & BIT_MASK_REG_CP_ICP_SEL_FAST) << BIT_SHIFT_REG_CP_ICP_SEL_FAST) #define BITS_REG_CP_ICP_SEL_FAST \ (BIT_MASK_REG_CP_ICP_SEL_FAST << BIT_SHIFT_REG_CP_ICP_SEL_FAST) #define BIT_CLEAR_REG_CP_ICP_SEL_FAST(x) ((x) & (~BITS_REG_CP_ICP_SEL_FAST)) #define BIT_GET_REG_CP_ICP_SEL_FAST(x) \ (((x) >> BIT_SHIFT_REG_CP_ICP_SEL_FAST) & BIT_MASK_REG_CP_ICP_SEL_FAST) #define BIT_SET_REG_CP_ICP_SEL_FAST(x, v) \ (BIT_CLEAR_REG_CP_ICP_SEL_FAST(x) | BIT_REG_CP_ICP_SEL_FAST(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_GM_STEP BIT(7) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_SHIFT_REG_CP_ICP_SEL 6 #define BIT_MASK_REG_CP_ICP_SEL 0x7 #define BIT_REG_CP_ICP_SEL(x) \ (((x) & BIT_MASK_REG_CP_ICP_SEL) << BIT_SHIFT_REG_CP_ICP_SEL) #define BITS_REG_CP_ICP_SEL \ (BIT_MASK_REG_CP_ICP_SEL << BIT_SHIFT_REG_CP_ICP_SEL) #define BIT_CLEAR_REG_CP_ICP_SEL(x) ((x) & (~BITS_REG_CP_ICP_SEL)) #define BIT_GET_REG_CP_ICP_SEL(x) \ (((x) >> BIT_SHIFT_REG_CP_ICP_SEL) & BIT_MASK_REG_CP_ICP_SEL) #define BIT_SET_REG_CP_ICP_SEL(x, v) \ (BIT_CLEAR_REG_CP_ICP_SEL(x) | BIT_REG_CP_ICP_SEL(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_SHIFT_CP_ICP_SEL_4_0 4 #define BIT_MASK_CP_ICP_SEL_4_0 0x1f #define BIT_CP_ICP_SEL_4_0(x) \ (((x) & BIT_MASK_CP_ICP_SEL_4_0) << BIT_SHIFT_CP_ICP_SEL_4_0) #define BITS_CP_ICP_SEL_4_0 \ (BIT_MASK_CP_ICP_SEL_4_0 << BIT_SHIFT_CP_ICP_SEL_4_0) #define BIT_CLEAR_CP_ICP_SEL_4_0(x) ((x) & (~BITS_CP_ICP_SEL_4_0)) #define BIT_GET_CP_ICP_SEL_4_0(x) \ (((x) >> BIT_SHIFT_CP_ICP_SEL_4_0) & BIT_MASK_CP_ICP_SEL_4_0) #define BIT_SET_CP_ICP_SEL_4_0(x, v) \ (BIT_CLEAR_CP_ICP_SEL_4_0(x) | BIT_CP_ICP_SEL_4_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_SHIFT_REG_IB_PI 4 #define BIT_MASK_REG_IB_PI 0x3 #define BIT_REG_IB_PI(x) (((x) & BIT_MASK_REG_IB_PI) << BIT_SHIFT_REG_IB_PI) #define BITS_REG_IB_PI (BIT_MASK_REG_IB_PI << BIT_SHIFT_REG_IB_PI) #define BIT_CLEAR_REG_IB_PI(x) ((x) & (~BITS_REG_IB_PI)) #define BIT_GET_REG_IB_PI(x) (((x) >> BIT_SHIFT_REG_IB_PI) & BIT_MASK_REG_IB_PI) #define BIT_SET_REG_IB_PI(x, v) (BIT_CLEAR_REG_IB_PI(x) | BIT_REG_IB_PI(v)) #define BIT_LDO2PWRCUT BIT(3) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_SHIFT_IB_PI_1_0 2 #define BIT_MASK_IB_PI_1_0 0x3 #define BIT_IB_PI_1_0(x) (((x) & BIT_MASK_IB_PI_1_0) << BIT_SHIFT_IB_PI_1_0) #define BITS_IB_PI_1_0 (BIT_MASK_IB_PI_1_0 << BIT_SHIFT_IB_PI_1_0) #define BIT_CLEAR_IB_PI_1_0(x) ((x) & (~BITS_IB_PI_1_0)) #define BIT_GET_IB_PI_1_0(x) (((x) >> BIT_SHIFT_IB_PI_1_0) & BIT_MASK_IB_PI_1_0) #define BIT_SET_IB_PI_1_0(x, v) (BIT_CLEAR_IB_PI_1_0(x) | BIT_IB_PI_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_VPULSE_LDO BIT(2) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ #define BIT_OFFSET_PLUS BIT(1) #define BIT_SHIFT_LDO_VSEL 0 #define BIT_MASK_LDO_VSEL 0x3 #define BIT_LDO_VSEL(x) (((x) & BIT_MASK_LDO_VSEL) << BIT_SHIFT_LDO_VSEL) #define BITS_LDO_VSEL (BIT_MASK_LDO_VSEL << BIT_SHIFT_LDO_VSEL) #define BIT_CLEAR_LDO_VSEL(x) ((x) & (~BITS_LDO_VSEL)) #define BIT_GET_LDO_VSEL(x) (((x) >> BIT_SHIFT_LDO_VSEL) & BIT_MASK_LDO_VSEL) #define BIT_SET_LDO_VSEL(x, v) (BIT_CLEAR_LDO_VSEL(x) | BIT_LDO_VSEL(v)) #define BIT_RESET_N BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_SHIFT_CKX_USB_IB_SEL 29 #define BIT_MASK_CKX_USB_IB_SEL 0x7 #define BIT_CKX_USB_IB_SEL(x) \ (((x) & BIT_MASK_CKX_USB_IB_SEL) << BIT_SHIFT_CKX_USB_IB_SEL) #define BITS_CKX_USB_IB_SEL \ (BIT_MASK_CKX_USB_IB_SEL << BIT_SHIFT_CKX_USB_IB_SEL) #define BIT_CLEAR_CKX_USB_IB_SEL(x) ((x) & (~BITS_CKX_USB_IB_SEL)) #define BIT_GET_CKX_USB_IB_SEL(x) \ (((x) >> BIT_SHIFT_CKX_USB_IB_SEL) & BIT_MASK_CKX_USB_IB_SEL) #define BIT_SET_CKX_USB_IB_SEL(x, v) \ (BIT_CLEAR_CKX_USB_IB_SEL(x) | BIT_CKX_USB_IB_SEL(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_SHIFT_REG_CK_MON_SEL 29 #define BIT_MASK_REG_CK_MON_SEL 0x7 #define BIT_REG_CK_MON_SEL(x) \ (((x) & BIT_MASK_REG_CK_MON_SEL) << BIT_SHIFT_REG_CK_MON_SEL) #define BITS_REG_CK_MON_SEL \ (BIT_MASK_REG_CK_MON_SEL << BIT_SHIFT_REG_CK_MON_SEL) #define BIT_CLEAR_REG_CK_MON_SEL(x) ((x) & (~BITS_REG_CK_MON_SEL)) #define BIT_GET_REG_CK_MON_SEL(x) \ (((x) >> BIT_SHIFT_REG_CK_MON_SEL) & BIT_MASK_REG_CK_MON_SEL) #define BIT_SET_REG_CK_MON_SEL(x, v) \ (BIT_CLEAR_REG_CK_MON_SEL(x) | BIT_REG_CK_MON_SEL(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_PFD_DN_GATED BIT(28) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_REG_CK_MON_EN BIT(28) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_PFD_UP_GATED BIT(27) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_REG_XTAL_FREQ_SEL BIT(27) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_PFD_RESET_GATED BIT(26) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_REG_XTAL_EDGE_SEL BIT(26) #define BIT_REG_VCO_KVCO BIT(25) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_SHIFT_PFD_OUT_DRV_1_0 24 #define BIT_MASK_PFD_OUT_DRV_1_0 0x3 #define BIT_PFD_OUT_DRV_1_0(x) \ (((x) & BIT_MASK_PFD_OUT_DRV_1_0) << BIT_SHIFT_PFD_OUT_DRV_1_0) #define BITS_PFD_OUT_DRV_1_0 \ (BIT_MASK_PFD_OUT_DRV_1_0 << BIT_SHIFT_PFD_OUT_DRV_1_0) #define BIT_CLEAR_PFD_OUT_DRV_1_0(x) ((x) & (~BITS_PFD_OUT_DRV_1_0)) #define BIT_GET_PFD_OUT_DRV_1_0(x) \ (((x) >> BIT_SHIFT_PFD_OUT_DRV_1_0) & BIT_MASK_PFD_OUT_DRV_1_0) #define BIT_SET_PFD_OUT_DRV_1_0(x, v) \ (BIT_CLEAR_PFD_OUT_DRV_1_0(x) | BIT_PFD_OUT_DRV_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_REG_SDM_EDGE_SEL BIT(24) #define BIT_REG_SDM_CK_SEL BIT(23) #define BIT_REG_SDM_CK_GATED BIT(22) #define BIT_REG_PFD_RESET_GATED BIT(21) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_SHIFT_LPF_TIEMID_2_0 20 #define BIT_MASK_LPF_TIEMID_2_0 0x7 #define BIT_LPF_TIEMID_2_0(x) \ (((x) & BIT_MASK_LPF_TIEMID_2_0) << BIT_SHIFT_LPF_TIEMID_2_0) #define BITS_LPF_TIEMID_2_0 \ (BIT_MASK_LPF_TIEMID_2_0 << BIT_SHIFT_LPF_TIEMID_2_0) #define BIT_CLEAR_LPF_TIEMID_2_0(x) ((x) & (~BITS_LPF_TIEMID_2_0)) #define BIT_GET_LPF_TIEMID_2_0(x) \ (((x) >> BIT_SHIFT_LPF_TIEMID_2_0) & BIT_MASK_LPF_TIEMID_2_0) #define BIT_SET_LPF_TIEMID_2_0(x, v) \ (BIT_CLEAR_LPF_TIEMID_2_0(x) | BIT_LPF_TIEMID_2_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_SHIFT_REG_LPF_R3_FAST 16 #define BIT_MASK_REG_LPF_R3_FAST 0x1f #define BIT_REG_LPF_R3_FAST(x) \ (((x) & BIT_MASK_REG_LPF_R3_FAST) << BIT_SHIFT_REG_LPF_R3_FAST) #define BITS_REG_LPF_R3_FAST \ (BIT_MASK_REG_LPF_R3_FAST << BIT_SHIFT_REG_LPF_R3_FAST) #define BIT_CLEAR_REG_LPF_R3_FAST(x) ((x) & (~BITS_REG_LPF_R3_FAST)) #define BIT_GET_REG_LPF_R3_FAST(x) \ (((x) >> BIT_SHIFT_REG_LPF_R3_FAST) & BIT_MASK_REG_LPF_R3_FAST) #define BIT_SET_REG_LPF_R3_FAST(x, v) \ (BIT_CLEAR_REG_LPF_R3_FAST(x) | BIT_REG_LPF_R3_FAST(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_SHIFT_LPF_R3_4_0 15 #define BIT_MASK_LPF_R3_4_0 0x1f #define BIT_LPF_R3_4_0(x) (((x) & BIT_MASK_LPF_R3_4_0) << BIT_SHIFT_LPF_R3_4_0) #define BITS_LPF_R3_4_0 (BIT_MASK_LPF_R3_4_0 << BIT_SHIFT_LPF_R3_4_0) #define BIT_CLEAR_LPF_R3_4_0(x) ((x) & (~BITS_LPF_R3_4_0)) #define BIT_GET_LPF_R3_4_0(x) \ (((x) >> BIT_SHIFT_LPF_R3_4_0) & BIT_MASK_LPF_R3_4_0) #define BIT_SET_LPF_R3_4_0(x, v) (BIT_CLEAR_LPF_R3_4_0(x) | BIT_LPF_R3_4_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_SHIFT_REG_LPF_R2_FAST 11 #define BIT_MASK_REG_LPF_R2_FAST 0x1f #define BIT_REG_LPF_R2_FAST(x) \ (((x) & BIT_MASK_REG_LPF_R2_FAST) << BIT_SHIFT_REG_LPF_R2_FAST) #define BITS_REG_LPF_R2_FAST \ (BIT_MASK_REG_LPF_R2_FAST << BIT_SHIFT_REG_LPF_R2_FAST) #define BIT_CLEAR_REG_LPF_R2_FAST(x) ((x) & (~BITS_REG_LPF_R2_FAST)) #define BIT_GET_REG_LPF_R2_FAST(x) \ (((x) >> BIT_SHIFT_REG_LPF_R2_FAST) & BIT_MASK_REG_LPF_R2_FAST) #define BIT_SET_REG_LPF_R2_FAST(x, v) \ (BIT_CLEAR_REG_LPF_R2_FAST(x) | BIT_REG_LPF_R2_FAST(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_SHIFT_LPF_R2_4_0 10 #define BIT_MASK_LPF_R2_4_0 0x1f #define BIT_LPF_R2_4_0(x) (((x) & BIT_MASK_LPF_R2_4_0) << BIT_SHIFT_LPF_R2_4_0) #define BITS_LPF_R2_4_0 (BIT_MASK_LPF_R2_4_0 << BIT_SHIFT_LPF_R2_4_0) #define BIT_CLEAR_LPF_R2_4_0(x) ((x) & (~BITS_LPF_R2_4_0)) #define BIT_GET_LPF_R2_4_0(x) \ (((x) >> BIT_SHIFT_LPF_R2_4_0) & BIT_MASK_LPF_R2_4_0) #define BIT_SET_LPF_R2_4_0(x, v) (BIT_CLEAR_LPF_R2_4_0(x) | BIT_LPF_R2_4_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_SHIFT_REG_LPF_C3_FAST 8 #define BIT_MASK_REG_LPF_C3_FAST 0x7 #define BIT_REG_LPF_C3_FAST(x) \ (((x) & BIT_MASK_REG_LPF_C3_FAST) << BIT_SHIFT_REG_LPF_C3_FAST) #define BITS_REG_LPF_C3_FAST \ (BIT_MASK_REG_LPF_C3_FAST << BIT_SHIFT_REG_LPF_C3_FAST) #define BIT_CLEAR_REG_LPF_C3_FAST(x) ((x) & (~BITS_REG_LPF_C3_FAST)) #define BIT_GET_REG_LPF_C3_FAST(x) \ (((x) >> BIT_SHIFT_REG_LPF_C3_FAST) & BIT_MASK_REG_LPF_C3_FAST) #define BIT_SET_REG_LPF_C3_FAST(x, v) \ (BIT_CLEAR_REG_LPF_C3_FAST(x) | BIT_REG_LPF_C3_FAST(v)) #define BIT_SHIFT_REG_LPF_C2_FAST 5 #define BIT_MASK_REG_LPF_C2_FAST 0x7 #define BIT_REG_LPF_C2_FAST(x) \ (((x) & BIT_MASK_REG_LPF_C2_FAST) << BIT_SHIFT_REG_LPF_C2_FAST) #define BITS_REG_LPF_C2_FAST \ (BIT_MASK_REG_LPF_C2_FAST << BIT_SHIFT_REG_LPF_C2_FAST) #define BIT_CLEAR_REG_LPF_C2_FAST(x) ((x) & (~BITS_REG_LPF_C2_FAST)) #define BIT_GET_REG_LPF_C2_FAST(x) \ (((x) >> BIT_SHIFT_REG_LPF_C2_FAST) & BIT_MASK_REG_LPF_C2_FAST) #define BIT_SET_REG_LPF_C2_FAST(x, v) \ (BIT_CLEAR_REG_LPF_C2_FAST(x) | BIT_REG_LPF_C2_FAST(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_SHIFT_LPF_C3_5_0 4 #define BIT_MASK_LPF_C3_5_0 0x3f #define BIT_LPF_C3_5_0(x) (((x) & BIT_MASK_LPF_C3_5_0) << BIT_SHIFT_LPF_C3_5_0) #define BITS_LPF_C3_5_0 (BIT_MASK_LPF_C3_5_0 << BIT_SHIFT_LPF_C3_5_0) #define BIT_CLEAR_LPF_C3_5_0(x) ((x) & (~BITS_LPF_C3_5_0)) #define BIT_GET_LPF_C3_5_0(x) \ (((x) >> BIT_SHIFT_LPF_C3_5_0) & BIT_MASK_LPF_C3_5_0) #define BIT_SET_LPF_C3_5_0(x, v) (BIT_CLEAR_LPF_C3_5_0(x) | BIT_LPF_C3_5_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_SHIFT_REG_LPF_C1_FAST 2 #define BIT_MASK_REG_LPF_C1_FAST 0x7 #define BIT_REG_LPF_C1_FAST(x) \ (((x) & BIT_MASK_REG_LPF_C1_FAST) << BIT_SHIFT_REG_LPF_C1_FAST) #define BITS_REG_LPF_C1_FAST \ (BIT_MASK_REG_LPF_C1_FAST << BIT_SHIFT_REG_LPF_C1_FAST) #define BIT_CLEAR_REG_LPF_C1_FAST(x) ((x) & (~BITS_REG_LPF_C1_FAST)) #define BIT_GET_REG_LPF_C1_FAST(x) \ (((x) >> BIT_SHIFT_REG_LPF_C1_FAST) & BIT_MASK_REG_LPF_C1_FAST) #define BIT_SET_REG_LPF_C1_FAST(x, v) \ (BIT_CLEAR_REG_LPF_C1_FAST(x) | BIT_REG_LPF_C1_FAST(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_SHIFT_LPF_C2_5_2 0 #define BIT_MASK_LPF_C2_5_2 0xf #define BIT_LPF_C2_5_2(x) (((x) & BIT_MASK_LPF_C2_5_2) << BIT_SHIFT_LPF_C2_5_2) #define BITS_LPF_C2_5_2 (BIT_MASK_LPF_C2_5_2 << BIT_SHIFT_LPF_C2_5_2) #define BIT_CLEAR_LPF_C2_5_2(x) ((x) & (~BITS_LPF_C2_5_2)) #define BIT_GET_LPF_C2_5_2(x) \ (((x) >> BIT_SHIFT_LPF_C2_5_2) & BIT_MASK_LPF_C2_5_2) #define BIT_SET_LPF_C2_5_2(x, v) (BIT_CLEAR_LPF_C2_5_2(x) | BIT_LPF_C2_5_2(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ #define BIT_SHIFT_REG_LPF_R3_V1 0 #define BIT_MASK_REG_LPF_R3_V1 0x3 #define BIT_REG_LPF_R3_V1(x) \ (((x) & BIT_MASK_REG_LPF_R3_V1) << BIT_SHIFT_REG_LPF_R3_V1) #define BITS_REG_LPF_R3_V1 (BIT_MASK_REG_LPF_R3_V1 << BIT_SHIFT_REG_LPF_R3_V1) #define BIT_CLEAR_REG_LPF_R3_V1(x) ((x) & (~BITS_REG_LPF_R3_V1)) #define BIT_GET_REG_LPF_R3_V1(x) \ (((x) >> BIT_SHIFT_REG_LPF_R3_V1) & BIT_MASK_REG_LPF_R3_V1) #define BIT_SET_REG_LPF_R3_V1(x, v) \ (BIT_CLEAR_REG_LPF_R3_V1(x) | BIT_REG_LPF_R3_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_CK_PHASE_SEL BIT(31) #define BIT_CK960M_EN BIT(30) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_SHIFT_AGPIO_DRV_V1 30 #define BIT_MASK_AGPIO_DRV_V1 0x3 #define BIT_AGPIO_DRV_V1(x) \ (((x) & BIT_MASK_AGPIO_DRV_V1) << BIT_SHIFT_AGPIO_DRV_V1) #define BITS_AGPIO_DRV_V1 (BIT_MASK_AGPIO_DRV_V1 << BIT_SHIFT_AGPIO_DRV_V1) #define BIT_CLEAR_AGPIO_DRV_V1(x) ((x) & (~BITS_AGPIO_DRV_V1)) #define BIT_GET_AGPIO_DRV_V1(x) \ (((x) >> BIT_SHIFT_AGPIO_DRV_V1) & BIT_MASK_AGPIO_DRV_V1) #define BIT_SET_AGPIO_DRV_V1(x, v) \ (BIT_CLEAR_AGPIO_DRV_V1(x) | BIT_AGPIO_DRV_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_CK640M_EN BIT(29) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_AGPIO_GPO_V1 BIT(29) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_CK240M_EN BIT(28) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_AGPIO_GPE_V1 BIT(28) #define BIT_SEL_CLK BIT(27) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_SHIFT_CK_MON_SEL_2_0 25 #define BIT_MASK_CK_MON_SEL_2_0 0x7 #define BIT_CK_MON_SEL_2_0(x) \ (((x) & BIT_MASK_CK_MON_SEL_2_0) << BIT_SHIFT_CK_MON_SEL_2_0) #define BITS_CK_MON_SEL_2_0 \ (BIT_MASK_CK_MON_SEL_2_0 << BIT_SHIFT_CK_MON_SEL_2_0) #define BIT_CLEAR_CK_MON_SEL_2_0(x) ((x) & (~BITS_CK_MON_SEL_2_0)) #define BIT_GET_CK_MON_SEL_2_0(x) \ (((x) >> BIT_SHIFT_CK_MON_SEL_2_0) & BIT_MASK_CK_MON_SEL_2_0) #define BIT_SET_CK_MON_SEL_2_0(x, v) \ (BIT_CLEAR_CK_MON_SEL_2_0(x) | BIT_CK_MON_SEL_2_0(v)) #define BIT_CK_MON_EN_V1 BIT(24) #define BIT_XTAL_SOURCE_SEL BIT(23) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_SHIFT_LS_XTAL_SEL 23 #define BIT_MASK_LS_XTAL_SEL 0xf #define BIT_LS_XTAL_SEL(x) \ (((x) & BIT_MASK_LS_XTAL_SEL) << BIT_SHIFT_LS_XTAL_SEL) #define BITS_LS_XTAL_SEL (BIT_MASK_LS_XTAL_SEL << BIT_SHIFT_LS_XTAL_SEL) #define BIT_CLEAR_LS_XTAL_SEL(x) ((x) & (~BITS_LS_XTAL_SEL)) #define BIT_GET_LS_XTAL_SEL(x) \ (((x) >> BIT_SHIFT_LS_XTAL_SEL) & BIT_MASK_LS_XTAL_SEL) #define BIT_SET_LS_XTAL_SEL(x, v) \ (BIT_CLEAR_LS_XTAL_SEL(x) | BIT_LS_XTAL_SEL(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_XTAL_FREQ_SEL BIT(22) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_LS_SDM_ORDER_V1 BIT(22) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_XTAL_EDGE_SEL BIT(21) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_LS_DELAY_PH BIT(21) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_XTAL_BUF_SEL BIT(20) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_DIVIDER_SEL BIT(20) #define BIT_SHIFT_PCODE 15 #define BIT_MASK_PCODE 0x1f #define BIT_PCODE(x) (((x) & BIT_MASK_PCODE) << BIT_SHIFT_PCODE) #define BITS_PCODE (BIT_MASK_PCODE << BIT_SHIFT_PCODE) #define BIT_CLEAR_PCODE(x) ((x) & (~BITS_PCODE)) #define BIT_GET_PCODE(x) (((x) >> BIT_SHIFT_PCODE) & BIT_MASK_PCODE) #define BIT_SET_PCODE(x, v) (BIT_CLEAR_PCODE(x) | BIT_PCODE(v)) #define BIT_SHIFT_NCODE 7 #define BIT_MASK_NCODE 0xff #define BIT_NCODE(x) (((x) & BIT_MASK_NCODE) << BIT_SHIFT_NCODE) #define BITS_NCODE (BIT_MASK_NCODE << BIT_SHIFT_NCODE) #define BIT_CLEAR_NCODE(x) ((x) & (~BITS_NCODE)) #define BIT_GET_NCODE(x) (((x) >> BIT_SHIFT_NCODE) & BIT_MASK_NCODE) #define BIT_SET_NCODE(x, v) (BIT_CLEAR_NCODE(x) | BIT_NCODE(v)) #define BIT_REG_BEACON BIT(6) #define BIT_REG_MBIASE BIT(5) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_SHIFT_VCO_CV_7_0 4 #define BIT_MASK_VCO_CV_7_0 0xff #define BIT_VCO_CV_7_0(x) (((x) & BIT_MASK_VCO_CV_7_0) << BIT_SHIFT_VCO_CV_7_0) #define BITS_VCO_CV_7_0 (BIT_MASK_VCO_CV_7_0 << BIT_SHIFT_VCO_CV_7_0) #define BIT_CLEAR_VCO_CV_7_0(x) ((x) & (~BITS_VCO_CV_7_0)) #define BIT_GET_VCO_CV_7_0(x) \ (((x) >> BIT_SHIFT_VCO_CV_7_0) & BIT_MASK_VCO_CV_7_0) #define BIT_SET_VCO_CV_7_0(x, v) (BIT_CLEAR_VCO_CV_7_0(x) | BIT_VCO_CV_7_0(v)) #define BIT_VCO_KVCO BIT(3) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_SHIFT_REG_FAST_SEL 3 #define BIT_MASK_REG_FAST_SEL 0x3 #define BIT_REG_FAST_SEL(x) \ (((x) & BIT_MASK_REG_FAST_SEL) << BIT_SHIFT_REG_FAST_SEL) #define BITS_REG_FAST_SEL (BIT_MASK_REG_FAST_SEL << BIT_SHIFT_REG_FAST_SEL) #define BIT_CLEAR_REG_FAST_SEL(x) ((x) & (~BITS_REG_FAST_SEL)) #define BIT_GET_REG_FAST_SEL(x) \ (((x) >> BIT_SHIFT_REG_FAST_SEL) & BIT_MASK_REG_FAST_SEL) #define BIT_SET_REG_FAST_SEL(x, v) \ (BIT_CLEAR_REG_FAST_SEL(x) | BIT_REG_FAST_SEL(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_SDM_EDGE_SEL BIT(2) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_REG_CK960M_EN BIT(2) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_SDM_CK_SEL BIT(1) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_REG_CK320M_EN BIT(1) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_SDM_CK_GATED BIT(0) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ #define BIT_REG_CK_5M_EN BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_MAC_3 (Offset 0x1024) */ #define BIT_SHIFT_LCK_WAIT_CYCLE_2_0 28 #define BIT_MASK_LCK_WAIT_CYCLE_2_0 0x7 #define BIT_LCK_WAIT_CYCLE_2_0(x) \ (((x) & BIT_MASK_LCK_WAIT_CYCLE_2_0) << BIT_SHIFT_LCK_WAIT_CYCLE_2_0) #define BITS_LCK_WAIT_CYCLE_2_0 \ (BIT_MASK_LCK_WAIT_CYCLE_2_0 << BIT_SHIFT_LCK_WAIT_CYCLE_2_0) #define BIT_CLEAR_LCK_WAIT_CYCLE_2_0(x) ((x) & (~BITS_LCK_WAIT_CYCLE_2_0)) #define BIT_GET_LCK_WAIT_CYCLE_2_0(x) \ (((x) >> BIT_SHIFT_LCK_WAIT_CYCLE_2_0) & BIT_MASK_LCK_WAIT_CYCLE_2_0) #define BIT_SET_LCK_WAIT_CYCLE_2_0(x, v) \ (BIT_CLEAR_LCK_WAIT_CYCLE_2_0(x) | BIT_LCK_WAIT_CYCLE_2_0(v)) #define BIT_SHIFT_LCK_VCO_DIVISOR_1_0 26 #define BIT_MASK_LCK_VCO_DIVISOR_1_0 0x3 #define BIT_LCK_VCO_DIVISOR_1_0(x) \ (((x) & BIT_MASK_LCK_VCO_DIVISOR_1_0) << BIT_SHIFT_LCK_VCO_DIVISOR_1_0) #define BITS_LCK_VCO_DIVISOR_1_0 \ (BIT_MASK_LCK_VCO_DIVISOR_1_0 << BIT_SHIFT_LCK_VCO_DIVISOR_1_0) #define BIT_CLEAR_LCK_VCO_DIVISOR_1_0(x) ((x) & (~BITS_LCK_VCO_DIVISOR_1_0)) #define BIT_GET_LCK_VCO_DIVISOR_1_0(x) \ (((x) >> BIT_SHIFT_LCK_VCO_DIVISOR_1_0) & BIT_MASK_LCK_VCO_DIVISOR_1_0) #define BIT_SET_LCK_VCO_DIVISOR_1_0(x, v) \ (BIT_CLEAR_LCK_VCO_DIVISOR_1_0(x) | BIT_LCK_VCO_DIVISOR_1_0(v)) #define BIT_SHIFT_LCK_SEARCH_MODE_1_0 24 #define BIT_MASK_LCK_SEARCH_MODE_1_0 0x3 #define BIT_LCK_SEARCH_MODE_1_0(x) \ (((x) & BIT_MASK_LCK_SEARCH_MODE_1_0) << BIT_SHIFT_LCK_SEARCH_MODE_1_0) #define BITS_LCK_SEARCH_MODE_1_0 \ (BIT_MASK_LCK_SEARCH_MODE_1_0 << BIT_SHIFT_LCK_SEARCH_MODE_1_0) #define BIT_CLEAR_LCK_SEARCH_MODE_1_0(x) ((x) & (~BITS_LCK_SEARCH_MODE_1_0)) #define BIT_GET_LCK_SEARCH_MODE_1_0(x) \ (((x) >> BIT_SHIFT_LCK_SEARCH_MODE_1_0) & BIT_MASK_LCK_SEARCH_MODE_1_0) #define BIT_SET_LCK_SEARCH_MODE_1_0(x, v) \ (BIT_CLEAR_LCK_SEARCH_MODE_1_0(x) | BIT_LCK_SEARCH_MODE_1_0(v)) #define BIT_SHIFT_LS_CV_OFFSET_3_0 12 #define BIT_MASK_LS_CV_OFFSET_3_0 0xf #define BIT_LS_CV_OFFSET_3_0(x) \ (((x) & BIT_MASK_LS_CV_OFFSET_3_0) << BIT_SHIFT_LS_CV_OFFSET_3_0) #define BITS_LS_CV_OFFSET_3_0 \ (BIT_MASK_LS_CV_OFFSET_3_0 << BIT_SHIFT_LS_CV_OFFSET_3_0) #define BIT_CLEAR_LS_CV_OFFSET_3_0(x) ((x) & (~BITS_LS_CV_OFFSET_3_0)) #define BIT_GET_LS_CV_OFFSET_3_0(x) \ (((x) >> BIT_SHIFT_LS_CV_OFFSET_3_0) & BIT_MASK_LS_CV_OFFSET_3_0) #define BIT_SET_LS_CV_OFFSET_3_0(x, v) \ (BIT_CLEAR_LS_CV_OFFSET_3_0(x) | BIT_LS_CV_OFFSET_3_0(v)) #define BIT_LS_EN_LC_CK40M BIT(11) #define BIT_LS__CV_MANUAL BIT(10) #define BIT_LS_PYPASS_PI BIT(9) #define BIT_MBIASE BIT(4) /* 2 REG_ANAPAR_MAC_4 (Offset 0x1028) */ #define BIT_LS_TIE_MID_MODE BIT(28) #define BIT_SHIFT_LS_SYNC_CYCLE_1_0 26 #define BIT_MASK_LS_SYNC_CYCLE_1_0 0x3 #define BIT_LS_SYNC_CYCLE_1_0(x) \ (((x) & BIT_MASK_LS_SYNC_CYCLE_1_0) << BIT_SHIFT_LS_SYNC_CYCLE_1_0) #define BITS_LS_SYNC_CYCLE_1_0 \ (BIT_MASK_LS_SYNC_CYCLE_1_0 << BIT_SHIFT_LS_SYNC_CYCLE_1_0) #define BIT_CLEAR_LS_SYNC_CYCLE_1_0(x) ((x) & (~BITS_LS_SYNC_CYCLE_1_0)) #define BIT_GET_LS_SYNC_CYCLE_1_0(x) \ (((x) >> BIT_SHIFT_LS_SYNC_CYCLE_1_0) & BIT_MASK_LS_SYNC_CYCLE_1_0) #define BIT_SET_LS_SYNC_CYCLE_1_0(x, v) \ (BIT_CLEAR_LS_SYNC_CYCLE_1_0(x) | BIT_LS_SYNC_CYCLE_1_0(v)) #define BIT_LS_SDM_ORDER BIT(25) #define BIT_LS_RST_LC_CAL BIT(14) #define BIT_LS_RSTB BIT(13) #define BIT_LS_POW_LC_CAL_PREP BIT(11) #define BIT_SHIFT_LCK_XTAL_DIVISOR_1_0 0 #define BIT_MASK_LCK_XTAL_DIVISOR_1_0 0x3 #define BIT_LCK_XTAL_DIVISOR_1_0(x) \ (((x) & BIT_MASK_LCK_XTAL_DIVISOR_1_0) \ << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0) #define BITS_LCK_XTAL_DIVISOR_1_0 \ (BIT_MASK_LCK_XTAL_DIVISOR_1_0 << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0) #define BIT_CLEAR_LCK_XTAL_DIVISOR_1_0(x) ((x) & (~BITS_LCK_XTAL_DIVISOR_1_0)) #define BIT_GET_LCK_XTAL_DIVISOR_1_0(x) \ (((x) >> BIT_SHIFT_LCK_XTAL_DIVISOR_1_0) & \ BIT_MASK_LCK_XTAL_DIVISOR_1_0) #define BIT_SET_LCK_XTAL_DIVISOR_1_0(x, v) \ (BIT_CLEAR_LCK_XTAL_DIVISOR_1_0(x) | BIT_LCK_XTAL_DIVISOR_1_0(v)) /* 2 REG_ANAPAR_MAC_5 (Offset 0x102C) */ #define BIT_SHIFT_LS_XTAL_SEL_3_0 0 #define BIT_MASK_LS_XTAL_SEL_3_0 0xf #define BIT_LS_XTAL_SEL_3_0(x) \ (((x) & BIT_MASK_LS_XTAL_SEL_3_0) << BIT_SHIFT_LS_XTAL_SEL_3_0) #define BITS_LS_XTAL_SEL_3_0 \ (BIT_MASK_LS_XTAL_SEL_3_0 << BIT_SHIFT_LS_XTAL_SEL_3_0) #define BIT_CLEAR_LS_XTAL_SEL_3_0(x) ((x) & (~BITS_LS_XTAL_SEL_3_0)) #define BIT_GET_LS_XTAL_SEL_3_0(x) \ (((x) >> BIT_SHIFT_LS_XTAL_SEL_3_0) & BIT_MASK_LS_XTAL_SEL_3_0) #define BIT_SET_LS_XTAL_SEL_3_0(x, v) \ (BIT_CLEAR_LS_XTAL_SEL_3_0(x) | BIT_LS_XTAL_SEL_3_0(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CFG4 (Offset 0x1034) */ #define BIT_EF_CSER_1 BIT(26) #define BIT_SW_PG_EN_1 BIT(10) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ #define BIT_XTAL_DRV_RF1_0 BIT(31) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ #define BIT_XTAL_SC_LPS BIT(31) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ #define BIT_XTAL_GATED_RF1N BIT(30) #define BIT_XTAL_GATED_RF1P BIT(29) #define BIT_XTAL_GM_SEP_V2 BIT(28) #define BIT_SHIFT_XTAL_LDO_1_0 26 #define BIT_MASK_XTAL_LDO_1_0 0x3 #define BIT_XTAL_LDO_1_0(x) \ (((x) & BIT_MASK_XTAL_LDO_1_0) << BIT_SHIFT_XTAL_LDO_1_0) #define BITS_XTAL_LDO_1_0 (BIT_MASK_XTAL_LDO_1_0 << BIT_SHIFT_XTAL_LDO_1_0) #define BIT_CLEAR_XTAL_LDO_1_0(x) ((x) & (~BITS_XTAL_LDO_1_0)) #define BIT_GET_XTAL_LDO_1_0(x) \ (((x) >> BIT_SHIFT_XTAL_LDO_1_0) & BIT_MASK_XTAL_LDO_1_0) #define BIT_SET_XTAL_LDO_1_0(x, v) \ (BIT_CLEAR_XTAL_LDO_1_0(x) | BIT_XTAL_LDO_1_0(v)) #define BIT_XQSEL_V1 BIT(25) #define BIT_GATED_XTAL_OK0 BIT(24) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ #define BIT_SHIFT_XTAL_SC_INIT 24 #define BIT_MASK_XTAL_SC_INIT 0x7f #define BIT_XTAL_SC_INIT(x) \ (((x) & BIT_MASK_XTAL_SC_INIT) << BIT_SHIFT_XTAL_SC_INIT) #define BITS_XTAL_SC_INIT (BIT_MASK_XTAL_SC_INIT << BIT_SHIFT_XTAL_SC_INIT) #define BIT_CLEAR_XTAL_SC_INIT(x) ((x) & (~BITS_XTAL_SC_INIT)) #define BIT_GET_XTAL_SC_INIT(x) \ (((x) >> BIT_SHIFT_XTAL_SC_INIT) & BIT_MASK_XTAL_SC_INIT) #define BIT_SET_XTAL_SC_INIT(x, v) \ (BIT_CLEAR_XTAL_SC_INIT(x) | BIT_XTAL_SC_INIT(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ #define BIT_SHIFT_XTAL_SC_XO_6_0 17 #define BIT_MASK_XTAL_SC_XO_6_0 0x7f #define BIT_XTAL_SC_XO_6_0(x) \ (((x) & BIT_MASK_XTAL_SC_XO_6_0) << BIT_SHIFT_XTAL_SC_XO_6_0) #define BITS_XTAL_SC_XO_6_0 \ (BIT_MASK_XTAL_SC_XO_6_0 << BIT_SHIFT_XTAL_SC_XO_6_0) #define BIT_CLEAR_XTAL_SC_XO_6_0(x) ((x) & (~BITS_XTAL_SC_XO_6_0)) #define BIT_GET_XTAL_SC_XO_6_0(x) \ (((x) >> BIT_SHIFT_XTAL_SC_XO_6_0) & BIT_MASK_XTAL_SC_XO_6_0) #define BIT_SET_XTAL_SC_XO_6_0(x, v) \ (BIT_CLEAR_XTAL_SC_XO_6_0(x) | BIT_XTAL_SC_XO_6_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ #define BIT_SHIFT_XTAL_SC_XO 17 #define BIT_MASK_XTAL_SC_XO 0x7f #define BIT_XTAL_SC_XO(x) (((x) & BIT_MASK_XTAL_SC_XO) << BIT_SHIFT_XTAL_SC_XO) #define BITS_XTAL_SC_XO (BIT_MASK_XTAL_SC_XO << BIT_SHIFT_XTAL_SC_XO) #define BIT_CLEAR_XTAL_SC_XO(x) ((x) & (~BITS_XTAL_SC_XO)) #define BIT_GET_XTAL_SC_XO(x) \ (((x) >> BIT_SHIFT_XTAL_SC_XO) & BIT_MASK_XTAL_SC_XO) #define BIT_SET_XTAL_SC_XO(x, v) (BIT_CLEAR_XTAL_SC_XO(x) | BIT_XTAL_SC_XO(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ #define BIT_SHIFT_XTAL_SC_XI_6_0 10 #define BIT_MASK_XTAL_SC_XI_6_0 0x7f #define BIT_XTAL_SC_XI_6_0(x) \ (((x) & BIT_MASK_XTAL_SC_XI_6_0) << BIT_SHIFT_XTAL_SC_XI_6_0) #define BITS_XTAL_SC_XI_6_0 \ (BIT_MASK_XTAL_SC_XI_6_0 << BIT_SHIFT_XTAL_SC_XI_6_0) #define BIT_CLEAR_XTAL_SC_XI_6_0(x) ((x) & (~BITS_XTAL_SC_XI_6_0)) #define BIT_GET_XTAL_SC_XI_6_0(x) \ (((x) >> BIT_SHIFT_XTAL_SC_XI_6_0) & BIT_MASK_XTAL_SC_XI_6_0) #define BIT_SET_XTAL_SC_XI_6_0(x, v) \ (BIT_CLEAR_XTAL_SC_XI_6_0(x) | BIT_XTAL_SC_XI_6_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ #define BIT_SHIFT_XTAL_SC_XI 10 #define BIT_MASK_XTAL_SC_XI 0x7f #define BIT_XTAL_SC_XI(x) (((x) & BIT_MASK_XTAL_SC_XI) << BIT_SHIFT_XTAL_SC_XI) #define BITS_XTAL_SC_XI (BIT_MASK_XTAL_SC_XI << BIT_SHIFT_XTAL_SC_XI) #define BIT_CLEAR_XTAL_SC_XI(x) ((x) & (~BITS_XTAL_SC_XI)) #define BIT_GET_XTAL_SC_XI(x) \ (((x) >> BIT_SHIFT_XTAL_SC_XI) & BIT_MASK_XTAL_SC_XI) #define BIT_SET_XTAL_SC_XI(x, v) (BIT_CLEAR_XTAL_SC_XI(x) | BIT_XTAL_SC_XI(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ #define BIT_SHIFT_XTAL_GMN_4_0 5 #define BIT_MASK_XTAL_GMN_4_0 0x1f #define BIT_XTAL_GMN_4_0(x) \ (((x) & BIT_MASK_XTAL_GMN_4_0) << BIT_SHIFT_XTAL_GMN_4_0) #define BITS_XTAL_GMN_4_0 (BIT_MASK_XTAL_GMN_4_0 << BIT_SHIFT_XTAL_GMN_4_0) #define BIT_CLEAR_XTAL_GMN_4_0(x) ((x) & (~BITS_XTAL_GMN_4_0)) #define BIT_GET_XTAL_GMN_4_0(x) \ (((x) >> BIT_SHIFT_XTAL_GMN_4_0) & BIT_MASK_XTAL_GMN_4_0) #define BIT_SET_XTAL_GMN_4_0(x, v) \ (BIT_CLEAR_XTAL_GMN_4_0(x) | BIT_XTAL_GMN_4_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ #define BIT_SHIFT_XTAL_GMN_V3 5 #define BIT_MASK_XTAL_GMN_V3 0x1f #define BIT_XTAL_GMN_V3(x) \ (((x) & BIT_MASK_XTAL_GMN_V3) << BIT_SHIFT_XTAL_GMN_V3) #define BITS_XTAL_GMN_V3 (BIT_MASK_XTAL_GMN_V3 << BIT_SHIFT_XTAL_GMN_V3) #define BIT_CLEAR_XTAL_GMN_V3(x) ((x) & (~BITS_XTAL_GMN_V3)) #define BIT_GET_XTAL_GMN_V3(x) \ (((x) >> BIT_SHIFT_XTAL_GMN_V3) & BIT_MASK_XTAL_GMN_V3) #define BIT_SET_XTAL_GMN_V3(x, v) \ (BIT_CLEAR_XTAL_GMN_V3(x) | BIT_XTAL_GMN_V3(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ #define BIT_SHIFT_XTAL_GMP_4_0 0 #define BIT_MASK_XTAL_GMP_4_0 0x1f #define BIT_XTAL_GMP_4_0(x) \ (((x) & BIT_MASK_XTAL_GMP_4_0) << BIT_SHIFT_XTAL_GMP_4_0) #define BITS_XTAL_GMP_4_0 (BIT_MASK_XTAL_GMP_4_0 << BIT_SHIFT_XTAL_GMP_4_0) #define BIT_CLEAR_XTAL_GMP_4_0(x) ((x) & (~BITS_XTAL_GMP_4_0)) #define BIT_GET_XTAL_GMP_4_0(x) \ (((x) >> BIT_SHIFT_XTAL_GMP_4_0) & BIT_MASK_XTAL_GMP_4_0) #define BIT_SET_XTAL_GMP_4_0(x, v) \ (BIT_CLEAR_XTAL_GMP_4_0(x) | BIT_XTAL_GMP_4_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ #define BIT_SHIFT_XTAL_GMP_V3 0 #define BIT_MASK_XTAL_GMP_V3 0x1f #define BIT_XTAL_GMP_V3(x) \ (((x) & BIT_MASK_XTAL_GMP_V3) << BIT_SHIFT_XTAL_GMP_V3) #define BITS_XTAL_GMP_V3 (BIT_MASK_XTAL_GMP_V3 << BIT_SHIFT_XTAL_GMP_V3) #define BIT_CLEAR_XTAL_GMP_V3(x) ((x) & (~BITS_XTAL_GMP_V3)) #define BIT_GET_XTAL_GMP_V3(x) \ (((x) >> BIT_SHIFT_XTAL_GMP_V3) & BIT_MASK_XTAL_GMP_V3) #define BIT_SET_XTAL_GMP_V3(x, v) \ (BIT_CLEAR_XTAL_GMP_V3(x) | BIT_XTAL_GMP_V3(v)) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_XTAL_SEL_TOK_V1 BIT(31) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_SHIFT_XTAL_LDO_OK_1_0 30 #define BIT_MASK_XTAL_LDO_OK_1_0 0x3 #define BIT_XTAL_LDO_OK_1_0(x) \ (((x) & BIT_MASK_XTAL_LDO_OK_1_0) << BIT_SHIFT_XTAL_LDO_OK_1_0) #define BITS_XTAL_LDO_OK_1_0 \ (BIT_MASK_XTAL_LDO_OK_1_0 << BIT_SHIFT_XTAL_LDO_OK_1_0) #define BIT_CLEAR_XTAL_LDO_OK_1_0(x) ((x) & (~BITS_XTAL_LDO_OK_1_0)) #define BIT_GET_XTAL_LDO_OK_1_0(x) \ (((x) >> BIT_SHIFT_XTAL_LDO_OK_1_0) & BIT_MASK_XTAL_LDO_OK_1_0) #define BIT_SET_XTAL_LDO_OK_1_0(x, v) \ (BIT_CLEAR_XTAL_LDO_OK_1_0(x) | BIT_XTAL_LDO_OK_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_XTAL_DELAY_DIGI_V2 BIT(30) #define BIT_XTAL_DELAY_USB_V2 BIT(29) #define BIT_XTAL_DELAY_AFE_V2 BIT(28) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_SHIFT_XTAL_XORES_SEL_2_0 27 #define BIT_MASK_XTAL_XORES_SEL_2_0 0x7 #define BIT_XTAL_XORES_SEL_2_0(x) \ (((x) & BIT_MASK_XTAL_XORES_SEL_2_0) << BIT_SHIFT_XTAL_XORES_SEL_2_0) #define BITS_XTAL_XORES_SEL_2_0 \ (BIT_MASK_XTAL_XORES_SEL_2_0 << BIT_SHIFT_XTAL_XORES_SEL_2_0) #define BIT_CLEAR_XTAL_XORES_SEL_2_0(x) ((x) & (~BITS_XTAL_XORES_SEL_2_0)) #define BIT_GET_XTAL_XORES_SEL_2_0(x) \ (((x) >> BIT_SHIFT_XTAL_XORES_SEL_2_0) & BIT_MASK_XTAL_XORES_SEL_2_0) #define BIT_SET_XTAL_XORES_SEL_2_0(x, v) \ (BIT_CLEAR_XTAL_XORES_SEL_2_0(x) | BIT_XTAL_XORES_SEL_2_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_SHIFT_XTAL_DRV_DIGI_V2 26 #define BIT_MASK_XTAL_DRV_DIGI_V2 0x3 #define BIT_XTAL_DRV_DIGI_V2(x) \ (((x) & BIT_MASK_XTAL_DRV_DIGI_V2) << BIT_SHIFT_XTAL_DRV_DIGI_V2) #define BITS_XTAL_DRV_DIGI_V2 \ (BIT_MASK_XTAL_DRV_DIGI_V2 << BIT_SHIFT_XTAL_DRV_DIGI_V2) #define BIT_CLEAR_XTAL_DRV_DIGI_V2(x) ((x) & (~BITS_XTAL_DRV_DIGI_V2)) #define BIT_GET_XTAL_DRV_DIGI_V2(x) \ (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_V2) & BIT_MASK_XTAL_DRV_DIGI_V2) #define BIT_SET_XTAL_DRV_DIGI_V2(x, v) \ (BIT_CLEAR_XTAL_DRV_DIGI_V2(x) | BIT_XTAL_DRV_DIGI_V2(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_SHIFT_XTAL_AAC_PK_SEL_1_0 25 #define BIT_MASK_XTAL_AAC_PK_SEL_1_0 0x3 #define BIT_XTAL_AAC_PK_SEL_1_0(x) \ (((x) & BIT_MASK_XTAL_AAC_PK_SEL_1_0) << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0) #define BITS_XTAL_AAC_PK_SEL_1_0 \ (BIT_MASK_XTAL_AAC_PK_SEL_1_0 << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0) #define BIT_CLEAR_XTAL_AAC_PK_SEL_1_0(x) ((x) & (~BITS_XTAL_AAC_PK_SEL_1_0)) #define BIT_GET_XTAL_AAC_PK_SEL_1_0(x) \ (((x) >> BIT_SHIFT_XTAL_AAC_PK_SEL_1_0) & BIT_MASK_XTAL_AAC_PK_SEL_1_0) #define BIT_SET_XTAL_AAC_PK_SEL_1_0(x, v) \ (BIT_CLEAR_XTAL_AAC_PK_SEL_1_0(x) | BIT_XTAL_AAC_PK_SEL_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_EN_XTAL_DRV_LPS BIT(25) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_EN_XTAL_AAC_PKDET BIT(24) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_EN_XTAL_DRV_DIGI_V2 BIT(24) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_EN_XTAL_AAC_GM BIT(23) #define BIT_XTAL_LPMODE BIT(22) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_SHIFT_XTAL_DRV_USB 22 #define BIT_MASK_XTAL_DRV_USB 0x3 #define BIT_XTAL_DRV_USB(x) \ (((x) & BIT_MASK_XTAL_DRV_USB) << BIT_SHIFT_XTAL_DRV_USB) #define BITS_XTAL_DRV_USB (BIT_MASK_XTAL_DRV_USB << BIT_SHIFT_XTAL_DRV_USB) #define BIT_CLEAR_XTAL_DRV_USB(x) ((x) & (~BITS_XTAL_DRV_USB)) #define BIT_GET_XTAL_DRV_USB(x) \ (((x) >> BIT_SHIFT_XTAL_DRV_USB) & BIT_MASK_XTAL_DRV_USB) #define BIT_SET_XTAL_DRV_USB(x, v) \ (BIT_CLEAR_XTAL_DRV_USB(x) | BIT_XTAL_DRV_USB(v)) #define BIT_EN_XTAL_DRV_USB BIT(21) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_SHIFT_XTAL_SEL_TOK_2_0 19 #define BIT_MASK_XTAL_SEL_TOK_2_0 0x7 #define BIT_XTAL_SEL_TOK_2_0(x) \ (((x) & BIT_MASK_XTAL_SEL_TOK_2_0) << BIT_SHIFT_XTAL_SEL_TOK_2_0) #define BITS_XTAL_SEL_TOK_2_0 \ (BIT_MASK_XTAL_SEL_TOK_2_0 << BIT_SHIFT_XTAL_SEL_TOK_2_0) #define BIT_CLEAR_XTAL_SEL_TOK_2_0(x) ((x) & (~BITS_XTAL_SEL_TOK_2_0)) #define BIT_GET_XTAL_SEL_TOK_2_0(x) \ (((x) >> BIT_SHIFT_XTAL_SEL_TOK_2_0) & BIT_MASK_XTAL_SEL_TOK_2_0) #define BIT_SET_XTAL_SEL_TOK_2_0(x, v) \ (BIT_CLEAR_XTAL_SEL_TOK_2_0(x) | BIT_XTAL_SEL_TOK_2_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_SHIFT_XTAL_DRV_AFE_V2 19 #define BIT_MASK_XTAL_DRV_AFE_V2 0x3 #define BIT_XTAL_DRV_AFE_V2(x) \ (((x) & BIT_MASK_XTAL_DRV_AFE_V2) << BIT_SHIFT_XTAL_DRV_AFE_V2) #define BITS_XTAL_DRV_AFE_V2 \ (BIT_MASK_XTAL_DRV_AFE_V2 << BIT_SHIFT_XTAL_DRV_AFE_V2) #define BIT_CLEAR_XTAL_DRV_AFE_V2(x) ((x) & (~BITS_XTAL_DRV_AFE_V2)) #define BIT_GET_XTAL_DRV_AFE_V2(x) \ (((x) >> BIT_SHIFT_XTAL_DRV_AFE_V2) & BIT_MASK_XTAL_DRV_AFE_V2) #define BIT_SET_XTAL_DRV_AFE_V2(x, v) \ (BIT_CLEAR_XTAL_DRV_AFE_V2(x) | BIT_XTAL_DRV_AFE_V2(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_XQSEL_RF_AWAKE_V2 BIT(18) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_EN_XTAL_DRV_AFE BIT(18) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_XQSEL_RF_INITIAL_V2 BIT(17) #define BIT_XTAL_DELAY_USB_V1 BIT(16) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_SHIFT_XTAL_DRV_RF2_V2 16 #define BIT_MASK_XTAL_DRV_RF2_V2 0x3 #define BIT_XTAL_DRV_RF2_V2(x) \ (((x) & BIT_MASK_XTAL_DRV_RF2_V2) << BIT_SHIFT_XTAL_DRV_RF2_V2) #define BITS_XTAL_DRV_RF2_V2 \ (BIT_MASK_XTAL_DRV_RF2_V2 << BIT_SHIFT_XTAL_DRV_RF2_V2) #define BIT_CLEAR_XTAL_DRV_RF2_V2(x) ((x) & (~BITS_XTAL_DRV_RF2_V2)) #define BIT_GET_XTAL_DRV_RF2_V2(x) \ (((x) >> BIT_SHIFT_XTAL_DRV_RF2_V2) & BIT_MASK_XTAL_DRV_RF2_V2) #define BIT_SET_XTAL_DRV_RF2_V2(x, v) \ (BIT_CLEAR_XTAL_DRV_RF2_V2(x) | BIT_XTAL_DRV_RF2_V2(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_XTAL_DELAY_DIGI_V1 BIT(15) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_EN_XTAL_DRV_RF2 BIT(15) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_XTAL_DELAY_AFE_V1 BIT(14) #define BIT_XTAL_DRV_RF_LATCH_V3 BIT(13) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_EN_XTAL_DRV_RF1 BIT(12) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_SHIFT_XTAL_DRV_DIGI_1_0 11 #define BIT_MASK_XTAL_DRV_DIGI_1_0 0x3 #define BIT_XTAL_DRV_DIGI_1_0(x) \ (((x) & BIT_MASK_XTAL_DRV_DIGI_1_0) << BIT_SHIFT_XTAL_DRV_DIGI_1_0) #define BITS_XTAL_DRV_DIGI_1_0 \ (BIT_MASK_XTAL_DRV_DIGI_1_0 << BIT_SHIFT_XTAL_DRV_DIGI_1_0) #define BIT_CLEAR_XTAL_DRV_DIGI_1_0(x) ((x) & (~BITS_XTAL_DRV_DIGI_1_0)) #define BIT_GET_XTAL_DRV_DIGI_1_0(x) \ (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_1_0) & BIT_MASK_XTAL_DRV_DIGI_1_0) #define BIT_SET_XTAL_DRV_DIGI_1_0(x, v) \ (BIT_CLEAR_XTAL_DRV_DIGI_1_0(x) | BIT_XTAL_DRV_DIGI_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_XTAL_DRV_RF_LATCH_V4 BIT(11) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_XTAL_GATED_DIGIN BIT(10) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_XTAL_GM_SEP_V3 BIT(10) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_XTAL_GATED_DIGIP BIT(9) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_XQSEL_RF_AWAKE_V3 BIT(9) #define BIT_XQSEL_RF_INITIAL_V3 BIT(8) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_SHIFT_XTAL_DRV_USB_1_0 7 #define BIT_MASK_XTAL_DRV_USB_1_0 0x3 #define BIT_XTAL_DRV_USB_1_0(x) \ (((x) & BIT_MASK_XTAL_DRV_USB_1_0) << BIT_SHIFT_XTAL_DRV_USB_1_0) #define BITS_XTAL_DRV_USB_1_0 \ (BIT_MASK_XTAL_DRV_USB_1_0 << BIT_SHIFT_XTAL_DRV_USB_1_0) #define BIT_CLEAR_XTAL_DRV_USB_1_0(x) ((x) & (~BITS_XTAL_DRV_USB_1_0)) #define BIT_GET_XTAL_DRV_USB_1_0(x) \ (((x) >> BIT_SHIFT_XTAL_DRV_USB_1_0) & BIT_MASK_XTAL_DRV_USB_1_0) #define BIT_SET_XTAL_DRV_USB_1_0(x, v) \ (BIT_CLEAR_XTAL_DRV_USB_1_0(x) | BIT_XTAL_DRV_USB_1_0(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_XQSEL_V2 BIT(7) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_XTAL_GATED_USBN BIT(6) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_GATED_XTAL_OK0_V2 BIT(6) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_XTAL_GATED_USBP BIT(5) #define BIT_SHIFT_XTAL_DRV_AFE_1_0 3 #define BIT_MASK_XTAL_DRV_AFE_1_0 0x3 #define BIT_XTAL_DRV_AFE_1_0(x) \ (((x) & BIT_MASK_XTAL_DRV_AFE_1_0) << BIT_SHIFT_XTAL_DRV_AFE_1_0) #define BITS_XTAL_DRV_AFE_1_0 \ (BIT_MASK_XTAL_DRV_AFE_1_0 << BIT_SHIFT_XTAL_DRV_AFE_1_0) #define BIT_CLEAR_XTAL_DRV_AFE_1_0(x) ((x) & (~BITS_XTAL_DRV_AFE_1_0)) #define BIT_GET_XTAL_DRV_AFE_1_0(x) \ (((x) >> BIT_SHIFT_XTAL_DRV_AFE_1_0) & BIT_MASK_XTAL_DRV_AFE_1_0) #define BIT_SET_XTAL_DRV_AFE_1_0(x, v) \ (BIT_CLEAR_XTAL_DRV_AFE_1_0(x) | BIT_XTAL_DRV_AFE_1_0(v)) #define BIT_XTAL_GATED_AFEN BIT(2) #define BIT_XTAL_GATED_AFEP BIT(1) #define BIT_XTAL_DRV_RF1_1 BIT(0) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ #define BIT_SHIFT_XTAL_SC_LPS_V2 0 #define BIT_MASK_XTAL_SC_LPS_V2 0x3f #define BIT_XTAL_SC_LPS_V2(x) \ (((x) & BIT_MASK_XTAL_SC_LPS_V2) << BIT_SHIFT_XTAL_SC_LPS_V2) #define BITS_XTAL_SC_LPS_V2 \ (BIT_MASK_XTAL_SC_LPS_V2 << BIT_SHIFT_XTAL_SC_LPS_V2) #define BIT_CLEAR_XTAL_SC_LPS_V2(x) ((x) & (~BITS_XTAL_SC_LPS_V2)) #define BIT_GET_XTAL_SC_LPS_V2(x) \ (((x) >> BIT_SHIFT_XTAL_SC_LPS_V2) & BIT_MASK_XTAL_SC_LPS_V2) #define BIT_SET_XTAL_SC_LPS_V2(x, v) \ (BIT_CLEAR_XTAL_SC_LPS_V2(x) | BIT_XTAL_SC_LPS_V2(v)) /* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ #define BIT_XTAL_AAC_CAP BIT(31) #define BIT_SHIFT_XTAL_PDSW 29 #define BIT_MASK_XTAL_PDSW 0x3 #define BIT_XTAL_PDSW(x) (((x) & BIT_MASK_XTAL_PDSW) << BIT_SHIFT_XTAL_PDSW) #define BITS_XTAL_PDSW (BIT_MASK_XTAL_PDSW << BIT_SHIFT_XTAL_PDSW) #define BIT_CLEAR_XTAL_PDSW(x) ((x) & (~BITS_XTAL_PDSW)) #define BIT_GET_XTAL_PDSW(x) (((x) >> BIT_SHIFT_XTAL_PDSW) & BIT_MASK_XTAL_PDSW) #define BIT_SET_XTAL_PDSW(x, v) (BIT_CLEAR_XTAL_PDSW(x) | BIT_XTAL_PDSW(v)) #define BIT_SHIFT_XTAL_LPS_BUF_VB 27 #define BIT_MASK_XTAL_LPS_BUF_VB 0x3 #define BIT_XTAL_LPS_BUF_VB(x) \ (((x) & BIT_MASK_XTAL_LPS_BUF_VB) << BIT_SHIFT_XTAL_LPS_BUF_VB) #define BITS_XTAL_LPS_BUF_VB \ (BIT_MASK_XTAL_LPS_BUF_VB << BIT_SHIFT_XTAL_LPS_BUF_VB) #define BIT_CLEAR_XTAL_LPS_BUF_VB(x) ((x) & (~BITS_XTAL_LPS_BUF_VB)) #define BIT_GET_XTAL_LPS_BUF_VB(x) \ (((x) >> BIT_SHIFT_XTAL_LPS_BUF_VB) & BIT_MASK_XTAL_LPS_BUF_VB) #define BIT_SET_XTAL_LPS_BUF_VB(x, v) \ (BIT_CLEAR_XTAL_LPS_BUF_VB(x) | BIT_XTAL_LPS_BUF_VB(v)) #define BIT_XTAL_PDCK_MANU BIT(26) #define BIT_XTAL_PDCK_OK_MANU BIT(25) #define BIT_SHIFT_XTAL_VREF_SEL 20 #define BIT_MASK_XTAL_VREF_SEL 0x1f #define BIT_XTAL_VREF_SEL(x) \ (((x) & BIT_MASK_XTAL_VREF_SEL) << BIT_SHIFT_XTAL_VREF_SEL) #define BITS_XTAL_VREF_SEL (BIT_MASK_XTAL_VREF_SEL << BIT_SHIFT_XTAL_VREF_SEL) #define BIT_CLEAR_XTAL_VREF_SEL(x) ((x) & (~BITS_XTAL_VREF_SEL)) #define BIT_GET_XTAL_VREF_SEL(x) \ (((x) >> BIT_SHIFT_XTAL_VREF_SEL) & BIT_MASK_XTAL_VREF_SEL) #define BIT_SET_XTAL_VREF_SEL(x, v) \ (BIT_CLEAR_XTAL_VREF_SEL(x) | BIT_XTAL_VREF_SEL(v)) #define BIT_EN_XTAL_PDCK_VREF BIT(19) #define BIT_XTAL_SEL_PWR_V1 BIT(18) #define BIT_XTAL_LPS_DIVISOR BIT(17) #define BIT_XTAL_CKDIGI_SEL BIT(16) #define BIT_EN_XTAL_LPS_CLK BIT(15) #define BIT_EN_XTAL_SCHMITT BIT(14) #define BIT_XTAL_PK_SEL_OFFSET BIT(13) #define BIT_SHIFT_XTAL_MANU_PK_SEL 11 #define BIT_MASK_XTAL_MANU_PK_SEL 0x3 #define BIT_XTAL_MANU_PK_SEL(x) \ (((x) & BIT_MASK_XTAL_MANU_PK_SEL) << BIT_SHIFT_XTAL_MANU_PK_SEL) #define BITS_XTAL_MANU_PK_SEL \ (BIT_MASK_XTAL_MANU_PK_SEL << BIT_SHIFT_XTAL_MANU_PK_SEL) #define BIT_CLEAR_XTAL_MANU_PK_SEL(x) ((x) & (~BITS_XTAL_MANU_PK_SEL)) #define BIT_GET_XTAL_MANU_PK_SEL(x) \ (((x) >> BIT_SHIFT_XTAL_MANU_PK_SEL) & BIT_MASK_XTAL_MANU_PK_SEL) #define BIT_SET_XTAL_MANU_PK_SEL(x, v) \ (BIT_CLEAR_XTAL_MANU_PK_SEL(x) | BIT_XTAL_MANU_PK_SEL(v)) #define BIT_XTAL_AACK_PK_MANU BIT(10) #define BIT_EN_XTAL_AAC_PKDET_V1 BIT(9) #define BIT_EN_XTAL_AAC_GM_V1 BIT(8) #define BIT_XTAL_LDO_OPVB_SEL BIT(7) #define BIT_SHIFT_XTAL_DUMMY_V1 7 #define BIT_MASK_XTAL_DUMMY_V1 0x3f #define BIT_XTAL_DUMMY_V1(x) \ (((x) & BIT_MASK_XTAL_DUMMY_V1) << BIT_SHIFT_XTAL_DUMMY_V1) #define BITS_XTAL_DUMMY_V1 (BIT_MASK_XTAL_DUMMY_V1 << BIT_SHIFT_XTAL_DUMMY_V1) #define BIT_CLEAR_XTAL_DUMMY_V1(x) ((x) & (~BITS_XTAL_DUMMY_V1)) #define BIT_GET_XTAL_DUMMY_V1(x) \ (((x) >> BIT_SHIFT_XTAL_DUMMY_V1) & BIT_MASK_XTAL_DUMMY_V1) #define BIT_SET_XTAL_DUMMY_V1(x, v) \ (BIT_CLEAR_XTAL_DUMMY_V1(x) | BIT_XTAL_DUMMY_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ #define BIT_XTAL_DRV_RF2_LATCH BIT(6) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ #define BIT_XTAL_LDO_NC BIT(6) #define BIT_XTAL_EN_LNBUF BIT(6) #define BIT_XTAL__AAC_TIE_MID BIT(5) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ #define BIT_SHIFT_XTAL_DRV_RF2_1_0 4 #define BIT_MASK_XTAL_DRV_RF2_1_0 0x3 #define BIT_XTAL_DRV_RF2_1_0(x) \ (((x) & BIT_MASK_XTAL_DRV_RF2_1_0) << BIT_SHIFT_XTAL_DRV_RF2_1_0) #define BITS_XTAL_DRV_RF2_1_0 \ (BIT_MASK_XTAL_DRV_RF2_1_0 << BIT_SHIFT_XTAL_DRV_RF2_1_0) #define BIT_CLEAR_XTAL_DRV_RF2_1_0(x) ((x) & (~BITS_XTAL_DRV_RF2_1_0)) #define BIT_GET_XTAL_DRV_RF2_1_0(x) \ (((x) >> BIT_SHIFT_XTAL_DRV_RF2_1_0) & BIT_MASK_XTAL_DRV_RF2_1_0) #define BIT_SET_XTAL_DRV_RF2_1_0(x, v) \ (BIT_CLEAR_XTAL_DRV_RF2_1_0(x) | BIT_XTAL_DRV_RF2_1_0(v)) #define BIT_XTAL_GATED_RF2N BIT(3) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ #define BIT_SHIFT_XTAL_LDO_VREF_V2 3 #define BIT_MASK_XTAL_LDO_VREF_V2 0x7 #define BIT_XTAL_LDO_VREF_V2(x) \ (((x) & BIT_MASK_XTAL_LDO_VREF_V2) << BIT_SHIFT_XTAL_LDO_VREF_V2) #define BITS_XTAL_LDO_VREF_V2 \ (BIT_MASK_XTAL_LDO_VREF_V2 << BIT_SHIFT_XTAL_LDO_VREF_V2) #define BIT_CLEAR_XTAL_LDO_VREF_V2(x) ((x) & (~BITS_XTAL_LDO_VREF_V2)) #define BIT_GET_XTAL_LDO_VREF_V2(x) \ (((x) >> BIT_SHIFT_XTAL_LDO_VREF_V2) & BIT_MASK_XTAL_LDO_VREF_V2) #define BIT_SET_XTAL_LDO_VREF_V2(x, v) \ (BIT_CLEAR_XTAL_LDO_VREF_V2(x) | BIT_XTAL_LDO_VREF_V2(v)) #define BIT_SHIFT_XTAL_AAC_OPCUR 3 #define BIT_MASK_XTAL_AAC_OPCUR 0x3 #define BIT_XTAL_AAC_OPCUR(x) \ (((x) & BIT_MASK_XTAL_AAC_OPCUR) << BIT_SHIFT_XTAL_AAC_OPCUR) #define BITS_XTAL_AAC_OPCUR \ (BIT_MASK_XTAL_AAC_OPCUR << BIT_SHIFT_XTAL_AAC_OPCUR) #define BIT_CLEAR_XTAL_AAC_OPCUR(x) ((x) & (~BITS_XTAL_AAC_OPCUR)) #define BIT_GET_XTAL_AAC_OPCUR(x) \ (((x) >> BIT_SHIFT_XTAL_AAC_OPCUR) & BIT_MASK_XTAL_AAC_OPCUR) #define BIT_SET_XTAL_AAC_OPCUR(x, v) \ (BIT_CLEAR_XTAL_AAC_OPCUR(x) | BIT_XTAL_AAC_OPCUR(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ #define BIT_XTAL_GATED_RF2P BIT(2) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ #define BIT_XTAL_LPMODE_V1 BIT(2) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ #define BIT_XTAL_LDO_DI BIT(1) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ #define BIT_SHIFT_XTAL_AAC_IOFFSET 1 #define BIT_MASK_XTAL_AAC_IOFFSET 0x3 #define BIT_XTAL_AAC_IOFFSET(x) \ (((x) & BIT_MASK_XTAL_AAC_IOFFSET) << BIT_SHIFT_XTAL_AAC_IOFFSET) #define BITS_XTAL_AAC_IOFFSET \ (BIT_MASK_XTAL_AAC_IOFFSET << BIT_SHIFT_XTAL_AAC_IOFFSET) #define BIT_CLEAR_XTAL_AAC_IOFFSET(x) ((x) & (~BITS_XTAL_AAC_IOFFSET)) #define BIT_GET_XTAL_AAC_IOFFSET(x) \ (((x) >> BIT_SHIFT_XTAL_AAC_IOFFSET) & BIT_MASK_XTAL_AAC_IOFFSET) #define BIT_SET_XTAL_AAC_IOFFSET(x, v) \ (BIT_CLEAR_XTAL_AAC_IOFFSET(x) | BIT_XTAL_AAC_IOFFSET(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ #define BIT_XTAL_SEL_PWR BIT(0) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ #define BIT_SHIFT_XTAL_SEL_TOK_V3 0 #define BIT_MASK_XTAL_SEL_TOK_V3 0x3 #define BIT_XTAL_SEL_TOK_V3(x) \ (((x) & BIT_MASK_XTAL_SEL_TOK_V3) << BIT_SHIFT_XTAL_SEL_TOK_V3) #define BITS_XTAL_SEL_TOK_V3 \ (BIT_MASK_XTAL_SEL_TOK_V3 << BIT_SHIFT_XTAL_SEL_TOK_V3) #define BIT_CLEAR_XTAL_SEL_TOK_V3(x) ((x) & (~BITS_XTAL_SEL_TOK_V3)) #define BIT_GET_XTAL_SEL_TOK_V3(x) \ (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V3) & BIT_MASK_XTAL_SEL_TOK_V3) #define BIT_SET_XTAL_SEL_TOK_V3(x, v) \ (BIT_CLEAR_XTAL_SEL_TOK_V3(x) | BIT_XTAL_SEL_TOK_V3(v)) #define BIT_XTAL_AAC_CAP_V1 BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ANAPAR_XTAL_AAC (Offset 0x104C) */ #define BIT_SHIFT_GM_MANUAL_4_0 21 #define BIT_MASK_GM_MANUAL_4_0 0x1f #define BIT_GM_MANUAL_4_0(x) \ (((x) & BIT_MASK_GM_MANUAL_4_0) << BIT_SHIFT_GM_MANUAL_4_0) #define BITS_GM_MANUAL_4_0 (BIT_MASK_GM_MANUAL_4_0 << BIT_SHIFT_GM_MANUAL_4_0) #define BIT_CLEAR_GM_MANUAL_4_0(x) ((x) & (~BITS_GM_MANUAL_4_0)) #define BIT_GET_GM_MANUAL_4_0(x) \ (((x) >> BIT_SHIFT_GM_MANUAL_4_0) & BIT_MASK_GM_MANUAL_4_0) #define BIT_SET_GM_MANUAL_4_0(x, v) \ (BIT_CLEAR_GM_MANUAL_4_0(x) | BIT_GM_MANUAL_4_0(v)) #define BIT_SHIFT_GM_STUP_4_0 16 #define BIT_MASK_GM_STUP_4_0 0x1f #define BIT_GM_STUP_4_0(x) \ (((x) & BIT_MASK_GM_STUP_4_0) << BIT_SHIFT_GM_STUP_4_0) #define BITS_GM_STUP_4_0 (BIT_MASK_GM_STUP_4_0 << BIT_SHIFT_GM_STUP_4_0) #define BIT_CLEAR_GM_STUP_4_0(x) ((x) & (~BITS_GM_STUP_4_0)) #define BIT_GET_GM_STUP_4_0(x) \ (((x) >> BIT_SHIFT_GM_STUP_4_0) & BIT_MASK_GM_STUP_4_0) #define BIT_SET_GM_STUP_4_0(x, v) \ (BIT_CLEAR_GM_STUP_4_0(x) | BIT_GM_STUP_4_0(v)) #define BIT_SHIFT_XTAL_CK_SET_2_0 13 #define BIT_MASK_XTAL_CK_SET_2_0 0x7 #define BIT_XTAL_CK_SET_2_0(x) \ (((x) & BIT_MASK_XTAL_CK_SET_2_0) << BIT_SHIFT_XTAL_CK_SET_2_0) #define BITS_XTAL_CK_SET_2_0 \ (BIT_MASK_XTAL_CK_SET_2_0 << BIT_SHIFT_XTAL_CK_SET_2_0) #define BIT_CLEAR_XTAL_CK_SET_2_0(x) ((x) & (~BITS_XTAL_CK_SET_2_0)) #define BIT_GET_XTAL_CK_SET_2_0(x) \ (((x) >> BIT_SHIFT_XTAL_CK_SET_2_0) & BIT_MASK_XTAL_CK_SET_2_0) #define BIT_SET_XTAL_CK_SET_2_0(x, v) \ (BIT_CLEAR_XTAL_CK_SET_2_0(x) | BIT_XTAL_CK_SET_2_0(v)) #define BIT_SHIFT_GM_INIT_4_0 8 #define BIT_MASK_GM_INIT_4_0 0x1f #define BIT_GM_INIT_4_0(x) \ (((x) & BIT_MASK_GM_INIT_4_0) << BIT_SHIFT_GM_INIT_4_0) #define BITS_GM_INIT_4_0 (BIT_MASK_GM_INIT_4_0 << BIT_SHIFT_GM_INIT_4_0) #define BIT_CLEAR_GM_INIT_4_0(x) ((x) & (~BITS_GM_INIT_4_0)) #define BIT_GET_GM_INIT_4_0(x) \ (((x) >> BIT_SHIFT_GM_INIT_4_0) & BIT_MASK_GM_INIT_4_0) #define BIT_SET_GM_INIT_4_0(x, v) \ (BIT_CLEAR_GM_INIT_4_0(x) | BIT_GM_INIT_4_0(v)) #define BIT_SHIFT_XAAC_GM_OFFSET_4_0 2 #define BIT_MASK_XAAC_GM_OFFSET_4_0 0x1f #define BIT_XAAC_GM_OFFSET_4_0(x) \ (((x) & BIT_MASK_XAAC_GM_OFFSET_4_0) << BIT_SHIFT_XAAC_GM_OFFSET_4_0) #define BITS_XAAC_GM_OFFSET_4_0 \ (BIT_MASK_XAAC_GM_OFFSET_4_0 << BIT_SHIFT_XAAC_GM_OFFSET_4_0) #define BIT_CLEAR_XAAC_GM_OFFSET_4_0(x) ((x) & (~BITS_XAAC_GM_OFFSET_4_0)) #define BIT_GET_XAAC_GM_OFFSET_4_0(x) \ (((x) >> BIT_SHIFT_XAAC_GM_OFFSET_4_0) & BIT_MASK_XAAC_GM_OFFSET_4_0) #define BIT_SET_XAAC_GM_OFFSET_4_0(x, v) \ (BIT_CLEAR_XAAC_GM_OFFSET_4_0(x) | BIT_XAAC_GM_OFFSET_4_0(v)) /* 2 REG_ANAPAR_XTAL_R_ONLY (Offset 0x1050) */ #define BIT_XTAL_PKDET_OUT BIT(6) #define BIT_SHIFT_XTAL_GM_AAC_4_0 1 #define BIT_MASK_XTAL_GM_AAC_4_0 0x1f #define BIT_XTAL_GM_AAC_4_0(x) \ (((x) & BIT_MASK_XTAL_GM_AAC_4_0) << BIT_SHIFT_XTAL_GM_AAC_4_0) #define BITS_XTAL_GM_AAC_4_0 \ (BIT_MASK_XTAL_GM_AAC_4_0 << BIT_SHIFT_XTAL_GM_AAC_4_0) #define BIT_CLEAR_XTAL_GM_AAC_4_0(x) ((x) & (~BITS_XTAL_GM_AAC_4_0)) #define BIT_GET_XTAL_GM_AAC_4_0(x) \ (((x) >> BIT_SHIFT_XTAL_GM_AAC_4_0) & BIT_MASK_XTAL_GM_AAC_4_0) #define BIT_SET_XTAL_GM_AAC_4_0(x, v) \ (BIT_CLEAR_XTAL_GM_AAC_4_0(x) | BIT_XTAL_GM_AAC_4_0(v)) #define BIT_XAAC_READY BIT(0) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ #define BIT_XAAC_LPOW BIT(31) #define BIT_SHIFT_AAC_MODE 29 #define BIT_MASK_AAC_MODE 0x3 #define BIT_AAC_MODE(x) (((x) & BIT_MASK_AAC_MODE) << BIT_SHIFT_AAC_MODE) #define BITS_AAC_MODE (BIT_MASK_AAC_MODE << BIT_SHIFT_AAC_MODE) #define BIT_CLEAR_AAC_MODE(x) ((x) & (~BITS_AAC_MODE)) #define BIT_GET_AAC_MODE(x) (((x) >> BIT_SHIFT_AAC_MODE) & BIT_MASK_AAC_MODE) #define BIT_SET_AAC_MODE(x, v) (BIT_CLEAR_AAC_MODE(x) | BIT_AAC_MODE(v)) #define BIT_SHIFT_GM_MANUAL 21 #define BIT_MASK_GM_MANUAL 0x1f #define BIT_GM_MANUAL(x) (((x) & BIT_MASK_GM_MANUAL) << BIT_SHIFT_GM_MANUAL) #define BITS_GM_MANUAL (BIT_MASK_GM_MANUAL << BIT_SHIFT_GM_MANUAL) #define BIT_CLEAR_GM_MANUAL(x) ((x) & (~BITS_GM_MANUAL)) #define BIT_GET_GM_MANUAL(x) (((x) >> BIT_SHIFT_GM_MANUAL) & BIT_MASK_GM_MANUAL) #define BIT_SET_GM_MANUAL(x, v) (BIT_CLEAR_GM_MANUAL(x) | BIT_GM_MANUAL(v)) #define BIT_SHIFT_XTAL_LDO_LPS 21 #define BIT_MASK_XTAL_LDO_LPS 0x7 #define BIT_XTAL_LDO_LPS(x) \ (((x) & BIT_MASK_XTAL_LDO_LPS) << BIT_SHIFT_XTAL_LDO_LPS) #define BITS_XTAL_LDO_LPS (BIT_MASK_XTAL_LDO_LPS << BIT_SHIFT_XTAL_LDO_LPS) #define BIT_CLEAR_XTAL_LDO_LPS(x) ((x) & (~BITS_XTAL_LDO_LPS)) #define BIT_GET_XTAL_LDO_LPS(x) \ (((x) >> BIT_SHIFT_XTAL_LDO_LPS) & BIT_MASK_XTAL_LDO_LPS) #define BIT_SET_XTAL_LDO_LPS(x, v) \ (BIT_CLEAR_XTAL_LDO_LPS(x) | BIT_XTAL_LDO_LPS(v)) #define BIT_SHIFT_GM_STUP 16 #define BIT_MASK_GM_STUP 0x1f #define BIT_GM_STUP(x) (((x) & BIT_MASK_GM_STUP) << BIT_SHIFT_GM_STUP) #define BITS_GM_STUP (BIT_MASK_GM_STUP << BIT_SHIFT_GM_STUP) #define BIT_CLEAR_GM_STUP(x) ((x) & (~BITS_GM_STUP)) #define BIT_GET_GM_STUP(x) (((x) >> BIT_SHIFT_GM_STUP) & BIT_MASK_GM_STUP) #define BIT_SET_GM_STUP(x, v) (BIT_CLEAR_GM_STUP(x) | BIT_GM_STUP(v)) #define BIT_SHIFT_XTAL_WAIT_CYC 15 #define BIT_MASK_XTAL_WAIT_CYC 0x3f #define BIT_XTAL_WAIT_CYC(x) \ (((x) & BIT_MASK_XTAL_WAIT_CYC) << BIT_SHIFT_XTAL_WAIT_CYC) #define BITS_XTAL_WAIT_CYC (BIT_MASK_XTAL_WAIT_CYC << BIT_SHIFT_XTAL_WAIT_CYC) #define BIT_CLEAR_XTAL_WAIT_CYC(x) ((x) & (~BITS_XTAL_WAIT_CYC)) #define BIT_GET_XTAL_WAIT_CYC(x) \ (((x) >> BIT_SHIFT_XTAL_WAIT_CYC) & BIT_MASK_XTAL_WAIT_CYC) #define BIT_SET_XTAL_WAIT_CYC(x, v) \ (BIT_CLEAR_XTAL_WAIT_CYC(x) | BIT_XTAL_WAIT_CYC(v)) #define BIT_SHIFT_XTAL_CK_SET 13 #define BIT_MASK_XTAL_CK_SET 0x7 #define BIT_XTAL_CK_SET(x) \ (((x) & BIT_MASK_XTAL_CK_SET) << BIT_SHIFT_XTAL_CK_SET) #define BITS_XTAL_CK_SET (BIT_MASK_XTAL_CK_SET << BIT_SHIFT_XTAL_CK_SET) #define BIT_CLEAR_XTAL_CK_SET(x) ((x) & (~BITS_XTAL_CK_SET)) #define BIT_GET_XTAL_CK_SET(x) \ (((x) >> BIT_SHIFT_XTAL_CK_SET) & BIT_MASK_XTAL_CK_SET) #define BIT_SET_XTAL_CK_SET(x, v) \ (BIT_CLEAR_XTAL_CK_SET(x) | BIT_XTAL_CK_SET(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CPHY_LDO (Offset 0x1054) */ #define BIT_SHIFT_CPHY_LDO_PD 12 #define BIT_MASK_CPHY_LDO_PD 0x3 #define BIT_CPHY_LDO_PD(x) \ (((x) & BIT_MASK_CPHY_LDO_PD) << BIT_SHIFT_CPHY_LDO_PD) #define BITS_CPHY_LDO_PD (BIT_MASK_CPHY_LDO_PD << BIT_SHIFT_CPHY_LDO_PD) #define BIT_CLEAR_CPHY_LDO_PD(x) ((x) & (~BITS_CPHY_LDO_PD)) #define BIT_GET_CPHY_LDO_PD(x) \ (((x) >> BIT_SHIFT_CPHY_LDO_PD) & BIT_MASK_CPHY_LDO_PD) #define BIT_SET_CPHY_LDO_PD(x, v) \ (BIT_CLEAR_CPHY_LDO_PD(x) | BIT_CPHY_LDO_PD(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ #define BIT_SHIFT_XTAL_LDO_OK 12 #define BIT_MASK_XTAL_LDO_OK 0x7 #define BIT_XTAL_LDO_OK(x) \ (((x) & BIT_MASK_XTAL_LDO_OK) << BIT_SHIFT_XTAL_LDO_OK) #define BITS_XTAL_LDO_OK (BIT_MASK_XTAL_LDO_OK << BIT_SHIFT_XTAL_LDO_OK) #define BIT_CLEAR_XTAL_LDO_OK(x) ((x) & (~BITS_XTAL_LDO_OK)) #define BIT_GET_XTAL_LDO_OK(x) \ (((x) >> BIT_SHIFT_XTAL_LDO_OK) & BIT_MASK_XTAL_LDO_OK) #define BIT_SET_XTAL_LDO_OK(x, v) \ (BIT_CLEAR_XTAL_LDO_OK(x) | BIT_XTAL_LDO_OK(v)) #define BIT_XTAL_MD_LPOW BIT(11) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CPHY_LDO (Offset 0x1054) */ #define BIT_SHIFT_CPHY_LDO_SR 10 #define BIT_MASK_CPHY_LDO_SR 0x3 #define BIT_CPHY_LDO_SR(x) \ (((x) & BIT_MASK_CPHY_LDO_SR) << BIT_SHIFT_CPHY_LDO_SR) #define BITS_CPHY_LDO_SR (BIT_MASK_CPHY_LDO_SR << BIT_SHIFT_CPHY_LDO_SR) #define BIT_CLEAR_CPHY_LDO_SR(x) ((x) & (~BITS_CPHY_LDO_SR)) #define BIT_GET_CPHY_LDO_SR(x) \ (((x) >> BIT_SHIFT_CPHY_LDO_SR) & BIT_MASK_CPHY_LDO_SR) #define BIT_SET_CPHY_LDO_SR(x, v) \ (BIT_CLEAR_CPHY_LDO_SR(x) | BIT_CPHY_LDO_SR(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ #define BIT_SHIFT_XTAL_OV_RATIO 9 #define BIT_MASK_XTAL_OV_RATIO 0x3 #define BIT_XTAL_OV_RATIO(x) \ (((x) & BIT_MASK_XTAL_OV_RATIO) << BIT_SHIFT_XTAL_OV_RATIO) #define BITS_XTAL_OV_RATIO (BIT_MASK_XTAL_OV_RATIO << BIT_SHIFT_XTAL_OV_RATIO) #define BIT_CLEAR_XTAL_OV_RATIO(x) ((x) & (~BITS_XTAL_OV_RATIO)) #define BIT_GET_XTAL_OV_RATIO(x) \ (((x) >> BIT_SHIFT_XTAL_OV_RATIO) & BIT_MASK_XTAL_OV_RATIO) #define BIT_SET_XTAL_OV_RATIO(x, v) \ (BIT_CLEAR_XTAL_OV_RATIO(x) | BIT_XTAL_OV_RATIO(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CPHY_LDO (Offset 0x1054) */ #define BIT_SHIFT_CPHY_LDO_TUNEREF 8 #define BIT_MASK_CPHY_LDO_TUNEREF 0x3 #define BIT_CPHY_LDO_TUNEREF(x) \ (((x) & BIT_MASK_CPHY_LDO_TUNEREF) << BIT_SHIFT_CPHY_LDO_TUNEREF) #define BITS_CPHY_LDO_TUNEREF \ (BIT_MASK_CPHY_LDO_TUNEREF << BIT_SHIFT_CPHY_LDO_TUNEREF) #define BIT_CLEAR_CPHY_LDO_TUNEREF(x) ((x) & (~BITS_CPHY_LDO_TUNEREF)) #define BIT_GET_CPHY_LDO_TUNEREF(x) \ (((x) >> BIT_SHIFT_CPHY_LDO_TUNEREF) & BIT_MASK_CPHY_LDO_TUNEREF) #define BIT_SET_CPHY_LDO_TUNEREF(x, v) \ (BIT_CLEAR_CPHY_LDO_TUNEREF(x) | BIT_CPHY_LDO_TUNEREF(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ #define BIT_SHIFT_GM_INIT 8 #define BIT_MASK_GM_INIT 0x1f #define BIT_GM_INIT(x) (((x) & BIT_MASK_GM_INIT) << BIT_SHIFT_GM_INIT) #define BITS_GM_INIT (BIT_MASK_GM_INIT << BIT_SHIFT_GM_INIT) #define BIT_CLEAR_GM_INIT(x) ((x) & (~BITS_GM_INIT)) #define BIT_GET_GM_INIT(x) (((x) >> BIT_SHIFT_GM_INIT) & BIT_MASK_GM_INIT) #define BIT_SET_GM_INIT(x, v) (BIT_CLEAR_GM_INIT(x) | BIT_GM_INIT(v)) #define BIT_SHIFT_XTAL_OV_UNIT 6 #define BIT_MASK_XTAL_OV_UNIT 0x7 #define BIT_XTAL_OV_UNIT(x) \ (((x) & BIT_MASK_XTAL_OV_UNIT) << BIT_SHIFT_XTAL_OV_UNIT) #define BITS_XTAL_OV_UNIT (BIT_MASK_XTAL_OV_UNIT << BIT_SHIFT_XTAL_OV_UNIT) #define BIT_CLEAR_XTAL_OV_UNIT(x) ((x) & (~BITS_XTAL_OV_UNIT)) #define BIT_GET_XTAL_OV_UNIT(x) \ (((x) >> BIT_SHIFT_XTAL_OV_UNIT) & BIT_MASK_XTAL_OV_UNIT) #define BIT_SET_XTAL_OV_UNIT(x, v) \ (BIT_CLEAR_XTAL_OV_UNIT(x) | BIT_XTAL_OV_UNIT(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CPHY_LDO (Offset 0x1054) */ #define BIT_SHIFT_CPHY_LDO_TUNE_VO 5 #define BIT_MASK_CPHY_LDO_TUNE_VO 0x7 #define BIT_CPHY_LDO_TUNE_VO(x) \ (((x) & BIT_MASK_CPHY_LDO_TUNE_VO) << BIT_SHIFT_CPHY_LDO_TUNE_VO) #define BITS_CPHY_LDO_TUNE_VO \ (BIT_MASK_CPHY_LDO_TUNE_VO << BIT_SHIFT_CPHY_LDO_TUNE_VO) #define BIT_CLEAR_CPHY_LDO_TUNE_VO(x) ((x) & (~BITS_CPHY_LDO_TUNE_VO)) #define BIT_GET_CPHY_LDO_TUNE_VO(x) \ (((x) >> BIT_SHIFT_CPHY_LDO_TUNE_VO) & BIT_MASK_CPHY_LDO_TUNE_VO) #define BIT_SET_CPHY_LDO_TUNE_VO(x, v) \ (BIT_CLEAR_CPHY_LDO_TUNE_VO(x) | BIT_CPHY_LDO_TUNE_VO(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ #define BIT_SHIFT_XTAL_MODE_MANUAL 4 #define BIT_MASK_XTAL_MODE_MANUAL 0x3 #define BIT_XTAL_MODE_MANUAL(x) \ (((x) & BIT_MASK_XTAL_MODE_MANUAL) << BIT_SHIFT_XTAL_MODE_MANUAL) #define BITS_XTAL_MODE_MANUAL \ (BIT_MASK_XTAL_MODE_MANUAL << BIT_SHIFT_XTAL_MODE_MANUAL) #define BIT_CLEAR_XTAL_MODE_MANUAL(x) ((x) & (~BITS_XTAL_MODE_MANUAL)) #define BIT_GET_XTAL_MODE_MANUAL(x) \ (((x) >> BIT_SHIFT_XTAL_MODE_MANUAL) & BIT_MASK_XTAL_MODE_MANUAL) #define BIT_SET_XTAL_MODE_MANUAL(x, v) \ (BIT_CLEAR_XTAL_MODE_MANUAL(x) | BIT_XTAL_MODE_MANUAL(v)) #define BIT_SHIFT_PK_END_AR 3 #define BIT_MASK_PK_END_AR 0x3 #define BIT_PK_END_AR(x) (((x) & BIT_MASK_PK_END_AR) << BIT_SHIFT_PK_END_AR) #define BITS_PK_END_AR (BIT_MASK_PK_END_AR << BIT_SHIFT_PK_END_AR) #define BIT_CLEAR_PK_END_AR(x) ((x) & (~BITS_PK_END_AR)) #define BIT_GET_PK_END_AR(x) (((x) >> BIT_SHIFT_PK_END_AR) & BIT_MASK_PK_END_AR) #define BIT_SET_PK_END_AR(x, v) (BIT_CLEAR_PK_END_AR(x) | BIT_PK_END_AR(v)) #define BIT_XTAL_MANU_SEL BIT(3) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CPHY_LDO (Offset 0x1054) */ #define BIT_SHIFT_CPHY_LDO_OCP_VTH 2 #define BIT_MASK_CPHY_LDO_OCP_VTH 0x7 #define BIT_CPHY_LDO_OCP_VTH(x) \ (((x) & BIT_MASK_CPHY_LDO_OCP_VTH) << BIT_SHIFT_CPHY_LDO_OCP_VTH) #define BITS_CPHY_LDO_OCP_VTH \ (BIT_MASK_CPHY_LDO_OCP_VTH << BIT_SHIFT_CPHY_LDO_OCP_VTH) #define BIT_CLEAR_CPHY_LDO_OCP_VTH(x) ((x) & (~BITS_CPHY_LDO_OCP_VTH)) #define BIT_GET_CPHY_LDO_OCP_VTH(x) \ (((x) >> BIT_SHIFT_CPHY_LDO_OCP_VTH) & BIT_MASK_CPHY_LDO_OCP_VTH) #define BIT_SET_CPHY_LDO_OCP_VTH(x, v) \ (BIT_CLEAR_CPHY_LDO_OCP_VTH(x) | BIT_CPHY_LDO_OCP_VTH(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ #define BIT_SHIFT_XAAC_GM_OFFSET 2 #define BIT_MASK_XAAC_GM_OFFSET 0x1f #define BIT_XAAC_GM_OFFSET(x) \ (((x) & BIT_MASK_XAAC_GM_OFFSET) << BIT_SHIFT_XAAC_GM_OFFSET) #define BITS_XAAC_GM_OFFSET \ (BIT_MASK_XAAC_GM_OFFSET << BIT_SHIFT_XAAC_GM_OFFSET) #define BIT_CLEAR_XAAC_GM_OFFSET(x) ((x) & (~BITS_XAAC_GM_OFFSET)) #define BIT_GET_XAAC_GM_OFFSET(x) \ (((x) >> BIT_SHIFT_XAAC_GM_OFFSET) & BIT_MASK_XAAC_GM_OFFSET) #define BIT_SET_XAAC_GM_OFFSET(x, v) \ (BIT_CLEAR_XAAC_GM_OFFSET(x) | BIT_XAAC_GM_OFFSET(v)) #define BIT_SHIFT_PK_START_AR 1 #define BIT_MASK_PK_START_AR 0x3 #define BIT_PK_START_AR(x) \ (((x) & BIT_MASK_PK_START_AR) << BIT_SHIFT_PK_START_AR) #define BITS_PK_START_AR (BIT_MASK_PK_START_AR << BIT_SHIFT_PK_START_AR) #define BIT_CLEAR_PK_START_AR(x) ((x) & (~BITS_PK_START_AR)) #define BIT_GET_PK_START_AR(x) \ (((x) >> BIT_SHIFT_PK_START_AR) & BIT_MASK_PK_START_AR) #define BIT_SET_PK_START_AR(x, v) \ (BIT_CLEAR_PK_START_AR(x) | BIT_PK_START_AR(v)) #define BIT_XTAL_MODE BIT(1) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CPHY_LDO (Offset 0x1054) */ #define BIT_SHIFT_VREF_LDO_OK 0 #define BIT_MASK_VREF_LDO_OK 0x3 #define BIT_VREF_LDO_OK(x) \ (((x) & BIT_MASK_VREF_LDO_OK) << BIT_SHIFT_VREF_LDO_OK) #define BITS_VREF_LDO_OK (BIT_MASK_VREF_LDO_OK << BIT_SHIFT_VREF_LDO_OK) #define BIT_CLEAR_VREF_LDO_OK(x) ((x) & (~BITS_VREF_LDO_OK)) #define BIT_GET_VREF_LDO_OK(x) \ (((x) >> BIT_SHIFT_VREF_LDO_OK) & BIT_MASK_VREF_LDO_OK) #define BIT_SET_VREF_LDO_OK(x, v) \ (BIT_CLEAR_VREF_LDO_OK(x) | BIT_VREF_LDO_OK(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ #define BIT_XAAC_LUT_MANUAL_EN BIT(0) #define BIT_RESET_N_DECODER BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CPHY_BG (Offset 0x1058) */ #define BIT_TXBCN_OK_PORT4 BIT(31) #define BIT_ATIMEND_PORT4 BIT(31) #define BIT_TXBCN_OK_PORT3 BIT(30) #define BIT_ATIMEND_PORT3 BIT(30) #define BIT_TXBCN_OK_PORT2 BIT(29) #define BIT_ATIMEND_PORT2 BIT(29) #define BIT_TXBCN_OK_PORT1 BIT(28) #define BIT_ATIMEND_PORT1 BIT(28) #define BIT_TXBCN15OK BIT(23) #define BIT_BCNDMAINT15 BIT(23) #define BIT_ATIMEND15 BIT(23) #define BIT_TXBCN14OK BIT(22) #define BIT_BCNDMAINT14 BIT(22) #define BIT_ATIMEND14 BIT(22) #define BIT_TXBCN13OK BIT(21) #define BIT_BCNDMAINT13 BIT(21) #define BIT_ATIMEND13 BIT(21) #define BIT_TXBCN12OK BIT(20) #define BIT_BCNDMAINT12 BIT(20) #define BIT_ATIMEND12 BIT(20) #define BIT_TXBCN11OK BIT(19) #define BIT_BCNDMAINT11 BIT(19) #define BIT_ATIMEND11 BIT(19) #define BIT_TXBCN10OK BIT(18) #define BIT_BCNDMAINT10 BIT(18) #define BIT_ATIMEND10 BIT(18) #define BIT_TXBCN9OK BIT(17) #define BIT_BCNDMAINT9 BIT(17) #define BIT_ATIMEND9 BIT(17) #define BIT_TXBCN8OK BIT(16) #define BIT_BCNDMAINT8 BIT(16) #define BIT_ATIMEND8 BIT(16) #define BIT_BCNDERR_PORT4 BIT(15) #define BIT_BCNDERR_PORT3 BIT(14) #define BIT_BCNDERR_PORT2 BIT(13) #define BIT_BCNDERR_PORT1 BIT(12) #define BIT_TXBCN15ERR BIT(7) #define BIT_BCNDERR15 BIT(7) #define BIT_TXBCN14ERR BIT(6) #define BIT_BCNDERR14 BIT(6) #define BIT_TXBCN13ERR BIT(5) #define BIT_BCNDERR13 BIT(5) #define BIT_PS_TIMER_EARLY_INT_5 BIT(5) #define BIT_TXBCN12ERR BIT(4) #define BIT_BCNDERR12 BIT(4) #define BIT_PS_TIMER_EARLY_INT_4 BIT(4) #define BIT_TXBCN11ERR BIT(3) #define BIT_BCNDERR11 BIT(3) #define BIT_PS_TIMER_EARLY_INT_3 BIT(3) #define BIT_TXBCN10ERR BIT(2) #define BIT_BCNDERR10 BIT(2) #define BIT_PS_TIMER_EARLY_INT_2 BIT(2) #define BIT_TXBCN9ERR BIT(1) #define BIT_BCNDERR9 BIT(1) #define BIT_PS_TIMER_EARLY_INT_1 BIT(1) #define BIT_SHIFT_BG 0 #define BIT_MASK_BG 0x7 #define BIT_BG(x) (((x) & BIT_MASK_BG) << BIT_SHIFT_BG) #define BITS_BG (BIT_MASK_BG << BIT_SHIFT_BG) #define BIT_CLEAR_BG(x) ((x) & (~BITS_BG)) #define BIT_GET_BG(x) (((x) >> BIT_SHIFT_BG) & BIT_MASK_BG) #define BIT_SET_BG(x, v) (BIT_CLEAR_BG(x) | BIT_BG(v)) #define BIT_TXBCN8ERR BIT(0) #define BIT_BCNDERR8 BIT(0) #define BIT_PS_TIMER_EARLY_INT_0 BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SYS_CFG5 (Offset 0x1070) */ #define BIT_LPS_STATUS BIT(3) #define BIT_HCI_TXDMA_BUSY BIT(2) #define BIT_HCI_TXDMA_ALLOW BIT(1) #define BIT_FW_CTRL_HCI_TXDMA_EN BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ #define BIT_SCH_PHY_TXOP_SIFS_INT BIT(23) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ #define BIT_WDT_AUTO_MODE BIT(22) #define BIT_WDT_PLATFORM_EN BIT(21) #define BIT_WDT_CPU_EN BIT(20) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ #define BIT_WDT_OPT_IOWRAPPER BIT(19) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ #define BIT_ANA_PORT_IDLE BIT(18) #define BIT_MAC_PORT_IDLE BIT(17) #define BIT_WL_PLATFORM_RST BIT(16) #define BIT_WL_SECURITY_CLK BIT(15) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ #define BIT_DDMA_EN BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ #define BIT_SHIFT_CPU_DMEM_CON 0 #define BIT_MASK_CPU_DMEM_CON 0xff #define BIT_CPU_DMEM_CON(x) \ (((x) & BIT_MASK_CPU_DMEM_CON) << BIT_SHIFT_CPU_DMEM_CON) #define BITS_CPU_DMEM_CON (BIT_MASK_CPU_DMEM_CON << BIT_SHIFT_CPU_DMEM_CON) #define BIT_CLEAR_CPU_DMEM_CON(x) ((x) & (~BITS_CPU_DMEM_CON)) #define BIT_GET_CPU_DMEM_CON(x) \ (((x) >> BIT_SHIFT_CPU_DMEM_CON) & BIT_MASK_CPU_DMEM_CON) #define BIT_SET_CPU_DMEM_CON(x, v) \ (BIT_CLEAR_CPU_DMEM_CON(x) | BIT_CPU_DMEM_CON(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_BOOT_REASON (Offset 0x1088) */ #define BIT_SHIFT_BOOT_REASON_V1 0 #define BIT_MASK_BOOT_REASON_V1 0x7 #define BIT_BOOT_REASON_V1(x) \ (((x) & BIT_MASK_BOOT_REASON_V1) << BIT_SHIFT_BOOT_REASON_V1) #define BITS_BOOT_REASON_V1 \ (BIT_MASK_BOOT_REASON_V1 << BIT_SHIFT_BOOT_REASON_V1) #define BIT_CLEAR_BOOT_REASON_V1(x) ((x) & (~BITS_BOOT_REASON_V1)) #define BIT_GET_BOOT_REASON_V1(x) \ (((x) >> BIT_SHIFT_BOOT_REASON_V1) & BIT_MASK_BOOT_REASON_V1) #define BIT_SET_BOOT_REASON_V1(x, v) \ (BIT_CLEAR_BOOT_REASON_V1(x) | BIT_BOOT_REASON_V1(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HIMR4 (Offset 0x1090) */ #define BIT_ATIM_END_INT16_MSK BIT(32) #define BIT_ATIM_END_INT15_MSK BIT(31) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ #define BIT_DATA_FW_READY BIT(31) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HIMR4 (Offset 0x1090) */ #define BIT_ATIM_END_INT14_MSK BIT(30) #define BIT_ATIM_END_INT13_MSK BIT(29) #define BIT_ATIM_END_INT12_MSK BIT(28) #define BIT_ATIM_END_INT11_MSK BIT(27) #define BIT_ATIM_END_INT10_MSK BIT(26) #define BIT_ATIM_END_INT9_MSK BIT(25) #define BIT_ATIM_END_INT8_MSK BIT(24) #define BIT_TX_BCN_ERR_INT15_MSK BIT(23) #define BIT_TX_BCN_ERR_INT14_MSK BIT(22) #define BIT_TX_BCN_ERR_INT13_MSK BIT(21) #define BIT_TX_BCN_ERR_INT12_MSK BIT(20) #define BIT_TX_BCN_ERR_INT11_MSK BIT(19) #define BIT_TX_BCN_ERR_INT10_MSK BIT(18) #define BIT_TX_BCN_ERR_INT9_MSK BIT(17) #define BIT_TX_BCN_ERR_INT8_MSK BIT(16) #define BIT_TX_BCN_OK_INT15_MSK BIT(15) #define BIT_TX_BCN_OK_INT14_MSK BIT(14) #define BIT_TX_BCN_OK_INT13_MSK BIT(13) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ #define BIT_WDT_SYS_RST BIT(13) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HIMR4 (Offset 0x1090) */ #define BIT_TX_BCN_OK_INT12_MSK BIT(12) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ #define BIT_WDT_ENABLE BIT(12) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HIMR4 (Offset 0x1090) */ #define BIT_TX_BCN_OK_INT11_MSK BIT(11) #define BIT_TX_BCN_OK_INT10_MSK BIT(10) #define BIT_TX_BCN_OK_INT9_MSK BIT(9) #define BIT_TX_BCN_OK_INT8_MSK BIT(8) #define BIT_BCN_DMA_INT15_MSK BIT(7) #define BIT_BCN_DMA_INT14_MSK BIT(6) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ #define BIT_SHIFT_BOOT_SEL 6 #define BIT_MASK_BOOT_SEL 0x3 #define BIT_BOOT_SEL(x) (((x) & BIT_MASK_BOOT_SEL) << BIT_SHIFT_BOOT_SEL) #define BITS_BOOT_SEL (BIT_MASK_BOOT_SEL << BIT_SHIFT_BOOT_SEL) #define BIT_CLEAR_BOOT_SEL(x) ((x) & (~BITS_BOOT_SEL)) #define BIT_GET_BOOT_SEL(x) (((x) >> BIT_SHIFT_BOOT_SEL) & BIT_MASK_BOOT_SEL) #define BIT_SET_BOOT_SEL(x, v) (BIT_CLEAR_BOOT_SEL(x) | BIT_BOOT_SEL(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HIMR4 (Offset 0x1090) */ #define BIT_BCN_DMA_INT13_MSK BIT(5) #define BIT_BCN_DMA_INT12_MSK BIT(4) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ #define BIT_CLK_SEL BIT(4) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HIMR4 (Offset 0x1090) */ #define BIT_BCN_DMA_INT11_MSK BIT(3) #define BIT_BCN_DMA_INT10_MSK BIT(2) #define BIT_BCN_DMA_INT9_MSK BIT(1) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ #define BIT_DATA_PLATFORM_RST BIT(1) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HIMR4 (Offset 0x1090) */ #define BIT_BCN_DMA_INT8_MSK BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ #define BIT_DATA_CPU_RST BIT(0) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HISR4 (Offset 0x1094) */ #define BIT_TX_BCN_ERR_INT15 BIT(23) #define BIT_TX_BCN_ERR_INT14 BIT(22) #define BIT_TX_BCN_ERR_INT13 BIT(21) #define BIT_TX_BCN_ERR_INT12 BIT(20) #define BIT_TX_BCN_ERR_INT11 BIT(19) #define BIT_TX_BCN_ERR_INT10 BIT(18) #define BIT_TX_BCN_ERR_INT9 BIT(17) #define BIT_TX_BCN_ERR_INT8 BIT(16) #define BIT_TX_BCN_OK_INT15 BIT(15) #define BIT_TX_BCN_OK_INT14 BIT(14) #define BIT_TX_BCN_OK_INT13 BIT(13) #define BIT_TX_BCN_OK_INT12 BIT(12) #define BIT_TX_BCN_OK_INT11 BIT(11) #define BIT_TX_BCN_OK_INT10 BIT(10) #define BIT_TX_BCN_OK_INT9 BIT(9) #define BIT_TX_BCN_OK_INT8 BIT(8) #define BIT_BCN_DMA_INT15 BIT(7) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ #define BIT_HOST_INTERFACE_IO_PATH BIT(7) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HISR4 (Offset 0x1094) */ #define BIT_BCN_DMA_INT14 BIT(6) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ #define BIT_EN_TXDMA_OFLD BIT(6) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HISR4 (Offset 0x1094) */ #define BIT_BCN_DMA_INT13 BIT(5) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ #define BIT_EN_RXDMA_OFLD BIT(5) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HISR4 (Offset 0x1094) */ #define BIT_BCN_DMA_INT12 BIT(4) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ #define BIT_EN_HCI_DMA_TX BIT(4) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HISR4 (Offset 0x1094) */ #define BIT_BCN_DMA_INT11 BIT(3) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ #define BIT_EN_HCI_DMA_RX BIT(3) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HISR4 (Offset 0x1094) */ #define BIT_BCN_DMA_INT10 BIT(2) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ #define BIT_EN_AXI_DMA_TX BIT(2) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HISR4 (Offset 0x1094) */ #define BIT_BCN_DMA_INT9 BIT(1) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ #define BIT_EN_AXI_DMA_RX BIT(1) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HISR4 (Offset 0x1094) */ #define BIT_BCN_DMA_INT8 BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ #define BIT_EN_PKT_ENG BIT(0) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HIMR5 (Offset 0x1098) */ #define BIT_BCN_QDMA_ERR_INT15_MSK BIT(7) #define BIT_BCN_QDMA_ERR_INT14_MSK BIT(6) #define BIT_BCN_QDMA_ERR_INT13_MSK BIT(5) #define BIT_BCN_QDMA_ERR_INT12_MSK BIT(4) #define BIT_BCN_QDMA_ERR_INT11_MSK BIT(3) #define BIT_BCN_QDMA_ERR_INT10_MSK BIT(2) #define BIT_BCN_QDMA_ERR_INT9_MSK BIT(1) #define BIT_BCN_QDMA_ERR_INT8_MSK BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXDMA_STOP_HIMR (Offset 0x1098) */ #define BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK 0 #define BIT_MASK_NTH_TXDMA_STOP_INT_MSK 0x1ffff #define BIT_NTH_TXDMA_STOP_INT_MSK(x) \ (((x) & BIT_MASK_NTH_TXDMA_STOP_INT_MSK) \ << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK) #define BITS_NTH_TXDMA_STOP_INT_MSK \ (BIT_MASK_NTH_TXDMA_STOP_INT_MSK << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK) #define BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK(x) \ ((x) & (~BITS_NTH_TXDMA_STOP_INT_MSK)) #define BIT_GET_NTH_TXDMA_STOP_INT_MSK(x) \ (((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK) & \ BIT_MASK_NTH_TXDMA_STOP_INT_MSK) #define BIT_SET_NTH_TXDMA_STOP_INT_MSK(x, v) \ (BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK(x) | BIT_NTH_TXDMA_STOP_INT_MSK(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HISR5 (Offset 0x109C) */ #define BIT_BCN_QDMA_ERR_INT15 BIT(7) #define BIT_BCN_QDMA_ERR_INT14 BIT(6) #define BIT_BCN_QDMA_ERR_INT13 BIT(5) #define BIT_BCN_QDMA_ERR_INT12 BIT(4) #define BIT_BCN_QDMA_ERR_INT11 BIT(3) #define BIT_BCN_QDMA_ERR_INT10 BIT(2) #define BIT_BCN_QDMA_ERR_INT9 BIT(1) #define BIT_BCN_QDMA_ERR_INT8 BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TXDMA_STOP_HISR (Offset 0x109C) */ #define BIT_SHIFT_NTH_TXDMA_STOP_INT 0 #define BIT_MASK_NTH_TXDMA_STOP_INT 0x1ffff #define BIT_NTH_TXDMA_STOP_INT(x) \ (((x) & BIT_MASK_NTH_TXDMA_STOP_INT) << BIT_SHIFT_NTH_TXDMA_STOP_INT) #define BITS_NTH_TXDMA_STOP_INT \ (BIT_MASK_NTH_TXDMA_STOP_INT << BIT_SHIFT_NTH_TXDMA_STOP_INT) #define BIT_CLEAR_NTH_TXDMA_STOP_INT(x) ((x) & (~BITS_NTH_TXDMA_STOP_INT)) #define BIT_GET_NTH_TXDMA_STOP_INT(x) \ (((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT) & BIT_MASK_NTH_TXDMA_STOP_INT) #define BIT_SET_NTH_TXDMA_STOP_INT(x, v) \ (BIT_CLEAR_NTH_TXDMA_STOP_INT(x) | BIT_NTH_TXDMA_STOP_INT(v)) /* 2 REG_TXDMA_START_HIMR (Offset 0x10A0) */ #define BIT_SHIFT_NTH_TXDMA_START_INT_MSK 0 #define BIT_MASK_NTH_TXDMA_START_INT_MSK 0x1ffff #define BIT_NTH_TXDMA_START_INT_MSK(x) \ (((x) & BIT_MASK_NTH_TXDMA_START_INT_MSK) \ << BIT_SHIFT_NTH_TXDMA_START_INT_MSK) #define BITS_NTH_TXDMA_START_INT_MSK \ (BIT_MASK_NTH_TXDMA_START_INT_MSK << BIT_SHIFT_NTH_TXDMA_START_INT_MSK) #define BIT_CLEAR_NTH_TXDMA_START_INT_MSK(x) \ ((x) & (~BITS_NTH_TXDMA_START_INT_MSK)) #define BIT_GET_NTH_TXDMA_START_INT_MSK(x) \ (((x) >> BIT_SHIFT_NTH_TXDMA_START_INT_MSK) & \ BIT_MASK_NTH_TXDMA_START_INT_MSK) #define BIT_SET_NTH_TXDMA_START_INT_MSK(x, v) \ (BIT_CLEAR_NTH_TXDMA_START_INT_MSK(x) | BIT_NTH_TXDMA_START_INT_MSK(v)) /* 2 REG_TXDMA_START_HISR (Offset 0x10A4) */ #define BIT_SHIFT_NTH_TXDMA_START_INT 0 #define BIT_MASK_NTH_TXDMA_START_INT 0x1ffff #define BIT_NTH_TXDMA_START_INT(x) \ (((x) & BIT_MASK_NTH_TXDMA_START_INT) << BIT_SHIFT_NTH_TXDMA_START_INT) #define BITS_NTH_TXDMA_START_INT \ (BIT_MASK_NTH_TXDMA_START_INT << BIT_SHIFT_NTH_TXDMA_START_INT) #define BIT_CLEAR_NTH_TXDMA_START_INT(x) ((x) & (~BITS_NTH_TXDMA_START_INT)) #define BIT_GET_NTH_TXDMA_START_INT(x) \ (((x) >> BIT_SHIFT_NTH_TXDMA_START_INT) & BIT_MASK_NTH_TXDMA_START_INT) #define BIT_SET_NTH_TXDMA_START_INT(x, v) \ (BIT_CLEAR_NTH_TXDMA_START_INT(x) | BIT_NTH_TXDMA_START_INT(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_NFCPAD_CTRL (Offset 0x10A8) */ #define BIT_PAD_SHUTDW BIT(18) #define BIT_SYSON_NFC_PAD BIT(17) #define BIT_NFC_INT_PAD_CTRL BIT(16) #define BIT_NFC_RFDIS_PAD_CTRL BIT(15) #define BIT_NFC_CLK_PAD_CTRL BIT(14) #define BIT_NFC_DATA_PAD_CTRL BIT(13) #define BIT_NFC_PAD_PULL_CTRL BIT(12) #define BIT_SHIFT_NFCPAD_IO_SEL 8 #define BIT_MASK_NFCPAD_IO_SEL 0xf #define BIT_NFCPAD_IO_SEL(x) \ (((x) & BIT_MASK_NFCPAD_IO_SEL) << BIT_SHIFT_NFCPAD_IO_SEL) #define BITS_NFCPAD_IO_SEL (BIT_MASK_NFCPAD_IO_SEL << BIT_SHIFT_NFCPAD_IO_SEL) #define BIT_CLEAR_NFCPAD_IO_SEL(x) ((x) & (~BITS_NFCPAD_IO_SEL)) #define BIT_GET_NFCPAD_IO_SEL(x) \ (((x) >> BIT_SHIFT_NFCPAD_IO_SEL) & BIT_MASK_NFCPAD_IO_SEL) #define BIT_SET_NFCPAD_IO_SEL(x, v) \ (BIT_CLEAR_NFCPAD_IO_SEL(x) | BIT_NFCPAD_IO_SEL(v)) #define BIT_SHIFT_NFCPAD_OUT 4 #define BIT_MASK_NFCPAD_OUT 0xf #define BIT_NFCPAD_OUT(x) (((x) & BIT_MASK_NFCPAD_OUT) << BIT_SHIFT_NFCPAD_OUT) #define BITS_NFCPAD_OUT (BIT_MASK_NFCPAD_OUT << BIT_SHIFT_NFCPAD_OUT) #define BIT_CLEAR_NFCPAD_OUT(x) ((x) & (~BITS_NFCPAD_OUT)) #define BIT_GET_NFCPAD_OUT(x) \ (((x) >> BIT_SHIFT_NFCPAD_OUT) & BIT_MASK_NFCPAD_OUT) #define BIT_SET_NFCPAD_OUT(x, v) (BIT_CLEAR_NFCPAD_OUT(x) | BIT_NFCPAD_OUT(v)) #define BIT_SHIFT_NFCPAD_IN 0 #define BIT_MASK_NFCPAD_IN 0xf #define BIT_NFCPAD_IN(x) (((x) & BIT_MASK_NFCPAD_IN) << BIT_SHIFT_NFCPAD_IN) #define BITS_NFCPAD_IN (BIT_MASK_NFCPAD_IN << BIT_SHIFT_NFCPAD_IN) #define BIT_CLEAR_NFCPAD_IN(x) ((x) & (~BITS_NFCPAD_IN)) #define BIT_GET_NFCPAD_IN(x) (((x) >> BIT_SHIFT_NFCPAD_IN) & BIT_MASK_NFCPAD_IN) #define BIT_SET_NFCPAD_IN(x, v) (BIT_CLEAR_NFCPAD_IN(x) | BIT_NFCPAD_IN(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR2 (Offset 0x10B0) */ #define BIT_BCNDMAINT_P4_MSK BIT(31) #define BIT_BCNDMAINT_P4 BIT(31) #define BIT_BCNDMAINT_P3_MSK BIT(30) #define BIT_BCNDMAINT_P3 BIT(30) #define BIT_BCNDMAINT_P2_MSK BIT(29) #define BIT_BCNDMAINT_P2 BIT(29) #define BIT_BCNDMAINT_P1_MSK BIT(28) #define BIT_BCNDMAINT_P1 BIT(28) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR2 (Offset 0x10B0) */ #define BIT_SCH_PHY_TXOP_SIFS_INT_MSK BIT(23) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR2 (Offset 0x10B0) */ #define BIT_ATIMEND7_MSK BIT(22) #define BIT_ATIMEND7 BIT(22) #define BIT_ATIMEND6_MSK BIT(21) #define BIT_ATIMEND6 BIT(21) #define BIT_ATIMEND5_MSK BIT(20) #define BIT_ATIMEND5 BIT(20) #define BIT_ATIMEND4_MSK BIT(19) #define BIT_ATIMEND4 BIT(19) #define BIT_ATIMEND3_MSK BIT(18) #define BIT_ATIMEND3 BIT(18) #define BIT_ATIMEND2_MSK BIT(17) #define BIT_ATIMEND2 BIT(17) #define BIT_ATIMEND1_MSK BIT(16) #define BIT_ATIMEND1 BIT(16) #define BIT_TXBCN7OK_MSK BIT(14) #define BIT_TXBCN7OK BIT(14) #define BIT_TXBCN6OK_MSK BIT(13) #define BIT_TXBCN6OK BIT(13) #define BIT_TXBCN5OK_MSK BIT(12) #define BIT_TXBCN5OK BIT(12) #define BIT_TXBCN4OK_MSK BIT(11) #define BIT_TXBCN4OK BIT(11) #define BIT_TXBCN3OK_MSK BIT(10) #define BIT_TXBCN3OK BIT(10) #define BIT_TXBCN2OK_MSK BIT(9) #define BIT_TXBCN2OK BIT(9) #define BIT_TXBCN1OK_MSK_V1 BIT(8) #define BIT_TXBCN1OK BIT(8) #define BIT_TXBCN7ERR_MSK BIT(6) #define BIT_TXBCN7ERR BIT(6) #define BIT_TXBCN6ERR_MSK BIT(5) #define BIT_TXBCN6ERR BIT(5) #define BIT_TXBCN5ERR_MSK BIT(4) #define BIT_TXBCN5ERR BIT(4) #define BIT_TXBCN4ERR_MSK BIT(3) #define BIT_TXBCN4ERR BIT(3) #define BIT_TXBCN3ERR_MSK BIT(2) #define BIT_TXBCN3ERR BIT(2) #define BIT_TXBCN2ERR_MSK BIT(1) #define BIT_TXBCN2ERR BIT(1) #define BIT_TXBCN1ERR_MSK_V1 BIT(0) #define BIT_TXBCN1ERR BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_GTINT12 BIT(24) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_GTINT12_MSK BIT(24) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_GTINT11 BIT(23) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_GTINT11_MSK BIT(23) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_GTINT10 BIT(22) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_GTINT10_MSK BIT(22) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_GTINT9 BIT(21) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_GTINT9_MSK BIT(21) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_RX_DESC_BUF_FULL BIT(20) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_RX_DESC_BUF_FULL_MSK BIT(20) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_CPHY_LDO_OCP_DET_INT BIT(19) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_CPHY_LDO_OCP_DET_INT_MSK BIT(19) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_WDT_PLATFORM_INT_MSK BIT(18) #define BIT_WDT_PLATFORM_INT BIT(18) #define BIT_WDT_CPU_INT_MSK BIT(17) #define BIT_WDT_CPU_INT BIT(17) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_SETH2CDOK_MASK BIT(16) #define BIT_SETH2CDOK BIT(16) #define BIT_H2C_CMD_FULL_MASK BIT(15) #define BIT_H2C_CMD_FULL BIT(15) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_PWR_INT_127_MASK BIT(14) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_PKT_TRANS_ERR BIT(14) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_PKT_TRANS_ERR_MASK BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK BIT(13) #define BIT_TXSHORTCUT_TXDESUPDATEOK BIT(13) #define BIT_TXSHORTCUT_BKUPDATEOK_MASK BIT(12) #define BIT_TXSHORTCUT_BKUPDATEOK BIT(12) #define BIT_TXSHORTCUT_BEUPDATEOK_MASK BIT(11) #define BIT_TXSHORTCUT_BEUPDATEOK BIT(11) #define BIT_TXSHORTCUT_VIUPDATEOK_MAS BIT(10) #define BIT_TXSHORTCUT_VIUPDATEOK BIT(10) #define BIT_TXSHORTCUT_VOUPDATEOK_MASK BIT(9) #define BIT_TXSHORTCUT_VOUPDATEOK BIT(9) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_PWR_INT_127_MASK_V1 BIT(8) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_SEARCH_FAIL BIT(8) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_SEARCH_FAIL_MSK BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_PWR_INT_126TO96_MASK BIT(7) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_PWR_INT_127TO96 BIT(7) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_PWR_INT_127TO96_MASK BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_PWR_INT_95TO64_MASK BIT(6) #define BIT_PWR_INT_95TO64 BIT(6) #define BIT_PWR_INT_63TO32_MASK BIT(5) #define BIT_PWR_INT_63TO32 BIT(5) #define BIT_PWR_INT_31TO0_MASK BIT(4) #define BIT_PWR_INT_31TO0 BIT(4) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_RX_DMA_STUCK_MSK BIT(3) #define BIT_RX_DMA_STUCK BIT(3) #define BIT_TX_DMA_STUCK_MSK BIT(2) #define BIT_TX_DMA_STUCK BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR3 (Offset 0x10B8) */ #define BIT_DDMA0_LP_INT_MSK BIT(1) #define BIT_DDMA0_LP_INT BIT(1) #define BIT_DDMA0_HP_INT_MSK BIT(0) #define BIT_DDMA0_HP_INT BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_HISR3 (Offset 0x10BC) */ #define BIT_PWR_INT_127 BIT(14) #define BIT_PWR_INT_127_V1 BIT(8) #define BIT_PWR_INT_126TO96 BIT(7) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_SW_MDIO (Offset 0x10C0) */ #define BIT_DIS_TIMEOUT_IO BIT(24) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SW_MDIO (Offset 0x10C0) */ #define BIT_SUS_PL BIT(18) #define BIT_SOP_ESUS BIT(17) #define BIT_SOP_DLDO BIT(16) #define BIT_R_OCP_ST_CLR BIT(8) #define BIT_SW_USB3_MD_SEL BIT(5) #define BIT_SW_PCIE_MD_SEL BIT(4) #define BIT_SW_MDCK BIT(2) #define BIT_SW_MDI BIT(1) #define BIT_MDO BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SW_FLUSH (Offset 0x10C4) */ #define BIT_FLUSH_HOLDN_EN BIT(25) #define BIT_FLUSH_WR_EN BIT(24) #define BIT_SW_FLASH_CONTROL BIT(23) #define BIT_SW_FLASH_WEN_E BIT(19) #define BIT_SW_FLASH_HOLDN_E BIT(18) #define BIT_SW_FLASH_SO_E BIT(17) #define BIT_SW_FLASH_SI_E BIT(16) #define BIT_SW_FLASH_SK_O BIT(13) #define BIT_SW_FLASH_CEN_O BIT(12) #define BIT_SW_FLASH_WEN_O BIT(11) #define BIT_SW_FLASH_HOLDN_O BIT(10) #define BIT_SW_FLASH_SO_O BIT(9) #define BIT_SW_FLASH_SI_O BIT(8) #define BIT_SW_FLASH_WEN_I BIT(3) #define BIT_SW_FLASH_HOLDN_I BIT(2) #define BIT_SW_FLASH_SO_I BIT(1) #define BIT_SW_FLASH_SI_I BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR_7 (Offset 0x10C8) */ #define BIT_DATA_CPU_WDT_INT_MSK BIT(31) #define BIT_OFLD_TXDMA_ERR_MSK BIT(30) #define BIT_OFLD_TXDMA_FULL_MSK BIT(29) #define BIT_OFLD_RXDMA_OVR_MSK BIT(28) #define BIT_OFLD_RXDMA_ERR_MSK BIT(27) #define BIT_OFLD_RXDMA_DES_UA_MSK BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ #define BIT_SHIFT_DBG_GPIO_BMUX_7 21 #define BIT_MASK_DBG_GPIO_BMUX_7 0x7 #define BIT_DBG_GPIO_BMUX_7(x) \ (((x) & BIT_MASK_DBG_GPIO_BMUX_7) << BIT_SHIFT_DBG_GPIO_BMUX_7) #define BITS_DBG_GPIO_BMUX_7 \ (BIT_MASK_DBG_GPIO_BMUX_7 << BIT_SHIFT_DBG_GPIO_BMUX_7) #define BIT_CLEAR_DBG_GPIO_BMUX_7(x) ((x) & (~BITS_DBG_GPIO_BMUX_7)) #define BIT_GET_DBG_GPIO_BMUX_7(x) \ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_7) & BIT_MASK_DBG_GPIO_BMUX_7) #define BIT_SET_DBG_GPIO_BMUX_7(x, v) \ (BIT_CLEAR_DBG_GPIO_BMUX_7(x) | BIT_DBG_GPIO_BMUX_7(v)) #define BIT_SHIFT_DBG_GPIO_BMUX_6 18 #define BIT_MASK_DBG_GPIO_BMUX_6 0x7 #define BIT_DBG_GPIO_BMUX_6(x) \ (((x) & BIT_MASK_DBG_GPIO_BMUX_6) << BIT_SHIFT_DBG_GPIO_BMUX_6) #define BITS_DBG_GPIO_BMUX_6 \ (BIT_MASK_DBG_GPIO_BMUX_6 << BIT_SHIFT_DBG_GPIO_BMUX_6) #define BIT_CLEAR_DBG_GPIO_BMUX_6(x) ((x) & (~BITS_DBG_GPIO_BMUX_6)) #define BIT_GET_DBG_GPIO_BMUX_6(x) \ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_6) & BIT_MASK_DBG_GPIO_BMUX_6) #define BIT_SET_DBG_GPIO_BMUX_6(x, v) \ (BIT_CLEAR_DBG_GPIO_BMUX_6(x) | BIT_DBG_GPIO_BMUX_6(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR_7 (Offset 0x10C8) */ #define BIT_TXDMAOK_CHANNEL_16_MSK BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ #define BIT_SHIFT_DBG_GPIO_BMUX_5 15 #define BIT_MASK_DBG_GPIO_BMUX_5 0x7 #define BIT_DBG_GPIO_BMUX_5(x) \ (((x) & BIT_MASK_DBG_GPIO_BMUX_5) << BIT_SHIFT_DBG_GPIO_BMUX_5) #define BITS_DBG_GPIO_BMUX_5 \ (BIT_MASK_DBG_GPIO_BMUX_5 << BIT_SHIFT_DBG_GPIO_BMUX_5) #define BIT_CLEAR_DBG_GPIO_BMUX_5(x) ((x) & (~BITS_DBG_GPIO_BMUX_5)) #define BIT_GET_DBG_GPIO_BMUX_5(x) \ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_5) & BIT_MASK_DBG_GPIO_BMUX_5) #define BIT_SET_DBG_GPIO_BMUX_5(x, v) \ (BIT_CLEAR_DBG_GPIO_BMUX_5(x) | BIT_DBG_GPIO_BMUX_5(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR_7 (Offset 0x10C8) */ #define BIT_TXDMAOK_CHANNEL_13_MSK BIT(13) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ #define BIT_SHIFT_DBG_GPIO_BMUX_4 12 #define BIT_MASK_DBG_GPIO_BMUX_4 0x7 #define BIT_DBG_GPIO_BMUX_4(x) \ (((x) & BIT_MASK_DBG_GPIO_BMUX_4) << BIT_SHIFT_DBG_GPIO_BMUX_4) #define BITS_DBG_GPIO_BMUX_4 \ (BIT_MASK_DBG_GPIO_BMUX_4 << BIT_SHIFT_DBG_GPIO_BMUX_4) #define BIT_CLEAR_DBG_GPIO_BMUX_4(x) ((x) & (~BITS_DBG_GPIO_BMUX_4)) #define BIT_GET_DBG_GPIO_BMUX_4(x) \ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_4) & BIT_MASK_DBG_GPIO_BMUX_4) #define BIT_SET_DBG_GPIO_BMUX_4(x, v) \ (BIT_CLEAR_DBG_GPIO_BMUX_4(x) | BIT_DBG_GPIO_BMUX_4(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR_7 (Offset 0x10C8) */ #define BIT_TXDMAOK_CHANNEL_12_MSK BIT(12) #define BIT_TXDMAOK_CHANNEL_11_MSK BIT(11) #define BIT_TXDMAOK_CHANNEL_10_MSK BIT(10) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ #define BIT_SHIFT_DBG_GPIO_BMUX_3 9 #define BIT_MASK_DBG_GPIO_BMUX_3 0x7 #define BIT_DBG_GPIO_BMUX_3(x) \ (((x) & BIT_MASK_DBG_GPIO_BMUX_3) << BIT_SHIFT_DBG_GPIO_BMUX_3) #define BITS_DBG_GPIO_BMUX_3 \ (BIT_MASK_DBG_GPIO_BMUX_3 << BIT_SHIFT_DBG_GPIO_BMUX_3) #define BIT_CLEAR_DBG_GPIO_BMUX_3(x) ((x) & (~BITS_DBG_GPIO_BMUX_3)) #define BIT_GET_DBG_GPIO_BMUX_3(x) \ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_3) & BIT_MASK_DBG_GPIO_BMUX_3) #define BIT_SET_DBG_GPIO_BMUX_3(x, v) \ (BIT_CLEAR_DBG_GPIO_BMUX_3(x) | BIT_DBG_GPIO_BMUX_3(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR_7 (Offset 0x10C8) */ #define BIT_TXDMAOK_CHANNEL_9_MSK BIT(9) #define BIT_TXDMAOK_CHANNEL_8_MSK BIT(8) #define BIT_TXDMAOK_CHANNEL_7_MSK BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ #define BIT_SHIFT_DBG_GPIO_BMUX_2 6 #define BIT_MASK_DBG_GPIO_BMUX_2 0x7 #define BIT_DBG_GPIO_BMUX_2(x) \ (((x) & BIT_MASK_DBG_GPIO_BMUX_2) << BIT_SHIFT_DBG_GPIO_BMUX_2) #define BITS_DBG_GPIO_BMUX_2 \ (BIT_MASK_DBG_GPIO_BMUX_2 << BIT_SHIFT_DBG_GPIO_BMUX_2) #define BIT_CLEAR_DBG_GPIO_BMUX_2(x) ((x) & (~BITS_DBG_GPIO_BMUX_2)) #define BIT_GET_DBG_GPIO_BMUX_2(x) \ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_2) & BIT_MASK_DBG_GPIO_BMUX_2) #define BIT_SET_DBG_GPIO_BMUX_2(x, v) \ (BIT_CLEAR_DBG_GPIO_BMUX_2(x) | BIT_DBG_GPIO_BMUX_2(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR_7 (Offset 0x10C8) */ #define BIT_TXDMAOK_CHANNEL_6_MSK BIT(6) #define BIT_TXDMAOK_CHANNEL_5_MSK BIT(5) #define BIT_TXDMAOK_CHANNEL_4_MSK BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ #define BIT_SHIFT_DBG_GPIO_BMUX_1 3 #define BIT_MASK_DBG_GPIO_BMUX_1 0x7 #define BIT_DBG_GPIO_BMUX_1(x) \ (((x) & BIT_MASK_DBG_GPIO_BMUX_1) << BIT_SHIFT_DBG_GPIO_BMUX_1) #define BITS_DBG_GPIO_BMUX_1 \ (BIT_MASK_DBG_GPIO_BMUX_1 << BIT_SHIFT_DBG_GPIO_BMUX_1) #define BIT_CLEAR_DBG_GPIO_BMUX_1(x) ((x) & (~BITS_DBG_GPIO_BMUX_1)) #define BIT_GET_DBG_GPIO_BMUX_1(x) \ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_1) & BIT_MASK_DBG_GPIO_BMUX_1) #define BIT_SET_DBG_GPIO_BMUX_1(x, v) \ (BIT_CLEAR_DBG_GPIO_BMUX_1(x) | BIT_DBG_GPIO_BMUX_1(v)) #define BIT_SHIFT_DBG_GPIO_BMUX_0 0 #define BIT_MASK_DBG_GPIO_BMUX_0 0x7 #define BIT_DBG_GPIO_BMUX_0(x) \ (((x) & BIT_MASK_DBG_GPIO_BMUX_0) << BIT_SHIFT_DBG_GPIO_BMUX_0) #define BITS_DBG_GPIO_BMUX_0 \ (BIT_MASK_DBG_GPIO_BMUX_0 << BIT_SHIFT_DBG_GPIO_BMUX_0) #define BIT_CLEAR_DBG_GPIO_BMUX_0(x) ((x) & (~BITS_DBG_GPIO_BMUX_0)) #define BIT_GET_DBG_GPIO_BMUX_0(x) \ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_0) & BIT_MASK_DBG_GPIO_BMUX_0) #define BIT_SET_DBG_GPIO_BMUX_0(x, v) \ (BIT_CLEAR_DBG_GPIO_BMUX_0(x) | BIT_DBG_GPIO_BMUX_0(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HISR_7 (Offset 0x10CC) */ #define BIT_DATA_CPU_WDT_INT BIT(31) #define BIT_OFLD_TXDMA_ERR BIT(30) #define BIT_OFLD_TXDMA_FULL BIT(29) #define BIT_OFLD_RXDMA_OVR BIT(28) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FPGA_TAG (Offset 0x10CC) */ #define BIT_WL_DSS_RSTN BIT(27) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HISR_7 (Offset 0x10CC) */ #define BIT_OFLD_RXDMA_ERR BIT(27) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FPGA_TAG (Offset 0x10CC) */ #define BIT_WL_DSS_EN_CLK BIT(26) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HISR_7 (Offset 0x10CC) */ #define BIT_OFLD_RXDMA_DES_UA BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FPGA_TAG (Offset 0x10CC) */ #define BIT_WL_DSS_SPEED_EN BIT(25) #define BIT_WL_DSS_WIRE_SEL BIT(24) #define BIT_SHIFT_WL_DSS_RO_SEL 20 #define BIT_MASK_WL_DSS_RO_SEL 0x7 #define BIT_WL_DSS_RO_SEL(x) \ (((x) & BIT_MASK_WL_DSS_RO_SEL) << BIT_SHIFT_WL_DSS_RO_SEL) #define BITS_WL_DSS_RO_SEL (BIT_MASK_WL_DSS_RO_SEL << BIT_SHIFT_WL_DSS_RO_SEL) #define BIT_CLEAR_WL_DSS_RO_SEL(x) ((x) & (~BITS_WL_DSS_RO_SEL)) #define BIT_GET_WL_DSS_RO_SEL(x) \ (((x) >> BIT_SHIFT_WL_DSS_RO_SEL) & BIT_MASK_WL_DSS_RO_SEL) #define BIT_SET_WL_DSS_RO_SEL(x, v) \ (BIT_CLEAR_WL_DSS_RO_SEL(x) | BIT_WL_DSS_RO_SEL(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HISR_7 (Offset 0x10CC) */ #define BIT_TXDMAOK_CHANNEL_16 BIT(16) #define BIT_TXDMAOK_CHANNEL_13 BIT(13) #define BIT_TXDMAOK_CHANNEL_12 BIT(12) #define BIT_TXDMAOK_CHANNEL_11 BIT(11) #define BIT_TXDMAOK_CHANNEL_10 BIT(10) #define BIT_TXDMAOK_CHANNEL_9 BIT(9) #define BIT_TXDMAOK_CHANNEL_8 BIT(8) #define BIT_TXDMAOK_CHANNEL_7 BIT(7) #define BIT_TXDMAOK_CHANNEL_6 BIT(6) #define BIT_TXDMAOK_CHANNEL_5 BIT(5) #define BIT_TXDMAOK_CHANNEL_4 BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FPGA_TAG (Offset 0x10CC) */ #define BIT_SHIFT_FPGA_TAG 0 #define BIT_MASK_FPGA_TAG 0xffffffffL #define BIT_FPGA_TAG(x) (((x) & BIT_MASK_FPGA_TAG) << BIT_SHIFT_FPGA_TAG) #define BITS_FPGA_TAG (BIT_MASK_FPGA_TAG << BIT_SHIFT_FPGA_TAG) #define BIT_CLEAR_FPGA_TAG(x) ((x) & (~BITS_FPGA_TAG)) #define BIT_GET_FPGA_TAG(x) (((x) >> BIT_SHIFT_FPGA_TAG) & BIT_MASK_FPGA_TAG) #define BIT_SET_FPGA_TAG(x, v) (BIT_CLEAR_FPGA_TAG(x) | BIT_FPGA_TAG(v)) #define BIT_SHIFT_WL_DSS_COUNT_OUT 0 #define BIT_MASK_WL_DSS_COUNT_OUT 0xfffff #define BIT_WL_DSS_COUNT_OUT(x) \ (((x) & BIT_MASK_WL_DSS_COUNT_OUT) << BIT_SHIFT_WL_DSS_COUNT_OUT) #define BITS_WL_DSS_COUNT_OUT \ (BIT_MASK_WL_DSS_COUNT_OUT << BIT_SHIFT_WL_DSS_COUNT_OUT) #define BIT_CLEAR_WL_DSS_COUNT_OUT(x) ((x) & (~BITS_WL_DSS_COUNT_OUT)) #define BIT_GET_WL_DSS_COUNT_OUT(x) \ (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT) & BIT_MASK_WL_DSS_COUNT_OUT) #define BIT_SET_WL_DSS_COUNT_OUT(x, v) \ (BIT_CLEAR_WL_DSS_COUNT_OUT(x) | BIT_WL_DSS_COUNT_OUT(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_H2C_PKT_READADDR (Offset 0x10D0) */ #define BIT_SHIFT_H2C_PKT_READADDR 0 #define BIT_MASK_H2C_PKT_READADDR 0x3ffff #define BIT_H2C_PKT_READADDR(x) \ (((x) & BIT_MASK_H2C_PKT_READADDR) << BIT_SHIFT_H2C_PKT_READADDR) #define BITS_H2C_PKT_READADDR \ (BIT_MASK_H2C_PKT_READADDR << BIT_SHIFT_H2C_PKT_READADDR) #define BIT_CLEAR_H2C_PKT_READADDR(x) ((x) & (~BITS_H2C_PKT_READADDR)) #define BIT_GET_H2C_PKT_READADDR(x) \ (((x) >> BIT_SHIFT_H2C_PKT_READADDR) & BIT_MASK_H2C_PKT_READADDR) #define BIT_SET_H2C_PKT_READADDR(x, v) \ (BIT_CLEAR_H2C_PKT_READADDR(x) | BIT_H2C_PKT_READADDR(v)) /* 2 REG_H2C_PKT_WRITEADDR (Offset 0x10D4) */ #define BIT_SHIFT_H2C_PKT_WRITEADDR 0 #define BIT_MASK_H2C_PKT_WRITEADDR 0x3ffff #define BIT_H2C_PKT_WRITEADDR(x) \ (((x) & BIT_MASK_H2C_PKT_WRITEADDR) << BIT_SHIFT_H2C_PKT_WRITEADDR) #define BITS_H2C_PKT_WRITEADDR \ (BIT_MASK_H2C_PKT_WRITEADDR << BIT_SHIFT_H2C_PKT_WRITEADDR) #define BIT_CLEAR_H2C_PKT_WRITEADDR(x) ((x) & (~BITS_H2C_PKT_WRITEADDR)) #define BIT_GET_H2C_PKT_WRITEADDR(x) \ (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_PKT_WRITEADDR) #define BIT_SET_H2C_PKT_WRITEADDR(x, v) \ (BIT_CLEAR_H2C_PKT_WRITEADDR(x) | BIT_H2C_PKT_WRITEADDR(v)) /* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ #define BIT_MEM_BB_SD BIT(17) #define BIT_MEM_BB_DS BIT(16) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ #define BIT_MEM_DENG_LS BIT(13) #define BIT_MEM_DENG_DS BIT(12) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ #define BIT_MEM_BT_DS BIT(10) #define BIT_MEM_SDIO_LS BIT(9) #define BIT_MEM_SDIO_DS BIT(8) #define BIT_MEM_USB_LS BIT(7) #define BIT_MEM_USB_DS BIT(6) #define BIT_MEM_PCI_LS BIT(5) #define BIT_MEM_PCI_DS BIT(4) #define BIT_MEM_WLMAC_LS BIT(3) #define BIT_MEM_WLMAC_DS BIT(2) #define BIT_MEM_WLMCU_LS BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_WL_DSS_CTRL1 (Offset 0x10D8) */ #define BIT_SHIFT_WL_DSS_DATA_IN 0 #define BIT_MASK_WL_DSS_DATA_IN 0xfffff #define BIT_WL_DSS_DATA_IN(x) \ (((x) & BIT_MASK_WL_DSS_DATA_IN) << BIT_SHIFT_WL_DSS_DATA_IN) #define BITS_WL_DSS_DATA_IN \ (BIT_MASK_WL_DSS_DATA_IN << BIT_SHIFT_WL_DSS_DATA_IN) #define BIT_CLEAR_WL_DSS_DATA_IN(x) ((x) & (~BITS_WL_DSS_DATA_IN)) #define BIT_GET_WL_DSS_DATA_IN(x) \ (((x) >> BIT_SHIFT_WL_DSS_DATA_IN) & BIT_MASK_WL_DSS_DATA_IN) #define BIT_SET_WL_DSS_DATA_IN(x, v) \ (BIT_CLEAR_WL_DSS_DATA_IN(x) | BIT_WL_DSS_DATA_IN(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ #define BIT_MEM_WLMCU_DS BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_WL_DSS_STATUS1 (Offset 0x10DC) */ #define BIT_WL_DSS_READY BIT(21) #define BIT_WL_DSS_WSORT_GO BIT(20) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FW_DRV_HANDSHAKE (Offset 0x10DC) */ #define BIT_SHIFT_FW_DRV_HANDSHAKE 0 #define BIT_MASK_FW_DRV_HANDSHAKE 0xffffffffL #define BIT_FW_DRV_HANDSHAKE(x) \ (((x) & BIT_MASK_FW_DRV_HANDSHAKE) << BIT_SHIFT_FW_DRV_HANDSHAKE) #define BITS_FW_DRV_HANDSHAKE \ (BIT_MASK_FW_DRV_HANDSHAKE << BIT_SHIFT_FW_DRV_HANDSHAKE) #define BIT_CLEAR_FW_DRV_HANDSHAKE(x) ((x) & (~BITS_FW_DRV_HANDSHAKE)) #define BIT_GET_FW_DRV_HANDSHAKE(x) \ (((x) >> BIT_SHIFT_FW_DRV_HANDSHAKE) & BIT_MASK_FW_DRV_HANDSHAKE) #define BIT_SET_FW_DRV_HANDSHAKE(x, v) \ (BIT_CLEAR_FW_DRV_HANDSHAKE(x) | BIT_FW_DRV_HANDSHAKE(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_FW_DBG0 (Offset 0x10E0) */ #define BIT_SHIFT_FW_DBG0 0 #define BIT_MASK_FW_DBG0 0xffffffffL #define BIT_FW_DBG0(x) (((x) & BIT_MASK_FW_DBG0) << BIT_SHIFT_FW_DBG0) #define BITS_FW_DBG0 (BIT_MASK_FW_DBG0 << BIT_SHIFT_FW_DBG0) #define BIT_CLEAR_FW_DBG0(x) ((x) & (~BITS_FW_DBG0)) #define BIT_GET_FW_DBG0(x) (((x) >> BIT_SHIFT_FW_DBG0) & BIT_MASK_FW_DBG0) #define BIT_SET_FW_DBG0(x, v) (BIT_CLEAR_FW_DBG0(x) | BIT_FW_DBG0(v)) /* 2 REG_FW_DBG1 (Offset 0x10E4) */ #define BIT_SHIFT_FW_DBG1 0 #define BIT_MASK_FW_DBG1 0xffffffffL #define BIT_FW_DBG1(x) (((x) & BIT_MASK_FW_DBG1) << BIT_SHIFT_FW_DBG1) #define BITS_FW_DBG1 (BIT_MASK_FW_DBG1 << BIT_SHIFT_FW_DBG1) #define BIT_CLEAR_FW_DBG1(x) ((x) & (~BITS_FW_DBG1)) #define BIT_GET_FW_DBG1(x) (((x) >> BIT_SHIFT_FW_DBG1) & BIT_MASK_FW_DBG1) #define BIT_SET_FW_DBG1(x, v) (BIT_CLEAR_FW_DBG1(x) | BIT_FW_DBG1(v)) /* 2 REG_FW_DBG2 (Offset 0x10E8) */ #define BIT_SHIFT_FW_DBG2 0 #define BIT_MASK_FW_DBG2 0xffffffffL #define BIT_FW_DBG2(x) (((x) & BIT_MASK_FW_DBG2) << BIT_SHIFT_FW_DBG2) #define BITS_FW_DBG2 (BIT_MASK_FW_DBG2 << BIT_SHIFT_FW_DBG2) #define BIT_CLEAR_FW_DBG2(x) ((x) & (~BITS_FW_DBG2)) #define BIT_GET_FW_DBG2(x) (((x) >> BIT_SHIFT_FW_DBG2) & BIT_MASK_FW_DBG2) #define BIT_SET_FW_DBG2(x, v) (BIT_CLEAR_FW_DBG2(x) | BIT_FW_DBG2(v)) /* 2 REG_FW_DBG3 (Offset 0x10EC) */ #define BIT_SHIFT_FW_DBG3 0 #define BIT_MASK_FW_DBG3 0xffffffffL #define BIT_FW_DBG3(x) (((x) & BIT_MASK_FW_DBG3) << BIT_SHIFT_FW_DBG3) #define BITS_FW_DBG3 (BIT_MASK_FW_DBG3 << BIT_SHIFT_FW_DBG3) #define BIT_CLEAR_FW_DBG3(x) ((x) & (~BITS_FW_DBG3)) #define BIT_GET_FW_DBG3(x) (((x) >> BIT_SHIFT_FW_DBG3) & BIT_MASK_FW_DBG3) #define BIT_SET_FW_DBG3(x, v) (BIT_CLEAR_FW_DBG3(x) | BIT_FW_DBG3(v)) /* 2 REG_FW_DBG4 (Offset 0x10F0) */ #define BIT_SHIFT_FW_DBG4 0 #define BIT_MASK_FW_DBG4 0xffffffffL #define BIT_FW_DBG4(x) (((x) & BIT_MASK_FW_DBG4) << BIT_SHIFT_FW_DBG4) #define BITS_FW_DBG4 (BIT_MASK_FW_DBG4 << BIT_SHIFT_FW_DBG4) #define BIT_CLEAR_FW_DBG4(x) ((x) & (~BITS_FW_DBG4)) #define BIT_GET_FW_DBG4(x) (((x) >> BIT_SHIFT_FW_DBG4) & BIT_MASK_FW_DBG4) #define BIT_SET_FW_DBG4(x, v) (BIT_CLEAR_FW_DBG4(x) | BIT_FW_DBG4(v)) /* 2 REG_FW_DBG5 (Offset 0x10F4) */ #define BIT_SHIFT_FW_DBG5 0 #define BIT_MASK_FW_DBG5 0xffffffffL #define BIT_FW_DBG5(x) (((x) & BIT_MASK_FW_DBG5) << BIT_SHIFT_FW_DBG5) #define BITS_FW_DBG5 (BIT_MASK_FW_DBG5 << BIT_SHIFT_FW_DBG5) #define BIT_CLEAR_FW_DBG5(x) ((x) & (~BITS_FW_DBG5)) #define BIT_GET_FW_DBG5(x) (((x) >> BIT_SHIFT_FW_DBG5) & BIT_MASK_FW_DBG5) #define BIT_SET_FW_DBG5(x, v) (BIT_CLEAR_FW_DBG5(x) | BIT_FW_DBG5(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FW_DBG6 (Offset 0x10F8) */ #define BIT_SHIFT_FW_DBG6 0 #define BIT_MASK_FW_DBG6 0xffffffffL #define BIT_FW_DBG6(x) (((x) & BIT_MASK_FW_DBG6) << BIT_SHIFT_FW_DBG6) #define BITS_FW_DBG6 (BIT_MASK_FW_DBG6 << BIT_SHIFT_FW_DBG6) #define BIT_CLEAR_FW_DBG6(x) ((x) & (~BITS_FW_DBG6)) #define BIT_GET_FW_DBG6(x) (((x) >> BIT_SHIFT_FW_DBG6) & BIT_MASK_FW_DBG6) #define BIT_SET_FW_DBG6(x, v) (BIT_CLEAR_FW_DBG6(x) | BIT_FW_DBG6(v)) /* 2 REG_FW_DBG7 (Offset 0x10FC) */ #define BIT_SHIFT_FW_DBG7 0 #define BIT_MASK_FW_DBG7 0xffffffffL #define BIT_FW_DBG7(x) (((x) & BIT_MASK_FW_DBG7) << BIT_SHIFT_FW_DBG7) #define BITS_FW_DBG7 (BIT_MASK_FW_DBG7 << BIT_SHIFT_FW_DBG7) #define BIT_CLEAR_FW_DBG7(x) ((x) & (~BITS_FW_DBG7)) #define BIT_GET_FW_DBG7(x) (((x) >> BIT_SHIFT_FW_DBG7) & BIT_MASK_FW_DBG7) #define BIT_SET_FW_DBG7(x, v) (BIT_CLEAR_FW_DBG7(x) | BIT_FW_DBG7(v)) /* 2 REG_CR_EXT (Offset 0x1100) */ #define BIT_SHIFT_PHY_REQ_DELAY 24 #define BIT_MASK_PHY_REQ_DELAY 0xf #define BIT_PHY_REQ_DELAY(x) \ (((x) & BIT_MASK_PHY_REQ_DELAY) << BIT_SHIFT_PHY_REQ_DELAY) #define BITS_PHY_REQ_DELAY (BIT_MASK_PHY_REQ_DELAY << BIT_SHIFT_PHY_REQ_DELAY) #define BIT_CLEAR_PHY_REQ_DELAY(x) ((x) & (~BITS_PHY_REQ_DELAY)) #define BIT_GET_PHY_REQ_DELAY(x) \ (((x) >> BIT_SHIFT_PHY_REQ_DELAY) & BIT_MASK_PHY_REQ_DELAY) #define BIT_SET_PHY_REQ_DELAY(x, v) \ (BIT_CLEAR_PHY_REQ_DELAY(x) | BIT_PHY_REQ_DELAY(v)) #define BIT_SPD_DOWN BIT(16) #define BIT_SHIFT_NETYPE4 4 #define BIT_MASK_NETYPE4 0x3 #define BIT_NETYPE4(x) (((x) & BIT_MASK_NETYPE4) << BIT_SHIFT_NETYPE4) #define BITS_NETYPE4 (BIT_MASK_NETYPE4 << BIT_SHIFT_NETYPE4) #define BIT_CLEAR_NETYPE4(x) ((x) & (~BITS_NETYPE4)) #define BIT_GET_NETYPE4(x) (((x) >> BIT_SHIFT_NETYPE4) & BIT_MASK_NETYPE4) #define BIT_SET_NETYPE4(x, v) (BIT_CLEAR_NETYPE4(x) | BIT_NETYPE4(v)) #define BIT_SHIFT_NETYPE3 2 #define BIT_MASK_NETYPE3 0x3 #define BIT_NETYPE3(x) (((x) & BIT_MASK_NETYPE3) << BIT_SHIFT_NETYPE3) #define BITS_NETYPE3 (BIT_MASK_NETYPE3 << BIT_SHIFT_NETYPE3) #define BIT_CLEAR_NETYPE3(x) ((x) & (~BITS_NETYPE3)) #define BIT_GET_NETYPE3(x) (((x) >> BIT_SHIFT_NETYPE3) & BIT_MASK_NETYPE3) #define BIT_SET_NETYPE3(x, v) (BIT_CLEAR_NETYPE3(x) | BIT_NETYPE3(v)) #define BIT_SHIFT_NETYPE2 0 #define BIT_MASK_NETYPE2 0x3 #define BIT_NETYPE2(x) (((x) & BIT_MASK_NETYPE2) << BIT_SHIFT_NETYPE2) #define BITS_NETYPE2 (BIT_MASK_NETYPE2 << BIT_SHIFT_NETYPE2) #define BIT_CLEAR_NETYPE2(x) ((x) & (~BITS_NETYPE2)) #define BIT_GET_NETYPE2(x) (((x) >> BIT_SHIFT_NETYPE2) & BIT_MASK_NETYPE2) #define BIT_SET_NETYPE2(x, v) (BIT_CLEAR_NETYPE2(x) | BIT_NETYPE2(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TC9_CTRL (Offset 0x1104) */ #define BIT_TC9INT_EN BIT(26) #define BIT_TC9MODE BIT(25) #define BIT_TC9EN BIT(24) #define BIT_SHIFT_TC9DATA 0 #define BIT_MASK_TC9DATA 0xffffff #define BIT_TC9DATA(x) (((x) & BIT_MASK_TC9DATA) << BIT_SHIFT_TC9DATA) #define BITS_TC9DATA (BIT_MASK_TC9DATA << BIT_SHIFT_TC9DATA) #define BIT_CLEAR_TC9DATA(x) ((x) & (~BITS_TC9DATA)) #define BIT_GET_TC9DATA(x) (((x) >> BIT_SHIFT_TC9DATA) & BIT_MASK_TC9DATA) #define BIT_SET_TC9DATA(x, v) (BIT_CLEAR_TC9DATA(x) | BIT_TC9DATA(v)) /* 2 REG_TC10_CTRL (Offset 0x1108) */ #define BIT_TC10INT_EN BIT(26) #define BIT_TC10MODE BIT(25) #define BIT_TC10EN BIT(24) #define BIT_SHIFT_TC10DATA 0 #define BIT_MASK_TC10DATA 0xffffff #define BIT_TC10DATA(x) (((x) & BIT_MASK_TC10DATA) << BIT_SHIFT_TC10DATA) #define BITS_TC10DATA (BIT_MASK_TC10DATA << BIT_SHIFT_TC10DATA) #define BIT_CLEAR_TC10DATA(x) ((x) & (~BITS_TC10DATA)) #define BIT_GET_TC10DATA(x) (((x) >> BIT_SHIFT_TC10DATA) & BIT_MASK_TC10DATA) #define BIT_SET_TC10DATA(x, v) (BIT_CLEAR_TC10DATA(x) | BIT_TC10DATA(v)) /* 2 REG_TC11_CTRL (Offset 0x110C) */ #define BIT_TC11INT_EN BIT(26) #define BIT_TC11MODE BIT(25) #define BIT_TC11EN BIT(24) #define BIT_SHIFT_TC11DATA 0 #define BIT_MASK_TC11DATA 0xffffff #define BIT_TC11DATA(x) (((x) & BIT_MASK_TC11DATA) << BIT_SHIFT_TC11DATA) #define BITS_TC11DATA (BIT_MASK_TC11DATA << BIT_SHIFT_TC11DATA) #define BIT_CLEAR_TC11DATA(x) ((x) & (~BITS_TC11DATA)) #define BIT_GET_TC11DATA(x) (((x) >> BIT_SHIFT_TC11DATA) & BIT_MASK_TC11DATA) #define BIT_SET_TC11DATA(x, v) (BIT_CLEAR_TC11DATA(x) | BIT_TC11DATA(v)) /* 2 REG_TC12_CTRL (Offset 0x1110) */ #define BIT_TC12INT_EN BIT(26) #define BIT_TC12MODE BIT(25) #define BIT_TC12EN BIT(24) #define BIT_P2P_PWROFF_NOA2_ERLY_INT BIT(22) #define BIT_P2P_PWROFF_NOA1_ERLY_INT BIT(21) #define BIT_P2P_PWROFF_NOA0_ERLY_INT BIT(20) #define BIT_SHIFT_TC12DATA 0 #define BIT_MASK_TC12DATA 0xffffff #define BIT_TC12DATA(x) (((x) & BIT_MASK_TC12DATA) << BIT_SHIFT_TC12DATA) #define BITS_TC12DATA (BIT_MASK_TC12DATA << BIT_SHIFT_TC12DATA) #define BIT_CLEAR_TC12DATA(x) ((x) & (~BITS_TC12DATA)) #define BIT_GET_TC12DATA(x) (((x) >> BIT_SHIFT_TC12DATA) & BIT_MASK_TC12DATA) #define BIT_SET_TC12DATA(x, v) (BIT_CLEAR_TC12DATA(x) | BIT_TC12DATA(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT) /* 2 REG_FWFF (Offset 0x1114) */ #define BIT_SHIFT_PKTNUM_TH 24 #define BIT_MASK_PKTNUM_TH 0xff #define BIT_PKTNUM_TH(x) (((x) & BIT_MASK_PKTNUM_TH) << BIT_SHIFT_PKTNUM_TH) #define BITS_PKTNUM_TH (BIT_MASK_PKTNUM_TH << BIT_SHIFT_PKTNUM_TH) #define BIT_CLEAR_PKTNUM_TH(x) ((x) & (~BITS_PKTNUM_TH)) #define BIT_GET_PKTNUM_TH(x) (((x) >> BIT_SHIFT_PKTNUM_TH) & BIT_MASK_PKTNUM_TH) #define BIT_SET_PKTNUM_TH(x, v) (BIT_CLEAR_PKTNUM_TH(x) | BIT_PKTNUM_TH(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FWFF (Offset 0x1114) */ #define BIT_SHIFT_PKTNUM_TH_V1 24 #define BIT_MASK_PKTNUM_TH_V1 0xff #define BIT_PKTNUM_TH_V1(x) \ (((x) & BIT_MASK_PKTNUM_TH_V1) << BIT_SHIFT_PKTNUM_TH_V1) #define BITS_PKTNUM_TH_V1 (BIT_MASK_PKTNUM_TH_V1 << BIT_SHIFT_PKTNUM_TH_V1) #define BIT_CLEAR_PKTNUM_TH_V1(x) ((x) & (~BITS_PKTNUM_TH_V1)) #define BIT_GET_PKTNUM_TH_V1(x) \ (((x) >> BIT_SHIFT_PKTNUM_TH_V1) & BIT_MASK_PKTNUM_TH_V1) #define BIT_SET_PKTNUM_TH_V1(x, v) \ (BIT_CLEAR_PKTNUM_TH_V1(x) | BIT_PKTNUM_TH_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWFF (Offset 0x1114) */ #define BIT_SHIFT_TIMER_TH 16 #define BIT_MASK_TIMER_TH 0xff #define BIT_TIMER_TH(x) (((x) & BIT_MASK_TIMER_TH) << BIT_SHIFT_TIMER_TH) #define BITS_TIMER_TH (BIT_MASK_TIMER_TH << BIT_SHIFT_TIMER_TH) #define BIT_CLEAR_TIMER_TH(x) ((x) & (~BITS_TIMER_TH)) #define BIT_GET_TIMER_TH(x) (((x) >> BIT_SHIFT_TIMER_TH) & BIT_MASK_TIMER_TH) #define BIT_SET_TIMER_TH(x, v) (BIT_CLEAR_TIMER_TH(x) | BIT_TIMER_TH(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT) /* 2 REG_FWFF (Offset 0x1114) */ #define BIT_EN_RXDMA_ALIGN_V1 BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FWFF (Offset 0x1114) */ #define BIT_SHIFT_RXPKT1ENADDR 0 #define BIT_MASK_RXPKT1ENADDR 0xffff #define BIT_RXPKT1ENADDR(x) \ (((x) & BIT_MASK_RXPKT1ENADDR) << BIT_SHIFT_RXPKT1ENADDR) #define BITS_RXPKT1ENADDR (BIT_MASK_RXPKT1ENADDR << BIT_SHIFT_RXPKT1ENADDR) #define BIT_CLEAR_RXPKT1ENADDR(x) ((x) & (~BITS_RXPKT1ENADDR)) #define BIT_GET_RXPKT1ENADDR(x) \ (((x) >> BIT_SHIFT_RXPKT1ENADDR) & BIT_MASK_RXPKT1ENADDR) #define BIT_SET_RXPKT1ENADDR(x, v) \ (BIT_CLEAR_RXPKT1ENADDR(x) | BIT_RXPKT1ENADDR(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT) /* 2 REG_FWFF (Offset 0x1114) */ #define BIT_EN_TXDMA_ALIGN_V1 BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE2IMR (Offset 0x1120) */ #define BIT__FE4ISR__IND_MSK BIT(29) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE2IMR (Offset 0x1120) */ #define BIT_FS_TXSC_DESC_DONE_INT_EN BIT(28) #define BIT_FS_TXSC_BKDONE_INT_EN BIT(27) #define BIT_FS_TXSC_BEDONE_INT_EN BIT(26) #define BIT_FS_TXSC_VIDONE_INT_EN BIT(25) #define BIT_FS_TXSC_VODONE_INT_EN BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE2IMR (Offset 0x1120) */ #define BIT_FS_ATIM_MB7_INT_EN BIT(23) #define BIT_FS_ATIM_MB6_INT_EN BIT(22) #define BIT_FS_ATIM_MB5_INT_EN BIT(21) #define BIT_FS_ATIM_MB4_INT_EN BIT(20) #define BIT_FS_ATIM_MB3_INT_EN BIT(19) #define BIT_FS_ATIM_MB2_INT_EN BIT(18) #define BIT_FS_ATIM_MB1_INT_EN BIT(17) #define BIT_FS_ATIM_MB0_INT_EN BIT(16) #define BIT_FS_TBTT4INT_EN BIT(11) #define BIT_FS_TBTT3INT_EN BIT(10) #define BIT_FS_TBTT2INT_EN BIT(9) #define BIT_FS_TBTT1INT_EN BIT(8) #define BIT_FS_TBTT0_MB7INT_EN BIT(7) #define BIT_FS_TBTT0_MB6INT_EN BIT(6) #define BIT_FS_TBTT0_MB5INT_EN BIT(5) #define BIT_FS_TBTT0_MB4INT_EN BIT(4) #define BIT_FS_TBTT0_MB3INT_EN BIT(3) #define BIT_FS_TBTT0_MB2INT_EN BIT(2) #define BIT_FS_TBTT0_MB1INT_EN BIT(1) #define BIT_FS_TBTT0_INT_EN BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE2ISR (Offset 0x1124) */ #define BIT__FE4ISR__IND_INT BIT(29) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE2ISR (Offset 0x1124) */ #define BIT_FS_TXSC_DESC_DONE_INT BIT(28) #define BIT_FS_TXSC_BKDONE_INT BIT(27) #define BIT_FS_TXSC_BEDONE_INT BIT(26) #define BIT_FS_TXSC_VIDONE_INT BIT(25) #define BIT_FS_TXSC_VODONE_INT BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE2ISR (Offset 0x1124) */ #define BIT_FS_ATIM_MB7_INT BIT(23) #define BIT_FS_ATIM_MB6_INT BIT(22) #define BIT_FS_ATIM_MB5_INT BIT(21) #define BIT_FS_ATIM_MB4_INT BIT(20) #define BIT_FS_ATIM_MB3_INT BIT(19) #define BIT_FS_ATIM_MB2_INT BIT(18) #define BIT_FS_ATIM_MB1_INT BIT(17) #define BIT_FS_ATIM_MB0_INT BIT(16) #define BIT_FS_TBTT4INT BIT(11) #define BIT_FS_TBTT3INT BIT(10) #define BIT_FS_TBTT2INT BIT(9) #define BIT_FS_TBTT1INT BIT(8) #define BIT_FS_TBTT0_MB7INT BIT(7) #define BIT_FS_TBTT0_MB6INT BIT(6) #define BIT_FS_TBTT0_MB5INT BIT(5) #define BIT_FS_TBTT0_MB4INT BIT(4) #define BIT_FS_TBTT0_MB3INT BIT(3) #define BIT_FS_TBTT0_MB2INT BIT(2) #define BIT_FS_TBTT0_MB1INT BIT(1) #define BIT_FS_TBTT0_INT BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE3IMR (Offset 0x1128) */ #define BIT_FS_BCNELY4_AGGR_INT_EN BIT(31) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE3IMR (Offset 0x1128) */ #define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN BIT(31) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE3IMR (Offset 0x1128) */ #define BIT_FS_BCNELY3_AGGR_INT_EN BIT(30) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE3IMR (Offset 0x1128) */ #define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN BIT(30) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE3IMR (Offset 0x1128) */ #define BIT_FS_BCNELY2_AGGR_INT_EN BIT(29) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE3IMR (Offset 0x1128) */ #define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN BIT(29) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE3IMR (Offset 0x1128) */ #define BIT_FS_BCNELY1_AGGR_INT_EN BIT(28) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE3IMR (Offset 0x1128) */ #define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN BIT(28) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE3IMR (Offset 0x1128) */ #define BIT_FS_BCNDMA4_INT_EN BIT(27) #define BIT_FS_BCNDMA3_INT_EN BIT(26) #define BIT_FS_BCNDMA2_INT_EN BIT(25) #define BIT_FS_BCNDMA1_INT_EN BIT(24) #define BIT_FS_BCNDMA0_MB7_INT_EN BIT(23) #define BIT_FS_BCNDMA0_MB6_INT_EN BIT(22) #define BIT_FS_BCNDMA0_MB5_INT_EN BIT(21) #define BIT_FS_BCNDMA0_MB4_INT_EN BIT(20) #define BIT_FS_BCNDMA0_MB3_INT_EN BIT(19) #define BIT_FS_BCNDMA0_MB2_INT_EN BIT(18) #define BIT_FS_BCNDMA0_MB1_INT_EN BIT(17) #define BIT_FS_BCNDMA0_INT_EN BIT(16) #define BIT_FS_MTI_BCNIVLEAR_INT__EN BIT(15) #define BIT_FS_BCNERLY4_INT_EN BIT(11) #define BIT_FS_BCNERLY3_INT_EN BIT(10) #define BIT_FS_BCNERLY2_INT_EN BIT(9) #define BIT_FS_BCNERLY1_INT_EN BIT(8) #define BIT_FS_BCNERLY0_MB7INT_EN BIT(7) #define BIT_FS_BCNERLY0_MB6INT_EN BIT(6) #define BIT_FS_BCNERLY0_MB5INT_EN BIT(5) #define BIT_FS_BCNERLY0_MB4INT_EN BIT(4) #define BIT_FS_BCNERLY0_MB3INT_EN BIT(3) #define BIT_FS_BCNERLY0_MB2INT_EN BIT(2) #define BIT_FS_BCNERLY0_MB1INT_EN BIT(1) #define BIT_FS_BCNERLY0_INT_EN BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE3ISR (Offset 0x112C) */ #define BIT_FS_BCNELY4_AGGR_INT BIT(31) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE3ISR (Offset 0x112C) */ #define BIT_FS_CLI3_MTI_BCNIVLEAR_INT BIT(31) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE3ISR (Offset 0x112C) */ #define BIT_FS_BCNELY3_AGGR_INT BIT(30) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE3ISR (Offset 0x112C) */ #define BIT_FS_CLI2_MTI_BCNIVLEAR_INT BIT(30) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE3ISR (Offset 0x112C) */ #define BIT_FS_BCNELY2_AGGR_INT BIT(29) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE3ISR (Offset 0x112C) */ #define BIT_FS_CLI1_MTI_BCNIVLEAR_INT BIT(29) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE3ISR (Offset 0x112C) */ #define BIT_FS_BCNELY1_AGGR_INT BIT(28) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE3ISR (Offset 0x112C) */ #define BIT_FS_CLI0_MTI_BCNIVLEAR_INT BIT(28) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FE3ISR (Offset 0x112C) */ #define BIT_FS_BCNDMA4_INT BIT(27) #define BIT_FS_BCNDMA3_INT BIT(26) #define BIT_FS_BCNDMA2_INT BIT(25) #define BIT_FS_BCNDMA1_INT BIT(24) #define BIT_FS_BCNDMA0_MB7_INT BIT(23) #define BIT_FS_BCNDMA0_MB6_INT BIT(22) #define BIT_FS_BCNDMA0_MB5_INT BIT(21) #define BIT_FS_BCNDMA0_MB4_INT BIT(20) #define BIT_FS_BCNDMA0_MB3_INT BIT(19) #define BIT_FS_BCNDMA0_MB2_INT BIT(18) #define BIT_FS_BCNDMA0_MB1_INT BIT(17) #define BIT_FS_BCNDMA0_INT BIT(16) #define BIT_FS_MTI_BCNIVLEAR_INT BIT(15) #define BIT_FS_BCNERLY4_INT BIT(11) #define BIT_FS_BCNERLY3_INT BIT(10) #define BIT_FS_BCNERLY2_INT BIT(9) #define BIT_FS_BCNERLY1_INT BIT(8) #define BIT_FS_BCNERLY0_MB7INT BIT(7) #define BIT_FS_BCNERLY0_MB6INT BIT(6) #define BIT_FS_BCNERLY0_MB5INT BIT(5) #define BIT_FS_BCNERLY0_MB4INT BIT(4) #define BIT_FS_BCNERLY0_MB3INT BIT(3) #define BIT_FS_BCNERLY0_MB2INT BIT(2) #define BIT_FS_BCNERLY0_MB1INT BIT(1) #define BIT_FS_BCNERLY0_INT BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT4_PKTIN_INT_EN BIT(19) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI3_TXPKTIN_INT_EN BIT(19) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT3_PKTIN_INT_EN BIT(18) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI2_TXPKTIN_INT_EN BIT(18) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT2_PKTIN_INT_EN BIT(17) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI1_TXPKTIN_INT_EN BIT(17) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT1_PKTIN_INT_EN BIT(16) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI0_TXPKTIN_INT_EN BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT4_RXUCMD0_OK_INT_EN BIT(15) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI3_RX_UMD0_INT_EN BIT(15) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT4_RXUCMD1_OK_INT_EN BIT(14) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI3_RX_UMD1_INT_EN BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT4_RXBCMD0_OK_INT_EN BIT(13) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI3_RX_BMD0_INT_EN BIT(13) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT4_RXBCMD1_OK_INT_EN BIT(12) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI3_RX_BMD1_INT_EN BIT(12) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT3_RXUCMD0_OK_INT_EN BIT(11) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI2_RX_UMD0_INT_EN BIT(11) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT3_RXUCMD1_OK_INT_EN BIT(10) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI2_RX_UMD1_INT_EN BIT(10) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT3_RXBCMD0_OK_INT_EN BIT(9) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI2_RX_BMD0_INT_EN BIT(9) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT3_RXBCMD1_OK_INT_EN BIT(8) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI2_RX_BMD1_INT_EN BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT2_RXUCMD0_OK_INT_EN BIT(7) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI1_RX_UMD0_INT_EN BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT2_RXUCMD1_OK_INT_EN BIT(6) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI1_RX_UMD1_INT_EN BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT2_RXBCMD0_OK_INT_EN BIT(5) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI1_RX_BMD0_INT_EN BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT2_RXBCMD1_OK_INT_EN BIT(4) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI1_RX_BMD1_INT_EN BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT1_RXUCMD0_OK_INT_EN BIT(3) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI0_RX_UMD0_INT_EN BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT1_RXUCMD1_OK_INT_EN BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_DMEM1_WPTR_UPDATE_INT_EN BIT(2) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI0_RX_UMD1_INT_EN BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT1_RXBCMD0_OK_INT_EN BIT(1) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI0_RX_BMD0_INT_EN BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_PORT1_RXBCMD1_OK_INT_EN BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4IMR (Offset 0x1130) */ #define BIT_FS_CLI0_RX_BMD1_INT_EN BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT4_PKTIN_INT BIT(19) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI3_TXPKTIN_INT BIT(19) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT3_PKTIN_INT BIT(18) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI2_TXPKTIN_INT BIT(18) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT2_PKTIN_INT BIT(17) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI1_TXPKTIN_INT BIT(17) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT1_PKTIN_INT BIT(16) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI0_TXPKTIN_INT BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT4_RXUCMD0_OK_INT BIT(15) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI3_RX_UMD0_INT BIT(15) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT4_RXUCMD1_OK_INT BIT(14) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI3_RX_UMD1_INT BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT4_RXBCMD0_OK_INT BIT(13) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI3_RX_BMD0_INT BIT(13) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT4_RXBCMD1_OK_INT BIT(12) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI3_RX_BMD1_INT BIT(12) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT3_RXUCMD0_OK_INT BIT(11) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI2_RX_UMD0_INT BIT(11) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT3_RXUCMD1_OK_INT BIT(10) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI2_RX_UMD1_INT BIT(10) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT3_RXBCMD0_OK_INT BIT(9) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI2_RX_BMD0_INT BIT(9) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT3_RXBCMD1_OK_INT BIT(8) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI2_RX_BMD1_INT BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT2_RXUCMD0_OK_INT BIT(7) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI1_RX_UMD0_INT BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT2_RXUCMD1_OK_INT BIT(6) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI1_RX_UMD1_INT BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT2_RXBCMD0_OK_INT BIT(5) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI1_RX_BMD0_INT BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT2_RXBCMD1_OK_INT BIT(4) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI1_RX_BMD1_INT BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT1_RXUCMD0_OK_INT BIT(3) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI0_RX_UMD0_INT BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT1_RXUCMD1_OK_INT BIT(2) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_DMEM1_WPTR_UPDATE_INT BIT(2) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI0_RX_UMD1_INT BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT1_RXBCMD0_OK_INT BIT(1) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI0_RX_BMD0_INT BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_PORT1_RXBCMD1_OK_INT BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FE4ISR (Offset 0x1134) */ #define BIT_FS_CLI0_RX_BMD1_INT BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FT1IMR (Offset 0x1138) */ #define BIT__FT2ISR__IND_MSK BIT(30) #define BIT_FTM_PTT_INT_EN BIT(29) #define BIT_RXFTMREQ_INT_EN BIT(28) #define BIT_RXFTM_INT_EN BIT(27) #define BIT_TXFTM_INT_EN BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT1IMR (Offset 0x1138) */ #define BIT_FS_H2C_CMD_OK_INT_EN BIT(25) #define BIT_FS_H2C_CMD_FULL_INT_EN BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT1IMR (Offset 0x1138) */ #define BIT_FS_MACID_PWRCHANGE5_INT_EN BIT(23) #define BIT_FS_MACID_PWRCHANGE4_INT_EN BIT(22) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FT1IMR (Offset 0x1138) */ #define BIT_FS_MACID_SEARCH_FAIL_INT_EN BIT(22) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FT1IMR (Offset 0x1138) */ #define BIT_FS_MACID_PWRCHANGE3_INT_EN BIT(21) #define BIT_FS_MACID_PWRCHANGE2_INT_EN BIT(20) #define BIT_FS_MACID_PWRCHANGE1_INT_EN BIT(19) #define BIT_FS_MACID_PWRCHANGE0_INT_EN BIT(18) #define BIT_FS_CTWEND2_INT_EN BIT(17) #define BIT_FS_CTWEND1_INT_EN BIT(16) #define BIT_FS_CTWEND0_INT_EN BIT(15) #define BIT_FS_TX_NULL1_INT_EN BIT(14) #define BIT_FS_TX_NULL0_INT_EN BIT(13) #define BIT_FS_TSF_BIT32_TOGGLE_EN BIT(12) #define BIT_FS_P2P_RFON2_INT_EN BIT(11) #define BIT_FS_P2P_RFOFF2_INT_EN BIT(10) #define BIT_FS_P2P_RFON1_INT_EN BIT(9) #define BIT_FS_P2P_RFOFF1_INT_EN BIT(8) #define BIT_FS_P2P_RFON0_INT_EN BIT(7) #define BIT_FS_P2P_RFOFF0_INT_EN BIT(6) #define BIT_FS_RX_UAPSDMD1_EN BIT(5) #define BIT_FS_RX_UAPSDMD0_EN BIT(4) #define BIT_FS_TRIGGER_PKT_EN BIT(3) #define BIT_FS_EOSP_INT_EN BIT(2) #define BIT_FS_RPWM2_INT_EN BIT(1) #define BIT_FS_RPWM_INT_EN BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT__FT2ISR__IND_INT BIT(30) #define BIT_FTM_PTT_INT BIT(29) #define BIT_RXFTMREQ_INT BIT(28) #define BIT_RXFTM_INT BIT(27) #define BIT_TXFTM_INT BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_H2C_CMD_OK_INT BIT(25) #define BIT_FS_H2C_CMD_FULL_INT BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_MACID_PWRCHANGE5_INT BIT(23) #define BIT_FS_MACID_PWRCHANGE4_INT BIT(22) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_MACID_SEARCH_FAIL_INT BIT(22) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_MACID_PWRCHANGE3_INT BIT(21) #define BIT_FS_MACID_PWRCHANGE2_INT BIT(20) #define BIT_FS_MACID_PWRCHANGE1_INT BIT(19) #define BIT_FS_MACID_PWRCHANGE0_INT BIT(18) #define BIT_FS_CTWEND2_INT BIT(17) #define BIT_FS_CTWEND1_INT BIT(16) #define BIT_FS_CTWEND0_INT BIT(15) #define BIT_FS_TX_NULL1_INT BIT(14) #define BIT_FS_TX_NULL0_INT BIT(13) #define BIT_FS_TSF_BIT32_TOGGLE_INT BIT(12) #define BIT_FS_P2P_RFON2_INT BIT(11) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_TXBCNOK_PORT4_INT_EN BIT(11) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_P2P_RFOFF2_INT BIT(10) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_TXBCNOK_PORT3_INT_EN BIT(10) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_P2P_RFON1_INT BIT(9) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_TXBCNOK_PORT2_INT_EN BIT(9) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_P2P_RFOFF1_INT BIT(8) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_TXBCNOK_PORT1_INT_EN BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_P2P_RFON0_INT BIT(7) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_TXBCNERR_PORT4_INT_EN BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_P2P_RFOFF0_INT BIT(6) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_TXBCNERR_PORT3_INT_EN BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_RX_UAPSDMD1_INT BIT(5) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_TXBCNERR_PORT2_INT_EN BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_RX_UAPSDMD0_INT BIT(4) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_TXBCNERR_PORT1_INT_EN BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_TRIGGER_PKT_INT BIT(3) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_ATIM_PORT4_INT_EN BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_EOSP_INT BIT(2) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_ATIM_PORT3_INT_EN BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_RPWM2_INT BIT(1) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_ATIM_PORT2_INT_EN BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_RPWM_INT BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FT1ISR (Offset 0x113C) */ #define BIT_FS_ATIM_PORT1_INT_EN BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SPWR0 (Offset 0x1140) */ #define BIT_SHIFT_MID_31TO0 0 #define BIT_MASK_MID_31TO0 0xffffffffL #define BIT_MID_31TO0(x) (((x) & BIT_MASK_MID_31TO0) << BIT_SHIFT_MID_31TO0) #define BITS_MID_31TO0 (BIT_MASK_MID_31TO0 << BIT_SHIFT_MID_31TO0) #define BIT_CLEAR_MID_31TO0(x) ((x) & (~BITS_MID_31TO0)) #define BIT_GET_MID_31TO0(x) (((x) >> BIT_SHIFT_MID_31TO0) & BIT_MASK_MID_31TO0) #define BIT_SET_MID_31TO0(x, v) (BIT_CLEAR_MID_31TO0(x) | BIT_MID_31TO0(v)) /* 2 REG_SPWR1 (Offset 0x1144) */ #define BIT_SHIFT_MID_63TO32 0 #define BIT_MASK_MID_63TO32 0xffffffffL #define BIT_MID_63TO32(x) (((x) & BIT_MASK_MID_63TO32) << BIT_SHIFT_MID_63TO32) #define BITS_MID_63TO32 (BIT_MASK_MID_63TO32 << BIT_SHIFT_MID_63TO32) #define BIT_CLEAR_MID_63TO32(x) ((x) & (~BITS_MID_63TO32)) #define BIT_GET_MID_63TO32(x) \ (((x) >> BIT_SHIFT_MID_63TO32) & BIT_MASK_MID_63TO32) #define BIT_SET_MID_63TO32(x, v) (BIT_CLEAR_MID_63TO32(x) | BIT_MID_63TO32(v)) /* 2 REG_SPWR2 (Offset 0x1148) */ #define BIT_SHIFT_MID_95O64 0 #define BIT_MASK_MID_95O64 0xffffffffL #define BIT_MID_95O64(x) (((x) & BIT_MASK_MID_95O64) << BIT_SHIFT_MID_95O64) #define BITS_MID_95O64 (BIT_MASK_MID_95O64 << BIT_SHIFT_MID_95O64) #define BIT_CLEAR_MID_95O64(x) ((x) & (~BITS_MID_95O64)) #define BIT_GET_MID_95O64(x) (((x) >> BIT_SHIFT_MID_95O64) & BIT_MASK_MID_95O64) #define BIT_SET_MID_95O64(x, v) (BIT_CLEAR_MID_95O64(x) | BIT_MID_95O64(v)) /* 2 REG_SPWR3 (Offset 0x114C) */ #define BIT_SHIFT_MID_127TO96 0 #define BIT_MASK_MID_127TO96 0xffffffffL #define BIT_MID_127TO96(x) \ (((x) & BIT_MASK_MID_127TO96) << BIT_SHIFT_MID_127TO96) #define BITS_MID_127TO96 (BIT_MASK_MID_127TO96 << BIT_SHIFT_MID_127TO96) #define BIT_CLEAR_MID_127TO96(x) ((x) & (~BITS_MID_127TO96)) #define BIT_GET_MID_127TO96(x) \ (((x) >> BIT_SHIFT_MID_127TO96) & BIT_MASK_MID_127TO96) #define BIT_SET_MID_127TO96(x, v) \ (BIT_CLEAR_MID_127TO96(x) | BIT_MID_127TO96(v)) /* 2 REG_POWSEQ (Offset 0x1150) */ #define BIT_SHIFT_SEQNUM_MID 16 #define BIT_MASK_SEQNUM_MID 0xffff #define BIT_SEQNUM_MID(x) (((x) & BIT_MASK_SEQNUM_MID) << BIT_SHIFT_SEQNUM_MID) #define BITS_SEQNUM_MID (BIT_MASK_SEQNUM_MID << BIT_SHIFT_SEQNUM_MID) #define BIT_CLEAR_SEQNUM_MID(x) ((x) & (~BITS_SEQNUM_MID)) #define BIT_GET_SEQNUM_MID(x) \ (((x) >> BIT_SHIFT_SEQNUM_MID) & BIT_MASK_SEQNUM_MID) #define BIT_SET_SEQNUM_MID(x, v) (BIT_CLEAR_SEQNUM_MID(x) | BIT_SEQNUM_MID(v)) #define BIT_SHIFT_REF_MID 0 #define BIT_MASK_REF_MID 0x7f #define BIT_REF_MID(x) (((x) & BIT_MASK_REF_MID) << BIT_SHIFT_REF_MID) #define BITS_REF_MID (BIT_MASK_REF_MID << BIT_SHIFT_REF_MID) #define BIT_CLEAR_REF_MID(x) ((x) & (~BITS_REF_MID)) #define BIT_GET_REF_MID(x) (((x) >> BIT_SHIFT_REF_MID) & BIT_MASK_REF_MID) #define BIT_SET_REF_MID(x, v) (BIT_CLEAR_REF_MID(x) | BIT_REF_MID(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RX_BCN_TBTT_ITVL0 (Offset 0x1160) */ #define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2 24 #define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2 0xff #define BIT_RX_BCN_TBTT_ITVL_CLIENT2(x) \ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2) \ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2) #define BITS_RX_BCN_TBTT_ITVL_CLIENT2 \ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2 \ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2) #define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2(x) \ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2)) #define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2(x) \ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2) & \ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2) #define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2(x, v) \ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2(x) | \ BIT_RX_BCN_TBTT_ITVL_CLIENT2(v)) #define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1 16 #define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1 0xff #define BIT_RX_BCN_TBTT_ITVL_CLIENT1(x) \ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1) \ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1) #define BITS_RX_BCN_TBTT_ITVL_CLIENT1 \ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1 \ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1) #define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1(x) \ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1)) #define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1(x) \ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1) & \ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1) #define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1(x, v) \ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1(x) | \ BIT_RX_BCN_TBTT_ITVL_CLIENT1(v)) #define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0 8 #define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0 0xff #define BIT_RX_BCN_TBTT_ITVL_CLIENT0(x) \ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0) \ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0) #define BITS_RX_BCN_TBTT_ITVL_CLIENT0 \ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0 \ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0) #define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0(x) \ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0)) #define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0(x) \ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0) & \ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0) #define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0(x, v) \ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0(x) | \ BIT_RX_BCN_TBTT_ITVL_CLIENT0(v)) #define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0 0 #define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0 0xff #define BIT_RX_BCN_TBTT_ITVL_PORT0(x) \ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0) \ << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0) #define BITS_RX_BCN_TBTT_ITVL_PORT0 \ (BIT_MASK_RX_BCN_TBTT_ITVL_PORT0 << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0) #define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0(x) \ ((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0)) #define BIT_GET_RX_BCN_TBTT_ITVL_PORT0(x) \ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0) & \ BIT_MASK_RX_BCN_TBTT_ITVL_PORT0) #define BIT_SET_RX_BCN_TBTT_ITVL_PORT0(x, v) \ (BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0(x) | BIT_RX_BCN_TBTT_ITVL_PORT0(v)) /* 2 REG_RX_BCN_TBTT_ITVL1 (Offset 0x1164) */ #define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3 0 #define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3 0xff #define BIT_RX_BCN_TBTT_ITVL_CLIENT3(x) \ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3) \ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3) #define BITS_RX_BCN_TBTT_ITVL_CLIENT3 \ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3 \ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3) #define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3(x) \ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3)) #define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3(x) \ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3) & \ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3) #define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3(x, v) \ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3(x) | \ BIT_RX_BCN_TBTT_ITVL_CLIENT3(v)) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_FWIMR1 (Offset 0x1168) */ #define BIT_FS_ATIM_MB15_INT_EN BIT(31) #define BIT_FS_ATIM_MB14_INT_EN BIT(30) #define BIT_FS_ATIM_MB13_INT_EN BIT(29) #define BIT_FS_ATIM_MB12_INT_EN BIT(28) #define BIT_FS_ATIM_MB11_INT_EN BIT(27) #define BIT_FS_ATIM_MB10_INT_EN BIT(26) #define BIT_FS_ATIM_MB9_INT_EN BIT(25) #define BIT_FS_ATIM_MB8_INT_EN BIT(24) #define BIT_FS_TXBCNERR_MB15_INT_EN BIT(23) #define BIT_FS_TXBCNERR_MB14_INT_EN BIT(22) #define BIT_FS_TXBCNERR_MB13_INT_EN BIT(21) #define BIT_FS_TXBCNERR_MB12_INT_EN BIT(20) #define BIT_FS_TXBCNERR_MB11_INT_EN BIT(19) #define BIT_FS_TXBCNERR_MB10_INT_EN BIT(18) #define BIT_FS_TXBCNERR_MB9_INT_EN BIT(17) #define BIT_FS_TXBCNERR_MB8_INT_EN BIT(16) #define BIT_FS_TXBCNOK_MB15_INT_EN BIT(15) #define BIT_FS_TXBCNOK_MB14_INT_EN BIT(14) #define BIT_FS_TXBCNOK_MB13_INT_EN BIT(13) #define BIT_FS_TXBCNOK_MB12_INT_EN BIT(12) #define BIT_FS_TXBCNOK_MB11_INT_EN BIT(11) #define BIT_FS_TXBCNOK_MB10_INT_EN BIT(10) #define BIT_FS_TXBCNOK_MB9_INT_EN BIT(9) #define BIT_FS_TXBCNOK_MB8_INT_EN BIT(8) #define BIT_FS_BCNERLY0_MB15INT_EN BIT(7) #define BIT_FS_BCNERLY0_MB14INT_EN BIT(6) #define BIT_FS_BCNERLY0_MB13INT_EN BIT(5) #define BIT_FS_BCNERLY0_MB12INT_EN BIT(4) #define BIT_FS_BCNERLY0_MB11INT_EN BIT(3) #define BIT_FS_BCNERLY0_MB10INT_EN BIT(2) #define BIT_FS_BCNERLY0_MB9INT_EN BIT(1) #define BIT_FS_BCNERLY0_MB8INT_EN BIT(0) /* 2 REG_FWISR1 (Offset 0x116C) */ #define BIT_FS_ATIM_MB15_INT BIT(31) #define BIT_FS_ATIM_MB14_INT BIT(30) #define BIT_FS_ATIM_MB13_INT BIT(29) #define BIT_FS_ATIM_MB12_INT BIT(28) #define BIT_FS_ATIM_MB11_INT BIT(27) #define BIT_FS_ATIM_MB10_INT BIT(26) #define BIT_FS_ATIM_MB9_INT BIT(25) #define BIT_FS_ATIM_MB8_INT BIT(24) #define BIT_FS_TXBCNERR_MB15_INT BIT(23) #define BIT_FS_TXBCNERR_MB14_INT BIT(22) #define BIT_FS_TXBCNERR_MB13_INT BIT(21) #define BIT_FS_TXBCNERR_MB12_INT BIT(20) #define BIT_FS_TXBCNERR_MB11_INT BIT(19) #define BIT_FS_TXBCNERR_MB10_INT BIT(18) #define BIT_FS_TXBCNERR_MB9_INT BIT(17) #define BIT_FS_TXBCNERR_MB8_INT BIT(16) #define BIT_FS_TXBCNOK_MB15_INT BIT(15) #define BIT_FS_TXBCNOK_MB14_INT BIT(14) #define BIT_FS_TXBCNOK_MB13_INT BIT(13) #define BIT_FS_TXBCNOK_MB12_INT BIT(12) #define BIT_FS_TXBCNOK_MB11_INT BIT(11) #define BIT_FS_TXBCNOK_MB10_INT BIT(10) #define BIT_FS_TXBCNOK_MB9_INT BIT(9) #define BIT_FS_TXBCNOK_MB8_INT BIT(8) #define BIT_FS_BCNERLY0_MB15INT BIT(7) #define BIT_FS_BCNERLY0_MB14INT BIT(6) #define BIT_FS_BCNERLY0_MB13INT BIT(5) #define BIT_FS_BCNERLY0_MB12INT BIT(4) #define BIT_FS_BCNERLY0_MB11INT BIT(3) #define BIT_FS_BCNERLY0_MB10INT BIT(2) #define BIT_FS_BCNERLY0_MB9INT BIT(1) #define BIT_FS_BCNERLY0_MB8INT BIT(0) /* 2 REG_FWIMR2 (Offset 0x1170) */ #define BIT_FS_BCNDMA0_MB15_INT_EN BIT(15) #define BIT_FS_BCNDMA0_MB14_INT_EN BIT(14) #define BIT_FS_BCNDMA0_MB13_INT_EN BIT(13) #define BIT_FS_BCNDMA0_MB12_INT_EN BIT(12) #define BIT_FS_BCNDMA0_MB11_INT_EN BIT(11) #define BIT_FS_BCNDMA0_MB10_INT_EN BIT(10) #define BIT_FS_BCNDMA0_MB9_INT_EN BIT(9) #define BIT_FS_BCNDMA0_MB8_INT_EN BIT(8) #define BIT_FS_TBTT0_MB15INT_EN BIT(7) #define BIT_FS_TBTT0_MB14INT_EN BIT(6) #define BIT_FS_TBTT0_MB13INT_EN BIT(5) #define BIT_FS_TBTT0_MB12INT_EN BIT(4) #define BIT_FS_TBTT0_MB11INT_EN BIT(3) #define BIT_FS_TBTT0_MB10INT_EN BIT(2) #define BIT_FS_TBTT0_MB9INT_EN BIT(1) #define BIT_FS_TBTT0_MB8INT_EN BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_IO_WRAP_ERR_FLAG (Offset 0x1170) */ #define BIT_IO_WRAP_ERR BIT(0) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_FWISR2 (Offset 0x1174) */ #define BIT_FS_BCNDMA0_MB15_INT BIT(15) #define BIT_FS_BCNDMA0_MB14_INT BIT(14) #define BIT_FS_BCNDMA0_MB13_INT BIT(13) #define BIT_FS_BCNDMA0_MB12_INT BIT(12) #define BIT_FS_BCNDMA0_MB11_INT BIT(11) #define BIT_FS_BCNDMA0_MB10_INT BIT(10) #define BIT_FS_BCNDMA0_MB9_INT BIT(9) #define BIT_FS_BCNDMA0_MB8_INT BIT(8) #define BIT_FS_TBTT0_MB15INT BIT(7) #define BIT_FS_TBTT0_MB14INT BIT(6) #define BIT_FS_TBTT0_MB13INT BIT(5) #define BIT_FS_TBTT0_MB12INT BIT(4) #define BIT_FS_TBTT0_MB11INT BIT(3) #define BIT_FS_TBTT0_MB10INT BIT(2) #define BIT_FS_TBTT0_MB9INT BIT(1) #define BIT_FS_TBTT0_MB8INT BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FWISR3 (Offset 0x117C) */ #define BIT_FS_TXBCNOK_PORT4_INT BIT(11) #define BIT_FS_TXBCNOK_PORT3_INT BIT(10) #define BIT_FS_TXBCNOK_PORT2_INT BIT(9) #define BIT_FS_TXBCNOK_PORT1_INT BIT(8) #define BIT_FS_TXBCNERR_PORT4_INT BIT(7) #define BIT_FS_TXBCNERR_PORT3_INT BIT(6) #define BIT_FS_TXBCNERR_PORT2_INT BIT(5) #define BIT_FS_TXBCNERR_PORT1_INT BIT(4) #define BIT_FS_ATIM_PORT4_INT BIT(3) #define BIT_FS_ATIM_PORT3_INT BIT(2) #define BIT_FS_ATIM_PORT2_INT BIT(1) #define BIT_FS_ATIM_PORT1_INT BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SPEED_SENSOR (Offset 0x1180) */ #define BIT_DSS_1_RST_N BIT(31) #define BIT_DSS_1_SPEED_EN BIT(30) #define BIT_DSS_1_WIRE_SEL BIT(29) #define BIT_DSS_ENCLK BIT(28) #define BIT_SHIFT_DSS_1_RO_SEL 24 #define BIT_MASK_DSS_1_RO_SEL 0x7 #define BIT_DSS_1_RO_SEL(x) \ (((x) & BIT_MASK_DSS_1_RO_SEL) << BIT_SHIFT_DSS_1_RO_SEL) #define BITS_DSS_1_RO_SEL (BIT_MASK_DSS_1_RO_SEL << BIT_SHIFT_DSS_1_RO_SEL) #define BIT_CLEAR_DSS_1_RO_SEL(x) ((x) & (~BITS_DSS_1_RO_SEL)) #define BIT_GET_DSS_1_RO_SEL(x) \ (((x) >> BIT_SHIFT_DSS_1_RO_SEL) & BIT_MASK_DSS_1_RO_SEL) #define BIT_SET_DSS_1_RO_SEL(x, v) \ (BIT_CLEAR_DSS_1_RO_SEL(x) | BIT_DSS_1_RO_SEL(v)) #define BIT_SHIFT_DSS_1_DATA_IN 0 #define BIT_MASK_DSS_1_DATA_IN 0xfffff #define BIT_DSS_1_DATA_IN(x) \ (((x) & BIT_MASK_DSS_1_DATA_IN) << BIT_SHIFT_DSS_1_DATA_IN) #define BITS_DSS_1_DATA_IN (BIT_MASK_DSS_1_DATA_IN << BIT_SHIFT_DSS_1_DATA_IN) #define BIT_CLEAR_DSS_1_DATA_IN(x) ((x) & (~BITS_DSS_1_DATA_IN)) #define BIT_GET_DSS_1_DATA_IN(x) \ (((x) >> BIT_SHIFT_DSS_1_DATA_IN) & BIT_MASK_DSS_1_DATA_IN) #define BIT_SET_DSS_1_DATA_IN(x, v) \ (BIT_CLEAR_DSS_1_DATA_IN(x) | BIT_DSS_1_DATA_IN(v)) /* 2 REG_SPEED_SENSOR1 (Offset 0x1184) */ #define BIT_DSS_1_READY BIT(31) #define BIT_DSS_1_WSORT_GO BIT(30) #define BIT_SHIFT_DSS_1_COUNT_OUT 0 #define BIT_MASK_DSS_1_COUNT_OUT 0xfffff #define BIT_DSS_1_COUNT_OUT(x) \ (((x) & BIT_MASK_DSS_1_COUNT_OUT) << BIT_SHIFT_DSS_1_COUNT_OUT) #define BITS_DSS_1_COUNT_OUT \ (BIT_MASK_DSS_1_COUNT_OUT << BIT_SHIFT_DSS_1_COUNT_OUT) #define BIT_CLEAR_DSS_1_COUNT_OUT(x) ((x) & (~BITS_DSS_1_COUNT_OUT)) #define BIT_GET_DSS_1_COUNT_OUT(x) \ (((x) >> BIT_SHIFT_DSS_1_COUNT_OUT) & BIT_MASK_DSS_1_COUNT_OUT) #define BIT_SET_DSS_1_COUNT_OUT(x, v) \ (BIT_CLEAR_DSS_1_COUNT_OUT(x) | BIT_DSS_1_COUNT_OUT(v)) /* 2 REG_SPEED_SENSOR2 (Offset 0x1188) */ #define BIT_DSS_2_RST_N BIT(31) #define BIT_DSS_2_SPEED_EN BIT(30) #define BIT_DSS_2_WIRE_SEL BIT(29) #define BIT_SHIFT_DSS_2_RO_SEL 24 #define BIT_MASK_DSS_2_RO_SEL 0x7 #define BIT_DSS_2_RO_SEL(x) \ (((x) & BIT_MASK_DSS_2_RO_SEL) << BIT_SHIFT_DSS_2_RO_SEL) #define BITS_DSS_2_RO_SEL (BIT_MASK_DSS_2_RO_SEL << BIT_SHIFT_DSS_2_RO_SEL) #define BIT_CLEAR_DSS_2_RO_SEL(x) ((x) & (~BITS_DSS_2_RO_SEL)) #define BIT_GET_DSS_2_RO_SEL(x) \ (((x) >> BIT_SHIFT_DSS_2_RO_SEL) & BIT_MASK_DSS_2_RO_SEL) #define BIT_SET_DSS_2_RO_SEL(x, v) \ (BIT_CLEAR_DSS_2_RO_SEL(x) | BIT_DSS_2_RO_SEL(v)) #define BIT_SHIFT_DSS_2_DATA_IN 0 #define BIT_MASK_DSS_2_DATA_IN 0xfffff #define BIT_DSS_2_DATA_IN(x) \ (((x) & BIT_MASK_DSS_2_DATA_IN) << BIT_SHIFT_DSS_2_DATA_IN) #define BITS_DSS_2_DATA_IN (BIT_MASK_DSS_2_DATA_IN << BIT_SHIFT_DSS_2_DATA_IN) #define BIT_CLEAR_DSS_2_DATA_IN(x) ((x) & (~BITS_DSS_2_DATA_IN)) #define BIT_GET_DSS_2_DATA_IN(x) \ (((x) >> BIT_SHIFT_DSS_2_DATA_IN) & BIT_MASK_DSS_2_DATA_IN) #define BIT_SET_DSS_2_DATA_IN(x, v) \ (BIT_CLEAR_DSS_2_DATA_IN(x) | BIT_DSS_2_DATA_IN(v)) /* 2 REG_SPEED_SENSOR3 (Offset 0x118C) */ #define BIT_DSS_2_READY BIT(31) #define BIT_DSS_2_WSORT_GO BIT(30) #define BIT_SHIFT_DSS_2_COUNT_OUT 0 #define BIT_MASK_DSS_2_COUNT_OUT 0xfffff #define BIT_DSS_2_COUNT_OUT(x) \ (((x) & BIT_MASK_DSS_2_COUNT_OUT) << BIT_SHIFT_DSS_2_COUNT_OUT) #define BITS_DSS_2_COUNT_OUT \ (BIT_MASK_DSS_2_COUNT_OUT << BIT_SHIFT_DSS_2_COUNT_OUT) #define BIT_CLEAR_DSS_2_COUNT_OUT(x) ((x) & (~BITS_DSS_2_COUNT_OUT)) #define BIT_GET_DSS_2_COUNT_OUT(x) \ (((x) >> BIT_SHIFT_DSS_2_COUNT_OUT) & BIT_MASK_DSS_2_COUNT_OUT) #define BIT_SET_DSS_2_COUNT_OUT(x, v) \ (BIT_CLEAR_DSS_2_COUNT_OUT(x) | BIT_DSS_2_COUNT_OUT(v)) /* 2 REG_SPEED_SENSOR4 (Offset 0x1190) */ #define BIT_DSS_3_RST_N BIT(31) #define BIT_DSS_3_SPEED_EN BIT(30) #define BIT_DSS_3_WIRE_SEL BIT(29) #define BIT_SHIFT_DSS_3_RO_SEL 24 #define BIT_MASK_DSS_3_RO_SEL 0x7 #define BIT_DSS_3_RO_SEL(x) \ (((x) & BIT_MASK_DSS_3_RO_SEL) << BIT_SHIFT_DSS_3_RO_SEL) #define BITS_DSS_3_RO_SEL (BIT_MASK_DSS_3_RO_SEL << BIT_SHIFT_DSS_3_RO_SEL) #define BIT_CLEAR_DSS_3_RO_SEL(x) ((x) & (~BITS_DSS_3_RO_SEL)) #define BIT_GET_DSS_3_RO_SEL(x) \ (((x) >> BIT_SHIFT_DSS_3_RO_SEL) & BIT_MASK_DSS_3_RO_SEL) #define BIT_SET_DSS_3_RO_SEL(x, v) \ (BIT_CLEAR_DSS_3_RO_SEL(x) | BIT_DSS_3_RO_SEL(v)) #define BIT_SHIFT_DSS_3_DATA_IN 0 #define BIT_MASK_DSS_3_DATA_IN 0xfffff #define BIT_DSS_3_DATA_IN(x) \ (((x) & BIT_MASK_DSS_3_DATA_IN) << BIT_SHIFT_DSS_3_DATA_IN) #define BITS_DSS_3_DATA_IN (BIT_MASK_DSS_3_DATA_IN << BIT_SHIFT_DSS_3_DATA_IN) #define BIT_CLEAR_DSS_3_DATA_IN(x) ((x) & (~BITS_DSS_3_DATA_IN)) #define BIT_GET_DSS_3_DATA_IN(x) \ (((x) >> BIT_SHIFT_DSS_3_DATA_IN) & BIT_MASK_DSS_3_DATA_IN) #define BIT_SET_DSS_3_DATA_IN(x, v) \ (BIT_CLEAR_DSS_3_DATA_IN(x) | BIT_DSS_3_DATA_IN(v)) /* 2 REG_SPEED_SENSOR5 (Offset 0x1194) */ #define BIT_DSS_3_READY BIT(31) #define BIT_DSS_3_WSORT_GO BIT(30) #define BIT_SHIFT_DSS_3_COUNT_OUT 0 #define BIT_MASK_DSS_3_COUNT_OUT 0xfffff #define BIT_DSS_3_COUNT_OUT(x) \ (((x) & BIT_MASK_DSS_3_COUNT_OUT) << BIT_SHIFT_DSS_3_COUNT_OUT) #define BITS_DSS_3_COUNT_OUT \ (BIT_MASK_DSS_3_COUNT_OUT << BIT_SHIFT_DSS_3_COUNT_OUT) #define BIT_CLEAR_DSS_3_COUNT_OUT(x) ((x) & (~BITS_DSS_3_COUNT_OUT)) #define BIT_GET_DSS_3_COUNT_OUT(x) \ (((x) >> BIT_SHIFT_DSS_3_COUNT_OUT) & BIT_MASK_DSS_3_COUNT_OUT) #define BIT_SET_DSS_3_COUNT_OUT(x, v) \ (BIT_CLEAR_DSS_3_COUNT_OUT(x) | BIT_DSS_3_COUNT_OUT(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_RXPKTBUF_1_MAX_ADDR (Offset 0x1198) */ #define BIT_SHIFT_RXPKTBUF_SIZE 30 #define BIT_MASK_RXPKTBUF_SIZE 0x3 #define BIT_RXPKTBUF_SIZE(x) \ (((x) & BIT_MASK_RXPKTBUF_SIZE) << BIT_SHIFT_RXPKTBUF_SIZE) #define BITS_RXPKTBUF_SIZE (BIT_MASK_RXPKTBUF_SIZE << BIT_SHIFT_RXPKTBUF_SIZE) #define BIT_CLEAR_RXPKTBUF_SIZE(x) ((x) & (~BITS_RXPKTBUF_SIZE)) #define BIT_GET_RXPKTBUF_SIZE(x) \ (((x) >> BIT_SHIFT_RXPKTBUF_SIZE) & BIT_MASK_RXPKTBUF_SIZE) #define BIT_SET_RXPKTBUF_SIZE(x, v) \ (BIT_CLEAR_RXPKTBUF_SIZE(x) | BIT_RXPKTBUF_SIZE(v)) #define BIT_RXPKTBUF_DBG_SEL BIT(29) #define BIT_SHIFT_RXPKTBUF_1_MAX_ADDR 0 #define BIT_MASK_RXPKTBUF_1_MAX_ADDR 0x3ffff #define BIT_RXPKTBUF_1_MAX_ADDR(x) \ (((x) & BIT_MASK_RXPKTBUF_1_MAX_ADDR) << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR) #define BITS_RXPKTBUF_1_MAX_ADDR \ (BIT_MASK_RXPKTBUF_1_MAX_ADDR << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR) #define BIT_CLEAR_RXPKTBUF_1_MAX_ADDR(x) ((x) & (~BITS_RXPKTBUF_1_MAX_ADDR)) #define BIT_GET_RXPKTBUF_1_MAX_ADDR(x) \ (((x) >> BIT_SHIFT_RXPKTBUF_1_MAX_ADDR) & BIT_MASK_RXPKTBUF_1_MAX_ADDR) #define BIT_SET_RXPKTBUF_1_MAX_ADDR(x, v) \ (BIT_CLEAR_RXPKTBUF_1_MAX_ADDR(x) | BIT_RXPKTBUF_1_MAX_ADDR(v)) /* 2 REG_RXFWBUF_1_MAX_ADDR (Offset 0x119C) */ #define BIT_SHIFT_RXFWBUF_1_MAX_ADDR 0 #define BIT_MASK_RXFWBUF_1_MAX_ADDR 0xffff #define BIT_RXFWBUF_1_MAX_ADDR(x) \ (((x) & BIT_MASK_RXFWBUF_1_MAX_ADDR) << BIT_SHIFT_RXFWBUF_1_MAX_ADDR) #define BITS_RXFWBUF_1_MAX_ADDR \ (BIT_MASK_RXFWBUF_1_MAX_ADDR << BIT_SHIFT_RXFWBUF_1_MAX_ADDR) #define BIT_CLEAR_RXFWBUF_1_MAX_ADDR(x) ((x) & (~BITS_RXFWBUF_1_MAX_ADDR)) #define BIT_GET_RXFWBUF_1_MAX_ADDR(x) \ (((x) >> BIT_SHIFT_RXFWBUF_1_MAX_ADDR) & BIT_MASK_RXFWBUF_1_MAX_ADDR) #define BIT_SET_RXFWBUF_1_MAX_ADDR(x, v) \ (BIT_CLEAR_RXFWBUF_1_MAX_ADDR(x) | BIT_RXFWBUF_1_MAX_ADDR(v)) /* 2 REG_RXPKTBUF_1_READ (Offset 0x11A4) */ #define BIT_SHIFT_RXPKTBUF_1_READ 0 #define BIT_MASK_RXPKTBUF_1_READ 0x3ffff #define BIT_RXPKTBUF_1_READ(x) \ (((x) & BIT_MASK_RXPKTBUF_1_READ) << BIT_SHIFT_RXPKTBUF_1_READ) #define BITS_RXPKTBUF_1_READ \ (BIT_MASK_RXPKTBUF_1_READ << BIT_SHIFT_RXPKTBUF_1_READ) #define BIT_CLEAR_RXPKTBUF_1_READ(x) ((x) & (~BITS_RXPKTBUF_1_READ)) #define BIT_GET_RXPKTBUF_1_READ(x) \ (((x) >> BIT_SHIFT_RXPKTBUF_1_READ) & BIT_MASK_RXPKTBUF_1_READ) #define BIT_SET_RXPKTBUF_1_READ(x, v) \ (BIT_CLEAR_RXPKTBUF_1_READ(x) | BIT_RXPKTBUF_1_READ(v)) /* 2 REG_RXPKTBUF_1_WRITE (Offset 0x11A8) */ #define BIT_SHIFT_R_OQT_DBG_SEL 16 #define BIT_MASK_R_OQT_DBG_SEL 0xff #define BIT_R_OQT_DBG_SEL(x) \ (((x) & BIT_MASK_R_OQT_DBG_SEL) << BIT_SHIFT_R_OQT_DBG_SEL) #define BITS_R_OQT_DBG_SEL (BIT_MASK_R_OQT_DBG_SEL << BIT_SHIFT_R_OQT_DBG_SEL) #define BIT_CLEAR_R_OQT_DBG_SEL(x) ((x) & (~BITS_R_OQT_DBG_SEL)) #define BIT_GET_R_OQT_DBG_SEL(x) \ (((x) >> BIT_SHIFT_R_OQT_DBG_SEL) & BIT_MASK_R_OQT_DBG_SEL) #define BIT_SET_R_OQT_DBG_SEL(x, v) \ (BIT_CLEAR_R_OQT_DBG_SEL(x) | BIT_R_OQT_DBG_SEL(v)) #define BIT_SHIFT_R_TXPKTBF_DBG_SEL 8 #define BIT_MASK_R_TXPKTBF_DBG_SEL 0x7 #define BIT_R_TXPKTBF_DBG_SEL(x) \ (((x) & BIT_MASK_R_TXPKTBF_DBG_SEL) << BIT_SHIFT_R_TXPKTBF_DBG_SEL) #define BITS_R_TXPKTBF_DBG_SEL \ (BIT_MASK_R_TXPKTBF_DBG_SEL << BIT_SHIFT_R_TXPKTBF_DBG_SEL) #define BIT_CLEAR_R_TXPKTBF_DBG_SEL(x) ((x) & (~BITS_R_TXPKTBF_DBG_SEL)) #define BIT_GET_R_TXPKTBF_DBG_SEL(x) \ (((x) >> BIT_SHIFT_R_TXPKTBF_DBG_SEL) & BIT_MASK_R_TXPKTBF_DBG_SEL) #define BIT_SET_R_TXPKTBF_DBG_SEL(x, v) \ (BIT_CLEAR_R_TXPKTBF_DBG_SEL(x) | BIT_R_TXPKTBF_DBG_SEL(v)) #define BIT_SHIFT_R_RXPKT_DBG_SEL 6 #define BIT_MASK_R_RXPKT_DBG_SEL 0x3 #define BIT_R_RXPKT_DBG_SEL(x) \ (((x) & BIT_MASK_R_RXPKT_DBG_SEL) << BIT_SHIFT_R_RXPKT_DBG_SEL) #define BITS_R_RXPKT_DBG_SEL \ (BIT_MASK_R_RXPKT_DBG_SEL << BIT_SHIFT_R_RXPKT_DBG_SEL) #define BIT_CLEAR_R_RXPKT_DBG_SEL(x) ((x) & (~BITS_R_RXPKT_DBG_SEL)) #define BIT_GET_R_RXPKT_DBG_SEL(x) \ (((x) >> BIT_SHIFT_R_RXPKT_DBG_SEL) & BIT_MASK_R_RXPKT_DBG_SEL) #define BIT_SET_R_RXPKT_DBG_SEL(x, v) \ (BIT_CLEAR_R_RXPKT_DBG_SEL(x) | BIT_R_RXPKT_DBG_SEL(v)) #define BIT_SHIFT_RXPKTBUF_1_WRITE 0 #define BIT_MASK_RXPKTBUF_1_WRITE 0x3ffff #define BIT_RXPKTBUF_1_WRITE(x) \ (((x) & BIT_MASK_RXPKTBUF_1_WRITE) << BIT_SHIFT_RXPKTBUF_1_WRITE) #define BITS_RXPKTBUF_1_WRITE \ (BIT_MASK_RXPKTBUF_1_WRITE << BIT_SHIFT_RXPKTBUF_1_WRITE) #define BIT_CLEAR_RXPKTBUF_1_WRITE(x) ((x) & (~BITS_RXPKTBUF_1_WRITE)) #define BIT_GET_RXPKTBUF_1_WRITE(x) \ (((x) >> BIT_SHIFT_RXPKTBUF_1_WRITE) & BIT_MASK_RXPKTBUF_1_WRITE) #define BIT_SET_RXPKTBUF_1_WRITE(x, v) \ (BIT_CLEAR_RXPKTBUF_1_WRITE(x) | BIT_RXPKTBUF_1_WRITE(v)) #define BIT_SHIFT_R_RXPKTBF_DBG_SEL 0 #define BIT_MASK_R_RXPKTBF_DBG_SEL 0x3 #define BIT_R_RXPKTBF_DBG_SEL(x) \ (((x) & BIT_MASK_R_RXPKTBF_DBG_SEL) << BIT_SHIFT_R_RXPKTBF_DBG_SEL) #define BITS_R_RXPKTBF_DBG_SEL \ (BIT_MASK_R_RXPKTBF_DBG_SEL << BIT_SHIFT_R_RXPKTBF_DBG_SEL) #define BIT_CLEAR_R_RXPKTBF_DBG_SEL(x) ((x) & (~BITS_R_RXPKTBF_DBG_SEL)) #define BIT_GET_R_RXPKTBF_DBG_SEL(x) \ (((x) >> BIT_SHIFT_R_RXPKTBF_DBG_SEL) & BIT_MASK_R_RXPKTBF_DBG_SEL) #define BIT_SET_R_RXPKTBF_DBG_SEL(x, v) \ (BIT_CLEAR_R_RXPKTBF_DBG_SEL(x) | BIT_R_RXPKTBF_DBG_SEL(v)) /* 2 REG_RFE_CTRL_PAD_E2 (Offset 0x11B0) */ #define BIT_RFE_CTRL_ANTSW_E2 BIT(16) #define BIT_RFE_CTRL_PIN15_E2 BIT(15) #define BIT_RFE_CTRL_PIN14_E2 BIT(14) #define BIT_RFE_CTRL_PIN13_E2 BIT(13) #define BIT_RFE_CTRL_PIN12_E2 BIT(12) #define BIT_RFE_CTRL_PIN11_E2 BIT(11) #define BIT_RFE_CTRL_PIN10_E2 BIT(10) #define BIT_RFE_CTRL_PIN9_E2 BIT(9) #define BIT_RFE_CTRL_PIN8_E2 BIT(8) #define BIT_RFE_CTRL_PIN7_E2 BIT(7) #define BIT_RFE_CTRL_PIN6_E2 BIT(6) #define BIT_RFE_CTRL_PIN5_E2 BIT(5) #define BIT_RFE_CTRL_PIN4_E2 BIT(4) #define BIT_RFE_CTRL_PIN3_E2 BIT(3) #define BIT_RFE_CTRL_PIN2_E2 BIT(2) #define BIT_RFE_CTRL_PIN1_E2 BIT(1) #define BIT_RFE_CTRL_PIN0_E2 BIT(0) /* 2 REG_RFE_CTRL_PAD_SR (Offset 0x11B4) */ #define BIT_RFE_CTRL_ANTSW_SR BIT(16) #define BIT_RFE_CTRL_PIN15_SR BIT(15) #define BIT_RFE_CTRL_PIN14_SR BIT(14) #define BIT_RFE_CTRL_PIN13_SR BIT(13) #define BIT_RFE_CTRL_PIN12_SR BIT(12) #define BIT_RFE_CTRL_PIN11_SR BIT(11) #define BIT_RFE_CTRL_PIN10_SR BIT(10) #define BIT_RFE_CTRL_PIN9_SR BIT(9) #define BIT_RFE_CTRL_PIN8_SR BIT(8) #define BIT_RFE_CTRL_PIN7_SR BIT(7) #define BIT_RFE_CTRL_PIN6_SR BIT(6) #define BIT_RFE_CTRL_PIN5_SR BIT(5) #define BIT_RFE_CTRL_PIN4_SR BIT(4) #define BIT_RFE_CTRL_PIN3_SR BIT(3) #define BIT_RFE_CTRL_PIN2_SR BIT(2) #define BIT_RFE_CTRL_PIN1_SR BIT(1) #define BIT_RFE_CTRL_PIN0_SR BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_EXT_QUEUE_REG (Offset 0x11C0) */ #define BIT_SHIFT_PCIE_PRIORITY_SEL 0 #define BIT_MASK_PCIE_PRIORITY_SEL 0x3 #define BIT_PCIE_PRIORITY_SEL(x) \ (((x) & BIT_MASK_PCIE_PRIORITY_SEL) << BIT_SHIFT_PCIE_PRIORITY_SEL) #define BITS_PCIE_PRIORITY_SEL \ (BIT_MASK_PCIE_PRIORITY_SEL << BIT_SHIFT_PCIE_PRIORITY_SEL) #define BIT_CLEAR_PCIE_PRIORITY_SEL(x) ((x) & (~BITS_PCIE_PRIORITY_SEL)) #define BIT_GET_PCIE_PRIORITY_SEL(x) \ (((x) >> BIT_SHIFT_PCIE_PRIORITY_SEL) & BIT_MASK_PCIE_PRIORITY_SEL) #define BIT_SET_PCIE_PRIORITY_SEL(x, v) \ (BIT_CLEAR_PCIE_PRIORITY_SEL(x) | BIT_PCIE_PRIORITY_SEL(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_H2C_PRIORITY_SEL (Offset 0x11C0) */ #define BIT_SHIFT_H2C_PRIORITY_SEL 0 #define BIT_MASK_H2C_PRIORITY_SEL 0x3 #define BIT_H2C_PRIORITY_SEL(x) \ (((x) & BIT_MASK_H2C_PRIORITY_SEL) << BIT_SHIFT_H2C_PRIORITY_SEL) #define BITS_H2C_PRIORITY_SEL \ (BIT_MASK_H2C_PRIORITY_SEL << BIT_SHIFT_H2C_PRIORITY_SEL) #define BIT_CLEAR_H2C_PRIORITY_SEL(x) ((x) & (~BITS_H2C_PRIORITY_SEL)) #define BIT_GET_H2C_PRIORITY_SEL(x) \ (((x) >> BIT_SHIFT_H2C_PRIORITY_SEL) & BIT_MASK_H2C_PRIORITY_SEL) #define BIT_SET_H2C_PRIORITY_SEL(x, v) \ (BIT_CLEAR_H2C_PRIORITY_SEL(x) | BIT_H2C_PRIORITY_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ #define BIT_EN_USB_CNT BIT(5) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_COUNTER_CTRL (Offset 0x11C4) */ #define BIT_USB_COUNT_EN BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ #define BIT_EN_PCIE_CNT BIT(4) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_COUNTER_CTRL (Offset 0x11C4) */ #define BIT_PCIE_COUNT_EN BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ #define BIT_RQPN_CNT BIT(3) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_COUNTER_CTRL (Offset 0x11C4) */ #define BIT_RQPN_COUNT_EN BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ #define BIT_RDE_CNT BIT(2) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_COUNTER_CTRL (Offset 0x11C4) */ #define BIT_RDE_COUNT_EN BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ #define BIT_TDE_CNT BIT(1) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_COUNTER_CTRL (Offset 0x11C4) */ #define BIT_TDE_COUNT_EN BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ #define BIT_DIS_CNT BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_COUNTER_CTRL (Offset 0x11C4) */ #define BIT_DISABLE_COUNTER BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_COUNTER_TH (Offset 0x11C8) */ #define BIT_CNT_ALL_MACID BIT(31) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_COUNTER_THRESHOLD (Offset 0x11C8) */ #define BIT_SEL_ALL_MACID BIT(31) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_COUNTER_TH (Offset 0x11C8) */ #define BIT_SHIFT_CNT_MACID 24 #define BIT_MASK_CNT_MACID 0x7f #define BIT_CNT_MACID(x) (((x) & BIT_MASK_CNT_MACID) << BIT_SHIFT_CNT_MACID) #define BITS_CNT_MACID (BIT_MASK_CNT_MACID << BIT_SHIFT_CNT_MACID) #define BIT_CLEAR_CNT_MACID(x) ((x) & (~BITS_CNT_MACID)) #define BIT_GET_CNT_MACID(x) (((x) >> BIT_SHIFT_CNT_MACID) & BIT_MASK_CNT_MACID) #define BIT_SET_CNT_MACID(x, v) (BIT_CLEAR_CNT_MACID(x) | BIT_CNT_MACID(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_COUNTER_THRESHOLD (Offset 0x11C8) */ #define BIT_SHIFT_COUNTER_MACID 24 #define BIT_MASK_COUNTER_MACID 0x7f #define BIT_COUNTER_MACID(x) \ (((x) & BIT_MASK_COUNTER_MACID) << BIT_SHIFT_COUNTER_MACID) #define BITS_COUNTER_MACID (BIT_MASK_COUNTER_MACID << BIT_SHIFT_COUNTER_MACID) #define BIT_CLEAR_COUNTER_MACID(x) ((x) & (~BITS_COUNTER_MACID)) #define BIT_GET_COUNTER_MACID(x) \ (((x) >> BIT_SHIFT_COUNTER_MACID) & BIT_MASK_COUNTER_MACID) #define BIT_SET_COUNTER_MACID(x, v) \ (BIT_CLEAR_COUNTER_MACID(x) | BIT_COUNTER_MACID(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_COUNTER_SET (Offset 0x11CC) */ #define BIT_RTS_RST BIT(24) #define BIT_PTCL_RST BIT(23) #define BIT_SCH_RST BIT(22) #define BIT_EDCA_RST BIT(21) #define BIT_RQPN_RST BIT(20) #define BIT_USB_RST BIT(19) #define BIT_PCIE_RST BIT(18) #define BIT_RXDMA_RST BIT(17) #define BIT_TXDMA_RST BIT(16) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_COUNTER_SET (Offset 0x11CC) */ #define BIT_SHIFT_REQUEST_RESET 16 #define BIT_MASK_REQUEST_RESET 0xffff #define BIT_REQUEST_RESET(x) \ (((x) & BIT_MASK_REQUEST_RESET) << BIT_SHIFT_REQUEST_RESET) #define BITS_REQUEST_RESET (BIT_MASK_REQUEST_RESET << BIT_SHIFT_REQUEST_RESET) #define BIT_CLEAR_REQUEST_RESET(x) ((x) & (~BITS_REQUEST_RESET)) #define BIT_GET_REQUEST_RESET(x) \ (((x) >> BIT_SHIFT_REQUEST_RESET) & BIT_MASK_REQUEST_RESET) #define BIT_SET_REQUEST_RESET(x, v) \ (BIT_CLEAR_REQUEST_RESET(x) | BIT_REQUEST_RESET(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_COUNTER_SET (Offset 0x11CC) */ #define BIT_EN_RTS_START BIT(8) #define BIT_EN_PTCL_START BIT(7) #define BIT_EN_SCH_START BIT(6) #define BIT_EN_EDCA_START BIT(5) #define BIT_EN_RQPN_START BIT(4) #define BIT_EN_USB_START BIT(3) #define BIT_EN_PCIE_START BIT(2) #define BIT_EN_RXDMA_START BIT(1) #define BIT_EN_TXDMA_START BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_COUNTER_SET (Offset 0x11CC) */ #define BIT_SHIFT_REQUEST_START 0 #define BIT_MASK_REQUEST_START 0xffff #define BIT_REQUEST_START(x) \ (((x) & BIT_MASK_REQUEST_START) << BIT_SHIFT_REQUEST_START) #define BITS_REQUEST_START (BIT_MASK_REQUEST_START << BIT_SHIFT_REQUEST_START) #define BIT_CLEAR_REQUEST_START(x) ((x) & (~BITS_REQUEST_START)) #define BIT_GET_REQUEST_START(x) \ (((x) >> BIT_SHIFT_REQUEST_START) & BIT_MASK_REQUEST_START) #define BIT_SET_REQUEST_START(x, v) \ (BIT_CLEAR_REQUEST_START(x) | BIT_REQUEST_START(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_COUNTER_OVERFLOW (Offset 0x11D0) */ #define BIT_RTS_OVF BIT(8) #define BIT_PTCL_OVF BIT(7) #define BIT_SCH_OVF BIT(6) #define BIT_EDCA_OVF BIT(5) #define BIT_RQPN_OVF BIT(4) #define BIT_USB_OVF BIT(3) #define BIT_PCIE_OVF BIT(2) #define BIT_RXDMA_OVF BIT(1) #define BIT_TXDMA_OVF BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_COUNTER_OVERFLOW (Offset 0x11D0) */ #define BIT_SHIFT_CNT_OVF_REG 0 #define BIT_MASK_CNT_OVF_REG 0xffff #define BIT_CNT_OVF_REG(x) \ (((x) & BIT_MASK_CNT_OVF_REG) << BIT_SHIFT_CNT_OVF_REG) #define BITS_CNT_OVF_REG (BIT_MASK_CNT_OVF_REG << BIT_SHIFT_CNT_OVF_REG) #define BIT_CLEAR_CNT_OVF_REG(x) ((x) & (~BITS_CNT_OVF_REG)) #define BIT_GET_CNT_OVF_REG(x) \ (((x) >> BIT_SHIFT_CNT_OVF_REG) & BIT_MASK_CNT_OVF_REG) #define BIT_SET_CNT_OVF_REG(x, v) \ (BIT_CLEAR_CNT_OVF_REG(x) | BIT_CNT_OVF_REG(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_TDE_LEN_TH (Offset 0x11D4) */ #define BIT_SHIFT_TXDMA_LEN_TH0 16 #define BIT_MASK_TXDMA_LEN_TH0 0xffff #define BIT_TXDMA_LEN_TH0(x) \ (((x) & BIT_MASK_TXDMA_LEN_TH0) << BIT_SHIFT_TXDMA_LEN_TH0) #define BITS_TXDMA_LEN_TH0 (BIT_MASK_TXDMA_LEN_TH0 << BIT_SHIFT_TXDMA_LEN_TH0) #define BIT_CLEAR_TXDMA_LEN_TH0(x) ((x) & (~BITS_TXDMA_LEN_TH0)) #define BIT_GET_TXDMA_LEN_TH0(x) \ (((x) >> BIT_SHIFT_TXDMA_LEN_TH0) & BIT_MASK_TXDMA_LEN_TH0) #define BIT_SET_TXDMA_LEN_TH0(x, v) \ (BIT_CLEAR_TXDMA_LEN_TH0(x) | BIT_TXDMA_LEN_TH0(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXDMA_LEN_THRESHOLD (Offset 0x11D4) */ #define BIT_SHIFT_TDE_LEN_TH1 16 #define BIT_MASK_TDE_LEN_TH1 0xffff #define BIT_TDE_LEN_TH1(x) \ (((x) & BIT_MASK_TDE_LEN_TH1) << BIT_SHIFT_TDE_LEN_TH1) #define BITS_TDE_LEN_TH1 (BIT_MASK_TDE_LEN_TH1 << BIT_SHIFT_TDE_LEN_TH1) #define BIT_CLEAR_TDE_LEN_TH1(x) ((x) & (~BITS_TDE_LEN_TH1)) #define BIT_GET_TDE_LEN_TH1(x) \ (((x) >> BIT_SHIFT_TDE_LEN_TH1) & BIT_MASK_TDE_LEN_TH1) #define BIT_SET_TDE_LEN_TH1(x, v) \ (BIT_CLEAR_TDE_LEN_TH1(x) | BIT_TDE_LEN_TH1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_TDE_LEN_TH (Offset 0x11D4) */ #define BIT_SHIFT_TXDMA_LEN_TH1 0 #define BIT_MASK_TXDMA_LEN_TH1 0xffff #define BIT_TXDMA_LEN_TH1(x) \ (((x) & BIT_MASK_TXDMA_LEN_TH1) << BIT_SHIFT_TXDMA_LEN_TH1) #define BITS_TXDMA_LEN_TH1 (BIT_MASK_TXDMA_LEN_TH1 << BIT_SHIFT_TXDMA_LEN_TH1) #define BIT_CLEAR_TXDMA_LEN_TH1(x) ((x) & (~BITS_TXDMA_LEN_TH1)) #define BIT_GET_TXDMA_LEN_TH1(x) \ (((x) >> BIT_SHIFT_TXDMA_LEN_TH1) & BIT_MASK_TXDMA_LEN_TH1) #define BIT_SET_TXDMA_LEN_TH1(x, v) \ (BIT_CLEAR_TXDMA_LEN_TH1(x) | BIT_TXDMA_LEN_TH1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TXDMA_LEN_THRESHOLD (Offset 0x11D4) */ #define BIT_SHIFT_TDE_LEN_TH0 0 #define BIT_MASK_TDE_LEN_TH0 0xffff #define BIT_TDE_LEN_TH0(x) \ (((x) & BIT_MASK_TDE_LEN_TH0) << BIT_SHIFT_TDE_LEN_TH0) #define BITS_TDE_LEN_TH0 (BIT_MASK_TDE_LEN_TH0 << BIT_SHIFT_TDE_LEN_TH0) #define BIT_CLEAR_TDE_LEN_TH0(x) ((x) & (~BITS_TDE_LEN_TH0)) #define BIT_GET_TDE_LEN_TH0(x) \ (((x) >> BIT_SHIFT_TDE_LEN_TH0) & BIT_MASK_TDE_LEN_TH0) #define BIT_SET_TDE_LEN_TH0(x, v) \ (BIT_CLEAR_TDE_LEN_TH0(x) | BIT_TDE_LEN_TH0(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_RDE_LEN_TH (Offset 0x11D8) */ #define BIT_SHIFT_RXDMA_LEN_TH0 16 #define BIT_MASK_RXDMA_LEN_TH0 0xffff #define BIT_RXDMA_LEN_TH0(x) \ (((x) & BIT_MASK_RXDMA_LEN_TH0) << BIT_SHIFT_RXDMA_LEN_TH0) #define BITS_RXDMA_LEN_TH0 (BIT_MASK_RXDMA_LEN_TH0 << BIT_SHIFT_RXDMA_LEN_TH0) #define BIT_CLEAR_RXDMA_LEN_TH0(x) ((x) & (~BITS_RXDMA_LEN_TH0)) #define BIT_GET_RXDMA_LEN_TH0(x) \ (((x) >> BIT_SHIFT_RXDMA_LEN_TH0) & BIT_MASK_RXDMA_LEN_TH0) #define BIT_SET_RXDMA_LEN_TH0(x, v) \ (BIT_CLEAR_RXDMA_LEN_TH0(x) | BIT_RXDMA_LEN_TH0(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXDMA_LEN_THRESHOLD (Offset 0x11D8) */ #define BIT_SHIFT_RDE_LEN_TH1 16 #define BIT_MASK_RDE_LEN_TH1 0xffff #define BIT_RDE_LEN_TH1(x) \ (((x) & BIT_MASK_RDE_LEN_TH1) << BIT_SHIFT_RDE_LEN_TH1) #define BITS_RDE_LEN_TH1 (BIT_MASK_RDE_LEN_TH1 << BIT_SHIFT_RDE_LEN_TH1) #define BIT_CLEAR_RDE_LEN_TH1(x) ((x) & (~BITS_RDE_LEN_TH1)) #define BIT_GET_RDE_LEN_TH1(x) \ (((x) >> BIT_SHIFT_RDE_LEN_TH1) & BIT_MASK_RDE_LEN_TH1) #define BIT_SET_RDE_LEN_TH1(x, v) \ (BIT_CLEAR_RDE_LEN_TH1(x) | BIT_RDE_LEN_TH1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_RDE_LEN_TH (Offset 0x11D8) */ #define BIT_SHIFT_RXDMA_LEN_TH1 0 #define BIT_MASK_RXDMA_LEN_TH1 0xffff #define BIT_RXDMA_LEN_TH1(x) \ (((x) & BIT_MASK_RXDMA_LEN_TH1) << BIT_SHIFT_RXDMA_LEN_TH1) #define BITS_RXDMA_LEN_TH1 (BIT_MASK_RXDMA_LEN_TH1 << BIT_SHIFT_RXDMA_LEN_TH1) #define BIT_CLEAR_RXDMA_LEN_TH1(x) ((x) & (~BITS_RXDMA_LEN_TH1)) #define BIT_GET_RXDMA_LEN_TH1(x) \ (((x) >> BIT_SHIFT_RXDMA_LEN_TH1) & BIT_MASK_RXDMA_LEN_TH1) #define BIT_SET_RXDMA_LEN_TH1(x, v) \ (BIT_CLEAR_RXDMA_LEN_TH1(x) | BIT_RXDMA_LEN_TH1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXDMA_LEN_THRESHOLD (Offset 0x11D8) */ #define BIT_SHIFT_RDE_LEN_TH0 0 #define BIT_MASK_RDE_LEN_TH0 0xffff #define BIT_RDE_LEN_TH0(x) \ (((x) & BIT_MASK_RDE_LEN_TH0) << BIT_SHIFT_RDE_LEN_TH0) #define BITS_RDE_LEN_TH0 (BIT_MASK_RDE_LEN_TH0 << BIT_SHIFT_RDE_LEN_TH0) #define BIT_CLEAR_RDE_LEN_TH0(x) ((x) & (~BITS_RDE_LEN_TH0)) #define BIT_GET_RDE_LEN_TH0(x) \ (((x) >> BIT_SHIFT_RDE_LEN_TH0) & BIT_MASK_RDE_LEN_TH0) #define BIT_SET_RDE_LEN_TH0(x, v) \ (BIT_CLEAR_RDE_LEN_TH0(x) | BIT_RDE_LEN_TH0(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PCIE_EXEC_TIME (Offset 0x11DC) */ #define BIT_SHIFT_COUNTER_INTERVAL_SEL 16 #define BIT_MASK_COUNTER_INTERVAL_SEL 0x3 #define BIT_COUNTER_INTERVAL_SEL(x) \ (((x) & BIT_MASK_COUNTER_INTERVAL_SEL) \ << BIT_SHIFT_COUNTER_INTERVAL_SEL) #define BITS_COUNTER_INTERVAL_SEL \ (BIT_MASK_COUNTER_INTERVAL_SEL << BIT_SHIFT_COUNTER_INTERVAL_SEL) #define BIT_CLEAR_COUNTER_INTERVAL_SEL(x) ((x) & (~BITS_COUNTER_INTERVAL_SEL)) #define BIT_GET_COUNTER_INTERVAL_SEL(x) \ (((x) >> BIT_SHIFT_COUNTER_INTERVAL_SEL) & \ BIT_MASK_COUNTER_INTERVAL_SEL) #define BIT_SET_COUNTER_INTERVAL_SEL(x, v) \ (BIT_CLEAR_COUNTER_INTERVAL_SEL(x) | BIT_COUNTER_INTERVAL_SEL(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PCIE_EXEC_TIME_THRESHOLD (Offset 0x11DC) */ #define BIT_SHIFT_COUNT_INT_SEL 16 #define BIT_MASK_COUNT_INT_SEL 0x3 #define BIT_COUNT_INT_SEL(x) \ (((x) & BIT_MASK_COUNT_INT_SEL) << BIT_SHIFT_COUNT_INT_SEL) #define BITS_COUNT_INT_SEL (BIT_MASK_COUNT_INT_SEL << BIT_SHIFT_COUNT_INT_SEL) #define BIT_CLEAR_COUNT_INT_SEL(x) ((x) & (~BITS_COUNT_INT_SEL)) #define BIT_GET_COUNT_INT_SEL(x) \ (((x) >> BIT_SHIFT_COUNT_INT_SEL) & BIT_MASK_COUNT_INT_SEL) #define BIT_SET_COUNT_INT_SEL(x, v) \ (BIT_CLEAR_COUNT_INT_SEL(x) | BIT_COUNT_INT_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PCIE_EXEC_TIME (Offset 0x11DC) */ #define BIT_SHIFT_PCIE_TRANS_DATA_TH1 0 #define BIT_MASK_PCIE_TRANS_DATA_TH1 0xffff #define BIT_PCIE_TRANS_DATA_TH1(x) \ (((x) & BIT_MASK_PCIE_TRANS_DATA_TH1) << BIT_SHIFT_PCIE_TRANS_DATA_TH1) #define BITS_PCIE_TRANS_DATA_TH1 \ (BIT_MASK_PCIE_TRANS_DATA_TH1 << BIT_SHIFT_PCIE_TRANS_DATA_TH1) #define BIT_CLEAR_PCIE_TRANS_DATA_TH1(x) ((x) & (~BITS_PCIE_TRANS_DATA_TH1)) #define BIT_GET_PCIE_TRANS_DATA_TH1(x) \ (((x) >> BIT_SHIFT_PCIE_TRANS_DATA_TH1) & BIT_MASK_PCIE_TRANS_DATA_TH1) #define BIT_SET_PCIE_TRANS_DATA_TH1(x, v) \ (BIT_CLEAR_PCIE_TRANS_DATA_TH1(x) | BIT_PCIE_TRANS_DATA_TH1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PCIE_EXEC_TIME_THRESHOLD (Offset 0x11DC) */ #define BIT_SHIFT_EXEC_TIME_TH 0 #define BIT_MASK_EXEC_TIME_TH 0xffff #define BIT_EXEC_TIME_TH(x) \ (((x) & BIT_MASK_EXEC_TIME_TH) << BIT_SHIFT_EXEC_TIME_TH) #define BITS_EXEC_TIME_TH (BIT_MASK_EXEC_TIME_TH << BIT_SHIFT_EXEC_TIME_TH) #define BIT_CLEAR_EXEC_TIME_TH(x) ((x) & (~BITS_EXEC_TIME_TH)) #define BIT_GET_EXEC_TIME_TH(x) \ (((x) >> BIT_SHIFT_EXEC_TIME_TH) & BIT_MASK_EXEC_TIME_TH) #define BIT_SET_EXEC_TIME_TH(x, v) \ (BIT_CLEAR_EXEC_TIME_TH(x) | BIT_EXEC_TIME_TH(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_EN BIT(31) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI3_RX_UAPSDMD1_EN BIT(31) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT_EN BIT(30) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI3_RX_UAPSDMD0_EN BIT(30) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT4_TRIPKT_OK_INT_EN BIT(29) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI3_TRIGGER_PKT_EN BIT(29) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT4_RX_EOSP_OK_INT_EN BIT(28) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI3_EOSP_INT_EN BIT(28) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT_EN BIT(27) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI2_RX_UAPSDMD1_EN BIT(27) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT_EN BIT(26) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI2_RX_UAPSDMD0_EN BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT3_TRIPKT_OK_INT_EN BIT(25) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI2_TRIGGER_PKT_EN BIT(25) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT3_RX_EOSP_OK_INT_EN BIT(24) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI2_EOSP_INT_EN BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT_EN BIT(23) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI1_RX_UAPSDMD1_EN BIT(23) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT_EN BIT(22) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI1_RX_UAPSDMD0_EN BIT(22) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT2_TRIPKT_OK_INT_EN BIT(21) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI1_TRIGGER_PKT_EN BIT(21) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT2_RX_EOSP_OK_INT_EN BIT(20) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI1_EOSP_INT_EN BIT(20) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT_EN BIT(19) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI0_RX_UAPSDMD1_EN BIT(19) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT_EN BIT(18) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI0_RX_UAPSDMD0_EN BIT(18) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT1_TRIPKT_OK_INT_EN BIT(17) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI0_TRIGGER_PKT_EN BIT(17) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT1_RX_EOSP_OK_INT_EN BIT(16) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI0_EOSP_INT_EN BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_NOA2_TSFT_BIT32_TOGGLE_INT_EN BIT(9) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN BIT(9) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_NOA1_TSFT_BIT32_TOGGLE_INT_EN BIT(8) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT4_TX_NULL1_DONE_INT_EN BIT(7) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI3_TX_NULL1_INT_EN BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT4_TX_NULL0_DONE_INT_EN BIT(6) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI3_TX_NULL0_INT_EN BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT3_TX_NULL1_DONE_INT_EN BIT(5) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI2_TX_NULL1_INT_EN BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT3_TX_NULL0_DONE_INT_EN BIT(4) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI2_TX_NULL0_INT_EN BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT2_TX_NULL1_DONE_INT_EN BIT(3) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI1_TX_NULL1_INT_EN BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT2_TX_NULL0_DONE_INT_EN BIT(2) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI1_TX_NULL0_INT_EN BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT1_TX_NULL1_DONE_INT_EN BIT(1) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI0_TX_NULL1_INT_EN BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_PORT1_TX_NULL0_DONE_INT_EN BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2IMR (Offset 0x11E0) */ #define BIT_FS_CLI0_TX_NULL0_INT_EN BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT BIT(31) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI3_RX_UAPSDMD1_INT BIT(31) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT BIT(30) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI3_RX_UAPSDMD0_INT BIT(30) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT4_TRIPKT_OK_INT BIT(29) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI3_TRIGGER_PKT_INT BIT(29) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT4_RX_EOSP_OK_INT BIT(28) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI3_EOSP_INT BIT(28) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT BIT(27) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI2_RX_UAPSDMD1_INT BIT(27) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT BIT(26) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI2_RX_UAPSDMD0_INT BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT3_TRIPKT_OK_INT BIT(25) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI2_TRIGGER_PKT_INT BIT(25) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT3_RX_EOSP_OK_INT BIT(24) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI2_EOSP_INT BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT BIT(23) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI1_RX_UAPSDMD1_INT BIT(23) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT BIT(22) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI1_RX_UAPSDMD0_INT BIT(22) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT2_TRIPKT_OK_INT BIT(21) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI1_TRIGGER_PKT_INT BIT(21) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT2_RX_EOSP_OK_INT BIT(20) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI1_EOSP_INT BIT(20) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT BIT(19) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI0_RX_UAPSDMD1_INT BIT(19) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT BIT(18) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI0_RX_UAPSDMD0_INT BIT(18) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT1_TRIPKT_OK_INT BIT(17) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI0_TRIGGER_PKT_INT BIT(17) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT1_RX_EOSP_OK_INT BIT(16) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI0_EOSP_INT BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_NOA2_TSFT_BIT32_TOGGLE_INT BIT(9) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT BIT(9) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_NOA1_TSFT_BIT32_TOGGLE_INT BIT(8) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT4_TX_NULL1_DONE_INT BIT(7) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI3_TX_NULL1_INT BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT4_TX_NULL0_DONE_INT BIT(6) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI3_TX_NULL0_INT BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT3_TX_NULL1_DONE_INT BIT(5) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI2_TX_NULL1_INT BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT3_TX_NULL0_DONE_INT BIT(4) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI2_TX_NULL0_INT BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT2_TX_NULL1_DONE_INT BIT(3) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI1_TX_NULL1_INT BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT2_TX_NULL0_DONE_INT BIT(2) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI1_TX_NULL0_INT BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT1_TX_NULL1_DONE_INT BIT(1) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI0_TX_NULL1_INT BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_PORT1_TX_NULL0_DONE_INT BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_FT2ISR (Offset 0x11E4) */ #define BIT_FS_CLI0_TX_NULL0_INT BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MSG2 (Offset 0x11F0) */ #define BIT_SHIFT_FW_MSG2 0 #define BIT_MASK_FW_MSG2 0xffffffffL #define BIT_FW_MSG2(x) (((x) & BIT_MASK_FW_MSG2) << BIT_SHIFT_FW_MSG2) #define BITS_FW_MSG2 (BIT_MASK_FW_MSG2 << BIT_SHIFT_FW_MSG2) #define BIT_CLEAR_FW_MSG2(x) ((x) & (~BITS_FW_MSG2)) #define BIT_GET_FW_MSG2(x) (((x) >> BIT_SHIFT_FW_MSG2) & BIT_MASK_FW_MSG2) #define BIT_SET_FW_MSG2(x, v) (BIT_CLEAR_FW_MSG2(x) | BIT_FW_MSG2(v)) /* 2 REG_MSG3 (Offset 0x11F4) */ #define BIT_SHIFT_FW_MSG3 0 #define BIT_MASK_FW_MSG3 0xffffffffL #define BIT_FW_MSG3(x) (((x) & BIT_MASK_FW_MSG3) << BIT_SHIFT_FW_MSG3) #define BITS_FW_MSG3 (BIT_MASK_FW_MSG3 << BIT_SHIFT_FW_MSG3) #define BIT_CLEAR_FW_MSG3(x) ((x) & (~BITS_FW_MSG3)) #define BIT_GET_FW_MSG3(x) (((x) >> BIT_SHIFT_FW_MSG3) & BIT_MASK_FW_MSG3) #define BIT_SET_FW_MSG3(x, v) (BIT_CLEAR_FW_MSG3(x) | BIT_FW_MSG3(v)) /* 2 REG_MSG4 (Offset 0x11F8) */ #define BIT_SHIFT_FW_MSG4 0 #define BIT_MASK_FW_MSG4 0xffffffffL #define BIT_FW_MSG4(x) (((x) & BIT_MASK_FW_MSG4) << BIT_SHIFT_FW_MSG4) #define BITS_FW_MSG4 (BIT_MASK_FW_MSG4 << BIT_SHIFT_FW_MSG4) #define BIT_CLEAR_FW_MSG4(x) ((x) & (~BITS_FW_MSG4)) #define BIT_GET_FW_MSG4(x) (((x) >> BIT_SHIFT_FW_MSG4) & BIT_MASK_FW_MSG4) #define BIT_SET_FW_MSG4(x, v) (BIT_CLEAR_FW_MSG4(x) | BIT_FW_MSG4(v)) /* 2 REG_MSG5 (Offset 0x11FC) */ #define BIT_SHIFT_FW_MSG5 0 #define BIT_MASK_FW_MSG5 0xffffffffL #define BIT_FW_MSG5(x) (((x) & BIT_MASK_FW_MSG5) << BIT_SHIFT_FW_MSG5) #define BITS_FW_MSG5 (BIT_MASK_FW_MSG5 << BIT_SHIFT_FW_MSG5) #define BIT_CLEAR_FW_MSG5(x) ((x) & (~BITS_FW_MSG5)) #define BIT_GET_FW_MSG5(x) (((x) >> BIT_SHIFT_FW_MSG5) & BIT_MASK_FW_MSG5) #define BIT_SET_FW_MSG5(x, v) (BIT_CLEAR_FW_MSG5(x) | BIT_FW_MSG5(v)) /* 2 REG_DDMA_CH0SA (Offset 0x1200) */ #define BIT_SHIFT_DDMACH0_SA 0 #define BIT_MASK_DDMACH0_SA 0xffffffffL #define BIT_DDMACH0_SA(x) (((x) & BIT_MASK_DDMACH0_SA) << BIT_SHIFT_DDMACH0_SA) #define BITS_DDMACH0_SA (BIT_MASK_DDMACH0_SA << BIT_SHIFT_DDMACH0_SA) #define BIT_CLEAR_DDMACH0_SA(x) ((x) & (~BITS_DDMACH0_SA)) #define BIT_GET_DDMACH0_SA(x) \ (((x) >> BIT_SHIFT_DDMACH0_SA) & BIT_MASK_DDMACH0_SA) #define BIT_SET_DDMACH0_SA(x, v) (BIT_CLEAR_DDMACH0_SA(x) | BIT_DDMACH0_SA(v)) /* 2 REG_DDMA_CH0DA (Offset 0x1204) */ #define BIT_SHIFT_DDMACH0_DA 0 #define BIT_MASK_DDMACH0_DA 0xffffffffL #define BIT_DDMACH0_DA(x) (((x) & BIT_MASK_DDMACH0_DA) << BIT_SHIFT_DDMACH0_DA) #define BITS_DDMACH0_DA (BIT_MASK_DDMACH0_DA << BIT_SHIFT_DDMACH0_DA) #define BIT_CLEAR_DDMACH0_DA(x) ((x) & (~BITS_DDMACH0_DA)) #define BIT_GET_DDMACH0_DA(x) \ (((x) >> BIT_SHIFT_DDMACH0_DA) & BIT_MASK_DDMACH0_DA) #define BIT_SET_DDMACH0_DA(x, v) (BIT_CLEAR_DDMACH0_DA(x) | BIT_DDMACH0_DA(v)) /* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */ #define BIT_DDMACH0_OWN BIT(31) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */ #define BIT_DDMACH0_ERR_MON BIT(30) #endif #if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */ #define BIT_DDMACH0_IDMEM_ERR BIT(30) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */ #define BIT_DDMACH0_CHKSUM_EN BIT(29) #define BIT_DDMACH0_DA_W_DISABLE BIT(28) #define BIT_DDMACH0_CHKSUM_STS BIT(27) #define BIT_DDMACH0_DDMA_MODE BIT(26) #define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25) #define BIT_DDMACH0_CHKSUM_CONT BIT(24) #define BIT_SHIFT_DDMACH0_DLEN 0 #define BIT_MASK_DDMACH0_DLEN 0x3ffff #define BIT_DDMACH0_DLEN(x) \ (((x) & BIT_MASK_DDMACH0_DLEN) << BIT_SHIFT_DDMACH0_DLEN) #define BITS_DDMACH0_DLEN (BIT_MASK_DDMACH0_DLEN << BIT_SHIFT_DDMACH0_DLEN) #define BIT_CLEAR_DDMACH0_DLEN(x) ((x) & (~BITS_DDMACH0_DLEN)) #define BIT_GET_DDMACH0_DLEN(x) \ (((x) >> BIT_SHIFT_DDMACH0_DLEN) & BIT_MASK_DDMACH0_DLEN) #define BIT_SET_DDMACH0_DLEN(x, v) \ (BIT_CLEAR_DDMACH0_DLEN(x) | BIT_DDMACH0_DLEN(v)) /* 2 REG_DDMA_CH1SA (Offset 0x1210) */ #define BIT_SHIFT_DDMACH1_SA 0 #define BIT_MASK_DDMACH1_SA 0xffffffffL #define BIT_DDMACH1_SA(x) (((x) & BIT_MASK_DDMACH1_SA) << BIT_SHIFT_DDMACH1_SA) #define BITS_DDMACH1_SA (BIT_MASK_DDMACH1_SA << BIT_SHIFT_DDMACH1_SA) #define BIT_CLEAR_DDMACH1_SA(x) ((x) & (~BITS_DDMACH1_SA)) #define BIT_GET_DDMACH1_SA(x) \ (((x) >> BIT_SHIFT_DDMACH1_SA) & BIT_MASK_DDMACH1_SA) #define BIT_SET_DDMACH1_SA(x, v) (BIT_CLEAR_DDMACH1_SA(x) | BIT_DDMACH1_SA(v)) /* 2 REG_DDMA_CH1DA (Offset 0x1214) */ #define BIT_SHIFT_DDMACH1_DA 0 #define BIT_MASK_DDMACH1_DA 0xffffffffL #define BIT_DDMACH1_DA(x) (((x) & BIT_MASK_DDMACH1_DA) << BIT_SHIFT_DDMACH1_DA) #define BITS_DDMACH1_DA (BIT_MASK_DDMACH1_DA << BIT_SHIFT_DDMACH1_DA) #define BIT_CLEAR_DDMACH1_DA(x) ((x) & (~BITS_DDMACH1_DA)) #define BIT_GET_DDMACH1_DA(x) \ (((x) >> BIT_SHIFT_DDMACH1_DA) & BIT_MASK_DDMACH1_DA) #define BIT_SET_DDMACH1_DA(x, v) (BIT_CLEAR_DDMACH1_DA(x) | BIT_DDMACH1_DA(v)) /* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ #define BIT_DDMACH1_OWN BIT(31) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ #define BIT_DDMACH1_ERR_MON BIT(30) #endif #if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ #define BIT_DDMACH1_IDMEM_ERR BIT(30) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ #define BIT_DDMACH1_CHKSUM_EN BIT(29) #define BIT_DDMACH1_DA_W_DISABLE BIT(28) #define BIT_DDMACH1_CHKSUM_STS BIT(27) #define BIT_DDMACH1_DDMA_MODE BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ #define BIT_DDMACH1_RESET_CHKSUM_STS BIT(25) #define BIT_DDMACH1_CHKSUM_CONT BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ #define BIT_SHIFT_DDMACH1_DLEN 0 #define BIT_MASK_DDMACH1_DLEN 0x3ffff #define BIT_DDMACH1_DLEN(x) \ (((x) & BIT_MASK_DDMACH1_DLEN) << BIT_SHIFT_DDMACH1_DLEN) #define BITS_DDMACH1_DLEN (BIT_MASK_DDMACH1_DLEN << BIT_SHIFT_DDMACH1_DLEN) #define BIT_CLEAR_DDMACH1_DLEN(x) ((x) & (~BITS_DDMACH1_DLEN)) #define BIT_GET_DDMACH1_DLEN(x) \ (((x) >> BIT_SHIFT_DDMACH1_DLEN) & BIT_MASK_DDMACH1_DLEN) #define BIT_SET_DDMACH1_DLEN(x, v) \ (BIT_CLEAR_DDMACH1_DLEN(x) | BIT_DDMACH1_DLEN(v)) /* 2 REG_DDMA_CH2SA (Offset 0x1220) */ #define BIT_SHIFT_DDMACH2_SA 0 #define BIT_MASK_DDMACH2_SA 0xffffffffL #define BIT_DDMACH2_SA(x) (((x) & BIT_MASK_DDMACH2_SA) << BIT_SHIFT_DDMACH2_SA) #define BITS_DDMACH2_SA (BIT_MASK_DDMACH2_SA << BIT_SHIFT_DDMACH2_SA) #define BIT_CLEAR_DDMACH2_SA(x) ((x) & (~BITS_DDMACH2_SA)) #define BIT_GET_DDMACH2_SA(x) \ (((x) >> BIT_SHIFT_DDMACH2_SA) & BIT_MASK_DDMACH2_SA) #define BIT_SET_DDMACH2_SA(x, v) (BIT_CLEAR_DDMACH2_SA(x) | BIT_DDMACH2_SA(v)) /* 2 REG_DDMA_CH2DA (Offset 0x1224) */ #define BIT_SHIFT_DDMACH2_DA 0 #define BIT_MASK_DDMACH2_DA 0xffffffffL #define BIT_DDMACH2_DA(x) (((x) & BIT_MASK_DDMACH2_DA) << BIT_SHIFT_DDMACH2_DA) #define BITS_DDMACH2_DA (BIT_MASK_DDMACH2_DA << BIT_SHIFT_DDMACH2_DA) #define BIT_CLEAR_DDMACH2_DA(x) ((x) & (~BITS_DDMACH2_DA)) #define BIT_GET_DDMACH2_DA(x) \ (((x) >> BIT_SHIFT_DDMACH2_DA) & BIT_MASK_DDMACH2_DA) #define BIT_SET_DDMACH2_DA(x, v) (BIT_CLEAR_DDMACH2_DA(x) | BIT_DDMACH2_DA(v)) /* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ #define BIT_DDMACH2_OWN BIT(31) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ #define BIT_DDMACH2_ERR_MON BIT(30) #endif #if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ #define BIT_DDMACH2_IDMEM_ERR BIT(30) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ #define BIT_DDMACH2_CHKSUM_EN BIT(29) #define BIT_DDMACH2_DA_W_DISABLE BIT(28) #define BIT_DDMACH2_CHKSUM_STS BIT(27) #define BIT_DDMACH2_DDMA_MODE BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ #define BIT_DDMACH2_RESET_CHKSUM_STS BIT(25) #define BIT_DDMACH2_CHKSUM_CONT BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ #define BIT_SHIFT_DDMACH2_DLEN 0 #define BIT_MASK_DDMACH2_DLEN 0x3ffff #define BIT_DDMACH2_DLEN(x) \ (((x) & BIT_MASK_DDMACH2_DLEN) << BIT_SHIFT_DDMACH2_DLEN) #define BITS_DDMACH2_DLEN (BIT_MASK_DDMACH2_DLEN << BIT_SHIFT_DDMACH2_DLEN) #define BIT_CLEAR_DDMACH2_DLEN(x) ((x) & (~BITS_DDMACH2_DLEN)) #define BIT_GET_DDMACH2_DLEN(x) \ (((x) >> BIT_SHIFT_DDMACH2_DLEN) & BIT_MASK_DDMACH2_DLEN) #define BIT_SET_DDMACH2_DLEN(x, v) \ (BIT_CLEAR_DDMACH2_DLEN(x) | BIT_DDMACH2_DLEN(v)) /* 2 REG_DDMA_CH3SA (Offset 0x1230) */ #define BIT_SHIFT_DDMACH3_SA 0 #define BIT_MASK_DDMACH3_SA 0xffffffffL #define BIT_DDMACH3_SA(x) (((x) & BIT_MASK_DDMACH3_SA) << BIT_SHIFT_DDMACH3_SA) #define BITS_DDMACH3_SA (BIT_MASK_DDMACH3_SA << BIT_SHIFT_DDMACH3_SA) #define BIT_CLEAR_DDMACH3_SA(x) ((x) & (~BITS_DDMACH3_SA)) #define BIT_GET_DDMACH3_SA(x) \ (((x) >> BIT_SHIFT_DDMACH3_SA) & BIT_MASK_DDMACH3_SA) #define BIT_SET_DDMACH3_SA(x, v) (BIT_CLEAR_DDMACH3_SA(x) | BIT_DDMACH3_SA(v)) /* 2 REG_DDMA_CH3DA (Offset 0x1234) */ #define BIT_SHIFT_DDMACH3_DA 0 #define BIT_MASK_DDMACH3_DA 0xffffffffL #define BIT_DDMACH3_DA(x) (((x) & BIT_MASK_DDMACH3_DA) << BIT_SHIFT_DDMACH3_DA) #define BITS_DDMACH3_DA (BIT_MASK_DDMACH3_DA << BIT_SHIFT_DDMACH3_DA) #define BIT_CLEAR_DDMACH3_DA(x) ((x) & (~BITS_DDMACH3_DA)) #define BIT_GET_DDMACH3_DA(x) \ (((x) >> BIT_SHIFT_DDMACH3_DA) & BIT_MASK_DDMACH3_DA) #define BIT_SET_DDMACH3_DA(x, v) (BIT_CLEAR_DDMACH3_DA(x) | BIT_DDMACH3_DA(v)) /* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ #define BIT_DDMACH3_OWN BIT(31) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ #define BIT_DDMACH3_ERR_MON BIT(30) #endif #if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ #define BIT_DDMACH3_IDMEM_ERR BIT(30) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ #define BIT_DDMACH3_CHKSUM_EN BIT(29) #define BIT_DDMACH3_DA_W_DISABLE BIT(28) #define BIT_DDMACH3_CHKSUM_STS BIT(27) #define BIT_DDMACH3_DDMA_MODE BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ #define BIT_DDMACH3_RESET_CHKSUM_STS BIT(25) #define BIT_DDMACH3_CHKSUM_CONT BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ #define BIT_SHIFT_DDMACH3_DLEN 0 #define BIT_MASK_DDMACH3_DLEN 0x3ffff #define BIT_DDMACH3_DLEN(x) \ (((x) & BIT_MASK_DDMACH3_DLEN) << BIT_SHIFT_DDMACH3_DLEN) #define BITS_DDMACH3_DLEN (BIT_MASK_DDMACH3_DLEN << BIT_SHIFT_DDMACH3_DLEN) #define BIT_CLEAR_DDMACH3_DLEN(x) ((x) & (~BITS_DDMACH3_DLEN)) #define BIT_GET_DDMACH3_DLEN(x) \ (((x) >> BIT_SHIFT_DDMACH3_DLEN) & BIT_MASK_DDMACH3_DLEN) #define BIT_SET_DDMACH3_DLEN(x, v) \ (BIT_CLEAR_DDMACH3_DLEN(x) | BIT_DDMACH3_DLEN(v)) /* 2 REG_DDMA_CH4SA (Offset 0x1240) */ #define BIT_SHIFT_DDMACH4_SA 0 #define BIT_MASK_DDMACH4_SA 0xffffffffL #define BIT_DDMACH4_SA(x) (((x) & BIT_MASK_DDMACH4_SA) << BIT_SHIFT_DDMACH4_SA) #define BITS_DDMACH4_SA (BIT_MASK_DDMACH4_SA << BIT_SHIFT_DDMACH4_SA) #define BIT_CLEAR_DDMACH4_SA(x) ((x) & (~BITS_DDMACH4_SA)) #define BIT_GET_DDMACH4_SA(x) \ (((x) >> BIT_SHIFT_DDMACH4_SA) & BIT_MASK_DDMACH4_SA) #define BIT_SET_DDMACH4_SA(x, v) (BIT_CLEAR_DDMACH4_SA(x) | BIT_DDMACH4_SA(v)) /* 2 REG_DDMA_CH4DA (Offset 0x1244) */ #define BIT_SHIFT_DDMACH4_DA 0 #define BIT_MASK_DDMACH4_DA 0xffffffffL #define BIT_DDMACH4_DA(x) (((x) & BIT_MASK_DDMACH4_DA) << BIT_SHIFT_DDMACH4_DA) #define BITS_DDMACH4_DA (BIT_MASK_DDMACH4_DA << BIT_SHIFT_DDMACH4_DA) #define BIT_CLEAR_DDMACH4_DA(x) ((x) & (~BITS_DDMACH4_DA)) #define BIT_GET_DDMACH4_DA(x) \ (((x) >> BIT_SHIFT_DDMACH4_DA) & BIT_MASK_DDMACH4_DA) #define BIT_SET_DDMACH4_DA(x, v) (BIT_CLEAR_DDMACH4_DA(x) | BIT_DDMACH4_DA(v)) /* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ #define BIT_DDMACH4_OWN BIT(31) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ #define BIT_DDMACH4_ERR_MON BIT(30) #endif #if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ #define BIT_DDMACH4_IDMEM_ERR BIT(30) #define BIT_DDMACH5_IDMEM_ERR BIT(30) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ #define BIT_DDMACH4_CHKSUM_EN BIT(29) #define BIT_DDMACH4_DA_W_DISABLE BIT(28) #define BIT_DDMACH4_CHKSUM_STS BIT(27) #define BIT_DDMACH4_DDMA_MODE BIT(26) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ #define BIT_DDMACH4_RESET_CHKSUM_STS BIT(25) #define BIT_DDMACH5_RESET_CHKSUM_STS BIT(25) #define BIT_DDMACH4_CHKSUM_CONT BIT(24) #define BIT_DDMACH5_CHKSUM_CONT BIT(24) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ #define BIT_SHIFT_DDMACH4_DLEN 0 #define BIT_MASK_DDMACH4_DLEN 0x3ffff #define BIT_DDMACH4_DLEN(x) \ (((x) & BIT_MASK_DDMACH4_DLEN) << BIT_SHIFT_DDMACH4_DLEN) #define BITS_DDMACH4_DLEN (BIT_MASK_DDMACH4_DLEN << BIT_SHIFT_DDMACH4_DLEN) #define BIT_CLEAR_DDMACH4_DLEN(x) ((x) & (~BITS_DDMACH4_DLEN)) #define BIT_GET_DDMACH4_DLEN(x) \ (((x) >> BIT_SHIFT_DDMACH4_DLEN) & BIT_MASK_DDMACH4_DLEN) #define BIT_SET_DDMACH4_DLEN(x, v) \ (BIT_CLEAR_DDMACH4_DLEN(x) | BIT_DDMACH4_DLEN(v)) /* 2 REG_DDMA_CH5SA (Offset 0x1250) */ #define BIT_SHIFT_DDMACH5_SA 0 #define BIT_MASK_DDMACH5_SA 0xffffffffL #define BIT_DDMACH5_SA(x) (((x) & BIT_MASK_DDMACH5_SA) << BIT_SHIFT_DDMACH5_SA) #define BITS_DDMACH5_SA (BIT_MASK_DDMACH5_SA << BIT_SHIFT_DDMACH5_SA) #define BIT_CLEAR_DDMACH5_SA(x) ((x) & (~BITS_DDMACH5_SA)) #define BIT_GET_DDMACH5_SA(x) \ (((x) >> BIT_SHIFT_DDMACH5_SA) & BIT_MASK_DDMACH5_SA) #define BIT_SET_DDMACH5_SA(x, v) (BIT_CLEAR_DDMACH5_SA(x) | BIT_DDMACH5_SA(v)) /* 2 REG_DDMA_CH5DA (Offset 0x1254) */ #define BIT_DDMACH5_OWN BIT(31) #define BIT_DDMACH5_CHKSUM_EN BIT(29) #define BIT_DDMACH5_DA_W_DISABLE BIT(28) #define BIT_DDMACH5_CHKSUM_STS BIT(27) #define BIT_DDMACH5_DDMA_MODE BIT(26) #define BIT_SHIFT_DDMACH5_DA 0 #define BIT_MASK_DDMACH5_DA 0xffffffffL #define BIT_DDMACH5_DA(x) (((x) & BIT_MASK_DDMACH5_DA) << BIT_SHIFT_DDMACH5_DA) #define BITS_DDMACH5_DA (BIT_MASK_DDMACH5_DA << BIT_SHIFT_DDMACH5_DA) #define BIT_CLEAR_DDMACH5_DA(x) ((x) & (~BITS_DDMACH5_DA)) #define BIT_GET_DDMACH5_DA(x) \ (((x) >> BIT_SHIFT_DDMACH5_DA) & BIT_MASK_DDMACH5_DA) #define BIT_SET_DDMACH5_DA(x, v) (BIT_CLEAR_DDMACH5_DA(x) | BIT_DDMACH5_DA(v)) #define BIT_SHIFT_DDMACH5_DLEN 0 #define BIT_MASK_DDMACH5_DLEN 0x3ffff #define BIT_DDMACH5_DLEN(x) \ (((x) & BIT_MASK_DDMACH5_DLEN) << BIT_SHIFT_DDMACH5_DLEN) #define BITS_DDMACH5_DLEN (BIT_MASK_DDMACH5_DLEN << BIT_SHIFT_DDMACH5_DLEN) #define BIT_CLEAR_DDMACH5_DLEN(x) ((x) & (~BITS_DDMACH5_DLEN)) #define BIT_GET_DDMACH5_DLEN(x) \ (((x) >> BIT_SHIFT_DDMACH5_DLEN) & BIT_MASK_DDMACH5_DLEN) #define BIT_SET_DDMACH5_DLEN(x, v) \ (BIT_CLEAR_DDMACH5_DLEN(x) | BIT_DDMACH5_DLEN(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_REG_DDMA_CH5CTRL (Offset 0x1258) */ #define BIT_DDMACH5_ERR_MON BIT(30) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DDMA_INT_MSK (Offset 0x12E0) */ #define BIT_DDMACH5_MSK BIT(5) #define BIT_DDMACH4_MSK BIT(4) #define BIT_DDMACH3_MSK BIT(3) #define BIT_DDMACH2_MSK BIT(2) #define BIT_DDMACH1_MSK BIT(1) #define BIT_DDMACH0_MSK BIT(0) /* 2 REG_DDMA_CHSTATUS (Offset 0x12E8) */ #define BIT_DDMACH5_BUSY BIT(5) #define BIT_DDMACH4_BUSY BIT(4) #define BIT_DDMACH3_BUSY BIT(3) #define BIT_DDMACH2_BUSY BIT(2) #define BIT_DDMACH1_BUSY BIT(1) #define BIT_DDMACH0_BUSY BIT(0) /* 2 REG_DDMA_CHKSUM (Offset 0x12F0) */ #define BIT_SHIFT_IDDMA0_CHKSUM 0 #define BIT_MASK_IDDMA0_CHKSUM 0xffff #define BIT_IDDMA0_CHKSUM(x) \ (((x) & BIT_MASK_IDDMA0_CHKSUM) << BIT_SHIFT_IDDMA0_CHKSUM) #define BITS_IDDMA0_CHKSUM (BIT_MASK_IDDMA0_CHKSUM << BIT_SHIFT_IDDMA0_CHKSUM) #define BIT_CLEAR_IDDMA0_CHKSUM(x) ((x) & (~BITS_IDDMA0_CHKSUM)) #define BIT_GET_IDDMA0_CHKSUM(x) \ (((x) >> BIT_SHIFT_IDDMA0_CHKSUM) & BIT_MASK_IDDMA0_CHKSUM) #define BIT_SET_IDDMA0_CHKSUM(x, v) \ (BIT_CLEAR_IDDMA0_CHKSUM(x) | BIT_IDDMA0_CHKSUM(v)) /* 2 REG_DDMA_MONITOR (Offset 0x12FC) */ #define BIT_IDDMA0_PERMU_UNDERFLOW BIT(14) #define BIT_IDDMA0_FIFO_UNDERFLOW BIT(13) #define BIT_IDDMA0_FIFO_OVERFLOW BIT(12) #define BIT_CH5_ERR BIT(5) #define BIT_CH4_ERR BIT(4) #define BIT_CH3_ERR BIT(3) #define BIT_CH2_ERR BIT(2) #define BIT_CH1_ERR BIT(1) #define BIT_CH0_ERR BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_STC_INT_CS (Offset 0x1300) */ #define BIT_STC_INT_EN BIT(31) #define BIT_STC_INT_GRP_EN BIT(31) #define BIT_SHIFT_STC_INT_FLAG 16 #define BIT_MASK_STC_INT_FLAG 0xff #define BIT_STC_INT_FLAG(x) \ (((x) & BIT_MASK_STC_INT_FLAG) << BIT_SHIFT_STC_INT_FLAG) #define BITS_STC_INT_FLAG (BIT_MASK_STC_INT_FLAG << BIT_SHIFT_STC_INT_FLAG) #define BIT_CLEAR_STC_INT_FLAG(x) ((x) & (~BITS_STC_INT_FLAG)) #define BIT_GET_STC_INT_FLAG(x) \ (((x) >> BIT_SHIFT_STC_INT_FLAG) & BIT_MASK_STC_INT_FLAG) #define BIT_SET_STC_INT_FLAG(x, v) \ (BIT_CLEAR_STC_INT_FLAG(x) | BIT_STC_INT_FLAG(v)) #define BIT_SHIFT_STC_INT_IDX 8 #define BIT_MASK_STC_INT_IDX 0x7 #define BIT_STC_INT_IDX(x) \ (((x) & BIT_MASK_STC_INT_IDX) << BIT_SHIFT_STC_INT_IDX) #define BITS_STC_INT_IDX (BIT_MASK_STC_INT_IDX << BIT_SHIFT_STC_INT_IDX) #define BIT_CLEAR_STC_INT_IDX(x) ((x) & (~BITS_STC_INT_IDX)) #define BIT_GET_STC_INT_IDX(x) \ (((x) >> BIT_SHIFT_STC_INT_IDX) & BIT_MASK_STC_INT_IDX) #define BIT_SET_STC_INT_IDX(x, v) \ (BIT_CLEAR_STC_INT_IDX(x) | BIT_STC_INT_IDX(v)) #define BIT_SHIFT_STC_INT_EXPECT_LS 8 #define BIT_MASK_STC_INT_EXPECT_LS 0x3f #define BIT_STC_INT_EXPECT_LS(x) \ (((x) & BIT_MASK_STC_INT_EXPECT_LS) << BIT_SHIFT_STC_INT_EXPECT_LS) #define BITS_STC_INT_EXPECT_LS \ (BIT_MASK_STC_INT_EXPECT_LS << BIT_SHIFT_STC_INT_EXPECT_LS) #define BIT_CLEAR_STC_INT_EXPECT_LS(x) ((x) & (~BITS_STC_INT_EXPECT_LS)) #define BIT_GET_STC_INT_EXPECT_LS(x) \ (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS) & BIT_MASK_STC_INT_EXPECT_LS) #define BIT_SET_STC_INT_EXPECT_LS(x, v) \ (BIT_CLEAR_STC_INT_EXPECT_LS(x) | BIT_STC_INT_EXPECT_LS(v)) #define BIT_SHIFT_STC_INT_REALTIME_CS 0 #define BIT_MASK_STC_INT_REALTIME_CS 0x3f #define BIT_STC_INT_REALTIME_CS(x) \ (((x) & BIT_MASK_STC_INT_REALTIME_CS) << BIT_SHIFT_STC_INT_REALTIME_CS) #define BITS_STC_INT_REALTIME_CS \ (BIT_MASK_STC_INT_REALTIME_CS << BIT_SHIFT_STC_INT_REALTIME_CS) #define BIT_CLEAR_STC_INT_REALTIME_CS(x) ((x) & (~BITS_STC_INT_REALTIME_CS)) #define BIT_GET_STC_INT_REALTIME_CS(x) \ (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS) & BIT_MASK_STC_INT_REALTIME_CS) #define BIT_SET_STC_INT_REALTIME_CS(x, v) \ (BIT_CLEAR_STC_INT_REALTIME_CS(x) | BIT_STC_INT_REALTIME_CS(v)) #define BIT_SHIFT_STC_INT_EXPECT_CS 0 #define BIT_MASK_STC_INT_EXPECT_CS 0x3f #define BIT_STC_INT_EXPECT_CS(x) \ (((x) & BIT_MASK_STC_INT_EXPECT_CS) << BIT_SHIFT_STC_INT_EXPECT_CS) #define BITS_STC_INT_EXPECT_CS \ (BIT_MASK_STC_INT_EXPECT_CS << BIT_SHIFT_STC_INT_EXPECT_CS) #define BIT_CLEAR_STC_INT_EXPECT_CS(x) ((x) & (~BITS_STC_INT_EXPECT_CS)) #define BIT_GET_STC_INT_EXPECT_CS(x) \ (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS) & BIT_MASK_STC_INT_EXPECT_CS) #define BIT_SET_STC_INT_EXPECT_CS(x, v) \ (BIT_CLEAR_STC_INT_EXPECT_CS(x) | BIT_STC_INT_EXPECT_CS(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH4_ACH5_TXBD_NUM (Offset 0x130C) */ #define BIT_PCIE_ACH5_FLAG BIT(30) #define BIT_SHIFT_ACH5_DESC_MODE 28 #define BIT_MASK_ACH5_DESC_MODE 0x3 #define BIT_ACH5_DESC_MODE(x) \ (((x) & BIT_MASK_ACH5_DESC_MODE) << BIT_SHIFT_ACH5_DESC_MODE) #define BITS_ACH5_DESC_MODE \ (BIT_MASK_ACH5_DESC_MODE << BIT_SHIFT_ACH5_DESC_MODE) #define BIT_CLEAR_ACH5_DESC_MODE(x) ((x) & (~BITS_ACH5_DESC_MODE)) #define BIT_GET_ACH5_DESC_MODE(x) \ (((x) >> BIT_SHIFT_ACH5_DESC_MODE) & BIT_MASK_ACH5_DESC_MODE) #define BIT_SET_ACH5_DESC_MODE(x, v) \ (BIT_CLEAR_ACH5_DESC_MODE(x) | BIT_ACH5_DESC_MODE(v)) #define BIT_SHIFT_ACH5_DESC_NUM 16 #define BIT_MASK_ACH5_DESC_NUM 0xfff #define BIT_ACH5_DESC_NUM(x) \ (((x) & BIT_MASK_ACH5_DESC_NUM) << BIT_SHIFT_ACH5_DESC_NUM) #define BITS_ACH5_DESC_NUM (BIT_MASK_ACH5_DESC_NUM << BIT_SHIFT_ACH5_DESC_NUM) #define BIT_CLEAR_ACH5_DESC_NUM(x) ((x) & (~BITS_ACH5_DESC_NUM)) #define BIT_GET_ACH5_DESC_NUM(x) \ (((x) >> BIT_SHIFT_ACH5_DESC_NUM) & BIT_MASK_ACH5_DESC_NUM) #define BIT_SET_ACH5_DESC_NUM(x, v) \ (BIT_CLEAR_ACH5_DESC_NUM(x) | BIT_ACH5_DESC_NUM(v)) #define BIT_PCIE_ACH4_FLAG BIT(14) #define BIT_SHIFT_ACH4_DESC_MODE 12 #define BIT_MASK_ACH4_DESC_MODE 0x3 #define BIT_ACH4_DESC_MODE(x) \ (((x) & BIT_MASK_ACH4_DESC_MODE) << BIT_SHIFT_ACH4_DESC_MODE) #define BITS_ACH4_DESC_MODE \ (BIT_MASK_ACH4_DESC_MODE << BIT_SHIFT_ACH4_DESC_MODE) #define BIT_CLEAR_ACH4_DESC_MODE(x) ((x) & (~BITS_ACH4_DESC_MODE)) #define BIT_GET_ACH4_DESC_MODE(x) \ (((x) >> BIT_SHIFT_ACH4_DESC_MODE) & BIT_MASK_ACH4_DESC_MODE) #define BIT_SET_ACH4_DESC_MODE(x, v) \ (BIT_CLEAR_ACH4_DESC_MODE(x) | BIT_ACH4_DESC_MODE(v)) #define BIT_SHIFT_ACH4_DESC_NUM 0 #define BIT_MASK_ACH4_DESC_NUM 0xfff #define BIT_ACH4_DESC_NUM(x) \ (((x) & BIT_MASK_ACH4_DESC_NUM) << BIT_SHIFT_ACH4_DESC_NUM) #define BITS_ACH4_DESC_NUM (BIT_MASK_ACH4_DESC_NUM << BIT_SHIFT_ACH4_DESC_NUM) #define BIT_CLEAR_ACH4_DESC_NUM(x) ((x) & (~BITS_ACH4_DESC_NUM)) #define BIT_GET_ACH4_DESC_NUM(x) \ (((x) >> BIT_SHIFT_ACH4_DESC_NUM) & BIT_MASK_ACH4_DESC_NUM) #define BIT_SET_ACH4_DESC_NUM(x, v) \ (BIT_CLEAR_ACH4_DESC_NUM(x) | BIT_ACH4_DESC_NUM(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_CMU_DLY_CTRL (Offset 0x1310) */ #define BIT_CMU_DLY_EN BIT(31) #define BIT_CMU_DLY_MODE BIT(30) #define BIT_SHIFT_CMU_DLY_PRE_DIV 0 #define BIT_MASK_CMU_DLY_PRE_DIV 0xff #define BIT_CMU_DLY_PRE_DIV(x) \ (((x) & BIT_MASK_CMU_DLY_PRE_DIV) << BIT_SHIFT_CMU_DLY_PRE_DIV) #define BITS_CMU_DLY_PRE_DIV \ (BIT_MASK_CMU_DLY_PRE_DIV << BIT_SHIFT_CMU_DLY_PRE_DIV) #define BIT_CLEAR_CMU_DLY_PRE_DIV(x) ((x) & (~BITS_CMU_DLY_PRE_DIV)) #define BIT_GET_CMU_DLY_PRE_DIV(x) \ (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV) & BIT_MASK_CMU_DLY_PRE_DIV) #define BIT_SET_CMU_DLY_PRE_DIV(x, v) \ (BIT_CLEAR_CMU_DLY_PRE_DIV(x) | BIT_CMU_DLY_PRE_DIV(v)) /* 2 REG_CMU_DLY_CFG (Offset 0x1314) */ #define BIT_SHIFT_CMU_DLY_LTR_A2I 24 #define BIT_MASK_CMU_DLY_LTR_A2I 0xff #define BIT_CMU_DLY_LTR_A2I(x) \ (((x) & BIT_MASK_CMU_DLY_LTR_A2I) << BIT_SHIFT_CMU_DLY_LTR_A2I) #define BITS_CMU_DLY_LTR_A2I \ (BIT_MASK_CMU_DLY_LTR_A2I << BIT_SHIFT_CMU_DLY_LTR_A2I) #define BIT_CLEAR_CMU_DLY_LTR_A2I(x) ((x) & (~BITS_CMU_DLY_LTR_A2I)) #define BIT_GET_CMU_DLY_LTR_A2I(x) \ (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I) & BIT_MASK_CMU_DLY_LTR_A2I) #define BIT_SET_CMU_DLY_LTR_A2I(x, v) \ (BIT_CLEAR_CMU_DLY_LTR_A2I(x) | BIT_CMU_DLY_LTR_A2I(v)) #define BIT_SHIFT_CMU_DLY_LTR_I2A 16 #define BIT_MASK_CMU_DLY_LTR_I2A 0xff #define BIT_CMU_DLY_LTR_I2A(x) \ (((x) & BIT_MASK_CMU_DLY_LTR_I2A) << BIT_SHIFT_CMU_DLY_LTR_I2A) #define BITS_CMU_DLY_LTR_I2A \ (BIT_MASK_CMU_DLY_LTR_I2A << BIT_SHIFT_CMU_DLY_LTR_I2A) #define BIT_CLEAR_CMU_DLY_LTR_I2A(x) ((x) & (~BITS_CMU_DLY_LTR_I2A)) #define BIT_GET_CMU_DLY_LTR_I2A(x) \ (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A) & BIT_MASK_CMU_DLY_LTR_I2A) #define BIT_SET_CMU_DLY_LTR_I2A(x, v) \ (BIT_CLEAR_CMU_DLY_LTR_I2A(x) | BIT_CMU_DLY_LTR_I2A(v)) #define BIT_SHIFT_CMU_DLY_LTR_IDLE 8 #define BIT_MASK_CMU_DLY_LTR_IDLE 0xff #define BIT_CMU_DLY_LTR_IDLE(x) \ (((x) & BIT_MASK_CMU_DLY_LTR_IDLE) << BIT_SHIFT_CMU_DLY_LTR_IDLE) #define BITS_CMU_DLY_LTR_IDLE \ (BIT_MASK_CMU_DLY_LTR_IDLE << BIT_SHIFT_CMU_DLY_LTR_IDLE) #define BIT_CLEAR_CMU_DLY_LTR_IDLE(x) ((x) & (~BITS_CMU_DLY_LTR_IDLE)) #define BIT_GET_CMU_DLY_LTR_IDLE(x) \ (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE) & BIT_MASK_CMU_DLY_LTR_IDLE) #define BIT_SET_CMU_DLY_LTR_IDLE(x, v) \ (BIT_CLEAR_CMU_DLY_LTR_IDLE(x) | BIT_CMU_DLY_LTR_IDLE(v)) #define BIT_SHIFT_CMU_DLY_LTR_ACT 0 #define BIT_MASK_CMU_DLY_LTR_ACT 0xff #define BIT_CMU_DLY_LTR_ACT(x) \ (((x) & BIT_MASK_CMU_DLY_LTR_ACT) << BIT_SHIFT_CMU_DLY_LTR_ACT) #define BITS_CMU_DLY_LTR_ACT \ (BIT_MASK_CMU_DLY_LTR_ACT << BIT_SHIFT_CMU_DLY_LTR_ACT) #define BIT_CLEAR_CMU_DLY_LTR_ACT(x) ((x) & (~BITS_CMU_DLY_LTR_ACT)) #define BIT_GET_CMU_DLY_LTR_ACT(x) \ (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT) & BIT_MASK_CMU_DLY_LTR_ACT) #define BIT_SET_CMU_DLY_LTR_ACT(x, v) \ (BIT_CLEAR_CMU_DLY_LTR_ACT(x) | BIT_CMU_DLY_LTR_ACT(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FWCMDQ_TXBD_IDX (Offset 0x1318) */ #define BIT_SHIFT_FWCMDQ_HW_IDX 16 #define BIT_MASK_FWCMDQ_HW_IDX 0xfff #define BIT_FWCMDQ_HW_IDX(x) \ (((x) & BIT_MASK_FWCMDQ_HW_IDX) << BIT_SHIFT_FWCMDQ_HW_IDX) #define BITS_FWCMDQ_HW_IDX (BIT_MASK_FWCMDQ_HW_IDX << BIT_SHIFT_FWCMDQ_HW_IDX) #define BIT_CLEAR_FWCMDQ_HW_IDX(x) ((x) & (~BITS_FWCMDQ_HW_IDX)) #define BIT_GET_FWCMDQ_HW_IDX(x) \ (((x) >> BIT_SHIFT_FWCMDQ_HW_IDX) & BIT_MASK_FWCMDQ_HW_IDX) #define BIT_SET_FWCMDQ_HW_IDX(x, v) \ (BIT_CLEAR_FWCMDQ_HW_IDX(x) | BIT_FWCMDQ_HW_IDX(v)) #define BIT_SHIFT_FWCMDQ_HOST_IDX 0 #define BIT_MASK_FWCMDQ_HOST_IDX 0xfff #define BIT_FWCMDQ_HOST_IDX(x) \ (((x) & BIT_MASK_FWCMDQ_HOST_IDX) << BIT_SHIFT_FWCMDQ_HOST_IDX) #define BITS_FWCMDQ_HOST_IDX \ (BIT_MASK_FWCMDQ_HOST_IDX << BIT_SHIFT_FWCMDQ_HOST_IDX) #define BIT_CLEAR_FWCMDQ_HOST_IDX(x) ((x) & (~BITS_FWCMDQ_HOST_IDX)) #define BIT_GET_FWCMDQ_HOST_IDX(x) \ (((x) >> BIT_SHIFT_FWCMDQ_HOST_IDX) & BIT_MASK_FWCMDQ_HOST_IDX) #define BIT_SET_FWCMDQ_HOST_IDX(x, v) \ (BIT_CLEAR_FWCMDQ_HOST_IDX(x) | BIT_FWCMDQ_HOST_IDX(v)) /* 2 REG_P0HI8Q_TXBD_IDX (Offset 0x131C) */ #define BIT_SHIFT_P0HI8Q_HW_IDX 16 #define BIT_MASK_P0HI8Q_HW_IDX 0xfff #define BIT_P0HI8Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI8Q_HW_IDX) << BIT_SHIFT_P0HI8Q_HW_IDX) #define BITS_P0HI8Q_HW_IDX (BIT_MASK_P0HI8Q_HW_IDX << BIT_SHIFT_P0HI8Q_HW_IDX) #define BIT_CLEAR_P0HI8Q_HW_IDX(x) ((x) & (~BITS_P0HI8Q_HW_IDX)) #define BIT_GET_P0HI8Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI8Q_HW_IDX) & BIT_MASK_P0HI8Q_HW_IDX) #define BIT_SET_P0HI8Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI8Q_HW_IDX(x) | BIT_P0HI8Q_HW_IDX(v)) #define BIT_SHIFT_P0HI8Q_HOST_IDX 0 #define BIT_MASK_P0HI8Q_HOST_IDX 0xfff #define BIT_P0HI8Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI8Q_HOST_IDX) << BIT_SHIFT_P0HI8Q_HOST_IDX) #define BITS_P0HI8Q_HOST_IDX \ (BIT_MASK_P0HI8Q_HOST_IDX << BIT_SHIFT_P0HI8Q_HOST_IDX) #define BIT_CLEAR_P0HI8Q_HOST_IDX(x) ((x) & (~BITS_P0HI8Q_HOST_IDX)) #define BIT_GET_P0HI8Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI8Q_HOST_IDX) & BIT_MASK_P0HI8Q_HOST_IDX) #define BIT_SET_P0HI8Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI8Q_HOST_IDX(x) | BIT_P0HI8Q_HOST_IDX(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_H2CQ_TXBD_DESA (Offset 0x1320) */ #define BIT_SHIFT_H2CQ_TXBD_DESA 0 #define BIT_MASK_H2CQ_TXBD_DESA 0xffffffffffffffffL #define BIT_H2CQ_TXBD_DESA(x) \ (((x) & BIT_MASK_H2CQ_TXBD_DESA) << BIT_SHIFT_H2CQ_TXBD_DESA) #define BITS_H2CQ_TXBD_DESA \ (BIT_MASK_H2CQ_TXBD_DESA << BIT_SHIFT_H2CQ_TXBD_DESA) #define BIT_CLEAR_H2CQ_TXBD_DESA(x) ((x) & (~BITS_H2CQ_TXBD_DESA)) #define BIT_GET_H2CQ_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA) & BIT_MASK_H2CQ_TXBD_DESA) #define BIT_SET_H2CQ_TXBD_DESA(x, v) \ (BIT_CLEAR_H2CQ_TXBD_DESA(x) | BIT_H2CQ_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_H2CQ_TXBD_DESA_L (Offset 0x1320) */ #define BIT_SHIFT_H2CQ_TXBD_DESA_L 0 #define BIT_MASK_H2CQ_TXBD_DESA_L 0xffffffffL #define BIT_H2CQ_TXBD_DESA_L(x) \ (((x) & BIT_MASK_H2CQ_TXBD_DESA_L) << BIT_SHIFT_H2CQ_TXBD_DESA_L) #define BITS_H2CQ_TXBD_DESA_L \ (BIT_MASK_H2CQ_TXBD_DESA_L << BIT_SHIFT_H2CQ_TXBD_DESA_L) #define BIT_CLEAR_H2CQ_TXBD_DESA_L(x) ((x) & (~BITS_H2CQ_TXBD_DESA_L)) #define BIT_GET_H2CQ_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_L) & BIT_MASK_H2CQ_TXBD_DESA_L) #define BIT_SET_H2CQ_TXBD_DESA_L(x, v) \ (BIT_CLEAR_H2CQ_TXBD_DESA_L(x) | BIT_H2CQ_TXBD_DESA_L(v)) /* 2 REG_H2CQ_TXBD_DESA_H (Offset 0x1324) */ #define BIT_SHIFT_H2CQ_TXBD_DESA_H 0 #define BIT_MASK_H2CQ_TXBD_DESA_H 0xffffffffL #define BIT_H2CQ_TXBD_DESA_H(x) \ (((x) & BIT_MASK_H2CQ_TXBD_DESA_H) << BIT_SHIFT_H2CQ_TXBD_DESA_H) #define BITS_H2CQ_TXBD_DESA_H \ (BIT_MASK_H2CQ_TXBD_DESA_H << BIT_SHIFT_H2CQ_TXBD_DESA_H) #define BIT_CLEAR_H2CQ_TXBD_DESA_H(x) ((x) & (~BITS_H2CQ_TXBD_DESA_H)) #define BIT_GET_H2CQ_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_H) & BIT_MASK_H2CQ_TXBD_DESA_H) #define BIT_SET_H2CQ_TXBD_DESA_H(x, v) \ (BIT_CLEAR_H2CQ_TXBD_DESA_H(x) | BIT_H2CQ_TXBD_DESA_H(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ #define BIT_HCI_H2CQ_FLAG BIT(14) #endif #if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ #define BIT_PCIE_H2CQ_FLAG BIT(14) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ #define BIT_SHIFT_H2CQ_DESC_MODE 12 #define BIT_MASK_H2CQ_DESC_MODE 0x3 #define BIT_H2CQ_DESC_MODE(x) \ (((x) & BIT_MASK_H2CQ_DESC_MODE) << BIT_SHIFT_H2CQ_DESC_MODE) #define BITS_H2CQ_DESC_MODE \ (BIT_MASK_H2CQ_DESC_MODE << BIT_SHIFT_H2CQ_DESC_MODE) #define BIT_CLEAR_H2CQ_DESC_MODE(x) ((x) & (~BITS_H2CQ_DESC_MODE)) #define BIT_GET_H2CQ_DESC_MODE(x) \ (((x) >> BIT_SHIFT_H2CQ_DESC_MODE) & BIT_MASK_H2CQ_DESC_MODE) #define BIT_SET_H2CQ_DESC_MODE(x, v) \ (BIT_CLEAR_H2CQ_DESC_MODE(x) | BIT_H2CQ_DESC_MODE(v)) #define BIT_SHIFT_H2CQ_DESC_NUM 0 #define BIT_MASK_H2CQ_DESC_NUM 0xfff #define BIT_H2CQ_DESC_NUM(x) \ (((x) & BIT_MASK_H2CQ_DESC_NUM) << BIT_SHIFT_H2CQ_DESC_NUM) #define BITS_H2CQ_DESC_NUM (BIT_MASK_H2CQ_DESC_NUM << BIT_SHIFT_H2CQ_DESC_NUM) #define BIT_CLEAR_H2CQ_DESC_NUM(x) ((x) & (~BITS_H2CQ_DESC_NUM)) #define BIT_GET_H2CQ_DESC_NUM(x) \ (((x) >> BIT_SHIFT_H2CQ_DESC_NUM) & BIT_MASK_H2CQ_DESC_NUM) #define BIT_SET_H2CQ_DESC_NUM(x, v) \ (BIT_CLEAR_H2CQ_DESC_NUM(x) | BIT_H2CQ_DESC_NUM(v)) /* 2 REG_H2CQ_TXBD_IDX (Offset 0x132C) */ #define BIT_SHIFT_H2CQ_HW_IDX 16 #define BIT_MASK_H2CQ_HW_IDX 0xfff #define BIT_H2CQ_HW_IDX(x) \ (((x) & BIT_MASK_H2CQ_HW_IDX) << BIT_SHIFT_H2CQ_HW_IDX) #define BITS_H2CQ_HW_IDX (BIT_MASK_H2CQ_HW_IDX << BIT_SHIFT_H2CQ_HW_IDX) #define BIT_CLEAR_H2CQ_HW_IDX(x) ((x) & (~BITS_H2CQ_HW_IDX)) #define BIT_GET_H2CQ_HW_IDX(x) \ (((x) >> BIT_SHIFT_H2CQ_HW_IDX) & BIT_MASK_H2CQ_HW_IDX) #define BIT_SET_H2CQ_HW_IDX(x, v) \ (BIT_CLEAR_H2CQ_HW_IDX(x) | BIT_H2CQ_HW_IDX(v)) #define BIT_SHIFT_H2CQ_HOST_IDX 0 #define BIT_MASK_H2CQ_HOST_IDX 0xfff #define BIT_H2CQ_HOST_IDX(x) \ (((x) & BIT_MASK_H2CQ_HOST_IDX) << BIT_SHIFT_H2CQ_HOST_IDX) #define BITS_H2CQ_HOST_IDX (BIT_MASK_H2CQ_HOST_IDX << BIT_SHIFT_H2CQ_HOST_IDX) #define BIT_CLEAR_H2CQ_HOST_IDX(x) ((x) & (~BITS_H2CQ_HOST_IDX)) #define BIT_GET_H2CQ_HOST_IDX(x) \ (((x) >> BIT_SHIFT_H2CQ_HOST_IDX) & BIT_MASK_H2CQ_HOST_IDX) #define BIT_SET_H2CQ_HOST_IDX(x, v) \ (BIT_CLEAR_H2CQ_HOST_IDX(x) | BIT_H2CQ_HOST_IDX(v)) /* 2 REG_H2CQ_CSR (Offset 0x1330) */ #define BIT_H2CQ_FULL BIT(31) #define BIT_CLR_H2CQ_HOST_IDX BIT(16) #define BIT_CLR_H2CQ_HW_IDX BIT(8) #define BIT_STOP_H2CQ BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI9Q_TXBD_IDX (Offset 0x1334) */ #define BIT_SHIFT_P0HI9Q_HW_IDX 16 #define BIT_MASK_P0HI9Q_HW_IDX 0xfff #define BIT_P0HI9Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI9Q_HW_IDX) << BIT_SHIFT_P0HI9Q_HW_IDX) #define BITS_P0HI9Q_HW_IDX (BIT_MASK_P0HI9Q_HW_IDX << BIT_SHIFT_P0HI9Q_HW_IDX) #define BIT_CLEAR_P0HI9Q_HW_IDX(x) ((x) & (~BITS_P0HI9Q_HW_IDX)) #define BIT_GET_P0HI9Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI9Q_HW_IDX) & BIT_MASK_P0HI9Q_HW_IDX) #define BIT_SET_P0HI9Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI9Q_HW_IDX(x) | BIT_P0HI9Q_HW_IDX(v)) #define BIT_SHIFT_P0HI9Q_HOST_IDX 0 #define BIT_MASK_P0HI9Q_HOST_IDX 0xfff #define BIT_P0HI9Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI9Q_HOST_IDX) << BIT_SHIFT_P0HI9Q_HOST_IDX) #define BITS_P0HI9Q_HOST_IDX \ (BIT_MASK_P0HI9Q_HOST_IDX << BIT_SHIFT_P0HI9Q_HOST_IDX) #define BIT_CLEAR_P0HI9Q_HOST_IDX(x) ((x) & (~BITS_P0HI9Q_HOST_IDX)) #define BIT_GET_P0HI9Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI9Q_HOST_IDX) & BIT_MASK_P0HI9Q_HOST_IDX) #define BIT_SET_P0HI9Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI9Q_HOST_IDX(x) | BIT_P0HI9Q_HOST_IDX(v)) /* 2 REG_P0HI10Q_TXBD_IDX (Offset 0x1338) */ #define BIT_SHIFT_P0HI10Q_HW_IDX 16 #define BIT_MASK_P0HI10Q_HW_IDX 0xfff #define BIT_P0HI10Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI10Q_HW_IDX) << BIT_SHIFT_P0HI10Q_HW_IDX) #define BITS_P0HI10Q_HW_IDX \ (BIT_MASK_P0HI10Q_HW_IDX << BIT_SHIFT_P0HI10Q_HW_IDX) #define BIT_CLEAR_P0HI10Q_HW_IDX(x) ((x) & (~BITS_P0HI10Q_HW_IDX)) #define BIT_GET_P0HI10Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI10Q_HW_IDX) & BIT_MASK_P0HI10Q_HW_IDX) #define BIT_SET_P0HI10Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI10Q_HW_IDX(x) | BIT_P0HI10Q_HW_IDX(v)) #define BIT_SHIFT_P0HI10Q_HOST_IDX 0 #define BIT_MASK_P0HI10Q_HOST_IDX 0xfff #define BIT_P0HI10Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI10Q_HOST_IDX) << BIT_SHIFT_P0HI10Q_HOST_IDX) #define BITS_P0HI10Q_HOST_IDX \ (BIT_MASK_P0HI10Q_HOST_IDX << BIT_SHIFT_P0HI10Q_HOST_IDX) #define BIT_CLEAR_P0HI10Q_HOST_IDX(x) ((x) & (~BITS_P0HI10Q_HOST_IDX)) #define BIT_GET_P0HI10Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI10Q_HOST_IDX) & BIT_MASK_P0HI10Q_HOST_IDX) #define BIT_SET_P0HI10Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI10Q_HOST_IDX(x) | BIT_P0HI10Q_HOST_IDX(v)) /* 2 REG_P0HI11Q_TXBD_IDX (Offset 0x133C) */ #define BIT_SHIFT_P0HI11Q_HW_IDX 16 #define BIT_MASK_P0HI11Q_HW_IDX 0xfff #define BIT_P0HI11Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI11Q_HW_IDX) << BIT_SHIFT_P0HI11Q_HW_IDX) #define BITS_P0HI11Q_HW_IDX \ (BIT_MASK_P0HI11Q_HW_IDX << BIT_SHIFT_P0HI11Q_HW_IDX) #define BIT_CLEAR_P0HI11Q_HW_IDX(x) ((x) & (~BITS_P0HI11Q_HW_IDX)) #define BIT_GET_P0HI11Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI11Q_HW_IDX) & BIT_MASK_P0HI11Q_HW_IDX) #define BIT_SET_P0HI11Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI11Q_HW_IDX(x) | BIT_P0HI11Q_HW_IDX(v)) #define BIT_SHIFT_P0HI11Q_HOST_IDX 0 #define BIT_MASK_P0HI11Q_HOST_IDX 0xfff #define BIT_P0HI11Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI11Q_HOST_IDX) << BIT_SHIFT_P0HI11Q_HOST_IDX) #define BITS_P0HI11Q_HOST_IDX \ (BIT_MASK_P0HI11Q_HOST_IDX << BIT_SHIFT_P0HI11Q_HOST_IDX) #define BIT_CLEAR_P0HI11Q_HOST_IDX(x) ((x) & (~BITS_P0HI11Q_HOST_IDX)) #define BIT_GET_P0HI11Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI11Q_HOST_IDX) & BIT_MASK_P0HI11Q_HOST_IDX) #define BIT_SET_P0HI11Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI11Q_HOST_IDX(x) | BIT_P0HI11Q_HOST_IDX(v)) /* 2 REG_P0HI12Q_TXBD_IDX (Offset 0x1340) */ #define BIT_SHIFT_P0HI12Q_HW_IDX 16 #define BIT_MASK_P0HI12Q_HW_IDX 0xfff #define BIT_P0HI12Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI12Q_HW_IDX) << BIT_SHIFT_P0HI12Q_HW_IDX) #define BITS_P0HI12Q_HW_IDX \ (BIT_MASK_P0HI12Q_HW_IDX << BIT_SHIFT_P0HI12Q_HW_IDX) #define BIT_CLEAR_P0HI12Q_HW_IDX(x) ((x) & (~BITS_P0HI12Q_HW_IDX)) #define BIT_GET_P0HI12Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI12Q_HW_IDX) & BIT_MASK_P0HI12Q_HW_IDX) #define BIT_SET_P0HI12Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI12Q_HW_IDX(x) | BIT_P0HI12Q_HW_IDX(v)) #define BIT_SHIFT_P0HI12Q_HOST_IDX 0 #define BIT_MASK_P0HI12Q_HOST_IDX 0xfff #define BIT_P0HI12Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI12Q_HOST_IDX) << BIT_SHIFT_P0HI12Q_HOST_IDX) #define BITS_P0HI12Q_HOST_IDX \ (BIT_MASK_P0HI12Q_HOST_IDX << BIT_SHIFT_P0HI12Q_HOST_IDX) #define BIT_CLEAR_P0HI12Q_HOST_IDX(x) ((x) & (~BITS_P0HI12Q_HOST_IDX)) #define BIT_GET_P0HI12Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI12Q_HOST_IDX) & BIT_MASK_P0HI12Q_HOST_IDX) #define BIT_SET_P0HI12Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI12Q_HOST_IDX(x) | BIT_P0HI12Q_HOST_IDX(v)) /* 2 REG_P0HI13Q_TXBD_IDX (Offset 0x1344) */ #define BIT_SHIFT_P0HI13Q_HW_IDX 16 #define BIT_MASK_P0HI13Q_HW_IDX 0xfff #define BIT_P0HI13Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI13Q_HW_IDX) << BIT_SHIFT_P0HI13Q_HW_IDX) #define BITS_P0HI13Q_HW_IDX \ (BIT_MASK_P0HI13Q_HW_IDX << BIT_SHIFT_P0HI13Q_HW_IDX) #define BIT_CLEAR_P0HI13Q_HW_IDX(x) ((x) & (~BITS_P0HI13Q_HW_IDX)) #define BIT_GET_P0HI13Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI13Q_HW_IDX) & BIT_MASK_P0HI13Q_HW_IDX) #define BIT_SET_P0HI13Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI13Q_HW_IDX(x) | BIT_P0HI13Q_HW_IDX(v)) #define BIT_SHIFT_P0HI13Q_HOST_IDX 0 #define BIT_MASK_P0HI13Q_HOST_IDX 0xfff #define BIT_P0HI13Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI13Q_HOST_IDX) << BIT_SHIFT_P0HI13Q_HOST_IDX) #define BITS_P0HI13Q_HOST_IDX \ (BIT_MASK_P0HI13Q_HOST_IDX << BIT_SHIFT_P0HI13Q_HOST_IDX) #define BIT_CLEAR_P0HI13Q_HOST_IDX(x) ((x) & (~BITS_P0HI13Q_HOST_IDX)) #define BIT_GET_P0HI13Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI13Q_HOST_IDX) & BIT_MASK_P0HI13Q_HOST_IDX) #define BIT_SET_P0HI13Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI13Q_HOST_IDX(x) | BIT_P0HI13Q_HOST_IDX(v)) /* 2 REG_P0HI14Q_TXBD_IDX (Offset 0x1348) */ #define BIT_SHIFT_P0HI14Q_HW_IDX 16 #define BIT_MASK_P0HI14Q_HW_IDX 0xfff #define BIT_P0HI14Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI14Q_HW_IDX) << BIT_SHIFT_P0HI14Q_HW_IDX) #define BITS_P0HI14Q_HW_IDX \ (BIT_MASK_P0HI14Q_HW_IDX << BIT_SHIFT_P0HI14Q_HW_IDX) #define BIT_CLEAR_P0HI14Q_HW_IDX(x) ((x) & (~BITS_P0HI14Q_HW_IDX)) #define BIT_GET_P0HI14Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI14Q_HW_IDX) & BIT_MASK_P0HI14Q_HW_IDX) #define BIT_SET_P0HI14Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI14Q_HW_IDX(x) | BIT_P0HI14Q_HW_IDX(v)) #define BIT_SHIFT_P0HI14Q_HOST_IDX 0 #define BIT_MASK_P0HI14Q_HOST_IDX 0xfff #define BIT_P0HI14Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI14Q_HOST_IDX) << BIT_SHIFT_P0HI14Q_HOST_IDX) #define BITS_P0HI14Q_HOST_IDX \ (BIT_MASK_P0HI14Q_HOST_IDX << BIT_SHIFT_P0HI14Q_HOST_IDX) #define BIT_CLEAR_P0HI14Q_HOST_IDX(x) ((x) & (~BITS_P0HI14Q_HOST_IDX)) #define BIT_GET_P0HI14Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI14Q_HOST_IDX) & BIT_MASK_P0HI14Q_HOST_IDX) #define BIT_SET_P0HI14Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI14Q_HOST_IDX(x) | BIT_P0HI14Q_HOST_IDX(v)) /* 2 REG_P0HI15Q_TXBD_IDX (Offset 0x134C) */ #define BIT_SHIFT_P0HI15Q_HW_IDX 16 #define BIT_MASK_P0HI15Q_HW_IDX 0xfff #define BIT_P0HI15Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI15Q_HW_IDX) << BIT_SHIFT_P0HI15Q_HW_IDX) #define BITS_P0HI15Q_HW_IDX \ (BIT_MASK_P0HI15Q_HW_IDX << BIT_SHIFT_P0HI15Q_HW_IDX) #define BIT_CLEAR_P0HI15Q_HW_IDX(x) ((x) & (~BITS_P0HI15Q_HW_IDX)) #define BIT_GET_P0HI15Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI15Q_HW_IDX) & BIT_MASK_P0HI15Q_HW_IDX) #define BIT_SET_P0HI15Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI15Q_HW_IDX(x) | BIT_P0HI15Q_HW_IDX(v)) #define BIT_SHIFT_P0HI15Q_HOST_IDX 0 #define BIT_MASK_P0HI15Q_HOST_IDX 0xfff #define BIT_P0HI15Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI15Q_HOST_IDX) << BIT_SHIFT_P0HI15Q_HOST_IDX) #define BITS_P0HI15Q_HOST_IDX \ (BIT_MASK_P0HI15Q_HOST_IDX << BIT_SHIFT_P0HI15Q_HOST_IDX) #define BIT_CLEAR_P0HI15Q_HOST_IDX(x) ((x) & (~BITS_P0HI15Q_HOST_IDX)) #define BIT_GET_P0HI15Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI15Q_HOST_IDX) & BIT_MASK_P0HI15Q_HOST_IDX) #define BIT_SET_P0HI15Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI15Q_HOST_IDX(x) | BIT_P0HI15Q_HOST_IDX(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ #define BIT_AXI_RXDMA_TIMEOUT_RE BIT(21) #define BIT_AXI_TXDMA_TIMEOUT_RE BIT(20) #define BIT_AXI_DECERR_W_RE BIT(19) #define BIT_AXI_DECERR_R_RE BIT(18) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ #define BIT_CHANGE_PCIE_SPEED BIT(18) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ #define BIT_AXI_SLVERR_W_RE BIT(17) #define BIT_AXI_SLVERR_R_RE BIT(16) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ #define BIT_SHIFT_GEN1_GEN2 16 #define BIT_MASK_GEN1_GEN2 0x3 #define BIT_GEN1_GEN2(x) (((x) & BIT_MASK_GEN1_GEN2) << BIT_SHIFT_GEN1_GEN2) #define BITS_GEN1_GEN2 (BIT_MASK_GEN1_GEN2 << BIT_SHIFT_GEN1_GEN2) #define BIT_CLEAR_GEN1_GEN2(x) ((x) & (~BITS_GEN1_GEN2)) #define BIT_GET_GEN1_GEN2(x) (((x) >> BIT_SHIFT_GEN1_GEN2) & BIT_MASK_GEN1_GEN2) #define BIT_SET_GEN1_GEN2(x, v) (BIT_CLEAR_GEN1_GEN2(x) | BIT_GEN1_GEN2(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ #define BIT_AXI_RXDMA_TIMEOUT_IE BIT(13) #define BIT_AXI_TXDMA_TIMEOUT_IE BIT(12) #define BIT_AXI_DECERR_W_IE BIT(11) #define BIT_AXI_DECERR_R_IE BIT(10) #define BIT_AXI_SLVERR_W_IE BIT(9) #define BIT_AXI_SLVERR_R_IE BIT(8) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ #define BIT_SHIFT_RXDMA_ERROR_COUNTER 8 #define BIT_MASK_RXDMA_ERROR_COUNTER 0xff #define BIT_RXDMA_ERROR_COUNTER(x) \ (((x) & BIT_MASK_RXDMA_ERROR_COUNTER) << BIT_SHIFT_RXDMA_ERROR_COUNTER) #define BITS_RXDMA_ERROR_COUNTER \ (BIT_MASK_RXDMA_ERROR_COUNTER << BIT_SHIFT_RXDMA_ERROR_COUNTER) #define BIT_CLEAR_RXDMA_ERROR_COUNTER(x) ((x) & (~BITS_RXDMA_ERROR_COUNTER)) #define BIT_GET_RXDMA_ERROR_COUNTER(x) \ (((x) >> BIT_SHIFT_RXDMA_ERROR_COUNTER) & BIT_MASK_RXDMA_ERROR_COUNTER) #define BIT_SET_RXDMA_ERROR_COUNTER(x, v) \ (BIT_CLEAR_RXDMA_ERROR_COUNTER(x) | BIT_RXDMA_ERROR_COUNTER(v)) #define BIT_TXDMA_ERROR_HANDLE_STATUS BIT(7) #define BIT_TXDMA_ERROR_PULSE BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ #define BIT_AXI_RXDMA_TIMEOUT_FLAG BIT(5) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ #define BIT_TXDMA_STUCK_ERROR_HANDLE_ENABLE BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ #define BIT_AXI_TXDMA_TIMEOUT_FLAG BIT(4) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ #define BIT_TXDMA_RETURN_ERROR_ENABLE BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ #define BIT_AXI_DECERR_W_FLAG BIT(3) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ #define BIT_RXDMA_ERROR_HANDLE_STATUS BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ #define BIT_AXI_DECERR_R_FLAG BIT(2) #define BIT_AXI_SLVERR_W_FLAG BIT(1) #define BIT_AXI_SLVERR_R_FLAG BIT(0) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ #define BIT_SHIFT_AUTO_HANG_RELEASE 0 #define BIT_MASK_AUTO_HANG_RELEASE 0x7 #define BIT_AUTO_HANG_RELEASE(x) \ (((x) & BIT_MASK_AUTO_HANG_RELEASE) << BIT_SHIFT_AUTO_HANG_RELEASE) #define BITS_AUTO_HANG_RELEASE \ (BIT_MASK_AUTO_HANG_RELEASE << BIT_SHIFT_AUTO_HANG_RELEASE) #define BIT_CLEAR_AUTO_HANG_RELEASE(x) ((x) & (~BITS_AUTO_HANG_RELEASE)) #define BIT_GET_AUTO_HANG_RELEASE(x) \ (((x) >> BIT_SHIFT_AUTO_HANG_RELEASE) & BIT_MASK_AUTO_HANG_RELEASE) #define BIT_SET_AUTO_HANG_RELEASE(x, v) \ (BIT_CLEAR_AUTO_HANG_RELEASE(x) | BIT_AUTO_HANG_RELEASE(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AXI_EXCEPT_TIME (Offset 0x1354) */ #define BIT_SHIFT_AXI_RECOVERY_TIME 24 #define BIT_MASK_AXI_RECOVERY_TIME 0xff #define BIT_AXI_RECOVERY_TIME(x) \ (((x) & BIT_MASK_AXI_RECOVERY_TIME) << BIT_SHIFT_AXI_RECOVERY_TIME) #define BITS_AXI_RECOVERY_TIME \ (BIT_MASK_AXI_RECOVERY_TIME << BIT_SHIFT_AXI_RECOVERY_TIME) #define BIT_CLEAR_AXI_RECOVERY_TIME(x) ((x) & (~BITS_AXI_RECOVERY_TIME)) #define BIT_GET_AXI_RECOVERY_TIME(x) \ (((x) >> BIT_SHIFT_AXI_RECOVERY_TIME) & BIT_MASK_AXI_RECOVERY_TIME) #define BIT_SET_AXI_RECOVERY_TIME(x, v) \ (BIT_CLEAR_AXI_RECOVERY_TIME(x) | BIT_AXI_RECOVERY_TIME(v)) #define BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL 12 #define BIT_MASK_AXI_RXDMA_TIMEOUT_VAL 0xfff #define BIT_AXI_RXDMA_TIMEOUT_VAL(x) \ (((x) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL) \ << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL) #define BITS_AXI_RXDMA_TIMEOUT_VAL \ (BIT_MASK_AXI_RXDMA_TIMEOUT_VAL << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL) #define BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL(x) ((x) & (~BITS_AXI_RXDMA_TIMEOUT_VAL)) #define BIT_GET_AXI_RXDMA_TIMEOUT_VAL(x) \ (((x) >> BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL) & \ BIT_MASK_AXI_RXDMA_TIMEOUT_VAL) #define BIT_SET_AXI_RXDMA_TIMEOUT_VAL(x, v) \ (BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL(x) | BIT_AXI_RXDMA_TIMEOUT_VAL(v)) #define BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL 0 #define BIT_MASK_AXI_TXDMA_TIMEOUT_VAL 0xfff #define BIT_AXI_TXDMA_TIMEOUT_VAL(x) \ (((x) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL) \ << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL) #define BITS_AXI_TXDMA_TIMEOUT_VAL \ (BIT_MASK_AXI_TXDMA_TIMEOUT_VAL << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL) #define BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL(x) ((x) & (~BITS_AXI_TXDMA_TIMEOUT_VAL)) #define BIT_GET_AXI_TXDMA_TIMEOUT_VAL(x) \ (((x) >> BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL) & \ BIT_MASK_AXI_TXDMA_TIMEOUT_VAL) #define BIT_SET_AXI_TXDMA_TIMEOUT_VAL(x, v) \ (BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL(x) | BIT_AXI_TXDMA_TIMEOUT_VAL(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DEBUG_STATE1 (Offset 0x1354) */ #define BIT_SHIFT_DEBUG_STATE1 0 #define BIT_MASK_DEBUG_STATE1 0xffffffffL #define BIT_DEBUG_STATE1(x) \ (((x) & BIT_MASK_DEBUG_STATE1) << BIT_SHIFT_DEBUG_STATE1) #define BITS_DEBUG_STATE1 (BIT_MASK_DEBUG_STATE1 << BIT_SHIFT_DEBUG_STATE1) #define BIT_CLEAR_DEBUG_STATE1(x) ((x) & (~BITS_DEBUG_STATE1)) #define BIT_GET_DEBUG_STATE1(x) \ (((x) >> BIT_SHIFT_DEBUG_STATE1) & BIT_MASK_DEBUG_STATE1) #define BIT_SET_DEBUG_STATE1(x, v) \ (BIT_CLEAR_DEBUG_STATE1(x) | BIT_DEBUG_STATE1(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI8Q_TXBD_IDX (Offset 0x1358) */ #define BIT_SHIFT_HI8Q_HW_IDX 16 #define BIT_MASK_HI8Q_HW_IDX 0xfff #define BIT_HI8Q_HW_IDX(x) \ (((x) & BIT_MASK_HI8Q_HW_IDX) << BIT_SHIFT_HI8Q_HW_IDX) #define BITS_HI8Q_HW_IDX (BIT_MASK_HI8Q_HW_IDX << BIT_SHIFT_HI8Q_HW_IDX) #define BIT_CLEAR_HI8Q_HW_IDX(x) ((x) & (~BITS_HI8Q_HW_IDX)) #define BIT_GET_HI8Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_HI8Q_HW_IDX) & BIT_MASK_HI8Q_HW_IDX) #define BIT_SET_HI8Q_HW_IDX(x, v) \ (BIT_CLEAR_HI8Q_HW_IDX(x) | BIT_HI8Q_HW_IDX(v)) #define BIT_SHIFT_HI8Q_HOST_IDX 0 #define BIT_MASK_HI8Q_HOST_IDX 0xfff #define BIT_HI8Q_HOST_IDX(x) \ (((x) & BIT_MASK_HI8Q_HOST_IDX) << BIT_SHIFT_HI8Q_HOST_IDX) #define BITS_HI8Q_HOST_IDX (BIT_MASK_HI8Q_HOST_IDX << BIT_SHIFT_HI8Q_HOST_IDX) #define BIT_CLEAR_HI8Q_HOST_IDX(x) ((x) & (~BITS_HI8Q_HOST_IDX)) #define BIT_GET_HI8Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_HI8Q_HOST_IDX) & BIT_MASK_HI8Q_HOST_IDX) #define BIT_SET_HI8Q_HOST_IDX(x, v) \ (BIT_CLEAR_HI8Q_HOST_IDX(x) | BIT_HI8Q_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DEBUG_STATE2 (Offset 0x1358) */ #define BIT_SHIFT_DEBUG_STATE2 0 #define BIT_MASK_DEBUG_STATE2 0xffffffffL #define BIT_DEBUG_STATE2(x) \ (((x) & BIT_MASK_DEBUG_STATE2) << BIT_SHIFT_DEBUG_STATE2) #define BITS_DEBUG_STATE2 (BIT_MASK_DEBUG_STATE2 << BIT_SHIFT_DEBUG_STATE2) #define BIT_CLEAR_DEBUG_STATE2(x) ((x) & (~BITS_DEBUG_STATE2)) #define BIT_GET_DEBUG_STATE2(x) \ (((x) >> BIT_SHIFT_DEBUG_STATE2) & BIT_MASK_DEBUG_STATE2) #define BIT_SET_DEBUG_STATE2(x, v) \ (BIT_CLEAR_DEBUG_STATE2(x) | BIT_DEBUG_STATE2(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI9Q_TXBD_IDX (Offset 0x135C) */ #define BIT_SHIFT_HI9Q_HW_IDX 16 #define BIT_MASK_HI9Q_HW_IDX 0xfff #define BIT_HI9Q_HW_IDX(x) \ (((x) & BIT_MASK_HI9Q_HW_IDX) << BIT_SHIFT_HI9Q_HW_IDX) #define BITS_HI9Q_HW_IDX (BIT_MASK_HI9Q_HW_IDX << BIT_SHIFT_HI9Q_HW_IDX) #define BIT_CLEAR_HI9Q_HW_IDX(x) ((x) & (~BITS_HI9Q_HW_IDX)) #define BIT_GET_HI9Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_HI9Q_HW_IDX) & BIT_MASK_HI9Q_HW_IDX) #define BIT_SET_HI9Q_HW_IDX(x, v) \ (BIT_CLEAR_HI9Q_HW_IDX(x) | BIT_HI9Q_HW_IDX(v)) #define BIT_SHIFT_HI9Q_HOST_IDX 0 #define BIT_MASK_HI9Q_HOST_IDX 0xfff #define BIT_HI9Q_HOST_IDX(x) \ (((x) & BIT_MASK_HI9Q_HOST_IDX) << BIT_SHIFT_HI9Q_HOST_IDX) #define BITS_HI9Q_HOST_IDX (BIT_MASK_HI9Q_HOST_IDX << BIT_SHIFT_HI9Q_HOST_IDX) #define BIT_CLEAR_HI9Q_HOST_IDX(x) ((x) & (~BITS_HI9Q_HOST_IDX)) #define BIT_GET_HI9Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_HI9Q_HOST_IDX) & BIT_MASK_HI9Q_HOST_IDX) #define BIT_SET_HI9Q_HOST_IDX(x, v) \ (BIT_CLEAR_HI9Q_HOST_IDX(x) | BIT_HI9Q_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_DEBUG_STATE3 (Offset 0x135C) */ #define BIT_SHIFT_DEBUG_STATE3 0 #define BIT_MASK_DEBUG_STATE3 0xffffffffL #define BIT_DEBUG_STATE3(x) \ (((x) & BIT_MASK_DEBUG_STATE3) << BIT_SHIFT_DEBUG_STATE3) #define BITS_DEBUG_STATE3 (BIT_MASK_DEBUG_STATE3 << BIT_SHIFT_DEBUG_STATE3) #define BIT_CLEAR_DEBUG_STATE3(x) ((x) & (~BITS_DEBUG_STATE3)) #define BIT_GET_DEBUG_STATE3(x) \ (((x) >> BIT_SHIFT_DEBUG_STATE3) & BIT_MASK_DEBUG_STATE3) #define BIT_SET_DEBUG_STATE3(x, v) \ (BIT_CLEAR_DEBUG_STATE3(x) | BIT_DEBUG_STATE3(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI10Q_TXBD_IDX (Offset 0x1360) */ #define BIT_SHIFT_HI10Q_HW_IDX 16 #define BIT_MASK_HI10Q_HW_IDX 0xfff #define BIT_HI10Q_HW_IDX(x) \ (((x) & BIT_MASK_HI10Q_HW_IDX) << BIT_SHIFT_HI10Q_HW_IDX) #define BITS_HI10Q_HW_IDX (BIT_MASK_HI10Q_HW_IDX << BIT_SHIFT_HI10Q_HW_IDX) #define BIT_CLEAR_HI10Q_HW_IDX(x) ((x) & (~BITS_HI10Q_HW_IDX)) #define BIT_GET_HI10Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_HI10Q_HW_IDX) & BIT_MASK_HI10Q_HW_IDX) #define BIT_SET_HI10Q_HW_IDX(x, v) \ (BIT_CLEAR_HI10Q_HW_IDX(x) | BIT_HI10Q_HW_IDX(v)) #define BIT_SHIFT_HI10Q_HOST_IDX 0 #define BIT_MASK_HI10Q_HOST_IDX 0xfff #define BIT_HI10Q_HOST_IDX(x) \ (((x) & BIT_MASK_HI10Q_HOST_IDX) << BIT_SHIFT_HI10Q_HOST_IDX) #define BITS_HI10Q_HOST_IDX \ (BIT_MASK_HI10Q_HOST_IDX << BIT_SHIFT_HI10Q_HOST_IDX) #define BIT_CLEAR_HI10Q_HOST_IDX(x) ((x) & (~BITS_HI10Q_HOST_IDX)) #define BIT_GET_HI10Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_HI10Q_HOST_IDX) & BIT_MASK_HI10Q_HOST_IDX) #define BIT_SET_HI10Q_HOST_IDX(x, v) \ (BIT_CLEAR_HI10Q_HOST_IDX(x) | BIT_HI10Q_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH5_TXBD_DESA_L (Offset 0x1360) */ #define BIT_SHIFT_ACH5_TXBD_DESA_L 0 #define BIT_MASK_ACH5_TXBD_DESA_L 0xffffffffL #define BIT_ACH5_TXBD_DESA_L(x) \ (((x) & BIT_MASK_ACH5_TXBD_DESA_L) << BIT_SHIFT_ACH5_TXBD_DESA_L) #define BITS_ACH5_TXBD_DESA_L \ (BIT_MASK_ACH5_TXBD_DESA_L << BIT_SHIFT_ACH5_TXBD_DESA_L) #define BIT_CLEAR_ACH5_TXBD_DESA_L(x) ((x) & (~BITS_ACH5_TXBD_DESA_L)) #define BIT_GET_ACH5_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_ACH5_TXBD_DESA_L) & BIT_MASK_ACH5_TXBD_DESA_L) #define BIT_SET_ACH5_TXBD_DESA_L(x, v) \ (BIT_CLEAR_ACH5_TXBD_DESA_L(x) | BIT_ACH5_TXBD_DESA_L(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI11Q_TXBD_IDX (Offset 0x1364) */ #define BIT_SHIFT_HI11Q_HW_IDX 16 #define BIT_MASK_HI11Q_HW_IDX 0xfff #define BIT_HI11Q_HW_IDX(x) \ (((x) & BIT_MASK_HI11Q_HW_IDX) << BIT_SHIFT_HI11Q_HW_IDX) #define BITS_HI11Q_HW_IDX (BIT_MASK_HI11Q_HW_IDX << BIT_SHIFT_HI11Q_HW_IDX) #define BIT_CLEAR_HI11Q_HW_IDX(x) ((x) & (~BITS_HI11Q_HW_IDX)) #define BIT_GET_HI11Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_HI11Q_HW_IDX) & BIT_MASK_HI11Q_HW_IDX) #define BIT_SET_HI11Q_HW_IDX(x, v) \ (BIT_CLEAR_HI11Q_HW_IDX(x) | BIT_HI11Q_HW_IDX(v)) #define BIT_SHIFT_HI11Q_HOST_IDX 0 #define BIT_MASK_HI11Q_HOST_IDX 0xfff #define BIT_HI11Q_HOST_IDX(x) \ (((x) & BIT_MASK_HI11Q_HOST_IDX) << BIT_SHIFT_HI11Q_HOST_IDX) #define BITS_HI11Q_HOST_IDX \ (BIT_MASK_HI11Q_HOST_IDX << BIT_SHIFT_HI11Q_HOST_IDX) #define BIT_CLEAR_HI11Q_HOST_IDX(x) ((x) & (~BITS_HI11Q_HOST_IDX)) #define BIT_GET_HI11Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_HI11Q_HOST_IDX) & BIT_MASK_HI11Q_HOST_IDX) #define BIT_SET_HI11Q_HOST_IDX(x, v) \ (BIT_CLEAR_HI11Q_HOST_IDX(x) | BIT_HI11Q_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH5_TXBD_DESA_H (Offset 0x1364) */ #define BIT_SHIFT_ACH5_TXBD_DESA_H 0 #define BIT_MASK_ACH5_TXBD_DESA_H 0xffffffffL #define BIT_ACH5_TXBD_DESA_H(x) \ (((x) & BIT_MASK_ACH5_TXBD_DESA_H) << BIT_SHIFT_ACH5_TXBD_DESA_H) #define BITS_ACH5_TXBD_DESA_H \ (BIT_MASK_ACH5_TXBD_DESA_H << BIT_SHIFT_ACH5_TXBD_DESA_H) #define BIT_CLEAR_ACH5_TXBD_DESA_H(x) ((x) & (~BITS_ACH5_TXBD_DESA_H)) #define BIT_GET_ACH5_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_ACH5_TXBD_DESA_H) & BIT_MASK_ACH5_TXBD_DESA_H) #define BIT_SET_ACH5_TXBD_DESA_H(x, v) \ (BIT_CLEAR_ACH5_TXBD_DESA_H(x) | BIT_ACH5_TXBD_DESA_H(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI12Q_TXBD_IDX (Offset 0x1368) */ #define BIT_SHIFT_HI12Q_HW_IDX 16 #define BIT_MASK_HI12Q_HW_IDX 0xfff #define BIT_HI12Q_HW_IDX(x) \ (((x) & BIT_MASK_HI12Q_HW_IDX) << BIT_SHIFT_HI12Q_HW_IDX) #define BITS_HI12Q_HW_IDX (BIT_MASK_HI12Q_HW_IDX << BIT_SHIFT_HI12Q_HW_IDX) #define BIT_CLEAR_HI12Q_HW_IDX(x) ((x) & (~BITS_HI12Q_HW_IDX)) #define BIT_GET_HI12Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_HI12Q_HW_IDX) & BIT_MASK_HI12Q_HW_IDX) #define BIT_SET_HI12Q_HW_IDX(x, v) \ (BIT_CLEAR_HI12Q_HW_IDX(x) | BIT_HI12Q_HW_IDX(v)) #define BIT_SHIFT_HI12Q_HOST_IDX 0 #define BIT_MASK_HI12Q_HOST_IDX 0xfff #define BIT_HI12Q_HOST_IDX(x) \ (((x) & BIT_MASK_HI12Q_HOST_IDX) << BIT_SHIFT_HI12Q_HOST_IDX) #define BITS_HI12Q_HOST_IDX \ (BIT_MASK_HI12Q_HOST_IDX << BIT_SHIFT_HI12Q_HOST_IDX) #define BIT_CLEAR_HI12Q_HOST_IDX(x) ((x) & (~BITS_HI12Q_HOST_IDX)) #define BIT_GET_HI12Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_HI12Q_HOST_IDX) & BIT_MASK_HI12Q_HOST_IDX) #define BIT_SET_HI12Q_HOST_IDX(x, v) \ (BIT_CLEAR_HI12Q_HOST_IDX(x) | BIT_HI12Q_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH6_TXBD_DESA_L (Offset 0x1368) */ #define BIT_SHIFT_ACH6_TXBD_DESA_L 0 #define BIT_MASK_ACH6_TXBD_DESA_L 0xffffffffL #define BIT_ACH6_TXBD_DESA_L(x) \ (((x) & BIT_MASK_ACH6_TXBD_DESA_L) << BIT_SHIFT_ACH6_TXBD_DESA_L) #define BITS_ACH6_TXBD_DESA_L \ (BIT_MASK_ACH6_TXBD_DESA_L << BIT_SHIFT_ACH6_TXBD_DESA_L) #define BIT_CLEAR_ACH6_TXBD_DESA_L(x) ((x) & (~BITS_ACH6_TXBD_DESA_L)) #define BIT_GET_ACH6_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_ACH6_TXBD_DESA_L) & BIT_MASK_ACH6_TXBD_DESA_L) #define BIT_SET_ACH6_TXBD_DESA_L(x, v) \ (BIT_CLEAR_ACH6_TXBD_DESA_L(x) | BIT_ACH6_TXBD_DESA_L(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI13Q_TXBD_IDX (Offset 0x136C) */ #define BIT_SHIFT_HI13Q_HW_IDX 16 #define BIT_MASK_HI13Q_HW_IDX 0xfff #define BIT_HI13Q_HW_IDX(x) \ (((x) & BIT_MASK_HI13Q_HW_IDX) << BIT_SHIFT_HI13Q_HW_IDX) #define BITS_HI13Q_HW_IDX (BIT_MASK_HI13Q_HW_IDX << BIT_SHIFT_HI13Q_HW_IDX) #define BIT_CLEAR_HI13Q_HW_IDX(x) ((x) & (~BITS_HI13Q_HW_IDX)) #define BIT_GET_HI13Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_HI13Q_HW_IDX) & BIT_MASK_HI13Q_HW_IDX) #define BIT_SET_HI13Q_HW_IDX(x, v) \ (BIT_CLEAR_HI13Q_HW_IDX(x) | BIT_HI13Q_HW_IDX(v)) #define BIT_SHIFT_HI13Q_HOST_IDX 0 #define BIT_MASK_HI13Q_HOST_IDX 0xfff #define BIT_HI13Q_HOST_IDX(x) \ (((x) & BIT_MASK_HI13Q_HOST_IDX) << BIT_SHIFT_HI13Q_HOST_IDX) #define BITS_HI13Q_HOST_IDX \ (BIT_MASK_HI13Q_HOST_IDX << BIT_SHIFT_HI13Q_HOST_IDX) #define BIT_CLEAR_HI13Q_HOST_IDX(x) ((x) & (~BITS_HI13Q_HOST_IDX)) #define BIT_GET_HI13Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_HI13Q_HOST_IDX) & BIT_MASK_HI13Q_HOST_IDX) #define BIT_SET_HI13Q_HOST_IDX(x, v) \ (BIT_CLEAR_HI13Q_HOST_IDX(x) | BIT_HI13Q_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH6_TXBD_DESA_H (Offset 0x136C) */ #define BIT_SHIFT_ACH6_TXBD_DESA_H 0 #define BIT_MASK_ACH6_TXBD_DESA_H 0xffffffffL #define BIT_ACH6_TXBD_DESA_H(x) \ (((x) & BIT_MASK_ACH6_TXBD_DESA_H) << BIT_SHIFT_ACH6_TXBD_DESA_H) #define BITS_ACH6_TXBD_DESA_H \ (BIT_MASK_ACH6_TXBD_DESA_H << BIT_SHIFT_ACH6_TXBD_DESA_H) #define BIT_CLEAR_ACH6_TXBD_DESA_H(x) ((x) & (~BITS_ACH6_TXBD_DESA_H)) #define BIT_GET_ACH6_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_ACH6_TXBD_DESA_H) & BIT_MASK_ACH6_TXBD_DESA_H) #define BIT_SET_ACH6_TXBD_DESA_H(x, v) \ (BIT_CLEAR_ACH6_TXBD_DESA_H(x) | BIT_ACH6_TXBD_DESA_H(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI14Q_TXBD_IDX (Offset 0x1370) */ #define BIT_SHIFT_HI14Q_HW_IDX 16 #define BIT_MASK_HI14Q_HW_IDX 0xfff #define BIT_HI14Q_HW_IDX(x) \ (((x) & BIT_MASK_HI14Q_HW_IDX) << BIT_SHIFT_HI14Q_HW_IDX) #define BITS_HI14Q_HW_IDX (BIT_MASK_HI14Q_HW_IDX << BIT_SHIFT_HI14Q_HW_IDX) #define BIT_CLEAR_HI14Q_HW_IDX(x) ((x) & (~BITS_HI14Q_HW_IDX)) #define BIT_GET_HI14Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_HI14Q_HW_IDX) & BIT_MASK_HI14Q_HW_IDX) #define BIT_SET_HI14Q_HW_IDX(x, v) \ (BIT_CLEAR_HI14Q_HW_IDX(x) | BIT_HI14Q_HW_IDX(v)) #define BIT_SHIFT_HI14Q_HOST_IDX 0 #define BIT_MASK_HI14Q_HOST_IDX 0xfff #define BIT_HI14Q_HOST_IDX(x) \ (((x) & BIT_MASK_HI14Q_HOST_IDX) << BIT_SHIFT_HI14Q_HOST_IDX) #define BITS_HI14Q_HOST_IDX \ (BIT_MASK_HI14Q_HOST_IDX << BIT_SHIFT_HI14Q_HOST_IDX) #define BIT_CLEAR_HI14Q_HOST_IDX(x) ((x) & (~BITS_HI14Q_HOST_IDX)) #define BIT_GET_HI14Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_HI14Q_HOST_IDX) & BIT_MASK_HI14Q_HOST_IDX) #define BIT_SET_HI14Q_HOST_IDX(x, v) \ (BIT_CLEAR_HI14Q_HOST_IDX(x) | BIT_HI14Q_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH7_TXBD_DESA_L (Offset 0x1370) */ #define BIT_SHIFT_ACH7_TXBD_DESA_L 0 #define BIT_MASK_ACH7_TXBD_DESA_L 0xffffffffL #define BIT_ACH7_TXBD_DESA_L(x) \ (((x) & BIT_MASK_ACH7_TXBD_DESA_L) << BIT_SHIFT_ACH7_TXBD_DESA_L) #define BITS_ACH7_TXBD_DESA_L \ (BIT_MASK_ACH7_TXBD_DESA_L << BIT_SHIFT_ACH7_TXBD_DESA_L) #define BIT_CLEAR_ACH7_TXBD_DESA_L(x) ((x) & (~BITS_ACH7_TXBD_DESA_L)) #define BIT_GET_ACH7_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_ACH7_TXBD_DESA_L) & BIT_MASK_ACH7_TXBD_DESA_L) #define BIT_SET_ACH7_TXBD_DESA_L(x, v) \ (BIT_CLEAR_ACH7_TXBD_DESA_L(x) | BIT_ACH7_TXBD_DESA_L(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI15Q_TXBD_IDX (Offset 0x1374) */ #define BIT_SHIFT_HI15Q_HW_IDX 16 #define BIT_MASK_HI15Q_HW_IDX 0xfff #define BIT_HI15Q_HW_IDX(x) \ (((x) & BIT_MASK_HI15Q_HW_IDX) << BIT_SHIFT_HI15Q_HW_IDX) #define BITS_HI15Q_HW_IDX (BIT_MASK_HI15Q_HW_IDX << BIT_SHIFT_HI15Q_HW_IDX) #define BIT_CLEAR_HI15Q_HW_IDX(x) ((x) & (~BITS_HI15Q_HW_IDX)) #define BIT_GET_HI15Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_HI15Q_HW_IDX) & BIT_MASK_HI15Q_HW_IDX) #define BIT_SET_HI15Q_HW_IDX(x, v) \ (BIT_CLEAR_HI15Q_HW_IDX(x) | BIT_HI15Q_HW_IDX(v)) #define BIT_SHIFT_HI15Q_HOST_IDX 0 #define BIT_MASK_HI15Q_HOST_IDX 0xfff #define BIT_HI15Q_HOST_IDX(x) \ (((x) & BIT_MASK_HI15Q_HOST_IDX) << BIT_SHIFT_HI15Q_HOST_IDX) #define BITS_HI15Q_HOST_IDX \ (BIT_MASK_HI15Q_HOST_IDX << BIT_SHIFT_HI15Q_HOST_IDX) #define BIT_CLEAR_HI15Q_HOST_IDX(x) ((x) & (~BITS_HI15Q_HOST_IDX)) #define BIT_GET_HI15Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_HI15Q_HOST_IDX) & BIT_MASK_HI15Q_HOST_IDX) #define BIT_SET_HI15Q_HOST_IDX(x, v) \ (BIT_CLEAR_HI15Q_HOST_IDX(x) | BIT_HI15Q_HOST_IDX(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH7_TXBD_DESA_H (Offset 0x1374) */ #define BIT_SHIFT_ACH7_TXBD_DESA_H 0 #define BIT_MASK_ACH7_TXBD_DESA_H 0xffffffffL #define BIT_ACH7_TXBD_DESA_H(x) \ (((x) & BIT_MASK_ACH7_TXBD_DESA_H) << BIT_SHIFT_ACH7_TXBD_DESA_H) #define BITS_ACH7_TXBD_DESA_H \ (BIT_MASK_ACH7_TXBD_DESA_H << BIT_SHIFT_ACH7_TXBD_DESA_H) #define BIT_CLEAR_ACH7_TXBD_DESA_H(x) ((x) & (~BITS_ACH7_TXBD_DESA_H)) #define BIT_GET_ACH7_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_ACH7_TXBD_DESA_H) & BIT_MASK_ACH7_TXBD_DESA_H) #define BIT_SET_ACH7_TXBD_DESA_H(x, v) \ (BIT_CLEAR_ACH7_TXBD_DESA_H(x) | BIT_ACH7_TXBD_DESA_H(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI8Q_TXBD_DESA (Offset 0x1378) */ #define BIT_SHIFT_HI8Q_TXBD_DESA 0 #define BIT_MASK_HI8Q_TXBD_DESA 0xffffffffffffffffL #define BIT_HI8Q_TXBD_DESA(x) \ (((x) & BIT_MASK_HI8Q_TXBD_DESA) << BIT_SHIFT_HI8Q_TXBD_DESA) #define BITS_HI8Q_TXBD_DESA \ (BIT_MASK_HI8Q_TXBD_DESA << BIT_SHIFT_HI8Q_TXBD_DESA) #define BIT_CLEAR_HI8Q_TXBD_DESA(x) ((x) & (~BITS_HI8Q_TXBD_DESA)) #define BIT_GET_HI8Q_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_HI8Q_TXBD_DESA) & BIT_MASK_HI8Q_TXBD_DESA) #define BIT_SET_HI8Q_TXBD_DESA(x, v) \ (BIT_CLEAR_HI8Q_TXBD_DESA(x) | BIT_HI8Q_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH8_TXBD_DESA_L (Offset 0x1378) */ #define BIT_SHIFT_ACH8_TXBD_DESA_L 0 #define BIT_MASK_ACH8_TXBD_DESA_L 0xffffffffL #define BIT_ACH8_TXBD_DESA_L(x) \ (((x) & BIT_MASK_ACH8_TXBD_DESA_L) << BIT_SHIFT_ACH8_TXBD_DESA_L) #define BITS_ACH8_TXBD_DESA_L \ (BIT_MASK_ACH8_TXBD_DESA_L << BIT_SHIFT_ACH8_TXBD_DESA_L) #define BIT_CLEAR_ACH8_TXBD_DESA_L(x) ((x) & (~BITS_ACH8_TXBD_DESA_L)) #define BIT_GET_ACH8_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_ACH8_TXBD_DESA_L) & BIT_MASK_ACH8_TXBD_DESA_L) #define BIT_SET_ACH8_TXBD_DESA_L(x, v) \ (BIT_CLEAR_ACH8_TXBD_DESA_L(x) | BIT_ACH8_TXBD_DESA_L(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_CHNL_DMA_CFG_V1 (Offset 0x137C) */ #define BIT_TXHCI_EN_V1 BIT(26) #define BIT_TXHCI_IDLE_V1 BIT(25) #define BIT_DMA_PRI_EN_V1 BIT(24) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH8_TXBD_DESA_H (Offset 0x137C) */ #define BIT_SHIFT_ACH8_TXBD_DESA_H 0 #define BIT_MASK_ACH8_TXBD_DESA_H 0xffffffffL #define BIT_ACH8_TXBD_DESA_H(x) \ (((x) & BIT_MASK_ACH8_TXBD_DESA_H) << BIT_SHIFT_ACH8_TXBD_DESA_H) #define BITS_ACH8_TXBD_DESA_H \ (BIT_MASK_ACH8_TXBD_DESA_H << BIT_SHIFT_ACH8_TXBD_DESA_H) #define BIT_CLEAR_ACH8_TXBD_DESA_H(x) ((x) & (~BITS_ACH8_TXBD_DESA_H)) #define BIT_GET_ACH8_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_ACH8_TXBD_DESA_H) & BIT_MASK_ACH8_TXBD_DESA_H) #define BIT_SET_ACH8_TXBD_DESA_H(x, v) \ (BIT_CLEAR_ACH8_TXBD_DESA_H(x) | BIT_ACH8_TXBD_DESA_H(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI9Q_TXBD_DESA (Offset 0x1380) */ #define BIT_SHIFT_HI9Q_TXBD_DESA 0 #define BIT_MASK_HI9Q_TXBD_DESA 0xffffffffffffffffL #define BIT_HI9Q_TXBD_DESA(x) \ (((x) & BIT_MASK_HI9Q_TXBD_DESA) << BIT_SHIFT_HI9Q_TXBD_DESA) #define BITS_HI9Q_TXBD_DESA \ (BIT_MASK_HI9Q_TXBD_DESA << BIT_SHIFT_HI9Q_TXBD_DESA) #define BIT_CLEAR_HI9Q_TXBD_DESA(x) ((x) & (~BITS_HI9Q_TXBD_DESA)) #define BIT_GET_HI9Q_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_HI9Q_TXBD_DESA) & BIT_MASK_HI9Q_TXBD_DESA) #define BIT_SET_HI9Q_TXBD_DESA(x, v) \ (BIT_CLEAR_HI9Q_TXBD_DESA(x) | BIT_HI9Q_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH9_TXBD_DESA_L (Offset 0x1380) */ #define BIT_SHIFT_ACH9_TXBD_DESA_L 0 #define BIT_MASK_ACH9_TXBD_DESA_L 0xffffffffL #define BIT_ACH9_TXBD_DESA_L(x) \ (((x) & BIT_MASK_ACH9_TXBD_DESA_L) << BIT_SHIFT_ACH9_TXBD_DESA_L) #define BITS_ACH9_TXBD_DESA_L \ (BIT_MASK_ACH9_TXBD_DESA_L << BIT_SHIFT_ACH9_TXBD_DESA_L) #define BIT_CLEAR_ACH9_TXBD_DESA_L(x) ((x) & (~BITS_ACH9_TXBD_DESA_L)) #define BIT_GET_ACH9_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_ACH9_TXBD_DESA_L) & BIT_MASK_ACH9_TXBD_DESA_L) #define BIT_SET_ACH9_TXBD_DESA_L(x, v) \ (BIT_CLEAR_ACH9_TXBD_DESA_L(x) | BIT_ACH9_TXBD_DESA_L(v)) /* 2 REG_ACH9_TXBD_DESA_H (Offset 0x1384) */ #define BIT_SHIFT_ACH9_TXBD_DESA_H 0 #define BIT_MASK_ACH9_TXBD_DESA_H 0xffffffffL #define BIT_ACH9_TXBD_DESA_H(x) \ (((x) & BIT_MASK_ACH9_TXBD_DESA_H) << BIT_SHIFT_ACH9_TXBD_DESA_H) #define BITS_ACH9_TXBD_DESA_H \ (BIT_MASK_ACH9_TXBD_DESA_H << BIT_SHIFT_ACH9_TXBD_DESA_H) #define BIT_CLEAR_ACH9_TXBD_DESA_H(x) ((x) & (~BITS_ACH9_TXBD_DESA_H)) #define BIT_GET_ACH9_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_ACH9_TXBD_DESA_H) & BIT_MASK_ACH9_TXBD_DESA_H) #define BIT_SET_ACH9_TXBD_DESA_H(x, v) \ (BIT_CLEAR_ACH9_TXBD_DESA_H(x) | BIT_ACH9_TXBD_DESA_H(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI10Q_TXBD_DESA (Offset 0x1388) */ #define BIT_SHIFT_HI10Q_TXBD_DESA 0 #define BIT_MASK_HI10Q_TXBD_DESA 0xffffffffffffffffL #define BIT_HI10Q_TXBD_DESA(x) \ (((x) & BIT_MASK_HI10Q_TXBD_DESA) << BIT_SHIFT_HI10Q_TXBD_DESA) #define BITS_HI10Q_TXBD_DESA \ (BIT_MASK_HI10Q_TXBD_DESA << BIT_SHIFT_HI10Q_TXBD_DESA) #define BIT_CLEAR_HI10Q_TXBD_DESA(x) ((x) & (~BITS_HI10Q_TXBD_DESA)) #define BIT_GET_HI10Q_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_HI10Q_TXBD_DESA) & BIT_MASK_HI10Q_TXBD_DESA) #define BIT_SET_HI10Q_TXBD_DESA(x, v) \ (BIT_CLEAR_HI10Q_TXBD_DESA(x) | BIT_HI10Q_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH10_TXBD_DESA_L (Offset 0x1388) */ #define BIT_SHIFT_ACH10_TXBD_DESA_L 0 #define BIT_MASK_ACH10_TXBD_DESA_L 0xffffffffL #define BIT_ACH10_TXBD_DESA_L(x) \ (((x) & BIT_MASK_ACH10_TXBD_DESA_L) << BIT_SHIFT_ACH10_TXBD_DESA_L) #define BITS_ACH10_TXBD_DESA_L \ (BIT_MASK_ACH10_TXBD_DESA_L << BIT_SHIFT_ACH10_TXBD_DESA_L) #define BIT_CLEAR_ACH10_TXBD_DESA_L(x) ((x) & (~BITS_ACH10_TXBD_DESA_L)) #define BIT_GET_ACH10_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_ACH10_TXBD_DESA_L) & BIT_MASK_ACH10_TXBD_DESA_L) #define BIT_SET_ACH10_TXBD_DESA_L(x, v) \ (BIT_CLEAR_ACH10_TXBD_DESA_L(x) | BIT_ACH10_TXBD_DESA_L(v)) /* 2 REG_ACH10_TXBD_DESA_H (Offset 0x138C) */ #define BIT_SHIFT_ACH10_TXBD_DESA_H 0 #define BIT_MASK_ACH10_TXBD_DESA_H 0xffffffffL #define BIT_ACH10_TXBD_DESA_H(x) \ (((x) & BIT_MASK_ACH10_TXBD_DESA_H) << BIT_SHIFT_ACH10_TXBD_DESA_H) #define BITS_ACH10_TXBD_DESA_H \ (BIT_MASK_ACH10_TXBD_DESA_H << BIT_SHIFT_ACH10_TXBD_DESA_H) #define BIT_CLEAR_ACH10_TXBD_DESA_H(x) ((x) & (~BITS_ACH10_TXBD_DESA_H)) #define BIT_GET_ACH10_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_ACH10_TXBD_DESA_H) & BIT_MASK_ACH10_TXBD_DESA_H) #define BIT_SET_ACH10_TXBD_DESA_H(x, v) \ (BIT_CLEAR_ACH10_TXBD_DESA_H(x) | BIT_ACH10_TXBD_DESA_H(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI11Q_TXBD_DESA (Offset 0x1390) */ #define BIT_SHIFT_HI11Q_TXBD_DESA 0 #define BIT_MASK_HI11Q_TXBD_DESA 0xffffffffffffffffL #define BIT_HI11Q_TXBD_DESA(x) \ (((x) & BIT_MASK_HI11Q_TXBD_DESA) << BIT_SHIFT_HI11Q_TXBD_DESA) #define BITS_HI11Q_TXBD_DESA \ (BIT_MASK_HI11Q_TXBD_DESA << BIT_SHIFT_HI11Q_TXBD_DESA) #define BIT_CLEAR_HI11Q_TXBD_DESA(x) ((x) & (~BITS_HI11Q_TXBD_DESA)) #define BIT_GET_HI11Q_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_HI11Q_TXBD_DESA) & BIT_MASK_HI11Q_TXBD_DESA) #define BIT_SET_HI11Q_TXBD_DESA(x, v) \ (BIT_CLEAR_HI11Q_TXBD_DESA(x) | BIT_HI11Q_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH11_TXBD_DESA_L (Offset 0x1390) */ #define BIT_SHIFT_ACH11_TXBD_DESA_L 0 #define BIT_MASK_ACH11_TXBD_DESA_L 0xffffffffL #define BIT_ACH11_TXBD_DESA_L(x) \ (((x) & BIT_MASK_ACH11_TXBD_DESA_L) << BIT_SHIFT_ACH11_TXBD_DESA_L) #define BITS_ACH11_TXBD_DESA_L \ (BIT_MASK_ACH11_TXBD_DESA_L << BIT_SHIFT_ACH11_TXBD_DESA_L) #define BIT_CLEAR_ACH11_TXBD_DESA_L(x) ((x) & (~BITS_ACH11_TXBD_DESA_L)) #define BIT_GET_ACH11_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_ACH11_TXBD_DESA_L) & BIT_MASK_ACH11_TXBD_DESA_L) #define BIT_SET_ACH11_TXBD_DESA_L(x, v) \ (BIT_CLEAR_ACH11_TXBD_DESA_L(x) | BIT_ACH11_TXBD_DESA_L(v)) /* 2 REG_ACH11_TXBD_DESA_H (Offset 0x1394) */ #define BIT_SHIFT_ACH11_TXBD_DESA_H 0 #define BIT_MASK_ACH11_TXBD_DESA_H 0xffffffffL #define BIT_ACH11_TXBD_DESA_H(x) \ (((x) & BIT_MASK_ACH11_TXBD_DESA_H) << BIT_SHIFT_ACH11_TXBD_DESA_H) #define BITS_ACH11_TXBD_DESA_H \ (BIT_MASK_ACH11_TXBD_DESA_H << BIT_SHIFT_ACH11_TXBD_DESA_H) #define BIT_CLEAR_ACH11_TXBD_DESA_H(x) ((x) & (~BITS_ACH11_TXBD_DESA_H)) #define BIT_GET_ACH11_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_ACH11_TXBD_DESA_H) & BIT_MASK_ACH11_TXBD_DESA_H) #define BIT_SET_ACH11_TXBD_DESA_H(x, v) \ (BIT_CLEAR_ACH11_TXBD_DESA_H(x) | BIT_ACH11_TXBD_DESA_H(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI12Q_TXBD_DESA (Offset 0x1398) */ #define BIT_SHIFT_HI12Q_TXBD_DESA 0 #define BIT_MASK_HI12Q_TXBD_DESA 0xffffffffffffffffL #define BIT_HI12Q_TXBD_DESA(x) \ (((x) & BIT_MASK_HI12Q_TXBD_DESA) << BIT_SHIFT_HI12Q_TXBD_DESA) #define BITS_HI12Q_TXBD_DESA \ (BIT_MASK_HI12Q_TXBD_DESA << BIT_SHIFT_HI12Q_TXBD_DESA) #define BIT_CLEAR_HI12Q_TXBD_DESA(x) ((x) & (~BITS_HI12Q_TXBD_DESA)) #define BIT_GET_HI12Q_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_HI12Q_TXBD_DESA) & BIT_MASK_HI12Q_TXBD_DESA) #define BIT_SET_HI12Q_TXBD_DESA(x, v) \ (BIT_CLEAR_HI12Q_TXBD_DESA(x) | BIT_HI12Q_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH12_TXBD_DESA_L (Offset 0x1398) */ #define BIT_SHIFT_ACH12_TXBD_DESA_L 0 #define BIT_MASK_ACH12_TXBD_DESA_L 0xffffffffL #define BIT_ACH12_TXBD_DESA_L(x) \ (((x) & BIT_MASK_ACH12_TXBD_DESA_L) << BIT_SHIFT_ACH12_TXBD_DESA_L) #define BITS_ACH12_TXBD_DESA_L \ (BIT_MASK_ACH12_TXBD_DESA_L << BIT_SHIFT_ACH12_TXBD_DESA_L) #define BIT_CLEAR_ACH12_TXBD_DESA_L(x) ((x) & (~BITS_ACH12_TXBD_DESA_L)) #define BIT_GET_ACH12_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_ACH12_TXBD_DESA_L) & BIT_MASK_ACH12_TXBD_DESA_L) #define BIT_SET_ACH12_TXBD_DESA_L(x, v) \ (BIT_CLEAR_ACH12_TXBD_DESA_L(x) | BIT_ACH12_TXBD_DESA_L(v)) /* 2 REG_ACH12_TXBD_DESA_H (Offset 0x139C) */ #define BIT_SHIFT_ACH12_TXBD_DESA_H 0 #define BIT_MASK_ACH12_TXBD_DESA_H 0xffffffffL #define BIT_ACH12_TXBD_DESA_H(x) \ (((x) & BIT_MASK_ACH12_TXBD_DESA_H) << BIT_SHIFT_ACH12_TXBD_DESA_H) #define BITS_ACH12_TXBD_DESA_H \ (BIT_MASK_ACH12_TXBD_DESA_H << BIT_SHIFT_ACH12_TXBD_DESA_H) #define BIT_CLEAR_ACH12_TXBD_DESA_H(x) ((x) & (~BITS_ACH12_TXBD_DESA_H)) #define BIT_GET_ACH12_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_ACH12_TXBD_DESA_H) & BIT_MASK_ACH12_TXBD_DESA_H) #define BIT_SET_ACH12_TXBD_DESA_H(x, v) \ (BIT_CLEAR_ACH12_TXBD_DESA_H(x) | BIT_ACH12_TXBD_DESA_H(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI13Q_TXBD_DESA (Offset 0x13A0) */ #define BIT_SHIFT_HI13Q_TXBD_DESA 0 #define BIT_MASK_HI13Q_TXBD_DESA 0xffffffffffffffffL #define BIT_HI13Q_TXBD_DESA(x) \ (((x) & BIT_MASK_HI13Q_TXBD_DESA) << BIT_SHIFT_HI13Q_TXBD_DESA) #define BITS_HI13Q_TXBD_DESA \ (BIT_MASK_HI13Q_TXBD_DESA << BIT_SHIFT_HI13Q_TXBD_DESA) #define BIT_CLEAR_HI13Q_TXBD_DESA(x) ((x) & (~BITS_HI13Q_TXBD_DESA)) #define BIT_GET_HI13Q_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_HI13Q_TXBD_DESA) & BIT_MASK_HI13Q_TXBD_DESA) #define BIT_SET_HI13Q_TXBD_DESA(x, v) \ (BIT_CLEAR_HI13Q_TXBD_DESA(x) | BIT_HI13Q_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH13_TXBD_DESA_L (Offset 0x13A0) */ #define BIT_SHIFT_ACH13_TXBD_DESA_L 0 #define BIT_MASK_ACH13_TXBD_DESA_L 0xffffffffL #define BIT_ACH13_TXBD_DESA_L(x) \ (((x) & BIT_MASK_ACH13_TXBD_DESA_L) << BIT_SHIFT_ACH13_TXBD_DESA_L) #define BITS_ACH13_TXBD_DESA_L \ (BIT_MASK_ACH13_TXBD_DESA_L << BIT_SHIFT_ACH13_TXBD_DESA_L) #define BIT_CLEAR_ACH13_TXBD_DESA_L(x) ((x) & (~BITS_ACH13_TXBD_DESA_L)) #define BIT_GET_ACH13_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_ACH13_TXBD_DESA_L) & BIT_MASK_ACH13_TXBD_DESA_L) #define BIT_SET_ACH13_TXBD_DESA_L(x, v) \ (BIT_CLEAR_ACH13_TXBD_DESA_L(x) | BIT_ACH13_TXBD_DESA_L(v)) /* 2 REG_ACH13_TXBD_DESA_H (Offset 0x13A4) */ #define BIT_SHIFT_ACH13_TXBD_DESA_H 0 #define BIT_MASK_ACH13_TXBD_DESA_H 0xffffffffL #define BIT_ACH13_TXBD_DESA_H(x) \ (((x) & BIT_MASK_ACH13_TXBD_DESA_H) << BIT_SHIFT_ACH13_TXBD_DESA_H) #define BITS_ACH13_TXBD_DESA_H \ (BIT_MASK_ACH13_TXBD_DESA_H << BIT_SHIFT_ACH13_TXBD_DESA_H) #define BIT_CLEAR_ACH13_TXBD_DESA_H(x) ((x) & (~BITS_ACH13_TXBD_DESA_H)) #define BIT_GET_ACH13_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_ACH13_TXBD_DESA_H) & BIT_MASK_ACH13_TXBD_DESA_H) #define BIT_SET_ACH13_TXBD_DESA_H(x, v) \ (BIT_CLEAR_ACH13_TXBD_DESA_H(x) | BIT_ACH13_TXBD_DESA_H(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI14Q_TXBD_DESA (Offset 0x13A8) */ #define BIT_SHIFT_HI14Q_TXBD_DESA 0 #define BIT_MASK_HI14Q_TXBD_DESA 0xffffffffffffffffL #define BIT_HI14Q_TXBD_DESA(x) \ (((x) & BIT_MASK_HI14Q_TXBD_DESA) << BIT_SHIFT_HI14Q_TXBD_DESA) #define BITS_HI14Q_TXBD_DESA \ (BIT_MASK_HI14Q_TXBD_DESA << BIT_SHIFT_HI14Q_TXBD_DESA) #define BIT_CLEAR_HI14Q_TXBD_DESA(x) ((x) & (~BITS_HI14Q_TXBD_DESA)) #define BIT_GET_HI14Q_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_HI14Q_TXBD_DESA) & BIT_MASK_HI14Q_TXBD_DESA) #define BIT_SET_HI14Q_TXBD_DESA(x, v) \ (BIT_CLEAR_HI14Q_TXBD_DESA(x) | BIT_HI14Q_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HI0Q_TXBD_DESA_L (Offset 0x13A8) */ #define BIT_SHIFT_HI0Q_TXBD_DESA_L 0 #define BIT_MASK_HI0Q_TXBD_DESA_L 0xffffffffL #define BIT_HI0Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI0Q_TXBD_DESA_L) << BIT_SHIFT_HI0Q_TXBD_DESA_L) #define BITS_HI0Q_TXBD_DESA_L \ (BIT_MASK_HI0Q_TXBD_DESA_L << BIT_SHIFT_HI0Q_TXBD_DESA_L) #define BIT_CLEAR_HI0Q_TXBD_DESA_L(x) ((x) & (~BITS_HI0Q_TXBD_DESA_L)) #define BIT_GET_HI0Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_L) & BIT_MASK_HI0Q_TXBD_DESA_L) #define BIT_SET_HI0Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI0Q_TXBD_DESA_L(x) | BIT_HI0Q_TXBD_DESA_L(v)) /* 2 REG_HI0Q_TXBD_DESA_H (Offset 0x13AC) */ #define BIT_SHIFT_HI0Q_TXBD_DESA_H 0 #define BIT_MASK_HI0Q_TXBD_DESA_H 0xffffffffL #define BIT_HI0Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI0Q_TXBD_DESA_H) << BIT_SHIFT_HI0Q_TXBD_DESA_H) #define BITS_HI0Q_TXBD_DESA_H \ (BIT_MASK_HI0Q_TXBD_DESA_H << BIT_SHIFT_HI0Q_TXBD_DESA_H) #define BIT_CLEAR_HI0Q_TXBD_DESA_H(x) ((x) & (~BITS_HI0Q_TXBD_DESA_H)) #define BIT_GET_HI0Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_H) & BIT_MASK_HI0Q_TXBD_DESA_H) #define BIT_SET_HI0Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI0Q_TXBD_DESA_H(x) | BIT_HI0Q_TXBD_DESA_H(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI15Q_TXBD_DESA (Offset 0x13B0) */ #define BIT_SHIFT_HI15Q_TXBD_DESA 0 #define BIT_MASK_HI15Q_TXBD_DESA 0xffffffffffffffffL #define BIT_HI15Q_TXBD_DESA(x) \ (((x) & BIT_MASK_HI15Q_TXBD_DESA) << BIT_SHIFT_HI15Q_TXBD_DESA) #define BITS_HI15Q_TXBD_DESA \ (BIT_MASK_HI15Q_TXBD_DESA << BIT_SHIFT_HI15Q_TXBD_DESA) #define BIT_CLEAR_HI15Q_TXBD_DESA(x) ((x) & (~BITS_HI15Q_TXBD_DESA)) #define BIT_GET_HI15Q_TXBD_DESA(x) \ (((x) >> BIT_SHIFT_HI15Q_TXBD_DESA) & BIT_MASK_HI15Q_TXBD_DESA) #define BIT_SET_HI15Q_TXBD_DESA(x, v) \ (BIT_CLEAR_HI15Q_TXBD_DESA(x) | BIT_HI15Q_TXBD_DESA(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HI1Q_TXBD_DESA_L (Offset 0x13B0) */ #define BIT_SHIFT_HI1Q_TXBD_DESA_L 0 #define BIT_MASK_HI1Q_TXBD_DESA_L 0xffffffffL #define BIT_HI1Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI1Q_TXBD_DESA_L) << BIT_SHIFT_HI1Q_TXBD_DESA_L) #define BITS_HI1Q_TXBD_DESA_L \ (BIT_MASK_HI1Q_TXBD_DESA_L << BIT_SHIFT_HI1Q_TXBD_DESA_L) #define BIT_CLEAR_HI1Q_TXBD_DESA_L(x) ((x) & (~BITS_HI1Q_TXBD_DESA_L)) #define BIT_GET_HI1Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_L) & BIT_MASK_HI1Q_TXBD_DESA_L) #define BIT_SET_HI1Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI1Q_TXBD_DESA_L(x) | BIT_HI1Q_TXBD_DESA_L(v)) /* 2 REG_HI1Q_TXBD_DESA_H (Offset 0x13B4) */ #define BIT_SHIFT_HI1Q_TXBD_DESA_H 0 #define BIT_MASK_HI1Q_TXBD_DESA_H 0xffffffffL #define BIT_HI1Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI1Q_TXBD_DESA_H) << BIT_SHIFT_HI1Q_TXBD_DESA_H) #define BITS_HI1Q_TXBD_DESA_H \ (BIT_MASK_HI1Q_TXBD_DESA_H << BIT_SHIFT_HI1Q_TXBD_DESA_H) #define BIT_CLEAR_HI1Q_TXBD_DESA_H(x) ((x) & (~BITS_HI1Q_TXBD_DESA_H)) #define BIT_GET_HI1Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_H) & BIT_MASK_HI1Q_TXBD_DESA_H) #define BIT_SET_HI1Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI1Q_TXBD_DESA_H(x) | BIT_HI1Q_TXBD_DESA_H(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI8Q_TXBD_NUM (Offset 0x13B8) */ #define BIT_HI8Q_FLAG BIT(14) #define BIT_SHIFT_HI8Q_DESC_MODE 12 #define BIT_MASK_HI8Q_DESC_MODE 0x3 #define BIT_HI8Q_DESC_MODE(x) \ (((x) & BIT_MASK_HI8Q_DESC_MODE) << BIT_SHIFT_HI8Q_DESC_MODE) #define BITS_HI8Q_DESC_MODE \ (BIT_MASK_HI8Q_DESC_MODE << BIT_SHIFT_HI8Q_DESC_MODE) #define BIT_CLEAR_HI8Q_DESC_MODE(x) ((x) & (~BITS_HI8Q_DESC_MODE)) #define BIT_GET_HI8Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_HI8Q_DESC_MODE) & BIT_MASK_HI8Q_DESC_MODE) #define BIT_SET_HI8Q_DESC_MODE(x, v) \ (BIT_CLEAR_HI8Q_DESC_MODE(x) | BIT_HI8Q_DESC_MODE(v)) #define BIT_SHIFT_HI8Q_DESC_NUM 0 #define BIT_MASK_HI8Q_DESC_NUM 0xfff #define BIT_HI8Q_DESC_NUM(x) \ (((x) & BIT_MASK_HI8Q_DESC_NUM) << BIT_SHIFT_HI8Q_DESC_NUM) #define BITS_HI8Q_DESC_NUM (BIT_MASK_HI8Q_DESC_NUM << BIT_SHIFT_HI8Q_DESC_NUM) #define BIT_CLEAR_HI8Q_DESC_NUM(x) ((x) & (~BITS_HI8Q_DESC_NUM)) #define BIT_GET_HI8Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_HI8Q_DESC_NUM) & BIT_MASK_HI8Q_DESC_NUM) #define BIT_SET_HI8Q_DESC_NUM(x, v) \ (BIT_CLEAR_HI8Q_DESC_NUM(x) | BIT_HI8Q_DESC_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HI2Q_TXBD_DESA_L (Offset 0x13B8) */ #define BIT_SHIFT_HI2Q_TXBD_DESA_L 0 #define BIT_MASK_HI2Q_TXBD_DESA_L 0xffffffffL #define BIT_HI2Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI2Q_TXBD_DESA_L) << BIT_SHIFT_HI2Q_TXBD_DESA_L) #define BITS_HI2Q_TXBD_DESA_L \ (BIT_MASK_HI2Q_TXBD_DESA_L << BIT_SHIFT_HI2Q_TXBD_DESA_L) #define BIT_CLEAR_HI2Q_TXBD_DESA_L(x) ((x) & (~BITS_HI2Q_TXBD_DESA_L)) #define BIT_GET_HI2Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_L) & BIT_MASK_HI2Q_TXBD_DESA_L) #define BIT_SET_HI2Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI2Q_TXBD_DESA_L(x) | BIT_HI2Q_TXBD_DESA_L(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI9Q_TXBD_NUM (Offset 0x13BA) */ #define BIT_HI9Q_FLAG BIT(14) #define BIT_SHIFT_HI9Q_DESC_MODE 12 #define BIT_MASK_HI9Q_DESC_MODE 0x3 #define BIT_HI9Q_DESC_MODE(x) \ (((x) & BIT_MASK_HI9Q_DESC_MODE) << BIT_SHIFT_HI9Q_DESC_MODE) #define BITS_HI9Q_DESC_MODE \ (BIT_MASK_HI9Q_DESC_MODE << BIT_SHIFT_HI9Q_DESC_MODE) #define BIT_CLEAR_HI9Q_DESC_MODE(x) ((x) & (~BITS_HI9Q_DESC_MODE)) #define BIT_GET_HI9Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_HI9Q_DESC_MODE) & BIT_MASK_HI9Q_DESC_MODE) #define BIT_SET_HI9Q_DESC_MODE(x, v) \ (BIT_CLEAR_HI9Q_DESC_MODE(x) | BIT_HI9Q_DESC_MODE(v)) #define BIT_SHIFT_HI9Q_DESC_NUM 0 #define BIT_MASK_HI9Q_DESC_NUM 0xfff #define BIT_HI9Q_DESC_NUM(x) \ (((x) & BIT_MASK_HI9Q_DESC_NUM) << BIT_SHIFT_HI9Q_DESC_NUM) #define BITS_HI9Q_DESC_NUM (BIT_MASK_HI9Q_DESC_NUM << BIT_SHIFT_HI9Q_DESC_NUM) #define BIT_CLEAR_HI9Q_DESC_NUM(x) ((x) & (~BITS_HI9Q_DESC_NUM)) #define BIT_GET_HI9Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_HI9Q_DESC_NUM) & BIT_MASK_HI9Q_DESC_NUM) #define BIT_SET_HI9Q_DESC_NUM(x, v) \ (BIT_CLEAR_HI9Q_DESC_NUM(x) | BIT_HI9Q_DESC_NUM(v)) /* 2 REG_HI10Q_TXBD_NUM (Offset 0x13BC) */ #define BIT_HI10Q_FLAG BIT(14) #define BIT_SHIFT_HI10Q_DESC_MODE 12 #define BIT_MASK_HI10Q_DESC_MODE 0x3 #define BIT_HI10Q_DESC_MODE(x) \ (((x) & BIT_MASK_HI10Q_DESC_MODE) << BIT_SHIFT_HI10Q_DESC_MODE) #define BITS_HI10Q_DESC_MODE \ (BIT_MASK_HI10Q_DESC_MODE << BIT_SHIFT_HI10Q_DESC_MODE) #define BIT_CLEAR_HI10Q_DESC_MODE(x) ((x) & (~BITS_HI10Q_DESC_MODE)) #define BIT_GET_HI10Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_HI10Q_DESC_MODE) & BIT_MASK_HI10Q_DESC_MODE) #define BIT_SET_HI10Q_DESC_MODE(x, v) \ (BIT_CLEAR_HI10Q_DESC_MODE(x) | BIT_HI10Q_DESC_MODE(v)) #define BIT_SHIFT_HI10Q_DESC_NUM 0 #define BIT_MASK_HI10Q_DESC_NUM 0xfff #define BIT_HI10Q_DESC_NUM(x) \ (((x) & BIT_MASK_HI10Q_DESC_NUM) << BIT_SHIFT_HI10Q_DESC_NUM) #define BITS_HI10Q_DESC_NUM \ (BIT_MASK_HI10Q_DESC_NUM << BIT_SHIFT_HI10Q_DESC_NUM) #define BIT_CLEAR_HI10Q_DESC_NUM(x) ((x) & (~BITS_HI10Q_DESC_NUM)) #define BIT_GET_HI10Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_HI10Q_DESC_NUM) & BIT_MASK_HI10Q_DESC_NUM) #define BIT_SET_HI10Q_DESC_NUM(x, v) \ (BIT_CLEAR_HI10Q_DESC_NUM(x) | BIT_HI10Q_DESC_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HI2Q_TXBD_DESA_H (Offset 0x13BC) */ #define BIT_SHIFT_HI2Q_TXBD_DESA_H 0 #define BIT_MASK_HI2Q_TXBD_DESA_H 0xffffffffL #define BIT_HI2Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI2Q_TXBD_DESA_H) << BIT_SHIFT_HI2Q_TXBD_DESA_H) #define BITS_HI2Q_TXBD_DESA_H \ (BIT_MASK_HI2Q_TXBD_DESA_H << BIT_SHIFT_HI2Q_TXBD_DESA_H) #define BIT_CLEAR_HI2Q_TXBD_DESA_H(x) ((x) & (~BITS_HI2Q_TXBD_DESA_H)) #define BIT_GET_HI2Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_H) & BIT_MASK_HI2Q_TXBD_DESA_H) #define BIT_SET_HI2Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI2Q_TXBD_DESA_H(x) | BIT_HI2Q_TXBD_DESA_H(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI11Q_TXBD_NUM (Offset 0x13BE) */ #define BIT_HI11Q_FLAG BIT(14) #define BIT_SHIFT_HI11Q_DESC_MODE 12 #define BIT_MASK_HI11Q_DESC_MODE 0x3 #define BIT_HI11Q_DESC_MODE(x) \ (((x) & BIT_MASK_HI11Q_DESC_MODE) << BIT_SHIFT_HI11Q_DESC_MODE) #define BITS_HI11Q_DESC_MODE \ (BIT_MASK_HI11Q_DESC_MODE << BIT_SHIFT_HI11Q_DESC_MODE) #define BIT_CLEAR_HI11Q_DESC_MODE(x) ((x) & (~BITS_HI11Q_DESC_MODE)) #define BIT_GET_HI11Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_HI11Q_DESC_MODE) & BIT_MASK_HI11Q_DESC_MODE) #define BIT_SET_HI11Q_DESC_MODE(x, v) \ (BIT_CLEAR_HI11Q_DESC_MODE(x) | BIT_HI11Q_DESC_MODE(v)) #define BIT_SHIFT_HI11Q_DESC_NUM 0 #define BIT_MASK_HI11Q_DESC_NUM 0xfff #define BIT_HI11Q_DESC_NUM(x) \ (((x) & BIT_MASK_HI11Q_DESC_NUM) << BIT_SHIFT_HI11Q_DESC_NUM) #define BITS_HI11Q_DESC_NUM \ (BIT_MASK_HI11Q_DESC_NUM << BIT_SHIFT_HI11Q_DESC_NUM) #define BIT_CLEAR_HI11Q_DESC_NUM(x) ((x) & (~BITS_HI11Q_DESC_NUM)) #define BIT_GET_HI11Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_HI11Q_DESC_NUM) & BIT_MASK_HI11Q_DESC_NUM) #define BIT_SET_HI11Q_DESC_NUM(x, v) \ (BIT_CLEAR_HI11Q_DESC_NUM(x) | BIT_HI11Q_DESC_NUM(v)) /* 2 REG_HI12Q_TXBD_NUM (Offset 0x13C0) */ #define BIT_HI12Q_FLAG BIT(14) #define BIT_SHIFT_HI12Q_DESC_MODE 12 #define BIT_MASK_HI12Q_DESC_MODE 0x3 #define BIT_HI12Q_DESC_MODE(x) \ (((x) & BIT_MASK_HI12Q_DESC_MODE) << BIT_SHIFT_HI12Q_DESC_MODE) #define BITS_HI12Q_DESC_MODE \ (BIT_MASK_HI12Q_DESC_MODE << BIT_SHIFT_HI12Q_DESC_MODE) #define BIT_CLEAR_HI12Q_DESC_MODE(x) ((x) & (~BITS_HI12Q_DESC_MODE)) #define BIT_GET_HI12Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_HI12Q_DESC_MODE) & BIT_MASK_HI12Q_DESC_MODE) #define BIT_SET_HI12Q_DESC_MODE(x, v) \ (BIT_CLEAR_HI12Q_DESC_MODE(x) | BIT_HI12Q_DESC_MODE(v)) #define BIT_SHIFT_HI12Q_DESC_NUM 0 #define BIT_MASK_HI12Q_DESC_NUM 0xfff #define BIT_HI12Q_DESC_NUM(x) \ (((x) & BIT_MASK_HI12Q_DESC_NUM) << BIT_SHIFT_HI12Q_DESC_NUM) #define BITS_HI12Q_DESC_NUM \ (BIT_MASK_HI12Q_DESC_NUM << BIT_SHIFT_HI12Q_DESC_NUM) #define BIT_CLEAR_HI12Q_DESC_NUM(x) ((x) & (~BITS_HI12Q_DESC_NUM)) #define BIT_GET_HI12Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_HI12Q_DESC_NUM) & BIT_MASK_HI12Q_DESC_NUM) #define BIT_SET_HI12Q_DESC_NUM(x, v) \ (BIT_CLEAR_HI12Q_DESC_NUM(x) | BIT_HI12Q_DESC_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HI3Q_TXBD_DESA_L (Offset 0x13C0) */ #define BIT_SHIFT_HI3Q_TXBD_DESA_L 0 #define BIT_MASK_HI3Q_TXBD_DESA_L 0xffffffffL #define BIT_HI3Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI3Q_TXBD_DESA_L) << BIT_SHIFT_HI3Q_TXBD_DESA_L) #define BITS_HI3Q_TXBD_DESA_L \ (BIT_MASK_HI3Q_TXBD_DESA_L << BIT_SHIFT_HI3Q_TXBD_DESA_L) #define BIT_CLEAR_HI3Q_TXBD_DESA_L(x) ((x) & (~BITS_HI3Q_TXBD_DESA_L)) #define BIT_GET_HI3Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_L) & BIT_MASK_HI3Q_TXBD_DESA_L) #define BIT_SET_HI3Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI3Q_TXBD_DESA_L(x) | BIT_HI3Q_TXBD_DESA_L(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI13Q_TXBD_NUM (Offset 0x13C2) */ #define BIT_HI13Q_FLAG BIT(14) #define BIT_SHIFT_HI13Q_DESC_MODE 12 #define BIT_MASK_HI13Q_DESC_MODE 0x3 #define BIT_HI13Q_DESC_MODE(x) \ (((x) & BIT_MASK_HI13Q_DESC_MODE) << BIT_SHIFT_HI13Q_DESC_MODE) #define BITS_HI13Q_DESC_MODE \ (BIT_MASK_HI13Q_DESC_MODE << BIT_SHIFT_HI13Q_DESC_MODE) #define BIT_CLEAR_HI13Q_DESC_MODE(x) ((x) & (~BITS_HI13Q_DESC_MODE)) #define BIT_GET_HI13Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_HI13Q_DESC_MODE) & BIT_MASK_HI13Q_DESC_MODE) #define BIT_SET_HI13Q_DESC_MODE(x, v) \ (BIT_CLEAR_HI13Q_DESC_MODE(x) | BIT_HI13Q_DESC_MODE(v)) #define BIT_SHIFT_HI13Q_DESC_NUM 0 #define BIT_MASK_HI13Q_DESC_NUM 0xfff #define BIT_HI13Q_DESC_NUM(x) \ (((x) & BIT_MASK_HI13Q_DESC_NUM) << BIT_SHIFT_HI13Q_DESC_NUM) #define BITS_HI13Q_DESC_NUM \ (BIT_MASK_HI13Q_DESC_NUM << BIT_SHIFT_HI13Q_DESC_NUM) #define BIT_CLEAR_HI13Q_DESC_NUM(x) ((x) & (~BITS_HI13Q_DESC_NUM)) #define BIT_GET_HI13Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_HI13Q_DESC_NUM) & BIT_MASK_HI13Q_DESC_NUM) #define BIT_SET_HI13Q_DESC_NUM(x, v) \ (BIT_CLEAR_HI13Q_DESC_NUM(x) | BIT_HI13Q_DESC_NUM(v)) /* 2 REG_HI14Q_TXBD_NUM (Offset 0x13C4) */ #define BIT_HI14Q_FLAG BIT(14) #define BIT_SHIFT_HI14Q_DESC_MODE 12 #define BIT_MASK_HI14Q_DESC_MODE 0x3 #define BIT_HI14Q_DESC_MODE(x) \ (((x) & BIT_MASK_HI14Q_DESC_MODE) << BIT_SHIFT_HI14Q_DESC_MODE) #define BITS_HI14Q_DESC_MODE \ (BIT_MASK_HI14Q_DESC_MODE << BIT_SHIFT_HI14Q_DESC_MODE) #define BIT_CLEAR_HI14Q_DESC_MODE(x) ((x) & (~BITS_HI14Q_DESC_MODE)) #define BIT_GET_HI14Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_HI14Q_DESC_MODE) & BIT_MASK_HI14Q_DESC_MODE) #define BIT_SET_HI14Q_DESC_MODE(x, v) \ (BIT_CLEAR_HI14Q_DESC_MODE(x) | BIT_HI14Q_DESC_MODE(v)) #define BIT_SHIFT_HI14Q_DESC_NUM 0 #define BIT_MASK_HI14Q_DESC_NUM 0xfff #define BIT_HI14Q_DESC_NUM(x) \ (((x) & BIT_MASK_HI14Q_DESC_NUM) << BIT_SHIFT_HI14Q_DESC_NUM) #define BITS_HI14Q_DESC_NUM \ (BIT_MASK_HI14Q_DESC_NUM << BIT_SHIFT_HI14Q_DESC_NUM) #define BIT_CLEAR_HI14Q_DESC_NUM(x) ((x) & (~BITS_HI14Q_DESC_NUM)) #define BIT_GET_HI14Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_HI14Q_DESC_NUM) & BIT_MASK_HI14Q_DESC_NUM) #define BIT_SET_HI14Q_DESC_NUM(x, v) \ (BIT_CLEAR_HI14Q_DESC_NUM(x) | BIT_HI14Q_DESC_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HI3Q_TXBD_DESA_H (Offset 0x13C4) */ #define BIT_SHIFT_HI3Q_TXBD_DESA_H 0 #define BIT_MASK_HI3Q_TXBD_DESA_H 0xffffffffL #define BIT_HI3Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI3Q_TXBD_DESA_H) << BIT_SHIFT_HI3Q_TXBD_DESA_H) #define BITS_HI3Q_TXBD_DESA_H \ (BIT_MASK_HI3Q_TXBD_DESA_H << BIT_SHIFT_HI3Q_TXBD_DESA_H) #define BIT_CLEAR_HI3Q_TXBD_DESA_H(x) ((x) & (~BITS_HI3Q_TXBD_DESA_H)) #define BIT_GET_HI3Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_H) & BIT_MASK_HI3Q_TXBD_DESA_H) #define BIT_SET_HI3Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI3Q_TXBD_DESA_H(x) | BIT_HI3Q_TXBD_DESA_H(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_HI15Q_TXBD_NUM (Offset 0x13C6) */ #define BIT_HI15Q_FLAG BIT(14) #define BIT_SHIFT_HI15Q_DESC_MODE 12 #define BIT_MASK_HI15Q_DESC_MODE 0x3 #define BIT_HI15Q_DESC_MODE(x) \ (((x) & BIT_MASK_HI15Q_DESC_MODE) << BIT_SHIFT_HI15Q_DESC_MODE) #define BITS_HI15Q_DESC_MODE \ (BIT_MASK_HI15Q_DESC_MODE << BIT_SHIFT_HI15Q_DESC_MODE) #define BIT_CLEAR_HI15Q_DESC_MODE(x) ((x) & (~BITS_HI15Q_DESC_MODE)) #define BIT_GET_HI15Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_HI15Q_DESC_MODE) & BIT_MASK_HI15Q_DESC_MODE) #define BIT_SET_HI15Q_DESC_MODE(x, v) \ (BIT_CLEAR_HI15Q_DESC_MODE(x) | BIT_HI15Q_DESC_MODE(v)) #define BIT_SHIFT_HI15Q_DESC_NUM 0 #define BIT_MASK_HI15Q_DESC_NUM 0xfff #define BIT_HI15Q_DESC_NUM(x) \ (((x) & BIT_MASK_HI15Q_DESC_NUM) << BIT_SHIFT_HI15Q_DESC_NUM) #define BITS_HI15Q_DESC_NUM \ (BIT_MASK_HI15Q_DESC_NUM << BIT_SHIFT_HI15Q_DESC_NUM) #define BIT_CLEAR_HI15Q_DESC_NUM(x) ((x) & (~BITS_HI15Q_DESC_NUM)) #define BIT_GET_HI15Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_HI15Q_DESC_NUM) & BIT_MASK_HI15Q_DESC_NUM) #define BIT_SET_HI15Q_DESC_NUM(x, v) \ (BIT_CLEAR_HI15Q_DESC_NUM(x) | BIT_HI15Q_DESC_NUM(v)) /* 2 REG_HIQ_DMA_STOP (Offset 0x13C8) */ #define BIT_STOP_HI15Q BIT(7) #define BIT_STOP_HI14Q BIT(6) #define BIT_STOP_HI13Q BIT(5) #define BIT_STOP_HI12Q BIT(4) #define BIT_STOP_HI11Q BIT(3) #define BIT_STOP_HI10Q BIT(2) #define BIT_STOP_HI9Q BIT(1) #define BIT_STOP_HI8Q BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HI4Q_TXBD_DESA_L (Offset 0x13C8) */ #define BIT_SHIFT_HI4Q_TXBD_DESA_L 0 #define BIT_MASK_HI4Q_TXBD_DESA_L 0xffffffffL #define BIT_HI4Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI4Q_TXBD_DESA_L) << BIT_SHIFT_HI4Q_TXBD_DESA_L) #define BITS_HI4Q_TXBD_DESA_L \ (BIT_MASK_HI4Q_TXBD_DESA_L << BIT_SHIFT_HI4Q_TXBD_DESA_L) #define BIT_CLEAR_HI4Q_TXBD_DESA_L(x) ((x) & (~BITS_HI4Q_TXBD_DESA_L)) #define BIT_GET_HI4Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_L) & BIT_MASK_HI4Q_TXBD_DESA_L) #define BIT_SET_HI4Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI4Q_TXBD_DESA_L(x) | BIT_HI4Q_TXBD_DESA_L(v)) /* 2 REG_HI4Q_TXBD_DESA_H (Offset 0x13CC) */ #define BIT_SHIFT_HI4Q_TXBD_DESA_H 0 #define BIT_MASK_HI4Q_TXBD_DESA_H 0xffffffffL #define BIT_HI4Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI4Q_TXBD_DESA_H) << BIT_SHIFT_HI4Q_TXBD_DESA_H) #define BITS_HI4Q_TXBD_DESA_H \ (BIT_MASK_HI4Q_TXBD_DESA_H << BIT_SHIFT_HI4Q_TXBD_DESA_H) #define BIT_CLEAR_HI4Q_TXBD_DESA_H(x) ((x) & (~BITS_HI4Q_TXBD_DESA_H)) #define BIT_GET_HI4Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_H) & BIT_MASK_HI4Q_TXBD_DESA_H) #define BIT_SET_HI4Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI4Q_TXBD_DESA_H(x) | BIT_HI4Q_TXBD_DESA_H(v)) /* 2 REG_HI5Q_TXBD_DESA_L (Offset 0x13D0) */ #define BIT_SHIFT_HI5Q_TXBD_DESA_L 0 #define BIT_MASK_HI5Q_TXBD_DESA_L 0xffffffffL #define BIT_HI5Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI5Q_TXBD_DESA_L) << BIT_SHIFT_HI5Q_TXBD_DESA_L) #define BITS_HI5Q_TXBD_DESA_L \ (BIT_MASK_HI5Q_TXBD_DESA_L << BIT_SHIFT_HI5Q_TXBD_DESA_L) #define BIT_CLEAR_HI5Q_TXBD_DESA_L(x) ((x) & (~BITS_HI5Q_TXBD_DESA_L)) #define BIT_GET_HI5Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_L) & BIT_MASK_HI5Q_TXBD_DESA_L) #define BIT_SET_HI5Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI5Q_TXBD_DESA_L(x) | BIT_HI5Q_TXBD_DESA_L(v)) /* 2 REG_HI5Q_TXBD_DESA_H (Offset 0x13D4) */ #define BIT_SHIFT_HI5Q_TXBD_DESA_H 0 #define BIT_MASK_HI5Q_TXBD_DESA_H 0xffffffffL #define BIT_HI5Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI5Q_TXBD_DESA_H) << BIT_SHIFT_HI5Q_TXBD_DESA_H) #define BITS_HI5Q_TXBD_DESA_H \ (BIT_MASK_HI5Q_TXBD_DESA_H << BIT_SHIFT_HI5Q_TXBD_DESA_H) #define BIT_CLEAR_HI5Q_TXBD_DESA_H(x) ((x) & (~BITS_HI5Q_TXBD_DESA_H)) #define BIT_GET_HI5Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_H) & BIT_MASK_HI5Q_TXBD_DESA_H) #define BIT_SET_HI5Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI5Q_TXBD_DESA_H(x) | BIT_HI5Q_TXBD_DESA_H(v)) /* 2 REG_HI6Q_TXBD_DESA_L (Offset 0x13D8) */ #define BIT_SHIFT_HI6Q_TXBD_DESA_L 0 #define BIT_MASK_HI6Q_TXBD_DESA_L 0xffffffffL #define BIT_HI6Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI6Q_TXBD_DESA_L) << BIT_SHIFT_HI6Q_TXBD_DESA_L) #define BITS_HI6Q_TXBD_DESA_L \ (BIT_MASK_HI6Q_TXBD_DESA_L << BIT_SHIFT_HI6Q_TXBD_DESA_L) #define BIT_CLEAR_HI6Q_TXBD_DESA_L(x) ((x) & (~BITS_HI6Q_TXBD_DESA_L)) #define BIT_GET_HI6Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_L) & BIT_MASK_HI6Q_TXBD_DESA_L) #define BIT_SET_HI6Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI6Q_TXBD_DESA_L(x) | BIT_HI6Q_TXBD_DESA_L(v)) /* 2 REG_HI6Q_TXBD_DESA_H (Offset 0x13DC) */ #define BIT_SHIFT_HI6Q_TXBD_DESA_H 0 #define BIT_MASK_HI6Q_TXBD_DESA_H 0xffffffffL #define BIT_HI6Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI6Q_TXBD_DESA_H) << BIT_SHIFT_HI6Q_TXBD_DESA_H) #define BITS_HI6Q_TXBD_DESA_H \ (BIT_MASK_HI6Q_TXBD_DESA_H << BIT_SHIFT_HI6Q_TXBD_DESA_H) #define BIT_CLEAR_HI6Q_TXBD_DESA_H(x) ((x) & (~BITS_HI6Q_TXBD_DESA_H)) #define BIT_GET_HI6Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_H) & BIT_MASK_HI6Q_TXBD_DESA_H) #define BIT_SET_HI6Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI6Q_TXBD_DESA_H(x) | BIT_HI6Q_TXBD_DESA_H(v)) /* 2 REG_HI7Q_TXBD_DESA_L (Offset 0x13E0) */ #define BIT_SHIFT_HI7Q_TXBD_DESA_L 0 #define BIT_MASK_HI7Q_TXBD_DESA_L 0xffffffffL #define BIT_HI7Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI7Q_TXBD_DESA_L) << BIT_SHIFT_HI7Q_TXBD_DESA_L) #define BITS_HI7Q_TXBD_DESA_L \ (BIT_MASK_HI7Q_TXBD_DESA_L << BIT_SHIFT_HI7Q_TXBD_DESA_L) #define BIT_CLEAR_HI7Q_TXBD_DESA_L(x) ((x) & (~BITS_HI7Q_TXBD_DESA_L)) #define BIT_GET_HI7Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_L) & BIT_MASK_HI7Q_TXBD_DESA_L) #define BIT_SET_HI7Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI7Q_TXBD_DESA_L(x) | BIT_HI7Q_TXBD_DESA_L(v)) /* 2 REG_HI7Q_TXBD_DESA_H (Offset 0x13E4) */ #define BIT_SHIFT_HI7Q_TXBD_DESA_H 0 #define BIT_MASK_HI7Q_TXBD_DESA_H 0xffffffffL #define BIT_HI7Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI7Q_TXBD_DESA_H) << BIT_SHIFT_HI7Q_TXBD_DESA_H) #define BITS_HI7Q_TXBD_DESA_H \ (BIT_MASK_HI7Q_TXBD_DESA_H << BIT_SHIFT_HI7Q_TXBD_DESA_H) #define BIT_CLEAR_HI7Q_TXBD_DESA_H(x) ((x) & (~BITS_HI7Q_TXBD_DESA_H)) #define BIT_GET_HI7Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_H) & BIT_MASK_HI7Q_TXBD_DESA_H) #define BIT_SET_HI7Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI7Q_TXBD_DESA_H(x) | BIT_HI7Q_TXBD_DESA_H(v)) /* 2 REG_ACH8_ACH9_TXBD_NUM (Offset 0x13E8) */ #define BIT_PCIE_ACH9_FLAG BIT(30) #define BIT_SHIFT_ACH9_DESC_MODE 28 #define BIT_MASK_ACH9_DESC_MODE 0x3 #define BIT_ACH9_DESC_MODE(x) \ (((x) & BIT_MASK_ACH9_DESC_MODE) << BIT_SHIFT_ACH9_DESC_MODE) #define BITS_ACH9_DESC_MODE \ (BIT_MASK_ACH9_DESC_MODE << BIT_SHIFT_ACH9_DESC_MODE) #define BIT_CLEAR_ACH9_DESC_MODE(x) ((x) & (~BITS_ACH9_DESC_MODE)) #define BIT_GET_ACH9_DESC_MODE(x) \ (((x) >> BIT_SHIFT_ACH9_DESC_MODE) & BIT_MASK_ACH9_DESC_MODE) #define BIT_SET_ACH9_DESC_MODE(x, v) \ (BIT_CLEAR_ACH9_DESC_MODE(x) | BIT_ACH9_DESC_MODE(v)) #define BIT_SHIFT_ACH9_DESC_NUM 16 #define BIT_MASK_ACH9_DESC_NUM 0xfff #define BIT_ACH9_DESC_NUM(x) \ (((x) & BIT_MASK_ACH9_DESC_NUM) << BIT_SHIFT_ACH9_DESC_NUM) #define BITS_ACH9_DESC_NUM (BIT_MASK_ACH9_DESC_NUM << BIT_SHIFT_ACH9_DESC_NUM) #define BIT_CLEAR_ACH9_DESC_NUM(x) ((x) & (~BITS_ACH9_DESC_NUM)) #define BIT_GET_ACH9_DESC_NUM(x) \ (((x) >> BIT_SHIFT_ACH9_DESC_NUM) & BIT_MASK_ACH9_DESC_NUM) #define BIT_SET_ACH9_DESC_NUM(x, v) \ (BIT_CLEAR_ACH9_DESC_NUM(x) | BIT_ACH9_DESC_NUM(v)) #define BIT_PCIE_ACH8_FLAG BIT(14) #define BIT_SHIFT_ACH8_DESC_MODE 12 #define BIT_MASK_ACH8_DESC_MODE 0x3 #define BIT_ACH8_DESC_MODE(x) \ (((x) & BIT_MASK_ACH8_DESC_MODE) << BIT_SHIFT_ACH8_DESC_MODE) #define BITS_ACH8_DESC_MODE \ (BIT_MASK_ACH8_DESC_MODE << BIT_SHIFT_ACH8_DESC_MODE) #define BIT_CLEAR_ACH8_DESC_MODE(x) ((x) & (~BITS_ACH8_DESC_MODE)) #define BIT_GET_ACH8_DESC_MODE(x) \ (((x) >> BIT_SHIFT_ACH8_DESC_MODE) & BIT_MASK_ACH8_DESC_MODE) #define BIT_SET_ACH8_DESC_MODE(x, v) \ (BIT_CLEAR_ACH8_DESC_MODE(x) | BIT_ACH8_DESC_MODE(v)) #define BIT_SHIFT_ACH8_DESC_NUM 0 #define BIT_MASK_ACH8_DESC_NUM 0xfff #define BIT_ACH8_DESC_NUM(x) \ (((x) & BIT_MASK_ACH8_DESC_NUM) << BIT_SHIFT_ACH8_DESC_NUM) #define BITS_ACH8_DESC_NUM (BIT_MASK_ACH8_DESC_NUM << BIT_SHIFT_ACH8_DESC_NUM) #define BIT_CLEAR_ACH8_DESC_NUM(x) ((x) & (~BITS_ACH8_DESC_NUM)) #define BIT_GET_ACH8_DESC_NUM(x) \ (((x) >> BIT_SHIFT_ACH8_DESC_NUM) & BIT_MASK_ACH8_DESC_NUM) #define BIT_SET_ACH8_DESC_NUM(x, v) \ (BIT_CLEAR_ACH8_DESC_NUM(x) | BIT_ACH8_DESC_NUM(v)) /* 2 REG_ACH10_ACH11_TXBD_NUM (Offset 0x13EC) */ #define BIT_PCIE_ACH11_FLAG BIT(30) #define BIT_SHIFT_ACH11_DESC_MODE 28 #define BIT_MASK_ACH11_DESC_MODE 0x3 #define BIT_ACH11_DESC_MODE(x) \ (((x) & BIT_MASK_ACH11_DESC_MODE) << BIT_SHIFT_ACH11_DESC_MODE) #define BITS_ACH11_DESC_MODE \ (BIT_MASK_ACH11_DESC_MODE << BIT_SHIFT_ACH11_DESC_MODE) #define BIT_CLEAR_ACH11_DESC_MODE(x) ((x) & (~BITS_ACH11_DESC_MODE)) #define BIT_GET_ACH11_DESC_MODE(x) \ (((x) >> BIT_SHIFT_ACH11_DESC_MODE) & BIT_MASK_ACH11_DESC_MODE) #define BIT_SET_ACH11_DESC_MODE(x, v) \ (BIT_CLEAR_ACH11_DESC_MODE(x) | BIT_ACH11_DESC_MODE(v)) #define BIT_SHIFT_ACH11_DESC_NUM 16 #define BIT_MASK_ACH11_DESC_NUM 0xfff #define BIT_ACH11_DESC_NUM(x) \ (((x) & BIT_MASK_ACH11_DESC_NUM) << BIT_SHIFT_ACH11_DESC_NUM) #define BITS_ACH11_DESC_NUM \ (BIT_MASK_ACH11_DESC_NUM << BIT_SHIFT_ACH11_DESC_NUM) #define BIT_CLEAR_ACH11_DESC_NUM(x) ((x) & (~BITS_ACH11_DESC_NUM)) #define BIT_GET_ACH11_DESC_NUM(x) \ (((x) >> BIT_SHIFT_ACH11_DESC_NUM) & BIT_MASK_ACH11_DESC_NUM) #define BIT_SET_ACH11_DESC_NUM(x, v) \ (BIT_CLEAR_ACH11_DESC_NUM(x) | BIT_ACH11_DESC_NUM(v)) #define BIT_PCIE_ACH10_FLAG BIT(14) #define BIT_SHIFT_ACH10_DESC_MODE 12 #define BIT_MASK_ACH10_DESC_MODE 0x3 #define BIT_ACH10_DESC_MODE(x) \ (((x) & BIT_MASK_ACH10_DESC_MODE) << BIT_SHIFT_ACH10_DESC_MODE) #define BITS_ACH10_DESC_MODE \ (BIT_MASK_ACH10_DESC_MODE << BIT_SHIFT_ACH10_DESC_MODE) #define BIT_CLEAR_ACH10_DESC_MODE(x) ((x) & (~BITS_ACH10_DESC_MODE)) #define BIT_GET_ACH10_DESC_MODE(x) \ (((x) >> BIT_SHIFT_ACH10_DESC_MODE) & BIT_MASK_ACH10_DESC_MODE) #define BIT_SET_ACH10_DESC_MODE(x, v) \ (BIT_CLEAR_ACH10_DESC_MODE(x) | BIT_ACH10_DESC_MODE(v)) #define BIT_SHIFT_ACH10_DESC_NUM 0 #define BIT_MASK_ACH10_DESC_NUM 0xfff #define BIT_ACH10_DESC_NUM(x) \ (((x) & BIT_MASK_ACH10_DESC_NUM) << BIT_SHIFT_ACH10_DESC_NUM) #define BITS_ACH10_DESC_NUM \ (BIT_MASK_ACH10_DESC_NUM << BIT_SHIFT_ACH10_DESC_NUM) #define BIT_CLEAR_ACH10_DESC_NUM(x) ((x) & (~BITS_ACH10_DESC_NUM)) #define BIT_GET_ACH10_DESC_NUM(x) \ (((x) >> BIT_SHIFT_ACH10_DESC_NUM) & BIT_MASK_ACH10_DESC_NUM) #define BIT_SET_ACH10_DESC_NUM(x, v) \ (BIT_CLEAR_ACH10_DESC_NUM(x) | BIT_ACH10_DESC_NUM(v)) /* 2 REG_ACH12_ACH13_TXBD_NUM (Offset 0x13F0) */ #define BIT_PCIE_ACH13_FLAG BIT(30) #define BIT_SHIFT_ACH13_DESC_MODE 28 #define BIT_MASK_ACH13_DESC_MODE 0x3 #define BIT_ACH13_DESC_MODE(x) \ (((x) & BIT_MASK_ACH13_DESC_MODE) << BIT_SHIFT_ACH13_DESC_MODE) #define BITS_ACH13_DESC_MODE \ (BIT_MASK_ACH13_DESC_MODE << BIT_SHIFT_ACH13_DESC_MODE) #define BIT_CLEAR_ACH13_DESC_MODE(x) ((x) & (~BITS_ACH13_DESC_MODE)) #define BIT_GET_ACH13_DESC_MODE(x) \ (((x) >> BIT_SHIFT_ACH13_DESC_MODE) & BIT_MASK_ACH13_DESC_MODE) #define BIT_SET_ACH13_DESC_MODE(x, v) \ (BIT_CLEAR_ACH13_DESC_MODE(x) | BIT_ACH13_DESC_MODE(v)) #define BIT_SHIFT_ACH13_DESC_NUM 16 #define BIT_MASK_ACH13_DESC_NUM 0xfff #define BIT_ACH13_DESC_NUM(x) \ (((x) & BIT_MASK_ACH13_DESC_NUM) << BIT_SHIFT_ACH13_DESC_NUM) #define BITS_ACH13_DESC_NUM \ (BIT_MASK_ACH13_DESC_NUM << BIT_SHIFT_ACH13_DESC_NUM) #define BIT_CLEAR_ACH13_DESC_NUM(x) ((x) & (~BITS_ACH13_DESC_NUM)) #define BIT_GET_ACH13_DESC_NUM(x) \ (((x) >> BIT_SHIFT_ACH13_DESC_NUM) & BIT_MASK_ACH13_DESC_NUM) #define BIT_SET_ACH13_DESC_NUM(x, v) \ (BIT_CLEAR_ACH13_DESC_NUM(x) | BIT_ACH13_DESC_NUM(v)) #define BIT_PCIE_ACH12_FLAG BIT(14) #define BIT_SHIFT_ACH12_DESC_MODE 12 #define BIT_MASK_ACH12_DESC_MODE 0x3 #define BIT_ACH12_DESC_MODE(x) \ (((x) & BIT_MASK_ACH12_DESC_MODE) << BIT_SHIFT_ACH12_DESC_MODE) #define BITS_ACH12_DESC_MODE \ (BIT_MASK_ACH12_DESC_MODE << BIT_SHIFT_ACH12_DESC_MODE) #define BIT_CLEAR_ACH12_DESC_MODE(x) ((x) & (~BITS_ACH12_DESC_MODE)) #define BIT_GET_ACH12_DESC_MODE(x) \ (((x) >> BIT_SHIFT_ACH12_DESC_MODE) & BIT_MASK_ACH12_DESC_MODE) #define BIT_SET_ACH12_DESC_MODE(x, v) \ (BIT_CLEAR_ACH12_DESC_MODE(x) | BIT_ACH12_DESC_MODE(v)) #define BIT_SHIFT_ACH12_DESC_NUM 0 #define BIT_MASK_ACH12_DESC_NUM 0xfff #define BIT_ACH12_DESC_NUM(x) \ (((x) & BIT_MASK_ACH12_DESC_NUM) << BIT_SHIFT_ACH12_DESC_NUM) #define BITS_ACH12_DESC_NUM \ (BIT_MASK_ACH12_DESC_NUM << BIT_SHIFT_ACH12_DESC_NUM) #define BIT_CLEAR_ACH12_DESC_NUM(x) ((x) & (~BITS_ACH12_DESC_NUM)) #define BIT_GET_ACH12_DESC_NUM(x) \ (((x) >> BIT_SHIFT_ACH12_DESC_NUM) & BIT_MASK_ACH12_DESC_NUM) #define BIT_SET_ACH12_DESC_NUM(x, v) \ (BIT_CLEAR_ACH12_DESC_NUM(x) | BIT_ACH12_DESC_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_OLD_DEHANG (Offset 0x13F4) */ #define BIT_OLD_DEHANG BIT(1) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_ACH4_TXBD_DESA_L (Offset 0x13F8) */ #define BIT_SHIFT_ACH4_TXBD_DESA_L 0 #define BIT_MASK_ACH4_TXBD_DESA_L 0xffffffffL #define BIT_ACH4_TXBD_DESA_L(x) \ (((x) & BIT_MASK_ACH4_TXBD_DESA_L) << BIT_SHIFT_ACH4_TXBD_DESA_L) #define BITS_ACH4_TXBD_DESA_L \ (BIT_MASK_ACH4_TXBD_DESA_L << BIT_SHIFT_ACH4_TXBD_DESA_L) #define BIT_CLEAR_ACH4_TXBD_DESA_L(x) ((x) & (~BITS_ACH4_TXBD_DESA_L)) #define BIT_GET_ACH4_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_ACH4_TXBD_DESA_L) & BIT_MASK_ACH4_TXBD_DESA_L) #define BIT_SET_ACH4_TXBD_DESA_L(x, v) \ (BIT_CLEAR_ACH4_TXBD_DESA_L(x) | BIT_ACH4_TXBD_DESA_L(v)) /* 2 REG_ACH4_TXBD_DESA_H (Offset 0x13FC) */ #define BIT_SHIFT_ACH4_TXBD_DESA_H 0 #define BIT_MASK_ACH4_TXBD_DESA_H 0xffffffffL #define BIT_ACH4_TXBD_DESA_H(x) \ (((x) & BIT_MASK_ACH4_TXBD_DESA_H) << BIT_SHIFT_ACH4_TXBD_DESA_H) #define BITS_ACH4_TXBD_DESA_H \ (BIT_MASK_ACH4_TXBD_DESA_H << BIT_SHIFT_ACH4_TXBD_DESA_H) #define BIT_CLEAR_ACH4_TXBD_DESA_H(x) ((x) & (~BITS_ACH4_TXBD_DESA_H)) #define BIT_GET_ACH4_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_ACH4_TXBD_DESA_H) & BIT_MASK_ACH4_TXBD_DESA_H) #define BIT_SET_ACH4_TXBD_DESA_H(x, v) \ (BIT_CLEAR_ACH4_TXBD_DESA_H(x) | BIT_ACH4_TXBD_DESA_H(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q0_Q1_INFO (Offset 0x1400) */ #define BIT_SHIFT_AC1_PKT_INFO 16 #define BIT_MASK_AC1_PKT_INFO 0xfff #define BIT_AC1_PKT_INFO(x) \ (((x) & BIT_MASK_AC1_PKT_INFO) << BIT_SHIFT_AC1_PKT_INFO) #define BITS_AC1_PKT_INFO (BIT_MASK_AC1_PKT_INFO << BIT_SHIFT_AC1_PKT_INFO) #define BIT_CLEAR_AC1_PKT_INFO(x) ((x) & (~BITS_AC1_PKT_INFO)) #define BIT_GET_AC1_PKT_INFO(x) \ (((x) >> BIT_SHIFT_AC1_PKT_INFO) & BIT_MASK_AC1_PKT_INFO) #define BIT_SET_AC1_PKT_INFO(x, v) \ (BIT_CLEAR_AC1_PKT_INFO(x) | BIT_AC1_PKT_INFO(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MU_OFFSET (Offset 0x1400) */ #define BIT_SHIFT_MU_RATETABLE_OFFSET 16 #define BIT_MASK_MU_RATETABLE_OFFSET 0x1ff #define BIT_MU_RATETABLE_OFFSET(x) \ (((x) & BIT_MASK_MU_RATETABLE_OFFSET) << BIT_SHIFT_MU_RATETABLE_OFFSET) #define BITS_MU_RATETABLE_OFFSET \ (BIT_MASK_MU_RATETABLE_OFFSET << BIT_SHIFT_MU_RATETABLE_OFFSET) #define BIT_CLEAR_MU_RATETABLE_OFFSET(x) ((x) & (~BITS_MU_RATETABLE_OFFSET)) #define BIT_GET_MU_RATETABLE_OFFSET(x) \ (((x) >> BIT_SHIFT_MU_RATETABLE_OFFSET) & BIT_MASK_MU_RATETABLE_OFFSET) #define BIT_SET_MU_RATETABLE_OFFSET(x, v) \ (BIT_CLEAR_MU_RATETABLE_OFFSET(x) | BIT_MU_RATETABLE_OFFSET(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q0_Q1_INFO (Offset 0x1400) */ #define BIT_SHIFT_AC0_PKT_INFO 0 #define BIT_MASK_AC0_PKT_INFO 0xfff #define BIT_AC0_PKT_INFO(x) \ (((x) & BIT_MASK_AC0_PKT_INFO) << BIT_SHIFT_AC0_PKT_INFO) #define BITS_AC0_PKT_INFO (BIT_MASK_AC0_PKT_INFO << BIT_SHIFT_AC0_PKT_INFO) #define BIT_CLEAR_AC0_PKT_INFO(x) ((x) & (~BITS_AC0_PKT_INFO)) #define BIT_GET_AC0_PKT_INFO(x) \ (((x) >> BIT_SHIFT_AC0_PKT_INFO) & BIT_MASK_AC0_PKT_INFO) #define BIT_SET_AC0_PKT_INFO(x, v) \ (BIT_CLEAR_AC0_PKT_INFO(x) | BIT_AC0_PKT_INFO(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_ARFR6 (Offset 0x1400) */ #define BIT_SHIFT_ARFR6_V1 0 #define BIT_MASK_ARFR6_V1 0xffffffffffffffffL #define BIT_ARFR6_V1(x) (((x) & BIT_MASK_ARFR6_V1) << BIT_SHIFT_ARFR6_V1) #define BITS_ARFR6_V1 (BIT_MASK_ARFR6_V1 << BIT_SHIFT_ARFR6_V1) #define BIT_CLEAR_ARFR6_V1(x) ((x) & (~BITS_ARFR6_V1)) #define BIT_GET_ARFR6_V1(x) (((x) >> BIT_SHIFT_ARFR6_V1) & BIT_MASK_ARFR6_V1) #define BIT_SET_ARFR6_V1(x, v) (BIT_CLEAR_ARFR6_V1(x) | BIT_ARFR6_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MU_OFFSET (Offset 0x1400) */ #define BIT_SHIFT_MU_SCORETABLE_OFFSET 0 #define BIT_MASK_MU_SCORETABLE_OFFSET 0x1ff #define BIT_MU_SCORETABLE_OFFSET(x) \ (((x) & BIT_MASK_MU_SCORETABLE_OFFSET) \ << BIT_SHIFT_MU_SCORETABLE_OFFSET) #define BITS_MU_SCORETABLE_OFFSET \ (BIT_MASK_MU_SCORETABLE_OFFSET << BIT_SHIFT_MU_SCORETABLE_OFFSET) #define BIT_CLEAR_MU_SCORETABLE_OFFSET(x) ((x) & (~BITS_MU_SCORETABLE_OFFSET)) #define BIT_GET_MU_SCORETABLE_OFFSET(x) \ (((x) >> BIT_SHIFT_MU_SCORETABLE_OFFSET) & \ BIT_MASK_MU_SCORETABLE_OFFSET) #define BIT_SET_MU_SCORETABLE_OFFSET(x, v) \ (BIT_CLEAR_MU_SCORETABLE_OFFSET(x) | BIT_MU_SCORETABLE_OFFSET(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q2_Q3_INFO (Offset 0x1404) */ #define BIT_SHIFT_AC3_PKT_INFO 16 #define BIT_MASK_AC3_PKT_INFO 0xfff #define BIT_AC3_PKT_INFO(x) \ (((x) & BIT_MASK_AC3_PKT_INFO) << BIT_SHIFT_AC3_PKT_INFO) #define BITS_AC3_PKT_INFO (BIT_MASK_AC3_PKT_INFO << BIT_SHIFT_AC3_PKT_INFO) #define BIT_CLEAR_AC3_PKT_INFO(x) ((x) & (~BITS_AC3_PKT_INFO)) #define BIT_GET_AC3_PKT_INFO(x) \ (((x) >> BIT_SHIFT_AC3_PKT_INFO) & BIT_MASK_AC3_PKT_INFO) #define BIT_SET_AC3_PKT_INFO(x, v) \ (BIT_CLEAR_AC3_PKT_INFO(x) | BIT_AC3_PKT_INFO(v)) #define BIT_SHIFT_AC2_PKT_INFO 0 #define BIT_MASK_AC2_PKT_INFO 0xfff #define BIT_AC2_PKT_INFO(x) \ (((x) & BIT_MASK_AC2_PKT_INFO) << BIT_SHIFT_AC2_PKT_INFO) #define BITS_AC2_PKT_INFO (BIT_MASK_AC2_PKT_INFO << BIT_SHIFT_AC2_PKT_INFO) #define BIT_CLEAR_AC2_PKT_INFO(x) ((x) & (~BITS_AC2_PKT_INFO)) #define BIT_GET_AC2_PKT_INFO(x) \ (((x) >> BIT_SHIFT_AC2_PKT_INFO) & BIT_MASK_AC2_PKT_INFO) #define BIT_SET_AC2_PKT_INFO(x, v) \ (BIT_CLEAR_AC2_PKT_INFO(x) | BIT_AC2_PKT_INFO(v)) /* 2 REG_Q4_Q5_INFO (Offset 0x1408) */ #define BIT_SHIFT_AC5_PKT_INFO 16 #define BIT_MASK_AC5_PKT_INFO 0xfff #define BIT_AC5_PKT_INFO(x) \ (((x) & BIT_MASK_AC5_PKT_INFO) << BIT_SHIFT_AC5_PKT_INFO) #define BITS_AC5_PKT_INFO (BIT_MASK_AC5_PKT_INFO << BIT_SHIFT_AC5_PKT_INFO) #define BIT_CLEAR_AC5_PKT_INFO(x) ((x) & (~BITS_AC5_PKT_INFO)) #define BIT_GET_AC5_PKT_INFO(x) \ (((x) >> BIT_SHIFT_AC5_PKT_INFO) & BIT_MASK_AC5_PKT_INFO) #define BIT_SET_AC5_PKT_INFO(x, v) \ (BIT_CLEAR_AC5_PKT_INFO(x) | BIT_AC5_PKT_INFO(v)) #define BIT_SHIFT_AC4_PKT_INFO 0 #define BIT_MASK_AC4_PKT_INFO 0xfff #define BIT_AC4_PKT_INFO(x) \ (((x) & BIT_MASK_AC4_PKT_INFO) << BIT_SHIFT_AC4_PKT_INFO) #define BITS_AC4_PKT_INFO (BIT_MASK_AC4_PKT_INFO << BIT_SHIFT_AC4_PKT_INFO) #define BIT_CLEAR_AC4_PKT_INFO(x) ((x) & (~BITS_AC4_PKT_INFO)) #define BIT_GET_AC4_PKT_INFO(x) \ (((x) >> BIT_SHIFT_AC4_PKT_INFO) & BIT_MASK_AC4_PKT_INFO) #define BIT_SET_AC4_PKT_INFO(x, v) \ (BIT_CLEAR_AC4_PKT_INFO(x) | BIT_AC4_PKT_INFO(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_ARFR7 (Offset 0x1408) */ #define BIT_SHIFT_ARFR7_V1 0 #define BIT_MASK_ARFR7_V1 0xffffffffffffffffL #define BIT_ARFR7_V1(x) (((x) & BIT_MASK_ARFR7_V1) << BIT_SHIFT_ARFR7_V1) #define BITS_ARFR7_V1 (BIT_MASK_ARFR7_V1 << BIT_SHIFT_ARFR7_V1) #define BIT_CLEAR_ARFR7_V1(x) ((x) & (~BITS_ARFR7_V1)) #define BIT_GET_ARFR7_V1(x) (((x) >> BIT_SHIFT_ARFR7_V1) & BIT_MASK_ARFR7_V1) #define BIT_SET_ARFR7_V1(x, v) (BIT_CLEAR_ARFR7_V1(x) | BIT_ARFR7_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_Q6_Q7_INFO (Offset 0x140C) */ #define BIT_SHIFT_AC7_PKT_INFO 16 #define BIT_MASK_AC7_PKT_INFO 0xfff #define BIT_AC7_PKT_INFO(x) \ (((x) & BIT_MASK_AC7_PKT_INFO) << BIT_SHIFT_AC7_PKT_INFO) #define BITS_AC7_PKT_INFO (BIT_MASK_AC7_PKT_INFO << BIT_SHIFT_AC7_PKT_INFO) #define BIT_CLEAR_AC7_PKT_INFO(x) ((x) & (~BITS_AC7_PKT_INFO)) #define BIT_GET_AC7_PKT_INFO(x) \ (((x) >> BIT_SHIFT_AC7_PKT_INFO) & BIT_MASK_AC7_PKT_INFO) #define BIT_SET_AC7_PKT_INFO(x, v) \ (BIT_CLEAR_AC7_PKT_INFO(x) | BIT_AC7_PKT_INFO(v)) #define BIT_SHIFT_AC6_PKT_INFO 0 #define BIT_MASK_AC6_PKT_INFO 0xfff #define BIT_AC6_PKT_INFO(x) \ (((x) & BIT_MASK_AC6_PKT_INFO) << BIT_SHIFT_AC6_PKT_INFO) #define BITS_AC6_PKT_INFO (BIT_MASK_AC6_PKT_INFO << BIT_SHIFT_AC6_PKT_INFO) #define BIT_CLEAR_AC6_PKT_INFO(x) ((x) & (~BITS_AC6_PKT_INFO)) #define BIT_GET_AC6_PKT_INFO(x) \ (((x) >> BIT_SHIFT_AC6_PKT_INFO) & BIT_MASK_AC6_PKT_INFO) #define BIT_SET_AC6_PKT_INFO(x, v) \ (BIT_CLEAR_AC6_PKT_INFO(x) | BIT_AC6_PKT_INFO(v)) /* 2 REG_MGQ_HIQ_INFO (Offset 0x1410) */ #define BIT_SHIFT_HIQ_PKT_INFO 16 #define BIT_MASK_HIQ_PKT_INFO 0xfff #define BIT_HIQ_PKT_INFO(x) \ (((x) & BIT_MASK_HIQ_PKT_INFO) << BIT_SHIFT_HIQ_PKT_INFO) #define BITS_HIQ_PKT_INFO (BIT_MASK_HIQ_PKT_INFO << BIT_SHIFT_HIQ_PKT_INFO) #define BIT_CLEAR_HIQ_PKT_INFO(x) ((x) & (~BITS_HIQ_PKT_INFO)) #define BIT_GET_HIQ_PKT_INFO(x) \ (((x) >> BIT_SHIFT_HIQ_PKT_INFO) & BIT_MASK_HIQ_PKT_INFO) #define BIT_SET_HIQ_PKT_INFO(x, v) \ (BIT_CLEAR_HIQ_PKT_INFO(x) | BIT_HIQ_PKT_INFO(v)) #define BIT_SHIFT_MGQ_PKT_INFO 0 #define BIT_MASK_MGQ_PKT_INFO 0xfff #define BIT_MGQ_PKT_INFO(x) \ (((x) & BIT_MASK_MGQ_PKT_INFO) << BIT_SHIFT_MGQ_PKT_INFO) #define BITS_MGQ_PKT_INFO (BIT_MASK_MGQ_PKT_INFO << BIT_SHIFT_MGQ_PKT_INFO) #define BIT_CLEAR_MGQ_PKT_INFO(x) ((x) & (~BITS_MGQ_PKT_INFO)) #define BIT_GET_MGQ_PKT_INFO(x) \ (((x) >> BIT_SHIFT_MGQ_PKT_INFO) & BIT_MASK_MGQ_PKT_INFO) #define BIT_SET_MGQ_PKT_INFO(x, v) \ (BIT_CLEAR_MGQ_PKT_INFO(x) | BIT_MGQ_PKT_INFO(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_ARFR8 (Offset 0x1410) */ #define BIT_SHIFT_ARFR8_V1 0 #define BIT_MASK_ARFR8_V1 0xffffffffffffffffL #define BIT_ARFR8_V1(x) (((x) & BIT_MASK_ARFR8_V1) << BIT_SHIFT_ARFR8_V1) #define BITS_ARFR8_V1 (BIT_MASK_ARFR8_V1 << BIT_SHIFT_ARFR8_V1) #define BIT_CLEAR_ARFR8_V1(x) ((x) & (~BITS_ARFR8_V1)) #define BIT_GET_ARFR8_V1(x) (((x) >> BIT_SHIFT_ARFR8_V1) & BIT_MASK_ARFR8_V1) #define BIT_SET_ARFR8_V1(x, v) (BIT_CLEAR_ARFR8_V1(x) | BIT_ARFR8_V1(v)) #define BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER 0 #define BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER 0xff #define BIT_MEDIUM_HAS_IDLE_TRIGGER(x) \ (((x) & BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER) \ << BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER) #define BITS_MEDIUM_HAS_IDLE_TRIGGER \ (BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER << BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER) #define BIT_CLEAR_MEDIUM_HAS_IDLE_TRIGGER(x) \ ((x) & (~BITS_MEDIUM_HAS_IDLE_TRIGGER)) #define BIT_GET_MEDIUM_HAS_IDLE_TRIGGER(x) \ (((x) >> BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER) & \ BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER) #define BIT_SET_MEDIUM_HAS_IDLE_TRIGGER(x, v) \ (BIT_CLEAR_MEDIUM_HAS_IDLE_TRIGGER(x) | BIT_MEDIUM_HAS_IDLE_TRIGGER(v)) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ #define BIT_SHIFT_BCNQ_PKT_INFO_V1 16 #define BIT_MASK_BCNQ_PKT_INFO_V1 0xfff #define BIT_BCNQ_PKT_INFO_V1(x) \ (((x) & BIT_MASK_BCNQ_PKT_INFO_V1) << BIT_SHIFT_BCNQ_PKT_INFO_V1) #define BITS_BCNQ_PKT_INFO_V1 \ (BIT_MASK_BCNQ_PKT_INFO_V1 << BIT_SHIFT_BCNQ_PKT_INFO_V1) #define BIT_CLEAR_BCNQ_PKT_INFO_V1(x) ((x) & (~BITS_BCNQ_PKT_INFO_V1)) #define BIT_GET_BCNQ_PKT_INFO_V1(x) \ (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_V1) & BIT_MASK_BCNQ_PKT_INFO_V1) #define BIT_SET_BCNQ_PKT_INFO_V1(x, v) \ (BIT_CLEAR_BCNQ_PKT_INFO_V1(x) | BIT_BCNQ_PKT_INFO_V1(v)) #define BIT_SHIFT_BCNERR_PORT_SEL 16 #define BIT_MASK_BCNERR_PORT_SEL 0x7 #define BIT_BCNERR_PORT_SEL(x) \ (((x) & BIT_MASK_BCNERR_PORT_SEL) << BIT_SHIFT_BCNERR_PORT_SEL) #define BITS_BCNERR_PORT_SEL \ (BIT_MASK_BCNERR_PORT_SEL << BIT_SHIFT_BCNERR_PORT_SEL) #define BIT_CLEAR_BCNERR_PORT_SEL(x) ((x) & (~BITS_BCNERR_PORT_SEL)) #define BIT_GET_BCNERR_PORT_SEL(x) \ (((x) >> BIT_SHIFT_BCNERR_PORT_SEL) & BIT_MASK_BCNERR_PORT_SEL) #define BIT_SET_BCNERR_PORT_SEL(x, v) \ (BIT_CLEAR_BCNERR_PORT_SEL(x) | BIT_BCNERR_PORT_SEL(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ #define BIT_SHIFT_CMDQ_PKT_INFO 16 #define BIT_MASK_CMDQ_PKT_INFO 0xfff #define BIT_CMDQ_PKT_INFO(x) \ (((x) & BIT_MASK_CMDQ_PKT_INFO) << BIT_SHIFT_CMDQ_PKT_INFO) #define BITS_CMDQ_PKT_INFO (BIT_MASK_CMDQ_PKT_INFO << BIT_SHIFT_CMDQ_PKT_INFO) #define BIT_CLEAR_CMDQ_PKT_INFO(x) ((x) & (~BITS_CMDQ_PKT_INFO)) #define BIT_GET_CMDQ_PKT_INFO(x) \ (((x) >> BIT_SHIFT_CMDQ_PKT_INFO) & BIT_MASK_CMDQ_PKT_INFO) #define BIT_SET_CMDQ_PKT_INFO(x, v) \ (BIT_CLEAR_CMDQ_PKT_INFO(x) | BIT_CMDQ_PKT_INFO(v)) #endif #if (HALMAC_8197F_SUPPORT) /* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ #define BIT_SHIFT_CMDQ_PKT_INFO_V1 0 #define BIT_MASK_CMDQ_PKT_INFO_V1 0xfff #define BIT_CMDQ_PKT_INFO_V1(x) \ (((x) & BIT_MASK_CMDQ_PKT_INFO_V1) << BIT_SHIFT_CMDQ_PKT_INFO_V1) #define BITS_CMDQ_PKT_INFO_V1 \ (BIT_MASK_CMDQ_PKT_INFO_V1 << BIT_SHIFT_CMDQ_PKT_INFO_V1) #define BIT_CLEAR_CMDQ_PKT_INFO_V1(x) ((x) & (~BITS_CMDQ_PKT_INFO_V1)) #define BIT_GET_CMDQ_PKT_INFO_V1(x) \ (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_V1) & BIT_MASK_CMDQ_PKT_INFO_V1) #define BIT_SET_CMDQ_PKT_INFO_V1(x, v) \ (BIT_CLEAR_CMDQ_PKT_INFO_V1(x) | BIT_CMDQ_PKT_INFO_V1(v)) #endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ #define BIT_SHIFT_BCNQ_PKT_INFO 0 #define BIT_MASK_BCNQ_PKT_INFO 0xfff #define BIT_BCNQ_PKT_INFO(x) \ (((x) & BIT_MASK_BCNQ_PKT_INFO) << BIT_SHIFT_BCNQ_PKT_INFO) #define BITS_BCNQ_PKT_INFO (BIT_MASK_BCNQ_PKT_INFO << BIT_SHIFT_BCNQ_PKT_INFO) #define BIT_CLEAR_BCNQ_PKT_INFO(x) ((x) & (~BITS_BCNQ_PKT_INFO)) #define BIT_GET_BCNQ_PKT_INFO(x) \ (((x) >> BIT_SHIFT_BCNQ_PKT_INFO) & BIT_MASK_BCNQ_PKT_INFO) #define BIT_SET_BCNQ_PKT_INFO(x, v) \ (BIT_CLEAR_BCNQ_PKT_INFO(x) | BIT_BCNQ_PKT_INFO(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_USEREG_SETTING (Offset 0x1420) */ #define BIT_NDPA_USEREG BIT(21) #define BIT_SHIFT_RETRY_USEREG 19 #define BIT_MASK_RETRY_USEREG 0x3 #define BIT_RETRY_USEREG(x) \ (((x) & BIT_MASK_RETRY_USEREG) << BIT_SHIFT_RETRY_USEREG) #define BITS_RETRY_USEREG (BIT_MASK_RETRY_USEREG << BIT_SHIFT_RETRY_USEREG) #define BIT_CLEAR_RETRY_USEREG(x) ((x) & (~BITS_RETRY_USEREG)) #define BIT_GET_RETRY_USEREG(x) \ (((x) >> BIT_SHIFT_RETRY_USEREG) & BIT_MASK_RETRY_USEREG) #define BIT_SET_RETRY_USEREG(x, v) \ (BIT_CLEAR_RETRY_USEREG(x) | BIT_RETRY_USEREG(v)) #define BIT_SHIFT_TRYPKT_USEREG 17 #define BIT_MASK_TRYPKT_USEREG 0x3 #define BIT_TRYPKT_USEREG(x) \ (((x) & BIT_MASK_TRYPKT_USEREG) << BIT_SHIFT_TRYPKT_USEREG) #define BITS_TRYPKT_USEREG (BIT_MASK_TRYPKT_USEREG << BIT_SHIFT_TRYPKT_USEREG) #define BIT_CLEAR_TRYPKT_USEREG(x) ((x) & (~BITS_TRYPKT_USEREG)) #define BIT_GET_TRYPKT_USEREG(x) \ (((x) >> BIT_SHIFT_TRYPKT_USEREG) & BIT_MASK_TRYPKT_USEREG) #define BIT_SET_TRYPKT_USEREG(x, v) \ (BIT_CLEAR_TRYPKT_USEREG(x) | BIT_TRYPKT_USEREG(v)) #define BIT_CTLPKT_USEREG BIT(16) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_AESIV_SETTING (Offset 0x1424) */ #define BIT_SHIFT_AESIV_OFFSET 0 #define BIT_MASK_AESIV_OFFSET 0xfff #define BIT_AESIV_OFFSET(x) \ (((x) & BIT_MASK_AESIV_OFFSET) << BIT_SHIFT_AESIV_OFFSET) #define BITS_AESIV_OFFSET (BIT_MASK_AESIV_OFFSET << BIT_SHIFT_AESIV_OFFSET) #define BIT_CLEAR_AESIV_OFFSET(x) ((x) & (~BITS_AESIV_OFFSET)) #define BIT_GET_AESIV_OFFSET(x) \ (((x) >> BIT_SHIFT_AESIV_OFFSET) & BIT_MASK_AESIV_OFFSET) #define BIT_SET_AESIV_OFFSET(x, v) \ (BIT_CLEAR_AESIV_OFFSET(x) | BIT_AESIV_OFFSET(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BF0_TIME_SETTING (Offset 0x1428) */ #define BIT_BF0_TIMER_SET BIT(31) #define BIT_BF0_TIMER_CLR BIT(30) #define BIT_BF0_UPDATE_EN BIT(29) #define BIT_BF0_TIMER_EN BIT(28) #define BIT_SHIFT_BF0_PRETIME_OVER 16 #define BIT_MASK_BF0_PRETIME_OVER 0xfff #define BIT_BF0_PRETIME_OVER(x) \ (((x) & BIT_MASK_BF0_PRETIME_OVER) << BIT_SHIFT_BF0_PRETIME_OVER) #define BITS_BF0_PRETIME_OVER \ (BIT_MASK_BF0_PRETIME_OVER << BIT_SHIFT_BF0_PRETIME_OVER) #define BIT_CLEAR_BF0_PRETIME_OVER(x) ((x) & (~BITS_BF0_PRETIME_OVER)) #define BIT_GET_BF0_PRETIME_OVER(x) \ (((x) >> BIT_SHIFT_BF0_PRETIME_OVER) & BIT_MASK_BF0_PRETIME_OVER) #define BIT_SET_BF0_PRETIME_OVER(x, v) \ (BIT_CLEAR_BF0_PRETIME_OVER(x) | BIT_BF0_PRETIME_OVER(v)) #define BIT_SHIFT_BF0_LIFETIME 0 #define BIT_MASK_BF0_LIFETIME 0xffff #define BIT_BF0_LIFETIME(x) \ (((x) & BIT_MASK_BF0_LIFETIME) << BIT_SHIFT_BF0_LIFETIME) #define BITS_BF0_LIFETIME (BIT_MASK_BF0_LIFETIME << BIT_SHIFT_BF0_LIFETIME) #define BIT_CLEAR_BF0_LIFETIME(x) ((x) & (~BITS_BF0_LIFETIME)) #define BIT_GET_BF0_LIFETIME(x) \ (((x) >> BIT_SHIFT_BF0_LIFETIME) & BIT_MASK_BF0_LIFETIME) #define BIT_SET_BF0_LIFETIME(x, v) \ (BIT_CLEAR_BF0_LIFETIME(x) | BIT_BF0_LIFETIME(v)) /* 2 REG_BF1_TIME_SETTING (Offset 0x142C) */ #define BIT_BF1_TIMER_SET BIT(31) #define BIT_BF1_TIMER_CLR BIT(30) #define BIT_BF1_UPDATE_EN BIT(29) #define BIT_BF1_TIMER_EN BIT(28) #define BIT_SHIFT_BF1_PRETIME_OVER 16 #define BIT_MASK_BF1_PRETIME_OVER 0xfff #define BIT_BF1_PRETIME_OVER(x) \ (((x) & BIT_MASK_BF1_PRETIME_OVER) << BIT_SHIFT_BF1_PRETIME_OVER) #define BITS_BF1_PRETIME_OVER \ (BIT_MASK_BF1_PRETIME_OVER << BIT_SHIFT_BF1_PRETIME_OVER) #define BIT_CLEAR_BF1_PRETIME_OVER(x) ((x) & (~BITS_BF1_PRETIME_OVER)) #define BIT_GET_BF1_PRETIME_OVER(x) \ (((x) >> BIT_SHIFT_BF1_PRETIME_OVER) & BIT_MASK_BF1_PRETIME_OVER) #define BIT_SET_BF1_PRETIME_OVER(x, v) \ (BIT_CLEAR_BF1_PRETIME_OVER(x) | BIT_BF1_PRETIME_OVER(v)) #define BIT_SHIFT_BF1_LIFETIME 0 #define BIT_MASK_BF1_LIFETIME 0xffff #define BIT_BF1_LIFETIME(x) \ (((x) & BIT_MASK_BF1_LIFETIME) << BIT_SHIFT_BF1_LIFETIME) #define BITS_BF1_LIFETIME (BIT_MASK_BF1_LIFETIME << BIT_SHIFT_BF1_LIFETIME) #define BIT_CLEAR_BF1_LIFETIME(x) ((x) & (~BITS_BF1_LIFETIME)) #define BIT_GET_BF1_LIFETIME(x) \ (((x) >> BIT_SHIFT_BF1_LIFETIME) & BIT_MASK_BF1_LIFETIME) #define BIT_SET_BF1_LIFETIME(x, v) \ (BIT_CLEAR_BF1_LIFETIME(x) | BIT_BF1_LIFETIME(v)) /* 2 REG_BF_TIMEOUT_EN (Offset 0x1430) */ #define BIT_EN_VHT_LDPC BIT(9) #define BIT_EN_HT_LDPC BIT(8) #define BIT_BF1_TIMEOUT_EN BIT(1) #define BIT_BF0_TIMEOUT_EN BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MACID_RELEASE0 (Offset 0x1434) */ #define BIT_SHIFT_MACID31_0_RELEASE 0 #define BIT_MASK_MACID31_0_RELEASE 0xffffffffL #define BIT_MACID31_0_RELEASE(x) \ (((x) & BIT_MASK_MACID31_0_RELEASE) << BIT_SHIFT_MACID31_0_RELEASE) #define BITS_MACID31_0_RELEASE \ (BIT_MASK_MACID31_0_RELEASE << BIT_SHIFT_MACID31_0_RELEASE) #define BIT_CLEAR_MACID31_0_RELEASE(x) ((x) & (~BITS_MACID31_0_RELEASE)) #define BIT_GET_MACID31_0_RELEASE(x) \ (((x) >> BIT_SHIFT_MACID31_0_RELEASE) & BIT_MASK_MACID31_0_RELEASE) #define BIT_SET_MACID31_0_RELEASE(x, v) \ (BIT_CLEAR_MACID31_0_RELEASE(x) | BIT_MACID31_0_RELEASE(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MACID_RELEASE_INFO (Offset 0x1434) */ #define BIT_SHIFT_MACID_RELEASE_INFO 0 #define BIT_MASK_MACID_RELEASE_INFO 0xffffffffL #define BIT_MACID_RELEASE_INFO(x) \ (((x) & BIT_MASK_MACID_RELEASE_INFO) << BIT_SHIFT_MACID_RELEASE_INFO) #define BITS_MACID_RELEASE_INFO \ (BIT_MASK_MACID_RELEASE_INFO << BIT_SHIFT_MACID_RELEASE_INFO) #define BIT_CLEAR_MACID_RELEASE_INFO(x) ((x) & (~BITS_MACID_RELEASE_INFO)) #define BIT_GET_MACID_RELEASE_INFO(x) \ (((x) >> BIT_SHIFT_MACID_RELEASE_INFO) & BIT_MASK_MACID_RELEASE_INFO) #define BIT_SET_MACID_RELEASE_INFO(x, v) \ (BIT_CLEAR_MACID_RELEASE_INFO(x) | BIT_MACID_RELEASE_INFO(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MACID_RELEASE1 (Offset 0x1438) */ #define BIT_SHIFT_MACID63_32_RELEASE 0 #define BIT_MASK_MACID63_32_RELEASE 0xffffffffL #define BIT_MACID63_32_RELEASE(x) \ (((x) & BIT_MASK_MACID63_32_RELEASE) << BIT_SHIFT_MACID63_32_RELEASE) #define BITS_MACID63_32_RELEASE \ (BIT_MASK_MACID63_32_RELEASE << BIT_SHIFT_MACID63_32_RELEASE) #define BIT_CLEAR_MACID63_32_RELEASE(x) ((x) & (~BITS_MACID63_32_RELEASE)) #define BIT_GET_MACID63_32_RELEASE(x) \ (((x) >> BIT_SHIFT_MACID63_32_RELEASE) & BIT_MASK_MACID63_32_RELEASE) #define BIT_SET_MACID63_32_RELEASE(x, v) \ (BIT_CLEAR_MACID63_32_RELEASE(x) | BIT_MACID63_32_RELEASE(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MACID_RELEASE_SUCCESS_INFO (Offset 0x1438) */ #define BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO 0 #define BIT_MASK_MACID_RELEASE_SUCCESS_INFO 0xffffffffL #define BIT_MACID_RELEASE_SUCCESS_INFO(x) \ (((x) & BIT_MASK_MACID_RELEASE_SUCCESS_INFO) \ << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO) #define BITS_MACID_RELEASE_SUCCESS_INFO \ (BIT_MASK_MACID_RELEASE_SUCCESS_INFO \ << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO) #define BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO(x) \ ((x) & (~BITS_MACID_RELEASE_SUCCESS_INFO)) #define BIT_GET_MACID_RELEASE_SUCCESS_INFO(x) \ (((x) >> BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO) & \ BIT_MASK_MACID_RELEASE_SUCCESS_INFO) #define BIT_SET_MACID_RELEASE_SUCCESS_INFO(x, v) \ (BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO(x) | \ BIT_MACID_RELEASE_SUCCESS_INFO(v)) /* 2 REG_MACID_RELEASE_CTRL (Offset 0x143C) */ #define BIT_SHIFT_MACID_RELEASE_SEL 24 #define BIT_MASK_MACID_RELEASE_SEL 0x7 #define BIT_MACID_RELEASE_SEL(x) \ (((x) & BIT_MASK_MACID_RELEASE_SEL) << BIT_SHIFT_MACID_RELEASE_SEL) #define BITS_MACID_RELEASE_SEL \ (BIT_MASK_MACID_RELEASE_SEL << BIT_SHIFT_MACID_RELEASE_SEL) #define BIT_CLEAR_MACID_RELEASE_SEL(x) ((x) & (~BITS_MACID_RELEASE_SEL)) #define BIT_GET_MACID_RELEASE_SEL(x) \ (((x) >> BIT_SHIFT_MACID_RELEASE_SEL) & BIT_MASK_MACID_RELEASE_SEL) #define BIT_SET_MACID_RELEASE_SEL(x, v) \ (BIT_CLEAR_MACID_RELEASE_SEL(x) | BIT_MACID_RELEASE_SEL(v)) #define BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET 16 #define BIT_MASK_MACID_RELEASE_CLEAR_OFFSET 0xff #define BIT_MACID_RELEASE_CLEAR_OFFSET(x) \ (((x) & BIT_MASK_MACID_RELEASE_CLEAR_OFFSET) \ << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET) #define BITS_MACID_RELEASE_CLEAR_OFFSET \ (BIT_MASK_MACID_RELEASE_CLEAR_OFFSET \ << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET) #define BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET(x) \ ((x) & (~BITS_MACID_RELEASE_CLEAR_OFFSET)) #define BIT_GET_MACID_RELEASE_CLEAR_OFFSET(x) \ (((x) >> BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET) & \ BIT_MASK_MACID_RELEASE_CLEAR_OFFSET) #define BIT_SET_MACID_RELEASE_CLEAR_OFFSET(x, v) \ (BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET(x) | \ BIT_MACID_RELEASE_CLEAR_OFFSET(v)) #define BIT_MACID_RELEASE_VALUE BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MACID_RELEASE2 (Offset 0x143C) */ #define BIT_SHIFT_MACID95_64_RELEASE 0 #define BIT_MASK_MACID95_64_RELEASE 0xffffffffL #define BIT_MACID95_64_RELEASE(x) \ (((x) & BIT_MASK_MACID95_64_RELEASE) << BIT_SHIFT_MACID95_64_RELEASE) #define BITS_MACID95_64_RELEASE \ (BIT_MASK_MACID95_64_RELEASE << BIT_SHIFT_MACID95_64_RELEASE) #define BIT_CLEAR_MACID95_64_RELEASE(x) ((x) & (~BITS_MACID95_64_RELEASE)) #define BIT_GET_MACID95_64_RELEASE(x) \ (((x) >> BIT_SHIFT_MACID95_64_RELEASE) & BIT_MASK_MACID95_64_RELEASE) #define BIT_SET_MACID95_64_RELEASE(x, v) \ (BIT_CLEAR_MACID95_64_RELEASE(x) | BIT_MACID95_64_RELEASE(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MACID_RELEASE_CTRL (Offset 0x143C) */ #define BIT_SHIFT_MACID_RELEASE_OFFSET 0 #define BIT_MASK_MACID_RELEASE_OFFSET 0xff #define BIT_MACID_RELEASE_OFFSET(x) \ (((x) & BIT_MASK_MACID_RELEASE_OFFSET) \ << BIT_SHIFT_MACID_RELEASE_OFFSET) #define BITS_MACID_RELEASE_OFFSET \ (BIT_MASK_MACID_RELEASE_OFFSET << BIT_SHIFT_MACID_RELEASE_OFFSET) #define BIT_CLEAR_MACID_RELEASE_OFFSET(x) ((x) & (~BITS_MACID_RELEASE_OFFSET)) #define BIT_GET_MACID_RELEASE_OFFSET(x) \ (((x) >> BIT_SHIFT_MACID_RELEASE_OFFSET) & \ BIT_MASK_MACID_RELEASE_OFFSET) #define BIT_SET_MACID_RELEASE_OFFSET(x, v) \ (BIT_CLEAR_MACID_RELEASE_OFFSET(x) | BIT_MACID_RELEASE_OFFSET(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MACID_RELEASE3 (Offset 0x1440) */ #define BIT_SHIFT_MACID127_96_RELEASE 0 #define BIT_MASK_MACID127_96_RELEASE 0xffffffffL #define BIT_MACID127_96_RELEASE(x) \ (((x) & BIT_MASK_MACID127_96_RELEASE) << BIT_SHIFT_MACID127_96_RELEASE) #define BITS_MACID127_96_RELEASE \ (BIT_MASK_MACID127_96_RELEASE << BIT_SHIFT_MACID127_96_RELEASE) #define BIT_CLEAR_MACID127_96_RELEASE(x) ((x) & (~BITS_MACID127_96_RELEASE)) #define BIT_GET_MACID127_96_RELEASE(x) \ (((x) >> BIT_SHIFT_MACID127_96_RELEASE) & BIT_MASK_MACID127_96_RELEASE) #define BIT_SET_MACID127_96_RELEASE(x, v) \ (BIT_CLEAR_MACID127_96_RELEASE(x) | BIT_MACID127_96_RELEASE(v)) /* 2 REG_MACID_RELEASE_SETTING (Offset 0x1444) */ #define BIT_MACID_VALUE BIT(7) #define BIT_SHIFT_MACID_OFFSET 0 #define BIT_MASK_MACID_OFFSET 0x7f #define BIT_MACID_OFFSET(x) \ (((x) & BIT_MASK_MACID_OFFSET) << BIT_SHIFT_MACID_OFFSET) #define BITS_MACID_OFFSET (BIT_MASK_MACID_OFFSET << BIT_SHIFT_MACID_OFFSET) #define BIT_CLEAR_MACID_OFFSET(x) ((x) & (~BITS_MACID_OFFSET)) #define BIT_GET_MACID_OFFSET(x) \ (((x) >> BIT_SHIFT_MACID_OFFSET) & BIT_MASK_MACID_OFFSET) #define BIT_SET_MACID_OFFSET(x, v) \ (BIT_CLEAR_MACID_OFFSET(x) | BIT_MACID_OFFSET(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FAST_EDCA_VOVI_SETTING (Offset 0x1448) */ #define BIT_SHIFT_VI_FAST_EDCA_TO 24 #define BIT_MASK_VI_FAST_EDCA_TO 0xff #define BIT_VI_FAST_EDCA_TO(x) \ (((x) & BIT_MASK_VI_FAST_EDCA_TO) << BIT_SHIFT_VI_FAST_EDCA_TO) #define BITS_VI_FAST_EDCA_TO \ (BIT_MASK_VI_FAST_EDCA_TO << BIT_SHIFT_VI_FAST_EDCA_TO) #define BIT_CLEAR_VI_FAST_EDCA_TO(x) ((x) & (~BITS_VI_FAST_EDCA_TO)) #define BIT_GET_VI_FAST_EDCA_TO(x) \ (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO) & BIT_MASK_VI_FAST_EDCA_TO) #define BIT_SET_VI_FAST_EDCA_TO(x, v) \ (BIT_CLEAR_VI_FAST_EDCA_TO(x) | BIT_VI_FAST_EDCA_TO(v)) #define BIT_VI_THRESHOLD_SEL BIT(23) #define BIT_SHIFT_VI_FAST_EDCA_PKT_TH 16 #define BIT_MASK_VI_FAST_EDCA_PKT_TH 0x7f #define BIT_VI_FAST_EDCA_PKT_TH(x) \ (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH) #define BITS_VI_FAST_EDCA_PKT_TH \ (BIT_MASK_VI_FAST_EDCA_PKT_TH << BIT_SHIFT_VI_FAST_EDCA_PKT_TH) #define BIT_CLEAR_VI_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_VI_FAST_EDCA_PKT_TH)) #define BIT_GET_VI_FAST_EDCA_PKT_TH(x) \ (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH) & BIT_MASK_VI_FAST_EDCA_PKT_TH) #define BIT_SET_VI_FAST_EDCA_PKT_TH(x, v) \ (BIT_CLEAR_VI_FAST_EDCA_PKT_TH(x) | BIT_VI_FAST_EDCA_PKT_TH(v)) #define BIT_SHIFT_VO_FAST_EDCA_TO 8 #define BIT_MASK_VO_FAST_EDCA_TO 0xff #define BIT_VO_FAST_EDCA_TO(x) \ (((x) & BIT_MASK_VO_FAST_EDCA_TO) << BIT_SHIFT_VO_FAST_EDCA_TO) #define BITS_VO_FAST_EDCA_TO \ (BIT_MASK_VO_FAST_EDCA_TO << BIT_SHIFT_VO_FAST_EDCA_TO) #define BIT_CLEAR_VO_FAST_EDCA_TO(x) ((x) & (~BITS_VO_FAST_EDCA_TO)) #define BIT_GET_VO_FAST_EDCA_TO(x) \ (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO) & BIT_MASK_VO_FAST_EDCA_TO) #define BIT_SET_VO_FAST_EDCA_TO(x, v) \ (BIT_CLEAR_VO_FAST_EDCA_TO(x) | BIT_VO_FAST_EDCA_TO(v)) #define BIT_VO_THRESHOLD_SEL BIT(7) #define BIT_SHIFT_VO_FAST_EDCA_PKT_TH 0 #define BIT_MASK_VO_FAST_EDCA_PKT_TH 0x7f #define BIT_VO_FAST_EDCA_PKT_TH(x) \ (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH) #define BITS_VO_FAST_EDCA_PKT_TH \ (BIT_MASK_VO_FAST_EDCA_PKT_TH << BIT_SHIFT_VO_FAST_EDCA_PKT_TH) #define BIT_CLEAR_VO_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_VO_FAST_EDCA_PKT_TH)) #define BIT_GET_VO_FAST_EDCA_PKT_TH(x) \ (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH) & BIT_MASK_VO_FAST_EDCA_PKT_TH) #define BIT_SET_VO_FAST_EDCA_PKT_TH(x, v) \ (BIT_CLEAR_VO_FAST_EDCA_PKT_TH(x) | BIT_VO_FAST_EDCA_PKT_TH(v)) /* 2 REG_FAST_EDCA_BEBK_SETTING (Offset 0x144C) */ #define BIT_SHIFT_BK_FAST_EDCA_TO 24 #define BIT_MASK_BK_FAST_EDCA_TO 0xff #define BIT_BK_FAST_EDCA_TO(x) \ (((x) & BIT_MASK_BK_FAST_EDCA_TO) << BIT_SHIFT_BK_FAST_EDCA_TO) #define BITS_BK_FAST_EDCA_TO \ (BIT_MASK_BK_FAST_EDCA_TO << BIT_SHIFT_BK_FAST_EDCA_TO) #define BIT_CLEAR_BK_FAST_EDCA_TO(x) ((x) & (~BITS_BK_FAST_EDCA_TO)) #define BIT_GET_BK_FAST_EDCA_TO(x) \ (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO) & BIT_MASK_BK_FAST_EDCA_TO) #define BIT_SET_BK_FAST_EDCA_TO(x, v) \ (BIT_CLEAR_BK_FAST_EDCA_TO(x) | BIT_BK_FAST_EDCA_TO(v)) #define BIT_BK_THRESHOLD_SEL BIT(23) #define BIT_SHIFT_BK_FAST_EDCA_PKT_TH 16 #define BIT_MASK_BK_FAST_EDCA_PKT_TH 0x7f #define BIT_BK_FAST_EDCA_PKT_TH(x) \ (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH) #define BITS_BK_FAST_EDCA_PKT_TH \ (BIT_MASK_BK_FAST_EDCA_PKT_TH << BIT_SHIFT_BK_FAST_EDCA_PKT_TH) #define BIT_CLEAR_BK_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_BK_FAST_EDCA_PKT_TH)) #define BIT_GET_BK_FAST_EDCA_PKT_TH(x) \ (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH) & BIT_MASK_BK_FAST_EDCA_PKT_TH) #define BIT_SET_BK_FAST_EDCA_PKT_TH(x, v) \ (BIT_CLEAR_BK_FAST_EDCA_PKT_TH(x) | BIT_BK_FAST_EDCA_PKT_TH(v)) #define BIT_SHIFT_BE_FAST_EDCA_TO 8 #define BIT_MASK_BE_FAST_EDCA_TO 0xff #define BIT_BE_FAST_EDCA_TO(x) \ (((x) & BIT_MASK_BE_FAST_EDCA_TO) << BIT_SHIFT_BE_FAST_EDCA_TO) #define BITS_BE_FAST_EDCA_TO \ (BIT_MASK_BE_FAST_EDCA_TO << BIT_SHIFT_BE_FAST_EDCA_TO) #define BIT_CLEAR_BE_FAST_EDCA_TO(x) ((x) & (~BITS_BE_FAST_EDCA_TO)) #define BIT_GET_BE_FAST_EDCA_TO(x) \ (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO) & BIT_MASK_BE_FAST_EDCA_TO) #define BIT_SET_BE_FAST_EDCA_TO(x, v) \ (BIT_CLEAR_BE_FAST_EDCA_TO(x) | BIT_BE_FAST_EDCA_TO(v)) #define BIT_BE_THRESHOLD_SEL BIT(7) #define BIT_EN_P2P_CTWINDOW BIT(1) #define BIT_SHIFT_BE_FAST_EDCA_PKT_TH 0 #define BIT_MASK_BE_FAST_EDCA_PKT_TH 0x7f #define BIT_BE_FAST_EDCA_PKT_TH(x) \ (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH) #define BITS_BE_FAST_EDCA_PKT_TH \ (BIT_MASK_BE_FAST_EDCA_PKT_TH << BIT_SHIFT_BE_FAST_EDCA_PKT_TH) #define BIT_CLEAR_BE_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_BE_FAST_EDCA_PKT_TH)) #define BIT_GET_BE_FAST_EDCA_PKT_TH(x) \ (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH) & BIT_MASK_BE_FAST_EDCA_PKT_TH) #define BIT_SET_BE_FAST_EDCA_PKT_TH(x, v) \ (BIT_CLEAR_BE_FAST_EDCA_PKT_TH(x) | BIT_BE_FAST_EDCA_PKT_TH(v)) #define BIT_EN_P2P_BCNQ_AREA BIT(0) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MACID_DROP0 (Offset 0x1450) */ #define BIT_SHIFT_MACID31_0_DROP 0 #define BIT_MASK_MACID31_0_DROP 0xffffffffL #define BIT_MACID31_0_DROP(x) \ (((x) & BIT_MASK_MACID31_0_DROP) << BIT_SHIFT_MACID31_0_DROP) #define BITS_MACID31_0_DROP \ (BIT_MASK_MACID31_0_DROP << BIT_SHIFT_MACID31_0_DROP) #define BIT_CLEAR_MACID31_0_DROP(x) ((x) & (~BITS_MACID31_0_DROP)) #define BIT_GET_MACID31_0_DROP(x) \ (((x) >> BIT_SHIFT_MACID31_0_DROP) & BIT_MASK_MACID31_0_DROP) #define BIT_SET_MACID31_0_DROP(x, v) \ (BIT_CLEAR_MACID31_0_DROP(x) | BIT_MACID31_0_DROP(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MACID_DROP_INFO (Offset 0x1450) */ #define BIT_SHIFT_MACID_DROP_INFO 0 #define BIT_MASK_MACID_DROP_INFO 0xffffffffL #define BIT_MACID_DROP_INFO(x) \ (((x) & BIT_MASK_MACID_DROP_INFO) << BIT_SHIFT_MACID_DROP_INFO) #define BITS_MACID_DROP_INFO \ (BIT_MASK_MACID_DROP_INFO << BIT_SHIFT_MACID_DROP_INFO) #define BIT_CLEAR_MACID_DROP_INFO(x) ((x) & (~BITS_MACID_DROP_INFO)) #define BIT_GET_MACID_DROP_INFO(x) \ (((x) >> BIT_SHIFT_MACID_DROP_INFO) & BIT_MASK_MACID_DROP_INFO) #define BIT_SET_MACID_DROP_INFO(x, v) \ (BIT_CLEAR_MACID_DROP_INFO(x) | BIT_MACID_DROP_INFO(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MACID_DROP1 (Offset 0x1454) */ #define BIT_SHIFT_MACID63_32_DROP 0 #define BIT_MASK_MACID63_32_DROP 0xffffffffL #define BIT_MACID63_32_DROP(x) \ (((x) & BIT_MASK_MACID63_32_DROP) << BIT_SHIFT_MACID63_32_DROP) #define BITS_MACID63_32_DROP \ (BIT_MASK_MACID63_32_DROP << BIT_SHIFT_MACID63_32_DROP) #define BIT_CLEAR_MACID63_32_DROP(x) ((x) & (~BITS_MACID63_32_DROP)) #define BIT_GET_MACID63_32_DROP(x) \ (((x) >> BIT_SHIFT_MACID63_32_DROP) & BIT_MASK_MACID63_32_DROP) #define BIT_SET_MACID63_32_DROP(x, v) \ (BIT_CLEAR_MACID63_32_DROP(x) | BIT_MACID63_32_DROP(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MACID_DROP_CTRL (Offset 0x1454) */ #define BIT_SHIFT_MACID_DROP_SEL 0 #define BIT_MASK_MACID_DROP_SEL 0x7 #define BIT_MACID_DROP_SEL(x) \ (((x) & BIT_MASK_MACID_DROP_SEL) << BIT_SHIFT_MACID_DROP_SEL) #define BITS_MACID_DROP_SEL \ (BIT_MASK_MACID_DROP_SEL << BIT_SHIFT_MACID_DROP_SEL) #define BIT_CLEAR_MACID_DROP_SEL(x) ((x) & (~BITS_MACID_DROP_SEL)) #define BIT_GET_MACID_DROP_SEL(x) \ (((x) >> BIT_SHIFT_MACID_DROP_SEL) & BIT_MASK_MACID_DROP_SEL) #define BIT_SET_MACID_DROP_SEL(x, v) \ (BIT_CLEAR_MACID_DROP_SEL(x) | BIT_MACID_DROP_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MACID_DROP2 (Offset 0x1458) */ #define BIT_SHIFT_MACID95_64_DROP 0 #define BIT_MASK_MACID95_64_DROP 0xffffffffL #define BIT_MACID95_64_DROP(x) \ (((x) & BIT_MASK_MACID95_64_DROP) << BIT_SHIFT_MACID95_64_DROP) #define BITS_MACID95_64_DROP \ (BIT_MASK_MACID95_64_DROP << BIT_SHIFT_MACID95_64_DROP) #define BIT_CLEAR_MACID95_64_DROP(x) ((x) & (~BITS_MACID95_64_DROP)) #define BIT_GET_MACID95_64_DROP(x) \ (((x) >> BIT_SHIFT_MACID95_64_DROP) & BIT_MASK_MACID95_64_DROP) #define BIT_SET_MACID95_64_DROP(x, v) \ (BIT_CLEAR_MACID95_64_DROP(x) | BIT_MACID95_64_DROP(v)) /* 2 REG_MACID_DROP3 (Offset 0x145C) */ #define BIT_SHIFT_MACID127_96_DROP 0 #define BIT_MASK_MACID127_96_DROP 0xffffffffL #define BIT_MACID127_96_DROP(x) \ (((x) & BIT_MASK_MACID127_96_DROP) << BIT_SHIFT_MACID127_96_DROP) #define BITS_MACID127_96_DROP \ (BIT_MASK_MACID127_96_DROP << BIT_SHIFT_MACID127_96_DROP) #define BIT_CLEAR_MACID127_96_DROP(x) ((x) & (~BITS_MACID127_96_DROP)) #define BIT_GET_MACID127_96_DROP(x) \ (((x) >> BIT_SHIFT_MACID127_96_DROP) & BIT_MASK_MACID127_96_DROP) #define BIT_SET_MACID127_96_DROP(x, v) \ (BIT_CLEAR_MACID127_96_DROP(x) | BIT_MACID127_96_DROP(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_R_MACID_RELEASE_SUCCESS_0 (Offset 0x1460) */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_0 0xffffffffL #define BIT_R_MACID_RELEASE_SUCCESS_0(x) \ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0) \ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) #define BITS_R_MACID_RELEASE_SUCCESS_0 \ (BIT_MASK_R_MACID_RELEASE_SUCCESS_0 \ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) #define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0(x) \ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0)) #define BIT_GET_R_MACID_RELEASE_SUCCESS_0(x) \ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) & \ BIT_MASK_R_MACID_RELEASE_SUCCESS_0) #define BIT_SET_R_MACID_RELEASE_SUCCESS_0(x, v) \ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0(x) | \ BIT_R_MACID_RELEASE_SUCCESS_0(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_1 (Offset 0x1464) */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_1 0xffffffffL #define BIT_R_MACID_RELEASE_SUCCESS_1(x) \ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1) \ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) #define BITS_R_MACID_RELEASE_SUCCESS_1 \ (BIT_MASK_R_MACID_RELEASE_SUCCESS_1 \ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) #define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1(x) \ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1)) #define BIT_GET_R_MACID_RELEASE_SUCCESS_1(x) \ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) & \ BIT_MASK_R_MACID_RELEASE_SUCCESS_1) #define BIT_SET_R_MACID_RELEASE_SUCCESS_1(x, v) \ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1(x) | \ BIT_R_MACID_RELEASE_SUCCESS_1(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_2 (Offset 0x1468) */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_2 0xffffffffL #define BIT_R_MACID_RELEASE_SUCCESS_2(x) \ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2) \ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) #define BITS_R_MACID_RELEASE_SUCCESS_2 \ (BIT_MASK_R_MACID_RELEASE_SUCCESS_2 \ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) #define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2(x) \ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2)) #define BIT_GET_R_MACID_RELEASE_SUCCESS_2(x) \ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) & \ BIT_MASK_R_MACID_RELEASE_SUCCESS_2) #define BIT_SET_R_MACID_RELEASE_SUCCESS_2(x, v) \ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2(x) | \ BIT_R_MACID_RELEASE_SUCCESS_2(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_3 (Offset 0x146C) */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_3 0xffffffffL #define BIT_R_MACID_RELEASE_SUCCESS_3(x) \ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3) \ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) #define BITS_R_MACID_RELEASE_SUCCESS_3 \ (BIT_MASK_R_MACID_RELEASE_SUCCESS_3 \ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) #define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3(x) \ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3)) #define BIT_GET_R_MACID_RELEASE_SUCCESS_3(x) \ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) & \ BIT_MASK_R_MACID_RELEASE_SUCCESS_3) #define BIT_SET_R_MACID_RELEASE_SUCCESS_3(x, v) \ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3(x) | \ BIT_R_MACID_RELEASE_SUCCESS_3(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */ #define BIT_R_MGG_FIFO_EN BIT(31) #define BIT_SHIFT_R_MGG_FIFO_PG_SIZE 28 #define BIT_MASK_R_MGG_FIFO_PG_SIZE 0x7 #define BIT_R_MGG_FIFO_PG_SIZE(x) \ (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE) #define BITS_R_MGG_FIFO_PG_SIZE \ (BIT_MASK_R_MGG_FIFO_PG_SIZE << BIT_SHIFT_R_MGG_FIFO_PG_SIZE) #define BIT_CLEAR_R_MGG_FIFO_PG_SIZE(x) ((x) & (~BITS_R_MGG_FIFO_PG_SIZE)) #define BIT_GET_R_MGG_FIFO_PG_SIZE(x) \ (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE) & BIT_MASK_R_MGG_FIFO_PG_SIZE) #define BIT_SET_R_MGG_FIFO_PG_SIZE(x, v) \ (BIT_CLEAR_R_MGG_FIFO_PG_SIZE(x) | BIT_R_MGG_FIFO_PG_SIZE(v)) #define BIT_SHIFT_R_MGG_FIFO_START_PG 16 #define BIT_MASK_R_MGG_FIFO_START_PG 0xfff #define BIT_R_MGG_FIFO_START_PG(x) \ (((x) & BIT_MASK_R_MGG_FIFO_START_PG) << BIT_SHIFT_R_MGG_FIFO_START_PG) #define BITS_R_MGG_FIFO_START_PG \ (BIT_MASK_R_MGG_FIFO_START_PG << BIT_SHIFT_R_MGG_FIFO_START_PG) #define BIT_CLEAR_R_MGG_FIFO_START_PG(x) ((x) & (~BITS_R_MGG_FIFO_START_PG)) #define BIT_GET_R_MGG_FIFO_START_PG(x) \ (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG) & BIT_MASK_R_MGG_FIFO_START_PG) #define BIT_SET_R_MGG_FIFO_START_PG(x, v) \ (BIT_CLEAR_R_MGG_FIFO_START_PG(x) | BIT_R_MGG_FIFO_START_PG(v)) #define BIT_SHIFT_R_MGG_FIFO_SIZE 14 #define BIT_MASK_R_MGG_FIFO_SIZE 0x3 #define BIT_R_MGG_FIFO_SIZE(x) \ (((x) & BIT_MASK_R_MGG_FIFO_SIZE) << BIT_SHIFT_R_MGG_FIFO_SIZE) #define BITS_R_MGG_FIFO_SIZE \ (BIT_MASK_R_MGG_FIFO_SIZE << BIT_SHIFT_R_MGG_FIFO_SIZE) #define BIT_CLEAR_R_MGG_FIFO_SIZE(x) ((x) & (~BITS_R_MGG_FIFO_SIZE)) #define BIT_GET_R_MGG_FIFO_SIZE(x) \ (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE) & BIT_MASK_R_MGG_FIFO_SIZE) #define BIT_SET_R_MGG_FIFO_SIZE(x, v) \ (BIT_CLEAR_R_MGG_FIFO_SIZE(x) | BIT_R_MGG_FIFO_SIZE(v)) #define BIT_R_MGG_FIFO_PAUSE BIT(13) #define BIT_SHIFT_R_MGG_FIFO_RPTR 8 #define BIT_MASK_R_MGG_FIFO_RPTR 0x1f #define BIT_R_MGG_FIFO_RPTR(x) \ (((x) & BIT_MASK_R_MGG_FIFO_RPTR) << BIT_SHIFT_R_MGG_FIFO_RPTR) #define BITS_R_MGG_FIFO_RPTR \ (BIT_MASK_R_MGG_FIFO_RPTR << BIT_SHIFT_R_MGG_FIFO_RPTR) #define BIT_CLEAR_R_MGG_FIFO_RPTR(x) ((x) & (~BITS_R_MGG_FIFO_RPTR)) #define BIT_GET_R_MGG_FIFO_RPTR(x) \ (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR) & BIT_MASK_R_MGG_FIFO_RPTR) #define BIT_SET_R_MGG_FIFO_RPTR(x, v) \ (BIT_CLEAR_R_MGG_FIFO_RPTR(x) | BIT_R_MGG_FIFO_RPTR(v)) #define BIT_R_MGG_FIFO_OV BIT(7) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MGQ_FIFO_WRITE_POINTER (Offset 0x1470) */ #define BIT_MGQ_FIFO_OV BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */ #define BIT_R_MGG_FIFO_WPTR_ERROR BIT(6) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MGQ_FIFO_WRITE_POINTER (Offset 0x1470) */ #define BIT_MGQ_FIFO_WPTR_ERROR BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */ #define BIT_R_EN_CPU_LIFETIME BIT(5) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MGQ_FIFO_WRITE_POINTER (Offset 0x1470) */ #define BIT_EN_MGQ_FIFO_LIFETIME BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */ #define BIT_SHIFT_R_MGG_FIFO_WPTR 0 #define BIT_MASK_R_MGG_FIFO_WPTR 0x1f #define BIT_R_MGG_FIFO_WPTR(x) \ (((x) & BIT_MASK_R_MGG_FIFO_WPTR) << BIT_SHIFT_R_MGG_FIFO_WPTR) #define BITS_R_MGG_FIFO_WPTR \ (BIT_MASK_R_MGG_FIFO_WPTR << BIT_SHIFT_R_MGG_FIFO_WPTR) #define BIT_CLEAR_R_MGG_FIFO_WPTR(x) ((x) & (~BITS_R_MGG_FIFO_WPTR)) #define BIT_GET_R_MGG_FIFO_WPTR(x) \ (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR) & BIT_MASK_R_MGG_FIFO_WPTR) #define BIT_SET_R_MGG_FIFO_WPTR(x, v) \ (BIT_CLEAR_R_MGG_FIFO_WPTR(x) | BIT_R_MGG_FIFO_WPTR(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MGQ_FIFO_WRITE_POINTER (Offset 0x1470) */ #define BIT_SHIFT_MGQ_FIFO_WPTR 0 #define BIT_MASK_MGQ_FIFO_WPTR 0x1f #define BIT_MGQ_FIFO_WPTR(x) \ (((x) & BIT_MASK_MGQ_FIFO_WPTR) << BIT_SHIFT_MGQ_FIFO_WPTR) #define BITS_MGQ_FIFO_WPTR (BIT_MASK_MGQ_FIFO_WPTR << BIT_SHIFT_MGQ_FIFO_WPTR) #define BIT_CLEAR_MGQ_FIFO_WPTR(x) ((x) & (~BITS_MGQ_FIFO_WPTR)) #define BIT_GET_MGQ_FIFO_WPTR(x) \ (((x) >> BIT_SHIFT_MGQ_FIFO_WPTR) & BIT_MASK_MGQ_FIFO_WPTR) #define BIT_SET_MGQ_FIFO_WPTR(x, v) \ (BIT_CLEAR_MGQ_FIFO_WPTR(x) | BIT_MGQ_FIFO_WPTR(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MGQ_FIFO_ENABLE (Offset 0x1472) */ #define BIT_MGQ_FIFO_EN_V1 BIT(15) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MGQ_FIFO_ENABLE (Offset 0x1472) */ #define BIT_MGQ_FIFO_EN BIT(15) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MGQ_FIFO_READ_POINTER (Offset 0x1472) */ #define BIT_SHIFT_MGQ_FIFO_SIZE 14 #define BIT_MASK_MGQ_FIFO_SIZE 0x3 #define BIT_MGQ_FIFO_SIZE(x) \ (((x) & BIT_MASK_MGQ_FIFO_SIZE) << BIT_SHIFT_MGQ_FIFO_SIZE) #define BITS_MGQ_FIFO_SIZE (BIT_MASK_MGQ_FIFO_SIZE << BIT_SHIFT_MGQ_FIFO_SIZE) #define BIT_CLEAR_MGQ_FIFO_SIZE(x) ((x) & (~BITS_MGQ_FIFO_SIZE)) #define BIT_GET_MGQ_FIFO_SIZE(x) \ (((x) >> BIT_SHIFT_MGQ_FIFO_SIZE) & BIT_MASK_MGQ_FIFO_SIZE) #define BIT_SET_MGQ_FIFO_SIZE(x, v) \ (BIT_CLEAR_MGQ_FIFO_SIZE(x) | BIT_MGQ_FIFO_SIZE(v)) #define BIT_MGQ_FIFO_PAUSE BIT(13) #define BIT_SHIFT_MGQ_FIFO_PG_SIZE 12 #define BIT_MASK_MGQ_FIFO_PG_SIZE 0x7 #define BIT_MGQ_FIFO_PG_SIZE(x) \ (((x) & BIT_MASK_MGQ_FIFO_PG_SIZE) << BIT_SHIFT_MGQ_FIFO_PG_SIZE) #define BITS_MGQ_FIFO_PG_SIZE \ (BIT_MASK_MGQ_FIFO_PG_SIZE << BIT_SHIFT_MGQ_FIFO_PG_SIZE) #define BIT_CLEAR_MGQ_FIFO_PG_SIZE(x) ((x) & (~BITS_MGQ_FIFO_PG_SIZE)) #define BIT_GET_MGQ_FIFO_PG_SIZE(x) \ (((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE) & BIT_MASK_MGQ_FIFO_PG_SIZE) #define BIT_SET_MGQ_FIFO_PG_SIZE(x, v) \ (BIT_CLEAR_MGQ_FIFO_PG_SIZE(x) | BIT_MGQ_FIFO_PG_SIZE(v)) #define BIT_SHIFT_MGQ_FIFO_RPTR 8 #define BIT_MASK_MGQ_FIFO_RPTR 0x1f #define BIT_MGQ_FIFO_RPTR(x) \ (((x) & BIT_MASK_MGQ_FIFO_RPTR) << BIT_SHIFT_MGQ_FIFO_RPTR) #define BITS_MGQ_FIFO_RPTR (BIT_MASK_MGQ_FIFO_RPTR << BIT_SHIFT_MGQ_FIFO_RPTR) #define BIT_CLEAR_MGQ_FIFO_RPTR(x) ((x) & (~BITS_MGQ_FIFO_RPTR)) #define BIT_GET_MGQ_FIFO_RPTR(x) \ (((x) >> BIT_SHIFT_MGQ_FIFO_RPTR) & BIT_MASK_MGQ_FIFO_RPTR) #define BIT_SET_MGQ_FIFO_RPTR(x, v) \ (BIT_CLEAR_MGQ_FIFO_RPTR(x) | BIT_MGQ_FIFO_RPTR(v)) #define BIT_SHIFT_MGQ_FIFO_START_PG 0 #define BIT_MASK_MGQ_FIFO_START_PG 0xfff #define BIT_MGQ_FIFO_START_PG(x) \ (((x) & BIT_MASK_MGQ_FIFO_START_PG) << BIT_SHIFT_MGQ_FIFO_START_PG) #define BITS_MGQ_FIFO_START_PG \ (BIT_MASK_MGQ_FIFO_START_PG << BIT_SHIFT_MGQ_FIFO_START_PG) #define BIT_CLEAR_MGQ_FIFO_START_PG(x) ((x) & (~BITS_MGQ_FIFO_START_PG)) #define BIT_GET_MGQ_FIFO_START_PG(x) \ (((x) >> BIT_SHIFT_MGQ_FIFO_START_PG) & BIT_MASK_MGQ_FIFO_START_PG) #define BIT_SET_MGQ_FIFO_START_PG(x, v) \ (BIT_CLEAR_MGQ_FIFO_START_PG(x) | BIT_MGQ_FIFO_START_PG(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MGG_FIFO_INT (Offset 0x1474) */ #define BIT_SHIFT_R_MGG_FIFO_INT_FLAG 16 #define BIT_MASK_R_MGG_FIFO_INT_FLAG 0xffff #define BIT_R_MGG_FIFO_INT_FLAG(x) \ (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG) #define BITS_R_MGG_FIFO_INT_FLAG \ (BIT_MASK_R_MGG_FIFO_INT_FLAG << BIT_SHIFT_R_MGG_FIFO_INT_FLAG) #define BIT_CLEAR_R_MGG_FIFO_INT_FLAG(x) ((x) & (~BITS_R_MGG_FIFO_INT_FLAG)) #define BIT_GET_R_MGG_FIFO_INT_FLAG(x) \ (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG) & BIT_MASK_R_MGG_FIFO_INT_FLAG) #define BIT_SET_R_MGG_FIFO_INT_FLAG(x, v) \ (BIT_CLEAR_R_MGG_FIFO_INT_FLAG(x) | BIT_R_MGG_FIFO_INT_FLAG(v)) #define BIT_SHIFT_R_MGG_FIFO_INT_MASK 0 #define BIT_MASK_R_MGG_FIFO_INT_MASK 0xffff #define BIT_R_MGG_FIFO_INT_MASK(x) \ (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK) << BIT_SHIFT_R_MGG_FIFO_INT_MASK) #define BITS_R_MGG_FIFO_INT_MASK \ (BIT_MASK_R_MGG_FIFO_INT_MASK << BIT_SHIFT_R_MGG_FIFO_INT_MASK) #define BIT_CLEAR_R_MGG_FIFO_INT_MASK(x) ((x) & (~BITS_R_MGG_FIFO_INT_MASK)) #define BIT_GET_R_MGG_FIFO_INT_MASK(x) \ (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK) & BIT_MASK_R_MGG_FIFO_INT_MASK) #define BIT_SET_R_MGG_FIFO_INT_MASK(x, v) \ (BIT_CLEAR_R_MGG_FIFO_INT_MASK(x) | BIT_R_MGG_FIFO_INT_MASK(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MGQ_FIFO_RELEASE_INT_MASK (Offset 0x1474) */ #define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK 0 #define BIT_MASK_MGQ_FIFO_REL_INT_MASK 0xffff #define BIT_MGQ_FIFO_REL_INT_MASK(x) \ (((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK) \ << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK) #define BITS_MGQ_FIFO_REL_INT_MASK \ (BIT_MASK_MGQ_FIFO_REL_INT_MASK << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK) #define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK(x) ((x) & (~BITS_MGQ_FIFO_REL_INT_MASK)) #define BIT_GET_MGQ_FIFO_REL_INT_MASK(x) \ (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK) & \ BIT_MASK_MGQ_FIFO_REL_INT_MASK) #define BIT_SET_MGQ_FIFO_REL_INT_MASK(x, v) \ (BIT_CLEAR_MGQ_FIFO_REL_INT_MASK(x) | BIT_MGQ_FIFO_REL_INT_MASK(v)) /* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG (Offset 0x1476) */ #define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG 0 #define BIT_MASK_MGQ_FIFO_REL_INT_FLAG 0xffff #define BIT_MGQ_FIFO_REL_INT_FLAG(x) \ (((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG) \ << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG) #define BITS_MGQ_FIFO_REL_INT_FLAG \ (BIT_MASK_MGQ_FIFO_REL_INT_FLAG << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG) #define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG(x) ((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG)) #define BIT_GET_MGQ_FIFO_REL_INT_FLAG(x) \ (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG) & \ BIT_MASK_MGQ_FIFO_REL_INT_FLAG) #define BIT_SET_MGQ_FIFO_REL_INT_FLAG(x, v) \ (BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG(x) | BIT_MGQ_FIFO_REL_INT_FLAG(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MGG_FIFO_LIFETIME (Offset 0x1478) */ #define BIT_SHIFT_R_MGG_FIFO_LIFETIME 16 #define BIT_MASK_R_MGG_FIFO_LIFETIME 0xffff #define BIT_R_MGG_FIFO_LIFETIME(x) \ (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME) << BIT_SHIFT_R_MGG_FIFO_LIFETIME) #define BITS_R_MGG_FIFO_LIFETIME \ (BIT_MASK_R_MGG_FIFO_LIFETIME << BIT_SHIFT_R_MGG_FIFO_LIFETIME) #define BIT_CLEAR_R_MGG_FIFO_LIFETIME(x) ((x) & (~BITS_R_MGG_FIFO_LIFETIME)) #define BIT_GET_R_MGG_FIFO_LIFETIME(x) \ (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME) & BIT_MASK_R_MGG_FIFO_LIFETIME) #define BIT_SET_R_MGG_FIFO_LIFETIME(x, v) \ (BIT_CLEAR_R_MGG_FIFO_LIFETIME(x) | BIT_R_MGG_FIFO_LIFETIME(v)) #define BIT_SHIFT_R_MGG_FIFO_VALID_MAP 0 #define BIT_MASK_R_MGG_FIFO_VALID_MAP 0xffff #define BIT_R_MGG_FIFO_VALID_MAP(x) \ (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP) \ << BIT_SHIFT_R_MGG_FIFO_VALID_MAP) #define BITS_R_MGG_FIFO_VALID_MAP \ (BIT_MASK_R_MGG_FIFO_VALID_MAP << BIT_SHIFT_R_MGG_FIFO_VALID_MAP) #define BIT_CLEAR_R_MGG_FIFO_VALID_MAP(x) ((x) & (~BITS_R_MGG_FIFO_VALID_MAP)) #define BIT_GET_R_MGG_FIFO_VALID_MAP(x) \ (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP) & \ BIT_MASK_R_MGG_FIFO_VALID_MAP) #define BIT_SET_R_MGG_FIFO_VALID_MAP(x, v) \ (BIT_CLEAR_R_MGG_FIFO_VALID_MAP(x) | BIT_R_MGG_FIFO_VALID_MAP(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MGQ_FIFO_VALID_MAP (Offset 0x1478) */ #define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP 0 #define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP 0xffff #define BIT_MGQ_FIFO_PKT_VALID_MAP(x) \ (((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP) \ << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP) #define BITS_MGQ_FIFO_PKT_VALID_MAP \ (BIT_MASK_MGQ_FIFO_PKT_VALID_MAP << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP) #define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP(x) \ ((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP)) #define BIT_GET_MGQ_FIFO_PKT_VALID_MAP(x) \ (((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP) & \ BIT_MASK_MGQ_FIFO_PKT_VALID_MAP) #define BIT_SET_MGQ_FIFO_PKT_VALID_MAP(x, v) \ (BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP(x) | BIT_MGQ_FIFO_PKT_VALID_MAP(v)) /* 2 REG_MGQ_FIFO_LIFETIME (Offset 0x147A) */ #define BIT_SHIFT_MGQ_FIFO_LIFETIME 0 #define BIT_MASK_MGQ_FIFO_LIFETIME 0xffff #define BIT_MGQ_FIFO_LIFETIME(x) \ (((x) & BIT_MASK_MGQ_FIFO_LIFETIME) << BIT_SHIFT_MGQ_FIFO_LIFETIME) #define BITS_MGQ_FIFO_LIFETIME \ (BIT_MASK_MGQ_FIFO_LIFETIME << BIT_SHIFT_MGQ_FIFO_LIFETIME) #define BIT_CLEAR_MGQ_FIFO_LIFETIME(x) ((x) & (~BITS_MGQ_FIFO_LIFETIME)) #define BIT_GET_MGQ_FIFO_LIFETIME(x) \ (((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME) & BIT_MASK_MGQ_FIFO_LIFETIME) #define BIT_SET_MGQ_FIFO_LIFETIME(x, v) \ (BIT_CLEAR_MGQ_FIFO_LIFETIME(x) | BIT_MGQ_FIFO_LIFETIME(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET (Offset 0x147C) */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x7f #define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) \ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) \ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) #define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET \ (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET \ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) #define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) \ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)) #define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) \ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) & \ BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) #define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x, v) \ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) | \ BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PKT_TRANS (Offset 0x1480) */ #define BIT_SHIFT_IE_DESC_OFFSET 16 #define BIT_MASK_IE_DESC_OFFSET 0x1ff #define BIT_IE_DESC_OFFSET(x) \ (((x) & BIT_MASK_IE_DESC_OFFSET) << BIT_SHIFT_IE_DESC_OFFSET) #define BITS_IE_DESC_OFFSET \ (BIT_MASK_IE_DESC_OFFSET << BIT_SHIFT_IE_DESC_OFFSET) #define BIT_CLEAR_IE_DESC_OFFSET(x) ((x) & (~BITS_IE_DESC_OFFSET)) #define BIT_GET_IE_DESC_OFFSET(x) \ (((x) >> BIT_SHIFT_IE_DESC_OFFSET) & BIT_MASK_IE_DESC_OFFSET) #define BIT_SET_IE_DESC_OFFSET(x, v) \ (BIT_CLEAR_IE_DESC_OFFSET(x) | BIT_IE_DESC_OFFSET(v)) #define BIT_DIS_FWCMD_PATH_ERRCHK BIT(13) #define BIT_MAC_HDR_CONVERT_EN BIT(12) #define BIT_TXDESC_TRANS_EN BIT(8) #define BIT_PKT_TRANS_ERRINT_EN BIT(7) #define BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL 4 #define BIT_MASK_PKT_TRANS_ERR_MACID_SEL 0x3 #define BIT_PKT_TRANS_ERR_MACID_SEL(x) \ (((x) & BIT_MASK_PKT_TRANS_ERR_MACID_SEL) \ << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL) #define BITS_PKT_TRANS_ERR_MACID_SEL \ (BIT_MASK_PKT_TRANS_ERR_MACID_SEL << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL) #define BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL(x) \ ((x) & (~BITS_PKT_TRANS_ERR_MACID_SEL)) #define BIT_GET_PKT_TRANS_ERR_MACID_SEL(x) \ (((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL) & \ BIT_MASK_PKT_TRANS_ERR_MACID_SEL) #define BIT_SET_PKT_TRANS_ERR_MACID_SEL(x, v) \ (BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL(x) | BIT_PKT_TRANS_ERR_MACID_SEL(v)) #define BIT_PKT_TRANS_IEINIT_ERR BIT(3) #define BIT_PKT_TRANS_IENUM_ERR BIT(2) #define BIT_PKT_TRANS_IECNT_ERR1 BIT(1) #define BIT_PKT_TRANS_IECNT_ERR0 BIT(0) /* 2 REG_SHCUT_LLC_ETH_TYPE1 (Offset 0x1488) */ #define BIT_SHIFT_SHCUT_MHDR_OFFSET 16 #define BIT_MASK_SHCUT_MHDR_OFFSET 0x1ff #define BIT_SHCUT_MHDR_OFFSET(x) \ (((x) & BIT_MASK_SHCUT_MHDR_OFFSET) << BIT_SHIFT_SHCUT_MHDR_OFFSET) #define BITS_SHCUT_MHDR_OFFSET \ (BIT_MASK_SHCUT_MHDR_OFFSET << BIT_SHIFT_SHCUT_MHDR_OFFSET) #define BIT_CLEAR_SHCUT_MHDR_OFFSET(x) ((x) & (~BITS_SHCUT_MHDR_OFFSET)) #define BIT_GET_SHCUT_MHDR_OFFSET(x) \ (((x) >> BIT_SHIFT_SHCUT_MHDR_OFFSET) & BIT_MASK_SHCUT_MHDR_OFFSET) #define BIT_SET_SHCUT_MHDR_OFFSET(x, v) \ (BIT_CLEAR_SHCUT_MHDR_OFFSET(x) | BIT_SHCUT_MHDR_OFFSET(v)) #define BIT_SHIFT_PKT_TRANS_ERR_MACID 0 #define BIT_MASK_PKT_TRANS_ERR_MACID 0xffffffffL #define BIT_PKT_TRANS_ERR_MACID(x) \ (((x) & BIT_MASK_PKT_TRANS_ERR_MACID) << BIT_SHIFT_PKT_TRANS_ERR_MACID) #define BITS_PKT_TRANS_ERR_MACID \ (BIT_MASK_PKT_TRANS_ERR_MACID << BIT_SHIFT_PKT_TRANS_ERR_MACID) #define BIT_CLEAR_PKT_TRANS_ERR_MACID(x) ((x) & (~BITS_PKT_TRANS_ERR_MACID)) #define BIT_GET_PKT_TRANS_ERR_MACID(x) \ (((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID) & BIT_MASK_PKT_TRANS_ERR_MACID) #define BIT_SET_PKT_TRANS_ERR_MACID(x, v) \ (BIT_CLEAR_PKT_TRANS_ERR_MACID(x) | BIT_PKT_TRANS_ERR_MACID(v)) /* 2 REG_FWCMDQ_CTRL (Offset 0x14A0) */ #define BIT_FW_RELEASEPKT_POLLING BIT(31) #define BIT_SHIFT_FWCMDQ_RELEASE_HEAD 16 #define BIT_MASK_FWCMDQ_RELEASE_HEAD 0xfff #define BIT_FWCMDQ_RELEASE_HEAD(x) \ (((x) & BIT_MASK_FWCMDQ_RELEASE_HEAD) << BIT_SHIFT_FWCMDQ_RELEASE_HEAD) #define BITS_FWCMDQ_RELEASE_HEAD \ (BIT_MASK_FWCMDQ_RELEASE_HEAD << BIT_SHIFT_FWCMDQ_RELEASE_HEAD) #define BIT_CLEAR_FWCMDQ_RELEASE_HEAD(x) ((x) & (~BITS_FWCMDQ_RELEASE_HEAD)) #define BIT_GET_FWCMDQ_RELEASE_HEAD(x) \ (((x) >> BIT_SHIFT_FWCMDQ_RELEASE_HEAD) & BIT_MASK_FWCMDQ_RELEASE_HEAD) #define BIT_SET_FWCMDQ_RELEASE_HEAD(x, v) \ (BIT_CLEAR_FWCMDQ_RELEASE_HEAD(x) | BIT_FWCMDQ_RELEASE_HEAD(v)) #define BIT_FW_GETPKTT_POLLING BIT(15) #define BIT_SHIFT_FWCMDQ_H 0 #define BIT_MASK_FWCMDQ_H 0xfff #define BIT_FWCMDQ_H(x) (((x) & BIT_MASK_FWCMDQ_H) << BIT_SHIFT_FWCMDQ_H) #define BITS_FWCMDQ_H (BIT_MASK_FWCMDQ_H << BIT_SHIFT_FWCMDQ_H) #define BIT_CLEAR_FWCMDQ_H(x) ((x) & (~BITS_FWCMDQ_H)) #define BIT_GET_FWCMDQ_H(x) (((x) >> BIT_SHIFT_FWCMDQ_H) & BIT_MASK_FWCMDQ_H) #define BIT_SET_FWCMDQ_H(x, v) (BIT_CLEAR_FWCMDQ_H(x) | BIT_FWCMDQ_H(v)) /* 2 REG_FWCMDQ_PAGE (Offset 0x14A4) */ #define BIT_SHIFT_FWCMDQ_TOTAL_PAGE 16 #define BIT_MASK_FWCMDQ_TOTAL_PAGE 0xfff #define BIT_FWCMDQ_TOTAL_PAGE(x) \ (((x) & BIT_MASK_FWCMDQ_TOTAL_PAGE) << BIT_SHIFT_FWCMDQ_TOTAL_PAGE) #define BITS_FWCMDQ_TOTAL_PAGE \ (BIT_MASK_FWCMDQ_TOTAL_PAGE << BIT_SHIFT_FWCMDQ_TOTAL_PAGE) #define BIT_CLEAR_FWCMDQ_TOTAL_PAGE(x) ((x) & (~BITS_FWCMDQ_TOTAL_PAGE)) #define BIT_GET_FWCMDQ_TOTAL_PAGE(x) \ (((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PAGE) & BIT_MASK_FWCMDQ_TOTAL_PAGE) #define BIT_SET_FWCMDQ_TOTAL_PAGE(x, v) \ (BIT_CLEAR_FWCMDQ_TOTAL_PAGE(x) | BIT_FWCMDQ_TOTAL_PAGE(v)) #define BIT_SHIFT_FWCMDQ_QUEUE_PAGE 0 #define BIT_MASK_FWCMDQ_QUEUE_PAGE 0xfff #define BIT_FWCMDQ_QUEUE_PAGE(x) \ (((x) & BIT_MASK_FWCMDQ_QUEUE_PAGE) << BIT_SHIFT_FWCMDQ_QUEUE_PAGE) #define BITS_FWCMDQ_QUEUE_PAGE \ (BIT_MASK_FWCMDQ_QUEUE_PAGE << BIT_SHIFT_FWCMDQ_QUEUE_PAGE) #define BIT_CLEAR_FWCMDQ_QUEUE_PAGE(x) ((x) & (~BITS_FWCMDQ_QUEUE_PAGE)) #define BIT_GET_FWCMDQ_QUEUE_PAGE(x) \ (((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PAGE) & BIT_MASK_FWCMDQ_QUEUE_PAGE) #define BIT_SET_FWCMDQ_QUEUE_PAGE(x, v) \ (BIT_CLEAR_FWCMDQ_QUEUE_PAGE(x) | BIT_FWCMDQ_QUEUE_PAGE(v)) /* 2 REG_FWCMDQ_INFO (Offset 0x14A8) */ #define BIT_FWCMD_READY BIT(31) #define BIT_FWCMDQ_OVERFLOW BIT(30) #define BIT_FWCMDQ_UNDERFLOW BIT(29) #define BIT_FWCMDQ_RELEASE_MISS BIT(28) #define BIT_SHIFT_FWCMDQ_TOTAL_PKT 16 #define BIT_MASK_FWCMDQ_TOTAL_PKT 0xfff #define BIT_FWCMDQ_TOTAL_PKT(x) \ (((x) & BIT_MASK_FWCMDQ_TOTAL_PKT) << BIT_SHIFT_FWCMDQ_TOTAL_PKT) #define BITS_FWCMDQ_TOTAL_PKT \ (BIT_MASK_FWCMDQ_TOTAL_PKT << BIT_SHIFT_FWCMDQ_TOTAL_PKT) #define BIT_CLEAR_FWCMDQ_TOTAL_PKT(x) ((x) & (~BITS_FWCMDQ_TOTAL_PKT)) #define BIT_GET_FWCMDQ_TOTAL_PKT(x) \ (((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PKT) & BIT_MASK_FWCMDQ_TOTAL_PKT) #define BIT_SET_FWCMDQ_TOTAL_PKT(x, v) \ (BIT_CLEAR_FWCMDQ_TOTAL_PKT(x) | BIT_FWCMDQ_TOTAL_PKT(v)) #define BIT_SHIFT_FWCMDQ_QUEUE_PKT 0 #define BIT_MASK_FWCMDQ_QUEUE_PKT 0xfff #define BIT_FWCMDQ_QUEUE_PKT(x) \ (((x) & BIT_MASK_FWCMDQ_QUEUE_PKT) << BIT_SHIFT_FWCMDQ_QUEUE_PKT) #define BITS_FWCMDQ_QUEUE_PKT \ (BIT_MASK_FWCMDQ_QUEUE_PKT << BIT_SHIFT_FWCMDQ_QUEUE_PKT) #define BIT_CLEAR_FWCMDQ_QUEUE_PKT(x) ((x) & (~BITS_FWCMDQ_QUEUE_PKT)) #define BIT_GET_FWCMDQ_QUEUE_PKT(x) \ (((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PKT) & BIT_MASK_FWCMDQ_QUEUE_PKT) #define BIT_SET_FWCMDQ_QUEUE_PKT(x, v) \ (BIT_CLEAR_FWCMDQ_QUEUE_PKT(x) | BIT_FWCMDQ_QUEUE_PKT(v)) /* 2 REG_FWCMDQ_HOLD_PKTNUM (Offset 0x14AC) */ #define BIT_SHIFT_FWCMDQ_HOLD__PKTNUM 0 #define BIT_MASK_FWCMDQ_HOLD__PKTNUM 0xfff #define BIT_FWCMDQ_HOLD__PKTNUM(x) \ (((x) & BIT_MASK_FWCMDQ_HOLD__PKTNUM) << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM) #define BITS_FWCMDQ_HOLD__PKTNUM \ (BIT_MASK_FWCMDQ_HOLD__PKTNUM << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM) #define BIT_CLEAR_FWCMDQ_HOLD__PKTNUM(x) ((x) & (~BITS_FWCMDQ_HOLD__PKTNUM)) #define BIT_GET_FWCMDQ_HOLD__PKTNUM(x) \ (((x) >> BIT_SHIFT_FWCMDQ_HOLD__PKTNUM) & BIT_MASK_FWCMDQ_HOLD__PKTNUM) #define BIT_SET_FWCMDQ_HOLD__PKTNUM(x, v) \ (BIT_CLEAR_FWCMDQ_HOLD__PKTNUM(x) | BIT_FWCMDQ_HOLD__PKTNUM(v)) /* 2 REG_MU_TX_CTRL (Offset 0x14C0) */ #define BIT_SEARCH_DONE_RDY BIT(31) #define BIT_MU_EN BIT(30) #define BIT_MU_SECONDARY_WAITMODE_EN BIT(29) #define BIT_MU_BB_SCORE_EN BIT(28) #define BIT_MU_SECONDARY_ANT_COUNT_EN BIT(27) #define BIT_MUARB_SEARCH_ERR_EN BIT(26) #define BIT_SHIFT_DIS_SU_TXBF 16 #define BIT_MASK_DIS_SU_TXBF 0x3f #define BIT_DIS_SU_TXBF(x) \ (((x) & BIT_MASK_DIS_SU_TXBF) << BIT_SHIFT_DIS_SU_TXBF) #define BITS_DIS_SU_TXBF (BIT_MASK_DIS_SU_TXBF << BIT_SHIFT_DIS_SU_TXBF) #define BIT_CLEAR_DIS_SU_TXBF(x) ((x) & (~BITS_DIS_SU_TXBF)) #define BIT_GET_DIS_SU_TXBF(x) \ (((x) >> BIT_SHIFT_DIS_SU_TXBF) & BIT_MASK_DIS_SU_TXBF) #define BIT_SET_DIS_SU_TXBF(x, v) \ (BIT_CLEAR_DIS_SU_TXBF(x) | BIT_DIS_SU_TXBF(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MU_TX_CTL (Offset 0x14C0) */ #define BIT_R_MU_P1_WAIT_STATE_EN BIT(16) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MU_TX_CTRL (Offset 0x14C0) */ #define BIT_SHIFT_MU_RL 12 #define BIT_MASK_MU_RL 0xf #define BIT_MU_RL(x) (((x) & BIT_MASK_MU_RL) << BIT_SHIFT_MU_RL) #define BITS_MU_RL (BIT_MASK_MU_RL << BIT_SHIFT_MU_RL) #define BIT_CLEAR_MU_RL(x) ((x) & (~BITS_MU_RL)) #define BIT_GET_MU_RL(x) (((x) >> BIT_SHIFT_MU_RL) & BIT_MASK_MU_RL) #define BIT_SET_MU_RL(x, v) (BIT_CLEAR_MU_RL(x) | BIT_MU_RL(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MU_TX_CTL (Offset 0x14C0) */ #define BIT_SHIFT_R_MU_RL 12 #define BIT_MASK_R_MU_RL 0xf #define BIT_R_MU_RL(x) (((x) & BIT_MASK_R_MU_RL) << BIT_SHIFT_R_MU_RL) #define BITS_R_MU_RL (BIT_MASK_R_MU_RL << BIT_SHIFT_R_MU_RL) #define BIT_CLEAR_R_MU_RL(x) ((x) & (~BITS_R_MU_RL)) #define BIT_GET_R_MU_RL(x) (((x) >> BIT_SHIFT_R_MU_RL) & BIT_MASK_R_MU_RL) #define BIT_SET_R_MU_RL(x, v) (BIT_CLEAR_R_MU_RL(x) | BIT_R_MU_RL(v)) #define BIT_R_FORCE_P1_RATEDOWN BIT(11) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MU_TX_CTRL (Offset 0x14C0) */ #define BIT_SHIFT_MU_TAB_SEL 8 #define BIT_MASK_MU_TAB_SEL 0xf #define BIT_MU_TAB_SEL(x) (((x) & BIT_MASK_MU_TAB_SEL) << BIT_SHIFT_MU_TAB_SEL) #define BITS_MU_TAB_SEL (BIT_MASK_MU_TAB_SEL << BIT_SHIFT_MU_TAB_SEL) #define BIT_CLEAR_MU_TAB_SEL(x) ((x) & (~BITS_MU_TAB_SEL)) #define BIT_GET_MU_TAB_SEL(x) \ (((x) >> BIT_SHIFT_MU_TAB_SEL) & BIT_MASK_MU_TAB_SEL) #define BIT_SET_MU_TAB_SEL(x, v) (BIT_CLEAR_MU_TAB_SEL(x) | BIT_MU_TAB_SEL(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MU_TX_CTL (Offset 0x14C0) */ #define BIT_SHIFT_R_MU_TAB_SEL 8 #define BIT_MASK_R_MU_TAB_SEL 0x7 #define BIT_R_MU_TAB_SEL(x) \ (((x) & BIT_MASK_R_MU_TAB_SEL) << BIT_SHIFT_R_MU_TAB_SEL) #define BITS_R_MU_TAB_SEL (BIT_MASK_R_MU_TAB_SEL << BIT_SHIFT_R_MU_TAB_SEL) #define BIT_CLEAR_R_MU_TAB_SEL(x) ((x) & (~BITS_R_MU_TAB_SEL)) #define BIT_GET_R_MU_TAB_SEL(x) \ (((x) >> BIT_SHIFT_R_MU_TAB_SEL) & BIT_MASK_R_MU_TAB_SEL) #define BIT_SET_R_MU_TAB_SEL(x, v) \ (BIT_CLEAR_R_MU_TAB_SEL(x) | BIT_R_MU_TAB_SEL(v)) #define BIT_R_EN_MU_MIMO BIT(7) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MU_TX_CTL (Offset 0x14C0) */ #define BIT_R_EN_REVERS_GTAB BIT(6) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MU_TX_CTRL (Offset 0x14C0) */ #define BIT_SHIFT_MU_TAB_VALID 0 #define BIT_MASK_MU_TAB_VALID 0x3f #define BIT_MU_TAB_VALID(x) \ (((x) & BIT_MASK_MU_TAB_VALID) << BIT_SHIFT_MU_TAB_VALID) #define BITS_MU_TAB_VALID (BIT_MASK_MU_TAB_VALID << BIT_SHIFT_MU_TAB_VALID) #define BIT_CLEAR_MU_TAB_VALID(x) ((x) & (~BITS_MU_TAB_VALID)) #define BIT_GET_MU_TAB_VALID(x) \ (((x) >> BIT_SHIFT_MU_TAB_VALID) & BIT_MASK_MU_TAB_VALID) #define BIT_SET_MU_TAB_VALID(x, v) \ (BIT_CLEAR_MU_TAB_VALID(x) | BIT_MU_TAB_VALID(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MU_TX_CTL (Offset 0x14C0) */ #define BIT_SHIFT_R_MU_TABLE_VALID 0 #define BIT_MASK_R_MU_TABLE_VALID 0x3f #define BIT_R_MU_TABLE_VALID(x) \ (((x) & BIT_MASK_R_MU_TABLE_VALID) << BIT_SHIFT_R_MU_TABLE_VALID) #define BITS_R_MU_TABLE_VALID \ (BIT_MASK_R_MU_TABLE_VALID << BIT_SHIFT_R_MU_TABLE_VALID) #define BIT_CLEAR_R_MU_TABLE_VALID(x) ((x) & (~BITS_R_MU_TABLE_VALID)) #define BIT_GET_R_MU_TABLE_VALID(x) \ (((x) >> BIT_SHIFT_R_MU_TABLE_VALID) & BIT_MASK_R_MU_TABLE_VALID) #define BIT_SET_R_MU_TABLE_VALID(x, v) \ (BIT_CLEAR_R_MU_TABLE_VALID(x) | BIT_R_MU_TABLE_VALID(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MU_STA_GID_VLD (Offset 0x14C4) */ #define BIT_SHIFT_MU_STA_GTAB_VALID 0 #define BIT_MASK_MU_STA_GTAB_VALID 0xffffffffL #define BIT_MU_STA_GTAB_VALID(x) \ (((x) & BIT_MASK_MU_STA_GTAB_VALID) << BIT_SHIFT_MU_STA_GTAB_VALID) #define BITS_MU_STA_GTAB_VALID \ (BIT_MASK_MU_STA_GTAB_VALID << BIT_SHIFT_MU_STA_GTAB_VALID) #define BIT_CLEAR_MU_STA_GTAB_VALID(x) ((x) & (~BITS_MU_STA_GTAB_VALID)) #define BIT_GET_MU_STA_GTAB_VALID(x) \ (((x) >> BIT_SHIFT_MU_STA_GTAB_VALID) & BIT_MASK_MU_STA_GTAB_VALID) #define BIT_SET_MU_STA_GTAB_VALID(x, v) \ (BIT_CLEAR_MU_STA_GTAB_VALID(x) | BIT_MU_STA_GTAB_VALID(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MU_STA_GID_VLD (Offset 0x14C4) */ #define BIT_SHIFT_R_MU_STA_GTAB_VALID 0 #define BIT_MASK_R_MU_STA_GTAB_VALID 0xffffffffL #define BIT_R_MU_STA_GTAB_VALID(x) \ (((x) & BIT_MASK_R_MU_STA_GTAB_VALID) << BIT_SHIFT_R_MU_STA_GTAB_VALID) #define BITS_R_MU_STA_GTAB_VALID \ (BIT_MASK_R_MU_STA_GTAB_VALID << BIT_SHIFT_R_MU_STA_GTAB_VALID) #define BIT_CLEAR_R_MU_STA_GTAB_VALID(x) ((x) & (~BITS_R_MU_STA_GTAB_VALID)) #define BIT_GET_R_MU_STA_GTAB_VALID(x) \ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID) & BIT_MASK_R_MU_STA_GTAB_VALID) #define BIT_SET_R_MU_STA_GTAB_VALID(x, v) \ (BIT_CLEAR_R_MU_STA_GTAB_VALID(x) | BIT_R_MU_STA_GTAB_VALID(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MU_STA_USER_POS_INFO (Offset 0x14C8) */ #define BIT_SHIFT_MU_STA_GTAB_POSITION_L 0 #define BIT_MASK_MU_STA_GTAB_POSITION_L 0xffffffffL #define BIT_MU_STA_GTAB_POSITION_L(x) \ (((x) & BIT_MASK_MU_STA_GTAB_POSITION_L) \ << BIT_SHIFT_MU_STA_GTAB_POSITION_L) #define BITS_MU_STA_GTAB_POSITION_L \ (BIT_MASK_MU_STA_GTAB_POSITION_L << BIT_SHIFT_MU_STA_GTAB_POSITION_L) #define BIT_CLEAR_MU_STA_GTAB_POSITION_L(x) \ ((x) & (~BITS_MU_STA_GTAB_POSITION_L)) #define BIT_GET_MU_STA_GTAB_POSITION_L(x) \ (((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_L) & \ BIT_MASK_MU_STA_GTAB_POSITION_L) #define BIT_SET_MU_STA_GTAB_POSITION_L(x, v) \ (BIT_CLEAR_MU_STA_GTAB_POSITION_L(x) | BIT_MU_STA_GTAB_POSITION_L(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MU_STA_USER_POS_INFO (Offset 0x14C8) */ #define BIT_SHIFT_R_MU_STA_GTAB_POSITION_L 0 #define BIT_MASK_R_MU_STA_GTAB_POSITION_L 0xffffffffL #define BIT_R_MU_STA_GTAB_POSITION_L(x) \ (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_L) \ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L) #define BITS_R_MU_STA_GTAB_POSITION_L \ (BIT_MASK_R_MU_STA_GTAB_POSITION_L \ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L) #define BIT_CLEAR_R_MU_STA_GTAB_POSITION_L(x) \ ((x) & (~BITS_R_MU_STA_GTAB_POSITION_L)) #define BIT_GET_R_MU_STA_GTAB_POSITION_L(x) \ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_L) & \ BIT_MASK_R_MU_STA_GTAB_POSITION_L) #define BIT_SET_R_MU_STA_GTAB_POSITION_L(x, v) \ (BIT_CLEAR_R_MU_STA_GTAB_POSITION_L(x) | \ BIT_R_MU_STA_GTAB_POSITION_L(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MU_STA_USER_POS_INFO_H (Offset 0x14CC) */ #define BIT_SHIFT_MU_STA_GTAB_POSITION_H 0 #define BIT_MASK_MU_STA_GTAB_POSITION_H 0xffffffffL #define BIT_MU_STA_GTAB_POSITION_H(x) \ (((x) & BIT_MASK_MU_STA_GTAB_POSITION_H) \ << BIT_SHIFT_MU_STA_GTAB_POSITION_H) #define BITS_MU_STA_GTAB_POSITION_H \ (BIT_MASK_MU_STA_GTAB_POSITION_H << BIT_SHIFT_MU_STA_GTAB_POSITION_H) #define BIT_CLEAR_MU_STA_GTAB_POSITION_H(x) \ ((x) & (~BITS_MU_STA_GTAB_POSITION_H)) #define BIT_GET_MU_STA_GTAB_POSITION_H(x) \ (((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_H) & \ BIT_MASK_MU_STA_GTAB_POSITION_H) #define BIT_SET_MU_STA_GTAB_POSITION_H(x, v) \ (BIT_CLEAR_MU_STA_GTAB_POSITION_H(x) | BIT_MU_STA_GTAB_POSITION_H(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MU_STA_USER_POS_INFO_H (Offset 0x14CC) */ #define BIT_SHIFT_R_MU_STA_GTAB_POSITION_H 0 #define BIT_MASK_R_MU_STA_GTAB_POSITION_H 0xffffffffL #define BIT_R_MU_STA_GTAB_POSITION_H(x) \ (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_H) \ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H) #define BITS_R_MU_STA_GTAB_POSITION_H \ (BIT_MASK_R_MU_STA_GTAB_POSITION_H \ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H) #define BIT_CLEAR_R_MU_STA_GTAB_POSITION_H(x) \ ((x) & (~BITS_R_MU_STA_GTAB_POSITION_H)) #define BIT_GET_R_MU_STA_GTAB_POSITION_H(x) \ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_H) & \ BIT_MASK_R_MU_STA_GTAB_POSITION_H) #define BIT_SET_R_MU_STA_GTAB_POSITION_H(x, v) \ (BIT_CLEAR_R_MU_STA_GTAB_POSITION_H(x) | \ BIT_R_MU_STA_GTAB_POSITION_H(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MU_TRX_DBG_CNT (Offset 0x14D0) */ #define BIT_MU_DNGCNT_RST BIT(20) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MU_TRX_DBG_CNT (Offset 0x14D0) */ #define BIT_SHIFT_MU_DBGCNT_SEL 16 #define BIT_MASK_MU_DBGCNT_SEL 0xf #define BIT_MU_DBGCNT_SEL(x) \ (((x) & BIT_MASK_MU_DBGCNT_SEL) << BIT_SHIFT_MU_DBGCNT_SEL) #define BITS_MU_DBGCNT_SEL (BIT_MASK_MU_DBGCNT_SEL << BIT_SHIFT_MU_DBGCNT_SEL) #define BIT_CLEAR_MU_DBGCNT_SEL(x) ((x) & (~BITS_MU_DBGCNT_SEL)) #define BIT_GET_MU_DBGCNT_SEL(x) \ (((x) >> BIT_SHIFT_MU_DBGCNT_SEL) & BIT_MASK_MU_DBGCNT_SEL) #define BIT_SET_MU_DBGCNT_SEL(x, v) \ (BIT_CLEAR_MU_DBGCNT_SEL(x) | BIT_MU_DBGCNT_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_CHNL_INFO_CTRL (Offset 0x14D0) */ #define BIT_CHNL_REF_RXNAV BIT(7) #define BIT_CHNL_REF_VBON BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_CHNL_INFO_CTRL (Offset 0x14D0) */ #define BIT_CHNL_REF_EDCCA BIT(5) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CHNL_INFO_CTRL (Offset 0x14D0) */ #define BIT_CHNL_REF_EDCA BIT(5) #define BIT_CHNL_REF_CCA BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_CHNL_INFO_CTRL (Offset 0x14D0) */ #define BIT_RST_CHNL_BUSY BIT(3) #define BIT_RST_CHNL_IDLE BIT(2) #define BIT_CHNL_INFO_RST BIT(1) #define BIT_ATM_AIRTIME_EN BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_MU_TRX_DBG_CNT (Offset 0x14D0) */ #define BIT_SHIFT_MU_DNGCNT 0 #define BIT_MASK_MU_DNGCNT 0xffff #define BIT_MU_DNGCNT(x) (((x) & BIT_MASK_MU_DNGCNT) << BIT_SHIFT_MU_DNGCNT) #define BITS_MU_DNGCNT (BIT_MASK_MU_DNGCNT << BIT_SHIFT_MU_DNGCNT) #define BIT_CLEAR_MU_DNGCNT(x) ((x) & (~BITS_MU_DNGCNT)) #define BIT_GET_MU_DNGCNT(x) (((x) >> BIT_SHIFT_MU_DNGCNT) & BIT_MASK_MU_DNGCNT) #define BIT_SET_MU_DNGCNT(x, v) (BIT_CLEAR_MU_DNGCNT(x) | BIT_MU_DNGCNT(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_CHNL_IDLE_TIME (Offset 0x14D4) */ #define BIT_SHIFT_CHNL_IDLE_TIME 0 #define BIT_MASK_CHNL_IDLE_TIME 0xffffffffL #define BIT_CHNL_IDLE_TIME(x) \ (((x) & BIT_MASK_CHNL_IDLE_TIME) << BIT_SHIFT_CHNL_IDLE_TIME) #define BITS_CHNL_IDLE_TIME \ (BIT_MASK_CHNL_IDLE_TIME << BIT_SHIFT_CHNL_IDLE_TIME) #define BIT_CLEAR_CHNL_IDLE_TIME(x) ((x) & (~BITS_CHNL_IDLE_TIME)) #define BIT_GET_CHNL_IDLE_TIME(x) \ (((x) >> BIT_SHIFT_CHNL_IDLE_TIME) & BIT_MASK_CHNL_IDLE_TIME) #define BIT_SET_CHNL_IDLE_TIME(x, v) \ (BIT_CLEAR_CHNL_IDLE_TIME(x) | BIT_CHNL_IDLE_TIME(v)) /* 2 REG_CHNL_BUSY_TIME (Offset 0x14D8) */ #define BIT_SHIFT_CHNL_BUSY_TIME 0 #define BIT_MASK_CHNL_BUSY_TIME 0xffffffffL #define BIT_CHNL_BUSY_TIME(x) \ (((x) & BIT_MASK_CHNL_BUSY_TIME) << BIT_SHIFT_CHNL_BUSY_TIME) #define BITS_CHNL_BUSY_TIME \ (BIT_MASK_CHNL_BUSY_TIME << BIT_SHIFT_CHNL_BUSY_TIME) #define BIT_CLEAR_CHNL_BUSY_TIME(x) ((x) & (~BITS_CHNL_BUSY_TIME)) #define BIT_GET_CHNL_BUSY_TIME(x) \ (((x) >> BIT_SHIFT_CHNL_BUSY_TIME) & BIT_MASK_CHNL_BUSY_TIME) #define BIT_SET_CHNL_BUSY_TIME(x, v) \ (BIT_CLEAR_CHNL_BUSY_TIME(x) | BIT_CHNL_BUSY_TIME(v)) #define BIT_SHIFT_BW_CFG 0 #define BIT_MASK_BW_CFG 0x3 #define BIT_BW_CFG(x) (((x) & BIT_MASK_BW_CFG) << BIT_SHIFT_BW_CFG) #define BITS_BW_CFG (BIT_MASK_BW_CFG << BIT_SHIFT_BW_CFG) #define BIT_CLEAR_BW_CFG(x) ((x) & (~BITS_BW_CFG)) #define BIT_GET_BW_CFG(x) (((x) >> BIT_SHIFT_BW_CFG) & BIT_MASK_BW_CFG) #define BIT_SET_BW_CFG(x, v) (BIT_CLEAR_BW_CFG(x) | BIT_BW_CFG(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_MU_TRX_DBG_CNT_V1 (Offset 0x14DC) */ #define BIT_FORCE_SND_STS_EN BIT(31) #define BIT_SHIFT_SND_STS_VALUE 24 #define BIT_MASK_SND_STS_VALUE 0x3f #define BIT_SND_STS_VALUE(x) \ (((x) & BIT_MASK_SND_STS_VALUE) << BIT_SHIFT_SND_STS_VALUE) #define BITS_SND_STS_VALUE (BIT_MASK_SND_STS_VALUE << BIT_SHIFT_SND_STS_VALUE) #define BIT_CLEAR_SND_STS_VALUE(x) ((x) & (~BITS_SND_STS_VALUE)) #define BIT_GET_SND_STS_VALUE(x) \ (((x) >> BIT_SHIFT_SND_STS_VALUE) & BIT_MASK_SND_STS_VALUE) #define BIT_SET_SND_STS_VALUE(x, v) \ (BIT_CLEAR_SND_STS_VALUE(x) | BIT_SND_STS_VALUE(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MU_TRX_DBG_CNT_V1 (Offset 0x14DC) */ #define BIT_SHIFT_MU_DNGCNT_SEL 16 #define BIT_MASK_MU_DNGCNT_SEL 0xf #define BIT_MU_DNGCNT_SEL(x) \ (((x) & BIT_MASK_MU_DNGCNT_SEL) << BIT_SHIFT_MU_DNGCNT_SEL) #define BITS_MU_DNGCNT_SEL (BIT_MASK_MU_DNGCNT_SEL << BIT_SHIFT_MU_DNGCNT_SEL) #define BIT_CLEAR_MU_DNGCNT_SEL(x) ((x) & (~BITS_MU_DNGCNT_SEL)) #define BIT_GET_MU_DNGCNT_SEL(x) \ (((x) >> BIT_SHIFT_MU_DNGCNT_SEL) & BIT_MASK_MU_DNGCNT_SEL) #define BIT_SET_MU_DNGCNT_SEL(x, v) \ (BIT_CLEAR_MU_DNGCNT_SEL(x) | BIT_MU_DNGCNT_SEL(v)) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_SWPS_CTRL (Offset 0x14F4) */ #define BIT_SHIFT_SWPS_RPT_LENGTH 8 #define BIT_MASK_SWPS_RPT_LENGTH 0x7f #define BIT_SWPS_RPT_LENGTH(x) \ (((x) & BIT_MASK_SWPS_RPT_LENGTH) << BIT_SHIFT_SWPS_RPT_LENGTH) #define BITS_SWPS_RPT_LENGTH \ (BIT_MASK_SWPS_RPT_LENGTH << BIT_SHIFT_SWPS_RPT_LENGTH) #define BIT_CLEAR_SWPS_RPT_LENGTH(x) ((x) & (~BITS_SWPS_RPT_LENGTH)) #define BIT_GET_SWPS_RPT_LENGTH(x) \ (((x) >> BIT_SHIFT_SWPS_RPT_LENGTH) & BIT_MASK_SWPS_RPT_LENGTH) #define BIT_SET_SWPS_RPT_LENGTH(x, v) \ (BIT_CLEAR_SWPS_RPT_LENGTH(x) | BIT_SWPS_RPT_LENGTH(v)) #define BIT_SHIFT_MACID_SWPS_EN_SEL 2 #define BIT_MASK_MACID_SWPS_EN_SEL 0x3 #define BIT_MACID_SWPS_EN_SEL(x) \ (((x) & BIT_MASK_MACID_SWPS_EN_SEL) << BIT_SHIFT_MACID_SWPS_EN_SEL) #define BITS_MACID_SWPS_EN_SEL \ (BIT_MASK_MACID_SWPS_EN_SEL << BIT_SHIFT_MACID_SWPS_EN_SEL) #define BIT_CLEAR_MACID_SWPS_EN_SEL(x) ((x) & (~BITS_MACID_SWPS_EN_SEL)) #define BIT_GET_MACID_SWPS_EN_SEL(x) \ (((x) >> BIT_SHIFT_MACID_SWPS_EN_SEL) & BIT_MASK_MACID_SWPS_EN_SEL) #define BIT_SET_MACID_SWPS_EN_SEL(x, v) \ (BIT_CLEAR_MACID_SWPS_EN_SEL(x) | BIT_MACID_SWPS_EN_SEL(v)) #define BIT_SWPS_MANUALL_POLLING BIT(1) #define BIT_SWPS_EN BIT(0) /* 2 REG_SWPS_PKT_TH (Offset 0x14F6) */ #define BIT_SHIFT_SWPS_PKT_TH 0 #define BIT_MASK_SWPS_PKT_TH 0xffff #define BIT_SWPS_PKT_TH(x) \ (((x) & BIT_MASK_SWPS_PKT_TH) << BIT_SHIFT_SWPS_PKT_TH) #define BITS_SWPS_PKT_TH (BIT_MASK_SWPS_PKT_TH << BIT_SHIFT_SWPS_PKT_TH) #define BIT_CLEAR_SWPS_PKT_TH(x) ((x) & (~BITS_SWPS_PKT_TH)) #define BIT_GET_SWPS_PKT_TH(x) \ (((x) >> BIT_SHIFT_SWPS_PKT_TH) & BIT_MASK_SWPS_PKT_TH) #define BIT_SET_SWPS_PKT_TH(x, v) \ (BIT_CLEAR_SWPS_PKT_TH(x) | BIT_SWPS_PKT_TH(v)) /* 2 REG_SWPS_TIME_TH (Offset 0x14F8) */ #define BIT_SHIFT_SWPS_PSTIME_TH 16 #define BIT_MASK_SWPS_PSTIME_TH 0xffff #define BIT_SWPS_PSTIME_TH(x) \ (((x) & BIT_MASK_SWPS_PSTIME_TH) << BIT_SHIFT_SWPS_PSTIME_TH) #define BITS_SWPS_PSTIME_TH \ (BIT_MASK_SWPS_PSTIME_TH << BIT_SHIFT_SWPS_PSTIME_TH) #define BIT_CLEAR_SWPS_PSTIME_TH(x) ((x) & (~BITS_SWPS_PSTIME_TH)) #define BIT_GET_SWPS_PSTIME_TH(x) \ (((x) >> BIT_SHIFT_SWPS_PSTIME_TH) & BIT_MASK_SWPS_PSTIME_TH) #define BIT_SET_SWPS_PSTIME_TH(x, v) \ (BIT_CLEAR_SWPS_PSTIME_TH(x) | BIT_SWPS_PSTIME_TH(v)) #define BIT_SHIFT_SWPS_TIME_TH 0 #define BIT_MASK_SWPS_TIME_TH 0xffff #define BIT_SWPS_TIME_TH(x) \ (((x) & BIT_MASK_SWPS_TIME_TH) << BIT_SHIFT_SWPS_TIME_TH) #define BITS_SWPS_TIME_TH (BIT_MASK_SWPS_TIME_TH << BIT_SHIFT_SWPS_TIME_TH) #define BIT_CLEAR_SWPS_TIME_TH(x) ((x) & (~BITS_SWPS_TIME_TH)) #define BIT_GET_SWPS_TIME_TH(x) \ (((x) >> BIT_SHIFT_SWPS_TIME_TH) & BIT_MASK_SWPS_TIME_TH) #define BIT_SET_SWPS_TIME_TH(x, v) \ (BIT_CLEAR_SWPS_TIME_TH(x) | BIT_SWPS_TIME_TH(v)) /* 2 REG_MACID_SWPS_EN (Offset 0x14FC) */ #define BIT_SHIFT_MACID_SWPS_EN 0 #define BIT_MASK_MACID_SWPS_EN 0xffffffffL #define BIT_MACID_SWPS_EN(x) \ (((x) & BIT_MASK_MACID_SWPS_EN) << BIT_SHIFT_MACID_SWPS_EN) #define BITS_MACID_SWPS_EN (BIT_MASK_MACID_SWPS_EN << BIT_SHIFT_MACID_SWPS_EN) #define BIT_CLEAR_MACID_SWPS_EN(x) ((x) & (~BITS_MACID_SWPS_EN)) #define BIT_GET_MACID_SWPS_EN(x) \ (((x) >> BIT_SHIFT_MACID_SWPS_EN) & BIT_MASK_MACID_SWPS_EN) #define BIT_SET_MACID_SWPS_EN(x, v) \ (BIT_CLEAR_MACID_SWPS_EN(x) | BIT_MACID_SWPS_EN(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PORT_CTRL_SEL (Offset 0x1500) */ #define BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1 4 #define BIT_MASK_BCN_TIMER_SEL_FWRD_V1 0x7 #define BIT_BCN_TIMER_SEL_FWRD_V1(x) \ (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_V1) \ << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1) #define BITS_BCN_TIMER_SEL_FWRD_V1 \ (BIT_MASK_BCN_TIMER_SEL_FWRD_V1 << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1) #define BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1(x) ((x) & (~BITS_BCN_TIMER_SEL_FWRD_V1)) #define BIT_GET_BCN_TIMER_SEL_FWRD_V1(x) \ (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1) & \ BIT_MASK_BCN_TIMER_SEL_FWRD_V1) #define BIT_SET_BCN_TIMER_SEL_FWRD_V1(x, v) \ (BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1(x) | BIT_BCN_TIMER_SEL_FWRD_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CPUMGQ_TX_TIMER (Offset 0x1500) */ #define BIT_SHIFT_CPUMGQ_TX_TIMER_V1 0 #define BIT_MASK_CPUMGQ_TX_TIMER_V1 0xffffffffL #define BIT_CPUMGQ_TX_TIMER_V1(x) \ (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1) #define BITS_CPUMGQ_TX_TIMER_V1 \ (BIT_MASK_CPUMGQ_TX_TIMER_V1 << BIT_SHIFT_CPUMGQ_TX_TIMER_V1) #define BIT_CLEAR_CPUMGQ_TX_TIMER_V1(x) ((x) & (~BITS_CPUMGQ_TX_TIMER_V1)) #define BIT_GET_CPUMGQ_TX_TIMER_V1(x) \ (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1) & BIT_MASK_CPUMGQ_TX_TIMER_V1) #define BIT_SET_CPUMGQ_TX_TIMER_V1(x, v) \ (BIT_CLEAR_CPUMGQ_TX_TIMER_V1(x) | BIT_CPUMGQ_TX_TIMER_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_PORT_CTRL_SEL (Offset 0x1500) */ #define BIT_SHIFT_PORT_CTRL_SEL 0 #define BIT_MASK_PORT_CTRL_SEL 0x7 #define BIT_PORT_CTRL_SEL(x) \ (((x) & BIT_MASK_PORT_CTRL_SEL) << BIT_SHIFT_PORT_CTRL_SEL) #define BITS_PORT_CTRL_SEL (BIT_MASK_PORT_CTRL_SEL << BIT_SHIFT_PORT_CTRL_SEL) #define BIT_CLEAR_PORT_CTRL_SEL(x) ((x) & (~BITS_PORT_CTRL_SEL)) #define BIT_GET_PORT_CTRL_SEL(x) \ (((x) >> BIT_SHIFT_PORT_CTRL_SEL) & BIT_MASK_PORT_CTRL_SEL) #define BIT_SET_PORT_CTRL_SEL(x, v) \ (BIT_CLEAR_PORT_CTRL_SEL(x) | BIT_PORT_CTRL_SEL(v)) /* 2 REG_PORT_CTRL_CFG (Offset 0x1501) */ #define BIT_BCNERR_CNT_EN_V1 BIT(11) #define BIT_DIS_TRX_CAL_BCN_V1 BIT(10) #define BIT_DIS_TX_CAL_TBTT_V1 BIT(9) #define BIT_BCN_AGGRESSION_V1 BIT(8) #define BIT_TSFTR_RST_V1 BIT(7) #define BIT_EN_TXBCN_RPT_V1 BIT(5) #define BIT_EN_PORT_FUNCTION BIT(3) #define BIT_EN_RXBCN_RPT BIT(2) /* 2 REG_TBTT_PROHIBIT_CFG (Offset 0x1504) */ #define BIT_MASK_PROHIBIT BIT(23) #define BIT_SHIFT_TBTT_HOLD_TIME 8 #define BIT_MASK_TBTT_HOLD_TIME 0xfff #define BIT_TBTT_HOLD_TIME(x) \ (((x) & BIT_MASK_TBTT_HOLD_TIME) << BIT_SHIFT_TBTT_HOLD_TIME) #define BITS_TBTT_HOLD_TIME \ (BIT_MASK_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME) #define BIT_CLEAR_TBTT_HOLD_TIME(x) ((x) & (~BITS_TBTT_HOLD_TIME)) #define BIT_GET_TBTT_HOLD_TIME(x) \ (((x) >> BIT_SHIFT_TBTT_HOLD_TIME) & BIT_MASK_TBTT_HOLD_TIME) #define BIT_SET_TBTT_HOLD_TIME(x, v) \ (BIT_CLEAR_TBTT_HOLD_TIME(x) | BIT_TBTT_HOLD_TIME(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PS_TIMER_A (Offset 0x1504) */ #define BIT_SHIFT_PS_TIMER_A_V1 0 #define BIT_MASK_PS_TIMER_A_V1 0xffffffffL #define BIT_PS_TIMER_A_V1(x) \ (((x) & BIT_MASK_PS_TIMER_A_V1) << BIT_SHIFT_PS_TIMER_A_V1) #define BITS_PS_TIMER_A_V1 (BIT_MASK_PS_TIMER_A_V1 << BIT_SHIFT_PS_TIMER_A_V1) #define BIT_CLEAR_PS_TIMER_A_V1(x) ((x) & (~BITS_PS_TIMER_A_V1)) #define BIT_GET_PS_TIMER_A_V1(x) \ (((x) >> BIT_SHIFT_PS_TIMER_A_V1) & BIT_MASK_PS_TIMER_A_V1) #define BIT_SET_PS_TIMER_A_V1(x, v) \ (BIT_CLEAR_PS_TIMER_A_V1(x) | BIT_PS_TIMER_A_V1(v)) /* 2 REG_PS_TIMER_B (Offset 0x1508) */ #define BIT_SHIFT_PS_TIMER_B_V1 0 #define BIT_MASK_PS_TIMER_B_V1 0xffffffffL #define BIT_PS_TIMER_B_V1(x) \ (((x) & BIT_MASK_PS_TIMER_B_V1) << BIT_SHIFT_PS_TIMER_B_V1) #define BITS_PS_TIMER_B_V1 (BIT_MASK_PS_TIMER_B_V1 << BIT_SHIFT_PS_TIMER_B_V1) #define BIT_CLEAR_PS_TIMER_B_V1(x) ((x) & (~BITS_PS_TIMER_B_V1)) #define BIT_GET_PS_TIMER_B_V1(x) \ (((x) >> BIT_SHIFT_PS_TIMER_B_V1) & BIT_MASK_PS_TIMER_B_V1) #define BIT_SET_PS_TIMER_B_V1(x, v) \ (BIT_CLEAR_PS_TIMER_B_V1(x) | BIT_PS_TIMER_B_V1(v)) /* 2 REG_PS_TIMER_C (Offset 0x150C) */ #define BIT_SHIFT_PS_TIMER_C_V1 0 #define BIT_MASK_PS_TIMER_C_V1 0xffffffffL #define BIT_PS_TIMER_C_V1(x) \ (((x) & BIT_MASK_PS_TIMER_C_V1) << BIT_SHIFT_PS_TIMER_C_V1) #define BITS_PS_TIMER_C_V1 (BIT_MASK_PS_TIMER_C_V1 << BIT_SHIFT_PS_TIMER_C_V1) #define BIT_CLEAR_PS_TIMER_C_V1(x) ((x) & (~BITS_PS_TIMER_C_V1)) #define BIT_GET_PS_TIMER_C_V1(x) \ (((x) >> BIT_SHIFT_PS_TIMER_C_V1) & BIT_MASK_PS_TIMER_C_V1) #define BIT_SET_PS_TIMER_C_V1(x, v) \ (BIT_CLEAR_PS_TIMER_C_V1(x) | BIT_PS_TIMER_C_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TSFTR_SYNC_OFFSET_CFG (Offset 0x150C) */ #define BIT_SHIFT_TSFTR_SNC_OFFSET_V1 0 #define BIT_MASK_TSFTR_SNC_OFFSET_V1 0xffffff #define BIT_TSFTR_SNC_OFFSET_V1(x) \ (((x) & BIT_MASK_TSFTR_SNC_OFFSET_V1) << BIT_SHIFT_TSFTR_SNC_OFFSET_V1) #define BITS_TSFTR_SNC_OFFSET_V1 \ (BIT_MASK_TSFTR_SNC_OFFSET_V1 << BIT_SHIFT_TSFTR_SNC_OFFSET_V1) #define BIT_CLEAR_TSFTR_SNC_OFFSET_V1(x) ((x) & (~BITS_TSFTR_SNC_OFFSET_V1)) #define BIT_GET_TSFTR_SNC_OFFSET_V1(x) \ (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_V1) & BIT_MASK_TSFTR_SNC_OFFSET_V1) #define BIT_SET_TSFTR_SNC_OFFSET_V1(x, v) \ (BIT_CLEAR_TSFTR_SNC_OFFSET_V1(x) | BIT_TSFTR_SNC_OFFSET_V1(v)) /* 2 REG_TSFTR_SYNC_CTRL_CFG (Offset 0x150F) */ #define BIT_SYNC_TSF_NOW_V1 BIT(5) #define BIT_SYNC_TSF_ONCE BIT(4) #define BIT_SYNC_TSF_AUTO BIT(3) #define BIT_SHIFT_SYNC_PORT_SEL 0 #define BIT_MASK_SYNC_PORT_SEL 0x7 #define BIT_SYNC_PORT_SEL(x) \ (((x) & BIT_MASK_SYNC_PORT_SEL) << BIT_SHIFT_SYNC_PORT_SEL) #define BITS_SYNC_PORT_SEL (BIT_MASK_SYNC_PORT_SEL << BIT_SHIFT_SYNC_PORT_SEL) #define BIT_CLEAR_SYNC_PORT_SEL(x) ((x) & (~BITS_SYNC_PORT_SEL)) #define BIT_GET_SYNC_PORT_SEL(x) \ (((x) >> BIT_SHIFT_SYNC_PORT_SEL) & BIT_MASK_SYNC_PORT_SEL) #define BIT_SET_SYNC_PORT_SEL(x, v) \ (BIT_CLEAR_SYNC_PORT_SEL(x) | BIT_SYNC_PORT_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL (Offset 0x1510) */ #define BIT_CPUMGQ_TIMER_EN BIT(31) #define BIT_CPUMGQ_TX_EN BIT(28) #define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL 24 #define BIT_MASK_CPUMGQ_TIMER_TSF_SEL 0x7 #define BIT_CPUMGQ_TIMER_TSF_SEL(x) \ (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL) \ << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) #define BITS_CPUMGQ_TIMER_TSF_SEL \ (BIT_MASK_CPUMGQ_TIMER_TSF_SEL << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) #define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL(x) ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL)) #define BIT_GET_CPUMGQ_TIMER_TSF_SEL(x) \ (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) & \ BIT_MASK_CPUMGQ_TIMER_TSF_SEL) #define BIT_SET_CPUMGQ_TIMER_TSF_SEL(x, v) \ (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL(x) | BIT_CPUMGQ_TIMER_TSF_SEL(v)) #define BIT_PS_TIMER_C_EN BIT(23) #define BIT_SHIFT_PS_TIMER_C_TSF_SEL 16 #define BIT_MASK_PS_TIMER_C_TSF_SEL 0x7 #define BIT_PS_TIMER_C_TSF_SEL(x) \ (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL) << BIT_SHIFT_PS_TIMER_C_TSF_SEL) #define BITS_PS_TIMER_C_TSF_SEL \ (BIT_MASK_PS_TIMER_C_TSF_SEL << BIT_SHIFT_PS_TIMER_C_TSF_SEL) #define BIT_CLEAR_PS_TIMER_C_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_C_TSF_SEL)) #define BIT_GET_PS_TIMER_C_TSF_SEL(x) \ (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL) & BIT_MASK_PS_TIMER_C_TSF_SEL) #define BIT_SET_PS_TIMER_C_TSF_SEL(x, v) \ (BIT_CLEAR_PS_TIMER_C_TSF_SEL(x) | BIT_PS_TIMER_C_TSF_SEL(v)) #define BIT_PS_TIMER_B_EN BIT(15) #define BIT_SHIFT_PS_TIMER_B_TSF_SEL 8 #define BIT_MASK_PS_TIMER_B_TSF_SEL 0x7 #define BIT_PS_TIMER_B_TSF_SEL(x) \ (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL) << BIT_SHIFT_PS_TIMER_B_TSF_SEL) #define BITS_PS_TIMER_B_TSF_SEL \ (BIT_MASK_PS_TIMER_B_TSF_SEL << BIT_SHIFT_PS_TIMER_B_TSF_SEL) #define BIT_CLEAR_PS_TIMER_B_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_B_TSF_SEL)) #define BIT_GET_PS_TIMER_B_TSF_SEL(x) \ (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL) & BIT_MASK_PS_TIMER_B_TSF_SEL) #define BIT_SET_PS_TIMER_B_TSF_SEL(x, v) \ (BIT_CLEAR_PS_TIMER_B_TSF_SEL(x) | BIT_PS_TIMER_B_TSF_SEL(v)) #define BIT_PS_TIMER_A_EN BIT(7) #define BIT_SHIFT_PS_TIMER_A_TSF_SEL 0 #define BIT_MASK_PS_TIMER_A_TSF_SEL 0x7 #define BIT_PS_TIMER_A_TSF_SEL(x) \ (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL) << BIT_SHIFT_PS_TIMER_A_TSF_SEL) #define BITS_PS_TIMER_A_TSF_SEL \ (BIT_MASK_PS_TIMER_A_TSF_SEL << BIT_SHIFT_PS_TIMER_A_TSF_SEL) #define BIT_CLEAR_PS_TIMER_A_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_A_TSF_SEL)) #define BIT_GET_PS_TIMER_A_TSF_SEL(x) \ (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL) & BIT_MASK_PS_TIMER_A_TSF_SEL) #define BIT_SET_PS_TIMER_A_TSF_SEL(x, v) \ (BIT_CLEAR_PS_TIMER_A_TSF_SEL(x) | BIT_PS_TIMER_A_TSF_SEL(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_BCN_SPACE_CFG (Offset 0x1510) */ #define BIT_SHIFT_BCN_SPACE 0 #define BIT_MASK_BCN_SPACE 0xffff #define BIT_BCN_SPACE(x) (((x) & BIT_MASK_BCN_SPACE) << BIT_SHIFT_BCN_SPACE) #define BITS_BCN_SPACE (BIT_MASK_BCN_SPACE << BIT_SHIFT_BCN_SPACE) #define BIT_CLEAR_BCN_SPACE(x) ((x) & (~BITS_BCN_SPACE)) #define BIT_GET_BCN_SPACE(x) (((x) >> BIT_SHIFT_BCN_SPACE) & BIT_MASK_BCN_SPACE) #define BIT_SET_BCN_SPACE(x, v) (BIT_CLEAR_BCN_SPACE(x) | BIT_BCN_SPACE(v)) /* 2 REG_EARLY_INT_ADJUST_CFG (Offset 0x1512) */ #define BIT_SHIFT_EARLY_INT_ADJUST 0 #define BIT_MASK_EARLY_INT_ADJUST 0xffff #define BIT_EARLY_INT_ADJUST(x) \ (((x) & BIT_MASK_EARLY_INT_ADJUST) << BIT_SHIFT_EARLY_INT_ADJUST) #define BITS_EARLY_INT_ADJUST \ (BIT_MASK_EARLY_INT_ADJUST << BIT_SHIFT_EARLY_INT_ADJUST) #define BIT_CLEAR_EARLY_INT_ADJUST(x) ((x) & (~BITS_EARLY_INT_ADJUST)) #define BIT_GET_EARLY_INT_ADJUST(x) \ (((x) >> BIT_SHIFT_EARLY_INT_ADJUST) & BIT_MASK_EARLY_INT_ADJUST) #define BIT_SET_EARLY_INT_ADJUST(x, v) \ (BIT_CLEAR_EARLY_INT_ADJUST(x) | BIT_EARLY_INT_ADJUST(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CPUMGQ_TX_TIMER_EARLY (Offset 0x1514) */ #define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY 0 #define BIT_MASK_CPUMGQ_TX_TIMER_EARLY 0xff #define BIT_CPUMGQ_TX_TIMER_EARLY(x) \ (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY) \ << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) #define BITS_CPUMGQ_TX_TIMER_EARLY \ (BIT_MASK_CPUMGQ_TX_TIMER_EARLY << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) #define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY(x) ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY)) #define BIT_GET_CPUMGQ_TX_TIMER_EARLY(x) \ (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) & \ BIT_MASK_CPUMGQ_TX_TIMER_EARLY) #define BIT_SET_CPUMGQ_TX_TIMER_EARLY(x, v) \ (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY(x) | BIT_CPUMGQ_TX_TIMER_EARLY(v)) /* 2 REG_PS_TIMER_A_EARLY (Offset 0x1515) */ #define BIT_SHIFT_PS_TIMER_A_EARLY 0 #define BIT_MASK_PS_TIMER_A_EARLY 0xff #define BIT_PS_TIMER_A_EARLY(x) \ (((x) & BIT_MASK_PS_TIMER_A_EARLY) << BIT_SHIFT_PS_TIMER_A_EARLY) #define BITS_PS_TIMER_A_EARLY \ (BIT_MASK_PS_TIMER_A_EARLY << BIT_SHIFT_PS_TIMER_A_EARLY) #define BIT_CLEAR_PS_TIMER_A_EARLY(x) ((x) & (~BITS_PS_TIMER_A_EARLY)) #define BIT_GET_PS_TIMER_A_EARLY(x) \ (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY) & BIT_MASK_PS_TIMER_A_EARLY) #define BIT_SET_PS_TIMER_A_EARLY(x, v) \ (BIT_CLEAR_PS_TIMER_A_EARLY(x) | BIT_PS_TIMER_A_EARLY(v)) /* 2 REG_PS_TIMER_B_EARLY (Offset 0x1516) */ #define BIT_SHIFT_PS_TIMER_B_EARLY 0 #define BIT_MASK_PS_TIMER_B_EARLY 0xff #define BIT_PS_TIMER_B_EARLY(x) \ (((x) & BIT_MASK_PS_TIMER_B_EARLY) << BIT_SHIFT_PS_TIMER_B_EARLY) #define BITS_PS_TIMER_B_EARLY \ (BIT_MASK_PS_TIMER_B_EARLY << BIT_SHIFT_PS_TIMER_B_EARLY) #define BIT_CLEAR_PS_TIMER_B_EARLY(x) ((x) & (~BITS_PS_TIMER_B_EARLY)) #define BIT_GET_PS_TIMER_B_EARLY(x) \ (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY) & BIT_MASK_PS_TIMER_B_EARLY) #define BIT_SET_PS_TIMER_B_EARLY(x, v) \ (BIT_CLEAR_PS_TIMER_B_EARLY(x) | BIT_PS_TIMER_B_EARLY(v)) /* 2 REG_PS_TIMER_C_EARLY (Offset 0x1517) */ #define BIT_SHIFT_PS_TIMER_C_EARLY 0 #define BIT_MASK_PS_TIMER_C_EARLY 0xff #define BIT_PS_TIMER_C_EARLY(x) \ (((x) & BIT_MASK_PS_TIMER_C_EARLY) << BIT_SHIFT_PS_TIMER_C_EARLY) #define BITS_PS_TIMER_C_EARLY \ (BIT_MASK_PS_TIMER_C_EARLY << BIT_SHIFT_PS_TIMER_C_EARLY) #define BIT_CLEAR_PS_TIMER_C_EARLY(x) ((x) & (~BITS_PS_TIMER_C_EARLY)) #define BIT_GET_PS_TIMER_C_EARLY(x) \ (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY) & BIT_MASK_PS_TIMER_C_EARLY) #define BIT_SET_PS_TIMER_C_EARLY(x, v) \ (BIT_CLEAR_PS_TIMER_C_EARLY(x) | BIT_PS_TIMER_C_EARLY(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_CPUMGQ_PARAMETER (Offset 0x1518) */ #define BIT_STOP_CPUMGQ BIT(16) #define BIT_SHIFT_CPUMGQ_PARAMETER 0 #define BIT_MASK_CPUMGQ_PARAMETER 0xffff #define BIT_CPUMGQ_PARAMETER(x) \ (((x) & BIT_MASK_CPUMGQ_PARAMETER) << BIT_SHIFT_CPUMGQ_PARAMETER) #define BITS_CPUMGQ_PARAMETER \ (BIT_MASK_CPUMGQ_PARAMETER << BIT_SHIFT_CPUMGQ_PARAMETER) #define BIT_CLEAR_CPUMGQ_PARAMETER(x) ((x) & (~BITS_CPUMGQ_PARAMETER)) #define BIT_GET_CPUMGQ_PARAMETER(x) \ (((x) >> BIT_SHIFT_CPUMGQ_PARAMETER) & BIT_MASK_CPUMGQ_PARAMETER) #define BIT_SET_CPUMGQ_PARAMETER(x, v) \ (BIT_CLEAR_CPUMGQ_PARAMETER(x) | BIT_CPUMGQ_PARAMETER(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_SW_TBTT_TSF_INFO (Offset 0x151C) */ #define BIT_SHIFT_SW_TBTT_TSF_INFO 0 #define BIT_MASK_SW_TBTT_TSF_INFO 0xffffffffL #define BIT_SW_TBTT_TSF_INFO(x) \ (((x) & BIT_MASK_SW_TBTT_TSF_INFO) << BIT_SHIFT_SW_TBTT_TSF_INFO) #define BITS_SW_TBTT_TSF_INFO \ (BIT_MASK_SW_TBTT_TSF_INFO << BIT_SHIFT_SW_TBTT_TSF_INFO) #define BIT_CLEAR_SW_TBTT_TSF_INFO(x) ((x) & (~BITS_SW_TBTT_TSF_INFO)) #define BIT_GET_SW_TBTT_TSF_INFO(x) \ (((x) >> BIT_SHIFT_SW_TBTT_TSF_INFO) & BIT_MASK_SW_TBTT_TSF_INFO) #define BIT_SET_SW_TBTT_TSF_INFO(x, v) \ (BIT_CLEAR_SW_TBTT_TSF_INFO(x) | BIT_SW_TBTT_TSF_INFO(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_TSF_SYNC_ADJ (Offset 0x1520) */ #define BIT_SHIFT_R_P0_TSFT_ADJ_VAL 16 #define BIT_MASK_R_P0_TSFT_ADJ_VAL 0xffff #define BIT_R_P0_TSFT_ADJ_VAL(x) \ (((x) & BIT_MASK_R_P0_TSFT_ADJ_VAL) << BIT_SHIFT_R_P0_TSFT_ADJ_VAL) #define BITS_R_P0_TSFT_ADJ_VAL \ (BIT_MASK_R_P0_TSFT_ADJ_VAL << BIT_SHIFT_R_P0_TSFT_ADJ_VAL) #define BIT_CLEAR_R_P0_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_P0_TSFT_ADJ_VAL)) #define BIT_GET_R_P0_TSFT_ADJ_VAL(x) \ (((x) >> BIT_SHIFT_R_P0_TSFT_ADJ_VAL) & BIT_MASK_R_P0_TSFT_ADJ_VAL) #define BIT_SET_R_P0_TSFT_ADJ_VAL(x, v) \ (BIT_CLEAR_R_P0_TSFT_ADJ_VAL(x) | BIT_R_P0_TSFT_ADJ_VAL(v)) #define BIT_R_X_COMP_Y_OVER BIT(8) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_TSF_SYN_CTRL0 (Offset 0x1520) */ #define BIT_TSF_SYNC_COMPARE_POLLING BIT(7) #define BIT_TSF_SYNC_POLLING BIT(6) #define BIT_SHIFT_TSF_SYNC_DUT 3 #define BIT_MASK_TSF_SYNC_DUT 0x7 #define BIT_TSF_SYNC_DUT(x) \ (((x) & BIT_MASK_TSF_SYNC_DUT) << BIT_SHIFT_TSF_SYNC_DUT) #define BITS_TSF_SYNC_DUT (BIT_MASK_TSF_SYNC_DUT << BIT_SHIFT_TSF_SYNC_DUT) #define BIT_CLEAR_TSF_SYNC_DUT(x) ((x) & (~BITS_TSF_SYNC_DUT)) #define BIT_GET_TSF_SYNC_DUT(x) \ (((x) >> BIT_SHIFT_TSF_SYNC_DUT) & BIT_MASK_TSF_SYNC_DUT) #define BIT_SET_TSF_SYNC_DUT(x, v) \ (BIT_CLEAR_TSF_SYNC_DUT(x) | BIT_TSF_SYNC_DUT(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_TSF_SYNC_ADJ (Offset 0x1520) */ #define BIT_SHIFT_R_X_SYNC_SEL 3 #define BIT_MASK_R_X_SYNC_SEL 0x7 #define BIT_R_X_SYNC_SEL(x) \ (((x) & BIT_MASK_R_X_SYNC_SEL) << BIT_SHIFT_R_X_SYNC_SEL) #define BITS_R_X_SYNC_SEL (BIT_MASK_R_X_SYNC_SEL << BIT_SHIFT_R_X_SYNC_SEL) #define BIT_CLEAR_R_X_SYNC_SEL(x) ((x) & (~BITS_R_X_SYNC_SEL)) #define BIT_GET_R_X_SYNC_SEL(x) \ (((x) >> BIT_SHIFT_R_X_SYNC_SEL) & BIT_MASK_R_X_SYNC_SEL) #define BIT_SET_R_X_SYNC_SEL(x, v) \ (BIT_CLEAR_R_X_SYNC_SEL(x) | BIT_R_X_SYNC_SEL(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_TSF_SYN_CTRL0 (Offset 0x1520) */ #define BIT_SHIFT_TSF_SYNC_SOURCE 0 #define BIT_MASK_TSF_SYNC_SOURCE 0x7 #define BIT_TSF_SYNC_SOURCE(x) \ (((x) & BIT_MASK_TSF_SYNC_SOURCE) << BIT_SHIFT_TSF_SYNC_SOURCE) #define BITS_TSF_SYNC_SOURCE \ (BIT_MASK_TSF_SYNC_SOURCE << BIT_SHIFT_TSF_SYNC_SOURCE) #define BIT_CLEAR_TSF_SYNC_SOURCE(x) ((x) & (~BITS_TSF_SYNC_SOURCE)) #define BIT_GET_TSF_SYNC_SOURCE(x) \ (((x) >> BIT_SHIFT_TSF_SYNC_SOURCE) & BIT_MASK_TSF_SYNC_SOURCE) #define BIT_SET_TSF_SYNC_SOURCE(x, v) \ (BIT_CLEAR_TSF_SYNC_SOURCE(x) | BIT_TSF_SYNC_SOURCE(v)) #define BIT_TSF_SYNC_SIGNAL BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TSFTR_LOW (Offset 0x1520) */ #define BIT_SHIFT_TSF_TIMER_LOW 0 #define BIT_MASK_TSF_TIMER_LOW 0xffffffffL #define BIT_TSF_TIMER_LOW(x) \ (((x) & BIT_MASK_TSF_TIMER_LOW) << BIT_SHIFT_TSF_TIMER_LOW) #define BITS_TSF_TIMER_LOW (BIT_MASK_TSF_TIMER_LOW << BIT_SHIFT_TSF_TIMER_LOW) #define BIT_CLEAR_TSF_TIMER_LOW(x) ((x) & (~BITS_TSF_TIMER_LOW)) #define BIT_GET_TSF_TIMER_LOW(x) \ (((x) >> BIT_SHIFT_TSF_TIMER_LOW) & BIT_MASK_TSF_TIMER_LOW) #define BIT_SET_TSF_TIMER_LOW(x, v) \ (BIT_CLEAR_TSF_TIMER_LOW(x) | BIT_TSF_TIMER_LOW(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_TSF_SYNC_ADJ (Offset 0x1520) */ #define BIT_SHIFT_R_SYNC_Y_SEL 0 #define BIT_MASK_R_SYNC_Y_SEL 0x7 #define BIT_R_SYNC_Y_SEL(x) \ (((x) & BIT_MASK_R_SYNC_Y_SEL) << BIT_SHIFT_R_SYNC_Y_SEL) #define BITS_R_SYNC_Y_SEL (BIT_MASK_R_SYNC_Y_SEL << BIT_SHIFT_R_SYNC_Y_SEL) #define BIT_CLEAR_R_SYNC_Y_SEL(x) ((x) & (~BITS_R_SYNC_Y_SEL)) #define BIT_GET_R_SYNC_Y_SEL(x) \ (((x) >> BIT_SHIFT_R_SYNC_Y_SEL) & BIT_MASK_R_SYNC_Y_SEL) #define BIT_SET_R_SYNC_Y_SEL(x, v) \ (BIT_CLEAR_R_SYNC_Y_SEL(x) | BIT_R_SYNC_Y_SEL(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_TSF_SYN_OFFSET0 (Offset 0x1522) */ #define BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0 0 #define BIT_MASK_TSF_SYNC_INTERVAL_PORT0 0xffff #define BIT_TSF_SYNC_INTERVAL_PORT0(x) \ (((x) & BIT_MASK_TSF_SYNC_INTERVAL_PORT0) \ << BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0) #define BITS_TSF_SYNC_INTERVAL_PORT0 \ (BIT_MASK_TSF_SYNC_INTERVAL_PORT0 << BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0) #define BIT_CLEAR_TSF_SYNC_INTERVAL_PORT0(x) \ ((x) & (~BITS_TSF_SYNC_INTERVAL_PORT0)) #define BIT_GET_TSF_SYNC_INTERVAL_PORT0(x) \ (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0) & \ BIT_MASK_TSF_SYNC_INTERVAL_PORT0) #define BIT_SET_TSF_SYNC_INTERVAL_PORT0(x, v) \ (BIT_CLEAR_TSF_SYNC_INTERVAL_PORT0(x) | BIT_TSF_SYNC_INTERVAL_PORT0(v)) /* 2 REG_TSF_SYN_OFFSET1 (Offset 0x1524) */ #define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1 16 #define BIT_MASK_TSF_SYNC_INTERVAL_CLI1 0xffff #define BIT_TSF_SYNC_INTERVAL_CLI1(x) \ (((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI1) \ << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1) #define BITS_TSF_SYNC_INTERVAL_CLI1 \ (BIT_MASK_TSF_SYNC_INTERVAL_CLI1 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1) #define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI1(x) \ ((x) & (~BITS_TSF_SYNC_INTERVAL_CLI1)) #define BIT_GET_TSF_SYNC_INTERVAL_CLI1(x) \ (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1) & \ BIT_MASK_TSF_SYNC_INTERVAL_CLI1) #define BIT_SET_TSF_SYNC_INTERVAL_CLI1(x, v) \ (BIT_CLEAR_TSF_SYNC_INTERVAL_CLI1(x) | BIT_TSF_SYNC_INTERVAL_CLI1(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_TSF_ADJ_VLAUE (Offset 0x1524) */ #define BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL 16 #define BIT_MASK_R_CLI1_TSFT_ADJ_VAL 0xffff #define BIT_R_CLI1_TSFT_ADJ_VAL(x) \ (((x) & BIT_MASK_R_CLI1_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL) #define BITS_R_CLI1_TSFT_ADJ_VAL \ (BIT_MASK_R_CLI1_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL) #define BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI1_TSFT_ADJ_VAL)) #define BIT_GET_R_CLI1_TSFT_ADJ_VAL(x) \ (((x) >> BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL) & BIT_MASK_R_CLI1_TSFT_ADJ_VAL) #define BIT_SET_R_CLI1_TSFT_ADJ_VAL(x, v) \ (BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL(x) | BIT_R_CLI1_TSFT_ADJ_VAL(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_TSF_SYN_OFFSET1 (Offset 0x1524) */ #define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0 0 #define BIT_MASK_TSF_SYNC_INTERVAL_CLI0 0xffff #define BIT_TSF_SYNC_INTERVAL_CLI0(x) \ (((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI0) \ << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0) #define BITS_TSF_SYNC_INTERVAL_CLI0 \ (BIT_MASK_TSF_SYNC_INTERVAL_CLI0 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0) #define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI0(x) \ ((x) & (~BITS_TSF_SYNC_INTERVAL_CLI0)) #define BIT_GET_TSF_SYNC_INTERVAL_CLI0(x) \ (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0) & \ BIT_MASK_TSF_SYNC_INTERVAL_CLI0) #define BIT_SET_TSF_SYNC_INTERVAL_CLI0(x, v) \ (BIT_CLEAR_TSF_SYNC_INTERVAL_CLI0(x) | BIT_TSF_SYNC_INTERVAL_CLI0(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_TSFTR_HIGH (Offset 0x1524) */ #define BIT_SHIFT_TSF_TIMER_HIGH 0 #define BIT_MASK_TSF_TIMER_HIGH 0xffffffffL #define BIT_TSF_TIMER_HIGH(x) \ (((x) & BIT_MASK_TSF_TIMER_HIGH) << BIT_SHIFT_TSF_TIMER_HIGH) #define BITS_TSF_TIMER_HIGH \ (BIT_MASK_TSF_TIMER_HIGH << BIT_SHIFT_TSF_TIMER_HIGH) #define BIT_CLEAR_TSF_TIMER_HIGH(x) ((x) & (~BITS_TSF_TIMER_HIGH)) #define BIT_GET_TSF_TIMER_HIGH(x) \ (((x) >> BIT_SHIFT_TSF_TIMER_HIGH) & BIT_MASK_TSF_TIMER_HIGH) #define BIT_SET_TSF_TIMER_HIGH(x, v) \ (BIT_CLEAR_TSF_TIMER_HIGH(x) | BIT_TSF_TIMER_HIGH(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_TSF_ADJ_VLAUE (Offset 0x1524) */ #define BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL 0 #define BIT_MASK_R_CLI0_TSFT_ADJ_VAL 0xffff #define BIT_R_CLI0_TSFT_ADJ_VAL(x) \ (((x) & BIT_MASK_R_CLI0_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL) #define BITS_R_CLI0_TSFT_ADJ_VAL \ (BIT_MASK_R_CLI0_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL) #define BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI0_TSFT_ADJ_VAL)) #define BIT_GET_R_CLI0_TSFT_ADJ_VAL(x) \ (((x) >> BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL) & BIT_MASK_R_CLI0_TSFT_ADJ_VAL) #define BIT_SET_R_CLI0_TSFT_ADJ_VAL(x, v) \ (BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL(x) | BIT_R_CLI0_TSFT_ADJ_VAL(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_TSF_SYN_OFFSET2 (Offset 0x1528) */ #define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3 16 #define BIT_MASK_TSF_SYNC_INTERVAL_CLI3 0xffff #define BIT_TSF_SYNC_INTERVAL_CLI3(x) \ (((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI3) \ << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3) #define BITS_TSF_SYNC_INTERVAL_CLI3 \ (BIT_MASK_TSF_SYNC_INTERVAL_CLI3 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3) #define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI3(x) \ ((x) & (~BITS_TSF_SYNC_INTERVAL_CLI3)) #define BIT_GET_TSF_SYNC_INTERVAL_CLI3(x) \ (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3) & \ BIT_MASK_TSF_SYNC_INTERVAL_CLI3) #define BIT_SET_TSF_SYNC_INTERVAL_CLI3(x, v) \ (BIT_CLEAR_TSF_SYNC_INTERVAL_CLI3(x) | BIT_TSF_SYNC_INTERVAL_CLI3(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_TSF_ADJ_VLAUE_2 (Offset 0x1528) */ #define BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL 16 #define BIT_MASK_R_CLI3_TSFT_ADJ_VAL 0xffff #define BIT_R_CLI3_TSFT_ADJ_VAL(x) \ (((x) & BIT_MASK_R_CLI3_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL) #define BITS_R_CLI3_TSFT_ADJ_VAL \ (BIT_MASK_R_CLI3_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL) #define BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI3_TSFT_ADJ_VAL)) #define BIT_GET_R_CLI3_TSFT_ADJ_VAL(x) \ (((x) >> BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL) & BIT_MASK_R_CLI3_TSFT_ADJ_VAL) #define BIT_SET_R_CLI3_TSFT_ADJ_VAL(x, v) \ (BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL(x) | BIT_R_CLI3_TSFT_ADJ_VAL(v)) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_TSF_SYN_OFFSET2 (Offset 0x1528) */ #define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2 0 #define BIT_MASK_TSF_SYNC_INTERVAL_CLI2 0xffff #define BIT_TSF_SYNC_INTERVAL_CLI2(x) \ (((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI2) \ << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2) #define BITS_TSF_SYNC_INTERVAL_CLI2 \ (BIT_MASK_TSF_SYNC_INTERVAL_CLI2 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2) #define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI2(x) \ ((x) & (~BITS_TSF_SYNC_INTERVAL_CLI2)) #define BIT_GET_TSF_SYNC_INTERVAL_CLI2(x) \ (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2) & \ BIT_MASK_TSF_SYNC_INTERVAL_CLI2) #define BIT_SET_TSF_SYNC_INTERVAL_CLI2(x, v) \ (BIT_CLEAR_TSF_SYNC_INTERVAL_CLI2(x) | BIT_TSF_SYNC_INTERVAL_CLI2(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_BCN_ERR_CNT_MAC (Offset 0x1528) */ #define BIT_SHIFT_BCN_ERR_CNT_MAC 0 #define BIT_MASK_BCN_ERR_CNT_MAC 0xff #define BIT_BCN_ERR_CNT_MAC(x) \ (((x) & BIT_MASK_BCN_ERR_CNT_MAC) << BIT_SHIFT_BCN_ERR_CNT_MAC) #define BITS_BCN_ERR_CNT_MAC \ (BIT_MASK_BCN_ERR_CNT_MAC << BIT_SHIFT_BCN_ERR_CNT_MAC) #define BIT_CLEAR_BCN_ERR_CNT_MAC(x) ((x) & (~BITS_BCN_ERR_CNT_MAC)) #define BIT_GET_BCN_ERR_CNT_MAC(x) \ (((x) >> BIT_SHIFT_BCN_ERR_CNT_MAC) & BIT_MASK_BCN_ERR_CNT_MAC) #define BIT_SET_BCN_ERR_CNT_MAC(x, v) \ (BIT_CLEAR_BCN_ERR_CNT_MAC(x) | BIT_BCN_ERR_CNT_MAC(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_TSF_ADJ_VLAUE_2 (Offset 0x1528) */ #define BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL 0 #define BIT_MASK_R_CLI2_TSFT_ADJ_VAL 0xffff #define BIT_R_CLI2_TSFT_ADJ_VAL(x) \ (((x) & BIT_MASK_R_CLI2_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL) #define BITS_R_CLI2_TSFT_ADJ_VAL \ (BIT_MASK_R_CLI2_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL) #define BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI2_TSFT_ADJ_VAL)) #define BIT_GET_R_CLI2_TSFT_ADJ_VAL(x) \ (((x) >> BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL) & BIT_MASK_R_CLI2_TSFT_ADJ_VAL) #define BIT_SET_R_CLI2_TSFT_ADJ_VAL(x, v) \ (BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL(x) | BIT_R_CLI2_TSFT_ADJ_VAL(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_BCN_ERR_CNT_EDCCA (Offset 0x1529) */ #define BIT_SHIFT_BCN_ERR_CNT_EDCCA 0 #define BIT_MASK_BCN_ERR_CNT_EDCCA 0xff #define BIT_BCN_ERR_CNT_EDCCA(x) \ (((x) & BIT_MASK_BCN_ERR_CNT_EDCCA) << BIT_SHIFT_BCN_ERR_CNT_EDCCA) #define BITS_BCN_ERR_CNT_EDCCA \ (BIT_MASK_BCN_ERR_CNT_EDCCA << BIT_SHIFT_BCN_ERR_CNT_EDCCA) #define BIT_CLEAR_BCN_ERR_CNT_EDCCA(x) ((x) & (~BITS_BCN_ERR_CNT_EDCCA)) #define BIT_GET_BCN_ERR_CNT_EDCCA(x) \ (((x) >> BIT_SHIFT_BCN_ERR_CNT_EDCCA) & BIT_MASK_BCN_ERR_CNT_EDCCA) #define BIT_SET_BCN_ERR_CNT_EDCCA(x, v) \ (BIT_CLEAR_BCN_ERR_CNT_EDCCA(x) | BIT_BCN_ERR_CNT_EDCCA(v)) /* 2 REG_BCN_ERR_CNT_CCA (Offset 0x152A) */ #define BIT_SHIFT_BCN_ERR_CNT_CCA 0 #define BIT_MASK_BCN_ERR_CNT_CCA 0xff #define BIT_BCN_ERR_CNT_CCA(x) \ (((x) & BIT_MASK_BCN_ERR_CNT_CCA) << BIT_SHIFT_BCN_ERR_CNT_CCA) #define BITS_BCN_ERR_CNT_CCA \ (BIT_MASK_BCN_ERR_CNT_CCA << BIT_SHIFT_BCN_ERR_CNT_CCA) #define BIT_CLEAR_BCN_ERR_CNT_CCA(x) ((x) & (~BITS_BCN_ERR_CNT_CCA)) #define BIT_GET_BCN_ERR_CNT_CCA(x) \ (((x) >> BIT_SHIFT_BCN_ERR_CNT_CCA) & BIT_MASK_BCN_ERR_CNT_CCA) #define BIT_SET_BCN_ERR_CNT_CCA(x, v) \ (BIT_CLEAR_BCN_ERR_CNT_CCA(x) | BIT_BCN_ERR_CNT_CCA(v)) /* 2 REG_BCN_ERR_CNT_INVALID (Offset 0x152B) */ #define BIT_SHIFT_BCN_ERR_CNT_INVALID 0 #define BIT_MASK_BCN_ERR_CNT_INVALID 0xff #define BIT_BCN_ERR_CNT_INVALID(x) \ (((x) & BIT_MASK_BCN_ERR_CNT_INVALID) << BIT_SHIFT_BCN_ERR_CNT_INVALID) #define BITS_BCN_ERR_CNT_INVALID \ (BIT_MASK_BCN_ERR_CNT_INVALID << BIT_SHIFT_BCN_ERR_CNT_INVALID) #define BIT_CLEAR_BCN_ERR_CNT_INVALID(x) ((x) & (~BITS_BCN_ERR_CNT_INVALID)) #define BIT_GET_BCN_ERR_CNT_INVALID(x) \ (((x) >> BIT_SHIFT_BCN_ERR_CNT_INVALID) & BIT_MASK_BCN_ERR_CNT_INVALID) #define BIT_SET_BCN_ERR_CNT_INVALID(x, v) \ (BIT_CLEAR_BCN_ERR_CNT_INVALID(x) | BIT_BCN_ERR_CNT_INVALID(v)) /* 2 REG_BCN_ERR_CNT_OTHERS (Offset 0x152C) */ #define BIT_SHIFT_BCN_ERR_CNT_OTHERS 0 #define BIT_MASK_BCN_ERR_CNT_OTHERS 0xff #define BIT_BCN_ERR_CNT_OTHERS(x) \ (((x) & BIT_MASK_BCN_ERR_CNT_OTHERS) << BIT_SHIFT_BCN_ERR_CNT_OTHERS) #define BITS_BCN_ERR_CNT_OTHERS \ (BIT_MASK_BCN_ERR_CNT_OTHERS << BIT_SHIFT_BCN_ERR_CNT_OTHERS) #define BIT_CLEAR_BCN_ERR_CNT_OTHERS(x) ((x) & (~BITS_BCN_ERR_CNT_OTHERS)) #define BIT_GET_BCN_ERR_CNT_OTHERS(x) \ (((x) >> BIT_SHIFT_BCN_ERR_CNT_OTHERS) & BIT_MASK_BCN_ERR_CNT_OTHERS) #define BIT_SET_BCN_ERR_CNT_OTHERS(x, v) \ (BIT_CLEAR_BCN_ERR_CNT_OTHERS(x) | BIT_BCN_ERR_CNT_OTHERS(v)) /* 2 REG_RX_BCN_TIMER (Offset 0x152D) */ #define BIT_SHIFT_RX_BCN_TIMER 0 #define BIT_MASK_RX_BCN_TIMER 0xffff #define BIT_RX_BCN_TIMER(x) \ (((x) & BIT_MASK_RX_BCN_TIMER) << BIT_SHIFT_RX_BCN_TIMER) #define BITS_RX_BCN_TIMER (BIT_MASK_RX_BCN_TIMER << BIT_SHIFT_RX_BCN_TIMER) #define BIT_CLEAR_RX_BCN_TIMER(x) ((x) & (~BITS_RX_BCN_TIMER)) #define BIT_GET_RX_BCN_TIMER(x) \ (((x) >> BIT_SHIFT_RX_BCN_TIMER) & BIT_MASK_RX_BCN_TIMER) #define BIT_SET_RX_BCN_TIMER(x, v) \ (BIT_CLEAR_RX_BCN_TIMER(x) | BIT_RX_BCN_TIMER(v)) /* 2 REG_SUB_BCN_SPACE (Offset 0x1534) */ #define BIT_SHIFT_SUB_BCN_SPACE_V2 0 #define BIT_MASK_SUB_BCN_SPACE_V2 0xff #define BIT_SUB_BCN_SPACE_V2(x) \ (((x) & BIT_MASK_SUB_BCN_SPACE_V2) << BIT_SHIFT_SUB_BCN_SPACE_V2) #define BITS_SUB_BCN_SPACE_V2 \ (BIT_MASK_SUB_BCN_SPACE_V2 << BIT_SHIFT_SUB_BCN_SPACE_V2) #define BIT_CLEAR_SUB_BCN_SPACE_V2(x) ((x) & (~BITS_SUB_BCN_SPACE_V2)) #define BIT_GET_SUB_BCN_SPACE_V2(x) \ (((x) >> BIT_SHIFT_SUB_BCN_SPACE_V2) & BIT_MASK_SUB_BCN_SPACE_V2) #define BIT_SET_SUB_BCN_SPACE_V2(x, v) \ (BIT_CLEAR_SUB_BCN_SPACE_V2(x) | BIT_SUB_BCN_SPACE_V2(v)) /* 2 REG_MBID_NUM_V1 (Offset 0x1535) */ #define BIT_SHIFT_BCN_ERR_PORT_SEL 4 #define BIT_MASK_BCN_ERR_PORT_SEL 0xf #define BIT_BCN_ERR_PORT_SEL(x) \ (((x) & BIT_MASK_BCN_ERR_PORT_SEL) << BIT_SHIFT_BCN_ERR_PORT_SEL) #define BITS_BCN_ERR_PORT_SEL \ (BIT_MASK_BCN_ERR_PORT_SEL << BIT_SHIFT_BCN_ERR_PORT_SEL) #define BIT_CLEAR_BCN_ERR_PORT_SEL(x) ((x) & (~BITS_BCN_ERR_PORT_SEL)) #define BIT_GET_BCN_ERR_PORT_SEL(x) \ (((x) >> BIT_SHIFT_BCN_ERR_PORT_SEL) & BIT_MASK_BCN_ERR_PORT_SEL) #define BIT_SET_BCN_ERR_PORT_SEL(x, v) \ (BIT_CLEAR_BCN_ERR_PORT_SEL(x) | BIT_BCN_ERR_PORT_SEL(v)) #define BIT_SHIFT_MBID_BCN_NUM_V1 0 #define BIT_MASK_MBID_BCN_NUM_V1 0xf #define BIT_MBID_BCN_NUM_V1(x) \ (((x) & BIT_MASK_MBID_BCN_NUM_V1) << BIT_SHIFT_MBID_BCN_NUM_V1) #define BITS_MBID_BCN_NUM_V1 \ (BIT_MASK_MBID_BCN_NUM_V1 << BIT_SHIFT_MBID_BCN_NUM_V1) #define BIT_CLEAR_MBID_BCN_NUM_V1(x) ((x) & (~BITS_MBID_BCN_NUM_V1)) #define BIT_GET_MBID_BCN_NUM_V1(x) \ (((x) >> BIT_SHIFT_MBID_BCN_NUM_V1) & BIT_MASK_MBID_BCN_NUM_V1) #define BIT_SET_MBID_BCN_NUM_V1(x, v) \ (BIT_CLEAR_MBID_BCN_NUM_V1(x) | BIT_MBID_BCN_NUM_V1(v)) /* 2 REG_MBSSID_CTRL_V1 (Offset 0x1536) */ #define BIT_MBID_BCNQ15_EN BIT(15) #define BIT_MBID_BCNQ14_EN BIT(14) #define BIT_MBID_BCNQ13_EN BIT(13) #define BIT_MBID_BCNQ12_EN BIT(12) #define BIT_MBID_BCNQ11_EN BIT(11) #define BIT_MBID_BCNQ10_EN BIT(10) #define BIT_MBID_BCNQ9_EN BIT(9) #define BIT_MBID_BCNQ8_EN BIT(8) /* 2 REG_BW_CFG (Offset 0x1539) */ #define BIT_SLEEP_32K_EN BIT(3) #define BIT_DIS_MARK_TSF_US_V1 BIT(2) /* 2 REG_ATIMWND_CFG (Offset 0x153A) */ #define BIT_SHIFT_ATIMWND_V1 0 #define BIT_MASK_ATIMWND_V1 0xff #define BIT_ATIMWND_V1(x) (((x) & BIT_MASK_ATIMWND_V1) << BIT_SHIFT_ATIMWND_V1) #define BITS_ATIMWND_V1 (BIT_MASK_ATIMWND_V1 << BIT_SHIFT_ATIMWND_V1) #define BIT_CLEAR_ATIMWND_V1(x) ((x) & (~BITS_ATIMWND_V1)) #define BIT_GET_ATIMWND_V1(x) \ (((x) >> BIT_SHIFT_ATIMWND_V1) & BIT_MASK_ATIMWND_V1) #define BIT_SET_ATIMWND_V1(x, v) (BIT_CLEAR_ATIMWND_V1(x) | BIT_ATIMWND_V1(v)) /* 2 REG_DTIM_COUNTER_CFG (Offset 0x153B) */ #define BIT_SHIFT_DTIM_COUNT 0 #define BIT_MASK_DTIM_COUNT 0xff #define BIT_DTIM_COUNT(x) (((x) & BIT_MASK_DTIM_COUNT) << BIT_SHIFT_DTIM_COUNT) #define BITS_DTIM_COUNT (BIT_MASK_DTIM_COUNT << BIT_SHIFT_DTIM_COUNT) #define BIT_CLEAR_DTIM_COUNT(x) ((x) & (~BITS_DTIM_COUNT)) #define BIT_GET_DTIM_COUNT(x) \ (((x) >> BIT_SHIFT_DTIM_COUNT) & BIT_MASK_DTIM_COUNT) #define BIT_SET_DTIM_COUNT(x, v) (BIT_CLEAR_DTIM_COUNT(x) | BIT_DTIM_COUNT(v)) /* 2 REG_ATIM_DTIM_CTRL_SEL (Offset 0x153C) */ #define BIT_DTIM_BYPASS_V1 BIT(7) #define BIT_SHIFT_ATIM_DTIM_SEL 0 #define BIT_MASK_ATIM_DTIM_SEL 0x1f #define BIT_ATIM_DTIM_SEL(x) \ (((x) & BIT_MASK_ATIM_DTIM_SEL) << BIT_SHIFT_ATIM_DTIM_SEL) #define BITS_ATIM_DTIM_SEL (BIT_MASK_ATIM_DTIM_SEL << BIT_SHIFT_ATIM_DTIM_SEL) #define BIT_CLEAR_ATIM_DTIM_SEL(x) ((x) & (~BITS_ATIM_DTIM_SEL)) #define BIT_GET_ATIM_DTIM_SEL(x) \ (((x) >> BIT_SHIFT_ATIM_DTIM_SEL) & BIT_MASK_ATIM_DTIM_SEL) #define BIT_SET_ATIM_DTIM_SEL(x, v) \ (BIT_CLEAR_ATIM_DTIM_SEL(x) | BIT_ATIM_DTIM_SEL(v)) /* 2 REG_DIS_ATIM_V1 (Offset 0x1540) */ #define BIT_DIS_ATIM_P4 BIT(19) #define BIT_DIS_ATIM_P3 BIT(18) #define BIT_DIS_ATIM_P2 BIT(17) #define BIT_DIS_ATIM_P1 BIT(16) #define BIT_DIS_ATIM_VAP15 BIT(15) #define BIT_DIS_ATIM_VAP14 BIT(14) #define BIT_DIS_ATIM_VAP13 BIT(13) #define BIT_DIS_ATIM_VAP12 BIT(12) #define BIT_DIS_ATIM_VAP11 BIT(11) #define BIT_DIS_ATIM_VAP10 BIT(10) #define BIT_DIS_ATIM_VAP9 BIT(9) #define BIT_DIS_ATIM_VAP8 BIT(8) #define BIT_DIS_ATIM_ROOT_P0 BIT(0) /* 2 REG_HIQ_NO_LMT_EN_V1 (Offset 0x1544) */ #define BIT_HIQ_NO_LMT_EN_P4 BIT(19) #define BIT_HIQ_NO_LMT_EN_P3 BIT(18) #define BIT_HIQ_NO_LMT_EN_P2 BIT(17) #define BIT_HIQ_NO_LMT_EN_P1 BIT(16) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_HIQ_NO_LMT_EN_V1 (Offset 0x1544) */ #define BIT_HIQ_NO_LMT_EN_VAP15 BIT(15) #define BIT_HIQ_NO_LMT_EN_VAP14 BIT(14) #define BIT_HIQ_NO_LMT_EN_VAP13 BIT(13) #define BIT_HIQ_NO_LMT_EN_VAP12 BIT(12) #define BIT_HIQ_NO_LMT_EN_VAP11 BIT(11) #define BIT_HIQ_NO_LMT_EN_VAP10 BIT(10) #define BIT_HIQ_NO_LMT_EN_VAP9 BIT(9) #define BIT_HIQ_NO_LMT_EN_VAP8 BIT(8) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_HIQ_NO_LMT_EN_V1 (Offset 0x1544) */ #define BIT_HIQ_NO_LMT_EN_ROOT_P0 BIT(0) /* 2 REG_P2PPS_CTRL_V1 (Offset 0x1548) */ #define BIT_P2P_PWR_RST1_V2 BIT(15) #define BIT_P2P_PWR_RST0_V2 BIT(14) #define BIT_EN_TSFBIT32_RST_P2P_V1 BIT(13) #define BIT_SHIFT_NOA_UNIT0_SEL_V1 8 #define BIT_MASK_NOA_UNIT0_SEL_V1 0x7 #define BIT_NOA_UNIT0_SEL_V1(x) \ (((x) & BIT_MASK_NOA_UNIT0_SEL_V1) << BIT_SHIFT_NOA_UNIT0_SEL_V1) #define BITS_NOA_UNIT0_SEL_V1 \ (BIT_MASK_NOA_UNIT0_SEL_V1 << BIT_SHIFT_NOA_UNIT0_SEL_V1) #define BIT_CLEAR_NOA_UNIT0_SEL_V1(x) ((x) & (~BITS_NOA_UNIT0_SEL_V1)) #define BIT_GET_NOA_UNIT0_SEL_V1(x) \ (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_V1) & BIT_MASK_NOA_UNIT0_SEL_V1) #define BIT_SET_NOA_UNIT0_SEL_V1(x, v) \ (BIT_CLEAR_NOA_UNIT0_SEL_V1(x) | BIT_NOA_UNIT0_SEL_V1(v)) #define BIT_P2P_CTW_ALLSTASLEEP_V1 BIT(7) #define BIT_P2P_OFF_DISTX_EN_V1 BIT(6) #define BIT_PWR_MGT_EN_V1 BIT(5) #define BIT_P2P_NOA1_EN_V1 BIT(2) #define BIT_P2P_NOA0_EN_V1 BIT(1) /* 2 REG_P2PPS1_CTRL_V1 (Offset 0x154C) */ #define BIT_P2P1_PWR_RST1_V2 BIT(15) #define BIT_P2P1_PWR_RST0_V2 BIT(14) #define BIT_EN_TSFBIT32_RST_P2P1_V1 BIT(13) #define BIT_SHIFT_NOA_UNIT1_SEL_V1 8 #define BIT_MASK_NOA_UNIT1_SEL_V1 0x7 #define BIT_NOA_UNIT1_SEL_V1(x) \ (((x) & BIT_MASK_NOA_UNIT1_SEL_V1) << BIT_SHIFT_NOA_UNIT1_SEL_V1) #define BITS_NOA_UNIT1_SEL_V1 \ (BIT_MASK_NOA_UNIT1_SEL_V1 << BIT_SHIFT_NOA_UNIT1_SEL_V1) #define BIT_CLEAR_NOA_UNIT1_SEL_V1(x) ((x) & (~BITS_NOA_UNIT1_SEL_V1)) #define BIT_GET_NOA_UNIT1_SEL_V1(x) \ (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_V1) & BIT_MASK_NOA_UNIT1_SEL_V1) #define BIT_SET_NOA_UNIT1_SEL_V1(x, v) \ (BIT_CLEAR_NOA_UNIT1_SEL_V1(x) | BIT_NOA_UNIT1_SEL_V1(v)) #define BIT_P2P1_CTW_ALLSTASLEEP_V1 BIT(7) #define BIT_P2P1_PWR_MGT_EN_V1 BIT(5) #define BIT_P2P1_NOA1_EN_V1 BIT(2) #define BIT_P2P1_NOA0_EN_V1 BIT(1) /* 2 REG_P2PPS1_SPEC_STATE_V1 (Offset 0x154E) */ #define BIT_P2P1_SPEC_POWER_STATEP BIT(7) #define BIT_P2P1_SPEC_BEACON_AREA_ON BIT(5) /* 2 REG_P2PPS2_CTRL_V1 (Offset 0x1550) */ #define BIT_P2P2_PWR_RST1_V2 BIT(15) #define BIT_P2P2_PWR_RST0_V2 BIT(14) #define BIT_EN_TSFBIT32_RST_P2P2_V1 BIT(13) #define BIT_SHIFT_NOA_UNIT2_SEL_V1 8 #define BIT_MASK_NOA_UNIT2_SEL_V1 0x7 #define BIT_NOA_UNIT2_SEL_V1(x) \ (((x) & BIT_MASK_NOA_UNIT2_SEL_V1) << BIT_SHIFT_NOA_UNIT2_SEL_V1) #define BITS_NOA_UNIT2_SEL_V1 \ (BIT_MASK_NOA_UNIT2_SEL_V1 << BIT_SHIFT_NOA_UNIT2_SEL_V1) #define BIT_CLEAR_NOA_UNIT2_SEL_V1(x) ((x) & (~BITS_NOA_UNIT2_SEL_V1)) #define BIT_GET_NOA_UNIT2_SEL_V1(x) \ (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_V1) & BIT_MASK_NOA_UNIT2_SEL_V1) #define BIT_SET_NOA_UNIT2_SEL_V1(x, v) \ (BIT_CLEAR_NOA_UNIT2_SEL_V1(x) | BIT_NOA_UNIT2_SEL_V1(v)) #define BIT_P2P2_CTW_ALLSTASLEEP_V1 BIT(7) #define BIT_P2P2_OFF_DISTX_EN_V1 BIT(6) #define BIT_P2P2_PWR_MGT_EN_V1 BIT(5) #define BIT_P2P2_NOA1_EN_V1 BIT(2) #define BIT_P2P2_NOA0_EN_V1 BIT(1) /* 2 REG_P2PPS2_SPEC_STATE_V1 (Offset 0x1552) */ #define BIT_P2P2_SPEC_POWER_STATEP BIT(7) #define BIT_P2P2_SPEC_BEACON_AREA_ON BIT(5) /* 2 REG_CHG_POWER_BCN_AREA (Offset 0x1556) */ #define BIT_CHG_POWER_BCN_AREA BIT(0) /* 2 REG_NOA_SEL (Offset 0x1557) */ #define BIT_SHIFT_NOA_SEL_V1 0 #define BIT_MASK_NOA_SEL_V1 0x7 #define BIT_NOA_SEL_V1(x) (((x) & BIT_MASK_NOA_SEL_V1) << BIT_SHIFT_NOA_SEL_V1) #define BITS_NOA_SEL_V1 (BIT_MASK_NOA_SEL_V1 << BIT_SHIFT_NOA_SEL_V1) #define BIT_CLEAR_NOA_SEL_V1(x) ((x) & (~BITS_NOA_SEL_V1)) #define BIT_GET_NOA_SEL_V1(x) \ (((x) >> BIT_SHIFT_NOA_SEL_V1) & BIT_MASK_NOA_SEL_V1) #define BIT_SET_NOA_SEL_V1(x, v) (BIT_CLEAR_NOA_SEL_V1(x) | BIT_NOA_SEL_V1(v)) /* 2 REG_NOA_PARAM_3_V1 (Offset 0x1564) */ #define BIT_SHIFT_NOA_COUNT_V2 0 #define BIT_MASK_NOA_COUNT_V2 0xffffffffL #define BIT_NOA_COUNT_V2(x) \ (((x) & BIT_MASK_NOA_COUNT_V2) << BIT_SHIFT_NOA_COUNT_V2) #define BITS_NOA_COUNT_V2 (BIT_MASK_NOA_COUNT_V2 << BIT_SHIFT_NOA_COUNT_V2) #define BIT_CLEAR_NOA_COUNT_V2(x) ((x) & (~BITS_NOA_COUNT_V2)) #define BIT_GET_NOA_COUNT_V2(x) \ (((x) >> BIT_SHIFT_NOA_COUNT_V2) & BIT_MASK_NOA_COUNT_V2) #define BIT_SET_NOA_COUNT_V2(x, v) \ (BIT_CLEAR_NOA_COUNT_V2(x) | BIT_NOA_COUNT_V2(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_P2PPS_HW_AUTO_PAUSE_CTRL (Offset 0x156C) */ #define BIT_P2PPS_NOA_STOP_TX_HANG BIT(31) #define BIT_P2PPS_MACID_PAUSE_EN BIT(11) #define BIT_P2PPS__MGQ_PAUSE BIT(10) #define BIT_P2PPS__HIQ_PAUSE BIT(9) #define BIT_P2PPS__BCNQ_PAUSE BIT(8) #define BIT_SHIFT_P2PPS_MACID_PAUSE 0 #define BIT_MASK_P2PPS_MACID_PAUSE 0xff #define BIT_P2PPS_MACID_PAUSE(x) \ (((x) & BIT_MASK_P2PPS_MACID_PAUSE) << BIT_SHIFT_P2PPS_MACID_PAUSE) #define BITS_P2PPS_MACID_PAUSE \ (BIT_MASK_P2PPS_MACID_PAUSE << BIT_SHIFT_P2PPS_MACID_PAUSE) #define BIT_CLEAR_P2PPS_MACID_PAUSE(x) ((x) & (~BITS_P2PPS_MACID_PAUSE)) #define BIT_GET_P2PPS_MACID_PAUSE(x) \ (((x) >> BIT_SHIFT_P2PPS_MACID_PAUSE) & BIT_MASK_P2PPS_MACID_PAUSE) #define BIT_SET_P2PPS_MACID_PAUSE(x, v) \ (BIT_CLEAR_P2PPS_MACID_PAUSE(x) | BIT_P2PPS_MACID_PAUSE(v)) /* 2 REG_P2PPS1_HW_AUTO_PAUSE_CTRL (Offset 0x1570) */ #define BIT_P2PPS1_NOA_STOP_TX_HANG BIT(31) #define BIT_P2PPS1_MACID_PAUSE_EN BIT(11) #define BIT_P2PPS1__MGQ_PAUSE BIT(10) #define BIT_P2PPS1__HIQ_PAUSE BIT(9) #define BIT_P2PPS1__BCNQ_PAUSE BIT(8) #define BIT_SHIFT_P2PPS1_MACID_PAUSE 0 #define BIT_MASK_P2PPS1_MACID_PAUSE 0xff #define BIT_P2PPS1_MACID_PAUSE(x) \ (((x) & BIT_MASK_P2PPS1_MACID_PAUSE) << BIT_SHIFT_P2PPS1_MACID_PAUSE) #define BITS_P2PPS1_MACID_PAUSE \ (BIT_MASK_P2PPS1_MACID_PAUSE << BIT_SHIFT_P2PPS1_MACID_PAUSE) #define BIT_CLEAR_P2PPS1_MACID_PAUSE(x) ((x) & (~BITS_P2PPS1_MACID_PAUSE)) #define BIT_GET_P2PPS1_MACID_PAUSE(x) \ (((x) >> BIT_SHIFT_P2PPS1_MACID_PAUSE) & BIT_MASK_P2PPS1_MACID_PAUSE) #define BIT_SET_P2PPS1_MACID_PAUSE(x, v) \ (BIT_CLEAR_P2PPS1_MACID_PAUSE(x) | BIT_P2PPS1_MACID_PAUSE(v)) /* 2 REG_P2PPS2_HW_AUTO_PAUSE_CTRL (Offset 0x1574) */ #define BIT_P2PPS2_NOA_STOP_TX_HANG BIT(31) #define BIT_P2PPS2_MACID_PAUSE_EN BIT(11) #define BIT_P2PPS2__MGQ_PAUSE BIT(10) #define BIT_P2PPS2__HIQ_PAUSE BIT(9) #define BIT_P2PPS2__BCNQ_PAUSE BIT(8) #define BIT_SHIFT_P2PPS2_MACID_PAUSE 0 #define BIT_MASK_P2PPS2_MACID_PAUSE 0xff #define BIT_P2PPS2_MACID_PAUSE(x) \ (((x) & BIT_MASK_P2PPS2_MACID_PAUSE) << BIT_SHIFT_P2PPS2_MACID_PAUSE) #define BITS_P2PPS2_MACID_PAUSE \ (BIT_MASK_P2PPS2_MACID_PAUSE << BIT_SHIFT_P2PPS2_MACID_PAUSE) #define BIT_CLEAR_P2PPS2_MACID_PAUSE(x) ((x) & (~BITS_P2PPS2_MACID_PAUSE)) #define BIT_GET_P2PPS2_MACID_PAUSE(x) \ (((x) >> BIT_SHIFT_P2PPS2_MACID_PAUSE) & BIT_MASK_P2PPS2_MACID_PAUSE) #define BIT_SET_P2PPS2_MACID_PAUSE(x, v) \ (BIT_CLEAR_P2PPS2_MACID_PAUSE(x) | BIT_P2PPS2_MACID_PAUSE(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_RX_TBTT_SHIFT (Offset 0x1578) */ #define BIT_SHIFT_RX_TBTT_SHIFT_SEL 24 #define BIT_MASK_RX_TBTT_SHIFT_SEL 0x7 #define BIT_RX_TBTT_SHIFT_SEL(x) \ (((x) & BIT_MASK_RX_TBTT_SHIFT_SEL) << BIT_SHIFT_RX_TBTT_SHIFT_SEL) #define BITS_RX_TBTT_SHIFT_SEL \ (BIT_MASK_RX_TBTT_SHIFT_SEL << BIT_SHIFT_RX_TBTT_SHIFT_SEL) #define BIT_CLEAR_RX_TBTT_SHIFT_SEL(x) ((x) & (~BITS_RX_TBTT_SHIFT_SEL)) #define BIT_GET_RX_TBTT_SHIFT_SEL(x) \ (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL) & BIT_MASK_RX_TBTT_SHIFT_SEL) #define BIT_SET_RX_TBTT_SHIFT_SEL(x, v) \ (BIT_CLEAR_RX_TBTT_SHIFT_SEL(x) | BIT_RX_TBTT_SHIFT_SEL(v)) #define BIT_RX_TBTT_SHIFT_RW_FLAG BIT(15) #define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET 0 #define BIT_MASK_RX_TBTT_SHIFT_OFFSET 0xfff #define BIT_RX_TBTT_SHIFT_OFFSET(x) \ (((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET) \ << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET) #define BITS_RX_TBTT_SHIFT_OFFSET \ (BIT_MASK_RX_TBTT_SHIFT_OFFSET << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET) #define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET(x) ((x) & (~BITS_RX_TBTT_SHIFT_OFFSET)) #define BIT_GET_RX_TBTT_SHIFT_OFFSET(x) \ (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET) & \ BIT_MASK_RX_TBTT_SHIFT_OFFSET) #define BIT_SET_RX_TBTT_SHIFT_OFFSET(x, v) \ (BIT_CLEAR_RX_TBTT_SHIFT_OFFSET(x) | BIT_RX_TBTT_SHIFT_OFFSET(v)) /* 2 REG_FREERUN_CNT_LOW (Offset 0x1580) */ #define BIT_SHIFT_FREERUN_CNT_LOW 0 #define BIT_MASK_FREERUN_CNT_LOW 0xffffffffL #define BIT_FREERUN_CNT_LOW(x) \ (((x) & BIT_MASK_FREERUN_CNT_LOW) << BIT_SHIFT_FREERUN_CNT_LOW) #define BITS_FREERUN_CNT_LOW \ (BIT_MASK_FREERUN_CNT_LOW << BIT_SHIFT_FREERUN_CNT_LOW) #define BIT_CLEAR_FREERUN_CNT_LOW(x) ((x) & (~BITS_FREERUN_CNT_LOW)) #define BIT_GET_FREERUN_CNT_LOW(x) \ (((x) >> BIT_SHIFT_FREERUN_CNT_LOW) & BIT_MASK_FREERUN_CNT_LOW) #define BIT_SET_FREERUN_CNT_LOW(x, v) \ (BIT_CLEAR_FREERUN_CNT_LOW(x) | BIT_FREERUN_CNT_LOW(v)) /* 2 REG_FREERUN_CNT_HIGH (Offset 0x1584) */ #define BIT_SHIFT_FREERUN_CNT_HIGH 0 #define BIT_MASK_FREERUN_CNT_HIGH 0xffffffffL #define BIT_FREERUN_CNT_HIGH(x) \ (((x) & BIT_MASK_FREERUN_CNT_HIGH) << BIT_SHIFT_FREERUN_CNT_HIGH) #define BITS_FREERUN_CNT_HIGH \ (BIT_MASK_FREERUN_CNT_HIGH << BIT_SHIFT_FREERUN_CNT_HIGH) #define BIT_CLEAR_FREERUN_CNT_HIGH(x) ((x) & (~BITS_FREERUN_CNT_HIGH)) #define BIT_GET_FREERUN_CNT_HIGH(x) \ (((x) >> BIT_SHIFT_FREERUN_CNT_HIGH) & BIT_MASK_FREERUN_CNT_HIGH) #define BIT_SET_FREERUN_CNT_HIGH(x, v) \ (BIT_CLEAR_FREERUN_CNT_HIGH(x) | BIT_FREERUN_CNT_HIGH(v)) /* 2 REG_PS_TIMER_0 (Offset 0x158C) */ #define BIT_SHIFT_PS_TIMER_0 0 #define BIT_MASK_PS_TIMER_0 0xffffffffL #define BIT_PS_TIMER_0(x) (((x) & BIT_MASK_PS_TIMER_0) << BIT_SHIFT_PS_TIMER_0) #define BITS_PS_TIMER_0 (BIT_MASK_PS_TIMER_0 << BIT_SHIFT_PS_TIMER_0) #define BIT_CLEAR_PS_TIMER_0(x) ((x) & (~BITS_PS_TIMER_0)) #define BIT_GET_PS_TIMER_0(x) \ (((x) >> BIT_SHIFT_PS_TIMER_0) & BIT_MASK_PS_TIMER_0) #define BIT_SET_PS_TIMER_0(x, v) (BIT_CLEAR_PS_TIMER_0(x) | BIT_PS_TIMER_0(v)) /* 2 REG_PS_TIMER_1 (Offset 0x1590) */ #define BIT_SHIFT_PS_TIMER_1 0 #define BIT_MASK_PS_TIMER_1 0xffffffffL #define BIT_PS_TIMER_1(x) (((x) & BIT_MASK_PS_TIMER_1) << BIT_SHIFT_PS_TIMER_1) #define BITS_PS_TIMER_1 (BIT_MASK_PS_TIMER_1 << BIT_SHIFT_PS_TIMER_1) #define BIT_CLEAR_PS_TIMER_1(x) ((x) & (~BITS_PS_TIMER_1)) #define BIT_GET_PS_TIMER_1(x) \ (((x) >> BIT_SHIFT_PS_TIMER_1) & BIT_MASK_PS_TIMER_1) #define BIT_SET_PS_TIMER_1(x, v) (BIT_CLEAR_PS_TIMER_1(x) | BIT_PS_TIMER_1(v)) /* 2 REG_PS_TIMER_2 (Offset 0x1594) */ #define BIT_SHIFT_PS_TIMER_2 0 #define BIT_MASK_PS_TIMER_2 0xffffffffL #define BIT_PS_TIMER_2(x) (((x) & BIT_MASK_PS_TIMER_2) << BIT_SHIFT_PS_TIMER_2) #define BITS_PS_TIMER_2 (BIT_MASK_PS_TIMER_2 << BIT_SHIFT_PS_TIMER_2) #define BIT_CLEAR_PS_TIMER_2(x) ((x) & (~BITS_PS_TIMER_2)) #define BIT_GET_PS_TIMER_2(x) \ (((x) >> BIT_SHIFT_PS_TIMER_2) & BIT_MASK_PS_TIMER_2) #define BIT_SET_PS_TIMER_2(x, v) (BIT_CLEAR_PS_TIMER_2(x) | BIT_PS_TIMER_2(v)) /* 2 REG_PS_TIMER_3 (Offset 0x1598) */ #define BIT_SHIFT_PS_TIMER_3 0 #define BIT_MASK_PS_TIMER_3 0xffffffffL #define BIT_PS_TIMER_3(x) (((x) & BIT_MASK_PS_TIMER_3) << BIT_SHIFT_PS_TIMER_3) #define BITS_PS_TIMER_3 (BIT_MASK_PS_TIMER_3 << BIT_SHIFT_PS_TIMER_3) #define BIT_CLEAR_PS_TIMER_3(x) ((x) & (~BITS_PS_TIMER_3)) #define BIT_GET_PS_TIMER_3(x) \ (((x) >> BIT_SHIFT_PS_TIMER_3) & BIT_MASK_PS_TIMER_3) #define BIT_SET_PS_TIMER_3(x, v) (BIT_CLEAR_PS_TIMER_3(x) | BIT_PS_TIMER_3(v)) /* 2 REG_PS_TIMER_4 (Offset 0x159C) */ #define BIT_SHIFT_PS_TIMER_4 0 #define BIT_MASK_PS_TIMER_4 0xffffffffL #define BIT_PS_TIMER_4(x) (((x) & BIT_MASK_PS_TIMER_4) << BIT_SHIFT_PS_TIMER_4) #define BITS_PS_TIMER_4 (BIT_MASK_PS_TIMER_4 << BIT_SHIFT_PS_TIMER_4) #define BIT_CLEAR_PS_TIMER_4(x) ((x) & (~BITS_PS_TIMER_4)) #define BIT_GET_PS_TIMER_4(x) \ (((x) >> BIT_SHIFT_PS_TIMER_4) & BIT_MASK_PS_TIMER_4) #define BIT_SET_PS_TIMER_4(x, v) (BIT_CLEAR_PS_TIMER_4(x) | BIT_PS_TIMER_4(v)) /* 2 REG_PS_TIMER_5 (Offset 0x15A0) */ #define BIT_SHIFT_PS_TIMER_5 0 #define BIT_MASK_PS_TIMER_5 0xffffffffL #define BIT_PS_TIMER_5(x) (((x) & BIT_MASK_PS_TIMER_5) << BIT_SHIFT_PS_TIMER_5) #define BITS_PS_TIMER_5 (BIT_MASK_PS_TIMER_5 << BIT_SHIFT_PS_TIMER_5) #define BIT_CLEAR_PS_TIMER_5(x) ((x) & (~BITS_PS_TIMER_5)) #define BIT_GET_PS_TIMER_5(x) \ (((x) >> BIT_SHIFT_PS_TIMER_5) & BIT_MASK_PS_TIMER_5) #define BIT_SET_PS_TIMER_5(x, v) (BIT_CLEAR_PS_TIMER_5(x) | BIT_PS_TIMER_5(v)) /* 2 REG_PS_TIMER_01_CTRL (Offset 0x15A4) */ #define BIT_SHIFT_PS_TIMER_1_EARLY_TIME 24 #define BIT_MASK_PS_TIMER_1_EARLY_TIME 0xff #define BIT_PS_TIMER_1_EARLY_TIME(x) \ (((x) & BIT_MASK_PS_TIMER_1_EARLY_TIME) \ << BIT_SHIFT_PS_TIMER_1_EARLY_TIME) #define BITS_PS_TIMER_1_EARLY_TIME \ (BIT_MASK_PS_TIMER_1_EARLY_TIME << BIT_SHIFT_PS_TIMER_1_EARLY_TIME) #define BIT_CLEAR_PS_TIMER_1_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_1_EARLY_TIME)) #define BIT_GET_PS_TIMER_1_EARLY_TIME(x) \ (((x) >> BIT_SHIFT_PS_TIMER_1_EARLY_TIME) & \ BIT_MASK_PS_TIMER_1_EARLY_TIME) #define BIT_SET_PS_TIMER_1_EARLY_TIME(x, v) \ (BIT_CLEAR_PS_TIMER_1_EARLY_TIME(x) | BIT_PS_TIMER_1_EARLY_TIME(v)) #define BIT_PS_TIMER_1_EN BIT(23) #define BIT_SHIFT_PS_TIMER_1_TSF_SEL 16 #define BIT_MASK_PS_TIMER_1_TSF_SEL 0x7 #define BIT_PS_TIMER_1_TSF_SEL(x) \ (((x) & BIT_MASK_PS_TIMER_1_TSF_SEL) << BIT_SHIFT_PS_TIMER_1_TSF_SEL) #define BITS_PS_TIMER_1_TSF_SEL \ (BIT_MASK_PS_TIMER_1_TSF_SEL << BIT_SHIFT_PS_TIMER_1_TSF_SEL) #define BIT_CLEAR_PS_TIMER_1_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_1_TSF_SEL)) #define BIT_GET_PS_TIMER_1_TSF_SEL(x) \ (((x) >> BIT_SHIFT_PS_TIMER_1_TSF_SEL) & BIT_MASK_PS_TIMER_1_TSF_SEL) #define BIT_SET_PS_TIMER_1_TSF_SEL(x, v) \ (BIT_CLEAR_PS_TIMER_1_TSF_SEL(x) | BIT_PS_TIMER_1_TSF_SEL(v)) #define BIT_SHIFT_PS_TIMER_0_EARLY_TIME 8 #define BIT_MASK_PS_TIMER_0_EARLY_TIME 0xff #define BIT_PS_TIMER_0_EARLY_TIME(x) \ (((x) & BIT_MASK_PS_TIMER_0_EARLY_TIME) \ << BIT_SHIFT_PS_TIMER_0_EARLY_TIME) #define BITS_PS_TIMER_0_EARLY_TIME \ (BIT_MASK_PS_TIMER_0_EARLY_TIME << BIT_SHIFT_PS_TIMER_0_EARLY_TIME) #define BIT_CLEAR_PS_TIMER_0_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_0_EARLY_TIME)) #define BIT_GET_PS_TIMER_0_EARLY_TIME(x) \ (((x) >> BIT_SHIFT_PS_TIMER_0_EARLY_TIME) & \ BIT_MASK_PS_TIMER_0_EARLY_TIME) #define BIT_SET_PS_TIMER_0_EARLY_TIME(x, v) \ (BIT_CLEAR_PS_TIMER_0_EARLY_TIME(x) | BIT_PS_TIMER_0_EARLY_TIME(v)) #define BIT_PS_TIMER_0_EN BIT(7) #define BIT_SHIFT_PS_TIMER_0_TSF_SEL 0 #define BIT_MASK_PS_TIMER_0_TSF_SEL 0x7 #define BIT_PS_TIMER_0_TSF_SEL(x) \ (((x) & BIT_MASK_PS_TIMER_0_TSF_SEL) << BIT_SHIFT_PS_TIMER_0_TSF_SEL) #define BITS_PS_TIMER_0_TSF_SEL \ (BIT_MASK_PS_TIMER_0_TSF_SEL << BIT_SHIFT_PS_TIMER_0_TSF_SEL) #define BIT_CLEAR_PS_TIMER_0_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_0_TSF_SEL)) #define BIT_GET_PS_TIMER_0_TSF_SEL(x) \ (((x) >> BIT_SHIFT_PS_TIMER_0_TSF_SEL) & BIT_MASK_PS_TIMER_0_TSF_SEL) #define BIT_SET_PS_TIMER_0_TSF_SEL(x, v) \ (BIT_CLEAR_PS_TIMER_0_TSF_SEL(x) | BIT_PS_TIMER_0_TSF_SEL(v)) /* 2 REG_PS_TIMER_23_CTRL (Offset 0x15A8) */ #define BIT_SHIFT_PS_TIMER_3_EARLY_TIME 24 #define BIT_MASK_PS_TIMER_3_EARLY_TIME 0xff #define BIT_PS_TIMER_3_EARLY_TIME(x) \ (((x) & BIT_MASK_PS_TIMER_3_EARLY_TIME) \ << BIT_SHIFT_PS_TIMER_3_EARLY_TIME) #define BITS_PS_TIMER_3_EARLY_TIME \ (BIT_MASK_PS_TIMER_3_EARLY_TIME << BIT_SHIFT_PS_TIMER_3_EARLY_TIME) #define BIT_CLEAR_PS_TIMER_3_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_3_EARLY_TIME)) #define BIT_GET_PS_TIMER_3_EARLY_TIME(x) \ (((x) >> BIT_SHIFT_PS_TIMER_3_EARLY_TIME) & \ BIT_MASK_PS_TIMER_3_EARLY_TIME) #define BIT_SET_PS_TIMER_3_EARLY_TIME(x, v) \ (BIT_CLEAR_PS_TIMER_3_EARLY_TIME(x) | BIT_PS_TIMER_3_EARLY_TIME(v)) #define BIT_PS_TIMER_3_EN BIT(23) #define BIT_SHIFT_PS_TIMER_3_TSF_SEL 16 #define BIT_MASK_PS_TIMER_3_TSF_SEL 0x7 #define BIT_PS_TIMER_3_TSF_SEL(x) \ (((x) & BIT_MASK_PS_TIMER_3_TSF_SEL) << BIT_SHIFT_PS_TIMER_3_TSF_SEL) #define BITS_PS_TIMER_3_TSF_SEL \ (BIT_MASK_PS_TIMER_3_TSF_SEL << BIT_SHIFT_PS_TIMER_3_TSF_SEL) #define BIT_CLEAR_PS_TIMER_3_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_3_TSF_SEL)) #define BIT_GET_PS_TIMER_3_TSF_SEL(x) \ (((x) >> BIT_SHIFT_PS_TIMER_3_TSF_SEL) & BIT_MASK_PS_TIMER_3_TSF_SEL) #define BIT_SET_PS_TIMER_3_TSF_SEL(x, v) \ (BIT_CLEAR_PS_TIMER_3_TSF_SEL(x) | BIT_PS_TIMER_3_TSF_SEL(v)) #define BIT_SHIFT_PS_TIMER_2_EARLY_TIME 8 #define BIT_MASK_PS_TIMER_2_EARLY_TIME 0xff #define BIT_PS_TIMER_2_EARLY_TIME(x) \ (((x) & BIT_MASK_PS_TIMER_2_EARLY_TIME) \ << BIT_SHIFT_PS_TIMER_2_EARLY_TIME) #define BITS_PS_TIMER_2_EARLY_TIME \ (BIT_MASK_PS_TIMER_2_EARLY_TIME << BIT_SHIFT_PS_TIMER_2_EARLY_TIME) #define BIT_CLEAR_PS_TIMER_2_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_2_EARLY_TIME)) #define BIT_GET_PS_TIMER_2_EARLY_TIME(x) \ (((x) >> BIT_SHIFT_PS_TIMER_2_EARLY_TIME) & \ BIT_MASK_PS_TIMER_2_EARLY_TIME) #define BIT_SET_PS_TIMER_2_EARLY_TIME(x, v) \ (BIT_CLEAR_PS_TIMER_2_EARLY_TIME(x) | BIT_PS_TIMER_2_EARLY_TIME(v)) #define BIT_PS_TIMER_2_EN BIT(7) #define BIT_SHIFT_PS_TIMER_2_TSF_SEL 0 #define BIT_MASK_PS_TIMER_2_TSF_SEL 0x7 #define BIT_PS_TIMER_2_TSF_SEL(x) \ (((x) & BIT_MASK_PS_TIMER_2_TSF_SEL) << BIT_SHIFT_PS_TIMER_2_TSF_SEL) #define BITS_PS_TIMER_2_TSF_SEL \ (BIT_MASK_PS_TIMER_2_TSF_SEL << BIT_SHIFT_PS_TIMER_2_TSF_SEL) #define BIT_CLEAR_PS_TIMER_2_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_2_TSF_SEL)) #define BIT_GET_PS_TIMER_2_TSF_SEL(x) \ (((x) >> BIT_SHIFT_PS_TIMER_2_TSF_SEL) & BIT_MASK_PS_TIMER_2_TSF_SEL) #define BIT_SET_PS_TIMER_2_TSF_SEL(x, v) \ (BIT_CLEAR_PS_TIMER_2_TSF_SEL(x) | BIT_PS_TIMER_2_TSF_SEL(v)) /* 2 REG_PS_TIMER_45_CTRL (Offset 0x15AC) */ #define BIT_SHIFT_PS_TIMER_5_EARLY_TIME 24 #define BIT_MASK_PS_TIMER_5_EARLY_TIME 0xff #define BIT_PS_TIMER_5_EARLY_TIME(x) \ (((x) & BIT_MASK_PS_TIMER_5_EARLY_TIME) \ << BIT_SHIFT_PS_TIMER_5_EARLY_TIME) #define BITS_PS_TIMER_5_EARLY_TIME \ (BIT_MASK_PS_TIMER_5_EARLY_TIME << BIT_SHIFT_PS_TIMER_5_EARLY_TIME) #define BIT_CLEAR_PS_TIMER_5_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_5_EARLY_TIME)) #define BIT_GET_PS_TIMER_5_EARLY_TIME(x) \ (((x) >> BIT_SHIFT_PS_TIMER_5_EARLY_TIME) & \ BIT_MASK_PS_TIMER_5_EARLY_TIME) #define BIT_SET_PS_TIMER_5_EARLY_TIME(x, v) \ (BIT_CLEAR_PS_TIMER_5_EARLY_TIME(x) | BIT_PS_TIMER_5_EARLY_TIME(v)) #define BIT_PS_TIMER_5_EN BIT(23) #define BIT_SHIFT_PS_TIMER_5_TSF_SEL 16 #define BIT_MASK_PS_TIMER_5_TSF_SEL 0x7 #define BIT_PS_TIMER_5_TSF_SEL(x) \ (((x) & BIT_MASK_PS_TIMER_5_TSF_SEL) << BIT_SHIFT_PS_TIMER_5_TSF_SEL) #define BITS_PS_TIMER_5_TSF_SEL \ (BIT_MASK_PS_TIMER_5_TSF_SEL << BIT_SHIFT_PS_TIMER_5_TSF_SEL) #define BIT_CLEAR_PS_TIMER_5_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_5_TSF_SEL)) #define BIT_GET_PS_TIMER_5_TSF_SEL(x) \ (((x) >> BIT_SHIFT_PS_TIMER_5_TSF_SEL) & BIT_MASK_PS_TIMER_5_TSF_SEL) #define BIT_SET_PS_TIMER_5_TSF_SEL(x, v) \ (BIT_CLEAR_PS_TIMER_5_TSF_SEL(x) | BIT_PS_TIMER_5_TSF_SEL(v)) #define BIT_SHIFT_PS_TIMER_4_EARLY_TIME 8 #define BIT_MASK_PS_TIMER_4_EARLY_TIME 0xff #define BIT_PS_TIMER_4_EARLY_TIME(x) \ (((x) & BIT_MASK_PS_TIMER_4_EARLY_TIME) \ << BIT_SHIFT_PS_TIMER_4_EARLY_TIME) #define BITS_PS_TIMER_4_EARLY_TIME \ (BIT_MASK_PS_TIMER_4_EARLY_TIME << BIT_SHIFT_PS_TIMER_4_EARLY_TIME) #define BIT_CLEAR_PS_TIMER_4_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_4_EARLY_TIME)) #define BIT_GET_PS_TIMER_4_EARLY_TIME(x) \ (((x) >> BIT_SHIFT_PS_TIMER_4_EARLY_TIME) & \ BIT_MASK_PS_TIMER_4_EARLY_TIME) #define BIT_SET_PS_TIMER_4_EARLY_TIME(x, v) \ (BIT_CLEAR_PS_TIMER_4_EARLY_TIME(x) | BIT_PS_TIMER_4_EARLY_TIME(v)) #define BIT_PS_TIMER_4_EN BIT(7) #define BIT_SHIFT_PS_TIMER_4_TSF_SEL 0 #define BIT_MASK_PS_TIMER_4_TSF_SEL 0x7 #define BIT_PS_TIMER_4_TSF_SEL(x) \ (((x) & BIT_MASK_PS_TIMER_4_TSF_SEL) << BIT_SHIFT_PS_TIMER_4_TSF_SEL) #define BITS_PS_TIMER_4_TSF_SEL \ (BIT_MASK_PS_TIMER_4_TSF_SEL << BIT_SHIFT_PS_TIMER_4_TSF_SEL) #define BIT_CLEAR_PS_TIMER_4_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_4_TSF_SEL)) #define BIT_GET_PS_TIMER_4_TSF_SEL(x) \ (((x) >> BIT_SHIFT_PS_TIMER_4_TSF_SEL) & BIT_MASK_PS_TIMER_4_TSF_SEL) #define BIT_SET_PS_TIMER_4_TSF_SEL(x, v) \ (BIT_CLEAR_PS_TIMER_4_TSF_SEL(x) | BIT_PS_TIMER_4_TSF_SEL(v)) /* 2 REG_CPUMGQ_FREERUN_TIMER_CTRL (Offset 0x15B0) */ #define BIT_FREECNT_RST_V1 BIT(23) #define BIT_EN_FREECNT_V1 BIT(16) #define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1 8 #define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1 0xff #define BIT_CPUMGQ_TX_TIMER_EARLY_V1(x) \ (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1) \ << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1) #define BITS_CPUMGQ_TX_TIMER_EARLY_V1 \ (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1 \ << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1) #define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1(x) \ ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_V1)) #define BIT_GET_CPUMGQ_TX_TIMER_EARLY_V1(x) \ (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1) & \ BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1) #define BIT_SET_CPUMGQ_TX_TIMER_EARLY_V1(x, v) \ (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1(x) | \ BIT_CPUMGQ_TX_TIMER_EARLY_V1(v)) #define BIT_CPUMGQ_TIMER_EN_V1 BIT(7) #define BIT_CPUMGQ_DROP_BY_HOLDTIME BIT(5) #define BIT_CPUMGQ_TX_EN_V1 BIT(4) #define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1 0 #define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1 0x7 #define BIT_CPUMGQ_TIMER_TSF_SEL_V1(x) \ (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1) \ << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1) #define BITS_CPUMGQ_TIMER_TSF_SEL_V1 \ (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1) #define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1(x) \ ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_V1)) #define BIT_GET_CPUMGQ_TIMER_TSF_SEL_V1(x) \ (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1) & \ BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1) #define BIT_SET_CPUMGQ_TIMER_TSF_SEL_V1(x, v) \ (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1(x) | BIT_CPUMGQ_TIMER_TSF_SEL_V1(v)) /* 2 REG_CPUMGQ_PROHIBIT (Offset 0x15B4) */ #define BIT_SHIFT_CPUMGQ_HOLD_TIME 8 #define BIT_MASK_CPUMGQ_HOLD_TIME 0xfff #define BIT_CPUMGQ_HOLD_TIME(x) \ (((x) & BIT_MASK_CPUMGQ_HOLD_TIME) << BIT_SHIFT_CPUMGQ_HOLD_TIME) #define BITS_CPUMGQ_HOLD_TIME \ (BIT_MASK_CPUMGQ_HOLD_TIME << BIT_SHIFT_CPUMGQ_HOLD_TIME) #define BIT_CLEAR_CPUMGQ_HOLD_TIME(x) ((x) & (~BITS_CPUMGQ_HOLD_TIME)) #define BIT_GET_CPUMGQ_HOLD_TIME(x) \ (((x) >> BIT_SHIFT_CPUMGQ_HOLD_TIME) & BIT_MASK_CPUMGQ_HOLD_TIME) #define BIT_SET_CPUMGQ_HOLD_TIME(x, v) \ (BIT_CLEAR_CPUMGQ_HOLD_TIME(x) | BIT_CPUMGQ_HOLD_TIME(v)) #define BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP 0 #define BIT_MASK_CPUMGQ_PROHIBIT_SETUP 0xf #define BIT_CPUMGQ_PROHIBIT_SETUP(x) \ (((x) & BIT_MASK_CPUMGQ_PROHIBIT_SETUP) \ << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP) #define BITS_CPUMGQ_PROHIBIT_SETUP \ (BIT_MASK_CPUMGQ_PROHIBIT_SETUP << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP) #define BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP(x) ((x) & (~BITS_CPUMGQ_PROHIBIT_SETUP)) #define BIT_GET_CPUMGQ_PROHIBIT_SETUP(x) \ (((x) >> BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP) & \ BIT_MASK_CPUMGQ_PROHIBIT_SETUP) #define BIT_SET_CPUMGQ_PROHIBIT_SETUP(x, v) \ (BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP(x) | BIT_CPUMGQ_PROHIBIT_SETUP(v)) /* 2 REG_TIMER_COMPARE (Offset 0x15C0) */ #define BIT_COMP_TRIGGER BIT(7) #define BIT_SHIFT_Y_COMP 4 #define BIT_MASK_Y_COMP 0x7 #define BIT_Y_COMP(x) (((x) & BIT_MASK_Y_COMP) << BIT_SHIFT_Y_COMP) #define BITS_Y_COMP (BIT_MASK_Y_COMP << BIT_SHIFT_Y_COMP) #define BIT_CLEAR_Y_COMP(x) ((x) & (~BITS_Y_COMP)) #define BIT_GET_Y_COMP(x) (((x) >> BIT_SHIFT_Y_COMP) & BIT_MASK_Y_COMP) #define BIT_SET_Y_COMP(x, v) (BIT_CLEAR_Y_COMP(x) | BIT_Y_COMP(v)) #define BIT_X_COMP_Y_OVERFLOW BIT(3) #define BIT_SHIFT_X_COMP 0 #define BIT_MASK_X_COMP 0x7 #define BIT_X_COMP(x) (((x) & BIT_MASK_X_COMP) << BIT_SHIFT_X_COMP) #define BITS_X_COMP (BIT_MASK_X_COMP << BIT_SHIFT_X_COMP) #define BIT_CLEAR_X_COMP(x) ((x) & (~BITS_X_COMP)) #define BIT_GET_X_COMP(x) (((x) >> BIT_SHIFT_X_COMP) & BIT_MASK_X_COMP) #define BIT_SET_X_COMP(x, v) (BIT_CLEAR_X_COMP(x) | BIT_X_COMP(v)) /* 2 REG_TIMER_COMPARE_VALUE_LOW (Offset 0x15C4) */ #define BIT_SHIFT_COMP_VALUE_LOW 0 #define BIT_MASK_COMP_VALUE_LOW 0xffffffffL #define BIT_COMP_VALUE_LOW(x) \ (((x) & BIT_MASK_COMP_VALUE_LOW) << BIT_SHIFT_COMP_VALUE_LOW) #define BITS_COMP_VALUE_LOW \ (BIT_MASK_COMP_VALUE_LOW << BIT_SHIFT_COMP_VALUE_LOW) #define BIT_CLEAR_COMP_VALUE_LOW(x) ((x) & (~BITS_COMP_VALUE_LOW)) #define BIT_GET_COMP_VALUE_LOW(x) \ (((x) >> BIT_SHIFT_COMP_VALUE_LOW) & BIT_MASK_COMP_VALUE_LOW) #define BIT_SET_COMP_VALUE_LOW(x, v) \ (BIT_CLEAR_COMP_VALUE_LOW(x) | BIT_COMP_VALUE_LOW(v)) /* 2 REG_TIMER_COMPARE_VALUE_HIGH (Offset 0x15C8) */ #define BIT_SHIFT_COMP_VALUE_HIGH 0 #define BIT_MASK_COMP_VALUE_HIGH 0xffffffffL #define BIT_COMP_VALUE_HIGH(x) \ (((x) & BIT_MASK_COMP_VALUE_HIGH) << BIT_SHIFT_COMP_VALUE_HIGH) #define BITS_COMP_VALUE_HIGH \ (BIT_MASK_COMP_VALUE_HIGH << BIT_SHIFT_COMP_VALUE_HIGH) #define BIT_CLEAR_COMP_VALUE_HIGH(x) ((x) & (~BITS_COMP_VALUE_HIGH)) #define BIT_GET_COMP_VALUE_HIGH(x) \ (((x) >> BIT_SHIFT_COMP_VALUE_HIGH) & BIT_MASK_COMP_VALUE_HIGH) #define BIT_SET_COMP_VALUE_HIGH(x, v) \ (BIT_CLEAR_COMP_VALUE_HIGH(x) | BIT_COMP_VALUE_HIGH(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BCN_PSR_RPT2 (Offset 0x1600) */ #define BIT_SHIFT_DTIM_CNT2 24 #define BIT_MASK_DTIM_CNT2 0xff #define BIT_DTIM_CNT2(x) (((x) & BIT_MASK_DTIM_CNT2) << BIT_SHIFT_DTIM_CNT2) #define BITS_DTIM_CNT2 (BIT_MASK_DTIM_CNT2 << BIT_SHIFT_DTIM_CNT2) #define BIT_CLEAR_DTIM_CNT2(x) ((x) & (~BITS_DTIM_CNT2)) #define BIT_GET_DTIM_CNT2(x) (((x) >> BIT_SHIFT_DTIM_CNT2) & BIT_MASK_DTIM_CNT2) #define BIT_SET_DTIM_CNT2(x, v) (BIT_CLEAR_DTIM_CNT2(x) | BIT_DTIM_CNT2(v)) #define BIT_SHIFT_DTIM_PERIOD2 16 #define BIT_MASK_DTIM_PERIOD2 0xff #define BIT_DTIM_PERIOD2(x) \ (((x) & BIT_MASK_DTIM_PERIOD2) << BIT_SHIFT_DTIM_PERIOD2) #define BITS_DTIM_PERIOD2 (BIT_MASK_DTIM_PERIOD2 << BIT_SHIFT_DTIM_PERIOD2) #define BIT_CLEAR_DTIM_PERIOD2(x) ((x) & (~BITS_DTIM_PERIOD2)) #define BIT_GET_DTIM_PERIOD2(x) \ (((x) >> BIT_SHIFT_DTIM_PERIOD2) & BIT_MASK_DTIM_PERIOD2) #define BIT_SET_DTIM_PERIOD2(x, v) \ (BIT_CLEAR_DTIM_PERIOD2(x) | BIT_DTIM_PERIOD2(v)) #define BIT_DTIM2 BIT(15) #define BIT_TIM2 BIT(14) #define BIT_SHIFT_PS_AID_2 0 #define BIT_MASK_PS_AID_2 0x7ff #define BIT_PS_AID_2(x) (((x) & BIT_MASK_PS_AID_2) << BIT_SHIFT_PS_AID_2) #define BITS_PS_AID_2 (BIT_MASK_PS_AID_2 << BIT_SHIFT_PS_AID_2) #define BIT_CLEAR_PS_AID_2(x) ((x) & (~BITS_PS_AID_2)) #define BIT_GET_PS_AID_2(x) (((x) >> BIT_SHIFT_PS_AID_2) & BIT_MASK_PS_AID_2) #define BIT_SET_PS_AID_2(x, v) (BIT_CLEAR_PS_AID_2(x) | BIT_PS_AID_2(v)) /* 2 REG_BCN_PSR_RPT3 (Offset 0x1604) */ #define BIT_SHIFT_DTIM_CNT3 24 #define BIT_MASK_DTIM_CNT3 0xff #define BIT_DTIM_CNT3(x) (((x) & BIT_MASK_DTIM_CNT3) << BIT_SHIFT_DTIM_CNT3) #define BITS_DTIM_CNT3 (BIT_MASK_DTIM_CNT3 << BIT_SHIFT_DTIM_CNT3) #define BIT_CLEAR_DTIM_CNT3(x) ((x) & (~BITS_DTIM_CNT3)) #define BIT_GET_DTIM_CNT3(x) (((x) >> BIT_SHIFT_DTIM_CNT3) & BIT_MASK_DTIM_CNT3) #define BIT_SET_DTIM_CNT3(x, v) (BIT_CLEAR_DTIM_CNT3(x) | BIT_DTIM_CNT3(v)) #define BIT_SHIFT_DTIM_PERIOD3 16 #define BIT_MASK_DTIM_PERIOD3 0xff #define BIT_DTIM_PERIOD3(x) \ (((x) & BIT_MASK_DTIM_PERIOD3) << BIT_SHIFT_DTIM_PERIOD3) #define BITS_DTIM_PERIOD3 (BIT_MASK_DTIM_PERIOD3 << BIT_SHIFT_DTIM_PERIOD3) #define BIT_CLEAR_DTIM_PERIOD3(x) ((x) & (~BITS_DTIM_PERIOD3)) #define BIT_GET_DTIM_PERIOD3(x) \ (((x) >> BIT_SHIFT_DTIM_PERIOD3) & BIT_MASK_DTIM_PERIOD3) #define BIT_SET_DTIM_PERIOD3(x, v) \ (BIT_CLEAR_DTIM_PERIOD3(x) | BIT_DTIM_PERIOD3(v)) #define BIT_DTIM3 BIT(15) #define BIT_TIM3 BIT(14) #define BIT_SHIFT_PS_AID_3 0 #define BIT_MASK_PS_AID_3 0x7ff #define BIT_PS_AID_3(x) (((x) & BIT_MASK_PS_AID_3) << BIT_SHIFT_PS_AID_3) #define BITS_PS_AID_3 (BIT_MASK_PS_AID_3 << BIT_SHIFT_PS_AID_3) #define BIT_CLEAR_PS_AID_3(x) ((x) & (~BITS_PS_AID_3)) #define BIT_GET_PS_AID_3(x) (((x) >> BIT_SHIFT_PS_AID_3) & BIT_MASK_PS_AID_3) #define BIT_SET_PS_AID_3(x, v) (BIT_CLEAR_PS_AID_3(x) | BIT_PS_AID_3(v)) /* 2 REG_BCN_PSR_RPT4 (Offset 0x1608) */ #define BIT_SHIFT_DTIM_CNT4 24 #define BIT_MASK_DTIM_CNT4 0xff #define BIT_DTIM_CNT4(x) (((x) & BIT_MASK_DTIM_CNT4) << BIT_SHIFT_DTIM_CNT4) #define BITS_DTIM_CNT4 (BIT_MASK_DTIM_CNT4 << BIT_SHIFT_DTIM_CNT4) #define BIT_CLEAR_DTIM_CNT4(x) ((x) & (~BITS_DTIM_CNT4)) #define BIT_GET_DTIM_CNT4(x) (((x) >> BIT_SHIFT_DTIM_CNT4) & BIT_MASK_DTIM_CNT4) #define BIT_SET_DTIM_CNT4(x, v) (BIT_CLEAR_DTIM_CNT4(x) | BIT_DTIM_CNT4(v)) #define BIT_SHIFT_DTIM_PERIOD4 16 #define BIT_MASK_DTIM_PERIOD4 0xff #define BIT_DTIM_PERIOD4(x) \ (((x) & BIT_MASK_DTIM_PERIOD4) << BIT_SHIFT_DTIM_PERIOD4) #define BITS_DTIM_PERIOD4 (BIT_MASK_DTIM_PERIOD4 << BIT_SHIFT_DTIM_PERIOD4) #define BIT_CLEAR_DTIM_PERIOD4(x) ((x) & (~BITS_DTIM_PERIOD4)) #define BIT_GET_DTIM_PERIOD4(x) \ (((x) >> BIT_SHIFT_DTIM_PERIOD4) & BIT_MASK_DTIM_PERIOD4) #define BIT_SET_DTIM_PERIOD4(x, v) \ (BIT_CLEAR_DTIM_PERIOD4(x) | BIT_DTIM_PERIOD4(v)) #define BIT_DTIM4 BIT(15) #define BIT_TIM4 BIT(14) #define BIT_SHIFT_PS_AID_4 0 #define BIT_MASK_PS_AID_4 0x7ff #define BIT_PS_AID_4(x) (((x) & BIT_MASK_PS_AID_4) << BIT_SHIFT_PS_AID_4) #define BITS_PS_AID_4 (BIT_MASK_PS_AID_4 << BIT_SHIFT_PS_AID_4) #define BIT_CLEAR_PS_AID_4(x) ((x) & (~BITS_PS_AID_4)) #define BIT_GET_PS_AID_4(x) (((x) >> BIT_SHIFT_PS_AID_4) & BIT_MASK_PS_AID_4) #define BIT_SET_PS_AID_4(x, v) (BIT_CLEAR_PS_AID_4(x) | BIT_PS_AID_4(v)) /* 2 REG_A1_ADDR_MASK (Offset 0x160C) */ #define BIT_SHIFT_A1_ADDR_MASK 0 #define BIT_MASK_A1_ADDR_MASK 0xffffffffL #define BIT_A1_ADDR_MASK(x) \ (((x) & BIT_MASK_A1_ADDR_MASK) << BIT_SHIFT_A1_ADDR_MASK) #define BITS_A1_ADDR_MASK (BIT_MASK_A1_ADDR_MASK << BIT_SHIFT_A1_ADDR_MASK) #define BIT_CLEAR_A1_ADDR_MASK(x) ((x) & (~BITS_A1_ADDR_MASK)) #define BIT_GET_A1_ADDR_MASK(x) \ (((x) >> BIT_SHIFT_A1_ADDR_MASK) & BIT_MASK_A1_ADDR_MASK) #define BIT_SET_A1_ADDR_MASK(x, v) \ (BIT_CLEAR_A1_ADDR_MASK(x) | BIT_A1_ADDR_MASK(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_RXPSF_CTRL (Offset 0x1610) */ #define BIT_RXGCK_FIFOTHR_EN BIT(28) #define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26 #define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3 #define BIT_RXGCK_VHT_FIFOTHR(x) \ (((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR) #define BITS_RXGCK_VHT_FIFOTHR \ (BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR) #define BIT_CLEAR_RXGCK_VHT_FIFOTHR(x) ((x) & (~BITS_RXGCK_VHT_FIFOTHR)) #define BIT_GET_RXGCK_VHT_FIFOTHR(x) \ (((x) >> BIT_SHIFT_RXGCK_VHT_FIFOTHR) & BIT_MASK_RXGCK_VHT_FIFOTHR) #define BIT_SET_RXGCK_VHT_FIFOTHR(x, v) \ (BIT_CLEAR_RXGCK_VHT_FIFOTHR(x) | BIT_RXGCK_VHT_FIFOTHR(v)) #define BIT_SHIFT_RXGCK_HT_FIFOTHR 24 #define BIT_MASK_RXGCK_HT_FIFOTHR 0x3 #define BIT_RXGCK_HT_FIFOTHR(x) \ (((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR) #define BITS_RXGCK_HT_FIFOTHR \ (BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR) #define BIT_CLEAR_RXGCK_HT_FIFOTHR(x) ((x) & (~BITS_RXGCK_HT_FIFOTHR)) #define BIT_GET_RXGCK_HT_FIFOTHR(x) \ (((x) >> BIT_SHIFT_RXGCK_HT_FIFOTHR) & BIT_MASK_RXGCK_HT_FIFOTHR) #define BIT_SET_RXGCK_HT_FIFOTHR(x, v) \ (BIT_CLEAR_RXGCK_HT_FIFOTHR(x) | BIT_RXGCK_HT_FIFOTHR(v)) #define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22 #define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3 #define BIT_RXGCK_OFDM_FIFOTHR(x) \ (((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR) #define BITS_RXGCK_OFDM_FIFOTHR \ (BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR) #define BIT_CLEAR_RXGCK_OFDM_FIFOTHR(x) ((x) & (~BITS_RXGCK_OFDM_FIFOTHR)) #define BIT_GET_RXGCK_OFDM_FIFOTHR(x) \ (((x) >> BIT_SHIFT_RXGCK_OFDM_FIFOTHR) & BIT_MASK_RXGCK_OFDM_FIFOTHR) #define BIT_SET_RXGCK_OFDM_FIFOTHR(x, v) \ (BIT_CLEAR_RXGCK_OFDM_FIFOTHR(x) | BIT_RXGCK_OFDM_FIFOTHR(v)) #define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20 #define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3 #define BIT_RXGCK_CCK_FIFOTHR(x) \ (((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR) #define BITS_RXGCK_CCK_FIFOTHR \ (BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR) #define BIT_CLEAR_RXGCK_CCK_FIFOTHR(x) ((x) & (~BITS_RXGCK_CCK_FIFOTHR)) #define BIT_GET_RXGCK_CCK_FIFOTHR(x) \ (((x) >> BIT_SHIFT_RXGCK_CCK_FIFOTHR) & BIT_MASK_RXGCK_CCK_FIFOTHR) #define BIT_SET_RXGCK_CCK_FIFOTHR(x, v) \ (BIT_CLEAR_RXGCK_CCK_FIFOTHR(x) | BIT_RXGCK_CCK_FIFOTHR(v)) #define BIT_SHIFT_RXGCK_ENTRY_DELAY 17 #define BIT_MASK_RXGCK_ENTRY_DELAY 0x7 #define BIT_RXGCK_ENTRY_DELAY(x) \ (((x) & BIT_MASK_RXGCK_ENTRY_DELAY) << BIT_SHIFT_RXGCK_ENTRY_DELAY) #define BITS_RXGCK_ENTRY_DELAY \ (BIT_MASK_RXGCK_ENTRY_DELAY << BIT_SHIFT_RXGCK_ENTRY_DELAY) #define BIT_CLEAR_RXGCK_ENTRY_DELAY(x) ((x) & (~BITS_RXGCK_ENTRY_DELAY)) #define BIT_GET_RXGCK_ENTRY_DELAY(x) \ (((x) >> BIT_SHIFT_RXGCK_ENTRY_DELAY) & BIT_MASK_RXGCK_ENTRY_DELAY) #define BIT_SET_RXGCK_ENTRY_DELAY(x, v) \ (BIT_CLEAR_RXGCK_ENTRY_DELAY(x) | BIT_RXGCK_ENTRY_DELAY(v)) #define BIT_RXGCK_OFDMCCA_EN BIT(16) #define BIT_SHIFT_RXPSF_PKTLENTHR 13 #define BIT_MASK_RXPSF_PKTLENTHR 0x7 #define BIT_RXPSF_PKTLENTHR(x) \ (((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR) #define BITS_RXPSF_PKTLENTHR \ (BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR) #define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR)) #define BIT_GET_RXPSF_PKTLENTHR(x) \ (((x) >> BIT_SHIFT_RXPSF_PKTLENTHR) & BIT_MASK_RXPSF_PKTLENTHR) #define BIT_SET_RXPSF_PKTLENTHR(x, v) \ (BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v)) #define BIT_RXPSF_CTRLEN BIT(12) #define BIT_RXPSF_VHTCHKEN BIT(11) #define BIT_RXPSF_HTCHKEN BIT(10) #define BIT_RXPSF_OFDMCHKEN BIT(9) #define BIT_RXPSF_CCKCHKEN BIT(8) #define BIT_RXPSF_OFDMRST BIT(7) #define BIT_RXPSF_CCKRST BIT(6) #define BIT_RXPSF_MHCHKEN BIT(5) #define BIT_RXPSF_CONT_ERRCHKEN BIT(4) #define BIT_RXPSF_ALL_ERRCHKEN BIT(3) #define BIT_SHIFT_RXPSF_ERRTHR 0 #define BIT_MASK_RXPSF_ERRTHR 0x7 #define BIT_RXPSF_ERRTHR(x) \ (((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR) #define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR) #define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR)) #define BIT_GET_RXPSF_ERRTHR(x) \ (((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR) #define BIT_SET_RXPSF_ERRTHR(x, v) \ (BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v)) /* 2 REG_RXPSF_TYPE_CTRL (Offset 0x1614) */ #define BIT_RXPSF_DATA15EN BIT(31) #define BIT_RXPSF_DATA14EN BIT(30) #define BIT_RXPSF_DATA13EN BIT(29) #define BIT_RXPSF_DATA12EN BIT(28) #define BIT_RXPSF_DATA11EN BIT(27) #define BIT_RXPSF_DATA10EN BIT(26) #define BIT_RXPSF_DATA9EN BIT(25) #define BIT_RXPSF_DATA8EN BIT(24) #define BIT_RXPSF_DATA7EN BIT(23) #define BIT_RXPSF_DATA6EN BIT(22) #define BIT_RXPSF_DATA5EN BIT(21) #define BIT_RXPSF_DATA4EN BIT(20) #define BIT_RXPSF_DATA3EN BIT(19) #define BIT_RXPSF_DATA2EN BIT(18) #define BIT_RXPSF_DATA1EN BIT(17) #define BIT_RXPSF_DATA0EN BIT(16) #define BIT_RXPSF_MGT15EN BIT(15) #define BIT_RXPSF_MGT14EN BIT(14) #define BIT_RXPSF_MGT13EN BIT(13) #define BIT_RXPSF_MGT12EN BIT(12) #define BIT_RXPSF_MGT11EN BIT(11) #define BIT_RXPSF_MGT10EN BIT(10) #define BIT_RXPSF_MGT9EN BIT(9) #define BIT_RXPSF_MGT8EN BIT(8) #define BIT_RXPSF_MGT7EN BIT(7) #define BIT_RXPSF_MGT6EN BIT(6) #define BIT_RXPSF_MGT5EN BIT(5) #define BIT_RXPSF_MGT4EN BIT(4) #define BIT_RXPSF_MGT3EN BIT(3) #define BIT_RXPSF_MGT2EN BIT(2) #define BIT_RXPSF_MGT1EN BIT(1) #define BIT_RXPSF_MGT0EN BIT(0) /* 2 REG_CAM_ACCESS_CTRL (Offset 0x1618) */ #define BIT_INDIRECT_ERR BIT(6) #define BIT_DIRECT_ERR BIT(5) #define BIT_DIR_ACCESS_EN_RX_BA BIT(4) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CAM_ACCESS_CTRL (Offset 0x1618) */ #define BIT_DIR_ACCESS_EN_ADDRCAM BIT(3) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_CAM_ACCESS_CTRL (Offset 0x1618) */ #define BIT_DIR_ACCESS_EN_MBSSIDCAM BIT(3) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CAM_ACCESS_CTRL (Offset 0x1618) */ #define BIT_DIR_ACCESS_EN_KEY BIT(2) #define BIT_DIR_ACCESS_EN_WOWLAN BIT(1) #define BIT_DIR_ACCESS_EN_FW_FILTER BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_CUT_AMSDU_CTRL (Offset 0x161C) */ #define BIT__CUT_AMSDU_CHKLEN_EN BIT(31) #define BIT_EN_CUT_AMSDU BIT(30) #define BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH 16 #define BIT_MASK_CUT_AMSDU_CHKLEN_L_TH 0xff #define BIT_CUT_AMSDU_CHKLEN_L_TH(x) \ (((x) & BIT_MASK_CUT_AMSDU_CHKLEN_L_TH) \ << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH) #define BITS_CUT_AMSDU_CHKLEN_L_TH \ (BIT_MASK_CUT_AMSDU_CHKLEN_L_TH << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH) #define BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH(x) ((x) & (~BITS_CUT_AMSDU_CHKLEN_L_TH)) #define BIT_GET_CUT_AMSDU_CHKLEN_L_TH(x) \ (((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH) & \ BIT_MASK_CUT_AMSDU_CHKLEN_L_TH) #define BIT_SET_CUT_AMSDU_CHKLEN_L_TH(x, v) \ (BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH(x) | BIT_CUT_AMSDU_CHKLEN_L_TH(v)) #define BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH 0 #define BIT_MASK_CUT_AMSDU_CHKLEN_H_TH 0xffff #define BIT_CUT_AMSDU_CHKLEN_H_TH(x) \ (((x) & BIT_MASK_CUT_AMSDU_CHKLEN_H_TH) \ << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH) #define BITS_CUT_AMSDU_CHKLEN_H_TH \ (BIT_MASK_CUT_AMSDU_CHKLEN_H_TH << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH) #define BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH(x) ((x) & (~BITS_CUT_AMSDU_CHKLEN_H_TH)) #define BIT_GET_CUT_AMSDU_CHKLEN_H_TH(x) \ (((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH) & \ BIT_MASK_CUT_AMSDU_CHKLEN_H_TH) #define BIT_SET_CUT_AMSDU_CHKLEN_H_TH(x, v) \ (BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH(x) | BIT_CUT_AMSDU_CHKLEN_H_TH(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_HT_SND_REF_RATE (Offset 0x161C) */ #define BIT_SHIFT_WMAC_HT_CSI_RATE 0 #define BIT_MASK_WMAC_HT_CSI_RATE 0x3f #define BIT_WMAC_HT_CSI_RATE(x) \ (((x) & BIT_MASK_WMAC_HT_CSI_RATE) << BIT_SHIFT_WMAC_HT_CSI_RATE) #define BITS_WMAC_HT_CSI_RATE \ (BIT_MASK_WMAC_HT_CSI_RATE << BIT_SHIFT_WMAC_HT_CSI_RATE) #define BIT_CLEAR_WMAC_HT_CSI_RATE(x) ((x) & (~BITS_WMAC_HT_CSI_RATE)) #define BIT_GET_WMAC_HT_CSI_RATE(x) \ (((x) >> BIT_SHIFT_WMAC_HT_CSI_RATE) & BIT_MASK_WMAC_HT_CSI_RATE) #define BIT_SET_WMAC_HT_CSI_RATE(x, v) \ (BIT_CLEAR_WMAC_HT_CSI_RATE(x) | BIT_WMAC_HT_CSI_RATE(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MACID2 (Offset 0x1620) */ #define BIT_SHIFT_MACID2 0 #define BIT_MASK_MACID2 0xffffffffffffL #define BIT_MACID2(x) (((x) & BIT_MASK_MACID2) << BIT_SHIFT_MACID2) #define BITS_MACID2 (BIT_MASK_MACID2 << BIT_SHIFT_MACID2) #define BIT_CLEAR_MACID2(x) ((x) & (~BITS_MACID2)) #define BIT_GET_MACID2(x) (((x) >> BIT_SHIFT_MACID2) & BIT_MASK_MACID2) #define BIT_SET_MACID2(x, v) (BIT_CLEAR_MACID2(x) | BIT_MACID2(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MACID2 (Offset 0x1620) */ #define BIT_SHIFT_MACID2_V1 0 #define BIT_MASK_MACID2_V1 0xffffffffL #define BIT_MACID2_V1(x) (((x) & BIT_MASK_MACID2_V1) << BIT_SHIFT_MACID2_V1) #define BITS_MACID2_V1 (BIT_MASK_MACID2_V1 << BIT_SHIFT_MACID2_V1) #define BIT_CLEAR_MACID2_V1(x) ((x) & (~BITS_MACID2_V1)) #define BIT_GET_MACID2_V1(x) (((x) >> BIT_SHIFT_MACID2_V1) & BIT_MASK_MACID2_V1) #define BIT_SET_MACID2_V1(x, v) (BIT_CLEAR_MACID2_V1(x) | BIT_MACID2_V1(v)) /* 2 REG_MACID2_H (Offset 0x1624) */ #define BIT_SHIFT_MACID2_H_V1 0 #define BIT_MASK_MACID2_H_V1 0xffff #define BIT_MACID2_H_V1(x) \ (((x) & BIT_MASK_MACID2_H_V1) << BIT_SHIFT_MACID2_H_V1) #define BITS_MACID2_H_V1 (BIT_MASK_MACID2_H_V1 << BIT_SHIFT_MACID2_H_V1) #define BIT_CLEAR_MACID2_H_V1(x) ((x) & (~BITS_MACID2_H_V1)) #define BIT_GET_MACID2_H_V1(x) \ (((x) >> BIT_SHIFT_MACID2_H_V1) & BIT_MASK_MACID2_H_V1) #define BIT_SET_MACID2_H_V1(x, v) \ (BIT_CLEAR_MACID2_H_V1(x) | BIT_MACID2_H_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BSSID2 (Offset 0x1628) */ #define BIT_SHIFT_BSSID2 0 #define BIT_MASK_BSSID2 0xffffffffffffL #define BIT_BSSID2(x) (((x) & BIT_MASK_BSSID2) << BIT_SHIFT_BSSID2) #define BITS_BSSID2 (BIT_MASK_BSSID2 << BIT_SHIFT_BSSID2) #define BIT_CLEAR_BSSID2(x) ((x) & (~BITS_BSSID2)) #define BIT_GET_BSSID2(x) (((x) >> BIT_SHIFT_BSSID2) & BIT_MASK_BSSID2) #define BIT_SET_BSSID2(x, v) (BIT_CLEAR_BSSID2(x) | BIT_BSSID2(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BSSID2 (Offset 0x1628) */ #define BIT_SHIFT_BSSID2_V1 0 #define BIT_MASK_BSSID2_V1 0xffffffffL #define BIT_BSSID2_V1(x) (((x) & BIT_MASK_BSSID2_V1) << BIT_SHIFT_BSSID2_V1) #define BITS_BSSID2_V1 (BIT_MASK_BSSID2_V1 << BIT_SHIFT_BSSID2_V1) #define BIT_CLEAR_BSSID2_V1(x) ((x) & (~BITS_BSSID2_V1)) #define BIT_GET_BSSID2_V1(x) (((x) >> BIT_SHIFT_BSSID2_V1) & BIT_MASK_BSSID2_V1) #define BIT_SET_BSSID2_V1(x, v) (BIT_CLEAR_BSSID2_V1(x) | BIT_BSSID2_V1(v)) /* 2 REG_BSSID2_H (Offset 0x162C) */ #define BIT_SHIFT_BSSID2_H_V1 0 #define BIT_MASK_BSSID2_H_V1 0xffff #define BIT_BSSID2_H_V1(x) \ (((x) & BIT_MASK_BSSID2_H_V1) << BIT_SHIFT_BSSID2_H_V1) #define BITS_BSSID2_H_V1 (BIT_MASK_BSSID2_H_V1 << BIT_SHIFT_BSSID2_H_V1) #define BIT_CLEAR_BSSID2_H_V1(x) ((x) & (~BITS_BSSID2_H_V1)) #define BIT_GET_BSSID2_H_V1(x) \ (((x) >> BIT_SHIFT_BSSID2_H_V1) & BIT_MASK_BSSID2_H_V1) #define BIT_SET_BSSID2_H_V1(x, v) \ (BIT_CLEAR_BSSID2_H_V1(x) | BIT_BSSID2_H_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MACID3 (Offset 0x1630) */ #define BIT_SHIFT_MACID3 0 #define BIT_MASK_MACID3 0xffffffffffffL #define BIT_MACID3(x) (((x) & BIT_MASK_MACID3) << BIT_SHIFT_MACID3) #define BITS_MACID3 (BIT_MASK_MACID3 << BIT_SHIFT_MACID3) #define BIT_CLEAR_MACID3(x) ((x) & (~BITS_MACID3)) #define BIT_GET_MACID3(x) (((x) >> BIT_SHIFT_MACID3) & BIT_MASK_MACID3) #define BIT_SET_MACID3(x, v) (BIT_CLEAR_MACID3(x) | BIT_MACID3(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MACID3 (Offset 0x1630) */ #define BIT_SHIFT_MACID3_V1 0 #define BIT_MASK_MACID3_V1 0xffffffffL #define BIT_MACID3_V1(x) (((x) & BIT_MASK_MACID3_V1) << BIT_SHIFT_MACID3_V1) #define BITS_MACID3_V1 (BIT_MASK_MACID3_V1 << BIT_SHIFT_MACID3_V1) #define BIT_CLEAR_MACID3_V1(x) ((x) & (~BITS_MACID3_V1)) #define BIT_GET_MACID3_V1(x) (((x) >> BIT_SHIFT_MACID3_V1) & BIT_MASK_MACID3_V1) #define BIT_SET_MACID3_V1(x, v) (BIT_CLEAR_MACID3_V1(x) | BIT_MACID3_V1(v)) /* 2 REG_MACID3_H (Offset 0x1634) */ #define BIT_SHIFT_MACID3_H_V1 0 #define BIT_MASK_MACID3_H_V1 0xffff #define BIT_MACID3_H_V1(x) \ (((x) & BIT_MASK_MACID3_H_V1) << BIT_SHIFT_MACID3_H_V1) #define BITS_MACID3_H_V1 (BIT_MASK_MACID3_H_V1 << BIT_SHIFT_MACID3_H_V1) #define BIT_CLEAR_MACID3_H_V1(x) ((x) & (~BITS_MACID3_H_V1)) #define BIT_GET_MACID3_H_V1(x) \ (((x) >> BIT_SHIFT_MACID3_H_V1) & BIT_MASK_MACID3_H_V1) #define BIT_SET_MACID3_H_V1(x, v) \ (BIT_CLEAR_MACID3_H_V1(x) | BIT_MACID3_H_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BSSID3 (Offset 0x1638) */ #define BIT_SHIFT_BSSID3 0 #define BIT_MASK_BSSID3 0xffffffffffffL #define BIT_BSSID3(x) (((x) & BIT_MASK_BSSID3) << BIT_SHIFT_BSSID3) #define BITS_BSSID3 (BIT_MASK_BSSID3 << BIT_SHIFT_BSSID3) #define BIT_CLEAR_BSSID3(x) ((x) & (~BITS_BSSID3)) #define BIT_GET_BSSID3(x) (((x) >> BIT_SHIFT_BSSID3) & BIT_MASK_BSSID3) #define BIT_SET_BSSID3(x, v) (BIT_CLEAR_BSSID3(x) | BIT_BSSID3(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BSSID3 (Offset 0x1638) */ #define BIT_SHIFT_BSSID3_V1 0 #define BIT_MASK_BSSID3_V1 0xffffffffL #define BIT_BSSID3_V1(x) (((x) & BIT_MASK_BSSID3_V1) << BIT_SHIFT_BSSID3_V1) #define BITS_BSSID3_V1 (BIT_MASK_BSSID3_V1 << BIT_SHIFT_BSSID3_V1) #define BIT_CLEAR_BSSID3_V1(x) ((x) & (~BITS_BSSID3_V1)) #define BIT_GET_BSSID3_V1(x) (((x) >> BIT_SHIFT_BSSID3_V1) & BIT_MASK_BSSID3_V1) #define BIT_SET_BSSID3_V1(x, v) (BIT_CLEAR_BSSID3_V1(x) | BIT_BSSID3_V1(v)) /* 2 REG_BSSID3_H (Offset 0x163C) */ #define BIT_SHIFT_BSSID3_H_V1 0 #define BIT_MASK_BSSID3_H_V1 0xffff #define BIT_BSSID3_H_V1(x) \ (((x) & BIT_MASK_BSSID3_H_V1) << BIT_SHIFT_BSSID3_H_V1) #define BITS_BSSID3_H_V1 (BIT_MASK_BSSID3_H_V1 << BIT_SHIFT_BSSID3_H_V1) #define BIT_CLEAR_BSSID3_H_V1(x) ((x) & (~BITS_BSSID3_H_V1)) #define BIT_GET_BSSID3_H_V1(x) \ (((x) >> BIT_SHIFT_BSSID3_H_V1) & BIT_MASK_BSSID3_H_V1) #define BIT_SET_BSSID3_H_V1(x, v) \ (BIT_CLEAR_BSSID3_H_V1(x) | BIT_BSSID3_H_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_MACID4 (Offset 0x1640) */ #define BIT_SHIFT_MACID4 0 #define BIT_MASK_MACID4 0xffffffffffffL #define BIT_MACID4(x) (((x) & BIT_MASK_MACID4) << BIT_SHIFT_MACID4) #define BITS_MACID4 (BIT_MASK_MACID4 << BIT_SHIFT_MACID4) #define BIT_CLEAR_MACID4(x) ((x) & (~BITS_MACID4)) #define BIT_GET_MACID4(x) (((x) >> BIT_SHIFT_MACID4) & BIT_MASK_MACID4) #define BIT_SET_MACID4(x, v) (BIT_CLEAR_MACID4(x) | BIT_MACID4(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MACID4 (Offset 0x1640) */ #define BIT_SHIFT_MACID4_V1 0 #define BIT_MASK_MACID4_V1 0xffffffffL #define BIT_MACID4_V1(x) (((x) & BIT_MASK_MACID4_V1) << BIT_SHIFT_MACID4_V1) #define BITS_MACID4_V1 (BIT_MASK_MACID4_V1 << BIT_SHIFT_MACID4_V1) #define BIT_CLEAR_MACID4_V1(x) ((x) & (~BITS_MACID4_V1)) #define BIT_GET_MACID4_V1(x) (((x) >> BIT_SHIFT_MACID4_V1) & BIT_MASK_MACID4_V1) #define BIT_SET_MACID4_V1(x, v) (BIT_CLEAR_MACID4_V1(x) | BIT_MACID4_V1(v)) /* 2 REG_MACID4_H (Offset 0x1644) */ #define BIT_SHIFT_MACID4_H_V1 0 #define BIT_MASK_MACID4_H_V1 0xffff #define BIT_MACID4_H_V1(x) \ (((x) & BIT_MASK_MACID4_H_V1) << BIT_SHIFT_MACID4_H_V1) #define BITS_MACID4_H_V1 (BIT_MASK_MACID4_H_V1 << BIT_SHIFT_MACID4_H_V1) #define BIT_CLEAR_MACID4_H_V1(x) ((x) & (~BITS_MACID4_H_V1)) #define BIT_GET_MACID4_H_V1(x) \ (((x) >> BIT_SHIFT_MACID4_H_V1) & BIT_MASK_MACID4_H_V1) #define BIT_SET_MACID4_H_V1(x, v) \ (BIT_CLEAR_MACID4_H_V1(x) | BIT_MACID4_H_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_BSSID4 (Offset 0x1648) */ #define BIT_SHIFT_BSSID4 0 #define BIT_MASK_BSSID4 0xffffffffffffL #define BIT_BSSID4(x) (((x) & BIT_MASK_BSSID4) << BIT_SHIFT_BSSID4) #define BITS_BSSID4 (BIT_MASK_BSSID4 << BIT_SHIFT_BSSID4) #define BIT_CLEAR_BSSID4(x) ((x) & (~BITS_BSSID4)) #define BIT_GET_BSSID4(x) (((x) >> BIT_SHIFT_BSSID4) & BIT_MASK_BSSID4) #define BIT_SET_BSSID4(x, v) (BIT_CLEAR_BSSID4(x) | BIT_BSSID4(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_BSSID4 (Offset 0x1648) */ #define BIT_SHIFT_BSSID4_V1 0 #define BIT_MASK_BSSID4_V1 0xffffffffL #define BIT_BSSID4_V1(x) (((x) & BIT_MASK_BSSID4_V1) << BIT_SHIFT_BSSID4_V1) #define BITS_BSSID4_V1 (BIT_MASK_BSSID4_V1 << BIT_SHIFT_BSSID4_V1) #define BIT_CLEAR_BSSID4_V1(x) ((x) & (~BITS_BSSID4_V1)) #define BIT_GET_BSSID4_V1(x) (((x) >> BIT_SHIFT_BSSID4_V1) & BIT_MASK_BSSID4_V1) #define BIT_SET_BSSID4_V1(x, v) (BIT_CLEAR_BSSID4_V1(x) | BIT_BSSID4_V1(v)) /* 2 REG_BSSID4_H (Offset 0x164C) */ #define BIT_SHIFT_BSSID4_H_V1 0 #define BIT_MASK_BSSID4_H_V1 0xffff #define BIT_BSSID4_H_V1(x) \ (((x) & BIT_MASK_BSSID4_H_V1) << BIT_SHIFT_BSSID4_H_V1) #define BITS_BSSID4_H_V1 (BIT_MASK_BSSID4_H_V1 << BIT_SHIFT_BSSID4_H_V1) #define BIT_CLEAR_BSSID4_H_V1(x) ((x) & (~BITS_BSSID4_H_V1)) #define BIT_GET_BSSID4_H_V1(x) \ (((x) >> BIT_SHIFT_BSSID4_H_V1) & BIT_MASK_BSSID4_H_V1) #define BIT_SET_BSSID4_H_V1(x, v) \ (BIT_CLEAR_BSSID4_H_V1(x) | BIT_BSSID4_H_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_NOA_REPORT (Offset 0x1650) */ #define BIT_SHIFT_NOA_RPT 0 #define BIT_MASK_NOA_RPT 0xffffffffL #define BIT_NOA_RPT(x) (((x) & BIT_MASK_NOA_RPT) << BIT_SHIFT_NOA_RPT) #define BITS_NOA_RPT (BIT_MASK_NOA_RPT << BIT_SHIFT_NOA_RPT) #define BIT_CLEAR_NOA_RPT(x) ((x) & (~BITS_NOA_RPT)) #define BIT_GET_NOA_RPT(x) (((x) >> BIT_SHIFT_NOA_RPT) & BIT_MASK_NOA_RPT) #define BIT_SET_NOA_RPT(x, v) (BIT_CLEAR_NOA_RPT(x) | BIT_NOA_RPT(v)) /* 2 REG_NOA_REPORT_1 (Offset 0x1654) */ #define BIT_SHIFT_NOA_RPT_1 0 #define BIT_MASK_NOA_RPT_1 0xffffffffL #define BIT_NOA_RPT_1(x) (((x) & BIT_MASK_NOA_RPT_1) << BIT_SHIFT_NOA_RPT_1) #define BITS_NOA_RPT_1 (BIT_MASK_NOA_RPT_1 << BIT_SHIFT_NOA_RPT_1) #define BIT_CLEAR_NOA_RPT_1(x) ((x) & (~BITS_NOA_RPT_1)) #define BIT_GET_NOA_RPT_1(x) (((x) >> BIT_SHIFT_NOA_RPT_1) & BIT_MASK_NOA_RPT_1) #define BIT_SET_NOA_RPT_1(x, v) (BIT_CLEAR_NOA_RPT_1(x) | BIT_NOA_RPT_1(v)) /* 2 REG_NOA_REPORT_2 (Offset 0x1658) */ #define BIT_SHIFT_NOA_RPT_2 0 #define BIT_MASK_NOA_RPT_2 0xffffffffL #define BIT_NOA_RPT_2(x) (((x) & BIT_MASK_NOA_RPT_2) << BIT_SHIFT_NOA_RPT_2) #define BITS_NOA_RPT_2 (BIT_MASK_NOA_RPT_2 << BIT_SHIFT_NOA_RPT_2) #define BIT_CLEAR_NOA_RPT_2(x) ((x) & (~BITS_NOA_RPT_2)) #define BIT_GET_NOA_RPT_2(x) (((x) >> BIT_SHIFT_NOA_RPT_2) & BIT_MASK_NOA_RPT_2) #define BIT_SET_NOA_RPT_2(x, v) (BIT_CLEAR_NOA_RPT_2(x) | BIT_NOA_RPT_2(v)) /* 2 REG_NOA_REPORT_3 (Offset 0x165C) */ #define BIT_SHIFT_NOA_RPT_3 0 #define BIT_MASK_NOA_RPT_3 0xff #define BIT_NOA_RPT_3(x) (((x) & BIT_MASK_NOA_RPT_3) << BIT_SHIFT_NOA_RPT_3) #define BITS_NOA_RPT_3 (BIT_MASK_NOA_RPT_3 << BIT_SHIFT_NOA_RPT_3) #define BIT_CLEAR_NOA_RPT_3(x) ((x) & (~BITS_NOA_RPT_3)) #define BIT_GET_NOA_RPT_3(x) (((x) >> BIT_SHIFT_NOA_RPT_3) & BIT_MASK_NOA_RPT_3) #define BIT_SET_NOA_RPT_3(x, v) (BIT_CLEAR_NOA_RPT_3(x) | BIT_NOA_RPT_3(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ #define BIT_CLI3_WMAC_TCRPWRMGT_HWCTL_EN BIT(15) #define BIT_CLI3_WMAC_TCRPWRMGT_HWDATA_EN BIT(14) #define BIT_CLI3_WMAC_TCRPWRMGT_HWACT_EN BIT(13) #define BIT_CLI3_PWR_ST_V1 BIT(12) #define BIT_CLI2_WMAC_TCRPWRMGT_HWCTL_EN BIT(11) #define BIT_CLI2_WMAC_TCRPWRMGT_HWDATA_EN BIT(10) #define BIT_CLI2_WMAC_TCRPWRMGT_HWACT_EN BIT(9) #define BIT_CLI2_PWR_ST_V1 BIT(8) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ #define BIT_CLI3_PWRBIT_OW_EN BIT(7) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ #define BIT_CLI1_WMAC_TCRPWRMGT_HWCTL_EN BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ #define BIT_CLI3_PWR_ST BIT(6) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ #define BIT_CLI1_WMAC_TCRPWRMGT_HWDATA_EN BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ #define BIT_CLI2_PWRBIT_OW_EN BIT(5) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ #define BIT_CLI1_WMAC_TCRPWRMGT_HWACT_EN BIT(5) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ #define BIT_CLI2_PWR_ST BIT(4) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ #define BIT_CLI1_PWR_ST_V1 BIT(4) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ #define BIT_CLI1_PWRBIT_OW_EN BIT(3) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ #define BIT_CLI0_WMAC_TCRPWRMGT_HWCTL_EN BIT(3) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ #define BIT_CLI1_PWR_ST BIT(2) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ #define BIT_CLI0_WMAC_TCRPWRMGT_HWDATA_EN BIT(2) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ #define BIT_CLI0_PWRBIT_OW_EN BIT(1) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ #define BIT_CLI0_WMAC_TCRPWRMGT_HWACT_EN BIT(1) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ #define BIT_CLI0_PWR_ST BIT(0) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ #define BIT_CLI0_PWR_ST_V1 BIT(0) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_GENERAL_OPTION (Offset 0x1664) */ #define BIT_WMAC_EXT_DBG_SEL_V1 BIT(6) #define BIT_RX_DMA_BYPASS_CHECK_DATABYPASS_CHECK_DATA BIT(4) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_GENERAL_OPTION (Offset 0x1664) */ #define BIT_PATTERN_MATCH_FIX_EN BIT(3) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_GENERAL_OPTION (Offset 0x1664) */ #define BIT_RX_DMA_BYPASS_CHECK_MGTBIT_RX_DMA_BYPASS_CHECK_MGT BIT(3) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_GENERAL_OPTION (Offset 0x1664) */ #define BIT_TXSERV_FIELD_SEL BIT(2) #define BIT_RXVHT_LEN_SEL BIT(1) #define BIT_RXMIC_PROTECT_EN BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_FWPHYFF_RCR (Offset 0x1668) */ #define BIT_RCR2_AAMSDU BIT(25) #define BIT_RCR2_CBSSID_BCN BIT(24) #define BIT_RCR2_ACRC32 BIT(23) #define BIT_RCR2_TA_BCN BIT(22) #define BIT_RCR2_CBSSID_DATA BIT(21) #define BIT_RCR2_ADD3 BIT(20) #define BIT_RCR2_AB BIT(19) #define BIT_RCR2_AM BIT(18) #define BIT_RCR2_APM BIT(17) #define BIT_RCR2_AAP BIT(16) #define BIT_RCR1_AAMSDU BIT(9) #define BIT_RCR1_CBSSID_BCN BIT(8) #define BIT_RCR1_ACRC32 BIT(7) #define BIT_RCR1_TA_BCN BIT(6) #define BIT_RCR1_CBSSID_DATA BIT(5) #define BIT_RCR1_ADD3 BIT(4) #define BIT_RCR1_AB BIT(3) #define BIT_RCR1_AM BIT(2) #define BIT_RCR1_APM BIT(1) #define BIT_RCR1_AAP BIT(0) /* 2 REG_ADDRCAM_WRITE_CONTENT (Offset 0x166C) */ #define BIT_SHIFT_ADDRCAM_WDATA 0 #define BIT_MASK_ADDRCAM_WDATA 0xffffffffL #define BIT_ADDRCAM_WDATA(x) \ (((x) & BIT_MASK_ADDRCAM_WDATA) << BIT_SHIFT_ADDRCAM_WDATA) #define BITS_ADDRCAM_WDATA (BIT_MASK_ADDRCAM_WDATA << BIT_SHIFT_ADDRCAM_WDATA) #define BIT_CLEAR_ADDRCAM_WDATA(x) ((x) & (~BITS_ADDRCAM_WDATA)) #define BIT_GET_ADDRCAM_WDATA(x) \ (((x) >> BIT_SHIFT_ADDRCAM_WDATA) & BIT_MASK_ADDRCAM_WDATA) #define BIT_SET_ADDRCAM_WDATA(x, v) \ (BIT_CLEAR_ADDRCAM_WDATA(x) | BIT_ADDRCAM_WDATA(v)) /* 2 REG_ADDRCAM_READ_CONTENT (Offset 0x1670) */ #define BIT_SHIFT_ADDRCAM_RDATA 0 #define BIT_MASK_ADDRCAM_RDATA 0xffffffffL #define BIT_ADDRCAM_RDATA(x) \ (((x) & BIT_MASK_ADDRCAM_RDATA) << BIT_SHIFT_ADDRCAM_RDATA) #define BITS_ADDRCAM_RDATA (BIT_MASK_ADDRCAM_RDATA << BIT_SHIFT_ADDRCAM_RDATA) #define BIT_CLEAR_ADDRCAM_RDATA(x) ((x) & (~BITS_ADDRCAM_RDATA)) #define BIT_GET_ADDRCAM_RDATA(x) \ (((x) >> BIT_SHIFT_ADDRCAM_RDATA) & BIT_MASK_ADDRCAM_RDATA) #define BIT_SET_ADDRCAM_RDATA(x, v) \ (BIT_CLEAR_ADDRCAM_RDATA(x) | BIT_ADDRCAM_RDATA(v)) /* 2 REG_ADDRCAM_CFG (Offset 0x1674) */ #define BIT_ADDRCAM_POLL BIT(31) #define BIT__ADDRCAM_WT_EN BIT(30) #define BIT_CLRADDRCAM BIT(29) #define BIT_SHIFT__ADDRCAM_ADDR 8 #define BIT_MASK__ADDRCAM_ADDR 0x3ff #define BIT__ADDRCAM_ADDR(x) \ (((x) & BIT_MASK__ADDRCAM_ADDR) << BIT_SHIFT__ADDRCAM_ADDR) #define BITS__ADDRCAM_ADDR (BIT_MASK__ADDRCAM_ADDR << BIT_SHIFT__ADDRCAM_ADDR) #define BIT_CLEAR__ADDRCAM_ADDR(x) ((x) & (~BITS__ADDRCAM_ADDR)) #define BIT_GET__ADDRCAM_ADDR(x) \ (((x) >> BIT_SHIFT__ADDRCAM_ADDR) & BIT_MASK__ADDRCAM_ADDR) #define BIT_SET__ADDRCAM_ADDR(x, v) \ (BIT_CLEAR__ADDRCAM_ADDR(x) | BIT__ADDRCAM_ADDR(v)) #define BIT_SHIFT_ADDRCAM_RANGE 0 #define BIT_MASK_ADDRCAM_RANGE 0x7f #define BIT_ADDRCAM_RANGE(x) \ (((x) & BIT_MASK_ADDRCAM_RANGE) << BIT_SHIFT_ADDRCAM_RANGE) #define BITS_ADDRCAM_RANGE (BIT_MASK_ADDRCAM_RANGE << BIT_SHIFT_ADDRCAM_RANGE) #define BIT_CLEAR_ADDRCAM_RANGE(x) ((x) & (~BITS_ADDRCAM_RANGE)) #define BIT_GET_ADDRCAM_RANGE(x) \ (((x) >> BIT_SHIFT_ADDRCAM_RANGE) & BIT_MASK_ADDRCAM_RANGE) #define BIT_SET_ADDRCAM_RANGE(x, v) \ (BIT_CLEAR_ADDRCAM_RANGE(x) | BIT_ADDRCAM_RANGE(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_CSI_RRSR (Offset 0x1678) */ #define BIT_CSI_LDPC_EN BIT(29) #define BIT_CSI_STBC_EN BIT(28) #define BIT_SHIFT_CSI_RRSC_BITMAP 4 #define BIT_MASK_CSI_RRSC_BITMAP 0xffffff #define BIT_CSI_RRSC_BITMAP(x) \ (((x) & BIT_MASK_CSI_RRSC_BITMAP) << BIT_SHIFT_CSI_RRSC_BITMAP) #define BITS_CSI_RRSC_BITMAP \ (BIT_MASK_CSI_RRSC_BITMAP << BIT_SHIFT_CSI_RRSC_BITMAP) #define BIT_CLEAR_CSI_RRSC_BITMAP(x) ((x) & (~BITS_CSI_RRSC_BITMAP)) #define BIT_GET_CSI_RRSC_BITMAP(x) \ (((x) >> BIT_SHIFT_CSI_RRSC_BITMAP) & BIT_MASK_CSI_RRSC_BITMAP) #define BIT_SET_CSI_RRSC_BITMAP(x, v) \ (BIT_CLEAR_CSI_RRSC_BITMAP(x) | BIT_CSI_RRSC_BITMAP(v)) #define BIT_SHIFT_OFDM_LEN_TH 0 #define BIT_MASK_OFDM_LEN_TH 0xf #define BIT_OFDM_LEN_TH(x) \ (((x) & BIT_MASK_OFDM_LEN_TH) << BIT_SHIFT_OFDM_LEN_TH) #define BITS_OFDM_LEN_TH (BIT_MASK_OFDM_LEN_TH << BIT_SHIFT_OFDM_LEN_TH) #define BIT_CLEAR_OFDM_LEN_TH(x) ((x) & (~BITS_OFDM_LEN_TH)) #define BIT_GET_OFDM_LEN_TH(x) \ (((x) >> BIT_SHIFT_OFDM_LEN_TH) & BIT_MASK_OFDM_LEN_TH) #define BIT_SET_OFDM_LEN_TH(x, v) \ (BIT_CLEAR_OFDM_LEN_TH(x) | BIT_OFDM_LEN_TH(v)) #define BIT_SHIFT_WMAC_MULBK_PAGE_SIZE 0 #define BIT_MASK_WMAC_MULBK_PAGE_SIZE 0xff #define BIT_WMAC_MULBK_PAGE_SIZE(x) \ (((x) & BIT_MASK_WMAC_MULBK_PAGE_SIZE) \ << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE) #define BITS_WMAC_MULBK_PAGE_SIZE \ (BIT_MASK_WMAC_MULBK_PAGE_SIZE << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE) #define BIT_CLEAR_WMAC_MULBK_PAGE_SIZE(x) ((x) & (~BITS_WMAC_MULBK_PAGE_SIZE)) #define BIT_GET_WMAC_MULBK_PAGE_SIZE(x) \ (((x) >> BIT_SHIFT_WMAC_MULBK_PAGE_SIZE) & \ BIT_MASK_WMAC_MULBK_PAGE_SIZE) #define BIT_SET_WMAC_MULBK_PAGE_SIZE(x, v) \ (BIT_CLEAR_WMAC_MULBK_PAGE_SIZE(x) | BIT_WMAC_MULBK_PAGE_SIZE(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ #define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MU_BF_OPTION (Offset 0x167C) */ #define BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_PAUSE_BB_CLR_TH (Offset 0x167D) */ #define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH 0 #define BIT_MASK_WMAC_PAUSE_BB_CLR_TH 0xff #define BIT_WMAC_PAUSE_BB_CLR_TH(x) \ (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH) \ << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) #define BITS_WMAC_PAUSE_BB_CLR_TH \ (BIT_MASK_WMAC_PAUSE_BB_CLR_TH << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) #define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH(x) ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH)) #define BIT_GET_WMAC_PAUSE_BB_CLR_TH(x) \ (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) & \ BIT_MASK_WMAC_PAUSE_BB_CLR_TH) #define BIT_SET_WMAC_PAUSE_BB_CLR_TH(x, v) \ (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH(x) | BIT_WMAC_PAUSE_BB_CLR_TH(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_MU_ARB (Offset 0x167E) */ #define BIT_WMAC_ARB_HW_ADAPT_EN BIT(7) #define BIT_WMAC_ARB_SW_EN BIT(6) #define BIT_SHIFT_WMAC_ARB_SW_STATE 0 #define BIT_MASK_WMAC_ARB_SW_STATE 0x3f #define BIT_WMAC_ARB_SW_STATE(x) \ (((x) & BIT_MASK_WMAC_ARB_SW_STATE) << BIT_SHIFT_WMAC_ARB_SW_STATE) #define BITS_WMAC_ARB_SW_STATE \ (BIT_MASK_WMAC_ARB_SW_STATE << BIT_SHIFT_WMAC_ARB_SW_STATE) #define BIT_CLEAR_WMAC_ARB_SW_STATE(x) ((x) & (~BITS_WMAC_ARB_SW_STATE)) #define BIT_GET_WMAC_ARB_SW_STATE(x) \ (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE) & BIT_MASK_WMAC_ARB_SW_STATE) #define BIT_SET_WMAC_ARB_SW_STATE(x, v) \ (BIT_CLEAR_WMAC_ARB_SW_STATE(x) | BIT_WMAC_ARB_SW_STATE(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_WMAC_MU_OPTION (Offset 0x167F) */ #define BIT_NOCHK_BFPOLL_BMP BIT(7) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_MU_OPTION (Offset 0x167F) */ #define BIT_SHIFT_WMAC_MU_DBGSEL 5 #define BIT_MASK_WMAC_MU_DBGSEL 0x3 #define BIT_WMAC_MU_DBGSEL(x) \ (((x) & BIT_MASK_WMAC_MU_DBGSEL) << BIT_SHIFT_WMAC_MU_DBGSEL) #define BITS_WMAC_MU_DBGSEL \ (BIT_MASK_WMAC_MU_DBGSEL << BIT_SHIFT_WMAC_MU_DBGSEL) #define BIT_CLEAR_WMAC_MU_DBGSEL(x) ((x) & (~BITS_WMAC_MU_DBGSEL)) #define BIT_GET_WMAC_MU_DBGSEL(x) \ (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL) & BIT_MASK_WMAC_MU_DBGSEL) #define BIT_SET_WMAC_MU_DBGSEL(x, v) \ (BIT_CLEAR_WMAC_MU_DBGSEL(x) | BIT_WMAC_MU_DBGSEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_MU_OPTION (Offset 0x167F) */ #define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT 0 #define BIT_MASK_WMAC_MU_CPRD_TIMEOUT 0x1f #define BIT_WMAC_MU_CPRD_TIMEOUT(x) \ (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT) \ << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) #define BITS_WMAC_MU_CPRD_TIMEOUT \ (BIT_MASK_WMAC_MU_CPRD_TIMEOUT << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) #define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT(x) ((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT)) #define BIT_GET_WMAC_MU_CPRD_TIMEOUT(x) \ (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) & \ BIT_MASK_WMAC_MU_CPRD_TIMEOUT) #define BIT_SET_WMAC_MU_CPRD_TIMEOUT(x, v) \ (BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT(x) | BIT_WMAC_MU_CPRD_TIMEOUT(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_MU_BF_CTL (Offset 0x1680) */ #define BIT_WMAC_INVLD_BFPRT_CHK BIT(15) #define BIT_WMAC_RETXBFRPTSEQ_UPD BIT(14) #define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL 12 #define BIT_MASK_WMAC_MU_BFRPTSEG_SEL 0x3 #define BIT_WMAC_MU_BFRPTSEG_SEL(x) \ (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL) \ << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) #define BITS_WMAC_MU_BFRPTSEG_SEL \ (BIT_MASK_WMAC_MU_BFRPTSEG_SEL << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) #define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL(x) ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL)) #define BIT_GET_WMAC_MU_BFRPTSEG_SEL(x) \ (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) & \ BIT_MASK_WMAC_MU_BFRPTSEG_SEL) #define BIT_SET_WMAC_MU_BFRPTSEG_SEL(x, v) \ (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL(x) | BIT_WMAC_MU_BFRPTSEG_SEL(v)) #define BIT_SHIFT_WMAC_MU_BF_MYAID 0 #define BIT_MASK_WMAC_MU_BF_MYAID 0xfff #define BIT_WMAC_MU_BF_MYAID(x) \ (((x) & BIT_MASK_WMAC_MU_BF_MYAID) << BIT_SHIFT_WMAC_MU_BF_MYAID) #define BITS_WMAC_MU_BF_MYAID \ (BIT_MASK_WMAC_MU_BF_MYAID << BIT_SHIFT_WMAC_MU_BF_MYAID) #define BIT_CLEAR_WMAC_MU_BF_MYAID(x) ((x) & (~BITS_WMAC_MU_BF_MYAID)) #define BIT_GET_WMAC_MU_BF_MYAID(x) \ (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID) & BIT_MASK_WMAC_MU_BF_MYAID) #define BIT_SET_WMAC_MU_BF_MYAID(x, v) \ (BIT_CLEAR_WMAC_MU_BF_MYAID(x) | BIT_WMAC_MU_BF_MYAID(v)) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ #define BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1 13 #define BIT_MASK_BFRPT_PARA_USERID_SEL_V1 0x7 #define BIT_BFRPT_PARA_USERID_SEL_V1(x) \ (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_V1) \ << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1) #define BITS_BFRPT_PARA_USERID_SEL_V1 \ (BIT_MASK_BFRPT_PARA_USERID_SEL_V1 \ << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1) #define BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1(x) \ ((x) & (~BITS_BFRPT_PARA_USERID_SEL_V1)) #define BIT_GET_BFRPT_PARA_USERID_SEL_V1(x) \ (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1) & \ BIT_MASK_BFRPT_PARA_USERID_SEL_V1) #define BIT_SET_BFRPT_PARA_USERID_SEL_V1(x, v) \ (BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1(x) | \ BIT_BFRPT_PARA_USERID_SEL_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ #define BIT_SHIFT_BFRPT_PARA_USERID_SEL 12 #define BIT_MASK_BFRPT_PARA_USERID_SEL 0x7 #define BIT_BFRPT_PARA_USERID_SEL(x) \ (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL) \ << BIT_SHIFT_BFRPT_PARA_USERID_SEL) #define BITS_BFRPT_PARA_USERID_SEL \ (BIT_MASK_BFRPT_PARA_USERID_SEL << BIT_SHIFT_BFRPT_PARA_USERID_SEL) #define BIT_CLEAR_BFRPT_PARA_USERID_SEL(x) ((x) & (~BITS_BFRPT_PARA_USERID_SEL)) #define BIT_GET_BFRPT_PARA_USERID_SEL(x) \ (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL) & \ BIT_MASK_BFRPT_PARA_USERID_SEL) #define BIT_SET_BFRPT_PARA_USERID_SEL(x, v) \ (BIT_CLEAR_BFRPT_PARA_USERID_SEL(x) | BIT_BFRPT_PARA_USERID_SEL(v)) #endif #if (HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ #define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL 12 #define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL 0x7 #define BIT_BIT_BFRPT_PARA_USERID_SEL(x) \ (((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL) \ << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) #define BITS_BIT_BFRPT_PARA_USERID_SEL \ (BIT_MASK_BIT_BFRPT_PARA_USERID_SEL \ << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) #define BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL(x) \ ((x) & (~BITS_BIT_BFRPT_PARA_USERID_SEL)) #define BIT_GET_BIT_BFRPT_PARA_USERID_SEL(x) \ (((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) & \ BIT_MASK_BIT_BFRPT_PARA_USERID_SEL) #define BIT_SET_BIT_BFRPT_PARA_USERID_SEL(x, v) \ (BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL(x) | \ BIT_BIT_BFRPT_PARA_USERID_SEL(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ #define BIT_SHIFT_BFRPT_PARA 0 #define BIT_MASK_BFRPT_PARA 0xfff #define BIT_BFRPT_PARA(x) (((x) & BIT_MASK_BFRPT_PARA) << BIT_SHIFT_BFRPT_PARA) #define BITS_BFRPT_PARA (BIT_MASK_BFRPT_PARA << BIT_SHIFT_BFRPT_PARA) #define BIT_CLEAR_BFRPT_PARA(x) ((x) & (~BITS_BFRPT_PARA)) #define BIT_GET_BFRPT_PARA(x) \ (((x) >> BIT_SHIFT_BFRPT_PARA) & BIT_MASK_BFRPT_PARA) #define BIT_SET_BFRPT_PARA(x, v) (BIT_CLEAR_BFRPT_PARA(x) | BIT_BFRPT_PARA(v)) #endif #if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ #define BIT_SHIFT_BFRPT_PARA_V1 0 #define BIT_MASK_BFRPT_PARA_V1 0x1fff #define BIT_BFRPT_PARA_V1(x) \ (((x) & BIT_MASK_BFRPT_PARA_V1) << BIT_SHIFT_BFRPT_PARA_V1) #define BITS_BFRPT_PARA_V1 (BIT_MASK_BFRPT_PARA_V1 << BIT_SHIFT_BFRPT_PARA_V1) #define BIT_CLEAR_BFRPT_PARA_V1(x) ((x) & (~BITS_BFRPT_PARA_V1)) #define BIT_GET_BFRPT_PARA_V1(x) \ (((x) >> BIT_SHIFT_BFRPT_PARA_V1) & BIT_MASK_BFRPT_PARA_V1) #define BIT_SET_BFRPT_PARA_V1(x, v) \ (BIT_CLEAR_BFRPT_PARA_V1(x) | BIT_BFRPT_PARA_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */ #define BIT_STATUS_BFEE2 BIT(10) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */ #define BIT_WMAC_MU_BFEE2_EN BIT(9) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */ #define BIT_WMAC_MU_BFEE2_USER_EN BIT(9) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */ #define BIT_SHIFT_WMAC_MU_BFEE2_AID 0 #define BIT_MASK_WMAC_MU_BFEE2_AID 0x1ff #define BIT_WMAC_MU_BFEE2_AID(x) \ (((x) & BIT_MASK_WMAC_MU_BFEE2_AID) << BIT_SHIFT_WMAC_MU_BFEE2_AID) #define BITS_WMAC_MU_BFEE2_AID \ (BIT_MASK_WMAC_MU_BFEE2_AID << BIT_SHIFT_WMAC_MU_BFEE2_AID) #define BIT_CLEAR_WMAC_MU_BFEE2_AID(x) ((x) & (~BITS_WMAC_MU_BFEE2_AID)) #define BIT_GET_WMAC_MU_BFEE2_AID(x) \ (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID) & BIT_MASK_WMAC_MU_BFEE2_AID) #define BIT_SET_WMAC_MU_BFEE2_AID(x, v) \ (BIT_CLEAR_WMAC_MU_BFEE2_AID(x) | BIT_WMAC_MU_BFEE2_AID(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */ #define BIT_STATUS_BFEE3 BIT(10) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */ #define BIT_WMAC_MU_BFEE3_EN BIT(9) #endif #if (HALMAC_8198F_SUPPORT) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */ #define BIT_WMAC_MU_BFEE3_USER_EN BIT(9) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */ #define BIT_SHIFT_WMAC_MU_BFEE3_AID 0 #define BIT_MASK_WMAC_MU_BFEE3_AID 0x1ff #define BIT_WMAC_MU_BFEE3_AID(x) \ (((x) & BIT_MASK_WMAC_MU_BFEE3_AID) << BIT_SHIFT_WMAC_MU_BFEE3_AID) #define BITS_WMAC_MU_BFEE3_AID \ (BIT_MASK_WMAC_MU_BFEE3_AID << BIT_SHIFT_WMAC_MU_BFEE3_AID) #define BIT_CLEAR_WMAC_MU_BFEE3_AID(x) ((x) & (~BITS_WMAC_MU_BFEE3_AID)) #define BIT_GET_WMAC_MU_BFEE3_AID(x) \ (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID) & BIT_MASK_WMAC_MU_BFEE3_AID) #define BIT_SET_WMAC_MU_BFEE3_AID(x, v) \ (BIT_CLEAR_WMAC_MU_BFEE3_AID(x) | BIT_WMAC_MU_BFEE3_AID(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4 (Offset 0x1688) */ #define BIT_STATUS_BFEE4 BIT(10) #define BIT_WMAC_MU_BFEE4_EN BIT(9) #define BIT_SHIFT_WMAC_MU_BFEE4_AID 0 #define BIT_MASK_WMAC_MU_BFEE4_AID 0x1ff #define BIT_WMAC_MU_BFEE4_AID(x) \ (((x) & BIT_MASK_WMAC_MU_BFEE4_AID) << BIT_SHIFT_WMAC_MU_BFEE4_AID) #define BITS_WMAC_MU_BFEE4_AID \ (BIT_MASK_WMAC_MU_BFEE4_AID << BIT_SHIFT_WMAC_MU_BFEE4_AID) #define BIT_CLEAR_WMAC_MU_BFEE4_AID(x) ((x) & (~BITS_WMAC_MU_BFEE4_AID)) #define BIT_GET_WMAC_MU_BFEE4_AID(x) \ (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID) & BIT_MASK_WMAC_MU_BFEE4_AID) #define BIT_SET_WMAC_MU_BFEE4_AID(x, v) \ (BIT_CLEAR_WMAC_MU_BFEE4_AID(x) | BIT_WMAC_MU_BFEE4_AID(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ #define BIT_STATUS_BFEE5 BIT(10) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ #define BIT_BIT_STATUS_BFEE5 BIT(10) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ #define BIT_WMAC_MU_BFEE5_EN BIT(9) #define BIT_SHIFT_WMAC_MU_BFEE5_AID 0 #define BIT_MASK_WMAC_MU_BFEE5_AID 0x1ff #define BIT_WMAC_MU_BFEE5_AID(x) \ (((x) & BIT_MASK_WMAC_MU_BFEE5_AID) << BIT_SHIFT_WMAC_MU_BFEE5_AID) #define BITS_WMAC_MU_BFEE5_AID \ (BIT_MASK_WMAC_MU_BFEE5_AID << BIT_SHIFT_WMAC_MU_BFEE5_AID) #define BIT_CLEAR_WMAC_MU_BFEE5_AID(x) ((x) & (~BITS_WMAC_MU_BFEE5_AID)) #define BIT_GET_WMAC_MU_BFEE5_AID(x) \ (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID) & BIT_MASK_WMAC_MU_BFEE5_AID) #define BIT_SET_WMAC_MU_BFEE5_AID(x, v) \ (BIT_CLEAR_WMAC_MU_BFEE5_AID(x) | BIT_WMAC_MU_BFEE5_AID(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6 (Offset 0x168C) */ #define BIT_STATUS_BFEE6 BIT(10) #define BIT_WMAC_MU_BFEE6_EN BIT(9) #define BIT_SHIFT_WMAC_MU_BFEE6_AID 0 #define BIT_MASK_WMAC_MU_BFEE6_AID 0x1ff #define BIT_WMAC_MU_BFEE6_AID(x) \ (((x) & BIT_MASK_WMAC_MU_BFEE6_AID) << BIT_SHIFT_WMAC_MU_BFEE6_AID) #define BITS_WMAC_MU_BFEE6_AID \ (BIT_MASK_WMAC_MU_BFEE6_AID << BIT_SHIFT_WMAC_MU_BFEE6_AID) #define BIT_CLEAR_WMAC_MU_BFEE6_AID(x) ((x) & (~BITS_WMAC_MU_BFEE6_AID)) #define BIT_GET_WMAC_MU_BFEE6_AID(x) \ (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID) & BIT_MASK_WMAC_MU_BFEE6_AID) #define BIT_SET_WMAC_MU_BFEE6_AID(x, v) \ (BIT_CLEAR_WMAC_MU_BFEE6_AID(x) | BIT_WMAC_MU_BFEE6_AID(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */ #define BIT_BIT_STATUS_BFEE4 BIT(10) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */ #define BIT_STATUS_BFEE7 BIT(10) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */ #define BIT_WMAC_MU_BFEE7_EN BIT(9) #define BIT_SHIFT_WMAC_MU_BFEE7_AID 0 #define BIT_MASK_WMAC_MU_BFEE7_AID 0x1ff #define BIT_WMAC_MU_BFEE7_AID(x) \ (((x) & BIT_MASK_WMAC_MU_BFEE7_AID) << BIT_SHIFT_WMAC_MU_BFEE7_AID) #define BITS_WMAC_MU_BFEE7_AID \ (BIT_MASK_WMAC_MU_BFEE7_AID << BIT_SHIFT_WMAC_MU_BFEE7_AID) #define BIT_CLEAR_WMAC_MU_BFEE7_AID(x) ((x) & (~BITS_WMAC_MU_BFEE7_AID)) #define BIT_GET_WMAC_MU_BFEE7_AID(x) \ (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID) & BIT_MASK_WMAC_MU_BFEE7_AID) #define BIT_SET_WMAC_MU_BFEE7_AID(x, v) \ (BIT_CLEAR_WMAC_MU_BFEE7_AID(x) | BIT_WMAC_MU_BFEE7_AID(v)) /* 2 REG_WMAC_BB_STOP_RX_COUNTER (Offset 0x1690) */ #define BIT_RST_ALL_COUNTER BIT(31) #define BIT_SHIFT_ABORT_RX_VBON_COUNTER 16 #define BIT_MASK_ABORT_RX_VBON_COUNTER 0xff #define BIT_ABORT_RX_VBON_COUNTER(x) \ (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER) \ << BIT_SHIFT_ABORT_RX_VBON_COUNTER) #define BITS_ABORT_RX_VBON_COUNTER \ (BIT_MASK_ABORT_RX_VBON_COUNTER << BIT_SHIFT_ABORT_RX_VBON_COUNTER) #define BIT_CLEAR_ABORT_RX_VBON_COUNTER(x) ((x) & (~BITS_ABORT_RX_VBON_COUNTER)) #define BIT_GET_ABORT_RX_VBON_COUNTER(x) \ (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER) & \ BIT_MASK_ABORT_RX_VBON_COUNTER) #define BIT_SET_ABORT_RX_VBON_COUNTER(x, v) \ (BIT_CLEAR_ABORT_RX_VBON_COUNTER(x) | BIT_ABORT_RX_VBON_COUNTER(v)) #define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER 8 #define BIT_MASK_ABORT_RX_RDRDY_COUNTER 0xff #define BIT_ABORT_RX_RDRDY_COUNTER(x) \ (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER) \ << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) #define BITS_ABORT_RX_RDRDY_COUNTER \ (BIT_MASK_ABORT_RX_RDRDY_COUNTER << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) #define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER(x) \ ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER)) #define BIT_GET_ABORT_RX_RDRDY_COUNTER(x) \ (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) & \ BIT_MASK_ABORT_RX_RDRDY_COUNTER) #define BIT_SET_ABORT_RX_RDRDY_COUNTER(x, v) \ (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER(x) | BIT_ABORT_RX_RDRDY_COUNTER(v)) #define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER 0 #define BIT_MASK_VBON_EARLY_FALLING_COUNTER 0xff #define BIT_VBON_EARLY_FALLING_COUNTER(x) \ (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER) \ << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) #define BITS_VBON_EARLY_FALLING_COUNTER \ (BIT_MASK_VBON_EARLY_FALLING_COUNTER \ << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) #define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER(x) \ ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER)) #define BIT_GET_VBON_EARLY_FALLING_COUNTER(x) \ (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) & \ BIT_MASK_VBON_EARLY_FALLING_COUNTER) #define BIT_SET_VBON_EARLY_FALLING_COUNTER(x, v) \ (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER(x) | \ BIT_VBON_EARLY_FALLING_COUNTER(v)) /* 2 REG_WMAC_PLCP_MONITOR (Offset 0x1694) */ #define BIT_WMAC_PLCP_TRX_SEL BIT(31) #define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL 28 #define BIT_MASK_WMAC_PLCP_RDSIG_SEL 0x7 #define BIT_WMAC_PLCP_RDSIG_SEL(x) \ (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) #define BITS_WMAC_PLCP_RDSIG_SEL \ (BIT_MASK_WMAC_PLCP_RDSIG_SEL << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) #define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL)) #define BIT_GET_WMAC_PLCP_RDSIG_SEL(x) \ (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) #define BIT_SET_WMAC_PLCP_RDSIG_SEL(x, v) \ (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL(x) | BIT_WMAC_PLCP_RDSIG_SEL(v)) #define BIT_SHIFT_WMAC_RATE_IDX 24 #define BIT_MASK_WMAC_RATE_IDX 0xf #define BIT_WMAC_RATE_IDX(x) \ (((x) & BIT_MASK_WMAC_RATE_IDX) << BIT_SHIFT_WMAC_RATE_IDX) #define BITS_WMAC_RATE_IDX (BIT_MASK_WMAC_RATE_IDX << BIT_SHIFT_WMAC_RATE_IDX) #define BIT_CLEAR_WMAC_RATE_IDX(x) ((x) & (~BITS_WMAC_RATE_IDX)) #define BIT_GET_WMAC_RATE_IDX(x) \ (((x) >> BIT_SHIFT_WMAC_RATE_IDX) & BIT_MASK_WMAC_RATE_IDX) #define BIT_SET_WMAC_RATE_IDX(x, v) \ (BIT_CLEAR_WMAC_RATE_IDX(x) | BIT_WMAC_RATE_IDX(v)) #define BIT_SHIFT_WMAC_PLCP_RDSIG 0 #define BIT_MASK_WMAC_PLCP_RDSIG 0xffffff #define BIT_WMAC_PLCP_RDSIG(x) \ (((x) & BIT_MASK_WMAC_PLCP_RDSIG) << BIT_SHIFT_WMAC_PLCP_RDSIG) #define BITS_WMAC_PLCP_RDSIG \ (BIT_MASK_WMAC_PLCP_RDSIG << BIT_SHIFT_WMAC_PLCP_RDSIG) #define BIT_CLEAR_WMAC_PLCP_RDSIG(x) ((x) & (~BITS_WMAC_PLCP_RDSIG)) #define BIT_GET_WMAC_PLCP_RDSIG(x) \ (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG) & BIT_MASK_WMAC_PLCP_RDSIG) #define BIT_SET_WMAC_PLCP_RDSIG(x, v) \ (BIT_CLEAR_WMAC_PLCP_RDSIG(x) | BIT_WMAC_PLCP_RDSIG(v)) #endif #if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_PLCP_MONITOR_MUTX (Offset 0x1698) */ #define BIT_WMAC_MUTX_IDX BIT(24) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_WMAC_DEBUG_PORT (Offset 0x1698) */ #define BIT_SHIFT_WMAC_DEBUG_PORT 0 #define BIT_MASK_WMAC_DEBUG_PORT 0xffffffffL #define BIT_WMAC_DEBUG_PORT(x) \ (((x) & BIT_MASK_WMAC_DEBUG_PORT) << BIT_SHIFT_WMAC_DEBUG_PORT) #define BITS_WMAC_DEBUG_PORT \ (BIT_MASK_WMAC_DEBUG_PORT << BIT_SHIFT_WMAC_DEBUG_PORT) #define BIT_CLEAR_WMAC_DEBUG_PORT(x) ((x) & (~BITS_WMAC_DEBUG_PORT)) #define BIT_GET_WMAC_DEBUG_PORT(x) \ (((x) >> BIT_SHIFT_WMAC_DEBUG_PORT) & BIT_MASK_WMAC_DEBUG_PORT) #define BIT_SET_WMAC_DEBUG_PORT(x, v) \ (BIT_CLEAR_WMAC_DEBUG_PORT(x) | BIT_WMAC_DEBUG_PORT(v)) #endif #if (HALMAC_8822C_SUPPORT) /* 2 REG_WMAC_CSIDMA_CFG (Offset 0x169C) */ #define BIT_SHIFT_CSI_SEG_SIZE 16 #define BIT_MASK_CSI_SEG_SIZE 0xfff #define BIT_CSI_SEG_SIZE(x) \ (((x) & BIT_MASK_CSI_SEG_SIZE) << BIT_SHIFT_CSI_SEG_SIZE) #define BITS_CSI_SEG_SIZE (BIT_MASK_CSI_SEG_SIZE << BIT_SHIFT_CSI_SEG_SIZE) #define BIT_CLEAR_CSI_SEG_SIZE(x) ((x) & (~BITS_CSI_SEG_SIZE)) #define BIT_GET_CSI_SEG_SIZE(x) \ (((x) >> BIT_SHIFT_CSI_SEG_SIZE) & BIT_MASK_CSI_SEG_SIZE) #define BIT_SET_CSI_SEG_SIZE(x, v) \ (BIT_CLEAR_CSI_SEG_SIZE(x) | BIT_CSI_SEG_SIZE(v)) #define BIT_SHIFT_CSI_START_PAGE 0 #define BIT_MASK_CSI_START_PAGE 0xfff #define BIT_CSI_START_PAGE(x) \ (((x) & BIT_MASK_CSI_START_PAGE) << BIT_SHIFT_CSI_START_PAGE) #define BITS_CSI_START_PAGE \ (BIT_MASK_CSI_START_PAGE << BIT_SHIFT_CSI_START_PAGE) #define BIT_CLEAR_CSI_START_PAGE(x) ((x) & (~BITS_CSI_START_PAGE)) #define BIT_GET_CSI_START_PAGE(x) \ (((x) >> BIT_SHIFT_CSI_START_PAGE) & BIT_MASK_CSI_START_PAGE) #define BIT_SET_CSI_START_PAGE(x, v) \ (BIT_CLEAR_CSI_START_PAGE(x) | BIT_CSI_START_PAGE(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TRANSMIT_ADDRSS_0 (Offset 0x16A0) */ #define BIT_SHIFT_TA0 0 #define BIT_MASK_TA0 0xffffffffffffL #define BIT_TA0(x) (((x) & BIT_MASK_TA0) << BIT_SHIFT_TA0) #define BITS_TA0 (BIT_MASK_TA0 << BIT_SHIFT_TA0) #define BIT_CLEAR_TA0(x) ((x) & (~BITS_TA0)) #define BIT_GET_TA0(x) (((x) >> BIT_SHIFT_TA0) & BIT_MASK_TA0) #define BIT_SET_TA0(x, v) (BIT_CLEAR_TA0(x) | BIT_TA0(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TRANSMIT_ADDRSS_0 (Offset 0x16A0) */ #define BIT_SHIFT_TA0_V1 0 #define BIT_MASK_TA0_V1 0xffffffffL #define BIT_TA0_V1(x) (((x) & BIT_MASK_TA0_V1) << BIT_SHIFT_TA0_V1) #define BITS_TA0_V1 (BIT_MASK_TA0_V1 << BIT_SHIFT_TA0_V1) #define BIT_CLEAR_TA0_V1(x) ((x) & (~BITS_TA0_V1)) #define BIT_GET_TA0_V1(x) (((x) >> BIT_SHIFT_TA0_V1) & BIT_MASK_TA0_V1) #define BIT_SET_TA0_V1(x, v) (BIT_CLEAR_TA0_V1(x) | BIT_TA0_V1(v)) /* 2 REG_TRANSMIT_ADDRSS_0_H (Offset 0x16A4) */ #define BIT_SHIFT_TA0_H_V1 0 #define BIT_MASK_TA0_H_V1 0xffff #define BIT_TA0_H_V1(x) (((x) & BIT_MASK_TA0_H_V1) << BIT_SHIFT_TA0_H_V1) #define BITS_TA0_H_V1 (BIT_MASK_TA0_H_V1 << BIT_SHIFT_TA0_H_V1) #define BIT_CLEAR_TA0_H_V1(x) ((x) & (~BITS_TA0_H_V1)) #define BIT_GET_TA0_H_V1(x) (((x) >> BIT_SHIFT_TA0_H_V1) & BIT_MASK_TA0_H_V1) #define BIT_SET_TA0_H_V1(x, v) (BIT_CLEAR_TA0_H_V1(x) | BIT_TA0_H_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TRANSMIT_ADDRSS_1 (Offset 0x16A8) */ #define BIT_SHIFT_TA1 0 #define BIT_MASK_TA1 0xffffffffffffL #define BIT_TA1(x) (((x) & BIT_MASK_TA1) << BIT_SHIFT_TA1) #define BITS_TA1 (BIT_MASK_TA1 << BIT_SHIFT_TA1) #define BIT_CLEAR_TA1(x) ((x) & (~BITS_TA1)) #define BIT_GET_TA1(x) (((x) >> BIT_SHIFT_TA1) & BIT_MASK_TA1) #define BIT_SET_TA1(x, v) (BIT_CLEAR_TA1(x) | BIT_TA1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TRANSMIT_ADDRSS_1 (Offset 0x16A8) */ #define BIT_SHIFT_TA1_V1 0 #define BIT_MASK_TA1_V1 0xffffffffL #define BIT_TA1_V1(x) (((x) & BIT_MASK_TA1_V1) << BIT_SHIFT_TA1_V1) #define BITS_TA1_V1 (BIT_MASK_TA1_V1 << BIT_SHIFT_TA1_V1) #define BIT_CLEAR_TA1_V1(x) ((x) & (~BITS_TA1_V1)) #define BIT_GET_TA1_V1(x) (((x) >> BIT_SHIFT_TA1_V1) & BIT_MASK_TA1_V1) #define BIT_SET_TA1_V1(x, v) (BIT_CLEAR_TA1_V1(x) | BIT_TA1_V1(v)) /* 2 REG_TRANSMIT_ADDRSS_1_H (Offset 0x16AC) */ #define BIT_SHIFT_TA1_H_V1 0 #define BIT_MASK_TA1_H_V1 0xffff #define BIT_TA1_H_V1(x) (((x) & BIT_MASK_TA1_H_V1) << BIT_SHIFT_TA1_H_V1) #define BITS_TA1_H_V1 (BIT_MASK_TA1_H_V1 << BIT_SHIFT_TA1_H_V1) #define BIT_CLEAR_TA1_H_V1(x) ((x) & (~BITS_TA1_H_V1)) #define BIT_GET_TA1_H_V1(x) (((x) >> BIT_SHIFT_TA1_H_V1) & BIT_MASK_TA1_H_V1) #define BIT_SET_TA1_H_V1(x, v) (BIT_CLEAR_TA1_H_V1(x) | BIT_TA1_H_V1(v)) #define BIT_SHIFT_TA2_V1 0 #define BIT_MASK_TA2_V1 0xffffffffL #define BIT_TA2_V1(x) (((x) & BIT_MASK_TA2_V1) << BIT_SHIFT_TA2_V1) #define BITS_TA2_V1 (BIT_MASK_TA2_V1 << BIT_SHIFT_TA2_V1) #define BIT_CLEAR_TA2_V1(x) ((x) & (~BITS_TA2_V1)) #define BIT_GET_TA2_V1(x) (((x) >> BIT_SHIFT_TA2_V1) & BIT_MASK_TA2_V1) #define BIT_SET_TA2_V1(x, v) (BIT_CLEAR_TA2_V1(x) | BIT_TA2_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TRANSMIT_ADDRSS_2 (Offset 0x16B0) */ #define BIT_SHIFT_TA2 0 #define BIT_MASK_TA2 0xffffffffffffL #define BIT_TA2(x) (((x) & BIT_MASK_TA2) << BIT_SHIFT_TA2) #define BITS_TA2 (BIT_MASK_TA2 << BIT_SHIFT_TA2) #define BIT_CLEAR_TA2(x) ((x) & (~BITS_TA2)) #define BIT_GET_TA2(x) (((x) >> BIT_SHIFT_TA2) & BIT_MASK_TA2) #define BIT_SET_TA2(x, v) (BIT_CLEAR_TA2(x) | BIT_TA2(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TRANSMIT_ADDRSS_2_H (Offset 0x16B4) */ #define BIT_SHIFT_TA2_H_V1 0 #define BIT_MASK_TA2_H_V1 0xffff #define BIT_TA2_H_V1(x) (((x) & BIT_MASK_TA2_H_V1) << BIT_SHIFT_TA2_H_V1) #define BITS_TA2_H_V1 (BIT_MASK_TA2_H_V1 << BIT_SHIFT_TA2_H_V1) #define BIT_CLEAR_TA2_H_V1(x) ((x) & (~BITS_TA2_H_V1)) #define BIT_GET_TA2_H_V1(x) (((x) >> BIT_SHIFT_TA2_H_V1) & BIT_MASK_TA2_H_V1) #define BIT_SET_TA2_H_V1(x, v) (BIT_CLEAR_TA2_H_V1(x) | BIT_TA2_H_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TRANSMIT_ADDRSS_3 (Offset 0x16B8) */ #define BIT_SHIFT_TA3 0 #define BIT_MASK_TA3 0xffffffffffffL #define BIT_TA3(x) (((x) & BIT_MASK_TA3) << BIT_SHIFT_TA3) #define BITS_TA3 (BIT_MASK_TA3 << BIT_SHIFT_TA3) #define BIT_CLEAR_TA3(x) ((x) & (~BITS_TA3)) #define BIT_GET_TA3(x) (((x) >> BIT_SHIFT_TA3) & BIT_MASK_TA3) #define BIT_SET_TA3(x, v) (BIT_CLEAR_TA3(x) | BIT_TA3(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TRANSMIT_ADDRSS_3_H (Offset 0x16BC) */ #define BIT_SHIFT_TA3_H_V1 0 #define BIT_MASK_TA3_H_V1 0xffff #define BIT_TA3_H_V1(x) (((x) & BIT_MASK_TA3_H_V1) << BIT_SHIFT_TA3_H_V1) #define BITS_TA3_H_V1 (BIT_MASK_TA3_H_V1 << BIT_SHIFT_TA3_H_V1) #define BIT_CLEAR_TA3_H_V1(x) ((x) & (~BITS_TA3_H_V1)) #define BIT_GET_TA3_H_V1(x) (((x) >> BIT_SHIFT_TA3_H_V1) & BIT_MASK_TA3_H_V1) #define BIT_SET_TA3_H_V1(x, v) (BIT_CLEAR_TA3_H_V1(x) | BIT_TA3_H_V1(v)) #endif #if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TRANSMIT_ADDRSS_4 (Offset 0x16C0) */ #define BIT_R_WMAC_RX_SYNCFIFO_SYNC BIT(55) #define BIT_R_WMAC_RXRST_DLY BIT(54) #define BIT_R_WMAC_SRCH_TXRPT_REF_DROP BIT(53) #define BIT_R_WMAC_SRCH_TXRPT_UA1 BIT(52) #define BIT_SHIFT_TA4 0 #define BIT_MASK_TA4 0xffffffffffffL #define BIT_TA4(x) (((x) & BIT_MASK_TA4) << BIT_SHIFT_TA4) #define BITS_TA4 (BIT_MASK_TA4 << BIT_SHIFT_TA4) #define BIT_CLEAR_TA4(x) ((x) & (~BITS_TA4)) #define BIT_GET_TA4(x) (((x) >> BIT_SHIFT_TA4) & BIT_MASK_TA4) #define BIT_SET_TA4(x, v) (BIT_CLEAR_TA4(x) | BIT_TA4(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_TRANSMIT_ADDRSS_4 (Offset 0x16C0) */ #define BIT_SHIFT_TA4_V1 0 #define BIT_MASK_TA4_V1 0xffffffffL #define BIT_TA4_V1(x) (((x) & BIT_MASK_TA4_V1) << BIT_SHIFT_TA4_V1) #define BITS_TA4_V1 (BIT_MASK_TA4_V1 << BIT_SHIFT_TA4_V1) #define BIT_CLEAR_TA4_V1(x) ((x) & (~BITS_TA4_V1)) #define BIT_GET_TA4_V1(x) (((x) >> BIT_SHIFT_TA4_V1) & BIT_MASK_TA4_V1) #define BIT_SET_TA4_V1(x, v) (BIT_CLEAR_TA4_V1(x) | BIT_TA4_V1(v)) /* 2 REG_TRANSMIT_ADDRSS_4_H (Offset 0x16C4) */ #define BIT_SHIFT_TA4_H_V1 0 #define BIT_MASK_TA4_H_V1 0xffff #define BIT_TA4_H_V1(x) (((x) & BIT_MASK_TA4_H_V1) << BIT_SHIFT_TA4_H_V1) #define BITS_TA4_H_V1 (BIT_MASK_TA4_H_V1 << BIT_SHIFT_TA4_H_V1) #define BIT_CLEAR_TA4_H_V1(x) ((x) & (~BITS_TA4_H_V1)) #define BIT_GET_TA4_H_V1(x) (((x) >> BIT_SHIFT_TA4_H_V1) & BIT_MASK_TA4_H_V1) #define BIT_SET_TA4_H_V1(x, v) (BIT_CLEAR_TA4_H_V1(x) | BIT_TA4_H_V1(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ HALMAC_8822C_SUPPORT) /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 (Offset 0x1700) */ #define BIT_LTECOEX_ACCESS_START_V1 BIT(31) #define BIT_LTECOEX_WRITE_MODE_V1 BIT(30) #define BIT_LTECOEX_READY_BIT_V1 BIT(29) #define BIT_SHIFT_WRITE_BYTE_EN_V1 16 #define BIT_MASK_WRITE_BYTE_EN_V1 0xf #define BIT_WRITE_BYTE_EN_V1(x) \ (((x) & BIT_MASK_WRITE_BYTE_EN_V1) << BIT_SHIFT_WRITE_BYTE_EN_V1) #define BITS_WRITE_BYTE_EN_V1 \ (BIT_MASK_WRITE_BYTE_EN_V1 << BIT_SHIFT_WRITE_BYTE_EN_V1) #define BIT_CLEAR_WRITE_BYTE_EN_V1(x) ((x) & (~BITS_WRITE_BYTE_EN_V1)) #define BIT_GET_WRITE_BYTE_EN_V1(x) \ (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1) & BIT_MASK_WRITE_BYTE_EN_V1) #define BIT_SET_WRITE_BYTE_EN_V1(x, v) \ (BIT_CLEAR_WRITE_BYTE_EN_V1(x) | BIT_WRITE_BYTE_EN_V1(v)) #define BIT_SHIFT_LTECOEX_REG_ADDR_V1 0 #define BIT_MASK_LTECOEX_REG_ADDR_V1 0xffff #define BIT_LTECOEX_REG_ADDR_V1(x) \ (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1) << BIT_SHIFT_LTECOEX_REG_ADDR_V1) #define BITS_LTECOEX_REG_ADDR_V1 \ (BIT_MASK_LTECOEX_REG_ADDR_V1 << BIT_SHIFT_LTECOEX_REG_ADDR_V1) #define BIT_CLEAR_LTECOEX_REG_ADDR_V1(x) ((x) & (~BITS_LTECOEX_REG_ADDR_V1)) #define BIT_GET_LTECOEX_REG_ADDR_V1(x) \ (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1) & BIT_MASK_LTECOEX_REG_ADDR_V1) #define BIT_SET_LTECOEX_REG_ADDR_V1(x, v) \ (BIT_CLEAR_LTECOEX_REG_ADDR_V1(x) | BIT_LTECOEX_REG_ADDR_V1(v)) /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 (Offset 0x1704) */ #define BIT_SHIFT_LTECOEX_W_DATA_V1 0 #define BIT_MASK_LTECOEX_W_DATA_V1 0xffffffffL #define BIT_LTECOEX_W_DATA_V1(x) \ (((x) & BIT_MASK_LTECOEX_W_DATA_V1) << BIT_SHIFT_LTECOEX_W_DATA_V1) #define BITS_LTECOEX_W_DATA_V1 \ (BIT_MASK_LTECOEX_W_DATA_V1 << BIT_SHIFT_LTECOEX_W_DATA_V1) #define BIT_CLEAR_LTECOEX_W_DATA_V1(x) ((x) & (~BITS_LTECOEX_W_DATA_V1)) #define BIT_GET_LTECOEX_W_DATA_V1(x) \ (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1) & BIT_MASK_LTECOEX_W_DATA_V1) #define BIT_SET_LTECOEX_W_DATA_V1(x, v) \ (BIT_CLEAR_LTECOEX_W_DATA_V1(x) | BIT_LTECOEX_W_DATA_V1(v)) /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 (Offset 0x1708) */ #define BIT_SHIFT_LTECOEX_R_DATA_V1 0 #define BIT_MASK_LTECOEX_R_DATA_V1 0xffffffffL #define BIT_LTECOEX_R_DATA_V1(x) \ (((x) & BIT_MASK_LTECOEX_R_DATA_V1) << BIT_SHIFT_LTECOEX_R_DATA_V1) #define BITS_LTECOEX_R_DATA_V1 \ (BIT_MASK_LTECOEX_R_DATA_V1 << BIT_SHIFT_LTECOEX_R_DATA_V1) #define BIT_CLEAR_LTECOEX_R_DATA_V1(x) ((x) & (~BITS_LTECOEX_R_DATA_V1)) #define BIT_GET_LTECOEX_R_DATA_V1(x) \ (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1) & BIT_MASK_LTECOEX_R_DATA_V1) #define BIT_SET_LTECOEX_R_DATA_V1(x, v) \ (BIT_CLEAR_LTECOEX_R_DATA_V1(x) | BIT_LTECOEX_R_DATA_V1(v)) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_DMA_RQPN_INFO_0 (Offset 0x2200) */ #define BIT_SHIFT_CH0_AVAL_PG 16 #define BIT_MASK_CH0_AVAL_PG 0xfff #define BIT_CH0_AVAL_PG(x) \ (((x) & BIT_MASK_CH0_AVAL_PG) << BIT_SHIFT_CH0_AVAL_PG) #define BITS_CH0_AVAL_PG (BIT_MASK_CH0_AVAL_PG << BIT_SHIFT_CH0_AVAL_PG) #define BIT_CLEAR_CH0_AVAL_PG(x) ((x) & (~BITS_CH0_AVAL_PG)) #define BIT_GET_CH0_AVAL_PG(x) \ (((x) >> BIT_SHIFT_CH0_AVAL_PG) & BIT_MASK_CH0_AVAL_PG) #define BIT_SET_CH0_AVAL_PG(x, v) \ (BIT_CLEAR_CH0_AVAL_PG(x) | BIT_CH0_AVAL_PG(v)) #define BIT_SHIFT_CH0_RSVD_PG 0 #define BIT_MASK_CH0_RSVD_PG 0xfff #define BIT_CH0_RSVD_PG(x) \ (((x) & BIT_MASK_CH0_RSVD_PG) << BIT_SHIFT_CH0_RSVD_PG) #define BITS_CH0_RSVD_PG (BIT_MASK_CH0_RSVD_PG << BIT_SHIFT_CH0_RSVD_PG) #define BIT_CLEAR_CH0_RSVD_PG(x) ((x) & (~BITS_CH0_RSVD_PG)) #define BIT_GET_CH0_RSVD_PG(x) \ (((x) >> BIT_SHIFT_CH0_RSVD_PG) & BIT_MASK_CH0_RSVD_PG) #define BIT_SET_CH0_RSVD_PG(x, v) \ (BIT_CLEAR_CH0_RSVD_PG(x) | BIT_CH0_RSVD_PG(v)) /* 2 REG_DMA_RQPN_INFO_1 (Offset 0x2204) */ #define BIT_SHIFT_CH1_AVAL_PG 16 #define BIT_MASK_CH1_AVAL_PG 0xfff #define BIT_CH1_AVAL_PG(x) \ (((x) & BIT_MASK_CH1_AVAL_PG) << BIT_SHIFT_CH1_AVAL_PG) #define BITS_CH1_AVAL_PG (BIT_MASK_CH1_AVAL_PG << BIT_SHIFT_CH1_AVAL_PG) #define BIT_CLEAR_CH1_AVAL_PG(x) ((x) & (~BITS_CH1_AVAL_PG)) #define BIT_GET_CH1_AVAL_PG(x) \ (((x) >> BIT_SHIFT_CH1_AVAL_PG) & BIT_MASK_CH1_AVAL_PG) #define BIT_SET_CH1_AVAL_PG(x, v) \ (BIT_CLEAR_CH1_AVAL_PG(x) | BIT_CH1_AVAL_PG(v)) #define BIT_SHIFT_CH1_RSVD_PG 0 #define BIT_MASK_CH1_RSVD_PG 0xfff #define BIT_CH1_RSVD_PG(x) \ (((x) & BIT_MASK_CH1_RSVD_PG) << BIT_SHIFT_CH1_RSVD_PG) #define BITS_CH1_RSVD_PG (BIT_MASK_CH1_RSVD_PG << BIT_SHIFT_CH1_RSVD_PG) #define BIT_CLEAR_CH1_RSVD_PG(x) ((x) & (~BITS_CH1_RSVD_PG)) #define BIT_GET_CH1_RSVD_PG(x) \ (((x) >> BIT_SHIFT_CH1_RSVD_PG) & BIT_MASK_CH1_RSVD_PG) #define BIT_SET_CH1_RSVD_PG(x, v) \ (BIT_CLEAR_CH1_RSVD_PG(x) | BIT_CH1_RSVD_PG(v)) /* 2 REG_DMA_RQPN_INFO_2 (Offset 0x2208) */ #define BIT_SHIFT_CH2_AVAL_PG 16 #define BIT_MASK_CH2_AVAL_PG 0xfff #define BIT_CH2_AVAL_PG(x) \ (((x) & BIT_MASK_CH2_AVAL_PG) << BIT_SHIFT_CH2_AVAL_PG) #define BITS_CH2_AVAL_PG (BIT_MASK_CH2_AVAL_PG << BIT_SHIFT_CH2_AVAL_PG) #define BIT_CLEAR_CH2_AVAL_PG(x) ((x) & (~BITS_CH2_AVAL_PG)) #define BIT_GET_CH2_AVAL_PG(x) \ (((x) >> BIT_SHIFT_CH2_AVAL_PG) & BIT_MASK_CH2_AVAL_PG) #define BIT_SET_CH2_AVAL_PG(x, v) \ (BIT_CLEAR_CH2_AVAL_PG(x) | BIT_CH2_AVAL_PG(v)) #define BIT_SHIFT_CH2_RSVD_PG 0 #define BIT_MASK_CH2_RSVD_PG 0xfff #define BIT_CH2_RSVD_PG(x) \ (((x) & BIT_MASK_CH2_RSVD_PG) << BIT_SHIFT_CH2_RSVD_PG) #define BITS_CH2_RSVD_PG (BIT_MASK_CH2_RSVD_PG << BIT_SHIFT_CH2_RSVD_PG) #define BIT_CLEAR_CH2_RSVD_PG(x) ((x) & (~BITS_CH2_RSVD_PG)) #define BIT_GET_CH2_RSVD_PG(x) \ (((x) >> BIT_SHIFT_CH2_RSVD_PG) & BIT_MASK_CH2_RSVD_PG) #define BIT_SET_CH2_RSVD_PG(x, v) \ (BIT_CLEAR_CH2_RSVD_PG(x) | BIT_CH2_RSVD_PG(v)) /* 2 REG_DMA_RQPN_INFO_3 (Offset 0x220C) */ #define BIT_SHIFT_CH3_AVAL_PG 16 #define BIT_MASK_CH3_AVAL_PG 0xfff #define BIT_CH3_AVAL_PG(x) \ (((x) & BIT_MASK_CH3_AVAL_PG) << BIT_SHIFT_CH3_AVAL_PG) #define BITS_CH3_AVAL_PG (BIT_MASK_CH3_AVAL_PG << BIT_SHIFT_CH3_AVAL_PG) #define BIT_CLEAR_CH3_AVAL_PG(x) ((x) & (~BITS_CH3_AVAL_PG)) #define BIT_GET_CH3_AVAL_PG(x) \ (((x) >> BIT_SHIFT_CH3_AVAL_PG) & BIT_MASK_CH3_AVAL_PG) #define BIT_SET_CH3_AVAL_PG(x, v) \ (BIT_CLEAR_CH3_AVAL_PG(x) | BIT_CH3_AVAL_PG(v)) #define BIT_SHIFT_CH3_RSVD_PG 0 #define BIT_MASK_CH3_RSVD_PG 0xfff #define BIT_CH3_RSVD_PG(x) \ (((x) & BIT_MASK_CH3_RSVD_PG) << BIT_SHIFT_CH3_RSVD_PG) #define BITS_CH3_RSVD_PG (BIT_MASK_CH3_RSVD_PG << BIT_SHIFT_CH3_RSVD_PG) #define BIT_CLEAR_CH3_RSVD_PG(x) ((x) & (~BITS_CH3_RSVD_PG)) #define BIT_GET_CH3_RSVD_PG(x) \ (((x) >> BIT_SHIFT_CH3_RSVD_PG) & BIT_MASK_CH3_RSVD_PG) #define BIT_SET_CH3_RSVD_PG(x, v) \ (BIT_CLEAR_CH3_RSVD_PG(x) | BIT_CH3_RSVD_PG(v)) /* 2 REG_DMA_RQPN_INFO_4 (Offset 0x2210) */ #define BIT_SHIFT_CH4_AVAL_PG 16 #define BIT_MASK_CH4_AVAL_PG 0xfff #define BIT_CH4_AVAL_PG(x) \ (((x) & BIT_MASK_CH4_AVAL_PG) << BIT_SHIFT_CH4_AVAL_PG) #define BITS_CH4_AVAL_PG (BIT_MASK_CH4_AVAL_PG << BIT_SHIFT_CH4_AVAL_PG) #define BIT_CLEAR_CH4_AVAL_PG(x) ((x) & (~BITS_CH4_AVAL_PG)) #define BIT_GET_CH4_AVAL_PG(x) \ (((x) >> BIT_SHIFT_CH4_AVAL_PG) & BIT_MASK_CH4_AVAL_PG) #define BIT_SET_CH4_AVAL_PG(x, v) \ (BIT_CLEAR_CH4_AVAL_PG(x) | BIT_CH4_AVAL_PG(v)) #define BIT_SHIFT_CH4_RSVD_PG 0 #define BIT_MASK_CH4_RSVD_PG 0xfff #define BIT_CH4_RSVD_PG(x) \ (((x) & BIT_MASK_CH4_RSVD_PG) << BIT_SHIFT_CH4_RSVD_PG) #define BITS_CH4_RSVD_PG (BIT_MASK_CH4_RSVD_PG << BIT_SHIFT_CH4_RSVD_PG) #define BIT_CLEAR_CH4_RSVD_PG(x) ((x) & (~BITS_CH4_RSVD_PG)) #define BIT_GET_CH4_RSVD_PG(x) \ (((x) >> BIT_SHIFT_CH4_RSVD_PG) & BIT_MASK_CH4_RSVD_PG) #define BIT_SET_CH4_RSVD_PG(x, v) \ (BIT_CLEAR_CH4_RSVD_PG(x) | BIT_CH4_RSVD_PG(v)) /* 2 REG_DMA_RQPN_INFO_5 (Offset 0x2214) */ #define BIT_SHIFT_CH5_AVAL_PG 16 #define BIT_MASK_CH5_AVAL_PG 0xfff #define BIT_CH5_AVAL_PG(x) \ (((x) & BIT_MASK_CH5_AVAL_PG) << BIT_SHIFT_CH5_AVAL_PG) #define BITS_CH5_AVAL_PG (BIT_MASK_CH5_AVAL_PG << BIT_SHIFT_CH5_AVAL_PG) #define BIT_CLEAR_CH5_AVAL_PG(x) ((x) & (~BITS_CH5_AVAL_PG)) #define BIT_GET_CH5_AVAL_PG(x) \ (((x) >> BIT_SHIFT_CH5_AVAL_PG) & BIT_MASK_CH5_AVAL_PG) #define BIT_SET_CH5_AVAL_PG(x, v) \ (BIT_CLEAR_CH5_AVAL_PG(x) | BIT_CH5_AVAL_PG(v)) #define BIT_SHIFT_CH5_RSVD_PG 0 #define BIT_MASK_CH5_RSVD_PG 0xfff #define BIT_CH5_RSVD_PG(x) \ (((x) & BIT_MASK_CH5_RSVD_PG) << BIT_SHIFT_CH5_RSVD_PG) #define BITS_CH5_RSVD_PG (BIT_MASK_CH5_RSVD_PG << BIT_SHIFT_CH5_RSVD_PG) #define BIT_CLEAR_CH5_RSVD_PG(x) ((x) & (~BITS_CH5_RSVD_PG)) #define BIT_GET_CH5_RSVD_PG(x) \ (((x) >> BIT_SHIFT_CH5_RSVD_PG) & BIT_MASK_CH5_RSVD_PG) #define BIT_SET_CH5_RSVD_PG(x, v) \ (BIT_CLEAR_CH5_RSVD_PG(x) | BIT_CH5_RSVD_PG(v)) /* 2 REG_DMA_RQPN_INFO_6 (Offset 0x2218) */ #define BIT_SHIFT_CH6_AVAL_PG 16 #define BIT_MASK_CH6_AVAL_PG 0xfff #define BIT_CH6_AVAL_PG(x) \ (((x) & BIT_MASK_CH6_AVAL_PG) << BIT_SHIFT_CH6_AVAL_PG) #define BITS_CH6_AVAL_PG (BIT_MASK_CH6_AVAL_PG << BIT_SHIFT_CH6_AVAL_PG) #define BIT_CLEAR_CH6_AVAL_PG(x) ((x) & (~BITS_CH6_AVAL_PG)) #define BIT_GET_CH6_AVAL_PG(x) \ (((x) >> BIT_SHIFT_CH6_AVAL_PG) & BIT_MASK_CH6_AVAL_PG) #define BIT_SET_CH6_AVAL_PG(x, v) \ (BIT_CLEAR_CH6_AVAL_PG(x) | BIT_CH6_AVAL_PG(v)) #define BIT_SHIFT_CH6_RSVD_PG 0 #define BIT_MASK_CH6_RSVD_PG 0xfff #define BIT_CH6_RSVD_PG(x) \ (((x) & BIT_MASK_CH6_RSVD_PG) << BIT_SHIFT_CH6_RSVD_PG) #define BITS_CH6_RSVD_PG (BIT_MASK_CH6_RSVD_PG << BIT_SHIFT_CH6_RSVD_PG) #define BIT_CLEAR_CH6_RSVD_PG(x) ((x) & (~BITS_CH6_RSVD_PG)) #define BIT_GET_CH6_RSVD_PG(x) \ (((x) >> BIT_SHIFT_CH6_RSVD_PG) & BIT_MASK_CH6_RSVD_PG) #define BIT_SET_CH6_RSVD_PG(x, v) \ (BIT_CLEAR_CH6_RSVD_PG(x) | BIT_CH6_RSVD_PG(v)) /* 2 REG_DMA_RQPN_INFO_7 (Offset 0x221C) */ #define BIT_SHIFT_CH7_AVAL_PG 16 #define BIT_MASK_CH7_AVAL_PG 0xfff #define BIT_CH7_AVAL_PG(x) \ (((x) & BIT_MASK_CH7_AVAL_PG) << BIT_SHIFT_CH7_AVAL_PG) #define BITS_CH7_AVAL_PG (BIT_MASK_CH7_AVAL_PG << BIT_SHIFT_CH7_AVAL_PG) #define BIT_CLEAR_CH7_AVAL_PG(x) ((x) & (~BITS_CH7_AVAL_PG)) #define BIT_GET_CH7_AVAL_PG(x) \ (((x) >> BIT_SHIFT_CH7_AVAL_PG) & BIT_MASK_CH7_AVAL_PG) #define BIT_SET_CH7_AVAL_PG(x, v) \ (BIT_CLEAR_CH7_AVAL_PG(x) | BIT_CH7_AVAL_PG(v)) #define BIT_SHIFT_CH7_RSVD_PG 0 #define BIT_MASK_CH7_RSVD_PG 0xfff #define BIT_CH7_RSVD_PG(x) \ (((x) & BIT_MASK_CH7_RSVD_PG) << BIT_SHIFT_CH7_RSVD_PG) #define BITS_CH7_RSVD_PG (BIT_MASK_CH7_RSVD_PG << BIT_SHIFT_CH7_RSVD_PG) #define BIT_CLEAR_CH7_RSVD_PG(x) ((x) & (~BITS_CH7_RSVD_PG)) #define BIT_GET_CH7_RSVD_PG(x) \ (((x) >> BIT_SHIFT_CH7_RSVD_PG) & BIT_MASK_CH7_RSVD_PG) #define BIT_SET_CH7_RSVD_PG(x, v) \ (BIT_CLEAR_CH7_RSVD_PG(x) | BIT_CH7_RSVD_PG(v)) /* 2 REG_DMA_RQPN_INFO_8 (Offset 0x2220) */ #define BIT_SHIFT_CH8_AVAL_PG 16 #define BIT_MASK_CH8_AVAL_PG 0xfff #define BIT_CH8_AVAL_PG(x) \ (((x) & BIT_MASK_CH8_AVAL_PG) << BIT_SHIFT_CH8_AVAL_PG) #define BITS_CH8_AVAL_PG (BIT_MASK_CH8_AVAL_PG << BIT_SHIFT_CH8_AVAL_PG) #define BIT_CLEAR_CH8_AVAL_PG(x) ((x) & (~BITS_CH8_AVAL_PG)) #define BIT_GET_CH8_AVAL_PG(x) \ (((x) >> BIT_SHIFT_CH8_AVAL_PG) & BIT_MASK_CH8_AVAL_PG) #define BIT_SET_CH8_AVAL_PG(x, v) \ (BIT_CLEAR_CH8_AVAL_PG(x) | BIT_CH8_AVAL_PG(v)) #define BIT_SHIFT_CH8_RSVD_PG 0 #define BIT_MASK_CH8_RSVD_PG 0xfff #define BIT_CH8_RSVD_PG(x) \ (((x) & BIT_MASK_CH8_RSVD_PG) << BIT_SHIFT_CH8_RSVD_PG) #define BITS_CH8_RSVD_PG (BIT_MASK_CH8_RSVD_PG << BIT_SHIFT_CH8_RSVD_PG) #define BIT_CLEAR_CH8_RSVD_PG(x) ((x) & (~BITS_CH8_RSVD_PG)) #define BIT_GET_CH8_RSVD_PG(x) \ (((x) >> BIT_SHIFT_CH8_RSVD_PG) & BIT_MASK_CH8_RSVD_PG) #define BIT_SET_CH8_RSVD_PG(x, v) \ (BIT_CLEAR_CH8_RSVD_PG(x) | BIT_CH8_RSVD_PG(v)) /* 2 REG_DMA_RQPN_INFO_9 (Offset 0x2224) */ #define BIT_SHIFT_CH9_AVAL_PG 16 #define BIT_MASK_CH9_AVAL_PG 0xfff #define BIT_CH9_AVAL_PG(x) \ (((x) & BIT_MASK_CH9_AVAL_PG) << BIT_SHIFT_CH9_AVAL_PG) #define BITS_CH9_AVAL_PG (BIT_MASK_CH9_AVAL_PG << BIT_SHIFT_CH9_AVAL_PG) #define BIT_CLEAR_CH9_AVAL_PG(x) ((x) & (~BITS_CH9_AVAL_PG)) #define BIT_GET_CH9_AVAL_PG(x) \ (((x) >> BIT_SHIFT_CH9_AVAL_PG) & BIT_MASK_CH9_AVAL_PG) #define BIT_SET_CH9_AVAL_PG(x, v) \ (BIT_CLEAR_CH9_AVAL_PG(x) | BIT_CH9_AVAL_PG(v)) #define BIT_SHIFT_CH9_RSVD_PG 0 #define BIT_MASK_CH9_RSVD_PG 0xfff #define BIT_CH9_RSVD_PG(x) \ (((x) & BIT_MASK_CH9_RSVD_PG) << BIT_SHIFT_CH9_RSVD_PG) #define BITS_CH9_RSVD_PG (BIT_MASK_CH9_RSVD_PG << BIT_SHIFT_CH9_RSVD_PG) #define BIT_CLEAR_CH9_RSVD_PG(x) ((x) & (~BITS_CH9_RSVD_PG)) #define BIT_GET_CH9_RSVD_PG(x) \ (((x) >> BIT_SHIFT_CH9_RSVD_PG) & BIT_MASK_CH9_RSVD_PG) #define BIT_SET_CH9_RSVD_PG(x, v) \ (BIT_CLEAR_CH9_RSVD_PG(x) | BIT_CH9_RSVD_PG(v)) /* 2 REG_DMA_RQPN_INFO_10 (Offset 0x2228) */ #define BIT_SHIFT_CH10_AVAL_PG 16 #define BIT_MASK_CH10_AVAL_PG 0xfff #define BIT_CH10_AVAL_PG(x) \ (((x) & BIT_MASK_CH10_AVAL_PG) << BIT_SHIFT_CH10_AVAL_PG) #define BITS_CH10_AVAL_PG (BIT_MASK_CH10_AVAL_PG << BIT_SHIFT_CH10_AVAL_PG) #define BIT_CLEAR_CH10_AVAL_PG(x) ((x) & (~BITS_CH10_AVAL_PG)) #define BIT_GET_CH10_AVAL_PG(x) \ (((x) >> BIT_SHIFT_CH10_AVAL_PG) & BIT_MASK_CH10_AVAL_PG) #define BIT_SET_CH10_AVAL_PG(x, v) \ (BIT_CLEAR_CH10_AVAL_PG(x) | BIT_CH10_AVAL_PG(v)) #define BIT_SHIFT_CH10_RSVD_PG 0 #define BIT_MASK_CH10_RSVD_PG 0xfff #define BIT_CH10_RSVD_PG(x) \ (((x) & BIT_MASK_CH10_RSVD_PG) << BIT_SHIFT_CH10_RSVD_PG) #define BITS_CH10_RSVD_PG (BIT_MASK_CH10_RSVD_PG << BIT_SHIFT_CH10_RSVD_PG) #define BIT_CLEAR_CH10_RSVD_PG(x) ((x) & (~BITS_CH10_RSVD_PG)) #define BIT_GET_CH10_RSVD_PG(x) \ (((x) >> BIT_SHIFT_CH10_RSVD_PG) & BIT_MASK_CH10_RSVD_PG) #define BIT_SET_CH10_RSVD_PG(x, v) \ (BIT_CLEAR_CH10_RSVD_PG(x) | BIT_CH10_RSVD_PG(v)) /* 2 REG_DMA_RQPN_INFO_11 (Offset 0x222C) */ #define BIT_SHIFT_CH11_AVAL_PG 16 #define BIT_MASK_CH11_AVAL_PG 0xfff #define BIT_CH11_AVAL_PG(x) \ (((x) & BIT_MASK_CH11_AVAL_PG) << BIT_SHIFT_CH11_AVAL_PG) #define BITS_CH11_AVAL_PG (BIT_MASK_CH11_AVAL_PG << BIT_SHIFT_CH11_AVAL_PG) #define BIT_CLEAR_CH11_AVAL_PG(x) ((x) & (~BITS_CH11_AVAL_PG)) #define BIT_GET_CH11_AVAL_PG(x) \ (((x) >> BIT_SHIFT_CH11_AVAL_PG) & BIT_MASK_CH11_AVAL_PG) #define BIT_SET_CH11_AVAL_PG(x, v) \ (BIT_CLEAR_CH11_AVAL_PG(x) | BIT_CH11_AVAL_PG(v)) #define BIT_SHIFT_CH11_RSVD_PG 0 #define BIT_MASK_CH11_RSVD_PG 0xfff #define BIT_CH11_RSVD_PG(x) \ (((x) & BIT_MASK_CH11_RSVD_PG) << BIT_SHIFT_CH11_RSVD_PG) #define BITS_CH11_RSVD_PG (BIT_MASK_CH11_RSVD_PG << BIT_SHIFT_CH11_RSVD_PG) #define BIT_CLEAR_CH11_RSVD_PG(x) ((x) & (~BITS_CH11_RSVD_PG)) #define BIT_GET_CH11_RSVD_PG(x) \ (((x) >> BIT_SHIFT_CH11_RSVD_PG) & BIT_MASK_CH11_RSVD_PG) #define BIT_SET_CH11_RSVD_PG(x, v) \ (BIT_CLEAR_CH11_RSVD_PG(x) | BIT_CH11_RSVD_PG(v)) /* 2 REG_DMA_RQPN_INFO_12 (Offset 0x2230) */ #define BIT_SHIFT_CH12_AVAL_PG 16 #define BIT_MASK_CH12_AVAL_PG 0xfff #define BIT_CH12_AVAL_PG(x) \ (((x) & BIT_MASK_CH12_AVAL_PG) << BIT_SHIFT_CH12_AVAL_PG) #define BITS_CH12_AVAL_PG (BIT_MASK_CH12_AVAL_PG << BIT_SHIFT_CH12_AVAL_PG) #define BIT_CLEAR_CH12_AVAL_PG(x) ((x) & (~BITS_CH12_AVAL_PG)) #define BIT_GET_CH12_AVAL_PG(x) \ (((x) >> BIT_SHIFT_CH12_AVAL_PG) & BIT_MASK_CH12_AVAL_PG) #define BIT_SET_CH12_AVAL_PG(x, v) \ (BIT_CLEAR_CH12_AVAL_PG(x) | BIT_CH12_AVAL_PG(v)) #define BIT_SHIFT_CH12_RSVD_PG 0 #define BIT_MASK_CH12_RSVD_PG 0xfff #define BIT_CH12_RSVD_PG(x) \ (((x) & BIT_MASK_CH12_RSVD_PG) << BIT_SHIFT_CH12_RSVD_PG) #define BITS_CH12_RSVD_PG (BIT_MASK_CH12_RSVD_PG << BIT_SHIFT_CH12_RSVD_PG) #define BIT_CLEAR_CH12_RSVD_PG(x) ((x) & (~BITS_CH12_RSVD_PG)) #define BIT_GET_CH12_RSVD_PG(x) \ (((x) >> BIT_SHIFT_CH12_RSVD_PG) & BIT_MASK_CH12_RSVD_PG) #define BIT_SET_CH12_RSVD_PG(x, v) \ (BIT_CLEAR_CH12_RSVD_PG(x) | BIT_CH12_RSVD_PG(v)) /* 2 REG_DMA_RQPN_INFO_13 (Offset 0x2234) */ #define BIT_SHIFT_CH13_AVAL_PG 16 #define BIT_MASK_CH13_AVAL_PG 0xfff #define BIT_CH13_AVAL_PG(x) \ (((x) & BIT_MASK_CH13_AVAL_PG) << BIT_SHIFT_CH13_AVAL_PG) #define BITS_CH13_AVAL_PG (BIT_MASK_CH13_AVAL_PG << BIT_SHIFT_CH13_AVAL_PG) #define BIT_CLEAR_CH13_AVAL_PG(x) ((x) & (~BITS_CH13_AVAL_PG)) #define BIT_GET_CH13_AVAL_PG(x) \ (((x) >> BIT_SHIFT_CH13_AVAL_PG) & BIT_MASK_CH13_AVAL_PG) #define BIT_SET_CH13_AVAL_PG(x, v) \ (BIT_CLEAR_CH13_AVAL_PG(x) | BIT_CH13_AVAL_PG(v)) #define BIT_SHIFT_CH13_RSVD_PG 0 #define BIT_MASK_CH13_RSVD_PG 0xfff #define BIT_CH13_RSVD_PG(x) \ (((x) & BIT_MASK_CH13_RSVD_PG) << BIT_SHIFT_CH13_RSVD_PG) #define BITS_CH13_RSVD_PG (BIT_MASK_CH13_RSVD_PG << BIT_SHIFT_CH13_RSVD_PG) #define BIT_CLEAR_CH13_RSVD_PG(x) ((x) & (~BITS_CH13_RSVD_PG)) #define BIT_GET_CH13_RSVD_PG(x) \ (((x) >> BIT_SHIFT_CH13_RSVD_PG) & BIT_MASK_CH13_RSVD_PG) #define BIT_SET_CH13_RSVD_PG(x, v) \ (BIT_CLEAR_CH13_RSVD_PG(x) | BIT_CH13_RSVD_PG(v)) /* 2 REG_DMA_RQPN_INFO_14 (Offset 0x2238) */ #define BIT_SHIFT_CH14_AVAL_PG 16 #define BIT_MASK_CH14_AVAL_PG 0xfff #define BIT_CH14_AVAL_PG(x) \ (((x) & BIT_MASK_CH14_AVAL_PG) << BIT_SHIFT_CH14_AVAL_PG) #define BITS_CH14_AVAL_PG (BIT_MASK_CH14_AVAL_PG << BIT_SHIFT_CH14_AVAL_PG) #define BIT_CLEAR_CH14_AVAL_PG(x) ((x) & (~BITS_CH14_AVAL_PG)) #define BIT_GET_CH14_AVAL_PG(x) \ (((x) >> BIT_SHIFT_CH14_AVAL_PG) & BIT_MASK_CH14_AVAL_PG) #define BIT_SET_CH14_AVAL_PG(x, v) \ (BIT_CLEAR_CH14_AVAL_PG(x) | BIT_CH14_AVAL_PG(v)) #define BIT_SHIFT_CH14_RSVD_PG 0 #define BIT_MASK_CH14_RSVD_PG 0xfff #define BIT_CH14_RSVD_PG(x) \ (((x) & BIT_MASK_CH14_RSVD_PG) << BIT_SHIFT_CH14_RSVD_PG) #define BITS_CH14_RSVD_PG (BIT_MASK_CH14_RSVD_PG << BIT_SHIFT_CH14_RSVD_PG) #define BIT_CLEAR_CH14_RSVD_PG(x) ((x) & (~BITS_CH14_RSVD_PG)) #define BIT_GET_CH14_RSVD_PG(x) \ (((x) >> BIT_SHIFT_CH14_RSVD_PG) & BIT_MASK_CH14_RSVD_PG) #define BIT_SET_CH14_RSVD_PG(x, v) \ (BIT_CLEAR_CH14_RSVD_PG(x) | BIT_CH14_RSVD_PG(v)) /* 2 REG_DMA_RQPN_INFO_15 (Offset 0x223C) */ #define BIT_SHIFT_CH15_AVAL_PG 16 #define BIT_MASK_CH15_AVAL_PG 0xfff #define BIT_CH15_AVAL_PG(x) \ (((x) & BIT_MASK_CH15_AVAL_PG) << BIT_SHIFT_CH15_AVAL_PG) #define BITS_CH15_AVAL_PG (BIT_MASK_CH15_AVAL_PG << BIT_SHIFT_CH15_AVAL_PG) #define BIT_CLEAR_CH15_AVAL_PG(x) ((x) & (~BITS_CH15_AVAL_PG)) #define BIT_GET_CH15_AVAL_PG(x) \ (((x) >> BIT_SHIFT_CH15_AVAL_PG) & BIT_MASK_CH15_AVAL_PG) #define BIT_SET_CH15_AVAL_PG(x, v) \ (BIT_CLEAR_CH15_AVAL_PG(x) | BIT_CH15_AVAL_PG(v)) #define BIT_SHIFT_CH15_RSVD_PG 0 #define BIT_MASK_CH15_RSVD_PG 0xfff #define BIT_CH15_RSVD_PG(x) \ (((x) & BIT_MASK_CH15_RSVD_PG) << BIT_SHIFT_CH15_RSVD_PG) #define BITS_CH15_RSVD_PG (BIT_MASK_CH15_RSVD_PG << BIT_SHIFT_CH15_RSVD_PG) #define BIT_CLEAR_CH15_RSVD_PG(x) ((x) & (~BITS_CH15_RSVD_PG)) #define BIT_GET_CH15_RSVD_PG(x) \ (((x) >> BIT_SHIFT_CH15_RSVD_PG) & BIT_MASK_CH15_RSVD_PG) #define BIT_SET_CH15_RSVD_PG(x, v) \ (BIT_CLEAR_CH15_RSVD_PG(x) | BIT_CH15_RSVD_PG(v)) /* 2 REG_DMA_RQPN_INFO_16 (Offset 0x2240) */ #define BIT_SHIFT_CH16_AVAL_PG 16 #define BIT_MASK_CH16_AVAL_PG 0xfff #define BIT_CH16_AVAL_PG(x) \ (((x) & BIT_MASK_CH16_AVAL_PG) << BIT_SHIFT_CH16_AVAL_PG) #define BITS_CH16_AVAL_PG (BIT_MASK_CH16_AVAL_PG << BIT_SHIFT_CH16_AVAL_PG) #define BIT_CLEAR_CH16_AVAL_PG(x) ((x) & (~BITS_CH16_AVAL_PG)) #define BIT_GET_CH16_AVAL_PG(x) \ (((x) >> BIT_SHIFT_CH16_AVAL_PG) & BIT_MASK_CH16_AVAL_PG) #define BIT_SET_CH16_AVAL_PG(x, v) \ (BIT_CLEAR_CH16_AVAL_PG(x) | BIT_CH16_AVAL_PG(v)) #define BIT_SHIFT_CH16_RSVD_PG 0 #define BIT_MASK_CH16_RSVD_PG 0xfff #define BIT_CH16_RSVD_PG(x) \ (((x) & BIT_MASK_CH16_RSVD_PG) << BIT_SHIFT_CH16_RSVD_PG) #define BITS_CH16_RSVD_PG (BIT_MASK_CH16_RSVD_PG << BIT_SHIFT_CH16_RSVD_PG) #define BIT_CLEAR_CH16_RSVD_PG(x) ((x) & (~BITS_CH16_RSVD_PG)) #define BIT_GET_CH16_RSVD_PG(x) \ (((x) >> BIT_SHIFT_CH16_RSVD_PG) & BIT_MASK_CH16_RSVD_PG) #define BIT_SET_CH16_RSVD_PG(x, v) \ (BIT_CLEAR_CH16_RSVD_PG(x) | BIT_CH16_RSVD_PG(v)) /* 2 REG_HWAMSDU_CTL1 (Offset 0x2250) */ #define BIT_SHIFT_HWAMSDU_PKTNUM 8 #define BIT_MASK_HWAMSDU_PKTNUM 0x3f #define BIT_HWAMSDU_PKTNUM(x) \ (((x) & BIT_MASK_HWAMSDU_PKTNUM) << BIT_SHIFT_HWAMSDU_PKTNUM) #define BITS_HWAMSDU_PKTNUM \ (BIT_MASK_HWAMSDU_PKTNUM << BIT_SHIFT_HWAMSDU_PKTNUM) #define BIT_CLEAR_HWAMSDU_PKTNUM(x) ((x) & (~BITS_HWAMSDU_PKTNUM)) #define BIT_GET_HWAMSDU_PKTNUM(x) \ (((x) >> BIT_SHIFT_HWAMSDU_PKTNUM) & BIT_MASK_HWAMSDU_PKTNUM) #define BIT_SET_HWAMSDU_PKTNUM(x, v) \ (BIT_CLEAR_HWAMSDU_PKTNUM(x) | BIT_HWAMSDU_PKTNUM(v)) #define BIT_HWAMSDU_BUSY BIT(7) #define BIT_SINGLE_AMSDU BIT(2) #define BIT_HWAMSDU_PADDING_MODE BIT(1) #define BIT_HWAMSDU_EN BIT(0) /* 2 REG_HWAMSDU_CTL2 (Offset 0x2254) */ #define BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT 16 #define BIT_MASK_HWAMSDU_AMSDU_TIMEOUT 0xffff #define BIT_HWAMSDU_AMSDU_TIMEOUT(x) \ (((x) & BIT_MASK_HWAMSDU_AMSDU_TIMEOUT) \ << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT) #define BITS_HWAMSDU_AMSDU_TIMEOUT \ (BIT_MASK_HWAMSDU_AMSDU_TIMEOUT << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT) #define BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT(x) ((x) & (~BITS_HWAMSDU_AMSDU_TIMEOUT)) #define BIT_GET_HWAMSDU_AMSDU_TIMEOUT(x) \ (((x) >> BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT) & \ BIT_MASK_HWAMSDU_AMSDU_TIMEOUT) #define BIT_SET_HWAMSDU_AMSDU_TIMEOUT(x, v) \ (BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT(x) | BIT_HWAMSDU_AMSDU_TIMEOUT(v)) #define BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT 0 #define BIT_MASK_HWAMSDU_MSDU_TIMEOUT 0xffff #define BIT_HWAMSDU_MSDU_TIMEOUT(x) \ (((x) & BIT_MASK_HWAMSDU_MSDU_TIMEOUT) \ << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT) #define BITS_HWAMSDU_MSDU_TIMEOUT \ (BIT_MASK_HWAMSDU_MSDU_TIMEOUT << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT) #define BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT(x) ((x) & (~BITS_HWAMSDU_MSDU_TIMEOUT)) #define BIT_GET_HWAMSDU_MSDU_TIMEOUT(x) \ (((x) >> BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT) & \ BIT_MASK_HWAMSDU_MSDU_TIMEOUT) #define BIT_SET_HWAMSDU_MSDU_TIMEOUT(x, v) \ (BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT(x) | BIT_HWAMSDU_MSDU_TIMEOUT(v)) /* 2 REG_HI8Q_TXBD_DESA_L (Offset 0x2300) */ #define BIT_SHIFT_HI8Q_TXBD_DESA_L 0 #define BIT_MASK_HI8Q_TXBD_DESA_L 0xffffffffL #define BIT_HI8Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI8Q_TXBD_DESA_L) << BIT_SHIFT_HI8Q_TXBD_DESA_L) #define BITS_HI8Q_TXBD_DESA_L \ (BIT_MASK_HI8Q_TXBD_DESA_L << BIT_SHIFT_HI8Q_TXBD_DESA_L) #define BIT_CLEAR_HI8Q_TXBD_DESA_L(x) ((x) & (~BITS_HI8Q_TXBD_DESA_L)) #define BIT_GET_HI8Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_L) & BIT_MASK_HI8Q_TXBD_DESA_L) #define BIT_SET_HI8Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI8Q_TXBD_DESA_L(x) | BIT_HI8Q_TXBD_DESA_L(v)) /* 2 REG_HI8Q_TXBD_DESA_H (Offset 0x2304) */ #define BIT_SHIFT_HI8Q_TXBD_DESA_H 0 #define BIT_MASK_HI8Q_TXBD_DESA_H 0xffffffffL #define BIT_HI8Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI8Q_TXBD_DESA_H) << BIT_SHIFT_HI8Q_TXBD_DESA_H) #define BITS_HI8Q_TXBD_DESA_H \ (BIT_MASK_HI8Q_TXBD_DESA_H << BIT_SHIFT_HI8Q_TXBD_DESA_H) #define BIT_CLEAR_HI8Q_TXBD_DESA_H(x) ((x) & (~BITS_HI8Q_TXBD_DESA_H)) #define BIT_GET_HI8Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_H) & BIT_MASK_HI8Q_TXBD_DESA_H) #define BIT_SET_HI8Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI8Q_TXBD_DESA_H(x) | BIT_HI8Q_TXBD_DESA_H(v)) /* 2 REG_HI9Q_TXBD_DESA_L (Offset 0x2308) */ #define BIT_SHIFT_HI9Q_TXBD_DESA_L 0 #define BIT_MASK_HI9Q_TXBD_DESA_L 0xffffffffL #define BIT_HI9Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI9Q_TXBD_DESA_L) << BIT_SHIFT_HI9Q_TXBD_DESA_L) #define BITS_HI9Q_TXBD_DESA_L \ (BIT_MASK_HI9Q_TXBD_DESA_L << BIT_SHIFT_HI9Q_TXBD_DESA_L) #define BIT_CLEAR_HI9Q_TXBD_DESA_L(x) ((x) & (~BITS_HI9Q_TXBD_DESA_L)) #define BIT_GET_HI9Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_L) & BIT_MASK_HI9Q_TXBD_DESA_L) #define BIT_SET_HI9Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI9Q_TXBD_DESA_L(x) | BIT_HI9Q_TXBD_DESA_L(v)) /* 2 REG_HI9Q_TXBD_DESA_H (Offset 0x230C) */ #define BIT_SHIFT_HI9Q_TXBD_DESA_H 0 #define BIT_MASK_HI9Q_TXBD_DESA_H 0xffffffffL #define BIT_HI9Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI9Q_TXBD_DESA_H) << BIT_SHIFT_HI9Q_TXBD_DESA_H) #define BITS_HI9Q_TXBD_DESA_H \ (BIT_MASK_HI9Q_TXBD_DESA_H << BIT_SHIFT_HI9Q_TXBD_DESA_H) #define BIT_CLEAR_HI9Q_TXBD_DESA_H(x) ((x) & (~BITS_HI9Q_TXBD_DESA_H)) #define BIT_GET_HI9Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_H) & BIT_MASK_HI9Q_TXBD_DESA_H) #define BIT_SET_HI9Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI9Q_TXBD_DESA_H(x) | BIT_HI9Q_TXBD_DESA_H(v)) /* 2 REG_HI10Q_TXBD_DESA_L (Offset 0x2310) */ #define BIT_SHIFT_HI10Q_TXBD_DESA_L 0 #define BIT_MASK_HI10Q_TXBD_DESA_L 0xffffffffL #define BIT_HI10Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI10Q_TXBD_DESA_L) << BIT_SHIFT_HI10Q_TXBD_DESA_L) #define BITS_HI10Q_TXBD_DESA_L \ (BIT_MASK_HI10Q_TXBD_DESA_L << BIT_SHIFT_HI10Q_TXBD_DESA_L) #define BIT_CLEAR_HI10Q_TXBD_DESA_L(x) ((x) & (~BITS_HI10Q_TXBD_DESA_L)) #define BIT_GET_HI10Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_L) & BIT_MASK_HI10Q_TXBD_DESA_L) #define BIT_SET_HI10Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI10Q_TXBD_DESA_L(x) | BIT_HI10Q_TXBD_DESA_L(v)) /* 2 REG_HI10Q_TXBD_DESA_H (Offset 0x2314) */ #define BIT_SHIFT_HI10Q_TXBD_DESA_H 0 #define BIT_MASK_HI10Q_TXBD_DESA_H 0xffffffffL #define BIT_HI10Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI10Q_TXBD_DESA_H) << BIT_SHIFT_HI10Q_TXBD_DESA_H) #define BITS_HI10Q_TXBD_DESA_H \ (BIT_MASK_HI10Q_TXBD_DESA_H << BIT_SHIFT_HI10Q_TXBD_DESA_H) #define BIT_CLEAR_HI10Q_TXBD_DESA_H(x) ((x) & (~BITS_HI10Q_TXBD_DESA_H)) #define BIT_GET_HI10Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_H) & BIT_MASK_HI10Q_TXBD_DESA_H) #define BIT_SET_HI10Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI10Q_TXBD_DESA_H(x) | BIT_HI10Q_TXBD_DESA_H(v)) /* 2 REG_HI11Q_TXBD_DESA_L (Offset 0x2318) */ #define BIT_SHIFT_HI11Q_TXBD_DESA_L 0 #define BIT_MASK_HI11Q_TXBD_DESA_L 0xffffffffL #define BIT_HI11Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI11Q_TXBD_DESA_L) << BIT_SHIFT_HI11Q_TXBD_DESA_L) #define BITS_HI11Q_TXBD_DESA_L \ (BIT_MASK_HI11Q_TXBD_DESA_L << BIT_SHIFT_HI11Q_TXBD_DESA_L) #define BIT_CLEAR_HI11Q_TXBD_DESA_L(x) ((x) & (~BITS_HI11Q_TXBD_DESA_L)) #define BIT_GET_HI11Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_L) & BIT_MASK_HI11Q_TXBD_DESA_L) #define BIT_SET_HI11Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI11Q_TXBD_DESA_L(x) | BIT_HI11Q_TXBD_DESA_L(v)) /* 2 REG_HI11Q_TXBD_DESA_H (Offset 0x231C) */ #define BIT_SHIFT_HI11Q_TXBD_DESA_H 0 #define BIT_MASK_HI11Q_TXBD_DESA_H 0xffffffffL #define BIT_HI11Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI11Q_TXBD_DESA_H) << BIT_SHIFT_HI11Q_TXBD_DESA_H) #define BITS_HI11Q_TXBD_DESA_H \ (BIT_MASK_HI11Q_TXBD_DESA_H << BIT_SHIFT_HI11Q_TXBD_DESA_H) #define BIT_CLEAR_HI11Q_TXBD_DESA_H(x) ((x) & (~BITS_HI11Q_TXBD_DESA_H)) #define BIT_GET_HI11Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_H) & BIT_MASK_HI11Q_TXBD_DESA_H) #define BIT_SET_HI11Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI11Q_TXBD_DESA_H(x) | BIT_HI11Q_TXBD_DESA_H(v)) /* 2 REG_HI12Q_TXBD_DESA_L (Offset 0x2320) */ #define BIT_SHIFT_HI12Q_TXBD_DESA_L 0 #define BIT_MASK_HI12Q_TXBD_DESA_L 0xffffffffL #define BIT_HI12Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI12Q_TXBD_DESA_L) << BIT_SHIFT_HI12Q_TXBD_DESA_L) #define BITS_HI12Q_TXBD_DESA_L \ (BIT_MASK_HI12Q_TXBD_DESA_L << BIT_SHIFT_HI12Q_TXBD_DESA_L) #define BIT_CLEAR_HI12Q_TXBD_DESA_L(x) ((x) & (~BITS_HI12Q_TXBD_DESA_L)) #define BIT_GET_HI12Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_L) & BIT_MASK_HI12Q_TXBD_DESA_L) #define BIT_SET_HI12Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI12Q_TXBD_DESA_L(x) | BIT_HI12Q_TXBD_DESA_L(v)) /* 2 REG_HI12Q_TXBD_DESA_H (Offset 0x2324) */ #define BIT_SHIFT_HI12Q_TXBD_DESA_H 0 #define BIT_MASK_HI12Q_TXBD_DESA_H 0xffffffffL #define BIT_HI12Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI12Q_TXBD_DESA_H) << BIT_SHIFT_HI12Q_TXBD_DESA_H) #define BITS_HI12Q_TXBD_DESA_H \ (BIT_MASK_HI12Q_TXBD_DESA_H << BIT_SHIFT_HI12Q_TXBD_DESA_H) #define BIT_CLEAR_HI12Q_TXBD_DESA_H(x) ((x) & (~BITS_HI12Q_TXBD_DESA_H)) #define BIT_GET_HI12Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_H) & BIT_MASK_HI12Q_TXBD_DESA_H) #define BIT_SET_HI12Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI12Q_TXBD_DESA_H(x) | BIT_HI12Q_TXBD_DESA_H(v)) /* 2 REG_HI13Q_TXBD_DESA_L (Offset 0x2328) */ #define BIT_SHIFT_HI13Q_TXBD_DESA_L 0 #define BIT_MASK_HI13Q_TXBD_DESA_L 0xffffffffL #define BIT_HI13Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI13Q_TXBD_DESA_L) << BIT_SHIFT_HI13Q_TXBD_DESA_L) #define BITS_HI13Q_TXBD_DESA_L \ (BIT_MASK_HI13Q_TXBD_DESA_L << BIT_SHIFT_HI13Q_TXBD_DESA_L) #define BIT_CLEAR_HI13Q_TXBD_DESA_L(x) ((x) & (~BITS_HI13Q_TXBD_DESA_L)) #define BIT_GET_HI13Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_L) & BIT_MASK_HI13Q_TXBD_DESA_L) #define BIT_SET_HI13Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI13Q_TXBD_DESA_L(x) | BIT_HI13Q_TXBD_DESA_L(v)) /* 2 REG_HI13Q_TXBD_DESA_H (Offset 0x232C) */ #define BIT_SHIFT_HI13Q_TXBD_DESA_H 0 #define BIT_MASK_HI13Q_TXBD_DESA_H 0xffffffffL #define BIT_HI13Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI13Q_TXBD_DESA_H) << BIT_SHIFT_HI13Q_TXBD_DESA_H) #define BITS_HI13Q_TXBD_DESA_H \ (BIT_MASK_HI13Q_TXBD_DESA_H << BIT_SHIFT_HI13Q_TXBD_DESA_H) #define BIT_CLEAR_HI13Q_TXBD_DESA_H(x) ((x) & (~BITS_HI13Q_TXBD_DESA_H)) #define BIT_GET_HI13Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_H) & BIT_MASK_HI13Q_TXBD_DESA_H) #define BIT_SET_HI13Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI13Q_TXBD_DESA_H(x) | BIT_HI13Q_TXBD_DESA_H(v)) /* 2 REG_HI14Q_TXBD_DESA_L (Offset 0x2330) */ #define BIT_SHIFT_HI14Q_TXBD_DESA_L 0 #define BIT_MASK_HI14Q_TXBD_DESA_L 0xffffffffL #define BIT_HI14Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI14Q_TXBD_DESA_L) << BIT_SHIFT_HI14Q_TXBD_DESA_L) #define BITS_HI14Q_TXBD_DESA_L \ (BIT_MASK_HI14Q_TXBD_DESA_L << BIT_SHIFT_HI14Q_TXBD_DESA_L) #define BIT_CLEAR_HI14Q_TXBD_DESA_L(x) ((x) & (~BITS_HI14Q_TXBD_DESA_L)) #define BIT_GET_HI14Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_L) & BIT_MASK_HI14Q_TXBD_DESA_L) #define BIT_SET_HI14Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI14Q_TXBD_DESA_L(x) | BIT_HI14Q_TXBD_DESA_L(v)) /* 2 REG_HI14Q_TXBD_DESA_H (Offset 0x2334) */ #define BIT_SHIFT_HI14Q_TXBD_DESA_H 0 #define BIT_MASK_HI14Q_TXBD_DESA_H 0xffffffffL #define BIT_HI14Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI14Q_TXBD_DESA_H) << BIT_SHIFT_HI14Q_TXBD_DESA_H) #define BITS_HI14Q_TXBD_DESA_H \ (BIT_MASK_HI14Q_TXBD_DESA_H << BIT_SHIFT_HI14Q_TXBD_DESA_H) #define BIT_CLEAR_HI14Q_TXBD_DESA_H(x) ((x) & (~BITS_HI14Q_TXBD_DESA_H)) #define BIT_GET_HI14Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_H) & BIT_MASK_HI14Q_TXBD_DESA_H) #define BIT_SET_HI14Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI14Q_TXBD_DESA_H(x) | BIT_HI14Q_TXBD_DESA_H(v)) /* 2 REG_HI15Q_TXBD_DESA_L (Offset 0x2338) */ #define BIT_SHIFT_HI15Q_TXBD_DESA_L 0 #define BIT_MASK_HI15Q_TXBD_DESA_L 0xffffffffL #define BIT_HI15Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI15Q_TXBD_DESA_L) << BIT_SHIFT_HI15Q_TXBD_DESA_L) #define BITS_HI15Q_TXBD_DESA_L \ (BIT_MASK_HI15Q_TXBD_DESA_L << BIT_SHIFT_HI15Q_TXBD_DESA_L) #define BIT_CLEAR_HI15Q_TXBD_DESA_L(x) ((x) & (~BITS_HI15Q_TXBD_DESA_L)) #define BIT_GET_HI15Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_L) & BIT_MASK_HI15Q_TXBD_DESA_L) #define BIT_SET_HI15Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI15Q_TXBD_DESA_L(x) | BIT_HI15Q_TXBD_DESA_L(v)) /* 2 REG_HI15Q_TXBD_DESA_H (Offset 0x233C) */ #define BIT_SHIFT_HI15Q_TXBD_DESA_H 0 #define BIT_MASK_HI15Q_TXBD_DESA_H 0xffffffffL #define BIT_HI15Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI15Q_TXBD_DESA_H) << BIT_SHIFT_HI15Q_TXBD_DESA_H) #define BITS_HI15Q_TXBD_DESA_H \ (BIT_MASK_HI15Q_TXBD_DESA_H << BIT_SHIFT_HI15Q_TXBD_DESA_H) #define BIT_CLEAR_HI15Q_TXBD_DESA_H(x) ((x) & (~BITS_HI15Q_TXBD_DESA_H)) #define BIT_GET_HI15Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_H) & BIT_MASK_HI15Q_TXBD_DESA_H) #define BIT_SET_HI15Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI15Q_TXBD_DESA_H(x) | BIT_HI15Q_TXBD_DESA_H(v)) /* 2 REG_HI16Q_TXBD_DESA_L (Offset 0x2340) */ #define BIT_SHIFT_HI16Q_TXBD_DESA_L 0 #define BIT_MASK_HI16Q_TXBD_DESA_L 0xffffffffL #define BIT_HI16Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI16Q_TXBD_DESA_L) << BIT_SHIFT_HI16Q_TXBD_DESA_L) #define BITS_HI16Q_TXBD_DESA_L \ (BIT_MASK_HI16Q_TXBD_DESA_L << BIT_SHIFT_HI16Q_TXBD_DESA_L) #define BIT_CLEAR_HI16Q_TXBD_DESA_L(x) ((x) & (~BITS_HI16Q_TXBD_DESA_L)) #define BIT_GET_HI16Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_L) & BIT_MASK_HI16Q_TXBD_DESA_L) #define BIT_SET_HI16Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI16Q_TXBD_DESA_L(x) | BIT_HI16Q_TXBD_DESA_L(v)) /* 2 REG_HI16Q_TXBD_DESA_H (Offset 0x2344) */ #define BIT_SHIFT_HI16Q_TXBD_DESA_H 0 #define BIT_MASK_HI16Q_TXBD_DESA_H 0xffffffffL #define BIT_HI16Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI16Q_TXBD_DESA_H) << BIT_SHIFT_HI16Q_TXBD_DESA_H) #define BITS_HI16Q_TXBD_DESA_H \ (BIT_MASK_HI16Q_TXBD_DESA_H << BIT_SHIFT_HI16Q_TXBD_DESA_H) #define BIT_CLEAR_HI16Q_TXBD_DESA_H(x) ((x) & (~BITS_HI16Q_TXBD_DESA_H)) #define BIT_GET_HI16Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_H) & BIT_MASK_HI16Q_TXBD_DESA_H) #define BIT_SET_HI16Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI16Q_TXBD_DESA_H(x) | BIT_HI16Q_TXBD_DESA_H(v)) /* 2 REG_HI17Q_TXBD_DESA_L (Offset 0x2348) */ #define BIT_SHIFT_HI17Q_TXBD_DESA_L 0 #define BIT_MASK_HI17Q_TXBD_DESA_L 0xffffffffL #define BIT_HI17Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI17Q_TXBD_DESA_L) << BIT_SHIFT_HI17Q_TXBD_DESA_L) #define BITS_HI17Q_TXBD_DESA_L \ (BIT_MASK_HI17Q_TXBD_DESA_L << BIT_SHIFT_HI17Q_TXBD_DESA_L) #define BIT_CLEAR_HI17Q_TXBD_DESA_L(x) ((x) & (~BITS_HI17Q_TXBD_DESA_L)) #define BIT_GET_HI17Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_L) & BIT_MASK_HI17Q_TXBD_DESA_L) #define BIT_SET_HI17Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI17Q_TXBD_DESA_L(x) | BIT_HI17Q_TXBD_DESA_L(v)) /* 2 REG_HI17Q_TXBD_DESA_H (Offset 0x234C) */ #define BIT_SHIFT_HI17Q_TXBD_DESA_H 0 #define BIT_MASK_HI17Q_TXBD_DESA_H 0xffffffffL #define BIT_HI17Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI17Q_TXBD_DESA_H) << BIT_SHIFT_HI17Q_TXBD_DESA_H) #define BITS_HI17Q_TXBD_DESA_H \ (BIT_MASK_HI17Q_TXBD_DESA_H << BIT_SHIFT_HI17Q_TXBD_DESA_H) #define BIT_CLEAR_HI17Q_TXBD_DESA_H(x) ((x) & (~BITS_HI17Q_TXBD_DESA_H)) #define BIT_GET_HI17Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_H) & BIT_MASK_HI17Q_TXBD_DESA_H) #define BIT_SET_HI17Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI17Q_TXBD_DESA_H(x) | BIT_HI17Q_TXBD_DESA_H(v)) /* 2 REG_HI18Q_TXBD_DESA_L (Offset 0x2350) */ #define BIT_SHIFT_HI18Q_TXBD_DESA_L 0 #define BIT_MASK_HI18Q_TXBD_DESA_L 0xffffffffL #define BIT_HI18Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI18Q_TXBD_DESA_L) << BIT_SHIFT_HI18Q_TXBD_DESA_L) #define BITS_HI18Q_TXBD_DESA_L \ (BIT_MASK_HI18Q_TXBD_DESA_L << BIT_SHIFT_HI18Q_TXBD_DESA_L) #define BIT_CLEAR_HI18Q_TXBD_DESA_L(x) ((x) & (~BITS_HI18Q_TXBD_DESA_L)) #define BIT_GET_HI18Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_L) & BIT_MASK_HI18Q_TXBD_DESA_L) #define BIT_SET_HI18Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI18Q_TXBD_DESA_L(x) | BIT_HI18Q_TXBD_DESA_L(v)) /* 2 REG_HI18Q_TXBD_DESA_H (Offset 0x2354) */ #define BIT_SHIFT_HI18Q_TXBD_DESA_H 0 #define BIT_MASK_HI18Q_TXBD_DESA_H 0xffffffffL #define BIT_HI18Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI18Q_TXBD_DESA_H) << BIT_SHIFT_HI18Q_TXBD_DESA_H) #define BITS_HI18Q_TXBD_DESA_H \ (BIT_MASK_HI18Q_TXBD_DESA_H << BIT_SHIFT_HI18Q_TXBD_DESA_H) #define BIT_CLEAR_HI18Q_TXBD_DESA_H(x) ((x) & (~BITS_HI18Q_TXBD_DESA_H)) #define BIT_GET_HI18Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_H) & BIT_MASK_HI18Q_TXBD_DESA_H) #define BIT_SET_HI18Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI18Q_TXBD_DESA_H(x) | BIT_HI18Q_TXBD_DESA_H(v)) /* 2 REG_HI19Q_TXBD_DESA_L (Offset 0x2358) */ #define BIT_SHIFT_HI19Q_TXBD_DESA_L 0 #define BIT_MASK_HI19Q_TXBD_DESA_L 0xffffffffL #define BIT_HI19Q_TXBD_DESA_L(x) \ (((x) & BIT_MASK_HI19Q_TXBD_DESA_L) << BIT_SHIFT_HI19Q_TXBD_DESA_L) #define BITS_HI19Q_TXBD_DESA_L \ (BIT_MASK_HI19Q_TXBD_DESA_L << BIT_SHIFT_HI19Q_TXBD_DESA_L) #define BIT_CLEAR_HI19Q_TXBD_DESA_L(x) ((x) & (~BITS_HI19Q_TXBD_DESA_L)) #define BIT_GET_HI19Q_TXBD_DESA_L(x) \ (((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_L) & BIT_MASK_HI19Q_TXBD_DESA_L) #define BIT_SET_HI19Q_TXBD_DESA_L(x, v) \ (BIT_CLEAR_HI19Q_TXBD_DESA_L(x) | BIT_HI19Q_TXBD_DESA_L(v)) /* 2 REG_HI19Q_TXBD_DESA_H (Offset 0x235C) */ #define BIT_CLR_P0HI19Q_HW_IDX BIT(25) #define BIT_CLR_P0HI18Q_HW_IDX BIT(24) #define BIT_CLR_P0HI17Q_HW_IDX BIT(23) #define BIT_CLR_P0HI16Q_HW_IDX BIT(22) #define BIT_CLR_P0HI19Q_HOST_IDX BIT(9) #define BIT_CLR_P0HI18Q_HOST_IDX BIT(8) #define BIT_CLR_P0HI17Q_HOST_IDX BIT(7) #define BIT_CLR_P0HI16Q_HOST_IDX BIT(6) #define BIT_SHIFT_HI19Q_TXBD_DESA_H 0 #define BIT_MASK_HI19Q_TXBD_DESA_H 0xffffffffL #define BIT_HI19Q_TXBD_DESA_H(x) \ (((x) & BIT_MASK_HI19Q_TXBD_DESA_H) << BIT_SHIFT_HI19Q_TXBD_DESA_H) #define BITS_HI19Q_TXBD_DESA_H \ (BIT_MASK_HI19Q_TXBD_DESA_H << BIT_SHIFT_HI19Q_TXBD_DESA_H) #define BIT_CLEAR_HI19Q_TXBD_DESA_H(x) ((x) & (~BITS_HI19Q_TXBD_DESA_H)) #define BIT_GET_HI19Q_TXBD_DESA_H(x) \ (((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_H) & BIT_MASK_HI19Q_TXBD_DESA_H) #define BIT_SET_HI19Q_TXBD_DESA_H(x, v) \ (BIT_CLEAR_HI19Q_TXBD_DESA_H(x) | BIT_HI19Q_TXBD_DESA_H(v)) /* 2 REG_P0HI16Q_TXBD_IDX (Offset 0x2370) */ #define BIT_SHIFT_P0HI16Q_HW_IDX 16 #define BIT_MASK_P0HI16Q_HW_IDX 0xfff #define BIT_P0HI16Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI16Q_HW_IDX) << BIT_SHIFT_P0HI16Q_HW_IDX) #define BITS_P0HI16Q_HW_IDX \ (BIT_MASK_P0HI16Q_HW_IDX << BIT_SHIFT_P0HI16Q_HW_IDX) #define BIT_CLEAR_P0HI16Q_HW_IDX(x) ((x) & (~BITS_P0HI16Q_HW_IDX)) #define BIT_GET_P0HI16Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI16Q_HW_IDX) & BIT_MASK_P0HI16Q_HW_IDX) #define BIT_SET_P0HI16Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI16Q_HW_IDX(x) | BIT_P0HI16Q_HW_IDX(v)) #define BIT_SHIFT_P0HI16Q_HOST_IDX 0 #define BIT_MASK_P0HI16Q_HOST_IDX 0xfff #define BIT_P0HI16Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI16Q_HOST_IDX) << BIT_SHIFT_P0HI16Q_HOST_IDX) #define BITS_P0HI16Q_HOST_IDX \ (BIT_MASK_P0HI16Q_HOST_IDX << BIT_SHIFT_P0HI16Q_HOST_IDX) #define BIT_CLEAR_P0HI16Q_HOST_IDX(x) ((x) & (~BITS_P0HI16Q_HOST_IDX)) #define BIT_GET_P0HI16Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI16Q_HOST_IDX) & BIT_MASK_P0HI16Q_HOST_IDX) #define BIT_SET_P0HI16Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI16Q_HOST_IDX(x) | BIT_P0HI16Q_HOST_IDX(v)) /* 2 REG_P0HI17Q_TXBD_IDX (Offset 0x2374) */ #define BIT_SHIFT_P0HI17Q_HW_IDX 16 #define BIT_MASK_P0HI17Q_HW_IDX 0xfff #define BIT_P0HI17Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI17Q_HW_IDX) << BIT_SHIFT_P0HI17Q_HW_IDX) #define BITS_P0HI17Q_HW_IDX \ (BIT_MASK_P0HI17Q_HW_IDX << BIT_SHIFT_P0HI17Q_HW_IDX) #define BIT_CLEAR_P0HI17Q_HW_IDX(x) ((x) & (~BITS_P0HI17Q_HW_IDX)) #define BIT_GET_P0HI17Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI17Q_HW_IDX) & BIT_MASK_P0HI17Q_HW_IDX) #define BIT_SET_P0HI17Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI17Q_HW_IDX(x) | BIT_P0HI17Q_HW_IDX(v)) #define BIT_SHIFT_P0HI17Q_HOST_IDX 0 #define BIT_MASK_P0HI17Q_HOST_IDX 0xfff #define BIT_P0HI17Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI17Q_HOST_IDX) << BIT_SHIFT_P0HI17Q_HOST_IDX) #define BITS_P0HI17Q_HOST_IDX \ (BIT_MASK_P0HI17Q_HOST_IDX << BIT_SHIFT_P0HI17Q_HOST_IDX) #define BIT_CLEAR_P0HI17Q_HOST_IDX(x) ((x) & (~BITS_P0HI17Q_HOST_IDX)) #define BIT_GET_P0HI17Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI17Q_HOST_IDX) & BIT_MASK_P0HI17Q_HOST_IDX) #define BIT_SET_P0HI17Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI17Q_HOST_IDX(x) | BIT_P0HI17Q_HOST_IDX(v)) /* 2 REG_P0HI18Q_TXBD_IDX (Offset 0x2378) */ #define BIT_SHIFT_P0HI18Q_HW_IDX 16 #define BIT_MASK_P0HI18Q_HW_IDX 0xfff #define BIT_P0HI18Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI18Q_HW_IDX) << BIT_SHIFT_P0HI18Q_HW_IDX) #define BITS_P0HI18Q_HW_IDX \ (BIT_MASK_P0HI18Q_HW_IDX << BIT_SHIFT_P0HI18Q_HW_IDX) #define BIT_CLEAR_P0HI18Q_HW_IDX(x) ((x) & (~BITS_P0HI18Q_HW_IDX)) #define BIT_GET_P0HI18Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI18Q_HW_IDX) & BIT_MASK_P0HI18Q_HW_IDX) #define BIT_SET_P0HI18Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI18Q_HW_IDX(x) | BIT_P0HI18Q_HW_IDX(v)) #define BIT_SHIFT_P0HI18Q_HOST_IDX 0 #define BIT_MASK_P0HI18Q_HOST_IDX 0xfff #define BIT_P0HI18Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI18Q_HOST_IDX) << BIT_SHIFT_P0HI18Q_HOST_IDX) #define BITS_P0HI18Q_HOST_IDX \ (BIT_MASK_P0HI18Q_HOST_IDX << BIT_SHIFT_P0HI18Q_HOST_IDX) #define BIT_CLEAR_P0HI18Q_HOST_IDX(x) ((x) & (~BITS_P0HI18Q_HOST_IDX)) #define BIT_GET_P0HI18Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI18Q_HOST_IDX) & BIT_MASK_P0HI18Q_HOST_IDX) #define BIT_SET_P0HI18Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI18Q_HOST_IDX(x) | BIT_P0HI18Q_HOST_IDX(v)) /* 2 REG_P0HI19Q_TXBD_IDX (Offset 0x237C) */ #define BIT_SHIFT_P0HI19Q_HW_IDX 16 #define BIT_MASK_P0HI19Q_HW_IDX 0xfff #define BIT_P0HI19Q_HW_IDX(x) \ (((x) & BIT_MASK_P0HI19Q_HW_IDX) << BIT_SHIFT_P0HI19Q_HW_IDX) #define BITS_P0HI19Q_HW_IDX \ (BIT_MASK_P0HI19Q_HW_IDX << BIT_SHIFT_P0HI19Q_HW_IDX) #define BIT_CLEAR_P0HI19Q_HW_IDX(x) ((x) & (~BITS_P0HI19Q_HW_IDX)) #define BIT_GET_P0HI19Q_HW_IDX(x) \ (((x) >> BIT_SHIFT_P0HI19Q_HW_IDX) & BIT_MASK_P0HI19Q_HW_IDX) #define BIT_SET_P0HI19Q_HW_IDX(x, v) \ (BIT_CLEAR_P0HI19Q_HW_IDX(x) | BIT_P0HI19Q_HW_IDX(v)) #define BIT_SHIFT_P0HI19Q_HOST_IDX 0 #define BIT_MASK_P0HI19Q_HOST_IDX 0xfff #define BIT_P0HI19Q_HOST_IDX(x) \ (((x) & BIT_MASK_P0HI19Q_HOST_IDX) << BIT_SHIFT_P0HI19Q_HOST_IDX) #define BITS_P0HI19Q_HOST_IDX \ (BIT_MASK_P0HI19Q_HOST_IDX << BIT_SHIFT_P0HI19Q_HOST_IDX) #define BIT_CLEAR_P0HI19Q_HOST_IDX(x) ((x) & (~BITS_P0HI19Q_HOST_IDX)) #define BIT_GET_P0HI19Q_HOST_IDX(x) \ (((x) >> BIT_SHIFT_P0HI19Q_HOST_IDX) & BIT_MASK_P0HI19Q_HOST_IDX) #define BIT_SET_P0HI19Q_HOST_IDX(x, v) \ (BIT_CLEAR_P0HI19Q_HOST_IDX(x) | BIT_P0HI19Q_HOST_IDX(v)) /* 2 REG_P0HI16Q_HI17Q_TXBD_NUM (Offset 0x2380) */ #define BIT_P0HI17Q_FLAG BIT(30) #define BIT_SHIFT_P0HI17Q_DESC_MODE 28 #define BIT_MASK_P0HI17Q_DESC_MODE 0x3 #define BIT_P0HI17Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI17Q_DESC_MODE) << BIT_SHIFT_P0HI17Q_DESC_MODE) #define BITS_P0HI17Q_DESC_MODE \ (BIT_MASK_P0HI17Q_DESC_MODE << BIT_SHIFT_P0HI17Q_DESC_MODE) #define BIT_CLEAR_P0HI17Q_DESC_MODE(x) ((x) & (~BITS_P0HI17Q_DESC_MODE)) #define BIT_GET_P0HI17Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI17Q_DESC_MODE) & BIT_MASK_P0HI17Q_DESC_MODE) #define BIT_SET_P0HI17Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI17Q_DESC_MODE(x) | BIT_P0HI17Q_DESC_MODE(v)) #define BIT_SHIFT_P0HI17Q_DESC_NUM 16 #define BIT_MASK_P0HI17Q_DESC_NUM 0xfff #define BIT_P0HI17Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI17Q_DESC_NUM) << BIT_SHIFT_P0HI17Q_DESC_NUM) #define BITS_P0HI17Q_DESC_NUM \ (BIT_MASK_P0HI17Q_DESC_NUM << BIT_SHIFT_P0HI17Q_DESC_NUM) #define BIT_CLEAR_P0HI17Q_DESC_NUM(x) ((x) & (~BITS_P0HI17Q_DESC_NUM)) #define BIT_GET_P0HI17Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI17Q_DESC_NUM) & BIT_MASK_P0HI17Q_DESC_NUM) #define BIT_SET_P0HI17Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI17Q_DESC_NUM(x) | BIT_P0HI17Q_DESC_NUM(v)) #define BIT_P0HI16Q_FLAG BIT(14) #define BIT_SHIFT_P0HI16Q_DESC_MODE 12 #define BIT_MASK_P0HI16Q_DESC_MODE 0x3 #define BIT_P0HI16Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI16Q_DESC_MODE) << BIT_SHIFT_P0HI16Q_DESC_MODE) #define BITS_P0HI16Q_DESC_MODE \ (BIT_MASK_P0HI16Q_DESC_MODE << BIT_SHIFT_P0HI16Q_DESC_MODE) #define BIT_CLEAR_P0HI16Q_DESC_MODE(x) ((x) & (~BITS_P0HI16Q_DESC_MODE)) #define BIT_GET_P0HI16Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI16Q_DESC_MODE) & BIT_MASK_P0HI16Q_DESC_MODE) #define BIT_SET_P0HI16Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI16Q_DESC_MODE(x) | BIT_P0HI16Q_DESC_MODE(v)) #define BIT_SHIFT_P0HI16Q_DESC_NUM 0 #define BIT_MASK_P0HI16Q_DESC_NUM 0xfff #define BIT_P0HI16Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI16Q_DESC_NUM) << BIT_SHIFT_P0HI16Q_DESC_NUM) #define BITS_P0HI16Q_DESC_NUM \ (BIT_MASK_P0HI16Q_DESC_NUM << BIT_SHIFT_P0HI16Q_DESC_NUM) #define BIT_CLEAR_P0HI16Q_DESC_NUM(x) ((x) & (~BITS_P0HI16Q_DESC_NUM)) #define BIT_GET_P0HI16Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI16Q_DESC_NUM) & BIT_MASK_P0HI16Q_DESC_NUM) #define BIT_SET_P0HI16Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI16Q_DESC_NUM(x) | BIT_P0HI16Q_DESC_NUM(v)) /* 2 REG_P0HI18Q_HI19Q_TXBD_NUM (Offset 0x2384) */ #define BIT_P0HI19Q_FLAG BIT(30) #define BIT_SHIFT_P0HI19Q_DESC_MODE 28 #define BIT_MASK_P0HI19Q_DESC_MODE 0x3 #define BIT_P0HI19Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI19Q_DESC_MODE) << BIT_SHIFT_P0HI19Q_DESC_MODE) #define BITS_P0HI19Q_DESC_MODE \ (BIT_MASK_P0HI19Q_DESC_MODE << BIT_SHIFT_P0HI19Q_DESC_MODE) #define BIT_CLEAR_P0HI19Q_DESC_MODE(x) ((x) & (~BITS_P0HI19Q_DESC_MODE)) #define BIT_GET_P0HI19Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI19Q_DESC_MODE) & BIT_MASK_P0HI19Q_DESC_MODE) #define BIT_SET_P0HI19Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI19Q_DESC_MODE(x) | BIT_P0HI19Q_DESC_MODE(v)) #define BIT_SHIFT_P0HI19Q_DESC_NUM 16 #define BIT_MASK_P0HI19Q_DESC_NUM 0xfff #define BIT_P0HI19Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI19Q_DESC_NUM) << BIT_SHIFT_P0HI19Q_DESC_NUM) #define BITS_P0HI19Q_DESC_NUM \ (BIT_MASK_P0HI19Q_DESC_NUM << BIT_SHIFT_P0HI19Q_DESC_NUM) #define BIT_CLEAR_P0HI19Q_DESC_NUM(x) ((x) & (~BITS_P0HI19Q_DESC_NUM)) #define BIT_GET_P0HI19Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI19Q_DESC_NUM) & BIT_MASK_P0HI19Q_DESC_NUM) #define BIT_SET_P0HI19Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI19Q_DESC_NUM(x) | BIT_P0HI19Q_DESC_NUM(v)) #define BIT_P0HI18Q_FLAG BIT(14) #define BIT_SHIFT_P0HI18Q_DESC_MODE 12 #define BIT_MASK_P0HI18Q_DESC_MODE 0x3 #define BIT_P0HI18Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI18Q_DESC_MODE) << BIT_SHIFT_P0HI18Q_DESC_MODE) #define BITS_P0HI18Q_DESC_MODE \ (BIT_MASK_P0HI18Q_DESC_MODE << BIT_SHIFT_P0HI18Q_DESC_MODE) #define BIT_CLEAR_P0HI18Q_DESC_MODE(x) ((x) & (~BITS_P0HI18Q_DESC_MODE)) #define BIT_GET_P0HI18Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI18Q_DESC_MODE) & BIT_MASK_P0HI18Q_DESC_MODE) #define BIT_SET_P0HI18Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI18Q_DESC_MODE(x) | BIT_P0HI18Q_DESC_MODE(v)) #define BIT_SHIFT_P0HI18Q_DESC_NUM 0 #define BIT_MASK_P0HI18Q_DESC_NUM 0xfff #define BIT_P0HI18Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI18Q_DESC_NUM) << BIT_SHIFT_P0HI18Q_DESC_NUM) #define BITS_P0HI18Q_DESC_NUM \ (BIT_MASK_P0HI18Q_DESC_NUM << BIT_SHIFT_P0HI18Q_DESC_NUM) #define BIT_CLEAR_P0HI18Q_DESC_NUM(x) ((x) & (~BITS_P0HI18Q_DESC_NUM)) #define BIT_GET_P0HI18Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI18Q_DESC_NUM) & BIT_MASK_P0HI18Q_DESC_NUM) #define BIT_SET_P0HI18Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI18Q_DESC_NUM(x) | BIT_P0HI18Q_DESC_NUM(v)) #endif #if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PCIE_HISR0 (Offset 0x23B4) */ #define BIT_PRE_TX_ERR_INT BIT(31) #define BIT_HISR1_IND BIT(11) #define BIT_TXDMAOK_CHANNEL15 BIT(7) #define BIT_TXDMAOK_CHANNEL14 BIT(6) #define BIT_TXDMAOK_CHANNEL3 BIT(5) #define BIT_TXDMAOK_CHANNEL2 BIT(4) #define BIT_TXDMAOK_CHANNEL1 BIT(3) #define BIT_TXDMAOK_CHANNEL0 BIT(2) /* 2 REG_PCIE_HISR1 (Offset 0x23BC) */ #define BIT_CPU_MGQ_EARLY_INT BIT(6) #define BIT_PSTIMER_5 BIT(4) #define BIT_PSTIMER_4 BIT(3) #define BIT_PSTIMER_3 BIT(2) #define BIT_BB_STOPRX_INT BIT(0) #endif #if (HALMAC_8814B_SUPPORT) /* 2 REG_P0HI8Q_HI9Q_TXBD_NUM (Offset 0x23C0) */ #define BIT_P0HI9Q_FLAG BIT(30) #define BIT_SHIFT_P0HI9Q_DESC_MODE 28 #define BIT_MASK_P0HI9Q_DESC_MODE 0x3 #define BIT_P0HI9Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI9Q_DESC_MODE) << BIT_SHIFT_P0HI9Q_DESC_MODE) #define BITS_P0HI9Q_DESC_MODE \ (BIT_MASK_P0HI9Q_DESC_MODE << BIT_SHIFT_P0HI9Q_DESC_MODE) #define BIT_CLEAR_P0HI9Q_DESC_MODE(x) ((x) & (~BITS_P0HI9Q_DESC_MODE)) #define BIT_GET_P0HI9Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI9Q_DESC_MODE) & BIT_MASK_P0HI9Q_DESC_MODE) #define BIT_SET_P0HI9Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI9Q_DESC_MODE(x) | BIT_P0HI9Q_DESC_MODE(v)) #define BIT_SHIFT_P0HI9Q_DESC_NUM 16 #define BIT_MASK_P0HI9Q_DESC_NUM 0xfff #define BIT_P0HI9Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI9Q_DESC_NUM) << BIT_SHIFT_P0HI9Q_DESC_NUM) #define BITS_P0HI9Q_DESC_NUM \ (BIT_MASK_P0HI9Q_DESC_NUM << BIT_SHIFT_P0HI9Q_DESC_NUM) #define BIT_CLEAR_P0HI9Q_DESC_NUM(x) ((x) & (~BITS_P0HI9Q_DESC_NUM)) #define BIT_GET_P0HI9Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI9Q_DESC_NUM) & BIT_MASK_P0HI9Q_DESC_NUM) #define BIT_SET_P0HI9Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI9Q_DESC_NUM(x) | BIT_P0HI9Q_DESC_NUM(v)) #define BIT_P0HI8Q_FLAG BIT(14) #define BIT_SHIFT_P0HI8Q_DESC_MODE 12 #define BIT_MASK_P0HI8Q_DESC_MODE 0x3 #define BIT_P0HI8Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI8Q_DESC_MODE) << BIT_SHIFT_P0HI8Q_DESC_MODE) #define BITS_P0HI8Q_DESC_MODE \ (BIT_MASK_P0HI8Q_DESC_MODE << BIT_SHIFT_P0HI8Q_DESC_MODE) #define BIT_CLEAR_P0HI8Q_DESC_MODE(x) ((x) & (~BITS_P0HI8Q_DESC_MODE)) #define BIT_GET_P0HI8Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI8Q_DESC_MODE) & BIT_MASK_P0HI8Q_DESC_MODE) #define BIT_SET_P0HI8Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI8Q_DESC_MODE(x) | BIT_P0HI8Q_DESC_MODE(v)) #define BIT_SHIFT_P0HI8Q_DESC_NUM 0 #define BIT_MASK_P0HI8Q_DESC_NUM 0xfff #define BIT_P0HI8Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI8Q_DESC_NUM) << BIT_SHIFT_P0HI8Q_DESC_NUM) #define BITS_P0HI8Q_DESC_NUM \ (BIT_MASK_P0HI8Q_DESC_NUM << BIT_SHIFT_P0HI8Q_DESC_NUM) #define BIT_CLEAR_P0HI8Q_DESC_NUM(x) ((x) & (~BITS_P0HI8Q_DESC_NUM)) #define BIT_GET_P0HI8Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI8Q_DESC_NUM) & BIT_MASK_P0HI8Q_DESC_NUM) #define BIT_SET_P0HI8Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI8Q_DESC_NUM(x) | BIT_P0HI8Q_DESC_NUM(v)) /* 2 REG_P0HI10Q_HI11Q_TXBD_NUM (Offset 0x23C4) */ #define BIT_P0HI11Q_FLAG BIT(30) #define BIT_SHIFT_P0HI11Q_DESC_MODE 28 #define BIT_MASK_P0HI11Q_DESC_MODE 0x3 #define BIT_P0HI11Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI11Q_DESC_MODE) << BIT_SHIFT_P0HI11Q_DESC_MODE) #define BITS_P0HI11Q_DESC_MODE \ (BIT_MASK_P0HI11Q_DESC_MODE << BIT_SHIFT_P0HI11Q_DESC_MODE) #define BIT_CLEAR_P0HI11Q_DESC_MODE(x) ((x) & (~BITS_P0HI11Q_DESC_MODE)) #define BIT_GET_P0HI11Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI11Q_DESC_MODE) & BIT_MASK_P0HI11Q_DESC_MODE) #define BIT_SET_P0HI11Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI11Q_DESC_MODE(x) | BIT_P0HI11Q_DESC_MODE(v)) #define BIT_SHIFT_P0HI11Q_DESC_NUM 16 #define BIT_MASK_P0HI11Q_DESC_NUM 0xfff #define BIT_P0HI11Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI11Q_DESC_NUM) << BIT_SHIFT_P0HI11Q_DESC_NUM) #define BITS_P0HI11Q_DESC_NUM \ (BIT_MASK_P0HI11Q_DESC_NUM << BIT_SHIFT_P0HI11Q_DESC_NUM) #define BIT_CLEAR_P0HI11Q_DESC_NUM(x) ((x) & (~BITS_P0HI11Q_DESC_NUM)) #define BIT_GET_P0HI11Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI11Q_DESC_NUM) & BIT_MASK_P0HI11Q_DESC_NUM) #define BIT_SET_P0HI11Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI11Q_DESC_NUM(x) | BIT_P0HI11Q_DESC_NUM(v)) #define BIT_P0HI10Q_FLAG BIT(14) #define BIT_SHIFT_P0HI10Q_DESC_MODE 12 #define BIT_MASK_P0HI10Q_DESC_MODE 0x3 #define BIT_P0HI10Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI10Q_DESC_MODE) << BIT_SHIFT_P0HI10Q_DESC_MODE) #define BITS_P0HI10Q_DESC_MODE \ (BIT_MASK_P0HI10Q_DESC_MODE << BIT_SHIFT_P0HI10Q_DESC_MODE) #define BIT_CLEAR_P0HI10Q_DESC_MODE(x) ((x) & (~BITS_P0HI10Q_DESC_MODE)) #define BIT_GET_P0HI10Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI10Q_DESC_MODE) & BIT_MASK_P0HI10Q_DESC_MODE) #define BIT_SET_P0HI10Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI10Q_DESC_MODE(x) | BIT_P0HI10Q_DESC_MODE(v)) #define BIT_SHIFT_P0HI10Q_DESC_NUM 0 #define BIT_MASK_P0HI10Q_DESC_NUM 0xfff #define BIT_P0HI10Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI10Q_DESC_NUM) << BIT_SHIFT_P0HI10Q_DESC_NUM) #define BITS_P0HI10Q_DESC_NUM \ (BIT_MASK_P0HI10Q_DESC_NUM << BIT_SHIFT_P0HI10Q_DESC_NUM) #define BIT_CLEAR_P0HI10Q_DESC_NUM(x) ((x) & (~BITS_P0HI10Q_DESC_NUM)) #define BIT_GET_P0HI10Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI10Q_DESC_NUM) & BIT_MASK_P0HI10Q_DESC_NUM) #define BIT_SET_P0HI10Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI10Q_DESC_NUM(x) | BIT_P0HI10Q_DESC_NUM(v)) /* 2 REG_P0HI12Q_HI13Q_TXBD_NUM (Offset 0x23C8) */ #define BIT_P0HI13Q_FLAG BIT(30) #define BIT_SHIFT_P0HI13Q_DESC_MODE 28 #define BIT_MASK_P0HI13Q_DESC_MODE 0x3 #define BIT_P0HI13Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI13Q_DESC_MODE) << BIT_SHIFT_P0HI13Q_DESC_MODE) #define BITS_P0HI13Q_DESC_MODE \ (BIT_MASK_P0HI13Q_DESC_MODE << BIT_SHIFT_P0HI13Q_DESC_MODE) #define BIT_CLEAR_P0HI13Q_DESC_MODE(x) ((x) & (~BITS_P0HI13Q_DESC_MODE)) #define BIT_GET_P0HI13Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI13Q_DESC_MODE) & BIT_MASK_P0HI13Q_DESC_MODE) #define BIT_SET_P0HI13Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI13Q_DESC_MODE(x) | BIT_P0HI13Q_DESC_MODE(v)) #define BIT_SHIFT_P0HI13Q_DESC_NUM 16 #define BIT_MASK_P0HI13Q_DESC_NUM 0xfff #define BIT_P0HI13Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI13Q_DESC_NUM) << BIT_SHIFT_P0HI13Q_DESC_NUM) #define BITS_P0HI13Q_DESC_NUM \ (BIT_MASK_P0HI13Q_DESC_NUM << BIT_SHIFT_P0HI13Q_DESC_NUM) #define BIT_CLEAR_P0HI13Q_DESC_NUM(x) ((x) & (~BITS_P0HI13Q_DESC_NUM)) #define BIT_GET_P0HI13Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI13Q_DESC_NUM) & BIT_MASK_P0HI13Q_DESC_NUM) #define BIT_SET_P0HI13Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI13Q_DESC_NUM(x) | BIT_P0HI13Q_DESC_NUM(v)) #define BIT_P0HI12Q_FLAG BIT(14) #define BIT_SHIFT_P0HI12Q_DESC_MODE 12 #define BIT_MASK_P0HI12Q_DESC_MODE 0x3 #define BIT_P0HI12Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI12Q_DESC_MODE) << BIT_SHIFT_P0HI12Q_DESC_MODE) #define BITS_P0HI12Q_DESC_MODE \ (BIT_MASK_P0HI12Q_DESC_MODE << BIT_SHIFT_P0HI12Q_DESC_MODE) #define BIT_CLEAR_P0HI12Q_DESC_MODE(x) ((x) & (~BITS_P0HI12Q_DESC_MODE)) #define BIT_GET_P0HI12Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI12Q_DESC_MODE) & BIT_MASK_P0HI12Q_DESC_MODE) #define BIT_SET_P0HI12Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI12Q_DESC_MODE(x) | BIT_P0HI12Q_DESC_MODE(v)) #define BIT_SHIFT_P0HI12Q_DESC_NUM 0 #define BIT_MASK_P0HI12Q_DESC_NUM 0xfff #define BIT_P0HI12Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI12Q_DESC_NUM) << BIT_SHIFT_P0HI12Q_DESC_NUM) #define BITS_P0HI12Q_DESC_NUM \ (BIT_MASK_P0HI12Q_DESC_NUM << BIT_SHIFT_P0HI12Q_DESC_NUM) #define BIT_CLEAR_P0HI12Q_DESC_NUM(x) ((x) & (~BITS_P0HI12Q_DESC_NUM)) #define BIT_GET_P0HI12Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI12Q_DESC_NUM) & BIT_MASK_P0HI12Q_DESC_NUM) #define BIT_SET_P0HI12Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI12Q_DESC_NUM(x) | BIT_P0HI12Q_DESC_NUM(v)) /* 2 REG_P0HI14Q_HI15Q_TXBD_NUM (Offset 0x23CC) */ #define BIT_P0HI15Q_FLAG BIT(30) #define BIT_SHIFT_P0HI15Q_DESC_MODE 28 #define BIT_MASK_P0HI15Q_DESC_MODE 0x3 #define BIT_P0HI15Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI15Q_DESC_MODE) << BIT_SHIFT_P0HI15Q_DESC_MODE) #define BITS_P0HI15Q_DESC_MODE \ (BIT_MASK_P0HI15Q_DESC_MODE << BIT_SHIFT_P0HI15Q_DESC_MODE) #define BIT_CLEAR_P0HI15Q_DESC_MODE(x) ((x) & (~BITS_P0HI15Q_DESC_MODE)) #define BIT_GET_P0HI15Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI15Q_DESC_MODE) & BIT_MASK_P0HI15Q_DESC_MODE) #define BIT_SET_P0HI15Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI15Q_DESC_MODE(x) | BIT_P0HI15Q_DESC_MODE(v)) #define BIT_SHIFT_P0HI15Q_DESC_NUM 16 #define BIT_MASK_P0HI15Q_DESC_NUM 0xfff #define BIT_P0HI15Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI15Q_DESC_NUM) << BIT_SHIFT_P0HI15Q_DESC_NUM) #define BITS_P0HI15Q_DESC_NUM \ (BIT_MASK_P0HI15Q_DESC_NUM << BIT_SHIFT_P0HI15Q_DESC_NUM) #define BIT_CLEAR_P0HI15Q_DESC_NUM(x) ((x) & (~BITS_P0HI15Q_DESC_NUM)) #define BIT_GET_P0HI15Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI15Q_DESC_NUM) & BIT_MASK_P0HI15Q_DESC_NUM) #define BIT_SET_P0HI15Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI15Q_DESC_NUM(x) | BIT_P0HI15Q_DESC_NUM(v)) #define BIT_P0HI14Q_FLAG BIT(14) #define BIT_SHIFT_P0HI14Q_DESC_MODE 12 #define BIT_MASK_P0HI14Q_DESC_MODE 0x3 #define BIT_P0HI14Q_DESC_MODE(x) \ (((x) & BIT_MASK_P0HI14Q_DESC_MODE) << BIT_SHIFT_P0HI14Q_DESC_MODE) #define BITS_P0HI14Q_DESC_MODE \ (BIT_MASK_P0HI14Q_DESC_MODE << BIT_SHIFT_P0HI14Q_DESC_MODE) #define BIT_CLEAR_P0HI14Q_DESC_MODE(x) ((x) & (~BITS_P0HI14Q_DESC_MODE)) #define BIT_GET_P0HI14Q_DESC_MODE(x) \ (((x) >> BIT_SHIFT_P0HI14Q_DESC_MODE) & BIT_MASK_P0HI14Q_DESC_MODE) #define BIT_SET_P0HI14Q_DESC_MODE(x, v) \ (BIT_CLEAR_P0HI14Q_DESC_MODE(x) | BIT_P0HI14Q_DESC_MODE(v)) #define BIT_SHIFT_P0HI14Q_DESC_NUM 0 #define BIT_MASK_P0HI14Q_DESC_NUM 0xfff #define BIT_P0HI14Q_DESC_NUM(x) \ (((x) & BIT_MASK_P0HI14Q_DESC_NUM) << BIT_SHIFT_P0HI14Q_DESC_NUM) #define BITS_P0HI14Q_DESC_NUM \ (BIT_MASK_P0HI14Q_DESC_NUM << BIT_SHIFT_P0HI14Q_DESC_NUM) #define BIT_CLEAR_P0HI14Q_DESC_NUM(x) ((x) & (~BITS_P0HI14Q_DESC_NUM)) #define BIT_GET_P0HI14Q_DESC_NUM(x) \ (((x) >> BIT_SHIFT_P0HI14Q_DESC_NUM) & BIT_MASK_P0HI14Q_DESC_NUM) #define BIT_SET_P0HI14Q_DESC_NUM(x, v) \ (BIT_CLEAR_P0HI14Q_DESC_NUM(x) | BIT_P0HI14Q_DESC_NUM(v)) /* 2 REG_ACH6_ACH7_TXBD_NUM (Offset 0x23F0) */ #define BIT_PCIE_ACH7_FLAG BIT(30) #define BIT_SHIFT_ACH7_DESC_MODE 28 #define BIT_MASK_ACH7_DESC_MODE 0x3 #define BIT_ACH7_DESC_MODE(x) \ (((x) & BIT_MASK_ACH7_DESC_MODE) << BIT_SHIFT_ACH7_DESC_MODE) #define BITS_ACH7_DESC_MODE \ (BIT_MASK_ACH7_DESC_MODE << BIT_SHIFT_ACH7_DESC_MODE) #define BIT_CLEAR_ACH7_DESC_MODE(x) ((x) & (~BITS_ACH7_DESC_MODE)) #define BIT_GET_ACH7_DESC_MODE(x) \ (((x) >> BIT_SHIFT_ACH7_DESC_MODE) & BIT_MASK_ACH7_DESC_MODE) #define BIT_SET_ACH7_DESC_MODE(x, v) \ (BIT_CLEAR_ACH7_DESC_MODE(x) | BIT_ACH7_DESC_MODE(v)) #define BIT_SHIFT_ACH7_DESC_NUM 16 #define BIT_MASK_ACH7_DESC_NUM 0xfff #define BIT_ACH7_DESC_NUM(x) \ (((x) & BIT_MASK_ACH7_DESC_NUM) << BIT_SHIFT_ACH7_DESC_NUM) #define BITS_ACH7_DESC_NUM (BIT_MASK_ACH7_DESC_NUM << BIT_SHIFT_ACH7_DESC_NUM) #define BIT_CLEAR_ACH7_DESC_NUM(x) ((x) & (~BITS_ACH7_DESC_NUM)) #define BIT_GET_ACH7_DESC_NUM(x) \ (((x) >> BIT_SHIFT_ACH7_DESC_NUM) & BIT_MASK_ACH7_DESC_NUM) #define BIT_SET_ACH7_DESC_NUM(x, v) \ (BIT_CLEAR_ACH7_DESC_NUM(x) | BIT_ACH7_DESC_NUM(v)) #define BIT_PCIE_ACH6_FLAG BIT(14) #define BIT_SHIFT_ACH6_DESC_MODE 12 #define BIT_MASK_ACH6_DESC_MODE 0x3 #define BIT_ACH6_DESC_MODE(x) \ (((x) & BIT_MASK_ACH6_DESC_MODE) << BIT_SHIFT_ACH6_DESC_MODE) #define BITS_ACH6_DESC_MODE \ (BIT_MASK_ACH6_DESC_MODE << BIT_SHIFT_ACH6_DESC_MODE) #define BIT_CLEAR_ACH6_DESC_MODE(x) ((x) & (~BITS_ACH6_DESC_MODE)) #define BIT_GET_ACH6_DESC_MODE(x) \ (((x) >> BIT_SHIFT_ACH6_DESC_MODE) & BIT_MASK_ACH6_DESC_MODE) #define BIT_SET_ACH6_DESC_MODE(x, v) \ (BIT_CLEAR_ACH6_DESC_MODE(x) | BIT_ACH6_DESC_MODE(v)) #define BIT_SHIFT_ACH6_DESC_NUM 0 #define BIT_MASK_ACH6_DESC_NUM 0xfff #define BIT_ACH6_DESC_NUM(x) \ (((x) & BIT_MASK_ACH6_DESC_NUM) << BIT_SHIFT_ACH6_DESC_NUM) #define BITS_ACH6_DESC_NUM (BIT_MASK_ACH6_DESC_NUM << BIT_SHIFT_ACH6_DESC_NUM) #define BIT_CLEAR_ACH6_DESC_NUM(x) ((x) & (~BITS_ACH6_DESC_NUM)) #define BIT_GET_ACH6_DESC_NUM(x) \ (((x) >> BIT_SHIFT_ACH6_DESC_NUM) & BIT_MASK_ACH6_DESC_NUM) #define BIT_SET_ACH6_DESC_NUM(x, v) \ (BIT_CLEAR_ACH6_DESC_NUM(x) | BIT_ACH6_DESC_NUM(v)) /* 2 REG_TXPAGE_INT_CTRL_0 (Offset 0x3200) */ #define BIT_CH0_INT_EN BIT(31) #define BIT_SHIFT_CH0_HIGH_TH 16 #define BIT_MASK_CH0_HIGH_TH 0xfff #define BIT_CH0_HIGH_TH(x) \ (((x) & BIT_MASK_CH0_HIGH_TH) << BIT_SHIFT_CH0_HIGH_TH) #define BITS_CH0_HIGH_TH (BIT_MASK_CH0_HIGH_TH << BIT_SHIFT_CH0_HIGH_TH) #define BIT_CLEAR_CH0_HIGH_TH(x) ((x) & (~BITS_CH0_HIGH_TH)) #define BIT_GET_CH0_HIGH_TH(x) \ (((x) >> BIT_SHIFT_CH0_HIGH_TH) & BIT_MASK_CH0_HIGH_TH) #define BIT_SET_CH0_HIGH_TH(x, v) \ (BIT_CLEAR_CH0_HIGH_TH(x) | BIT_CH0_HIGH_TH(v)) #define BIT_SHIFT_CH0_LOW_TH 0 #define BIT_MASK_CH0_LOW_TH 0xfff #define BIT_CH0_LOW_TH(x) (((x) & BIT_MASK_CH0_LOW_TH) << BIT_SHIFT_CH0_LOW_TH) #define BITS_CH0_LOW_TH (BIT_MASK_CH0_LOW_TH << BIT_SHIFT_CH0_LOW_TH) #define BIT_CLEAR_CH0_LOW_TH(x) ((x) & (~BITS_CH0_LOW_TH)) #define BIT_GET_CH0_LOW_TH(x) \ (((x) >> BIT_SHIFT_CH0_LOW_TH) & BIT_MASK_CH0_LOW_TH) #define BIT_SET_CH0_LOW_TH(x, v) (BIT_CLEAR_CH0_LOW_TH(x) | BIT_CH0_LOW_TH(v)) /* 2 REG_TXPAGE_INT_CTRL_1 (Offset 0x3204) */ #define BIT_CH1_INT_EN BIT(31) #define BIT_SHIFT_CH1_HIGH_TH 16 #define BIT_MASK_CH1_HIGH_TH 0xfff #define BIT_CH1_HIGH_TH(x) \ (((x) & BIT_MASK_CH1_HIGH_TH) << BIT_SHIFT_CH1_HIGH_TH) #define BITS_CH1_HIGH_TH (BIT_MASK_CH1_HIGH_TH << BIT_SHIFT_CH1_HIGH_TH) #define BIT_CLEAR_CH1_HIGH_TH(x) ((x) & (~BITS_CH1_HIGH_TH)) #define BIT_GET_CH1_HIGH_TH(x) \ (((x) >> BIT_SHIFT_CH1_HIGH_TH) & BIT_MASK_CH1_HIGH_TH) #define BIT_SET_CH1_HIGH_TH(x, v) \ (BIT_CLEAR_CH1_HIGH_TH(x) | BIT_CH1_HIGH_TH(v)) #define BIT_SHIFT_CH1_LOW_TH 0 #define BIT_MASK_CH1_LOW_TH 0xfff #define BIT_CH1_LOW_TH(x) (((x) & BIT_MASK_CH1_LOW_TH) << BIT_SHIFT_CH1_LOW_TH) #define BITS_CH1_LOW_TH (BIT_MASK_CH1_LOW_TH << BIT_SHIFT_CH1_LOW_TH) #define BIT_CLEAR_CH1_LOW_TH(x) ((x) & (~BITS_CH1_LOW_TH)) #define BIT_GET_CH1_LOW_TH(x) \ (((x) >> BIT_SHIFT_CH1_LOW_TH) & BIT_MASK_CH1_LOW_TH) #define BIT_SET_CH1_LOW_TH(x, v) (BIT_CLEAR_CH1_LOW_TH(x) | BIT_CH1_LOW_TH(v)) /* 2 REG_TXPAGE_INT_CTRL_2 (Offset 0x3208) */ #define BIT_CH2_INT_EN BIT(31) #define BIT_SHIFT_CH2_HIGH_TH 16 #define BIT_MASK_CH2_HIGH_TH 0xfff #define BIT_CH2_HIGH_TH(x) \ (((x) & BIT_MASK_CH2_HIGH_TH) << BIT_SHIFT_CH2_HIGH_TH) #define BITS_CH2_HIGH_TH (BIT_MASK_CH2_HIGH_TH << BIT_SHIFT_CH2_HIGH_TH) #define BIT_CLEAR_CH2_HIGH_TH(x) ((x) & (~BITS_CH2_HIGH_TH)) #define BIT_GET_CH2_HIGH_TH(x) \ (((x) >> BIT_SHIFT_CH2_HIGH_TH) & BIT_MASK_CH2_HIGH_TH) #define BIT_SET_CH2_HIGH_TH(x, v) \ (BIT_CLEAR_CH2_HIGH_TH(x) | BIT_CH2_HIGH_TH(v)) #define BIT_SHIFT_CH2_LOW_TH 0 #define BIT_MASK_CH2_LOW_TH 0xfff #define BIT_CH2_LOW_TH(x) (((x) & BIT_MASK_CH2_LOW_TH) << BIT_SHIFT_CH2_LOW_TH) #define BITS_CH2_LOW_TH (BIT_MASK_CH2_LOW_TH << BIT_SHIFT_CH2_LOW_TH) #define BIT_CLEAR_CH2_LOW_TH(x) ((x) & (~BITS_CH2_LOW_TH)) #define BIT_GET_CH2_LOW_TH(x) \ (((x) >> BIT_SHIFT_CH2_LOW_TH) & BIT_MASK_CH2_LOW_TH) #define BIT_SET_CH2_LOW_TH(x, v) (BIT_CLEAR_CH2_LOW_TH(x) | BIT_CH2_LOW_TH(v)) /* 2 REG_TXPAGE_INT_CTRL_3 (Offset 0x320C) */ #define BIT_CH3_INT_EN BIT(31) #define BIT_SHIFT_CH3_HIGH_TH 16 #define BIT_MASK_CH3_HIGH_TH 0xfff #define BIT_CH3_HIGH_TH(x) \ (((x) & BIT_MASK_CH3_HIGH_TH) << BIT_SHIFT_CH3_HIGH_TH) #define BITS_CH3_HIGH_TH (BIT_MASK_CH3_HIGH_TH << BIT_SHIFT_CH3_HIGH_TH) #define BIT_CLEAR_CH3_HIGH_TH(x) ((x) & (~BITS_CH3_HIGH_TH)) #define BIT_GET_CH3_HIGH_TH(x) \ (((x) >> BIT_SHIFT_CH3_HIGH_TH) & BIT_MASK_CH3_HIGH_TH) #define BIT_SET_CH3_HIGH_TH(x, v) \ (BIT_CLEAR_CH3_HIGH_TH(x) | BIT_CH3_HIGH_TH(v)) #define BIT_SHIFT_CH3_LOW_TH 0 #define BIT_MASK_CH3_LOW_TH 0xfff #define BIT_CH3_LOW_TH(x) (((x) & BIT_MASK_CH3_LOW_TH) << BIT_SHIFT_CH3_LOW_TH) #define BITS_CH3_LOW_TH (BIT_MASK_CH3_LOW_TH << BIT_SHIFT_CH3_LOW_TH) #define BIT_CLEAR_CH3_LOW_TH(x) ((x) & (~BITS_CH3_LOW_TH)) #define BIT_GET_CH3_LOW_TH(x) \ (((x) >> BIT_SHIFT_CH3_LOW_TH) & BIT_MASK_CH3_LOW_TH) #define BIT_SET_CH3_LOW_TH(x, v) (BIT_CLEAR_CH3_LOW_TH(x) | BIT_CH3_LOW_TH(v)) /* 2 REG_TXPAGE_INT_CTRL_4 (Offset 0x3210) */ #define BIT_CH4_INT_EN BIT(31) #define BIT_SHIFT_CH4_HIGH_TH 16 #define BIT_MASK_CH4_HIGH_TH 0xfff #define BIT_CH4_HIGH_TH(x) \ (((x) & BIT_MASK_CH4_HIGH_TH) << BIT_SHIFT_CH4_HIGH_TH) #define BITS_CH4_HIGH_TH (BIT_MASK_CH4_HIGH_TH << BIT_SHIFT_CH4_HIGH_TH) #define BIT_CLEAR_CH4_HIGH_TH(x) ((x) & (~BITS_CH4_HIGH_TH)) #define BIT_GET_CH4_HIGH_TH(x) \ (((x) >> BIT_SHIFT_CH4_HIGH_TH) & BIT_MASK_CH4_HIGH_TH) #define BIT_SET_CH4_HIGH_TH(x, v) \ (BIT_CLEAR_CH4_HIGH_TH(x) | BIT_CH4_HIGH_TH(v)) #define BIT_SHIFT_CH4_LOW_TH 0 #define BIT_MASK_CH4_LOW_TH 0xfff #define BIT_CH4_LOW_TH(x) (((x) & BIT_MASK_CH4_LOW_TH) << BIT_SHIFT_CH4_LOW_TH) #define BITS_CH4_LOW_TH (BIT_MASK_CH4_LOW_TH << BIT_SHIFT_CH4_LOW_TH) #define BIT_CLEAR_CH4_LOW_TH(x) ((x) & (~BITS_CH4_LOW_TH)) #define BIT_GET_CH4_LOW_TH(x) \ (((x) >> BIT_SHIFT_CH4_LOW_TH) & BIT_MASK_CH4_LOW_TH) #define BIT_SET_CH4_LOW_TH(x, v) (BIT_CLEAR_CH4_LOW_TH(x) | BIT_CH4_LOW_TH(v)) /* 2 REG_TXPAGE_INT_CTRL_5 (Offset 0x3214) */ #define BIT_CH5_INT_EN BIT(31) #define BIT_SHIFT_CH5_HIGH_TH 16 #define BIT_MASK_CH5_HIGH_TH 0xfff #define BIT_CH5_HIGH_TH(x) \ (((x) & BIT_MASK_CH5_HIGH_TH) << BIT_SHIFT_CH5_HIGH_TH) #define BITS_CH5_HIGH_TH (BIT_MASK_CH5_HIGH_TH << BIT_SHIFT_CH5_HIGH_TH) #define BIT_CLEAR_CH5_HIGH_TH(x) ((x) & (~BITS_CH5_HIGH_TH)) #define BIT_GET_CH5_HIGH_TH(x) \ (((x) >> BIT_SHIFT_CH5_HIGH_TH) & BIT_MASK_CH5_HIGH_TH) #define BIT_SET_CH5_HIGH_TH(x, v) \ (BIT_CLEAR_CH5_HIGH_TH(x) | BIT_CH5_HIGH_TH(v)) #define BIT_SHIFT_CH5_LOW_TH 0 #define BIT_MASK_CH5_LOW_TH 0xfff #define BIT_CH5_LOW_TH(x) (((x) & BIT_MASK_CH5_LOW_TH) << BIT_SHIFT_CH5_LOW_TH) #define BITS_CH5_LOW_TH (BIT_MASK_CH5_LOW_TH << BIT_SHIFT_CH5_LOW_TH) #define BIT_CLEAR_CH5_LOW_TH(x) ((x) & (~BITS_CH5_LOW_TH)) #define BIT_GET_CH5_LOW_TH(x) \ (((x) >> BIT_SHIFT_CH5_LOW_TH) & BIT_MASK_CH5_LOW_TH) #define BIT_SET_CH5_LOW_TH(x, v) (BIT_CLEAR_CH5_LOW_TH(x) | BIT_CH5_LOW_TH(v)) /* 2 REG_TXPAGE_INT_CTRL_6 (Offset 0x3218) */ #define BIT_CH6_INT_EN BIT(31) #define BIT_SHIFT_CH6_HIGH_TH 16 #define BIT_MASK_CH6_HIGH_TH 0xfff #define BIT_CH6_HIGH_TH(x) \ (((x) & BIT_MASK_CH6_HIGH_TH) << BIT_SHIFT_CH6_HIGH_TH) #define BITS_CH6_HIGH_TH (BIT_MASK_CH6_HIGH_TH << BIT_SHIFT_CH6_HIGH_TH) #define BIT_CLEAR_CH6_HIGH_TH(x) ((x) & (~BITS_CH6_HIGH_TH)) #define BIT_GET_CH6_HIGH_TH(x) \ (((x) >> BIT_SHIFT_CH6_HIGH_TH) & BIT_MASK_CH6_HIGH_TH) #define BIT_SET_CH6_HIGH_TH(x, v) \ (BIT_CLEAR_CH6_HIGH_TH(x) | BIT_CH6_HIGH_TH(v)) #define BIT_SHIFT_CH6_LOW_TH 0 #define BIT_MASK_CH6_LOW_TH 0xfff #define BIT_CH6_LOW_TH(x) (((x) & BIT_MASK_CH6_LOW_TH) << BIT_SHIFT_CH6_LOW_TH) #define BITS_CH6_LOW_TH (BIT_MASK_CH6_LOW_TH << BIT_SHIFT_CH6_LOW_TH) #define BIT_CLEAR_CH6_LOW_TH(x) ((x) & (~BITS_CH6_LOW_TH)) #define BIT_GET_CH6_LOW_TH(x) \ (((x) >> BIT_SHIFT_CH6_LOW_TH) & BIT_MASK_CH6_LOW_TH) #define BIT_SET_CH6_LOW_TH(x, v) (BIT_CLEAR_CH6_LOW_TH(x) | BIT_CH6_LOW_TH(v)) /* 2 REG_TXPAGE_INT_CTRL_7 (Offset 0x321C) */ #define BIT_CH7_INT_EN BIT(31) #define BIT_SHIFT_CH7_HIGH_TH 16 #define BIT_MASK_CH7_HIGH_TH 0xfff #define BIT_CH7_HIGH_TH(x) \ (((x) & BIT_MASK_CH7_HIGH_TH) << BIT_SHIFT_CH7_HIGH_TH) #define BITS_CH7_HIGH_TH (BIT_MASK_CH7_HIGH_TH << BIT_SHIFT_CH7_HIGH_TH) #define BIT_CLEAR_CH7_HIGH_TH(x) ((x) & (~BITS_CH7_HIGH_TH)) #define BIT_GET_CH7_HIGH_TH(x) \ (((x) >> BIT_SHIFT_CH7_HIGH_TH) & BIT_MASK_CH7_HIGH_TH) #define BIT_SET_CH7_HIGH_TH(x, v) \ (BIT_CLEAR_CH7_HIGH_TH(x) | BIT_CH7_HIGH_TH(v)) #define BIT_SHIFT_CH7_LOW_TH 0 #define BIT_MASK_CH7_LOW_TH 0xfff #define BIT_CH7_LOW_TH(x) (((x) & BIT_MASK_CH7_LOW_TH) << BIT_SHIFT_CH7_LOW_TH) #define BITS_CH7_LOW_TH (BIT_MASK_CH7_LOW_TH << BIT_SHIFT_CH7_LOW_TH) #define BIT_CLEAR_CH7_LOW_TH(x) ((x) & (~BITS_CH7_LOW_TH)) #define BIT_GET_CH7_LOW_TH(x) \ (((x) >> BIT_SHIFT_CH7_LOW_TH) & BIT_MASK_CH7_LOW_TH) #define BIT_SET_CH7_LOW_TH(x, v) (BIT_CLEAR_CH7_LOW_TH(x) | BIT_CH7_LOW_TH(v)) /* 2 REG_TXPAGE_INT_CTRL_8 (Offset 0x3220) */ #define BIT_CH8_INT_EN BIT(31) #define BIT_SHIFT_CH8_HIGH_TH 16 #define BIT_MASK_CH8_HIGH_TH 0xfff #define BIT_CH8_HIGH_TH(x) \ (((x) & BIT_MASK_CH8_HIGH_TH) << BIT_SHIFT_CH8_HIGH_TH) #define BITS_CH8_HIGH_TH (BIT_MASK_CH8_HIGH_TH << BIT_SHIFT_CH8_HIGH_TH) #define BIT_CLEAR_CH8_HIGH_TH(x) ((x) & (~BITS_CH8_HIGH_TH)) #define BIT_GET_CH8_HIGH_TH(x) \ (((x) >> BIT_SHIFT_CH8_HIGH_TH) & BIT_MASK_CH8_HIGH_TH) #define BIT_SET_CH8_HIGH_TH(x, v) \ (BIT_CLEAR_CH8_HIGH_TH(x) | BIT_CH8_HIGH_TH(v)) #define BIT_SHIFT_CH8_LOW_TH 0 #define BIT_MASK_CH8_LOW_TH 0xfff #define BIT_CH8_LOW_TH(x) (((x) & BIT_MASK_CH8_LOW_TH) << BIT_SHIFT_CH8_LOW_TH) #define BITS_CH8_LOW_TH (BIT_MASK_CH8_LOW_TH << BIT_SHIFT_CH8_LOW_TH) #define BIT_CLEAR_CH8_LOW_TH(x) ((x) & (~BITS_CH8_LOW_TH)) #define BIT_GET_CH8_LOW_TH(x) \ (((x) >> BIT_SHIFT_CH8_LOW_TH) & BIT_MASK_CH8_LOW_TH) #define BIT_SET_CH8_LOW_TH(x, v) (BIT_CLEAR_CH8_LOW_TH(x) | BIT_CH8_LOW_TH(v)) /* 2 REG_TXPAGE_INT_CTRL_9 (Offset 0x3224) */ #define BIT_CH9_INT_EN BIT(31) #define BIT_SHIFT_CH9_HIGH_TH 16 #define BIT_MASK_CH9_HIGH_TH 0xfff #define BIT_CH9_HIGH_TH(x) \ (((x) & BIT_MASK_CH9_HIGH_TH) << BIT_SHIFT_CH9_HIGH_TH) #define BITS_CH9_HIGH_TH (BIT_MASK_CH9_HIGH_TH << BIT_SHIFT_CH9_HIGH_TH) #define BIT_CLEAR_CH9_HIGH_TH(x) ((x) & (~BITS_CH9_HIGH_TH)) #define BIT_GET_CH9_HIGH_TH(x) \ (((x) >> BIT_SHIFT_CH9_HIGH_TH) & BIT_MASK_CH9_HIGH_TH) #define BIT_SET_CH9_HIGH_TH(x, v) \ (BIT_CLEAR_CH9_HIGH_TH(x) | BIT_CH9_HIGH_TH(v)) #define BIT_SHIFT_CH9_LOW_TH 0 #define BIT_MASK_CH9_LOW_TH 0xfff #define BIT_CH9_LOW_TH(x) (((x) & BIT_MASK_CH9_LOW_TH) << BIT_SHIFT_CH9_LOW_TH) #define BITS_CH9_LOW_TH (BIT_MASK_CH9_LOW_TH << BIT_SHIFT_CH9_LOW_TH) #define BIT_CLEAR_CH9_LOW_TH(x) ((x) & (~BITS_CH9_LOW_TH)) #define BIT_GET_CH9_LOW_TH(x) \ (((x) >> BIT_SHIFT_CH9_LOW_TH) & BIT_MASK_CH9_LOW_TH) #define BIT_SET_CH9_LOW_TH(x, v) (BIT_CLEAR_CH9_LOW_TH(x) | BIT_CH9_LOW_TH(v)) /* 2 REG_TXPAGE_INT_CTRL_10 (Offset 0x3228) */ #define BIT_CH10_INT_EN BIT(31) #define BIT_SHIFT_CH10_HIGH_TH 16 #define BIT_MASK_CH10_HIGH_TH 0xfff #define BIT_CH10_HIGH_TH(x) \ (((x) & BIT_MASK_CH10_HIGH_TH) << BIT_SHIFT_CH10_HIGH_TH) #define BITS_CH10_HIGH_TH (BIT_MASK_CH10_HIGH_TH << BIT_SHIFT_CH10_HIGH_TH) #define BIT_CLEAR_CH10_HIGH_TH(x) ((x) & (~BITS_CH10_HIGH_TH)) #define BIT_GET_CH10_HIGH_TH(x) \ (((x) >> BIT_SHIFT_CH10_HIGH_TH) & BIT_MASK_CH10_HIGH_TH) #define BIT_SET_CH10_HIGH_TH(x, v) \ (BIT_CLEAR_CH10_HIGH_TH(x) | BIT_CH10_HIGH_TH(v)) #define BIT_SHIFT_CH10_LOW_TH 0 #define BIT_MASK_CH10_LOW_TH 0xfff #define BIT_CH10_LOW_TH(x) \ (((x) & BIT_MASK_CH10_LOW_TH) << BIT_SHIFT_CH10_LOW_TH) #define BITS_CH10_LOW_TH (BIT_MASK_CH10_LOW_TH << BIT_SHIFT_CH10_LOW_TH) #define BIT_CLEAR_CH10_LOW_TH(x) ((x) & (~BITS_CH10_LOW_TH)) #define BIT_GET_CH10_LOW_TH(x) \ (((x) >> BIT_SHIFT_CH10_LOW_TH) & BIT_MASK_CH10_LOW_TH) #define BIT_SET_CH10_LOW_TH(x, v) \ (BIT_CLEAR_CH10_LOW_TH(x) | BIT_CH10_LOW_TH(v)) /* 2 REG_TXPAGE_INT_CTRL_11 (Offset 0x322C) */ #define BIT_CH11_INT_EN BIT(31) #define BIT_SHIFT_CH11_HIGH_TH 16 #define BIT_MASK_CH11_HIGH_TH 0xfff #define BIT_CH11_HIGH_TH(x) \ (((x) & BIT_MASK_CH11_HIGH_TH) << BIT_SHIFT_CH11_HIGH_TH) #define BITS_CH11_HIGH_TH (BIT_MASK_CH11_HIGH_TH << BIT_SHIFT_CH11_HIGH_TH) #define BIT_CLEAR_CH11_HIGH_TH(x) ((x) & (~BITS_CH11_HIGH_TH)) #define BIT_GET_CH11_HIGH_TH(x) \ (((x) >> BIT_SHIFT_CH11_HIGH_TH) & BIT_MASK_CH11_HIGH_TH) #define BIT_SET_CH11_HIGH_TH(x, v) \ (BIT_CLEAR_CH11_HIGH_TH(x) | BIT_CH11_HIGH_TH(v)) #define BIT_SHIFT_CH11_LOW_TH 0 #define BIT_MASK_CH11_LOW_TH 0xfff #define BIT_CH11_LOW_TH(x) \ (((x) & BIT_MASK_CH11_LOW_TH) << BIT_SHIFT_CH11_LOW_TH) #define BITS_CH11_LOW_TH (BIT_MASK_CH11_LOW_TH << BIT_SHIFT_CH11_LOW_TH) #define BIT_CLEAR_CH11_LOW_TH(x) ((x) & (~BITS_CH11_LOW_TH)) #define BIT_GET_CH11_LOW_TH(x) \ (((x) >> BIT_SHIFT_CH11_LOW_TH) & BIT_MASK_CH11_LOW_TH) #define BIT_SET_CH11_LOW_TH(x, v) \ (BIT_CLEAR_CH11_LOW_TH(x) | BIT_CH11_LOW_TH(v)) /* 2 REG_TXPAGE_INT_CTRL_12 (Offset 0x3230) */ #define BIT_CH12_INT_EN BIT(31) #define BIT_SHIFT_CH12_HIGH_TH 16 #define BIT_MASK_CH12_HIGH_TH 0xfff #define BIT_CH12_HIGH_TH(x) \ (((x) & BIT_MASK_CH12_HIGH_TH) << BIT_SHIFT_CH12_HIGH_TH) #define BITS_CH12_HIGH_TH (BIT_MASK_CH12_HIGH_TH << BIT_SHIFT_CH12_HIGH_TH) #define BIT_CLEAR_CH12_HIGH_TH(x) ((x) & (~BITS_CH12_HIGH_TH)) #define BIT_GET_CH12_HIGH_TH(x) \ (((x) >> BIT_SHIFT_CH12_HIGH_TH) & BIT_MASK_CH12_HIGH_TH) #define BIT_SET_CH12_HIGH_TH(x, v) \ (BIT_CLEAR_CH12_HIGH_TH(x) | BIT_CH12_HIGH_TH(v)) #define BIT_SHIFT_CH12_LOW_TH 0 #define BIT_MASK_CH12_LOW_TH 0xfff #define BIT_CH12_LOW_TH(x) \ (((x) & BIT_MASK_CH12_LOW_TH) << BIT_SHIFT_CH12_LOW_TH) #define BITS_CH12_LOW_TH (BIT_MASK_CH12_LOW_TH << BIT_SHIFT_CH12_LOW_TH) #define BIT_CLEAR_CH12_LOW_TH(x) ((x) & (~BITS_CH12_LOW_TH)) #define BIT_GET_CH12_LOW_TH(x) \ (((x) >> BIT_SHIFT_CH12_LOW_TH) & BIT_MASK_CH12_LOW_TH) #define BIT_SET_CH12_LOW_TH(x, v) \ (BIT_CLEAR_CH12_LOW_TH(x) | BIT_CH12_LOW_TH(v)) /* 2 REG_TXPAGE_INT_CTRL_13 (Offset 0x3234) */ #define BIT_CH13_INT_EN BIT(31) #define BIT_SHIFT_CH13_HIGH_TH 16 #define BIT_MASK_CH13_HIGH_TH 0xfff #define BIT_CH13_HIGH_TH(x) \ (((x) & BIT_MASK_CH13_HIGH_TH) << BIT_SHIFT_CH13_HIGH_TH) #define BITS_CH13_HIGH_TH (BIT_MASK_CH13_HIGH_TH << BIT_SHIFT_CH13_HIGH_TH) #define BIT_CLEAR_CH13_HIGH_TH(x) ((x) & (~BITS_CH13_HIGH_TH)) #define BIT_GET_CH13_HIGH_TH(x) \ (((x) >> BIT_SHIFT_CH13_HIGH_TH) & BIT_MASK_CH13_HIGH_TH) #define BIT_SET_CH13_HIGH_TH(x, v) \ (BIT_CLEAR_CH13_HIGH_TH(x) | BIT_CH13_HIGH_TH(v)) #define BIT_SHIFT_CH13_LOW_TH 0 #define BIT_MASK_CH13_LOW_TH 0xfff #define BIT_CH13_LOW_TH(x) \ (((x) & BIT_MASK_CH13_LOW_TH) << BIT_SHIFT_CH13_LOW_TH) #define BITS_CH13_LOW_TH (BIT_MASK_CH13_LOW_TH << BIT_SHIFT_CH13_LOW_TH) #define BIT_CLEAR_CH13_LOW_TH(x) ((x) & (~BITS_CH13_LOW_TH)) #define BIT_GET_CH13_LOW_TH(x) \ (((x) >> BIT_SHIFT_CH13_LOW_TH) & BIT_MASK_CH13_LOW_TH) #define BIT_SET_CH13_LOW_TH(x, v) \ (BIT_CLEAR_CH13_LOW_TH(x) | BIT_CH13_LOW_TH(v)) /* 2 REG_TXPAGE_INT_CTRL_14 (Offset 0x3238) */ #define BIT_CH14_INT_EN BIT(31) #define BIT_SHIFT_CH14_HIGH_TH 16 #define BIT_MASK_CH14_HIGH_TH 0xfff #define BIT_CH14_HIGH_TH(x) \ (((x) & BIT_MASK_CH14_HIGH_TH) << BIT_SHIFT_CH14_HIGH_TH) #define BITS_CH14_HIGH_TH (BIT_MASK_CH14_HIGH_TH << BIT_SHIFT_CH14_HIGH_TH) #define BIT_CLEAR_CH14_HIGH_TH(x) ((x) & (~BITS_CH14_HIGH_TH)) #define BIT_GET_CH14_HIGH_TH(x) \ (((x) >> BIT_SHIFT_CH14_HIGH_TH) & BIT_MASK_CH14_HIGH_TH) #define BIT_SET_CH14_HIGH_TH(x, v) \ (BIT_CLEAR_CH14_HIGH_TH(x) | BIT_CH14_HIGH_TH(v)) #define BIT_SHIFT_CH14_LOW_TH 0 #define BIT_MASK_CH14_LOW_TH 0xfff #define BIT_CH14_LOW_TH(x) \ (((x) & BIT_MASK_CH14_LOW_TH) << BIT_SHIFT_CH14_LOW_TH) #define BITS_CH14_LOW_TH (BIT_MASK_CH14_LOW_TH << BIT_SHIFT_CH14_LOW_TH) #define BIT_CLEAR_CH14_LOW_TH(x) ((x) & (~BITS_CH14_LOW_TH)) #define BIT_GET_CH14_LOW_TH(x) \ (((x) >> BIT_SHIFT_CH14_LOW_TH) & BIT_MASK_CH14_LOW_TH) #define BIT_SET_CH14_LOW_TH(x, v) \ (BIT_CLEAR_CH14_LOW_TH(x) | BIT_CH14_LOW_TH(v)) /* 2 REG_TXPAGE_INT_CTRL_15 (Offset 0x323C) */ #define BIT_CH15_INT_EN BIT(31) #define BIT_SHIFT_CH15_HIGH_TH 16 #define BIT_MASK_CH15_HIGH_TH 0xfff #define BIT_CH15_HIGH_TH(x) \ (((x) & BIT_MASK_CH15_HIGH_TH) << BIT_SHIFT_CH15_HIGH_TH) #define BITS_CH15_HIGH_TH (BIT_MASK_CH15_HIGH_TH << BIT_SHIFT_CH15_HIGH_TH) #define BIT_CLEAR_CH15_HIGH_TH(x) ((x) & (~BITS_CH15_HIGH_TH)) #define BIT_GET_CH15_HIGH_TH(x) \ (((x) >> BIT_SHIFT_CH15_HIGH_TH) & BIT_MASK_CH15_HIGH_TH) #define BIT_SET_CH15_HIGH_TH(x, v) \ (BIT_CLEAR_CH15_HIGH_TH(x) | BIT_CH15_HIGH_TH(v)) #define BIT_SHIFT_CH15_LOW_TH 0 #define BIT_MASK_CH15_LOW_TH 0xfff #define BIT_CH15_LOW_TH(x) \ (((x) & BIT_MASK_CH15_LOW_TH) << BIT_SHIFT_CH15_LOW_TH) #define BITS_CH15_LOW_TH (BIT_MASK_CH15_LOW_TH << BIT_SHIFT_CH15_LOW_TH) #define BIT_CLEAR_CH15_LOW_TH(x) ((x) & (~BITS_CH15_LOW_TH)) #define BIT_GET_CH15_LOW_TH(x) \ (((x) >> BIT_SHIFT_CH15_LOW_TH) & BIT_MASK_CH15_LOW_TH) #define BIT_SET_CH15_LOW_TH(x, v) \ (BIT_CLEAR_CH15_LOW_TH(x) | BIT_CH15_LOW_TH(v)) /* 2 REG_TXPAGE_INT_CTRL_16 (Offset 0x3240) */ #define BIT_CH16_INT_EN BIT(31) #define BIT_SHIFT_CH16_HIGH_TH 16 #define BIT_MASK_CH16_HIGH_TH 0xfff #define BIT_CH16_HIGH_TH(x) \ (((x) & BIT_MASK_CH16_HIGH_TH) << BIT_SHIFT_CH16_HIGH_TH) #define BITS_CH16_HIGH_TH (BIT_MASK_CH16_HIGH_TH << BIT_SHIFT_CH16_HIGH_TH) #define BIT_CLEAR_CH16_HIGH_TH(x) ((x) & (~BITS_CH16_HIGH_TH)) #define BIT_GET_CH16_HIGH_TH(x) \ (((x) >> BIT_SHIFT_CH16_HIGH_TH) & BIT_MASK_CH16_HIGH_TH) #define BIT_SET_CH16_HIGH_TH(x, v) \ (BIT_CLEAR_CH16_HIGH_TH(x) | BIT_CH16_HIGH_TH(v)) #define BIT_SHIFT_CH16_LOW_TH 0 #define BIT_MASK_CH16_LOW_TH 0xfff #define BIT_CH16_LOW_TH(x) \ (((x) & BIT_MASK_CH16_LOW_TH) << BIT_SHIFT_CH16_LOW_TH) #define BITS_CH16_LOW_TH (BIT_MASK_CH16_LOW_TH << BIT_SHIFT_CH16_LOW_TH) #define BIT_CLEAR_CH16_LOW_TH(x) ((x) & (~BITS_CH16_LOW_TH)) #define BIT_GET_CH16_LOW_TH(x) \ (((x) >> BIT_SHIFT_CH16_LOW_TH) & BIT_MASK_CH16_LOW_TH) #define BIT_SET_CH16_LOW_TH(x, v) \ (BIT_CLEAR_CH16_LOW_TH(x) | BIT_CH16_LOW_TH(v)) /* 2 REG_ACH4_TXBD_IDX (Offset 0x3340) */ #define BIT_SHIFT_ACH4_HW_IDX 16 #define BIT_MASK_ACH4_HW_IDX 0xfff #define BIT_ACH4_HW_IDX(x) \ (((x) & BIT_MASK_ACH4_HW_IDX) << BIT_SHIFT_ACH4_HW_IDX) #define BITS_ACH4_HW_IDX (BIT_MASK_ACH4_HW_IDX << BIT_SHIFT_ACH4_HW_IDX) #define BIT_CLEAR_ACH4_HW_IDX(x) ((x) & (~BITS_ACH4_HW_IDX)) #define BIT_GET_ACH4_HW_IDX(x) \ (((x) >> BIT_SHIFT_ACH4_HW_IDX) & BIT_MASK_ACH4_HW_IDX) #define BIT_SET_ACH4_HW_IDX(x, v) \ (BIT_CLEAR_ACH4_HW_IDX(x) | BIT_ACH4_HW_IDX(v)) #define BIT_SHIFT_ACH4_HOST_IDX 0 #define BIT_MASK_ACH4_HOST_IDX 0xfff #define BIT_ACH4_HOST_IDX(x) \ (((x) & BIT_MASK_ACH4_HOST_IDX) << BIT_SHIFT_ACH4_HOST_IDX) #define BITS_ACH4_HOST_IDX (BIT_MASK_ACH4_HOST_IDX << BIT_SHIFT_ACH4_HOST_IDX) #define BIT_CLEAR_ACH4_HOST_IDX(x) ((x) & (~BITS_ACH4_HOST_IDX)) #define BIT_GET_ACH4_HOST_IDX(x) \ (((x) >> BIT_SHIFT_ACH4_HOST_IDX) & BIT_MASK_ACH4_HOST_IDX) #define BIT_SET_ACH4_HOST_IDX(x, v) \ (BIT_CLEAR_ACH4_HOST_IDX(x) | BIT_ACH4_HOST_IDX(v)) /* 2 REG_ACH5_TXBD_IDX (Offset 0x3344) */ #define BIT_SHIFT_ACH5_HW_IDX 16 #define BIT_MASK_ACH5_HW_IDX 0xfff #define BIT_ACH5_HW_IDX(x) \ (((x) & BIT_MASK_ACH5_HW_IDX) << BIT_SHIFT_ACH5_HW_IDX) #define BITS_ACH5_HW_IDX (BIT_MASK_ACH5_HW_IDX << BIT_SHIFT_ACH5_HW_IDX) #define BIT_CLEAR_ACH5_HW_IDX(x) ((x) & (~BITS_ACH5_HW_IDX)) #define BIT_GET_ACH5_HW_IDX(x) \ (((x) >> BIT_SHIFT_ACH5_HW_IDX) & BIT_MASK_ACH5_HW_IDX) #define BIT_SET_ACH5_HW_IDX(x, v) \ (BIT_CLEAR_ACH5_HW_IDX(x) | BIT_ACH5_HW_IDX(v)) #define BIT_SHIFT_ACH5_HOST_IDX 0 #define BIT_MASK_ACH5_HOST_IDX 0xfff #define BIT_ACH5_HOST_IDX(x) \ (((x) & BIT_MASK_ACH5_HOST_IDX) << BIT_SHIFT_ACH5_HOST_IDX) #define BITS_ACH5_HOST_IDX (BIT_MASK_ACH5_HOST_IDX << BIT_SHIFT_ACH5_HOST_IDX) #define BIT_CLEAR_ACH5_HOST_IDX(x) ((x) & (~BITS_ACH5_HOST_IDX)) #define BIT_GET_ACH5_HOST_IDX(x) \ (((x) >> BIT_SHIFT_ACH5_HOST_IDX) & BIT_MASK_ACH5_HOST_IDX) #define BIT_SET_ACH5_HOST_IDX(x, v) \ (BIT_CLEAR_ACH5_HOST_IDX(x) | BIT_ACH5_HOST_IDX(v)) /* 2 REG_ACH6_TXBD_IDX (Offset 0x3348) */ #define BIT_SHIFT_ACH6_HW_IDX 16 #define BIT_MASK_ACH6_HW_IDX 0xfff #define BIT_ACH6_HW_IDX(x) \ (((x) & BIT_MASK_ACH6_HW_IDX) << BIT_SHIFT_ACH6_HW_IDX) #define BITS_ACH6_HW_IDX (BIT_MASK_ACH6_HW_IDX << BIT_SHIFT_ACH6_HW_IDX) #define BIT_CLEAR_ACH6_HW_IDX(x) ((x) & (~BITS_ACH6_HW_IDX)) #define BIT_GET_ACH6_HW_IDX(x) \ (((x) >> BIT_SHIFT_ACH6_HW_IDX) & BIT_MASK_ACH6_HW_IDX) #define BIT_SET_ACH6_HW_IDX(x, v) \ (BIT_CLEAR_ACH6_HW_IDX(x) | BIT_ACH6_HW_IDX(v)) #define BIT_SHIFT_ACH6_HOST_IDX 0 #define BIT_MASK_ACH6_HOST_IDX 0xfff #define BIT_ACH6_HOST_IDX(x) \ (((x) & BIT_MASK_ACH6_HOST_IDX) << BIT_SHIFT_ACH6_HOST_IDX) #define BITS_ACH6_HOST_IDX (BIT_MASK_ACH6_HOST_IDX << BIT_SHIFT_ACH6_HOST_IDX) #define BIT_CLEAR_ACH6_HOST_IDX(x) ((x) & (~BITS_ACH6_HOST_IDX)) #define BIT_GET_ACH6_HOST_IDX(x) \ (((x) >> BIT_SHIFT_ACH6_HOST_IDX) & BIT_MASK_ACH6_HOST_IDX) #define BIT_SET_ACH6_HOST_IDX(x, v) \ (BIT_CLEAR_ACH6_HOST_IDX(x) | BIT_ACH6_HOST_IDX(v)) /* 2 REG_ACH7_TXBD_IDX (Offset 0x334C) */ #define BIT_SHIFT_ACH7_HW_IDX 16 #define BIT_MASK_ACH7_HW_IDX 0xfff #define BIT_ACH7_HW_IDX(x) \ (((x) & BIT_MASK_ACH7_HW_IDX) << BIT_SHIFT_ACH7_HW_IDX) #define BITS_ACH7_HW_IDX (BIT_MASK_ACH7_HW_IDX << BIT_SHIFT_ACH7_HW_IDX) #define BIT_CLEAR_ACH7_HW_IDX(x) ((x) & (~BITS_ACH7_HW_IDX)) #define BIT_GET_ACH7_HW_IDX(x) \ (((x) >> BIT_SHIFT_ACH7_HW_IDX) & BIT_MASK_ACH7_HW_IDX) #define BIT_SET_ACH7_HW_IDX(x, v) \ (BIT_CLEAR_ACH7_HW_IDX(x) | BIT_ACH7_HW_IDX(v)) #define BIT_SHIFT_ACH7_HOST_IDX 0 #define BIT_MASK_ACH7_HOST_IDX 0xfff #define BIT_ACH7_HOST_IDX(x) \ (((x) & BIT_MASK_ACH7_HOST_IDX) << BIT_SHIFT_ACH7_HOST_IDX) #define BITS_ACH7_HOST_IDX (BIT_MASK_ACH7_HOST_IDX << BIT_SHIFT_ACH7_HOST_IDX) #define BIT_CLEAR_ACH7_HOST_IDX(x) ((x) & (~BITS_ACH7_HOST_IDX)) #define BIT_GET_ACH7_HOST_IDX(x) \ (((x) >> BIT_SHIFT_ACH7_HOST_IDX) & BIT_MASK_ACH7_HOST_IDX) #define BIT_SET_ACH7_HOST_IDX(x, v) \ (BIT_CLEAR_ACH7_HOST_IDX(x) | BIT_ACH7_HOST_IDX(v)) /* 2 REG_ACH8_TXBD_IDX (Offset 0x3350) */ #define BIT_SHIFT_ACH8_HW_IDX 16 #define BIT_MASK_ACH8_HW_IDX 0xfff #define BIT_ACH8_HW_IDX(x) \ (((x) & BIT_MASK_ACH8_HW_IDX) << BIT_SHIFT_ACH8_HW_IDX) #define BITS_ACH8_HW_IDX (BIT_MASK_ACH8_HW_IDX << BIT_SHIFT_ACH8_HW_IDX) #define BIT_CLEAR_ACH8_HW_IDX(x) ((x) & (~BITS_ACH8_HW_IDX)) #define BIT_GET_ACH8_HW_IDX(x) \ (((x) >> BIT_SHIFT_ACH8_HW_IDX) & BIT_MASK_ACH8_HW_IDX) #define BIT_SET_ACH8_HW_IDX(x, v) \ (BIT_CLEAR_ACH8_HW_IDX(x) | BIT_ACH8_HW_IDX(v)) #define BIT_SHIFT_ACH8_HOST_IDX 0 #define BIT_MASK_ACH8_HOST_IDX 0xfff #define BIT_ACH8_HOST_IDX(x) \ (((x) & BIT_MASK_ACH8_HOST_IDX) << BIT_SHIFT_ACH8_HOST_IDX) #define BITS_ACH8_HOST_IDX (BIT_MASK_ACH8_HOST_IDX << BIT_SHIFT_ACH8_HOST_IDX) #define BIT_CLEAR_ACH8_HOST_IDX(x) ((x) & (~BITS_ACH8_HOST_IDX)) #define BIT_GET_ACH8_HOST_IDX(x) \ (((x) >> BIT_SHIFT_ACH8_HOST_IDX) & BIT_MASK_ACH8_HOST_IDX) #define BIT_SET_ACH8_HOST_IDX(x, v) \ (BIT_CLEAR_ACH8_HOST_IDX(x) | BIT_ACH8_HOST_IDX(v)) /* 2 REG_ACH9_TXBD_IDX (Offset 0x3354) */ #define BIT_SHIFT_ACH9_HW_IDX 16 #define BIT_MASK_ACH9_HW_IDX 0xfff #define BIT_ACH9_HW_IDX(x) \ (((x) & BIT_MASK_ACH9_HW_IDX) << BIT_SHIFT_ACH9_HW_IDX) #define BITS_ACH9_HW_IDX (BIT_MASK_ACH9_HW_IDX << BIT_SHIFT_ACH9_HW_IDX) #define BIT_CLEAR_ACH9_HW_IDX(x) ((x) & (~BITS_ACH9_HW_IDX)) #define BIT_GET_ACH9_HW_IDX(x) \ (((x) >> BIT_SHIFT_ACH9_HW_IDX) & BIT_MASK_ACH9_HW_IDX) #define BIT_SET_ACH9_HW_IDX(x, v) \ (BIT_CLEAR_ACH9_HW_IDX(x) | BIT_ACH9_HW_IDX(v)) #define BIT_SHIFT_ACH9_HOST_IDX 0 #define BIT_MASK_ACH9_HOST_IDX 0xfff #define BIT_ACH9_HOST_IDX(x) \ (((x) & BIT_MASK_ACH9_HOST_IDX) << BIT_SHIFT_ACH9_HOST_IDX) #define BITS_ACH9_HOST_IDX (BIT_MASK_ACH9_HOST_IDX << BIT_SHIFT_ACH9_HOST_IDX) #define BIT_CLEAR_ACH9_HOST_IDX(x) ((x) & (~BITS_ACH9_HOST_IDX)) #define BIT_GET_ACH9_HOST_IDX(x) \ (((x) >> BIT_SHIFT_ACH9_HOST_IDX) & BIT_MASK_ACH9_HOST_IDX) #define BIT_SET_ACH9_HOST_IDX(x, v) \ (BIT_CLEAR_ACH9_HOST_IDX(x) | BIT_ACH9_HOST_IDX(v)) /* 2 REG_ACH10_TXBD_IDX (Offset 0x3358) */ #define BIT_SHIFT_ACH10_HW_IDX 16 #define BIT_MASK_ACH10_HW_IDX 0xfff #define BIT_ACH10_HW_IDX(x) \ (((x) & BIT_MASK_ACH10_HW_IDX) << BIT_SHIFT_ACH10_HW_IDX) #define BITS_ACH10_HW_IDX (BIT_MASK_ACH10_HW_IDX << BIT_SHIFT_ACH10_HW_IDX) #define BIT_CLEAR_ACH10_HW_IDX(x) ((x) & (~BITS_ACH10_HW_IDX)) #define BIT_GET_ACH10_HW_IDX(x) \ (((x) >> BIT_SHIFT_ACH10_HW_IDX) & BIT_MASK_ACH10_HW_IDX) #define BIT_SET_ACH10_HW_IDX(x, v) \ (BIT_CLEAR_ACH10_HW_IDX(x) | BIT_ACH10_HW_IDX(v)) #define BIT_SHIFT_ACH10_HOST_IDX 0 #define BIT_MASK_ACH10_HOST_IDX 0xfff #define BIT_ACH10_HOST_IDX(x) \ (((x) & BIT_MASK_ACH10_HOST_IDX) << BIT_SHIFT_ACH10_HOST_IDX) #define BITS_ACH10_HOST_IDX \ (BIT_MASK_ACH10_HOST_IDX << BIT_SHIFT_ACH10_HOST_IDX) #define BIT_CLEAR_ACH10_HOST_IDX(x) ((x) & (~BITS_ACH10_HOST_IDX)) #define BIT_GET_ACH10_HOST_IDX(x) \ (((x) >> BIT_SHIFT_ACH10_HOST_IDX) & BIT_MASK_ACH10_HOST_IDX) #define BIT_SET_ACH10_HOST_IDX(x, v) \ (BIT_CLEAR_ACH10_HOST_IDX(x) | BIT_ACH10_HOST_IDX(v)) /* 2 REG_ACH11_TXBD_IDX (Offset 0x335C) */ #define BIT_SHIFT_ACH11_HW_IDX 16 #define BIT_MASK_ACH11_HW_IDX 0xfff #define BIT_ACH11_HW_IDX(x) \ (((x) & BIT_MASK_ACH11_HW_IDX) << BIT_SHIFT_ACH11_HW_IDX) #define BITS_ACH11_HW_IDX (BIT_MASK_ACH11_HW_IDX << BIT_SHIFT_ACH11_HW_IDX) #define BIT_CLEAR_ACH11_HW_IDX(x) ((x) & (~BITS_ACH11_HW_IDX)) #define BIT_GET_ACH11_HW_IDX(x) \ (((x) >> BIT_SHIFT_ACH11_HW_IDX) & BIT_MASK_ACH11_HW_IDX) #define BIT_SET_ACH11_HW_IDX(x, v) \ (BIT_CLEAR_ACH11_HW_IDX(x) | BIT_ACH11_HW_IDX(v)) #define BIT_SHIFT_ACH11_HOST_IDX 0 #define BIT_MASK_ACH11_HOST_IDX 0xfff #define BIT_ACH11_HOST_IDX(x) \ (((x) & BIT_MASK_ACH11_HOST_IDX) << BIT_SHIFT_ACH11_HOST_IDX) #define BITS_ACH11_HOST_IDX \ (BIT_MASK_ACH11_HOST_IDX << BIT_SHIFT_ACH11_HOST_IDX) #define BIT_CLEAR_ACH11_HOST_IDX(x) ((x) & (~BITS_ACH11_HOST_IDX)) #define BIT_GET_ACH11_HOST_IDX(x) \ (((x) >> BIT_SHIFT_ACH11_HOST_IDX) & BIT_MASK_ACH11_HOST_IDX) #define BIT_SET_ACH11_HOST_IDX(x, v) \ (BIT_CLEAR_ACH11_HOST_IDX(x) | BIT_ACH11_HOST_IDX(v)) /* 2 REG_ACH12_TXBD_IDX (Offset 0x3360) */ #define BIT_SHIFT_ACH12_HW_IDX 16 #define BIT_MASK_ACH12_HW_IDX 0xfff #define BIT_ACH12_HW_IDX(x) \ (((x) & BIT_MASK_ACH12_HW_IDX) << BIT_SHIFT_ACH12_HW_IDX) #define BITS_ACH12_HW_IDX (BIT_MASK_ACH12_HW_IDX << BIT_SHIFT_ACH12_HW_IDX) #define BIT_CLEAR_ACH12_HW_IDX(x) ((x) & (~BITS_ACH12_HW_IDX)) #define BIT_GET_ACH12_HW_IDX(x) \ (((x) >> BIT_SHIFT_ACH12_HW_IDX) & BIT_MASK_ACH12_HW_IDX) #define BIT_SET_ACH12_HW_IDX(x, v) \ (BIT_CLEAR_ACH12_HW_IDX(x) | BIT_ACH12_HW_IDX(v)) #define BIT_SHIFT_ACH12_HOST_IDX 0 #define BIT_MASK_ACH12_HOST_IDX 0xfff #define BIT_ACH12_HOST_IDX(x) \ (((x) & BIT_MASK_ACH12_HOST_IDX) << BIT_SHIFT_ACH12_HOST_IDX) #define BITS_ACH12_HOST_IDX \ (BIT_MASK_ACH12_HOST_IDX << BIT_SHIFT_ACH12_HOST_IDX) #define BIT_CLEAR_ACH12_HOST_IDX(x) ((x) & (~BITS_ACH12_HOST_IDX)) #define BIT_GET_ACH12_HOST_IDX(x) \ (((x) >> BIT_SHIFT_ACH12_HOST_IDX) & BIT_MASK_ACH12_HOST_IDX) #define BIT_SET_ACH12_HOST_IDX(x, v) \ (BIT_CLEAR_ACH12_HOST_IDX(x) | BIT_ACH12_HOST_IDX(v)) /* 2 REG_ACH13_TXBD_IDX (Offset 0x3364) */ #define BIT_SHIFT_ACH13_HW_IDX 16 #define BIT_MASK_ACH13_HW_IDX 0xfff #define BIT_ACH13_HW_IDX(x) \ (((x) & BIT_MASK_ACH13_HW_IDX) << BIT_SHIFT_ACH13_HW_IDX) #define BITS_ACH13_HW_IDX (BIT_MASK_ACH13_HW_IDX << BIT_SHIFT_ACH13_HW_IDX) #define BIT_CLEAR_ACH13_HW_IDX(x) ((x) & (~BITS_ACH13_HW_IDX)) #define BIT_GET_ACH13_HW_IDX(x) \ (((x) >> BIT_SHIFT_ACH13_HW_IDX) & BIT_MASK_ACH13_HW_IDX) #define BIT_SET_ACH13_HW_IDX(x, v) \ (BIT_CLEAR_ACH13_HW_IDX(x) | BIT_ACH13_HW_IDX(v)) #define BIT_SHIFT_ACH13_HOST_IDX 0 #define BIT_MASK_ACH13_HOST_IDX 0xfff #define BIT_ACH13_HOST_IDX(x) \ (((x) & BIT_MASK_ACH13_HOST_IDX) << BIT_SHIFT_ACH13_HOST_IDX) #define BITS_ACH13_HOST_IDX \ (BIT_MASK_ACH13_HOST_IDX << BIT_SHIFT_ACH13_HOST_IDX) #define BIT_CLEAR_ACH13_HOST_IDX(x) ((x) & (~BITS_ACH13_HOST_IDX)) #define BIT_GET_ACH13_HOST_IDX(x) \ (((x) >> BIT_SHIFT_ACH13_HOST_IDX) & BIT_MASK_ACH13_HOST_IDX) #define BIT_SET_ACH13_HOST_IDX(x, v) \ (BIT_CLEAR_ACH13_HOST_IDX(x) | BIT_ACH13_HOST_IDX(v)) /* 2 REG_AC_CHANNEL0_WEIGHT (Offset 0x3368) */ #define BIT_SHIFT_AC_CHANNEL0_WEIGHT 0 #define BIT_MASK_AC_CHANNEL0_WEIGHT 0xff #define BIT_AC_CHANNEL0_WEIGHT(x) \ (((x) & BIT_MASK_AC_CHANNEL0_WEIGHT) << BIT_SHIFT_AC_CHANNEL0_WEIGHT) #define BITS_AC_CHANNEL0_WEIGHT \ (BIT_MASK_AC_CHANNEL0_WEIGHT << BIT_SHIFT_AC_CHANNEL0_WEIGHT) #define BIT_CLEAR_AC_CHANNEL0_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL0_WEIGHT)) #define BIT_GET_AC_CHANNEL0_WEIGHT(x) \ (((x) >> BIT_SHIFT_AC_CHANNEL0_WEIGHT) & BIT_MASK_AC_CHANNEL0_WEIGHT) #define BIT_SET_AC_CHANNEL0_WEIGHT(x, v) \ (BIT_CLEAR_AC_CHANNEL0_WEIGHT(x) | BIT_AC_CHANNEL0_WEIGHT(v)) /* 2 REG_AC_CHANNEL1_WEIGHT (Offset 0x3369) */ #define BIT_SHIFT_AC_CHANNEL1_WEIGHT 0 #define BIT_MASK_AC_CHANNEL1_WEIGHT 0xff #define BIT_AC_CHANNEL1_WEIGHT(x) \ (((x) & BIT_MASK_AC_CHANNEL1_WEIGHT) << BIT_SHIFT_AC_CHANNEL1_WEIGHT) #define BITS_AC_CHANNEL1_WEIGHT \ (BIT_MASK_AC_CHANNEL1_WEIGHT << BIT_SHIFT_AC_CHANNEL1_WEIGHT) #define BIT_CLEAR_AC_CHANNEL1_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL1_WEIGHT)) #define BIT_GET_AC_CHANNEL1_WEIGHT(x) \ (((x) >> BIT_SHIFT_AC_CHANNEL1_WEIGHT) & BIT_MASK_AC_CHANNEL1_WEIGHT) #define BIT_SET_AC_CHANNEL1_WEIGHT(x, v) \ (BIT_CLEAR_AC_CHANNEL1_WEIGHT(x) | BIT_AC_CHANNEL1_WEIGHT(v)) /* 2 REG_AC_CHANNEL2_WEIGHT (Offset 0x336A) */ #define BIT_SHIFT_AC_CHANNEL2_WEIGHT 0 #define BIT_MASK_AC_CHANNEL2_WEIGHT 0xff #define BIT_AC_CHANNEL2_WEIGHT(x) \ (((x) & BIT_MASK_AC_CHANNEL2_WEIGHT) << BIT_SHIFT_AC_CHANNEL2_WEIGHT) #define BITS_AC_CHANNEL2_WEIGHT \ (BIT_MASK_AC_CHANNEL2_WEIGHT << BIT_SHIFT_AC_CHANNEL2_WEIGHT) #define BIT_CLEAR_AC_CHANNEL2_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL2_WEIGHT)) #define BIT_GET_AC_CHANNEL2_WEIGHT(x) \ (((x) >> BIT_SHIFT_AC_CHANNEL2_WEIGHT) & BIT_MASK_AC_CHANNEL2_WEIGHT) #define BIT_SET_AC_CHANNEL2_WEIGHT(x, v) \ (BIT_CLEAR_AC_CHANNEL2_WEIGHT(x) | BIT_AC_CHANNEL2_WEIGHT(v)) /* 2 REG_AC_CHANNEL3_WEIGHT (Offset 0x336B) */ #define BIT_SHIFT_AC_CHANNEL3_WEIGHT 0 #define BIT_MASK_AC_CHANNEL3_WEIGHT 0xff #define BIT_AC_CHANNEL3_WEIGHT(x) \ (((x) & BIT_MASK_AC_CHANNEL3_WEIGHT) << BIT_SHIFT_AC_CHANNEL3_WEIGHT) #define BITS_AC_CHANNEL3_WEIGHT \ (BIT_MASK_AC_CHANNEL3_WEIGHT << BIT_SHIFT_AC_CHANNEL3_WEIGHT) #define BIT_CLEAR_AC_CHANNEL3_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL3_WEIGHT)) #define BIT_GET_AC_CHANNEL3_WEIGHT(x) \ (((x) >> BIT_SHIFT_AC_CHANNEL3_WEIGHT) & BIT_MASK_AC_CHANNEL3_WEIGHT) #define BIT_SET_AC_CHANNEL3_WEIGHT(x, v) \ (BIT_CLEAR_AC_CHANNEL3_WEIGHT(x) | BIT_AC_CHANNEL3_WEIGHT(v)) /* 2 REG_AC_CHANNEL4_WEIGHT (Offset 0x336C) */ #define BIT_SHIFT_AC_CHANNEL4_WEIGHT 0 #define BIT_MASK_AC_CHANNEL4_WEIGHT 0xff #define BIT_AC_CHANNEL4_WEIGHT(x) \ (((x) & BIT_MASK_AC_CHANNEL4_WEIGHT) << BIT_SHIFT_AC_CHANNEL4_WEIGHT) #define BITS_AC_CHANNEL4_WEIGHT \ (BIT_MASK_AC_CHANNEL4_WEIGHT << BIT_SHIFT_AC_CHANNEL4_WEIGHT) #define BIT_CLEAR_AC_CHANNEL4_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL4_WEIGHT)) #define BIT_GET_AC_CHANNEL4_WEIGHT(x) \ (((x) >> BIT_SHIFT_AC_CHANNEL4_WEIGHT) & BIT_MASK_AC_CHANNEL4_WEIGHT) #define BIT_SET_AC_CHANNEL4_WEIGHT(x, v) \ (BIT_CLEAR_AC_CHANNEL4_WEIGHT(x) | BIT_AC_CHANNEL4_WEIGHT(v)) /* 2 REG_AC_CHANNEL5_WEIGHT (Offset 0x336D) */ #define BIT_SHIFT_AC_CHANNEL5_WEIGHT 0 #define BIT_MASK_AC_CHANNEL5_WEIGHT 0xff #define BIT_AC_CHANNEL5_WEIGHT(x) \ (((x) & BIT_MASK_AC_CHANNEL5_WEIGHT) << BIT_SHIFT_AC_CHANNEL5_WEIGHT) #define BITS_AC_CHANNEL5_WEIGHT \ (BIT_MASK_AC_CHANNEL5_WEIGHT << BIT_SHIFT_AC_CHANNEL5_WEIGHT) #define BIT_CLEAR_AC_CHANNEL5_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL5_WEIGHT)) #define BIT_GET_AC_CHANNEL5_WEIGHT(x) \ (((x) >> BIT_SHIFT_AC_CHANNEL5_WEIGHT) & BIT_MASK_AC_CHANNEL5_WEIGHT) #define BIT_SET_AC_CHANNEL5_WEIGHT(x, v) \ (BIT_CLEAR_AC_CHANNEL5_WEIGHT(x) | BIT_AC_CHANNEL5_WEIGHT(v)) /* 2 REG_AC_CHANNEL6_WEIGHT (Offset 0x336E) */ #define BIT_SHIFT_AC_CHANNEL6_WEIGHT 0 #define BIT_MASK_AC_CHANNEL6_WEIGHT 0xff #define BIT_AC_CHANNEL6_WEIGHT(x) \ (((x) & BIT_MASK_AC_CHANNEL6_WEIGHT) << BIT_SHIFT_AC_CHANNEL6_WEIGHT) #define BITS_AC_CHANNEL6_WEIGHT \ (BIT_MASK_AC_CHANNEL6_WEIGHT << BIT_SHIFT_AC_CHANNEL6_WEIGHT) #define BIT_CLEAR_AC_CHANNEL6_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL6_WEIGHT)) #define BIT_GET_AC_CHANNEL6_WEIGHT(x) \ (((x) >> BIT_SHIFT_AC_CHANNEL6_WEIGHT) & BIT_MASK_AC_CHANNEL6_WEIGHT) #define BIT_SET_AC_CHANNEL6_WEIGHT(x, v) \ (BIT_CLEAR_AC_CHANNEL6_WEIGHT(x) | BIT_AC_CHANNEL6_WEIGHT(v)) /* 2 REG_AC_CHANNEL7_WEIGHT (Offset 0x336F) */ #define BIT_SHIFT_AC_CHANNEL7_WEIGHT 0 #define BIT_MASK_AC_CHANNEL7_WEIGHT 0xff #define BIT_AC_CHANNEL7_WEIGHT(x) \ (((x) & BIT_MASK_AC_CHANNEL7_WEIGHT) << BIT_SHIFT_AC_CHANNEL7_WEIGHT) #define BITS_AC_CHANNEL7_WEIGHT \ (BIT_MASK_AC_CHANNEL7_WEIGHT << BIT_SHIFT_AC_CHANNEL7_WEIGHT) #define BIT_CLEAR_AC_CHANNEL7_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL7_WEIGHT)) #define BIT_GET_AC_CHANNEL7_WEIGHT(x) \ (((x) >> BIT_SHIFT_AC_CHANNEL7_WEIGHT) & BIT_MASK_AC_CHANNEL7_WEIGHT) #define BIT_SET_AC_CHANNEL7_WEIGHT(x, v) \ (BIT_CLEAR_AC_CHANNEL7_WEIGHT(x) | BIT_AC_CHANNEL7_WEIGHT(v)) /* 2 REG_AC_CHANNEL8_WEIGHT (Offset 0x3370) */ #define BIT_SHIFT_AC_CHANNEL8_WEIGHT 0 #define BIT_MASK_AC_CHANNEL8_WEIGHT 0xff #define BIT_AC_CHANNEL8_WEIGHT(x) \ (((x) & BIT_MASK_AC_CHANNEL8_WEIGHT) << BIT_SHIFT_AC_CHANNEL8_WEIGHT) #define BITS_AC_CHANNEL8_WEIGHT \ (BIT_MASK_AC_CHANNEL8_WEIGHT << BIT_SHIFT_AC_CHANNEL8_WEIGHT) #define BIT_CLEAR_AC_CHANNEL8_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL8_WEIGHT)) #define BIT_GET_AC_CHANNEL8_WEIGHT(x) \ (((x) >> BIT_SHIFT_AC_CHANNEL8_WEIGHT) & BIT_MASK_AC_CHANNEL8_WEIGHT) #define BIT_SET_AC_CHANNEL8_WEIGHT(x, v) \ (BIT_CLEAR_AC_CHANNEL8_WEIGHT(x) | BIT_AC_CHANNEL8_WEIGHT(v)) /* 2 REG_AC_CHANNEL9_WEIGHT (Offset 0x3371) */ #define BIT_SHIFT_AC_CHANNEL9_WEIGHT 0 #define BIT_MASK_AC_CHANNEL9_WEIGHT 0xff #define BIT_AC_CHANNEL9_WEIGHT(x) \ (((x) & BIT_MASK_AC_CHANNEL9_WEIGHT) << BIT_SHIFT_AC_CHANNEL9_WEIGHT) #define BITS_AC_CHANNEL9_WEIGHT \ (BIT_MASK_AC_CHANNEL9_WEIGHT << BIT_SHIFT_AC_CHANNEL9_WEIGHT) #define BIT_CLEAR_AC_CHANNEL9_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL9_WEIGHT)) #define BIT_GET_AC_CHANNEL9_WEIGHT(x) \ (((x) >> BIT_SHIFT_AC_CHANNEL9_WEIGHT) & BIT_MASK_AC_CHANNEL9_WEIGHT) #define BIT_SET_AC_CHANNEL9_WEIGHT(x, v) \ (BIT_CLEAR_AC_CHANNEL9_WEIGHT(x) | BIT_AC_CHANNEL9_WEIGHT(v)) /* 2 REG_AC_CHANNEL10_WEIGHT (Offset 0x3372) */ #define BIT_SHIFT_AC_CHANNEL10_WEIGHT 0 #define BIT_MASK_AC_CHANNEL10_WEIGHT 0xff #define BIT_AC_CHANNEL10_WEIGHT(x) \ (((x) & BIT_MASK_AC_CHANNEL10_WEIGHT) << BIT_SHIFT_AC_CHANNEL10_WEIGHT) #define BITS_AC_CHANNEL10_WEIGHT \ (BIT_MASK_AC_CHANNEL10_WEIGHT << BIT_SHIFT_AC_CHANNEL10_WEIGHT) #define BIT_CLEAR_AC_CHANNEL10_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL10_WEIGHT)) #define BIT_GET_AC_CHANNEL10_WEIGHT(x) \ (((x) >> BIT_SHIFT_AC_CHANNEL10_WEIGHT) & BIT_MASK_AC_CHANNEL10_WEIGHT) #define BIT_SET_AC_CHANNEL10_WEIGHT(x, v) \ (BIT_CLEAR_AC_CHANNEL10_WEIGHT(x) | BIT_AC_CHANNEL10_WEIGHT(v)) /* 2 REG_AC_CHANNEL11_WEIGHT (Offset 0x3373) */ #define BIT_SHIFT_AC_CHANNEL11_WEIGHT 0 #define BIT_MASK_AC_CHANNEL11_WEIGHT 0xff #define BIT_AC_CHANNEL11_WEIGHT(x) \ (((x) & BIT_MASK_AC_CHANNEL11_WEIGHT) << BIT_SHIFT_AC_CHANNEL11_WEIGHT) #define BITS_AC_CHANNEL11_WEIGHT \ (BIT_MASK_AC_CHANNEL11_WEIGHT << BIT_SHIFT_AC_CHANNEL11_WEIGHT) #define BIT_CLEAR_AC_CHANNEL11_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL11_WEIGHT)) #define BIT_GET_AC_CHANNEL11_WEIGHT(x) \ (((x) >> BIT_SHIFT_AC_CHANNEL11_WEIGHT) & BIT_MASK_AC_CHANNEL11_WEIGHT) #define BIT_SET_AC_CHANNEL11_WEIGHT(x, v) \ (BIT_CLEAR_AC_CHANNEL11_WEIGHT(x) | BIT_AC_CHANNEL11_WEIGHT(v)) /* 2 REG_AC_CHANNEL12_WEIGHT (Offset 0x3374) */ #define BIT_SHIFT_AC_CHANNEL12_WEIGHT 0 #define BIT_MASK_AC_CHANNEL12_WEIGHT 0xff #define BIT_AC_CHANNEL12_WEIGHT(x) \ (((x) & BIT_MASK_AC_CHANNEL12_WEIGHT) << BIT_SHIFT_AC_CHANNEL12_WEIGHT) #define BITS_AC_CHANNEL12_WEIGHT \ (BIT_MASK_AC_CHANNEL12_WEIGHT << BIT_SHIFT_AC_CHANNEL12_WEIGHT) #define BIT_CLEAR_AC_CHANNEL12_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL12_WEIGHT)) #define BIT_GET_AC_CHANNEL12_WEIGHT(x) \ (((x) >> BIT_SHIFT_AC_CHANNEL12_WEIGHT) & BIT_MASK_AC_CHANNEL12_WEIGHT) #define BIT_SET_AC_CHANNEL12_WEIGHT(x, v) \ (BIT_CLEAR_AC_CHANNEL12_WEIGHT(x) | BIT_AC_CHANNEL12_WEIGHT(v)) /* 2 REG_AC_CHANNEL13_WEIGHT (Offset 0x3375) */ #define BIT_SHIFT_AC_CHANNEL13_WEIGHT 0 #define BIT_MASK_AC_CHANNEL13_WEIGHT 0xff #define BIT_AC_CHANNEL13_WEIGHT(x) \ (((x) & BIT_MASK_AC_CHANNEL13_WEIGHT) << BIT_SHIFT_AC_CHANNEL13_WEIGHT) #define BITS_AC_CHANNEL13_WEIGHT \ (BIT_MASK_AC_CHANNEL13_WEIGHT << BIT_SHIFT_AC_CHANNEL13_WEIGHT) #define BIT_CLEAR_AC_CHANNEL13_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL13_WEIGHT)) #define BIT_GET_AC_CHANNEL13_WEIGHT(x) \ (((x) >> BIT_SHIFT_AC_CHANNEL13_WEIGHT) & BIT_MASK_AC_CHANNEL13_WEIGHT) #define BIT_SET_AC_CHANNEL13_WEIGHT(x, v) \ (BIT_CLEAR_AC_CHANNEL13_WEIGHT(x) | BIT_AC_CHANNEL13_WEIGHT(v)) #endif #endif /* __RTL_WLAN_BITDEF_H__ */