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Update to 5.8.7.1

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Rin Cat
2020-08-02 05:12:24 -04:00
parent 314b662331
commit e3b09b28f7
449 changed files with 106089 additions and 83748 deletions
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129
include/Hal8188EPhyCfg.h
View File

@@ -55,129 +55,118 @@
/*
* BB and RF register read/write
* */
u32 PHY_QueryBBReg8188E(IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask);
void PHY_SetBBReg8188E(IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data);
u32 PHY_QueryRFReg8188E(IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask);
void PHY_SetRFReg8188E(IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data);
u32 PHY_QueryBBReg8188E(PADAPTER Adapter,
u32 RegAddr,
u32 BitMask);
void PHY_SetBBReg8188E(PADAPTER Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data);
u32 PHY_QueryRFReg8188E(PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask);
void PHY_SetRFReg8188E(PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask,
u32 Data);
/*
* Initialization related function
*/
/* MAC/BB/RF HAL config */
int PHY_MACConfig8188E(IN PADAPTER Adapter);
int PHY_BBConfig8188E(IN PADAPTER Adapter);
int PHY_RFConfig8188E(IN PADAPTER Adapter);
int PHY_MACConfig8188E(PADAPTER Adapter);
int PHY_BBConfig8188E(PADAPTER Adapter);
int PHY_RFConfig8188E(PADAPTER Adapter);
/* RF config */
int rtl8188e_PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN u8 *pFileName, enum rf_path eRFPath);
int rtl8188e_PHY_ConfigRFWithParaFile( PADAPTER Adapter, u8 *pFileName, enum rf_path eRFPath);
/*
* RF Power setting
*/
/* extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter,
* IN RT_RF_POWER_STATE eRFPowerState); */
/* extern BOOLEAN PHY_SetRFPowerState(PADAPTER Adapter,
* RT_RF_POWER_STATE eRFPowerState); */
/*
* BB TX Power R/W
* */
void PHY_GetTxPowerLevel8188E(IN PADAPTER Adapter,
OUT s32 *powerlevel);
void PHY_SetTxPowerLevel8188E(IN PADAPTER Adapter,
IN u8 channel);
BOOLEAN PHY_UpdateTxPowerDbm8188E(IN PADAPTER Adapter,
IN int powerInDbm);
void PHY_SetTxPowerLevel8188E(PADAPTER Adapter,
u8 channel);
VOID
void
PHY_SetTxPowerIndex_8188E(
IN PADAPTER Adapter,
IN u32 PowerIndex,
IN enum rf_path RFPath,
IN u8 Rate
PADAPTER Adapter,
u32 PowerIndex,
enum rf_path RFPath,
u8 Rate
);
u8
PHY_GetTxPowerIndex_8188E(
IN PADAPTER pAdapter,
IN enum rf_path RFPath,
IN u8 Rate,
IN u8 BandWidth,
IN u8 Channel,
struct txpwr_idx_comp *tic
);
s8 phy_get_txpwr_target_extra_bias_8188e(_adapter *adapter, enum rf_path rfpath
, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch);
/*
* Switch bandwidth for 8192S
*/
/* extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer ); */
void PHY_SetBWMode8188E(IN PADAPTER pAdapter,
IN enum channel_width ChnlWidth,
IN unsigned char Offset);
/* extern void PHY_SetBWModeCallback8192C(PRT_TIMER pTimer ); */
void PHY_SetBWMode8188E(PADAPTER pAdapter,
enum channel_width ChnlWidth,
unsigned char Offset);
/*
* Set FW CMD IO for 8192S.
*/
/* extern BOOLEAN HalSetIO8192C( IN PADAPTER Adapter,
* IN IO_TYPE IOType); */
/* extern BOOLEAN HalSetIO8192C(PADAPTER Adapter,
* IO_TYPE IOType); */
/*
* Set A2 entry to fw for 8192S
* */
extern void FillA2Entry8192C(IN PADAPTER Adapter,
IN u8 index,
IN u8 *val);
extern void FillA2Entry8192C(PADAPTER Adapter,
u8 index,
u8 *val);
/*
* channel switch related funciton
*/
/* extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer ); */
void PHY_SwChnl8188E(IN PADAPTER pAdapter,
IN u8 channel);
/* extern void PHY_SwChnlCallback8192C(PRT_TIMER pTimer ); */
void PHY_SwChnl8188E(PADAPTER pAdapter,
u8 channel);
VOID
void
PHY_SetSwChnlBWMode8188E(
IN PADAPTER Adapter,
IN u8 channel,
IN enum channel_width Bandwidth,
IN u8 Offset40,
IN u8 Offset80
PADAPTER Adapter,
u8 channel,
enum channel_width Bandwidth,
u8 Offset40,
u8 Offset80
);
VOID
void
PHY_SetRFEReg_8188E(
IN PADAPTER Adapter
PADAPTER Adapter
);
/*
* BB/MAC/RF other monitor API
* */
VOID phy_set_rf_path_switch_8188e(IN struct dm_struct *phydm, IN bool bMain);
void phy_set_rf_path_switch_8188e(struct dm_struct *phydm, bool bMain);
extern VOID
extern void
PHY_SwitchEphyParameter(
IN PADAPTER Adapter
PADAPTER Adapter
);
extern VOID
extern void
PHY_EnableHostClkReq(
IN PADAPTER Adapter
PADAPTER Adapter
);
BOOLEAN
SetAntennaConfig92C(
IN PADAPTER Adapter,
IN u8 DefaultAnt
PADAPTER Adapter,
u8 DefaultAnt
);
/*--------------------------Exported Function prototype---------------------*/
@@ -253,7 +242,7 @@ SetAntennaConfig92C(
#endif
#if (SIC_ENABLE == 1)
VOID SIC_Init(IN PADAPTER Adapter);
void SIC_Init( PADAPTER Adapter);
#endif

90
include/Hal8188FPhyCfg.h
View File

@@ -39,34 +39,34 @@
/*--------------------------Exported Function prototype---------------------*/
u32
PHY_QueryBBReg_8188F(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask
PADAPTER Adapter,
u32 RegAddr,
u32 BitMask
);
VOID
void
PHY_SetBBReg_8188F(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
PADAPTER Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data
);
u32
PHY_QueryRFReg_8188F(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask
PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask
);
VOID
void
PHY_SetRFReg_8188F(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask,
u32 Data
);
/* MAC/BB/RF HAL config */
@@ -78,53 +78,37 @@ s32 PHY_MACConfig8188F(PADAPTER padapter);
int
PHY_ConfigRFWithParaFile_8188F(
IN PADAPTER Adapter,
IN u8 *pFileName,
PADAPTER Adapter,
u8 *pFileName,
enum rf_path eRFPath
);
VOID
void
PHY_SetTxPowerIndex_8188F(
IN PADAPTER Adapter,
IN u32 PowerIndex,
IN enum rf_path RFPath,
IN u8 Rate
PADAPTER Adapter,
u32 PowerIndex,
enum rf_path RFPath,
u8 Rate
);
u8
PHY_GetTxPowerIndex_8188F(
IN PADAPTER pAdapter,
IN enum rf_path RFPath,
IN u8 Rate,
IN u8 BandWidth,
IN u8 Channel,
struct txpwr_idx_comp *tic
);
VOID
PHY_GetTxPowerLevel8188F(
IN PADAPTER Adapter,
OUT s32 *powerlevel
);
VOID
void
PHY_SetTxPowerLevel8188F(
IN PADAPTER Adapter,
IN u8 channel
PADAPTER Adapter,
u8 channel
);
VOID
void
PHY_SetSwChnlBWMode8188F(
IN PADAPTER Adapter,
IN u8 channel,
IN enum channel_width Bandwidth,
IN u8 Offset40,
IN u8 Offset80
PADAPTER Adapter,
u8 channel,
enum channel_width Bandwidth,
u8 Offset40,
u8 Offset80
);
VOID phy_set_rf_path_switch_8188f(
IN struct dm_struct *phydm,
IN bool bMain
void phy_set_rf_path_switch_8188f(
struct dm_struct *phydm,
bool bMain
);
void BBTurnOnBlock_8188F(_adapter *adapter);

92
include/Hal8192EPhyCfg.h
View File

@@ -51,30 +51,30 @@
/*
* BB and RF register read/write
* */
u32 PHY_QueryBBReg8192E(IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask);
void PHY_SetBBReg8192E(IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data);
u32 PHY_QueryRFReg8192E(IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask);
void PHY_SetRFReg8192E(IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data);
u32 PHY_QueryBBReg8192E(PADAPTER Adapter,
u32 RegAddr,
u32 BitMask);
void PHY_SetBBReg8192E(PADAPTER Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data);
u32 PHY_QueryRFReg8192E(PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask);
void PHY_SetRFReg8192E(PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask,
u32 Data);
/*
* Initialization related function
*
* MAC/BB/RF HAL config */
int PHY_MACConfig8192E(IN PADAPTER Adapter);
int PHY_BBConfig8192E(IN PADAPTER Adapter);
int PHY_RFConfig8192E(IN PADAPTER Adapter);
int PHY_MACConfig8192E(PADAPTER Adapter);
int PHY_BBConfig8192E(PADAPTER Adapter);
int PHY_RFConfig8192E(PADAPTER Adapter);
/* RF config */
@@ -82,66 +82,54 @@ int PHY_RFConfig8192E(IN PADAPTER Adapter);
/*
* BB TX Power R/W
* */
void PHY_GetTxPowerLevel8192E(IN PADAPTER Adapter, OUT s32 *powerlevel);
void PHY_SetTxPowerLevel8192E(IN PADAPTER Adapter, IN u8 channel);
BOOLEAN PHY_UpdateTxPowerDbm8192E(IN PADAPTER Adapter, IN int powerInDbm);
void PHY_SetTxPowerLevel8192E(PADAPTER Adapter, u8 channel);
VOID
void
PHY_SetTxPowerIndex_8192E(
IN PADAPTER Adapter,
IN u32 PowerIndex,
IN enum rf_path RFPath,
IN u8 Rate
);
u8
PHY_GetTxPowerIndex_8192E(
IN PADAPTER pAdapter,
IN enum rf_path RFPath,
IN u8 Rate,
IN u8 BandWidth,
IN u8 Channel,
struct txpwr_idx_comp *tic
PADAPTER Adapter,
u32 PowerIndex,
enum rf_path RFPath,
u8 Rate
);
/*
* channel switch related funciton
* */
VOID
void
PHY_SetSwChnlBWMode8192E(
IN PADAPTER Adapter,
IN u8 channel,
IN enum channel_width Bandwidth,
IN u8 Offset40,
IN u8 Offset80
PADAPTER Adapter,
u8 channel,
enum channel_width Bandwidth,
u8 Offset40,
u8 Offset80
);
VOID
void
PHY_SetRFEReg_8192E(
IN PADAPTER Adapter
PADAPTER Adapter
);
void
phy_SpurCalibration_8192E(
IN PADAPTER Adapter,
IN enum spur_cal_method method
PADAPTER Adapter,
enum spur_cal_method method
);
void PHY_SpurCalibration_8192E(IN PADAPTER Adapter);
void PHY_SpurCalibration_8192E( PADAPTER Adapter);
#ifdef CONFIG_SPUR_CAL_NBI
void
phy_SpurCalibration_8192E_NBI(
IN PADAPTER Adapter
PADAPTER Adapter
);
#endif
/*
* BB/MAC/RF other monitor API
* */
VOID
void
phy_set_rf_path_switch_8192e(
IN struct dm_struct *phydm,
IN bool bMain
struct dm_struct *phydm,
bool bMain
);
/*--------------------------Exported Function prototype---------------------*/

90
include/Hal8192FPhyCfg.h
View File

@@ -39,34 +39,34 @@
/*--------------------------Exported Function prototype---------------------*/
u32
PHY_QueryBBReg_8192F(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask
PADAPTER Adapter,
u32 RegAddr,
u32 BitMask
);
VOID
void
PHY_SetBBReg_8192F(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
PADAPTER Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data
);
u32
PHY_QueryRFReg_8192F(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask
PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask
);
VOID
void
PHY_SetRFReg_8192F(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask,
u32 Data
);
/* MAC/BB/RF HAL config */
@@ -78,53 +78,37 @@ s32 PHY_MACConfig8192F(PADAPTER padapter);
int
PHY_ConfigRFWithParaFile_8192F(
IN PADAPTER Adapter,
IN u8 *pFileName,
PADAPTER Adapter,
u8 *pFileName,
enum rf_path eRFPath
);
VOID
void
PHY_SetTxPowerIndex_8192F(
IN PADAPTER Adapter,
IN u32 PowerIndex,
IN enum rf_path RFPath,
IN u8 Rate
PADAPTER Adapter,
u32 PowerIndex,
enum rf_path RFPath,
u8 Rate
);
u8
PHY_GetTxPowerIndex_8192F(
IN PADAPTER pAdapter,
IN enum rf_path RFPath,
IN u8 Rate,
IN u8 BandWidth,
IN u8 Channel,
struct txpwr_idx_comp *tic
);
VOID
PHY_GetTxPowerLevel8192F(
IN PADAPTER Adapter,
OUT s32 *powerlevel
);
VOID
void
PHY_SetTxPowerLevel8192F(
IN PADAPTER Adapter,
IN u8 channel
PADAPTER Adapter,
u8 channel
);
VOID
void
PHY_SetSwChnlBWMode8192F(
IN PADAPTER Adapter,
IN u8 channel,
IN enum channel_width Bandwidth,
IN u8 Offset40,
IN u8 Offset80
PADAPTER Adapter,
u8 channel,
enum channel_width Bandwidth,
u8 Offset40,
u8 Offset80
);
VOID phy_set_rf_path_switch_8192f(
IN PADAPTER pAdapter,
IN bool bMain
void phy_set_rf_path_switch_8192f(
PADAPTER pAdapter,
bool bMain
);
/*--------------------------Exported Function prototype End---------------------*/

90
include/Hal8703BPhyCfg.h
View File

@@ -39,34 +39,34 @@
/*--------------------------Exported Function prototype---------------------*/
u32
PHY_QueryBBReg_8703B(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask
PADAPTER Adapter,
u32 RegAddr,
u32 BitMask
);
VOID
void
PHY_SetBBReg_8703B(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
PADAPTER Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data
);
u32
PHY_QueryRFReg_8703B(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask
PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask
);
VOID
void
PHY_SetRFReg_8703B(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask,
u32 Data
);
/* MAC/BB/RF HAL config */
@@ -78,53 +78,37 @@ s32 PHY_MACConfig8703B(PADAPTER padapter);
int
PHY_ConfigRFWithParaFile_8703B(
IN PADAPTER Adapter,
IN u8 *pFileName,
PADAPTER Adapter,
u8 *pFileName,
enum rf_path eRFPath
);
VOID
void
PHY_SetTxPowerIndex_8703B(
IN PADAPTER Adapter,
IN u32 PowerIndex,
IN enum rf_path RFPath,
IN u8 Rate
PADAPTER Adapter,
u32 PowerIndex,
enum rf_path RFPath,
u8 Rate
);
u8
PHY_GetTxPowerIndex_8703B(
IN PADAPTER pAdapter,
IN enum rf_path RFPath,
IN u8 Rate,
IN u8 BandWidth,
IN u8 Channel,
struct txpwr_idx_comp *tic
);
VOID
PHY_GetTxPowerLevel8703B(
IN PADAPTER Adapter,
OUT s32 *powerlevel
);
VOID
void
PHY_SetTxPowerLevel8703B(
IN PADAPTER Adapter,
IN u8 channel
PADAPTER Adapter,
u8 channel
);
VOID
void
PHY_SetSwChnlBWMode8703B(
IN PADAPTER Adapter,
IN u8 channel,
IN enum channel_width Bandwidth,
IN u8 Offset40,
IN u8 Offset80
PADAPTER Adapter,
u8 channel,
enum channel_width Bandwidth,
u8 Offset40,
u8 Offset80
);
VOID phy_set_rf_path_switch_8703b(
IN struct dm_struct *phydm,
IN bool bMain
void phy_set_rf_path_switch_8703b(
struct dm_struct *phydm,
bool bMain
);
/*--------------------------Exported Function prototype End---------------------*/

84
include/Hal8710BPhyCfg.h
View File

@@ -39,34 +39,34 @@
/*--------------------------Exported Function prototype---------------------*/
u32
PHY_QueryBBReg_8710B(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask
PADAPTER Adapter,
u32 RegAddr,
u32 BitMask
);
VOID
void
PHY_SetBBReg_8710B(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
PADAPTER Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data
);
u32
PHY_QueryRFReg_8710B(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask
PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask
);
VOID
void
PHY_SetRFReg_8710B(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask,
u32 Data
);
/* MAC/BB/RF HAL config */
@@ -78,48 +78,32 @@ s32 PHY_MACConfig8710B(PADAPTER padapter);
int
PHY_ConfigRFWithParaFile_8710B(
IN PADAPTER Adapter,
IN u8 *pFileName,
PADAPTER Adapter,
u8 *pFileName,
enum rf_path eRFPath
);
VOID
void
PHY_SetTxPowerIndex_8710B(
IN PADAPTER Adapter,
IN u32 PowerIndex,
IN enum rf_path RFPath,
IN u8 Rate
PADAPTER Adapter,
u32 PowerIndex,
enum rf_path RFPath,
u8 Rate
);
u8
PHY_GetTxPowerIndex_8710B(
IN PADAPTER pAdapter,
IN enum rf_path RFPath,
IN u8 Rate,
IN u8 BandWidth,
IN u8 Channel,
struct txpwr_idx_comp *tic
);
VOID
PHY_GetTxPowerLevel8710B(
IN PADAPTER Adapter,
OUT s32 *powerlevel
);
VOID
void
PHY_SetTxPowerLevel8710B(
IN PADAPTER Adapter,
IN u8 channel
PADAPTER Adapter,
u8 channel
);
VOID
void
PHY_SetSwChnlBWMode8710B(
IN PADAPTER Adapter,
IN u8 channel,
IN enum channel_width Bandwidth,
IN u8 Offset40,
IN u8 Offset80
PADAPTER Adapter,
u8 channel,
enum channel_width Bandwidth,
u8 Offset40,
u8 Offset80
);
/*--------------------------Exported Function prototype End---------------------*/

90
include/Hal8723BPhyCfg.h
View File

@@ -39,34 +39,34 @@
/*--------------------------Exported Function prototype---------------------*/
u32
PHY_QueryBBReg_8723B(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask
PADAPTER Adapter,
u32 RegAddr,
u32 BitMask
);
VOID
void
PHY_SetBBReg_8723B(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
PADAPTER Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data
);
u32
PHY_QueryRFReg_8723B(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask
PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask
);
VOID
void
PHY_SetRFReg_8723B(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask,
u32 Data
);
/* MAC/BB/RF HAL config */
@@ -78,53 +78,37 @@ s32 PHY_MACConfig8723B(PADAPTER padapter);
int
PHY_ConfigRFWithParaFile_8723B(
IN PADAPTER Adapter,
IN u8 *pFileName,
PADAPTER Adapter,
u8 *pFileName,
enum rf_path eRFPath
);
VOID
void
PHY_SetTxPowerIndex_8723B(
IN PADAPTER Adapter,
IN u32 PowerIndex,
IN enum rf_path RFPath,
IN u8 Rate
PADAPTER Adapter,
u32 PowerIndex,
enum rf_path RFPath,
u8 Rate
);
u8
PHY_GetTxPowerIndex_8723B(
IN PADAPTER pAdapter,
IN enum rf_path RFPath,
IN u8 Rate,
IN u8 BandWidth,
IN u8 Channel,
struct txpwr_idx_comp *tic
);
VOID
PHY_GetTxPowerLevel8723B(
IN PADAPTER Adapter,
OUT s32 *powerlevel
);
VOID
void
PHY_SetTxPowerLevel8723B(
IN PADAPTER Adapter,
IN u8 channel
PADAPTER Adapter,
u8 channel
);
VOID
void
PHY_SetSwChnlBWMode8723B(
IN PADAPTER Adapter,
IN u8 channel,
IN enum channel_width Bandwidth,
IN u8 Offset40,
IN u8 Offset80
PADAPTER Adapter,
u8 channel,
enum channel_width Bandwidth,
u8 Offset40,
u8 Offset80
);
VOID phy_set_rf_path_switch_8723b(
IN struct dm_struct *phydm,
IN bool bMain
void phy_set_rf_path_switch_8723b(
struct dm_struct *phydm,
bool bMain
);
/*--------------------------Exported Function prototype End---------------------*/

90
include/Hal8723DPhyCfg.h
View File

@@ -39,34 +39,34 @@
/*--------------------------Exported Function prototype---------------------*/
u32
PHY_QueryBBReg_8723D(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask
PADAPTER Adapter,
u32 RegAddr,
u32 BitMask
);
VOID
void
PHY_SetBBReg_8723D(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
PADAPTER Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data
);
u32
PHY_QueryRFReg_8723D(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask
PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask
);
VOID
void
PHY_SetRFReg_8723D(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask,
u32 Data
);
/* MAC/BB/RF HAL config */
@@ -78,53 +78,37 @@ s32 PHY_MACConfig8723D(PADAPTER padapter);
int
PHY_ConfigRFWithParaFile_8723D(
IN PADAPTER Adapter,
IN u8 *pFileName,
PADAPTER Adapter,
u8 *pFileName,
enum rf_path eRFPath
);
VOID
void
PHY_SetTxPowerIndex_8723D(
IN PADAPTER Adapter,
IN u32 PowerIndex,
IN enum rf_path RFPath,
IN u8 Rate
PADAPTER Adapter,
u32 PowerIndex,
enum rf_path RFPath,
u8 Rate
);
u8
PHY_GetTxPowerIndex_8723D(
IN PADAPTER pAdapter,
IN enum rf_path RFPath,
IN u8 Rate,
IN u8 BandWidth,
IN u8 Channel,
struct txpwr_idx_comp *tic
);
VOID
PHY_GetTxPowerLevel8723D(
IN PADAPTER Adapter,
OUT s32 *powerlevel
);
VOID
void
PHY_SetTxPowerLevel8723D(
IN PADAPTER Adapter,
IN u8 channel
PADAPTER Adapter,
u8 channel
);
VOID
void
PHY_SetSwChnlBWMode8723D(
IN PADAPTER Adapter,
IN u8 channel,
IN enum channel_width Bandwidth,
IN u8 Offset40,
IN u8 Offset80
PADAPTER Adapter,
u8 channel,
enum channel_width Bandwidth,
u8 Offset40,
u8 Offset80
);
VOID phy_set_rf_path_switch_8723d(
IN struct dm_struct *phydm,
IN bool bMain
void phy_set_rf_path_switch_8723d(
struct dm_struct *phydm,
bool bMain
);
/*--------------------------Exported Function prototype End---------------------*/

91
include/Hal8812PhyCfg.h
View File

@@ -53,90 +53,81 @@
/*
* BB and RF register read/write
* */
u32 PHY_QueryBBReg8812(IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask);
void PHY_SetBBReg8812(IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data);
u32 PHY_QueryRFReg8812(IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask);
void PHY_SetRFReg8812(IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data);
u32 PHY_QueryBBReg8812(PADAPTER Adapter,
u32 RegAddr,
u32 BitMask);
void PHY_SetBBReg8812(PADAPTER Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data);
u32 PHY_QueryRFReg8812(PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask);
void PHY_SetRFReg8812(PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask,
u32 Data);
/*
* Initialization related function
*
* MAC/BB/RF HAL config */
int PHY_MACConfig8812(IN PADAPTER Adapter);
int PHY_BBConfig8812(IN PADAPTER Adapter);
void PHY_BB8812_Config_1T(IN PADAPTER Adapter);
int PHY_RFConfig8812(IN PADAPTER Adapter);
int PHY_MACConfig8812(PADAPTER Adapter);
int PHY_BBConfig8812(PADAPTER Adapter);
void PHY_BB8812_Config_1T(PADAPTER Adapter);
int PHY_RFConfig8812(PADAPTER Adapter);
/* RF config */
s32
PHY_SwitchWirelessBand8812(
IN PADAPTER Adapter,
IN u8 Band
PADAPTER Adapter,
u8 Band
);
/*
* BB TX Power R/W
* */
void PHY_GetTxPowerLevel8812(IN PADAPTER Adapter, OUT s32 *powerlevel);
void PHY_SetTxPowerLevel8812(IN PADAPTER Adapter, IN u8 Channel);
void PHY_SetTxPowerLevel8812(PADAPTER Adapter, u8 Channel);
BOOLEAN PHY_UpdateTxPowerDbm8812(IN PADAPTER Adapter, IN int powerInDbm);
u8 PHY_GetTxPowerIndex_8812A(
IN PADAPTER pAdapter,
IN enum rf_path RFPath,
IN u8 Rate,
IN u8 BandWidth,
IN u8 Channel,
struct txpwr_idx_comp *tic
);
bool phy_get_txpwr_target_skip_by_rate_8812a(_adapter *adapter, enum MGN_RATE rate);
u32 phy_get_tx_bb_swing_8812a(
IN PADAPTER Adapter,
IN BAND_TYPE Band,
IN enum rf_path RFPath
PADAPTER Adapter,
BAND_TYPE Band,
enum rf_path RFPath
);
VOID
void
PHY_SetTxPowerIndex_8812A(
IN PADAPTER Adapter,
IN u32 PowerIndex,
IN enum rf_path RFPath,
IN u8 Rate
PADAPTER Adapter,
u32 PowerIndex,
enum rf_path RFPath,
u8 Rate
);
/*
* channel switch related funciton
* */
VOID
void
PHY_SetSwChnlBWMode8812(
IN PADAPTER Adapter,
IN u8 channel,
IN enum channel_width Bandwidth,
IN u8 Offset40,
IN u8 Offset80
PADAPTER Adapter,
u8 channel,
enum channel_width Bandwidth,
u8 Offset40,
u8 Offset80
);
/*
* BB/MAC/RF other monitor API
* */
VOID
void
phy_set_rf_path_switch_8812a(
IN struct dm_struct *phydm,
IN bool bMain
struct dm_struct *phydm,
bool bMain
);
/*--------------------------Exported Function prototype---------------------*/

192
include/Hal8814PhyCfg.h
View File

@@ -55,52 +55,52 @@
/* 1. BB register R/W API */
extern u32
PHY_QueryBBReg8814A(IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask);
VOID
PHY_SetBBReg8814A(IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data);
extern u32
PHY_QueryRFReg8814A(IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask);
PHY_QueryBBReg8814A(PADAPTER Adapter,
u32 RegAddr,
u32 BitMask);
void
PHY_SetRFReg8814A(IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data);
PHY_SetBBReg8814A(PADAPTER Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data);
extern u32
PHY_QueryRFReg8814A(PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask);
void
PHY_SetRFReg8814A(PADAPTER Adapter,
enum rf_path eRFPath,
u32 RegAddr,
u32 BitMask,
u32 Data);
/* 1 3. Initial BB/RF config by reading MAC/BB/RF txt. */
s32
phy_BB8814A_Config_ParaFile(
IN PADAPTER Adapter
PADAPTER Adapter
);
VOID
void
PHY_ConfigBB_8814A(
IN PADAPTER Adapter
PADAPTER Adapter
);
VOID
void
phy_ADC_CLK_8814A(
IN PADAPTER Adapter
PADAPTER Adapter
);
s32
PHY_RFConfig8814A(
IN PADAPTER Adapter
PADAPTER Adapter
);
/*
@@ -110,151 +110,123 @@ PHY_RFConfig8814A(
/* 1 5. Tx Power setting API */
VOID
PHY_GetTxPowerLevel8814(
IN PADAPTER Adapter,
OUT ps4Byte powerlevel
);
VOID
void
PHY_SetTxPowerLevel8814(
IN PADAPTER Adapter,
IN u8 Channel
PADAPTER Adapter,
u8 Channel
);
u8
phy_get_tx_power_index_8814a(
IN PADAPTER Adapter,
IN enum rf_path RFPath,
IN u8 Rate,
IN enum channel_width BandWidth,
IN u8 Channel
PADAPTER Adapter,
enum rf_path RFPath,
u8 Rate,
enum channel_width BandWidth,
u8 Channel
);
u8
PHY_GetTxPowerIndex8814A(
IN PADAPTER Adapter,
IN enum rf_path RFPath,
IN u8 Rate,
IN u8 BandWidth,
IN u8 Channel,
struct txpwr_idx_comp *tic
);
VOID
void
PHY_SetTxPowerIndex_8814A(
IN PADAPTER Adapter,
IN u32 PowerIndex,
IN enum rf_path RFPath,
IN u8 Rate
PADAPTER Adapter,
u32 PowerIndex,
enum rf_path RFPath,
u8 Rate
);
BOOLEAN
PHY_UpdateTxPowerDbm8814A(
IN PADAPTER Adapter,
IN s4Byte powerInDbm
);
u32
PHY_GetTxBBSwing_8814A(
IN PADAPTER Adapter,
IN BAND_TYPE Band,
IN enum rf_path RFPath
PADAPTER Adapter,
BAND_TYPE Band,
enum rf_path RFPath
);
/* 1 6. Channel setting API */
#if 0
VOID
void
PHY_SwChnlTimerCallback8814A(
IN struct timer_list *p_timer
struct timer_list *p_timer
);
#endif
VOID
void
PHY_SwChnlWorkItemCallback8814A(
IN PVOID pContext
void *pContext
);
VOID
void
HAL_HandleSwChnl8814A(
IN PADAPTER pAdapter,
IN u8 channel
PADAPTER pAdapter,
u8 channel
);
VOID
PHY_SwChnlSynchronously8814A(IN PADAPTER pAdapter,
IN u8 channel);
void
PHY_SwChnlSynchronously8814A(PADAPTER pAdapter,
u8 channel);
VOID
PHY_SwChnlAndSetBWModeCallback8814A(IN PVOID pContext);
VOID
void
PHY_HandleSwChnlAndSetBW8814A(
IN PADAPTER Adapter,
IN BOOLEAN bSwitchChannel,
IN BOOLEAN bSetBandWidth,
IN u8 ChannelNum,
IN enum channel_width ChnlWidth,
IN u8 ChnlOffsetOf40MHz,
IN u8 ChnlOffsetOf80MHz,
IN u8 CenterFrequencyIndex1
PADAPTER Adapter,
BOOLEAN bSwitchChannel,
BOOLEAN bSetBandWidth,
u8 ChannelNum,
enum channel_width ChnlWidth,
u8 ChnlOffsetOf40MHz,
u8 ChnlOffsetOf80MHz,
u8 CenterFrequencyIndex1
);
BOOLEAN
PHY_QueryRFPathSwitch_8814A(IN PADAPTER pAdapter);
PHY_QueryRFPathSwitch_8814A(PADAPTER pAdapter);
#if (USE_WORKITEM)
VOID
void
RtCheckForHangWorkItemCallback8814A(
IN PVOID pContext
void *pContext
);
#endif
BOOLEAN
SetAntennaConfig8814A(
IN PADAPTER Adapter,
IN u8 DefaultAnt
PADAPTER Adapter,
u8 DefaultAnt
);
VOID
void
PHY_SetRFEReg8814A(
IN PADAPTER Adapter,
IN BOOLEAN bInit,
IN u8 Band
PADAPTER Adapter,
BOOLEAN bInit,
u8 Band
);
s32
PHY_SwitchWirelessBand8814A(
IN PADAPTER Adapter,
IN u8 Band
PADAPTER Adapter,
u8 Band
);
VOID
void
PHY_SetIO_8814A(
PADAPTER pAdapter
);
VOID
void
PHY_SetSwChnlBWMode8814(
IN PADAPTER Adapter,
IN u8 channel,
IN enum channel_width Bandwidth,
IN u8 Offset40,
IN u8 Offset80
PADAPTER Adapter,
u8 channel,
enum channel_width Bandwidth,
u8 Offset40,
u8 Offset80
);
s32 PHY_MACConfig8814(PADAPTER Adapter);
int PHY_BBConfig8814(PADAPTER Adapter);
VOID PHY_Set_SecCCATH_by_RXANT_8814A(PADAPTER pAdapter, u4Byte ulAntennaRx);
void PHY_Set_SecCCATH_by_RXANT_8814A(PADAPTER pAdapter, u32 ulAntennaRx);

14
include/Hal8814PwrSeq.h
View File

@@ -76,9 +76,9 @@
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
{0x0002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \
{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
{0x0002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/ \
/*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},*/ /*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x28}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/ \
@@ -188,9 +188,9 @@
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \
{0x0002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \
{0x0002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x05F1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Respond TxOK to scheduler*/
@@ -209,7 +209,7 @@
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x1002[1:0] = 2b'11 enable BB macro*/ \
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x1002[1:0] = 2b'11 enable BB macro*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8814A_TRANS_END \

6
include/HalVerDef.h
View File

@@ -39,6 +39,8 @@ typedef enum tag_HAL_IC_Type_Definition {
CHIP_8710B = 16,
CHIP_8192F = 17,
CHIP_8188GTV = 18,
CHIP_8822C = 19,
CHIP_8814B = 20,
} HAL_IC_TYPE_E;
/* HAL_CHIP_TYPE_E */
@@ -126,6 +128,8 @@ typedef struct tag_HAL_VERSION {
#define IS_8821C_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821C) ? TRUE : FALSE)
#define IS_8723D_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723D) ? TRUE : FALSE)
#define IS_8710B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8710B) ? TRUE : FALSE)
#define IS_8822C_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8822C) ? TRUE : FALSE)
#define IS_8814B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8814B) ? TRUE : FALSE)
#define IS_8192F_SERIES(version)\
((GET_CVID_IC_TYPE(version) == CHIP_8192F) ? TRUE : FALSE)
@@ -153,6 +157,8 @@ typedef struct tag_HAL_VERSION {
#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R) ? TRUE : FALSE)
#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R) ? TRUE : FALSE)
#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R) ? TRUE : FALSE)
#define IS_2T3R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T3R) ? TRUE : FALSE)
#define IS_2T4R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T4R) ? TRUE : FALSE)
#define IS_3T3R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_3T3R) ? TRUE : FALSE)
#define IS_3T4R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_3T4R) ? TRUE : FALSE)
#define IS_4T4R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_4T4R) ? TRUE : FALSE)

6
include/autoconf.h Normal file → Executable file
View File

@@ -33,7 +33,6 @@
* Wi-Fi Functions Config
*/
#define CONFIG_IEEE80211_BAND_5GHZ 1
#define CONFIG_80211N_HT
#define CONFIG_80211AC_VHT
#ifdef CONFIG_80211AC_VHT
@@ -204,9 +203,6 @@
#endif
#define RTW_NOTCH_FILTER 0 /* 0:Disable, 1:Enable, */
#define CONFIG_TX_MCAST2UNI /*Support IP multicast->unicast*/
/* #define CONFIG_CHECK_AC_LIFETIME 1 */ /* Check packet lifetime of 4 ACs. */
/*
* Interface Related Config
@@ -312,8 +308,6 @@
*/
#define DBG 1
#define CONFIG_PROC_DEBUG
#define DBG_CONFIG_ERROR_DETECT
/* #define CONFIG_DIS_UPHY */

61
include/basic_types.h
View File

@@ -77,24 +77,9 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/utsname.h>
#define IN
#define OUT
#define VOID void
#define NDIS_OID uint
#define NDIS_STATUS uint
typedef signed int sint;
#ifndef PVOID
typedef void *PVOID;
/* #define PVOID (void *) */
#endif
#define UCHAR u8
#define USHORT u16
#define UINT u32
#define ULONG u32
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19))
typedef _Bool bool;
@@ -110,37 +95,8 @@ enum {
typedef __kernel_ssize_t SSIZE_T;
#define FIELD_OFFSET(s, field) ((SSIZE_T)&((s *)(0))->field)
#define u1Byte u8
#define pu1Byte u8*
#define u2Byte u16
#define pu2Byte u16*
#define u4Byte u32
#define pu4Byte u32*
#define u8Byte u64
#define pu8Byte u64*
#define s1Byte s8
#define ps1Byte s8*
#define s2Byte s16
#define ps2Byte s16*
#define s4Byte s32
#define ps4Byte s32*
#define s8Byte s64
#define ps8Byte s64*
#define UCHAR u8
#define USHORT u16
#define UINT u32
#define ULONG u32
#define PULONG u32*
#endif
#define NDIS_OID uint
#endif /*PLATFORM_LINUX*/
#ifdef PLATFORM_FREEBSD
@@ -160,21 +116,8 @@ enum {
typedef signed long long s64;
typedef unsigned long long u64;
#define IN
#define OUT
#define VOID void
#define NDIS_OID uint
#define NDIS_STATUS uint
#ifndef PVOID
typedef void *PVOID;
/* #define PVOID (void *) */
#endif
typedef u32 dma_addr_t;
#define UCHAR u8
#define USHORT u16
#define UINT u32
#define ULONG u32
typedef void (*proc_t)(void *);

16
include/cmn_info/rtw_sta_info.h
View File

@@ -89,6 +89,7 @@ enum rf_type {
};
enum bb_path {
BB_PATH_NON = 0,
BB_PATH_A = 0x00000001,
BB_PATH_B = 0x00000002,
BB_PATH_C = 0x00000004,
@@ -107,6 +108,7 @@ enum bb_path {
BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
BB_PATH_AUTO = 0xff /*for path diversity*/
};
enum rf_path {
@@ -132,6 +134,11 @@ enum rf_syn {
RF_SYN1 = 1,
};
enum rfc_mode {
rfc_4x4 = 0,
rfc_2x2 = 1,
};
enum wireless_set {
WIRELESS_CCK = 0x00000001,
WIRELESS_OFDM = 0x00000002,
@@ -189,7 +196,7 @@ struct dtp_info {
};
struct cmn_sta_info {
u16 dm_ctrl; /*[Driver]*/
u16 dm_ctrl; /*[Driver]*/
enum channel_width bw_mode; /*[Driver] max support BW*/
u8 mac_id; /*[Driver]*/
u8 mac_addr[6]; /*[Driver]*/
@@ -211,7 +218,12 @@ struct cmn_sta_info {
/*u8 total_pw2cca_cnt;*/
};
struct phydm_phyinfo_fw_struct {
u8 rx_rssi[4]; /* RSSI in 0~100 index */
};
struct phydm_phyinfo_struct {
boolean physts_rpt_valid; /* @if physts_rpt_valid is false, please ignore the parsing result in this structure*/
u8 rx_pwdb_all;
u8 signal_quality; /* OFDM: signal_quality=rx_mimo_signal_quality[0], CCK: signal qualityin 0-100 index. */
u8 rx_mimo_signal_strength[4]; /* RSSI in 0~100 index */
@@ -228,7 +240,7 @@ struct phydm_phyinfo_struct {
u8 ant_idx[4]; /*per-path's antenna index*/
/*ODM_PHY_STATUS_NEW_TYPE_SUPPORT*/
u8 rx_count:2; /* RX path counter---*/
u8 band_width:2;
u8 band_width:3;
u8 rxsc:4; /* sub-channel---*/
u8 channel; /* channel number---*/
u8 is_mu_packet:1; /* is MU packet or not---boolean*/

12
include/custom_gpio.h
View File

@@ -18,18 +18,6 @@
#include <drv_conf.h>
#include <osdep_service.h>
#ifdef PLATFORM_OS_XP
#include <drv_types_xp.h>
#endif
#ifdef PLATFORM_OS_CE
#include <drv_types_ce.h>
#endif
#ifdef PLATFORM_LINUX
#include <drv_types_linux.h>
#endif
typedef enum cust_gpio_modes {
WLAN_PWDN_ON,
WLAN_PWDN_OFF,

193
include/drv_conf.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
* Copyright(c) 2007 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -16,11 +16,7 @@
#define __DRV_CONF_H__
#include "autoconf.h"
#include "hal_ic_cfg.h"
#if defined(PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
#error "Shall be Linux or Windows, but not both!\n"
#endif
#define CONFIG_RSSI_PRIORITY
#ifdef CONFIG_RTW_REPEATER_SON
#ifndef CONFIG_AP
@@ -114,14 +110,6 @@
#define CONFIG_USB_VENDOR_REQ_MUTEX
#endif
#if defined(CONFIG_DFS_SLAVE_WITH_RADAR_DETECT) && !defined(CONFIG_DFS_MASTER)
#define CONFIG_DFS_MASTER
#endif
#if !defined(CONFIG_AP_MODE) && defined(CONFIG_DFS_MASTER)
#error "enable CONFIG_DFS_MASTER without CONFIG_AP_MODE"
#endif
#ifdef CONFIG_WIFI_MONITOR
/* #define CONFIG_MONITOR_MODE_XMIT */
#endif
@@ -130,9 +118,6 @@
#ifndef CONFIG_WIFI_MONITOR
#define CONFIG_WIFI_MONITOR
#endif
#ifndef CONFIG_MONITOR_MODE_XMIT
#define CONFIG_MONITOR_MODE_XMIT
#endif
#ifdef CONFIG_POWER_SAVING
#undef CONFIG_POWER_SAVING
#endif
@@ -147,6 +132,11 @@
#endif
#endif
#ifdef CONFIG_AP_MODE
#define CONFIG_LIMITED_AP_NUM 1
#define CONFIG_TX_MCAST2UNI /* AP mode support IP multicast->unicast */
#endif
#ifdef CONFIG_RTW_MESH
#ifndef CONFIG_RTW_MESH_ACNODE_PREVENT
#define CONFIG_RTW_MESH_ACNODE_PREVENT 1
@@ -163,6 +153,9 @@
#ifndef CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
#define CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST 1
#endif
#ifndef CONFIG_RTW_MESH_CTO_MGATE_CARRIER
#define CONFIG_RTW_MESH_CTO_MGATE_CARRIER CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
#endif
#ifndef CONFIG_RTW_MPM_TX_IES_SYNC_BSS
#define CONFIG_RTW_MPM_TX_IES_SYNC_BSS 1
@@ -186,6 +179,22 @@
#define RTW_SCAN_SPARSE_BG 0
#define RTW_SCAN_SPARSE_ROAMING_ACTIVE 1
#ifndef CONFIG_TX_AC_LIFETIME
#define CONFIG_TX_AC_LIFETIME 1
#endif
#ifndef CONFIG_TX_ACLT_FLAGS
#define CONFIG_TX_ACLT_FLAGS 0x00
#endif
#ifndef CONFIG_TX_ACLT_CONF_DEFAULT
#define CONFIG_TX_ACLT_CONF_DEFAULT {0x0, 1024 * 1000, 1024 * 1000}
#endif
#ifndef CONFIG_TX_ACLT_CONF_AP_M2U
#define CONFIG_TX_ACLT_CONF_AP_M2U {0xF, 256 * 1000, 256 * 1000}
#endif
#ifndef CONFIG_TX_ACLT_CONF_MESH
#define CONFIG_TX_ACLT_CONF_MESH {0xF, 256 * 1000, 256 * 1000}
#endif
#ifndef CONFIG_RTW_HIQ_FILTER
#define CONFIG_RTW_HIQ_FILTER 1
#endif
@@ -210,8 +219,36 @@
#define CONFIG_RTW_EXCL_CHS {0}
#endif
#ifndef CONFIG_RTW_DFS_REGION_DOMAIN
#ifndef CONFIG_IEEE80211_BAND_5GHZ
#if defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8821C) \
|| defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) \
|| defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8814B)
#define CONFIG_IEEE80211_BAND_5GHZ 1
#else
#define CONFIG_IEEE80211_BAND_5GHZ 0
#endif
#endif
#ifndef CONFIG_DFS
#define CONFIG_DFS 1
#endif
#if CONFIG_IEEE80211_BAND_5GHZ && CONFIG_DFS && defined(CONFIG_AP_MODE)
#if !defined(CONFIG_DFS_SLAVE_WITH_RADAR_DETECT)
#define CONFIG_DFS_SLAVE_WITH_RADAR_DETECT 0
#endif
#if !defined(CONFIG_DFS_MASTER) || CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
#define CONFIG_DFS_MASTER
#endif
#if defined(CONFIG_DFS_MASTER) && !defined(CONFIG_RTW_DFS_REGION_DOMAIN)
#define CONFIG_RTW_DFS_REGION_DOMAIN 0
#endif
#else
#undef CONFIG_DFS_MASTER
#undef CONFIG_RTW_DFS_REGION_DOMAIN
#define CONFIG_RTW_DFS_REGION_DOMAIN 0
#undef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
#define CONFIG_DFS_SLAVE_WITH_RADAR_DETECT 0
#endif
#ifndef CONFIG_TXPWR_BY_RATE_EN
@@ -250,8 +287,9 @@
#define CONFIG_TXPWR_LIMIT_EN 1
#endif
#if !defined(CONFIG_TXPWR_LIMIT) && CONFIG_TXPWR_LIMIT_EN
#define CONFIG_TXPWR_LIMIT
#if !CONFIG_TXPWR_LIMIT && CONFIG_TXPWR_LIMIT_EN
#undef CONFIG_TXPWR_LIMIT
#define CONFIG_TXPWR_LIMIT 1
#endif
#ifdef CONFIG_RTW_IPCAM_APPLICATION
@@ -259,9 +297,9 @@
#define CONFIG_TXPWR_BY_RATE_EN 1
#define CONFIG_RTW_CUSTOMIZE_BEEDCA 0x0000431C
#define CONFIG_RTW_CUSTOMIZE_BWMODE 0x00
#define CONFIG_RTW_CUSTOMIZE_RLSTA 0x7
#define CONFIG_RTW_CUSTOMIZE_RLSTA 0x30
#if defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B)
#define CONFIG_RTW_TX_2PATH_EN /* mutually incompatible with STBC_TX & Beamformer */
#define CONFIG_RTW_TX_NPATH_EN /* mutually incompatible with STBC_TX & Beamformer */
#endif
#endif
/*#define CONFIG_EXTEND_LOWRATE_TXOP */
@@ -349,6 +387,32 @@
#error "CONFIG_IFACE_NUMBER cound not be 0 !!"
#endif
#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8188F) || \
defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8192F) || \
defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8710B) || \
defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8723D)
#define CONFIG_HWMPCAP_GEN1
#elif defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) /*|| defined(CONFIG_RTL8814A)*/
#define CONFIG_HWMPCAP_GEN2
#elif defined(CONFIG_RTL8814B) /*Address CAM - 128*/
#define CONFIG_HWMPCAP_GEN3
#endif
#if defined(CONFIG_HWMPCAP_GEN1) && (CONFIG_IFACE_NUMBER > 2)
#ifdef CONFIG_POWER_SAVING
/*#warning "Disable PS when CONFIG_IFACE_NUMBER > 2"*/
#undef CONFIG_POWER_SAVING
#endif
#ifdef CONFIG_WOWLAN
#error "This IC can't support MI and WoWLan at the same time"
#endif
#endif
#if defined(CONFIG_HWMPCAP_GEN1) && (CONFIG_IFACE_NUMBER > 3)
#error " This IC can't support over 3 interfaces !!"
#endif
#if (CONFIG_IFACE_NUMBER > 4)
#error "Not support over 4 interfaces yet !!"
#endif
@@ -368,38 +432,37 @@
#endif
#ifdef CONFIG_AP_MODE
#undef CONFIG_LIMITED_AP_NUM
#define CONFIG_LIMITED_AP_NUM 2
#define CONFIG_SUPPORT_MULTI_BCN
#define CONFIG_SWTIMER_BASED_TXBCN
#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) /* || defined(CONFIG_RTL8822C)*/
#ifdef CONFIG_HWMPCAP_GEN2 /*CONFIG_RTL8822B/CONFIG_RTL8821C/CONFIG_RTL8822C*/
#define CONFIG_FW_HANDLE_TXBCN
#ifdef CONFIG_FW_HANDLE_TXBCN
#ifdef CONFIG_SWTIMER_BASED_TXBCN
#undef CONFIG_SWTIMER_BASED_TXBCN
#endif
#undef CONFIG_LIMITED_AP_NUM
#define CONFIG_LIMITED_AP_NUM 4
#endif
#endif /*defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) */ /*|| defined(CONFIG_RTL8822C)*/
#endif /*CONFIG_HWMPCAP_GEN2*/
#endif /*CONFIG_AP_MODE*/
#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
#ifdef CONFIG_HWMPCAP_GEN2 /*CONFIG_RTL8822B/CONFIG_RTL8821C/CONFIG_RTL8822C*/
#define CONFIG_CLIENT_PORT_CFG
#define CONFIG_NEW_NETDEV_HDL
#endif/*defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)*/
#endif/*CONFIG_HWMPCAP_GEN2*/
#endif/*(CONFIG_IFACE_NUMBER > 2)*/
#define MACID_NUM_SW_LIMIT 32
#define SEC_CAM_ENT_NUM_SW_LIMIT 32
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
#define CONFIG_IEEE80211_BAND_5GHZ
#endif
#if defined(CONFIG_WOWLAN) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8814A))
#if defined(CONFIG_WOWLAN) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B))
#define CONFIG_WOW_PATTERN_HW_CAM
#endif
@@ -466,6 +529,61 @@
#endif
#endif
/* IPS */
#ifndef RTW_IPS_MODE
#if defined(CONFIG_IPS)
#define RTW_IPS_MODE 1
#else
#define RTW_IPS_MODE 0
#endif
#endif /* !RTW_IPS_MODE */
#if (RTW_IPS_MODE > 1 || RTW_IPS_MODE < 0)
#error "The CONFIG_IPS_MODE value is wrong. Please follow HowTo_enable_the_power_saving_functionality.pdf.\n"
#endif
/* LPS */
#ifndef RTW_LPS_MODE
#if defined(CONFIG_LPS_PG) || defined(CONFIG_LPS_PG_DDMA)
#define RTW_LPS_MODE 3
#elif defined(CONFIG_LPS_LCLK)
#define RTW_LPS_MODE 2
#elif defined(CONFIG_LPS)
#define RTW_LPS_MODE 1
#else
#define RTW_LPS_MODE 0
#endif
#endif /* !RTW_LPS_MODE */
#if (RTW_LPS_MODE > 3 || RTW_LPS_MODE < 0)
#error "The CONFIG_LPS_MODE value is wrong. Please follow HowTo_enable_the_power_saving_functionality.pdf.\n"
#endif
#ifndef RTW_LPS_1T1R
#define RTW_LPS_1T1R 0
#endif
#ifndef RTW_WOW_LPS_1T1R
#define RTW_WOW_LPS_1T1R 0
#endif
/* WOW LPS */
#ifndef RTW_WOW_LPS_MODE
#if defined(CONFIG_LPS_PG) || defined(CONFIG_LPS_PG_DDMA)
#define RTW_WOW_LPS_MODE 3
#elif defined(CONFIG_LPS_LCLK)
#define RTW_WOW_LPS_MODE 2
#elif defined(CONFIG_LPS)
#define RTW_WOW_LPS_MODE 1
#else
#define RTW_WOW_LPS_MODE 0
#endif
#endif /* !RTW_WOW_LPS_MODE */
#if (RTW_WOW_LPS_MODE > 3 || RTW_WOW_LPS_MODE < 0)
#error "The RTW_WOW_LPS_MODE value is wrong. Please follow HowTo_enable_the_power_saving_functionality.pdf.\n"
#endif
#ifdef RTW_REDUCE_SCAN_SWITCH_CH_TIME
#ifndef CONFIG_RTL8822B
#error "Only 8822B support RTW_REDUCE_SCAN_SWITCH_CH_TIME"
@@ -485,4 +603,15 @@
#define CONFIG_RTW_PCI_MSI_DISABLE
#endif
#if defined(CONFIG_PCI_DYNAMIC_ASPM_L1_LATENCY) || \
defined(CONFIG_PCI_DYNAMIC_ASPM_LINK_CTRL)
#define CONFIG_PCI_DYNAMIC_ASPM
#endif
#if 0
/* Debug related compiler flags */
#define DBG_THREAD_PID /* Add thread pid to debug message prefix */
#define DBG_CPU_INFO /* Add CPU info to debug message prefix */
#endif
#endif /* __DRV_CONF_H__ */

231
include/drv_types.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
* Copyright(c) 2007 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -70,10 +70,6 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER;
#include <rtw_vht.h>
#endif
#ifdef CONFIG_INTEL_WIDI
#include <rtw_intel_widi.h>
#endif
#include <rtw_cmd.h>
#include <cmd_osdep.h>
#include <rtw_security.h>
@@ -102,7 +98,6 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER;
#include <rtw_ioctl.h>
#include <rtw_ioctl_set.h>
#include <rtw_ioctl_query.h>
#include <rtw_ioctl_rtl.h>
#include <osdep_intf.h>
#include <rtw_eeprom.h>
#include <sta_info.h>
@@ -198,7 +193,17 @@ struct registry_priv {
u8 power_mgnt;
u8 ips_mode;
u8 lps_level;
#ifdef CONFIG_LPS_1T1R
u8 lps_1t1r;
#endif
u8 lps_chk_by_tp;
#ifdef CONFIG_WOWLAN
u8 wow_power_mgnt;
u8 wow_lps_level;
#ifdef CONFIG_LPS_1T1R
u8 wow_lps_1t1r;
#endif
#endif /* CONFIG_WOWLAN */
u8 smart_ps;
#ifdef CONFIG_WMMPS_STA
u8 wmm_smart_ps;
@@ -219,6 +224,9 @@ struct registry_priv {
u8 software_decrypt;
#ifdef CONFIG_TX_EARLY_MODE
u8 early_mode;
#endif
#ifdef CONFIG_NARROWBAND_SUPPORTING
u8 rtw_nb_config;
#endif
u8 acm_method;
/* WMM */
@@ -232,6 +240,11 @@ struct registry_priv {
WLAN_BSSID_EX dev_network;
#if CONFIG_TX_AC_LIFETIME
u8 tx_aclt_flags;
struct tx_aclt_conf_t tx_aclt_confs[TX_ACLT_CONF_NUM];
#endif
u8 tx_bw_mode;
#ifdef CONFIG_AP_MODE
u8 bmc_tx_rate;
@@ -257,6 +270,12 @@ struct registry_priv {
u8 ldpc_cap;
/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */
u8 stbc_cap;
#if defined(CONFIG_RTW_TX_NPATH_EN)
u8 tx_npath;
#endif
#if defined(CONFIG_RTW_PATH_DIV)
u8 path_div;
#endif
/*
* BIT0: Enable VHT SU Beamformer
* BIT1: Enable VHT SU Beamformee
@@ -278,11 +297,14 @@ struct registry_priv {
u8 lowrate_two_xmit;
u8 rf_config ;
u8 low_power ;
u8 wifi_spec;/* !turbo_mode */
u8 special_rf_path; /* 0: 2T2R ,1: only turn on path A 1T1R */
u8 rf_path; /*rf_config*/
u8 tx_nss;
u8 rx_nss;
char alpha2[2];
u8 channel_plan;
u8 excl_chs[MAX_CHANNEL_NUM];
@@ -335,14 +357,14 @@ struct registry_priv {
u8 pll_ref_clk_sel;
/* define for tx power adjust */
#ifdef CONFIG_TXPWR_LIMIT
#if CONFIG_TXPWR_LIMIT
u8 RegEnableTxPowerLimit;
#endif
u8 RegEnableTxPowerByRate;
u8 target_tx_pwr_valid;
s8 target_tx_pwr_2g[RF_PATH_MAX][RATE_SECTION_NUM];
#ifdef CONFIG_IEEE80211_BAND_5GHZ
#if CONFIG_IEEE80211_BAND_5GHZ
s8 target_tx_pwr_5g[RF_PATH_MAX][RATE_SECTION_NUM - 1];
#endif
@@ -366,6 +388,9 @@ struct registry_priv {
#endif
#ifdef CONFIG_CONCURRENT_MODE
u8 virtual_iface_num;
#ifdef CONFIG_P2P
u8 sel_p2p_iface;
#endif
#endif
u8 qos_opt_enable;
@@ -377,6 +402,7 @@ struct registry_priv {
u8 boffefusemask;
BOOLEAN bFileMaskEfuse;
BOOLEAN bBTFileMaskEfuse;
#ifdef CONFIG_RTW_ACS
u8 acs_auto_scan;
u8 acs_mode;
@@ -406,6 +432,7 @@ struct registry_priv {
s8 rtw_mcc_policy_table_idx;
u8 rtw_mcc_duration;
u8 rtw_mcc_enable_runtime_duration;
u8 rtw_mcc_phydm_offload;
#endif /* CONFIG_MCC_MODE */
#ifdef CONFIG_RTW_NAPI
@@ -428,7 +455,11 @@ struct registry_priv {
#endif
u8 check_hw_status;
u8 wowlan_sta_mix_mode;
#ifdef CONFIG_PCI_HCI
u32 pci_aspm_config;
u32 pci_dynamic_aspm_linkctrl;
#endif
u8 iqk_fw_offload;
u8 ch_switch_offload;
@@ -458,10 +489,27 @@ struct registry_priv {
#ifdef DBG_LA_MODE
u8 la_mode_en;
#endif
u32 phydm_ability;
u32 halrf_ability;
#ifdef CONFIG_TDMADIG
u8 tdmadig_en;
u8 tdmadig_mode;
u8 tdmadig_dynamic;
#endif/*CONFIG_TDMADIG*/
#ifdef CONFIG_RTW_MESH
u8 peer_alive_based_preq;
#endif
/*
* vht_2g4: use VHT rate on 2.4G or not
* 0: deny
* 1: allow
*/
u8 vht_2g4;
};
/* For registry parameters */
#define RGTRY_OFT(field) ((ULONG)FIELD_OFFSET(struct registry_priv, field))
#define RGTRY_OFT(field) ((u32)FIELD_OFFSET(struct registry_priv, field))
#define RGTRY_SZ(field) sizeof(((struct registry_priv *) 0)->field)
#define GetRegAmplifierType2G(_Adapter) (_Adapter->registrypriv.AmplifierType_2G)
@@ -476,7 +524,7 @@ struct registry_priv {
#define GetRegPowerTrackingType(_Adapter) (_Adapter->registrypriv.PowerTracking_Type)
#define WOWLAN_IS_STA_MIX_MODE(_Adapter) (_Adapter->registrypriv.wowlan_sta_mix_mode)
#define BSSID_OFT(field) ((ULONG)FIELD_OFFSET(WLAN_BSSID_EX, field))
#define BSSID_OFT(field) ((u32)FIELD_OFFSET(WLAN_BSSID_EX, field))
#define BSSID_SZ(field) sizeof(((PWLAN_BSSID_EX) 0)->field)
#define BW_MODE_2G(bw_mode) ((bw_mode) & 0x0F)
@@ -494,6 +542,10 @@ struct registry_priv {
#define REGSTY_IS_11AC_ENABLE(regsty) ((regsty)->vht_enable != 0)
#define REGSTY_IS_11AC_AUTO(regsty) ((regsty)->vht_enable == 2)
#define rtw_is_vht_2g4(adapter) ((adapter)->registrypriv.vht_2g4 != 0)
#define rtw_set_vht_2g4(adapter, enable) \
((adapter)->registrypriv.vht_2g4 = (enable ? 1 : 0))
typedef struct rtw_if_operations {
int __must_check (*read)(struct dvobj_priv *d, unsigned int addr, void *buf,
size_t len, bool fixed);
@@ -512,14 +564,14 @@ typedef struct rtw_if_operations {
#include <drv_types_pci.h>
#endif
#define get_hw_port(adapter) (adapter->hw_port)
#ifdef CONFIG_CONCURRENT_MODE
#define is_primary_adapter(adapter) (adapter->adapter_type == PRIMARY_ADAPTER)
#define is_vir_adapter(adapter) (adapter->adapter_type == VIRTUAL_ADAPTER)
#define get_hw_port(adapter) (adapter->hw_port)
#else
#define is_primary_adapter(adapter) (1)
#define is_vir_adapter(adapter) (0)
#define get_hw_port(adapter) (HW_PORT0)
#endif
#define GET_PRIMARY_ADAPTER(padapter) (((_adapter *)padapter)->dvobj->padapters[IFACE_ID0])
#define GET_IFACE_NUMS(padapter) (((_adapter *)padapter)->dvobj->iface_nums)
@@ -799,10 +851,15 @@ struct macid_ctl_t {
u8 vht_en[MACID_NUM_SW_LIMIT];
u32 rate_bmp0[MACID_NUM_SW_LIMIT];
u32 rate_bmp1[MACID_NUM_SW_LIMIT];
u8 op_num[H2C_MSR_ROLE_MAX]; /* number of macid having h2c_msr's OPMODE = 1 for specific ROLE */
struct sta_info *sta[MACID_NUM_SW_LIMIT]; /* corresponding stainfo when macid is not shared */
/* macid sleep registers */
#ifdef CONFIG_PROTSEL_MACSLEEP
u16 reg_sleep_ctrl;
u16 reg_sleep_info;
#else
u16 reg_sleep_m0;
#if (MACID_NUM_SW_LIMIT > 32)
u16 reg_sleep_m1;
@@ -813,6 +870,7 @@ struct macid_ctl_t {
#if (MACID_NUM_SW_LIMIT > 96)
u16 reg_sleep_m3;
#endif
#endif
};
/* used for rf_ctl_t.rate_bmp_cck_ofdm */
@@ -838,15 +896,18 @@ struct macid_ctl_t {
#define RATE_BMP_GET_HT_4SS(_bmp_ht) ((_bmp_ht & RATE_BMP_HT_4SS) >> 24)
/* used for rf_ctl_t.rate_bmp_vht_by_bw */
#define RATE_BMP_VHT_1SS 0x000003FF
#define RATE_BMP_VHT_2SS 0x000FFC00
#define RATE_BMP_VHT_3SS 0x3FF00000
#define RATE_BMP_VHT_1SS 0x00000003FF
#define RATE_BMP_VHT_2SS 0x00000FFC00
#define RATE_BMP_VHT_3SS 0x003FF00000
#define RATE_BMP_VHT_4SS 0xFFC0000000
#define RATE_BMP_HAS_VHT_1SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_1SS)
#define RATE_BMP_HAS_VHT_2SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_2SS)
#define RATE_BMP_HAS_VHT_3SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_3SS)
#define RATE_BMP_GET_VHT_1SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_1SS)
#define RATE_BMP_GET_VHT_2SS(_bmp_vht) ((_bmp_vht & RATE_BMP_VHT_2SS) >> 10)
#define RATE_BMP_GET_VHT_3SS(_bmp_vht) ((_bmp_vht & RATE_BMP_VHT_3SS) >> 20)
#define RATE_BMP_HAS_VHT_4SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_4SS)
#define RATE_BMP_GET_VHT_1SS(_bmp_vht) ((u16)(_bmp_vht & RATE_BMP_VHT_1SS))
#define RATE_BMP_GET_VHT_2SS(_bmp_vht) ((u16)((_bmp_vht & RATE_BMP_VHT_2SS) >> 10))
#define RATE_BMP_GET_VHT_3SS(_bmp_vht) ((u16)((_bmp_vht & RATE_BMP_VHT_3SS) >> 20))
#define RATE_BMP_GET_VHT_4SS(_bmp_vht) ((u16)((_bmp_vht & RATE_BMP_VHT_4SS) >> 30))
#define TXPWR_LMT_REF_VHT_FROM_HT BIT0
#define TXPWR_LMT_REF_HT_FROM_VHT BIT1
@@ -878,13 +939,12 @@ struct rf_ctl_t {
/* used for debug or by tx power limit */
u16 rate_bmp_cck_ofdm; /* 20MHz */
u32 rate_bmp_ht_by_bw[2]; /* 20MHz, 40MHz. 4SS supported */
u32 rate_bmp_vht_by_bw[4]; /* 20MHz, 40MHz, 80MHz, 160MHz. up to 3SS supported */
u64 rate_bmp_vht_by_bw[4]; /* 20MHz, 40MHz, 80MHz, 160MHz. 4SS supported */
/* used by tx power limit */
#if CONFIG_TXPWR_LIMIT
u8 highest_ht_rate_bw_bmp;
u8 highest_vht_rate_bw_bmp;
#ifdef CONFIG_TXPWR_LIMIT
_mutex txpwr_lmt_mutex;
_list reg_exc_list;
u8 regd_exc_num;
@@ -893,18 +953,19 @@ struct rf_ctl_t {
const char *regd_name;
u8 txpwr_lmt_2g_cck_ofdm_state;
#ifdef CONFIG_IEEE80211_BAND_5GHZ
#if CONFIG_IEEE80211_BAND_5GHZ
u8 txpwr_lmt_5g_cck_ofdm_state;
u8 txpwr_lmt_5g_20_40_ref;
#endif
#endif
u8 ch_sel_same_band_prefer;
bool ch_sel_within_same_band;
#ifdef CONFIG_DFS
#if CONFIG_DFS
u8 csa_ch;
#ifdef CONFIG_DFS_MASTER
u8 dfs_region_domain;
_timer radar_detect_timer;
bool radar_detect_by_others;
u8 radar_detect_enabled;
@@ -918,7 +979,7 @@ struct rf_ctl_t {
systime cac_end_time;
u8 cac_force_stop;
#ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
#if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
u8 dfs_slave_with_rd;
#endif
u8 dfs_ch_sel_d_flags;
@@ -943,7 +1004,7 @@ struct rf_ctl_t {
#define IS_RADAR_DETECTED(rfctl) 0
#endif /* CONFIG_DFS_MASTER */
#ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
#if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
#define IS_DFS_SLAVE_WITH_RD(rfctl) ((rfctl)->dfs_slave_with_rd)
#else
#define IS_DFS_SLAVE_WITH_RD(rfctl) 0
@@ -1002,6 +1063,24 @@ struct tsf_info {
};
#endif
struct protsel {
_mutex mutex; /* protect this structure */
ATOMIC_T refcnt; /* reference count */
u32 sel; /* save the last sel port */
};
#ifdef CONFIG_RTL8814B
#define MAX_BULKOUT_NUM 7
#ifdef CONFIG_USB_HCI
#define MAX_ENDPOINT_NUM 8
#endif
#else
#define MAX_BULKOUT_NUM 4
#ifdef CONFIG_USB_HCI
#define MAX_ENDPOINT_NUM 6
#endif
#endif
struct dvobj_priv {
/*-------- below is common data --------*/
u8 chip_type;
@@ -1018,6 +1097,8 @@ struct dvobj_priv {
_mutex hw_init_mutex;
_mutex h2c_fwcmd_mutex;
_mutex ioctrl_mutex;
#ifdef CONFIG_RTW_CUSTOMER_STR
_mutex customer_str_mutex;
struct submit_ctx *customer_str_sctx;
@@ -1079,13 +1160,15 @@ struct dvobj_priv {
struct rf_ctl_t rf_ctl;
/* For 92D, DMDP have 2 interface. */
u8 InterfaceNumber;
u8 NumInterfaces;
#if CONFIG_TX_AC_LIFETIME
struct tx_aclt_conf_t tx_aclt_force_val;
u8 tx_aclt_flags;
struct tx_aclt_conf_t tx_aclt_confs[TX_ACLT_CONF_NUM];
#endif
/* In /Out Pipe information */
int RtInPipe[2];
int RtOutPipe[4];
int RtOutPipe[MAX_BULKOUT_NUM];
u8 Queue2Pipe[HW_QUEUE_ENTRY];/* for out pipe mapping */
u8 irq_alloc;
@@ -1148,7 +1231,7 @@ struct dvobj_priv {
u8 nr_endpoint;
u8 RtNumInPipes;
u8 RtNumOutPipes;
int ep_num[6]; /* endpoint number */
int ep_num[MAX_ENDPOINT_NUM]; /* endpoint number */
int RegUsbSS;
@@ -1163,31 +1246,6 @@ struct dvobj_priv {
u8 *usb_vendor_req_buf;
#endif
#ifdef PLATFORM_WINDOWS
/* related device objects */
PDEVICE_OBJECT pphysdevobj;/* pPhysDevObj; */
PDEVICE_OBJECT pfuncdevobj;/* pFuncDevObj; */
PDEVICE_OBJECT pnextdevobj;/* pNextDevObj; */
u8 nextdevstacksz;/* unsigned char NextDeviceStackSize; */ /* = (CHAR)CEdevice->pUsbDevObj->StackSize + 1; */
/* urb for control diescriptor request */
#ifdef PLATFORM_OS_XP
struct _URB_CONTROL_DESCRIPTOR_REQUEST descriptor_urb;
PUSB_CONFIGURATION_DESCRIPTOR pconfig_descriptor;/* UsbConfigurationDescriptor; */
#endif
#ifdef PLATFORM_OS_CE
WCHAR active_path[MAX_ACTIVE_REG_PATH]; /* adapter regpath */
USB_EXTENSION usb_extension;
_nic_hdl pipehdls_r8192c[0x10];
#endif
u32 config_descriptor_len;/* ULONG UsbConfigurationDescriptorLength; */
#endif/* PLATFORM_WINDOWS */
#ifdef PLATFORM_LINUX
struct usb_interface *pusbintf;
struct usb_device *pusbdev;
@@ -1234,17 +1292,6 @@ struct dvobj_priv {
RT_ISR_CONTENT isr_content;
_lock irq_th_lock;
/* ASPM */
u8 const_pci_aspm;
u8 const_amdpci_aspm;
u8 const_hwsw_rfoff_d3;
u8 const_support_pciaspm;
/* pci-e bridge */
u8 const_hostpci_aspm_setting;
/* pci-e device */
u8 const_devicepci_aspm_setting;
u8 b_support_aspm; /* If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00. */
u8 b_support_backdoor;
u8 bdma64;
#endif/* PLATFORM_LINUX */
@@ -1262,6 +1309,16 @@ struct dvobj_priv {
/* also for RTK T/P Testing Mode */
u8 scan_deny;
/* protect sel to safely access */
#ifdef CONFIG_PROTSEL_PORT
struct protsel protsel_port;
#endif
#ifdef CONFIG_PROTSEL_ATIMDTIM
struct protsel protsel_atimdtim;
#endif
#ifdef CONFIG_PROTSEL_MACSLEEP
struct protsel protsel_macsleep;
#endif
};
#define DEV_STA_NUM(_dvobj) MSTATE_STA_NUM(&((_dvobj)->iface_state))
@@ -1384,18 +1441,6 @@ enum _NAPI_STATE {
};
#endif
#ifdef CONFIG_INTEL_PROXIM
struct proxim {
bool proxim_support;
bool proxim_on;
void *proximity_priv;
int (*proxim_rx)(_adapter *padapter,
union recv_frame *precv_frame);
u8(*proxim_get_var)(_adapter *padapter, u8 type);
};
#endif /* CONFIG_INTEL_PROXIM */
#ifdef CONFIG_MAC_LOOPBACK_DRIVER
typedef struct loopbackdata {
_sema sema;
@@ -1490,7 +1535,7 @@ struct _ADAPTER {
ERROR_CODE LastError; /* <20130613, Kordan> Only the functions associated with MP records the error code by now. */
PVOID HalData;
void *HalData;
u32 hal_data_sz;
struct hal_ops hal_func;
@@ -1520,25 +1565,10 @@ struct _ADAPTER {
_thread_hdl_ recvThread;
#endif
u8 registered;
#ifndef PLATFORM_LINUX
NDIS_STATUS(*dvobj_init)(struct dvobj_priv *dvobj);
void (*dvobj_deinit)(struct dvobj_priv *dvobj);
#endif
void (*intf_start)(_adapter *adapter);
void (*intf_stop)(_adapter *adapter);
#ifdef PLATFORM_WINDOWS
_nic_hdl hndis_adapter;/* hNdisAdapter(NDISMiniportAdapterHandle); */
_nic_hdl hndis_config;/* hNdisConfiguration; */
NDIS_STRING fw_img;
u32 NdisPacketFilter;
u8 MCList[MAX_MCAST_LIST_NUM][6];
u32 MCAddrCount;
#endif /* end of PLATFORM_WINDOWS */
#ifdef PLATFORM_LINUX
_nic_hdl pnetdev;
char old_ifname[IFNAMSIZ];
@@ -1630,13 +1660,6 @@ struct _ADAPTER {
struct br_ext_info ethBrExtInfo;
#endif /* CONFIG_BR_EXT */
#ifdef CONFIG_INTEL_PROXIM
/* intel Proximity, should be alloc mem
* in intel Proximity module and can only
* be used in intel Proximity mode */
struct proxim proximity;
#endif /* CONFIG_INTEL_PROXIM */
#ifdef CONFIG_MAC_LOOPBACK_DRIVER
PLOOPBACKDATA ploopback;
#endif

228
include/drv_types_pci.h
View File

@@ -15,211 +15,38 @@
#ifndef __DRV_TYPES_PCI_H__
#define __DRV_TYPES_PCI_H__
#ifdef PLATFORM_LINUX
#include <linux/pci.h>
#endif
#define INTEL_VENDOR_ID 0x8086
#define SIS_VENDOR_ID 0x1039
#define ATI_VENDOR_ID 0x1002
#define ATI_DEVICE_ID 0x7914
#define AMD_VENDOR_ID 0x1022
#define PCI_MAX_BRIDGE_NUMBER 255
#define PCI_MAX_DEVICES 32
#define PCI_MAX_FUNCTION 8
#define PCI_CONF_ADDRESS 0x0CF8 /* PCI Configuration Space Address */
#define PCI_CONF_DATA 0x0CFC /* PCI Configuration Space Data */
#define PCI_CLASS_BRIDGE_DEV 0x06
#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10
#define U1DONTCARE 0xFF
#define U2DONTCARE 0xFFFF
#define U4DONTCARE 0xFFFFFFFF
#define PCI_VENDER_ID_REALTEK 0x10ec
#define HAL_HW_PCI_8180_DEVICE_ID 0x8180
#define HAL_HW_PCI_8185_DEVICE_ID 0x8185 /* 8185 or 8185b */
#define HAL_HW_PCI_8188_DEVICE_ID 0x8188 /* 8185b */
#define HAL_HW_PCI_8198_DEVICE_ID 0x8198 /* 8185b */
#define HAL_HW_PCI_8190_DEVICE_ID 0x8190 /* 8190 */
#define HAL_HW_PCI_8723E_DEVICE_ID 0x8723 /* 8723E */
#define HAL_HW_PCI_8192_DEVICE_ID 0x8192 /* 8192 PCI-E */
#define HAL_HW_PCI_8192SE_DEVICE_ID 0x8192 /* 8192 SE */
#define HAL_HW_PCI_8174_DEVICE_ID 0x8174 /* 8192 SE */
#define HAL_HW_PCI_8173_DEVICE_ID 0x8173 /* 8191 SE Crab */
#define HAL_HW_PCI_8172_DEVICE_ID 0x8172 /* 8191 SE RE */
#define HAL_HW_PCI_8171_DEVICE_ID 0x8171 /* 8191 SE Unicron */
#define HAL_HW_PCI_0045_DEVICE_ID 0x0045 /* 8190 PCI for Ceraga */
#define HAL_HW_PCI_0046_DEVICE_ID 0x0046 /* 8190 Cardbus for Ceraga */
#define HAL_HW_PCI_0044_DEVICE_ID 0x0044 /* 8192e PCIE for Ceraga */
#define HAL_HW_PCI_0047_DEVICE_ID 0x0047 /* 8192e Express Card for Ceraga */
#define HAL_HW_PCI_700F_DEVICE_ID 0x700F
#define HAL_HW_PCI_701F_DEVICE_ID 0x701F
#define HAL_HW_PCI_DLINK_DEVICE_ID 0x3304
#define HAL_HW_PCI_8188EE_DEVICE_ID 0x8179
#define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI 0x1000 /* 8190 support 16 pages of IO registers */
#define HAL_HW_PCI_REVISION_ID_8190PCI 0x00
#define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE 0x4000 /* 8192 support 16 pages of IO registers */
#define HAL_HW_PCI_REVISION_ID_8192PCIE 0x01
#define HAL_MEMORY_MAPPED_IO_RANGE_8192SE 0x4000 /* 8192 support 16 pages of IO registers */
#define HAL_HW_PCI_REVISION_ID_8192SE 0x10
#define HAL_HW_PCI_REVISION_ID_8192CE 0x1
#define HAL_MEMORY_MAPPED_IO_RANGE_8192CE 0x4000 /* 8192 support 16 pages of IO registers */
#define HAL_HW_PCI_REVISION_ID_8192DE 0x0
#define HAL_MEMORY_MAPPED_IO_RANGE_8192DE 0x4000 /* 8192 support 16 pages of IO registers */
enum pci_bridge_vendor {
PCI_BRIDGE_VENDOR_INTEL = 0x0,/* 0b'0000,0001 */
PCI_BRIDGE_VENDOR_ATI, /* = 0x02, */ /* 0b'0000,0010 */
PCI_BRIDGE_VENDOR_AMD, /* = 0x04, */ /* 0b'0000,0100 */
PCI_BRIDGE_VENDOR_SIS ,/* = 0x08, */ /* 0b'0000,1000 */
PCI_BRIDGE_VENDOR_UNKNOWN, /* = 0x40, */ /* 0b'0100,0000 */
PCI_BRIDGE_VENDOR_MAX ,/* = 0x80 */
} ;
/* copy this data structor defination from MSDN SDK */
typedef struct _PCI_COMMON_CONFIG {
u16 VendorID;
u16 DeviceID;
u16 Command;
u16 Status;
u8 RevisionID;
u8 ProgIf;
u8 SubClass;
u8 BaseClass;
u8 CacheLineSize;
u8 LatencyTimer;
u8 HeaderType;
u8 BIST;
union {
struct _PCI_HEADER_TYPE_0 {
u32 BaseAddresses[6];
u32 CIS;
u16 SubVendorID;
u16 SubSystemID;
u32 ROMBaseAddress;
u8 CapabilitiesPtr;
u8 Reserved1[3];
u32 Reserved2;
u8 InterruptLine;
u8 InterruptPin;
u8 MinimumGrant;
u8 MaximumLatency;
} type0;
#if 0
struct _PCI_HEADER_TYPE_1 {
ULONG BaseAddresses[PCI_TYPE1_ADDRESSES];
UCHAR PrimaryBusNumber;
UCHAR SecondaryBusNumber;
UCHAR SubordinateBusNumber;
UCHAR SecondaryLatencyTimer;
UCHAR IOBase;
UCHAR IOLimit;
USHORT SecondaryStatus;
USHORT MemoryBase;
USHORT MemoryLimit;
USHORT PrefetchableMemoryBase;
USHORT PrefetchableMemoryLimit;
ULONG PrefetchableMemoryBaseUpper32;
ULONG PrefetchableMemoryLimitUpper32;
USHORT IOBaseUpper;
USHORT IOLimitUpper;
ULONG Reserved2;
ULONG ExpansionROMBase;
UCHAR InterruptLine;
UCHAR InterruptPin;
USHORT BridgeControl;
} type1;
struct _PCI_HEADER_TYPE_2 {
ULONG BaseAddress;
UCHAR CapabilitiesPtr;
UCHAR Reserved2;
USHORT SecondaryStatus;
UCHAR PrimaryBusNumber;
UCHAR CardbusBusNumber;
UCHAR SubordinateBusNumber;
UCHAR CardbusLatencyTimer;
ULONG MemoryBase0;
ULONG MemoryLimit0;
ULONG MemoryBase1;
ULONG MemoryLimit1;
USHORT IOBase0_LO;
USHORT IOBase0_HI;
USHORT IOLimit0_LO;
USHORT IOLimit0_HI;
USHORT IOBase1_LO;
USHORT IOBase1_HI;
USHORT IOLimit1_LO;
USHORT IOLimit1_HI;
UCHAR InterruptLine;
UCHAR InterruptPin;
USHORT BridgeControl;
USHORT SubVendorID;
USHORT SubSystemID;
ULONG LegacyBaseAddress;
UCHAR Reserved3[56];
ULONG SystemControl;
UCHAR MultiMediaControl;
UCHAR GeneralStatus;
UCHAR Reserved4[2];
UCHAR GPIO0Control;
UCHAR GPIO1Control;
UCHAR GPIO2Control;
UCHAR GPIO3Control;
ULONG IRQMuxRouting;
UCHAR RetryStatus;
UCHAR CardControl;
UCHAR DeviceControl;
UCHAR Diagnostic;
} type2;
#endif
} u;
u8 DeviceSpecific[108];
} PCI_COMMON_CONFIG , *PPCI_COMMON_CONFIG;
typedef struct _RT_PCI_CAPABILITIES_HEADER {
u8 CapabilityID;
u8 Next;
} RT_PCI_CAPABILITIES_HEADER, *PRT_PCI_CAPABILITIES_HEADER;
enum aspm_mode {
ASPM_MODE_UND,
ASPM_MODE_PERF,
ASPM_MODE_PS,
ASPM_MODE_DEF,
};
struct pci_priv {
BOOLEAN pci_clk_req;
u8 pciehdr_offset;
/* PCIeCap is only differece between B-cut and C-cut. */
/* Configuration Space offset 72[7:4] */
/* 0: A/B cut */
/* 1: C cut and later. */
u8 pcie_cap;
u8 linkctrl_reg;
u8 busnumber;
u8 devnumber;
u8 funcnumber;
u8 pcibridge_busnum;
u8 pcibridge_devnum;
u8 pcibridge_funcnum;
u8 pcibridge_vendor;
u16 pcibridge_vendorid;
u16 pcibridge_deviceid;
u8 pcibridge_pciehdr_offset;
u8 pcibridge_linkctrlreg;
u8 amd_l1_patch;
#ifdef CONFIG_PCI_DYNAMIC_ASPM
u8 aspm_mode;
#endif
};
typedef struct _RT_ISR_CONTENT {
@@ -230,37 +57,4 @@ typedef struct _RT_ISR_CONTENT {
};
} RT_ISR_CONTENT, *PRT_ISR_CONTENT;
/* #define RegAddr(addr) (addr + 0xB2000000UL) */
/* some platform macros will def here */
static inline void NdisRawWritePortUlong(u32 port, u32 val)
{
outl(val, port);
/* writel(val, (u8 *)RegAddr(port)); */
}
static inline void NdisRawWritePortUchar(u32 port, u8 val)
{
outb(val, port);
/* writeb(val, (u8 *)RegAddr(port)); */
}
static inline void NdisRawReadPortUchar(u32 port, u8 *pval)
{
*pval = inb(port);
/* *pval = readb((u8 *)RegAddr(port)); */
}
static inline void NdisRawReadPortUshort(u32 port, u16 *pval)
{
*pval = inw(port);
/* *pval = readw((u8 *)RegAddr(port)); */
}
static inline void NdisRawReadPortUlong(u32 port, u32 *pval)
{
*pval = inl(port);
/* *pval = readl((u8 *)RegAddr(port)); */
}
#endif

54
include/drv_types_sdio.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
* Copyright(c) 2007 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -28,15 +28,6 @@
#endif /* CONFIG_PLATFORM_SPRD */
#endif
#ifdef PLATFORM_OS_XP
#include <wdm.h>
#include <ntddsd.h>
#endif
#ifdef PLATFORM_OS_CE
#include <sdcardddk.h>
#endif
#define RTW_SDIO_CLK_33M 33000000
#define RTW_SDIO_CLK_40M 40000000
#define RTW_SDIO_CLK_80M 80000000
@@ -50,6 +41,7 @@ typedef struct sdio_data {
u32 block_transfer_len;
#ifdef PLATFORM_LINUX
struct mmc_card *card;
struct sdio_func *func;
_thread_hdl_ sys_sdio_irq_thd;
unsigned int clock;
@@ -57,22 +49,34 @@ typedef struct sdio_data {
u8 sd3_bus_mode;
#endif
#ifdef PLATFORM_OS_XP
PDEVICE_OBJECT pphysdevobj;
PDEVICE_OBJECT pfuncdevobj;
PDEVICE_OBJECT pnextdevobj;
SDBUS_INTERFACE_STANDARD sdbusinft;
u8 nextdevstacksz;
#endif
#ifdef DBG_SDIO
#ifdef PLATFORM_LINUX
struct proc_dir_entry *proc_sdio_dbg;
#endif /* PLATFORM_LINUX */
#ifdef PLATFORM_OS_CE
SD_DEVICE_HANDLE hDevice;
SD_CARD_RCA sd_rca;
SD_CARD_INTERFACE card_intf;
BOOLEAN enableIsarWithStatus;
WCHAR active_path[MAX_ACTIVE_REG_PATH];
SD_HOST_BLOCK_CAPABILITY sd_host_blk_cap;
#endif
u32 cmd52_err_cnt; /* CMD52 I/O error count */
u32 cmd53_err_cnt; /* CMD53 I/O error count */
#if (DBG_SDIO >= 1)
u32 reg_dump_mark; /* reg dump at specific error count */
#endif /* DBG_SDIO >= 1 */
#if (DBG_SDIO >= 2)
u8 *dbg_msg; /* Messages for debug */
u8 dbg_msg_size;
u8 *reg_mac; /* Device MAC register, 0x0~0x800 */
u8 *reg_mac_ext; /* Device MAC extend register, 0x1000~0x1800 */
u8 *reg_local; /* Device SDIO local register, 0x0~0xFF */
u8 *reg_cia; /* SDIO CIA(CCCR, FBR and etc.), 0x0~0x1FF */
#endif /* DBG_SDIO >= 2 */
#if (DBG_SDIO >= 3)
u8 dbg_enable; /* 0/1: disable/enable debug mode */
u8 err_stop; /* Stop(surprise remove) when I/O error happen */
u8 err_test; /* Simulate error happen */
u8 err_test_triggered; /* Simulate error already triggered */
#endif /* DBG_SDIO >= 3 */
#endif /* DBG_SDIO */
} SDIO_DATA, *PSDIO_DATA;
#define dvobj_to_sdio_func(d) ((d)->intf_data.func)

14
include/ethernet.h
View File

@@ -23,14 +23,14 @@
#define MINIMUM_ETHERNET_PACKET_SIZE 60 /* !< Minimum Ethernet Packet Size */
#define MAXIMUM_ETHERNET_PACKET_SIZE 1514 /* !< Maximum Ethernet Packet Size */
#define RT_ETH_IS_MULTICAST(_pAddr) ((((UCHAR *)(_pAddr))[0]&0x01) != 0) /* !< Is Multicast Address? */
#define RT_ETH_IS_MULTICAST(_pAddr) ((((u8 *)(_pAddr))[0]&0x01) != 0) /* !< Is Multicast Address? */
#define RT_ETH_IS_BROADCAST(_pAddr) (\
((UCHAR *)(_pAddr))[0] == 0xff && \
((UCHAR *)(_pAddr))[1] == 0xff && \
((UCHAR *)(_pAddr))[2] == 0xff && \
((UCHAR *)(_pAddr))[3] == 0xff && \
((UCHAR *)(_pAddr))[4] == 0xff && \
((UCHAR *)(_pAddr))[5] == 0xff) /* !< Is Broadcast Address? */
((u8 *)(_pAddr))[0] == 0xff && \
((u8 *)(_pAddr))[1] == 0xff && \
((u8 *)(_pAddr))[2] == 0xff && \
((u8 *)(_pAddr))[3] == 0xff && \
((u8 *)(_pAddr))[4] == 0xff && \
((u8 *)(_pAddr))[5] == 0xff) /* !< Is Broadcast Address? */
#endif /* #ifndef __INC_ETHERNET_H */

6
include/gspi_osintf.h
View File

@@ -16,10 +16,4 @@
#define __SDIO_OSINTF_H__
#ifdef PLATFORM_OS_CE
extern NDIS_STATUS ce_sd_get_dev_hdl(PADAPTER padapter);
SD_API_STATUS ce_sd_int_callback(SD_DEVICE_HANDLE hDevice, PADAPTER padapter);
extern void sd_setup_irs(PADAPTER padapter);
#endif
#endif

2
include/h2clbk.h
View File

@@ -21,6 +21,6 @@ void _lbk_cmd(PADAPTER Adapter);
void _lbk_rsp(PADAPTER Adapter);
void _lbk_evt(IN PADAPTER Adapter);
void _lbk_evt(PADAPTER Adapter);
void h2c_event_callback(unsigned char *dev, unsigned char *pbuf);

11
include/hal_btcoex.h
View File

@@ -67,6 +67,9 @@ u8 hal_btcoex_IsLpsOn(PADAPTER);
u8 hal_btcoex_RpwmVal(PADAPTER);
u8 hal_btcoex_LpsVal(PADAPTER);
u32 hal_btcoex_GetRaMask(PADAPTER);
u8 hal_btcoex_query_reduced_wl_pwr_lvl(PADAPTER padapter);
void hal_btcoex_set_reduced_wl_pwr_lvl(PADAPTER padapter, u8 val);
void hal_btcoex_do_reduce_wl_pwr_lvl(PADAPTER padapter);
void hal_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen);
void hal_btcoex_DisplayBtCoexInfo(PADAPTER, u8 *pbuf, u32 bufsize);
void hal_btcoex_SetDBG(PADAPTER, u32 *pDbgModule);
@@ -80,7 +83,7 @@ void hal_btcoex_StackUpdateProfileInfo(void);
void hal_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON);
void hal_btcoex_SetAntIsolationType(PADAPTER padapter, u8 anttype);
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
int hal_btcoex_AntIsolationConfig_ParaFile(IN PADAPTER Adapter, IN char *pFileName);
int hal_btcoex_AntIsolationConfig_ParaFile(PADAPTER Adapter, char *pFileName);
int hal_btcoex_ParseAntIsolationConfigFile(PADAPTER Adapter, char *buffer);
#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */
u16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data);
@@ -89,9 +92,15 @@ void hal_btcoex_set_rfe_type(u8 type);
void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type);
void hal_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length);
void hal_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id);
u16 hal_btcoex_btset_testode(PADAPTER padapter, u8 type);
#ifdef CONFIG_RF4CE_COEXIST
void hal_btcoex_set_rf4ce_link_state(u8 state);
u8 hal_btcoex_get_rf4ce_link_state(void);
#endif
#ifdef CONFIG_SDIO_HCI
#include <hal_sdio_coex.h> /* sdio multi coex */
#endif
#endif /* !__HAL_BTCOEX_H__ */

31
include/hal_btcoex_wifionly.h
View File

@@ -19,12 +19,19 @@
#include <hal_data.h>
/* Define the ICs that support wifi only cfg in coex. codes */
#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
#define CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG 1
#else
#define CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG 0
#endif
/* Define the ICs that support hal btc common file structure */
#if defined(CONFIG_RTL8822C) || (defined(CONFIG_RTL8192F) && defined(CONFIG_BT_COEXIST))
#define CONFIG_BTCOEX_SUPPORT_BTC_CMN 1
#else
#define CONFIG_BTCOEX_SUPPORT_BTC_CMN 0
#endif
#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1)
typedef enum _WIFIONLY_CHIP_INTERFACE {
@@ -49,20 +56,20 @@ struct wifi_only_haldata {
};
struct wifi_only_cfg {
PVOID Adapter;
struct wifi_only_haldata haldata_info;
void *Adapter;
struct wifi_only_haldata haldata_info;
WIFIONLY_CHIP_INTERFACE chip_interface;
};
void halwifionly_write1byte(PVOID pwifionlyContext, u32 RegAddr, u8 Data);
void halwifionly_write2byte(PVOID pwifionlyContext, u32 RegAddr, u16 Data);
void halwifionly_write4byte(PVOID pwifionlyContext, u32 RegAddr, u32 Data);
u8 halwifionly_read1byte(PVOID pwifionlyContext, u32 RegAddr);
u16 halwifionly_read2byte(PVOID pwifionlyContext, u32 RegAddr);
u32 halwifionly_read4byte(PVOID pwifionlyContext, u32 RegAddr);
void halwifionly_bitmaskwrite1byte(PVOID pwifionlyContext, u32 regAddr, u8 bitMask, u8 data);
void halwifionly_phy_set_rf_reg(PVOID pwifionlyContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
void halwifionly_phy_set_bb_reg(PVOID pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data);
void halwifionly_write1byte(void *pwifionlyContext, u32 RegAddr, u8 Data);
void halwifionly_write2byte(void *pwifionlyContext, u32 RegAddr, u16 Data);
void halwifionly_write4byte(void *pwifionlyContext, u32 RegAddr, u32 Data);
u8 halwifionly_read1byte(void *pwifionlyContext, u32 RegAddr);
u16 halwifionly_read2byte(void *pwifionlyContext, u32 RegAddr);
u32 halwifionly_read4byte(void *pwifionlyContext, u32 RegAddr);
void halwifionly_bitmaskwrite1byte(void *pwifionlyContext, u32 regAddr, u8 bitMask, u8 data);
void halwifionly_phy_set_rf_reg(void *pwifionlyContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
void halwifionly_phy_set_bb_reg(void *pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data);
void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter);
void hal_btcoex_wifionly_scan_notify(PADAPTER padapter);
void hal_btcoex_wifionly_connect_notify(PADAPTER padapter);

174
include/hal_com.h
View File

@@ -119,6 +119,29 @@
#define DESC_RATEVHTSS4MCS8 0x52
#define DESC_RATEVHTSS4MCS9 0x53
#define IS_CCK_HRATE(_rate) ((_rate) <= DESC_RATE11M)
#define IS_OFDM_HRATE(_rate) ((_rate) >= DESC_RATE6M && (_rate) <= DESC_RATE54M)
#define IS_LEGACY_HRATE(_rate) ((_rate) <= DESC_RATE54M)
#define IS_HT_HRATE(_rate) ((_rate) >= DESC_RATEMCS0 && (_rate) <= DESC_RATEMCS31)
#define IS_VHT_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS1MCS0 && (_rate) <= DESC_RATEVHTSS4MCS9)
#define IS_HT1SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS0 && (_rate) <= DESC_RATEMCS7)
#define IS_HT2SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS8 && (_rate) <= DESC_RATEMCS15)
#define IS_HT3SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS16 && (_rate) <= DESC_RATEMCS23)
#define IS_HT4SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS24 && (_rate) <= DESC_RATEMCS31)
#define IS_VHT1SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS1MCS0 && (_rate) <= DESC_RATEVHTSS1MCS9)
#define IS_VHT2SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS2MCS0 && (_rate) <= DESC_RATEVHTSS2MCS9)
#define IS_VHT3SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS3MCS0 && (_rate) <= DESC_RATEVHTSS3MCS9)
#define IS_VHT4SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS4MCS0 && (_rate) <= DESC_RATEVHTSS4MCS9)
#define IS_1SS_HRATE(_rate) (IS_CCK_HRATE((_rate)) || IS_OFDM_HRATE((_rate)) || IS_HT1SS_HRATE((_rate)) || IS_VHT1SS_HRATE((_rate)))
#define IS_2SS_HRATE(_rate) (IS_HT2SS_HRATE((_rate)) || IS_VHT2SS_HRATE((_rate)))
#define IS_3SS_HRATE(_rate) (IS_HT3SS_HRATE((_rate)) || IS_VHT3SS_HRATE((_rate)))
#define IS_4SS_HRATE(_rate) (IS_HT4SS_HRATE((_rate)) || IS_VHT4SS_HRATE((_rate)))
#define HRARE_SS_NUM(_rate) (IS_1SS_HRATE(_rate) ? 1 : (IS_2SS_HRATE(_rate) ? 2 : (IS_3SS_HRATE(_rate) ? 3 : (IS_4SS_HRATE(_rate) ? 4 : 0))))
#define HDATA_RATE(rate)\
(rate == DESC_RATE1M) ? "CCK_1M" :\
(rate == DESC_RATE2M) ? "CCK_2M" :\
@@ -156,6 +179,14 @@
(rate == DESC_RATEMCS21) ? "MCS21" :\
(rate == DESC_RATEMCS22) ? "MCS22" :\
(rate == DESC_RATEMCS23) ? "MCS23" :\
(rate == DESC_RATEMCS24) ? "MCS24" :\
(rate == DESC_RATEMCS25) ? "MCS25" :\
(rate == DESC_RATEMCS26) ? "MCS26" :\
(rate == DESC_RATEMCS27) ? "MCS27" :\
(rate == DESC_RATEMCS28) ? "MCS28" :\
(rate == DESC_RATEMCS29) ? "MCS29" :\
(rate == DESC_RATEMCS30) ? "MCS30" :\
(rate == DESC_RATEMCS31) ? "MCS31" :\
(rate == DESC_RATEVHTSS1MCS0) ? "VHTSS1MCS0" :\
(rate == DESC_RATEVHTSS1MCS1) ? "VHTSS1MCS1" :\
(rate == DESC_RATEVHTSS1MCS2) ? "VHTSS1MCS2" :\
@@ -185,7 +216,18 @@
(rate == DESC_RATEVHTSS3MCS6) ? "VHTSS3MCS6" :\
(rate == DESC_RATEVHTSS3MCS7) ? "VHTSS3MCS7" :\
(rate == DESC_RATEVHTSS3MCS8) ? "VHTSS3MCS8" :\
(rate == DESC_RATEVHTSS3MCS9) ? "VHTSS3MCS9" : "UNKNOWN"
(rate == DESC_RATEVHTSS3MCS9) ? "VHTSS3MCS9" :\
(rate == DESC_RATEVHTSS4MCS0) ? "VHTSS4MCS0" :\
(rate == DESC_RATEVHTSS4MCS1) ? "VHTSS4MCS1" :\
(rate == DESC_RATEVHTSS4MCS2) ? "VHTSS4MCS2" :\
(rate == DESC_RATEVHTSS4MCS3) ? "VHTSS4MCS3" :\
(rate == DESC_RATEVHTSS4MCS4) ? "VHTSS4MCS4" :\
(rate == DESC_RATEVHTSS4MCS5) ? "VHTSS4MCS5" :\
(rate == DESC_RATEVHTSS4MCS6) ? "VHTSS4MCS6" :\
(rate == DESC_RATEVHTSS4MCS7) ? "VHTSS4MCS7" :\
(rate == DESC_RATEVHTSS4MCS8) ? "VHTSS4MCS8" :\
(rate == DESC_RATEVHTSS4MCS9) ? "VHTSS4MCS9" :\
"UNKNOWN"
enum {
UP_LINK,
@@ -309,7 +351,6 @@ void rtw_reset_phy_trx_ok_counters(_adapter *padapter);
#endif
void dump_chip_info(HAL_VERSION ChipVersion);
void rtw_hal_config_rftype(PADAPTER padapter);
#define BAND_CAP_2G BIT0
#define BAND_CAP_5G BIT1
@@ -355,13 +396,12 @@ u8 hal_largest_bw(_adapter *adapter, u8 in_bw);
bool hal_chk_wl_func(_adapter *adapter, u8 func);
void hal_com_config_channel_plan(
IN PADAPTER padapter,
IN char *hw_alpha2,
IN u8 hw_chplan,
IN char *sw_alpha2,
IN u8 sw_chplan,
IN u8 def_chplan,
IN BOOLEAN AutoLoadFail
PADAPTER padapter,
char *hw_alpha2,
u8 hw_chplan,
char *sw_alpha2,
u8 sw_chplan,
BOOLEAN AutoLoadFail
);
int hal_config_macaddr(_adapter *adapter, bool autoload_fail);
@@ -372,8 +412,8 @@ void rtw_hal_hw_port_disable(_adapter *adapter);
BOOLEAN
HAL_IsLegalChannel(
IN PADAPTER Adapter,
IN u32 Channel
PADAPTER Adapter,
u32 Channel
);
u8 MRateToHwRate(u8 rate);
@@ -381,14 +421,14 @@ u8 MRateToHwRate(u8 rate);
u8 hw_rate_to_m_rate(u8 rate);
void HalSetBrateCfg(
IN PADAPTER Adapter,
IN u8 *mBratesOS,
OUT u16 *pBrateCfg);
PADAPTER Adapter,
u8 *mBratesOS,
u16 *pBrateCfg);
BOOLEAN
Hal_MappingOutPipe(
IN PADAPTER pAdapter,
IN u8 NumOutPipe
PADAPTER pAdapter,
u8 NumOutPipe
);
void rtw_dump_fw_info(void *sel, _adapter *adapter);
@@ -434,8 +474,30 @@ void rtw_iface_disable_tsf_update(_adapter *adapter);
void rtw_hal_periodic_tsf_update_chk(_adapter *adapter);
void rtw_hal_periodic_tsf_update_end_timer_hdl(void *ctx);
void hw_var_port_switch(_adapter *adapter);
#if CONFIG_TX_AC_LIFETIME
#define TX_ACLT_CONF_DEFAULT 0
#define TX_ACLT_CONF_AP_M2U 1
#define TX_ACLT_CONF_MESH 2
#define TX_ACLT_CONF_NUM 3
extern const char *const _tx_aclt_conf_str[];
#define tx_aclt_conf_str(conf) (((conf) >= TX_ACLT_CONF_NUM) ? _tx_aclt_conf_str[TX_ACLT_CONF_NUM] : _tx_aclt_conf_str[(conf)])
struct tx_aclt_conf_t {
u8 en;
u32 vo_vi;
u32 be_bk;
};
void dump_tx_aclt_force_val(void *sel, struct dvobj_priv *dvobj);
void rtw_hal_set_tx_aclt_force_val(_adapter *adapter, struct tx_aclt_conf_t *input, u8 arg_num);
void dump_tx_aclt_confs(void *sel, struct dvobj_priv *dvobj);
void rtw_hal_set_tx_aclt_conf(_adapter *adapter, u8 conf_idx, struct tx_aclt_conf_t *input, u8 arg_num);
void rtw_hal_update_tx_aclt(_adapter *adapter);
#endif
void hw_var_port_switch(_adapter *adapter);
void rtw_var_set_basic_rate(PADAPTER padapter, u8 *val);
u8 SetHwReg(PADAPTER padapter, u8 variable, u8 *val);
void GetHwReg(PADAPTER padapter, u8 variable, u8 *val);
void rtw_hal_check_rxfifo_full(_adapter *adapter);
@@ -453,42 +515,42 @@ eqNByte(
u32
MapCharToHexDigit(
IN char chTmp
char chTmp
);
BOOLEAN
GetHexValueFromString(
IN char *szStr,
IN OUT u32 *pu4bVal,
IN OUT u32 *pu4bMove
char *szStr,
u32 *pu4bVal,
u32 *pu4bMove
);
BOOLEAN
GetFractionValueFromString(
IN char *szStr,
IN OUT u8 *pInteger,
IN OUT u8 *pFraction,
IN OUT u32 *pu4bMove
char *szStr,
u8 *pInteger,
u8 *pFraction,
u32 *pu4bMove
);
BOOLEAN
IsCommentString(
IN char *szStr
char *szStr
);
BOOLEAN
ParseQualifiedString(
IN char *In,
IN OUT u32 *Start,
OUT char *Out,
IN char LeftQualifier,
IN char RightQualifier
char *In,
u32 *Start,
char *Out,
char LeftQualifier,
char RightQualifier
);
BOOLEAN
GetU1ByteIntegerFromStringInDecimal(
IN char *Str,
IN OUT u8 *pInt
char *Str,
u8 *pInt
);
BOOLEAN
@@ -577,7 +639,6 @@ void update_IOT_info(_adapter *padapter);
#ifdef CONFIG_RTS_FULL_BW
void rtw_set_rts_bw(_adapter *padapter);
#endif/*CONFIG_RTS_FULL_BW*/
void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap);
void ResumeTxBeacon(_adapter *padapter);
void StopTxBeacon(_adapter *padapter);
@@ -614,7 +675,7 @@ enum lps_pg_hdl_id {
LPS_PG_PHYDM_EN,
};
u8 rtw_hal_set_lps_pg_info(_adapter *adapter);
u8 rtw_hal_set_lps_pg_info(_adapter *adapter);
#endif
int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, u32 page_num, u8 *buffer, u32 buffer_size);
@@ -635,13 +696,6 @@ void rtw_wow_pattern_read_cam_ent(_adapter *adapter, u8 id, struct rtl_wow_patt
void rtw_dump_wow_pattern(void *sel, struct rtl_wow_pattern *pwow_pattern, u8 idx);
#endif
#ifdef CONFIG_PNO_SUPPORT
struct pno_ssid;
void rtw_hal_construct_ProbeReq(_adapter *padapter, u8 *pframe,
u32 *pLength, struct pno_ssid *ssid);
#endif
struct rtw_ndp_info {
u8 enable:1;
u8 check_remote_ip:1; /* Need to Check Sender IP or not */
@@ -708,21 +762,45 @@ void rtw_ap_mbid_bcn_en(_adapter *adapter, u8 mbcn_id);
void rtw_ap_mbid_bcn_dis(_adapter *adapter, u8 mbcn_id);
#endif
void rtw_hal_get_rf_path(struct dvobj_priv *d, enum rf_type *type,
void rtw_hal_get_trx_path(struct dvobj_priv *d, enum rf_type *type,
enum bb_path *tx, enum bb_path *rx);
#ifdef CONFIG_BEAMFORMING
#ifdef RTW_BEAMFORMING_VERSION_2
void rtw_hal_beamforming_config_csirate(PADAPTER adapter);
#endif
#endif
#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8812A) ||\
defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8192E) ||\
defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821A)
u8 phy_get_current_tx_num(IN PADAPTER pAdapter, IN u8 Rate);
#endif
u8 phy_get_current_tx_num(PADAPTER pAdapter, u8 Rate);
#ifdef CONFIG_RTL8812A
u8 * rtw_hal_set_8812a_vendor_ie(_adapter *padapter , u8 *pframe ,uint *frlen );
#endif
#ifdef CONFIG_PROTSEL_PORT
void rtw_enter_protsel_port(_adapter *padapter, u8 port_sel);
bool rtw_assert_protsel_port(_adapter *padapter, u32 addr, u8 len);
void rtw_leave_protsel_port(_adapter *padapter);
#else
static inline void rtw_enter_protsel_port(_adapter *padapter, u8 port_sel) {}
static inline bool rtw_assert_protsel_port(_adapter *padapter, u32 addr, u8 len) {return true; }
static inline void rtw_leave_protsel_port(_adapter *padapter) {}
#endif
#ifdef CONFIG_PROTSEL_ATIMDTIM
void rtw_enter_protsel_atimdtim(_adapter *padapter, u8 port_sel);
bool rtw_assert_protsel_atimdtim(_adapter *padapter, u32 addr, u8 len);
void rtw_leave_protsel_atimdtim(_adapter *padapter);
#else
static inline void rtw_enter_protsel_atimdtim(_adapter *padapter, u8 port_sel) {}
static inline bool rtw_assert_protsel_atimdtim(_adapter *padapter, u32 addr, u8 len) {return true; }
static inline void rtw_leave_protsel_atimdtim(_adapter *padapter) {}
#endif
#ifdef CONFIG_PROTSEL_MACSLEEP
void rtw_enter_protsel_macsleep(_adapter *padapter, u8 sel);
bool rtw_assert_protsel_macsleep(_adapter *padapter, u32 addr, u8 len);
void rtw_leave_protsel_macsleep(_adapter *padapter);
#else
static inline void rtw_enter_protsel_macsleep(_adapter *padapter, u8 port_sel) {}
static inline bool rtw_assert_protsel_macsleep(_adapter *padapter, u32 addr, u8 len) {return true; }
static inline void rtw_leave_protsel_macsleep(_adapter *padapter) {}
#endif
#endif /* __HAL_COMMON_H__ */

39
include/hal_com_h2c.h
View File

@@ -110,7 +110,6 @@ enum h2c_cmd {
H2C_AOAC_RSVDPAGE3 = 0x88,
H2C_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
H2C_P2P_OFFLOAD = 0x8B,
H2C_NLO_INFO = 0x8C, /* for 3081 Chip*/
#ifdef CONFIG_FW_HANDLE_TXBCN
H2C_FW_BCN_OFFLOAD = 0xBA,
#endif
@@ -170,7 +169,11 @@ enum h2c_cmd {
#define H2C_MCC_IQK_PARAM_LEN 7
#endif /* CONFIG_MCC_MODE */
#ifdef CONFIG_LPS_PG
#ifdef CONFIG_RTL8822C
#define H2C_LPS_PG_INFO_LEN 4
#else
#define H2C_LPS_PG_INFO_LEN 2
#endif
#define H2C_LPSPG_LEN 16
#endif
#ifdef CONFIG_LPS_POFF
@@ -188,8 +191,6 @@ enum h2c_cmd {
#define H2C_SINGLE_CHANNELSWITCH_V2_LEN 2
#define H2C_NLO_INFO_LEN 2
#define eq_mac_addr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0)
#define cp_mac_addr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5])
#define cpIpAddr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3])
@@ -542,11 +543,6 @@ s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs);
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_PACKET(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SCAN_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SSID_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
/* NLO SCAN offload for 8822B/8814A/8821C */
#define SET_H2CCMD_NLO_FUN_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 1, __Value)
#define SET_H2CCMD_NLO_PS_32K(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 1, 1, __Value)
#define SET_H2CCMD_NLO_LOC_NLO_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#endif /* CONFIG_PNO_SUPPORT */
#ifdef CONFIG_P2P_WOWLAN
@@ -565,7 +561,9 @@ s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs);
#define SET_H2CCMD_LPSPG_MACID_SEARCH_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)/*MACIDSearch_En*/
#define SET_H2CCMD_LPSPG_TXSC_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)/*TXSC_En*/
#define SET_H2CCMD_LPSPG_MU_RATE_TB_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)/*MURateTable_En*/
#define SET_H2CCMD_LPSPG_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)/*Loc_LPS_PG*/
#define SET_H2CCMD_LPSPG_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)/*Loc_LPS_PG*/
#define SET_H2CCMD_LPSPG_DPK_INFO_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)/*Loc_LPS_PG_DPK_info*/
#define SET_H2CCMD_LPSPG_IQK_INFO_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 0, 8, __Value)/*Loc_IQK_result*/
#endif
#ifdef DBG_FW_DEBUG_MSG_PKT
@@ -573,6 +571,14 @@ s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs);
#define SET_H2CCMD_RSVDPAGE_LOC_FW_DBG_MSG_PKT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) /*loc_debug_packet*/
#endif /*DBG_FW_DEBUG_MSG_PKT*/
#ifdef DBG_RSVD_PAGE_CFG
#define RSVD_PAGE_CFG(ops, v1, v2, v3) \
RTW_INFO("=== [RSVD][%s]-NeedPage:%d, TotalPageNum:%d TotalPacketLen:%d ===\n", \
ops, v1, v2, v3)
#else
#define RSVD_PAGE_CFG(ops, v1, v2, v3) do {} while (0)
#endif
/* ---------------------------------------------------------------------------------------------------------
* ------------------------------------------- Structure --------------------------------------------------
* --------------------------------------------------------------------------------------------------------- */
@@ -615,6 +621,21 @@ typedef struct _RSVDPAGE_LOC {
#endif /*DBG_FW_DEBUG_MSG_PKT*/
} RSVDPAGE_LOC, *PRSVDPAGE_LOC;
struct rsvd_page_cache_t {
char *name;
u8 loc;
u8 page_num;
u8 *data;
u32 size;
};
bool rsvd_page_cache_update_all(struct rsvd_page_cache_t *cache, u8 loc
, u8 txdesc_len, u32 page_size, u8 *info, u32 info_len);
bool rsvd_page_cache_update_data(struct rsvd_page_cache_t *cache, u8 *info
, u32 info_len);
void rsvd_page_cache_free_data(struct rsvd_page_cache_t *cache);
void rsvd_page_cache_free(struct rsvd_page_cache_t *cache);
#endif
void dump_TX_FIFO(PADAPTER padapter, u8 page_num, u16 page_size);
u8 rtw_hal_set_fw_media_status_cmd(_adapter *adapter, u8 mstatus, u8 macid);

22
include/hal_com_led.h
View File

@@ -199,15 +199,15 @@ typedef struct _LED_PCIE {
typedef struct _LED_PCIE LED_DATA, *PLED_DATA;
typedef enum _LED_STRATEGY_PCIE LED_STRATEGY, *PLED_STRATEGY;
VOID
void
LedControlPCIE(
IN PADAPTER Adapter,
IN LED_CTL_MODE LedAction
PADAPTER Adapter,
LED_CTL_MODE LedAction
);
VOID
void
gen_RefreshLedState(
IN PADAPTER Adapter);
PADAPTER Adapter);
/* ********************************************************************************
* USB LED Definition.
@@ -274,10 +274,10 @@ typedef struct _LED_USB {
typedef struct _LED_USB LED_DATA, *PLED_DATA;
typedef enum _LED_STRATEGY_USB LED_STRATEGY, *PLED_STRATEGY;
#ifdef CONFIG_RTW_SW_LED
VOID
void
LedControlUSB(
IN PADAPTER Adapter,
IN LED_CTL_MODE LedAction
PADAPTER Adapter,
LED_CTL_MODE LedAction
);
#endif
@@ -336,10 +336,10 @@ typedef struct _LED_SDIO {
typedef struct _LED_SDIO LED_DATA, *PLED_DATA;
typedef enum _LED_STRATEGY_SDIO LED_STRATEGY, *PLED_STRATEGY;
VOID
void
LedControlSDIO(
IN PADAPTER Adapter,
IN LED_CTL_MODE LedAction
PADAPTER Adapter,
LED_CTL_MODE LedAction
);
#endif

271
include/hal_com_phycfg.h
View File

@@ -15,6 +15,10 @@
#ifndef __HAL_COM_PHYCFG_H__
#define __HAL_COM_PHYCFG_H__
#ifndef DBG_TX_POWER_IDX
#define DBG_TX_POWER_IDX 0
#endif
#define PathA 0x0 /* Useless */
#define PathB 0x1
#define PathC 0x2
@@ -29,6 +33,12 @@ typedef enum _RF_TX_NUM {
RF_TX_NUM_NONIMPLEMENT,
} RF_TX_NUM;
enum txpwr_pg_mode {
TXPWR_PG_WITH_PWR_IDX,
TXPWR_PG_WITH_TSSI_OFFSET,
TXPWR_PG_UNKNOWN, /* keep last */
};
/*------------------------------Define structure----------------------------*/
typedef struct _BB_REGISTER_DEFINITION {
u32 rfintfs; /* set software control: */
@@ -55,136 +65,153 @@ typedef struct _BB_REGISTER_DEFINITION {
/* ---------------------------------------------------------------------- */
u8
PHY_GetTxPowerByRateBase(
IN PADAPTER Adapter,
IN u8 Band,
IN u8 RfPath,
IN RATE_SECTION RateSection
extern const char *const _txpwr_pg_mode_str[];
#define txpwr_pg_mode_str(_mode) (((_mode) >= TXPWR_PG_UNKNOWN) ? _txpwr_pg_mode_str[TXPWR_PG_UNKNOWN] : _txpwr_pg_mode_str[(_mode)])
u8 phy_get_target_txpwr(
PADAPTER Adapter,
u8 Band,
u8 RfPath,
RATE_SECTION RateSection
);
VOID
void
PHY_GetRateValuesOfTxPowerByRate(
IN PADAPTER pAdapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Value,
OUT u8 *Rate,
OUT s8 *PwrByRateVal,
OUT u8 *RateNum
PADAPTER pAdapter,
u32 RegAddr,
u32 BitMask,
u32 Value,
u8 *Rate,
s8 *PwrByRateVal,
u8 *RateNum
);
u8
PHY_GetRateIndexOfTxPowerByRate(
IN u8 Rate
u8 Rate
);
VOID
void
phy_set_tx_power_index_by_rate_section(
IN PADAPTER pAdapter,
IN enum rf_path RFPath,
IN u8 Channel,
IN u8 RateSection
PADAPTER pAdapter,
enum rf_path RFPath,
u8 Channel,
u8 RateSection
);
s8
_PHY_GetTxPowerByRate(
IN PADAPTER pAdapter,
IN u8 Band,
IN enum rf_path RFPath,
IN u8 RateIndex
PADAPTER pAdapter,
u8 Band,
enum rf_path RFPath,
u8 RateIndex
);
s8
PHY_GetTxPowerByRate(
IN PADAPTER pAdapter,
IN u8 Band,
IN enum rf_path RFPath,
IN u8 RateIndex
PADAPTER pAdapter,
u8 Band,
enum rf_path RFPath,
RATE_SECTION rs,
enum MGN_RATE rate
);
VOID
void
PHY_SetTxPowerByRate(
IN PADAPTER pAdapter,
IN u8 Band,
IN enum rf_path RFPath,
IN u8 Rate,
IN s8 Value
PADAPTER pAdapter,
u8 Band,
enum rf_path RFPath,
u8 Rate,
s8 Value
);
VOID
void
phy_set_tx_power_level_by_path(
IN PADAPTER Adapter,
IN u8 channel,
IN u8 path
PADAPTER Adapter,
u8 channel,
u8 path
);
VOID
PHY_SetTxPowerIndexByRateArray(
IN PADAPTER pAdapter,
IN enum rf_path RFPath,
IN enum channel_width BandWidth,
IN u8 Channel,
IN u8 *Rates,
IN u8 RateArraySize
);
VOID
void
PHY_InitTxPowerByRate(
IN PADAPTER pAdapter
PADAPTER pAdapter
);
VOID
void
phy_store_tx_power_by_rate(
IN PADAPTER pAdapter,
IN u32 Band,
IN u32 RfPath,
IN u32 TxNum,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
PADAPTER pAdapter,
u32 Band,
u32 RfPath,
u32 TxNum,
u32 RegAddr,
u32 BitMask,
u32 Data
);
VOID
void
PHY_TxPowerByRateConfiguration(
IN PADAPTER pAdapter
PADAPTER pAdapter
);
u8
PHY_GetTxPowerIndexBase(
IN PADAPTER pAdapter,
IN enum rf_path RFPath,
IN u8 Rate,
u8 ntx_idx,
IN enum channel_width BandWidth,
IN u8 Channel,
OUT PBOOLEAN bIn24G
);
bool phy_chk_ch_setting_consistency(_adapter *adapter, u8 ch);
#ifdef CONFIG_TXPWR_LIMIT
s8 phy_get_txpwr_lmt_abs(_adapter *adapter
#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
u8 phy_get_pg_txpwr_idx(_adapter *pAdapter
, enum rf_path RFPath, RATE_SECTION rs, u8 ntx_idx
, enum channel_width BandWidth, u8 band, u8 Channel);
#endif
#if CONFIG_TXPWR_LIMIT
s8 phy_get_txpwr_lmt(_adapter *adapter
, const char *regd_name
, BAND_TYPE band, enum channel_width bw
, u8 tlrs, u8 ntx_idx, u8 cch, u8 lock
);
s8 phy_get_txpwr_lmt(_adapter *adapter
s8 phy_get_txpwr_lmt_diff(_adapter *adapter
, const char *regd_name
, BAND_TYPE band, enum channel_width bw
, u8 rfpath, u8 rs, u8 ntx_idx, u8 cch, u8 lock
, u8 rfpath, u8 rs, u8 tlrs, u8 ntx_idx, u8 cch, u8 lock
);
s8 PHY_GetTxPowerLimit(_adapter *adapter
s8 phy_get_txpwr_lmt_sub_chs(_adapter *adapter
, const char *regd_name
, BAND_TYPE band, enum channel_width bw
, u8 rfpath, u8 rate, u8 ntx_idx, u8 cch
, u8 rfpath, u8 rate, u8 ntx_idx, u8 cch, u8 opch
);
#else
#define phy_get_txpwr_lmt_abs(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max)
#define phy_get_txpwr_lmt(adapter, regd_name, band, bw, rfpath, rs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max)
#define PHY_GetTxPowerLimit(adapter, regd_name, band, bw, rfpath, rate, ntx_idx, cch) (GET_HAL_SPEC(adapter)->txgi_max)
#define phy_get_txpwr_lmt(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max)
#define phy_get_txpwr_lmt_diff(adapter, regd_name, band, bw, rfpath, rs, tlrs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max)
#define phy_get_txpwr_lmt_sub_chs(adapter, regd_name, band, bw, rfpath, rate, ntx_idx, cch, opch) (GET_HAL_SPEC(adapter)->txgi_max)
#endif /* CONFIG_TXPWR_LIMIT */
s8 phy_get_txpwr_target(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate, u8 ntx_idx
, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch, struct txpwr_idx_comp *tic);
s8 phy_get_txpwr_amends(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate, u8 ntx_idx
, enum channel_width bw, BAND_TYPE band, u8 cch, struct txpwr_idx_comp *tic);
#ifdef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
s8 phy_get_tssi_txpwr_by_rate_ref(_adapter *adapter, enum rf_path path
, enum channel_width bw, u8 cch, u8 opch);
#endif
u8 hal_com_get_txpwr_idx(_adapter *adapter, enum rf_path rfpath
, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch
, struct txpwr_idx_comp *tic);
s16 phy_get_txpwr_single_mbm(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate
, enum channel_width bw, u8 cch, u8 opch, struct txpwr_idx_comp *tic);
s16 phy_get_txpwr_total_mbm(_adapter *adapter, RATE_SECTION rs, u8 rate
, enum channel_width bw, u8 cch, u8 opch, struct txpwr_idx_comp *tic);
s16 phy_get_txpwr_single_max_mbm(_adapter *adapter, u8 rfpath
, enum channel_width bw, u8 cch, u8 opch, u16 bmp_cck_ofdm, u32 bmp_ht, u64 bmp_vht);
s16 phy_get_txpwr_total_max_mbm(_adapter *adapter
, enum channel_width bw, u8 cch, u8 opch, u16 bmp_cck_ofdm, u32 bmp_ht, u64 bmp_vht);
s8
phy_get_tx_power_final_absolute_value(_adapter *adapter, u8 rfpath, u8 rate,
enum channel_width bw, u8 channel);
s8
PHY_GetTxPowerTrackingOffset(
PADAPTER pAdapter,
@@ -194,38 +221,65 @@ PHY_GetTxPowerTrackingOffset(
struct txpwr_idx_comp {
u8 ntx_idx;
u8 base;
s8 target;
s8 base;
/* for target */
s8 by_rate;
s8 btc;
s8 extra;
s8 utarget;
s8 limit;
s8 ulimit;
/* for amends */
s8 tpt;
s8 ebias;
s8 dpd;
};
u8 phy_get_tx_power_index_ex(_adapter *adapter
, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate
, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch);
u8
phy_get_tx_power_index(
IN PADAPTER pAdapter,
IN enum rf_path RFPath,
IN u8 Rate,
IN enum channel_width BandWidth,
IN u8 Channel
PADAPTER pAdapter,
enum rf_path RFPath,
u8 Rate,
enum channel_width BandWidth,
u8 Channel
);
VOID
void
PHY_SetTxPowerIndex(
IN PADAPTER pAdapter,
IN u32 PowerIndex,
IN enum rf_path RFPath,
IN u8 Rate
PADAPTER pAdapter,
u32 PowerIndex,
enum rf_path RFPath,
u8 Rate
);
void dump_tx_power_idx_title(void *sel, _adapter *adapter);
void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath, u8 rs);
void dump_tx_power_idx(void *sel, _adapter *adapter);
bool phy_is_txpwr_user_mbm_valid(_adapter *adapter, s16 mbm);
bool phy_is_txpwr_user_target_specified(_adapter *adapter);
void dump_tx_power_index_inline(void *sel, _adapter *adapter, u8 rfpath
, enum channel_width bw, u8 cch, enum MGN_RATE rate, u8 pwr_idx, struct txpwr_idx_comp *tic);
void dump_tx_power_idx_title(void *sel, _adapter *adapter
, enum channel_width bw, u8 cch, u8 opch);
void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath
, RATE_SECTION rs, enum channel_width bw, u8 cch, u8 opch);
void dump_tx_power_idx(void *sel, _adapter *adapter
, enum channel_width bw, u8 cch, u8 opch);
void dump_txpwr_total_dbm_title(void *sel, _adapter *adapter
, enum channel_width bw, u8 cch, u8 opch);
void dump_txpwr_total_dbm_by_rs(void *sel, _adapter *adapter, u8 rs
, enum channel_width bw, u8 cch, u8 opch);
void dump_txpwr_total_dbm(void *sel, _adapter *adapter
, enum channel_width bw, u8 cch, u8 opch);
bool phy_is_tx_power_limit_needed(_adapter *adapter);
bool phy_is_tx_power_by_rate_needed(_adapter *adapter);
int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file);
#ifdef CONFIG_TXPWR_LIMIT
#if CONFIG_TXPWR_LIMIT
int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file);
#endif
void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file);
@@ -238,15 +292,12 @@ const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter);
int check_phy_efuse_tx_power_info_valid(_adapter *adapter);
#endif
#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
void dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt);
void dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt);
void hal_load_txpwr_info(
_adapter *adapter,
TxPowerInfo24G *pwr_info_2g,
TxPowerInfo5G *pwr_info_5g,
u8 *pg_data
);
void hal_load_txpwr_info(_adapter *adapter);
#endif
void dump_tx_power_ext_info(void *sel, _adapter *adapter);
void dump_target_tx_power(void *sel, _adapter *adapter);
@@ -273,7 +324,7 @@ int rtw_get_phy_file_path(_adapter *adapter, const char *file_name);
#define PHY_FILE_WIFI_ANT_ISOLATION "wifi_ant_isolation.txt"
#define MAX_PARA_FILE_BUF_LEN 25600
#define MAX_PARA_FILE_BUF_LEN 32768 /* 32k */
#define LOAD_MAC_PARA_FILE BIT0
#define LOAD_BB_PARA_FILE BIT1
@@ -283,14 +334,14 @@ int rtw_get_phy_file_path(_adapter *adapter, const char *file_name);
#define LOAD_RF_TXPWR_TRACK_PARA_FILE BIT5
#define LOAD_RF_TXPWR_LMT_PARA_FILE BIT6
int phy_ConfigMACWithParaFile(IN PADAPTER Adapter, IN char *pFileName);
int phy_ConfigBBWithParaFile(IN PADAPTER Adapter, IN char *pFileName, IN u32 ConfigType);
int phy_ConfigBBWithPgParaFile(IN PADAPTER Adapter, IN const char *pFileName);
int phy_ConfigBBWithMpParaFile(IN PADAPTER Adapter, IN char *pFileName);
int PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN char *pFileName, IN enum rf_path eRFPath);
int PHY_ConfigRFWithTxPwrTrackParaFile(IN PADAPTER Adapter, IN char *pFileName);
#ifdef CONFIG_TXPWR_LIMIT
int PHY_ConfigRFWithPowerLimitTableParaFile(IN PADAPTER Adapter, IN const char *pFileName);
int phy_ConfigMACWithParaFile(PADAPTER Adapter, char *pFileName);
int phy_ConfigBBWithParaFile(PADAPTER Adapter, char *pFileName, u32 ConfigType);
int phy_ConfigBBWithPgParaFile(PADAPTER Adapter, const char *pFileName);
int phy_ConfigBBWithMpParaFile(PADAPTER Adapter, char *pFileName);
int PHY_ConfigRFWithParaFile(PADAPTER Adapter, char *pFileName, enum rf_path eRFPath);
int PHY_ConfigRFWithTxPwrTrackParaFile(PADAPTER Adapter, char *pFileName);
#if CONFIG_TXPWR_LIMIT
int PHY_ConfigRFWithPowerLimitTableParaFile(PADAPTER Adapter, const char *pFileName);
#endif
void phy_free_filebuf_mask(_adapter *padapter, u8 mask);
void phy_free_filebuf(_adapter *padapter);

66
include/hal_com_reg.h
View File

@@ -173,6 +173,8 @@
#define REG_TXDMA_OFFSET_CHK 0x020C
#define REG_TXDMA_STATUS 0x0210
#define REG_RQPN_NPQ 0x0214
#define REG_TQPNT1 0x0218
#define REG_TQPNT2 0x021C
#define REG_AUTO_LLT 0x0224
@@ -254,7 +256,7 @@
#define REG_HWSEQ_CTRL 0x0423
#define REG_BCNQ_BDNY 0x0424
#define REG_MGQ_BDNY 0x0425
#define REG_LIFETIME_CTRL 0x0426
#define REG_LIFETIME_EN 0x0426
#define REG_MULTI_BCNQ_OFFSET 0x0427
#define REG_SPEC_SIFS 0x0428
#define REG_RETRY_LIMIT 0x042A
@@ -289,8 +291,9 @@
#define REG_POWER_STAGE1 0x04B4
#define REG_POWER_STAGE2 0x04B8
#define REG_PKT_VO_VI_LIFE_TIME 0x04C0
#define REG_PKT_BE_BK_LIFE_TIME 0x04C2
#define REG_PKT_LIFE_TIME 0x04C0
#define REG_PKT_LIFE_TIME_VO_VI 0x04C0
#define REG_PKT_LIFE_TIME_BE_BK 0x04C2
#define REG_STBC_SETTING 0x04C4
#define REG_QUEUE_CTRL 0x04C6
#define REG_SINGLE_AMPDU_CTRL 0x04c7
@@ -506,6 +509,11 @@
/* Enable/Disable Port 0 and Port 1 for Specific ICs (ex. 8192F)*/
#define REG_WLAN_ACT_MASK_CTRL_1 0x076C
/* GPIO Control */
#define REG_SW_GPIO_SHARE_CTRL 0x1038
#define REG_SW_GPIO_A_OUT 0x1040
#define REG_SW_GPIO_A_OEN 0x1044
/* Hardware Port 2 */
#define REG_MACID2 0x1620
#define REG_BSSID2 0x1628
@@ -586,16 +594,6 @@
#define IDR0 REG_MACID /* MAC ID Register, Offset 0x0050-0x0053 */
#define IDR4 (REG_MACID + 4) /* MAC ID Register, Offset 0x0054-0x0055 */
/*
* 9. Security Control Registers (Offset: )
* */
#define RWCAM REG_CAMCMD /* IN 8190 Data Sheet is called CAMcmd */
#define WCAMI REG_CAMWRITE /* Software write CAM input content */
#define RCAMO REG_CAMREAD /* Software read/write CAM config */
#define CAMDBG REG_CAMDBG
#define SECR REG_SECCFG /* Security Configuration Register */
/* Unused register */
#define UnusedRegister 0x1BF
#define DCAM UnusedRegister
@@ -684,6 +682,23 @@ Default: 00b.
#define USB_INTR_CONTENT_HISRE_OFFSET 52
#define USB_INTR_CONTENT_LENGTH 56
/* WOL bit information */
#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0)
#define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1)
#define HAL92C_WOL_DISASSOC_EVENT BIT(2)
#define HAL92C_WOL_DEAUTH_EVENT BIT(3)
#define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4)
/*----------------------------------------------------------------------------
** REG_CCK_CHECK (offset 0x454)
------------------------------------------------------------------------------*/
#define BIT_BCN_PORT_SEL BIT(5)
#define BIT_EN_BCN_PKT_REL BIT(6)
#endif /* RTW_HALMAC */
/* ----------------------------------------------------------------------------
* Response Rate Set Register (offset 0x440, 24bits)
* ---------------------------------------------------------------------------- */
@@ -711,22 +726,6 @@ Default: 00b.
#define RRSR_CCK_RATES (RRSR_11M | RRSR_5_5M | RRSR_2M | RRSR_1M)
#define RRSR_OFDM_RATES (RRSR_54M | RRSR_48M | RRSR_36M | RRSR_24M | RRSR_18M | RRSR_12M | RRSR_9M | RRSR_6M)
/* WOL bit information */
#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0)
#define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1)
#define HAL92C_WOL_DISASSOC_EVENT BIT(2)
#define HAL92C_WOL_DEAUTH_EVENT BIT(3)
#define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4)
/*----------------------------------------------------------------------------
** REG_CCK_CHECK (offset 0x454)
------------------------------------------------------------------------------*/
#define BIT_BCN_PORT_SEL BIT(5)
#define BIT_EN_BCN_PKT_REL BIT(6)
#endif /* RTW_HALMAC */
/* ----------------------------------------------------------------------------
* Rate Definition
* ---------------------------------------------------------------------------- */
@@ -1247,6 +1246,15 @@ Current IOREG MAP
#define EFUSE_BT_SEL_1 0x2
#define EFUSE_BT_SEL_2 0x3
/* 2 REG_GPIO_INTM (Offset 0x0048) */
#define BIT_EXTWOL_EN BIT(16)
/* 2 REG_LED_CFG (Offset 0x004C) */
#define BIT_SW_SPDT_SEL BIT(22)
/* 2 REG_SW_GPIO_SHARE_CTRL (Offset 0x1038) */
#define BIT_BTGP_WAKE_LOC (BIT(10) | BIT(11))
#define BIT_SW_GPIO_FUNC BIT(0)
/* 2 8051FWDL
* 2 MCUFWDL */

380
include/hal_data.h
View File

@@ -94,8 +94,8 @@ typedef enum _RT_AMPDU_BRUST_MODE {
#define MAX_RATE_SECTION_NUM 10
#define MAX_5G_BANDWIDTH_NUM 4
#define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */
#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 /* OFDM:1, HT:4, VHT:4 */
#define NUM_OF_TARGET_TXPWR_2G 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */
#define NUM_OF_TARGET_TXPWR_5G 9 /* OFDM:1, HT:4, VHT:4 */
#ifdef RTW_RX_AGGREGATION
typedef enum _RX_AGG_MODE {
@@ -144,7 +144,7 @@ typedef enum _RX_AGG_MODE {
#define EFUSE_MAP_SIZE 512
#endif
#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8814B)
#define EFUSE_MAX_SIZE 1024
#elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8710B)
#define EFUSE_MAX_SIZE 256
@@ -209,7 +209,7 @@ struct kfree_data_t {
u8 flag;
s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX];
#ifdef CONFIG_IEEE80211_BAND_5GHZ
#if CONFIG_IEEE80211_BAND_5GHZ
s8 pa_bias_5g[RF_PATH_MAX];
s8 pad_bias_5g[RF_PATH_MAX];
#endif
@@ -227,18 +227,26 @@ struct hal_spec_t {
u8 rfpath_num_2g:4; /* used for tx power index path */
u8 rfpath_num_5g:4; /* used for tx power index path */
u8 txgi_max; /* maximum tx power gain index */
u8 txgi_pdbm; /* tx power gain index per dBm */
u8 rf_reg_path_num;
u8 max_tx_cnt;
u8 tx_nss_num:4;
u8 rx_nss_num:4;
u8 band_cap; /* value of BAND_CAP_XXX */
u8 bw_cap; /* value of BW_CAP_XXX */
u8 port_num;
u8 proto_cap; /* value of PROTO_CAP_XXX */
u8 txgi_max; /* maximum tx power gain index */
u8 txgi_pdbm; /* tx power gain index per dBm */
u8 wl_func; /* value of WL_FUNC_XXX */
#if CONFIG_TX_AC_LIFETIME
u8 tx_aclt_unit_factor; /* how many 32us */
#endif
u8 rx_tsf_filter:1;
u8 pg_txpwr_saddr; /* starting address of PG tx power info */
@@ -253,8 +261,6 @@ struct hal_spec_t {
_band == BAND_ON_2_4G ? HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) : \
_band == BAND_ON_5G ? HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) : 0)
#define HAL_SPEC_CHK_TX_CNT(_spec, _cnt_idx) ((_spec)->max_tx_cnt > (_cnt_idx))
#ifdef CONFIG_PHY_CAPABILITY_QUERY
struct phy_spec_t {
u32 trx_cap;
@@ -313,7 +319,7 @@ typedef struct hal_p2p_ps_para {
#define TXPWR_LMT_RS_NUM_2G 4 /* CCK, OFDM, HT, VHT */
#define TXPWR_LMT_RS_NUM_5G 3 /* OFDM, HT, VHT */
#ifdef CONFIG_TXPWR_LIMIT
#if CONFIG_TXPWR_LIMIT
extern const char *const _txpwr_lmt_rs_str[];
#define txpwr_lmt_rs_str(rs) (((rs) >= TXPWR_LMT_RS_NUM) ? _txpwr_lmt_rs_str[TXPWR_LMT_RS_NUM] : _txpwr_lmt_rs_str[(rs)])
@@ -325,7 +331,7 @@ struct txpwr_lmt_ent {
[CENTER_CH_2G_NUM]
[MAX_TX_COUNT];
#ifdef CONFIG_IEEE80211_BAND_5GHZ
#if CONFIG_IEEE80211_BAND_5GHZ
s8 lmt_5g[MAX_5G_BANDWIDTH_NUM]
[TXPWR_LMT_RS_NUM_5G]
[CENTER_CH_5G_ALL_NUM]
@@ -353,6 +359,9 @@ typedef struct hal_com_data {
u8 bBTFWReady;
u8 fw_ractrl;
u8 LastHMEBoxNum; /* H2C - for host message to fw */
#ifdef CONFIG_LPS_1T1R
u8 lps_1t1r;
#endif
/****** current WIFI_PHY values ******/
WIRELESS_MODE CurrentWirelessMode;
@@ -377,7 +386,6 @@ typedef struct hal_com_data {
BOOLEAN bSWToBW40M;
BOOLEAN bSWToBW80M;
BOOLEAN bChnlBWInitialized;
u32 BackUp_BB_REG_4_2nd_CCA[3];
#ifdef CONFIG_RTW_ACS
struct auto_chan_sel acs;
@@ -388,11 +396,23 @@ typedef struct hal_com_data {
/****** rf_ctrl *****/
u8 rf_chip;
u8 rf_type; /*enum rf_type*/
u8 trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp */
u8 rf_type; /*enum rf_type , is RF_PATH - GET_HAL_RFPATH*/
u8 NumTotalRFPath; /*GET_HAL_RFPATH_NUM*/
u8 max_tx_cnt;
u8 tx_nss; /*tx Spatial Streams - GET_HAL_TX_NSS*/
u8 rx_nss; /*rx Spatial Streams - GET_HAL_RX_NSS*/
u8 PackageType;
u8 NumTotalRFPath;
u8 antenna_test;
/* runtime TRX path setting */
enum bb_path txpath; /* TX path bmp */
enum bb_path rxpath; /* RX path bmp */
enum bb_path txpath_nss[4]; /* path bmp for NSS TX, [0] for 1SS, [3] for 4SS */
u8 txpath_num_nss[4]; /* path num for NSS TX, [0] for 1SS, [3] for 4SS */
/****** Debug ******/
u16 ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */
u8 bDumpRxPkt;
@@ -433,6 +453,10 @@ typedef struct hal_com_data {
u8 EEPROMBluetoothAntIsolation;
u8 EEPROMBluetoothRadioShared;
u8 EEPROMMACAddr[ETH_ALEN];
u8 eeprom_trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp. 0x00:not specified */
u8 eeprom_max_tx_cnt; /* 0: not specified */
u8 tx_bbswing_24G;
u8 tx_bbswing_5G;
u8 efuse0x3d7; /* efuse[0x3D7] */
@@ -444,6 +468,9 @@ typedef struct hal_com_data {
struct kfree_data_t kfree_data;
#endif /*CONFIG_RF_POWER_TRIM*/
#ifdef CONFIG_RTL8814A
u32 BackUp_BB_REG_4_2nd_CCA[3];
#endif
#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \
defined(CONFIG_RTL8723D) || \
defined(CONFIG_RTL8192F)
@@ -456,7 +483,10 @@ typedef struct hal_com_data {
/*u8 EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/
EFUSE_HAL EfuseHal;
u8 txpwr_pg_mode; /* enum txpwr_pg_mode */
/*---------------------------------------------------------------------------------*/
#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
/* 2.4G TX power info for target TX power*/
u8 Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];
u8 Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];
@@ -466,7 +496,7 @@ typedef struct hal_com_data {
s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
/* 5G TX power info for target TX power*/
#ifdef CONFIG_IEEE80211_BAND_5GHZ
#if CONFIG_IEEE80211_BAND_5GHZ
u8 Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM];
u8 Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM];
s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
@@ -474,25 +504,29 @@ typedef struct hal_com_data {
s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
#endif
#endif /* CONFIG_TXPWR_PG_WITH_PWR_IDX */
u8 txpwr_by_rate_undefined_band_path[TX_PWR_BY_RATE_NUM_BAND]
[TX_PWR_BY_RATE_NUM_RF];
s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND]
s8 TxPwrByRate[TX_PWR_BY_RATE_NUM_BAND]
[TX_PWR_BY_RATE_NUM_RF]
[TX_PWR_BY_RATE_NUM_RATE];
/* Store the original power by rate value of the base rate for each rate section and rf path */
u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF]
[MAX_BASE_NUM_IN_PHY_REG_PG_2_4G];
u8 TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF]
[MAX_BASE_NUM_IN_PHY_REG_PG_5G];
/* Store the target power for each rate section and rf path */
u8 target_txpwr_2g[TX_PWR_BY_RATE_NUM_RF]
[NUM_OF_TARGET_TXPWR_2G];
u8 target_txpwr_5g[TX_PWR_BY_RATE_NUM_RF]
[NUM_OF_TARGET_TXPWR_5G];
#if defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
u32 txagc_set_buf;
#endif
u8 txpwr_by_rate_loaded:1;
u8 txpwr_by_rate_from_file:1;
u8 txpwr_limit_loaded:1;
u8 txpwr_limit_from_file:1;
u8 rf_power_tracking_type;
/* Read/write are allow for following hardware information variables */
u8 crystal_cap;
@@ -522,7 +556,10 @@ typedef struct hal_com_data {
/* RDG enable */
BOOLEAN bRDGEnable;
u16 RegRRSR;
#if defined (CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
u32 RegRRSR;
#endif
/****** antenna diversity ******/
u8 AntDivCfg;
u8 with_extenal_ant_switch;
@@ -552,9 +589,6 @@ typedef struct hal_com_data {
/* 2010/08/09 MH Add CU power down mode. */
BOOLEAN pwrdown;
/* Add for dual MAC 0--Mac0 1--Mac1 */
u32 interfaceIndex;
#ifdef CONFIG_P2P
#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
u16 p2p_ps_offload;
@@ -607,6 +641,9 @@ typedef struct hal_com_data {
#else
u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
#endif/*CONFIG_RTL8192F*/
#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
u8 sdio_avail_int_en_q;
#endif
_lock SdioTxFIFOFreePageLock;
u8 SdioTxOQTMaxFreeSpace;
u8 SdioTxOQTFreeSpace;
@@ -618,7 +655,11 @@ typedef struct hal_com_data {
/* SDIO Rx FIFO related. */
/* */
u8 SdioRxFIFOCnt;
#ifdef CONFIG_RTL8822C
u32 SdioRxFIFOSize;
#else
u16 SdioRxFIFOSize;
#endif
#ifndef RTW_HALMAC
u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */
@@ -684,8 +725,6 @@ typedef struct hal_com_data {
u32 IntrMaskReg[2];
u32 IntrMaskDefault[4];
BOOLEAN bL1OffSupport;
BOOLEAN bSupportBackDoor;
u32 pci_backdoor_ctrl;
u8 bDefaultAntenna;
@@ -694,9 +733,6 @@ typedef struct hal_com_data {
u8 bDisableTxInt;
u16 RxTag;
#ifdef CONFIG_PCI_DYNAMIC_ASPM
BOOLEAN bAspmL1LastIdle;
#endif
#endif /* CONFIG_PCI_HCI */
@@ -756,9 +792,10 @@ typedef struct hal_com_data {
#if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN)
BOOLEAN bCorrectBCN;
#endif
#ifdef CONFIG_RTL8814A
u32 RxGainOffset[4]; /*{2G, 5G_Low, 5G_Middle, G_High}*/
u8 BackUp_IG_REG_4_Chnl_Section[4]; /*{A,B,C,D}*/
#endif
struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM];
#ifdef RTW_HALMAC
@@ -780,16 +817,22 @@ typedef struct hal_com_data {
#ifdef CONFIG_RTW_LED
struct led_priv led;
#endif
/* for multi channel case (ex: MCC/TDLS) */
u8 multi_ch_switch_mode;
#ifdef CONFIG_RTL8814B
u8 dma_ch_map[32]; /* TXDESC qsel maximum size */
#endif
} HAL_DATA_COMMON, *PHAL_DATA_COMMON;
typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE;
#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)(((struct _ADAPTER*)__pAdapter)->HalData))
#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)(((struct _ADAPTER*)__pAdapter)->HalData))
#define GET_HAL_SPEC(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->hal_spec))
#define adapter_to_led(adapter) (&(GET_HAL_DATA(adapter)->led))
#define GET_HAL_RFPATH_NUM(__pAdapter) (((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath)
#define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel)
#define GET_RF_TYPE(__pAdapter) (GET_HAL_DATA(__pAdapter)->rf_type)
#define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data))
#define SUPPORT_HW_RADIO_DETECT(Adapter) (RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD || \
@@ -801,266 +844,21 @@ typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE;
#define rtw_get_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed)
#define rtw_set_hw_init_completed(adapter, cmp) (GET_HAL_DATA(adapter)->hw_init_completed = cmp)
#define rtw_is_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE)
/* refer to (hal_data->version_id.RFType / registrypriv->rf_path / 8814a from efuse or registrypriv)*/
#define GET_HAL_RFPATH(adapter) (GET_HAL_DATA(adapter)->rf_type)
#define GET_HAL_RFPATH_NUM(adapter) (GET_HAL_DATA(adapter)->NumTotalRFPath)
#define GET_HAL_TX_PATH_BMP(adapter) ((GET_HAL_DATA(adapter)->trx_path_bmp & 0xF0) >> 4)
#define GET_HAL_RX_PATH_BMP(adapter) (GET_HAL_DATA(adapter)->trx_path_bmp & 0x0F)
/* refer to (registrypriv-> tx_nss,rx_nss / hal_spec->tx_nss_num,rx_nss_num)*/
#define GET_HAL_TX_NSS(adapter) (GET_HAL_DATA(adapter)->tx_nss)
#define GET_HAL_RX_NSS(adapter) (GET_HAL_DATA(adapter)->rx_nss)
#endif
#ifdef RTW_HALMAC
int rtw_halmac_deinit_adapter(struct dvobj_priv *);
#endif /* RTW_HALMAC */
/* alias for phydm coding style */
#define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance
#define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold
#define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack
#define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage
#define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1
#define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1
#define REG_A_TX_SCALE_JAGUAR rA_TxScale_Jaguar
#define REG_B_TX_SCALE_JAGUAR rB_TxScale_Jaguar
#define REG_FPGA0_XAB_RF_INTERFACE_SW rFPGA0_XAB_RFInterfaceSW
#define REG_FPGA0_XAB_RF_PARAMETER rFPGA0_XAB_RFParameter
#define REG_FPGA0_XA_HSSI_PARAMETER1 rFPGA0_XA_HSSIParameter1
#define REG_FPGA0_XA_LSSI_PARAMETER rFPGA0_XA_LSSIParameter
#define REG_FPGA0_XA_RF_INTERFACE_OE rFPGA0_XA_RFInterfaceOE
#define REG_FPGA0_XB_HSSI_PARAMETER1 rFPGA0_XB_HSSIParameter1
#define REG_FPGA0_XB_LSSI_PARAMETER rFPGA0_XB_LSSIParameter
#define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack
#define REG_FPGA0_XB_RF_INTERFACE_OE rFPGA0_XB_RFInterfaceOE
#define REG_FPGA0_XCD_RF_INTERFACE_SW rFPGA0_XCD_RFInterfaceSW
#define REG_FPGA0_XCD_SWITCH_CONTROL rFPGA0_XCD_SwitchControl
#define REG_FPGA1_TX_BLOCK rFPGA1_TxBlock
#define REG_FPGA1_TX_INFO rFPGA1_TxInfo
#define REG_IQK_AGC_CONT rIQK_AGC_Cont
#define REG_IQK_AGC_PTS rIQK_AGC_Pts
#define REG_IQK_AGC_RSP rIQK_AGC_Rsp
#define REG_OFDM_0_AGC_RSSI_TABLE rOFDM0_AGCRSSITable
#define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold
#define REG_OFDM_0_RX_IQ_EXT_ANTA rOFDM0_RxIQExtAnta
#define REG_OFDM_0_TR_MUX_PAR rOFDM0_TRMuxPar
#define REG_OFDM_0_TRX_PATH_ENABLE rOFDM0_TRxPathEnable
#define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1
#define REG_OFDM_0_XA_RX_IQ_IMBALANCE rOFDM0_XARxIQImbalance
#define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance
#define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1
#define REG_OFDM_0_XB_RX_IQ_IMBALANCE rOFDM0_XBRxIQImbalance
#define REG_OFDM_0_XB_TX_IQ_IMBALANCE rOFDM0_XBTxIQImbalance
#define REG_OFDM_0_XC_TX_AFE rOFDM0_XCTxAFE
#define REG_OFDM_0_XD_TX_AFE rOFDM0_XDTxAFE
/*#define REG_A_CFO_LONG_DUMP_92E rA_CfoLongDump_92E*/
#define REG_A_CFO_LONG_DUMP_JAGUAR rA_CfoLongDump_Jaguar
/*#define REG_A_CFO_SHORT_DUMP_92E rA_CfoShortDump_92E*/
#define REG_A_CFO_SHORT_DUMP_JAGUAR rA_CfoShortDump_Jaguar
#define REG_A_RFE_PINMUX_JAGUAR rA_RFE_Pinmux_Jaguar
/*#define REG_A_RSSI_DUMP_92E rA_RSSIDump_92E*/
#define REG_A_RSSI_DUMP_JAGUAR rA_RSSIDump_Jaguar
/*#define REG_A_RX_SNR_DUMP_92E rA_RXsnrDump_92E*/
#define REG_A_RX_SNR_DUMP_JAGUAR rA_RXsnrDump_Jaguar
/*#define REG_A_TX_AGC rA_TXAGC*/
#define REG_A_TX_SCALE_JAGUAR rA_TxScale_Jaguar
#define REG_BW_INDICATION_JAGUAR rBWIndication_Jaguar
/*#define REG_B_BBSWING rB_BBSWING*/
/*#define REG_B_CFO_LONG_DUMP_92E rB_CfoLongDump_92E*/
#define REG_B_CFO_LONG_DUMP_JAGUAR rB_CfoLongDump_Jaguar
/*#define REG_B_CFO_SHORT_DUMP_92E rB_CfoShortDump_92E*/
#define REG_B_CFO_SHORT_DUMP_JAGUAR rB_CfoShortDump_Jaguar
/*#define REG_B_RSSI_DUMP_92E rB_RSSIDump_92E*/
#define REG_B_RSSI_DUMP_JAGUAR rB_RSSIDump_Jaguar
/*#define REG_B_RX_SNR_DUMP_92E rB_RXsnrDump_92E*/
#define REG_B_RX_SNR_DUMP_JAGUAR rB_RXsnrDump_Jaguar
/*#define REG_B_TX_AGC rB_TXAGC*/
#define REG_B_TX_SCALE_JAGUAR rB_TxScale_Jaguar
#define REG_BLUE_TOOTH rBlue_Tooth
#define REG_CCK_0_AFE_SETTING rCCK0_AFESetting
/*#define REG_C_BBSWING rC_BBSWING*/
/*#define REG_C_TX_AGC rC_TXAGC*/
#define REG_C_TX_SCALE_JAGUAR2 rC_TxScale_Jaguar2
#define REG_CONFIG_ANT_A rConfig_AntA
#define REG_CONFIG_ANT_B rConfig_AntB
#define REG_CONFIG_PMPD_ANT_A rConfig_Pmpd_AntA
#define REG_CONFIG_PMPD_ANT_B rConfig_Pmpd_AntB
#define REG_DPDT_CONTROL rDPDT_control
/*#define REG_D_BBSWING rD_BBSWING*/
/*#define REG_D_TX_AGC rD_TXAGC*/
#define REG_D_TX_SCALE_JAGUAR2 rD_TxScale_Jaguar2
#define REG_FPGA0_ANALOG_PARAMETER4 rFPGA0_AnalogParameter4
#define REG_FPGA0_IQK rFPGA0_IQK
#define REG_FPGA0_PSD_FUNCTION rFPGA0_PSDFunction
#define REG_FPGA0_PSD_REPORT rFPGA0_PSDReport
#define REG_FPGA0_RFMOD rFPGA0_RFMOD
#define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage
#define REG_FPGA0_XAB_RF_INTERFACE_SW rFPGA0_XAB_RFInterfaceSW
#define REG_FPGA0_XAB_RF_PARAMETER rFPGA0_XAB_RFParameter
#define REG_FPGA0_XA_HSSI_PARAMETER1 rFPGA0_XA_HSSIParameter1
#define REG_FPGA0_XA_LSSI_PARAMETER rFPGA0_XA_LSSIParameter
#define REG_FPGA0_XA_RF_INTERFACE_OE rFPGA0_XA_RFInterfaceOE
#define REG_FPGA0_XB_HSSI_PARAMETER1 rFPGA0_XB_HSSIParameter1
#define REG_FPGA0_XB_LSSI_PARAMETER rFPGA0_XB_LSSIParameter
#define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack
#define REG_FPGA0_XB_RF_INTERFACE_OE rFPGA0_XB_RFInterfaceOE
#define REG_FPGA0_XCD_RF_INTERFACE_SW rFPGA0_XCD_RFInterfaceSW
#define REG_FPGA0_XCD_SWITCH_CONTROL rFPGA0_XCD_SwitchControl
#define REG_FPGA1_TX_BLOCK rFPGA1_TxBlock
#define REG_FPGA1_TX_INFO rFPGA1_TxInfo
#define REG_IQK_AGC_CONT rIQK_AGC_Cont
#define REG_IQK_AGC_PTS rIQK_AGC_Pts
#define REG_IQK_AGC_RSP rIQK_AGC_Rsp
#define REG_OFDM_0_AGC_RSSI_TABLE rOFDM0_AGCRSSITable
#define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold
#define REG_OFDM_0_RX_IQ_EXT_ANTA rOFDM0_RxIQExtAnta
#define REG_OFDM_0_TR_MUX_PAR rOFDM0_TRMuxPar
#define REG_OFDM_0_TRX_PATH_ENABLE rOFDM0_TRxPathEnable
#define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1
#define REG_OFDM_0_XA_RX_IQ_IMBALANCE rOFDM0_XARxIQImbalance
#define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance
#define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1
#define REG_OFDM_0_XB_RX_IQ_IMBALANCE rOFDM0_XBRxIQImbalance
#define REG_OFDM_0_XB_TX_IQ_IMBALANCE rOFDM0_XBTxIQImbalance
#define REG_OFDM_0_XC_TX_AFE rOFDM0_XCTxAFE
#define REG_OFDM_0_XD_TX_AFE rOFDM0_XDTxAFE
#define REG_PMPD_ANAEN rPMPD_ANAEN
#define REG_PDP_ANT_A rPdp_AntA
#define REG_PDP_ANT_A_4 rPdp_AntA_4
#define REG_PDP_ANT_B rPdp_AntB
#define REG_PDP_ANT_B_4 rPdp_AntB_4
#define REG_PWED_TH_JAGUAR rPwed_TH_Jaguar
#define REG_RX_CCK rRx_CCK
#define REG_RX_IQK rRx_IQK
#define REG_RX_IQK_PI_A rRx_IQK_PI_A
#define REG_RX_IQK_PI_B rRx_IQK_PI_B
#define REG_RX_IQK_TONE_A rRx_IQK_Tone_A
#define REG_RX_IQK_TONE_B rRx_IQK_Tone_B
#define REG_RX_OFDM rRx_OFDM
#define REG_RX_POWER_AFTER_IQK_A_2 rRx_Power_After_IQK_A_2
#define REG_RX_POWER_AFTER_IQK_B_2 rRx_Power_After_IQK_B_2
#define REG_RX_POWER_BEFORE_IQK_A_2 rRx_Power_Before_IQK_A_2
#define REG_RX_POWER_BEFORE_IQK_B_2 rRx_Power_Before_IQK_B_2
#define REG_RX_TO_RX rRx_TO_Rx
#define REG_RX_WAIT_CCA rRx_Wait_CCA
#define REG_RX_WAIT_RIFS rRx_Wait_RIFS
#define REG_S0_S1_PATH_SWITCH rS0S1_PathSwitch
/*#define REG_S1_RXEVM_DUMP_92E rS1_RXevmDump_92E*/
#define REG_S1_RXEVM_DUMP_JAGUAR rS1_RXevmDump_Jaguar
/*#define REG_S2_RXEVM_DUMP_92E rS2_RXevmDump_92E*/
#define REG_S2_RXEVM_DUMP_JAGUAR rS2_RXevmDump_Jaguar
#define REG_SYM_WLBT_PAPE_SEL rSYM_WLBT_PAPE_SEL
#define REG_SINGLE_TONE_CONT_TX_JAGUAR rSingleTone_ContTx_Jaguar
#define REG_SLEEP rSleep
#define REG_STANDBY rStandby
#define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR rTxAGC_A_CCK11_CCK1_JAguar
#define REG_TX_AGC_A_CCK_1_MCS32 rTxAGC_A_CCK1_Mcs32
#define REG_TX_AGC_A_MCS11_MCS8_JAGUAR rTxAGC_A_MCS11_MCS8_JAguar
#define REG_TX_AGC_A_MCS15_MCS12_JAGUAR rTxAGC_A_MCS15_MCS12_JAguar
#define REG_TX_AGC_A_MCS19_MCS16_JAGUAR rTxAGC_A_MCS19_MCS16_JAguar
#define REG_TX_AGC_A_MCS23_MCS20_JAGUAR rTxAGC_A_MCS23_MCS20_JAguar
#define REG_TX_AGC_A_MCS3_MCS0_JAGUAR rTxAGC_A_MCS3_MCS0_JAguar
#define REG_TX_AGC_A_MCS7_MCS4_JAGUAR rTxAGC_A_MCS7_MCS4_JAguar
#define REG_TX_AGC_A_MCS03_MCS00 rTxAGC_A_Mcs03_Mcs00
#define REG_TX_AGC_A_MCS07_MCS04 rTxAGC_A_Mcs07_Mcs04
#define REG_TX_AGC_A_MCS11_MCS08 rTxAGC_A_Mcs11_Mcs08
#define REG_TX_AGC_A_MCS15_MCS12 rTxAGC_A_Mcs15_Mcs12
#define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_A_Nss1Index3_Nss1Index0_JAguar
#define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_A_Nss1Index7_Nss1Index4_JAguar
#define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_A_Nss2Index1_Nss1Index8_JAguar
#define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_A_Nss2Index5_Nss2Index2_JAguar
#define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_A_Nss2Index9_Nss2Index6_JAguar
#define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_A_Nss3Index3_Nss3Index0_JAguar
#define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_A_Nss3Index7_Nss3Index4_JAguar
#define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_A_Nss3Index9_Nss3Index8_JAguar
#define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR rTxAGC_A_Ofdm18_Ofdm6_JAguar
#define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR rTxAGC_A_Ofdm54_Ofdm24_JAguar
#define REG_TX_AGC_A_RATE18_06 rTxAGC_A_Rate18_06
#define REG_TX_AGC_A_RATE54_24 rTxAGC_A_Rate54_24
#define REG_TX_AGC_B_CCK_11_A_CCK_2_11 rTxAGC_B_CCK11_A_CCK2_11
#define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR rTxAGC_B_CCK11_CCK1_JAguar
#define REG_TX_AGC_B_CCK_1_55_MCS32 rTxAGC_B_CCK1_55_Mcs32
#define REG_TX_AGC_B_MCS11_MCS8_JAGUAR rTxAGC_B_MCS11_MCS8_JAguar
#define REG_TX_AGC_B_MCS15_MCS12_JAGUAR rTxAGC_B_MCS15_MCS12_JAguar
#define REG_TX_AGC_B_MCS19_MCS16_JAGUAR rTxAGC_B_MCS19_MCS16_JAguar
#define REG_TX_AGC_B_MCS23_MCS20_JAGUAR rTxAGC_B_MCS23_MCS20_JAguar
#define REG_TX_AGC_B_MCS3_MCS0_JAGUAR rTxAGC_B_MCS3_MCS0_JAguar
#define REG_TX_AGC_B_MCS7_MCS4_JAGUAR rTxAGC_B_MCS7_MCS4_JAguar
#define REG_TX_AGC_B_MCS03_MCS00 rTxAGC_B_Mcs03_Mcs00
#define REG_TX_AGC_B_MCS07_MCS04 rTxAGC_B_Mcs07_Mcs04
#define REG_TX_AGC_B_MCS11_MCS08 rTxAGC_B_Mcs11_Mcs08
#define REG_TX_AGC_B_MCS15_MCS12 rTxAGC_B_Mcs15_Mcs12
#define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_B_Nss1Index3_Nss1Index0_JAguar
#define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_B_Nss1Index7_Nss1Index4_JAguar
#define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_B_Nss2Index1_Nss1Index8_JAguar
#define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_B_Nss2Index5_Nss2Index2_JAguar
#define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_B_Nss2Index9_Nss2Index6_JAguar
#define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_B_Nss3Index3_Nss3Index0_JAguar
#define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_B_Nss3Index7_Nss3Index4_JAguar
#define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_B_Nss3Index9_Nss3Index8_JAguar
#define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR rTxAGC_B_Ofdm18_Ofdm6_JAguar
#define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR rTxAGC_B_Ofdm54_Ofdm24_JAguar
#define REG_TX_AGC_B_RATE18_06 rTxAGC_B_Rate18_06
#define REG_TX_AGC_B_RATE54_24 rTxAGC_B_Rate54_24
#define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR rTxAGC_C_CCK11_CCK1_JAguar
#define REG_TX_AGC_C_MCS11_MCS8_JAGUAR rTxAGC_C_MCS11_MCS8_JAguar
#define REG_TX_AGC_C_MCS15_MCS12_JAGUAR rTxAGC_C_MCS15_MCS12_JAguar
#define REG_TX_AGC_C_MCS19_MCS16_JAGUAR rTxAGC_C_MCS19_MCS16_JAguar
#define REG_TX_AGC_C_MCS23_MCS20_JAGUAR rTxAGC_C_MCS23_MCS20_JAguar
#define REG_TX_AGC_C_MCS3_MCS0_JAGUAR rTxAGC_C_MCS3_MCS0_JAguar
#define REG_TX_AGC_C_MCS7_MCS4_JAGUAR rTxAGC_C_MCS7_MCS4_JAguar
#define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_C_Nss1Index3_Nss1Index0_JAguar
#define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_C_Nss1Index7_Nss1Index4_JAguar
#define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_C_Nss2Index1_Nss1Index8_JAguar
#define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_C_Nss2Index5_Nss2Index2_JAguar
#define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_C_Nss2Index9_Nss2Index6_JAguar
#define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_C_Nss3Index3_Nss3Index0_JAguar
#define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_C_Nss3Index7_Nss3Index4_JAguar
#define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_C_Nss3Index9_Nss3Index8_JAguar
#define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR rTxAGC_C_Ofdm18_Ofdm6_JAguar
#define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR rTxAGC_C_Ofdm54_Ofdm24_JAguar
#define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR rTxAGC_D_CCK11_CCK1_JAguar
#define REG_TX_AGC_D_MCS11_MCS8_JAGUAR rTxAGC_D_MCS11_MCS8_JAguar
#define REG_TX_AGC_D_MCS15_MCS12_JAGUAR rTxAGC_D_MCS15_MCS12_JAguar
#define REG_TX_AGC_D_MCS19_MCS16_JAGUAR rTxAGC_D_MCS19_MCS16_JAguar
#define REG_TX_AGC_D_MCS23_MCS20_JAGUAR rTxAGC_D_MCS23_MCS20_JAguar
#define REG_TX_AGC_D_MCS3_MCS0_JAGUAR rTxAGC_D_MCS3_MCS0_JAguar
#define REG_TX_AGC_D_MCS7_MCS4_JAGUAR rTxAGC_D_MCS7_MCS4_JAguar
#define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_D_Nss1Index3_Nss1Index0_JAguar
#define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_D_Nss1Index7_Nss1Index4_JAguar
#define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_D_Nss2Index1_Nss1Index8_JAguar
#define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_D_Nss2Index5_Nss2Index2_JAguar
#define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_D_Nss2Index9_Nss2Index6_JAguar
#define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_D_Nss3Index3_Nss3Index0_JAguar
#define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_D_Nss3Index7_Nss3Index4_JAguar
#define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_D_Nss3Index9_Nss3Index8_JAguar
#define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR rTxAGC_D_Ofdm18_Ofdm6_JAguar
#define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR rTxAGC_D_Ofdm54_Ofdm24_JAguar
#define REG_TX_PATH_JAGUAR rTxPath_Jaguar
#define REG_TX_CCK_BBON rTx_CCK_BBON
#define REG_TX_CCK_RFON rTx_CCK_RFON
#define REG_TX_IQK rTx_IQK
#define REG_TX_IQK_PI_A rTx_IQK_PI_A
#define REG_TX_IQK_PI_B rTx_IQK_PI_B
#define REG_TX_IQK_TONE_A rTx_IQK_Tone_A
#define REG_TX_IQK_TONE_B rTx_IQK_Tone_B
#define REG_TX_OFDM_BBON rTx_OFDM_BBON
#define REG_TX_OFDM_RFON rTx_OFDM_RFON
#define REG_TX_POWER_AFTER_IQK_A rTx_Power_After_IQK_A
#define REG_TX_POWER_AFTER_IQK_B rTx_Power_After_IQK_B
#define REG_TX_POWER_BEFORE_IQK_A rTx_Power_Before_IQK_A
#define REG_TX_POWER_BEFORE_IQK_B rTx_Power_Before_IQK_B
#define REG_TX_TO_RX rTx_To_Rx
#define REG_TX_TO_TX rTx_To_Tx
#define REG_APK rAPK
#define REG_ANTSEL_SW_JAGUAR r_ANTSEL_SW_Jaguar
#define rf_welut_jaguar RF_WeLut_Jaguar
#define rf_mode_table_addr RF_ModeTableAddr
#define rf_mode_table_data0 RF_ModeTableData0
#define rf_mode_table_data1 RF_ModeTableData1
#define RX_SMOOTH_FACTOR Rx_Smooth_Factor
#endif /* __HAL_DATA_H__ */

295
include/hal_ic_cfg.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
* Copyright(c) 2007 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -36,9 +36,11 @@
#define RTL8198F_SUPPORT 0
#define RTL8195B_SUPPORT 0
#define RTL8822C_SUPPORT 0
#define RTL8721D_SUPPORT 0
#define RTL8812F_SUPPORT 0
#define RTL8197G_SUPPORT 0
#define RTL8721D_SUPPORT 0
#define RTL8710C_SUPPORT 0
/*#if (RTL8188E_SUPPORT==1)*/
#define RATE_ADAPTIVE_SUPPORT 0
@@ -55,6 +57,10 @@
#define RTL8188E_SUPPORT 1
#define RATE_ADAPTIVE_SUPPORT 1
#define POWER_TRAINING_ACTIVE 1
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
#endif
#endif
#ifdef CONFIG_RTL8812A
@@ -63,7 +69,16 @@
#ifndef CONFIG_FW_C2H_PKT
#define CONFIG_FW_C2H_PKT
#endif
#ifdef CONFIG_BEAMFORMING
#define CONFIG_BEAMFORMER_FW_NDPA
#define BEAMFORMING_SUPPORT 1 /*for phydm beamforming*/
#define SUPPORT_MU_BF 0
#endif /*CONFIG_BEAMFORMING*/
#define CONFIG_RTS_FULL_BW
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
#endif
#endif
#ifdef CONFIG_RTL8821A
@@ -72,7 +87,16 @@
#ifndef CONFIG_FW_C2H_PKT
#define CONFIG_FW_C2H_PKT
#endif
#ifdef CONFIG_BEAMFORMING
#define CONFIG_BEAMFORMER_FW_NDPA
#define BEAMFORMING_SUPPORT 1 /*for phydm beamforming*/
#define SUPPORT_MU_BF 0
#endif
#define CONFIG_RTS_FULL_BW
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
#endif
#endif
#ifdef CONFIG_RTL8192E
@@ -82,6 +106,10 @@
#define CONFIG_FW_C2H_PKT
#endif
#define CONFIG_RTS_FULL_BW
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
#endif
#endif
#ifdef CONFIG_RTL8192F
@@ -99,6 +127,17 @@
#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
#endif
#define CONFIG_RTS_FULL_BW
/* #define CONFIG_NARROWBAND_SUPPORTING */
#ifdef CONFIG_NARROWBAND_SUPPORTING
#define CONFIG_NB_VALUE RTW_NB_CONFIG_NONE /*RTW_NB_CONFIG_WIDTH_10 or RTW_NB_CONFIG_WIDTH_5 */
#endif
#ifdef CONFIG_WOWLAN
#define CONFIG_WOW_PATTERN_IN_TXFIFO
#endif
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
#endif
#endif
#ifdef CONFIG_RTL8723B
@@ -108,6 +147,10 @@
#define CONFIG_FW_C2H_PKT
#endif
#define CONFIG_RTS_FULL_BW
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
#endif
#endif
#ifdef CONFIG_RTL8723D
@@ -123,6 +166,10 @@
#define CONFIG_RTW_CUSTOMER_STR
#endif
#define CONFIG_RTS_FULL_BW
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
#endif
#endif
#ifdef CONFIG_RTL8814A
@@ -132,7 +179,15 @@
#define CONFIG_FW_C2H_PKT
#endif
#define CONFIG_FW_CORRECT_BCN
#ifdef CONFIG_BEAMFORMING
#define BEAMFORMING_SUPPORT 1 /*for phydm beamforming*/
#define SUPPORT_MU_BF 0
#endif
#define CONFIG_RTS_FULL_BW
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
#endif
#endif
#ifdef CONFIG_RTL8703B
@@ -145,6 +200,10 @@
#define CONFIG_RTW_MAC_HIDDEN_RPT
#endif
#define CONFIG_RTS_FULL_BW
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
#endif
#endif
#ifdef CONFIG_RTL8188F
@@ -160,6 +219,10 @@
#define CONFIG_RTW_CUSTOMER_STR
#endif
#define CONFIG_RTS_FULL_BW
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
#endif
#endif
#ifdef CONFIG_RTL8188GTV
@@ -175,6 +238,10 @@
#define CONFIG_RTW_CUSTOMER_STR
#endif
#define CONFIG_RTS_FULL_BW
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
#endif
#endif
#ifdef CONFIG_RTL8822B
@@ -184,7 +251,6 @@
#define CONFIG_FW_C2H_PKT
#endif /* CONFIG_FW_C2H_PKT */
#define RTW_TX_PA_BIAS /* Adjust TX PA Bias from eFuse */
#define CONFIG_DFS /* Enable 5G band 2&3 channel */
#define RTW_AMPDU_AGG_RETRY_AND_NEW
#ifdef CONFIG_WOWLAN
@@ -206,8 +272,6 @@
/*
* Beamforming related definition
*/
/* Beamforming mechanism is on driver not phydm, always disable it */
#define BEAMFORMING_SUPPORT 0
/* Only support new beamforming mechanism */
#ifdef CONFIG_BEAMFORMING
#define RTW_BEAMFORMING_VERSION_2
@@ -226,13 +290,17 @@
#endif /* RTW_IQK_FW_OFFLOAD */
/* Checksum offload feature */
/*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/ /* not ready */
/*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/
#if defined(CONFIG_TCP_CSUM_OFFLOAD_TX) && !defined(CONFIG_RTW_NETIF_SG)
#define CONFIG_RTW_NETIF_SG
#endif
#define CONFIG_TCP_CSUM_OFFLOAD_RX
#define CONFIG_ADVANCE_OTA
#ifdef CONFIG_MCC_MODE
#define CONFIG_MCC_MODE_V2
#define CONFIG_MCC_PHYDM_OFFLOAD
#endif /* CONFIG_MCC_MODE */
#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
@@ -256,11 +324,110 @@
#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
#endif
#define CONFIG_RTS_FULL_BW
#ifdef CONFIG_LPS
#define CONFIG_LPS_ACK
#define CONFIG_LPS_ACK /* Supported after FW v30 & v27.9 */
#endif
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
#endif
#endif /* CONFIG_RTL8822B */
#ifdef CONFIG_RTL8822C
#undef RTL8822C_SUPPORT
#define RTL8822C_SUPPORT 1
/*#define DBG_LA_MODE*/
#ifndef CONFIG_FW_C2H_PKT
#define CONFIG_FW_C2H_PKT
#endif /* CONFIG_FW_C2H_PKT */
#define RTW_TX_PA_BIAS /* Adjust TX PA Bias from eFuse */
#ifdef CONFIG_WOWLAN
#define CONFIG_GTK_OL
/*#define CONFIG_ARP_KEEP_ALIVE*/
#ifdef CONFIG_GPIO_WAKEUP
#ifndef WAKEUP_GPIO_IDX
#define WAKEUP_GPIO_IDX 6 /* WIFI Chip Side */
#endif /* !WAKEUP_GPIO_IDX */
#endif /* CONFIG_GPIO_WAKEUP */
#endif /* CONFIG_WOWLAN */
#ifdef CONFIG_CONCURRENT_MODE
#define CONFIG_AP_PORT_SWAP
#define CONFIG_FW_MULTI_PORT_SUPPORT
#endif /* CONFIG_CONCURRENT_MODE */
/*
* Beamforming related definition
*/
/* Only support new beamforming mechanism */
#ifdef CONFIG_BEAMFORMING
#define RTW_BEAMFORMING_VERSION_2
#endif /* CONFIG_BEAMFORMING */
#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
#define CONFIG_RTW_MAC_HIDDEN_RPT
#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */
#ifndef DBG_RX_DFRAME_RAW_DATA
#define DBG_RX_DFRAME_RAW_DATA
#endif /* DBG_RX_DFRAME_RAW_DATA */
#ifndef RTW_IQK_FW_OFFLOAD
/* #define RTW_IQK_FW_OFFLOAD */
#endif /* RTW_IQK_FW_OFFLOAD */
#define CONFIG_ADVANCE_OTA
#ifdef CONFIG_MCC_MODE
#define CONFIG_MCC_MODE_V2
#endif /* CONFIG_MCC_MODE */
#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
#define CONFIG_TDLS_CH_SW_V2
#endif
#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
#ifdef CONFIG_TDLS_CH_SW_V2
#define RTW_CHANNEL_SWITCH_OFFLOAD
#endif
#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
#if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW)
/* Supported since fw v22.1 */
#define RTW_PER_CMD_SUPPORT_FW
#endif /* RTW_PER_CMD_SUPPORT_FW */
#define CONFIG_SUPPORT_FIFO_DUMP
#define CONFIG_HW_P0_TSF_SYNC
#define CONFIG_BCN_RECV_TIME
/*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/
#if defined(CONFIG_TCP_CSUM_OFFLOAD_TX) && !defined(CONFIG_RTW_NETIF_SG)
#define CONFIG_RTW_NETIF_SG
#endif
#define CONFIG_TCP_CSUM_OFFLOAD_RX
#ifdef CONFIG_P2P_PS
#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
#endif
#define CONFIG_RTS_FULL_BW
#ifdef CONFIG_LPS
#define CONFIG_LPS_ACK /* Supported after FW v07 */
#define CONFIG_LPS_1T1R /* Supported after FW v07 */
#endif
#define CONFIG_BT_EFUSE_MASK
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
#endif
#ifndef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
#define CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
#endif
#endif /* CONFIG_RTL8822C */
#ifdef CONFIG_RTL8821C
#undef RTL8821C_SUPPORT
#define RTL8821C_SUPPORT 1
@@ -290,8 +457,6 @@
/*#define DBG_PRE_TX_HANG*/
/* Beamforming related definition */
/* Beamforming mechanism is on driver not phydm, always disable it */
#define BEAMFORMING_SUPPORT 0
/* Only support new beamforming mechanism */
#ifdef CONFIG_BEAMFORMING
#define RTW_BEAMFORMING_VERSION_2
@@ -302,6 +467,14 @@
#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
#endif
#define CONFIG_RTS_FULL_BW
#ifdef CONFIG_LPS
/* #define CONFIG_LPS_ACK */ /* Supported after FW v25 */
#endif
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
#endif
#endif /*CONFIG_RTL8821C*/
#ifdef CONFIG_RTL8710B
@@ -311,6 +484,110 @@
#define CONFIG_FW_C2H_PKT
#endif
#define CONFIG_RTS_FULL_BW
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
#endif
#endif
#ifdef CONFIG_RTL8814B
#undef RTL8814B_SUPPORT
#define RTL8814B_SUPPORT 1
#ifndef CONFIG_FW_C2H_PKT
#define CONFIG_FW_C2H_PKT
#endif /* CONFIG_FW_C2H_PKT */
#define RTW_TX_PA_BIAS /* Adjust TX PA Bias from eFuse */
#define RTW_AMPDU_AGG_RETRY_AND_NEW
#ifdef CONFIG_WOWLAN
#define CONFIG_GTK_OL
/*#define CONFIG_ARP_KEEP_ALIVE*/
#ifdef CONFIG_GPIO_WAKEUP
#ifndef WAKEUP_GPIO_IDX
#define WAKEUP_GPIO_IDX 6 /* WIFI Chip Side */
#endif /* !WAKEUP_GPIO_IDX */
#endif /* CONFIG_GPIO_WAKEUP */
#endif /* CONFIG_WOWLAN */
#ifdef CONFIG_CONCURRENT_MODE
/*#define CONFIG_AP_PORT_SWAP*/
#define CONFIG_FW_MULTI_PORT_SUPPORT
#define CONFIG_SUPPORT_AP_PORT1
#endif /* CONFIG_CONCURRENT_MODE */
/*
* Beamforming related definition
*/
/* Only support new beamforming mechanism */
#ifdef CONFIG_BEAMFORMING
#define RTW_BEAMFORMING_VERSION_2
#endif /* CONFIG_BEAMFORMING */
#ifndef DBG_RX_DFRAME_RAW_DATA
#define DBG_RX_DFRAME_RAW_DATA
#endif /* DBG_RX_DFRAME_RAW_DATA */
#ifndef RTW_IQK_FW_OFFLOAD
#define RTW_IQK_FW_OFFLOAD
#endif /* RTW_IQK_FW_OFFLOAD */
/* Checksum offload feature */
/*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/ /* not ready */
#define CONFIG_TCP_CSUM_OFFLOAD_RX
#define CONFIG_ADVANCE_OTA
#ifdef CONFIG_MCC_MODE
#define CONFIG_MCC_MODE_V2
#define CONFIG_MCC_PHYDM_OFFLOAD
#endif /* CONFIG_MCC_MODE */
#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
#define CONFIG_TDLS_CH_SW_V2
#endif
#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
#ifdef CONFIG_TDLS_CH_SW_V2
#define RTW_CHANNEL_SWITCH_OFFLOAD
#endif
#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
#if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW)
/* Supported since fw v22.1 */
#define RTW_PER_CMD_SUPPORT_FW
#endif /* RTW_PER_CMD_SUPPORT_FW */
#define CONFIG_SUPPORT_FIFO_DUMP
#define CONFIG_HW_P0_TSF_SYNC
#define CONFIG_BCN_RECV_TIME
#ifdef CONFIG_P2P_PS
#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
#endif
#define CONFIG_RTS_FULL_BW
#define CONFIG_PROTSEL_PORT
#define CONFIG_PROTSEL_ATIMDTIM
#define CONFIG_PROTSEL_MACSLEEP
#define CONFIG_HAS_HW_VAR_BCN_CTRL_ADDR
#define CONFIG_HAS_HW_VAR_BCN_FUNC
#define CONFIG_HAS_HW_VAR_MLME_DISCONNECT
#define CONFIG_HAS_HW_VAR_MLME_JOIN
#define CONFIG_HAS_HW_VAR_CORRECT_TSF
#define CONFIG_HAS_TX_BEACON_PAUSE
#define CONFIG_RTW_TX_NPATH_EN /* 8814B is always 4TX */
#ifdef CONFIG_LPS
/* #define CONFIG_LPS_ACK */ /* Supported after FW v04 */
#endif
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
#endif
#ifndef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
#define CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
#endif
#endif /* CONFIG_RTL8814B */
#endif /*__HAL_IC_CFG_H__*/

85
include/hal_intf.h
View File

@@ -40,6 +40,8 @@ enum _CHIP_TYPE {
RTL8821C,
RTL8710B,
RTL8192F,
RTL8822C,
RTL8814B,
MAX_CHIP_TYPE
};
@@ -85,7 +87,6 @@ typedef enum _HW_VARIABLES {
HW_VAR_SEC_CFG,
HW_VAR_SEC_DK_CFG,
HW_VAR_BCN_VALID,
HW_VAR_RF_TYPE,
HW_VAR_FREECNT,
/* PHYDM odm->SupportAbility */
@@ -143,6 +144,8 @@ typedef enum _HW_VARIABLES {
#endif
HW_VAR_RPWM_TOG,
#ifdef CONFIG_GPIO_WAKEUP
HW_VAR_WOW_OUTPUT_GPIO,
HW_VAR_WOW_INPUT_GPIO,
HW_SET_GPIO_WL_CTRL,
#endif
HW_VAR_SYS_CLKR,
@@ -246,9 +249,8 @@ typedef enum _HAL_DEF_VARIABLE {
HAL_DEF_TX_PAGE_SIZE,
HAL_DEF_TX_PAGE_BOUNDARY,
HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN,
HAL_DEF_TX_BUFFER_LAST_ENTRY,
HAL_DEF_ANT_DETECT,/* to do for 8723a */
HAL_DEF_PCI_SUUPORT_L1_BACKDOOR, /* Determine if the L1 Backdoor setting is turned on. */
HAL_DEF_PCI_AMD_L1_SUPPORT,
HAL_DEF_PCI_ASPM_OSC, /* Support for ASPM OSC, added by Roger, 2013.03.27. */
HAL_DEF_EFUSE_USAGE, /* Get current EFUSE utilization. 2008.12.19. Added by Roger. */
HAL_DEF_EFUSE_BYTES,
@@ -339,11 +341,13 @@ struct hal_ops {
#endif
void (*set_chnl_bw_handler)(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80);
void (*set_tx_power_level_handler)(_adapter *padapter, u8 channel);
void (*get_tx_power_level_handler)(_adapter *padapter, s32 *powerlevel);
void (*set_tx_power_level_handler)(_adapter *adapter, u8 channel);
void (*set_txpwr_done)(_adapter *adapter);
void (*set_tx_power_index_handler)(_adapter *adapter, u32 powerindex, enum rf_path rfpath, u8 rate);
void (*set_tx_power_index_handler)(_adapter *padapter, u32 powerindex, enum rf_path rfpath, u8 rate);
u8 (*get_tx_power_index_handler)(_adapter *padapter, enum rf_path rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic);
u8 (*get_tx_power_index_handler)(_adapter *adapter, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate
, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch, struct txpwr_idx_comp *tic);
s8 (*get_txpwr_target_extra_bias)(_adapter *adapter, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch);
void (*hal_dm_watchdog)(_adapter *padapter);
@@ -353,12 +357,12 @@ struct hal_ops {
u8 (*get_hal_def_var_handler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
u8 (*get_hal_def_var_handler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
u8(*SetHalDefVarHandler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
u8(*SetHalDefVarHandler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
void (*GetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, PVOID pValue2);
void (*SetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet);
void (*GetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2);
void (*SetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet);
void (*SetBeaconRelatedRegistersHandler)(_adapter *padapter);
@@ -445,7 +449,9 @@ struct hal_ops {
#ifdef CONFIG_RFKILL_POLL
bool (*hal_radio_onoff_check)(_adapter *adapter, u8 *valid);
#endif
#ifdef CONFIG_PCI_TX_POLLING
void (*tx_poll_handler)(_adapter *adapter);
#endif
};
typedef enum _RT_EEPROM_TYPE {
@@ -506,6 +512,12 @@ typedef enum _HARDWARE_TYPE {
HARDWARE_TYPE_RTL8192FS,
HARDWARE_TYPE_RTL8192FU,
HARDWARE_TYPE_RTL8192FE,
HARDWARE_TYPE_RTL8822CE,
HARDWARE_TYPE_RTL8822CU,
HARDWARE_TYPE_RTL8822CS,
HARDWARE_TYPE_RTL8814BE,
HARDWARE_TYPE_RTL8814BU,
HARDWARE_TYPE_RTL8814BS,
HARDWARE_TYPE_MAX,
} HARDWARE_TYPE;
@@ -626,12 +638,29 @@ typedef enum _HARDWARE_TYPE {
#define IS_HARDWARE_TYPE_8821C(_Adapter) \
(IS_HARDWARE_TYPE_8821CE(_Adapter) || IS_HARDWARE_TYPE_8821CU(_Adapter) || IS_HARDWARE_TYPE_8821CS(_Adapter))
#define IS_HARDWARE_TYPE_8822CE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CE)
#define IS_HARDWARE_TYPE_8822CU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CU)
#define IS_HARDWARE_TYPE_8822CS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CS)
#define IS_HARDWARE_TYPE_8822C(_Adapter) \
(IS_HARDWARE_TYPE_8822CE(_Adapter) || IS_HARDWARE_TYPE_8822CU(_Adapter) || IS_HARDWARE_TYPE_8822CS(_Adapter))
#define IS_HARDWARE_TYPE_8814BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BE)
#define IS_HARDWARE_TYPE_8814BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BU)
#define IS_HARDWARE_TYPE_8814BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BS)
#define IS_HARDWARE_TYPE_8814B(_Adapter) \
(IS_HARDWARE_TYPE_8814BE(_Adapter) || IS_HARDWARE_TYPE_8814BU(_Adapter) || IS_HARDWARE_TYPE_8814BS(_Adapter))
#define IS_HARDWARE_TYPE_JAGUAR2(_Adapter) \
(IS_HARDWARE_TYPE_8814A(_Adapter) || IS_HARDWARE_TYPE_8821B(_Adapter) || IS_HARDWARE_TYPE_8822B(_Adapter) || IS_HARDWARE_TYPE_8821C(_Adapter))
#define IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(_Adapter) \
(IS_HARDWARE_TYPE_JAGUAR(_Adapter) || IS_HARDWARE_TYPE_JAGUAR2(_Adapter))
#define IS_HARDWARE_TYPE_JAGUAR3(_Adapter) \
(IS_HARDWARE_TYPE_8814B(_Adapter) || IS_HARDWARE_TYPE_8822C(_Adapter))
#define IS_HARDWARE_TYPE_JAGUAR_ALL(_Adapter) \
(IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(_Adapter) || IS_HARDWARE_TYPE_JAGUAR3(_Adapter))
typedef enum _wowlan_subcode {
@@ -668,6 +697,13 @@ uint rtw_hal_init(_adapter *padapter);
#ifdef CONFIG_NEW_NETDEV_HDL
uint rtw_hal_iface_init(_adapter *adapter);
#endif
enum rf_type rtw_chip_rftype_to_hal_rftype(_adapter *adapter, u8 limit);
void dump_hal_runtime_trx_mode(void *sel, _adapter *adapter);
void dump_hal_trx_mode(void *sel, _adapter *adapter);
u8 rtw_hal_rfpath_init(_adapter *adapter);
u8 rtw_hal_trxnss_init(_adapter *adapter);
uint rtw_hal_deinit(_adapter *padapter);
void rtw_hal_stop(_adapter *padapter);
u8 rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val);
@@ -677,11 +713,11 @@ void rtw_hal_chip_configure(_adapter *padapter);
u8 rtw_hal_read_chip_info(_adapter *padapter);
void rtw_hal_read_chip_version(_adapter *padapter);
u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue);
u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet);
void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, PVOID pValue2);
void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet);
void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2);
void rtw_hal_enable_interrupt(_adapter *padapter);
void rtw_hal_disable_interrupt(_adapter *padapter);
@@ -755,9 +791,6 @@ void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Band
void rtw_hal_dm_watchdog(_adapter *padapter);
void rtw_hal_dm_watchdog_in_lps(_adapter *padapter);
void rtw_hal_set_tx_power_level(_adapter *padapter, u8 channel);
void rtw_hal_get_tx_power_level(_adapter *padapter, s32 *powerlevel);
#ifdef CONFIG_HOSTAPD_MLME
s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
#endif
@@ -828,9 +861,17 @@ s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan);
void rtw_hal_clear_interrupt(_adapter *padapter);
#endif
void rtw_hal_set_tx_power_index(PADAPTER adapter, u32 powerindex, enum rf_path rfpath, u8 rate);
u8 rtw_hal_get_tx_power_index(PADAPTER adapter, enum rf_path
rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic);
void rtw_hal_set_tx_power_level(_adapter *adapter, u8 channel);
void rtw_hal_update_txpwr_level(_adapter *adapter);
void rtw_hal_set_txpwr_done(_adapter *adapter);
void rtw_hal_set_tx_power_index(_adapter *adapter, u32 powerindex
, enum rf_path rfpath, u8 rate);
u8 rtw_hal_get_tx_power_index(_adapter *adapter, enum rf_path rfpath
, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch
, struct txpwr_idx_comp *tic);
s8 rtw_hal_get_txpwr_target_extra_bias(_adapter *adapter, enum rf_path rfpath
, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch);
u8 rtw_hal_ops_check(_adapter *padapter);

110
include/hal_pg.h Normal file → Executable file
View File

@@ -581,6 +581,50 @@
#define EEPROM_MAC_ADDR_8723DS 0x11A
#define EEPROM_Voltage_ADDR_8723D 0x8
/*
* ====================================================
* EEPROM/Efuse PG Offset for 8822C
* ====================================================
*/
#define EEPROM_TX_PWR_INX_8822C 0x10
#define EEPROM_ChannelPlan_8822C 0xB8
#define EEPROM_XTAL_8822C 0xB9
#define EEPROM_IQK_LCK_8822C 0xBB
#define EEPROM_2G_5G_PA_TYPE_8822C 0xBC
/* PATH A & PATH B */
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822C 0xBD
/* PATH C & PATH D */
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8822C 0xBE
/* PATH A & PATH B */
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822C 0xBF
/* PATH C & PATH D */
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8822C 0xC0
#define EEPROM_RF_BOARD_OPTION_8822C 0xC1
#define EEPROM_FEATURE_OPTION_8822C 0xC2
#define EEPROM_RF_BT_SETTING_8822C 0xC3
#define EEPROM_VERSION_8822C 0xC4
#define EEPROM_CustomID_8822C 0xC5
#define EEPROM_TX_BBSWING_2G_8822C 0xC6
#define EEPROM_TX_PWR_CALIBRATE_RATE_8822C 0xC8
#define EEPROM_RF_ANTENNA_OPT_8822C 0xC9
#define EEPROM_RFE_OPTION_8822C 0xCA
#define EEPROM_COUNTRY_CODE_8822C 0xCB
#define EEPROM_THERMAL_METER_A_8822C 0xD0
#define EEPROM_THERMAL_METER_B_8822C 0xD1
/* RTL8822CU */
#define EEPROM_MAC_ADDR_8822CU 0x157
#define EEPROM_VID_8822CU 0x100
#define EEPROM_PID_8822CU 0x102
#define EEPROM_USB_OPTIONAL_FUNCTION0_8822CU 0x104
#define EEPROM_USB_MODE_8822CU 0x06
/* RTL8822CS */
#define EEPROM_MAC_ADDR_8822CS 0x16A
/* RTL8822CE */
#define EEPROM_MAC_ADDR_8822CE 0x120
/* ****************************************************
* EEPROM/Efuse PG Offset for 8192F
* **************************************************** */
@@ -652,6 +696,47 @@
#define EEPROM_VID_8710BU 0x1C0
#define EEPROM_PID_8710BU 0x1C2
/* ****************************************************
* EEPROM/Efuse PG Offset for 8814B
* **************************************************** */
#define EEPROM_USB_MODE_8814BU 0x06
/* 0x10 ~ 0x63 = TX power area. */
#define EEPROM_TX_PWR_INX_8814B 0x10
#define EEPROM_ChannelPlan_8814B 0xB8
#define EEPROM_XTAL_8814B 0xB9
#define EEPROM_THERMAL_METER_8814B 0xBA
#define EEPROM_IQK_LCK_8814B 0xBB
#define EEPROM_PA_TYPE_8814B 0xBC
#define EEPROM_LNA_TYPE_AB_2G_8814B 0xBD
#define EEPROM_LNA_TYPE_CD_2G_8814B 0xBE
#define EEPROM_LNA_TYPE_AB_5G_8814B 0xBF
#define EEPROM_LNA_TYPE_CD_5G_8814B 0xC0
#define EEPROM_RF_BOARD_OPTION_8814B 0xC1
#define EEPROM_RF_FEATURE_OPTION_8814B 0xC2
#define EEPROM_RF_BT_SETTING_8814B 0xC3
#define EEPROM_VERSION_8814B 0xC4
#define EEPROM_CustomID_8814B 0xC5
#define EEPROM_TX_BBSWING_2G_8814B 0xC6
#define EEPROM_TX_BBSWING_5G_8814B 0xC7
#define EEPROM_TX_PWR_CALIBRATE_RATE_8814B 0xC8
#define EEPROM_RF_ANTENNA_OPT_8814B 0xC9
#define EEPROM_RFE_OPTION_8814B 0xCA
#define EEPROM_COUNTRY_CODE_8814B 0xCB
#define EEPROM_MAC_ADDR_8814BE 0x120
#define EEPROM_VID_8814B 0x126
#define EEPROM_DID_8814B 0x128
#define EEPROM_SVID_8814B 0x12A
#define EEPROM_SMID_8814B 0x12C
/* RTL8814BU */
#define EEPROM_MAC_ADDR_8814BU 0x157
#define EEPROM_VID_8814BU 0x150
#define EEPROM_PID_8814BU 0x152
#define EEPROM_USB_OPTIONAL_FUNCTION0_8814BU 0x154
/* ****************************************************
* EEPROM/Efuse Value Type
* **************************************************** */
@@ -720,6 +805,8 @@
#define EEPROM_Default_CrystalCap_8188F 0x20
#define EEPROM_Default_CrystalCap_8188GTV 0x20
#define EEPROM_Default_CrystalCap_8192F 0x20
#define EEPROM_Default_CrystalCap_8822C 0x3F
#define EEPROM_Default_CrystalCap_8814B 0x40
#define EEPROM_Default_CrystalFreq 0x0
#define EEPROM_Default_TxPowerLevel_92C 0x22
#define EEPROM_Default_TxPowerLevel_2G 0x2C
@@ -825,27 +912,6 @@
/* It must always set to 4, otherwise read efuse table sequence will be wrong. */
#define MAX_TX_COUNT 4
typedef struct _TxPowerInfo24G {
u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
/* If only one tx, only BW20 and OFDM are used. */
s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
} TxPowerInfo24G, *PTxPowerInfo24G;
typedef struct _TxPowerInfo5G {
u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
/* If only one tx, only BW20, OFDM, BW80 and BW160 are used. */
s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW80_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW160_Diff[MAX_RF_PATH][MAX_TX_COUNT];
} TxPowerInfo5G, *PTxPowerInfo5G;
typedef enum _BT_Ant_NUM {
Ant_x2 = 0,
Ant_x1 = 1
@@ -869,6 +935,8 @@ typedef enum _BT_CoType {
BT_RTL8723D = 14,
BT_RTL8821C = 15,
BT_RTL8192F = 16,
BT_RTL8822C = 17,
BT_RTL8814B = 18,
} BT_CoType, *PBT_CoType;
typedef enum _BT_RadioShared {

70
include/hal_phy.h
View File

@@ -174,61 +174,61 @@ typedef struct RF_Shadow_Compare_Map {
u32
PHY_RFShadowRead(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 Offset);
PADAPTER Adapter,
enum rf_path eRFPath,
u32 Offset);
VOID
void
PHY_RFShadowWrite(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 Offset,
IN u32 Data);
PADAPTER Adapter,
enum rf_path eRFPath,
u32 Offset,
u32 Data);
BOOLEAN
PHY_RFShadowCompare(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 Offset);
PADAPTER Adapter,
enum rf_path eRFPath,
u32 Offset);
VOID
void
PHY_RFShadowRecorver(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 Offset);
PADAPTER Adapter,
enum rf_path eRFPath,
u32 Offset);
VOID
void
PHY_RFShadowCompareAll(
IN PADAPTER Adapter);
PADAPTER Adapter);
VOID
void
PHY_RFShadowRecorverAll(
IN PADAPTER Adapter);
PADAPTER Adapter);
VOID
void
PHY_RFShadowCompareFlagSet(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 Offset,
IN u8 Type);
PADAPTER Adapter,
enum rf_path eRFPath,
u32 Offset,
u8 Type);
VOID
void
PHY_RFShadowRecorverFlagSet(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 Offset,
IN u8 Type);
PADAPTER Adapter,
enum rf_path eRFPath,
u32 Offset,
u8 Type);
VOID
void
PHY_RFShadowCompareFlagSetAll(
IN PADAPTER Adapter);
PADAPTER Adapter);
VOID
void
PHY_RFShadowRecorverFlagSetAll(
IN PADAPTER Adapter);
PADAPTER Adapter);
VOID
void
PHY_RFShadowRefresh(
IN PADAPTER Adapter);
PADAPTER Adapter);
#endif /*#CONFIG_RF_SHADOW_RW*/
#endif /* __HAL_COMMON_H__ */

255
include/hal_phy_reg.h
View File

@@ -15,11 +15,256 @@
#ifndef __HAL_PHY_REG_H__
#define __HAL_PHY_REG_H__
/* for PutRFRegsetting & GetRFRegSetting BitMask
* #if (RTL92SE_FPGA_VERIFY == 1)
* #define bRFRegOffsetMask 0xfff
* #else */
/* for PutRFRegsetting & GetRFRegSetting BitMask*/
#define bRFRegOffsetMask 0xfffff
/* #endif */
/* alias for phydm coding style */
#define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance
#define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold
#define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack
#define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage
#define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1
#define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1
#define REG_A_TX_SCALE_JAGUAR rA_TxScale_Jaguar
#define REG_B_TX_SCALE_JAGUAR rB_TxScale_Jaguar
#define REG_FPGA0_XAB_RF_INTERFACE_SW rFPGA0_XAB_RFInterfaceSW
#define REG_FPGA0_XAB_RF_PARAMETER rFPGA0_XAB_RFParameter
#define REG_FPGA0_XA_HSSI_PARAMETER1 rFPGA0_XA_HSSIParameter1
#define REG_FPGA0_XA_LSSI_PARAMETER rFPGA0_XA_LSSIParameter
#define REG_FPGA0_XA_RF_INTERFACE_OE rFPGA0_XA_RFInterfaceOE
#define REG_FPGA0_XB_HSSI_PARAMETER1 rFPGA0_XB_HSSIParameter1
#define REG_FPGA0_XB_LSSI_PARAMETER rFPGA0_XB_LSSIParameter
#define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack
#define REG_FPGA0_XB_RF_INTERFACE_OE rFPGA0_XB_RFInterfaceOE
#define REG_FPGA0_XCD_RF_INTERFACE_SW rFPGA0_XCD_RFInterfaceSW
#define REG_FPGA0_XCD_SWITCH_CONTROL rFPGA0_XCD_SwitchControl
#define REG_FPGA1_TX_BLOCK rFPGA1_TxBlock
#define REG_FPGA1_TX_INFO rFPGA1_TxInfo
#define REG_IQK_AGC_CONT rIQK_AGC_Cont
#define REG_IQK_AGC_PTS rIQK_AGC_Pts
#define REG_IQK_AGC_RSP rIQK_AGC_Rsp
#define REG_OFDM_0_AGC_RSSI_TABLE rOFDM0_AGCRSSITable
#define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold
#define REG_OFDM_0_RX_IQ_EXT_ANTA rOFDM0_RxIQExtAnta
#define REG_OFDM_0_TR_MUX_PAR rOFDM0_TRMuxPar
#define REG_OFDM_0_TRX_PATH_ENABLE rOFDM0_TRxPathEnable
#define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1
#define REG_OFDM_0_XA_RX_IQ_IMBALANCE rOFDM0_XARxIQImbalance
#define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance
#define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1
#define REG_OFDM_0_XB_RX_IQ_IMBALANCE rOFDM0_XBRxIQImbalance
#define REG_OFDM_0_XB_TX_IQ_IMBALANCE rOFDM0_XBTxIQImbalance
#define REG_OFDM_0_XC_TX_AFE rOFDM0_XCTxAFE
#define REG_OFDM_0_XD_TX_AFE rOFDM0_XDTxAFE
/*#define REG_A_CFO_LONG_DUMP_92E rA_CfoLongDump_92E*/
#define REG_A_CFO_LONG_DUMP_JAGUAR rA_CfoLongDump_Jaguar
/*#define REG_A_CFO_SHORT_DUMP_92E rA_CfoShortDump_92E*/
#define REG_A_CFO_SHORT_DUMP_JAGUAR rA_CfoShortDump_Jaguar
#define REG_A_RFE_PINMUX_JAGUAR rA_RFE_Pinmux_Jaguar
/*#define REG_A_RSSI_DUMP_92E rA_RSSIDump_92E*/
#define REG_A_RSSI_DUMP_JAGUAR rA_RSSIDump_Jaguar
/*#define REG_A_RX_SNR_DUMP_92E rA_RXsnrDump_92E*/
#define REG_A_RX_SNR_DUMP_JAGUAR rA_RXsnrDump_Jaguar
/*#define REG_A_TX_AGC rA_TXAGC*/
#define REG_A_TX_SCALE_JAGUAR rA_TxScale_Jaguar
#define REG_BW_INDICATION_JAGUAR rBWIndication_Jaguar
/*#define REG_B_BBSWING rB_BBSWING*/
/*#define REG_B_CFO_LONG_DUMP_92E rB_CfoLongDump_92E*/
#define REG_B_CFO_LONG_DUMP_JAGUAR rB_CfoLongDump_Jaguar
/*#define REG_B_CFO_SHORT_DUMP_92E rB_CfoShortDump_92E*/
#define REG_B_CFO_SHORT_DUMP_JAGUAR rB_CfoShortDump_Jaguar
/*#define REG_B_RSSI_DUMP_92E rB_RSSIDump_92E*/
#define REG_B_RSSI_DUMP_JAGUAR rB_RSSIDump_Jaguar
/*#define REG_B_RX_SNR_DUMP_92E rB_RXsnrDump_92E*/
#define REG_B_RX_SNR_DUMP_JAGUAR rB_RXsnrDump_Jaguar
/*#define REG_B_TX_AGC rB_TXAGC*/
#define REG_B_TX_SCALE_JAGUAR rB_TxScale_Jaguar
#define REG_BLUE_TOOTH rBlue_Tooth
#define REG_CCK_0_AFE_SETTING rCCK0_AFESetting
/*#define REG_C_BBSWING rC_BBSWING*/
/*#define REG_C_TX_AGC rC_TXAGC*/
#define REG_C_TX_SCALE_JAGUAR2 rC_TxScale_Jaguar2
#define REG_CONFIG_ANT_A rConfig_AntA
#define REG_CONFIG_ANT_B rConfig_AntB
#define REG_CONFIG_PMPD_ANT_A rConfig_Pmpd_AntA
#define REG_CONFIG_PMPD_ANT_B rConfig_Pmpd_AntB
#define REG_DPDT_CONTROL rDPDT_control
/*#define REG_D_BBSWING rD_BBSWING*/
/*#define REG_D_TX_AGC rD_TXAGC*/
#define REG_D_TX_SCALE_JAGUAR2 rD_TxScale_Jaguar2
#define REG_FPGA0_ANALOG_PARAMETER4 rFPGA0_AnalogParameter4
#define REG_FPGA0_IQK rFPGA0_IQK
#define REG_FPGA0_PSD_FUNCTION rFPGA0_PSDFunction
#define REG_FPGA0_PSD_REPORT rFPGA0_PSDReport
#define REG_FPGA0_RFMOD rFPGA0_RFMOD
#define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage
#define REG_FPGA0_XAB_RF_INTERFACE_SW rFPGA0_XAB_RFInterfaceSW
#define REG_FPGA0_XAB_RF_PARAMETER rFPGA0_XAB_RFParameter
#define REG_FPGA0_XA_HSSI_PARAMETER1 rFPGA0_XA_HSSIParameter1
#define REG_FPGA0_XA_LSSI_PARAMETER rFPGA0_XA_LSSIParameter
#define REG_FPGA0_XA_RF_INTERFACE_OE rFPGA0_XA_RFInterfaceOE
#define REG_FPGA0_XB_HSSI_PARAMETER1 rFPGA0_XB_HSSIParameter1
#define REG_FPGA0_XB_LSSI_PARAMETER rFPGA0_XB_LSSIParameter
#define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack
#define REG_FPGA0_XB_RF_INTERFACE_OE rFPGA0_XB_RFInterfaceOE
#define REG_FPGA0_XCD_RF_INTERFACE_SW rFPGA0_XCD_RFInterfaceSW
#define REG_FPGA0_XCD_SWITCH_CONTROL rFPGA0_XCD_SwitchControl
#define REG_FPGA1_TX_BLOCK rFPGA1_TxBlock
#define REG_FPGA1_TX_INFO rFPGA1_TxInfo
#define REG_IQK_AGC_CONT rIQK_AGC_Cont
#define REG_IQK_AGC_PTS rIQK_AGC_Pts
#define REG_IQK_AGC_RSP rIQK_AGC_Rsp
#define REG_OFDM_0_AGC_RSSI_TABLE rOFDM0_AGCRSSITable
#define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold
#define REG_OFDM_0_RX_IQ_EXT_ANTA rOFDM0_RxIQExtAnta
#define REG_OFDM_0_TR_MUX_PAR rOFDM0_TRMuxPar
#define REG_OFDM_0_TRX_PATH_ENABLE rOFDM0_TRxPathEnable
#define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1
#define REG_OFDM_0_XA_RX_IQ_IMBALANCE rOFDM0_XARxIQImbalance
#define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance
#define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1
#define REG_OFDM_0_XB_RX_IQ_IMBALANCE rOFDM0_XBRxIQImbalance
#define REG_OFDM_0_XB_TX_IQ_IMBALANCE rOFDM0_XBTxIQImbalance
#define REG_OFDM_0_XC_TX_AFE rOFDM0_XCTxAFE
#define REG_OFDM_0_XD_TX_AFE rOFDM0_XDTxAFE
#define REG_PMPD_ANAEN rPMPD_ANAEN
#define REG_PDP_ANT_A rPdp_AntA
#define REG_PDP_ANT_A_4 rPdp_AntA_4
#define REG_PDP_ANT_B rPdp_AntB
#define REG_PDP_ANT_B_4 rPdp_AntB_4
#define REG_PWED_TH_JAGUAR rPwed_TH_Jaguar
#define REG_RX_CCK rRx_CCK
#define REG_RX_IQK rRx_IQK
#define REG_RX_IQK_PI_A rRx_IQK_PI_A
#define REG_RX_IQK_PI_B rRx_IQK_PI_B
#define REG_RX_IQK_TONE_A rRx_IQK_Tone_A
#define REG_RX_IQK_TONE_B rRx_IQK_Tone_B
#define REG_RX_OFDM rRx_OFDM
#define REG_RX_POWER_AFTER_IQK_A_2 rRx_Power_After_IQK_A_2
#define REG_RX_POWER_AFTER_IQK_B_2 rRx_Power_After_IQK_B_2
#define REG_RX_POWER_BEFORE_IQK_A_2 rRx_Power_Before_IQK_A_2
#define REG_RX_POWER_BEFORE_IQK_B_2 rRx_Power_Before_IQK_B_2
#define REG_RX_TO_RX rRx_TO_Rx
#define REG_RX_WAIT_CCA rRx_Wait_CCA
#define REG_RX_WAIT_RIFS rRx_Wait_RIFS
#define REG_S0_S1_PATH_SWITCH rS0S1_PathSwitch
/*#define REG_S1_RXEVM_DUMP_92E rS1_RXevmDump_92E*/
#define REG_S1_RXEVM_DUMP_JAGUAR rS1_RXevmDump_Jaguar
/*#define REG_S2_RXEVM_DUMP_92E rS2_RXevmDump_92E*/
#define REG_S2_RXEVM_DUMP_JAGUAR rS2_RXevmDump_Jaguar
#define REG_SYM_WLBT_PAPE_SEL rSYM_WLBT_PAPE_SEL
#define REG_SINGLE_TONE_CONT_TX_JAGUAR rSingleTone_ContTx_Jaguar
#define REG_SLEEP rSleep
#define REG_STANDBY rStandby
#define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR rTxAGC_A_CCK11_CCK1_JAguar
#define REG_TX_AGC_A_CCK_1_MCS32 rTxAGC_A_CCK1_Mcs32
#define REG_TX_AGC_A_MCS11_MCS8_JAGUAR rTxAGC_A_MCS11_MCS8_JAguar
#define REG_TX_AGC_A_MCS15_MCS12_JAGUAR rTxAGC_A_MCS15_MCS12_JAguar
#define REG_TX_AGC_A_MCS19_MCS16_JAGUAR rTxAGC_A_MCS19_MCS16_JAguar
#define REG_TX_AGC_A_MCS23_MCS20_JAGUAR rTxAGC_A_MCS23_MCS20_JAguar
#define REG_TX_AGC_A_MCS3_MCS0_JAGUAR rTxAGC_A_MCS3_MCS0_JAguar
#define REG_TX_AGC_A_MCS7_MCS4_JAGUAR rTxAGC_A_MCS7_MCS4_JAguar
#define REG_TX_AGC_A_MCS03_MCS00 rTxAGC_A_Mcs03_Mcs00
#define REG_TX_AGC_A_MCS07_MCS04 rTxAGC_A_Mcs07_Mcs04
#define REG_TX_AGC_A_MCS11_MCS08 rTxAGC_A_Mcs11_Mcs08
#define REG_TX_AGC_A_MCS15_MCS12 rTxAGC_A_Mcs15_Mcs12
#define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_A_Nss1Index3_Nss1Index0_JAguar
#define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_A_Nss1Index7_Nss1Index4_JAguar
#define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_A_Nss2Index1_Nss1Index8_JAguar
#define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_A_Nss2Index5_Nss2Index2_JAguar
#define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_A_Nss2Index9_Nss2Index6_JAguar
#define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_A_Nss3Index3_Nss3Index0_JAguar
#define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_A_Nss3Index7_Nss3Index4_JAguar
#define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_A_Nss3Index9_Nss3Index8_JAguar
#define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR rTxAGC_A_Ofdm18_Ofdm6_JAguar
#define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR rTxAGC_A_Ofdm54_Ofdm24_JAguar
#define REG_TX_AGC_A_RATE18_06 rTxAGC_A_Rate18_06
#define REG_TX_AGC_A_RATE54_24 rTxAGC_A_Rate54_24
#define REG_TX_AGC_B_CCK_11_A_CCK_2_11 rTxAGC_B_CCK11_A_CCK2_11
#define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR rTxAGC_B_CCK11_CCK1_JAguar
#define REG_TX_AGC_B_CCK_1_55_MCS32 rTxAGC_B_CCK1_55_Mcs32
#define REG_TX_AGC_B_MCS11_MCS8_JAGUAR rTxAGC_B_MCS11_MCS8_JAguar
#define REG_TX_AGC_B_MCS15_MCS12_JAGUAR rTxAGC_B_MCS15_MCS12_JAguar
#define REG_TX_AGC_B_MCS19_MCS16_JAGUAR rTxAGC_B_MCS19_MCS16_JAguar
#define REG_TX_AGC_B_MCS23_MCS20_JAGUAR rTxAGC_B_MCS23_MCS20_JAguar
#define REG_TX_AGC_B_MCS3_MCS0_JAGUAR rTxAGC_B_MCS3_MCS0_JAguar
#define REG_TX_AGC_B_MCS7_MCS4_JAGUAR rTxAGC_B_MCS7_MCS4_JAguar
#define REG_TX_AGC_B_MCS03_MCS00 rTxAGC_B_Mcs03_Mcs00
#define REG_TX_AGC_B_MCS07_MCS04 rTxAGC_B_Mcs07_Mcs04
#define REG_TX_AGC_B_MCS11_MCS08 rTxAGC_B_Mcs11_Mcs08
#define REG_TX_AGC_B_MCS15_MCS12 rTxAGC_B_Mcs15_Mcs12
#define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_B_Nss1Index3_Nss1Index0_JAguar
#define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_B_Nss1Index7_Nss1Index4_JAguar
#define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_B_Nss2Index1_Nss1Index8_JAguar
#define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_B_Nss2Index5_Nss2Index2_JAguar
#define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_B_Nss2Index9_Nss2Index6_JAguar
#define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_B_Nss3Index3_Nss3Index0_JAguar
#define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_B_Nss3Index7_Nss3Index4_JAguar
#define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_B_Nss3Index9_Nss3Index8_JAguar
#define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR rTxAGC_B_Ofdm18_Ofdm6_JAguar
#define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR rTxAGC_B_Ofdm54_Ofdm24_JAguar
#define REG_TX_AGC_B_RATE18_06 rTxAGC_B_Rate18_06
#define REG_TX_AGC_B_RATE54_24 rTxAGC_B_Rate54_24
#define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR rTxAGC_C_CCK11_CCK1_JAguar
#define REG_TX_AGC_C_MCS11_MCS8_JAGUAR rTxAGC_C_MCS11_MCS8_JAguar
#define REG_TX_AGC_C_MCS15_MCS12_JAGUAR rTxAGC_C_MCS15_MCS12_JAguar
#define REG_TX_AGC_C_MCS19_MCS16_JAGUAR rTxAGC_C_MCS19_MCS16_JAguar
#define REG_TX_AGC_C_MCS23_MCS20_JAGUAR rTxAGC_C_MCS23_MCS20_JAguar
#define REG_TX_AGC_C_MCS3_MCS0_JAGUAR rTxAGC_C_MCS3_MCS0_JAguar
#define REG_TX_AGC_C_MCS7_MCS4_JAGUAR rTxAGC_C_MCS7_MCS4_JAguar
#define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_C_Nss1Index3_Nss1Index0_JAguar
#define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_C_Nss1Index7_Nss1Index4_JAguar
#define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_C_Nss2Index1_Nss1Index8_JAguar
#define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_C_Nss2Index5_Nss2Index2_JAguar
#define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_C_Nss2Index9_Nss2Index6_JAguar
#define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_C_Nss3Index3_Nss3Index0_JAguar
#define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_C_Nss3Index7_Nss3Index4_JAguar
#define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_C_Nss3Index9_Nss3Index8_JAguar
#define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR rTxAGC_C_Ofdm18_Ofdm6_JAguar
#define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR rTxAGC_C_Ofdm54_Ofdm24_JAguar
#define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR rTxAGC_D_CCK11_CCK1_JAguar
#define REG_TX_AGC_D_MCS11_MCS8_JAGUAR rTxAGC_D_MCS11_MCS8_JAguar
#define REG_TX_AGC_D_MCS15_MCS12_JAGUAR rTxAGC_D_MCS15_MCS12_JAguar
#define REG_TX_AGC_D_MCS19_MCS16_JAGUAR rTxAGC_D_MCS19_MCS16_JAguar
#define REG_TX_AGC_D_MCS23_MCS20_JAGUAR rTxAGC_D_MCS23_MCS20_JAguar
#define REG_TX_AGC_D_MCS3_MCS0_JAGUAR rTxAGC_D_MCS3_MCS0_JAguar
#define REG_TX_AGC_D_MCS7_MCS4_JAGUAR rTxAGC_D_MCS7_MCS4_JAguar
#define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_D_Nss1Index3_Nss1Index0_JAguar
#define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_D_Nss1Index7_Nss1Index4_JAguar
#define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_D_Nss2Index1_Nss1Index8_JAguar
#define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_D_Nss2Index5_Nss2Index2_JAguar
#define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_D_Nss2Index9_Nss2Index6_JAguar
#define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_D_Nss3Index3_Nss3Index0_JAguar
#define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_D_Nss3Index7_Nss3Index4_JAguar
#define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_D_Nss3Index9_Nss3Index8_JAguar
#define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR rTxAGC_D_Ofdm18_Ofdm6_JAguar
#define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR rTxAGC_D_Ofdm54_Ofdm24_JAguar
#define REG_TX_PATH_JAGUAR rTxPath_Jaguar
#define REG_TX_CCK_BBON rTx_CCK_BBON
#define REG_TX_CCK_RFON rTx_CCK_RFON
#define REG_TX_IQK rTx_IQK
#define REG_TX_IQK_PI_A rTx_IQK_PI_A
#define REG_TX_IQK_PI_B rTx_IQK_PI_B
#define REG_TX_IQK_TONE_A rTx_IQK_Tone_A
#define REG_TX_IQK_TONE_B rTx_IQK_Tone_B
#define REG_TX_OFDM_BBON rTx_OFDM_BBON
#define REG_TX_OFDM_RFON rTx_OFDM_RFON
#define REG_TX_POWER_AFTER_IQK_A rTx_Power_After_IQK_A
#define REG_TX_POWER_AFTER_IQK_B rTx_Power_After_IQK_B
#define REG_TX_POWER_BEFORE_IQK_A rTx_Power_Before_IQK_A
#define REG_TX_POWER_BEFORE_IQK_B rTx_Power_Before_IQK_B
#define REG_TX_TO_RX rTx_To_Rx
#define REG_TX_TO_TX rTx_To_Tx
#define REG_APK rAPK
#define REG_ANTSEL_SW_JAGUAR r_ANTSEL_SW_Jaguar
#define rf_welut_jaguar RF_WeLut_Jaguar
#define rf_mode_table_addr RF_ModeTableAddr
#define rf_mode_table_data0 RF_ModeTableData0
#define rf_mode_table_data1 RF_ModeTableData1
#define RX_SMOOTH_FACTOR Rx_Smooth_Factor
#endif /* __HAL_PHY_REG_H__ */

28
include/hal_sdio.h
View File

@@ -17,6 +17,11 @@
#define ffaddr2deviceId(pdvobj, addr) (pdvobj->Queue2Pipe[addr])
#ifndef RTW_HALMAC
extern const char *_sdio_tx_queue_str[];
#define sdio_tx_queue_str(_page_idx) (_page_idx >= SDIO_MAX_TX_QUEUE ? "UNKNOWN" : _sdio_tx_queue_str[_page_idx])
#endif
u8 rtw_hal_sdio_max_txoqt_free_space(_adapter *padapter);
u8 rtw_hal_sdio_query_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
void rtw_hal_sdio_update_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
@@ -24,6 +29,13 @@ void rtw_hal_set_sdio_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 nu
u32 rtw_hal_get_sdio_tx_max_length(PADAPTER padapter, u8 queue_idx);
bool sdio_power_on_check(PADAPTER padapter);
#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8821A)
void rtw_hal_sdio_avail_page_threshold_init(_adapter *adapter);
void rtw_hal_sdio_avail_page_threshold_en(_adapter *adapter, u8 qidx);
#endif
#endif /* CONFIG_SDIO_TX_ENABLE_AVAL_INT */
#ifdef CONFIG_FW_C2H_REG
void sd_c2h_hisr_hdl(_adapter *adapter);
#endif
@@ -53,4 +65,20 @@ s32 sdio_iwrite32(struct intf_hdl *pintfhdl, u32 addr, u32 val);
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
u32 cmd53_4byte_alignment(struct intf_hdl *pintfhdl, u32 addr);
#ifndef CONFIG_SDIO_TX_TASKLET
#ifdef SDIO_FREE_XMIT_BUF_SEMA
void _rtw_sdio_free_xmitbuf_sema_up(struct xmit_priv *xmit);
void _rtw_sdio_free_xmitbuf_sema_down(struct xmit_priv *xmit);
#ifdef DBG_SDIO_FREE_XMIT_BUF_SEMA
void dbg_rtw_sdio_free_xmitbuf_sema_up(struct xmit_priv *xmit, const char *caller);
void dbg_rtw_sdio_free_xmitbuf_sema_down(struct xmit_priv *xmit, const char *caller);
#define rtw_sdio_free_xmitbuf_sema_up(_xmit) dbg_rtw_sdio_free_xmitbuf_sema_up(_xmit, __func__)
#define rtw_sdio_free_xmitbuf_sema_down(_xmit) dbg_rtw_sdio_free_xmitbuf_sema_down(_xmit, __func__)
#else
#define rtw_sdio_free_xmitbuf_sema_up(_xmit) _rtw_sdio_free_xmitbuf_sema_up(_xmit)
#define rtw_sdio_free_xmitbuf_sema_down(_xmit) _rtw_sdio_free_xmitbuf_sema_down(_xmit)
#endif /* DBG_SDIO_FREE_XMIT_BUF_SEMA */
#endif /* SDIO_FREE_XMIT_BUF_SEMA */
#endif /* !CONFIG_SDIO_TX_TASKLET */
#endif /* __HAL_SDIO_H_ */

41
include/hal_sdio_coex.h Normal file
View File

@@ -0,0 +1,41 @@
/******************************************************************************
*
* Copyright(c) 2013 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_SDIO_COEX_H__
#define __HAL_SDIO_COEX_H__
#include <drv_types.h>
#ifdef CONFIG_SDIO_MULTI_FUNCTION_COEX
enum { /* for sdio multi-func. coex */
SDIO_MULTI_WIFI = 0,
SDIO_MULTI_BT,
SDIO_MULTI_NUM
};
bool ex_hal_sdio_multi_if_bus_available(PADAPTER adapter);
#else
#define ex_hal_sdio_multi_if_bus_available(adapter) TRUE
#endif /* CONFIG_SDIO_MULTI_FUNCTION_COEX */
#endif /* !__HAL_SDIO_COEX_H__ */

203
include/ieee80211.h
View File

@@ -15,16 +15,6 @@
#ifndef __IEEE80211_H
#define __IEEE80211_H
#ifndef CONFIG_RTL8711FW
#if defined PLATFORM_OS_XP
#include <ntstrsafe.h>
#endif
#else
#endif
#define MGMT_QUEUE_NUM 5
#define ETH_ALEN 6
@@ -251,6 +241,8 @@ typedef enum _RATEID_IDX_ {
RATEID_IDX_MIX2 = 12,
RATEID_IDX_VHT_3SS = 13,
RATEID_IDX_BGN_3SS = 14,
RATEID_IDX_BGN_4SS = 15,
RATEID_IDX_VHT_4SS = 16,
} RATEID_IDX, *PRATEID_IDX;
typedef enum _RATR_TABLE_MODE {
@@ -423,7 +415,7 @@ struct ieee_ibss_seq {
_list list;
};
#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) || defined(PLATFORM_FREEBSD)
#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
struct rtw_ieee80211_hdr {
u16 frame_ctl;
@@ -498,54 +490,6 @@ struct rtw_ieee80211s_hdr {
} __attribute__((packed));
#endif
#ifdef PLATFORM_WINDOWS
#pragma pack(1)
struct rtw_ieee80211_hdr {
u16 frame_ctl;
u16 duration_id;
u8 addr1[ETH_ALEN];
u8 addr2[ETH_ALEN];
u8 addr3[ETH_ALEN];
u16 seq_ctl;
u8 addr4[ETH_ALEN];
};
struct rtw_ieee80211_hdr_3addr {
u16 frame_ctl;
u16 duration_id;
u8 addr1[ETH_ALEN];
u8 addr2[ETH_ALEN];
u8 addr3[ETH_ALEN];
u16 seq_ctl;
};
struct rtw_ieee80211_hdr_qos {
struct rtw_ieee80211_hdr wlan_hdr;
u16 qc;
};
struct rtw_ieee80211_hdr_3addr_qos {
struct rtw_ieee80211_hdr_3addr wlan_hdr;
u16 qc;
};
struct eapol {
u8 snap[6];
u16 ethertype;
u8 version;
u8 type;
u16 length;
};
#pragma pack()
#endif
enum eap_type {
EAP_PACKET = 0,
EAPOL_START,
@@ -654,7 +598,7 @@ enum eap_type {
#define P80211_OUI_LEN 3
#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) || defined(PLATFORM_FREEBSD)
#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
struct ieee80211_snap_hdr {
@@ -667,22 +611,6 @@ struct ieee80211_snap_hdr {
#endif
#ifdef PLATFORM_WINDOWS
#pragma pack(1)
struct ieee80211_snap_hdr {
u8 dsap; /* always 0xAA */
u8 ssap; /* always 0xAA */
u8 ctrl; /* always 0x03 */
u8 oui[P80211_OUI_LEN]; /* organizational universal id */
};
#pragma pack()
#endif
#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)
#define WLAN_FC_GET_TYPE(fc) ((fc) & RTW_IEEE80211_FCTL_FTYPE)
@@ -1109,6 +1037,8 @@ typedef enum _RATE_SECTION {
RATE_SECTION_NUM,
} RATE_SECTION;
RATE_SECTION mgn_rate_to_rs(enum MGN_RATE rate);
const char *rate_section_str(u8 section);
#define IS_CCK_RATE_SECTION(section) ((section) == CCK)
@@ -1242,8 +1172,7 @@ struct ieee80211_softmac_stats {
#define BIP_MAX_KEYID 5
#define BIP_AAD_SIZE 20
#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW)
#if defined(PLATFORM_LINUX)
struct ieee80211_security {
u16 active_key:2,
enabled:1,
@@ -1258,24 +1187,6 @@ struct ieee80211_security {
#endif
#ifdef PLATFORM_WINDOWS
#pragma pack(1)
struct ieee80211_security {
u16 active_key:2,
enabled:1,
auth_mode:2,
auth_algo:4,
unicast_uses_group:1;
u8 key_sizes[WEP_KEYS];
u8 keys[WEP_KEYS][WEP_KEY_LEN];
u8 level;
u16 flags;
} ;
#pragma pack()
#endif
/*
802.11 data frame from AP
@@ -1316,8 +1227,7 @@ struct ieee80211_header_data {
#define MFIE_TYPE_RATES_EX 50
#define MFIE_TYPE_GENERIC 221
#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW)
#if defined(PLATFORM_LINUX)
struct ieee80211_info_element_hdr {
u8 id;
u8 len;
@@ -1330,23 +1240,6 @@ struct ieee80211_info_element {
} __attribute__((packed));
#endif
#ifdef PLATFORM_WINDOWS
#pragma pack(1)
struct ieee80211_info_element_hdr {
u8 id;
u8 len;
} ;
struct ieee80211_info_element {
u8 id;
u8 len;
u8 data[0];
} ;
#pragma pack()
#endif
/*
* These are the data types that can make up management packets
@@ -1369,9 +1262,7 @@ struct ieee80211_info_element {
#define IEEE80211_DEFAULT_BASIC_RATE 10
#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW)
#if defined(PLATFORM_LINUX)
struct ieee80211_authentication {
struct ieee80211_header_data header;
u16 algorithm;
@@ -1411,57 +1302,6 @@ struct ieee80211_assoc_response_frame {
} __attribute__((packed));
#endif
#ifdef PLATFORM_WINDOWS
#pragma pack(1)
struct ieee80211_authentication {
struct ieee80211_header_data header;
u16 algorithm;
u16 transaction;
u16 status;
/* struct ieee80211_info_element_hdr info_element; */
} ;
struct ieee80211_probe_response {
struct ieee80211_header_data header;
u32 time_stamp[2];
u16 beacon_interval;
u16 capability;
struct ieee80211_info_element info_element;
} ;
struct ieee80211_probe_request {
struct ieee80211_header_data header;
/*struct ieee80211_info_element info_element;*/
} ;
struct ieee80211_assoc_request_frame {
struct rtw_ieee80211_hdr_3addr header;
u16 capability;
u16 listen_interval;
/* u8 current_ap[ETH_ALEN]; */
struct ieee80211_info_element_hdr info_element;
} ;
struct ieee80211_assoc_response_frame {
struct rtw_ieee80211_hdr_3addr header;
u16 capability;
u16 status;
u16 aid;
/* struct ieee80211_info_element info_element; supported rates */
};
#pragma pack()
#endif
struct ieee80211_txb {
u8 nr_frags;
u8 encrypted;
@@ -1610,29 +1450,13 @@ enum ieee80211_state {
#define PORT_FMT "%u"
#define PORT_ARG(x) ntohs(*((u16 *)(x)))
#ifdef PLATFORM_FREEBSD /* Baron change func to macro */
#define is_multicast_mac_addr(Addr) ((((Addr[0]) & 0x01) == 0x01) && ((Addr[0]) != 0xff))
#define is_broadcast_mac_addr(Addr) ((((Addr[0]) & 0xff) == 0xff) && (((Addr[1]) & 0xff) == 0xff) && \
(((Addr[2]) & 0xff) == 0xff) && (((Addr[3]) & 0xff) == 0xff) && (((Addr[4]) & 0xff) == 0xff) && \
(((Addr[5]) & 0xff) == 0xff))
#else
static __always_inline int is_multicast_mac_addr(const u8 *addr)
{
return (addr[0] != 0xff) && (0x01 & addr[0]);
}
#define is_zero_mac_addr(Addr) ((Addr[0] == 0x00) && (Addr[1] == 0x00) && (Addr[2] == 0x00) && \
(Addr[3] == 0x00) && (Addr[4] == 0x00) && (Addr[5] == 0x00))
static __always_inline int is_broadcast_mac_addr(const u8 *addr)
{
return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) && \
(addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff));
}
static __always_inline int is_zero_mac_addr(const u8 *addr)
{
return ((addr[0] == 0x00) && (addr[1] == 0x00) && (addr[2] == 0x00) && \
(addr[3] == 0x00) && (addr[4] == 0x00) && (addr[5] == 0x00));
}
#endif /* PLATFORM_FREEBSD */
#define CFG_IEEE80211_RESERVE_FCS (1<<0)
#define CFG_IEEE80211_COMPUTE_FCS (1<<1)
@@ -2072,7 +1896,8 @@ u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset
u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, u8 flags, u16 reason, u16 precedence);
u8 *rtw_get_ie(const u8 *pbuf, sint index, sint *len, sint limit);
int rtw_remove_ie_g_rate(u8 *ie, uint *ie_len, uint offset, u8 eid);
u8 rtw_update_rate_bymode(WLAN_BSSID_EX *pbss_network, u32 mode);
u8 *rtw_get_ie_ex(const u8 *in_ie, uint in_len, u8 eid, const u8 *oui, u8 oui_len, u8 *ie, uint *ielen);
int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len);
@@ -2187,7 +2012,7 @@ int rtw_check_network_type(unsigned char *rate, int ratelen, int channel);
u8 rtw_check_invalid_mac_address(u8 *mac_addr, u8 check_local_bit);
void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr);
u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI, unsigned char *MCS_rate);
u16 rtw_ht_mcs_rate(u8 bw_40MHz, u8 short_GI, unsigned char *MCS_rate);
u8 rtw_ht_mcsset_to_nss(u8 *supp_mcs_set);
u32 rtw_ht_mcs_set_to_bitmap(u8 *mcs_set, u8 nss);

159
include/ieee80211_ext.h
View File

@@ -100,27 +100,6 @@ struct wme_parameter_element {
#endif
#ifdef PLATFORM_WINDOWS
#pragma pack(1)
struct wpa_ie_hdr {
u8 elem_id;
u8 len;
u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
u8 version[2]; /* little endian */
};
struct rsn_ie_hdr {
u8 elem_id; /* WLAN_EID_RSN */
u8 len;
u8 version[2]; /* little endian */
};
#pragma pack()
#endif
#define WPA_PUT_LE16(a, val) \
do { \
(a)[1] = ((u16) (val)) >> 8; \
@@ -325,144 +304,6 @@ struct ieee80211_mgmt {
#endif
#ifdef PLATFORM_WINDOWS
#pragma pack(1)
struct ieee80211_mgmt {
u16 frame_control;
u16 duration;
u8 da[6];
u8 sa[6];
u8 bssid[6];
u16 seq_ctrl;
union {
struct {
u16 auth_alg;
u16 auth_transaction;
u16 status_code;
/* possibly followed by Challenge text */
u8 variable[0];
} auth;
struct {
u16 reason_code;
} deauth;
struct {
u16 capab_info;
u16 listen_interval;
/* followed by SSID and Supported rates */
u8 variable[0];
} assoc_req;
struct {
u16 capab_info;
u16 status_code;
u16 aid;
/* followed by Supported rates */
u8 variable[0];
} assoc_resp, reassoc_resp;
struct {
u16 capab_info;
u16 listen_interval;
u8 current_ap[6];
/* followed by SSID and Supported rates */
u8 variable[0];
} reassoc_req;
struct {
u16 reason_code;
} disassoc;
#if 0
struct {
__le64 timestamp;
u16 beacon_int;
u16 capab_info;
/* followed by some of SSID, Supported rates,
* FH Params, DS Params, CF Params, IBSS Params, TIM */
u8 variable[0];
} beacon;
struct {
/* only variable items: SSID, Supported rates */
u8 variable[0];
} probe_req;
struct {
__le64 timestamp;
u16 beacon_int;
u16 capab_info;
/* followed by some of SSID, Supported rates,
* FH Params, DS Params, CF Params, IBSS Params */
u8 variable[0];
} probe_resp;
#endif
struct {
u8 category;
union {
struct {
u8 action_code;
u8 dialog_token;
u8 status_code;
u8 variable[0];
} wme_action;
#if 0
struct{
u8 action_code;
u8 element_id;
u8 length;
struct ieee80211_channel_sw_ie sw_elem;
} chan_switch;
struct{
u8 action_code;
u8 dialog_token;
u8 element_id;
u8 length;
struct ieee80211_msrment_ie msr_elem;
} measurement;
#endif
struct {
u8 action_code;
u8 dialog_token;
u16 capab;
u16 timeout;
u16 start_seq_num;
} addba_req;
struct {
u8 action_code;
u8 dialog_token;
u16 status;
u16 capab;
u16 timeout;
} addba_resp;
struct {
u8 action_code;
u16 params;
u16 reason_code;
} delba;
struct {
u8 action_code;
/* capab_info for open and confirm,
* reason for close
*/
u16 aux;
/* Followed in plink_confirm by status
* code, AID and supported rates,
* and directly by supported rates in
* plink_open and plink_close
*/
u8 variable[0];
} plink_action;
struct {
u8 action_code;
u8 variable[0];
} mesh_action;
} u;
} action;
} u;
} ;
#pragma pack()
#endif
/* mgmt header + 1 byte category code */
#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u)

4
include/mlme_osdep.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
* Copyright(c) 2007 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -16,7 +16,7 @@
#define __MLME_OSDEP_H_
extern void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated);
extern void rtw_os_indicate_connect(_adapter *adapter);
extern int rtw_os_indicate_connect(_adapter *adapter);
void rtw_os_indicate_scan_done(_adapter *padapter, bool aborted);
extern void rtw_report_sec_ie(_adapter *adapter, u8 authmode, u8 *sec_ie);

348
include/mp_custom_oid.h
View File

@@ -1,348 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __CUSTOM_OID_H
#define __CUSTOM_OID_H
/* by Owen
* 0xFF818000 - 0xFF81802F RTL8180 Mass Production Kit
* 0xFF818500 - 0xFF81850F RTL8185 Setup Utility
* 0xFF818580 - 0xFF81858F RTL8185 Phy Status Utility */
/* */
/* by Owen for Production Kit
* For Production Kit with Agilent Equipments
* in order to make our custom oids hopefully somewhat unique
* we will use 0xFF (indicating implementation specific OID)
* 81(first byte of non zero Realtek unique identifier)
* 80 (second byte of non zero Realtek unique identifier)
* XX (the custom OID number - providing 255 possible custom oids) */
#define OID_RT_PRO_RESET_DUT 0xFF818000
#define OID_RT_PRO_SET_DATA_RATE 0xFF818001
#define OID_RT_PRO_START_TEST 0xFF818002
#define OID_RT_PRO_STOP_TEST 0xFF818003
#define OID_RT_PRO_SET_PREAMBLE 0xFF818004
#define OID_RT_PRO_SET_SCRAMBLER 0xFF818005
#define OID_RT_PRO_SET_FILTER_BB 0xFF818006
#define OID_RT_PRO_SET_MANUAL_DIVERSITY_BB 0xFF818007
#define OID_RT_PRO_SET_CHANNEL_DIRECT_CALL 0xFF818008
#define OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL 0xFF818009
#define OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL 0xFF81800A
#define OID_RT_PRO_SET_TX_ANTENNA_BB 0xFF81800D
#define OID_RT_PRO_SET_ANTENNA_BB 0xFF81800E
#define OID_RT_PRO_SET_CR_SCRAMBLER 0xFF81800F
#define OID_RT_PRO_SET_CR_NEW_FILTER 0xFF818010
#define OID_RT_PRO_SET_TX_POWER_CONTROL 0xFF818011
#define OID_RT_PRO_SET_CR_TX_CONFIG 0xFF818012
#define OID_RT_PRO_GET_TX_POWER_CONTROL 0xFF818013
#define OID_RT_PRO_GET_CR_SIGNAL_QUALITY 0xFF818014
#define OID_RT_PRO_SET_CR_SETPOINT 0xFF818015
#define OID_RT_PRO_SET_INTEGRATOR 0xFF818016
#define OID_RT_PRO_SET_SIGNAL_QUALITY 0xFF818017
#define OID_RT_PRO_GET_INTEGRATOR 0xFF818018
#define OID_RT_PRO_GET_SIGNAL_QUALITY 0xFF818019
#define OID_RT_PRO_QUERY_EEPROM_TYPE 0xFF81801A
#define OID_RT_PRO_WRITE_MAC_ADDRESS 0xFF81801B
#define OID_RT_PRO_READ_MAC_ADDRESS 0xFF81801C
#define OID_RT_PRO_WRITE_CIS_DATA 0xFF81801D
#define OID_RT_PRO_READ_CIS_DATA 0xFF81801E
#define OID_RT_PRO_WRITE_POWER_CONTROL 0xFF81801F
#define OID_RT_PRO_READ_POWER_CONTROL 0xFF818020
#define OID_RT_PRO_WRITE_EEPROM 0xFF818021
#define OID_RT_PRO_READ_EEPROM 0xFF818022
#define OID_RT_PRO_RESET_TX_PACKET_SENT 0xFF818023
#define OID_RT_PRO_QUERY_TX_PACKET_SENT 0xFF818024
#define OID_RT_PRO_RESET_RX_PACKET_RECEIVED 0xFF818025
#define OID_RT_PRO_QUERY_RX_PACKET_RECEIVED 0xFF818026
#define OID_RT_PRO_QUERY_RX_PACKET_CRC32_ERROR 0xFF818027
#define OID_RT_PRO_QUERY_CURRENT_ADDRESS 0xFF818028
#define OID_RT_PRO_QUERY_PERMANENT_ADDRESS 0xFF818029
#define OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS 0xFF81802A
#define OID_RT_PRO_RECEIVE_PACKET 0xFF81802C
/* added by Owen on 04/08/03 for Cameo's request */
#define OID_RT_PRO_WRITE_EEPROM_BYTE 0xFF81802D
#define OID_RT_PRO_READ_EEPROM_BYTE 0xFF81802E
#define OID_RT_PRO_SET_MODULATION 0xFF81802F
/* */
/* Sean */
#define OID_RT_DRIVER_OPTION 0xFF818080
#define OID_RT_RF_OFF 0xFF818081
#define OID_RT_AUTH_STATUS 0xFF818082
/* ************************************************************************ */
#define OID_RT_PRO_SET_CONTINUOUS_TX 0xFF81800B
#define OID_RT_PRO_SET_SINGLE_CARRIER_TX 0xFF81800C
#define OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX 0xFF81802B
#define OID_RT_PRO_SET_SINGLE_TONE_TX 0xFF818043
/* ************************************************************************ */
/* by Owen for RTL8185 Phy Status Report Utility */
#define OID_RT_UTILITY_FALSE_ALARM_COUNTERS 0xFF818580
#define OID_RT_UTILITY_SELECT_DEBUG_MODE 0xFF818581
#define OID_RT_UTILITY_SELECT_SUBCARRIER_NUMBER 0xFF818582
#define OID_RT_UTILITY_GET_RSSI_STATUS 0xFF818583
#define OID_RT_UTILITY_GET_FRAME_DETECTION_STATUS 0xFF818584
#define OID_RT_UTILITY_GET_AGC_AND_FREQUENCY_OFFSET_ESTIMATION_STATUS 0xFF818585
#define OID_RT_UTILITY_GET_CHANNEL_ESTIMATION_STATUS 0xFF818586
/* */
/* by Owen on 03/09/19-03/09/22 for RTL8185 */
#define OID_RT_WIRELESS_MODE 0xFF818500
#define OID_RT_SUPPORTED_RATES 0xFF818501
#define OID_RT_DESIRED_RATES 0xFF818502
#define OID_RT_WIRELESS_MODE_STARTING_ADHOC 0xFF818503
/* */
#define OID_RT_GET_CONNECT_STATE 0xFF030001
#define OID_RT_RESCAN 0xFF030002
#define OID_RT_SET_KEY_LENGTH 0xFF030003
#define OID_RT_SET_DEFAULT_KEY_ID 0xFF030004
#define OID_RT_SET_CHANNEL 0xFF010182
#define OID_RT_SET_SNIFFER_MODE 0xFF010183
#define OID_RT_GET_SIGNAL_QUALITY 0xFF010184
#define OID_RT_GET_SMALL_PACKET_CRC 0xFF010185
#define OID_RT_GET_MIDDLE_PACKET_CRC 0xFF010186
#define OID_RT_GET_LARGE_PACKET_CRC 0xFF010187
#define OID_RT_GET_TX_RETRY 0xFF010188
#define OID_RT_GET_RX_RETRY 0xFF010189
#define OID_RT_PRO_SET_FW_DIG_STATE 0xFF01018A/* S */
#define OID_RT_PRO_SET_FW_RA_STATE 0xFF01018B/* S */
#define OID_RT_GET_RX_TOTAL_PACKET 0xFF010190
#define OID_RT_GET_TX_BEACON_OK 0xFF010191
#define OID_RT_GET_TX_BEACON_ERR 0xFF010192
#define OID_RT_GET_RX_ICV_ERR 0xFF010193
#define OID_RT_SET_ENCRYPTION_ALGORITHM 0xFF010194
#define OID_RT_SET_NO_AUTO_RESCAN 0xFF010195
#define OID_RT_GET_PREAMBLE_MODE 0xFF010196
#define OID_RT_GET_DRIVER_UP_DELTA_TIME 0xFF010197
#define OID_RT_GET_AP_IP 0xFF010198
#define OID_RT_GET_CHANNELPLAN 0xFF010199
#define OID_RT_SET_PREAMBLE_MODE 0xFF01019A
#define OID_RT_SET_BCN_INTVL 0xFF01019B
#define OID_RT_GET_RF_VENDER 0xFF01019C
#define OID_RT_DEDICATE_PROBE 0xFF01019D
#define OID_RT_PRO_RX_FILTER_PATTERN 0xFF01019E
#define OID_RT_GET_DCST_CURRENT_THRESHOLD 0xFF01019F
#define OID_RT_GET_CCA_ERR 0xFF0101A0
#define OID_RT_GET_CCA_UPGRADE_THRESHOLD 0xFF0101A1
#define OID_RT_GET_CCA_FALLBACK_THRESHOLD 0xFF0101A2
#define OID_RT_GET_CCA_UPGRADE_EVALUATE_TIMES 0xFF0101A3
#define OID_RT_GET_CCA_FALLBACK_EVALUATE_TIMES 0xFF0101A4
/* by Owen on 03/31/03 for Cameo's request */
#define OID_RT_SET_RATE_ADAPTIVE 0xFF0101A5
/* */
#define OID_RT_GET_DCST_EVALUATE_PERIOD 0xFF0101A5
#define OID_RT_GET_DCST_TIME_UNIT_INDEX 0xFF0101A6
#define OID_RT_GET_TOTAL_TX_BYTES 0xFF0101A7
#define OID_RT_GET_TOTAL_RX_BYTES 0xFF0101A8
#define OID_RT_CURRENT_TX_POWER_LEVEL 0xFF0101A9
#define OID_RT_GET_ENC_KEY_MISMATCH_COUNT 0xFF0101AA
#define OID_RT_GET_ENC_KEY_MATCH_COUNT 0xFF0101AB
#define OID_RT_GET_CHANNEL 0xFF0101AC
#define OID_RT_SET_CHANNELPLAN 0xFF0101AD
#define OID_RT_GET_HARDWARE_RADIO_OFF 0xFF0101AE
#define OID_RT_CHANNELPLAN_BY_COUNTRY 0xFF0101AF
#define OID_RT_SCAN_AVAILABLE_BSSID 0xFF0101B0
#define OID_RT_GET_HARDWARE_VERSION 0xFF0101B1
#define OID_RT_GET_IS_ROAMING 0xFF0101B2
#define OID_RT_GET_IS_PRIVACY 0xFF0101B3
#define OID_RT_GET_KEY_MISMATCH 0xFF0101B4
#define OID_RT_SET_RSSI_ROAM_TRAFFIC_TH 0xFF0101B5
#define OID_RT_SET_RSSI_ROAM_SIGNAL_TH 0xFF0101B6
#define OID_RT_RESET_LOG 0xFF0101B7
#define OID_RT_GET_LOG 0xFF0101B8
#define OID_RT_SET_INDICATE_HIDDEN_AP 0xFF0101B9
#define OID_RT_GET_HEADER_FAIL 0xFF0101BA
#define OID_RT_SUPPORTED_WIRELESS_MODE 0xFF0101BB
#define OID_RT_GET_CHANNEL_LIST 0xFF0101BC
#define OID_RT_GET_SCAN_IN_PROGRESS 0xFF0101BD
#define OID_RT_GET_TX_INFO 0xFF0101BE
#define OID_RT_RF_READ_WRITE_OFFSET 0xFF0101BF
#define OID_RT_RF_READ_WRITE 0xFF0101C0
/* For Netgear request. 2005.01.13, by rcnjko. */
#define OID_RT_FORCED_DATA_RATE 0xFF0101C1
#define OID_RT_WIRELESS_MODE_FOR_SCAN_LIST 0xFF0101C2
/* For Netgear request. 2005.02.17, by rcnjko. */
#define OID_RT_GET_BSS_WIRELESS_MODE 0xFF0101C3
/* For AZ project. 2005.06.27, by rcnjko. */
#define OID_RT_SCAN_WITH_MAGIC_PACKET 0xFF0101C4
/* Vincent 8185MP */
#define OID_RT_PRO_RX_FILTER 0xFF0111C0
/* Andy TEST
* #define OID_RT_PRO_WRITE_REGISTRY 0xFF0111C1
* #define OID_RT_PRO_READ_REGISTRY 0xFF0111C2 */
#define OID_CE_USB_WRITE_REGISTRY 0xFF0111C1
#define OID_CE_USB_READ_REGISTRY 0xFF0111C2
#define OID_RT_PRO_SET_INITIAL_GAIN 0xFF0111C3
#define OID_RT_PRO_SET_BB_RF_STANDBY_MODE 0xFF0111C4
#define OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE 0xFF0111C5
#define OID_RT_PRO_SET_TX_CHARGE_PUMP 0xFF0111C6
#define OID_RT_PRO_SET_RX_CHARGE_PUMP 0xFF0111C7
#define OID_RT_PRO_RF_WRITE_REGISTRY 0xFF0111C8
#define OID_RT_PRO_RF_READ_REGISTRY 0xFF0111C9
#define OID_RT_PRO_QUERY_RF_TYPE 0xFF0111CA
/* AP OID */
#define OID_RT_AP_GET_ASSOCIATED_STATION_LIST 0xFF010300
#define OID_RT_AP_GET_CURRENT_TIME_STAMP 0xFF010301
#define OID_RT_AP_SWITCH_INTO_AP_MODE 0xFF010302
#define OID_RT_AP_SET_DTIM_PERIOD 0xFF010303
#define OID_RT_AP_SUPPORTED 0xFF010304 /* Determine if driver supports AP mode. 2004.08.27, by rcnjko. */
#define OID_RT_AP_SET_PASSPHRASE 0xFF010305 /* Set WPA-PSK passphrase into authenticator. 2005.07.08, byrcnjko. */
/* 8187MP. 2004.09.06, by rcnjko. */
#define OID_RT_PRO8187_WI_POLL 0xFF818780
#define OID_RT_PRO_WRITE_BB_REG 0xFF818781
#define OID_RT_PRO_READ_BB_REG 0xFF818782
#define OID_RT_PRO_WRITE_RF_REG 0xFF818783
#define OID_RT_PRO_READ_RF_REG 0xFF818784
/* Meeting House. added by Annie, 2005-07-20. */
#define OID_RT_MH_VENDER_ID 0xFFEDC100
/* 8711 MP OID added 20051230. */
#define OID_RT_PRO8711_JOIN_BSS 0xFF871100/* S */
#define OID_RT_PRO_READ_REGISTER 0xFF871101 /* Q */
#define OID_RT_PRO_WRITE_REGISTER 0xFF871102 /* S */
#define OID_RT_PRO_BURST_READ_REGISTER 0xFF871103 /* Q */
#define OID_RT_PRO_BURST_WRITE_REGISTER 0xFF871104 /* S */
#define OID_RT_PRO_WRITE_TXCMD 0xFF871105 /* S */
#define OID_RT_PRO_READ16_EEPROM 0xFF871106 /* Q */
#define OID_RT_PRO_WRITE16_EEPROM 0xFF871107 /* S */
#define OID_RT_PRO_H2C_SET_COMMAND 0xFF871108 /* S */
#define OID_RT_PRO_H2C_QUERY_RESULT 0xFF871109 /* Q */
#define OID_RT_PRO8711_WI_POLL 0xFF87110A /* Q */
#define OID_RT_PRO8711_PKT_LOSS 0xFF87110B /* Q */
#define OID_RT_RD_ATTRIB_MEM 0xFF87110C/* Q */
#define OID_RT_WR_ATTRIB_MEM 0xFF87110D/* S */
/* Method 2 for H2C/C2H */
#define OID_RT_PRO_H2C_CMD_MODE 0xFF871110 /* S */
#define OID_RT_PRO_H2C_CMD_RSP_MODE 0xFF871111 /* Q */
#define OID_RT_PRO_H2C_CMD_EVENT_MODE 0xFF871112 /* S */
#define OID_RT_PRO_WAIT_C2H_EVENT 0xFF871113 /* Q */
#define OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST 0xFF871114/* Q */
#define OID_RT_PRO_SCSI_ACCESS_TEST 0xFF871115 /* Q, S */
#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT 0xFF871116 /* S */
#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN 0xFF871117 /* Q, S */
#define OID_RT_RRO_RX_PKT_VIA_IOCTRL 0xFF871118 /* Q */
#define OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL 0xFF871119 /* Q */
#define OID_RT_RPO_SET_PWRMGT_TEST 0xFF87111A /* S */
#define OID_RT_PRO_QRY_PWRMGT_TEST 0XFF87111B /* Q */
#define OID_RT_RPO_ASYNC_RWIO_TEST 0xFF87111C /* S */
#define OID_RT_RPO_ASYNC_RWIO_POLL 0xFF87111D /* Q */
#define OID_RT_PRO_SET_RF_INTFS 0xFF87111E /* S */
#define OID_RT_POLL_RX_STATUS 0xFF87111F /* Q */
#define OID_RT_PRO_CFG_DEBUG_MESSAGE 0xFF871120 /* Q, S */
#define OID_RT_PRO_SET_DATA_RATE_EX 0xFF871121/* S */
#define OID_RT_PRO_SET_BASIC_RATE 0xFF871122/* S */
#define OID_RT_PRO_READ_TSSI 0xFF871123/* S */
#define OID_RT_PRO_SET_POWER_TRACKING 0xFF871124/* S */
#define OID_RT_PRO_QRY_PWRSTATE 0xFF871150 /* Q */
#define OID_RT_PRO_SET_PWRSTATE 0xFF871151 /* S */
/* Method 2 , using workitem */
#define OID_RT_SET_READ_REG 0xFF871181 /* S */
#define OID_RT_SET_WRITE_REG 0xFF871182 /* S */
#define OID_RT_SET_BURST_READ_REG 0xFF871183 /* S */
#define OID_RT_SET_BURST_WRITE_REG 0xFF871184 /* S */
#define OID_RT_SET_WRITE_TXCMD 0xFF871185 /* S */
#define OID_RT_SET_READ16_EEPROM 0xFF871186 /* S */
#define OID_RT_SET_WRITE16_EEPROM 0xFF871187 /* S */
#define OID_RT_QRY_POLL_WKITEM 0xFF871188 /* Q */
/* For SDIO INTERFACE only */
#define OID_RT_PRO_SYNCPAGERW_SRAM 0xFF8711A0 /* Q, S */
#define OID_RT_PRO_871X_DRV_EXT 0xFF8711A1
/* For USB INTERFACE only */
#define OID_RT_PRO_USB_VENDOR_REQ 0xFF8711B0 /* Q, S */
#define OID_RT_PRO_SCSI_AUTO_TEST 0xFF8711B1 /* S */
#define OID_RT_PRO_USB_MAC_AC_FIFO_WRITE 0xFF8711B2 /* S */
#define OID_RT_PRO_USB_MAC_RX_FIFO_READ 0xFF8711B3 /* Q */
#define OID_RT_PRO_USB_MAC_RX_FIFO_POLLING 0xFF8711B4 /* Q */
#define OID_RT_PRO_H2C_SET_RATE_TABLE 0xFF8711FB /* S */
#define OID_RT_PRO_H2C_GET_RATE_TABLE 0xFF8711FC /* S */
#define OID_RT_PRO_H2C_C2H_LBK_TEST 0xFF8711FE
#define OID_RT_PRO_ENCRYPTION_CTRL 0xFF871200 /* Q, S */
#define OID_RT_PRO_ADD_STA_INFO 0xFF871201 /* S */
#define OID_RT_PRO_DELE_STA_INFO 0xFF871202 /* S */
#define OID_RT_PRO_QUERY_DR_VARIABLE 0xFF871203 /* Q */
#define OID_RT_PRO_RX_PACKET_TYPE 0xFF871204 /* Q, S */
#define OID_RT_PRO_READ_EFUSE 0xFF871205 /* Q */
#define OID_RT_PRO_WRITE_EFUSE 0xFF871206 /* S */
#define OID_RT_PRO_RW_EFUSE_PGPKT 0xFF871207 /* Q, S */
#define OID_RT_GET_EFUSE_CURRENT_SIZE 0xFF871208 /* Q */
#define OID_RT_SET_BANDWIDTH 0xFF871209 /* S */
#define OID_RT_SET_CRYSTAL_CAP 0xFF87120A /* S */
#define OID_RT_SET_RX_PACKET_TYPE 0xFF87120B /* S */
#define OID_RT_GET_EFUSE_MAX_SIZE 0xFF87120C /* Q */
#define OID_RT_PRO_SET_TX_AGC_OFFSET 0xFF87120D /* S */
#define OID_RT_PRO_SET_PKT_TEST_MODE 0xFF87120E /* S */
#define OID_RT_PRO_FOR_EVM_TEST_SETTING 0xFF87120F /* S */
#define OID_RT_PRO_GET_THERMAL_METER 0xFF871210 /* Q */
#define OID_RT_RESET_PHY_RX_PACKET_COUNT 0xFF871211 /* S */
#define OID_RT_GET_PHY_RX_PACKET_RECEIVED 0xFF871212 /* Q */
#define OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR 0xFF871213 /* Q */
#define OID_RT_SET_POWER_DOWN 0xFF871214 /* S */
#define OID_RT_GET_POWER_MODE 0xFF871215 /* Q */
#define OID_RT_PRO_EFUSE 0xFF871216 /* Q, S */
#define OID_RT_PRO_EFUSE_MAP 0xFF871217 /* Q, S */
#endif /* #ifndef __CUSTOM_OID_H */

26
include/osdep_intf.h
View File

@@ -57,34 +57,8 @@ struct intf_priv {
#endif
#endif
#ifdef PLATFORM_OS_XP
#ifdef CONFIG_SDIO_HCI
/* below is for io_rwmem... */
PMDL pmdl;
PSDBUS_REQUEST_PACKET sdrp;
PSDBUS_REQUEST_PACKET recv_sdrp;
PSDBUS_REQUEST_PACKET xmit_sdrp;
PIRP piorw_irp;
#endif
#ifdef CONFIG_USB_HCI
PURB piorw_urb;
PIRP piorw_irp;
u8 io_irp_cnt;
u8 bio_irp_pending;
_sema io_retevt;
#endif
#endif
};
#ifdef CONFIG_R871X_TEST
int rtw_start_pseudo_adhoc(_adapter *padapter);
int rtw_stop_pseudo_adhoc(_adapter *padapter);
#endif
struct dvobj_priv *devobj_init(void);
void devobj_deinit(struct dvobj_priv *pdvobj);

24
include/osdep_service.h
View File

@@ -27,6 +27,9 @@
#define RTW_ALREADY 8
#define RTW_RA_RESOLVING 9
#define RTW_BMC_NO_NEED 10
#define RTW_XBUF_UNAVAIL 11
#define RTW_TX_BALANCE 12
#define RTW_TX_WAIT_MORE_FRAME 13
/* #define RTW_STATUS_TIMEDOUT -110 */
@@ -48,14 +51,17 @@
#include <linux/sched/types.h>
#endif
#include <osdep_service_linux.h>
#include <drv_types_linux.h>
#endif
#ifdef PLATFORM_OS_XP
#include <osdep_service_xp.h>
#include <drv_types_xp.h>
#endif
#ifdef PLATFORM_OS_CE
#include <osdep_service_ce.h>
#include <drv_types_ce.h>
#endif
/* #include <rtw_byteorder.h> */
@@ -104,6 +110,11 @@
#define BIT35 0x0800000000
#define BIT36 0x1000000000
#ifndef GENMASK
#define GENMASK(h, l) \
(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
#endif
extern int RTW_STATUS_CODE(int error_code);
#ifndef RTK_DMP_PLATFORM
@@ -580,6 +591,17 @@ static inline int largest_bit(u32 bitmask)
return i;
}
static inline int largest_bit_64(u64 bitmask)
{
int i;
for (i = 63; i >= 0; i--)
if (bitmask & BIT(i))
break;
return i;
}
#define rtw_abs(a) (a < 0 ? -a : a)
#define rtw_min(a, b) ((a > b) ? b : a)
#define rtw_is_range_a_in_b(hi_a, lo_a, hi_b, lo_b) (((hi_a) <= (hi_b)) && ((lo_a) >= (lo_b)))
@@ -624,8 +646,10 @@ extern int ATOMIC_DEC_RETURN(ATOMIC_T *v);
extern bool ATOMIC_INC_UNLESS(ATOMIC_T *v, int u);
/* File operation APIs, just for linux now */
extern int rtw_is_dir_readable(const char *path);
extern int rtw_is_file_readable(const char *path);
extern int rtw_is_file_readable_with_size(const char *path, u32 *sz);
extern int rtw_readable_file_sz_chk(const char *path, u32 sz);
extern int rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz);
extern int rtw_store_to_file(const char *path, u8 *buf, u32 sz);

1409
include/osdep_service_bsd.h
View File

File diff suppressed because it is too large Load Diff

306
include/osdep_service_ce.h
View File

@@ -12,113 +12,113 @@
* more details.
*
*****************************************************************************/
#ifndef __OSDEP_CE_SERVICE_H_
#define __OSDEP_CE_SERVICE_H_
#include <ndis.h>
#include <ntddndis.h>
#ifdef CONFIG_SDIO_HCI
#include "SDCardDDK.h"
#endif
#ifdef CONFIG_USB_HCI
#include <usbdi.h>
#endif
typedef HANDLE _sema;
typedef LIST_ENTRY _list;
typedef NDIS_STATUS _OS_STATUS;
typedef NDIS_SPIN_LOCK _lock;
typedef HANDLE _rwlock; //Mutex
typedef u32 _irqL;
typedef NDIS_HANDLE _nic_hdl;
#ifndef __OSDEP_CE_SERVICE_H_
#define __OSDEP_CE_SERVICE_H_
#include <ndis.h>
#include <ntddndis.h>
#ifdef CONFIG_SDIO_HCI
#include "SDCardDDK.h"
#endif
#ifdef CONFIG_USB_HCI
#include <usbdi.h>
#endif
typedef HANDLE _sema;
typedef LIST_ENTRY _list;
typedef NDIS_STATUS _OS_STATUS;
typedef NDIS_SPIN_LOCK _lock;
typedef HANDLE _rwlock; //Mutex
typedef u32 _irqL;
typedef NDIS_HANDLE _nic_hdl;
struct rtw_timer_list {
NDIS_MINIPORT_TIMER ndis_timer;
void (*function)(void *);
void *arg;
};
struct __queue {
LIST_ENTRY queue;
_lock lock;
};
typedef NDIS_PACKET _pkt;
typedef NDIS_BUFFER _buffer;
typedef struct __queue _queue;
typedef HANDLE _thread_hdl_;
typedef DWORD thread_return;
typedef void* thread_context;
typedef NDIS_WORK_ITEM _workitem;
#define SEMA_UPBND (0x7FFFFFFF) //8192
__inline static _list *get_prev(_list *list)
{
return list->Blink;
}
__inline static _list *get_next(_list *list)
{
return list->Flink;
}
__inline static _list *get_list_head(_queue *queue)
{
return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
{
NdisAcquireSpinLock(plock);
}
__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
{
NdisReleaseSpinLock(plock);
}
__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprAcquireSpinLock(plock);
}
__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprReleaseSpinLock(plock);
}
__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
{
WaitForSingleObject(*prwlock, INFINITE );
}
__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
{
ReleaseMutex(*prwlock);
}
__inline static void rtw_list_delete(_list *plist)
{
RemoveEntryList(plist);
InitializeListHead(plist);
}
struct __queue {
LIST_ENTRY queue;
_lock lock;
};
typedef NDIS_PACKET _pkt;
typedef NDIS_BUFFER _buffer;
typedef struct __queue _queue;
typedef HANDLE _thread_hdl_;
typedef DWORD thread_return;
typedef void* thread_context;
typedef NDIS_WORK_ITEM _workitem;
#define SEMA_UPBND (0x7FFFFFFF) //8192
__inline static _list *get_prev(_list *list)
{
return list->Blink;
}
__inline static _list *get_next(_list *list)
{
return list->Flink;
}
__inline static _list *get_list_head(_queue *queue)
{
return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
{
NdisAcquireSpinLock(plock);
}
__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
{
NdisReleaseSpinLock(plock);
}
__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprAcquireSpinLock(plock);
}
__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprReleaseSpinLock(plock);
}
__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
{
WaitForSingleObject(*prwlock, INFINITE );
}
__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
{
ReleaseMutex(*prwlock);
}
__inline static void rtw_list_delete(_list *plist)
{
RemoveEntryList(plist);
InitializeListHead(plist);
}
static inline void timer_hdl(
IN PVOID SystemSpecific1,
IN PVOID FunctionContext,
@@ -146,55 +146,55 @@ static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled)
{
NdisMCancelTimer(ptimer, bcancelled);
}
__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
{
NdisInitializeWorkItem(pwork, pfunc, cntx);
}
__inline static void _set_workitem(_workitem *pwork)
{
NdisScheduleWorkItem(pwork);
}
#define ATOMIC_INIT(i) { (i) }
//
// Global Mutex: can only be used at PASSIVE level.
//
#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
{ \
while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
NdisMSleep(10000); \
} \
}
#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
}
// limitation of path length
#define PATH_LENGTH_MAX MAX_PATH
//Atomic integer operations
#define ATOMIC_T LONG
#define NDEV_FMT "%s"
#define NDEV_ARG(ndev) ""
#define ADPT_FMT "%s"
#define ADPT_ARG(adapter) ""
#define FUNC_NDEV_FMT "%s"
#define FUNC_NDEV_ARG(ndev) __func__
#define FUNC_ADPT_FMT "%s"
#define FUNC_ADPT_ARG(adapter) __func__
#define STRUCT_PACKED
#endif
__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
{
NdisInitializeWorkItem(pwork, pfunc, cntx);
}
__inline static void _set_workitem(_workitem *pwork)
{
NdisScheduleWorkItem(pwork);
}
#define ATOMIC_INIT(i) { (i) }
//
// Global Mutex: can only be used at PASSIVE level.
//
#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
{ \
while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
NdisMSleep(10000); \
} \
}
#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
}
// limitation of path length
#define PATH_LENGTH_MAX MAX_PATH
//Atomic integer operations
#define ATOMIC_T LONG
#define NDEV_FMT "%s"
#define NDEV_ARG(ndev) ""
#define ADPT_FMT "%s"
#define ADPT_ARG(adapter) ""
#define FUNC_NDEV_FMT "%s"
#define FUNC_NDEV_ARG(ndev) __func__
#define FUNC_ADPT_FMT "%s"
#define FUNC_ADPT_ARG(adapter) __func__
#define STRUCT_PACKED
#endif

18
include/osdep_service_linux.h
View File

@@ -23,6 +23,7 @@
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/namei.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 5))
#include <linux/kref.h>
#endif
@@ -217,6 +218,7 @@ typedef void *timer_hdl_context;
#endif
typedef unsigned long systime;
typedef struct tasklet_struct _tasklet;
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22))
/* Porting from linux kernel, for compatible with old kernel. */
@@ -533,7 +535,21 @@ struct rtw_netdev_priv_indicator {
struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv);
extern struct net_device *rtw_alloc_etherdev(int sizeof_priv);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
#define rtw_get_same_net_ndev_by_name(ndev, name) dev_get_by_name(name)
#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))
#define rtw_get_same_net_ndev_by_name(ndev, name) dev_get_by_name(ndev->nd_net, name)
#else
#define rtw_get_same_net_ndev_by_name(ndev, name) dev_get_by_name(dev_net(ndev), name)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
#define rtw_get_bridge_ndev_by_name(name) dev_get_by_name(name)
#else
#define rtw_get_bridge_ndev_by_name(name) dev_get_by_name(&init_net, name)
#endif
#define STRUCT_PACKED __attribute__ ((packed))
#endif
#endif /* __OSDEP_LINUX_SERVICE_H_ */

328
include/osdep_service_xp.h
View File

@@ -12,122 +12,122 @@
* more details.
*
*****************************************************************************/
#ifndef __OSDEP_LINUX_SERVICE_H_
#define __OSDEP_LINUX_SERVICE_H_
#include <ndis.h>
#include <ntddk.h>
#include <ntddndis.h>
#include <ntdef.h>
#ifdef CONFIG_USB_HCI
#include <usb.h>
#include <usbioctl.h>
#include <usbdlib.h>
#endif
typedef KSEMAPHORE _sema;
typedef LIST_ENTRY _list;
typedef NDIS_STATUS _OS_STATUS;
typedef NDIS_SPIN_LOCK _lock;
typedef KMUTEX _mutex;
typedef KIRQL _irqL;
// USB_PIPE for WINCE , but handle can be use just integer under windows
typedef NDIS_HANDLE _nic_hdl;
#ifndef __OSDEP_LINUX_SERVICE_H_
#define __OSDEP_LINUX_SERVICE_H_
#include <ndis.h>
#include <ntddk.h>
#include <ntddndis.h>
#include <ntdef.h>
#ifdef CONFIG_USB_HCI
#include <usb.h>
#include <usbioctl.h>
#include <usbdlib.h>
#endif
typedef KSEMAPHORE _sema;
typedef LIST_ENTRY _list;
typedef NDIS_STATUS _OS_STATUS;
typedef NDIS_SPIN_LOCK _lock;
typedef KMUTEX _mutex;
typedef KIRQL _irqL;
// USB_PIPE for WINCE , but handle can be use just integer under windows
typedef NDIS_HANDLE _nic_hdl;
struct rtw_timer_list {
NDIS_MINIPORT_TIMER ndis_timer;
void (*function)(void *);
void *arg;
};
struct __queue {
LIST_ENTRY queue;
_lock lock;
};
typedef NDIS_PACKET _pkt;
typedef NDIS_BUFFER _buffer;
typedef struct __queue _queue;
typedef PKTHREAD _thread_hdl_;
typedef void thread_return;
typedef void* thread_context;
typedef NDIS_WORK_ITEM _workitem;
#define HZ 10000000
#define SEMA_UPBND (0x7FFFFFFF) //8192
__inline static _list *get_next(_list *list)
{
return list->Flink;
}
__inline static _list *get_list_head(_queue *queue)
{
return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
__inline static _enter_critical(_lock *plock, _irqL *pirqL)
{
NdisAcquireSpinLock(plock);
}
__inline static _exit_critical(_lock *plock, _irqL *pirqL)
{
NdisReleaseSpinLock(plock);
}
__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprAcquireSpinLock(plock);
}
__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprReleaseSpinLock(plock);
}
__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
{
NdisDprAcquireSpinLock(plock);
}
__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
{
NdisDprReleaseSpinLock(plock);
}
__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
{
KeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL);
}
__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
{
KeReleaseMutex(pmutex, FALSE);
}
__inline static void rtw_list_delete(_list *plist)
{
RemoveEntryList(plist);
InitializeListHead(plist);
}
struct __queue {
LIST_ENTRY queue;
_lock lock;
};
typedef NDIS_PACKET _pkt;
typedef NDIS_BUFFER _buffer;
typedef struct __queue _queue;
typedef PKTHREAD _thread_hdl_;
typedef void thread_return;
typedef void* thread_context;
typedef NDIS_WORK_ITEM _workitem;
#define HZ 10000000
#define SEMA_UPBND (0x7FFFFFFF) //8192
__inline static _list *get_next(_list *list)
{
return list->Flink;
}
__inline static _list *get_list_head(_queue *queue)
{
return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
__inline static _enter_critical(_lock *plock, _irqL *pirqL)
{
NdisAcquireSpinLock(plock);
}
__inline static _exit_critical(_lock *plock, _irqL *pirqL)
{
NdisReleaseSpinLock(plock);
}
__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprAcquireSpinLock(plock);
}
__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprReleaseSpinLock(plock);
}
__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
{
NdisDprAcquireSpinLock(plock);
}
__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
{
NdisDprReleaseSpinLock(plock);
}
__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
{
KeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL);
}
__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
{
KeReleaseMutex(pmutex, FALSE);
}
__inline static void rtw_list_delete(_list *plist)
{
RemoveEntryList(plist);
InitializeListHead(plist);
}
static inline void timer_hdl(
IN PVOID SystemSpecific1,
IN PVOID FunctionContext,
@@ -155,56 +155,56 @@ static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled)
{
NdisMCancelTimer(ptimer, bcancelled);
}
__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
{
NdisInitializeWorkItem(pwork, pfunc, cntx);
}
__inline static void _set_workitem(_workitem *pwork)
{
NdisScheduleWorkItem(pwork);
}
#define ATOMIC_INIT(i) { (i) }
//
// Global Mutex: can only be used at PASSIVE level.
//
#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
{ \
while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
NdisMSleep(10000); \
} \
}
#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
}
// limitation of path length
#define PATH_LENGTH_MAX MAX_PATH
//Atomic integer operations
#define ATOMIC_T LONG
#define NDEV_FMT "%s"
#define NDEV_ARG(ndev) ""
#define ADPT_FMT "%s"
#define ADPT_ARG(adapter) ""
#define FUNC_NDEV_FMT "%s"
#define FUNC_NDEV_ARG(ndev) __func__
#define FUNC_ADPT_FMT "%s"
#define FUNC_ADPT_ARG(adapter) __func__
#define STRUCT_PACKED
#endif
__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
{
NdisInitializeWorkItem(pwork, pfunc, cntx);
}
__inline static void _set_workitem(_workitem *pwork)
{
NdisScheduleWorkItem(pwork);
}
#define ATOMIC_INIT(i) { (i) }
//
// Global Mutex: can only be used at PASSIVE level.
//
#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
{ \
while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
NdisMSleep(10000); \
} \
}
#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
}
// limitation of path length
#define PATH_LENGTH_MAX MAX_PATH
//Atomic integer operations
#define ATOMIC_T LONG
#define NDEV_FMT "%s"
#define NDEV_ARG(ndev) ""
#define ADPT_FMT "%s"
#define ADPT_ARG(adapter) ""
#define FUNC_NDEV_FMT "%s"
#define FUNC_NDEV_ARG(ndev) __func__
#define FUNC_ADPT_FMT "%s"
#define FUNC_ADPT_ARG(adapter) __func__
#define STRUCT_PACKED
#endif

8
include/pci_hal.h
View File

@@ -47,6 +47,14 @@
void rtl8822be_set_hal_ops(PADAPTER padapter);
#endif
#ifdef CONFIG_RTL8822C
void rtl8822ce_set_hal_ops(PADAPTER padapter);
#endif
#ifdef CONFIG_RTL8814B
void rtl8814be_set_hal_ops(PADAPTER padapter);
#endif
u8 rtw_set_hal_ops(_adapter *padapter);
#endif /* __PCIE_HAL_H__ */

7
include/pci_ops.h
View File

@@ -106,4 +106,11 @@
void rtl8821ce_set_intf_ops(struct _io_ops *pops);
#endif
#ifdef CONFIG_RTL8822C
void rtl8822ce_set_intf_ops(struct _io_ops *pops);
#endif
#ifdef CONFIG_RTL8814B
void rtl8814be_set_intf_ops(struct _io_ops *pops);
#endif
#endif

29
include/pci_osintf.h
View File

@@ -35,16 +35,35 @@
//#define PCI_BC_ASPM_LTR BIT4
//#define PCI_BC_ASPM_OBFF BIT5
void rtw_pci_disable_aspm(_adapter *padapter);
void rtw_pci_enable_aspm(_adapter *padapter);
void PlatformClearPciPMEStatus(PADAPTER Adapter);
void rtw_pci_aspm_config(_adapter *padapter);
void rtw_pci_aspm_config_l1off_general(_adapter *padapter, u8 eanble);
#ifdef CONFIG_PCI_DYNAMIC_ASPM
void rtw_pci_aspm_config_dynamic_l1_ilde_time(_adapter *padapter);
#endif
#ifdef CONFIG_64BIT_DMA
u8 PlatformEnableDMA64(PADAPTER Adapter);
#endif
#ifdef CONFIG_PCI_DYNAMIC_ASPM
void rtw_pci_set_aspm_lnkctl(_adapter *padapter, u8 mode);
void rtw_pci_set_l1_latency(_adapter *padapter, u8 mode);
static inline void rtw_pci_dynamic_aspm_set_mode(_adapter *padapter, u8 mode)
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
if (mode == pcipriv->aspm_mode)
return;
pcipriv->aspm_mode = mode;
#ifdef CONFIG_PCI_DYNAMIC_ASPM_LINK_CTRL
rtw_pci_set_aspm_lnkctl(padapter, mode);
#endif
#ifdef CONFIG_PCI_DYNAMIC_ASPM_L1_LATENCY
rtw_pci_set_l1_latency(padapter, mode);
#endif
}
#else
#define rtw_pci_dynamic_aspm_set_mode(adapter, mode)
#endif
#endif

2
include/recv_osdep.h
View File

@@ -23,7 +23,7 @@ extern void _rtw_free_recv_priv(struct recv_priv *precvpriv);
extern s32 rtw_recv_entry(union recv_frame *precv_frame);
void rtw_rframe_set_os_pkt(union recv_frame *rframe);
extern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame);
extern void rtw_recv_returnpacket(IN _nic_hdl cnxt, IN _pkt *preturnedpkt);
extern void rtw_recv_returnpacket(_nic_hdl cnxt, _pkt *preturnedpkt);
extern int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame);

12
include/rtl8188e_dm.h
View File

@@ -15,13 +15,13 @@
#ifndef __RTL8188E_DM_H__
#define __RTL8188E_DM_H__
void rtl8188e_init_dm_priv(IN PADAPTER Adapter);
void rtl8188e_deinit_dm_priv(IN PADAPTER Adapter);
void rtl8188e_InitHalDm(IN PADAPTER Adapter);
void rtl8188e_HalDmWatchDog(IN PADAPTER Adapter);
void rtl8188e_init_dm_priv(PADAPTER Adapter);
void rtl8188e_deinit_dm_priv(PADAPTER Adapter);
void rtl8188e_InitHalDm(PADAPTER Adapter);
void rtl8188e_HalDmWatchDog(PADAPTER Adapter);
/* VOID rtl8192c_dm_CheckTXPowerTracking(IN PADAPTER Adapter); */
/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */
/* void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal); */
/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */
#endif

6
include/rtl8188e_hal.h
View File

@@ -306,9 +306,9 @@ void GetHwReg8188E(PADAPTER padapter, u8 variable, u8 *val);
u8
GetHalDefVar8188E(
IN PADAPTER Adapter,
IN HAL_DEF_VARIABLE eVariable,
IN PVOID pValue
PADAPTER Adapter,
HAL_DEF_VARIABLE eVariable,
void *pValue
);
#ifdef CONFIG_GPIO_API
int rtl8188e_GpioFuncCheck(PADAPTER adapter, u8 gpio_num);

19
include/rtl8188e_recv.h
View File

@@ -20,20 +20,15 @@
#define RECV_BLK_TH RECV_BLK_CNT
#if defined(CONFIG_USB_HCI)
#ifndef MAX_RECVBUF_SZ
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#else
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#else
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#endif
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#endif
#endif /* !MAX_RECVBUF_SZ */

10
include/rtl8188e_rf.h
View File

@@ -17,11 +17,11 @@
int PHY_RF6052_Config8188E(IN PADAPTER Adapter);
void rtl8188e_RF_ChangeTxPath(IN PADAPTER Adapter,
IN u16 DataRate);
int PHY_RF6052_Config8188E(PADAPTER Adapter);
void rtl8188e_RF_ChangeTxPath(PADAPTER Adapter,
u16 DataRate);
void rtl8188e_PHY_RF6052SetBandwidth(
IN PADAPTER Adapter,
IN enum channel_width Bandwidth);
PADAPTER Adapter,
enum channel_width Bandwidth);
#endif/* __RTL8188E_RF_H__ */

2
include/rtl8188f_cmd.h
View File

@@ -158,7 +158,7 @@ enum h2c_cmd_8188F {
#define SET_8188F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
/* _BT_FW_PATCH_0x6A */
#define SET_8188F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
#define SET_8188F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)

6
include/rtl8188f_hal.h
View File

@@ -208,7 +208,7 @@ void Hal_EfuseParseThermalMeter_8188F(PADAPTER padapter, u8 *hwinfo, u8 AutoLoad
void Hal_EfuseParseKFreeData_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
#if 0 /* Do not need for rtl8188f */
VOID Hal_EfuseParseVoltage_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseVoltage_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
#endif
void rtl8188f_set_pll_ref_clk_sel(_adapter *adapter, u8 sel);
@@ -244,7 +244,7 @@ void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
#endif
#ifdef CONFIG_MP_INCLUDED
int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
#endif
void CCX_FwC2HTxRpt_8188f(PADAPTER padapter, u8 *pdata, u8 len);
@@ -254,7 +254,7 @@ u8 HwRateToMRate8188F(u8 rate);
#ifdef CONFIG_PCI_HCI
BOOLEAN InterruptRecognized8188FE(PADAPTER Adapter);
VOID UpdateInterruptMask8188FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
void UpdateInterruptMask8188FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
#endif
#endif

27
include/rtl8188f_recv.h
View File

@@ -17,24 +17,21 @@
#if defined(CONFIG_USB_HCI)
#ifndef MAX_RECVBUF_SZ
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
#ifdef CONFIG_MINIMAL_MEMORY_USAGE
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#else
#ifdef CONFIG_MINIMAL_MEMORY_USAGE
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) /* 8K */
#elif defined(CONFIG_PLATFORM_HISILICON)
#define MAX_RECVBUF_SZ (16384) /* 16k */
#else
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) /* 8K */
#elif defined(CONFIG_PLATFORM_HISILICON)
#define MAX_RECVBUF_SZ (16384) /* 16k */
#else
#define MAX_RECVBUF_SZ (32768) /* 32k */
#endif
/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#define MAX_RECVBUF_SZ (32768) /* 32k */
#endif
/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#endif
#endif /* !MAX_RECVBUF_SZ */
#elif defined(CONFIG_PCI_HCI)

8
include/rtl8188f_rf.h
View File

@@ -15,11 +15,11 @@
#ifndef __RTL8188F_RF_H__
#define __RTL8188F_RF_H__
int PHY_RF6052_Config8188F(IN PADAPTER Adapter);
int PHY_RF6052_Config8188F(PADAPTER Adapter);
VOID
void
PHY_RF6052SetBandwidth8188F(
IN PADAPTER Adapter,
IN enum channel_width Bandwidth);
PADAPTER Adapter,
enum channel_width Bandwidth);
#endif

12
include/rtl8192e_dm.h
View File

@@ -16,13 +16,13 @@
#define __RTL8192E_DM_H__
void rtl8192e_init_dm_priv(IN PADAPTER Adapter);
void rtl8192e_deinit_dm_priv(IN PADAPTER Adapter);
void rtl8192e_InitHalDm(IN PADAPTER Adapter);
void rtl8192e_HalDmWatchDog(IN PADAPTER Adapter);
void rtl8192e_init_dm_priv(PADAPTER Adapter);
void rtl8192e_deinit_dm_priv(PADAPTER Adapter);
void rtl8192e_InitHalDm(PADAPTER Adapter);
void rtl8192e_HalDmWatchDog(PADAPTER Adapter);
/* VOID rtl8192c_dm_CheckTXPowerTracking(IN PADAPTER Adapter); */
/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */
/* void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal); */
/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */
#endif

50
include/rtl8192e_hal.h
View File

@@ -266,27 +266,27 @@ BOOLEAN HalDetectPwrDownMode8192E(PADAPTER Adapter);
/***********************************************************/
/* RTL8192E-MAC Setting */
VOID _InitQueueReservedPage_8192E(IN PADAPTER Adapter);
VOID _InitQueuePriority_8192E(IN PADAPTER Adapter);
VOID _InitTxBufferBoundary_8192E(IN PADAPTER Adapter, IN u8 txpktbuf_bndy);
VOID _InitPageBoundary_8192E(IN PADAPTER Adapter);
/* VOID _InitTransferPageSize_8192E(IN PADAPTER Adapter); */
VOID _InitDriverInfoSize_8192E(IN PADAPTER Adapter, IN u8 drvInfoSize);
VOID _InitRDGSetting_8192E(PADAPTER Adapter);
void _InitID_8192E(IN PADAPTER Adapter);
VOID _InitNetworkType_8192E(IN PADAPTER Adapter);
VOID _InitWMACSetting_8192E(IN PADAPTER Adapter);
VOID _InitAdaptiveCtrl_8192E(IN PADAPTER Adapter);
VOID _InitEDCA_8192E(IN PADAPTER Adapter);
VOID _InitRetryFunction_8192E(IN PADAPTER Adapter);
VOID _BBTurnOnBlock_8192E(IN PADAPTER Adapter);
VOID _InitBeaconParameters_8192E(IN PADAPTER Adapter);
VOID _InitBeaconMaxError_8192E(
IN PADAPTER Adapter,
IN BOOLEAN InfraMode
void _InitQueueReservedPage_8192E(PADAPTER Adapter);
void _InitQueuePriority_8192E(PADAPTER Adapter);
void _InitTxBufferBoundary_8192E(PADAPTER Adapter, u8 txpktbuf_bndy);
void _InitPageBoundary_8192E(PADAPTER Adapter);
/* void _InitTransferPageSize_8192E(PADAPTER Adapter); */
void _InitDriverInfoSize_8192E(PADAPTER Adapter, u8 drvInfoSize);
void _InitRDGSetting_8192E(PADAPTER Adapter);
void _InitID_8192E(PADAPTER Adapter);
void _InitNetworkType_8192E(PADAPTER Adapter);
void _InitWMACSetting_8192E(PADAPTER Adapter);
void _InitAdaptiveCtrl_8192E(PADAPTER Adapter);
void _InitEDCA_8192E(PADAPTER Adapter);
void _InitRetryFunction_8192E(PADAPTER Adapter);
void _BBTurnOnBlock_8192E(PADAPTER Adapter);
void _InitBeaconParameters_8192E(PADAPTER Adapter);
void _InitBeaconMaxError_8192E(
PADAPTER Adapter,
BOOLEAN InfraMode
);
void SetBeaconRelatedRegisters8192E(PADAPTER padapter);
VOID hal_ReadRFType_8192E(PADAPTER Adapter);
void hal_ReadRFType_8192E(PADAPTER Adapter);
/* RTL8192E-MAC Setting
***********************************************************/
@@ -294,15 +294,15 @@ u8 SetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val);
void GetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val);
u8
SetHalDefVar8192E(
IN PADAPTER Adapter,
IN HAL_DEF_VARIABLE eVariable,
IN PVOID pValue
PADAPTER Adapter,
HAL_DEF_VARIABLE eVariable,
void *pValue
);
u8
GetHalDefVar8192E(
IN PADAPTER Adapter,
IN HAL_DEF_VARIABLE eVariable,
IN PVOID pValue
PADAPTER Adapter,
HAL_DEF_VARIABLE eVariable,
void *pValue
);
void rtl8192e_set_hal_ops(struct hal_ops *pHalFunc);

34
include/rtl8192e_recv.h
View File

@@ -18,28 +18,24 @@
#if defined(CONFIG_USB_HCI)
#ifndef MAX_RECVBUF_SZ
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
#ifdef CONFIG_MINIMAL_MEMORY_USAGE
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#else
#ifdef CONFIG_MINIMAL_MEMORY_USAGE
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
#define MAX_RECVBUF_SZ (rtw_rtkm_get_buff_size()) /*depend rtkm*/
#elif defined(CONFIG_PLATFORM_HISILICON)
#define MAX_RECVBUF_SZ (16384) /* 16k */
#else
#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
#define MAX_RECVBUF_SZ (rtw_rtkm_get_buff_size()) /*depend rtkm*/
#elif defined(CONFIG_PLATFORM_HISILICON)
#define MAX_RECVBUF_SZ (16384) /* 16k */
#else
#define MAX_RECVBUF_SZ (32768) /* 32k */
#endif
/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
#undef MAX_RECVBUF_SZ
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
#define MAX_RECVBUF_SZ (32768) /* 32k */
#endif
/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
#undef MAX_RECVBUF_SZ
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
#endif
#endif /* !MAX_RECVBUF_SZ */

8
include/rtl8192e_rf.h
View File

@@ -15,14 +15,14 @@
#ifndef __RTL8192E_RF_H__
#define __RTL8192E_RF_H__
VOID
void
PHY_RF6052SetBandwidth8192E(
IN PADAPTER Adapter,
IN enum channel_width Bandwidth);
PADAPTER Adapter,
enum channel_width Bandwidth);
int
PHY_RF6052_Config_8192E(
IN PADAPTER Adapter);
PADAPTER Adapter);
#endif/* __RTL8192E_RF_H__ */

8
include/rtl8192f_cmd.h
View File

@@ -151,7 +151,7 @@ enum h2c_cmd_8192F {
#define SET_8192F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
/* _BT_FW_PATCH_0x6A */
#define SET_8192F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
#define SET_8192F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
@@ -173,10 +173,10 @@ void rtl8192f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
void rtl8192f_set_FwPsTuneParam_cmd(PADAPTER padapter);
void rtl8192f_download_rsvd_page(PADAPTER padapter, u8 mstatus);
#ifdef CONFIG_BT_COEXIST
void rtl8192f__download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
void rtl8192f_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
#endif /* CONFIG_BT_COEXIST */
#ifdef CONFIG_P2P
void rtl8192f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
void rtl8192f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
#endif /* CONFIG_P2P */
#ifdef CONFIG_TDLS
@@ -186,7 +186,7 @@ void rtl8192f_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
#endif
#ifdef CONFIG_P2P_WOWLAN
void rtl8192f_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
void rtl8192f_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
#endif
s32 FillH2CCmd8192F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);

12
include/rtl8192f_dm.h
View File

@@ -15,13 +15,13 @@
#ifndef __RTL8192F_DM_H__
#define __RTL8192F_DM_H__
void rtl8192f_init_dm_priv(IN PADAPTER Adapter);
void rtl8192f_deinit_dm_priv(IN PADAPTER Adapter);
void rtl8192f_InitHalDm(IN PADAPTER Adapter);
void rtl8192f_HalDmWatchDog(IN PADAPTER Adapter);
void rtl8192f_init_dm_priv(PADAPTER Adapter);
void rtl8192f_deinit_dm_priv(PADAPTER Adapter);
void rtl8192f_InitHalDm(PADAPTER Adapter);
void rtl8192f_HalDmWatchDog(PADAPTER Adapter);
/* VOID rtl8192c_dm_CheckTXPowerTracking(IN PADAPTER Adapter); */
/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */
/* void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal); */
/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */
#endif

17
include/rtl8192f_hal.h
View File

@@ -117,7 +117,8 @@ typedef struct _RT_8192F_FIRMWARE_HDR {
* NS offload: 2 NDP info: 1
*/
#ifdef CONFIG_WOWLAN
#define WOWLAN_PAGE_NUM_8192F 0x07
/* 7 pages for wow rsvd page + 2 pages for pattern */
#define WOWLAN_PAGE_NUM_8192F 0x09
#else
#define WOWLAN_PAGE_NUM_8192F 0x00
#endif
@@ -234,10 +235,10 @@ void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
void Hal_EfuseParseTxPowerInfo_8192F(PADAPTER padapter,
u8 *PROMContent, BOOLEAN AutoLoadFail);
/*
#ifdef CONFIG_BT_COEXIST
void Hal_EfuseParseBTCoexistInfo_8192F(PADAPTER padapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
*/
#endif /* CONFIG_BT_COEXIST */
void Hal_EfuseParseEEPROMVer_8192F(PADAPTER padapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseChnlPlan_8192F(PADAPTER padapter,
@@ -250,9 +251,9 @@ void Hal_EfuseParseXtal_8192F(PADAPTER pAdapter,
u8 *hwinfo, u8 AutoLoadFail);
void Hal_EfuseParseThermalMeter_8192F(PADAPTER padapter,
u8 *hwinfo, u8 AutoLoadFail);
VOID Hal_EfuseParseVoltage_8192F(PADAPTER pAdapter,
void Hal_EfuseParseVoltage_8192F(PADAPTER pAdapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
VOID Hal_EfuseParseBoardType_8192F(PADAPTER Adapter,
void Hal_EfuseParseBoardType_8192F(PADAPTER Adapter,
u8 *PROMContent, BOOLEAN AutoloadFail);
u8 Hal_ReadRFEType_8192F(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
void rtl8192f_set_hal_ops(struct hal_ops *pHalFunc);
@@ -286,7 +287,7 @@ void rtl8192f_stop_thread(_adapter *padapter);
void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
#endif
#ifdef CONFIG_MP_INCLUDED
int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
#endif
void CCX_FwC2HTxRpt_8192f(PADAPTER padapter, u8 *pdata, u8 len);
@@ -306,8 +307,8 @@ void rtl8192f_pretx_cd_config(_adapter *adapter);
#ifdef CONFIG_PCI_HCI
BOOLEAN InterruptRecognized8192FE(PADAPTER Adapter);
VOID UpdateInterruptMask8192FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
VOID InitMAC_TRXBD_8192FE(PADAPTER Adapter);
void UpdateInterruptMask8192FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
void InitMAC_TRXBD_8192FE(PADAPTER Adapter);
u16 get_txbd_rw_reg(u16 ff_hwaddr);
#endif

24
include/rtl8192f_recv.h
View File

@@ -22,22 +22,18 @@
#if defined(CONFIG_USB_HCI)
#ifndef MAX_RECVBUF_SZ
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
#else
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) /* 8K */
#else
#define MAX_RECVBUF_SZ (32768) /* 32k */
#endif
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) /* 8K */
#else
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#define MAX_RECVBUF_SZ (32768) /* 32k */
#endif
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#else
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#endif
#endif /* !MAX_RECVBUF_SZ */

68
include/rtl8192f_rf.h
View File

@@ -15,8 +15,72 @@
#ifndef __RTL8192F_RF_H__
#define __RTL8192F_RF_H__
int PHY_RF6052_Config8192F(IN PADAPTER pdapter);
/*default*/
/*#define CONFIG_8192F_DRV_DIS*/
/*AP*/
#define CONFIG_8192F_TYPE3_DRV_DIS
#define CONFIG_8192F_TYPE4_DRV_DIS
/*unused*/
#define CONFIG_8192F_TYPE13_DRV_DIS
#define CONFIG_8192F_TYPE14_DRV_DIS
#define CONFIG_8192F_TYPE15_DRV_DIS
#define CONFIG_8192F_TYPE16_DRV_DIS
#define CONFIG_8192F_TYPE17_DRV_DIS
#define CONFIG_8192F_TYPE18_DRV_DIS
#define CONFIG_8192F_TYPE19_DRV_DIS
#define CONFIG_8192F_TYPE20_DRV_DIS
#define CONFIG_8192F_TYPE21_DRV_DIS
#define CONFIG_8192F_TYPE22_DRV_DIS
#define CONFIG_8192F_TYPE23_DRV_DIS
#define CONFIG_8192F_TYPE24_DRV_DIS
#define CONFIG_8192F_TYPE25_DRV_DIS
#define CONFIG_8192F_TYPE26_DRV_DIS
#define CONFIG_8192F_TYPE27_DRV_DIS
#define CONFIG_8192F_TYPE28_DRV_DIS
#define CONFIG_8192F_TYPE29_DRV_DIS
#define CONFIG_8192F_TYPE30_DRV_DIS
#define CONFIG_8192F_TYPE31_DRV_DIS
void PHY_RF6052SetBandwidth8192F(IN PADAPTER Adapter, IN enum channel_width Bandwidth);
#ifdef CONFIG_SDIO_HCI /**/
/*usb*/
#define CONFIG_8192F_TYPE1_DRV_DIS
#define CONFIG_8192F_TYPE5_DRV_DIS
#define CONFIG_8192F_TYPE10_DRV_DIS
/*pcie*/
#define CONFIG_8192F_TYPE0_DRV_DIS
#define CONFIG_8192F_TYPE6_DRV_DIS
#define CONFIG_8192F_TYPE7_DRV_DIS
#define CONFIG_8192F_TYPE8_DRV_DIS
#define CONFIG_8192F_TYPE9_DRV_DIS
#define CONFIG_8192F_TYPE12_DRV_DIS
#endif/*CONFIG_SDIO_HCI*/
#ifdef CONFIG_USB_HCI
/*sdio*/
#define CONFIG_8192F_TYPE2_DRV_DIS
#define CONFIG_8192F_TYPE11_DRV_DIS
/*pcie*/
#define CONFIG_8192F_TYPE0_DRV_DIS
#define CONFIG_8192F_TYPE6_DRV_DIS
#define CONFIG_8192F_TYPE7_DRV_DIS
#define CONFIG_8192F_TYPE8_DRV_DIS
#define CONFIG_8192F_TYPE9_DRV_DIS
#define CONFIG_8192F_TYPE12_DRV_DIS
#endif/*CONFIG_USB_HCI*/
#ifdef CONFIG_PCI_HCI
/*sdio*/
#define CONFIG_8192F_TYPE2_DRV_DIS
#define CONFIG_8192F_TYPE11_DRV_DIS
/*usb*/
#define CONFIG_8192F_TYPE1_DRV_DIS
#define CONFIG_8192F_TYPE5_DRV_DIS
#define CONFIG_8192F_TYPE10_DRV_DIS
#endif/*CONFIG_PCI_HCI*/
int PHY_RF6052_Config8192F(PADAPTER pdapter);
void PHY_RF6052SetBandwidth8192F(PADAPTER Adapter, enum channel_width Bandwidth);
#endif/* __RTL8192F_RF_H__ */

5
include/rtl8192f_spec.h
View File

@@ -116,6 +116,7 @@
#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2
#define REG_C2HEVT_CMD_LEN_8192F 0x01AE
#define REG_C2HEVT_CLEAR_8192F 0x01AF
#define REG_TXBUF_WKCAM_OFFSET 0x01B1 /* RTL8192F */
#define REG_MCUTST_1_8192F 0x01C0
#define REG_WOWLAN_WAKE_REASON 0x01C7
#define REG_FMETHR_8192F 0x01C8
@@ -395,6 +396,10 @@
#define REG_LTR_IDLE_LATENCY_V1_8192F 0x0798
#define REG_LTR_ACTIVE_LATENCY_V1_8192F 0x079C
/* GPIO Control */
#define REG_SW_GPIO_SHARE_CTRL_8192F 0x1038
#define REG_SW_GPIO_A_OUT_8192F 0x1040
#define REG_SW_GPIO_A_OEN_8192F 0x1044
/* ************************************************************
* SDIO Bus Specification

2
include/rtl8703b_cmd.h
View File

@@ -158,7 +158,7 @@ enum h2c_cmd_8703B {
#define SET_8703B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
/* _BT_FW_PATCH_0x6A */
#define SET_8703B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
#define SET_8703B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)

8
include/rtl8703b_hal.h
View File

@@ -214,8 +214,8 @@ void Hal_EfuseParseCustomerID_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoL
void Hal_EfuseParseAntennaDiversity_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseXtal_8703B(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
void Hal_EfuseParseThermalMeter_8703B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
VOID Hal_EfuseParseVoltage_8703B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
VOID Hal_EfuseParseBoardType_8703B(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
void Hal_EfuseParseVoltage_8703B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseBoardType_8703B(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
void rtl8703b_set_hal_ops(struct hal_ops *pHalFunc);
void init_hal_spec_8703b(_adapter *adapter);
@@ -249,7 +249,7 @@ void rtl8703b_stop_thread(_adapter *padapter);
void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
#endif
#ifdef CONFIG_MP_INCLUDED
int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
#endif
void CCX_FwC2HTxRpt_8703b(PADAPTER padapter, u8 *pdata, u8 len);
@@ -260,7 +260,7 @@ void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
#ifdef CONFIG_PCI_HCI
BOOLEAN InterruptRecognized8703BE(PADAPTER Adapter);
VOID UpdateInterruptMask8703BE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
void UpdateInterruptMask8703BE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
#endif
#endif

24
include/rtl8703b_recv.h
View File

@@ -22,22 +22,18 @@
#if defined(CONFIG_USB_HCI)
#ifndef MAX_RECVBUF_SZ
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
#else
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) /* 8K */
#else
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
#endif
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) /* 8K */
#else
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
#endif
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#else
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#endif
#endif /* !MAX_RECVBUF_SZ */

8
include/rtl8703b_rf.h
View File

@@ -15,11 +15,11 @@
#ifndef __RTL8703B_RF_H__
#define __RTL8703B_RF_H__
int PHY_RF6052_Config8703B(IN PADAPTER Adapter);
int PHY_RF6052_Config8703B(PADAPTER Adapter);
VOID
void
PHY_RF6052SetBandwidth8703B(
IN PADAPTER Adapter,
IN enum channel_width Bandwidth);
PADAPTER Adapter,
enum channel_width Bandwidth);
#endif

2
include/rtl8710b_cmd.h
View File

@@ -132,7 +132,7 @@ enum h2c_cmd_8710B {
#define SET_8710B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
/* _BT_FW_PATCH_0x6A */
#define SET_8710B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
#define SET_8710B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)

6
include/rtl8710b_hal.h
View File

@@ -213,9 +213,9 @@ void rtl8710b_init_default_value(PADAPTER padapter);
u32 indirect_read32_8710b(PADAPTER padapter, u32 regaddr);
VOID indirect_write32_8710b(PADAPTER padapter, u32 regaddr, u32 data);
void indirect_write32_8710b(PADAPTER padapter, u32 regaddr, u32 data);
u32 hal_query_syson_reg_8710b(PADAPTER padapter, u32 regaddr, u32 bitmask);
VOID hal_set_syson_reg_8710b(PADAPTER padapter, u32 regaddr, u32 bitmask, u32 data);
void hal_set_syson_reg_8710b(PADAPTER padapter, u32 regaddr, u32 bitmask, u32 data);
#define HAL_SetSYSOnReg hal_set_syson_reg_8710b
@@ -241,7 +241,7 @@ void Hal_EfuseParseXtal_8710B(PADAPTER pAdapter,
u8 *hwinfo, u8 AutoLoadFail);
void Hal_EfuseParseThermalMeter_8710B(PADAPTER padapter,
u8 *hwinfo, u8 AutoLoadFail);
VOID Hal_EfuseParseBoardType_8710B(PADAPTER Adapter,
void Hal_EfuseParseBoardType_8710B(PADAPTER Adapter,
u8 *PROMContent, BOOLEAN AutoloadFail);
#endif

26
include/rtl8710b_recv.h
View File

@@ -21,23 +21,19 @@
#if defined(CONFIG_USB_HCI)
#ifndef MAX_RECVBUF_SZ
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
#ifdef CONFIG_MINIMAL_MEMORY_USAGE
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#else
#ifdef CONFIG_MINIMAL_MEMORY_USAGE
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#else
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) /* 8K */
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) /* 8K */
#elif defined(CONFIG_PLATFORM_HISILICON)
#define MAX_RECVBUF_SZ (16384) /* 16k */
#else
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
#endif
#define MAX_RECVBUF_SZ (16384) /* 16k */
#else
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
#endif
#endif
#endif /* !MAX_RECVBUF_SZ */

2
include/rtl8710b_rf.h
View File

@@ -15,6 +15,6 @@
#ifndef __RTL8710B_RF_H__
#define __RTL8710B_RF_H__
int PHY_RF6052_Config8710B(IN PADAPTER pdapter);
int PHY_RF6052_Config8710B(PADAPTER pdapter);
#endif

2
include/rtl8723b_cmd.h
View File

@@ -158,7 +158,7 @@ enum h2c_cmd_8723B {
#define SET_8723B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
/* _BT_FW_PATCH_0x6A */
#define SET_8723B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
#define SET_8723B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)

12
include/rtl8723b_hal.h
View File

@@ -216,9 +216,9 @@ void Hal_EfuseParseCustomerID_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoL
void Hal_EfuseParseAntennaDiversity_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseXtal_8723B(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
void Hal_EfuseParseThermalMeter_8723B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
VOID Hal_EfuseParsePackageType_8723B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
VOID Hal_EfuseParseVoltage_8723B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
VOID Hal_EfuseParseBoardType_8723B(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
void Hal_EfuseParsePackageType_8723B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseVoltage_8723B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseBoardType_8723B(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
void rtl8723b_set_hal_ops(struct hal_ops *pHalFunc);
void init_hal_spec_8723b(_adapter *adapter);
@@ -250,7 +250,7 @@ void rtl8723b_stop_thread(_adapter *padapter);
void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
#endif
#ifdef CONFIG_MP_INCLUDED
int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
#endif
void CCX_FwC2HTxRpt_8723b(PADAPTER padapter, u8 *pdata, u8 len);
@@ -263,12 +263,12 @@ u8 HwRateToMRate8723B(u8 rate);
#ifdef CONFIG_PCI_HCI
BOOLEAN InterruptRecognized8723BE(PADAPTER Adapter);
VOID UpdateInterruptMask8723BE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
void UpdateInterruptMask8723BE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
#endif
#ifdef CONFIG_GPIO_API
int rtl8723b_GpioFuncCheck(PADAPTER adapter, u8 gpio_num);
VOID rtl8723b_GpioMultiFuncReset(PADAPTER adapter, u8 gpio_num);
void rtl8723b_GpioMultiFuncReset(PADAPTER adapter, u8 gpio_num);
#endif
#endif

24
include/rtl8723b_recv.h
View File

@@ -22,22 +22,18 @@
#if defined(CONFIG_USB_HCI)
#ifndef MAX_RECVBUF_SZ
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
#else
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) /* 8K */
#else
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
#endif
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) /* 8K */
#else
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
#endif
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#else
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#endif
#endif /* !MAX_RECVBUF_SZ */

8
include/rtl8723b_rf.h
View File

@@ -15,11 +15,11 @@
#ifndef __RTL8723B_RF_H__
#define __RTL8723B_RF_H__
int PHY_RF6052_Config8723B(IN PADAPTER Adapter);
int PHY_RF6052_Config8723B(PADAPTER Adapter);
VOID
void
PHY_RF6052SetBandwidth8723B(
IN PADAPTER Adapter,
IN enum channel_width Bandwidth);
PADAPTER Adapter,
enum channel_width Bandwidth);
#endif

2
include/rtl8723d_cmd.h
View File

@@ -146,7 +146,7 @@ enum h2c_cmd_8723D {
#define SET_8723D_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
/* _BT_FW_PATCH_0x6A */
#define SET_8723D_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
#define SET_8723D_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)

8
include/rtl8723d_hal.h
View File

@@ -242,9 +242,9 @@ void Hal_EfuseParseXtal_8723D(PADAPTER pAdapter,
u8 *hwinfo, u8 AutoLoadFail);
void Hal_EfuseParseThermalMeter_8723D(PADAPTER padapter,
u8 *hwinfo, u8 AutoLoadFail);
VOID Hal_EfuseParseVoltage_8723D(PADAPTER pAdapter,
void Hal_EfuseParseVoltage_8723D(PADAPTER pAdapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
VOID Hal_EfuseParseBoardType_8723D(PADAPTER Adapter,
void Hal_EfuseParseBoardType_8723D(PADAPTER Adapter,
u8 *PROMContent, BOOLEAN AutoloadFail);
void rtl8723d_set_hal_ops(struct hal_ops *pHalFunc);
@@ -277,7 +277,7 @@ void rtl8723d_stop_thread(_adapter *padapter);
void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
#endif
#ifdef CONFIG_MP_INCLUDED
int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
#endif
void CCX_FwC2HTxRpt_8723d(PADAPTER padapter, u8 *pdata, u8 len);
@@ -296,7 +296,7 @@ void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
#ifdef CONFIG_PCI_HCI
BOOLEAN InterruptRecognized8723DE(PADAPTER Adapter);
VOID UpdateInterruptMask8723DE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
void UpdateInterruptMask8723DE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
u16 get_txbd_rw_reg(u16 ff_hwaddr);
#endif

24
include/rtl8723d_recv.h
View File

@@ -22,22 +22,18 @@
#if defined(CONFIG_USB_HCI)
#ifndef MAX_RECVBUF_SZ
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
#else
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) /* 8K */
#else
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
#endif
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) /* 8K */
#else
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
#endif
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#else
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#endif
#endif /* !MAX_RECVBUF_SZ */

4
include/rtl8723d_rf.h
View File

@@ -15,7 +15,7 @@
#ifndef __RTL8723D_RF_H__
#define __RTL8723D_RF_H__
int PHY_RF6052_Config8723D(IN PADAPTER pdapter);
int PHY_RF6052_Config8723D(PADAPTER pdapter);
void PHY_RF6052SetBandwidth8723D(IN PADAPTER Adapter, IN enum channel_width Bandwidth);
void PHY_RF6052SetBandwidth8723D(PADAPTER Adapter, enum channel_width Bandwidth);
#endif

10
include/rtl8812a_cmd.h
View File

@@ -147,11 +147,11 @@ void rtl8812_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
#define GET_8812_C2H_TX_RPT_FINAL_DATA_RATE(_Header) LE_BITS_TO_1BYTE((_Header + 5), 0, 8)
/* BT_FW_PATCH */
#define SET_8812_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+2, 0, 8, __Value)
#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+3, 0, 8, __Value)
#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+4, 0, 8, __Value)
#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+5, 0, 8, __Value)
#define SET_8812_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+2, 0, 8, __Value)
#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+3, 0, 8, __Value)
#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+4, 0, 8, __Value)
#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+5, 0, 8, __Value)
s32 c2h_handler_8812a(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);

12
include/rtl8812a_dm.h
View File

@@ -15,13 +15,13 @@
#ifndef __RTL8812A_DM_H__
#define __RTL8812A_DM_H__
void rtl8812_init_dm_priv(IN PADAPTER Adapter);
void rtl8812_deinit_dm_priv(IN PADAPTER Adapter);
void rtl8812_InitHalDm(IN PADAPTER Adapter);
void rtl8812_HalDmWatchDog(IN PADAPTER Adapter);
void rtl8812_init_dm_priv(PADAPTER Adapter);
void rtl8812_deinit_dm_priv(PADAPTER Adapter);
void rtl8812_InitHalDm(PADAPTER Adapter);
void rtl8812_HalDmWatchDog(PADAPTER Adapter);
/* VOID rtl8192c_dm_CheckTXPowerTracking(IN PADAPTER Adapter); */
/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */
/* void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal); */
/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */
#endif

10
include/rtl8812a_hal.h
View File

@@ -352,18 +352,18 @@ void rtl8812_stop_thread(PADAPTER padapter);
#ifdef CONFIG_PCI_HCI
BOOLEAN InterruptRecognized8812AE(PADAPTER Adapter);
VOID UpdateInterruptMask8812AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
VOID InitTRXDescHwAddress8812AE(PADAPTER Adapter);
void UpdateInterruptMask8812AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
void InitTRXDescHwAddress8812AE(PADAPTER Adapter);
#endif
#ifdef CONFIG_BT_COEXIST
void rtl8812a_combo_card_WifiOnlyHwInit(PADAPTER Adapter);
#endif
VOID
void
Hal_PatchwithJaguar_8812(
IN PADAPTER Adapter,
IN RT_MEDIA_STATUS MediaStatus
PADAPTER Adapter,
RT_MEDIA_STATUS MediaStatus
);
#endif /* __RTL8188E_HAL_H__ */

34
include/rtl8812a_recv.h
View File

@@ -18,27 +18,23 @@
#if defined(CONFIG_USB_HCI)
#ifndef MAX_RECVBUF_SZ
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
#else
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
#define MAX_RECVBUF_SZ (rtw_rtkm_get_buff_size()) /*depend rtkm*/
#else
#define MAX_RECVBUF_SZ (32768) /*32k*/
#endif
/* #define MAX_RECVBUF_SZ (24576) */ /* 24k */
/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
/* #define MAX_RECVBUF_SZ (15360) */ /* 15k < 16k */
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
#undef MAX_RECVBUF_SZ
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
#define MAX_RECVBUF_SZ (rtw_rtkm_get_buff_size()) /*depend rtkm*/
#else
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#define MAX_RECVBUF_SZ (32768) /*32k*/
#endif
/* #define MAX_RECVBUF_SZ (24576) */ /* 24k */
/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
/* #define MAX_RECVBUF_SZ (15360) */ /* 15k < 16k */
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
#undef MAX_RECVBUF_SZ
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
#else
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#endif
#endif /* !MAX_RECVBUF_SZ */

8
include/rtl8812a_rf.h
View File

@@ -15,14 +15,14 @@
#ifndef __RTL8812A_RF_H__
#define __RTL8812A_RF_H__
VOID
void
PHY_RF6052SetBandwidth8812(
IN PADAPTER Adapter,
IN enum channel_width Bandwidth);
PADAPTER Adapter,
enum channel_width Bandwidth);
int
PHY_RF6052_Config_8812(
IN PADAPTER Adapter);
PADAPTER Adapter);
#endif/* __RTL8188E_RF_H__ */

3
include/rtl8814a_cmd.h
View File

@@ -155,6 +155,9 @@ Set_RA_LDPC_8814(
s32 c2h_handler_8814a(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
#ifdef CONFIG_BT_COEXIST
void rtl8814a_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
#endif /* CONFIG_BT_COEXIST */
#ifdef CONFIG_P2P_PS
void rtl8814_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
#endif /* CONFIG_P2P */

8
include/rtl8814a_dm.h
View File

@@ -15,9 +15,9 @@
#ifndef __RTL8814A_DM_H__
#define __RTL8814A_DM_H__
void rtl8814_init_dm_priv(IN PADAPTER Adapter);
void rtl8814_deinit_dm_priv(IN PADAPTER Adapter);
void rtl8814_InitHalDm(IN PADAPTER Adapter);
void rtl8814_HalDmWatchDog(IN PADAPTER Adapter);
void rtl8814_init_dm_priv(PADAPTER Adapter);
void rtl8814_deinit_dm_priv(PADAPTER Adapter);
void rtl8814_InitHalDm(PADAPTER Adapter);
void rtl8814_HalDmWatchDog(PADAPTER Adapter);
#endif

44
include/rtl8814a_hal.h
View File

@@ -234,13 +234,13 @@ extern char *rtw_fw_mp_bt_file_path;
s32 FirmwareDownload8814A(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw);
void InitializeFirmwareVars8814(PADAPTER padapter);
VOID
void
Hal_InitEfuseVars_8814A(
IN PADAPTER Adapter
PADAPTER Adapter
);
s32 InitLLTTable8814A(
IN PADAPTER Adapter
PADAPTER Adapter
);
@@ -250,9 +250,9 @@ void InitRDGSetting8814A(PADAPTER padapter);
/* EFuse */
u8 GetEEPROMSize8814A(PADAPTER padapter);
VOID hal_InitPGData_8814A(
IN PADAPTER padapter,
IN OUT u8 *PROMContent
void hal_InitPGData_8814A(
PADAPTER padapter,
u8 *PROMContent
);
void hal_ReadPROMVersion8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
@@ -263,28 +263,26 @@ void hal_ReadChannelPlan8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFai
void hal_EfuseParseXtal_8814A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
void hal_ReadAntennaDiversity8814A(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
void hal_Read_TRX_antenna_8814A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
VOID hal_ReadAmplifierType_8814A(
IN PADAPTER Adapter
void hal_ReadAmplifierType_8814A(
PADAPTER Adapter
);
VOID hal_ReadPAType_8814A(
IN PADAPTER Adapter,
IN u8 *PROMContent,
IN BOOLEAN AutoloadFail,
OUT u8 *pPAType,
OUT u8 *pLNAType
void hal_ReadPAType_8814A(
PADAPTER Adapter,
u8 *PROMContent,
BOOLEAN AutoloadFail,
u8 *pPAType,
u8 *pLNAType
);
void hal_ReadPowerTrackingType_8814A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
void hal_GetRxGainOffset_8814A(
PADAPTER Adapter,
pu1Byte PROMContent,
u8 *PROMContent,
BOOLEAN AutoloadFail
);
void Hal_EfuseParseKFreeData_8814A(
IN PADAPTER Adapter,
IN u8 *PROMContent,
IN BOOLEAN AutoloadFail);
PADAPTER Adapter,
u8 *PROMContent,
BOOLEAN AutoloadFail);
void hal_ReadRFEType_8814A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
void hal_EfuseParseBTCoexistInfo8814A(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
@@ -318,13 +316,13 @@ void rtl8814_stop_thread(PADAPTER padapter);
#ifdef CONFIG_PCI_HCI
BOOLEAN InterruptRecognized8814AE(PADAPTER Adapter);
VOID UpdateInterruptMask8814AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
VOID InitMAC_TRXBD_8814AE(PADAPTER Adapter);
void UpdateInterruptMask8814AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
void InitMAC_TRXBD_8814AE(PADAPTER Adapter);
u16 get_txbd_rw_reg(u16 ff_hwaddr);
#endif
#ifdef CONFIG_BT_COEXIST
void rtl8812a_combo_card_WifiOnlyHwInit(PADAPTER Adapter);
void rtl8814a_combo_card_WifiOnlyHwInit(PADAPTER Adapter);
#endif
#endif /* __RTL8188E_HAL_H__ */

26
include/rtl8814a_recv.h
View File

@@ -18,23 +18,19 @@
#if defined(CONFIG_USB_HCI)
#ifndef MAX_RECVBUF_SZ
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
#else
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) /* 8K */
#else
#define MAX_RECVBUF_SZ (32768) /* 32k */
#endif
/* #define MAX_RECVBUF_SZ (24576) */ /* 24k */
/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
/* #define MAX_RECVBUF_SZ (15360) */ /* 15k < 16k */
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) /* 8K */
#else
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#define MAX_RECVBUF_SZ (32768) /* 32k */
#endif
/* #define MAX_RECVBUF_SZ (24576) */ /* 24k */
/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
/* #define MAX_RECVBUF_SZ (15360) */ /* 15k < 16k */
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#else
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#endif
#endif /* !MAX_RECVBUF_SZ */

8
include/rtl8814a_rf.h
View File

@@ -15,14 +15,14 @@
#ifndef __RTL8814A_RF_H__
#define __RTL8814A_RF_H__
VOID
void
PHY_RF6052SetBandwidth8814A(
IN PADAPTER Adapter,
IN enum channel_width Bandwidth);
PADAPTER Adapter,
enum channel_width Bandwidth);
int
PHY_RF6052_Config_8814A(
IN PADAPTER Adapter);
PADAPTER Adapter);
#endif/* __RTL8188E_RF_H__ */

2
include/rtl8814a_spec.h
View File

@@ -555,7 +555,7 @@
/*
* 9. Security Control Registers (Offset: )
* */
#define RWCAM_8814A REG_CAMCMD_8814A /* IN 8190 Data Sheet is called CAMcmd */
#define RWCAM_8814A REG_CAMCMD_8814A /* 8190 Data Sheet is called CAMcmd */
#define WCAMI_8814A REG_CAMWRITE_8814A /* Software write CAM input content */
#define RCAMO_8814A REG_CAMREAD_8814A /* Software read/write CAM config */
#define CAMDBG_8814A REG_CAMDBG_8814A

8
include/rtl8814a_xmit.h
View File

@@ -297,14 +297,14 @@ void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, u8 *ptxdesc);
u8
SCMapping_8814(
IN PADAPTER Adapter,
IN struct pkt_attrib *pattrib
PADAPTER Adapter,
struct pkt_attrib *pattrib
);
u8
BWMapping_8814(
IN PADAPTER Adapter,
IN struct pkt_attrib *pattrib
PADAPTER Adapter,
struct pkt_attrib *pattrib
);

239
include/rtl8814b_hal.h Executable file
View File

@@ -0,0 +1,239 @@
/******************************************************************************
*
* Copyright(c) 2015 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _RTL8814B_HAL_H_
#define _RTL8814B_HAL_H_
#include <osdep_service.h> /* BIT(x) */
#include <drv_types.h> /* PADAPTER */
#include "../hal/halmac/halmac_api.h" /* MAC REG definition */
#ifdef CONFIG_SUPPORT_TRX_SHARED
#define MAX_RECVBUF_SZ 46080 /* 45KB, TX: (256-64)KB */
#else /* !CONFIG_SUPPORT_TRX_SHARED */
#define MAX_RECVBUF_SZ 24576 /* 24KB, TX: 256KB */
#endif /* !CONFIG_SUPPORT_TRX_SHARED */
#if 0
/*
* MAC Register definition
*/
#define REG_AFE_XTAL_CTRL REG_AFE_CTRL1_8814B /* hal_com.c & phydm */
#define REG_AFE_PLL_CTRL REG_AFE_CTRL2_8814B /* hal_com.c & phydm */
#define REG_MAC_PHY_CTRL REG_AFE_CTRL3_8814B /* phydm only */
#endif
#define REG_LEDCFG0 REG_LED_CFG_8814B /* rtw_mp.c */
#if 0
#define MSR (REG_CR_8814B + 2) /* rtw_mp.c & hal_com.c */
#define MSR1 REG_CR_EXT_8814B /* rtw_mp.c & hal_com.c */
#endif
#define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */
#if 0
#define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */
#define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8814B /* hal_com.c */
#endif
#define REG_WKFMCAM_NUM REG_WKFMCAM_CMD_8814B /* hal_com.c: WOWLAN */
#define REG_WOWLAN_WAKE_REASON 0x01C7 /* hal_com.c: WOWLAN */
#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL_8814B + 2) /* hal_com.c: WOWLAN */
#define REG_RXPKT_NUM REG_RXDMA_CTRL_8814B /* hal_com.c: WOWLAN */
/* RXERR_RPT, for rtw_mp.c */
#define RXERR_TYPE_OFDM_PPDU 0
#define RXERR_TYPE_OFDM_FALSE_ALARM 2
#define RXERR_TYPE_OFDM_MPDU_OK 0
#define RXERR_TYPE_OFDM_MPDU_FAIL 1
#define RXERR_TYPE_CCK_PPDU 3
#define RXERR_TYPE_CCK_FALSE_ALARM 5
#define RXERR_TYPE_CCK_MPDU_OK 3
#define RXERR_TYPE_CCK_MPDU_FAIL 4
#define RXERR_TYPE_HT_PPDU 8
#define RXERR_TYPE_HT_FALSE_ALARM 9
#define RXERR_TYPE_HT_MPDU_TOTAL 6
#define RXERR_TYPE_HT_MPDU_OK 6
#define RXERR_TYPE_HT_MPDU_FAIL 7
#define RXERR_TYPE_RX_FULL_DROP 10
#define RXERR_COUNTER_MASK BIT_MASK_RPT_COUNTER_8814B
#define RXERR_RPT_RST BIT_RXERR_RPT_RST_8814B
#define _RXERR_RPT_SEL(type) (BIT_RXERR_RPT_SEL_V1_3_0_8814B(type) \
| ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8814B : 0))
/* hal_com.c:rtw_lps_state_chk() */
#define BIT_PWRBIT_OW_EN BIT_WMAC_TCRPWRMGT_HWDATA_EN_8814B
/*
* BB Register definition
*/
#define rPMAC_Reset 0x100 /* hal_mp.c */
#define rFPGA0_RFMOD 0x800
#define rFPGA0_TxInfo 0x804
#define rOFDMCCKEN_Jaguar 0x808 /* hal_mp.c */
#define rFPGA0_TxGainStage 0x80C /* phydm only */
#define rFPGA0_XA_HSSIParameter1 0x820 /* hal_mp.c */
#define rFPGA0_XA_HSSIParameter2 0x824 /* hal_mp.c */
#define rFPGA0_XB_HSSIParameter1 0x828 /* hal_mp.c */
#define rFPGA0_XB_HSSIParameter2 0x82C /* hal_mp.c */
#define rTxAGC_B_Rate18_06 0x830
#define rTxAGC_B_Rate54_24 0x834
#define rTxAGC_B_CCK1_55_Mcs32 0x838
#define rCCAonSec_Jaguar 0x838 /* hal_mp.c */
#define rTxAGC_B_Mcs03_Mcs00 0x83C
#define rTxAGC_B_Mcs07_Mcs04 0x848
#define rTxAGC_B_Mcs11_Mcs08 0x84C
#define rFPGA0_XA_RFInterfaceOE 0x860
#define rFPGA0_XB_RFInterfaceOE 0x864
#define rTxAGC_B_Mcs15_Mcs12 0x868
#define rTxAGC_B_CCK11_A_CCK2_11 0x86C
#define rFPGA0_XAB_RFInterfaceSW 0x870
#define rFPGA0_XAB_RFParameter 0x878
#define rFPGA0_AnalogParameter4 0x88C /* hal_mp.c & phydm */
#define rFPGA0_XB_LSSIReadBack 0x8A4 /* phydm */
#define rHSSIRead_Jaguar 0x8B0 /* RF read addr (rtl8814b_phy.c) */
#define rC_TxScale_Jaguar2 0x181C /* Pah_C TX scaling factor (hal_mp.c) */
#define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C (hal_mp.c) */
#define rFPGA1_TxInfo 0x90C /* hal_mp.c */
#define rSingleTone_ContTx_Jaguar 0x914 /* hal_mp.c */
/* TX BeamForming */
#define REG_BB_TX_PATH_SEL_1_8814B 0x93C /* rtl8814b_phy.c */
#define REG_BB_TX_PATH_SEL_2_8814B 0x940 /* rtl8814b_phy.c */
/* TX BeamForming */
#define REG_BB_TXBF_ANT_SET_BF1_8814B 0x19AC /* rtl8814b_phy.c */
#define REG_BB_TXBF_ANT_SET_BF0_8814B 0x19B4 /* rtl8814b_phy.c */
#define rCCK0_System 0xA00
#define rCCK0_AFESetting 0xA04
#define rCCK0_DSPParameter2 0xA1C
#define rCCK0_TxFilter1 0xA20
#define rCCK0_TxFilter2 0xA24
#define rCCK0_DebugPort 0xA28
#define rCCK0_FalseAlarmReport 0xA2C
#define rD_TxScale_Jaguar2 0x1A1C /* Path_D TX scaling factor (hal_mp.c) */
#define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D (hal_mp.c) */
#define rOFDM0_TRxPathEnable 0xC04
#define rOFDM0_TRMuxPar 0xC08
#define rA_TxScale_Jaguar 0xC1C /* Pah_A TX scaling factor (hal_mp.c) */
#define rOFDM0_RxDetector1 0xC30 /* rtw_mp.c */
#define rOFDM0_ECCAThreshold 0xC4C /* phydm only */
#define rOFDM0_XAAGCCore1 0xC50 /* phydm only */
#define rA_IGI_Jaguar 0xC50 /* Initial Gain for path-A (hal_mp.c) */
#define rOFDM0_XBAGCCore1 0xC58 /* phydm only */
#define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */
#define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8814b_phy.c) */
#define rOFDM1_LSTF 0xD00
#define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */
#define rA_PIRead_Jaguar 0xD04 /* RF readback with PI (rtl8814b_phy.c) */
#define rA_SIRead_Jaguar 0xD08 /* RF readback with SI (rtl8814b_phy.c) */
#define rB_PIRead_Jaguar 0xD44 /* RF readback with PI (rtl8814b_phy.c) */
#define rB_SIRead_Jaguar 0xD48 /* RF readback with SI (rtl8814b_phy.c) */
#define rTxAGC_A_Rate18_06 0xE00
#define rTxAGC_A_Rate54_24 0xE04
#define rTxAGC_A_CCK1_Mcs32 0xE08
#define rTxAGC_A_Mcs03_Mcs00 0xE10
#define rTxAGC_A_Mcs07_Mcs04 0xE14
#define rTxAGC_A_Mcs11_Mcs08 0xE18
#define rTxAGC_A_Mcs15_Mcs12 0xE1C
#define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */
#define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */
#define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8814b_phy.c) */
/* RFE */
#define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */
#define rB_RFE_Pinmux_Jaguar 0xEB0 /* Path_B RFE control pinmux */
#define rA_RFE_Inv_Jaguar 0xCB4 /* Path_A RFE cotrol */
#define rB_RFE_Inv_Jaguar 0xEB4 /* Path_B RFE control */
#define rA_RFE_Jaguar 0xCB8 /* Path_A RFE cotrol */
#define rB_RFE_Jaguar 0xEB8 /* Path_B RFE control */
#define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */
#define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */
#define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */
#define bMask_RFEInv_Jaguar 0x3FF00000
#define bMask_AntselPathFollow_Jaguar 0x00030000
#define rC_RFE_Pinmux_Jaguar 0x18B4 /* Path_C RFE cotrol pinmux*/
#define rD_RFE_Pinmux_Jaguar 0x1AB4 /* Path_D RFE cotrol pinmux*/
#define rA_RFE_Sel_Jaguar2 0x1990
/* Page1(0x100) */
#define bBBResetB 0x100
/* Page8(0x800) */
#define bCCKEn 0x1000000
#define bOFDMEn 0x2000000
/* Reg 0x80C rFPGA0_TxGainStage */
#define bXBTxAGC 0xF00
#define bXCTxAGC 0xF000
#define bXDTxAGC 0xF0000
/* PageA(0xA00) */
#define bCCKBBMode 0x3
#define bCCKScramble 0x8
#define bCCKTxRate 0x3000
/* General */
#define bMaskByte0 0xFF /* mp, rtw_odm.c & phydm */
#define bMaskByte1 0xFF00 /* hal_mp.c & phydm */
#define bMaskByte2 0xFF0000 /* hal_mp.c & phydm */
#define bMaskByte3 0xFF000000 /* hal_mp.c & phydm */
#define bMaskHWord 0xFFFF0000 /* hal_com.c, rtw_mp.c */
#define bMaskLWord 0x0000FFFF /* mp, hal_com.c & phydm */
#define bMaskDWord 0xFFFFFFFF /* mp, hal, rtw_odm.c & phydm */
#define bEnable 0x1 /* hal_mp.c, rtw_mp.c */
#define bDisable 0x0 /* rtw_mp.c */
#define MAX_STALL_TIME 50 /* unit: us, hal_com_phycfg.c */
#define Rx_Smooth_Factor 20 /* phydm only */
/*
* RF Register definition
*/
#define RF_AC 0x00
#define RF_AC_Jaguar 0x00 /* hal_mp.c */
#define RF_CHNLBW 0x18 /* rtl8814b_phy.c */
#define RF_ModeTableAddr 0x30 /* rtl8814b_phy.c */
#define RF_ModeTableData0 0x31 /* rtl8814b_phy.c */
#define RF_ModeTableData1 0x32 /* rtl8814b_phy.c */
#define RF_0x52 0x52
#define RF_WeLut_Jaguar 0xEF /* rtl8814b_phy.c */
/* General Functions */
void rtl8814b_init_hal_spec(PADAPTER); /* hal/hal_com.c */
#ifdef CONFIG_MP_INCLUDED
/* MP Functions */
#include <rtw_mp.h> /* struct mp_priv */
void rtl8814b_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */
void rtl8814b_mp_config_rfpath(PADAPTER); /* hal_mp.c */
#endif
void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus);
#ifdef CONFIG_USB_HCI
#include <rtl8814bu_hal.h>
#elif defined(CONFIG_PCI_HCI)
#include <rtl8814be_hal.h>
#endif
#endif /* _RTL8814B_HAL_H_ */

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include/rtl8814be_hal.h Normal file
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/******************************************************************************
*
* Copyright(c) 2015 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _RTL8814BE_HAL_H_
#define _RTL8814BE_HAL_H_
#include <drv_types.h> /* PADAPTER */
#define RT_BCN_INT_MASKS (BIT_BCNDMAINT0_MSK_8814B | \
BIT_TXBCN0OK_MSK_8814B | \
BIT_TXBCN0ERR_MSK_8814B | \
BIT_BCNDERR0_MSK_8814B)
/* rtl8814be_ops.c */
void UpdateInterruptMask8814BE(PADAPTER, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
u16 get_txbd_rw_reg(u16 q_idx);
#endif /* _RTL8814BE_HAL_H_ */

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