RinCat/RTL88x2BU-Linux-Driver
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Update to 5.8.7.1

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Rin Cat
2020-08-02 05:12:24 -04:00
parent 314b662331
commit e3b09b28f7
449 changed files with 106089 additions and 83748 deletions
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3
hal/phydm/txbf/haltxbf8822b.c
View File

@@ -306,7 +306,8 @@ hal_txbf_8822b_init(
if (dm->rf_type == RF_2T2R) { /*@2T2R*/
PHYDM_DBG(dm, DBG_TXBF, "%s: rf_type is 2T2R\n", __func__);
config_phydm_trx_mode_8822b(dm, (enum bb_path)3, (enum bb_path)3, true);/*Tx2path*/
config_phydm_trx_mode_8822b(dm, (enum bb_path)3,
(enum bb_path)3, BB_PATH_AB;
}
#if (OMNIPEEK_SNIFFER_ENABLED == 1)

304
hal/phydm/txbf/phydm_hal_txbf_api.c
View File

@@ -179,6 +179,7 @@ u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num)
return ndp_tx_rate;
}
#endif
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
/*this function is only used for BFer*/
void phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
@@ -188,27 +189,39 @@ void phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
if (dm->rf_type == RF_1T1R)
return;
#if (RTL8822C_SUPPORT == 1)
#if (RTL8822C_SUPPORT)
if (dm->support_ic_type == ODM_RTL8822C) {
if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
for (i = RF_PATH_A; i <= RF_PATH_B; i++) {
/*RF mode table write enable*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
BIT(19), 0x1);
/*Select RX mode*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33,
0xF, 3);
/*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e,
0x3, 0x2);
/*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f,
0xfffff, 0x61AFF);
/*RF mode table write disable*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
BIT(19), 0x0);
}
/*Path A ==================*/
/*RF mode table write enable*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x1);
/*Select RX mode*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, 0xF, 3);
/*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, 0x3, 0x2);
/*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0xfffff,
0x65AFF);
/*RF mode table write disable*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x0);
/*Path B ==================*/
/*RF mode table write enable*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x1);
/*Select RX mode*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x33, 0xF, 3);
/*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x3f, 0xfffff,
0x996BF);
/*Select Standby mode*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x33, 0xF, 1);
/*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x3f, 0xfffff,
0x99230);
/*RF mode table write disable*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x0);
}
/*@if Nsts > Nc, don't apply V matrix*/
odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
@@ -219,6 +232,60 @@ void phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
/* logic mapping */
/* TX BF logic map and TX path en for Nsts = 1~2 */
odm_set_bb_reg(dm, R_0x820, 0xff, 0x33);
odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x404);
odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0x33);
odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0x404);
} else {
/*@Disable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
/*@1SS~2ss A, AB*/
odm_set_bb_reg(dm, R_0x820, 0xff, 0x31);
odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x400);
}
}
#endif
#if (RTL8812F_SUPPORT)
if (dm->support_ic_type == ODM_RTL8812F) {
if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
/*Path A ==================*/
/*RF mode table write enable*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x1);
/*Select RX mode*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, 0xF, 3);
/*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, 0x3, 0x3);
/*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0xfffff,
0x61AFE);
/*RF mode table write disable*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x0);
/*Path B ==================*/
/*RF mode table write enable*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x1);
/*Select RX mode*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x33, 0xF, 3);
/*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x3f, 0xfffff,
0xD86BF);
/*RF mode table write disable*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x0);
}
/*@if Nsts > Nc, don't apply V matrix*/
odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
/*@enable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
/* logic mapping */
/* TX BF logic map and TX path en for Nsts = 1~2 */
odm_set_bb_reg(dm, R_0x820, 0xff, 0x33);
odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x404);
odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0x33);
odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0x404);
} else {
@@ -271,9 +338,9 @@ void phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
/* logic mapping */
/* TX BF logic map and TX path en for Nsts = 1~4 */
odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0xff55);
odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0xffff);
/*verification path-AC*/
odm_set_bb_reg(dm, R_0x1e30, 0xffffffff, 0xe4e41010);
odm_set_bb_reg(dm, R_0x1e30, 0xffffffff, 0xe4e4e4e4);
} else {
/*@Disable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
@@ -327,6 +394,137 @@ void phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
}
}
#endif
#if (RTL8197G_SUPPORT)
if (dm->support_ic_type == ODM_RTL8197G) {
if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
/*Path A ==================*/
/*RF mode table write enable*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x1);
/*Set RF Rx mode table*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff,
0x18000);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff,
0x000cf);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff,
0x71fc2);
/*RF mode table write disable*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x0);
/*Path B ==================*/
/*RF mode table write enable*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x1);
/*Set RF Rx mode table*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff,
0x18000);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff,
0x000cf);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff,
0x71fc2);
/*Set RF Standby mode table*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff,
0x18000);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff,
0x000ef);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff,
0x01042);
/*RF mode table write disable*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x0);
}
/*@if Nsts > Nc, don't apply V matrix*/
odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
/*@enable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
/* logic mapping */
/* TX BF logic map and TX path en for Nsts = 1~2 */
odm_set_bb_reg(dm, R_0x820, 0xff, 0x33);
odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x404);
odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0x33);
odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0x404);
} else {
/*@Disable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
/*@1SS~2ss A, AB*/
odm_set_bb_reg(dm, R_0x820, 0xff, 0x31);
odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x400);
}
}
#endif
}
void phydm_mu_rsoml_reset(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3;
PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] %s cnt reset\n", __func__);
odm_memory_set(dm, &rateinfo->num_mu_vht_pkt[0], 0, VHT_RATE_NUM * 2);
odm_memory_set(dm, &rateinfo->num_qry_vht_pkt[0], 0, VHT_RATE_NUM * 2);
}
void phydm_mu_rsoml_init(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3;
PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] %s - cnt init\n", __func__);
rateinfo->enable = 1;
rateinfo->mu_ratio_th = 30;
rateinfo->pre_mu_ratio = 0;
phydm_mu_rsoml_reset(dm);
}
void phydm_mu_rsoml_decision(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3;
u8 offset = 0;
u32 mu_ratio = 0;
u32 su_pkt = 0;
u32 mu_pkt = 0;
u32 total_pkt = 0;
PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML Decision eanble: %d\n",
rateinfo->enable);
if (!rateinfo->enable)
return;
for (offset = 0; offset < VHT_RATE_NUM; offset++) {
mu_pkt += rateinfo->num_mu_vht_pkt[offset];
su_pkt += rateinfo->num_qry_vht_pkt[offset];
}
total_pkt = su_pkt + mu_pkt;
if (total_pkt == 0)
mu_ratio = 0;
else
mu_ratio = (mu_pkt * 100) / total_pkt; // unit:%
PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] MU rx ratio: %d, total pkt: %d\n",
mu_ratio, total_pkt);
if (mu_ratio > rateinfo->mu_ratio_th &&
rateinfo->pre_mu_ratio > rateinfo->mu_ratio_th)
PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML status remain\n");
else if (mu_ratio <= rateinfo->mu_ratio_th &&
rateinfo->pre_mu_ratio <= rateinfo->mu_ratio_th)
PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML status remain\n");
else if (mu_ratio > rateinfo->mu_ratio_th)
odm_set_bb_reg(dm, R_0xc00, BIT(26), 0);
else
odm_set_bb_reg(dm, R_0xc00, BIT(26), 1);
rateinfo->pre_mu_ratio = mu_ratio;
phydm_mu_rsoml_reset(dm);
}
void phydm_txbf_avoid_hang(void *dm_void)
@@ -422,4 +620,70 @@ void phydm_txbf_80p80_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
}
#endif
#endif /*PHYSTS_3RD_TYPE_IC*/
void phydm_bf_debug(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
char help[] = "-h";
u32 var1[3] = {0};
u32 i;
if ((strcmp(input[1], help) == 0)) {
PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{BF ver1 :0}, {NO applyV:0; applyV:1; default:2}\n");
PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{MU RSOML:1}, {MU enable:1/0}, {MU Ratio:40}\n");
return;
}
for (i = 0; i < 3; i++) {
if (input[i + 1])
PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
}
if (var1[0] == 0) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#ifdef PHYDM_BEAMFORMING_SUPPORT
struct _RT_BEAMFORMING_INFO *beamforming_info = NULL;
beamforming_info = &dm->beamforming_info;
if (var1[1] == 0) {
beamforming_info->apply_v_matrix = false;
beamforming_info->snding3ss = true;
PDM_SNPF(*_out_len, *_used, output + *_used,
*_out_len - *_used,
"\r\n dont apply V matrix and 3SS 789 snding\n");
} else if (var1[1] == 1) {
beamforming_info->apply_v_matrix = true;
beamforming_info->snding3ss = true;
PDM_SNPF(*_out_len, *_used, output + *_used,
*_out_len - *_used,
"\r\n apply V matrix and 3SS 789 snding\n");
} else if (var1[1] == 2) {
beamforming_info->apply_v_matrix = true;
beamforming_info->snding3ss = false;
PDM_SNPF(*_out_len, *_used, output + *_used,
*_out_len - *_used,
"\r\n default txbf setting\n");
} else {
PDM_SNPF(*_out_len, *_used, output + *_used,
*_out_len - *_used,
"\r\n unknown cmd!!\n");
}
#endif
#endif
} else if (var1[0] == 1) {
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_bf_rate_info_jgr3 *bfinfo = &dm->bf_rate_info_jgr3;
bfinfo->enable = (u8)var1[1];
bfinfo->mu_ratio_th = (u8)var1[2];
PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[MU RSOML] enable= %d, MU ratio TH= %d\n",
bfinfo->enable, bfinfo->mu_ratio_th);
#endif
}
}
#endif /*CONFIG_BB_TXBF_API*/

21
hal/phydm/txbf/phydm_hal_txbf_api.h
View File

@@ -45,9 +45,9 @@ u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num);
#if (RTL8822B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8192F_SUPPORT == 1 ||\
RTL8814B_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
u8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *throughput,
u8 total_bfee_num, u8 *tx_rate);
u8 phydm_get_ndpa_rate(void *dm_void);
u8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput);
@@ -58,17 +58,28 @@ u8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput);
#define phydm_get_mu_bfee_snding_decision(dm, tp)
#endif
#ifdef PHYSTS_3RD_TYPE_IC
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
struct phydm_bf_rate_info_jgr3 {
u8 enable;
u8 mu_ratio_th;
u32 pre_mu_ratio;
u16 num_mu_vht_pkt[VHT_RATE_NUM];
u16 num_qry_vht_pkt[VHT_RATE_NUM];
};
/*this function is only used for BFer*/
void phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt);
void phydm_txbf_avoid_hang(void *dm_void);
void phydm_mu_rsoml_init(void *dm_void);
void phydm_mu_rsoml_decision(void *dm_void);
#if (RTL8814B_SUPPORT == 1)
void phydm_txbf_80p80_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt);
#endif
#endif /*PHYSTS_3RD_TYPE_IC*/
#endif /*#PHYDM_IC_JGR3_SERIES_SUPPORT*/
void phydm_bf_debug(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len);
#endif
#endif