RinCat/RTL88x2BU-Linux-Driver
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Update to 5.8.7.1

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This commit is contained in:
Rin Cat
2020-08-02 05:12:24 -04:00
parent 314b662331
commit e3b09b28f7
449 changed files with 106089 additions and 83748 deletions
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928
hal/phydm/rtl8822b/halhwimg8822b_bb.c
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File diff suppressed because it is too large Load Diff

11
hal/phydm/rtl8822b/halhwimg8822b_bb.h
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@@ -23,7 +23,7 @@
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.5.3*/
/*Image2HeaderVersion: R3 1.5.10*/
#if (RTL8822B_SUPPORT == 1)
#ifndef __INC_MP_BB_HW_IMG_8822B_H
#define __INC_MP_BB_HW_IMG_8822B_H
@@ -100,6 +100,15 @@ void
odm_read_and_config_mp_8822b_phy_reg_pg_type18(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_phy_reg_pg_type18(void);
/******************************************************************************
* phy_reg_pg_type19.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_phy_reg_pg_type19(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_phy_reg_pg_type19(void);
/******************************************************************************
* phy_reg_pg_type2.TXT
******************************************************************************/

12
hal/phydm/rtl8822b/halhwimg8822b_mac.c
View File

@@ -23,7 +23,7 @@
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.5.3*/
/*Image2HeaderVersion: R3 1.5.10*/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
@@ -104,14 +104,6 @@ check_positive(struct dm_struct *dm,
return false;
}
static boolean
check_negative(struct dm_struct *dm,
const u32 condition1,
const u32 condition2
)
{
return true;
}
/******************************************************************************
* mac_reg.TXT
@@ -309,7 +301,7 @@ odm_read_and_config_mp_8822b_mac_reg(struct dm_struct *dm)
u32
odm_get_version_mp_8822b_mac_reg(void)
{
return 113;
return 117;
}
#endif /* end of HWIMG_SUPPORT*/

2
hal/phydm/rtl8822b/halhwimg8822b_mac.h
View File

@@ -23,7 +23,7 @@
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.5.3*/
/*Image2HeaderVersion: R3 1.5.10*/
#if (RTL8822B_SUPPORT == 1)
#ifndef __INC_MP_MAC_HW_IMG_8822B_H
#define __INC_MP_MAC_HW_IMG_8822B_H

18646
hal/phydm/rtl8822b/halhwimg8822b_rf.c
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File diff suppressed because it is too large Load Diff

442
hal/phydm/rtl8822b/halhwimg8822b_rf.h
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@@ -1,442 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.5.3*/
#if (RTL8822B_SUPPORT == 1)
#ifndef __INC_MP_RF_HW_IMG_8822B_H
#define __INC_MP_RF_HW_IMG_8822B_H
/* Please add following compiler flags definition (#define CONFIG_XXX_DRV_DIS)
* into driver source code to reduce code size if necessary.
* #define CONFIG_8822B_DRV_DIS
* #define CONFIG_8822B_TYPE0_DRV_DIS
* #define CONFIG_8822B_TYPE1_DRV_DIS
* #define CONFIG_8822B_TYPE10_DRV_DIS
* #define CONFIG_8822B_TYPE11_DRV_DIS
* #define CONFIG_8822B_TYPE12_DRV_DIS
* #define CONFIG_8822B_TYPE13_DRV_DIS
* #define CONFIG_8822B_TYPE14_DRV_DIS
* #define CONFIG_8822B_TYPE15_DRV_DIS
* #define CONFIG_8822B_TYPE16_DRV_DIS
* #define CONFIG_8822B_TYPE17_DRV_DIS
* #define CONFIG_8822B_TYPE18_DRV_DIS
* #define CONFIG_8822B_TYPE2_DRV_DIS
* #define CONFIG_8822B_TYPE3_TYPE5_DRV_DIS
* #define CONFIG_8822B_TYPE4_DRV_DIS
* #define CONFIG_8822B_TYPE6_DRV_DIS
* #define CONFIG_8822B_TYPE7_DRV_DIS
* #define CONFIG_8822B_TYPE8_DRV_DIS
* #define CONFIG_8822B_TYPE9_DRV_DIS
* #define CONFIG_8822B_TYPE3_DRV_DIS
* #define CONFIG_8822B_TYPE5_DRV_DIS
*/
#define CONFIG_8822B
#ifdef CONFIG_8822B_DRV_DIS
#undef CONFIG_8822B
#endif
#define CONFIG_8822B_TYPE0
#ifdef CONFIG_8822B_TYPE0_DRV_DIS
#undef CONFIG_8822B_TYPE0
#endif
#define CONFIG_8822B_TYPE1
#ifdef CONFIG_8822B_TYPE1_DRV_DIS
#undef CONFIG_8822B_TYPE1
#endif
#define CONFIG_8822B_TYPE10
#ifdef CONFIG_8822B_TYPE10_DRV_DIS
#undef CONFIG_8822B_TYPE10
#endif
#define CONFIG_8822B_TYPE11
#ifdef CONFIG_8822B_TYPE11_DRV_DIS
#undef CONFIG_8822B_TYPE11
#endif
#define CONFIG_8822B_TYPE12
#ifdef CONFIG_8822B_TYPE12_DRV_DIS
#undef CONFIG_8822B_TYPE12
#endif
#define CONFIG_8822B_TYPE13
#ifdef CONFIG_8822B_TYPE13_DRV_DIS
#undef CONFIG_8822B_TYPE13
#endif
#define CONFIG_8822B_TYPE14
#ifdef CONFIG_8822B_TYPE14_DRV_DIS
#undef CONFIG_8822B_TYPE14
#endif
#define CONFIG_8822B_TYPE15
#ifdef CONFIG_8822B_TYPE15_DRV_DIS
#undef CONFIG_8822B_TYPE15
#endif
#define CONFIG_8822B_TYPE16
#ifdef CONFIG_8822B_TYPE16_DRV_DIS
#undef CONFIG_8822B_TYPE16
#endif
#define CONFIG_8822B_TYPE17
#ifdef CONFIG_8822B_TYPE17_DRV_DIS
#undef CONFIG_8822B_TYPE17
#endif
#define CONFIG_8822B_TYPE18
#ifdef CONFIG_8822B_TYPE18_DRV_DIS
#undef CONFIG_8822B_TYPE18
#endif
#define CONFIG_8822B_TYPE2
#ifdef CONFIG_8822B_TYPE2_DRV_DIS
#undef CONFIG_8822B_TYPE2
#endif
#define CONFIG_8822B_TYPE3_TYPE5
#ifdef CONFIG_8822B_TYPE3_TYPE5_DRV_DIS
#undef CONFIG_8822B_TYPE3_TYPE5
#endif
#define CONFIG_8822B_TYPE4
#ifdef CONFIG_8822B_TYPE4_DRV_DIS
#undef CONFIG_8822B_TYPE4
#endif
#define CONFIG_8822B_TYPE6
#ifdef CONFIG_8822B_TYPE6_DRV_DIS
#undef CONFIG_8822B_TYPE6
#endif
#define CONFIG_8822B_TYPE7
#ifdef CONFIG_8822B_TYPE7_DRV_DIS
#undef CONFIG_8822B_TYPE7
#endif
#define CONFIG_8822B_TYPE8
#ifdef CONFIG_8822B_TYPE8_DRV_DIS
#undef CONFIG_8822B_TYPE8
#endif
#define CONFIG_8822B_TYPE9
#ifdef CONFIG_8822B_TYPE9_DRV_DIS
#undef CONFIG_8822B_TYPE9
#endif
#define CONFIG_8822B_TYPE3
#ifdef CONFIG_8822B_TYPE3_DRV_DIS
#undef CONFIG_8822B_TYPE3
#endif
#define CONFIG_8822B_TYPE5
#ifdef CONFIG_8822B_TYPE5_DRV_DIS
#undef CONFIG_8822B_TYPE5
#endif
/******************************************************************************
* radioa.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_radioa(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_radioa(void);
/******************************************************************************
* radiob.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_radiob(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_radiob(void);
/******************************************************************************
* txpowertrack.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack(void);
/******************************************************************************
* txpowertrack_type0.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type0(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type0(void);
/******************************************************************************
* txpowertrack_type1.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type1(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type1(void);
/******************************************************************************
* txpowertrack_type10.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type10(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type10(void);
/******************************************************************************
* txpowertrack_type11.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type11(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type11(void);
/******************************************************************************
* txpowertrack_type12.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type12(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type12(void);
/******************************************************************************
* txpowertrack_type13.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type13(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type13(void);
/******************************************************************************
* txpowertrack_type14.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type14(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type14(void);
/******************************************************************************
* txpowertrack_type15.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type15(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type15(void);
/******************************************************************************
* txpowertrack_type16.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type16(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type16(void);
/******************************************************************************
* txpowertrack_type17.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type17(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type17(void);
/******************************************************************************
* txpowertrack_type18.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type18(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type18(void);
/******************************************************************************
* txpowertrack_type2.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type2(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type2(void);
/******************************************************************************
* txpowertrack_type3_type5.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type3_type5(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type3_type5(void);
/******************************************************************************
* txpowertrack_type4.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type4(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type4(void);
/******************************************************************************
* txpowertrack_type6.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type6(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type6(void);
/******************************************************************************
* txpowertrack_type7.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type7(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type7(void);
/******************************************************************************
* txpowertrack_type8.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type8(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type8(void);
/******************************************************************************
* txpowertrack_type9.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type9(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type9(void);
/******************************************************************************
* txpwr_lmt.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt(void);
/******************************************************************************
* txpwr_lmt_type12.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type12(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type12(void);
/******************************************************************************
* txpwr_lmt_type15.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type15(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type15(void);
/******************************************************************************
* txpwr_lmt_type16.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type16(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type16(void);
/******************************************************************************
* txpwr_lmt_type17.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type17(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type17(void);
/******************************************************************************
* txpwr_lmt_type18.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type18(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type18(void);
/******************************************************************************
* txpwr_lmt_type2.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type2(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type2(void);
/******************************************************************************
* txpwr_lmt_type3.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type3(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type3(void);
/******************************************************************************
* txpwr_lmt_type4.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type4(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type4(void);
/******************************************************************************
* txpwr_lmt_type5.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type5(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type5(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

304
hal/phydm/rtl8822b/phydm_hal_api8822b.c
View File

@@ -77,16 +77,16 @@ void phydm_8822b_type18_rfe(struct dm_struct *dm, u8 channel)
/* signal source */
odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x177517);
odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x177517);
odm_set_bb_reg(dm, R_0xcb4, MASKLWORD, 0x7557);
odm_set_bb_reg(dm, R_0xeb4, MASKLWORD, 0x7557);
odm_set_bb_reg(dm, R_0xcb4, MASKLWORD, 0x7577);
odm_set_bb_reg(dm, R_0xeb4, MASKLWORD, 0x7577);
odm_set_bb_reg(dm, R_0xcb8, BIT(5), 0);
odm_set_bb_reg(dm, R_0xeb8, BIT(5), 0);
} else if (channel > 64) {
/* signal source */
odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x177517);
odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x177517);
odm_set_bb_reg(dm, R_0xcb4, MASKLWORD, 0x7575);
odm_set_bb_reg(dm, R_0xeb4, MASKLWORD, 0x7575);
odm_set_bb_reg(dm, R_0xcb4, MASKLWORD, 0x7577);
odm_set_bb_reg(dm, R_0xeb4, MASKLWORD, 0x7577);
odm_set_bb_reg(dm, R_0xcb8, BIT(5), 0);
odm_set_bb_reg(dm, R_0xeb8, BIT(5), 0);
}
@@ -124,6 +124,11 @@ void phydm_8822b_type18_rfe(struct dm_struct *dm, u8 channel)
odm_set_bb_reg(dm, R_0xebc, (BIT(11) | BIT(10) | BIT(9)
| BIT(8)), 0x0);
if (channel <= 64)
odm_set_bb_reg(dm, 0xcbc, BIT(9), 0x1);
else
odm_set_bb_reg(dm, 0xcbc, BIT(8), 0x1);
/* delay 400ns for PAPE */
/* odm_set_bb_reg(p_dm, 0x810, MASKBYTE3|BIT20|BIT21*/
/* |BIT22|BIT23, 0x211); */
@@ -132,16 +137,16 @@ void phydm_8822b_type18_rfe(struct dm_struct *dm, u8 channel)
if (dm->rx_ant_status == BB_PATH_AB ||
dm->tx_ant_status == BB_PATH_AB) {
/* 2TX or 2RX */
odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0x5501);
odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0x5501);
odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa501);
odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa501);
} else if (dm->rx_ant_status == dm->tx_ant_status) {
/* TXA+RXA or TXB+RXB */
odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0x5500);
odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0x5500);
odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa500);
odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa500);
} else {
/* TXB+RXA or TXA+RXB */
odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0x5005);
odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0x5005);
odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa005);
odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa005);
}
}
}
@@ -219,11 +224,9 @@ u32 phydm_check_bit_mask(u32 bit_mask, u32 data_original, u32 data)
}
__iram_odm_func__
void phydm_rfe_8822b_setting(void *dm_void, u8 rfe_n, u8 mux_sel,
void phydm_rfe_8822b_setting(struct dm_struct *dm, u8 rfe_n, u8 mux_sel,
u8 inv_en, u8 source_sel)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s ======>\n", __func__);
PHYDM_DBG(dm, ODM_PHY_CONFIG,
"RFE[%d]:{Path=0x%x}{inv_en=%d}{source=0x%x}\n", rfe_n,
@@ -280,7 +283,6 @@ __iram_odm_func__
void phydm_rfe_4_11(struct dm_struct *dm, u8 channel)
{
boolean is_channel_2g = (channel <= 14) ? true : false;
u8 rfe_type = dm->rfe_type;
/*TRSW=trsw_forced_BT ? 0x804[0]:(0xCB8[2]?0xCB8[0]:trsw_lut);*/
/*trsw_lut = TXON*/
@@ -435,7 +437,6 @@ __iram_odm_func__
void phydm_rfe_ifem(struct dm_struct *dm, u8 channel)
{
boolean is_channel_2g = (channel <= 14) ? true : false;
u8 rfe_type = dm->rfe_type;
if (is_channel_2g) {
/* signal source */
@@ -638,7 +639,7 @@ phydm_rfe_8822b(struct dm_struct *dm, u8 channel)
else if ((rfe_type == 0) || (rfe_type == 3) || (rfe_type == 5) ||
(rfe_type == 8) || (rfe_type == 10) || (rfe_type == 12) ||
(rfe_type == 13) || (rfe_type == 14) || (rfe_type == 16) ||
(rfe_type == 17))
(rfe_type == 17) || (rfe_type == 19))
/* @iFEM */
phydm_rfe_ifem(dm, channel);
else if (rfe_type == 15)
@@ -767,7 +768,8 @@ void phydm_ccapar_by_rfe_8822b(struct dm_struct *dm)
odm_move_memory(dm, cca_efem, cca_efem_ccut, 12 * 4);
if (dm->rfe_type == 3 || dm->rfe_type == 5 ||
dm->rfe_type == 12 || dm->rfe_type == 15 ||
dm->rfe_type == 16 || dm->rfe_type == 17) {
dm->rfe_type == 16 || dm->rfe_type == 17 ||
dm->rfe_type == 19) {
odm_move_memory(dm, cca_ifem, cca_ifem_ccut_rfe, 12 * 4);
is_rfe_type = true;
} else {
@@ -910,6 +912,7 @@ phydm_write_txagc_1byte_8822b(struct dm_struct *dm,
__iram_odm_func__
void phydm_get_condi_num_acc_8822b(void *dm_void)
{
#if (PHYDM_FW_API_FUNC_ENABLE_8822B)
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
u8 i = 0;
@@ -923,6 +926,7 @@ void phydm_get_condi_num_acc_8822b(void *dm_void)
/*@disable report condition number*/
/*odm_set_bb_reg(dm, R_0x1988, BIT(22), 0x0);*/
#endif
#endif
}
__iram_odm_func__
@@ -1184,6 +1188,7 @@ u8 phydm_dsde_ch_idx(struct dm_struct *dm)
__iram_odm_func__
void phydm_dsde_nbi(struct dm_struct *dm)
{
#if (PHYDM_FW_API_FUNC_ENABLE_8822B)
u8 set_nbi = PHYDM_SET_NO_NEED;
/* Modify CCA parameters due to NBI */
@@ -1191,7 +1196,7 @@ void phydm_dsde_nbi(struct dm_struct *dm)
odm_set_bb_reg(dm, 0x82c, 0xff000, 0x86);
else
odm_set_bb_reg(dm, 0x82c, 0xff000, 0x97);
if (dm->rfe_type == 12) {
if (dm->rfe_type == 12 || dm->rfe_type == 19) {
if (*dm->band_width == CHANNEL_WIDTH_20) {
if (*dm->channel >= 5 && *dm->channel <= 7)
odm_set_bb_reg(dm, 0x82c, 0xf000, 0x3);
@@ -1265,11 +1270,13 @@ void phydm_dsde_nbi(struct dm_struct *dm)
} else {
set_nbi = PHYDM_SET_NO_NEED;
}
#endif
}
__iram_odm_func__
void phydm_dsde_csi(struct dm_struct *dm)
{
#if (PHYDM_FW_API_FUNC_ENABLE_8822B)
u8 set_result_csi = PHYDM_SET_NO_NEED;
if (*dm->band_width == CHANNEL_WIDTH_20) {
@@ -1328,6 +1335,7 @@ void phydm_dsde_csi(struct dm_struct *dm)
} else {
set_result_csi = PHYDM_SET_NO_NEED;
}
#endif
}
__iram_odm_func__
@@ -1387,21 +1395,21 @@ void phydm_dynamic_spur_det_eliminate(struct dm_struct *dm)
if (k == 0) {
f_pt_2g = freq_2g_n1[idx];
f_pt_2g_b = freq_2g_n1[idx] | BIT(16);
if (idx <= 10) {
if (idx < 10) {
f_pt_5g = freq_5g_n1[idx];
f_pt_5g_b = freq_5g_n1[idx] | BIT(16);
}
} else if (k == 1) {
f_pt_2g = freq_2g[idx];
f_pt_2g_b = freq_2g[idx] | BIT(16);
if (idx <= 10) {
if (idx < 10) {
f_pt_5g = freq_5g[idx];
f_pt_5g_b = freq_5g[idx] | BIT(16);
}
} else if (k == 2) {
f_pt_2g = freq_2g_p1[idx];
f_pt_2g_b = freq_2g_p1[idx] | BIT(16);
if (idx <= 10) {
if (idx < 10) {
f_pt_5g = freq_5g_p1[idx];
f_pt_5g_b = freq_5g_p1[idx] | BIT(16);
}
@@ -1530,18 +1538,17 @@ void phydm_dynamic_spur_det_eliminate(struct dm_struct *dm)
__iram_odm_func__
void phydm_spur_calibration_8822b(struct dm_struct *dm)
{
#ifdef CONFIG_8822B_SPUR_CALIBRATION
if (*dm->is_scan_in_process)
return;
#ifdef CONFIG_8822B_SPUR_CALIBRATION
odm_set_bb_reg(dm, R_0x87c, BIT(13), 0x0);
odm_set_bb_reg(dm, R_0xc20, BIT(28), 0x0);
odm_set_bb_reg(dm, R_0xe20, BIT(28), 0x0);
phydm_dynamic_spur_det_eliminate(dm);
PHYDM_DBG(dm, ODM_COMP_API,
"Enable spur eliminator at normal\n");
odm_set_bb_reg(dm, R_0x87c, BIT(13), 0x0);
odm_set_bb_reg(dm, R_0xc20, BIT(28), 0x0);
odm_set_bb_reg(dm, R_0xe20, BIT(28), 0x0);
phydm_dynamic_spur_det_eliminate(dm);
PHYDM_DBG(dm, ODM_COMP_API, "Enable spur eliminator at normal\n");
#else
PHYDM_DBG(dm, ODM_COMP_API, "NBI and CSI notch at normal\n");
PHYDM_DBG(dm, ODM_COMP_API, "NBI and CSI notch at normal\n");
#endif
}
@@ -1624,7 +1631,7 @@ config_phydm_switch_band_8822b(struct dm_struct *dm,
}
}
if (dm->rfe_type == 12) {
if (dm->rfe_type == 12 || dm->rfe_type == 19) {
odm_set_rf_reg(dm, RF_PATH_A, RF_0xb3, RFREGOFFSETMASK,
0x3C360);
odm_set_rf_reg(dm, RF_PATH_B, RF_0xb3, RFREGOFFSETMASK,
@@ -1689,7 +1696,7 @@ config_phydm_switch_band_8822b(struct dm_struct *dm,
}
}
if (dm->rfe_type == 12) {
if (dm->rfe_type == 12 || dm->rfe_type == 19) {
odm_set_rf_reg(dm, RF_PATH_A, RF_0xb3, RFREGOFFSETMASK,
0xFC760);
odm_set_rf_reg(dm, RF_PATH_B, RF_0xb3, RFREGOFFSETMASK,
@@ -2290,46 +2297,60 @@ config_phydm_switch_channel_bw_8822b(struct dm_struct *dm,
return true;
}
__iram_odm_func__
boolean
config_phydm_trx_mode_8822b(struct dm_struct *dm,
enum bb_path tx_path,
enum bb_path rx_path,
boolean is_tx2_path)
__odm_func__
void
phydm_config_cck_tx_path_8822b(struct dm_struct *dm, enum bb_path tx_path)
{
u32 rf_reg33 = 0;
u16 counter = 0;
PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s ======> TX:0x%x, RX:0x%x\n", __func__,
tx_path, rx_path);
if (dm->is_disable_phy_api) {
PHYDM_DBG(dm, ODM_PHY_CONFIG, "disable PHY API\n");
return true;
}
if (((tx_path & ~BB_PATH_AB) != 0) || ((rx_path & ~BB_PATH_AB) != 0)) {
PHYDM_DBG(dm, ODM_PHY_CONFIG, "Wrong set\n");
return false;
}
/* @[mode table] RF mode of path-A and path-B */
/* @Cannot shut down path-A, beacause synthesizer will be shut down */
/* when path-A is in shut down mode */
/* @3-wire setting */
/* @0: shutdown, 1: standby, 2: TX, 3: RX */
if ((tx_path | rx_path) & BB_PATH_A)
odm_set_bb_reg(dm, R_0xc08, MASKLWORD, 0x3231);
if (tx_path == BB_PATH_A)
odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x8);
else if (tx_path == BB_PATH_B)
odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x4);
else
odm_set_bb_reg(dm, R_0xc08, MASKLWORD, 0x1111);
odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0xc);
}
if ((tx_path | rx_path) & BB_PATH_B)
odm_set_bb_reg(dm, R_0xe08, MASKLWORD, 0x3231);
else
odm_set_bb_reg(dm, R_0xe08, MASKLWORD, 0x1111);
__odm_func__
void
phydm_config_ofdm_tx_path_8822b(struct dm_struct *dm, enum bb_path tx_path_en,
enum bb_path tx_path_sel_1ss)
{
/* @Set TX logic map and TX path_en*/
if (tx_path_en == BB_PATH_A) { /* @1T, 1ss */
odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x001);
} else if (tx_path_en == BB_PATH_B) {
odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x002);
} else { /*BB_PATH_AB*/
if (tx_path_sel_1ss == BB_PATH_A) {
odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x001);
odm_set_bb_reg(dm, R_0x940, 0xfff0, 0x043);
} else if (tx_path_sel_1ss == BB_PATH_B) {
odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x002);
odm_set_bb_reg(dm, R_0x940, 0xfff0, 0x043);
} else { /*BB_PATH_AB*/
odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x043);
odm_set_bb_reg(dm, R_0x940, 0xfff0, 0x043);
}
}
#if 1
/* @TX logic map and TX path en for Nsts = 2*/
/*
* @Due to LO is stand-by while 1T at path-b in normal driver,
* @so 0x940 is the same setting btw path-A/B
*/
if (tx_path_en == BB_PATH_A || tx_path_en == BB_PATH_B) {
odm_set_bb_reg(dm, R_0x940, 0xf0, 0x1);
odm_set_bb_reg(dm, R_0x940, 0xff00, 0x0);
}
#endif
}
/*@[TX Antenna Setting] ==========================================*/
__iram_odm_func__
void phydm_config_tx_path_8822b(struct dm_struct *dm, enum bb_path tx_path,
enum bb_path tx_path_sel_1ss,
enum bb_path tx_path_sel_cck)
{
dm->tx_ant_status = (u8)tx_path;
dm->tx_1ss_status = tx_path_sel_1ss;
/* Set TX antenna by Nsts */
odm_set_bb_reg(dm, R_0x93c, (BIT(19) | BIT(18)), 0x3);
@@ -2337,7 +2358,16 @@ config_phydm_trx_mode_8822b(struct dm_struct *dm,
/* @Control CCK TX path by 0xa07[7] */
odm_set_bb_reg(dm, R_0x80c, BIT(30), 0x1);
/* TX path HW block enable */
odm_set_bb_reg(dm, R_0x80c, MASKBYTE0, (tx_path << 4) | tx_path);
/*---- [CCK] ----*/
phydm_config_cck_tx_path_8822b(dm, tx_path_sel_cck);
/*---- [OFDM] ----*/
#if 1
phydm_config_ofdm_tx_path_8822b(dm, tx_path, tx_path_sel_1ss);
#else
/* TX logic map and TX path en for Nsts = 1, and CCK TX path*/
if (tx_path & BB_PATH_A) {
odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x001);
@@ -2355,8 +2385,6 @@ config_phydm_trx_mode_8822b(struct dm_struct *dm,
else
odm_set_bb_reg(dm, R_0x940, 0xfff0, 0x43);
/* TX path HW block enable */
odm_set_bb_reg(dm, R_0x80c, MASKBYTE0, ((tx_path << 4) | tx_path));
/* Tx2path for 1ss */
if (!(tx_path == BB_PATH_A || tx_path == BB_PATH_B)) {
@@ -2367,8 +2395,13 @@ config_phydm_trx_mode_8822b(struct dm_struct *dm,
odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0xc);
}
}
#endif
}
/*@[RX Antenna Setting] ==========================================*/
__iram_odm_func__
void phydm_config_rx_path_8822b(struct dm_struct *dm, enum bb_path rx_path)
{
dm->rx_ant_status = (u8)rx_path;
/*@Disable MRC for CCK CCA */
odm_set_bb_reg(dm, R_0xa2c, BIT(22), 0x0);
@@ -2382,66 +2415,93 @@ config_phydm_trx_mode_8822b(struct dm_struct *dm,
odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x5); /*@01,01*/
/* RX path enable */
odm_set_bb_reg(dm, R_0x808, MASKBYTE0, ((rx_path << 4) | rx_path));
odm_set_bb_reg(dm, R_0x808, MASKBYTE0, (rx_path << 4) | rx_path);
if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
/* @1R */
#if 0
/* @Disable MRC for CCA */
/* odm_set_bb_reg(dm, R_0xa2c, BIT22, 0x0); */
#endif
#if 0
/* @Disable MRC for barker */
/* odm_set_bb_reg(dm, R_0xa2c, BIT18, 0x0); */
#endif
#if 0
/* @Disable CCK antenna diversity */
/* odm_set_bb_reg(dm, R_0xa00, BIT15, 0x0); */
#endif
/* @Disable Antenna weighting */
/*@AntWgt_en*/
odm_set_bb_reg(dm, R_0x1904, BIT(16), 0x0);
/*@htstf ant-wgt enable = 0*/
/* @htstf ant-wgt enable = 0*/
odm_set_bb_reg(dm, R_0x800, BIT(28), 0x0);
/*@MRC_mode = 'original ZF eqz'*/
/* @MRC_mode = 'original ZF eqz'*/
odm_set_bb_reg(dm, R_0x850, BIT(23), 0x0);
} else {
/* @2R */
#if 0
/* @Enable MRC for CCA */
/* odm_set_bb_reg(dm, R_0xa2c, BIT22, 0x1); */
#endif
#if 0
/* @Enable MRC for barker */
/* odm_set_bb_reg(dm, R_0xa2c, BIT18, 0x1); */
#endif
#if 0
/* @Disable CCK antenna diversity */
/* odm_set_bb_reg(dm, R_0xa00, BIT15, 0x0); */
#endif
/* @Enable Antenna weighting */
/*@AntWgt_en*/
odm_set_bb_reg(dm, R_0x1904, BIT(16), 0x1);
/*@htstf ant-wgt enable = 1*/
/* @htstf ant-wgt enable = 1*/
odm_set_bb_reg(dm, R_0x800, BIT(28), 0x1);
/*@MRC_mode = 'modified ZF eqz'*/
/* @MRC_mode = 'modified ZF eqz'*/
odm_set_bb_reg(dm, R_0x850, BIT(23), 0x1);
}
}
/* Update TXRX antenna status for PHYDM */
dm->tx_ant_status = (tx_path & 0x3);
dm->rx_ant_status = (rx_path & 0x3);
__iram_odm_func__
boolean
config_phydm_trx_mode_8822b(struct dm_struct *dm,
enum bb_path tx_path_en,
enum bb_path rx_path,
enum bb_path tx_path_sel_1ss)
{
#ifdef CONFIG_PATH_DIVERSITY
struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
#endif
u32 rf_reg33 = 0;
u16 counter = 0;
PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s ======> TX:0x%x, RX:0x%x\n", __func__,
tx_path_en, rx_path);
if (dm->is_disable_phy_api) {
PHYDM_DBG(dm, ODM_PHY_CONFIG, "disable PHY API\n");
return true;
}
if ((tx_path_en & ~BB_PATH_AB) || (rx_path & ~BB_PATH_AB)) {
PHYDM_DBG(dm, ODM_PHY_CONFIG, "Wrong set\n");
return false;
}
/* @[mode table] RF mode of path-A and path-B
* Cannot shut down path-A, beacause synthesizer will be shut down
* when path-A is in shut down mode
*/
/* @[3-wire setting]
* 0:shutdown, 1:standby, 2:TX, 3:RX
*/
if ((tx_path_en | rx_path) & BB_PATH_A)
odm_set_bb_reg(dm, R_0xc08, MASKLWORD, 0x3231);
else
odm_set_bb_reg(dm, R_0xc08, MASKLWORD, 0x1111);
if ((tx_path_en | rx_path) & BB_PATH_B)
odm_set_bb_reg(dm, R_0xe08, MASKLWORD, 0x3231);
else
odm_set_bb_reg(dm, R_0xe08, MASKLWORD, 0x1111);
#ifdef CONFIG_PATH_DIVERSITY
if (tx_path_en == BB_PATH_A || tx_path_en == BB_PATH_B) {
p_div->stop_path_div = true;
tx_path_sel_1ss = tx_path_en;
} else if (tx_path_en == BB_PATH_AB) {
if (tx_path_sel_1ss == BB_PATH_AUTO) {
p_div->stop_path_div = false;
tx_path_sel_1ss = p_div->default_tx_path;
} else { /* @BB_PATH_AB, BB_PATH_A, BB_PATH_B*/
p_div->stop_path_div = true;
}
}
#else
tx_path_sel_1ss = tx_path_en;
#endif
/*@[TX Antenna Setting] ==========================================*/
phydm_config_tx_path_8822b(dm, tx_path_en,
tx_path_sel_1ss, tx_path_sel_1ss);
/*@[RX Antenna Setting] ==========================================*/
phydm_config_rx_path_8822b(dm, rx_path);
/* @MP driver need to support path-B TX\RX */
while (1) {
counter++;
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREG_MASK, 0x80000);
@@ -2461,7 +2521,8 @@ config_phydm_trx_mode_8822b(struct dm_struct *dm,
}
}
if (*dm->mp_mode || (*dm->antenna_test) || dm->normal_rx_path) {
if (*dm->mp_mode || *dm->antenna_test || dm->normal_rx_path ||
tx_path_sel_1ss == BB_PATH_B || tx_path_sel_1ss == BB_PATH_AUTO) {
/* @0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080e */
/* @0xef 0x00000 suggested by Lucas*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREG_MASK, 0x80000);
@@ -2512,17 +2573,6 @@ config_phydm_parameter_init_8822b(struct dm_struct *dm,
odm_set_bb_reg(dm, R_0x808, (BIT(28) | BIT(29)), 0x3);
PHYDM_DBG(dm, ODM_PHY_CONFIG,
"Post set: enable OFDM/CCK block\n");
#if (PHYDM_FW_API_FUNC_ENABLE_8822B == 1)
} else if (type == ODM_INIT_FW_SETTING) {
u8 h2c_content[4] = {0};
h2c_content[0] = dm->rfe_type;
h2c_content[1] = dm->rf_type;
h2c_content[2] = dm->cut_version;
h2c_content[3] = (dm->tx_ant_status << 4) | dm->rx_ant_status;
odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_GENERAL_INIT, 4, h2c_content);
#endif
} else {
PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: Wrong type!!\n", __func__);
return false;

11
hal/phydm/rtl8822b/phydm_hal_api8822b.h
View File

@@ -100,11 +100,16 @@ config_phydm_switch_channel_bw_8822b(struct dm_struct *dm,
u8 central_ch,
u8 primary_ch_idx,
enum channel_width bw);
void
phydm_config_tx_path_8822b(struct dm_struct *dm, enum bb_path tx_path,
enum bb_path tx_path_sel_1ss,
enum bb_path tx_path_sel_cck);
boolean
config_phydm_trx_mode_8822b(struct dm_struct *dm,
enum bb_path tx_path, enum bb_path rx_path,
boolean is_tx2_path);
enum bb_path tx_path_en,
enum bb_path rx_path,
enum bb_path tx_path_sel_1ss);
boolean
config_phydm_parameter_init_8822b(struct dm_struct *dm,
@@ -117,8 +122,6 @@ boolean
phydm_write_txagc_1byte_8822b(struct dm_struct *dm, u32 pw_idx,
enum rf_path path, u8 hw_rate);
void phydm_init_hw_info_by_rfe_type_8822b(struct dm_struct *dm);
void phydm_get_condi_num_acc_8822b(void *dm_void);
u32 phydm_get_condi_num_8822b(struct dm_struct *dm);

300
hal/phydm/rtl8822b/phydm_rtl8822b.c
View File

@@ -282,12 +282,28 @@ void phydm_1rcca_setting(struct dm_struct *dm, boolean enable_1rcca)
/* @Enable or disable 1RCCA setting accrodding to the control from driver */
if (enable_1rcca) {
if (reg_32 == 0x0)
odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x13); /* @CCK path-a */
/* @CCK path-a */
odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x13);
else if (reg_32 == 0x5)
odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x23); /* @CCK path-b */
/* @CCK path-b */
odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x23);
} else {
odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x33); /* @disable 1RCCA */
odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x0); /* @CCK default is at path-a */
if (dm->valid_path_set == BB_PATH_A) {
/* @disable 1RCCA */
/* @CCK default is at path-a */
odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x31);
odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x0);
} else if (dm->valid_path_set == BB_PATH_B) {
/* @disable 1RCCA */
/* @CCK default is at path-a */
odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x32);
odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x5);
} else {
/* @disable 1RCCA */
/* @CCK default is at path-a */
odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x33);
odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x0);
}
}
}
@@ -333,12 +349,8 @@ void phydm_somlrxhp_setting(struct dm_struct *dm, boolean switch_soml)
if (switch_soml) {
odm_set_bb_reg(dm, R_0x19a8, MASKDWORD, 0xd90a0000);
/* @Following are RxHP settings for T2R as always low, workaround for OTA test, required to classify */
odm_set_bb_reg(dm, R_0xc04, (BIT(21) | BIT(18)), 0x0);
odm_set_bb_reg(dm, R_0xe04, (BIT(21) | BIT(18)), 0x0);
} else {
odm_set_bb_reg(dm, R_0x19a8, MASKDWORD, 0x090a0000);
odm_set_bb_reg(dm, R_0xc04, (BIT(21) | BIT(18)), 0x0);
odm_set_bb_reg(dm, R_0xe04, (BIT(21) | BIT(18)), 0x0);
}
/* @Dynamic RxHP setting with SoML on/off apply on all RFE type */
@@ -454,279 +466,7 @@ void phydm_dynamic_ant_weighting_8822b(void *dm_void)
}
}
#endif
#ifdef CONFIG_MCC_DM
#ifdef DYN_ANT_WEIGHTING_SUPPORT
void phydm_set_weighting_cmn(struct dm_struct *dm)
{
PHYDM_DBG(dm, DBG_COMP_MCC, "phydm_set_weighting_cmn\n");
odm_set_bb_reg(dm, 0xc04, (BIT(18)|BIT(21)), 0x0);
odm_set_bb_reg(dm, 0xe04, (BIT(18)|BIT(21)), 0x0);
}
void phydm_set_weighting_mcc(u8 b_equal_weighting, void *dm_void, u8 port)
{
/*u8 reg_8;*/
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _phydm_mcc_dm_ *mcc_dm = &dm ->mcc_dm;
u8 val_0x98e, val_0x98f, val_0x81b;
PHYDM_DBG(dm , DBG_COMP_MCC, "ant_weighting_mcc ,port = %d\n", port);
if (b_equal_weighting) {
val_0x98e = (u8)(odm_get_bb_reg(dm , 0x98c, 0x00ff0000)>>16) & 0xc0;
val_0x98f = (u8)(odm_get_bb_reg(dm , 0x98c, 0xff000000)>>24) & 0x7f;
val_0x81b = (u8)(odm_get_bb_reg(dm , 0x818, 0xff000000)>>24) & 0xfd;
PHYDM_DBG(dm , DBG_COMP_MCC, "Equal weighting ,rssi_min = %d\n",
dm ->rssi_min);
/*equal weighting*/
/*
odm_set_bb_reg(p_dm_odm, 0x98c, 0x7fc0000, 0x0);
odm_set_bb_reg(p_dm_odm, 0x818, BIT(26), 0x0);
reg_8 = odm_get_bb_reg(p_dm_odm, 0xf94, BIT(0)|BIT(1)|BIT(2));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Equal weighting ,rssi_min = %d\n, 0xf94[2:0] = 0x%x\n", p_dm_odm->rssi_min, reg_8));*/
}
else
{
val_0x98e = 0x44;
val_0x98f = 0x43;
val_0x81b = (u8)(odm_get_bb_reg(dm , 0x818, 0xff000000)>>24) | BIT(2);
PHYDM_DBG(dm , DBG_COMP_MCC, "AGC weighting ,rssi_min = %d\n",
dm ->rssi_min);
/*fix sec_min_wgt = 1/2*/
/*
odm_set_bb_reg(p_dm_odm, 0x98c, MASKDWORD, 0x43440000);
odm_set_bb_reg(p_dm_odm, 0x818, BIT(26), 0x1);
reg_8 = odm_get_bb_reg(p_dm_odm, 0xf94, BIT(0)|BIT(1)|BIT(2));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("AGC weighting ,rssi_min = %d\n, 0xf94[2:0] = 0x%x\n", p_dm_odm->rssi_min, reg_8));*/
}
mcc_dm->mcc_reg_id[2] = 0x2;
mcc_dm->mcc_dm_reg[2] = 0x98e;
mcc_dm->mcc_dm_val[2][port] = val_0x98e;
mcc_dm->mcc_reg_id[3] = 0x3;
mcc_dm->mcc_dm_reg[3] = 0x98f;
mcc_dm->mcc_dm_val[3][port] = val_0x98f;
mcc_dm->mcc_reg_id[4] = 0x4;
mcc_dm->mcc_dm_reg[4] = 0x81b;
mcc_dm->mcc_dm_val[4][port] = val_0x81b;
}
void phydm_dyn_ant_dec_mcc(u8 port, u8 rssi_in, void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 rssi_l2h = 43, rssi_h2l = 37;
if (rssi_in == 0xff) {
phydm_set_weighting_mcc(FALSE, dm, port);
}
else if (rssi_in >= rssi_l2h) {
phydm_set_weighting_mcc(TRUE, dm, port);
}
else if (rssi_in <= rssi_h2l) {
phydm_set_weighting_mcc(FALSE, dm, port);
}
}
void phydm_dynamic_ant_weighting_mcc_8822b(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
u8 i;
phydm_set_weighting_cmn(dm);
for (i = 0; i <= 1; i++)
phydm_dyn_ant_dec_mcc(i, mcc_dm->mcc_rssi[i], dm);
}
#endif /*#ifdef DYN_ANT_WEIGHTING_SUPPORT*/
void phydm_mcc_init (void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
u8 i;
/*PHYDM_DBG(dm, DBG_COMP_MCC, ("MCC init\n"));*/
PHYDM_DBG(dm, DBG_COMP_MCC, "MCC init\n");
for (i = 0; i < MCC_DM_REG_NUM; i++ ) {
mcc_dm->mcc_reg_id[i] = 0xff;
mcc_dm->mcc_dm_reg[i] = 0;
mcc_dm->mcc_dm_val[i][0] = 0;
mcc_dm->mcc_dm_val[i][1] = 0;
}
for (i = 0; i < NUM_STA; i++ ) {
mcc_dm->sta_macid[0][i] = 0xff;
mcc_dm->sta_macid[1][i] = 0xff;
}
/* Function init */
dm->is_stop_dym_ant_weighting = 0;
}
u8 phydm_check(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
struct cmn_sta_info *p_entry = NULL;
u8 shift = 0;
u8 i = 0;
u8 j = 0;
u8 rssi_tmp_min[2] = {0xff, 0xff};
u8 sta_num = 8;
u8 mcc_macid = 0;
for (i = 0;i <= 1;i++) {
for (j = 0;j < sta_num;j++) {
if (mcc_dm->sta_macid[i][j] != 0xff) {
mcc_macid = mcc_dm->sta_macid[i][j];
p_entry = dm->phydm_sta_info[mcc_macid];
if (p_entry == NULL) {
PHYDM_DBG(dm, DBG_COMP_MCC, "Pentry == NULL(mac=%d)\n",
mcc_dm->sta_macid[i][j]);
return _FAIL;
}
PHYDM_DBG(dm, DBG_COMP_MCC, "undecorated_smoothed_pwdb=%d\n",
p_entry->rssi_stat.rssi);
if (p_entry->rssi_stat.rssi < rssi_tmp_min[i])
rssi_tmp_min[i] = p_entry->rssi_stat.rssi;
}
}
}
mcc_dm->mcc_rssi[0] = (u8)rssi_tmp_min[0];
mcc_dm->mcc_rssi[1] = (u8)rssi_tmp_min[1];
return _SUCCESS;
}
void phydm_mcc_h2ccmd_rst(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
u8 i;
u8 regid;
u8 h2c_mcc[H2C_MAX_LENGTH];
/* RST MCC */
for (i = 0; i < H2C_MAX_LENGTH; i++ ) {
h2c_mcc[i] = 0xff;
}
h2c_mcc[0] = 0x00;
odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH, h2c_mcc);
PHYDM_DBG(dm, DBG_COMP_MCC, "MCC H2C RST\n");
}
void phydm_mcc_h2ccmd(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
u8 i;
u8 regid;
u8 h2c_mcc[H2C_MAX_LENGTH];
if (mcc_dm->mcc_rf_channel[0] == 0xff && mcc_dm->mcc_rf_channel[1] == 0xff) {
PHYDM_DBG(dm, DBG_COMP_MCC, "MCC channel Error\n");
return;
}
/* Set Channel number */
for (i = 0; i < H2C_MAX_LENGTH; i++ ) {
h2c_mcc[i] = 0xff;
}
h2c_mcc[0] = 0xe0;
h2c_mcc[1] = (u8)(mcc_dm->mcc_rf_channel[0]);
h2c_mcc[2] = (u8)(mcc_dm->mcc_rf_channel[0] >> 8);
h2c_mcc[3] = (u8)(mcc_dm->mcc_rf_channel[1]);
h2c_mcc[4] = (u8)(mcc_dm->mcc_rf_channel[1] >> 8);
h2c_mcc[5] = 0xff;
h2c_mcc[6] = 0xff;
odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH, h2c_mcc);
PHYDM_DBG(dm, DBG_COMP_MCC, "MCC H2C SetCH: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
h2c_mcc[0], h2c_mcc[1], h2c_mcc[2], h2c_mcc[3], h2c_mcc[4],
h2c_mcc[5], h2c_mcc[6]);
/* Set Reg and value*/
for (i = 0; i < H2C_MAX_LENGTH; i++ ) {
h2c_mcc[i] = 0xff;
}
for (i = 0; i < MCC_DM_REG_NUM; i++ ) {
regid = mcc_dm->mcc_reg_id[i];
if (regid!=0xff) {
h2c_mcc[0] = 0xa0 | (regid & 0x1f);
h2c_mcc[1] = (u8)(mcc_dm->mcc_dm_reg[i]);
h2c_mcc[2] = (u8)(mcc_dm->mcc_dm_reg[i] >> 8);
h2c_mcc[3] = mcc_dm->mcc_dm_val[i][0];
h2c_mcc[4] = mcc_dm->mcc_dm_val[i][1];
h2c_mcc[5] = 0xff;
h2c_mcc[6] = 0xff;
odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH, h2c_mcc);
PHYDM_DBG(dm, DBG_COMP_MCC, "MCC H2C: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
h2c_mcc[0], h2c_mcc[1], h2c_mcc[2], h2c_mcc[3], h2c_mcc[4],
h2c_mcc[5], h2c_mcc[6]);
}
}
}
void phydm_mcc_ctrl(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
PHYDM_DBG(dm, DBG_COMP_MCC, "MCC status: %x\n", mcc_dm->mcc_status);
/*MCC stage no change*/
if (mcc_dm->mcc_status == mcc_dm->mcc_pre_status)
return;
/*Not in MCC stage*/
if (mcc_dm->mcc_status == 0)
{
/* Enable normal Ant-weighting */
dm->is_stop_dym_ant_weighting = 0;
/* Enable normal DIG */
odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, 0x20);
}
else
{
/* Disable normal Ant-weighting */
dm->is_stop_dym_ant_weighting = 1;
/* Enable normal DIG */
odm_pause_dig(dm, PHYDM_PAUSE_NO_SET, PHYDM_PAUSE_LEVEL_1, 0x20);
}
if (mcc_dm->mcc_status == 0 && mcc_dm->mcc_pre_status != 0)
phydm_mcc_init(dm);
mcc_dm->mcc_pre_status = mcc_dm->mcc_status;
}
void phydm_fill_mcccmd( void *dm_void, u8 regid, u16 reg_add, u8 val0, u8 val1)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
mcc_dm->mcc_reg_id[regid] = regid;
mcc_dm->mcc_dm_reg[regid] = reg_add;
mcc_dm->mcc_dm_val[regid][0] = val0;
mcc_dm->mcc_dm_val[regid][1] = val1;
}
void phydm_mcc_switch(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
s8 ret;
phydm_mcc_ctrl(dm);
if (mcc_dm->mcc_status == 0) {/*Not in MCC stage*/
phydm_mcc_h2ccmd_rst(dm);
return;
}
PHYDM_DBG(dm, DBG_COMP_MCC, "MCC switch\n");
ret = phydm_check(dm);
if (ret == _FAIL) {
PHYDM_DBG(dm, DBG_COMP_MCC, "MCC check fail\n");
return;
}
/* Set IGI*/
phydm_mcc_igi_cal(dm);
/* Set Antenna Gain*/
#if (RTL8822B_SUPPORT == 1)
phydm_dynamic_ant_weighting_mcc_8822b(dm);
#endif
/* Set H2C Cmd*/
phydm_mcc_h2ccmd(dm);
}
#endif
#ifdef CONFIG_DYNAMIC_BYPASS
void

11
hal/phydm/rtl8822b/phydm_rtl8822b.h
View File

@@ -30,17 +30,6 @@
void phydm_dynamic_ant_weighting_8822b(void *dm_void);
#endif
#ifdef CONFIG_MCC_DM
#ifdef DYN_ANT_WEIGHTING_SUPPORT
void phydm_dynamic_ant_weighting_mcc_8822b(void *dm_void);
#endif /*#ifdef DYN_ANT_WEIGHTING_SUPPORT*/
void phydm_fill_mcccmd( void *dm_void, u8 regid, u16 reg_add, u8 val0, u8 val1);
u8 phydm_check(void *dm_void);
void phydm_mcc_init (void *dm_void);
void phydm_mcc_switch(void *dm_void);
#endif /*#ifdef CONFIG_MCC_DM*/
void phydm_1rcca_setting(struct dm_struct *dm, boolean enable_1rcca);
void phydm_somlrxhp_setting(struct dm_struct *dm, boolean switch_soml);

4
hal/phydm/rtl8822b/version_rtl8822b.h
View File

@@ -29,6 +29,6 @@
* You do not need to fill up the version.h anymore,
* only the maintenance supervisor fills it before formal release.
*/
#define RELEASE_DATE_8822B 20181129
#define RELEASE_DATE_8822B 20190726
#define COMMIT_BY_8822B "BB_Colin"
#define RELEASE_VERSION_8822B 113
#define RELEASE_VERSION_8822B 117