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Rin Cat
2020-08-02 05:12:24 -04:00
parent 314b662331
commit e3b09b28f7
449 changed files with 106089 additions and 83748 deletions
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19934
hal/phydm/halrf/rtl8822b/halhwimg8822b_rf.c Normal file
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File diff suppressed because it is too large Load Diff

466
hal/phydm/halrf/rtl8822b/halhwimg8822b_rf.h Normal file
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@@ -0,0 +1,466 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.5.10*/
#if (RTL8822B_SUPPORT == 1)
#ifndef __INC_MP_RF_HW_IMG_8822B_H
#define __INC_MP_RF_HW_IMG_8822B_H
/* Please add following compiler flags definition (#define CONFIG_XXX_DRV_DIS)
* into driver source code to reduce code size if necessary.
* #define CONFIG_8822B_DRV_DIS
* #define CONFIG_8822B_TYPE0_DRV_DIS
* #define CONFIG_8822B_TYPE1_DRV_DIS
* #define CONFIG_8822B_TYPE10_DRV_DIS
* #define CONFIG_8822B_TYPE11_DRV_DIS
* #define CONFIG_8822B_TYPE12_DRV_DIS
* #define CONFIG_8822B_TYPE13_DRV_DIS
* #define CONFIG_8822B_TYPE14_DRV_DIS
* #define CONFIG_8822B_TYPE15_DRV_DIS
* #define CONFIG_8822B_TYPE16_DRV_DIS
* #define CONFIG_8822B_TYPE17_DRV_DIS
* #define CONFIG_8822B_TYPE18_DRV_DIS
* #define CONFIG_8822B_TYPE19_DRV_DIS
* #define CONFIG_8822B_TYPE2_DRV_DIS
* #define CONFIG_8822B_TYPE3_TYPE5_DRV_DIS
* #define CONFIG_8822B_TYPE4_DRV_DIS
* #define CONFIG_8822B_TYPE6_DRV_DIS
* #define CONFIG_8822B_TYPE7_DRV_DIS
* #define CONFIG_8822B_TYPE8_DRV_DIS
* #define CONFIG_8822B_TYPE9_DRV_DIS
* #define CONFIG_8822B_TYPE3_DRV_DIS
* #define CONFIG_8822B_TYPE5_DRV_DIS
*/
#define CONFIG_8822B
#ifdef CONFIG_8822B_DRV_DIS
#undef CONFIG_8822B
#endif
#define CONFIG_8822B_TYPE0
#ifdef CONFIG_8822B_TYPE0_DRV_DIS
#undef CONFIG_8822B_TYPE0
#endif
#define CONFIG_8822B_TYPE1
#ifdef CONFIG_8822B_TYPE1_DRV_DIS
#undef CONFIG_8822B_TYPE1
#endif
#define CONFIG_8822B_TYPE10
#ifdef CONFIG_8822B_TYPE10_DRV_DIS
#undef CONFIG_8822B_TYPE10
#endif
#define CONFIG_8822B_TYPE11
#ifdef CONFIG_8822B_TYPE11_DRV_DIS
#undef CONFIG_8822B_TYPE11
#endif
#define CONFIG_8822B_TYPE12
#ifdef CONFIG_8822B_TYPE12_DRV_DIS
#undef CONFIG_8822B_TYPE12
#endif
#define CONFIG_8822B_TYPE13
#ifdef CONFIG_8822B_TYPE13_DRV_DIS
#undef CONFIG_8822B_TYPE13
#endif
#define CONFIG_8822B_TYPE14
#ifdef CONFIG_8822B_TYPE14_DRV_DIS
#undef CONFIG_8822B_TYPE14
#endif
#define CONFIG_8822B_TYPE15
#ifdef CONFIG_8822B_TYPE15_DRV_DIS
#undef CONFIG_8822B_TYPE15
#endif
#define CONFIG_8822B_TYPE16
#ifdef CONFIG_8822B_TYPE16_DRV_DIS
#undef CONFIG_8822B_TYPE16
#endif
#define CONFIG_8822B_TYPE17
#ifdef CONFIG_8822B_TYPE17_DRV_DIS
#undef CONFIG_8822B_TYPE17
#endif
#define CONFIG_8822B_TYPE18
#ifdef CONFIG_8822B_TYPE18_DRV_DIS
#undef CONFIG_8822B_TYPE18
#endif
#define CONFIG_8822B_TYPE19
#ifdef CONFIG_8822B_TYPE19_DRV_DIS
#undef CONFIG_8822B_TYPE19
#endif
#define CONFIG_8822B_TYPE2
#ifdef CONFIG_8822B_TYPE2_DRV_DIS
#undef CONFIG_8822B_TYPE2
#endif
#define CONFIG_8822B_TYPE3_TYPE5
#ifdef CONFIG_8822B_TYPE3_TYPE5_DRV_DIS
#undef CONFIG_8822B_TYPE3_TYPE5
#endif
#define CONFIG_8822B_TYPE4
#ifdef CONFIG_8822B_TYPE4_DRV_DIS
#undef CONFIG_8822B_TYPE4
#endif
#define CONFIG_8822B_TYPE6
#ifdef CONFIG_8822B_TYPE6_DRV_DIS
#undef CONFIG_8822B_TYPE6
#endif
#define CONFIG_8822B_TYPE7
#ifdef CONFIG_8822B_TYPE7_DRV_DIS
#undef CONFIG_8822B_TYPE7
#endif
#define CONFIG_8822B_TYPE8
#ifdef CONFIG_8822B_TYPE8_DRV_DIS
#undef CONFIG_8822B_TYPE8
#endif
#define CONFIG_8822B_TYPE9
#ifdef CONFIG_8822B_TYPE9_DRV_DIS
#undef CONFIG_8822B_TYPE9
#endif
#define CONFIG_8822B_TYPE3
#ifdef CONFIG_8822B_TYPE3_DRV_DIS
#undef CONFIG_8822B_TYPE3
#endif
#define CONFIG_8822B_TYPE5
#ifdef CONFIG_8822B_TYPE5_DRV_DIS
#undef CONFIG_8822B_TYPE5
#endif
/******************************************************************************
* radioa.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_radioa(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_radioa(void);
/******************************************************************************
* radiob.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_radiob(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_radiob(void);
/******************************************************************************
* txpowertrack.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack(void);
/******************************************************************************
* txpowertrack_type0.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type0(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type0(void);
/******************************************************************************
* txpowertrack_type1.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type1(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type1(void);
/******************************************************************************
* txpowertrack_type10.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type10(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type10(void);
/******************************************************************************
* txpowertrack_type11.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type11(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type11(void);
/******************************************************************************
* txpowertrack_type12.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type12(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type12(void);
/******************************************************************************
* txpowertrack_type13.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type13(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type13(void);
/******************************************************************************
* txpowertrack_type14.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type14(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type14(void);
/******************************************************************************
* txpowertrack_type15.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type15(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type15(void);
/******************************************************************************
* txpowertrack_type16.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type16(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type16(void);
/******************************************************************************
* txpowertrack_type17.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type17(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type17(void);
/******************************************************************************
* txpowertrack_type18.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type18(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type18(void);
/******************************************************************************
* txpowertrack_type19.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type19(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type19(void);
/******************************************************************************
* txpowertrack_type2.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type2(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type2(void);
/******************************************************************************
* txpowertrack_type3_type5.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type3_type5(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type3_type5(void);
/******************************************************************************
* txpowertrack_type4.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type4(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type4(void);
/******************************************************************************
* txpowertrack_type6.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type6(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type6(void);
/******************************************************************************
* txpowertrack_type7.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type7(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type7(void);
/******************************************************************************
* txpowertrack_type8.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type8(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type8(void);
/******************************************************************************
* txpowertrack_type9.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type9(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type9(void);
/******************************************************************************
* txpwr_lmt.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt(void);
/******************************************************************************
* txpwr_lmt_type12.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type12(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type12(void);
/******************************************************************************
* txpwr_lmt_type15.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type15(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type15(void);
/******************************************************************************
* txpwr_lmt_type16.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type16(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type16(void);
/******************************************************************************
* txpwr_lmt_type17.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type17(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type17(void);
/******************************************************************************
* txpwr_lmt_type18.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type18(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type18(void);
/******************************************************************************
* txpwr_lmt_type19.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type19(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type19(void);
/******************************************************************************
* txpwr_lmt_type2.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type2(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type2(void);
/******************************************************************************
* txpwr_lmt_type3.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type3(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type3(void);
/******************************************************************************
* txpwr_lmt_type4.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type4(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type4(void);
/******************************************************************************
* txpwr_lmt_type5.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type5(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type5(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

21
hal/phydm/halrf/rtl8822b/halrf_8822b.c
View File

@@ -424,18 +424,17 @@ void get_delta_swing_table_8822b(void *dm_void,
void aac_check_8822b(struct dm_struct *dm)
{
struct _hal_rf_ *rf = &dm->rf_table;
u32 temp;
static boolean firstrun = true;
if (firstrun) {
if (!rf->aac_checked) {
RF_DBG(dm, DBG_RF_LCK, "[LCK]AAC check for 8822b\n");
temp = odm_get_rf_reg(dm, RF_PATH_A, 0xc9, 0xf8);
if (temp < 4 || temp > 7) {
odm_set_rf_reg(dm, RF_PATH_A, 0xca, BIT(19), 0x0);
odm_set_rf_reg(dm, RF_PATH_A, 0xb2, 0x7c000, 0x6);
}
firstrun = false;
rf->aac_checked = true;
}
}
@@ -538,16 +537,18 @@ void phy_set_rf_path_switch_8822b(void *adapter, boolean is_main)
odm_set_bb_reg(dm, R_0x1704, MASKDWORD, 0x0000ff00);
odm_set_bb_reg(dm, R_0x1700, MASKDWORD, 0xc00f0038);
if (is_main) {
if (dm->rfe_type != 0x12) {
if (is_main) {
#if 0
/*odm_set_bb_reg(dm, R_0xcbd, 0x3, 0x2); WiFi*/
/*odm_set_bb_reg(dm, R_0xcbd, 0x3, 0x2); WiFi*/
#endif
odm_set_bb_reg(dm, R_0xcbc, (BIT(9) | BIT(8)), 0x2); /*WiFi*/
} else {
odm_set_bb_reg(dm, R_0xcbc, (BIT(9) | BIT(8)), 0x2); /*WiFi*/
} else {
#if 0
/*odm_set_bb_reg(dm, R_0xcbd, 0x3, 0x1); BT*/
/*odm_set_bb_reg(dm, R_0xcbd, 0x3, 0x1); BT*/
#endif
odm_set_bb_reg(dm, R_0xcbc, (BIT(9) | BIT(8)), 0x1); /*BT*/
odm_set_bb_reg(dm, R_0xcbc, (BIT(9) | BIT(8)), 0x1); /*BT*/
}
}
}

305
hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c
View File

@@ -80,6 +80,59 @@ void do_iqk_8822b(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
}
#endif
u32 _iqk_ltec_read_8822b(struct dm_struct *dm, u16 reg_addr)
{
u32 j = 0;
/*wait for ready bit before access 0x1700*/
odm_write_4byte(dm, 0x1700, 0x800f0000 | reg_addr);
do {
j++;
} while (((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) && (j < 30000));
return odm_read_4byte(dm, 0x1708); /*get read data*/
}
void _iqk_ltec_write_8822b(struct dm_struct *dm, u16 reg_addr, u32 bit_mask,
u32 reg_value)
{
u32 val, i = 0, j = 0, bitpos = 0;
if (bit_mask == 0x0)
return;
if (bit_mask == 0xffffffff) {
odm_write_4byte(dm, 0x1704, reg_value); /*put write data*/
/*wait for ready bit before access 0x1700*/
do {
j++;
} while (((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) && (j < 30000));
odm_write_4byte(dm, 0x1700, 0xc00f0000 | reg_addr);
} else {
for (i = 0; i <= 31; i++) {
if (((bit_mask >> i) & 0x1) == 0x1) {
bitpos = i;
break;
}
}
/*read back register value before write*/
val = _iqk_ltec_read_8822b(dm, reg_addr);
val = (val & (~bit_mask)) | (reg_value << bitpos);
odm_write_4byte(dm, 0x1704, val); /*put write data*/
/*wait for ready bit before access 0x1700*/
do {
j++;
} while (((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) && (j < 30000));
odm_write_4byte(dm, 0x1700, 0xc00f0000 | reg_addr);
}
}
void _iqk_rf_set_check_8822b(struct dm_struct *dm, u8 path, u16 add, u32 data)
{
u32 i;
@@ -103,6 +156,19 @@ void _iqk_rf0xb0_workaround_8822b(struct dm_struct *dm)
odm_set_rf_reg(dm, (enum rf_path)0x0, RF_0xb8, MASK20BITS, 0x80a00);
}
void _iqk_0xc94_workaround_8822b(struct dm_struct *dm)
{
if (odm_get_bb_reg(dm, R_0xc94, BIT(0)) == 0x1) {
odm_set_bb_reg(dm, R_0xc94, BIT(0), 0x0);
odm_set_bb_reg(dm, R_0xc94, BIT(0), 0x1);
}
if (odm_get_bb_reg(dm, R_0xe94, BIT(0)) == 0x1) {
odm_set_bb_reg(dm, R_0xe94, BIT(0), 0x0);
odm_set_bb_reg(dm, R_0xe94, BIT(0), 0x1);
}
}
void _iqk_fill_iqk_report_8822b(void *dm_void, u8 ch)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
@@ -280,12 +346,6 @@ void _iqk_afe_setting_8822b(struct dm_struct *dm, boolean do_iqk)
odm_write_4byte(dm, 0xc60, 0x70038040);
odm_write_4byte(dm, 0xe60, 0x50000000);
odm_write_4byte(dm, 0xe60, 0x70038040);
odm_write_4byte(dm, 0xc58, 0xd8020402);
odm_write_4byte(dm, 0xc5c, 0xde000120);
odm_write_4byte(dm, 0xc6c, 0x0000122a);
odm_write_4byte(dm, 0xe58, 0xd8020402);
odm_write_4byte(dm, 0xe5c, 0xde000120);
odm_write_4byte(dm, 0xe6c, 0x0000122a);
#if 0
/* RF_DBG(dm, DBG_RF_IQK, "[IQK]AFE setting for Normal mode!!!!\n"); */
#endif
@@ -801,10 +861,12 @@ _iqk_rxk_gsearch_fail_8822b(struct dm_struct *dm, u8 path, u8 step)
IQK_CMD = 0xf8000208 | (1 << (path + 4));
RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d GS%d_Trigger = 0x%x\n", path,
step, IQK_CMD);
_iqk_ltec_write_8822b(dm, 0x38, 0xffff,0x7700);
odm_write_4byte(dm, 0x1b00, IQK_CMD);
odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
ODM_delay_ms(GS_delay_8822B);
fail = _iqk_check_cal_8822b(dm, path, 0x1);
_iqk_ltec_write_8822b(dm, 0x38, MASKDWORD, iqk->tmp_gntwl);
} else if (step == RXIQK2) {
for (idx = 0; idx < 4; idx++) {
if (iqk->tmp1bcc == IQMUX[idx])
@@ -816,10 +878,13 @@ _iqk_rxk_gsearch_fail_8822b(struct dm_struct *dm, u8 path, u8 step)
IQK_CMD = 0xf8000308 | (1 << (path + 4));
RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d GS%d_Trigger = 0x%x\n", path,
step, IQK_CMD);
_iqk_ltec_write_8822b(dm, 0x38, 0xffff,0x7700);
odm_write_4byte(dm, 0x1b00, IQK_CMD);
odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
ODM_delay_ms(GS_delay_8822B);
fail = _iqk_check_cal_8822b(dm, path, 0x1);
_iqk_ltec_write_8822b(dm, 0x38, MASKDWORD, iqk->tmp_gntwl);
rf_reg0 = odm_get_rf_reg(dm, (enum rf_path)path,
RF_0x0, MASK20BITS);
@@ -879,12 +944,16 @@ _lok_one_shot_8822b(void *dm_void, u8 path)
RF_DBG(dm, DBG_RF_IQK, "[IQK]==========S%d LOK ==========\n", path);
IQK_CMD = 0xf8000008 | (1 << (4 + path));
RF_DBG(dm, DBG_RF_IQK, "[IQK]LOK_Trigger = 0x%x\n", IQK_CMD);
_iqk_ltec_write_8822b(dm, 0x38, 0xffff,0x7700);
odm_write_4byte(dm, 0x1b00, IQK_CMD);
odm_write_4byte(dm, 0x1b00, IQK_CMD + 1);
/*LOK: CMD ID = 0 {0xf8000018, 0xf8000028}*/
/*LOK: CMD ID = 0 {0xf8000019, 0xf8000029}*/
ODM_delay_ms(LOK_delay_8822B);
LOK_notready = _iqk_check_cal_8822b(dm, path, 0x0);
_iqk_ltec_write_8822b(dm, 0x38, MASKDWORD, iqk->tmp_gntwl);
if (!LOK_notready)
_iqk_backup_iqk_8822b(dm, 0x1, path);
if (DBG_RF_IQK) {
@@ -951,10 +1020,12 @@ _iqk_one_shot_8822b(void *dm_void, u8 path, u8 idx)
((iqk->lna_idx & 0x7) << 10);
odm_write_4byte(dm, 0x1b24, tmp);
}
_iqk_ltec_write_8822b(dm, 0x38, 0xffff,0x7700);
odm_write_4byte(dm, 0x1b00, IQK_CMD);
odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
ODM_delay_ms(WBIQK_delay_8822B);
fail = _iqk_check_cal_8822b(dm, path, 0x1);
_iqk_ltec_write_8822b(dm, 0x38, MASKDWORD, iqk->tmp_gntwl);
if (dm->debug_components & DBG_RF_IQK) {
odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
@@ -1722,9 +1793,12 @@ void _phy_iq_calibrate_8822b(struct dm_struct *dm, boolean reset,
u32 MAC_backup[MAC_REG_NUM_8822B], BB_backup[BB_REG_NUM_8822B];
u32 RF_backup[RF_REG_NUM_8822B][SS_8822B];
u32 backup_mac_reg[MAC_REG_NUM_8822B] = {0x520, 0x550};
u32 backup_bb_reg[BB_REG_NUM_8822B] = {
0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0xe00, 0xeb0, 0xeb4,
0xebc, 0x1990, 0x9a4, 0xa04, 0xb00, 0x838};
u32 backup_bb_reg[BB_REG_NUM_8822B] = {0x808, 0x90c, 0xc00, 0xcb0,
0xcb4, 0xcbc, 0xe00, 0xeb0,
0xeb4, 0xebc, 0x1990, 0x9a4,
0xa04, 0xb00, 0x838, 0xc58,
0xc5c, 0xc6c, 0xe58, 0xe5c,
0xe6c};
u32 backup_rf_reg[RF_REG_NUM_8822B] = {0xdf, 0x8f, 0x65, 0x0, 0x1};
boolean is_mp = false;
@@ -1751,6 +1825,7 @@ void _phy_iq_calibrate_8822b(struct dm_struct *dm, boolean reset,
dm->rf_calibrate_info.iqk_step = 1;
iqk->rxiqk_step = 1;
iqk->tmp_gntwl = _iqk_ltec_read_8822b(dm, 0x38);
_iqk_backup_iqk_8822b(dm, 0x0, 0x0);
_iqk_backup_mac_bb_8822b(dm, MAC_backup, BB_backup,
backup_mac_reg, backup_bb_reg);
@@ -1831,6 +1906,7 @@ void phy_iq_calibrate_8822b(void *dm_void, boolean clear, boolean segment_iqk)
_iq_calibrate_8822b_init(dm);
_phy_iq_calibrate_8822b(dm, clear, segment_iqk);
}
_iqk_0xc94_workaround_8822b(dm);
_iqk_fail_count_8822b(dm);
if (*dm->mp_mode)
halrf_iqk_hwtx_check(dm, false);
@@ -1845,9 +1921,12 @@ void _phy_imr_measure_8822b(struct dm_struct *dm)
u32 MAC_backup[MAC_REG_NUM_8822B], BB_backup[BB_REG_NUM_8822B];
u32 RF_backup[RF_REG_NUM_8822B][SS_8822B];
u32 backup_mac_reg[MAC_REG_NUM_8822B] = {0x520, 0x550};
u32 backup_bb_reg[BB_REG_NUM_8822B] = {
0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0xe00, 0xeb0, 0xeb4,
0xebc, 0x1990, 0x9a4, 0xa04, 0xb00};
u32 backup_bb_reg[BB_REG_NUM_8822B] = {0x808, 0x90c, 0xc00, 0xcb0,
0xcb4, 0xcbc, 0xe00, 0xeb0,
0xeb4, 0xebc, 0x1990, 0x9a4,
0xa04, 0xb00, 0x838, 0xc58,
0xc5c, 0xc6c, 0xe58, 0xe5c,
0xe6c};
u32 backup_rf_reg[RF_REG_NUM_8822B] = {0xdf, 0x8f, 0x65, 0x0, 0x1};
_iqk_backup_iqk_8822b(dm, 0x0, 0x0);
@@ -1878,4 +1957,206 @@ void do_imr_test_8822b(void *dm_void)
RF_DBG(dm, DBG_RF_IQK,
"[IQK] **********End IMR Test *******************\n");
}
void phy_get_iqk_cfir_8822b(void *dm_void, u8 idx, u8 path, boolean debug)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_iqk_info *iqk_info = &dm->IQK_info;
u8 i, ch;
u32 tmp;
u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
if (debug)
ch = 2;
else
ch = 0;
odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0xf8000008 | path << 1);
if (idx == 0)
odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x3);
else
odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x1);
odm_set_bb_reg(dm, R_0x1bd4, bit_mask_20_16, 0x10);
for (i = 0; i < 8; i++) {
odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001 + (i * 4));
tmp = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
iqk_info->iqk_cfir_real[ch][path][idx][i] =
(tmp & 0x0fff0000) >> 16;
iqk_info->iqk_cfir_imag[ch][path][idx][i] = tmp & 0xfff;
}
odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x0);
}
void phy_iqk_dbg_cfir_backup_8822b(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_iqk_info *iqk_info = &dm->IQK_info;
u8 path, idx, i;
RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "backup TX/RX CFIR");
for (path = 0; path < 2; path++)
for (idx = 0; idx < 2; idx++)
phydm_get_iqk_cfir(dm, idx, path, true);
for (path = 0; path < 2; path++) {
for (idx = 0; idx < 2; idx++) {
for (i = 0; i < 8; i++) {
RF_DBG(dm, DBG_RF_IQK,
"[IQK]%-7s %-3s CFIR_real: %-2d: 0x%x\n",
(path == 0) ? "PATH A" : "PATH B",
(idx == 0) ? "TX" : "RX", i,
iqk_info->iqk_cfir_real[2][path][idx][i])
;
}
for (i = 0; i < 8; i++) {
RF_DBG(dm, DBG_RF_IQK,
"[IQK]%-7s %-3s CFIR_img:%-2d: 0x%x\n",
(path == 0) ? "PATH A" : "PATH B",
(idx == 0) ? "TX" : "RX", i,
iqk_info->iqk_cfir_imag[2][path][idx][i])
;
}
}
}
}
void phy_iqk_dbg_cfir_backup_update_8822b(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_iqk_info *iqk = &dm->IQK_info;
u8 i, path, idx;
u32 bmask13_12 = BIT(13) | BIT(12);
u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
u32 data;
if (iqk->iqk_cfir_real[2][0][0][0] == 0) {
RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "CFIR is invalid");
return;
}
for (path = 0; path < 2; path++) {
for (idx = 0; idx < 2; idx++) {
odm_set_bb_reg(dm, R_0x1b00, MASKDWORD,
0xf8000008 | path << 1);
odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7);
odm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x20000000);
odm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x20000000);
odm_set_bb_reg(dm, R_0x1bcc, MASKDWORD, 0x00000000);
if (idx == 0)
odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x3);
else
odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x1);
odm_set_bb_reg(dm, R_0x1bd4, bmask20_16, 0x10);
for (i = 0; i < 8; i++) {
data = ((0xc0000000 >> idx) + 0x3) + (i * 4) +
(iqk->iqk_cfir_real[2][path][idx][i]
<< 9);
odm_write_4byte(dm, 0x1bd8, data);
data = ((0xc0000000 >> idx) + 0x1) + (i * 4) +
(iqk->iqk_cfir_imag[2][path][idx][i]
<< 9);
odm_write_4byte(dm, 0x1bd8, data);
#if 0
/*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_real[2][path][idx][i]);*/
/*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_imag[2][path][idx][i]);*/
#endif
}
}
odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x0);
}
RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "update new CFIR");
}
void phy_iqk_dbg_cfir_reload_8822b(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_iqk_info *iqk = &dm->IQK_info;
u8 i, path, idx;
u32 bmask13_12 = BIT(13) | BIT(12);
u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
u32 data;
if (iqk->iqk_cfir_real[0][0][0][0] == 0) {
RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "CFIR is invalid");
return;
}
for (path = 0; path < 2; path++) {
for (idx = 0; idx < 2; idx++) {
odm_set_bb_reg(dm, R_0x1b00, MASKDWORD,
0xf8000008 | path << 1);
odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7);
odm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x20000000);
odm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x20000000);
odm_set_bb_reg(dm, R_0x1bcc, MASKDWORD, 0x00000000);
if (idx == 0)
odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x3);
else
odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x1);
odm_set_bb_reg(dm, R_0x1bd4, bmask20_16, 0x10);
for (i = 0; i < 8; i++) {
#if 0
/*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_real[0][path][idx][i]);*/
/*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_imag[0][path][idx][i]);*/
#endif
data = ((0xc0000000 >> idx) + 0x3) + (i * 4) +
(iqk->iqk_cfir_real[0][path][idx][i]
<< 9);
odm_write_4byte(dm, 0x1bd8, data);
data = ((0xc0000000 >> idx) + 0x1) + (i * 4) +
(iqk->iqk_cfir_imag[0][path][idx][i]
<< 9);
odm_write_4byte(dm, 0x1bd8, data);
}
}
odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x0);
}
RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "write CFIR with default value");
}
void phy_iqk_dbg_cfir_write_8822b(void *dm_void, u8 type, u32 path, u32 idx,
u32 i, u32 data)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_iqk_info *iqk_info = &dm->IQK_info;
if (type == 0)
iqk_info->iqk_cfir_real[2][path][idx][i] = (u16)data;
else
iqk_info->iqk_cfir_imag[2][path][idx][i] = (u16)data;
}
void phy_iqk_dbg_cfir_backup_show_8822b(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_iqk_info *iqk_info = &dm->IQK_info;
u8 path, idx, i;
RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "backup TX/RX CFIR");
for (path = 0; path < 2; path++) {
for (idx = 0; idx < 2; idx++) {
for (i = 0; i < 8; i++) {
RF_DBG(dm, DBG_RF_IQK,
"[IQK]%-10s %-3s CFIR_real:%-2d: 0x%x\n",
(path == 0) ? "PATH A" : "PATH B",
(idx == 0) ? "TX" : "RX", i,
iqk_info->iqk_cfir_real[2][path][idx][i])
;
}
for (i = 0; i < 8; i++) {
RF_DBG(dm, DBG_RF_IQK,
"[IQK]%-10s %-3s CFIR_img:%-2d: 0x%x\n",
(path == 0) ? "PATH A" : "PATH B",
(idx == 0) ? "TX" : "RX", i,
iqk_info->iqk_cfir_imag[2][path][idx][i])
;
}
}
}
}
#endif

17
hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.h
View File

@@ -29,7 +29,7 @@
#if (RTL8822B_SUPPORT == 1)
/*@--------------------------Define Parameters-------------------------------*/
#define MAC_REG_NUM_8822B 2
#define BB_REG_NUM_8822B 15
#define BB_REG_NUM_8822B 21
#define RF_REG_NUM_8822B 5
#define LOK_delay_8822B 2
#define GS_delay_8822B 2
@@ -51,6 +51,21 @@ void phy_iq_calibrate_8822b(void *dm_void, boolean clear, boolean segment_iqk);
void do_imr_test_8822b(void *dm_void);
void phy_get_iqk_cfir_8822b(void *dm_void, u8 idx, u8 path, boolean debug);
void phy_iqk_dbg_cfir_backup_8822b(void *dm_void);
void phy_iqk_dbg_cfir_backup_update_8822b(void *dm_void);
void phy_iqk_dbg_cfir_reload_8822b(void *dm_void);
void phy_iqk_dbg_cfir_write_8822b(void *dm_void, u8 type, u32 path, u32 idx, u32 i, u32 data);
void phy_iqk_dbg_cfir_backup_show_8822b(void *dm_void);
#else /* (RTL8822B_SUPPORT == 0)*/
#define phy_iq_calibrate_8822b(_pdm_void, clear, segment_iqk)

26
hal/phydm/halrf/rtl8822b/version_rtl8822b_rf.h Normal file
View File

@@ -0,0 +1,26 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*RTL8822B RF Parameters*/
#define RF_RELEASE_VERSION_8822B 1