RinCat/RTL88x2BU-Linux-Driver
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Update to 5.8.7.1

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Rin Cat
2020-08-02 05:12:24 -04:00
parent 314b662331
commit e3b09b28f7
449 changed files with 106089 additions and 83748 deletions
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58
hal/phydm/ap_makefile.mk
View File

@@ -28,6 +28,8 @@ _PHYDM_FILES :=\
phydm/phydm_lna_sat.o\
phydm/phydm_pmac_tx_setting.o\
phydm/phydm_mp.o\
phydm/phydm_cck_rx_pathdiv.o\
phydm/phydm_direct_bf.o\
phydm/txbf/phydm_hal_txbf_api.o\
EdcaTurboCheck.o\
phydm/halrf/halrf.o\
@@ -35,7 +37,8 @@ _PHYDM_FILES :=\
phydm/halrf/halphyrf_ap.o\
phydm/halrf/halrf_powertracking_ap.o\
phydm/halrf/halrf_powertracking.o\
phydm/halrf/halrf_kfree.o
phydm/halrf/halrf_kfree.o\
phydm/halrf/halrf_psd.o
ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
@@ -70,11 +73,11 @@ endif
ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_8814a_ap.o
rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_iqk_8814a.o
rtl8192cd-objs += phydm/halrf/rtl8814a/halhwimg8814a_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
rtl8192cd-objs += \
phydm/rtl8814a/halhwimg8814a_bb.o\
phydm/rtl8814a/halhwimg8814a_mac.o\
phydm/rtl8814a/halhwimg8814a_rf.o\
phydm/rtl8814a/phydm_regconfig8814a.o\
phydm/rtl8814a/phydm_rtl8814a.o
endif
@@ -83,11 +86,11 @@ endif
ifeq ($(CONFIG_WLAN_HAL_8822BE),y)
_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_8822b.o
_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_iqk_8822b.o
_PHYDM_FILES += phydm/halrf/rtl8822b/halhwimg8822b_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8822b/halhwimg8822b_bb.o\
phydm/rtl8822b/halhwimg8822b_mac.o\
phydm/rtl8822b/halhwimg8822b_rf.o\
phydm/rtl8822b/phydm_regconfig8822b.o\
phydm/rtl8822b/phydm_hal_api8822b.o\
phydm/rtl8822b/phydm_rtl8822b.o
@@ -98,25 +101,39 @@ ifeq ($(CONFIG_WLAN_HAL_8822CE),y)
_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_8822c.o
_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_iqk_8822c.o
_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_dpk_8822c.o
_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_rfk_init_8822c.o
_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_rfk_init_8822c.o
_PHYDM_FILES += phydm/halrf/rtl8822c/halhwimg8822c_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8822c/halhwimg8822c_bb.o\
phydm/rtl8822c/halhwimg8822c_mac.o\
phydm/rtl8822c/halhwimg8822c_rf.o\
phydm/rtl8822c/phydm_regconfig8822c.o\
phydm/rtl8822c/phydm_hal_api8822c.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8812FE),y)
_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_8812f.o
_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_iqk_8812f.o
_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_dpk_8812f.o
_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_tssi_8812f.o
_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_rfk_init_8812f.o
_PHYDM_FILES += phydm/halrf/rtl8812f/halhwimg8812f_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8812f/halhwimg8812f_bb.o\
phydm/rtl8812f/phydm_regconfig8812f.o\
phydm/rtl8812f/phydm_hal_api8812f.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8821CE),y)
_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_8821c.o
_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_iqk_8821c.o
_PHYDM_FILES += phydm/halrf/rtl8821c/halhwimg8821c_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8821c/halhwimg8821c_bb.o\
phydm/rtl8821c/halhwimg8821c_mac.o\
phydm/rtl8821c/halhwimg8821c_rf.o\
phydm/rtl8821c/phydm_regconfig8821c.o\
phydm/rtl8821c/phydm_hal_api8821c.o
endif
@@ -126,12 +143,12 @@ ifeq ($(CONFIG_WLAN_HAL_8197F),y)
_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_8197f.o
_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_iqk_8197f.o
_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_dpk_8197f.o
_PHYDM_FILES += phydm/halrf/rtl8197f/halhwimg8197f_rf.o
_PHYDM_FILES += efuse_97f/efuse.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8197f/halhwimg8197f_bb.o\
phydm/rtl8197f/halhwimg8197f_mac.o\
phydm/rtl8197f/halhwimg8197f_rf.o\
phydm/rtl8197f/phydm_hal_api8197f.o\
phydm/rtl8197f/phydm_regconfig8197f.o\
phydm/rtl8197f/phydm_rtl8197f.o
@@ -142,11 +159,11 @@ endif
ifeq ($(CONFIG_WLAN_HAL_8192FE),y)
_PHYDM_FILES += phydm/halrf/rtl8192f/halrf_8192f.o
_PHYDM_FILES += phydm/halrf/rtl8192f/halrf_dpk_8192f.o
_PHYDM_FILES += phydm/halrf/rtl8192f/halhwimg8192f_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8192f/halhwimg8192f_bb.o\
phydm/rtl8192f/halhwimg8192f_mac.o\
phydm/rtl8192f/halhwimg8192f_rf.o\
phydm/rtl8192f/phydm_hal_api8192f.o\
phydm/rtl8192f/phydm_regconfig8192f.o\
phydm/rtl8192f/phydm_rtl8192f.o
@@ -158,12 +175,12 @@ ifeq ($(CONFIG_WLAN_HAL_8198F),y)
_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_iqk_8198f.o
_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_dpk_8198f.o
_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_rfk_init_8198f.o
_PHYDM_FILES += phydm/halrf/rtl8198f/halhwimg8198f_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8198f/phydm_hal_api8198f.o\
phydm/rtl8198f/halhwimg8198f_bb.o\
phydm/rtl8198f/halhwimg8198f_mac.o\
phydm/rtl8198f/halhwimg8198f_rf.o\
phydm/rtl8198f/phydm_regconfig8198f.o \
phydm/halrf/rtl8198f/halrf_8198f.o
endif
@@ -172,17 +189,32 @@ endif
ifeq ($(CONFIG_WLAN_HAL_8814BE),y)
_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_8814b.o
_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_iqk_8814b.o
_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_dpk_8814b.o
_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_rfk_init_8814b.o
_PHYDM_FILES += phydm/halrf/rtl8814b/halhwimg8814b_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8814b/phydm_hal_api8814b.o\
phydm/rtl8814b/halhwimg8814b_bb.o\
phydm/rtl8814b/halhwimg8814b_mac.o\
phydm/rtl8814b/halhwimg8814b_rf.o\
phydm/rtl8814b/phydm_regconfig8814b.o \
phydm/halrf/rtl8814b/halrf_8814b.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8197G),y)
_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_8197g.o
_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_iqk_8197g.o
_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_dpk_8197g.o
_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_tssi_8197g.o
_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_rfk_init_8197g.o
_PHYDM_FILES += phydm/halrf/rtl8197g/halhwimg8197g_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8197g/phydm_hal_api8197g.o\
phydm/rtl8197g/halhwimg8197g_bb.o\
phydm/rtl8197g/halhwimg8197g_mac.o\
phydm/rtl8197g/phydm_regconfig8197g.o \
phydm/halrf/rtl8197g/halrf_8197g.o
endif
endif

303
hal/phydm/halrf/halphyrf_ap.c
View File

@@ -37,6 +37,28 @@
_offset = _size-1;\
} while (0)
void odm_clear_txpowertracking_state(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
struct rtl8192cd_priv *priv = dm->priv;
u8 i;
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "===>%s\n", __func__);
for (i = 0; i < MAX_RF_PATH; i++) {
cali_info->absolute_ofdm_swing_idx[i] = 0;
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "cali_info->absolute_ofdm_swing_idx[%d]=%d\n",
i, cali_info->absolute_ofdm_swing_idx[i]);
}
dm->rf_calibrate_info.thermal_value = 0;
dm->rf_calibrate_info.thermal_value_lck = 0;
dm->rf_calibrate_info.thermal_value_iqk = 0;
}
void configure_txpower_track(
void *dm_void,
@@ -84,6 +106,21 @@ void configure_txpower_track(
configure_txpower_track_8198f(config);
#endif
#if RTL8814B_SUPPORT
if (dm->support_ic_type == ODM_RTL8814B)
configure_txpower_track_8814b(config);
#endif
#if RTL8812F_SUPPORT
if (dm->support_ic_type == ODM_RTL8812F)
configure_txpower_track_8812f(config);
#endif
#if RTL8197G_SUPPORT
if (dm->support_ic_type == ODM_RTL8197G)
configure_txpower_track_8197g(config);
#endif
}
#if (RTL8192E_SUPPORT == 1)
@@ -318,7 +355,263 @@ odm_txpowertracking_callback_thermal_meter_92e(
}
#endif
#if (RTL8814B_SUPPORT == 1 || RTL8812F_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8197G_SUPPORT == 1)
void
odm_txpowertracking_callback_thermal_meter_jaguar_series4(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
struct dm_iqk_info *iqk_info = &dm->IQK_info;
struct _hal_rf_ *rf = &dm->rf_table;
struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
struct rtl8192cd_priv *priv = dm->priv;
struct txpwrtrack_cfg c;
if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
return;
u8 thermal_value[MAX_RF_PATH] = {0}, delta[MAX_RF_PATH] = {0};
u8 delta_swing_table_idx_tup[DELTA_SWINGIDX_SIZE] = {0};
u8 delta_swing_table_idx_tdown[DELTA_SWINGIDX_SIZE] = {0};
u8 delta_LCK = 0, delta_IQK = 0, i = 0, j = 0, p;
u8 thermal_value_avg_count[MAX_RF_PATH] = {0};
u32 thermal_value_avg[MAX_RF_PATH] = {0};
s8 thermal_value_temp[MAX_RF_PATH] = {0};
u8 *pwrtrk_tab_up_a = NULL;
u8 *pwrtrk_tab_down_a = NULL;
u8 *pwrtrk_tab_up_b = NULL;
u8 *pwrtrk_tab_down_b = NULL;
u8 *pwrtrk_tab_up_c = NULL;
u8 *pwrtrk_tab_down_c = NULL;
u8 *pwrtrk_tab_up_d = NULL;
u8 *pwrtrk_tab_down_d = NULL;
u8 tracking_method = MIX_MODE;
configure_txpower_track(dm, &c);
(*c.get_delta_swing_table)(dm,
(u8 **)&pwrtrk_tab_up_a, (u8 **)&pwrtrk_tab_down_a,
(u8 **)&pwrtrk_tab_up_b, (u8 **)&pwrtrk_tab_down_b);
if (GET_CHIP_VER(priv) == VERSION_8814B) {
(*c.get_delta_swing_table8814only)(dm,
(u8 **)&pwrtrk_tab_up_c, (u8 **)&pwrtrk_tab_down_c,
(u8 **)&pwrtrk_tab_up_d, (u8 **)&pwrtrk_tab_down_d);
}
cali_info->txpowertracking_callback_cnt++;
cali_info->is_txpowertracking_init = true;
/* Initialize */
if (!dm->rf_calibrate_info.thermal_value)
dm->rf_calibrate_info.thermal_value =
priv->pmib->dot11RFEntry.thermal[RF_PATH_A];
if (!dm->rf_calibrate_info.thermal_value_lck)
dm->rf_calibrate_info.thermal_value_lck =
priv->pmib->dot11RFEntry.thermal[RF_PATH_A];
if (!dm->rf_calibrate_info.thermal_value_iqk)
dm->rf_calibrate_info.thermal_value_iqk =
priv->pmib->dot11RFEntry.thermal[RF_PATH_A];
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base_path[RF_PATH_A], cali_info->default_ofdm_index);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"cali_info->txpowertrack_control=%d\n", cali_info->txpowertrack_control);
for (i = 0; i < c.rf_path_count; i++) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"PGthermal[%d]=0x%x(%d)\n", i,
priv->pmib->dot11RFEntry.thermal[i],
priv->pmib->dot11RFEntry.thermal[i]);
if (priv->pmib->dot11RFEntry.thermal[i] == 0xff ||
priv->pmib->dot11RFEntry.thermal[i] == 0x0)
return;
}
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)) {
for (i = 0; i < c.rf_path_count; i++)
thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0x7e); /* 0x42: RF Reg[6:1] Thermal Trim*/
} else {
for (i = 0; i < c.rf_path_count; i++) {
thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_thermal_offset(dm);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + power_time_thermal(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_thermal_offset(dm));
if (thermal_value_temp[i] > 63)
thermal_value[i] = 63;
else if (thermal_value_temp[i] < 0)
thermal_value[i] = 0;
else
thermal_value[i] = thermal_value_temp[i];
}
}
for (j = 0; j < c.rf_path_count; j++) {
cali_info->thermal_value_avg_path[j][cali_info->thermal_value_avg_index_path[j]] = thermal_value[j];
cali_info->thermal_value_avg_index_path[j]++;
if (cali_info->thermal_value_avg_index_path[j] == c.average_thermal_num) /*Average times = c.average_thermal_num*/
cali_info->thermal_value_avg_index_path[j] = 0;
for (i = 0; i < c.average_thermal_num; i++) {
if (cali_info->thermal_value_avg_path[j][i]) {
thermal_value_avg[j] += cali_info->thermal_value_avg_path[j][i];
thermal_value_avg_count[j]++;
}
}
if (thermal_value_avg_count[j]) { /* Calculate Average thermal_value after average enough times */
thermal_value[j] = (u8)(thermal_value_avg[j] / thermal_value_avg_count[j]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"PGthermal[%d] = 0x%x(%d), AVG Thermal Meter = 0x%x(%d)\n", j,
priv->pmib->dot11RFEntry.thermal[j],
priv->pmib->dot11RFEntry.thermal[j],
thermal_value[j],
thermal_value[j]);
}
/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
/* "delta" here is used to determine whether thermal value changes or not. */
delta[j] = RTL_ABS(thermal_value[j], priv->pmib->dot11RFEntry.thermal[j]);
delta_LCK = RTL_ABS(thermal_value[RF_PATH_A], dm->rf_calibrate_info.thermal_value_lck);
delta_IQK = RTL_ABS(thermal_value[RF_PATH_A], dm->rf_calibrate_info.thermal_value_iqk);
}
/*4 6. If necessary, do LCK.*/
for (i = 0; i < c.rf_path_count; i++)
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta[%d], delta_LCK, delta_IQK) = (%d, %d, %d)\n", i, delta[i], delta_LCK, delta_IQK);
/* Wait sacn to do LCK by RF Jenyu*/
if( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
/* Delta temperature is equal to or larger than 20 centigrade.*/
if (delta_LCK >= c.threshold_iqk) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
cali_info->thermal_value_lck = thermal_value[RF_PATH_A];
/*Use RTLCK, so close power tracking driver LCK*/
if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
if (c.phy_lc_calibrate)
(*c.phy_lc_calibrate)(dm);
} else
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do not do LCK\n");
}
}
/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
#ifdef _TRACKING_TABLE_FILE
for (i = 0; i < c.rf_path_count; i++) {
if (i == RF_PATH_B) {
odm_move_memory(dm, delta_swing_table_idx_tup, pwrtrk_tab_up_b, DELTA_SWINGIDX_SIZE);
odm_move_memory(dm, delta_swing_table_idx_tdown, pwrtrk_tab_down_b, DELTA_SWINGIDX_SIZE);
} else if (i == RF_PATH_C) {
odm_move_memory(dm, delta_swing_table_idx_tup, pwrtrk_tab_up_c, DELTA_SWINGIDX_SIZE);
odm_move_memory(dm, delta_swing_table_idx_tdown, pwrtrk_tab_down_c, DELTA_SWINGIDX_SIZE);
} else if (i == RF_PATH_D) {
odm_move_memory(dm, delta_swing_table_idx_tup, pwrtrk_tab_up_d, DELTA_SWINGIDX_SIZE);
odm_move_memory(dm, delta_swing_table_idx_tdown, pwrtrk_tab_down_d, DELTA_SWINGIDX_SIZE);
} else {
odm_move_memory(dm, delta_swing_table_idx_tup, pwrtrk_tab_up_a, DELTA_SWINGIDX_SIZE);
odm_move_memory(dm, delta_swing_table_idx_tdown, pwrtrk_tab_down_a, DELTA_SWINGIDX_SIZE);
}
cali_info->delta_power_index_last_path[i] = cali_info->delta_power_index_path[i]; /*recording poer index offset*/
delta[i] = thermal_value[i] > priv->pmib->dot11RFEntry.thermal[i] ? (thermal_value[i] - priv->pmib->dot11RFEntry.thermal[i]) : (priv->pmib->dot11RFEntry.thermal[i] - thermal_value[i]);
if (delta[i] >= TXPWR_TRACK_TABLE_SIZE)
delta[i] = TXPWR_TRACK_TABLE_SIZE - 1;
if (thermal_value[i] > priv->pmib->dot11RFEntry.thermal[i]) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tup[%d]=%d Path=%d\n", delta[i], delta_swing_table_idx_tup[delta[i]], i);
cali_info->delta_power_index_path[i] = delta_swing_table_idx_tup[delta[i]];
cali_info->absolute_ofdm_swing_idx[i] = delta_swing_table_idx_tup[delta[i]]; /*Record delta swing for mix mode power tracking*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\n", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);
} else {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tdown[%d]=%d Path=%d\n", delta[i], delta_swing_table_idx_tdown[delta[i]], i);
cali_info->delta_power_index_path[i] = -1 * delta_swing_table_idx_tdown[delta[i]];
cali_info->absolute_ofdm_swing_idx[i] = -1 * delta_swing_table_idx_tdown[delta[i]]; /*Record delta swing for mix mode power tracking*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\n", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);
}
}
#endif
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
if (cali_info->delta_power_index_path[p] == cali_info->delta_power_index_last_path[p]) /*If Thermal value changes but lookup table value still the same*/
cali_info->power_index_offset_path[p] = 0;
else
cali_info->power_index_offset_path[p] = cali_info->delta_power_index_path[p] - cali_info->delta_power_index_last_path[p]; /*Power index diff between 2 times Power Tracking*/
}
#if 0
if (dm->support_ic_type == ODM_RTL8814B) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
} else {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
}
#else
if (*dm->mp_mode == 1) {
if (cali_info->txpowertrack_control == 1) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
tracking_method = MIX_MODE;
} else if (cali_info->txpowertrack_control == 3) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI_MODE**********\n");
tracking_method = TSSI_MODE;
}
} else {
if (dm->priv->pmib->dot11RFEntry.tssi_enable == 0) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
tracking_method = MIX_MODE;
} else if (dm->priv->pmib->dot11RFEntry.tssi_enable == 1) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI_MODE**********\n");
tracking_method = TSSI_MODE;
}
}
if (dm->support_ic_type == ODM_RTL8822C || dm->support_ic_type == ODM_RTL8812F ||
dm->support_ic_type == ODM_RTL8814B || dm->support_ic_type == ODM_RTL8197G)
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, tracking_method, p, 0);
#endif
/* Wait sacn to do IQK by RF Jenyu*/
if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
if (delta_IQK >= c.threshold_iqk) {
cali_info->thermal_value_iqk = thermal_value[RF_PATH_A];
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
/*if (!cali_info->is_iqk_in_progress)*/
/* (*c.do_iqk)(dm, delta_IQK, thermal_value[RF_PATH_A], 8);*/
/*RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do IQK\n");*/
/*if (!cali_info->is_iqk_in_progress)*/
/* (*c.do_tssi_dck)(dm, true);*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do TSSI DCK\n");
}
}
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===%s\n", __func__);
cali_info->tx_powercount = 0;
}
#endif
#if (RTL8197F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\
RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
@@ -1034,6 +1327,13 @@ odm_txpowertracking_callback_thermal_meter(
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
struct dm_iqk_info *iqk_info = &dm->IQK_info;
#if (RTL8814B_SUPPORT == 1 || RTL8812F_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8197G_SUPPORT == 1)
if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8822C | ODM_RTL8197G)) {
odm_txpowertracking_callback_thermal_meter_jaguar_series4(dm);
return;
}
#endif
#if (RTL8197F_SUPPORT == 1 ||RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8197F || dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8822B
|| dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8198F) {
@@ -1351,8 +1651,9 @@ void phydm_rf_init(void *dm_void)
void phydm_rf_watchdog(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
odm_txpowertracking_check(dm);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
odm_iq_calibrate(dm);
#endif

34
hal/phydm/halrf/halphyrf_ap.h
View File

@@ -43,20 +43,37 @@
#include "halrf/rtl8198f/halrf_dpk_8198f.h"
#endif
#if (RTL8812F_SUPPORT == 1)
#include "halrf/rtl8812f/halrf_iqk_8812f.h"
#include "halrf/rtl8812f/halrf_dpk_8812f.h"
#include "halrf/rtl8812f/halrf_tssi_8812f.h"
#endif
#if (RTL8814B_SUPPORT == 1)
#include "halrf/rtl8814b/halrf_iqk_8814b.h"
#include "halrf/rtl8814b/halrf_dpk_8814b.h"
#endif
#if (RTL8197G_SUPPORT == 1)
#include "halrf/rtl8197g/halrf_iqk_8197g.h"
#include "halrf/rtl8197g/halrf_dpk_8197g.h"
#include "halrf/rtl8197g/halrf_tssi_8197g.h"
#endif
enum pwrtrack_method {
BBSWING,
TXAGC,
MIX_MODE,
TSSI_MODE
TSSI_MODE,
MIX_2G_TSSI_5G_MODE,
MIX_5G_TSSI_2G_MODE,
CLEAN_MODE
};
typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
typedef void(*func_iqk)(void *, u8, u8, u8);
typedef void (*func_lck)(void *);
typedef void (*func_tssi_dck)(void *, u8);
/* refine by YuChen for 8814A */
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
@@ -74,12 +91,18 @@ struct txpwrtrack_cfg {
func_set_pwr odm_tx_pwr_track_set_pwr;
func_iqk do_iqk;
func_lck phy_lc_calibrate;
func_tssi_dck do_tssi_dck;
func_swing get_delta_swing_table;
func_swing8814only get_delta_swing_table8814only;
func_all_swing get_delta_all_swing_table;
func_all_swing_ex get_delta_all_swing_table_ex;
};
void
odm_clear_txpowertracking_state(
void *dm_void
);
void
configure_txpower_track(
void *dm_void,
@@ -111,12 +134,19 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series(
void *dm_void
);
#elif (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
#elif (RTL8197F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\
RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
void
odm_txpowertracking_callback_thermal_meter_jaguar_series3(
void *dm_void
);
#elif (RTL8814B_SUPPORT == 1 || RTL8812F_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8197G_SUPPORT == 1)
void
odm_txpowertracking_callback_thermal_meter_jaguar_series4(
void *dm_void
);
#endif
#define IS_CCK_RATE(_rate) (ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M)

242
hal/phydm/halrf/halphyrf_ce.c
View File

@@ -104,6 +104,18 @@ void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config)
if (dm->support_ic_type == ODM_RTL8192F)
configure_txpower_track_8192f(config);
#endif
#if RTL8822C_SUPPORT
if (dm->support_ic_type == ODM_RTL8822C)
configure_txpower_track_8822c(config);
#endif
#if RTL8814B_SUPPORT
if (dm->support_ic_type == ODM_RTL8814B)
configure_txpower_track_8814b(config);
#endif
}
/*@ **********************************************************************
@@ -828,6 +840,235 @@ void odm_txpowertracking_callback_thermal_meter(void *adapter)
cali_info->tx_powercount = 0;
}
#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
void
odm_txpowertracking_new_callback_thermal_meter(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
struct dm_iqk_info *iqk_info = &dm->IQK_info;
struct _hal_rf_ *rf = &dm->rf_table;
struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
u8 thermal_value[MAX_RF_PATH] = {0}, delta[MAX_RF_PATH] = {0};
u8 delta_swing_table_idx_tup[DELTA_SWINGIDX_SIZE] = {0};
u8 delta_swing_table_idx_tdown[DELTA_SWINGIDX_SIZE] = {0};
u8 delta_LCK = 0, delta_IQK = 0, i = 0, j = 0, p;
u8 thermal_value_avg_count[MAX_RF_PATH] = {0};
u32 thermal_value_avg[MAX_RF_PATH] = {0};
s8 thermal_value_temp[MAX_RF_PATH] = {0};
u8 tracking_method = MIX_MODE;
struct txpwrtrack_cfg c;
u8 *delta_swing_table_idx_tup_a = NULL;
u8 *delta_swing_table_idx_tdown_a = NULL;
u8 *delta_swing_table_idx_tup_b = NULL;
u8 *delta_swing_table_idx_tdown_b = NULL;
u8 *delta_swing_table_idx_tup_c = NULL;
u8 *delta_swing_table_idx_tdown_c = NULL;
u8 *delta_swing_table_idx_tup_d = NULL;
u8 *delta_swing_table_idx_tdown_d = NULL;
configure_txpower_track(dm, &c);
(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
if (dm->support_ic_type == ODM_RTL8814B) {
(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
}
cali_info->txpowertracking_callback_cnt++;
cali_info->is_txpowertracking_init = true;
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"cali_info->txpowertrack_control=%d, tssi->thermal[RF_PATH_A]=%d tssi->thermal[RF_PATH_B]=%d\n",
cali_info->txpowertrack_control, tssi->thermal[RF_PATH_A], tssi->thermal[RF_PATH_B]);
if (dm->support_ic_type == ODM_RTL8822C) {
for (i = 0; i < c.rf_path_count; i++)
thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0x7e); /* 0x42: RF Reg[6:1] Thermal Trim*/
} else {
for (i = 0; i < c.rf_path_count; i++) {
thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10]*/
thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_thermal_offset(dm);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + power_time_thermal(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_thermal_offset(dm));
if (thermal_value_temp[i] > 63)
thermal_value[i] = 63;
else if (thermal_value_temp[i] < 0)
thermal_value[i] = 0;
else
thermal_value[i] = thermal_value_temp[i];
}
}
if ((tssi->thermal[RF_PATH_A] == 0xff || tssi->thermal[RF_PATH_B] == 0xff) &&
cali_info->txpowertrack_control != 3) {
for (i = 0; i < c.rf_path_count; i++)
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no pg, tssi->thermal[%d] = 0x%x\n",
i, tssi->thermal[i]);
return;
}
for (j = 0; j < c.rf_path_count; j++) {
cali_info->thermal_value_avg_path[j][cali_info->thermal_value_avg_index_path[j]] = thermal_value[j];
cali_info->thermal_value_avg_index_path[j]++;
if (cali_info->thermal_value_avg_index_path[j] == c.average_thermal_num) /*Average times = c.average_thermal_num*/
cali_info->thermal_value_avg_index_path[j] = 0;
for (i = 0; i < c.average_thermal_num; i++) {
if (cali_info->thermal_value_avg_path[j][i]) {
thermal_value_avg[j] += cali_info->thermal_value_avg_path[j][i];
thermal_value_avg_count[j]++;
}
}
if (thermal_value_avg_count[j]) { /* Calculate Average thermal_value after average enough times */
thermal_value[j] = (u8)(thermal_value_avg[j] / thermal_value_avg_count[j]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"AVG Thermal Meter = 0x%X, tssi->thermal[%d] = 0x%x\n",
thermal_value[j], j, tssi->thermal[j]);
}
/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
/* "delta" here is used to determine whether thermal value changes or not. */
delta[j] = (thermal_value[j] > cali_info->thermal_value_path[j]) ? (thermal_value[j] - cali_info->thermal_value_path[j]) : (cali_info->thermal_value_path[j] - thermal_value[j]);
delta_LCK = (thermal_value[0] > cali_info->thermal_value_lck) ? (thermal_value[0] - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value[0]);
delta_IQK = (thermal_value[0] > cali_info->thermal_value_iqk) ? (thermal_value[0] - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value[0]);
}
/*4 6. If necessary, do LCK.*/
for (i = 0; i < c.rf_path_count; i++)
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta[%d], delta_LCK, delta_IQK) = (%d, %d, %d)\n", i, delta[i], delta_LCK, delta_IQK);
/* Wait sacn to do LCK by RF Jenyu*/
if( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
/* Delta temperature is equal to or larger than 20 centigrade.*/
if (delta_LCK >= c.threshold_iqk) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
cali_info->thermal_value_lck = thermal_value[RF_PATH_A];
/*Use RTLCK, so close power tracking driver LCK*/
if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
if (c.phy_lc_calibrate)
(*c.phy_lc_calibrate)(dm);
} else
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do not do LCK\n");
}
}
/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
for (i = 0; i < c.rf_path_count; i++) {
if (i == RF_PATH_B) {
odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_b, DELTA_SWINGIDX_SIZE);
odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_b, DELTA_SWINGIDX_SIZE);
} else if (i == RF_PATH_C) {
odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_c, DELTA_SWINGIDX_SIZE);
odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_c, DELTA_SWINGIDX_SIZE);
} else if (i == RF_PATH_D) {
odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_d, DELTA_SWINGIDX_SIZE);
odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_d, DELTA_SWINGIDX_SIZE);
} else {
odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_a, DELTA_SWINGIDX_SIZE);
odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_a, DELTA_SWINGIDX_SIZE);
}
cali_info->delta_power_index_last[i] = cali_info->delta_power_index[i]; /*recording poer index offset*/
delta[i] = thermal_value[i] > tssi->thermal[i] ? (thermal_value[i] - tssi->thermal[i]) : (tssi->thermal[i] - thermal_value[i]);
if (delta[i] >= TXPWR_TRACK_TABLE_SIZE)
delta[i] = TXPWR_TRACK_TABLE_SIZE - 1;
if (thermal_value[i] > tssi->thermal[i]) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tup[%d]=%d Path=%d\n", delta[i], delta_swing_table_idx_tup[delta[i]], i);
cali_info->delta_power_index[i] = delta_swing_table_idx_tup[delta[i]];
cali_info->absolute_ofdm_swing_idx[i] = delta_swing_table_idx_tup[delta[i]]; /*Record delta swing for mix mode power tracking*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\n", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);
} else {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tdown[%d]=%d Path=%d\n", delta[i], delta_swing_table_idx_tdown[delta[i]], i);
cali_info->delta_power_index[i] = -1 * delta_swing_table_idx_tdown[delta[i]];
cali_info->absolute_ofdm_swing_idx[i] = -1 * delta_swing_table_idx_tdown[delta[i]]; /*Record delta swing for mix mode power tracking*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\n", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);
}
}
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/
cali_info->power_index_offset[p] = 0;
else
cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/
}
#if 0
if (dm->support_ic_type == ODM_RTL8822C) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
} else {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
}
#endif
if (*dm->mp_mode == 1) {
if (cali_info->txpowertrack_control == 1) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
tracking_method = MIX_MODE;
} else if (cali_info->txpowertrack_control == 3) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI_MODE**********\n");
tracking_method = TSSI_MODE;
}
} else {
if (rf->power_track_type >= 0 && rf->power_track_type <= 3) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
tracking_method = MIX_MODE;
} else if (rf->power_track_type >= 4 && rf->power_track_type <= 7) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI_MODE**********\n");
tracking_method = TSSI_MODE;
}
}
if (dm->support_ic_type == ODM_RTL8822C || dm->support_ic_type == ODM_RTL8814B)
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, tracking_method, p, 0);
/* Wait sacn to do IQK by RF Jenyu*/
if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
if (delta_IQK >= c.threshold_iqk) {
cali_info->thermal_value_iqk = thermal_value[RF_PATH_A];
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
/*if (!cali_info->is_iqk_in_progress)*/
/* (*c.do_iqk)(dm, delta_IQK, thermal_value[RF_PATH_A], 8);*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do IQK\n");
/*if (!cali_info->is_iqk_in_progress)*/
/* (*c.do_tssi_dck)(dm, true);*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do TSSI DCK\n");
}
}
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===%s\n", __func__);
cali_info->tx_powercount = 0;
}
#endif
/*@3============================================================
* 3 IQ Calibration
* 3============================================================
@@ -910,6 +1151,7 @@ void phydm_rf_init(void *dm_void)
void phydm_rf_watchdog(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
odm_txpowertracking_check(dm);
#if 0

12
hal/phydm/halrf/halphyrf_ce.h
View File

@@ -47,7 +47,8 @@
#endif
#if (RTL8814B_SUPPORT == 1)
#include "halrf/rtl8814b/halrf_iqk_8814b.h"
#include "halrf/rtl8814b/halrf_iqk_8814b.h"
#include "halrf/rtl8814b/halrf_dpk_8814b.h"
#endif
#include "halrf/halrf_powertracking_ce.h"
@@ -63,12 +64,14 @@ enum pwrtrack_method {
MIX_MODE,
TSSI_MODE,
MIX_2G_TSSI_5G_MODE,
MIX_5G_TSSI_2G_MODE
MIX_5G_TSSI_2G_MODE,
CLEAN_MODE
};
typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
typedef void (*func_iqk)(void *, u8, u8, u8);
typedef void (*func_lck)(void *);
typedef void (*func_tssi_dck)(void *, u8);
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
@@ -85,6 +88,7 @@ struct txpwrtrack_cfg {
func_set_pwr odm_tx_pwr_track_set_pwr;
func_iqk do_iqk;
func_lck phy_lc_calibrate;
func_tssi_dck do_tssi_dck;
func_swing get_delta_swing_table;
func_swing8814only get_delta_swing_table8814only;
func_swing_xtal get_delta_swing_xtal_table;
@@ -103,6 +107,10 @@ void odm_txpowertracking_callback_thermal_meter(void *dm);
void odm_txpowertracking_callback_thermal_meter(void *adapter);
#endif
#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
void odm_txpowertracking_new_callback_thermal_meter(void *dm_void);
#endif
#define ODM_TARGET_CHNL_NUM_2G_5G 59
void odm_reset_iqk_result(void *dm_void);

164
hal/phydm/halrf/halphyrf_iot.c
View File

@@ -49,7 +49,10 @@ void configure_txpower_track(
if (dm->support_ic_type == ODM_RTL8195B)
configure_txpower_track_8195b(config);
#endif
#if RTL8710C_SUPPORT
if (dm->support_ic_type == ODM_RTL8710C)
configure_txpower_track_8710c(config);
#endif
#if RTL8721D_SUPPORT
if (dm->support_ic_type == ODM_RTL8721D)
configure_txpower_track_8721d(config);
@@ -130,19 +133,33 @@ odm_txpowertracking_callback_thermal_meter(
u8 *delta_swing_table_idx_tdown_a = NULL;
u8 *delta_swing_table_idx_tup_b = NULL;
u8 *delta_swing_table_idx_tdown_b = NULL;
#if (RTL8721D_SUPPORT == 1)
u8 *delta_swing_table_idx_tup_a_cck = NULL;
u8 *delta_swing_table_idx_tdown_a_cck = NULL;
u8 *delta_swing_table_idx_tup_b_cck = NULL;
u8 *delta_swing_table_idx_tdown_b_cck = NULL;
#endif
/*for Xtal Offset by James.Tung*/
s8 *delta_swing_table_xtal_up = NULL;
s8 *delta_swing_table_xtal_down = NULL;
/* 4 2. Initialization ( 7 steps in total ) */
indexforchannel = odm_get_right_chnl_place_for_iqk(*dm->channel);
configure_txpower_track(dm, &c);
#if (RTL8721D_SUPPORT == 1)
(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b,
(u8 **)&delta_swing_table_idx_tup_a_cck, (u8 **)&delta_swing_table_idx_tdown_a_cck,
(u8 **)&delta_swing_table_idx_tup_b_cck, (u8 **)&delta_swing_table_idx_tdown_b_cck);
#else
(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
#endif
/*for Xtal Offset*/
if (dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8721D))
if (dm->support_ic_type == ODM_RTL8195B ||
dm->support_ic_type == ODM_RTL8721D ||
dm->support_ic_type == ODM_RTL8710C)
(*c.get_delta_swing_xtal_table)(dm,
(s8 **)&delta_swing_table_xtal_up,
(s8 **)&delta_swing_table_xtal_down);
@@ -160,7 +177,8 @@ odm_txpowertracking_callback_thermal_meter(
"cali_info->txpowertrack_control = %d, hal_data->eeprom_thermal_meter %d\n",
cali_info->txpowertrack_control, rf->eeprom_thermal);
if (dm->support_ic_type == ODM_RTL8721D)
if (dm->support_ic_type == ODM_RTL8721D
|| dm->support_ic_type == ODM_RTL8710C)
thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A,
c.thermal_reg_addr, 0x7e0);
/* 0x42: RF Reg[10:5] 8721D */
@@ -252,7 +270,16 @@ odm_txpowertracking_callback_thermal_meter(
case RF_PATH_B:
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
#if (RTL8721D_SUPPORT == 1)
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tup_b_cck[%d] = %d\n", delta, delta_swing_table_idx_tup_b_cck[delta]);
cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_b_cck[delta];
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_cck_swing_idx[RF_PATH_B] = %d\n",
cali_info->absolute_cck_swing_idx[p]);
#endif
cali_info->delta_power_index[p] =
delta_swing_table_idx_tup_b
[delta];
@@ -267,7 +294,15 @@ odm_txpowertracking_callback_thermal_meter(
default:
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
#if (RTL8721D_SUPPORT == 1)
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tup_a_cck[%d] = %d\n", delta, delta_swing_table_idx_tup_a_cck[delta]);
cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_a_cck[delta];
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_cck_swing_idx[p]);
#endif
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
cali_info->absolute_ofdm_swing_idx[p] =
delta_swing_table_idx_tup_a[delta];
@@ -279,8 +314,9 @@ odm_txpowertracking_callback_thermal_meter(
}
}
/* JJ ADD 20161014 */
if (dm->support_ic_type &
(ODM_RTL8195B | ODM_RTL8721D)) {
if (dm->support_ic_type == ODM_RTL8195B ||
dm->support_ic_type == ODM_RTL8721D ||
dm->support_ic_type == ODM_RTL8710C) {
/*Save xtal_offset from Xtal table*/
cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
@@ -297,6 +333,15 @@ odm_txpowertracking_callback_thermal_meter(
case RF_PATH_B:
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
#if (RTL8721D_SUPPORT == 1)
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_b_cck[%d] = %d\n", delta, delta_swing_table_idx_tdown_b_cck[delta]);
cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b_cck[delta];
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_cck_swing_idx[p]);
#endif
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
@@ -306,6 +351,15 @@ odm_txpowertracking_callback_thermal_meter(
default:
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
#if (RTL8721D_SUPPORT == 1)
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_a_cck[%d] = %d\n", delta, delta_swing_table_idx_tdown_a_cck[delta]);
cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a_cck[delta];
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_cck_swing_idx[p]);
#endif
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
@@ -315,8 +369,9 @@ odm_txpowertracking_callback_thermal_meter(
}
/* JJ ADD 20161014 */
if (dm->support_ic_type &
(ODM_RTL8195B | ODM_RTL8721D)) {
if (dm->support_ic_type == ODM_RTL8195B ||
dm->support_ic_type == ODM_RTL8721D ||
dm->support_ic_type == ODM_RTL8710C) {
/*Save xtal_offset from Xtal table*/
cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
@@ -386,6 +441,38 @@ odm_txpowertracking_callback_thermal_meter(
cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]);
}
#endif
#if (RTL8721D_SUPPORT == 1)
if (thermal_value != cali_info->thermal_value) {
if (thermal_value > rf->eeprom_thermal)
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"Temperature(%d) higher than PG value(%d)\n",
thermal_value, rf->eeprom_thermal);
else if (thermal_value < rf->eeprom_thermal)
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"Temperature(%d) lower than PG value(%d)\n",
thermal_value, rf->eeprom_thermal);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"**********Enter POWER Tracking MIX_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p,
indexforchannel);
/*Record last time Power Tracking result as base.*/
cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;
for (p = RF_PATH_A; p < c.rf_path_count; p++)
cali_info->bb_swing_idx_ofdm_base[p] =
cali_info->bb_swing_idx_ofdm[p];
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"cali_info->thermal_value = %d thermal_value= %d\n",
cali_info->thermal_value, thermal_value);
/*Record last Power Tracking Thermal value*/
cali_info->thermal_value = thermal_value;
}
#else
if (thermal_value > rf->eeprom_thermal) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"Temperature(%d) higher than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
@@ -404,7 +491,7 @@ odm_txpowertracking_callback_thermal_meter(
dm->support_ic_type == ODM_RTL8710B ||
dm->support_ic_type == ODM_RTL8192F ||
dm->support_ic_type == ODM_RTL8195B ||
dm->support_ic_type == ODM_RTL8721D){
dm->support_ic_type == ODM_RTL8710C){
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
@@ -431,7 +518,7 @@ odm_txpowertracking_callback_thermal_meter(
dm->support_ic_type == ODM_RTL8710B ||
dm->support_ic_type == ODM_RTL8192F ||
dm->support_ic_type == ODM_RTL8195B ||
dm->support_ic_type == ODM_RTL8721D) {
dm->support_ic_type == ODM_RTL8710C) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel);
@@ -450,9 +537,11 @@ odm_txpowertracking_callback_thermal_meter(
cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
}
#endif
/* JJ ADD 20161014 */
if (dm->support_ic_type == (ODM_RTL8195B | ODM_RTL8721D)) {
if (dm->support_ic_type == ODM_RTL8195B ||
dm->support_ic_type == ODM_RTL8721D ||
dm->support_ic_type == ODM_RTL8710C) {
if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (rf->eeprom_thermal != 0xff)) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
@@ -468,7 +557,7 @@ odm_txpowertracking_callback_thermal_meter(
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
}
}
#if (!RTL8721D_SUPPORT)
/* Wait sacn to do IQK by RF Jenyu*/
if ((!*dm->is_scan_in_process) && (!iqk_info->rfk_forbidden)) {
/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
@@ -479,7 +568,7 @@ odm_txpowertracking_callback_thermal_meter(
(*c.do_iqk)(dm, delta_IQK, thermal_value, 8);
}
}
#endif
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n");
cali_info->tx_powercount = 0;
@@ -498,17 +587,49 @@ odm_reset_iqk_result(
return;
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
{
u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64,
100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122,
124, 126, 128, 130, 132, 134, 136, 138, 140,
149, 151, 153, 155, 157, 159, 161, 163, 165};
u8 place = chnl;
if (chnl > 14) {
for (place = 14; place < sizeof(channel_all); place++) {
if (channel_all[place] == chnl)
return place - 13;
}
}
return 0;
}
#endif
void
odm_iq_calibrate(
struct dm_struct *dm
)
odm_rf_calibrate(struct dm_struct *dm)
{
#if (RTL8721D_SUPPORT == 1)
struct dm_iqk_info *iqk_info = &dm->IQK_info;
if (dm->is_linked && !iqk_info->rfk_forbidden) {
if ((*dm->channel != dm->pre_channel) &&
(!*dm->is_scan_in_process)) {
dm->pre_channel = *dm->channel;
dm->linked_interval = 0;
}
if (dm->linked_interval < 3)
dm->linked_interval++;
if (dm->linked_interval == 2)
halrf_rf_k_connect_trigger(dm, 0, SEGMENT_FREE);
} else {
dm->linked_interval = 0;
}
#endif
}
void phydm_rf_init(void *dm_void)
@@ -525,4 +646,7 @@ void phydm_rf_watchdog(void *dm_void)
struct dm_struct *dm = (struct dm_struct *)dm_void;
odm_txpowertracking_check(dm);
#if (RTL8721D_SUPPORT == 1)
odm_rf_calibrate(dm);
#endif
}

17
hal/phydm/halrf/halphyrf_iot.h
View File

@@ -39,6 +39,13 @@
#include "halrf/rtl8195b/halrf_dpk_8195b.h"
#endif
#if (RTL8710C_SUPPORT == 1)
// #include "halrf/rtl8710c/halrf.h"
#include "halrf/rtl8710c/halrf_iqk_8710c.h"
// #include "halrf/rtl8710c/halrf_txgapk_8710c.h"
// #include "halrf/rtl8710c/halrf_dpk_8710c.h"
#endif
#include "halrf/halrf_powertracking_iot.h"
@@ -53,13 +60,19 @@ enum pwrtrack_method {
MIX_MODE,
TSSI_MODE,
MIX_2G_TSSI_5G_MODE,
MIX_5G_TSSI_2G_MODE
MIX_5G_TSSI_2G_MODE,
CLEAN_MODE
};
typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
typedef void(*func_iqk)(void *, u8, u8, u8);
typedef void (*func_lck)(void *);
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
#if (RTL8721D_SUPPORT == 1)
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **,
u8 **, u8 **, u8 **, u8 **);
#else
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
#endif
typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void(*func_swing_xtal)(void *, s8 **, s8 **);
typedef void(*func_set_xtal)(void *);

262
hal/phydm/halrf/halphyrf_win.c
View File

@@ -104,6 +104,12 @@ void configure_txpower_track(
configure_txpower_track_8822c(config);
#endif
#if RTL8814B_SUPPORT
if (dm->support_ic_type == ODM_RTL8814B)
configure_txpower_track_8814b(config);
#endif
}
/* **********************************************************************
@@ -171,8 +177,9 @@ odm_txpowertracking_callback_thermal_meter(
#endif
#endif
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
struct dm_iqk_info *iqk_info = &dm->IQK_info;
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
struct dm_iqk_info *iqk_info = &dm->IQK_info;
struct _hal_rf_ *rf = &(dm->rf_table);
u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
s8 diff_DPK[4] = {0};
u8 thermal_value_avg_count = 0;
@@ -207,7 +214,7 @@ odm_txpowertracking_callback_thermal_meter(
(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
if (dm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/
if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8814B)) /*for 8814 path C & D*/
(*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
/* JJ ADD 20161014 */
@@ -559,7 +566,10 @@ odm_txpowertracking_callback_thermal_meter(
cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]);
}
if ((dm->support_ic_type & ODM_RTL8814A)) {
if (dm->support_ic_type & ODM_RTL8814B)
power_tracking_type = TSSI_MODE;
if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8814B)) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "power_tracking_type=%d\n", power_tracking_type);
if (power_tracking_type == 0) {
@@ -743,7 +753,233 @@ odm_txpowertracking_callback_thermal_meter(
cali_info->tx_powercount = 0;
}
#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
void
odm_txpowertracking_new_callback_thermal_meter(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
struct dm_iqk_info *iqk_info = &dm->IQK_info;
struct _hal_rf_ *rf = &dm->rf_table;
struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
u8 thermal_value[MAX_RF_PATH] = {0}, delta[MAX_RF_PATH] = {0};
u8 delta_swing_table_idx_tup[DELTA_SWINGIDX_SIZE] = {0};
u8 delta_swing_table_idx_tdown[DELTA_SWINGIDX_SIZE] = {0};
u8 delta_LCK = 0, delta_IQK = 0, i = 0, j = 0, p;
u8 thermal_value_avg_count[MAX_RF_PATH] = {0};
u32 thermal_value_avg[MAX_RF_PATH] = {0};
s8 thermal_value_temp[MAX_RF_PATH] = {0};
u8 tracking_method = MIX_MODE;
struct txpwrtrack_cfg c;
u8 *delta_swing_table_idx_tup_a = NULL;
u8 *delta_swing_table_idx_tdown_a = NULL;
u8 *delta_swing_table_idx_tup_b = NULL;
u8 *delta_swing_table_idx_tdown_b = NULL;
u8 *delta_swing_table_idx_tup_c = NULL;
u8 *delta_swing_table_idx_tdown_c = NULL;
u8 *delta_swing_table_idx_tup_d = NULL;
u8 *delta_swing_table_idx_tdown_d = NULL;
configure_txpower_track(dm, &c);
(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
if (dm->support_ic_type == ODM_RTL8814B) {
(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
}
cali_info->txpowertracking_callback_cnt++;
cali_info->is_txpowertracking_init = true;
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"cali_info->txpowertrack_control=%d, tssi->thermal[RF_PATH_A]=%d tssi->thermal[RF_PATH_B]=%d\n",
cali_info->txpowertrack_control, tssi->thermal[RF_PATH_A], tssi->thermal[RF_PATH_B]);
if (dm->support_ic_type == ODM_RTL8822C) {
for (i = 0; i < c.rf_path_count; i++)
thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0x7e); /* 0x42: RF Reg[6:1] Thermal Trim*/
} else {
for (i = 0; i < c.rf_path_count; i++) {
thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10]*/
thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_thermal_offset(dm);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + power_time_thermal(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_thermal_offset(dm));
if (thermal_value_temp[i] > 63)
thermal_value[i] = 63;
else if (thermal_value_temp[i] < 0)
thermal_value[i] = 0;
else
thermal_value[i] = thermal_value_temp[i];
}
}
if ((tssi->thermal[RF_PATH_A] == 0xff || tssi->thermal[RF_PATH_B] == 0xff)) {
for (i = 0; i < c.rf_path_count; i++)
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no pg, tssi->thermal[%d] = 0x%x\n",
i, tssi->thermal[i]);
return;
}
for (j = 0; j < c.rf_path_count; j++) {
cali_info->thermal_value_avg_path[j][cali_info->thermal_value_avg_index_path[j]] = thermal_value[j];
cali_info->thermal_value_avg_index_path[j]++;
if (cali_info->thermal_value_avg_index_path[j] == c.average_thermal_num) /*Average times = c.average_thermal_num*/
cali_info->thermal_value_avg_index_path[j] = 0;
for (i = 0; i < c.average_thermal_num; i++) {
if (cali_info->thermal_value_avg_path[j][i]) {
thermal_value_avg[j] += cali_info->thermal_value_avg_path[j][i];
thermal_value_avg_count[j]++;
}
}
if (thermal_value_avg_count[j]) { /* Calculate Average thermal_value after average enough times */
thermal_value[j] = (u8)(thermal_value_avg[j] / thermal_value_avg_count[j]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"AVG Thermal Meter = 0x%X, tssi->thermal[%d] = 0x%x\n",
thermal_value[j], j, tssi->thermal[j]);
}
/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
/* "delta" here is used to determine whether thermal value changes or not. */
delta[j] = (thermal_value[j] > cali_info->thermal_value_path[j]) ? (thermal_value[j] - cali_info->thermal_value_path[j]) : (cali_info->thermal_value_path[j] - thermal_value[j]);
delta_LCK = (thermal_value[0] > cali_info->thermal_value_lck) ? (thermal_value[0] - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value[0]);
delta_IQK = (thermal_value[0] > cali_info->thermal_value_iqk) ? (thermal_value[0] - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value[0]);
}
/*4 6. If necessary, do LCK.*/
for (i = 0; i < c.rf_path_count; i++)
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta[%d], delta_LCK, delta_IQK) = (%d, %d, %d)\n", i, delta[i], delta_LCK, delta_IQK);
/* Wait sacn to do LCK by RF Jenyu*/
if( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
/* Delta temperature is equal to or larger than 20 centigrade.*/
if (delta_LCK >= c.threshold_iqk) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
cali_info->thermal_value_lck = thermal_value[RF_PATH_A];
/*Use RTLCK, so close power tracking driver LCK*/
if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
if (c.phy_lc_calibrate)
(*c.phy_lc_calibrate)(dm);
} else
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do not do LCK\n");
}
}
/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
for (i = 0; i < c.rf_path_count; i++) {
if (i == RF_PATH_B) {
odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_b, DELTA_SWINGIDX_SIZE);
odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_b, DELTA_SWINGIDX_SIZE);
} else if (i == RF_PATH_C) {
odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_c, DELTA_SWINGIDX_SIZE);
odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_c, DELTA_SWINGIDX_SIZE);
} else if (i == RF_PATH_D) {
odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_d, DELTA_SWINGIDX_SIZE);
odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_d, DELTA_SWINGIDX_SIZE);
} else {
odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_a, DELTA_SWINGIDX_SIZE);
odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_a, DELTA_SWINGIDX_SIZE);
}
cali_info->delta_power_index_last[i] = cali_info->delta_power_index[i]; /*recording poer index offset*/
delta[i] = thermal_value[i] > tssi->thermal[i] ? (thermal_value[i] - tssi->thermal[i]) : (tssi->thermal[i] - thermal_value[i]);
if (delta[i] >= TXPWR_TRACK_TABLE_SIZE)
delta[i] = TXPWR_TRACK_TABLE_SIZE - 1;
if (thermal_value[i] > tssi->thermal[i]) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tup[%d]=%d Path=%d\n", delta[i], delta_swing_table_idx_tup[delta[i]], i);
cali_info->delta_power_index[i] = delta_swing_table_idx_tup[delta[i]];
cali_info->absolute_ofdm_swing_idx[i] = delta_swing_table_idx_tup[delta[i]]; /*Record delta swing for mix mode power tracking*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\n", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);
} else {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tdown[%d]=%d Path=%d\n", delta[i], delta_swing_table_idx_tdown[delta[i]], i);
cali_info->delta_power_index[i] = -1 * delta_swing_table_idx_tdown[delta[i]];
cali_info->absolute_ofdm_swing_idx[i] = -1 * delta_swing_table_idx_tdown[delta[i]]; /*Record delta swing for mix mode power tracking*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\n", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);
}
}
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/
cali_info->power_index_offset[p] = 0;
else
cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/
}
#if 0
if (dm->support_ic_type == ODM_RTL8822C) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
} else {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
}
#endif
if (*dm->mp_mode == 1) {
if (cali_info->txpowertrack_control == 1) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
tracking_method = MIX_MODE;
} else if (cali_info->txpowertrack_control == 3) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI_MODE**********\n");
tracking_method = TSSI_MODE;
}
} else {
if (rf->power_track_type >= 0 && rf->power_track_type <= 3) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
tracking_method = MIX_MODE;
} else if (rf->power_track_type >= 4 && rf->power_track_type <= 7) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI_MODE**********\n");
tracking_method = TSSI_MODE;
}
}
if (dm->support_ic_type == ODM_RTL8822C || dm->support_ic_type == ODM_RTL8814B)
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, tracking_method, p, 0);
/* Wait sacn to do IQK by RF Jenyu*/
if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
if (delta_IQK >= c.threshold_iqk) {
cali_info->thermal_value_iqk = thermal_value[RF_PATH_A];
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
/*if (!cali_info->is_iqk_in_progress)*/
/* (*c.do_iqk)(dm, delta_IQK, thermal_value[RF_PATH_A], 8);*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do IQK\n");
/*if (!cali_info->is_iqk_in_progress)*/
/* (*c.do_tssi_dck)(dm, true);*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do TSSI DCK\n");
}
}
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===%s\n", __func__);
cali_info->tx_powercount = 0;
}
#endif
/* 3============================================================
* 3 IQ Calibration
@@ -830,12 +1066,20 @@ void phydm_rf_init(struct dm_struct *dm)
}
void phydm_rf_watchdog(struct dm_struct *dm)
void phydm_rf_watchdog(struct dm_struct *dm)
{
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
FunctionIn(COMP_MLME);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
odm_txpowertracking_check(dm);
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
odm_iq_calibrate(dm);
if (*dm->mp_mode == 1) {
#if (MP_DRIVER == 1)
odm_txpowertracking_check(dm);
#endif
} else {
odm_txpowertracking_check(dm);
if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES))
odm_iq_calibrate(dm);
}
#endif
}

12
hal/phydm/halrf/halphyrf_win.h
View File

@@ -53,12 +53,14 @@ enum pwrtrack_method {
MIX_MODE,
TSSI_MODE,
MIX_2G_TSSI_5G_MODE,
MIX_5G_TSSI_2G_MODE
MIX_5G_TSSI_2G_MODE,
CLEAN_MODE
};
typedef void(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
typedef void(*func_iqk)(void *, u8, u8, u8);
typedef void(*func_lck)(void *);
typedef void(*func_tssi_dck)(void *, u8);
typedef void(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
@@ -75,7 +77,8 @@ struct txpwrtrack_cfg {
u32 thermal_reg_addr;
func_set_pwr odm_tx_pwr_track_set_pwr;
func_iqk do_iqk;
func_lck phy_lc_calibrate;
func_lck phy_lc_calibrate;
func_tssi_dck do_tssi_dck;
func_swing get_delta_swing_table;
func_swing8814only get_delta_swing_table8814only;
func_swing_xtal get_delta_swing_xtal_table;
@@ -104,7 +107,10 @@ odm_txpowertracking_callback_thermal_meter(
#endif
);
#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
void
odm_txpowertracking_new_callback_thermal_meter(void *dm_void);
#endif
#define ODM_TARGET_CHNL_NUM_2G_5G 59

1714
hal/phydm/halrf/halrf.c
View File

File diff suppressed because it is too large Load Diff

224
hal/phydm/halrf/halrf.h
View File

@@ -41,14 +41,22 @@
#endif
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
#if (RTL8197G_SUPPORT == 1)
#include "halrf/rtl8197g/halrf_rfk_init_8197g.h"
#endif
#if (RTL8198F_SUPPORT == 1)
#include "halrf/rtl8198f/halrf_rfk_init_8198f.h"
#endif
#if (RTL8812F_SUPPORT == 1)
#include "halrf/rtl8812f/halrf_rfk_init_8812f.h"
#endif
#endif
#if (RTL8814B_SUPPORT == 1)
#include "halrf/rtl8814b/halrf_rfk_init_8814b.h"
#include "halrf/rtl8814b/halrf_iqk_8814b.h"
#include "halrf/rtl8814b/halrf_dpk_8814b.h"
#endif
/*@============================================================*/
@@ -90,11 +98,14 @@
#define IQK_VER_8703B "0x05"
#define IQK_VER_8710B "0x01"
#define IQK_VER_8723D "0x02"
#define IQK_VER_8822B "0x2f"
#define IQK_VER_8822C "0x03"
#define IQK_VER_8822B "0x32"
#define IQK_VER_8822C "0x0c"
#define IQK_VER_8821C "0x23"
#define IQK_VER_8198F "0x09"
#define IQK_VER_8814B "0x06"
#define IQK_VER_8198F "0x0a"
#define IQK_VER_8814B "0x0e"
#define IQK_VER_8812F "0x08"
#define IQK_VER_8710C "0x05"
#define IQK_VER_8197G "0x02"
/*LCK version*/
#define LCK_VER_8188E "0x01"
@@ -112,8 +123,10 @@
#define LCK_VER_8822B "0x02"
#define LCK_VER_8822C "0x00"
#define LCK_VER_8821C "0x02"
#define LCK_VER_8814B "0x00"
#define LCK_VER_8814B "0x01"
#define LCK_VER_8195B "0x02"
#define LCK_VER_8710C "0x01"
#define LCK_VER_8197G "0x00"
/*power tracking version*/
#define PWRTRK_VER_8188E "0x01"
@@ -132,6 +145,7 @@
#define PWRTRK_VER_8822C "0x00"
#define PWRTRK_VER_8821C "0x01"
#define PWRTRK_VER_8814B "0x00"
#define PWRTRK_VER_8197G "0x00"
/*DPK version*/
#define DPK_VER_8188E "NONE"
@@ -146,22 +160,27 @@
#define DPK_VER_8710B "NONE"
#define DPK_VER_8723D "NONE"
#define DPK_VER_8822B "NONE"
#define DPK_VER_8822C "0x04"
#define DPK_VER_8822C "0x19"
#define DPK_VER_8821C "NONE"
#define DPK_VER_8192F "0x0c"
#define DPK_VER_8198F "0x0a"
#define DPK_VER_8814B "0x00"
#define DPK_VER_8195B "0x06"
#define DPK_VER_8192F "0x0d"
#define DPK_VER_8198F "0x0e"
#define DPK_VER_8814B "0x08"
#define DPK_VER_8195B "0x0b"
#define DPK_VER_8812F "0x06"
#define DPK_VER_8197G "0x04"
/*RFK_INIT version*/
#define RFK_INIT_VER_8822B "0x8"
#define RFK_INIT_VER_8822C "0x3"
#define RFK_INIT_VER_8822C "0x7"
#define RFK_INIT_VER_8195B "0x1"
#define RFK_INIT_VER_8198F "0x5"
#define RFK_INIT_VER_8814B "0x5"
#define RFK_INIT_VER_8198F "0x8"
#define RFK_INIT_VER_8814B "0xa"
#define RFK_INIT_VER_8812F "0x3"
#define RFK_INIT_VER_8197G "0x3"
/*DACK version*/
#define DACK_VER_8822C "0x3"
#define DACK_VER_8822C "0x6"
#define DACK_VER_8814B "0x3"
/*Kfree tracking version*/
#define KFREE_VER_8188E \
@@ -196,6 +215,14 @@
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
#define KFREE_VER_8814B \
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
#define KFREE_VER_8197G \
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
#define TSSI_VER_8812F "0x1"
#define TSSI_VER_8822C "0x1"
#define TSSI_VER_8821C "0x1"
#define TSSI_VER_8814B "0x1"
#define TSSI_VER_8197G "0x1"
/*PA Bias Calibration version*/
#define PABIASK_VER_8188E \
@@ -230,6 +257,8 @@
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define PABIASK_VER_8814B \
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define PABIASK_VER_8197G \
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define HALRF_IQK_VER \
(dm->support_ic_type == ODM_RTL8188E) ? IQK_VER_8188E : \
@@ -247,7 +276,9 @@
(dm->support_ic_type == ODM_RTL8822B) ? IQK_VER_8822B : \
(dm->support_ic_type == ODM_RTL8822C) ? IQK_VER_8822C : \
(dm->support_ic_type == ODM_RTL8821C) ? IQK_VER_8821C : \
(dm->support_ic_type == ODM_RTL8814B) ? IQK_VER_8814B : "unknown"
(dm->support_ic_type == ODM_RTL8814B) ? IQK_VER_8814B : \
(dm->support_ic_type == ODM_RTL8710C) ? IQK_VER_8710C : \
(dm->support_ic_type == ODM_RTL8197G) ? IQK_VER_8197G : "unknown"
#define HALRF_LCK_VER \
(dm->support_ic_type == ODM_RTL8188E) ? LCK_VER_8188E : \
@@ -265,8 +296,9 @@
(dm->support_ic_type == ODM_RTL8822B) ? LCK_VER_8822B : \
(dm->support_ic_type == ODM_RTL8822C) ? LCK_VER_8822C : \
(dm->support_ic_type == ODM_RTL8821C) ? LCK_VER_8821C : \
(dm->support_ic_type == ODM_RTL8814B) ? LCK_VER_8814B : "unknown"
(dm->support_ic_type == ODM_RTL8814B) ? LCK_VER_8814B : \
(dm->support_ic_type == ODM_RTL8710C) ? LCK_VER_8710C : \
(dm->support_ic_type == ODM_RTL8710C) ? LCK_VER_8710C : "unknown"
#define HALRF_POWRTRACKING_VER \
(dm->support_ic_type == ODM_RTL8188E) ? PWRTRK_VER_8188E : \
(dm->support_ic_type == ODM_RTL8192E) ? PWRTRK_VER_8192E : \
@@ -283,7 +315,7 @@
(dm->support_ic_type == ODM_RTL8822B) ? PWRTRK_VER_8822B : \
(dm->support_ic_type == ODM_RTL8822C) ? PWRTRK_VER_8822C : \
(dm->support_ic_type == ODM_RTL8821C) ? PWRTRK_VER_8821C : \
(dm->support_ic_type == ODM_RTL8814B) ? PWRTRK_VER_8814B : "unknown"
(dm->support_ic_type == ODM_RTL8197G) ? PWRTRK_VER_8197G : "unknown"
#define HALRF_DPK_VER \
(dm->support_ic_type == ODM_RTL8188E) ? DPK_VER_8188E : \
@@ -302,7 +334,8 @@
(dm->support_ic_type == ODM_RTL8822B) ? DPK_VER_8822B : \
(dm->support_ic_type == ODM_RTL8822C) ? DPK_VER_8822C : \
(dm->support_ic_type == ODM_RTL8821C) ? DPK_VER_8821C : \
(dm->support_ic_type == ODM_RTL8814B) ? DPK_VER_8814B : "unknown"
(dm->support_ic_type == ODM_RTL8814B) ? DPK_VER_8814B : \
(dm->support_ic_type == ODM_RTL8197G) ? DPK_VER_8197G : "unknown"
#define HALRF_KFREE_VER \
(dm->support_ic_type == ODM_RTL8188E) ? KFREE_VER_8188E : \
@@ -320,7 +353,15 @@
(dm->support_ic_type == ODM_RTL8822B) ? KFREE_VER_8822B : \
(dm->support_ic_type == ODM_RTL8822C) ? KFREE_VER_8822C : \
(dm->support_ic_type == ODM_RTL8821C) ? KFREE_VER_8821C : \
(dm->support_ic_type == ODM_RTL8814B) ? KFREE_VER_8814B : "unknown"
(dm->support_ic_type == ODM_RTL8814B) ? KFREE_VER_8814B : \
(dm->support_ic_type == ODM_RTL8197G) ? KFREE_VER_8197G : "unknown"
#define HALRF_TSSI_VER \
(dm->support_ic_type == ODM_RTL8812F) ? TSSI_VER_8812F : \
(dm->support_ic_type == ODM_RTL8822C) ? TSSI_VER_8822C : \
(dm->support_ic_type == ODM_RTL8821C) ? TSSI_VER_8821C : \
(dm->support_ic_type == ODM_RTL8814B) ? TSSI_VER_8814B : \
(dm->support_ic_type == ODM_RTL8197G) ? TSSI_VER_8197G : "unknown"
#define HALRF_PABIASK_VER \
(dm->support_ic_type == ODM_RTL8188E) ? PABIASK_VER_8188E : \
@@ -338,21 +379,31 @@
(dm->support_ic_type == ODM_RTL8822B) ? PABIASK_VER_8822B : \
(dm->support_ic_type == ODM_RTL8822C) ? PABIASK_VER_8822C : \
(dm->support_ic_type == ODM_RTL8821C) ? PABIASK_VER_8821C : \
(dm->support_ic_type == ODM_RTL8814B) ? PABIASK_VER_8814B : "unknown"
(dm->support_ic_type == ODM_RTL8814B) ? PABIASK_VER_8814B : \
(dm->support_ic_type == ODM_RTL8197G) ? PABIASK_VER_8197G : "unknown"
#define HALRF_RFK_INIT_VER \
(dm->support_ic_type == ODM_RTL8822B) ? RFK_INIT_VER_8822B : \
(dm->support_ic_type == ODM_RTL8822C) ? RFK_INIT_VER_8822C : \
(dm->support_ic_type == ODM_RTL8198F) ? RFK_INIT_VER_8198F : \
(dm->support_ic_type == ODM_RTL8814B) ? RFK_INIT_VER_8814B : "unknown"
(dm->support_ic_type == ODM_RTL8814B) ? RFK_INIT_VER_8814B : \
(dm->support_ic_type == ODM_RTL8197G) ? RFK_INIT_VER_8197G : "unknown"
#define HALRF_DACK_VER \
(dm->support_ic_type == ODM_RTL8822C) ? DACK_VER_8822C : "unknown"
(dm->support_ic_type == ODM_RTL8822C) ? DACK_VER_8822C : \
(dm->support_ic_type == ODM_RTL8814B) ? DACK_VER_8814B : "unknown"
#define IQK_THRESHOLD 8
#define DPK_THRESHOLD 4
#define HALRF_ABS(a,b) ((a>b) ? (a-b) : (b-a))
#define SN 100
#define CCK_TSSI_NUM 6
#define OFDM_2G_TSSI_NUM 5
#define OFDM_5G_TSSI_NUM 14
/*@===========================================================*/
/*AGC RX High Power mode*/
/*@===========================================================*/
@@ -365,12 +416,13 @@
/*@============================================================*/
enum halrf_func_idx { /*F_XXX = PHYDM XXX function*/
RF00_PWR_TRK = 0,
RF01_IQK = 1,
RF00_PWR_TRK = 0, /*Pow_trk, TSSI_trk*/
RF01_IQK = 1, /*LOK, IQK*/
RF02_LCK = 2,
RF03_DPK = 3,
RF04_TXGAPK = 4,
RF05_DACK = 5,
RF06_DPK_TRK = 6,
RF07_2GBAND_SHIFT = 7
};
@@ -381,6 +433,7 @@ enum halrf_ability {
HAL_RF_DPK = BIT(RF03_DPK),
HAL_RF_TXGAPK = BIT(RF04_TXGAPK),
HAL_RF_DACK = BIT(RF05_DACK),
HAL_RF_DPK_TRACK = BIT(RF06_DPK_TRK),
HAL_2GBAND_SHIFT = BIT(RF07_2GBAND_SHIFT)
};
@@ -413,14 +466,16 @@ enum halrf_cmninfo_init {
HALRF_CMNINFO_MP_PSD_POINT,
HALRF_CMNINFO_MP_PSD_START_POINT,
HALRF_CMNINFO_MP_PSD_STOP_POINT,
HALRF_CMNINFO_MP_PSD_AVERAGE
HALRF_CMNINFO_MP_PSD_AVERAGE,
HALRF_CMNINFO_IQK_TIMES
};
enum halrf_cmninfo_hook {
HALRF_CMNINFO_CON_TX,
HALRF_CMNINFO_SINGLE_TONE,
HALRF_CMNINFO_CARRIER_SUPPRESSION,
HALRF_CMNINFO_MP_RATE_INDEX
HALRF_CMNINFO_MP_RATE_INDEX,
HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY
};
enum halrf_lna_set {
@@ -428,6 +483,41 @@ enum halrf_lna_set {
HALRF_LNA_ENABLE = 1,
};
enum halrf_k_segment_time {
SEGMENT_FREE = 0,
SEGMENT_10MS = 10, /*10ms*/
SEGMENT_30MS = 30, /*30ms*/
SEGMENT_50MS = 50, /*50ms*/
};
#define POWER_INDEX_DIFF 4
#define TSSI_TXAGC_DIFF 2
#define TSSI_CODE_NUM 84
#define TSSI_SLOPE_2G 8
#define TSSI_SLOPE_5G 5
#define TSSI_EFUSE_NUM 25
#define TSSI_EFUSE_KFREE_NUM 4
struct _halrf_tssi_data {
s32 cck_offset_patha;
s32 cck_offset_pathb;
s32 tssi_trk_txagc_offset[PHYDM_MAX_RF_PATH];
s32 delta_tssi_txagc_offset[PHYDM_MAX_RF_PATH];
s16 txagc_codeword[TSSI_CODE_NUM];
u16 tssi_codeword[TSSI_CODE_NUM];
s8 tssi_efuse[PHYDM_MAX_RF_PATH][TSSI_EFUSE_NUM];
s8 tssi_kfree_efuse[PHYDM_MAX_RF_PATH][TSSI_EFUSE_KFREE_NUM];
u8 thermal[PHYDM_MAX_RF_PATH];
u32 index[PHYDM_MAX_RF_PATH][14];
u8 do_tssi;
u8 get_thermal;
u8 tssi_finish_bit[PHYDM_MAX_RF_PATH];
u8 thermal_trigger;
};
/*@============================================================*/
/*@ structure */
/*@============================================================*/
@@ -439,25 +529,34 @@ struct _hal_rf_ {
/*update*/
u32 rf_supportability;
u8 rf_shift_band;
/*u32 halrf_tssi_data;*/
u8 eeprom_thermal;
u8 dpk_en; /*Enable Function DPK OFF/ON = 0/1*/
boolean dpk_done;
u64 dpk_progressing_time;
u64 iqk_progressing_time;
u32 fw_ver;
boolean *is_con_tx;
boolean *is_single_tone;
boolean *is_carrier_suppresion;
boolean is_dpk_in_progress;
boolean is_tssi_in_progress;
boolean is_bt_iqk_timeout;
boolean aac_checked;
u8 *mp_rate_index;
u32 *manual_rf_supportability;
u32 p_rate_index;
u8 pwt_type;
u32 rf_dbg_comp;
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
struct _halrf_psd_data halrf_psd_data;
struct _halrf_tssi_data halrf_tssi_data;
#endif
u8 power_track_type;
u8 pre_band_type;
};
/*@============================================================*/
@@ -466,7 +565,9 @@ struct _hal_rf_ {
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
RTL8812F_SUPPORT == 1 || RTL8710C_SUPPORT == 1 ||\
RTL8197G_SUPPORT == 1)
void halrf_iqk_info_dump(void *dm_void, u32 *_used, char *output,
u32 *_out_len);
@@ -477,9 +578,10 @@ u8 halrf_match_iqk_version(void *dm_void);
void halrf_support_ability_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#ifdef CONFIG_2G_BAND_SHIFT
void halrf_support_band_shift_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
void halrf_cmn_info_init(void *dm_void, enum halrf_cmninfo_init cmn_info,
u32 value);
@@ -498,6 +600,11 @@ void halrf_init(void *dm_void);
void halrf_iqk_trigger(void *dm_void, boolean is_recovery);
void halrf_rfk_handshake(void *dm_void, boolean is_before_k);
void halrf_rf_k_connect_trigger(void *dm_void, boolean is_recovery,
enum halrf_k_segment_time seg_time);
void halrf_segment_iqk_trigger(void *dm_void, boolean clear,
boolean segment_iqk);
@@ -528,6 +635,8 @@ void halrf_dpk_track(void *dm_void);
void halrf_dpk_reload(void *dm_void);
void halrf_dpk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size);
/*Global function*/
void halrf_reload_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num);
@@ -558,16 +667,65 @@ halrf_config_rfk_with_header_file(void *dm_void, u32 config_type);
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
RTL8812F_SUPPORT == 1 || RTL8710C_SUPPORT == 1 ||\
RTL8197G_SUPPORT == 1)
void halrf_iqk_dbg(void *dm_void);
#endif
void halrf_tssi_init(void *dm_void);
void halrf_tssi_get_efuse(void *dm_void);
void halrf_do_tssi(void *dm_void);
void halrf_set_tssi_value(void *dm_void, u32 tssi_value);
void halrf_do_thermal(void *dm_void);
u32 halrf_set_tssi_value(void *dm_void, u32 tssi_value);
void halrf_set_tssi_power(void *dm_void, s8 power);
void halrf_tssi_set_de_for_tx_verify(void *dm_void, u32 tssi_de, u8 path);
u32 halrf_query_tssi_value(void *dm_void);
void halrf_tssi_cck(void *dm_void);
void halrf_thermal_cck(void *dm_void);
void halrf_tssi_set_de(void *dm_void);
void halrf_tssi_dck(void *dm_void, u8 direct_do);
void halrf_calculate_tssi_codeword(void *dm_void);
void halrf_set_tssi_codeword(void *dm_void);
u8 halrf_get_tssi_codeword_for_txindex(void *dm_void);
u32 halrf_tssi_get_de(void *dm_void, u8 path);
void halrf_tssi_trigger(void *dm_void);
void halrf_set_dpk_track(void *dm_void, u8 enable);
void halrf_set_dpkbychannel(void *dm_void, boolean dpk_by_ch);
void halrf_set_dpkenable(void *dm_void, boolean is_dpk_enable);
boolean halrf_get_dpkbychannel(void *dm_void);
boolean halrf_get_dpkenable(void *dm_void);
void _iqk_check_if_reload(void *dm_void);
void halrf_do_rxbb_dck(void *dm_void);
void config_halrf_path_adda_setting_trigger(void *dm_void);
void halrf_reload_iqk(void *dm_void, boolean reset);
void halrf_dack_dbg(void *dm_void);
void halrf_iqk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size);
void halrf_set_rfsupportability(void *dm_void);
#endif /*__HALRF_H__*/

87
hal/phydm/halrf/halrf_debug.c
View File

@@ -37,6 +37,78 @@ void halrf_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len)
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
u32 rf_release_ver = 0;
switch (dm->support_ic_type) {
#if (RTL8814A_SUPPORT)
case ODM_RTL8814A:
rf_release_ver = RF_RELEASE_VERSION_8814A;
break;
#endif
#if (RTL8821C_SUPPORT)
case ODM_RTL8821C:
rf_release_ver = RF_RELEASE_VERSION_8821C;
break;
#endif
#if (RTL8822B_SUPPORT)
case ODM_RTL8822B:
rf_release_ver = RF_RELEASE_VERSION_8822B;
break;
#endif
#if (RTL8822C_SUPPORT)
case ODM_RTL8822C:
rf_release_ver = RF_RELEASE_VERSION_8822C;
break;
#endif
#if (RTL8814B_SUPPORT)
case ODM_RTL8814B:
rf_release_ver = RF_RELEASE_VERSION_8814B;
break;
#endif
#if (RTL8812F_SUPPORT)
case ODM_RTL8812F:
rf_release_ver = RF_RELEASE_VERSION_8812F;
break;
#endif
#if (RTL8198F_SUPPORT)
case ODM_RTL8198F:
rf_release_ver = RF_RELEASE_VERSION_8198F;
break;
#endif
#if (RTL8197F_SUPPORT)
case ODM_RTL8197F:
rf_release_ver = RF_RELEASE_VERSION_8197F;
break;
#endif
#if (RTL8192F_SUPPORT)
case ODM_RTL8197F:
rf_release_ver = RF_RELEASE_VERSION_8192F;
break;
#endif
#if (RTL8710B_SUPPORT)
case ODM_RTL8710B:
rf_release_ver = RF_RELEASE_VERSION_8710B;
break;
#endif
#if (RTL8195B_SUPPORT)
case ODM_RTL8195B:
rf_release_ver = RF_RELEASE_VERSION_8195B;
break;
#endif
}
PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %d\n",
"RF Para Release Ver", rf_release_ver);
/* HAL RF version List */
PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n",
@@ -53,6 +125,8 @@ void halrf_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len)
"LCK", HALRF_LCK_VER);
PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
"DPK", HALRF_DPK_VER);
PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
"TSSI", HALRF_TSSI_VER);
PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
"KFREE", HALRF_KFREE_VER);
PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
@@ -139,7 +213,10 @@ enum halrf_CMD_ID {
HALRF_IQK_INFO,
HALRF_IQK,
HALRF_IQK_DEBUG,
HALRF_DPK,
#ifdef CONFIG_2G_BAND_SHIFT
HAL_BAND_SHIFT,
#endif
};
struct halrf_command halrf_cmd_ary[] = {
@@ -149,8 +226,11 @@ struct halrf_command halrf_cmd_ary[] = {
{"profile", HALRF_PROFILE},
{"iqk_info", HALRF_IQK_INFO},
{"iqk", HALRF_IQK},
{"dpk", HALRF_DPK},
{"iqk_dbg", HALRF_IQK_DEBUG},
#ifdef CONFIG_2G_BAND_SHIFT
{"band_shift", HAL_BAND_SHIFT},
#endif
};
void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
@@ -194,10 +274,12 @@ void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
halrf_support_ability_debug(dm, &input[0], &used, output,
&out_len);
break;
#ifdef CONFIG_2G_BAND_SHIFT
case HAL_BAND_SHIFT:
halrf_support_band_shift_debug(dm, &input[0], &used, output,
&out_len);
break;
#endif
case HALRF_DBG_COMP:
halrf_debug_trace(dm, &input[0], &used, output, &out_len);
break;
@@ -235,6 +317,11 @@ void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
#endif
}
break;
case HALRF_DPK:
PDM_SNPF(out_len, used, output + used, out_len - used,
"DPK Trigger\n");
halrf_dpk_trigger(dm);
break;
default:
break;
}

57
hal/phydm/halrf/halrf_dpk.h
View File

@@ -30,9 +30,11 @@
#define GAIN_LOSS 1
#define DO_DPK 2
#define DPK_ON 3
#define GAIN_LOSS_PULSE 4
#define DPK_PAS 5
#define DPK_LMS 6
#define DPK_LOK 4
#define DPK_TXK 5
#define DAGC 4
#define LOSS_CHK 0
#define GAIN_CHK 1
@@ -48,28 +50,64 @@ struct dm_dpk_info {
boolean is_dpk_enable;
boolean is_dpk_pwr_on;
boolean is_dpk_by_channel;
boolean is_tssi_mode;
boolean is_reload;
u16 dpk_path_ok;
/*@BIT(15)~BIT(12) : 5G reserved, BIT(11)~BIT(8) 5G_S3~5G_S0*/
/*@BIT(7)~BIT(4) : 2G reserved, BIT(3)~BIT(0) 2G_S3~2G_S0*/
u8 thermal_dpk;
u8 thermal_dpk_avg[AVG_THERMAL_NUM_DPK];
u8 thermal_dpk[4]; /*path*/
u8 thermal_dpk_avg[4][AVG_THERMAL_NUM_DPK]; /*path*/
u8 pre_pwsf[4];
u8 thermal_dpk_avg_index;
u32 gnt_control;
u32 gnt_value;
u8 dpk_ch;
u8 dpk_band;
u8 dpk_bw;
#if (RTL8822C_SUPPORT == 1)
u8 result[2][1]; /*path/group*/
u8 tx_agc[2][1]; /*path/group*/
u32 coef[2][1][20]; /*path/group/MDPD coefficient*/
#if (RTL8822C_SUPPORT == 1 || RTL8812F_SUPPORT == 1)
u8 result[2]; /*path*/
u8 dpk_txagc[2]; /*path*/
u32 coef[2][20]; /*path/MDPD coefficient*/
u16 dpk_gs[2]; /*MDPD coef gs*/
u8 thermal_dpk_delta[2]; /*path*/
#endif
#if (RTL8198F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
#if (RTL8198F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8197F_SUPPORT == 1 ||\
RTL8814B_SUPPORT == 1 || RTL8197G_SUPPORT == 1)
/*2G DPK data*/
u8 dpk_result[4][3]; /*path/group*/
u8 pwsf_2g[4][3]; /*path/group*/
u8 pwsf_2g[4][3]; /*path/group*/
u32 lut_2g_even[4][3][64]; /*path/group/LUT data*/
u32 lut_2g_odd[4][3][64]; /*path/group/LUT data*/
s16 tmp_pas_i[32]; /*PAScan I data*/
s16 tmp_pas_q[32]; /*PAScan Q data*/
/*5G DPK data*/
u8 dpk_5g_result[4][6]; /*path/group*/
u8 pwsf_5g[4][6]; /*path/group*/
u32 lut_5g[4][6][64]; /*path/group/LUT data*/
u32 lut_2g[4][3][64]; /*path/group/LUT data*/
/*8814B*/
u8 rxbb[4]; /*path/group*/
u8 txbb[4]; /*path/group*/
u8 tx_gain;
#endif
#if (RTL8195B_SUPPORT == 1)
/*2G DPK data*/
u8 dpk_2g_result[1][3]; /*path/group*/
u8 pwsf_2g[1][3]; /*path/group*/
u32 lut_2g_even[1][3][16]; /*path/group/LUT data*/
u32 lut_2g_odd[1][3][16]; /*path/group/LUT data*/
/*5G DPK data*/
u8 dpk_5g_result[1][13]; /*path/group*/
u8 pwsf_5g[1][13]; /*path/group*/
u32 lut_5g_even[1][13][16]; /*path/group/LUT data*/
u32 lut_5g_odd[1][13][16]; /*path/group/LUT data*/
#endif
#if (RTL8721D_SUPPORT == 1)
u8 dpk_txagc;
/*2G DPK data*/
u8 dpk_2g_result[1][3]; /*path/group*/
u8 pwsf_2g[1][3]; /*path/group*/
@@ -81,6 +119,7 @@ struct dm_dpk_info {
u32 lut_5g_even[1][6][16]; /*path/group/LUT data*/
u32 lut_5g_odd[1][6][16]; /*path/group/LUT data*/
#endif
};
#endif /*__HALRF_DPK_H__*/

25
hal/phydm/halrf/halrf_iqk.h
View File

@@ -36,7 +36,7 @@
#define RXIQK2 2
#define kcount_limit_80m 2
#define kcount_limit_others 4
#define rxiqk_gs_limit 10
#define rxiqk_gs_limit 6
#define TXWBIQK_EN 1
#define RXWBIQK_EN 1
#define NUM 4
@@ -47,6 +47,8 @@ struct dm_dack_info {
u32 qc_a;
u32 ic_b;
u32 qc_b;
boolean dack_en;
u16 msbk_d[2][2][15];
};
struct dm_iqk_info {
@@ -61,21 +63,37 @@ struct dm_iqk_info {
u8 rxiqk_step;
u8 tmp1bcc;
u8 txgain;
u32 txgain56;
u8 kcount;
u8 rfk_ing; /*bit0:IQKing, bit1:LCKing, bit2:DPKing*/
boolean rfk_forbidden;
u8 rxbb;
u32 rf_reg58;
boolean segment_iqk;
#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
RTL8812F_SUPPORT == 1 || RTL8197G_SUPPORT == 1 ||\
RTL8710C_SUPPORT == 1)
u32 iqk_channel[2];
boolean iqk_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */
/*channel / path / TRX(TX:0, RX:1) / CFIR_real*/
/*channel index = 2 is just for debug*/
#if (RTL8812F_SUPPORT == 1 || RTL8822C_SUPPORT == 1 )
u16 iqk_cfir_real[3][2][2][17];
/*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
/*channel index = 2 is just for debug*/
u16 iqk_cfir_imag[3][2][2][17];
u32 rx_cfir_real[2][2][17];
u32 rx_cfir_imag[2][2][17];
u32 rx_cfir[2][2];
/*times/path*/
#else
u32 iqk_cfir_real[3][4][2][8];
/*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
/*channel index = 2 is just for debug*/
u32 iqk_cfir_imag[3][4][2][8];
#endif
u8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */
u8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */
/* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */
@@ -88,7 +106,6 @@ struct dm_iqk_info {
boolean is_btg;
boolean isbnd;
boolean is_reload;
boolean segment_iqk;
boolean is_hwtx;
boolean xym_read;
boolean trximr_enable;
@@ -97,6 +114,8 @@ struct dm_iqk_info {
u32 gs1_xym[2][6];
u32 gs2_xym[2][6];
u32 rxk1_xym[2][6];
u32 txxy[2][2];
u32 rxxy[2][2];
#endif
};

1530
hal/phydm/halrf/halrf_kfree.c
View File

File diff suppressed because it is too large Load Diff

104
hal/phydm/halrf/halrf_kfree.h
View File

@@ -28,7 +28,7 @@
#define KFREE_VERSION "1.0"
#define KFREE_BAND_NUM 6
#define KFREE_BAND_NUM 9
#define KFREE_CH_NUM 3
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
@@ -45,13 +45,26 @@
#define PA_BIAS_FLAG_ON BIT(4)
#define TSSI_TRIM_FLAG_ON BIT(5)
#define LNA_FLAG_ON BIT(6)
#define PPG_THERMAL_OFFSET_98F 0x50
#define PPG_2GM_TXAB_98F 0x51
#define PPG_2GM_TXCD_98F 0x52
#define PPG_2GL_TXAB_98F 0x53
#define PPG_2GL_TXCD_98F 0x54
#define PPG_5GH_TXAB_98F 0x55
#define PPG_5GH_TXCD_98F 0x56
#define PPG_2GH_TXAB_98F 0x55
#define PPG_2GH_TXCD_98F 0x56
#define PPG_PABIAS_2GAB_98F 0x57
#define PPG_PABIAS_2GCD_98F 0x58
#define PPG_LNA_2GA_98F 0x59
#define PPG_LNA_2GB_98F 0x5a
#define PPG_LNA_2GC_98F 0x5b
#define PPG_LNA_2GD_98F 0x5c
#define PPG_THERMAL_OFFSET_21C 0x1EF
#define PPG_2G_TXAB_21C 0x1EE
@@ -88,10 +101,91 @@
#define PPG_PABIAS_2GA_22B 0x3D5
#define PPG_PABIAS_2GB_22B 0x3D6
#define PPG_THERMAL_A_OFFSET_22C 0x1ef
#define PPG_THERMAL_B_OFFSET_22C 0x1b0
#define PPG_2GL_TXAB_22C 0x1d4
#define PPG_2GM_TXAB_22C 0x1ee
#define PPG_2GH_TXAB_22C 0x1d2
#define PPG_5GL1_TXA_22C 0x1ec
#define PPG_5GL1_TXB_22C 0x1eb
#define PPG_5GL2_TXA_22C 0x1e8
#define PPG_5GL2_TXB_22C 0x1e7
#define PPG_5GM1_TXA_22C 0x1e4
#define PPG_5GM1_TXB_22C 0x1e3
#define PPG_5GM2_TXA_22C 0x1e0
#define PPG_5GM2_TXB_22C 0x1df
#define PPG_5GH1_TXA_22C 0x1dc
#define PPG_5GH1_TXB_22C 0x1db
#define PPG_PABIAS_2GA_22C 0x1d6
#define PPG_PABIAS_2GB_22C 0x1d5
#define PPG_PABIAS_5GA_22C 0x1d8
#define PPG_PABIAS_5GB_22C 0x1d7
#define TSSI_2GM_TXA_22C 0x1c0
#define TSSI_2GM_TXB_22C 0x1bf
#define TSSI_2GH_TXA_22C 0x1be
#define TSSI_2GH_TXB_22C 0x1bd
#define TSSI_5GL1_TXA_22C 0x1bc
#define TSSI_5GL1_TXB_22C 0x1bb
#define TSSI_5GL2_TXA_22C 0x1ba
#define TSSI_5GL2_TXB_22C 0x1b9
#define TSSI_5GM1_TXA_22C 0x1b8
#define TSSI_5GM1_TXB_22C 0x1b7
#define TSSI_5GM2_TXA_22C 0x1b6
#define TSSI_5GM2_TXB_22C 0x1b5
#define TSSI_5GH1_TXA_22C 0x1b4
#define TSSI_5GH1_TXB_22C 0x1b3
#define TSSI_5GH2_TXA_22C 0x1b2
#define TSSI_5GH2_TXB_22C 0x1b1
/*8195B*/
#define PPG_THERMAL_OFFSET_95B 0x1ef
#define PPG_2GL_TXA_95B 0x1d4
#define PPG_2GM_TXA_95B 0x1ee
#define PPG_2GH_TXA_95B 0x1d2
#define PPG_5GL1_TXA_95B 0x1ec
#define PPG_5GL2_TXA_95B 0x1e8
#define PPG_5GM1_TXA_95B 0x1e4
#define PPG_5GM2_TXA_95B 0x1e0
#define PPG_5GH1_TXA_95B 0x1dc
#define PPG_PABIAS_2GA_95B 0x1d6
#define PPG_PABIAS_5GA_95B 0x1d8
/*8721D*/
/*#define KFREE_BAND_NUM_8721D 6*/
#define PPG_THERMAL_OFFSET_8721D 0x1EF
#define PPG_2G_TXA_8721D 0x1EE
#define PPG_5GL1_TXA_8721D 0x1ED
#define PPG_5GL2_TXA_8721D 0x1EC
#define PPG_5GM1_TXA_8721D 0x1EB
#define PPG_5GM2_TXA_8721D 0x1EA
#define PPG_5GH1_TXA_8721D 0x1E9
/*8197G*/
#define PPG_THERMAL_OFFSET_97G 0x50
#define PPG_2GM_TXAB_97G 0x51
#define PPG_2GL_TXAB_97G 0x53
#define PPG_2GH_TXAB_97G 0x55
#define PPG_PABIAS_2GAB_97G 0x57
#define PPG_LNA_2GA_97G 0x21
#define PPG_LNA_2GB_97G 0x22
/*8710C Ameba Z2*/
#define PPG_THERMAL_OFFSET_10C 0x1EF
#define PPG_2GL_TX_10C 0x1D4
#define PPG_2GM_TX_10C 0x1EE
#define PPG_2GH_TX_10C 0x1D2
#define PPG_PABIAS_10C 0x1D6
#define PPG_LNA_10C 0x1D0
struct odm_power_trim_data {
u8 flag;
u8 pa_bias_flag;
u8 lna_flag;
s8 bb_gain[KFREE_BAND_NUM][MAX_RF_PATH];
s8 tssi_trim[KFREE_BAND_NUM][MAX_RF_PATH];
s8 thermal;
};
@@ -114,6 +208,10 @@ s8 phydm_get_thermal_offset(void *dm_void);
void phydm_clear_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data);
void phydm_config_new_kfree(void *dm_void);
s8 phydm_get_tssi_trim_de(void *dm_void, u8 path);
void phydm_config_kfree(void *dm_void, u8 channel_to_sw);
#endif /*__HALRF_KFREE_H__*/

25
hal/phydm/halrf/halrf_powertracking.c
View File

@@ -150,3 +150,28 @@ void halrf_update_init_rate_work_item_callback(
}
}
#endif
void halrf_set_pwr_track(void *dm_void, u8 enable)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
struct _hal_rf_ *rf = &(dm->rf_table);
struct txpwrtrack_cfg c;
u8 i;
configure_txpower_track(dm, &c);
if (enable) {
rf->rf_supportability = rf->rf_supportability | HAL_RF_TX_PWR_TRACK;
if (cali_info->txpowertrack_control == 1 || cali_info->txpowertrack_control == 3)
halrf_do_tssi(dm);
} else {
rf->rf_supportability = rf->rf_supportability & ~HAL_RF_TX_PWR_TRACK;
odm_clear_txpowertracking_state(dm);
halrf_do_tssi(dm);
halrf_calculate_tssi_codeword(dm);
halrf_set_tssi_codeword(dm);
for (i = 0; i < c.rf_path_count; i++)
(*c.odm_tx_pwr_track_set_pwr)(dm, CLEAN_MODE, i, 0);
}
}

2
hal/phydm/halrf/halrf_powertracking.h
View File

@@ -38,4 +38,6 @@ void halrf_update_init_rate_work_item_callback(
void *context);
#endif
void halrf_set_pwr_track(void *dm_void, u8 enable);
#endif /*#ifndef __HALRF_POWERTRACKING_H__*/

42
hal/phydm/halrf/halrf_powertracking_ap.c
View File

@@ -1120,7 +1120,6 @@ odm_txpowertracking_check(
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _hal_rf_ *rf = &(dm->rf_table);
if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
return;
@@ -1204,16 +1203,41 @@ odm_txpowertracking_check_ap(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
struct rtl8192cd_priv *priv = dm->priv;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _hal_rf_ *rf = &dm->rf_table;
struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
#if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1) || (RTL8198F_SUPPORT == 1))
if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8192F | ODM_RTL8198F))
#if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1) || (RTL8198F_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8812F_SUPPORT == 1))
if (!dm->rf_calibrate_info.tm_trigger) {
if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8192F | ODM_RTL8198F)) {
odm_set_rf_reg(dm, RF_PATH_A, 0x42, (BIT(17) | BIT(16)), 0x3);
} else if (dm->support_ic_type & ODM_RTL8812F) {
odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x00);
odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x00);
odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
} else if (dm->support_ic_type & ODM_RTL8814B) {
odm_set_rf_reg(dm, RF_PATH_A, 0x42, BIT(17), 0x1);
odm_set_rf_reg(dm, RF_PATH_B, 0x42, BIT(17), 0x1);
odm_set_rf_reg(dm, RF_PATH_C, 0x42, BIT(17), 0x1);
odm_set_rf_reg(dm, RF_PATH_D, 0x42, BIT(17), 0x1);
}
if (dm->support_ic_type & ODM_RTL8814B) {
ODM_delay_us(300);
odm_txpowertracking_callback_thermal_meter(dm);
tssi->thermal_trigger = 1;
}
dm->rf_calibrate_info.tm_trigger = 1;
} else {
odm_txpowertracking_callback_thermal_meter(dm);
else
#endif
{
if (dm->support_ic_type & ODM_RTL8814B)
tssi->thermal_trigger = 0;
dm->rf_calibrate_info.tm_trigger = 0;
}
#endif

10
hal/phydm/halrf/halrf_powertracking_ap.h
View File

@@ -79,6 +79,7 @@
#define ODM_OFDM_TABLE_SIZE 37
#define ODM_CCK_TABLE_SIZE 33
#define TXPWR_TRACK_TABLE_SIZE 30
/* <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
extern u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE];
extern u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE];
@@ -139,12 +140,16 @@ struct dm_rf_calibration_struct {
u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
u8 thermal_value;
u8 thermal_value_path[MAX_RF_PATH];
u8 thermal_value_lck;
u8 thermal_value_iqk;
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
u8 thermal_value_avg[AVG_THERMAL_NUM];
u8 thermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM];
u8 thermal_value_avg_index;
u8 thermal_value_avg_index_path[MAX_RF_PATH];
s8 power_index_offset_path[MAX_RF_PATH];
u8 thermal_value_rx_gain;
u8 thermal_value_crystal;
u8 thermal_value_dpk_store;
@@ -161,7 +166,9 @@ struct dm_rf_calibration_struct {
u8 OFDM_index[MAX_RF_PATH];
s8 power_index_offset;
s8 delta_power_index;
s8 delta_power_index_path[MAX_RF_PATH];
s8 delta_power_index_last;
s8 delta_power_index_last_path[MAX_RF_PATH];
boolean is_tx_power_changed;
struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
@@ -213,6 +220,7 @@ struct dm_rf_calibration_struct {
u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
#else
u8 bb_swing_idx_ofdm_base;
u8 bb_swing_idx_ofdm_base_path[MAX_RF_PATH];
#endif
boolean bb_swing_flag_ofdm;
u8 bb_swing_idx_cck;

113
hal/phydm/halrf/halrf_powertracking_ce.c
View File

@@ -605,15 +605,10 @@ u8 get_swing_index(void *dm_void)
if (dm->support_ic_type &
(ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |
ODM_RTL8188F | ODM_RTL8703B | ODM_RTL8723D |
ODM_RTL8710B | ODM_RTL8821)) {
#if (RTL8821A_SUPPORT == 1)
bb_swing =
phy_get_tx_bb_swing_8812a(adapter,
hal_data->current_band_type,
RF_PATH_A);
#else
ODM_RTL8710B)) {
bb_swing = odm_get_bb_reg(dm, R_0xc80, 0xFFC00000);
#endif
for (i = 0; i < OFDM_TABLE_SIZE; i++) {
table_value = ofdm_swing_table_new[i];
@@ -623,7 +618,7 @@ u8 get_swing_index(void *dm_void)
break;
}
} else {
#if (RTL8812A_SUPPORT == 1)
#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
bb_swing =
phy_get_tx_bb_swing_8812a(adapter,
hal_data->current_band_type,
@@ -672,11 +667,13 @@ u8 get_cck_swing_index(void *dm_void)
void odm_txpowertracking_thermal_meter_init(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
struct _hal_rf_ *rf = &dm->rf_table;
struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
u8 swing_idx = get_swing_index(dm);
u8 cckswing_idx = get_cck_swing_index(dm);
u8 p = 0;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
struct _hal_rf_ *rf = &dm->rf_table;
cali_info->is_txpowertracking = true;
cali_info->tx_powercount = 0;
@@ -699,6 +696,24 @@ void odm_txpowertracking_thermal_meter_init(void *dm_void)
cali_info->thermal_value_iqk = rf->eeprom_thermal;
cali_info->thermal_value_lck = rf->eeprom_thermal;
#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8822C) {
cali_info->thermal_value_path[RF_PATH_A] = tssi->thermal[RF_PATH_A];
cali_info->thermal_value_path[RF_PATH_B] = tssi->thermal[RF_PATH_B];
cali_info->thermal_value_iqk = tssi->thermal[RF_PATH_A];
cali_info->thermal_value_lck = tssi->thermal[RF_PATH_A];
}
if (dm->support_ic_type == ODM_RTL8814B) {
cali_info->thermal_value_path[RF_PATH_A] = tssi->thermal[RF_PATH_A];
cali_info->thermal_value_path[RF_PATH_B] = tssi->thermal[RF_PATH_B];
cali_info->thermal_value_path[RF_PATH_C] = tssi->thermal[RF_PATH_C];
cali_info->thermal_value_path[RF_PATH_D] = tssi->thermal[RF_PATH_D];
cali_info->thermal_value_iqk = tssi->thermal[RF_PATH_A];
cali_info->thermal_value_lck = tssi->thermal[RF_PATH_A];
}
#endif
if (!cali_info->default_bb_swing_index_flag) {
if (dm->support_ic_type &
(ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |
@@ -785,11 +800,20 @@ void odm_txpowertracking_check_ce(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _hal_rf_ *rf = &dm->rf_table;
struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
return;
if ((rf->power_track_type & 0xf0) >> 4 != 0) {
if (dm->support_ic_type & ODM_RTL8822C) {
/*halrf_tssi_cck(dm);*/
/*halrf_thermal_cck(dm);*/
return;
}
}
if (!dm->rf_calibrate_info.tm_trigger) {
if (dm->support_ic_type &
(ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8192E |
@@ -799,24 +823,48 @@ void odm_txpowertracking_check_ce(void *dm_void)
ODM_RTL8192F))
odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW,
(BIT(17) | BIT(16)), 0x03);
else
else if (dm->support_ic_type & ODM_RTL8822C) {
odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x00);
odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x00);
odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
} else if (dm->support_ic_type & ODM_RTL8814B) {
odm_set_rf_reg(dm, RF_PATH_A, 0x42, BIT(17), 0x1);
odm_set_rf_reg(dm, RF_PATH_B, 0x42, BIT(17), 0x1);
odm_set_rf_reg(dm, RF_PATH_C, 0x42, BIT(17), 0x1);
odm_set_rf_reg(dm, RF_PATH_D, 0x42, BIT(17), 0x1);
} else
odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_OLD,
RFREGOFFSETMASK, 0x60);
#if (RTL8814B_SUPPORT == 1)
if (dm->support_ic_type & ODM_RTL8814B) {
ODM_delay_us(300);
odm_txpowertracking_new_callback_thermal_meter(dm);
tssi->thermal_trigger = 1;
}
#endif
dm->rf_calibrate_info.tm_trigger = 1;
return;
}
if (dm->support_ic_type &
(ODM_RTL8822C | ODM_RTL8814B))
return;
odm_txpowertracking_callback_thermal_meter(dm);
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B)) {
#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
odm_txpowertracking_new_callback_thermal_meter(dm);
if (dm->support_ic_type & ODM_RTL8814B)
tssi->thermal_trigger = 0;
#endif
} else
odm_txpowertracking_callback_thermal_meter(dm);
dm->rf_calibrate_info.tm_trigger = 0;
#endif
}
void odm_txpowertracking_direct_ce(void *dm_void)
void
odm_txpowertracking_direct_ce(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _hal_rf_ *rf = &dm->rf_table;
@@ -825,22 +873,41 @@ void odm_txpowertracking_direct_ce(void *dm_void)
if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
return;
if (dm->support_ic_type & ODM_RTL8822C) {
/*halrf_tssi_cck(dm);*/
/*halrf_thermal_cck(dm);*/
return;
}
if (dm->support_ic_type &
(ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8192E |
ODM_RTL8723B | ODM_RTL8812 | ODM_RTL8821 |
ODM_RTL8814A | ODM_RTL8703B | ODM_RTL8723D |
ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8710B |
ODM_RTL8192F))
ODM_RTL8192F | ODM_RTL8814B))
odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03);
else
else if (dm->support_ic_type & ODM_RTL8822C) {
odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x00);
odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x00);
odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
} else
odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_OLD, RFREGOFFSETMASK, 0x60);
odm_txpowertracking_callback_thermal_meter(dm);
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B)) {
#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
odm_txpowertracking_new_callback_thermal_meter(dm);
#endif
} else
odm_txpowertracking_callback_thermal_meter(dm);
#endif
}
void odm_txpowertracking_check_mp(void *dm_void)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)

3
hal/phydm/halrf/halrf_powertracking_ce.h
View File

@@ -109,12 +109,15 @@ struct dm_rf_calibration_struct {
/* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
u8 thermal_meter[2];
u8 thermal_value;
u8 thermal_value_path[MAX_RF_PATH];
u8 thermal_value_lck;
u8 thermal_value_iqk;
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
u8 thermal_value_dpk;
u8 thermal_value_avg[AVG_THERMAL_NUM];
u8 thermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM];
u8 thermal_value_avg_index;
u8 thermal_value_avg_index_path[MAX_RF_PATH];
u8 thermal_value_rx_gain;
u8 thermal_value_crystal;
u8 thermal_value_dpk_store;

273
hal/phydm/halrf/halrf_powertracking_iot.c
View File

@@ -515,6 +515,220 @@ u32 cck_swing_table_ch1_ch14_8721d[CCK_TABLE_SIZE_8721D] = {
0x7FF,
};
u32 cck_swing_table_ch1_ch14_8710c[CCK_TABLE_SIZE_8710C] = {
0x0CD, /*0 , -20dB*/
0x0D9,
0x0E6,
0x0F3,
0x102,
0x111,
0x121,
0x132,
0x144,
0x158,
0x16C,
0x182,
0x198,
0x1B1,
0x1CA,
0x1E5,
0x202,
0x221,
0x241,
0x263,
0x287,
0x2AE,
0x2D6,
0x301,
0x32F,
0x35F,
0x392,
0x3C9,
0x402,
0x43F,
0x47F,
0x4C3,
0x50C,
0x558,
0x5A9,
0x5FF,
0x65A,
0x6BA,
0x720,
0x78C,
0x7FF,
};
u32 cck_swing_table_03db_ch1_ch14_8710c[CCK_03DB_TABLE_SIZE_8710C] = {
0x143, /*0 , -4dB*/
0x14C, /*1 , -3.75dB*/
0x156, /*2 , -3.5dB*/
0x160,
0x16A,
0x175,
0x17F,
0x18B,
0x196,
0x1A2,
0x1AE,
0x1BB,
0x1C8,
0x1D5,
0x1E3,
0x1F1,
0x200,
0x20F,
0x21E,
0x22F,
0x23F,
0x250,
0x261,
0x273,
0x285,
0x298,
0x2AB,
0x2BF,
0x2D6,
0x2E9,
0x2FF,
0x315,
0x32C,
0x344,
0x35C,
0x375,
0x390,
0x3AA,
0x3C5,
0x3E1,
0x402, /*40 , +6dB default*/
0x41C,
0x43B,
0x45A,
0x47C,
0x49C,
0x4BF,
0x4E2,
0x510,
0x52C,
0x553,
0x57B,
0x5A5,
0x5CE,
0x5F9,
0x626,
0x655,
0x683,
0x6B5,
0x6E6,
0x71E,
0x74E,
0x786,
0x7BD,
0x7F9,
0x832,
0x871,
0x8AF,
0x8F2,
0x932,
0x977,
0x9BE,
0xA0E,
0xA52,
0xAA1,
0xAEE,
0xB54,
0xB95,
0xBEB,
0xC43,
0xCA3 /*80 , +16dB*/
};
u32 ofdm_swing_table_03DB_8710c[OFDM_03DB_TABLE_SIZE_8710C] = {
0xE4, /*0 , -7dB*/
0xEB, /*1 , -6.75dB*/
0xF2, /*2 , -6.5dB*/
0xF9,
0x100,
0x108,
0x110,
0x118,
0x11F,
0x128,
0x131,
0x13A,
0x143,
0x14C,
0x156,
0x160,
0x16A,
0x175,
0x180,
0x18B,
0x196,
0x1A2,
0x1AE,
0x1BB,
0x1C8,
0x1D5,
0x1E3,
0x1F1,
0x200,
0x20F,
0x21F,
0x22F,
0x23F,
0x250,
0x261,
0x273,
0x286,
0x298,
0x2AB,
0x2BF,
0x2D6, /*40 , +3dB default*/
0x2E9,
0x2FF,
0x315,
0x32C,
0x344,
0x35C,
0x375,
0x390,
0x3AA,
0x3C5,
0x3E1,
0x3FF,
0x41C,
0x43B,
0x45A,
0x47B,
0x49C,
0x4BF,
0x4E2,
0x507,
0x52C,
0x553,
0x57B,
0x5A4,
0x5CE,
0x5F9,
0x626,
0x654,
0x683,
0x6B4,
0x6E6,
0x71B,
0x74E,
0x785,
0x7BD,
0x7F7,
0x832,
0x870,
0x8AF,
0x8F0 /*80 , +13dB*/
};
u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
0x081, /* 0, -12.0dB*/
0x088, /* 1, -11.5dB*/
@@ -570,25 +784,35 @@ get_swing_index(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i = 0;
u32 bb_swing;
u32 swing_table_size;
u32 *swing_table;
u8 i = 0;
u32 bb_swing;
u32 swing_table_size;
u32 *swing_table;
u32 table_value;
if (dm->support_ic_type == ODM_RTL8710C) {
bb_swing = odm_get_bb_reg(dm, R_0xcc8, 0x000007ff);
for (i = 0; i < OFDM_03DB_TABLE_SIZE_8710C; i++) {
if (bb_swing == ofdm_swing_table_03DB_8710c[i])
break;
}
}
if (dm->support_ic_type == ODM_RTL8195B) {
bb_swing = odm_get_bb_reg(dm, R_0xc1c, 0xFFE00000);
swing_table = tx_scaling_table_jaguar;
swing_table_size = TXSCALE_TABLE_SIZE;
}
for (i = 0; i < swing_table_size; i++) {
u32 table_value = swing_table[i];
for (i = 0; i < swing_table_size; i++) {
table_value = swing_table[i];
table_value = table_value;
if (bb_swing == table_value)
break;
table_value = table_value;
if (bb_swing == table_value)
break;
}
}
return i;
@@ -599,10 +823,10 @@ get_cck_swing_index(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i = 0;
u32 bb_cck_swing;
u8 i = 0;
u32 bb_cck_swing;
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
dm->support_ic_type == ODM_RTL8192E) {
@@ -619,6 +843,16 @@ get_cck_swing_index(
if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
break;
}
} else if (dm->support_ic_type == ODM_RTL8710C) {
bb_cck_swing = odm_get_bb_reg(dm, R_0xab4, 0x7ff);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"bb_cck_swing = 0x%x\n", bb_cck_swing);
for (i = 0; i < CCK_03DB_TABLE_SIZE_8710C; i++) {
if (bb_cck_swing == cck_swing_table_03db_ch1_ch14_8710c[i])
break;
}
}
return i;
@@ -630,7 +864,7 @@ odm_txpowertracking_thermal_meter_init(
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 default_swing_index = get_swing_index(dm);
u8 default_swing_index;
u8 p = 0;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
struct _hal_rf_ *rf = &dm->rf_table;
@@ -649,11 +883,15 @@ odm_txpowertracking_thermal_meter_init(
if (!cali_info->default_bb_swing_index_flag) {
if (dm->support_ic_type == ODM_RTL8195B) {
default_swing_index = get_swing_index(dm);
cali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
cali_info->default_cck_index = 24;
} else if (dm->support_ic_type == ODM_RTL8721D) {
cali_info->default_ofdm_index = 30; /*OFDM: 0dB*/
cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
cali_info->default_cck_index = 28; /*CCK: -6dB*/
} else if (dm->support_ic_type == ODM_RTL8710C) {
cali_info->default_ofdm_index = get_swing_index(dm);
cali_info->default_cck_index = get_cck_swing_index(dm);
}
cali_info->default_bb_swing_index_flag = true;
}
@@ -697,7 +935,8 @@ odm_txpowertracking_check_iot(
if (!dm->rf_calibrate_info.tm_trigger) {
if (dm->support_ic_type == ODM_RTL8195B)
odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03);
else if (dm->support_ic_type == ODM_RTL8721D)
else if (dm->support_ic_type == ODM_RTL8721D ||
dm->support_ic_type == ODM_RTL8710C)
odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW,
(BIT(12) | BIT(11)), 0x03);

22
hal/phydm/halrf/halrf_powertracking_iot.h
View File

@@ -37,6 +37,9 @@
#define CCK_TABLE_SIZE_8710B 41
#define CCK_TABLE_SIZE_8192F 41
#define CCK_TABLE_SIZE_8721D 41
#define CCK_TABLE_SIZE_8710C 41
#define CCK_03DB_TABLE_SIZE_8710C 81
#define OFDM_03DB_TABLE_SIZE_8710C 81
#define TXPWR_TRACK_TABLE_SIZE 30
@@ -74,6 +77,9 @@ extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
extern u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
extern u32 cck_swing_table_ch1_ch14_8721d[CCK_TABLE_SIZE_8721D];
extern u32 cck_swing_table_ch1_ch14_8710c[CCK_TABLE_SIZE_8710C];
extern u32 cck_swing_table_03db_ch1_ch14_8710c[CCK_03DB_TABLE_SIZE_8710C];
extern u32 ofdm_swing_table_03DB_8710c[OFDM_03DB_TABLE_SIZE_8710C];
extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
@@ -143,33 +149,46 @@ struct dm_rf_calibration_struct {
s8 xtal_offset;
s8 xtal_offset_last;
#if (RTL8710B_SUPPORT == 1 || RTL8721D_SUPPORT == 1)
struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
#endif
u8 delta_lck;
s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
#endif
u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
#endif
#if (RTL8195B_SUPPORT == 1)
u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
#endif
#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
#endif
#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
@@ -182,6 +201,7 @@ struct dm_rf_calibration_struct {
u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
#endif
s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
@@ -240,12 +260,14 @@ struct dm_rf_calibration_struct {
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
u32 IQK_BB_backup_recover[9];
u32 IQK_BB_backup[IQK_BB_REG_NUM];
#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
u32 tx_iqc_8723d[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8723d[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
#endif
/* JJ ADD 20161014 */
u32 tx_iqc_8710b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8710b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/

62
hal/phydm/halrf/halrf_powertracking_win.c
View File

@@ -598,6 +598,8 @@ odm_txpowertracking_thermal_meter_init(
u8 default_swing_index = get_swing_index(dm);
u8 default_cck_swing_index = get_cck_swing_index(dm);
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
struct _hal_rf_ *rf = &dm->rf_table;
struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter = dm->adapter;
@@ -656,10 +658,28 @@ odm_txpowertracking_thermal_meter_init(
cali_info->txpowertrack_control = true;
#endif
cali_info->thermal_value = hal_data->eeprom_thermal_meter;
cali_info->thermal_value = hal_data->eeprom_thermal_meter;
cali_info->thermal_value_iqk = hal_data->eeprom_thermal_meter;
cali_info->thermal_value_lck = hal_data->eeprom_thermal_meter;
#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8822C) {
cali_info->thermal_value_path[RF_PATH_A] = tssi->thermal[RF_PATH_A];
cali_info->thermal_value_path[RF_PATH_B] = tssi->thermal[RF_PATH_B];
cali_info->thermal_value_iqk = tssi->thermal[RF_PATH_A];
cali_info->thermal_value_lck = tssi->thermal[RF_PATH_A];
}
if (dm->support_ic_type == ODM_RTL8814B) {
cali_info->thermal_value_path[RF_PATH_A] = tssi->thermal[RF_PATH_A];
cali_info->thermal_value_path[RF_PATH_B] = tssi->thermal[RF_PATH_B];
cali_info->thermal_value_path[RF_PATH_C] = tssi->thermal[RF_PATH_C];
cali_info->thermal_value_path[RF_PATH_D] = tssi->thermal[RF_PATH_D];
cali_info->thermal_value_iqk = tssi->thermal[RF_PATH_A];
cali_info->thermal_value_lck = tssi->thermal[RF_PATH_A];
}
#endif
if (cali_info->default_bb_swing_index_flag != true) {
/*The index of "0 dB" in SwingTable.*/
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
@@ -818,7 +838,12 @@ odm_txpowertracking_direct_call(
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
odm_txpowertracking_callback_thermal_meter(adapter);
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B)) {
#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
odm_txpowertracking_new_callback_thermal_meter(dm);
#endif
} else
odm_txpowertracking_callback_thermal_meter(adapter);
}
void
@@ -830,6 +855,7 @@ odm_txpowertracking_thermal_meter_check(
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &(pHalData->DM_OutSrc);
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) {
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
@@ -840,20 +866,42 @@ odm_txpowertracking_thermal_meter_check(
if (!tm_trigger) {
if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8192E(adapter) || IS_HARDWARE_TYPE_8192F(adapter)
||IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8814A(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8703B(adapter)
|| IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8821C(adapter) || IS_HARDWARE_TYPE_8710B(adapter))/* JJ ADD 20161014 */
|| IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8821C(adapter) || IS_HARDWARE_TYPE_8710B(adapter)
)/* JJ ADD 20161014 */
PHY_SetRFReg(adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
else
else if (IS_HARDWARE_TYPE_8822C(adapter)) {
odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x00);
odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x00);
odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
} else if (IS_HARDWARE_TYPE_8814B(adapter)) {
odm_set_rf_reg(dm, RF_PATH_A, 0x42, BIT(17), 0x1);
odm_set_rf_reg(dm, RF_PATH_B, 0x42, BIT(17), 0x1);
odm_set_rf_reg(dm, RF_PATH_C, 0x42, BIT(17), 0x1);
odm_set_rf_reg(dm, RF_PATH_D, 0x42, BIT(17), 0x1);
} else
PHY_SetRFReg(adapter, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
if (dm->support_ic_type & ODM_RTL8814B) {
ODM_delay_us(300);
odm_txpowertracking_direct_call(adapter);
tssi->thermal_trigger = 1;
}
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Trigger Thermal Meter!!\n"));
tm_trigger = 1;
return;
} else if (IS_HARDWARE_TYPE_8822C(adapter) || IS_HARDWARE_TYPE_8814B(adapter))
return;
else {
} else {
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Schedule TxPowerTracking direct call!!\n"));
odm_txpowertracking_direct_call(adapter);
if (dm->support_ic_type & ODM_RTL8814B)
tssi->thermal_trigger = 0;
tm_trigger = 0;
}
}

7
hal/phydm/halrf/halrf_powertracking_win.h
View File

@@ -130,12 +130,15 @@ struct dm_rf_calibration_struct {
u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
u8 thermal_value;
u8 thermal_value_path[MAX_RF_PATH];
u8 thermal_value_lck;
u8 thermal_value_iqk;
u8 thermal_value_dpk;
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
u8 thermal_value_dpk;
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
u8 thermal_value_avg[AVG_THERMAL_NUM];
u8 thermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM];
u8 thermal_value_avg_index;
u8 thermal_value_avg_index_path[MAX_RF_PATH];
u8 thermal_value_rx_gain;

199
hal/phydm/halrf/halrf_psd.c
View File

@@ -20,15 +20,13 @@
#include "mp_precomp.h"
#include "phydm_precomp.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
u64 _sqrt(u64 x)
{
u64 i = 0;
u64 j = x / 2 + 1;
u64 j = (x >> 1) + 1;
while (i <= j) {
u64 mid = (i + j) / 2;
u64 mid = (i + j) >> 1;
u64 sq = mid * mid;
@@ -49,7 +47,7 @@ u32 halrf_get_psd_data(
{
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
u32 psd_val = 0, psd_reg, psd_report, psd_point, psd_start, i, delay_time;
u32 psd_val = 0, psd_reg, psd_report, psd_point, psd_start, i, delay_time = 0;
#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) {
@@ -128,10 +126,10 @@ void halrf_psd(
mode = average >> 16;
if (mode == 1)
average_tmp = average & 0xffff;
else if (mode == 2)
if (mode == 2)
average_tmp = 1;
else
average_tmp = average & 0xffff;
if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
psd_reg = R_0x910;
@@ -193,7 +191,7 @@ void halrf_psd(
/*dbg_print("\n");*/
#endif
data_tatal = ((data_tatal * 100) / average_tmp);
data_tatal = phydm_division64((data_tatal * 100), average_tmp);
psd->psd_data[j] = (u32)_sqrt(data_tatal);
i++;
@@ -216,22 +214,75 @@ void halrf_psd(
odm_set_bb_reg(dm, psd_reg, 0x3000, avg_org);
}
void backup_bb_register(struct dm_struct *dm, u32 *bb_backup, u32 *backup_bb_reg, u32 counter)
{
u32 i ;
for (i = 0; i < counter; i++)
bb_backup[i] = odm_get_bb_reg(dm, backup_bb_reg[i], MASKDWORD);
}
void restore_bb_register(struct dm_struct *dm, u32 *bb_backup, u32 *backup_bb_reg, u32 counter)
{
u32 i ;
for (i = 0; i < counter; i++)
odm_set_bb_reg(dm, backup_bb_reg[i], MASKDWORD, bb_backup[i]);
}
void _halrf_psd_iqk_init(struct dm_struct *dm)
{
odm_set_bb_reg(dm, 0x1b04, MASKDWORD, 0x0);
odm_set_bb_reg(dm, 0x1b08, MASKDWORD, 0x80);
odm_set_bb_reg(dm, 0x1b0c, 0xc00, 0x3);
odm_set_bb_reg(dm, 0x1b14, MASKDWORD, 0x0);
odm_set_bb_reg(dm, 0x1b18, BIT(0), 0x1);
if (dm->support_ic_type & ODM_RTL8197G)
odm_set_bb_reg(dm, 0x1b20, MASKDWORD, 0x00040008);
if (dm->support_ic_type & ODM_RTL8198F)
odm_set_bb_reg(dm, 0x1b20, MASKDWORD, 0x00000000);
if (dm->support_ic_type & (ODM_RTL8197G | ODM_RTL8198F)) {
odm_set_bb_reg(dm, 0x1b24, MASKDWORD, 0x00030000);
odm_set_bb_reg(dm, 0x1b28, MASKDWORD, 0x00000000);
odm_set_bb_reg(dm, 0x1b2c, MASKDWORD, 0x00180018);
odm_set_bb_reg(dm, 0x1b30, MASKDWORD, 0x20000000);
/*odm_set_bb_reg(dm, 0x1b38, MASKDWORD, 0x20000000);*/
/*odm_set_bb_reg(dm, 0x1b3c, MASKDWORD, 0x20000000);*/
}
odm_set_bb_reg(dm, 0x1b1c, 0xfff, 0xd21);
odm_set_bb_reg(dm, 0x1b1c, 0xfff00000, 0x821);
odm_set_bb_reg(dm, 0x1b28, MASKDWORD, 0x0);
odm_set_bb_reg(dm, 0x1bcc, 0x3f, 0x3f);
}
u32 halrf_get_iqk_psd_data(
struct dm_struct *dm,
u32 point)
{
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
u32 psd_val, psd_val1, psd_val2, psd_point, i, delay_time;
u32 psd_val, psd_val1, psd_val2, psd_point, i, delay_time = 0;
#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) {
delay_time = 0;
if (dm->support_ic_type & ODM_RTL8822C)
delay_time = 1000;
else
delay_time = 0;
}
#endif
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
if (dm->support_interface == ODM_ITRF_PCIE) {
delay_time = 150;
if (dm->support_ic_type & ODM_RTL8822C)
delay_time = 1000;
else
delay_time = 150;
}
#endif
psd_point = odm_get_bb_reg(dm, R_0x1b2c, MASKDWORD);
@@ -244,24 +295,44 @@ u32 halrf_get_iqk_psd_data(
odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, psd_point);
odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x1);
odm_set_bb_reg(dm, R_0x1b34, BIT(0), 0x1);
odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x0);
odm_set_bb_reg(dm, R_0x1b34, BIT(0), 0x0);
for (i = 0; i < delay_time; i++)
ODM_delay_us(1);
odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00250001);
if (dm->support_ic_type & (ODM_RTL8197G | ODM_RTL8198F)) {
if (dm->support_ic_type & ODM_RTL8197G)
odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x001a0001);
else
odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00250001);
psd_val1 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
psd_val1 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
psd_val1 = (psd_val1 & 0x07FF0000) >> 16;
psd_val1 = (psd_val1 & 0x001f0000) >> 16;
odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x002e0001);
if (dm->support_ic_type & ODM_RTL8197G)
odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x001b0001);
else
odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x002e0001);
psd_val2 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
psd_val2 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
psd_val = (psd_val1 << 21) + (psd_val2 >> 11);
psd_val = (psd_val1 << 27) + (psd_val2 >> 5);
} else {
odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00250001);
psd_val1 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
psd_val1 = (psd_val1 & 0x07FF0000) >> 16;
odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x002e0001);
psd_val2 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
psd_val = (psd_val1 << 21) + (psd_val2 >> 11);
}
return psd_val;
}
@@ -277,22 +348,42 @@ void halrf_iqk_psd(
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
u32 i = 0, j = 0, k = 0;
u32 psd_reg, avg_org, point_temp, average_tmp, mode;
u32 psd_reg, avg_org, point_temp, average_tmp = 32, mode, reg_tmp = 5;
u64 data_tatal = 0, data_temp[64] = {0};
s32 point_8814B;
s32 s_point_tmp;
psd->buf_size = 256;
mode = average >> 16;
if (mode == 1)
average_tmp = average & 0xffff;
else if (mode == 2) {
if (dm->support_ic_type & ODM_RTL8814B)
average_tmp = average & 0xffff;
else
if (mode == 2) {
if (dm->support_ic_type & ODM_RTL8822C)
average_tmp = 1;
else {
reg_tmp = odm_get_bb_reg(dm, R_0x1b1c, 0x000e0000);
if (reg_tmp == 0)
average_tmp = 1;
else if (reg_tmp == 3)
average_tmp = 8;
else if (reg_tmp == 4)
average_tmp = 16;
else if (reg_tmp == 5)
average_tmp = 32;
odm_set_bb_reg(dm, R_0x1b1c, 0x000e0000, 0x0);
}
} else {
reg_tmp = odm_get_bb_reg(dm, R_0x1b1c, 0x000e0000);
if (reg_tmp == 0)
average_tmp = 1;
else if (reg_tmp == 3)
average_tmp = 8;
else if (reg_tmp == 4)
average_tmp = 16;
else if (reg_tmp == 5)
average_tmp = 32;
odm_set_bb_reg(dm, R_0x1b1c, 0x000e0000, 0x0);
}
#if 0
DbgPrint("[PSD]point=%d, start_point=%d, stop_point=%d, average=0x%x, average_tmp=%d, buf_size=%d, mode=%d\n",
point, start_point, stop_point, average, average_tmp, psd->buf_size, mode);
@@ -311,8 +402,8 @@ void halrf_iqk_psd(
{
if (dm->support_ic_type & ODM_RTL8814B)
{
point_8814B = i -point -1;
point_temp = point_8814B & 0xfff;
s_point_tmp = i - point - 1;
point_temp = s_point_tmp & 0xfff;
}
else
point_temp = i;
@@ -331,15 +422,16 @@ void halrf_iqk_psd(
#endif
}
/*data_tatal = ((data_tatal * 100) / average_tmp);*/
/*psd->psd_data[j] = (u32)_sqrt(data_tatal);*/
psd->psd_data[j] = (u32)((data_tatal * 10) / average_tmp);
data_tatal = phydm_division64((data_tatal * 10), average_tmp);
psd->psd_data[j] = (u32)data_tatal;
i++;
j++;
}
if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8198F | ODM_RTL8197G))
odm_set_bb_reg(dm, R_0x1b1c, 0x000e0000, reg_tmp);
#if 0
DbgPrint("\n [iqk psd]psd result:\n");
@@ -354,49 +446,61 @@ void halrf_iqk_psd(
}
enum rt_status
u32
halrf_psd_init(
struct dm_struct *dm)
void *dm_void)
{
enum rt_status ret_status = RT_STATUS_SUCCESS;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
#if 0
u32 bb_backup[12];
u32 backup_bb_reg[12] = {0x1b04, 0x1b08, 0x1b0c, 0x1b14, 0x1b18,
0x1b1c, 0x1b28, 0x1bcc, 0x1b2c, 0x1b34,
0x1bd4, 0x1bfc};
#endif
if (psd->psd_progress) {
ret_status = RT_STATUS_PENDING;
} else {
psd->psd_progress = 1;
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B))
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8198F | ODM_RTL8197G)) {
/*backup_bb_register(dm, bb_backup, backup_bb_reg, 12);*/
_halrf_psd_iqk_init(dm);
halrf_iqk_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
else
/*restore_bb_register(dm, bb_backup, backup_bb_reg, 12);*/
} else
halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
psd->psd_progress = 0;
}
return ret_status;
}
enum rt_status
u32
halrf_psd_query(
struct dm_struct *dm,
void *dm_void,
u32 *outbuf,
u32 buf_size)
{
enum rt_status ret_status = RT_STATUS_SUCCESS;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
if (psd->psd_progress)
ret_status = RT_STATUS_PENDING;
else
PlatformMoveMemory(outbuf, psd->psd_data, 0x400);
odm_move_memory(dm, outbuf, psd->psd_data,
sizeof(u32) * psd->buf_size);
return ret_status;
}
enum rt_status
u32
halrf_psd_init_query(
struct dm_struct *dm,
void *dm_void,
u32 *outbuf,
u32 point,
u32 start_point,
@@ -405,6 +509,7 @@ halrf_psd_init_query(
u32 buf_size)
{
enum rt_status ret_status = RT_STATUS_SUCCESS;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
@@ -418,11 +523,9 @@ halrf_psd_init_query(
} else {
psd->psd_progress = 1;
halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
PlatformMoveMemory(outbuf, psd->psd_data, 0x400);
odm_move_memory(dm, outbuf, psd->psd_data, 0x400);
psd->psd_progress = 0;
}
return ret_status;
}
#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/

14
hal/phydm/halrf/halrf_psd.h
View File

@@ -16,7 +16,6 @@
#ifndef __HALRF_PSD_H__
#define __HALRF_PSD_H__
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
struct _halrf_psd_data {
u32 point;
@@ -28,19 +27,19 @@ struct _halrf_psd_data {
u32 psd_progress;
};
enum rt_status
u32
halrf_psd_init(
struct dm_struct *dm);
void *dm_void);
enum rt_status
u32
halrf_psd_query(
struct dm_struct *dm,
void *dm_void,
u32 *outbuf,
u32 buf_size);
enum rt_status
u32
halrf_psd_init_query(
struct dm_struct *dm,
void *dm_void,
u32 *outbuf,
u32 point,
u32 start_point,
@@ -48,5 +47,4 @@ halrf_psd_init_query(
u32 average,
u32 buf_size);
#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/
#endif /*#__HALRF_PSD_H__*/

1746
hal/phydm/rtl8822b/halhwimg8822b_rf.c → hal/phydm/halrf/rtl8822b/halhwimg8822b_rf.c
View File

File diff suppressed because it is too large Load Diff

26
hal/phydm/rtl8822b/halhwimg8822b_rf.h → hal/phydm/halrf/rtl8822b/halhwimg8822b_rf.h
View File

@@ -23,7 +23,7 @@
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.5.3*/
/*Image2HeaderVersion: R3 1.5.10*/
#if (RTL8822B_SUPPORT == 1)
#ifndef __INC_MP_RF_HW_IMG_8822B_H
#define __INC_MP_RF_HW_IMG_8822B_H
@@ -42,6 +42,7 @@
* #define CONFIG_8822B_TYPE16_DRV_DIS
* #define CONFIG_8822B_TYPE17_DRV_DIS
* #define CONFIG_8822B_TYPE18_DRV_DIS
* #define CONFIG_8822B_TYPE19_DRV_DIS
* #define CONFIG_8822B_TYPE2_DRV_DIS
* #define CONFIG_8822B_TYPE3_TYPE5_DRV_DIS
* #define CONFIG_8822B_TYPE4_DRV_DIS
@@ -113,6 +114,11 @@
#undef CONFIG_8822B_TYPE18
#endif
#define CONFIG_8822B_TYPE19
#ifdef CONFIG_8822B_TYPE19_DRV_DIS
#undef CONFIG_8822B_TYPE19
#endif
#define CONFIG_8822B_TYPE2
#ifdef CONFIG_8822B_TYPE2_DRV_DIS
#undef CONFIG_8822B_TYPE2
@@ -284,6 +290,15 @@ void
odm_read_and_config_mp_8822b_txpowertrack_type18(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type18(void);
/******************************************************************************
* txpowertrack_type19.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpowertrack_type19(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpowertrack_type19(void);
/******************************************************************************
* txpowertrack_type2.TXT
******************************************************************************/
@@ -401,6 +416,15 @@ void
odm_read_and_config_mp_8822b_txpwr_lmt_type18(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type18(void);
/******************************************************************************
* txpwr_lmt_type19.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type19(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_txpwr_lmt_type19(void);
/******************************************************************************
* txpwr_lmt_type2.TXT
******************************************************************************/

21
hal/phydm/halrf/rtl8822b/halrf_8822b.c
View File

@@ -424,18 +424,17 @@ void get_delta_swing_table_8822b(void *dm_void,
void aac_check_8822b(struct dm_struct *dm)
{
struct _hal_rf_ *rf = &dm->rf_table;
u32 temp;
static boolean firstrun = true;
if (firstrun) {
if (!rf->aac_checked) {
RF_DBG(dm, DBG_RF_LCK, "[LCK]AAC check for 8822b\n");
temp = odm_get_rf_reg(dm, RF_PATH_A, 0xc9, 0xf8);
if (temp < 4 || temp > 7) {
odm_set_rf_reg(dm, RF_PATH_A, 0xca, BIT(19), 0x0);
odm_set_rf_reg(dm, RF_PATH_A, 0xb2, 0x7c000, 0x6);
}
firstrun = false;
rf->aac_checked = true;
}
}
@@ -538,16 +537,18 @@ void phy_set_rf_path_switch_8822b(void *adapter, boolean is_main)
odm_set_bb_reg(dm, R_0x1704, MASKDWORD, 0x0000ff00);
odm_set_bb_reg(dm, R_0x1700, MASKDWORD, 0xc00f0038);
if (is_main) {
if (dm->rfe_type != 0x12) {
if (is_main) {
#if 0
/*odm_set_bb_reg(dm, R_0xcbd, 0x3, 0x2); WiFi*/
/*odm_set_bb_reg(dm, R_0xcbd, 0x3, 0x2); WiFi*/
#endif
odm_set_bb_reg(dm, R_0xcbc, (BIT(9) | BIT(8)), 0x2); /*WiFi*/
} else {
odm_set_bb_reg(dm, R_0xcbc, (BIT(9) | BIT(8)), 0x2); /*WiFi*/
} else {
#if 0
/*odm_set_bb_reg(dm, R_0xcbd, 0x3, 0x1); BT*/
/*odm_set_bb_reg(dm, R_0xcbd, 0x3, 0x1); BT*/
#endif
odm_set_bb_reg(dm, R_0xcbc, (BIT(9) | BIT(8)), 0x1); /*BT*/
odm_set_bb_reg(dm, R_0xcbc, (BIT(9) | BIT(8)), 0x1); /*BT*/
}
}
}

305
hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c
View File

@@ -80,6 +80,59 @@ void do_iqk_8822b(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
}
#endif
u32 _iqk_ltec_read_8822b(struct dm_struct *dm, u16 reg_addr)
{
u32 j = 0;
/*wait for ready bit before access 0x1700*/
odm_write_4byte(dm, 0x1700, 0x800f0000 | reg_addr);
do {
j++;
} while (((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) && (j < 30000));
return odm_read_4byte(dm, 0x1708); /*get read data*/
}
void _iqk_ltec_write_8822b(struct dm_struct *dm, u16 reg_addr, u32 bit_mask,
u32 reg_value)
{
u32 val, i = 0, j = 0, bitpos = 0;
if (bit_mask == 0x0)
return;
if (bit_mask == 0xffffffff) {
odm_write_4byte(dm, 0x1704, reg_value); /*put write data*/
/*wait for ready bit before access 0x1700*/
do {
j++;
} while (((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) && (j < 30000));
odm_write_4byte(dm, 0x1700, 0xc00f0000 | reg_addr);
} else {
for (i = 0; i <= 31; i++) {
if (((bit_mask >> i) & 0x1) == 0x1) {
bitpos = i;
break;
}
}
/*read back register value before write*/
val = _iqk_ltec_read_8822b(dm, reg_addr);
val = (val & (~bit_mask)) | (reg_value << bitpos);
odm_write_4byte(dm, 0x1704, val); /*put write data*/
/*wait for ready bit before access 0x1700*/
do {
j++;
} while (((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) && (j < 30000));
odm_write_4byte(dm, 0x1700, 0xc00f0000 | reg_addr);
}
}
void _iqk_rf_set_check_8822b(struct dm_struct *dm, u8 path, u16 add, u32 data)
{
u32 i;
@@ -103,6 +156,19 @@ void _iqk_rf0xb0_workaround_8822b(struct dm_struct *dm)
odm_set_rf_reg(dm, (enum rf_path)0x0, RF_0xb8, MASK20BITS, 0x80a00);
}
void _iqk_0xc94_workaround_8822b(struct dm_struct *dm)
{
if (odm_get_bb_reg(dm, R_0xc94, BIT(0)) == 0x1) {
odm_set_bb_reg(dm, R_0xc94, BIT(0), 0x0);
odm_set_bb_reg(dm, R_0xc94, BIT(0), 0x1);
}
if (odm_get_bb_reg(dm, R_0xe94, BIT(0)) == 0x1) {
odm_set_bb_reg(dm, R_0xe94, BIT(0), 0x0);
odm_set_bb_reg(dm, R_0xe94, BIT(0), 0x1);
}
}
void _iqk_fill_iqk_report_8822b(void *dm_void, u8 ch)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
@@ -280,12 +346,6 @@ void _iqk_afe_setting_8822b(struct dm_struct *dm, boolean do_iqk)
odm_write_4byte(dm, 0xc60, 0x70038040);
odm_write_4byte(dm, 0xe60, 0x50000000);
odm_write_4byte(dm, 0xe60, 0x70038040);
odm_write_4byte(dm, 0xc58, 0xd8020402);
odm_write_4byte(dm, 0xc5c, 0xde000120);
odm_write_4byte(dm, 0xc6c, 0x0000122a);
odm_write_4byte(dm, 0xe58, 0xd8020402);
odm_write_4byte(dm, 0xe5c, 0xde000120);
odm_write_4byte(dm, 0xe6c, 0x0000122a);
#if 0
/* RF_DBG(dm, DBG_RF_IQK, "[IQK]AFE setting for Normal mode!!!!\n"); */
#endif
@@ -801,10 +861,12 @@ _iqk_rxk_gsearch_fail_8822b(struct dm_struct *dm, u8 path, u8 step)
IQK_CMD = 0xf8000208 | (1 << (path + 4));
RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d GS%d_Trigger = 0x%x\n", path,
step, IQK_CMD);
_iqk_ltec_write_8822b(dm, 0x38, 0xffff,0x7700);
odm_write_4byte(dm, 0x1b00, IQK_CMD);
odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
ODM_delay_ms(GS_delay_8822B);
fail = _iqk_check_cal_8822b(dm, path, 0x1);
_iqk_ltec_write_8822b(dm, 0x38, MASKDWORD, iqk->tmp_gntwl);
} else if (step == RXIQK2) {
for (idx = 0; idx < 4; idx++) {
if (iqk->tmp1bcc == IQMUX[idx])
@@ -816,10 +878,13 @@ _iqk_rxk_gsearch_fail_8822b(struct dm_struct *dm, u8 path, u8 step)
IQK_CMD = 0xf8000308 | (1 << (path + 4));
RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d GS%d_Trigger = 0x%x\n", path,
step, IQK_CMD);
_iqk_ltec_write_8822b(dm, 0x38, 0xffff,0x7700);
odm_write_4byte(dm, 0x1b00, IQK_CMD);
odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
ODM_delay_ms(GS_delay_8822B);
fail = _iqk_check_cal_8822b(dm, path, 0x1);
_iqk_ltec_write_8822b(dm, 0x38, MASKDWORD, iqk->tmp_gntwl);
rf_reg0 = odm_get_rf_reg(dm, (enum rf_path)path,
RF_0x0, MASK20BITS);
@@ -879,12 +944,16 @@ _lok_one_shot_8822b(void *dm_void, u8 path)
RF_DBG(dm, DBG_RF_IQK, "[IQK]==========S%d LOK ==========\n", path);
IQK_CMD = 0xf8000008 | (1 << (4 + path));
RF_DBG(dm, DBG_RF_IQK, "[IQK]LOK_Trigger = 0x%x\n", IQK_CMD);
_iqk_ltec_write_8822b(dm, 0x38, 0xffff,0x7700);
odm_write_4byte(dm, 0x1b00, IQK_CMD);
odm_write_4byte(dm, 0x1b00, IQK_CMD + 1);
/*LOK: CMD ID = 0 {0xf8000018, 0xf8000028}*/
/*LOK: CMD ID = 0 {0xf8000019, 0xf8000029}*/
ODM_delay_ms(LOK_delay_8822B);
LOK_notready = _iqk_check_cal_8822b(dm, path, 0x0);
_iqk_ltec_write_8822b(dm, 0x38, MASKDWORD, iqk->tmp_gntwl);
if (!LOK_notready)
_iqk_backup_iqk_8822b(dm, 0x1, path);
if (DBG_RF_IQK) {
@@ -951,10 +1020,12 @@ _iqk_one_shot_8822b(void *dm_void, u8 path, u8 idx)
((iqk->lna_idx & 0x7) << 10);
odm_write_4byte(dm, 0x1b24, tmp);
}
_iqk_ltec_write_8822b(dm, 0x38, 0xffff,0x7700);
odm_write_4byte(dm, 0x1b00, IQK_CMD);
odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
ODM_delay_ms(WBIQK_delay_8822B);
fail = _iqk_check_cal_8822b(dm, path, 0x1);
_iqk_ltec_write_8822b(dm, 0x38, MASKDWORD, iqk->tmp_gntwl);
if (dm->debug_components & DBG_RF_IQK) {
odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
@@ -1722,9 +1793,12 @@ void _phy_iq_calibrate_8822b(struct dm_struct *dm, boolean reset,
u32 MAC_backup[MAC_REG_NUM_8822B], BB_backup[BB_REG_NUM_8822B];
u32 RF_backup[RF_REG_NUM_8822B][SS_8822B];
u32 backup_mac_reg[MAC_REG_NUM_8822B] = {0x520, 0x550};
u32 backup_bb_reg[BB_REG_NUM_8822B] = {
0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0xe00, 0xeb0, 0xeb4,
0xebc, 0x1990, 0x9a4, 0xa04, 0xb00, 0x838};
u32 backup_bb_reg[BB_REG_NUM_8822B] = {0x808, 0x90c, 0xc00, 0xcb0,
0xcb4, 0xcbc, 0xe00, 0xeb0,
0xeb4, 0xebc, 0x1990, 0x9a4,
0xa04, 0xb00, 0x838, 0xc58,
0xc5c, 0xc6c, 0xe58, 0xe5c,
0xe6c};
u32 backup_rf_reg[RF_REG_NUM_8822B] = {0xdf, 0x8f, 0x65, 0x0, 0x1};
boolean is_mp = false;
@@ -1751,6 +1825,7 @@ void _phy_iq_calibrate_8822b(struct dm_struct *dm, boolean reset,
dm->rf_calibrate_info.iqk_step = 1;
iqk->rxiqk_step = 1;
iqk->tmp_gntwl = _iqk_ltec_read_8822b(dm, 0x38);
_iqk_backup_iqk_8822b(dm, 0x0, 0x0);
_iqk_backup_mac_bb_8822b(dm, MAC_backup, BB_backup,
backup_mac_reg, backup_bb_reg);
@@ -1831,6 +1906,7 @@ void phy_iq_calibrate_8822b(void *dm_void, boolean clear, boolean segment_iqk)
_iq_calibrate_8822b_init(dm);
_phy_iq_calibrate_8822b(dm, clear, segment_iqk);
}
_iqk_0xc94_workaround_8822b(dm);
_iqk_fail_count_8822b(dm);
if (*dm->mp_mode)
halrf_iqk_hwtx_check(dm, false);
@@ -1845,9 +1921,12 @@ void _phy_imr_measure_8822b(struct dm_struct *dm)
u32 MAC_backup[MAC_REG_NUM_8822B], BB_backup[BB_REG_NUM_8822B];
u32 RF_backup[RF_REG_NUM_8822B][SS_8822B];
u32 backup_mac_reg[MAC_REG_NUM_8822B] = {0x520, 0x550};
u32 backup_bb_reg[BB_REG_NUM_8822B] = {
0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0xe00, 0xeb0, 0xeb4,
0xebc, 0x1990, 0x9a4, 0xa04, 0xb00};
u32 backup_bb_reg[BB_REG_NUM_8822B] = {0x808, 0x90c, 0xc00, 0xcb0,
0xcb4, 0xcbc, 0xe00, 0xeb0,
0xeb4, 0xebc, 0x1990, 0x9a4,
0xa04, 0xb00, 0x838, 0xc58,
0xc5c, 0xc6c, 0xe58, 0xe5c,
0xe6c};
u32 backup_rf_reg[RF_REG_NUM_8822B] = {0xdf, 0x8f, 0x65, 0x0, 0x1};
_iqk_backup_iqk_8822b(dm, 0x0, 0x0);
@@ -1878,4 +1957,206 @@ void do_imr_test_8822b(void *dm_void)
RF_DBG(dm, DBG_RF_IQK,
"[IQK] **********End IMR Test *******************\n");
}
void phy_get_iqk_cfir_8822b(void *dm_void, u8 idx, u8 path, boolean debug)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_iqk_info *iqk_info = &dm->IQK_info;
u8 i, ch;
u32 tmp;
u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
if (debug)
ch = 2;
else
ch = 0;
odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0xf8000008 | path << 1);
if (idx == 0)
odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x3);
else
odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x1);
odm_set_bb_reg(dm, R_0x1bd4, bit_mask_20_16, 0x10);
for (i = 0; i < 8; i++) {
odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001 + (i * 4));
tmp = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
iqk_info->iqk_cfir_real[ch][path][idx][i] =
(tmp & 0x0fff0000) >> 16;
iqk_info->iqk_cfir_imag[ch][path][idx][i] = tmp & 0xfff;
}
odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x0);
}
void phy_iqk_dbg_cfir_backup_8822b(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_iqk_info *iqk_info = &dm->IQK_info;
u8 path, idx, i;
RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "backup TX/RX CFIR");
for (path = 0; path < 2; path++)
for (idx = 0; idx < 2; idx++)
phydm_get_iqk_cfir(dm, idx, path, true);
for (path = 0; path < 2; path++) {
for (idx = 0; idx < 2; idx++) {
for (i = 0; i < 8; i++) {
RF_DBG(dm, DBG_RF_IQK,
"[IQK]%-7s %-3s CFIR_real: %-2d: 0x%x\n",
(path == 0) ? "PATH A" : "PATH B",
(idx == 0) ? "TX" : "RX", i,
iqk_info->iqk_cfir_real[2][path][idx][i])
;
}
for (i = 0; i < 8; i++) {
RF_DBG(dm, DBG_RF_IQK,
"[IQK]%-7s %-3s CFIR_img:%-2d: 0x%x\n",
(path == 0) ? "PATH A" : "PATH B",
(idx == 0) ? "TX" : "RX", i,
iqk_info->iqk_cfir_imag[2][path][idx][i])
;
}
}
}
}
void phy_iqk_dbg_cfir_backup_update_8822b(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_iqk_info *iqk = &dm->IQK_info;
u8 i, path, idx;
u32 bmask13_12 = BIT(13) | BIT(12);
u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
u32 data;
if (iqk->iqk_cfir_real[2][0][0][0] == 0) {
RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "CFIR is invalid");
return;
}
for (path = 0; path < 2; path++) {
for (idx = 0; idx < 2; idx++) {
odm_set_bb_reg(dm, R_0x1b00, MASKDWORD,
0xf8000008 | path << 1);
odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7);
odm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x20000000);
odm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x20000000);
odm_set_bb_reg(dm, R_0x1bcc, MASKDWORD, 0x00000000);
if (idx == 0)
odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x3);
else
odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x1);
odm_set_bb_reg(dm, R_0x1bd4, bmask20_16, 0x10);
for (i = 0; i < 8; i++) {
data = ((0xc0000000 >> idx) + 0x3) + (i * 4) +
(iqk->iqk_cfir_real[2][path][idx][i]
<< 9);
odm_write_4byte(dm, 0x1bd8, data);
data = ((0xc0000000 >> idx) + 0x1) + (i * 4) +
(iqk->iqk_cfir_imag[2][path][idx][i]
<< 9);
odm_write_4byte(dm, 0x1bd8, data);
#if 0
/*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_real[2][path][idx][i]);*/
/*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_imag[2][path][idx][i]);*/
#endif
}
}
odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x0);
}
RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "update new CFIR");
}
void phy_iqk_dbg_cfir_reload_8822b(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_iqk_info *iqk = &dm->IQK_info;
u8 i, path, idx;
u32 bmask13_12 = BIT(13) | BIT(12);
u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
u32 data;
if (iqk->iqk_cfir_real[0][0][0][0] == 0) {
RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "CFIR is invalid");
return;
}
for (path = 0; path < 2; path++) {
for (idx = 0; idx < 2; idx++) {
odm_set_bb_reg(dm, R_0x1b00, MASKDWORD,
0xf8000008 | path << 1);
odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7);
odm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x20000000);
odm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x20000000);
odm_set_bb_reg(dm, R_0x1bcc, MASKDWORD, 0x00000000);
if (idx == 0)
odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x3);
else
odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x1);
odm_set_bb_reg(dm, R_0x1bd4, bmask20_16, 0x10);
for (i = 0; i < 8; i++) {
#if 0
/*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_real[0][path][idx][i]);*/
/*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_imag[0][path][idx][i]);*/
#endif
data = ((0xc0000000 >> idx) + 0x3) + (i * 4) +
(iqk->iqk_cfir_real[0][path][idx][i]
<< 9);
odm_write_4byte(dm, 0x1bd8, data);
data = ((0xc0000000 >> idx) + 0x1) + (i * 4) +
(iqk->iqk_cfir_imag[0][path][idx][i]
<< 9);
odm_write_4byte(dm, 0x1bd8, data);
}
}
odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x0);
}
RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "write CFIR with default value");
}
void phy_iqk_dbg_cfir_write_8822b(void *dm_void, u8 type, u32 path, u32 idx,
u32 i, u32 data)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_iqk_info *iqk_info = &dm->IQK_info;
if (type == 0)
iqk_info->iqk_cfir_real[2][path][idx][i] = (u16)data;
else
iqk_info->iqk_cfir_imag[2][path][idx][i] = (u16)data;
}
void phy_iqk_dbg_cfir_backup_show_8822b(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_iqk_info *iqk_info = &dm->IQK_info;
u8 path, idx, i;
RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "backup TX/RX CFIR");
for (path = 0; path < 2; path++) {
for (idx = 0; idx < 2; idx++) {
for (i = 0; i < 8; i++) {
RF_DBG(dm, DBG_RF_IQK,
"[IQK]%-10s %-3s CFIR_real:%-2d: 0x%x\n",
(path == 0) ? "PATH A" : "PATH B",
(idx == 0) ? "TX" : "RX", i,
iqk_info->iqk_cfir_real[2][path][idx][i])
;
}
for (i = 0; i < 8; i++) {
RF_DBG(dm, DBG_RF_IQK,
"[IQK]%-10s %-3s CFIR_img:%-2d: 0x%x\n",
(path == 0) ? "PATH A" : "PATH B",
(idx == 0) ? "TX" : "RX", i,
iqk_info->iqk_cfir_imag[2][path][idx][i])
;
}
}
}
}
#endif

17
hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.h
View File

@@ -29,7 +29,7 @@
#if (RTL8822B_SUPPORT == 1)
/*@--------------------------Define Parameters-------------------------------*/
#define MAC_REG_NUM_8822B 2
#define BB_REG_NUM_8822B 15
#define BB_REG_NUM_8822B 21
#define RF_REG_NUM_8822B 5
#define LOK_delay_8822B 2
#define GS_delay_8822B 2
@@ -51,6 +51,21 @@ void phy_iq_calibrate_8822b(void *dm_void, boolean clear, boolean segment_iqk);
void do_imr_test_8822b(void *dm_void);
void phy_get_iqk_cfir_8822b(void *dm_void, u8 idx, u8 path, boolean debug);
void phy_iqk_dbg_cfir_backup_8822b(void *dm_void);
void phy_iqk_dbg_cfir_backup_update_8822b(void *dm_void);
void phy_iqk_dbg_cfir_reload_8822b(void *dm_void);
void phy_iqk_dbg_cfir_write_8822b(void *dm_void, u8 type, u32 path, u32 idx, u32 i, u32 data);
void phy_iqk_dbg_cfir_backup_show_8822b(void *dm_void);
#else /* (RTL8822B_SUPPORT == 0)*/
#define phy_iq_calibrate_8822b(_pdm_void, clear, segment_iqk)

26
hal/phydm/halrf/rtl8822b/version_rtl8822b_rf.h Normal file
View File

@@ -0,0 +1,26 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*RTL8822B RF Parameters*/
#define RF_RELEASE_VERSION_8822B 1

521
hal/phydm/phydm.c
View File

File diff suppressed because it is too large Load Diff

225
hal/phydm/phydm.h
View File

@@ -57,7 +57,7 @@
#include "phydm_dfs.h"
#include "phydm_ccx.h"
#include "txbf/phydm_hal_txbf_api.h"
#if (PHYDM_LA_MODE_SUPPORT == 1)
#if (PHYDM_LA_MODE_SUPPORT)
#include "phydm_adc_sampling.h"
#endif
#ifdef CONFIG_PSD_TOOL
@@ -86,10 +86,19 @@
#ifdef PHYDM_MP_SUPPORT
#include "phydm_mp.h"
#endif
#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
#include "phydm_cck_rx_pathdiv.h"
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#include "phydm_beamforming.h"
#endif
#ifdef CONFIG_DIRECTIONAL_BF
#include "phydm_direct_bf.h"
#endif
#include "phydm_regtable.h"
/*@HALRF header*/
@@ -107,7 +116,7 @@
#include "halrf/halphyrf_iot.h"
#endif
extern const u16 phy_rate_table[28];
extern const u16 phy_rate_table[84];
/*@============================================================*/
/*@Definition */
@@ -193,6 +202,7 @@ extern const u16 phy_rate_table[28];
#endif
#define PHY_HIST_SIZE 12
#define PHY_HIST_TH_SIZE (PHY_HIST_SIZE - 1)
/*@============================================================*/
/*structure and define*/
@@ -219,15 +229,15 @@ struct phydm_bb_ram_per_sta {
};
struct phydm_bb_ram_ctrl {
/*@ For 98F/14B/22C/12F, each TxAGC step will be 0.25dB*/
/*@ For 98F/14B/22C/12F, each tx_pwr_ofst step will be 1dB*/
struct phydm_bb_ram_per_sta pram_sta_ctrl[ODM_ASSOCIATE_ENTRY_NUM];
/*------------ For table2 do not set power offset by macid --------*/
/* For type == 2'b10, 0x1e70[22:16] = tx_pwr_offset_reg0, 0x1e70[23] = enable */
boolean tx_pwr_offset_reg0_en;
u8 tx_pwr_offset_reg0;
boolean tx_pwr_ofst_reg0_en;
u8 tx_pwr_ofst_reg0;
/* For type == 2'b11, 0x1e70[30:24] = tx_pwr_offset_reg1, 0x1e70[31] = enable */
boolean tx_pwr_offset_reg1_en;
u8 tx_pwr_offset_reg1;
boolean tx_pwr_ofst_reg1_en;
u8 tx_pwr_ofst_reg1;
};
#endif
@@ -236,77 +246,95 @@ struct phydm_phystatus_statistic {
/*@[CCK]*/
u32 rssi_cck_sum;
u32 rssi_cck_cnt;
u32 rssi_beacon_sum[RF_PATH_MEM_SIZE];
u32 rssi_beacon_cnt;
#ifdef PHYSTS_3RD_TYPE_SUPPORT
#if (defined(PHYDM_COMPILE_ABOVE_2SS))
u32 rssi_cck_sum_abv_2ss[RF_PATH_MEM_SIZE - 1];
#endif
#endif
/*@[OFDM]*/
u32 rssi_ofdm_sum;
u32 rssi_ofdm_sum[RF_PATH_MEM_SIZE];
u32 rssi_ofdm_cnt;
u32 evm_ofdm_sum;
u32 snr_ofdm_sum;
u32 snr_ofdm_sum[RF_PATH_MEM_SIZE];
u16 evm_ofdm_hist[PHY_HIST_SIZE];
u16 snr_ofdm_hist[PHY_HIST_SIZE];
/*@[1SS]*/
u32 rssi_1ss_cnt;
u32 rssi_1ss_sum;
u32 rssi_1ss_sum[RF_PATH_MEM_SIZE];
u32 evm_1ss_sum;
u32 snr_1ss_sum;
u32 snr_1ss_sum[RF_PATH_MEM_SIZE];
u16 evm_1ss_hist[PHY_HIST_SIZE];
u16 snr_1ss_hist[PHY_HIST_SIZE];
/*@[2SS]*/
#if (defined(PHYDM_COMPILE_ABOVE_2SS))
u32 rssi_2ss_cnt;
u32 rssi_2ss_sum[2];
u32 rssi_2ss_sum[RF_PATH_MEM_SIZE];
u32 evm_2ss_sum[2];
u32 snr_2ss_sum[2];
u32 snr_2ss_sum[RF_PATH_MEM_SIZE];
u16 evm_2ss_hist[2][PHY_HIST_SIZE];
u16 snr_2ss_hist[2][PHY_HIST_SIZE];
#endif
/*@[3SS]*/
#if (defined(PHYDM_COMPILE_ABOVE_3SS))
u32 rssi_3ss_cnt;
u32 rssi_3ss_sum[3];
u32 rssi_3ss_sum[RF_PATH_MEM_SIZE];
u32 evm_3ss_sum[3];
u32 snr_3ss_sum[3];
u32 snr_3ss_sum[RF_PATH_MEM_SIZE];
u16 evm_3ss_hist[3][PHY_HIST_SIZE];
u16 snr_3ss_hist[3][PHY_HIST_SIZE];
#endif
/*@[4SS]*/
#if (defined(PHYDM_COMPILE_ABOVE_4SS))
u32 rssi_4ss_cnt;
u32 rssi_4ss_sum[4];
u32 rssi_4ss_sum[RF_PATH_MEM_SIZE];
u32 evm_4ss_sum[4];
u32 snr_4ss_sum[4];
u32 snr_4ss_sum[RF_PATH_MEM_SIZE];
u16 evm_4ss_hist[4][PHY_HIST_SIZE];
u16 snr_4ss_hist[4][PHY_HIST_SIZE];
#endif
#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
u16 p4_cnt[RF_PATH_MEM_SIZE]; /*phy-sts page4 cnt*/
u16 cn_sum[RF_PATH_MEM_SIZE]; /*condition number*/
u16 cn_hist[RF_PATH_MEM_SIZE][PHY_HIST_SIZE];
#endif
};
struct phydm_phystatus_avg {
/*@[CCK]*/
u8 rssi_cck_avg;
u8 rssi_beacon_avg[RF_PATH_MEM_SIZE];
#ifdef PHYSTS_3RD_TYPE_SUPPORT
#if (defined(PHYDM_COMPILE_ABOVE_2SS))
u8 rssi_cck_avg_abv_2ss[RF_PATH_MEM_SIZE - 1];
#endif
#endif
/*@[OFDM]*/
u8 rssi_ofdm_avg;
u8 rssi_ofdm_avg[RF_PATH_MEM_SIZE];
u8 evm_ofdm_avg;
u8 snr_ofdm_avg;
u8 snr_ofdm_avg[RF_PATH_MEM_SIZE];
/*@[1SS]*/
u8 rssi_1ss_avg;
u8 rssi_1ss_avg[RF_PATH_MEM_SIZE];
u8 evm_1ss_avg;
u8 snr_1ss_avg;
u8 snr_1ss_avg[RF_PATH_MEM_SIZE];
/*@[2SS]*/
#if (defined(PHYDM_COMPILE_ABOVE_2SS))
u8 rssi_2ss_avg[2];
u8 rssi_2ss_avg[RF_PATH_MEM_SIZE];
u8 evm_2ss_avg[2];
u8 snr_2ss_avg[2];
u8 snr_2ss_avg[RF_PATH_MEM_SIZE];
#endif
/*@[3SS]*/
#if (defined(PHYDM_COMPILE_ABOVE_3SS))
u8 rssi_3ss_avg[3];
u8 rssi_3ss_avg[RF_PATH_MEM_SIZE];
u8 evm_3ss_avg[3];
u8 snr_3ss_avg[3];
u8 snr_3ss_avg[RF_PATH_MEM_SIZE];
#endif
/*@[4SS]*/
#if (defined(PHYDM_COMPILE_ABOVE_4SS))
u8 rssi_4ss_avg[4];
u8 rssi_4ss_avg[RF_PATH_MEM_SIZE];
u8 evm_4ss_avg[4];
u8 snr_4ss_avg[4];
u8 snr_4ss_avg[RF_PATH_MEM_SIZE];
#endif
};
@@ -314,7 +342,7 @@ struct odm_phy_dbg_info {
/*@ODM Write,debug info*/
u32 num_qry_phy_status_cck;
u32 num_qry_phy_status_ofdm;
#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) || (defined(PHYSTS_3RD_TYPE_SUPPORT))
#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) || (defined(PHYSTS_3RD_TYPE_SUPPORT))
u32 num_qry_mu_pkt;
u32 num_qry_bf_pkt;
u16 num_mu_vht_pkt[VHT_RATE_NUM];
@@ -342,8 +370,11 @@ struct odm_phy_dbg_info {
boolean vht_pkt_not_zero;
boolean low_bw_40_occur;
#endif
u16 snr_hist_th[PHY_HIST_SIZE - 1];
u16 evm_hist_th[PHY_HIST_SIZE - 1];
u16 snr_hist_th[PHY_HIST_TH_SIZE];
u16 evm_hist_th[PHY_HIST_TH_SIZE];
#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
u16 cn_hist_th[PHY_HIST_TH_SIZE]; /*U(16,1)*/
#endif
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
s16 cfo_tail[4]; /* per-path's cfo_tail */
#endif
@@ -393,12 +424,16 @@ enum odm_cmninfo {
ODM_CMNINFO_REGRFKFREEENABLE,
ODM_CMNINFO_RFKFREEENABLE,
ODM_CMNINFO_NORMAL_RX_PATH_CHANGE,
ODM_CMNINFO_VALID_PATH_SET,
ODM_CMNINFO_EFUSE0X3D8,
ODM_CMNINFO_EFUSE0X3D7,
ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING,
ODM_CMNINFO_X_CAP_SETTING,
ODM_CMNINFO_ADVANCE_OTA,
ODM_CMNINFO_HP_HWID,
ODM_CMNINFO_TSSI_ENABLE,
ODM_CMNINFO_DIS_DPD,
ODM_CMNINFO_POWER_VOLTAGE,
/*@-----------HOOK BEFORE REG INIT-----------*/
/*@Dynamic value:*/
@@ -436,6 +471,7 @@ enum odm_cmninfo {
ODM_CMNINFO_INTERRUPT_MASK,
ODM_CMNINFO_BB_OPERATION_MODE,
ODM_CMNINFO_BF_ANTDIV_DECISION,
ODM_CMNINFO_MANUAL_SUPPORTABILITY,
/*@--------- POINTER REFERENCE-----------*/
/*@------------CALL BY VALUE-------------*/
@@ -462,6 +498,10 @@ enum odm_cmninfo {
ODM_CMNINFO_POWER_TRAINING,
ODM_CMNINFO_DFS_REGION_DOMAIN,
ODM_CMNINFO_BT_CONTINUOUS_TURN,
ODM_CMNINFO_IS_DOWNLOAD_FW,
ODM_CMNINFO_PHYDM_PATCH_ID,
ODM_CMNINFO_RRSR_VAL,
ODM_CMNINFO_LINKED_BF_SUPPORT,
/*@------------CALL BY VALUE-------------*/
/*@Dynamic ptr array hook itms.*/
@@ -515,6 +555,7 @@ enum phydm_info_query {
PHYDM_INFO_RSSI_MAX,
PHYDM_INFO_CLM_RATIO,
PHYDM_INFO_NHM_RATIO,
PHYDM_INFO_NHM_NOISE_PWR,
};
enum phydm_api {
@@ -623,6 +664,7 @@ enum phy_reg_pg_type {
enum phydm_offload_ability {
PHYDM_PHY_PARAM_OFFLOAD = BIT(0),
PHYDM_RF_IQK_OFFLOAD = BIT(1),
PHYDM_RF_DPK_OFFLOAD = BIT(2),
};
struct phydm_pause_lv {
@@ -638,8 +680,14 @@ struct phydm_func_poiner {
};
struct pkt_process_info {
u8 phystatus_smp_mode_en; /*@send phystatus every sampling time*/
u8 pre_ppdu_cnt;
#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
/*@send phystatus in each sampling time*/
boolean physts_auto_swch_en;
u8 mac_ppdu_cnt;
u8 phy_ppdu_cnt; /*change with phy cca cnt*/
u8 page_bitmap_target;
u8 page_bitmap_record;
#endif
u8 lna_idx;
u8 vga_idx;
};
@@ -661,7 +709,7 @@ struct phydm_iot_center {
};
#if (RTL8822B_SUPPORT == 1)
#if (RTL8822B_SUPPORT)
struct drp_rtl8822b_struct {
enum bb_path path_judge;
u16 path_a_cck_fa;
@@ -683,11 +731,17 @@ struct _phydm_mcc_dm_ {
/* need to be config by driver*/
u8 mcc_status;
u8 sta_macid[2][NUM_STA];
u16 mcc_rf_channel[2];
u16 mcc_rf_ch[2];
};
#endif
#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
struct phydm_physts {
u8 cck_gi_u_bnd;
u8 cck_gi_l_bnd;
};
#endif
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (RT_PLATFORM != PLATFORM_LINUX)
@@ -713,7 +767,10 @@ struct dm_struct {
u32 num_qry_phy_status_all; /*@CCK + OFDM*/
u32 last_num_qry_phy_status_all;
u32 rx_pwdb_ave;
boolean is_init_hw_info_by_rfe;
boolean is_init_hw_info_by_rfe;
//TSSI
u8 en_tssi_mode;
/*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
boolean is_cck_high_power;
@@ -727,9 +784,11 @@ struct dm_struct {
u8 support_platform; /*@PHYDM Platform info WIN/AP/CE = 1/2/3 */
u8 normal_rx_path;
u8 valid_path_set; /*@use for single rx path only*/
boolean brxagcswitch; /* @for rx AGC table switch in Microsoft case */
u8 support_interface; /*@PHYDM PCIE/USB/SDIO = 1/2/3*/
u32 support_ic_type; /*@PHYDM supported IC*/
enum phydm_api_host run_in_drv_fw; /*@PHYDM API is using in FW or Driver*/
u8 ic_ip_series; /*N/AC/JGR3*/
enum phydm_phy_sts_type ic_phy_sts_type; /*@Type1/type2/type3*/
u8 cut_version; /*@cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/
@@ -760,10 +819,12 @@ struct dm_struct {
/*@cck agc relative*/
boolean cck_new_agc;
s8 cck_lna_gain_table[8];
u8 cck_sat_cnt_th_init;
/*@-------------------------------------*/
u32 phydm_sys_up_time;
u8 num_rf_path; /*@ex: 8821C=1, 8192E=2, 8814B=4*/
u32 soft_ap_special_setting;
boolean boolean_dummy;
s8 s8_dummy;
u8 u8_dummy;
u16 u16_dummy;
@@ -775,6 +836,13 @@ struct dm_struct {
boolean is_dfs_band;
u8 is_rx_blocking_en;
u16 fw_offload_ability;
boolean is_download_fw;
boolean en_dis_dpd;
u16 dis_dpd_rate;
#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8197G_SUPPORT)
u8 txagc_buff[RF_PATH_MEM_SIZE][PHY_NUM_RATE_IDX];
u32 bp_0x9b0;
#endif
/*@-----------HOOK BEFORE REG INIT-----------*/
/*@===========================================================*/
/*@====[ CALL BY Reference ]=========================================*/
@@ -793,7 +861,7 @@ struct dm_struct {
u8 *one_path_cca; /*@CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/
u8 *antenna_test;
boolean *is_net_closed;
boolean *is_fcs_mode_enable;
boolean *is_fcs_mode_enable; /*@fast channel switch (= MCC mode)*/
/*@--------- For 8723B IQK-------------------------------------*/
boolean *is_1_antenna;
u8 *rf_default_path; /* @0:S1, 1:S0 */
@@ -803,7 +871,7 @@ struct dm_struct {
u8 *enable_antdiv;
u8 *enable_pathdiv;
u8 *en_adap_soml;
u8 *enable_adaptivity;
u8 *edcca_mode;
u8 *hub_usb_mode; /*@1:USB2.0, 2:USB3.0*/
boolean *is_fw_dw_rsvd_page_in_progress;
u32 *current_tx_tp;
@@ -813,6 +881,7 @@ struct dm_struct {
u8 *mp_mode;
u32 *interrupt_mask;
u8 *bb_op_mode;
u32 *manual_supportability;
/*@===========================================================*/
/*@====[ CALL BY VALUE ]===========================================*/
/*@===========================================================*/
@@ -822,6 +891,9 @@ struct dm_struct {
boolean is_wifi_direct;
boolean is_wifi_display;
boolean is_linked;
boolean pre_is_linked;
boolean first_connect;
boolean first_disconnect;
boolean bsta_state;
u8 rssi_min;
u8 rssi_min_macid;
@@ -851,8 +923,18 @@ struct dm_struct {
u64 rssi_trsw_h;
u64 rssi_trsw_l;
u64 rssi_trsw_iso;
u8 tx_ant_status;
u8 rx_ant_status;
u8 tx_ant_status; /*TX path enable*/
u8 rx_ant_status; /*RX path enable*/
#ifdef PHYDM_COMPILE_ABOVE_4SS
enum bb_path tx_4ss_status; /*@Use N-X for 4STS rate*/
#endif
#ifdef PHYDM_COMPILE_ABOVE_3SS
enum bb_path tx_3ss_status; /*@Use N-X for 3STS rate*/
#endif
#ifdef PHYDM_COMPILE_ABOVE_2SS
enum bb_path tx_2ss_status; /*@Use N-X for 2STS rate*/
#endif
enum bb_path tx_1ss_status; /*@Use N-X for 1STS rate*/
u8 cck_lna_idx;
u8 cck_vga_idx;
u8 curr_station_id;
@@ -889,7 +971,7 @@ struct dm_struct {
u8 force_igi; /*@for debug*/
/*@[TDMA-DIG]*/
u8 tdma_dig_timer_ms;
u16 tdma_dig_timer_ms;
u8 tdma_dig_state_number;
u8 tdma_dig_low_upper_bond;
u8 force_tdma_low_igi;
@@ -904,6 +986,7 @@ struct dm_struct {
u8 fat_comb_a;
u8 fat_comb_b;
u8 antdiv_intvl;
u8 antdiv_delay;
u8 ant_type;
u8 ant_type2;
u8 pre_ant_type;
@@ -943,7 +1026,6 @@ struct dm_struct {
s8 th_edcca_hl_diff;
boolean carrier_sense_enable;
/*@-----------------------------------------------------------*/
u8 pre_dbg_priority;
u8 nbi_set_result;
u8 c2h_cmd_start;
@@ -951,7 +1033,19 @@ struct dm_struct {
u8 pre_c2h_seq;
boolean fw_buff_is_enpty;
u32 data_frame_num;
/*@--- for spur detection ---------------------------------------*/
boolean en_reg_mntr_bb;
boolean en_reg_mntr_rf;
boolean en_reg_mntr_mac;
boolean en_reg_mntr_byte;
/*@--------------------------------------------------------------*/
#if (RTL8814B_SUPPORT)
/*@--- for spur detection ---------------------------------------*/
u8 dsde_sel;
u8 nbi_path_sel;
u8 csi_wgt;
/*@------------------------------------------*/
#endif
/*@--- for noise detection ---------------------------------------*/
boolean is_noisy_state;
boolean noisy_decision; /*@b_noisy*/
@@ -968,7 +1062,7 @@ struct dm_struct {
struct cmn_sta_info *phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];
u8 phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];/*@sta_idx = phydm_macid_table[HW_macid]*/
#if (RATE_ADAPTIVE_SUPPORT == 1)
#if (RATE_ADAPTIVE_SUPPORT)
u16 currmin_rpt_time;
struct _phydm_txstatistic_ hw_stats;
struct _odm_ra_info_ ra_info[ODM_ASSOCIATE_ENTRY_NUM];
@@ -990,6 +1084,7 @@ struct dm_struct {
/*@-----------------------------------------------------------*/
boolean bsomlenabled; /* @D-SoML control */
u8 linked_bf_support;
boolean bhtstfdisabled; /* @dynamic HTSTF gain control*/
u32 n_iqk_cnt;
u32 n_iqk_ok_cnt;
@@ -1023,14 +1118,34 @@ struct dm_struct {
u32 radar_detect_reg_91c;
u32 radar_detect_reg_920;
u32 radar_detect_reg_924;
u32 radar_detect_reg_a40;
u32 radar_detect_reg_a44;
u32 radar_detect_reg_a48;
u32 radar_detect_reg_a4c;
u32 radar_detect_reg_a50;
u32 radar_detect_reg_a54;
u32 radar_detect_reg_f54;
u32 radar_detect_reg_f58;
u32 radar_detect_reg_f5c;
u32 radar_detect_reg_f70;
u32 radar_detect_reg_f74;
/*@---For zero-wait DFS---------------------------------------*/
boolean seg1_dfs_flag;
/*@-----------------------------------------------------------*/
/*@-----------------------------------------------------------*/
#endif
/*@=== RTL8721D ===*/
#if (RTL8721D_SUPPORT)
boolean cbw20_adc80;
boolean invalid_mode;
u8 power_voltage;
u8 cca_cbw20_lev;
u8 cca_cbw40_lev;
#endif
/*@=== PHYDM Timer ========================================== (start)*/
struct phydm_timer_list mpt_dig_timer;
@@ -1051,6 +1166,9 @@ struct dm_struct {
RT_WORK_ITEM ra_rpt_workitem;
RT_WORK_ITEM sbdcnt_workitem;
RT_WORK_ITEM phydm_evm_antdiv_workitem;
#ifdef PHYDM_TDMA_DIG_SUPPORT
RT_WORK_ITEM phydm_tdma_dig_workitem;
#endif
#endif
#endif
@@ -1068,6 +1186,10 @@ struct dm_struct {
struct odm_noise_monitor noise_level;
struct odm_phy_dbg_info phy_dbg_info;
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
struct phydm_bf_rate_info_jgr3 bf_rate_info_jgr3;
#endif
#ifdef CONFIG_ADAPTIVE_SOML
struct adaptive_soml dm_soml_table;
#endif
@@ -1090,6 +1212,7 @@ struct dm_struct {
struct dm_rf_calibration_struct rf_calibrate_info;
struct dm_iqk_info IQK_info;
struct dm_dpk_info dpk_info;
struct dm_dack_info dack_info;
#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
struct phydm_fat_struct dm_fat_table;
@@ -1124,7 +1247,7 @@ struct dm_struct {
struct ccx_info dm_ccx_info;
struct odm_power_trim_data power_trim_data;
#if (RTL8822B_SUPPORT == 1)
#if (RTL8822B_SUPPORT)
struct drp_rtl8822b_struct phydm_rtl8822b;
#endif
@@ -1132,7 +1255,7 @@ struct dm_struct {
struct psd_info dm_psd_table;
#endif
#if (PHYDM_LA_MODE_SUPPORT == 1)
#if (PHYDM_LA_MODE_SUPPORT)
struct rt_adcsmp adcsmp;
#endif
@@ -1166,8 +1289,17 @@ struct dm_struct {
#ifdef PHYDM_MP_SUPPORT
struct phydm_mp dm_mp_table;
#endif
#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
struct phydm_cck_rx_pathdiv dm_cck_rx_pathdiv_table;
#endif
/*@==========================================================*/
#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
/*@-------------------phydm_phystatus report --------------------*/
struct phydm_physts dm_physts_table;
#endif
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (RT_PLATFORM != PLATFORM_LINUX)
@@ -1296,6 +1428,9 @@ void
phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm,
enum phydm_pause_type pause_type, u8 rssi);
void
odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info, u64 value);

27
hal/phydm/phydm.mk
View File

@@ -17,6 +17,7 @@ _PHYDM_FILES := hal/phydm/phydm_debug.o \
hal/phydm/phydm_cfotracking.o\
hal/phydm/phydm_noisemonitor.o\
hal/phydm/phydm_beamforming.o\
hal/phydm/phydm_direct_bf.o\
hal/phydm/phydm_dfs.o\
hal/phydm/txbf/halcomtxbf.o\
hal/phydm/txbf/haltxbfinterface.o\
@@ -34,12 +35,14 @@ _PHYDM_FILES := hal/phydm/phydm_debug.o \
hal/phydm/phydm_lna_sat.o\
hal/phydm/phydm_pmac_tx_setting.o\
hal/phydm/phydm_mp.o\
hal/phydm/phydm_cck_rx_pathdiv.o\
hal/phydm/halrf/halrf.o\
hal/phydm/halrf/halrf_debug.o\
hal/phydm/halrf/halphyrf_ce.o\
hal/phydm/halrf/halrf_powertracking_ce.o\
hal/phydm/halrf/halrf_powertracking.o\
hal/phydm/halrf/halrf_kfree.o
hal/phydm/halrf/halrf_kfree.o\
hal/phydm/halrf/halrf_psd.o
ifeq ($(CONFIG_RTL8188E), y)
RTL871X = rtl8188e
@@ -104,7 +107,7 @@ ifeq ($(CONFIG_RTL8814A), y)
RTL871X = rtl8814a
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\
hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\
hal/phydm/$(RTL871X)/halhwimg8814a_rf.o\
hal/phydm/halrf/$(RTL871X)/halhwimg8814a_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\
hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\
hal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\
@@ -138,9 +141,9 @@ ifeq ($(CONFIG_RTL8710B), y)
RTL871X = rtl8710b
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8710b_bb.o\
hal/phydm/$(RTL871X)/halhwimg8710b_mac.o\
hal/phydm/$(RTL871X)/halhwimg8710b_rf.o\
hal/phydm/$(RTL871X)/phydm_regconfig8710b.o\
hal/phydm/$(RTL871X)/phydm_rtl8710b.o\
hal/phydm/halrf/$(RTL871X)/halhwimg8710b_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_8710b.o
endif
@@ -159,9 +162,9 @@ ifeq ($(CONFIG_RTL8822B), y)
RTL871X = rtl8822b
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \
hal/phydm/$(RTL871X)/halhwimg8822b_mac.o \
hal/phydm/$(RTL871X)/halhwimg8822b_rf.o \
hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \
hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \
hal/phydm/halrf/$(RTL871X)/halhwimg8822b_rf.o \
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \
hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822b.o \
hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \
@@ -175,9 +178,9 @@ ifeq ($(CONFIG_RTL8821C), y)
RTL871X = rtl8821c
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \
hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \
hal/phydm/$(RTL871X)/halhwimg8821c_rf.o \
hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \
hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\
hal/phydm/halrf/$(RTL871X)/halhwimg8821c_rf.o \
hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o
endif
@@ -185,10 +188,10 @@ ifeq ($(CONFIG_RTL8192F), y)
RTL871X = rtl8192f
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192f_bb.o\
hal/phydm/$(RTL871X)/halhwimg8192f_mac.o\
hal/phydm/$(RTL871X)/halhwimg8192f_rf.o\
hal/phydm/$(RTL871X)/phydm_hal_api8192f.o\
hal/phydm/$(RTL871X)/phydm_regconfig8192f.o\
hal/phydm/$(RTL871X)/phydm_rtl8192f.o\
hal/phydm/halrf/$(RTL871X)/halhwimg8192f_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_8192f.o
endif
@@ -196,23 +199,23 @@ ifeq ($(CONFIG_RTL8198F), y)
RTL871X = rtl8198f
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8198f_bb.o\
hal/phydm/$(RTL871X)/halhwimg8198f_mac.o\
hal/phydm/$(RTL871X)/halhwimg8198f_rf.o\
hal/phydm/$(RTL871X)/phydm_hal_api8198f.o\
hal/phydm/$(RTL871X)/phydm_regconfig8198f.o
hal/phydm/$(RTL871X)/phydm_regconfig8198f.o\
hal/phydm/halrf/$(RTL871X)/halhwimg8198f_rf.o
endif
ifeq ($(CONFIG_RTL8822C), y)
RTL871X = rtl8822c
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822c_bb.o\
hal/phydm/$(RTL871X)/halhwimg8822c_mac.o\
hal/phydm/$(RTL871X)/halhwimg8822c_rf.o\
hal/phydm/$(RTL871X)/phydm_hal_api8822c.o\
hal/phydm/$(RTL871X)/phydm_regconfig8822c.o\
hal/phydm/$(RTL871X)/phydm_rtl8822c.o\
hal/phydm/halrf/$(RTL871X)/halrf_8822c.o\
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822c.o\
hal/phydm/halrf/$(RTL871X)/halrf_tssi_8822c.o\
hal/phydm/halrf/$(RTL871X)/halrf_dpk_8822c.o\
hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822c.o
hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822c.o\
hal/phydm/halrf/$(RTL871X)/halhwimg8822c_rf.o
endif
ifeq ($(CONFIG_RTL8814B), y)
@@ -220,7 +223,9 @@ RTL871X = rtl8814b
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814b_bb.o\
hal/phydm/$(RTL871X)/phydm_hal_api8814b.o\
hal/phydm/$(RTL871X)/phydm_regconfig8814b.o\
hal/phydm/halrf/$(RTL871X)/halhwimg8814b_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_8814b.o \
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814b.o \
hal/phydm/halrf/$(RTL871X)/halrf_dpk_8814b.o\
hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8814b.o
endif

540
hal/phydm/phydm_adaptivity.c
View File

@@ -40,7 +40,7 @@ boolean
phydm_check_channel_plan(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adapt = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY);
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
void *adapter = dm->adapter;
PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
@@ -92,8 +92,8 @@ boolean
phydm_soft_ap_special_set(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY);
u8 disable_ap_adapt_setting = false;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
boolean disable_ap_adapt_setting = false;
if (dm->soft_ap_mode != NULL) {
if (*dm->soft_ap_mode != 0 &&
@@ -109,6 +109,43 @@ phydm_soft_ap_special_set(void *dm_void)
return disable_ap_adapt_setting;
}
boolean
phydm_ap_num_check(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
boolean dis_adapt = false;
if (dm->ap_total_num > adapt->ap_num_th)
dis_adapt = true;
else
dis_adapt = false;
PHYDM_DBG(dm, DBG_ADPTVTY, "AP total num = %d, AP num threshold = %d\n",
dm->ap_total_num, adapt->ap_num_th);
return dis_adapt;
}
void phydm_check_adaptivity(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
boolean disable_adapt = false;
if (!adapt->mode_cvrt_en)
return;
if (phydm_check_channel_plan(dm) || phydm_ap_num_check(dm) ||
phydm_soft_ap_special_set(dm))
disable_adapt = true;
if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE && disable_adapt)
*dm->edcca_mode = PHYDM_EDCCA_NORMAL_MODE;
else if (*dm->edcca_mode == PHYDM_EDCCA_NORMAL_MODE && !disable_adapt)
*dm->edcca_mode = PHYDM_EDCCA_ADAPT_MODE;
}
#endif
void phydm_dig_up_bound_lmt_en(void *dm_void)
@@ -116,9 +153,8 @@ void phydm_dig_up_bound_lmt_en(void *dm_void)
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
if (!(dm->support_ability & ODM_BB_ADAPTIVITY) ||
!dm->is_linked ||
!adapt->is_adapt_en) {
if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE ||
!dm->is_linked) {
adapt->igi_up_bound_lmt_cnt = 0;
adapt->igi_lmt_en = false;
return;
@@ -140,40 +176,6 @@ void phydm_dig_up_bound_lmt_en(void *dm_void)
adapt->igi_up_bound_lmt_cnt);
}
void phydm_check_adaptivity(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
if (!(dm->support_ability & ODM_BB_ADAPTIVITY)) {
adapt->is_adapt_en = false;
dm->th_l2h_ini = adapt->th_l2h_ini_mode2;
dm->th_edcca_hl_diff = adapt->th_edcca_hl_diff_mode2;
PHYDM_DBG(dm, DBG_ADPTVTY,
"adaptivity disable, enable EDCCA mode!!!\n");
return;
}
adapt->is_adapt_en = true;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
if (phydm_check_channel_plan(dm) ||
dm->ap_total_num > adapt->ap_num_th ||
phydm_soft_ap_special_set(dm)) {
adapt->is_adapt_en = false;
PHYDM_DBG(dm, DBG_ADPTVTY,
"AP total num > %d!!, disable adaptivity\n",
adapt->ap_num_th);
}
if (!adapt->is_adapt_en) {
dm->th_l2h_ini = adapt->th_l2h_ini_mode2;
dm->th_edcca_hl_diff = adapt->th_edcca_hl_diff_mode2;
} else {
dm->th_l2h_ini = adapt->th_l2h_ini_backup;
dm->th_edcca_hl_diff = adapt->th_edcca_hl_diff_backup;
}
#endif
}
void phydm_set_edcca_threshold(void *dm_void, s8 H2L, s8 L2H)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
@@ -195,15 +197,15 @@ void phydm_mac_edcca_state(void *dm_void, enum phydm_mac_edcca_type state)
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (state == PHYDM_IGNORE_EDCCA) {
odm_set_mac_reg(dm, R_0x520, BIT(15), 1); /*@ignore EDCCA*/
#if 0
/*odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 0);*/
#endif
/*@ignore EDCCA*/
odm_set_mac_reg(dm, R_0x520, BIT(15), 1);
/*@enable EDCCA count down*/
odm_set_mac_reg(dm, R_0x524, BIT(11), 0);
} else { /*@don't set MAC ignore EDCCA signal*/
odm_set_mac_reg(dm, R_0x520, BIT(15), 0); /*@don't ignore EDCCA*/
#if 0
/*odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 1);*/
#endif
/*@don't ignore EDCCA*/
odm_set_mac_reg(dm, R_0x520, BIT(15), 0);
/*@disable EDCCA count down*/
odm_set_mac_reg(dm, R_0x524, BIT(11), 1);
}
PHYDM_DBG(dm, DBG_ADPTVTY, "EDCCA enable state = %d\n", state);
}
@@ -216,18 +218,18 @@ void phydm_search_pwdb_lower_bound(void *dm_void)
u8 cnt = 0, try_count = 0;
u8 tx_edcca1 = 0;
boolean is_adjust = true;
s8 th_l2h_dmc, th_h2l_dmc, igi_target = 0x32;
s8 th_l2h, th_h2l, igi_target_dc = 0x32;
s8 diff = 0;
s8 IGI = adapt->igi_base + 30 + dm->th_l2h_ini - dm->th_edcca_hl_diff;
halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
diff = igi_target - IGI;
th_l2h_dmc = dm->th_l2h_ini + diff;
if (th_l2h_dmc > 10)
th_l2h_dmc = 10;
diff = igi_target_dc - IGI;
th_l2h = dm->th_l2h_ini + diff;
if (th_l2h > 10)
th_l2h = 10;
th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
th_h2l = th_l2h - dm->th_edcca_hl_diff;
phydm_set_edcca_threshold(dm, th_h2l, th_l2h);
ODM_delay_ms(30);
while (is_adjust) {
@@ -262,14 +264,14 @@ void phydm_search_pwdb_lower_bound(void *dm_void)
if (tx_edcca1 > 1) {
IGI = IGI - 1;
th_l2h_dmc = th_l2h_dmc + 1;
if (th_l2h_dmc > 10)
th_l2h_dmc = 10;
th_l2h = th_l2h + 1;
if (th_l2h > 10)
th_l2h = 10;
th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
th_h2l = th_l2h - dm->th_edcca_hl_diff;
phydm_set_edcca_threshold(dm, th_h2l, th_l2h);
tx_edcca1 = 0;
if (th_l2h_dmc == 10)
if (th_l2h == 10)
is_adjust = false;
} else {
@@ -278,15 +280,14 @@ void phydm_search_pwdb_lower_bound(void *dm_void)
}
adapt->adapt_igi_up = IGI - ADAPT_DC_BACKOFF;
adapt->h2l_lb = th_h2l_dmc + ADAPT_DC_BACKOFF;
adapt->l2h_lb = th_l2h_dmc + ADAPT_DC_BACKOFF;
adapt->h2l_lb = th_h2l + ADAPT_DC_BACKOFF;
adapt->l2h_lb = th_l2h + ADAPT_DC_BACKOFF;
halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
phydm_set_edcca_threshold(dm, 0x7f, 0x7f); /*resume to no link state*/
}
boolean
phydm_re_search_condition(void *dm_void)
boolean phydm_re_search_condition(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
@@ -302,50 +303,61 @@ void phydm_set_l2h_th_ini(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
if (dm->support_ic_type &
(ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A))
dm->th_l2h_ini = 0xf2;
/*@ [New Format: JGR3]IGI-idx:45 = RSSI:35 = -65dBm*/
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
if (dm->support_ic_type & ODM_RTL8822C)
dm->th_l2h_ini = 45;
else if (dm->support_ic_type & ODM_RTL8814B)
dm->th_l2h_ini = 49;
} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
/*@ [Old Format] -11+base(50) = IGI_idx:39 = RSSI:29 = -71dBm*/
if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812))
dm->th_l2h_ini = -17;
else
dm->th_l2h_ini = 0xef;
} else if (dm->support_ic_type & ODM_RTL8822C) {
dm->th_l2h_ini = 0x2d;
} else if (dm->support_ic_type & ODM_RTL8814B) {
dm->th_l2h_ini = 0x31;
} else {
dm->th_l2h_ini = 0xf5;
dm->th_l2h_ini = -14;
} else { /*ODM_IC_11N_SERIES*/
if (dm->support_ic_type & ODM_RTL8721D)
dm->th_l2h_ini = -14;
else
dm->th_l2h_ini = -11;
}
}
void phydm_set_l2h_th_ini_carrier_sense(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
dm->th_l2h_ini = 60; /*@ -50dBm*/
else
dm->th_l2h_ini = 10; /*@ -50dBm*/
}
void phydm_set_forgetting_factor(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A))
if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
return;
if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A |
ODM_RTL8195B))
odm_set_bb_reg(dm, R_0x8a0, BIT(1) | BIT(0), 0);
else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
odm_set_bb_reg(dm, R_0x83c, BIT(31) | BIT(30) | BIT(29), 0x7);
}
void phydm_set_pwdb_mode(void *dm_void)
void phydm_edcca_decision_opt(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ability & ODM_BB_ADAPTIVITY) {
if (dm->support_ic_type & ODM_RTL8822B)
odm_set_bb_reg(dm, R_0x8dc, BIT(5), 0x1);
else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
odm_set_bb_reg(dm, R_0xce8, BIT(13), 0x1);
else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
odm_set_bb_reg(dm, R_0x844, BIT(30) | BIT(29), 0x0);
} else {
if (dm->support_ic_type & ODM_RTL8822B)
odm_set_bb_reg(dm, R_0x8dc, BIT(5), 0x0);
else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
odm_set_bb_reg(dm, R_0xce8, BIT(13), 0x0);
else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
odm_set_bb_reg(dm, R_0x844, BIT(30) | BIT(29), 0x2);
}
if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
return;
if (dm->support_ic_type & ODM_RTL8822B)
odm_set_bb_reg(dm, R_0x8dc, BIT(5), 0x1);
else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
odm_set_bb_reg(dm, R_0xce8, BIT(13), 0x1);
else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
odm_set_bb_reg(dm, R_0x844, BIT(30) | BIT(29), 0x0);
}
void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,
@@ -374,10 +386,6 @@ void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,
"Enter debug mode: {1} {th_l2h_ini} {th_edcca_hl_diff}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"Leave debug mode: {2}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"Disable EDCCA thr: {3}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"Enable EDCCA thr: {4}\n");
goto out;
}
@@ -397,10 +405,6 @@ void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,
adaptivity->debug_mode = false;
dm->th_l2h_ini = adaptivity->th_l2h_ini_backup;
dm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup;
} else if (dm_value[0] == PHYDM_EDCCA_TH_PAUSE) {
adaptivity->edcca_en = false;
} else if (dm_value[0] == PHYDM_EDCCA_TH_RESUME) {
adaptivity->edcca_en = true;
} else if (dm_value[0] == PHYDM_ADAPT_MSG) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"debug_mode = %s, th_l2h_ini = %d\n",
@@ -454,14 +458,14 @@ boolean phydm_edcca_abort(void *dm_void)
u32 is_fw_in_psmode = false;
#endif
if (dm->pause_ability & ODM_BB_ADAPTIVITY) {
PHYDM_DBG(dm, DBG_ADPTVTY, "Return: Pause ADPTVTY in LV=%d\n",
dm->pause_lv_table.lv_adapt);
if (!(dm->support_ability & ODM_BB_ADAPTIVITY)) {
PHYDM_DBG(dm, DBG_ADPTVTY, "adaptivity disable\n");
return true;
}
if (!adapt->edcca_en) {
PHYDM_DBG(dm, DBG_ADPTVTY, "Disable EDCCA!!!\n");
if (dm->pause_ability & ODM_BB_ADAPTIVITY) {
PHYDM_DBG(dm, DBG_ADPTVTY, "Return: Pause ADPTVTY in LV=%d\n",
dm->pause_lv_table.lv_adapt);
return true;
}
@@ -477,43 +481,117 @@ boolean phydm_edcca_abort(void *dm_void)
return false;
}
void phydm_edcca_thre_calc_jgr3(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
u8 igi = dig_t->cur_ig_value;
s8 th_l2h = 0, th_h2l = 0;
if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
/*prevent pwdB clipping and result in Miss Detection*/
adapt->l2h_dyn_min = (u8)(dm->th_l2h_ini - ADC_BACKOFF);
if (igi < adapt->l2h_dyn_min)
th_l2h = igi + ADC_BACKOFF;
else
th_l2h = dm->th_l2h_ini;
th_h2l = th_l2h - dm->th_edcca_hl_diff;
} else {
th_l2h = MAX_2(igi + TH_L2H_DIFF_IGI, EDCCA_TH_L2H_LB);
th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL;
}
adapt->th_l2h = th_l2h;
adapt->th_h2l = th_h2l;
phydm_set_edcca_threshold(dm, adapt->th_h2l, adapt->th_l2h);
}
void phydm_edcca_thre_calc(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
u8 igi = dig_t->cur_ig_value;
s8 th_l2h = 0, th_h2l = 0;
s8 diff = 0, igi_target = adapt->igi_base;
if (dm->support_ic_type & ODM_IC_PWDB_EDCCA) {
/*@fix EDCCA hang issue*/
if (dm->support_ic_type & ODM_RTL8812) {
/*@ADC_mask disable*/
odm_set_bb_reg(dm, R_0x800, BIT(10), 1);
/*@ADC_mask enable*/
odm_set_bb_reg(dm, R_0x800, BIT(10), 0);
}
if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
/*@Limit IGI upper bound for adaptivity*/
phydm_dig_up_bound_lmt_en(dm);
diff = igi_target - (s8)igi;
th_l2h = dm->th_l2h_ini + diff;
if (th_l2h > 10)
th_l2h = 10;
th_h2l = th_l2h - dm->th_edcca_hl_diff;
} else {
th_l2h = 70 - igi;
th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL;
}
/*replace lower bound to prevent EDCCA always equal 1*/
if (th_h2l < adapt->h2l_lb)
th_h2l = adapt->h2l_lb;
if (th_l2h < adapt->l2h_lb)
th_l2h = adapt->l2h_lb;
PHYDM_DBG(dm, DBG_ADPTVTY,
"adapt_igi_up=0x%x, l2h_lb = %d dBm, h2l_lb = %d dBm\n",
adapt->adapt_igi_up,
IGI_2_DBM(adapt->l2h_lb + adapt->adapt_igi_up),
IGI_2_DBM(adapt->h2l_lb + adapt->adapt_igi_up));
} else { /* < JGR2 & N*/
if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
/*need to consider PwdB upper bound for 8814 later IC*/
adapt->l2h_dyn_min = (u8)(dm->th_l2h_ini + igi_target);
if (igi < adapt->l2h_dyn_min)
th_l2h = igi;
else
th_l2h = adapt->l2h_dyn_min;
th_h2l = th_l2h - dm->th_edcca_hl_diff;
} else {
th_l2h = MAX_2(igi + TH_L2H_DIFF_IGI, EDCCA_TH_L2H_LB);
th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL;
}
}
adapt->th_l2h = th_l2h;
adapt->th_h2l = th_h2l;
phydm_set_edcca_threshold(dm, adapt->th_h2l, adapt->th_l2h);
}
#endif
void phydm_set_edcca_threshold_api(void *dm_void, u8 IGI)
void phydm_set_edcca_threshold_api(void *dm_void)
{
#ifdef PHYDM_SUPPORT_ADAPTIVITY
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
s8 th_l2h_dmc = 0, th_h2l_dmc = 0;
s8 diff = 0, igi_target = 0x32;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
if (dm->support_ability & ODM_BB_ADAPTIVITY) {
if (!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
if (adaptivity->adajust_igi_level > IGI)
diff = adaptivity->adajust_igi_level - IGI;
if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
return;
th_l2h_dmc = dm->th_l2h_ini - diff + igi_target;
th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
} else {
diff = igi_target - (s8)IGI;
th_l2h_dmc = dm->th_l2h_ini + diff;
if (th_l2h_dmc > 10)
th_l2h_dmc = 10;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_edcca_thre_calc_jgr3(dm);
else
phydm_edcca_thre_calc(dm);
th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
/*replace lower bound to prevent EDCCA always equal 1*/
if (th_h2l_dmc < adaptivity->h2l_lb)
th_h2l_dmc = adaptivity->h2l_lb;
if (th_l2h_dmc < adaptivity->l2h_lb)
th_l2h_dmc = adaptivity->l2h_lb;
}
PHYDM_DBG(dm, DBG_ADPTVTY,
"API :IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n",
IGI, th_l2h_dmc, th_h2l_dmc);
phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
}
PHYDM_DBG(dm, DBG_ADPTVTY,
"API :IGI = 0x%x, th_l2h = %d, th_h2l = %d\n",
dm->dm_dig_table.cur_ig_value, adapt->th_l2h, adapt->th_h2l);
#endif
}
@@ -566,68 +644,83 @@ void phydm_adaptivity_init(void *dm_void)
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
/* @[Config Adaptivity]*/
if (!dm->edcca_mode) {
pr_debug("[%s] warning!\n", __func__);
dm->edcca_mode = &dm->u8_dummy;
dm->support_ability &= ~ODM_BB_ADAPTIVITY;
return;
}
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
if (!dm->carrier_sense_enable) {
if (dm->th_l2h_ini == 0)
phydm_set_l2h_th_ini(dm);
} else {
dm->th_l2h_ini = 0xa;
phydm_set_l2h_th_ini_carrier_sense(dm);
}
if (dm->th_edcca_hl_diff == 0)
dm->th_edcca_hl_diff = 7;
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
if (dm->wifi_test || *dm->mp_mode)
#else
if (dm->wifi_test & RT_WIFI_LOGO) /*@AP side use mib control*/
#endif
/*@even no adaptivity, we still enable EDCCA*/
adaptivity->edcca_en = false;
else
adaptivity->edcca_en = true;
if (dm->wifi_test & RT_WIFI_LOGO)
dm->support_ability &= ~ODM_BB_ADAPTIVITY;
if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE)
adaptivity->mode_cvrt_en = true;
else
adaptivity->mode_cvrt_en = false;
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
if (!dm->carrier_sense_enable) {
if (dm->th_l2h_ini == 0)
phydm_set_l2h_th_ini(dm);
} else {
phydm_set_l2h_th_ini_carrier_sense(dm);
}
if (dm->th_edcca_hl_diff == 0)
dm->th_edcca_hl_diff = 7;
if (dm->wifi_test || *dm->mp_mode)
dm->support_ability &= ~ODM_BB_ADAPTIVITY;
#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
if (dm->carrier_sense_enable) {
dm->th_l2h_ini = 0xa;
phydm_set_l2h_th_ini_carrier_sense(dm);
dm->th_edcca_hl_diff = 7;
} else {
dm->th_l2h_ini = dm->TH_L2H_default; /*set by mib*/
dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_default;
}
#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
if (!dm->carrier_sense_enable) {
if (dm->th_l2h_ini == 0)
phydm_set_l2h_th_ini(dm);
} else {
phydm_set_l2h_th_ini_carrier_sense(dm);
}
adaptivity->edcca_en = true;
if (dm->th_edcca_hl_diff == 0)
dm->th_edcca_hl_diff = 7;
#endif
adaptivity->is_adapt_en = false; /*@decide enable or not*/
adaptivity->debug_mode = false;
adaptivity->th_l2h_ini_mode2 = 20;
adaptivity->th_edcca_hl_diff_mode2 = 8;
adaptivity->th_l2h_ini_backup = dm->th_l2h_ini;
adaptivity->th_edcca_hl_diff_backup = dm->th_edcca_hl_diff;
adaptivity->igi_base = 0x32;
adaptivity->adapt_igi_up = 0;
adaptivity->h2l_lb = 0;
adaptivity->l2h_lb = 0;
adaptivity->adajust_igi_level = 0;
adaptivity->l2h_dyn_min = 0;
adaptivity->th_l2h = 0x7f;
adaptivity->th_h2l = 0x7f;
phydm_mac_edcca_state(dm, PHYDM_DONT_IGNORE_EDCCA);
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
adaptivity->adaptivity_dbg_port = 0x000;
odm_set_bb_reg(dm, R_0x1d6c, BIT(0), 1);
} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
if (dm->support_ic_type & ODM_IC_11N_SERIES)
adaptivity->adaptivity_dbg_port = 0x208;
} else {
else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
adaptivity->adaptivity_dbg_port = 0x209;
}
if (dm->support_ic_type & ODM_IC_11N_SERIES &&
!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
/*@interfernce need > 2^x us, and then EDCCA will be 1*/
#if 0
/*odm_set_bb_reg(dm, 0x948, 0x1c00, 0x7);*/
#endif
if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) {
/*set to page B1*/
odm_set_bb_reg(dm, R_0xe28, BIT(30), 0x1);
@@ -640,10 +733,6 @@ void phydm_adaptivity_init(void *dm_void)
}
} else if (dm->support_ic_type & ODM_IC_11AC_SERIES &&
!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
/*@interfernce need > 2^x us, and then EDCCA will be 1*/
#if 0
/*odm_set_bb_reg(dm, 0x900, 0x70000000, 0x7);*/
#endif
/*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
odm_set_bb_reg(dm, R_0x944, BIT(29) | BIT(28), 0x1);
}
@@ -657,11 +746,14 @@ void phydm_adaptivity_init(void *dm_void)
phydm_set_edcca_threshold(dm, 0x7f, 0x7f);
}
/*@whether to ignore EDCCA*/
phydm_mac_edcca_state(dm, PHYDM_DONT_IGNORE_EDCCA);
/*@forgetting factor setting*/
phydm_set_forgetting_factor(dm);
/*pwdb mode setting with 0: mean, 1:max*/
phydm_set_pwdb_mode(dm);
/*@EDCCA behavior based on maximum or mean power*/
phydm_edcca_decision_opt(dm);
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
adaptivity->igi_up_bound_lmt_val = 180;
@@ -677,88 +769,46 @@ void phydm_adaptivity(void *dm_void)
{
#ifdef PHYDM_SUPPORT_ADAPTIVITY
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
u8 igi = dig_t->cur_ig_value;
s8 th_l2h_dmc = 0, th_h2l_dmc = 0;
s8 diff = 0, igi_target = adapt->igi_base;
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
if (phydm_edcca_abort(dm))
return;
/*@fix AC series when enable EDCCA hang issue*/
if (dm->support_ic_type & ODM_RTL8812) {
odm_set_bb_reg(dm, R_0x800, BIT(10), 1); /*@ADC_mask disable*/
odm_set_bb_reg(dm, R_0x800, BIT(10), 0); /*@ADC_mask enable*/
}
if (!adapt->debug_mode)
phydm_check_adaptivity(dm); /*@Check adaptivity enable*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
phydm_check_adaptivity(dm); /*@Check adaptivity enable*/
#endif
PHYDM_DBG(dm, DBG_ADPTVTY, "%s ====>\n", __func__);
PHYDM_DBG(dm, DBG_ADPTVTY, "th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
dm->th_l2h_ini, dm->th_edcca_hl_diff);
PHYDM_DBG(dm, DBG_ADPTVTY, "is_adapt_en = %d, debug_mode = %d\n",
adapt->is_adapt_en, adapt->debug_mode);
if (dm->support_ic_type & ODM_IC_PWDB_EDCCA) {
/*@Limit IGI upper bound for adaptivity*/
phydm_dig_up_bound_lmt_en(dm);
PHYDM_DBG(dm, DBG_ADPTVTY, "mode = %s, debug_mode = %d\n",
(*dm->edcca_mode ?
(dm->carrier_sense_enable ?
"CARRIER SENSE" :
"ADAPTIVITY") :
"NORMAL"),
adapt->debug_mode);
diff = igi_target - (s8)igi;
th_l2h_dmc = dm->th_l2h_ini + diff;
if (th_l2h_dmc > 10 && adapt->is_adapt_en)
th_l2h_dmc = 10;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_edcca_thre_calc_jgr3(dm);
else
phydm_edcca_thre_calc(dm);
th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
/*replace lower bound to prevent EDCCA always equal 1*/
if (th_h2l_dmc < adapt->h2l_lb)
th_h2l_dmc = adapt->h2l_lb;
if (th_l2h_dmc < adapt->l2h_lb)
th_l2h_dmc = adapt->l2h_lb;
if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE)
PHYDM_DBG(dm, DBG_ADPTVTY,
"adapt_igi_up=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n",
adapt->adapt_igi_up, adapt->h2l_lb, adapt->l2h_lb);
} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
adapt->adajust_igi_level = (u8)(dm->th_l2h_ini - ADC_BACKOFF);
if (adapt->is_adapt_en) {
diff = adapt->adajust_igi_level > igi ?
adapt->adajust_igi_level - igi :
0;
th_l2h_dmc = dm->th_l2h_ini - diff;
th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
} else {
th_l2h_dmc = igi + 8 > adapt->th_l2h_ini_backup ?
igi + 8 :
adapt->th_l2h_ini_backup;
th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
}
} else {
/*we need to consider PwdB upper bound for 8814 later IC*/
adapt->adajust_igi_level = (u8)(dm->th_l2h_ini + igi_target -
PWDB_UPPER_BOUND + DFIR_LOSS);
if (adapt->adajust_igi_level > igi && adapt->is_adapt_en)
diff = adapt->adajust_igi_level - igi;
else if (!adapt->is_adapt_en)
diff = 0x3e - igi;
th_l2h_dmc = dm->th_l2h_ini - diff + igi_target;
if (dm->support_ic_type & ODM_RTL8198F) /* @need to check */
th_l2h_dmc -= 4;
th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
PHYDM_DBG(dm, DBG_ADPTVTY, "adajust_igi_level= 0x%x\n",
adapt->adajust_igi_level);
}
adapt->th_l2h = th_l2h_dmc;
adapt->th_h2l = th_h2l_dmc;
PHYDM_DBG(dm, DBG_ADPTVTY, "IGI=0x%x, th_l2h_dmc=%d, th_h2l_dmc=%d\n",
igi, th_l2h_dmc, th_h2l_dmc);
phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
if (adapt->is_adapt_en)
odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 1);
return;
"th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
dm->th_l2h_ini, dm->th_edcca_hl_diff);
if (dm->support_ic_type & ODM_IC_PWDB_EDCCA)
PHYDM_DBG(dm, DBG_ADPTVTY,
"IGI = 0x%x, th_l2h = %d dBm, th_h2l = %d dBm\n",
dig_t->cur_ig_value,
IGI_2_DBM(adapt->th_l2h + dig_t->cur_ig_value),
IGI_2_DBM(adapt->th_h2l + dig_t->cur_ig_value));
else
PHYDM_DBG(dm, DBG_ADPTVTY,
"IGI = 0x%x, th_l2h = %d dBm, th_h2l = %d dBm\n",
dig_t->cur_ig_value,
IGI_2_DBM(adapt->th_l2h),
IGI_2_DBM(adapt->th_h2l));
#endif
}

32
hal/phydm/phydm_adaptivity.h
View File

@@ -26,13 +26,15 @@
#ifndef __PHYDMADAPTIVITY_H__
#define __PHYDMADAPTIVITY_H__
#define ADAPTIVITY_VERSION "9.6.01" /*@20180814 changed by Kevin,
*add phydm_edcca_abort func.
#define ADAPTIVITY_VERSION "9.7.07" /*@20190321 changed by Kevin,
*add 8721D threshold l2h init
*/
#define PWDB_UPPER_BOUND 7
#define DFIR_LOSS 7
#define ADC_BACKOFF 12
#define EDCCA_TH_L2H_LB 48
#define TH_L2H_DIFF_IGI 8
#define EDCCA_HL_DIFF_NORMAL 8
#define IGI_2_DBM(igi) (igi - 110)
/*@ [PHYDM-337][Old IC] EDCCA TH = IGI + REG setting*/
#define ODM_IC_PWDB_EDCCA (ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |\
ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8812)
@@ -53,6 +55,11 @@ enum phydm_regulation_type {
};
#endif
enum phydm_edcca_mode {
PHYDM_EDCCA_NORMAL_MODE = 0,
PHYDM_EDCCA_ADAPT_MODE = 1
};
enum phydm_adapinfo {
PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,
PHYDM_ADAPINFO_TH_L2H_INI,
@@ -67,37 +74,32 @@ enum phydm_mac_edcca_type {
PHYDM_DONT_IGNORE_EDCCA = 1
};
enum phydm_adaptivity_mode {
enum phydm_adaptivity_debug_mode {
PHYDM_ADAPT_MSG = 0,
PHYDM_ADAPT_DEBUG = 1,
PHYDM_ADAPT_RESUME = 2,
PHYDM_EDCCA_TH_PAUSE = 3,
PHYDM_EDCCA_TH_RESUME = 4
};
struct phydm_adaptivity_struct {
boolean mode_cvrt_en;
s8 th_l2h_ini_backup;
s8 th_edcca_hl_diff_backup;
s8 igi_base;
s8 h2l_lb;
s8 l2h_lb;
u8 ap_num_th;
u8 adajust_igi_level;
u8 l2h_dyn_min;
u32 adaptivity_dbg_port; /*N:0x208, AC:0x209*/
u8 debug_mode;
u16 igi_up_bound_lmt_cnt; /*@When igi_up_bound_lmt_cnt !=0, limit IGI upper bound to "adapt_igi_up"*/
u16 igi_up_bound_lmt_val; /*@max value of igi_up_bound_lmt_cnt*/
boolean igi_lmt_en;
u8 adapt_igi_up;
u32 rvrt_val[2];
u32 rvrt_val[2]; /*@all rvrt_val for pause API must set to u32*/
s8 th_l2h;
s8 th_h2l;
u8 regulation_2g;
u8 regulation_5g;
boolean is_adapt_en;
boolean edcca_en;
s8 th_l2h_ini_mode2;
s8 th_edcca_hl_diff_mode2;
};
#ifdef PHYDM_SUPPORT_ADAPTIVITY
@@ -107,7 +109,7 @@ void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,
void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len);
#endif
void phydm_set_edcca_threshold_api(void *dm_void, u8 IGI);
void phydm_set_edcca_threshold_api(void *dm_void);
void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
u32 value);

2322
hal/phydm/phydm_adc_sampling.c
View File

File diff suppressed because it is too large Load Diff

144
hal/phydm/phydm_adc_sampling.h
View File

@@ -28,17 +28,32 @@
#if (PHYDM_LA_MODE_SUPPORT)
#define DYNAMIC_LA_MODE "3.0"
/* fix compile time flag*/
#define DYNAMIC_LA_MODE "4.1"
/* @1 ============================================================
* 1 Definition
* 1 ============================================================
*/
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
#if (RTL8197F_SUPPORT || RTL8198F_SUPPORT || RTL8197G_SUPPORT)
#define PHYDM_COMPILE_LA_STORE_IN_IMEM
#endif
#endif
#define PHYDM_LA_STORE_IN_IMEM_IC (ODM_RTL8197F | ODM_RTL8198F | ODM_RTL8197G)
#define FULL_BUFF_MODE_SUPPORT (ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8822C |\
ODM_RTL8812F | ODM_RTL8814B)
struct rt_adcsmp_string {
u32 *octet;
u32 length;
u32 buffer_size;
u32 start_pos;
u32 end_pos; /*@buf addr*/
/* @ ============================================================
* enumrate
* ============================================================
*/
enum la_dump_mode {
LA_BB_ADC_DUMP = 0,
LA_MAC_DBG_DUMP = 1
};
enum rt_adcsmp_trig_sel {
@@ -67,85 +82,108 @@ enum la_buff_mode {
ADCSMP_BUFF_ALL = 1 /*Only use in MP Driver*/
};
/* @ ============================================================
* structure
* ============================================================
*/
struct rt_adcsmp_string {
u32 *octet;
u32 length;
u32 buffer_size;
u32 start_pos;
u32 end_pos; /*@buf addr*/
};
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
struct la_adv_trig {
boolean la_adv_bbtrigger_en;
boolean la_ori_bb_dis;
u8 la_and1_sel;
u8 la_and1_val;
boolean la_and1_inv;
u8 la_and2_sel;
u8 la_and2_val;
boolean la_and2_inv;
u8 la_and3_sel;
u8 la_and3_val;
boolean la_and3_inv;
u32 la_and4_mask;
u32 la_and4_bitmap;
boolean la_and4_inv;
};
#endif
struct rt_adcsmp {
struct rt_adcsmp_string adc_smp_buf;
enum rt_adcsmp_state adc_smp_state;
enum la_buff_mode la_buff_mode;
enum la_dump_mode la_dump_mode;
u8 la_trig_mode;
u32 la_trig_sig_sel;
u8 la_dma_type;
u32 la_trigger_time;
/*
* @1.BB mode: for debug port header sel;
* 2.MAC mode: for reference mask
*/
/*@1.BB mode: Dbg port header sel, 2.MAC mode: for reference mask*/
u32 la_mac_mask_or_hdr_sel;
u32 la_dbg_port;
u8 la_trigger_edge;
u8 la_smp_rate;
u32 la_count;
u8 is_bb_trigger;
u8 la_work_item_index;
boolean la_en_new_bbtrigger;
boolean la_ori_bb_dis;
u8 la_and1_sel;
u8 la_and1_val;
u8 la_and2_sel;
u8 la_and2_val;
u8 la_and3_sel;
u8 la_and3_val;
u32 la_and4_en;
u32 la_and4_val;
boolean is_fake_trig;
u32 smp_number;
u32 smp_number_max;
u32 txff_page;
boolean is_la_print;
boolean en_fake_trig;
#if (RTL8197F_SUPPORT)
u32 backup_dma;
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
RT_WORK_ITEM adc_smp_work_item;
RT_WORK_ITEM adc_smp_work_item_1;
u8 la_work_item_index;
RT_WORK_ITEM adc_smp_work_item;
RT_WORK_ITEM adc_smp_work_item_1;
#endif
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
struct la_adv_trig adv_trig_table;
#endif
};
/* @ ============================================================
* Function Prototype
* ============================================================
*/
void phydm_la_set(void *dm_void);
void phydm_la_cmd(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len);
void phydm_la_stop(void *dm_void);
void phydm_la_init(void *dm_void);
void adc_smp_de_init(void *dm_void);
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
void adc_smp_work_item_callback(
void *context);
void adc_smp_work_item_callback(void *context);
#endif
void adc_smp_set(void *dm_void, u8 trig_mode, u32 trig_sig_sel,
u8 dma_data_sig_sel, u32 trig_time, u16 polling_time);
#if 0
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
enum rt_status
adc_smp_query(void *dm_void, ULONG info_buf_length, void *info_buf,
PULONG bytes_written);
enum rt_status adc_smp_query(void *dm_void, ULONG info_buf_length,
void *info_buf, PULONG bytes_written);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
void adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused);
s32 adc_smp_get_sample_counts(void *dm_void);
s32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len,
u32 idx);
#endif
void adc_smp_stop(void *dm_void);
void phydm_la_bb_adv_reset_jgr3(void *dm_void);
void adc_smp_init(void *dm_void);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
void adc_smp_de_init(void *dm_void);
#endif
void phydm_la_set_buff_mode(void *dm_void, enum la_buff_mode mode);
void phydm_la_mode_bb_setting(void *dm_void, boolean en_fake_trig);
void phydm_la_mode_set_trigger_time(void *dm_void, u32 trigger_time_mu_sec);
void phydm_lamode_trigger_cmd(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void phydm_la_pre_run(void *dm_void);
#endif
#endif

645
hal/phydm/phydm_antdiv.c
View File

File diff suppressed because it is too large Load Diff

14
hal/phydm/phydm_antdiv.h
View File

@@ -136,6 +136,9 @@
#define FORCE_RSSI_DIFF 10
#define HT_IDX 16
#define VHT_IDX 20
#define CSI_ON 1
#define CSI_OFF 0
@@ -260,6 +263,10 @@ struct phydm_fat_struct {
u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_ht_cnt[HT_IDX];
u16 aux_ht_cnt[HT_IDX];
u16 main_vht_cnt[VHT_IDX];
u16 aux_vht_cnt[VHT_IDX];
u16 main_sum[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_sum[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_cnt[ODM_ASSOCIATE_ENTRY_NUM];
@@ -270,10 +277,11 @@ struct phydm_fat_struct {
u16 aux_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
u8 rx_idle_ant;
u8 rx_idle_ant2;
u8 rvrt_val;
u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
u8 ant_div_on_off;
u8 div_path_type;
boolean is_become_linked;
boolean get_stats;
u32 min_max_rssi;
u8 idx_ant_div_counter_2g;
u8 idx_ant_div_counter_5g;
@@ -447,6 +455,10 @@ void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(void *dm_void,
#ifdef ODM_EVM_ENHANCE_ANTDIV
void phydm_evm_sw_antdiv_init(void *dm_void);
void phydm_rx_rate_for_antdiv(void *dm_void, void *pkt_info_void);
void phydm_antdiv_reset_rx_rate(void *dm_void);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void phydm_evm_antdiv_callback(struct phydm_timer_list *timer);

1012
hal/phydm/phydm_api.c
View File

File diff suppressed because it is too large Load Diff

37
hal/phydm/phydm_api.h
View File

@@ -26,12 +26,21 @@
#ifndef __PHYDM_API_H__
#define __PHYDM_API_H__
#define PHYDM_API_VERSION "1.0" /* @2017.07.10 Dino, Add phydm_api.h*/
/* 2019.03.05 add reset txagc API for jgr3 ics*/
#define PHYDM_API_VERSION "2.1"
/* @1 ============================================================
* 1 Definition
* 1 ============================================================
*/
#define N_IC_TX_OFFEST_5_BIT (ODM_RTL8188E | ODM_RTL8192E)
#define N_IC_TX_OFFEST_6_BIT (ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B |\
ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8195A |\
ODM_RTL8188F)
#define N_IC_TX_OFFEST_7_BIT (ODM_RTL8721D | ODM_RTL8710C)
#define CN_CNT_MAX 10 /*@max condition number threshold*/
#define FUNC_ENABLE 1
@@ -98,13 +107,9 @@ void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
void phydm_pathb_q_matrix_rotate_en(void *dm_void);
void phydm_pathb_q_matrix_rotate(void *dm_void, u16 phase_idx);
void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path);
void phydm_config_ofdm_rx_path(void *dm_void, u32 path);
void phydm_config_ofdm_rx_path(void *dm_void, enum bb_path path);
void phydm_config_cck_rx_path(void *dm_void, enum bb_path path);
@@ -113,6 +118,10 @@ void phydm_config_cck_rx_antenna_init(void *dm_void);
void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void phydm_config_ofdm_tx_path(void *dm_void, enum bb_path path);
void phydm_config_cck_tx_path(void *dm_void, enum bb_path path);
void phydm_tx_2path(void *dm_void);
void phydm_stop_3_wire(void *dm_void, u8 set_type);
@@ -160,10 +169,11 @@ u8 phydm_phystat_rpt_jgr3(void *dm_void, enum phystat_rpt info,
enum rf_path ant_path);
void phydm_user_position_for_sniffer(void *dm_void, u8 user_position);
void phydm_txagc_power_limit(void *dm_void, boolean is_bf, u8 ss, u8 pwr);
#endif
#ifdef PHYDM_COMMON_API_SUPPORT
void phydm_reset_txagc(void *dm_void);
boolean
phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path,
boolean is_positive);
@@ -179,8 +189,19 @@ phydm_api_switch_bw_channel(void *dm_void, u8 central_ch, u8 primary_ch_idx,
boolean
phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path,
boolean is_tx2_path);
enum bb_path tx_path_ctrl);
#endif
#ifdef CONFIG_MCC_DM
#ifdef DYN_ANT_WEIGHTING_SUPPORT
void phydm_dynamic_ant_weighting_mcc_8822b(void *dm_void);
#endif /*#ifdef DYN_ANT_WEIGHTING_SUPPORT*/
void phydm_fill_mcccmd(void *dm_void, u8 regid, u16 reg_add,
u8 val0, u8 val1);
u8 phydm_check(void *dm_void);
void phydm_mcc_init(void *dm_void);
void phydm_mcc_switch(void *dm_void);
#endif /*#ifdef CONFIG_MCC_DM*/
#endif

84
hal/phydm/phydm_auto_dbg.c
View File

@@ -64,7 +64,7 @@ void phydm_auto_check_hang_engine_n(
struct n_dbgport_803 dbgport_803 = {0};
u32 value32_tmp = 0, value32_tmp_2 = 0;
u8 i;
u32 curr_dbg_port_val[DBGPORT_CHK_NUM];
u32 curr_dbg_port_val[DBGPORT_CHK_NUM] = {0, 0, 0, 0, 0, 0};
u16 curr_ofdm_t_cnt;
u16 curr_ofdm_r_cnt;
u16 curr_cck_t_cnt;
@@ -564,7 +564,7 @@ void phydm_dbg_port_dump_jgr3(void *dm_void, u32 *_used, char *output,
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
u32 dbg_port_idx_all[3] = {0x000, 0x001, 0x002};
/*u32 dbg_port_idx_all[3] = {0x000, 0x001, 0x002};*/
u32 val = 0;
u32 dbg_port_idx = 0;
u32 i = 0;
@@ -572,9 +572,10 @@ void phydm_dbg_port_dump_jgr3(void *dm_void, u32 *_used, char *output,
if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
return;
PDM_SNPF(out_len, used, output + used, out_len - used,
"%-16s = %s\n", "DbgPort index", "Value");
PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
"%-17s = %s\n", "DbgPort index", "Value");
#if 0
/*0x000/0x001/0x002*/
for (i = 0; i < 3; i++) {
dbg_port_idx = dbg_port_idx_all[i];
@@ -585,13 +586,13 @@ void phydm_dbg_port_dump_jgr3(void *dm_void, u32 *_used, char *output,
phydm_release_bb_dbg_port(dm);
}
}
/*0x3a0/0x3a1/.../0x3ab/0x3ac*/
for (dbg_port_idx = 0x3a0; dbg_port_idx <= 0x3ac; dbg_port_idx++) {
#endif
for (dbg_port_idx = 0x0; dbg_port_idx <= 0xfff; dbg_port_idx++) {
if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port_idx)) {
val = phydm_get_bb_dbg_port_val(dm);
PDM_SNPF(out_len, used, output + used, out_len - used,
"0x%-15x = 0x%x\n", dbg_port_idx, val);
PDM_VAST_SNPF(out_len, used, output + used,
out_len - used,
"0x%-15x = 0x%x\n", dbg_port_idx, val);
phydm_release_bb_dbg_port(dm);
}
}
@@ -599,6 +600,42 @@ void phydm_dbg_port_dump_jgr3(void *dm_void, u32 *_used, char *output,
*_out_len = out_len;
}
#endif
void phydm_dbg_port_dump(void *dm_void, u32 *_used, char *output, u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
"------ BB debug port start ------\n");
switch (dm->ic_ip_series) {
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
case PHYDM_IC_JGR3:
phydm_dbg_port_dump_jgr3(dm, &used, output, &out_len);
break;
#endif
#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
case PHYDM_IC_AC:
phydm_dbg_port_dump_ac(dm, &used, output, &out_len);
break;
#endif
#if (ODM_IC_11N_SERIES_SUPPORT == 1)
case PHYDM_IC_N:
phydm_dbg_port_dump_n(dm, &used, output, &out_len);
break;
#endif
default:
break;
}
*_used = used;
*_out_len = out_len;
}
void phydm_auto_dbg_console(
void *dm_void,
char input[][16],
@@ -621,32 +658,7 @@ void phydm_auto_dbg_console(
} else if (var1[0] == 1) {
PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
if (var1[1] == 1) {
switch (dm->ic_ip_series) {
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
case PHYDM_IC_JGR3:
phydm_dbg_port_dump_jgr3(dm, &used, output,
&out_len);
break;
#endif
#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
case PHYDM_IC_AC:
phydm_dbg_port_dump_ac(dm, &used, output,
&out_len);
break;
#endif
#if (ODM_IC_11N_SERIES_SUPPORT == 1)
case PHYDM_IC_N:
phydm_dbg_port_dump_n(dm, &used, output,
&out_len);
break;
#endif
default:
break;
}
phydm_dbg_port_dump(dm, &used, output, &out_len);
} else if (var1[1] == 2) {
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
PDM_SNPF(out_len, used, output + used,
@@ -703,7 +715,7 @@ void phydm_auto_dbg_engine_init(void *dm_void)
u16 dbg_port_table[DBGPORT_CHK_NUM] = {0x0, 0x803, 0x208, 0xab0,
0xab1, 0xab2};
PHYDM_DBG(dm, ODM_COMP_API, "%s ======>n", __func__);
PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
odm_move_memory(dm, &atd_t->dbg_port_table[0],
&dbg_port_table[0], (DBGPORT_CHK_NUM * 2));

2
hal/phydm/phydm_auto_dbg.h
View File

@@ -99,6 +99,8 @@ struct phydm_auto_dbg_struct {
* 1 ============================================================
*/
void phydm_dbg_port_dump(void *dm_void, u32 *used, char *output, u32 *out_len);
void phydm_auto_dbg_console(
void *dm_void,
char input[][16],

52
hal/phydm/phydm_cck_pd.c
View File

@@ -502,8 +502,6 @@ void phydm_cck_pd_init_type3(void *dm_void)
cckpd_t->cck_cs_ratio_20m_2r = (u8)((reg_tmp & 0x3e0) >> 5);
cckpd_t->cck_cs_ratio_40m_1r = (u8)((reg_tmp & 0x1f00000) >> 20);
cckpd_t->cck_cs_ratio_40m_2r = (u8)((reg_tmp & 0x3e000000) >> 25);
phydm_set_cckpd_lv_type3(dm, CCK_PD_LV_0);
}
#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE3*/
@@ -664,7 +662,7 @@ void phydm_set_cck_pd_lv_type4(void *dm_void, enum cckpd_lv lv)
/*@pr_debug("[%s] warning!\n", __func__);*/
break;
}
phydm_write_cck_pd_type4(dm, lv, cck_mode);
phydm_write_cck_pd_type4(dm, lv, cck_mode);
}
void phydm_read_cckpd_para_type4(void *dm_void)
@@ -779,7 +777,6 @@ void phydm_cckpd_type4(void *dm_void)
cckpd_t->cck_pd_table_jgr3[cckpd_t->cck_bw]
[cckpd_t->cck_n_rx - 1][0][lv]);
}
phydm_read_cckpd_para_type4(dm);
}
@@ -905,6 +902,50 @@ void phydm_cck_pd_init_type4(void *dm_void)
#endif
}
}
void phydm_invalid_cckpd_type4(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
u8 val = 0;
u8 i = 0;
u8 k = 0;
PHYDM_DBG(dm, DBG_CCKPD, "[%s]======>\n", __func__);
for (i = 0; i < CCK_PD_LV_MAX; i++) {
for (k = RF_PATH_A; k < dm->num_rf_path; k++) {
val = cckpd_t->cck_pd_table_jgr3[0][k][1][i];
if (val == INVALID_CS_RATIO_0)
cckpd_t->cck_pd_table_jgr3[0][k][1][i] = 28;
else if (val == INVALID_CS_RATIO_1)
cckpd_t->cck_pd_table_jgr3[0][k][1][i] = 30;
else if (val > MAXVALID_CS_RATIO)
cckpd_t->cck_pd_table_jgr3[0][k][1][i] =
MAXVALID_CS_RATIO;
val = cckpd_t->cck_pd_table_jgr3[1][k][1][i];
if (val == INVALID_CS_RATIO_0)
cckpd_t->cck_pd_table_jgr3[1][k][1][i] = 28;
else if (val == INVALID_CS_RATIO_1)
cckpd_t->cck_pd_table_jgr3[1][k][1][i] = 30;
else if (val > MAXVALID_CS_RATIO)
cckpd_t->cck_pd_table_jgr3[1][k][1][i] =
MAXVALID_CS_RATIO;
val = cckpd_t->cck_pd_table_jgr3[0][k][0][i];
if (val > MAXVALID_PD_THRES)
cckpd_t->cck_pd_table_jgr3[0][k][0][i] =
MAXVALID_PD_THRES;
val = cckpd_t->cck_pd_table_jgr3[1][k][0][i];
if (val > MAXVALID_PD_THRES)
cckpd_t->cck_pd_table_jgr3[1][k][0][i] =
MAXVALID_PD_THRES;
}
}
}
#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE4*/
void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len)
@@ -1070,11 +1111,14 @@ void phydm_cck_pd_init(void *dm_void)
#ifdef PHYDM_COMPILE_CCKPD_TYPE3
case 3:
phydm_cck_pd_init_type3(dm);
phydm_set_cckpd_lv_type3(dm, CCK_PD_LV_0);
break;
#endif
#ifdef PHYDM_COMPILE_CCKPD_TYPE4
case 4:
phydm_cck_pd_init_type4(dm);
phydm_invalid_cckpd_type4(dm);
phydm_set_cck_pd_lv_type4(dm, CCK_PD_LV_0);
break;
#endif
default:

12
hal/phydm/phydm_cck_pd.h
View File

@@ -26,7 +26,7 @@
#ifndef __PHYDM_CCK_PD_H__
#define __PHYDM_CCK_PD_H__
#define CCK_PD_VERSION "3.1"
#define CCK_PD_VERSION "3.3" /* @ modify invalid type4 API*/
/*@
* 1 ============================================================
@@ -35,6 +35,10 @@
*/
#define CCK_FA_MA_RESET 0xffffffff
#define INVALID_CS_RATIO_0 27 /* @ only for type4 ICs*/
#define INVALID_CS_RATIO_1 29 /* @ only for type4 ICs*/
#define MAXVALID_CS_RATIO 31
#define MAXVALID_PD_THRES 255
/*@Run time flag of CCK_PD HW type*/
#define CCK_PD_IC_TYPE1 (ODM_RTL8188E | ODM_RTL8812 | ODM_RTL8821 |\
ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8814A |\
@@ -44,7 +48,7 @@
#define CCK_PD_IC_TYPE2 (ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8723D |\
ODM_RTL8710B | ODM_RTL8195B) /*extend 0xaaa*/
#define CCK_PD_IC_TYPE3 (ODM_RTL8192F | ODM_RTL8721D)
#define CCK_PD_IC_TYPE3 (ODM_RTL8192F | ODM_RTL8721D | ODM_RTL8710C)
/*@extend for different bw & path*/
#define CCK_PD_IC_TYPE4 ODM_IC_JGR3_SERIES /*@extend for different bw & path*/
@@ -62,7 +66,7 @@
#define PHYDM_COMPILE_CCKPD_TYPE2 /*@extend 0xaaa*/
#endif
#if (RTL8192F_SUPPORT || RTL8721D_SUPPORT)
#if (RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
#define PHYDM_COMPILE_CCKPD_TYPE3 /*@extend for different & path*/
#endif
@@ -106,7 +110,7 @@ struct phydm_cckpd_struct {
u8 cckpd_hw_type;
u8 cur_cck_cca_thres; /*@current cck_pd value 0xa0a*/
u32 cck_fa_ma;
u8 rvrt_val;
u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
u8 pause_lv;
u8 cck_n_rx;
enum channel_width cck_bw;

164
hal/phydm/phydm_cck_rx_pathdiv.c Normal file
View File

@@ -0,0 +1,164 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*@************************************************************
* include files
************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT /* @PHYDM-342*/
void phydm_cck_rx_pathdiv_manaul(void *dm_void, boolean en_cck_rx_pathdiv)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
/* @Can not apply for 98F/14B/97G from DD YC*/
if (en_cck_rx_pathdiv) {
odm_set_bb_reg(dm, R_0x1a14, BIT(7), 0x0);
odm_set_bb_reg(dm, R_0x1a74, BIT(8), 0x1);
} else {
odm_set_bb_reg(dm, R_0x1a14, BIT(7), 0x1);
odm_set_bb_reg(dm, R_0x1a74, BIT(8), 0x0);
}
}
void phydm_cck_rx_pathdiv_watchdog(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
u8 rssi_th = 0;
u32 rssi_a = 0, rssi_b = 0, rssi_avg = 0;
if (!cckrx_t->en_cck_rx_pathdiv)
return;
rssi_a = PHYDM_DIV(cckrx_t->path_a_sum, cckrx_t->path_a_cnt);
rssi_b = PHYDM_DIV(cckrx_t->path_b_sum, cckrx_t->path_b_cnt);
rssi_avg = (rssi_a + rssi_b) >> 1;
pr_debug("Rx-A:%d, Rx-B:%d, avg:%d\n", rssi_a, rssi_b, rssi_avg);
cckrx_t->path_a_cnt = 0;
cckrx_t->path_a_sum = 0;
cckrx_t->path_b_cnt = 0;
cckrx_t->path_b_sum = 0;
if (fa_t->cnt_all >= 100)
rssi_th = cckrx_t->rssi_fa_th;
else
rssi_th = cckrx_t->rssi_th;
if (dm->phy_dbg_info.num_qry_beacon_pkt > 14 && rssi_avg <= rssi_th)
phydm_cck_rx_pathdiv_manaul(dm, true);
else
phydm_cck_rx_pathdiv_manaul(dm, false);
}
void phydm_cck_rx_pathdiv_init(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
cckrx_t->en_cck_rx_pathdiv = false;
cckrx_t->path_a_cnt = 0;
cckrx_t->path_a_sum = 0;
cckrx_t->path_b_cnt = 0;
cckrx_t->path_b_sum = 0;
cckrx_t->rssi_fa_th = 45;
cckrx_t->rssi_th = 25;
}
void phydm_process_rssi_for_cck_rx_pathdiv(void *dm_void, void *phy_info_void,
void *pkt_info_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_phyinfo_struct *phy_info = NULL;
struct phydm_perpkt_info_struct *pktinfo = NULL;
struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_match_bssid))
return;
if (pktinfo->is_cck_rate)
return;
cckrx_t->path_a_sum += phy_info->rx_mimo_signal_strength[0];
cckrx_t->path_a_cnt++;
cckrx_t->path_b_sum += phy_info->rx_mimo_signal_strength[1];
cckrx_t->path_b_cnt++;
}
void phydm_cck_rx_pathdiv_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
char help[] = "-h";
u32 var1[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u8 i = 0;
if (!(dm->support_ic_type & ODM_RTL8822C))
return;
for (i = 0; i < 3; i++) {
if (input[i + 1])
PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
}
if ((strcmp(input[1], help) == 0)) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"CCK rx pathdiv manual on: {1} {En}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"CCK rx pathdiv watchdog on: {2} {En}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"CCK rx pathdiv rssi_th : {3} {th} {fa_th}\n");
} else if (var1[0] == 1) {
if (var1[1] == 1)
phydm_cck_rx_pathdiv_manaul(dm, true);
else
phydm_cck_rx_pathdiv_manaul(dm, false);
} else if (var1[0] == 2) {
if (var1[1] == 1) {
cckrx_t->en_cck_rx_pathdiv = true;
} else {
cckrx_t->en_cck_rx_pathdiv = false;
phydm_cck_rx_pathdiv_manaul(dm, false);
}
} else if (var1[0] == 3) {
cckrx_t->rssi_th = (u8)var1[1];
cckrx_t->rssi_fa_th = (u8)var1[2];
}
*_used = used;
*_out_len = out_len;
}
#endif

67
hal/phydm/phydm_cck_rx_pathdiv.h Normal file
View File

@@ -0,0 +1,67 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_CCK_RX_PATHDIV_H__
#define __PHYDM_CCK_RX_PATHDIV_H__
#define CCK_RX_PATHDIV_VERSION "1.1"
/* @1 ============================================================
* 1 Definition
* 1 ============================================================
*/
/* @1 ============================================================
* 1 structure
* 1 ============================================================
*/
struct phydm_cck_rx_pathdiv {
boolean en_cck_rx_pathdiv;
u32 path_a_sum;
u32 path_b_sum;
u16 path_a_cnt;
u16 path_b_cnt;
u8 rssi_fa_th;
u8 rssi_th;
};
/* @1 ============================================================
* 1 enumeration
* 1 ============================================================
*/
/* @1 ============================================================
* 1 function prototype
* 1 ============================================================
*/
void phydm_cck_rx_pathdiv_watchdog(void *dm_void);
void phydm_cck_rx_pathdiv_init(void *dm_void);
void phydm_process_rssi_for_cck_rx_pathdiv(void *dm_void, void *phy_info_void,
void *pkt_info_void);
void phydm_cck_rx_pathdiv_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif

595
hal/phydm/phydm_ccx.c
View File

@@ -389,7 +389,7 @@ void phydm_nhm_trigger(void *dm_void)
nhm_reg1 = R_0x890;
PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
/*Trigger NHM*/
/* @Trigger NHM*/
pdm_set_reg(dm, nhm_reg1, BIT(1), 0);
pdm_set_reg(dm, nhm_reg1, BIT(1), 1);
ccx->nhm_trigger_time = dm->phydm_sys_up_time;
@@ -403,12 +403,6 @@ phydm_nhm_check_rdy(void *dm_void)
struct dm_struct *dm = (struct dm_struct *)dm_void;
boolean is_ready = false;
u32 reg1 = 0, reg1_bit = 0;
#if (ENV_MNTR_DBG || ENV_MNTR_DBG_1)
u16 i = 0;
u64 start_time = 0, progressing_time = 0;
u32 reg_val_start = 0, reg_val = 0;
u8 print_rpt = 0;
#endif
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
reg1 = R_0xfb4;
@@ -420,70 +414,17 @@ phydm_nhm_check_rdy(void *dm_void)
#endif
} else {
reg1 = R_0x8b4;
if (dm->support_ic_type == ODM_RTL8710B) {
if (dm->support_ic_type & (ODM_RTL8710B | ODM_RTL8721D |
ODM_RTL8710C))
reg1_bit = 25;
} else {
else
reg1_bit = 17;
}
}
#if (ENV_MNTR_DBG_1)
start_time = odm_get_current_time(dm);
if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) {
PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM_period = %d\n",
odm_get_bb_reg(dm, R_0x990, MASKDWORD));
/*NHM trigger bit*/
reg_val_start = odm_get_bb_reg(dm, R_0x994, BIT(1));
PHYDM_DBG(dm, DBG_ENV_MNTR, "reg_val_start = %d\n",
reg_val_start);
for (i = 0; i <= 400; i++) {
if (print_rpt == 0) {
reg_val = odm_get_bb_reg(dm, R_0x994, BIT(1));
if (reg_val != reg_val_start) {
print_rpt = 1;
PHYDM_DBG(dm, DBG_ENV_MNTR,
"Trig[%d] (%d) -> (%d)\n",
i, reg_val_start, reg_val);
}
}
if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit))) {
is_ready = true;
break;
}
ODM_delay_ms(1);
}
} else {
if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit)))
is_ready = true;
}
progressing_time = odm_get_progressing_time(dm, start_time);
PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM rdy=%d, i=%d, NHM_polling_time=%lld\n",
is_ready, i, progressing_time);
#elif (ENV_MNTR_DBG)
start_time = odm_get_current_time(dm);
for (i = 0; i <= 400; i++) {
if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit))) {
is_ready = true;
break;
}
ODM_delay_ms(1);
}
progressing_time = odm_get_progressing_time(dm, start_time);
PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM rdy=%d, i=%d, NHM_polling_time=%lld\n",
is_ready, i, progressing_time);
#else
if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit)))
is_ready = true;
PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM rdy=%d\n", is_ready);
#endif
return is_ready;
}
@@ -524,17 +465,10 @@ phydm_nhm_get_result(void *dm_void)
nhm_reg1 = R_0x890;
PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
if (!(dm->support_ic_type == ODM_RTL8822C))
if (!(dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
ODM_RTL8197G)))
pdm_set_reg(dm, nhm_reg1, BIT(1), 0);
#if (ENV_MNTR_DBG_2)
PHYDM_DBG(dm, DBG_ENV_MNTR,
"[DBG][3] 0xc50=0x%x, 0x994=0x%x, 0x998=0x%x\n",
odm_get_bb_reg(dm, R_0xc50, MASKDWORD),
odm_get_bb_reg(dm, R_0x994, MASKDWORD),
odm_get_bb_reg(dm, R_0x998, MASKDWORD));
#endif
if (!(phydm_nhm_check_rdy(dm))) {
PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM report Fail\n");
phydm_nhm_racing_release(dm);
@@ -611,14 +545,6 @@ phydm_nhm_get_result(void *dm_void)
phydm_nhm_racing_release(dm);
#if (ENV_MNTR_DBG_2)
PHYDM_DBG(dm, DBG_ENV_MNTR,
"[DBG][4] 0xc50=0x%x, 0x994=0x%x, 0x998=0x%x\n",
odm_get_bb_reg(dm, R_0xc50, MASKDWORD),
odm_get_bb_reg(dm, R_0x994, MASKDWORD),
odm_get_bb_reg(dm, R_0x998, MASKDWORD));
#endif
if (nhm_rpt_sum_tmp > 255) {
PHYDM_DBG(dm, DBG_ENV_MNTR,
"[Warning] Invalid NHM RPT, total=%d\n",
@@ -695,7 +621,9 @@ phydm_nhm_th_update_chk(void *dm_void, enum nhm_application nhm_app, u8 *nhm_th,
0x78};
u8 nhm_igi_th_xbox[NHM_TH_NUM] = {0x1a, 0x2c, 0x2e, 0x30, 0x32, 0x34,
0x36, 0x38, 0x3a, 0x3c, 0x3d};
u8 i;
u8 i = 0;
u8 th_tmp = igi_curr - CCA_CAP;
u8 th_step = 2;
PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
PHYDM_DBG(dm, DBG_ENV_MNTR, "App=%d, nhm_igi=0x%x, igi_curr=0x%x\n",
@@ -705,7 +633,28 @@ phydm_nhm_th_update_chk(void *dm_void, enum nhm_application nhm_app, u8 *nhm_th,
return false;
switch (nhm_app) {
case NHM_BACKGROUND: /*@Get IGI form driver parameter(cur_ig_value)*/
case NHM_BACKGROUND: /* @Get IGI form driver parameter(cur_ig_value)*/
if (ccx->nhm_igi != igi_curr || ccx->nhm_app != nhm_app) {
is_update = true;
*igi_new = (u32)igi_curr;
#ifdef NHM_DYM_PW_TH_SUPPORT
if ((dm->support_ic_type & ODM_IC_JGR3_SERIES) &&
ccx->nhm_dym_pw_th_en) {
th_tmp = MAX_2(igi_curr - DYM_PWTH_CCA_CAP, 0);
th_step = 3;
}
#endif
nhm_th[0] = (u8)IGI_2_NHM_TH(th_tmp);
for (i = 1; i <= 10; i++)
nhm_th[i] = nhm_th[0] +
IGI_2_NHM_TH(th_step * i);
}
break;
case NHM_ACS:
if (ccx->nhm_igi != igi_curr || ccx->nhm_app != nhm_app) {
is_update = true;
@@ -803,11 +752,11 @@ void phydm_nhm_set(void *dm_void, enum nhm_option_txon_all include_tx,
ODM_RTL8195A | ODM_RTL8192E)) {
val_tmp = (u32)((include_tx << 2) |
(include_cca << 1) | 1);
pdm_set_reg(dm, reg1, R_0x700, val_tmp);
pdm_set_reg(dm, reg1, 0x700, val_tmp);
} else {
val_tmp = (u32)BIT_2_BYTE(divi_opt, include_tx,
include_cca, 1);
pdm_set_reg(dm, reg1, R_0xf00, val_tmp);
pdm_set_reg(dm, reg1, 0xf00, val_tmp);
}
ccx->nhm_include_txon = include_tx;
ccx->nhm_include_cca = include_cca;
@@ -883,6 +832,316 @@ u8 phydm_nhm_mntr_set(void *dm_void, struct nhm_para_info *nhm_para)
return PHYDM_SET_SUCCESS;
}
void phydm_nhm_cal_noise(void *dm_void, u8 start_i, u8 end_i, u8 n_sum)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct ccx_info *ccx = &dm->dm_ccx_info;
u8 i = 0;
u32 noise_tmp = 0;
u8 noise = 0;
u8 th_step = 2;
u32 nhm_valid = 0;
PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
if (n_sum == 0) {
PHYDM_DBG(dm, DBG_ENV_MNTR,
"n_sum = 0, don't need to update noise\n");
return;
} else if (end_i > NHM_RPT_NUM - 1) {
PHYDM_DBG(dm, DBG_ENV_MNTR,
"[WARNING]end_i is larger than 11!!\n");
return;
}
#ifdef NHM_DYM_PW_TH_SUPPORT
if ((dm->support_ic_type & ODM_IC_JGR3_SERIES) &&
ccx->nhm_dym_pw_th_en)
th_step = 3;
#endif
for (i = start_i; i <= end_i; i++)
noise_tmp += ccx->nhm_result[i] * (ccx->nhm_th[0] - th_step +
th_step * i * 2);
/* protection for the case of minus noise(RSSI)*/
noise = (u8)(NTH_TH_2_RSSI(MAX_2(PHYDM_DIV(noise_tmp, n_sum), 20)));
ccx->nhm_noise_pwr = noise;
ccx->nhm_noise_pwr_point = n_sum;
nhm_valid = (n_sum * 100) >> 8;
PHYDM_DBG(dm, DBG_ENV_MNTR,
"valid: ((%d)) percent, noise(RSSI)=((%d)), nhm_r[11](RSSI > %d)=((%d))\n",
nhm_valid, noise, NTH_TH_2_RSSI(ccx->nhm_th[NHM_TH_NUM - 1]),
ccx->nhm_result[NHM_RPT_NUM - 1]);
}
#ifdef NHM_DYM_PW_TH_SUPPORT
void
phydm_nhm_restore_pw_th(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct ccx_info *ccx = &dm->dm_ccx_info;
odm_set_bb_reg(dm, R_0x82c, 0x3f, ccx->nhm_pw_th_rf20_dft);
}
void
phydm_nhm_set_pw_th(void *dm_void, u8 noise, boolean chk_succ)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct ccx_info *ccx = &dm->dm_ccx_info;
u8 pre_pw_th_rf20 = 0;
u8 new_pw_th_rf20 = 0;
u8 pw_th_u_bnd = 0;
s8 noise_diff = 0;
u8 point_mean = 15;
PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
if (*dm->band_width != CHANNEL_WIDTH_20 ||
*dm->band_type == ODM_BAND_5G) {
PHYDM_DBG(dm, DBG_ENV_MNTR, "bandwidth=((%d)), band=((%d))\n",
*dm->band_width, *dm->band_type);
phydm_nhm_restore_pw_th(dm);
return;
}
pre_pw_th_rf20 = (u8)odm_get_bb_reg(dm, R_0x82c, 0x3f);
/* @pre_pw_th can not be lower than default value*/
if (pre_pw_th_rf20 < ccx->nhm_pw_th_rf20_dft) {
PHYDM_DBG(dm, DBG_ENV_MNTR,
"pre_pw_th=((%d)), new_pw_th=((%d))\n",
pre_pw_th_rf20, ccx->nhm_pw_th_rf20_dft);
phydm_nhm_restore_pw_th(dm);
return;
}
if (chk_succ) {
noise_diff = noise - (ccx->nhm_igi - 10);
pw_th_u_bnd = (u8)(noise_diff + 32 + point_mean);
pw_th_u_bnd = MIN_2(pw_th_u_bnd, ccx->nhm_pw_th_max);
PHYDM_DBG(dm, DBG_ENV_MNTR,
"noise_diff=((%d)), max=((%d)), pw_th_u_bnd=((%d))\n",
noise_diff, ccx->nhm_pw_th_max, pw_th_u_bnd);
if (pw_th_u_bnd > pre_pw_th_rf20) {
new_pw_th_rf20 = pre_pw_th_rf20 + 1;
} else if (pw_th_u_bnd == pre_pw_th_rf20) {
new_pw_th_rf20 = pre_pw_th_rf20;
} else {
if (pre_pw_th_rf20 > ccx->nhm_pw_th_rf20_dft)
new_pw_th_rf20 = pre_pw_th_rf20 - 1;
else /* @pre_pw_th = ccx->nhm_pw_th_dft*/
new_pw_th_rf20 = pre_pw_th_rf20;
}
} else {
if (pre_pw_th_rf20 > ccx->nhm_pw_th_rf20_dft)
new_pw_th_rf20 = pre_pw_th_rf20 - 1;
else /* @pre_pw_th = ccx->nhm_pw_th_dft*/
new_pw_th_rf20 = pre_pw_th_rf20;
}
PHYDM_DBG(dm, DBG_ENV_MNTR, "pre_pw_th=((%d)), new_pw_th=((%d))\n",
pre_pw_th_rf20, new_pw_th_rf20);
if (new_pw_th_rf20 != pre_pw_th_rf20)
odm_set_bb_reg(dm, R_0x82c, 0x3f, new_pw_th_rf20);
}
void
phydm_nhm_dym_pw_th_1peak(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct ccx_info *ccx = &dm->dm_ccx_info;
u8 i = 0;
u8 max_i = 0;
u8 m_dif_l1 = 0;
u8 m_dif_r1 = 0;
u8 patt_case = 0;
u8 l1_dif_r2 = 0;
u8 l2_dif_r1 = 0;
u8 l1_dif_r1 = 0;
u8 n_sum = 0;
u8 r1_dif_r2 = 0;
u8 l1_dif_l2 = 0;
u8 noise = 0;
boolean chk_succ = false;
PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
/* @step1*/
for (i = 1; i < NHM_RPT_NUM; i++) {
if (ccx->nhm_result[i] >= ccx->nhm_result[max_i])
max_i = i;
}
if (max_i == 0 || max_i == (NHM_RPT_NUM - 1)) {
PHYDM_DBG(dm, DBG_ENV_MNTR, "max index can not be 0 or 11\n");
phydm_nhm_set_pw_th(dm, 0, chk_succ);
return;
}
/* @step2*/
m_dif_l1 = ccx->nhm_result[max_i] - ccx->nhm_result[max_i - 1];
m_dif_r1 = ccx->nhm_result[max_i] - ccx->nhm_result[max_i + 1];
if (m_dif_r1 <= NHM_TH1 && (max_i != NHM_RPT_NUM - 1))
patt_case = NHM_1PEAK_PS;
else if ((m_dif_l1 <= NHM_TH1) && (max_i != 0))
patt_case = NHM_1PEAK_NS;
else
patt_case = NHM_1PEAK_SYM;
switch (patt_case) {
case NHM_1PEAK_PS:
/* @step3*/
l1_dif_r2 = DIFF_2(ccx->nhm_result[max_i - 1],
ccx->nhm_result[max_i + 2]);
if (l1_dif_r2 > NHM_TH2) {
PHYDM_DBG(dm, DBG_ENV_MNTR, "S3 fail:c1((%d))\n",
l1_dif_r2);
break;
}
/* @step4*/
n_sum = ccx->nhm_result[max_i - 1] + ccx->nhm_result[max_i] +
ccx->nhm_result[max_i + 1] + ccx->nhm_result[max_i + 2];
if (n_sum < NHM_TH4) {
PHYDM_DBG(dm, DBG_ENV_MNTR, "S4 fail:((%d))\n", n_sum);
break;
}
/* @step5*/
r1_dif_r2 = DIFF_2(ccx->nhm_result[max_i + 1],
ccx->nhm_result[max_i + 2]);
if (m_dif_l1 < NHM_TH5 || r1_dif_r2 < NHM_TH5) {
PHYDM_DBG(dm, DBG_ENV_MNTR, "S5 fail:c1((%d, %d))\n",
m_dif_l1, r1_dif_r2);
break;
}
/* @step6*/
chk_succ = true;
phydm_nhm_cal_noise(dm, max_i - 1, max_i + 2, n_sum);
break;
case NHM_1PEAK_NS:
/* @step3*/
l2_dif_r1 = DIFF_2(ccx->nhm_result[max_i - 2],
ccx->nhm_result[max_i + 1]);
if (l2_dif_r1 > NHM_TH2) {
PHYDM_DBG(dm, DBG_ENV_MNTR, "S3 fail:c2((%d))\n",
l2_dif_r1);
break;
}
/* @step4*/
n_sum = ccx->nhm_result[max_i - 2] +
ccx->nhm_result[max_i - 1] +
ccx->nhm_result[max_i] + ccx->nhm_result[max_i + 1];
if (n_sum < NHM_TH4) {
PHYDM_DBG(dm, DBG_ENV_MNTR, "S4 fail:((%d))\n", n_sum);
break;
}
/* @step5*/
l1_dif_l2 = DIFF_2(ccx->nhm_result[max_i - 1],
ccx->nhm_result[max_i - 2]);
if (m_dif_r1 < NHM_TH5 || l1_dif_l2 < NHM_TH5) {
PHYDM_DBG(dm, DBG_ENV_MNTR, "S5 fail:c2((%d, %d))\n",
m_dif_r1, l1_dif_l2);
break;
}
/* @step6*/
chk_succ = true;
phydm_nhm_cal_noise(dm, max_i - 2, max_i + 1, n_sum);
break;
case NHM_1PEAK_SYM:
/* @step3*/
l1_dif_r1 = DIFF_2(ccx->nhm_result[max_i - 1],
ccx->nhm_result[max_i + 1]);
if (l1_dif_r1 > NHM_TH3) {
PHYDM_DBG(dm, DBG_ENV_MNTR, "S3 fail: c3((%d))\n",
l1_dif_r1);
break;
}
/* @step4*/
n_sum = ccx->nhm_result[max_i - 1] + ccx->nhm_result[max_i] +
ccx->nhm_result[max_i + 1];
if (n_sum < NHM_TH4) {
PHYDM_DBG(dm, DBG_ENV_MNTR, "S4 fail:((%d))\n", n_sum);
break;
}
/* @step5*/
if (m_dif_l1 < NHM_TH6 || m_dif_r1 < NHM_TH6) {
PHYDM_DBG(dm, DBG_ENV_MNTR, "S5 fail:c3((%d, %d))\n",
m_dif_l1, m_dif_r1);
break;
}
/* @step6*/
chk_succ = true;
phydm_nhm_cal_noise(dm, max_i - 1, max_i + 1, n_sum);
break;
}
phydm_nhm_set_pw_th(dm, ccx->nhm_noise_pwr, chk_succ);
}
void
phydm_nhm_dym_pw_th_sl(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct ccx_info *ccx = &dm->dm_ccx_info;
u8 i = 0;
u8 n_sum = 0;
u8 noise = 0;
boolean chk_succ = false;
PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
for (i = 0; i < NHM_RPT_NUM - 3; i++) {
n_sum = ccx->nhm_result[i] + ccx->nhm_result[i + 1] +
ccx->nhm_result[i + 2] + ccx->nhm_result[i + 3];
if (n_sum >= ccx->nhm_sl_pw_th) {
PHYDM_DBG(dm, DBG_ENV_MNTR, "Do sl[%d:%d]\n", i, i + 3);
chk_succ = true;
phydm_nhm_cal_noise(dm, i, i + 3, n_sum);
break;
}
}
if (!chk_succ)
PHYDM_DBG(dm, DBG_ENV_MNTR, "SL method failed!\n");
phydm_nhm_set_pw_th(dm, ccx->nhm_noise_pwr, chk_succ);
}
void
phydm_nhm_dym_pw_th(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct ccx_info *ccx = &dm->dm_ccx_info;
if (ccx->nhm_dym_1_peak_en)
phydm_nhm_dym_pw_th_1peak(dm);
else
phydm_nhm_dym_pw_th_sl(dm);
}
void
phydm_nhm_dym_pw_th_patch_id_chk(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct ccx_info *ccx = &dm->dm_ccx_info;
if (dm->iot_table.phydm_patch_id == 0x100f0401) {
ccx->nhm_dym_pw_th_en = true;
} else {
if (ccx->nhm_dym_pw_th_en) {
phydm_nhm_restore_pw_th(dm);
ccx->nhm_dym_pw_th_en = false;
}
}
}
#endif
/*@Environment Monitor*/
boolean
phydm_nhm_mntr_chk(void *dm_void, u16 monitor_time /*unit ms*/)
@@ -911,18 +1170,53 @@ phydm_nhm_mntr_chk(void *dm_void, u16 monitor_time /*unit ms*/)
}
/*@[NHM get result & calculate Utility----------------------------*/
#ifdef NHM_DYM_PW_TH_SUPPORT
if (!(ccx->dym_pwth_manual_ctrl))
phydm_nhm_dym_pw_th_patch_id_chk(dm);
#endif
if (phydm_nhm_get_result(dm)) {
PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM_rpt success\n");
phydm_nhm_get_utility(dm);
#ifdef NHM_DYM_PW_TH_SUPPORT
if ((dm->support_ic_type & ODM_IC_JGR3_SERIES) &&
ccx->nhm_dym_pw_th_en)
phydm_nhm_dym_pw_th(dm);
else
#endif
/* bypass r[11]*/
phydm_nhm_cal_noise(dm, 0, NHM_RPT_NUM - 2,
ccx->nhm_rpt_sum -
ccx->nhm_result[11]);
} else {
#ifdef NHM_DYM_PW_TH_SUPPORT
if ((dm->support_ic_type & ODM_IC_JGR3_SERIES) &&
ccx->nhm_dym_pw_th_en)
phydm_nhm_set_pw_th(dm, 0, false);
#endif
}
/*@[NHM trigger]-------------------------------------------------*/
/*@[NHM trigger setting]------------------------------------------*/
nhm_para.incld_txon = NHM_EXCLUDE_TXON;
nhm_para.incld_cca = NHM_EXCLUDE_CCA;
nhm_para.div_opt = NHM_CNT_ALL;
#ifdef NHM_DYM_PW_TH_SUPPORT
if ((dm->support_ic_type & ODM_IC_JGR3_SERIES) &&
ccx->nhm_app == NHM_BACKGROUND && ccx->nhm_dym_pw_th_en)
nhm_para.div_opt = NHM_VALID;
else
#endif
nhm_para.div_opt = NHM_CNT_ALL;
nhm_para.nhm_app = NHM_BACKGROUND;
nhm_para.nhm_lv = NHM_LV_1;
nhm_para.mntr_time = monitor_time;
#ifdef NHM_DYM_PW_TH_SUPPORT
if ((dm->support_ic_type & ODM_IC_JGR3_SERIES) &&
ccx->nhm_app == NHM_BACKGROUND && ccx->nhm_dym_pw_th_en)
nhm_para.mntr_time = monitor_time >> ccx->nhm_period_decre;
else
#endif
nhm_para.mntr_time = monitor_time;
nhm_chk_result = phydm_nhm_mntr_set(dm, &nhm_para);
@@ -957,6 +1251,18 @@ void phydm_nhm_init(void *dm_void)
ccx->nhm_manual_ctrl = 0;
ccx->nhm_rpt_stamp = 0;
#ifdef NHM_DYM_PW_TH_SUPPORT
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
ccx->nhm_dym_pw_th_en = false;
ccx->nhm_dym_1_peak_en = false;
ccx->nhm_pw_th_rf20_dft = (u8)odm_get_bb_reg(dm, R_0x82c, 0x3f);
ccx->nhm_pw_th_max = 63;
ccx->nhm_sl_pw_th = 100; /* @39%*/
ccx->nhm_period_decre = 1;
ccx->dym_pwth_manual_ctrl = false;
}
#endif
}
void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
@@ -981,6 +1287,16 @@ void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
PDM_SNPF(out_len, used, output + used, out_len - used,
"NHM Adv-Trigger: {2} {Include TXON} {Include CCA}\n{0:Cnt_all, 1:Cnt valid} {App} {LV} {0~262ms}\n");
#ifdef NHM_DYM_PW_TH_SUPPORT
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"NHM dym_pw_th: {3} {0:off}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"NHM dym_pw_th: {3} {1:on} {en_1-peak} {max} {period_decre} {sl_th}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"NHM dym_pw_th: {3} {2:fast on}\n");
}
#endif
PDM_SNPF(out_len, used, output + used, out_len - used,
"NHM Get Result: {100}\n");
@@ -1006,7 +1322,37 @@ void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
"Get NHM_rpt Fail\n");
}
ccx->nhm_manual_ctrl = 0;
#ifdef NHM_DYM_PW_TH_SUPPORT
} else if (var1[0] == 3) { /* @NMH dym_pw_th*/
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
for (i = 1; i < 7; i++) {
if (input[i + 1]) {
PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
&var1[i]);
}
}
if (var1[1] == 1) {
ccx->nhm_dym_pw_th_en = true;
ccx->nhm_dym_1_peak_en = (boolean)var1[2];
ccx->nhm_pw_th_max = (u8)var1[3];
ccx->nhm_period_decre = (u8)var1[4];
ccx->nhm_sl_pw_th = (u8)var1[5];
ccx->dym_pwth_manual_ctrl = true;
} else if (var1[1] == 2) {
ccx->nhm_dym_pw_th_en = true;
ccx->nhm_dym_1_peak_en = false;
ccx->nhm_pw_th_max = 63;
ccx->nhm_period_decre = 1;
ccx->nhm_sl_pw_th = 100;
ccx->dym_pwth_manual_ctrl = true;
} else {
ccx->nhm_dym_pw_th_en = false;
phydm_nhm_restore_pw_th(dm);
ccx->dym_pwth_manual_ctrl = false;
}
}
#endif
} else { /*NMH trigger*/
ccx->nhm_manual_ctrl = 1;
@@ -1063,6 +1409,7 @@ void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
*_used = used;
*_out_len = out_len;
}
#endif /*@#ifdef NHM_SUPPORT*/
#ifdef CLM_SUPPORT
@@ -1080,7 +1427,7 @@ void phydm_clm_racing_release(void *dm_void)
ccx->clm_app = CLM_BACKGROUND;
}
u8 phydm_clm_racing_ctrl(void *dm_void, enum phydm_nhm_level clm_lv)
u8 phydm_clm_racing_ctrl(void *dm_void, enum phydm_clm_level clm_lv)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct ccx_info *ccx = &dm->dm_ccx_info;
@@ -1213,10 +1560,6 @@ phydm_clm_check_rdy(void *dm_void)
struct dm_struct *dm = (struct dm_struct *)dm_void;
boolean is_ready = false;
u32 reg1 = 0, reg1_bit = 0;
#if (ENV_MNTR_DBG)
u16 i = 0;
u64 start_time = 0, progressing_time = 0;
#endif
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
reg1 = R_0xfa4;
@@ -1227,7 +1570,8 @@ phydm_clm_check_rdy(void *dm_void)
reg1_bit = 16;
#endif
} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
if (dm->support_ic_type == ODM_RTL8710B) {
if (dm->support_ic_type & (ODM_RTL8710B | ODM_RTL8721D |
ODM_RTL8710C)) {
reg1 = R_0x8b4;
reg1_bit = 24;
} else {
@@ -1235,25 +1579,11 @@ phydm_clm_check_rdy(void *dm_void)
reg1_bit = 16;
}
}
#if (ENV_MNTR_DBG)
start_time = odm_get_current_time(dm);
for (i = 0; i <= 400; i++) {
if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit))) {
is_ready = true;
break;
}
ODM_delay_ms(1);
}
progressing_time = odm_get_progressing_time(dm, start_time);
PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM rdy=%d, i=%d, CLM_polling_time=%lld\n",
is_ready, i, progressing_time);
#else
if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit)))
is_ready = true;
PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM rdy=%d\n", is_ready);
#endif
return is_ready;
}
@@ -1291,9 +1621,10 @@ phydm_clm_get_result(void *dm_void)
#endif
else
reg1 = R_0x890;
if (!(dm->support_ic_type == ODM_RTL8822C))
if (!(dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
ODM_RTL8197G)))
odm_set_bb_reg(dm, reg1, BIT(0), 0x0);
if (phydm_clm_check_rdy(dm) == false) {
if (!(phydm_clm_check_rdy(dm))) {
PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM report Fail\n");
phydm_clm_racing_release(dm);
return false;
@@ -1495,7 +1826,6 @@ void phydm_clm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
ccx->clm_period << 2);
ccx->clm_manual_ctrl = 0;
} else if (var1[0] == 3) {
phydm_set_clm_mntr_mode(dm, (enum clm_monitor_mode)var1[1]);
PDM_SNPF(out_len, used, output + used, out_len - used,
@@ -1509,13 +1839,11 @@ void phydm_clm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
clm_para.clm_lv = CLM_LV_4;
clm_para.mntr_time = 262;
ccx->clm_mntr_mode = CLM_DRIVER_MNTR;
} else if (var1[0] == 2) {
clm_para.clm_app = (enum clm_application)var1[1];
clm_para.clm_lv = (enum phydm_clm_level)var1[2];
ccx->clm_mntr_mode = CLM_DRIVER_MNTR;
clm_para.mntr_time = (u16)var1[3];
}
PDM_SNPF(out_len, used, output + used, out_len - used,
@@ -1550,24 +1878,6 @@ u8 phydm_env_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para,
PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__);
#if (ENV_MNTR_DBG_2)
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
PHYDM_DBG(dm, DBG_ENV_MNTR,
"[DBG][2] 0xc50=0x%x, 0x994=0x%x, 0x998=0x%x\n",
odm_get_bb_reg(dm, R_0xc50, MASKDWORD),
odm_get_bb_reg(dm, R_0x994, MASKDWORD),
odm_get_bb_reg(dm, R_0x998, MASKDWORD));
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
PHYDM_DBG(dm, DBG_ENV_MNTR,
"[DBG][2] 0x1d70=0x%x, 0x1e60=0x%x, 0x1e44=0x%x\n",
odm_get_bb_reg(dm, R_0x1d70, MASKDWORD),
odm_get_bb_reg(dm, R_0x1e60, MASKDWORD),
odm_get_bb_reg(dm, R_0x1e44, MASKDWORD));
#endif
}
#endif
/*@[NHM]*/
nhm_set_ok = phydm_nhm_mntr_set(dm, nhm_para);
@@ -1616,29 +1926,15 @@ u8 phydm_env_mntr_result(void *dm_void, struct env_mntr_rpt *rpt)
PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__);
PHYDM_DBG(dm, DBG_ENV_MNTR, "env_time=%lld\n", progressing_time);
#if (ENV_MNTR_DBG_2)
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
PHYDM_DBG(dm, DBG_ENV_MNTR,
"[DBG][2] 0xc50=0x%x, 0x994=0x%x, 0x998=0x%x\n",
odm_get_bb_reg(dm, R_0xc50, MASKDWORD),
odm_get_bb_reg(dm, R_0x994, MASKDWORD),
odm_get_bb_reg(dm, R_0x998, MASKDWORD));
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
PHYDM_DBG(dm, DBG_ENV_MNTR,
"[DBG][2] 0x1d70=0x%x, 0x1e60=0x%x, 0x1e44=0x%x\n",
odm_get_bb_reg(dm, R_0x1d70, MASKDWORD),
odm_get_bb_reg(dm, R_0x1e60, MASKDWORD),
odm_get_bb_reg(dm, R_0x1e44, MASKDWORD));
#endif
}
#endif
/*@Get NHM result*/
if (phydm_nhm_get_result(dm)) {
PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM_rpt success\n");
phydm_nhm_get_utility(dm);
/* bypass r[11]*/
phydm_nhm_cal_noise(dm, 0, NHM_RPT_NUM - 2,
ccx->nhm_rpt_sum - ccx->nhm_result[11]);
rpt->nhm_ratio = ccx->nhm_ratio;
rpt->nhm_noise_pwr = ccx->nhm_noise_pwr;
env_mntr_rpt |= NHM_SUCCESS;
odm_move_memory(dm, &rpt->nhm_result[0],
@@ -1758,7 +2054,6 @@ void phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used,
PDM_SNPF(out_len, used, output + used, out_len - used,
"Get Result: {100}\n");
} else if (var1[0] == 100) { /* @Get CLM results */
set_result = phydm_env_mntr_result(dm, &rpt);
PDM_SNPF(out_len, used, output + used, out_len - used,

56
hal/phydm/phydm_ccx.h
View File

@@ -26,14 +26,13 @@
#ifndef __PHYDMCCX_H__
#define __PHYDMCCX_H__
/* 2019.03.27 add noise_pwr in env_mntr_rpt.*/
#define CCX_VERSION "2.4"
/* @1 ============================================================
* 1 Definition
* 1 ============================================================
*/
#define ENV_MNTR_DBG 0 /*@debug for the HW processing time from NHM/CLM trigger and get result*/
#define ENV_MNTR_DBG_1 0 /*@debug 8812A & 8821A P2P Fail to get result*/
#define ENV_MNTR_DBG_2 0 /*@debug for read reister*/
#define CCX_EN 1
#define MAX_ENV_MNTR_TIME 8 /*second*/
@@ -46,6 +45,18 @@
#define NHM_PERIOD_MAX 65534
#define NHM_TH_NUM 11 /*threshold number of NHM*/
#define NHM_RPT_NUM 12
#ifdef NHM_DYM_PW_TH_SUPPORT
#define DYM_PWTH_CCA_CAP 24
#define NHM_1PEAK_PS 1 /* @case1 : positive skew*/
#define NHM_1PEAK_NS 2 /* @case2 : negative skew*/
#define NHM_1PEAK_SYM 3 /* @case3 : symmetry*/
#define NHM_TH1 33 /* @13%, for step2 decision*/
#define NHM_TH2 35 /* @14%, for step3_c1_c2 decision*/
#define NHM_TH3 31 /* @12%, for step3_c3 decision*/
#define NHM_TH4 178 /* @70%, for step4 decision*/
#define NHM_TH5 25 /* @10%, for step5_c1_c2 decision*/
#define NHM_TH6 39 /* @15%, for step5_c3 decision*/
#endif
#define IGI_2_NHM_TH(igi) ((igi) << 1)/*NHM_threshold = IGI * 2*/
#define NTH_TH_2_RSSI(th) ((th >> 1) - 10)
@@ -141,6 +152,7 @@ struct env_mntr_rpt {
u8 clm_ratio;
u8 nhm_rpt_stamp;
u8 clm_rpt_stamp;
u8 nhm_noise_pwr;
};
struct nhm_para_info {
@@ -150,7 +162,6 @@ struct nhm_para_info {
enum nhm_application nhm_app;
enum phydm_nhm_level nhm_lv;
u16 mntr_time; /*@0~262 unit ms*/
};
struct clm_para_info {
@@ -180,7 +191,19 @@ struct ccx_info {
u8 nhm_set_lv;
boolean nhm_ongoing;
u8 nhm_rpt_stamp;
u8 nhm_noise_pwr;
u8 nhm_noise_pwr_point;
#ifdef NHM_DYM_PW_TH_SUPPORT
boolean nhm_dym_pw_th_en;
boolean nhm_dym_1_peak_en;
boolean dym_pwth_manual_ctrl;
u8 nhm_pw_th_rf20_dft;
u8 nhm_pw_th_max;
u8 nhm_period_decre;
u8 nhm_sl_pw_th;
#endif
#endif
#ifdef CLM_SUPPORT
enum clm_application clm_app;
u8 clm_manual_ctrl;
@@ -209,20 +232,14 @@ struct ccx_info {
*/
#ifdef FAHM_SUPPORT
void phydm_fahm_init(void *dm_void);
void phydm_fahm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len);
#endif
/*@NHM*/
#ifdef NHM_SUPPORT
void phydm_nhm_trigger(void *dm_void);
void phydm_nhm_init(void *dm_void);
void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len);
u8 phydm_get_igi(void *dm_void, enum bb_path path);
@@ -232,22 +249,6 @@ u8 phydm_get_igi(void *dm_void, enum bb_path path);
#ifdef CLM_SUPPORT
void phydm_clm_c2h_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
void phydm_clm_h2c(void *dm_void, u16 obs_time, u8 fw_clm_en);
void phydm_clm_setting(void *dm_void, u16 clm_period);
void phydm_clm_trigger(void *dm_void);
boolean phydm_clm_check_rdy(void *dm_void);
void phydm_clm_get_utility(void *dm_void);
boolean phydm_clm_get_result(void *dm_void);
u8 phydm_clm_mntr_set(void *dm_void, struct clm_para_info *clm_para);
void phydm_set_clm_mntr_mode(void *dm_void, enum clm_monitor_mode mode);
void phydm_clm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len);
#endif
@@ -264,5 +265,4 @@ void phydm_env_monitor_init(void *dm_void);
void phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif

56
hal/phydm/phydm_cfotracking.c
View File

@@ -108,7 +108,7 @@ void phydm_get_cfo_info_n(void *dm_void, struct phydm_cfo_rpt *cfo)
val[4] = odm_read_4byte(dm, R_0xdbc); /*@ End CFO*/
/*@[path-A]*/
if (dm->support_ic_type == ODM_RTL8721D) {
if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
val_tmp = (val[0] & 0x0fff0000) >> 16; /*@ Short CFO, S(12,11)*/
cfo->cfo_rpt_s[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
val_tmp = (val[1] & 0x0fff0000) >> 16; /*@ Long CFO, S(12,11)*/
@@ -203,21 +203,6 @@ void phydm_get_cfo_info(void *dm_void, struct phydm_cfo_rpt *cfo)
}
}
void phydm_set_crystal_cap(void *dm_void, u8 crystal_cap)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
if (cfo_track->crystal_cap == crystal_cap)
return;
if (phydm_set_crystal_cap_reg(dm, crystal_cap))
PHYDM_DBG(dm, DBG_CFO_TRK, "Set crystal_cap = 0x%x\n",
cfo_track->crystal_cap);
else
PHYDM_DBG(dm, DBG_CFO_TRK, "Set fail\n");
}
boolean
phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap)
{
@@ -226,7 +211,7 @@ phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap)
u32 reg_val = 0;
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |
ODM_RTL8195B | ODM_RTL8812F | ODM_RTL8721D)) {
ODM_RTL8195B | ODM_RTL8812F | ODM_RTL8721D | ODM_RTL8710C)) {
crystal_cap &= 0x7F;
reg_val = crystal_cap | (crystal_cap << 7);
} else {
@@ -264,9 +249,9 @@ phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap)
}
#endif
#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8197F_SUPPORT ||\
RTL8192F_SUPPORT)
RTL8192F_SUPPORT || RTL8197G_SUPPORT)
else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C |
ODM_RTL8197F | ODM_RTL8192F)) {
ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8197G)) {
/* write 0x24[30:25] = 0x28[6:1] = crystal_cap */
odm_set_mac_reg(dm, R_0x24, 0x7e000000, crystal_cap);
odm_set_mac_reg(dm, R_0x28, 0x7e, crystal_cap);
@@ -298,6 +283,13 @@ phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap)
temp_val);
}
#endif
#if (RTL8710C_SUPPORT)
else if (dm->support_ic_type & (ODM_RTL8710C)) {
/* write MAC reg 0x28[13:7][6:0] crystal_cap */
phydm_set_crystalcap(dm, (u8)(reg_val & 0x7f));
}
#endif
#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)
else if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |
ODM_RTL8812F)) {
@@ -310,6 +302,21 @@ phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap)
return true;
}
void phydm_set_crystal_cap(void *dm_void, u8 crystal_cap)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
if (cfo_track->crystal_cap == crystal_cap)
return;
if (phydm_set_crystal_cap_reg(dm, crystal_cap))
PHYDM_DBG(dm, DBG_CFO_TRK, "Set crystal_cap = 0x%x\n",
cfo_track->crystal_cap);
else
PHYDM_DBG(dm, DBG_CFO_TRK, "Set fail\n");
}
void phydm_cfo_tracking_reset(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
@@ -407,7 +414,8 @@ void phydm_cfo_tracking(void *dm_void)
cfo_abs = cfo_track->CFO_tail[i];
cfo_rpt_sum = (u32)CFO_HW_RPT_2_KHZ(cfo_abs);
cfo_khz_avg[i] = cfo_rpt_sum / cfo_track->CFO_cnt[i];
cfo_khz_avg[i] = PHYDM_DIV(cfo_rpt_sum,
cfo_track->CFO_cnt[i]);
PHYDM_DBG(dm, DBG_CFO_TRK,
"[Path-%d] CFO_sum=((%d)), cnt=((%d)), CFO_avg=((%s%d))kHz\n",
@@ -443,8 +451,8 @@ void phydm_cfo_tracking(void *dm_void)
cfo_avg < (-CFO_TRK_ENABLE_TH))
cfo_track->is_adjust = true;
} else {
if (cfo_avg < CFO_TRK_STOP_TH &&
cfo_avg > (-CFO_TRK_STOP_TH))
if (cfo_avg <= CFO_TRK_STOP_TH &&
cfo_avg >= (-CFO_TRK_STOP_TH))
cfo_track->is_adjust = false;
}
@@ -464,8 +472,8 @@ void phydm_cfo_tracking(void *dm_void)
else if (cfo_avg < (-CFO_TRK_STOP_TH))
crystal_cap -= 1;
if (dm->support_ic_type & (ODM_RTL8822C |
ODM_RTL8814B | ODM_RTL8195B | ODM_RTL8812F)) {
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |
ODM_RTL8195B | ODM_RTL8812F)) {
if (crystal_cap > 0x7F)
crystal_cap = 0x7F;
} else {

7
hal/phydm/phydm_cfotracking.h
View File

@@ -26,7 +26,8 @@
#ifndef __PHYDMCFOTRACK_H__
#define __PHYDMCFOTRACK_H__
#define CFO_TRACKING_VERSION "2.0"
/* 2019.03.28 fix 8197G crystal_cap register address*/
#define CFO_TRACKING_VERSION "2.4"
#define CFO_TRK_ENABLE_TH 20 /* @kHz enable CFO_Track threshold*/
#define CFO_TRK_STOP_TH 10 /* @kHz disable CFO_Track threshold*/
@@ -55,10 +56,10 @@ struct phydm_cfo_rpt {
void phydm_get_cfo_info(void *dm_void, struct phydm_cfo_rpt *cfo);
void phydm_set_crystal_cap(void *dm_void, u8 crystal_cap);
boolean phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap);
void phydm_set_crystal_cap(void *dm_void, u8 crystal_cap);
void phydm_cfo_tracking_init(void *dm_void);
void phydm_cfo_tracking(void *dm_void);

1585
hal/phydm/phydm_debug.c
View File

File diff suppressed because it is too large Load Diff

16
hal/phydm/phydm_debug.h
View File

@@ -26,11 +26,13 @@
#ifndef __ODM_DBG_H__
#define __ODM_DBG_H__
/*@#define DEBUG_VERSION "1.1"*/ /*@2015.07.29 YuChen*/
/*@#define DEBUG_VERSION "1.2"*/ /*@2015.08.28 Dino*/
/*@#define DEBUG_VERSION "1.3"*/ /*@2016.04.28 YuChen*/
/*@#define DEBUG_VERSION "1.4"*/ /*@2017.03.13 Dino*/
#define DEBUG_VERSION "2.0" /*@2018.01.10 Dino*/
/*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/
/*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/
/*#define DEBUG_VERSION "1.3"*/ /*2016.04.28 YuChen*/
/*#define DEBUG_VERSION "1.4"*/ /*2017.03.13 Dino*/
/*#define DEBUG_VERSION "2.0"*/ /*2018.01.10 Dino*/
/* 2019.03.25 fix nhm_r[11] debug msg error*/
#define DEBUG_VERSION "2.6"
/*@
* ============================================================
@@ -424,6 +426,8 @@ void phydm_init_debug_setting(struct dm_struct *dm);
void phydm_bb_dbg_port_header_sel(void *dm_void, u32 header_idx);
u32 phydm_get_bb_dbg_port_idx(void *dm_void);
u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port);
void phydm_release_bb_dbg_port(void *dm_void);
@@ -434,6 +438,8 @@ void phydm_reset_rx_rate_distribution(struct dm_struct *dm);
void phydm_rx_rate_distribution(void *dm_void);
u16 phydm_rx_avg_phy_rate(void *dm_void);
void phydm_show_phy_hitogram(void *dm_void);
void phydm_get_avg_phystatus_val(void *dm_void);

173
hal/phydm/phydm_dfs.c
View File

@@ -46,11 +46,34 @@ boolean phydm_dfs_is_meteorology_channel(void *dm_void)
(bw == CHANNEL_WIDTH_20 && (ch) >= 120 && (ch) <= 128));
}
void phydm_dfs_segment_distinguish(void *dm_void, enum rf_syn syn_path)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (!(dm->support_ic_type & (ODM_RTL8814B)))
return;
if (syn_path == RF_SYN1)
dm->seg1_dfs_flag = 1;
else
dm->seg1_dfs_flag = 0;
}
void phydm_dfs_segment_flag_reset(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (!(dm->support_ic_type & (ODM_RTL8814B)))
return;
if (dm->seg1_dfs_flag)
dm->seg1_dfs_flag = 0;
}
void phydm_radar_detect_reset(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
ODM_RTL8197G)) {
odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
odm_set_bb_reg(dm, R_0xa40, BIT(15), 1);
#if (RTL8721D_SUPPORT)
@@ -58,6 +81,14 @@ void phydm_radar_detect_reset(void *dm_void)
odm_set_bb_reg(dm, R_0xf58, BIT(29), 0);
odm_set_bb_reg(dm, R_0xf58, BIT(29), 1);
#endif
} else if (dm->support_ic_type & (ODM_RTL8814B)) {
if (dm->seg1_dfs_flag == 1) {
odm_set_bb_reg(dm, R_0xa6c, BIT(0), 0);
odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
return;
}
odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
odm_set_bb_reg(dm, R_0xa40, BIT(15), 1);
} else {
odm_set_bb_reg(dm, R_0x924, BIT(15), 0);
odm_set_bb_reg(dm, R_0x924, BIT(15), 1);
@@ -68,8 +99,17 @@ void phydm_radar_detect_disable(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
ODM_RTL8197G))
odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
else if (dm->support_ic_type & (ODM_RTL8814B)) {
if (dm->seg1_dfs_flag == 1) {
odm_set_bb_reg(dm, R_0xa6c, BIT(0), 0);
dm->seg1_dfs_flag = 0;
return;
}
odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
}
#if (RTL8721D_SUPPORT)
else if (dm->support_ic_type & (ODM_RTL8721D))
odm_set_bb_reg(dm, R_0xf58, BIT(29), 0);
@@ -95,6 +135,19 @@ static void phydm_radar_detect_with_dbg_parm(void *dm_void)
dm->radar_detect_reg_f70);
odm_set_bb_reg(dm, R_0xf74, MASKDWORD,
dm->radar_detect_reg_f74);
} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
odm_set_bb_reg(dm, R_0xa40, MASKDWORD,
dm->radar_detect_reg_a40);
odm_set_bb_reg(dm, R_0xa44, MASKDWORD,
dm->radar_detect_reg_a44);
odm_set_bb_reg(dm, R_0xa48, MASKDWORD,
dm->radar_detect_reg_a48);
odm_set_bb_reg(dm, R_0xa4c, MASKDWORD,
dm->radar_detect_reg_a4c);
odm_set_bb_reg(dm, R_0xa50, MASKDWORD,
dm->radar_detect_reg_a50);
odm_set_bb_reg(dm, R_0xa54, MASKDWORD,
dm->radar_detect_reg_a54);
} else {
odm_set_bb_reg(dm, R_0x918, MASKDWORD,
dm->radar_detect_reg_918);
@@ -116,7 +169,7 @@ void phydm_radar_detect_enable(void *dm_void)
u8 region_domain = dm->dfs_region_domain;
u8 c_channel = *dm->channel;
u8 band_width = *dm->band_width;
u8 enable = 0;
u8 enable = 0, i;
u8 short_pw_upperbound = 0;
PHYDM_DBG(dm, DBG_DFS, "test, region_domain = %d\n", region_domain);
@@ -384,6 +437,51 @@ void phydm_radar_detect_enable(void *dm_void)
}
} else if (dm->support_ic_type &
ODM_IC_JGR3_SERIES) {
if (dm->radar_detect_dbg_parm_en) {
phydm_radar_detect_with_dbg_parm(dm);
enable = 1;
goto exit;
}
if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
odm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb359c5bd);
if (dm->support_ic_type & (ODM_RTL8814B)) {
if (dm->seg1_dfs_flag == 1)
odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
}
odm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3033bebd);
odm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254);
odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0xa2533345);
odm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be003);
odm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500089e8);
} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
odm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb359c5bd);
if (dm->support_ic_type & (ODM_RTL8814B)) {
if (dm->seg1_dfs_flag == 1)
odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
}
odm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3033bebd);
odm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254);
odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0xa2533345);
odm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be003);
odm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500089e8);
} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
odm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb359c5bd);
if (dm->support_ic_type & (ODM_RTL8814B)) {
if (dm->seg1_dfs_flag == 1)
odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
}
odm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3033bebd);
odm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254);
odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0xa2533345);
odm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be003);
odm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500089e8);
} else {
/* not supported */
PHYDM_DBG(dm, DBG_DFS,
"Unsupported dfs_region_domain:%d\n",
region_domain);
goto exit;
}
#if (RTL8721D_SUPPORT)
} else if (dm->support_ic_type & ODM_RTL8721D) {
odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10);
@@ -500,7 +598,7 @@ void phydm_radar_detect_enable(void *dm_void)
dfs->three_peak_th2 = (u8)odm_get_bb_reg(dm, 0x924, 0x00007000);
}
phydm_dfs_parameter_init(dm);
phydm_dfs_parameter_init(dm);
exit:
if (enable) {
@@ -530,11 +628,14 @@ void phydm_dfs_parameter_init(void *dm_void)
dfs->det_print = 0;
dfs->det_print2 = 0;
dfs->print_hist_rpt = 0;
dfs->hist_cond_on = 1;
if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
dfs->hist_cond_on = 1;
else
dfs->hist_cond_on = 0;
/*@for dynamic dfs*/
dfs->pwdb_th = 8;
dfs->fa_mask_th = 30;
dfs->fa_mask_th = 30 * (dfs->dfs_polling_time / 100);
dfs->st_l2h_min = 0x20;
dfs->st_l2h_max = 0x4e;
dfs->pwdb_scalar_factor = 12;
@@ -738,7 +839,7 @@ phydm_radar_detect_dm_check(
u16 short_pulse_cnt_inc = 0, long_pulse_cnt_cur = 0;
u16 long_pulse_cnt_inc = 0, total_pulse_count_inc = 0;
u32 regf98_value = 0, reg918_value = 0, reg91c_value = 0;
u32 reg920_value = 0, reg924_value = 0, dbgport2dbc_value = 0;
u32 reg920_value = 0, reg924_value = 0, radar_rpt_reg_value = 0;
u32 regf54_value = 0, regf58_value = 0, regf5c_value = 0;
u32 regdf4_value = 0, regf70_value = 0, regf74_value = 0;
u32 rega40_value = 0, rega44_value = 0, rega48_value = 0;
@@ -895,15 +996,17 @@ phydm_radar_detect_dm_check(
ht_crc_ok_cnt_inc +
leg_crc_ok_cnt_inc;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x3b0)) {
odm_set_bb_reg(dm, 0x1e28, 0x03c00000, 8);
dbgport2dbc_value = phydm_get_bb_dbg_port_val(dm);
phydm_release_bb_dbg_port(dm);
}
short_pulse_cnt_cur = (u16)((dbgport2dbc_value & 0x000ff800)
if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
ODM_RTL8197G)) {
/* if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x3b0)) {
* odm_set_bb_reg(dm, 0x1e28, 0x03c00000, 8);
* dbgport2dbc_value = phydm_get_bb_dbg_port_val(dm);
* phydm_release_bb_dbg_port(dm); }
*/
radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e00, 0xffffffff);
short_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x000ff800)
>> 11);
long_pulse_cnt_cur = (u16)((dbgport2dbc_value & 0x0fc00000)
long_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x0fc00000)
>> 22);
#if (RTL8721D_SUPPORT)
} else if (dm->support_ic_type & (ODM_RTL8721D)) {
@@ -920,6 +1023,17 @@ phydm_radar_detect_dm_check(
odm_set_bb_reg(dm, R_0xf58, BIT(29), 1);
}
#endif
} else if (dm->support_ic_type & (ODM_RTL8814B)) {
if (dm->seg1_dfs_flag == 1)
radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e20,
0xffffffff);
else
radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e00,
0xffffffff);
short_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x000ff800)
>> 11);
long_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x0fc00000)
>> 22);
} else {
regf98_value = odm_get_bb_reg(dm, R_0xf98, 0xffffffff);
short_pulse_cnt_cur = (u16)(regf98_value & 0x000000ff);
@@ -973,7 +1087,7 @@ phydm_radar_detect_dm_check(
PHYDM_DBG(dm, DBG_DFS,
"Init_Gain[%x] st_l2h_cur[%x] 0x2dbc[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
dfs->igi_cur, dfs->st_l2h_cur,
dbgport2dbc_value, short_pulse_cnt_inc,
radar_rpt_reg_value, short_pulse_cnt_inc,
long_pulse_cnt_inc);
rega40_value = odm_get_bb_reg(dm, R_0xa40, MASKDWORD);
rega44_value = odm_get_bb_reg(dm, R_0xa44, MASKDWORD);
@@ -1013,8 +1127,8 @@ phydm_radar_detect_dm_check(
dfs->hist_cond_on);
}
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
tri_short_pulse = (dbgport2dbc_value & BIT(20)) ? 1 : 0;
tri_long_pulse = (dbgport2dbc_value & BIT(28)) ? 1 : 0;
tri_short_pulse = (radar_rpt_reg_value & BIT(20)) ? 1 : 0;
tri_long_pulse = (radar_rpt_reg_value & BIT(28)) ? 1 : 0;
} else {
tri_short_pulse = (regf98_value & BIT(17)) ? 1 : 0;
tri_long_pulse = (regf98_value & BIT(19)) ? 1 : 0;
@@ -1096,8 +1210,7 @@ phydm_radar_detect_dm_check(
if (dfs->mask_hist_checked >= 5 && dfs->pulse_flag_hist[index]) {
if (sum <= 2) {
if (dfs->hist_cond_on &&
(!(dm->support_ic_type & ODM_RTL8721D))) {
if (dfs->hist_cond_on) {
/*return the value from hist_radar_detected*/
radar_detected = phydm_dfs_hist_log(dm, index);
} else {
@@ -1925,10 +2038,12 @@ boolean phydm_radar_detect(void *dm_void)
dfs->igi_pre = dfs->igi_cur;
phydm_dfs_dynamic_setting(dm);
phydm_dfs_histogram_radar_distinguish(dm);
if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
phydm_dfs_histogram_radar_distinguish(dm);
radar_detected = phydm_radar_detect_dm_check(dm);
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
ODM_RTL8197G)) {
if (odm_get_bb_reg(dm, R_0xa40, BIT(15)))
enable_DFS = true;
#if (RTL8721D_SUPPORT)
@@ -1936,6 +2051,12 @@ boolean phydm_radar_detect(void *dm_void)
if (odm_get_bb_reg(dm, R_0xf58, BIT(29)))
enable_DFS = true;
#endif
} else if (dm->support_ic_type & (ODM_RTL8814B)) {
if (dm->seg1_dfs_flag == 1) {
if (odm_get_bb_reg(dm, R_0xa6c, BIT(15)))
enable_DFS = true;
} else if (odm_get_bb_reg(dm, R_0xa40, BIT(15)))
enable_DFS = true;
} else {
if (odm_get_bb_reg(dm, R_0x924, BIT(15)))
enable_DFS = true;
@@ -2265,14 +2386,14 @@ void phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used,
u8 phydm_dfs_polling_time(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 dfs_polling_time = 0;
struct _DFS_STATISTICS *dfs = &dm->dfs;
if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
dfs_polling_time = 40;
dfs->dfs_polling_time = 40;
else
dfs_polling_time = 100;
dfs->dfs_polling_time = 100;
return dfs_polling_time;
return dfs->dfs_polling_time;
}
#endif /* @defined(CONFIG_PHYDM_DFS_MASTER) */

7
hal/phydm/phydm_dfs.h
View File

@@ -76,6 +76,7 @@ struct _DFS_STATISTICS {
boolean det_print;
boolean det_print2;
boolean radar_type;
u8 dfs_polling_time;
/*@dfs histogram*/
boolean print_hist_rpt;
boolean hist_cond_on;
@@ -175,6 +176,12 @@ u8 phydm_dfs_polling_time(void *dm_void);
boolean
phydm_dfs_is_meteorology_channel(void *dm_void);
void
phydm_dfs_segment_distinguish(void *dm_void, enum rf_syn syn_path);
void
phydm_dfs_segment_flag_reset(void *dm_void);
boolean
phydm_is_dfs_band(void *dm_void);

356
hal/phydm/phydm_dig.c
View File

@@ -43,7 +43,7 @@ void phydm_dig_recorder_reset(void *dm_void)
sizeof(struct phydm_dig_recorder_strcut));
}
void phydm_dig_recorder(void *dm_void, boolean first_connect, u8 igi_curr,
void phydm_dig_recorder(void *dm_void, u8 igi_curr,
u32 fa_cnt)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
@@ -57,7 +57,7 @@ void phydm_dig_recorder(void *dm_void, boolean first_connect, u8 igi_curr,
PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
if (first_connect) {
if (dm->first_connect) {
phydm_dig_recorder_reset(dm);
dig_rc->igi_history[0] = igi_curr;
dig_rc->fa_history[0] = fa_cnt;
@@ -414,22 +414,61 @@ void phydm_fa_cnt_statistics_jgr3(void *dm_void)
cck_tx_counter = (u16)odm_get_bb_reg(dm, R_0x2de4, MASKLWORD);
ret_value = odm_get_bb_reg(dm, R_0x2d20, MASKDWORD);
fa_t->cnt_fast_fsync = (ret_value & 0xffff);
fa_t->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
fa_t->cnt_fast_fsync = ret_value & 0xffff;
fa_t->cnt_sb_search_fail = (ret_value & 0xffff0000) >> 16;
ret_value = odm_get_bb_reg(dm, R_0x2d04, MASKDWORD);
fa_t->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
fa_t->cnt_parity_fail = (ret_value & 0xffff0000) >> 16;
ret_value = odm_get_bb_reg(dm, R_0x2d08, MASKDWORD);
fa_t->cnt_rate_illegal = (ret_value & 0xffff);
fa_t->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
fa_t->cnt_rate_illegal = ret_value & 0xffff;
fa_t->cnt_crc8_fail = (ret_value & 0xffff0000) >> 16;
ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
fa_t->cnt_mcs_fail = (ret_value & 0xffff);
fa_t->cnt_mcs_fail = ret_value & 0xffff;
/* @read OFDM FA counter, subtract tx_cnt due to new design of brk_cnt*/
fa_t->cnt_ofdm_fail = odm_get_bb_reg(dm, R_0x2d00, MASKLWORD)
- ofdm_tx_counter;
/* read CCK CRC32 counter */
ret_value = odm_get_bb_reg(dm, R_0x2c04, MASKDWORD);
fa_t->cnt_cck_crc32_ok = ret_value & 0xffff;
fa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16;
/* read OFDM CRC32 counter */
ret_value = odm_get_bb_reg(dm, R_0x2c14, MASKDWORD);
fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;
fa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16;
/* read HT CRC32 counter */
ret_value = odm_get_bb_reg(dm, R_0x2c10, MASKDWORD);
fa_t->cnt_ht_crc32_ok = ret_value & 0xffff;
fa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16;
/* @for VHT part */
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
ODM_RTL8814B)) {
/* @read VHT CRC32 counter */
ret_value = odm_get_bb_reg(dm, R_0x2c0c, MASKDWORD);
fa_t->cnt_vht_crc32_ok = ret_value & 0xffff;
fa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16;
ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
fa_t->cnt_mcs_fail_vht = (ret_value & 0xffff0000) >> 16;
ret_value = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD);
fa_t->cnt_crc8_fail_vhta = ret_value & 0xffff;
fa_t->cnt_crc8_fail_vhtb = (ret_value & 0xffff0000) >> 16;
} else {
fa_t->cnt_vht_crc32_error = 0;
fa_t->cnt_vht_crc32_ok = 0;
fa_t->cnt_mcs_fail_vht = 0;
fa_t->cnt_crc8_fail_vhta = 0;
fa_t->cnt_crc8_fail_vhtb = 0;
}
/* @calculate OFDM FA counter instead of reading brk_cnt*/
fa_t->cnt_ofdm_fail = fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal +
fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail +
fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail +
fa_t->cnt_mcs_fail_vht + fa_t->cnt_crc8_fail_vhta;
/* Read CCK FA counter */
fa_t->cnt_cck_fail = odm_get_bb_reg(dm, R_0x1a5c, MASKLWORD);
@@ -439,42 +478,6 @@ void phydm_fa_cnt_statistics_jgr3(void *dm_void)
fa_t->cnt_ofdm_cca = ((ret_value & 0xffff0000) >> 16);
fa_t->cnt_cck_cca = ret_value & 0xffff;
/* read CCK CRC32 counter */
ret_value = odm_get_bb_reg(dm, R_0x2c04, MASKDWORD);
fa_t->cnt_cck_crc32_error = ((ret_value & 0xffff0000) >> 16);
fa_t->cnt_cck_crc32_ok = ret_value & 0xffff;
/* read OFDM CRC32 counter */
ret_value = odm_get_bb_reg(dm, R_0x2c14, MASKDWORD);
fa_t->cnt_ofdm_crc32_error = ((ret_value & 0xffff0000) >> 16);
fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;
/* read HT CRC32 counter */
ret_value = odm_get_bb_reg(dm, R_0x2c10, MASKDWORD);
fa_t->cnt_ht_crc32_error = ((ret_value & 0xffff0000) >> 16);
fa_t->cnt_ht_crc32_ok = ret_value & 0xffff;
/* @for VHT part */
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
ODM_RTL8814B)) {
/* read VHT CRC32 counter */
ret_value = odm_get_bb_reg(dm, R_0x2c0c, MASKDWORD);
fa_t->cnt_vht_crc32_error = ((ret_value & 0xffff0000) >> 16);
fa_t->cnt_vht_crc32_ok = ret_value & 0xffff;
ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
fa_t->cnt_mcs_fail_vht = ((ret_value & 0xffff0000) >> 16);
ret_value = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD);
fa_t->cnt_crc8_fail_vht = (ret_value & 0xffff) +
((ret_value & 0xffff0000) >> 16);
} else {
fa_t->cnt_vht_crc32_error = 0;
fa_t->cnt_vht_crc32_ok = 0;
fa_t->cnt_mcs_fail_vht = 0;
fa_t->cnt_crc8_fail_vht = 0;
}
/* @CCK RxIQ weighting = 1 => 0x1a14[9:8]=0x0 */
cck_enable = odm_get_bb_reg(dm, R_0x1a14, 0x300);
if (cck_enable == 0x0) { /* @if(*dm->band_type == ODM_BAND_2_4G) */
@@ -523,6 +526,7 @@ void phydm_write_dig_reg(void *dm_void, u8 igi)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
u8 rf_gain = 0;
PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
@@ -533,6 +537,24 @@ void phydm_write_dig_reg(void *dm_void, u8 igi)
#endif
phydm_write_dig_reg_c50(dm, igi);
#if (RTL8721D_SUPPORT)
if (dm->invalid_mode) {
if (igi <= 0x10)
rf_gain = 0xfa;
else if (igi <= 0x40)
rf_gain = 0xe3 + 0x20 - (igi >> 1);
else if (igi <= 0x50)
rf_gain = 0xcb - (igi >> 1);
else if (igi <= 0x5e)
rf_gain = 0x92 - (igi >> 1);
else if (igi <= 0x64)
rf_gain = 0x74 - (igi >> 1);
else
rf_gain = (0x3d > (igi >> 1)) ? (0x3d - (igi >> 1)) : 0;
odm_set_bb_reg(dm, R_0x850, 0x1fe0, rf_gain);
}
#endif
dig_t->cur_ig_value = igi;
}
@@ -580,13 +602,13 @@ void odm_write_dig(void *dm_void, u8 new_igi)
/*@Add by YuChen for USB IO too slow issue*/
if (!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
if (dm->support_ability & ODM_BB_ADAPTIVITY &&
if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
new_igi < dig_t->cur_ig_value) {
dig_t->cur_ig_value = new_igi;
phydm_adaptivity(dm);
}
} else {
if (dm->support_ability & ODM_BB_ADAPTIVITY &&
if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
new_igi > dig_t->cur_ig_value) {
dig_t->cur_ig_value = new_igi;
phydm_adaptivity(dm);
@@ -686,7 +708,7 @@ void odm_pause_dig(void *dm_void, enum phydm_pause_type type,
break;
}
PHYDM_DBG(dm, DBG_DIG, "pause_result=%d\n", rpt);
PHYDM_DBG(dm, DBG_DIG, "DIG pause_result=%d\n", rpt);
}
boolean
@@ -699,9 +721,8 @@ phydm_dig_abort(void *dm_void)
/* support_ability */
if ((!(dm->support_ability & ODM_BB_FA_CNT)) ||
(!(dm->support_ability & ODM_BB_DIG)) ||
*dm->is_scan_in_process) {
PHYDM_DBG(dm, DBG_DIG, "Not Support\n");
(!(dm->support_ability & ODM_BB_DIG))) {
PHYDM_DBG(dm, DBG_DIG, "[DIG] Not Support\n");
return true;
}
@@ -711,6 +732,11 @@ phydm_dig_abort(void *dm_void)
return true;
}
if (*dm->is_scan_in_process) {
PHYDM_DBG(dm, DBG_DIG, "Return: Scan in process\n");
return true;
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if OS_WIN_FROM_WIN7(OS_VERSION)
if (IsAPModeExist(adapter) && ((PADAPTER)(adapter))->bInHctTest) {
@@ -739,8 +765,6 @@ void phydm_dig_init(void *dm_void)
dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);
dig_t->is_media_connect = false;
dig_t->fa_th[0] = 250;
dig_t->fa_th[1] = 500;
dig_t->fa_th[2] = 750;
@@ -786,7 +810,6 @@ void phydm_dig_init(void *dm_void)
dig_t->dig_dl_en = 1;
#endif
}
void phydm_dig_abs_boundary_decision(struct dm_struct *dm, boolean is_dfs_band)
{
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
@@ -814,8 +837,8 @@ void phydm_dig_abs_boundary_decision(struct dm_struct *dm, boolean is_dfs_band)
#endif
} else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {
/*service 1 devices*/
if (adapt->is_adapt_en && (dm->support_ic_type &
(ODM_RTL8197F | ODM_RTL8192F)))
if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
/*dig_max shouldn't be too high because of adaptivity*/
dig_t->dm_dig_max =
MIN_2((adapt->th_l2h + 40),
@@ -954,10 +977,6 @@ u8 phydm_get_new_igi(struct dm_struct *dm, u8 igi, u32 fa_cnt,
{
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
u8 step[3] = {0};
boolean first_connect = false, first_dis_connect = false;
first_connect = (dm->is_linked) && !dig_t->is_media_connect;
first_dis_connect = (!dm->is_linked) && dig_t->is_media_connect;
if (dm->is_linked) {
if (dm->pre_rssi_min <= dm->rssi_min) {
@@ -979,7 +998,7 @@ u8 phydm_get_new_igi(struct dm_struct *dm, u8 igi, u32 fa_cnt,
PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1],
step[0]);
if (first_connect) {
if (dm->first_connect) {
if (is_dfs_band) {
if (dm->rssi_min > DIG_MAX_DFS)
igi = DIG_MAX_DFS;
@@ -1020,7 +1039,7 @@ u8 phydm_get_new_igi(struct dm_struct *dm, u8 igi, u32 fa_cnt,
/* @2 Before link */
PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n");
if (first_dis_connect) {
if (dm->first_disconnect) {
igi = dig_t->dm_dig_min;
PHYDM_DBG(dm, DBG_DIG,
"First disconnect:foce IGI to lower bound\n");
@@ -1071,7 +1090,6 @@ void phydm_dig(void *dm_void)
#ifdef PHYDM_TDMA_DIG_SUPPORT
struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
#endif
boolean first_connect, first_disconnect;
u8 igi = dig_t->cur_ig_value;
u8 new_igi = 0x20;
u32 fa_cnt = falm_cnt->cnt_all;
@@ -1093,14 +1111,10 @@ void phydm_dig(void *dm_void)
}
PHYDM_DBG(dm, DBG_DIG, "%s Start===>\n", __func__);
/* @1 Update status */
first_connect = (dm->is_linked) && !dig_t->is_media_connect;
first_disconnect = (!dm->is_linked) && dig_t->is_media_connect;
PHYDM_DBG(dm, DBG_DIG,
"is_linked=%d, RSSI=%d, 1stConnect=%d, 1stDisconnect=%d\n",
dm->is_linked, dm->rssi_min, first_connect, first_disconnect);
dm->is_linked, dm->rssi_min,
dm->first_connect, dm->first_disconnect);
PHYDM_DBG(dm, DBG_DIG, "DIG ((%s)) mode\n",
(*dm->bb_op_mode ? "Balance" : "Performance"));
@@ -1110,7 +1124,7 @@ void phydm_dig(void *dm_void)
#ifdef CFG_DIG_DAMPING_CHK
/*Record IGI History*/
phydm_dig_recorder(dm, first_connect, igi, fa_cnt);
phydm_dig_recorder(dm, igi, fa_cnt);
/*@DIG Damping Check*/
phydm_dig_damping_chk(dm);
@@ -1142,8 +1156,6 @@ void phydm_dig(void *dm_void)
} else
#endif
odm_write_dig(dm, new_igi);
dig_t->is_media_connect = dm->is_linked;
}
void phydm_dig_lps_32k(void *dm_void)
@@ -1429,25 +1441,25 @@ void phydm_fa_cnt_statistics_ac(void *dm_void)
return;
ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11AC, MASKDWORD);
fa_t->cnt_fast_fsync = ((ret_value & 0xffff0000) >> 16);
fa_t->cnt_fast_fsync = (ret_value & 0xffff0000) >> 16;
ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11AC, MASKDWORD);
fa_t->cnt_sb_search_fail = (ret_value & 0xffff);
fa_t->cnt_sb_search_fail = ret_value & 0xffff;
ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11AC, MASKDWORD);
fa_t->cnt_parity_fail = (ret_value & 0xffff);
fa_t->cnt_rate_illegal = ((ret_value & 0xffff0000) >> 16);
fa_t->cnt_parity_fail = ret_value & 0xffff;
fa_t->cnt_rate_illegal = (ret_value & 0xffff0000) >> 16;
ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11AC, MASKDWORD);
fa_t->cnt_crc8_fail = (ret_value & 0xffff);
fa_t->cnt_mcs_fail = ((ret_value & 0xffff0000) >> 16);
fa_t->cnt_crc8_fail = ret_value & 0xffff;
fa_t->cnt_mcs_fail = (ret_value & 0xffff0000) >> 16;
ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE5_11AC, MASKDWORD);
fa_t->cnt_crc8_fail_vht = (ret_value & 0xffff) +
(ret_value & 0xffff0000 >> 16);
fa_t->cnt_crc8_fail_vhta = ret_value & 0xffff;
fa_t->cnt_crc8_fail_vhtb = ret_value & 0xffff0000 >> 16;
ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE6_11AC, MASKDWORD);
fa_t->cnt_mcs_fail_vht = (ret_value & 0xffff);
fa_t->cnt_mcs_fail_vht = ret_value & 0xffff;
/* read OFDM FA counter */
fa_t->cnt_ofdm_fail = odm_get_bb_reg(dm, R_0xf48, MASKLWORD);
@@ -1572,8 +1584,8 @@ void phydm_false_alarm_counter_statistics(void *dm_void)
fa_t->cnt_sb_search_fail * 12 +
fa_t->cnt_parity_fail * 28 +
fa_t->cnt_rate_illegal * 28 +
fa_t->cnt_crc8_fail * 36 +
fa_t->cnt_crc8_fail_vht * 36 +
fa_t->cnt_crc8_fail * 20 +
fa_t->cnt_crc8_fail_vhta * 28 +
fa_t->cnt_mcs_fail_vht * 36 +
fa_t->cnt_mcs_fail * 32 +
fa_t->cnt_cck_fail * 80;
@@ -1593,9 +1605,10 @@ void phydm_false_alarm_counter_statistics(void *dm_void)
fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail);
PHYDM_DBG(dm, DBG_FA_CNT,
"[OFDM FA Detail-2] Fast_Fsync=((%d)), SBD=((%d)), VHT_CRC8=((%d)), VHT_MCS=((%d))\n",
"[OFDM FA Detail-2] Fast_Fsync=((%d)), SBD=((%d)), VHT_SIGA_CRC8=((%d)), VHT_SIGB_CRC8=((%d)), VHT_MCS=((%d))\n",
fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail,
fa_t->cnt_crc8_fail_vht, fa_t->cnt_mcs_fail_vht);
fa_t->cnt_crc8_fail_vhta, fa_t->cnt_crc8_fail_vhtb,
fa_t->cnt_mcs_fail_vht);
PHYDM_DBG(dm, DBG_FA_CNT,
"[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all);
@@ -1668,7 +1681,8 @@ void phydm_tdma_dig_timer_check(void *dm_void)
#ifdef IS_USE_NEW_TDMA
if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B |
ODM_RTL8812F | ODM_RTL8822B | ODM_RTL8192F |
ODM_RTL8821C)) {
ODM_RTL8821C | ODM_RTL8197G | ODM_RTL8822C |
ODM_RTL8723D)) {
PHYDM_DBG(dm, DBG_DIG,
"Check fail, Restart timer\n\n");
phydm_false_alarm_counter_reset(dm);
@@ -1676,7 +1690,7 @@ void phydm_tdma_dig_timer_check(void *dm_void)
dm->tdma_dig_timer_ms);
} else {
PHYDM_DBG(dm, DBG_DIG,
"Not 98F/14B/12F/22B/92F/21C no SW timer\n");
"Not support TDMADIG, no SW timer\n");
}
#else
/*@if interrupt mask info is got.*/
@@ -1949,9 +1963,9 @@ void phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input)
dm->original_dig_restore = !((boolean)input);
break;
case MODE_DECISION:
if (input == MODE_PERFORMANCE)
if (input == (u8)MODE_PERFORMANCE)
dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES + 2;
else if (input == MODE_COVERAGE)
else if (input == (u8)MODE_COVERAGE)
dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
else
dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
@@ -1960,10 +1974,61 @@ void phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input)
}
#ifdef IS_USE_NEW_TDMA
#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
static void pre_phydm_tdma_dig_cbk(unsigned long task_dm)
{
struct dm_struct *dm = (struct dm_struct *)task_dm;
struct rtl8192cd_priv *priv = dm->priv;
struct priv_shared_info *pshare = priv->pshare;
if (!(priv->drv_state & DRV_STATE_OPEN))
return;
if (pshare->bDriverStopped || pshare->bSurpriseRemoved) {
printk("[%s] bDriverStopped(%d) OR bSurpriseRemoved(%d)\n",
__FUNCTION__, pshare->bDriverStopped,
pshare->bSurpriseRemoved);
return;
}
rtw_enqueue_timer_event(priv, &pshare->tdma_dig_event,
ENQUEUE_TO_TAIL);
}
void phydm_tdma_dig_timers_usb(void *dm_void, u8 state)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
if (state == INIT_TDMA_DIG_TIMMER) {
struct rtl8192cd_priv *priv = dm->priv;
init_timer(&dm->tdma_dig_timer);
dm->tdma_dig_timer.data = (unsigned long)dm;
dm->tdma_dig_timer.function = pre_phydm_tdma_dig_cbk;
INIT_TIMER_EVENT_ENTRY(&priv->pshare->tdma_dig_event,
phydm_tdma_dig_cbk,
(unsigned long)dm);
} else if (state == CANCEL_TDMA_DIG_TIMMER) {
odm_cancel_timer(dm, &dm->tdma_dig_timer);
} else if (state == RELEASE_TDMA_DIG_TIMMER) {
odm_release_timer(dm, &dm->tdma_dig_timer);
}
}
#endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */
void phydm_tdma_dig_timers(void *dm_void, u8 state)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
struct rtl8192cd_priv *priv = dm->priv;
if (priv->hci_type == RTL_HCI_USB) {
phydm_tdma_dig_timers_usb(dm_void, state);
return;
}
#endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */
if (state == INIT_TDMA_DIG_TIMMER)
odm_initialize_timer(dm, &dm->tdma_dig_timer,
@@ -1981,10 +2046,6 @@ u8 get_new_igi_bound(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *rx_gain_max,
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
u8 step[3] = {0};
u8 cur_igi = igi;
boolean first_connect = false, first_dis_connect = false;
first_connect = (dm->is_linked) && !dig_t->is_media_connect;
first_dis_connect = (!dm->is_linked) && dig_t->is_media_connect;
if (dm->is_linked) {
if (dm->pre_rssi_min <= dm->rssi_min) {
@@ -2006,7 +2067,7 @@ u8 get_new_igi_bound(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *rx_gain_max,
PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1],
step[0]);
if (first_connect) {
if (dm->first_connect) {
if (is_dfs_band) {
if (dm->rssi_min > DIG_MAX_DFS)
igi = DIG_MAX_DFS;
@@ -2032,7 +2093,7 @@ u8 get_new_igi_bound(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *rx_gain_max,
/* @2 Before link */
PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n");
if (first_dis_connect) {
if (dm->first_disconnect) {
igi = dig_t->dm_dig_min;
PHYDM_DBG(dm, DBG_DIG,
"First disconnect:foce IGI to lower bound\n");
@@ -2056,14 +2117,9 @@ u8 get_new_igi_bound(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *rx_gain_max,
return igi;
}
/*@callback function triggered by SW timer*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void phydm_tdma_dig_cbk(struct phydm_timer_list *timer)
void phydm_tdma_dig_new(void *dm_void)
{
void *adapter = (void *)timer->Adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
if (phydm_dig_abort(dm) || dm->original_dig_restore)
@@ -2097,6 +2153,35 @@ void phydm_tdma_dig_cbk(struct phydm_timer_list *timer)
odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
}
/*@callback function triggered by SW timer*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void phydm_tdma_dig_cbk(struct phydm_timer_list *timer)
{
void *adapter = (void *)timer->Adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrcs;
#if DEV_BUS_TYPE == RT_PCI_INTERFACE
#if USE_WORKITEM
odm_schedule_work_item(&dm->phydm_tdma_dig_workitem);
#else
phydm_tdma_dig_new(dm);
#endif
#else
odm_schedule_work_item(&dm->phydm_tdma_dig_workitem);
#endif
}
void phydm_tdma_dig_workitem_callback(void *context)
{
void *adapter = (void *)context;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
phydm_tdma_dig_new(dm);
}
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
void phydm_tdma_dig_cbk(void *dm_void)
{
@@ -2195,7 +2280,7 @@ void phydm_tdma_fa_cnt_chk(void *dm_void)
struct phydm_fa_acc_struct *fa_t_acc = &dm->false_alm_cnt_acc;
struct phydm_fa_acc_struct *fa_t_acc_low = &dm->false_alm_cnt_acc_low;
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
boolean rssi_dump_en = false;
boolean tdma_dig_block_1sec_flag = false;
u32 timestamp = 0;
u8 states_per_block = dm->tdma_dig_state_number;
u8 cur_tdma_dig_state = 0;
@@ -2229,7 +2314,7 @@ void phydm_tdma_fa_cnt_chk(void *dm_void)
/*@1sec dump check*/
if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)
rssi_dump_en = true;
tdma_dig_block_1sec_flag = true;
/*@
*PHYDM_DBG(dm, DBG_DIG,"[L-state] tdma_dig_block_cnt=%d\n",
@@ -2238,11 +2323,12 @@ void phydm_tdma_fa_cnt_chk(void *dm_void)
/*@collect FA till this block end*/
phydm_false_alarm_counter_statistics(dm);
phydm_fa_cnt_acc(dm, rssi_dump_en, cur_tdma_dig_state);
phydm_fa_cnt_acc(dm, tdma_dig_block_1sec_flag,
cur_tdma_dig_state);
/*@1s L-FA collect end*/
/*@1sec dump reached*/
if (rssi_dump_en) {
if (tdma_dig_block_1sec_flag) {
/*@L-DIG*/
phydm_noisy_detection(dm);
#ifdef PHYDM_SUPPORT_CCKPD
@@ -2255,7 +2341,7 @@ void phydm_tdma_fa_cnt_chk(void *dm_void)
} else if (cur_tdma_dig_state == 1) {
/*@1sec dump check*/
if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)
rssi_dump_en = true;
tdma_dig_block_1sec_flag = true;
/*@
*PHYDM_DBG(dm, DBG_DIG,"[H-state] tdma_dig_block_cnt=%d\n",
@@ -2264,12 +2350,13 @@ void phydm_tdma_fa_cnt_chk(void *dm_void)
/*@collect FA till this block end*/
phydm_false_alarm_counter_statistics(dm);
phydm_fa_cnt_acc(dm, rssi_dump_en, cur_tdma_dig_state);
phydm_fa_cnt_acc(dm, tdma_dig_block_1sec_flag,
cur_tdma_dig_state);
/*@1s H-FA collect end*/
/*@1sec dump reached*/
state_diff = dm->tdma_dig_state_number - dig_t->tdma_dig_state;
if (rssi_dump_en && (state_diff == 1)) {
if (tdma_dig_block_1sec_flag && state_diff == 1) {
/*@H-DIG*/
phydm_noisy_detection(dm);
#ifdef PHYDM_SUPPORT_CCKPD
@@ -2310,7 +2397,6 @@ void phydm_tdma_low_dig(void *dm_void)
#ifdef CFG_DIG_DAMPING_CHK
struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
#endif
boolean first_connect, first_disconnect = false;
u8 igi = dig_t->cur_ig_value;
u8 new_igi = 0x20;
u8 tdma_l_igi = dig_t->low_ig_value;
@@ -2377,18 +2463,20 @@ void phydm_tdma_low_dig(void *dm_void)
/* @DIG lower bound in L-state*/
tdma_l_dym_min = dig_t->dm_dig_min;
#ifdef CFG_DIG_DAMPING_CHK
/*@Limit Dyn min by damping*/
if (dig_t->dig_dl_en &&
dig_rc->damping_limit_en &&
tdma_l_dym_min < dig_rc->damping_limit_val) {
PHYDM_DBG(dm, DBG_DIG,
"[Limit by Damping] dyn_min=0x%x -> 0x%x\n",
tdma_l_dym_min, dig_rc->damping_limit_val);
tdma_l_dym_min = dig_rc->damping_limit_val;
}
#endif
/*@
*#ifdef CFG_DIG_DAMPING_CHK
*@Limit Dyn min by damping
*if (dig_t->dig_dl_en &&
* dig_rc->damping_limit_en &&
* tdma_l_dym_min < dig_rc->damping_limit_val) {
* PHYDM_DBG(dm, DBG_DIG,
* "[Limit by Damping] dyn_min=0x%x -> 0x%x\n",
* tdma_l_dym_min, dig_rc->damping_limit_val);
*
* tdma_l_dym_min = dig_rc->damping_limit_val;
*}
*#endif
*/
/*@DIG upper bound in L-state*/
igi_upper_rssi_min = rssi_min + offset;
@@ -2453,8 +2541,6 @@ void phydm_tdma_low_dig(void *dm_void)
} else {
odm_write_dig(dm, new_igi);
}
dig_t->is_media_connect = dm->is_linked;
}
void phydm_tdma_high_dig(void *dm_void)
@@ -2466,7 +2552,6 @@ void phydm_tdma_high_dig(void *dm_void)
#ifdef CFG_DIG_DAMPING_CHK
struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
#endif
boolean first_connect, first_disconnect = false;
u8 igi = dig_t->cur_ig_value;
u8 new_igi = 0x20;
u8 tdma_h_igi = dig_t->cur_ig_value_tdma;
@@ -2630,11 +2715,9 @@ void phydm_tdma_high_dig(void *dm_void)
} else {
odm_write_dig(dm, new_igi);
}
dig_t->is_media_connect = dm->is_linked;
}
void phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en,
void phydm_fa_cnt_acc(void *dm_void, boolean tdma_dig_block_1sec_flag,
u8 cur_tdma_dig_state)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
@@ -2653,7 +2736,7 @@ void phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en,
/*@
*PHYDM_DBG(dm, DBG_DIG,
* "[%s] ==> dig_state=%d, one_sec=%d\n", __func__,
* cur_tdma_dig_state, rssi_dump_en);
* cur_tdma_dig_state, tdma_dig_block_1sec_flag);
*/
falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;
falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;
@@ -2690,7 +2773,7 @@ void phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en,
* falm_cnt->cnt_ofdm_fail,
* falm_cnt->cnt_all);
*/
if (rssi_dump_en == 1) {
if (tdma_dig_block_1sec_flag) {
total_state_number = dm->tdma_dig_state_number;
if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE) {
@@ -2807,11 +2890,12 @@ void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output,
}
#ifdef CONFIG_MCC_DM
#if (RTL8822B_SUPPORT)
#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT)
void phydm_mcc_igi_clr(void *dm_void, u8 clr_port)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
mcc_dm->mcc_rssi[clr_port] = 0xff;
mcc_dm->mcc_dm_val[0][clr_port] = 0xff; /* 0xc50 clr */
mcc_dm->mcc_dm_val[1][clr_port] = 0xff; /* 0xe50 clr */
@@ -2841,6 +2925,7 @@ void phydm_mcc_igi_cal(void *dm_void)
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
u8 shift = 0;
u8 igi_val0, igi_val1;
if (mcc_dm->mcc_rssi[0] == 0xff)
phydm_mcc_igi_clr(dm, 0);
if (mcc_dm->mcc_rssi[1] == 0xff)
@@ -2848,8 +2933,13 @@ void phydm_mcc_igi_cal(void *dm_void)
phydm_mcc_igi_chk(dm);
igi_val0 = mcc_dm->mcc_rssi[0] - shift;
igi_val1 = mcc_dm->mcc_rssi[1] - shift;
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
phydm_fill_mcccmd(dm, 0, R_0x1d70, igi_val0, igi_val1);
phydm_fill_mcccmd(dm, 1, R_0x1d70 + 1, igi_val0, igi_val1);
#else
phydm_fill_mcccmd(dm, 0, 0xc50, igi_val0, igi_val1);
phydm_fill_mcccmd(dm, 1, 0xe50, igi_val0, igi_val1);
#endif
PHYDM_DBG(dm, DBG_COMP_MCC, "RSSI_min: %d %d, MCC_igi: %d %d\n",
mcc_dm->mcc_rssi[0], mcc_dm->mcc_rssi[1],
mcc_dm->mcc_dm_val[0][0], mcc_dm->mcc_dm_val[0][1]);

12
hal/phydm/phydm_dig.h
View File

@@ -26,7 +26,7 @@
#ifndef __PHYDMDIG_H__
#define __PHYDMDIG_H__
#define DIG_VERSION "2.3"
#define DIG_VERSION "2.5" /* @Add new fa_cnt for VHT-SIGA/VHT-SIGB*/
#define DIG_HW 0
#define DIG_LIMIT_PERIOD 60 /*@60 sec*/
@@ -143,14 +143,13 @@ struct phydm_dig_struct {
#endif
boolean is_dbg_fa_th;
u8 cur_ig_value;
u8 rvrt_val;
u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
u8 igi_backup;
u8 rx_gain_range_max; /*@dig_dynamic_max*/
u8 rx_gain_range_min; /*@dig_dynamic_min*/
u8 dm_dig_max; /*@Absolutly upper bound*/
u8 dm_dig_min; /*@Absolutly lower bound*/
u8 dig_max_of_min; /*@Absolutly max of min*/
boolean is_media_connect;
u32 ant_div_rssi_max;
u8 *is_p2p_in_process;
enum dig_goupcheck_level go_up_chk_lv;
@@ -158,7 +157,7 @@ struct phydm_dig_struct {
#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\
RTL8198F_SUPPORT || RTL8192F_SUPPORT || RTL8195B_SUPPORT ||\
RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8721D_SUPPORT ||\
RTL8812F_SUPPORT || RTL8197G_SUPPORT)
RTL8710C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
u8 rf_gain_idx;
u8 agc_table_idx;
u8 big_jump_lmt[16];
@@ -174,7 +173,7 @@ struct phydm_dig_struct {
u8 cur_ig_value_tdma;
u8 low_ig_value;
u8 tdma_dig_state; /*@To distinguish which state is now.(L-sate or H-state)*/
u8 tdma_dig_cnt; /*@for phydm_tdma_dig_timer_check use*/
u32 tdma_dig_cnt; /*@for phydm_tdma_dig_timer_check use*/
u8 pre_tdma_dig_cnt;
u8 sec_factor;
u32 cur_timestamp;
@@ -197,7 +196,8 @@ struct phydm_fa_struct {
u32 cnt_parity_fail;
u32 cnt_rate_illegal;
u32 cnt_crc8_fail;
u32 cnt_crc8_fail_vht;
u32 cnt_crc8_fail_vhta;
u32 cnt_crc8_fail_vhtb;
u32 cnt_mcs_fail;
u32 cnt_mcs_fail_vht;
u32 cnt_ofdm_fail;

366
hal/phydm/phydm_direct_bf.c Normal file
View File

@@ -0,0 +1,366 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*@************************************************************
* include files
***************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef CONFIG_DIRECTIONAL_BF
#ifdef PHYDM_COMPILE_IC_2SS
void phydm_iq_gen_en(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
enum rf_path i = RF_PATH_A;
enum rf_path path = RF_PATH_A;
#if (ODM_IC_11AC_SERIES_SUPPORT)
if (dm->support_ic_type & ODM_RTL8822B) {
for (i = RF_PATH_A; i <= RF_PATH_B; i++) {
/*RF mode table write enable*/
odm_set_rf_reg(dm, path, RF_0xef, BIT(19), 0x1);
/*Select RX mode*/
odm_set_rf_reg(dm, path, RF_0x33, 0xF, 3);
/*Set Table data*/
odm_set_rf_reg(dm, path, RF_0x3e, 0xfffff, 0x00036);
/*Set Table data*/
odm_set_rf_reg(dm, path, RF_0x3f, 0xfffff, 0x5AFCE);
/*RF mode table write disable*/
odm_set_rf_reg(dm, path, RF_0xef, BIT(19), 0x0);
}
}
#endif
#if (ODM_IC_11N_SERIES_SUPPORT)
if (dm->support_ic_type & ODM_RTL8192F) {
/*RF mode table write enable*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1);
odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1);
/* Path A */
odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x08000);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0005f);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x01042);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0004f);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x71fc2);
/* Path B */
odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x08000);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x00050);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x01042);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x00040);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x71fc2);
/*RF mode table write disable*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0);
odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0);
}
#endif
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
if (dm->support_ic_type & ODM_RTL8197G) {
/*RF mode table write enable*/
/* Path A */
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x000cf);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x71fc2);
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0);
/* Path B */
odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x000cf);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x71fc2);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x000ef);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x01042);
odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0);
}
#endif
}
void phydm_dis_cdd(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (ODM_IC_11AC_SERIES_SUPPORT)
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
odm_set_bb_reg(dm, R_0x808, 0x3ffff00, 0);
odm_set_bb_reg(dm, R_0x9ac, 0x1fff, 0);
odm_set_bb_reg(dm, R_0x9ac, BIT(13), 1);
}
#endif
#if (ODM_IC_11N_SERIES_SUPPORT)
if (dm->support_ic_type & ODM_IC_11N_SERIES) {
odm_set_bb_reg(dm, R_0x90c, 0xffffffff, 0x83321333);
/* Set Tx delay setting for CCK pathA,B*/
odm_set_bb_reg(dm, R_0xa2c, 0xf0000000, 0);
/*Enable Tx CDD for HT part when spatial expansion is applied*/
odm_set_bb_reg(dm, R_0xd00, BIT(8), 0);
/* Tx CDD for Legacy*/
odm_set_bb_reg(dm, R_0xd04, 0xf0000, 0);
/* Tx CDD for non-HT*/
odm_set_bb_reg(dm, R_0xd0c, 0x3c0, 0);
/* Tx CDD for HT SS1*/
odm_set_bb_reg(dm, R_0xd0c, 0xf8000, 0);
}
#endif
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
/* Tx CDD for Legacy Preamble*/
odm_set_bb_reg(dm, R_0x1cc0, 0xffffffff, 0x24800000);
/* Tx CDD for HT Preamble*/
odm_set_bb_reg(dm, R_0x1cb0, 0xffffffff, 0);
}
#endif
}
void phydm_pathb_q_matrix_rotate_en(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
phydm_iq_gen_en(dm);
/*#ifdef PHYDM_COMMON_API_SUPPORT*/
/*path selection is controlled by driver*/
#if 0
if (!phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB, BB_PATH_AB))
return;
#endif
phydm_dis_cdd(dm);
phydm_pathb_q_matrix_rotate(dm, 0);
#if (ODM_IC_11AC_SERIES_SUPPORT)
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
/*Set Q matrix r_v11 =1*/
odm_set_bb_reg(dm, R_0x195c, MASKDWORD, 0x40000);
/*Set Q matrix enable*/
odm_set_bb_reg(dm, R_0x191c, BIT(7), 1);
}
#endif
}
void phydm_pathb_q_matrix_rotate(void *dm_void, u16 idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (ODM_IC_11AC_SERIES_SUPPORT)
u32 phase_table_0[ANGLE_NUM] = {0x40000, 0x376CF, 0x20000, 0x00000,
0xFE0000, 0xFC8930, 0xFC0000,
0xFC8930, 0xFDFFFF, 0x000000,
0x020000, 0x0376CF};
u32 phase_table_1[ANGLE_NUM] = {0x00000, 0x1FFFF, 0x376CF, 0x40000,
0x0376CF, 0x01FFFF, 0x000000,
0xFDFFFF, 0xFC8930, 0xFC0000,
0xFC8930, 0xFDFFFF};
#endif
#if (ODM_IC_11N_SERIES_SUPPORT)
u32 phase_table_n_0[ANGLE_NUM] = {0x00, 0x0B, 0x02, 0x00, 0x02, 0x02,
0x04, 0x02, 0x0D, 0x09, 0x04, 0x0B};
u32 phase_table_n_1[ANGLE_NUM] = {0x40000100, 0x377F00DD, 0x201D8880,
0x00000000, 0xE01D8B80, 0xC8BF0322,
0xC000FF00, 0xC8BF0322, 0xDFE2777F,
0xFFC003FF, 0x20227480, 0x377F00DD};
u32 phase_table_n_2[ANGLE_NUM] = {0x00, 0x1E, 0x3C, 0x4C, 0x3C, 0x1E,
0x0F, 0xD2, 0xC3, 0xC4, 0xC3, 0xD2};
#endif
if (idx >= ANGLE_NUM) {
pr_debug("[%s]warning Phase Set Error: %d\n", __func__, idx);
return;
}
switch (dm->ic_ip_series) {
#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
case PHYDM_IC_AC:
/*Set Q matrix r_v21*/
odm_set_bb_reg(dm, R_0x1954, 0xffffff, phase_table_0[idx]);
odm_set_bb_reg(dm, R_0x1950, 0xffffff, phase_table_1[idx]);
break;
#endif
#if (ODM_IC_11N_SERIES_SUPPORT == 1)
case PHYDM_IC_N:
/*Set Q matrix r_v21*/
odm_set_bb_reg(dm, R_0xc4c, 0xff000000, phase_table_n_0[idx]);
odm_set_bb_reg(dm, R_0xc88, 0xffffffff, phase_table_n_1[idx]);
odm_set_bb_reg(dm, R_0xc9c, 0xff000000, phase_table_n_2[idx]);
break;
#endif
default:
break;
}
}
/*Before use this API, Fill correct Tx Des. and Disable STBC in advance*/
void phydm_set_direct_bfer(void *dm_void, u16 phs_idx, u8 su_idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (RTL8822B_SUPPORT)
if (dm->support_ic_type & ODM_RTL8822B) {
#if 0
u8 phi[13] = {0x0, 0x5, 0xa, 0xf, 0x15, 0x1a, 0x1f, 0x25,
0x2a, 0x2f, 0x35, 0x3a, 0x0};
u8 psi[13] = {0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
0x7, 0x7, 0x7, 0x7};
u16 psiphi[13] = {0x1c0, 0x1c5, 0x1ca, 0x1cf, 0x1d5, 0x1da,
0x1df, 0x1e5, 0x1ea, 0x1ef, 0x1f5, 0x1fa,
0x1c0}; //{Psi_4bit, Phi_6bit} of 0~360
#endif
u16 ns[3] = {52, 108, 234}; //20/40/80 MHz subcarrier number
u16 psiphi[13] = {0x1c0, 0x1c5, 0x1ca, 0x1cf, 0x1d5, 0x1da,
0x1df, 0x1e5, 0x1ea, 0x1ef, 0x1f5, 0x1fa,
0x1c0}; //{Psi_4bit, Phi_6bit} of 0~360
u16 psiphiR;
u8 i;
u8 snr = 0x12; // for 1SS BF
u8 nc = 0x0; //bit 2-0
u8 nr = 0x1; //bit 5-3
u8 ng = 0x0; //bit 7-6
u8 cb = 0x1; //bit 9-8; 1 => phi:6, psi:4;
u32 bw = odm_get_bb_reg(dm, R_0x8ac, 0x3); //bit 11-10
u8 userid = su_idx; //bit 12
u32 csi_report = 0x0;
u32 ndp_bw = odm_get_bb_reg(dm, R_0x8ac, 0x3); //bit 11-10
u8 ndp_sc = 0; //bit 11-10
u32 ndp_info = 0x0;
u16 mem_num = 0;
u8 mem_move = 0;
u8 mem_sel = 0;
u16 mem_addr = 0;
u32 dw0, dw1;
u64 vm_info = 0;
u64 temp = 0;
u8 vm_cnt = 0;
mem_num = ((8 + (6 + 4) * ns[bw]) >> 6) + 1; // SU codebook 1
/* setting NDP BW/SC info*/
ndp_info = (ndp_bw & 0x3) | (ndp_bw & 0x3) << 6 |
(ndp_bw & 0x3) << 12 | (ndp_sc & 0xf) << 2 |
(ndp_sc & 0xf) << 8 | (ndp_sc & 0xf) << 14;
odm_set_bb_reg(dm, R_0xb58, 0x000FFFFC, ndp_info);
odm_set_bb_reg(dm, R_0x19f8, 0x00010000, 1);
ODM_delay_ms(1); // delay 1ms
odm_set_bb_reg(dm, R_0x19f8, 0x00010000, 0);
/* setting CSI report info*/
csi_report = (userid & 0x1) << 12 | (bw & 0x3) << 10 |
(cb & 0x3) << 8 | (ng & 0x3) << 6 |
(nr & 0x7) << 3 | (nc & 0x7);
odm_set_bb_reg(dm, R_0x72c, 0x1FFF, csi_report);
odm_set_bb_reg(dm, R_0x71c, 0x80000000, 1);
PHYDM_DBG(dm, DBG_TXBF, "[%s] direct BF csi report 0x%x\n",
__func__, csi_report);
/*========================*/
odm_set_bb_reg(dm, R_0x19b8, 0x40, 1); //0x19b8[6]:1 to csi_rpt
odm_set_bb_reg(dm, R_0x19e0, 0x3FC0, 0xFF); //gated_clk off
odm_set_bb_reg(dm, R_0x9e8, 0x2000000, 1); //abnormal txbf
odm_set_bb_reg(dm, R_0x9e8, 0x1000000, 0); //read phi psi
odm_set_bb_reg(dm, R_0x9e8, 0x70000000, su_idx); //SU user 0
odm_set_bb_reg(dm, R_0x1910, 0x8000, 0); //BFer
dw0 = 0; // for 0x9ec
dw1 = 0; // for 0x1900
mem_addr = 0;
mem_sel = 0;
mem_move = 0;
vm_info = vm_info | (snr & 0xff); //V matrix info
vm_cnt = 8; // V matrix length counter
psiphiR = (psiphi[phs_idx] & 0x3ff);
while (mem_addr < mem_num) {
while (vm_cnt <= 32) {
// shift only max. 32 bit
if (vm_cnt >= 20) {
temp = psiphiR << 20;
temp = temp << (vm_cnt - 20);
} else {
temp = psiphiR << vm_cnt;
}
vm_info |= temp;
vm_cnt += 10;
}
if (mem_sel == 0) {
dw0 = vm_info & 0xffffffff;
vm_info = vm_info >> 32;
vm_cnt -= 32;
mem_sel = 1;
mem_move = 0;
} else {
dw1 = vm_info & 0xffffffff;
vm_info = vm_info >> 32;
vm_cnt -= 32;
mem_sel = 0;
mem_move = 1;
}
if (mem_move == 1) {
odm_set_bb_reg(dm, 0x9e8, 0x1000000, 0);
//read phi psi
odm_set_bb_reg(dm, 0x1910, 0x3FF0000,
mem_addr);
odm_set_bb_reg(dm, 0x09ec, 0xFFFFFFFF, dw0);
odm_set_bb_reg(dm, 0x1900, 0xFFFFFFFF, dw1);
odm_set_bb_reg(dm, 0x9e8, 0x1000000, 1);
//write phi psi
mem_move = 0;
mem_addr += 1;
}
}
odm_set_bb_reg(dm, 0x9e8, 0x2000000, 0); //normal txbf
}
#endif
} //end function
/*Before use this API, Disable STBC in advance*/
/*only 1SS rate can improve performance*/
void phydm_set_direct_bfer_txdesc_en(void *dm_void, u8 enable)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (RTL8197G_SUPPORT)
if (dm->support_ic_type & ODM_RTL8197G) {
phydm_iq_gen_en(dm);
/*#ifdef PHYDM_COMMON_API_SUPPORT*/
/*path selection is controlled by driver, use 1ss 2Tx*/
#if 0
if (!phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB, BB_PATH_AB))
return;
#endif
phydm_dis_cdd(dm);
if (enable)
odm_set_bb_reg(dm, R_0x1d90, 0x8000, 1);
else
odm_set_bb_reg(dm, R_0x1d90, 0x8000, 0);
}
#endif
} //end function
#endif
#endif

44
hal/phydm/phydm_direct_bf.h Normal file
View File

@@ -0,0 +1,44 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_DIR_BF_H__
#define __PHYDM_DIR_BF_H__
#ifdef CONFIG_DIRECTIONAL_BF
#define ANGLE_NUM 12
/*@
* ============================================================
* function prototype
* ============================================================
*/
void phydm_iq_gen_en(void *dm_void);
void phydm_dis_cdd(void *dm_void);
void phydm_pathb_q_matrix_rotate_en(void *dm_void);
void phydm_pathb_q_matrix_rotate(void *dm_void, u16 idx);
void phydm_set_direct_bfer(void *dm_void, u16 phs_idx, u8 su_idx);
void phydm_set_direct_bfer_txdesc_en(void *dm_void, u8 enable);
#endif
#endif

436
hal/phydm/phydm_dynamictxpower.c
View File

@@ -30,50 +30,152 @@
#include "phydm_precomp.h"
#ifdef CONFIG_DYNAMIC_TX_TWR
#ifdef BB_RAM_SUPPORT
void
phydm_2ndtype_dtp_init(void *dm_void)
void phydm_rd_reg_pwr(void *dm_void, u32 *_used, char *output, u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 pwr_offset_minus3, pwr_offset_minus7;
/*@ 2's com, for offset 3dB and 7dB, which 1 step will be 0.25dB*/
pwr_offset_minus3 = BIT(7) | 0x74;
pwr_offset_minus7 = BIT(7) | 0x64;
odm_set_bb_reg(dm, 0x1e70, 0x00ff0000, pwr_offset_minus3);
odm_set_bb_reg(dm, 0x1e70, 0xff000000, pwr_offset_minus7);
u32 used = *_used;
u32 out_len = *_out_len;
boolean pwr_ofst0_en = false;
boolean pwr_ofst1_en = false;
s8 pwr_ofst0 = 0;
s8 pwr_ofst1 = 0;
pwr_ofst0_en = (boolean)odm_get_bb_reg(dm, R_0x1e70, BIT(23));
pwr_ofst1_en = (boolean)odm_get_bb_reg(dm, R_0x1e70, BIT(31));
pwr_ofst0 = (s8)odm_get_bb_reg(dm, R_0x1e70, 0x7f0000);
pwr_ofst1 = (s8)odm_get_bb_reg(dm, R_0x1e70, 0x7f000000);
PDM_SNPF(out_len, used, output + used, out_len - used,
"reg0: en:%d, pwr_ofst:0x%x, reg1: en:%d, pwr_ofst:0x%x\n",
pwr_ofst0_en, pwr_ofst0, pwr_ofst1_en, pwr_ofst1);
*_used = used;
*_out_len = out_len;
};
void
phdm_2ndtype_rd_ram_pwr(void *dm_void, u8 macid)
void phydm_wt_reg_pwr(void *dm_void, boolean is_ofst1, boolean pwr_ofst_en,
s8 pwr_ofst)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
u8 reg_0x1e70 = 0;
if (!is_ofst1) {
bb_ctrl->tx_pwr_ofst_reg0_en = pwr_ofst_en;
bb_ctrl->tx_pwr_ofst_reg0 = pwr_ofst;
reg_0x1e70 |= (pwr_ofst_en << 7) + (pwr_ofst & 0x7f);
odm_set_bb_reg(dm, R_0x1e70, 0x00ff0000, reg_0x1e70);
} else {
bb_ctrl->tx_pwr_ofst_reg1_en = pwr_ofst_en;
bb_ctrl->tx_pwr_ofst_reg1 = pwr_ofst;
reg_0x1e70 |= (pwr_ofst_en << 7) + (pwr_ofst & 0x7f);
odm_set_bb_reg(dm, R_0x1e70, 0xff000000, reg_0x1e70);
}
};
void
phdm_2ndtype_wt_ram_pwr(void *dm_void, u8 macid, boolean pwr_offset0_en,
boolean pwr_offset1_en, s8 pwr_offset0, s8 pwr_offset1)
void phydm_rd_ram_pwr(void *dm_void, u8 macid, u32 *_used, char *output,
u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
boolean pwr_ofst0_en = false;
boolean pwr_ofst1_en = false;
s8 pwr_ofst0 = 0;
s8 pwr_ofst1 = 0;
u32 reg_0x1e84 = 0;
reg_0x1e84 |= (macid & 0x3f) << 24; /* macid*/
reg_0x1e84 |= BIT(31); /* read_en*/
odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
pwr_ofst0_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(23));
pwr_ofst1_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(31));
pwr_ofst0 = (s8)odm_get_bb_reg(dm, R_0x2de8, 0x7f0000);
pwr_ofst1 = (s8)odm_get_bb_reg(dm, R_0x2de8, 0x7f000000);
odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/
PDM_SNPF(out_len, used, output + used, out_len - used,
"(macid:%d) ram0: en:%d, pwr_ofst:0x%x, ram1: en:%d, pwr_ofst:0x%x\n",
macid, pwr_ofst0_en, pwr_ofst0, pwr_ofst1_en, pwr_ofst1);
*_used = used;
*_out_len = out_len;
};
void phydm_wt_ram_pwr(void *dm_void, u8 macid, boolean is_ofst1,
boolean pwr_ofst_en, s8 pwr_ofst)
{
u32 reg_io_0x1e84 = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
u32 reg_0x1e84 = 0;
boolean pwr_ofst_ano_en = false;
s8 pwr_ofst_ano = 0;
if (macid > 63)
macid = 63;
dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[macid];
dm_ram_per_sta->tx_pwr_offset0_en = pwr_offset0_en;
dm_ram_per_sta->tx_pwr_offset1_en = pwr_offset1_en;
dm_ram_per_sta->tx_pwr_offset0 = pwr_offset0;
dm_ram_per_sta->tx_pwr_offset1 = pwr_offset1;
reg_io_0x1e84 = (dm_ram_per_sta->hw_igi_en<<7) + dm_ram_per_sta->hw_igi;
reg_io_0x1e84 |= (pwr_offset0_en<<15) + ((pwr_offset0&0x7f)<<8);
reg_io_0x1e84 |= (pwr_offset1_en<<23) + ((pwr_offset1&0x7f)<<16);
reg_io_0x1e84 |= (macid&0x3f)<<24;
reg_io_0x1e84 |= BIT(30);
odm_set_bb_reg(dm, 0x1e84, 0xffffffff, reg_io_0x1e84);
reg_0x1e84 = (dm_ram_per_sta->hw_igi_en << 7) + dm_ram_per_sta->hw_igi;
if (!is_ofst1) {
dm_ram_per_sta->tx_pwr_offset0_en = pwr_ofst_en;
dm_ram_per_sta->tx_pwr_offset0 = pwr_ofst;
pwr_ofst_ano_en = dm_ram_per_sta->tx_pwr_offset1_en;
pwr_ofst_ano = dm_ram_per_sta->tx_pwr_offset1;
reg_0x1e84 |= (pwr_ofst_en << 15) + ((pwr_ofst & 0x7f) << 8) +
(pwr_ofst_ano_en << 23) +
((pwr_ofst_ano & 0x7f) << 16);
} else {
dm_ram_per_sta->tx_pwr_offset1_en = pwr_ofst_en;
dm_ram_per_sta->tx_pwr_offset1 = pwr_ofst;
pwr_ofst_ano_en = dm_ram_per_sta->tx_pwr_offset0_en;
pwr_ofst_ano = dm_ram_per_sta->tx_pwr_offset1;
reg_0x1e84 |= (pwr_ofst_ano_en << 15) +
((pwr_ofst_ano & 0x7f) << 8) +
(pwr_ofst_en << 23) + ((pwr_ofst & 0x7f) << 16);
}
reg_0x1e84 |= (macid & 0x3f) << 24;/* macid*/
reg_0x1e84 |= BIT(30); /* write_en*/
odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000); /* read_en*/
odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/
};
u8 phydm_pwr_lv_mapping_2ndtype(u8 tx_pwr_lv)
void phydm_rst_ram_pwr(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
u32 reg_0x1e84 = 0;
u8 i = 0;
for (i = 0; i < 64; i++) {
dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[i];
dm_ram_per_sta->tx_pwr_offset0_en = false;
dm_ram_per_sta->tx_pwr_offset1_en = false;
dm_ram_per_sta->tx_pwr_offset0 = 0x0;
dm_ram_per_sta->tx_pwr_offset1 = 0x0;
reg_0x1e84 = (dm_ram_per_sta->hw_igi_en << 7) +
dm_ram_per_sta->hw_igi;
reg_0x1e84 |= (i & 0x3f) << 24;
reg_0x1e84 |= BIT(30);
odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
}
odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000);
odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0);
};
u8 phydm_pwr_lv_mapping_2nd(u8 tx_pwr_lv)
{
if (tx_pwr_lv == tx_high_pwr_level_level3)
/*PHYDM_2ND_OFFSET_MINUS_11DB;*/
return PHYDM_2ND_OFFSET_MINUS_7DB;
return PHYDM_2ND_OFFSET_MINUS_11DB;
else if (tx_pwr_lv == tx_high_pwr_level_level2)
return PHYDM_2ND_OFFSET_MINUS_7DB;
else if (tx_pwr_lv == tx_high_pwr_level_level1)
@@ -82,20 +184,61 @@ u8 phydm_pwr_lv_mapping_2ndtype(u8 tx_pwr_lv)
return PHYDM_2ND_OFFSET_ZERO;
}
void phydm_dtp_fill_cmninfo_2ndtype(void *dm_void, u8 macid, u8 dtp_lvl)
void phydm_pwr_lv_ctrl(void *dm_void, u8 macid, u8 tx_pwr_lv)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
s8 pwr_offset = 0;
if (tx_pwr_lv == tx_high_pwr_level_level3)
pwr_offset = PHYDM_BBRAM_OFFSET_MINUS_11DB;
else if (tx_pwr_lv == tx_high_pwr_level_level2)
pwr_offset = PHYDM_BBRAM_OFFSET_MINUS_7DB;
else if (tx_pwr_lv == tx_high_pwr_level_level1)
pwr_offset = PHYDM_BBRAM_OFFSET_MINUS_3DB;
else
pwr_offset = PHYDM_BBRAM_OFFSET_ZERO;
phydm_wt_ram_pwr(dm, macid, RAM_PWR_OFST0, true, pwr_offset);
/* still need to check with SD7*/
#if (RTL8822C_SUPPORT)
if (dm->support_ic_type & ODM_RTL8822C)
phydm_wt_ram_pwr(dm, 127, RAM_PWR_OFST0, true, pwr_offset);
#endif
}
void phydm_dtp_fill_cmninfo_2nd(void *dm_void, u8 macid, u8 dtp_lvl)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
struct dtp_info *dtp = NULL;
dtp = &dm->phydm_sta_info[macid]->dtp_stat;
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
if (!is_sta_active(sta))
return;
dtp->dyn_tx_power = phydm_pwr_lv_mapping_2ndtype(dtp_lvl);
dtp = &dm->phydm_sta_info[macid]->dtp_stat;
dtp->dyn_tx_power = phydm_pwr_lv_mapping_2nd(dtp_lvl);
phydm_pwr_lv_ctrl(dm, macid, dtp_lvl);
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"Fill cmninfo TxPwr: macid=(%d), PwrLv (%d)\n", macid,
dtp->dyn_tx_power);
/* dyn_tx_power is 2 bit at 8822C/14B/98F/12F*/
}
void phydm_dtp_init_2nd(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
return;
#if (RTL8822C_SUPPORT)
if (dm->support_ic_type & ODM_RTL8822C) {
phydm_rst_ram_pwr(dm);
/* rsp tx use type 0*/
odm_set_mac_reg(dm, R_0x6d8, BIT(19) | BIT(18), RAM_PWR_OFST0);
}
#endif
};
#endif
boolean
@@ -107,53 +250,48 @@ phydm_check_rates(void *dm_void, u8 rate_idx)
u32 check_rate_bitmap2 = 0x00080200; /* @check VHT3SS M9, VHT4SS M9*/
u32 bitmap_result;
#if (RTL8822B_SUPPORT == 1)
#if (RTL8822B_SUPPORT)
if (dm->support_ic_type & ODM_RTL8822B) {
check_rate_bitmap2 &= 0;
check_rate_bitmap1 &= 0xfffff000;
check_rate_bitmap0 &= 0x0fffffff;
}
#endif
#if (RTL8197F_SUPPORT == 1)
#if (RTL8197F_SUPPORT)
if (dm->support_ic_type & ODM_RTL8197F) {
check_rate_bitmap2 &= 0;
check_rate_bitmap1 &= 0;
check_rate_bitmap0 &= 0x0fffffff;
}
#endif
#if (RTL8192E_SUPPORT == 1)
#if (RTL8192E_SUPPORT)
if (dm->support_ic_type & ODM_RTL8192E) {
check_rate_bitmap2 &= 0;
check_rate_bitmap1 &= 0;
check_rate_bitmap0 &= 0x0fffffff;
}
#endif
/*@jj add 20170822*/
#if (RTL8192F_SUPPORT == 1)
#if (RTL8192F_SUPPORT)
if (dm->support_ic_type & ODM_RTL8192F) {
check_rate_bitmap2 &= 0;
check_rate_bitmap1 &= 0;
check_rate_bitmap0 &= 0x0fffffff;
}
#endif
#if (RTL8721D_SUPPORT == 1)
#if (RTL8721D_SUPPORT)
if (dm->support_ic_type & ODM_RTL8721D) {
check_rate_bitmap2 &= 0;
check_rate_bitmap1 &= 0;
check_rate_bitmap0 &= 0x000fffff;
}
#endif
#if (RTL8821C_SUPPORT == 1)
#if (RTL8821C_SUPPORT)
if (dm->support_ic_type & ODM_RTL8821C) {
check_rate_bitmap2 &= 0;
check_rate_bitmap1 &= 0x003ff000;
check_rate_bitmap0 &= 0x000fffff;
}
#endif
if (rate_idx >= 64)
bitmap_result = BIT(rate_idx - 64) & check_rate_bitmap2;
else if (rate_idx >= 32)
@@ -191,7 +329,7 @@ u8 phydm_dtp_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate)
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 ret = 0xff;
#if (RTL8192E_SUPPORT == 1)
#if (RTL8192E_SUPPORT)
ret = config_phydm_read_txagc_n(dm, path, hw_rate);
#endif
return ret;
@@ -222,7 +360,8 @@ u8 phydm_search_min_power_index(void *dm_void)
if (gain_index == 0xff) {
min_gain_index = 0x20;
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"Error Gain idx!! Rewite to: ((%d))\n", min_gain_index);
"Error Gain idx!! Rewite to: ((%d))\n",
min_gain_index);
break;
}
PHYDM_DBG(dm, DBG_DYN_TXPWR,
@@ -231,30 +370,44 @@ u8 phydm_search_min_power_index(void *dm_void)
if (gain_index < min_gain_index)
min_gain_index = gain_index;
}
return min_gain_index;
}
void phydm_dynamic_tx_power_init(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i;
u8 i = 0;
dm->last_dtp_lvl = tx_high_pwr_level_normal;
dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
for (i = 0; i < 3; i++) {
dm->enhance_pwr_th[i] = 0xff;
switch (dm->ic_ip_series) {
#ifdef BB_RAM_SUPPORT
case PHYDM_IC_JGR3:
dm->set_pwr_th[0] = TX_PWR_NEAR_FIELD_TH_JGR3_LVL1;
dm->set_pwr_th[1] = TX_PWR_NEAR_FIELD_TH_JGR3_LVL2;
dm->set_pwr_th[2] = TX_PWR_NEAR_FIELD_TH_JGR3_LVL3;
phydm_dtp_init_2nd(dm);
break;
#endif
default:
for (i = 0; i < 3; i++)
dm->enhance_pwr_th[i] = 0xff;
dm->set_pwr_th[0] = TX_POWER_NEAR_FIELD_THRESH_LVL1;
dm->set_pwr_th[1] = TX_POWER_NEAR_FIELD_THRESH_LVL2;
dm->set_pwr_th[2] = 0xff;
dm->min_power_index = phydm_search_min_power_index(dm);
PHYDM_DBG(dm, DBG_DYN_TXPWR, "DTP init: Min Gain idx: ((%d))\n",
dm->min_power_index);
break;
}
dm->set_pwr_th[0] = TX_POWER_NEAR_FIELD_THRESH_LVL1;
dm->set_pwr_th[1] = TX_POWER_NEAR_FIELD_THRESH_LVL2;
dm->set_pwr_th[2] = 0xff;
dm->min_power_index = phydm_search_min_power_index(dm);
PHYDM_DBG(dm, DBG_DYN_TXPWR, "DTP init: Min Gain idx: ((%d))\n",
dm->min_power_index);
}
void phydm_noisy_enhance_hp_th(void *dm_void, u8 noisy_state)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (noisy_state == 0) {
dm->enhance_pwr_th[0] = dm->set_pwr_th[0];
dm->enhance_pwr_th[1] = dm->set_pwr_th[1];
@@ -265,7 +418,7 @@ void phydm_noisy_enhance_hp_th(void *dm_void, u8 noisy_state)
dm->enhance_pwr_th[2] = dm->set_pwr_th[2];
}
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"DTP hp_th: Lv1_th =%d ,Lv2_th = %d ,Lv3_th = %d\n",
"DTP hp_enhance_th: Lv1_th =%d ,Lv2_th = %d ,Lv3_th = %d\n",
dm->enhance_pwr_th[0], dm->enhance_pwr_th[1],
dm->enhance_pwr_th[2]);
}
@@ -273,10 +426,21 @@ void phydm_noisy_enhance_hp_th(void *dm_void, u8 noisy_state)
u8 phydm_pwr_lvl_check(void *dm_void, u8 input_rssi)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 th0,th1,th2;
th2 = dm->enhance_pwr_th[2];
th1 = dm->enhance_pwr_th[1];
th0 = dm->enhance_pwr_th[0];
u8 th0, th1, th2;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
th2 = dm->set_pwr_th[2];
th1 = dm->set_pwr_th[1];
th0 = dm->set_pwr_th[0];
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"DTP th: Lv1_th = %d, Lv2_th = %d, Lv3_th = %d\n",
th0, th1, th2);
} else {
th2 = dm->enhance_pwr_th[2];
th1 = dm->enhance_pwr_th[1];
th0 = dm->enhance_pwr_th[0];
}
if (input_rssi >= th2)
return tx_high_pwr_level_level3;
else if (input_rssi < (th2 - 3) && input_rssi >= th1)
@@ -304,21 +468,23 @@ u8 phydm_pwr_lv_mapping(u8 tx_pwr_lv)
void phydm_dynamic_response_power(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 rpwr;
u8 rpwr = 0;
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
return;
if (dm->dynamic_tx_high_power_lvl == tx_high_pwr_level_unchange) {
dm->dynamic_tx_high_power_lvl = dm->last_dtp_lvl;
PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr not change\n");
return;
}
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"RespPwr update_DTP_lv: ((%d)) -> ((%d))\n", dm->last_dtp_lvl,
dm->dynamic_tx_high_power_lvl);
dm->last_dtp_lvl = dm->dynamic_tx_high_power_lvl;
rpwr = phydm_pwr_lv_mapping(dm->dynamic_tx_high_power_lvl);
odm_set_mac_reg(dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT(19) | BIT(18), rpwr);
odm_set_mac_reg(dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT(19) | BIT(18),
rpwr);
PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr Set TxPwr: Lv (%d)\n",
dm->dynamic_tx_high_power_lvl);
}
@@ -326,10 +492,13 @@ void phydm_dynamic_response_power(void *dm_void)
void phydm_dtp_fill_cmninfo(void *dm_void, u8 macid, u8 dtp_lvl)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
struct dtp_info *dtp = NULL;
dtp = &dm->phydm_sta_info[macid]->dtp_stat;
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
if (!is_sta_active(sta))
return;
dtp = &sta->dtp_stat;
dtp->dyn_tx_power = phydm_pwr_lv_mapping(dtp_lvl);
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"Fill cmninfo TxPwr: macid=(%d), PwrLv (%d)\n", macid,
@@ -342,13 +511,16 @@ void phydm_dtp_per_sta(void *dm_void, u8 macid)
struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
struct dtp_info *dtp = NULL;
struct rssi_info *rssi = NULL;
if (is_sta_active(sta)) {
dtp = &sta->dtp_stat;
rssi = &sta->rssi_stat;
dtp->sta_tx_high_power_lvl = phydm_pwr_lvl_check(dm, rssi->rssi);
dtp->sta_tx_high_power_lvl = phydm_pwr_lvl_check(dm,
rssi->rssi);
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"STA=%d , RSSI: %d , GetPwrLv: %d\n", macid,
rssi->rssi, dtp->sta_tx_high_power_lvl);
if (dtp->sta_tx_high_power_lvl == tx_high_pwr_level_unchange
|| dtp->sta_tx_high_power_lvl == dtp->sta_last_dtp_lvl) {
dtp->sta_tx_high_power_lvl = dtp->sta_last_dtp_lvl;
@@ -359,30 +531,46 @@ void phydm_dtp_per_sta(void *dm_void, u8 macid)
}
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"DTP_lv update: ((%d)) -> ((%d))\n", dm->last_dtp_lvl,
dm->dynamic_tx_high_power_lvl);
"DTP_lv update: ((%d)) -> ((%d))\n",
dtp->sta_last_dtp_lvl, dtp->sta_tx_high_power_lvl);
dtp->sta_last_dtp_lvl = dtp->sta_tx_high_power_lvl;
#ifdef BB_RAM_SUPPORT
phydm_dtp_fill_cmninfo_2ndtype(dm, macid, dtp->sta_tx_high_power_lvl);
#else
phydm_dtp_fill_cmninfo(dm, macid, dtp->sta_tx_high_power_lvl);
#endif
switch (dm->ic_ip_series) {
#ifdef BB_RAM_SUPPORT
case PHYDM_IC_JGR3:
phydm_dtp_fill_cmninfo_2nd(dm, macid,
dtp->sta_tx_high_power_lvl);
break;
#endif
default:
phydm_dtp_fill_cmninfo(dm, macid,
dtp->sta_tx_high_power_lvl);
break;
}
}
}
void odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 macid)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
struct dtp_info *dtp = NULL;
dtp = &dm->phydm_sta_info[macid]->dtp_stat;
if (!is_sta_active(sta))
return;
dtp = &sta->dtp_stat;
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
return;
if (dm->fill_desc_dyntxpwr)
dm->fill_desc_dyntxpwr(dm, desc, dtp->dyn_tx_power);
else
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"%s: fill_desc_dyntxpwr is null!\n", __func__);
if (dtp->last_tx_power != dtp->dyn_tx_power) {
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"%s: last_offset=%d, txpwr_offset=%d\n", __func__,
@@ -399,42 +587,90 @@ void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output,
struct dm_struct *dm = (struct dm_struct *)dm_void;
char help[] = "-h";
u32 var1[3] = {0};
u32 var1[7] = {0};
u8 set_pwr_th1, set_pwr_th2, set_pwr_th3;
u8 i;
u8 i = 0;
#ifdef BB_RAM_SUPPORT
s8 pwr_ofst_tmp = 0x0;
#endif
if ((strcmp(input[1], help) == 0)) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"Set DTP threhosld: {1} {TH[0]} {TH[1]} {TH[2]}\n");
"Set DTP threhosld: {1} {Lv1_th} {Lv2_th} {Lv3_th}\n");
#ifdef BB_RAM_SUPPORT
PDM_SNPF(out_len, used, output + used, out_len - used,
"Set pwr_tx_offset: {2} {0:reg 1:macid} {en} {offset 0/1} {0:-, 1:+} {Pwr Offset} {macid}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"Read pwr_tx_offset : {3} {0:reg 1:macid} {macid(0~63), 255:all}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"Reset all ram pwr_tx_offset : {4}\n");
#endif
} else {
for (i = 0; i < 3; i++) {
for (i = 0; i < 7; i++) {
if (input[i + 1])
PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
&var1[i]);
}
if (var1[0] == 1) {
for (i = 0; i < 3; i++)
switch (var1[0]) {
case 1:
for (i = 0; i < 3; i++) {
if (var1[i] == 0 || var1[i] > 100)
dm->set_pwr_th[i] = 0xff;
else
dm->set_pwr_th[i] = (u8)var1[1 + i];
}
PDM_SNPF(out_len, used, output + used, out_len - used,
"DTP_TH[0:2] = {%d, %d, %d}\n",
dm->set_pwr_th[0], dm->set_pwr_th[1],
dm->set_pwr_th[2]);
break;
#ifdef BB_RAM_SUPPORT
case 2:
if ((boolean)var1[4])
pwr_ofst_tmp = (s8)var1[5];
else
pwr_ofst_tmp = 0x0 - (s8)var1[5];
if ((boolean)var1[1])
phydm_wt_ram_pwr(dm, (u8)var1[6],
(boolean)var1[3],
(boolean)var1[2],
pwr_ofst_tmp);
else
phydm_wt_reg_pwr(dm, (boolean)var1[3],
(boolean)var1[2],
pwr_ofst_tmp);
break;
case 3:
if ((boolean)var1[1]) {
if ((u8)var1[2] == 0xff)
for (i = 0; i < 64; i++)
phydm_rd_ram_pwr(dm, i, &used,
output,
&out_len);
else
phydm_rd_ram_pwr(dm, (u8)var1[2], &used,
output, &out_len);
} else {
phydm_rd_reg_pwr(dm, &used, output, &out_len);
}
break;
case 4:
phydm_rst_ram_pwr(dm);
break;
#endif
}
}
*_used = used;
*_out_len = out_len;
}
void phydm_dynamic_tx_power(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct cmn_sta_info *sta = NULL;
u8 i;
u8 i = 0;
u8 cnt = 0;
u8 rssi_min = dm->rssi_min;
u8 rssi_tmp = 0;
@@ -442,15 +678,16 @@ void phydm_dynamic_tx_power(void *dm_void)
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
return;
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"[%s] RSSI_min = %d, Noisy_dec = %d\n", __func__, rssi_min,
dm->noisy_decision);
phydm_noisy_enhance_hp_th(dm, dm->noisy_decision);
#ifndef BB_RAM_SUPPORT
/* Response Power */
dm->dynamic_tx_high_power_lvl = phydm_pwr_lvl_check(dm, rssi_min);
phydm_dynamic_response_power(dm);
#endif /* #ifndef BB_RAM_SUPPORT */
if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) {
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"[%s] RSSI_min = %d, Noisy_dec = %d\n", __func__,
rssi_min, dm->noisy_decision);
phydm_noisy_enhance_hp_th(dm, dm->noisy_decision);
/* Response Power */
dm->dynamic_tx_high_power_lvl = phydm_pwr_lvl_check(dm,
rssi_min);
phydm_dynamic_response_power(dm);
}
/* Per STA Tx power */
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
phydm_dtp_per_sta(dm, i);
@@ -469,7 +706,6 @@ void phydm_dynamic_tx_power_init_win(void *dm_void)
HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
mgnt_info->bDynamicTxPowerEnable = false;
#if DEV_BUS_TYPE == RT_USB_INTERFACE
if (RT_GetInterfaceSelection((PADAPTER)adapter) ==
INTF_SEL1_USB_High_Power) {
@@ -491,12 +727,12 @@ void phydm_dynamic_tx_power_win(void *dm_void)
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
return;
#if (RTL8814A_SUPPORT == 1)
#if (RTL8814A_SUPPORT)
if (dm->support_ic_type == ODM_RTL8814A)
odm_dynamic_tx_power_8814a(dm);
#endif
#if (RTL8821A_SUPPORT == 1)
#if (RTL8821A_SUPPORT)
if (dm->support_ic_type & ODM_RTL8821) {
void *adapter = dm->adapter;
PMGNT_INFO mgnt_info = GetDefaultMgntInfo((PADAPTER)adapter);
@@ -504,10 +740,10 @@ void phydm_dynamic_tx_power_win(void *dm_void)
if (mgnt_info->RegRspPwr == 1) {
if (dm->rssi_min > 60) {
/*Resp TXAGC offset = -3dB*/
odm_set_mac_reg(dm, 0x6d8, 0x1C0000, 1);
odm_set_mac_reg(dm, R_0x6d8, 0x1C0000, 1);
} else if (dm->rssi_min < 55) {
/*Resp TXAGC offset = 0dB*/
odm_set_mac_reg(dm, 0x6d8, 0x1C0000, 0);
odm_set_mac_reg(dm, R_0x6d8, 0x1C0000, 0);
}
}
}

41
hal/phydm/phydm_dynamictxpower.h
View File

@@ -32,9 +32,8 @@
* ============================================================
*/
/*@#define DYNAMIC_TXPWR_VERSION "1.0"*/
/*@#define DYNAMIC_TXPWR_VERSION "1.3" */ /*@2015.08.26, Add 8814 Dynamic TX power*/
#define DYNAMIC_TXPWR_VERSION "1.4" /*@2015.11.06, Add CE 8821A Dynamic TX power*/
/* 2019.2.12, refine code structure and set macid 127 only for 22C*/
#define DYNAMIC_TXPWR_VERSION "1.8"
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
@@ -48,6 +47,20 @@
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 255
#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 74
#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 60
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 90
#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 85
#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 80
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 90
#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 85
#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 80
#endif
#define tx_high_pwr_level_normal 0
#define tx_high_pwr_level_level1 1
#define tx_high_pwr_level_level2 2
@@ -67,13 +80,27 @@ enum phydm_dtp_power_offset {
PHYDM_OFFSET_ADD_6DB = 5
};
enum phydm_dtp_power_offset_2ndtype {
enum phydm_dtp_power_offset_2nd {
PHYDM_2ND_OFFSET_ZERO = 0,
PHYDM_2ND_OFFSET_MINUS_3DB = 2,
PHYDM_2ND_OFFSET_MINUS_7DB = 3,
PHYDM_2ND_OFFSET_MINUS_11DB = 1
PHYDM_2ND_OFFSET_MINUS_3DB = 1,
PHYDM_2ND_OFFSET_MINUS_7DB = 2,
PHYDM_2ND_OFFSET_MINUS_11DB = 3
};
enum phydm_dtp_power_offset_bbram {
/*@ HW min use 1dB*/
PHYDM_BBRAM_OFFSET_ZERO = 0,
PHYDM_BBRAM_OFFSET_MINUS_3DB = -3,
PHYDM_BBRAM_OFFSET_MINUS_7DB = -7,
PHYDM_BBRAM_OFFSET_MINUS_11DB = -11
};
enum phydm_dtp_power_pkt_type {
RAM_PWR_OFST0 = 0,
RAM_PWR_OFST1 = 1,
REG_PWR_OFST0 = 2,
REG_PWR_OFST1 = 3
};
/* @============================================================
* structure

6
hal/phydm/phydm_features.h
View File

@@ -31,7 +31,9 @@
ODM_RTL8710B | \
ODM_RTL8192F | \
ODM_RTL8821C | \
ODM_RTL8721D)
ODM_RTL8822B | \
ODM_RTL8721D | \
ODM_RTL8710C)
#define ODM_RECEIVER_BLOCKING_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
/*@20170103 YuChen add for FW API*/
@@ -49,6 +51,8 @@
#define PHYDM_FW_API_FUNC_ENABLE_8814B 1
#define PHYDM_FW_API_ENABLE_8812F 1
#define PHYDM_FW_API_FUNC_ENABLE_8812F 1
#define PHYDM_FW_API_ENABLE_8197G 1
#define PHYDM_FW_API_FUNC_ENABLE_8197G 1
#define CONFIG_POWERSAVING 0

26
hal/phydm/phydm_features_ap.h
View File

@@ -18,7 +18,8 @@
#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT)
RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT ||\
RTL8197G_SUPPORT)
#define PHYDM_LA_MODE_SUPPORT 1
#else
#define PHYDM_LA_MODE_SUPPORT 0
@@ -35,15 +36,16 @@
#define NHM_SUPPORT
#define CLM_SUPPORT
#if (RTL8822B_SUPPORT)
/*#define PHYDM_PHYSTAUS_SMP_MODE*/
#if (RTL8812F_SUPPORT)
/*#define PHYDM_PHYSTAUS_AUTO_SWITCH*/
#endif
#if (RTL8197F_SUPPORT)
/*#define PHYDM_TDMA_DIG_SUPPORT*/
#endif
#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)
#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\
RTL8197G_SUPPORT)
#define PHYDM_TDMA_DIG_SUPPORT 1
#ifdef PHYDM_TDMA_DIG_SUPPORT
#define IS_USE_NEW_TDMA /*new tdma dig test*/
@@ -73,12 +75,14 @@
/*#define PHYDM_POWER_TRAINING_SUPPORT*/
#endif
#if (RTL8814B_SUPPORT)
/* #define PHYDM_PMAC_TX_SETTING_SUPPORT */
#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
RTL8812F_SUPPORT || RTL8197G_SUPPORT)
#define PHYDM_PMAC_TX_SETTING_SUPPORT
#endif
#if (RTL8814B_SUPPORT)
/* #define PHYDM_MP_SUPPORT */
#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
RTL8812F_SUPPORT || RTL8197G_SUPPORT)
#define PHYDM_MP_SUPPORT
#endif
#if (RTL8822B_SUPPORT)
@@ -111,6 +115,10 @@
/* #define CONFIG_8822B_SPUR_CALIBRATION */
#endif
#if (RTL8197G_SUPPORT)
#define CONFIG_DIRECTIONAL_BF
#endif
#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
#define CONFIG_DYNAMIC_TX_TWR
#endif
@@ -138,7 +146,7 @@
#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) || defined(CONFIG_RTL_8197F_ANT_SWITCH)
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
#define ODM_EVM_ENHANCE_ANTDIV
#define SKIP_EVM_ANTDIV_TRAINING_PATCH
/*#define SKIP_EVM_ANTDIV_TRAINING_PATCH*/
/*----------*/
#ifdef CONFIG_NO_2G_DIVERSITY_8197F

35
hal/phydm/phydm_features_ce.h
View File

@@ -45,13 +45,18 @@
#define NHM_SUPPORT
#define CLM_SUPPORT
#if (RTL8822B_SUPPORT)
/*@#define PHYDM_PHYSTAUS_SMP_MODE*/
#if (RTL8822C_SUPPORT)
#define NHM_DYM_PW_TH_SUPPORT
#endif
#if (RTL8822C_SUPPORT)
/*@#define PHYDM_PHYSTAUS_AUTO_SWITCH*/
#endif
/*@#define PHYDM_TDMA_DIG_SUPPORT*/
#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8821C_SUPPORT)
#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822C_SUPPORT || RTL8723D_SUPPORT)
#ifdef CONFIG_TDMADIG
#define PHYDM_TDMA_DIG_SUPPORT
#ifdef PHYDM_TDMA_DIG_SUPPORT
@@ -89,14 +94,18 @@
#define PHYDM_POWER_TRAINING_SUPPORT
#endif
#if (RTL8822C_SUPPORT)
#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT)
#define PHYDM_PMAC_TX_SETTING_SUPPORT
#endif
#if (RTL8822C_SUPPORT)
#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT)
#define PHYDM_MP_SUPPORT
#endif
#if (RTL8822C_SUPPORT)
#define PHYDM_CCK_RX_PATHDIV_SUPPORT
#endif
#if (RTL8822B_SUPPORT)
#define PHYDM_TXA_CALIBRATION
#endif
@@ -118,11 +127,11 @@
#define CONFIG_RECEIVER_BLOCKING
#endif
#if (RTL8192F_SUPPORT == 1)
#if (RTL8192F_SUPPORT)
/*#define CONFIG_8912F_SPUR_CALIBRATION*/
#endif
#if (RTL8822B_SUPPORT == 1)
#if (RTL8822B_SUPPORT)
#define CONFIG_8822B_SPUR_CALIBRATION
#endif
@@ -155,6 +164,10 @@
#endif
#endif
#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT || RTL8192F_SUPPORT)
#define CONFIG_PATH_DIVERSITY
#endif
/*@[SmartAntenna]*/
/*@#define CONFIG_SMART_ANTENNA*/
#ifdef CONFIG_SMART_ANTENNA
@@ -173,7 +186,6 @@
#define CONFIG_PSD_TOOL
/*@#define CONFIG_ANT_DETECTION*/
/*@#define CONFIG_PATH_DIVERSITY*/
/*@#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
#define CONFIG_BB_TXBF_API
#define CONFIG_PHYDM_DEBUG_FUNCTION
@@ -182,7 +194,7 @@
#define ODM_CONFIG_BT_COEXIST
#endif
#define PHYDM_SUPPORT_RSSI_MONITOR
/*@#define PHYDM_AUTO_DEGBUG*/
#define PHYDM_AUTO_DEGBUG
#define CFG_DIG_DAMPING_CHK
@@ -198,7 +210,7 @@
#endif
#endif
#if (RTL8822B_SUPPORT)
#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT)
#ifdef CONFIG_MCC_MODE
#define CONFIG_MCC_DM
#endif
@@ -210,5 +222,8 @@
#endif
#endif
#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT)
#define CONFIG_DIRECTIONAL_BF
#endif
#endif

11
hal/phydm/phydm_features_iot.h
View File

@@ -45,10 +45,6 @@
#define NHM_SUPPORT
#define CLM_SUPPORT
#if (RTL8822B_SUPPORT)
/*#define PHYDM_PHYSTAUS_SMP_MODE*/
#endif
/*#define PHYDM_TDMA_DIG_SUPPORT*/
#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT)
@@ -64,7 +60,7 @@
#endif
#endif
#if (RTL8822B_SUPPORT)
#if (RTL8822B_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
#define PHYDM_POWER_TRAINING_SUPPORT
#endif
@@ -85,7 +81,7 @@
#endif
#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8721D_SUPPORT)
RTL8822B_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
#define PHYDM_DC_CANCELLATION
#endif
@@ -153,7 +149,7 @@
/*#define CONFIG_ANT_DETECTION*/
/*#define CONFIG_PATH_DIVERSITY*/
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
#define CONFIG_BB_TXBF_API
//#define CONFIG_BB_TXBF_API
#define CONFIG_PHYDM_DEBUG_FUNCTION
#ifdef CONFIG_BT_COEXIST
@@ -168,6 +164,7 @@
RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8822C_SUPPORT || RTL8814B_SUPPORT)
#define DRIVER_BEAMFORMING_VERSION2
#define CONFIG_BB_TXBF_API
#endif
#endif

27
hal/phydm/phydm_features_win.h
View File

@@ -35,8 +35,12 @@
#define NHM_SUPPORT
#define CLM_SUPPORT
#if (RTL8822B_SUPPORT)
/*#define PHYDM_PHYSTAUS_SMP_MODE*/
#if (RTL8822C_SUPPORT)
#define NHM_DYM_PW_TH_SUPPORT
#endif
#if (RTL8822C_SUPPORT)
/*#define PHYDM_PHYSTAUS_AUTO_SWITCH*/
#endif
/*#define PHYDM_TDMA_DIG_SUPPORT*/
@@ -79,6 +83,10 @@
#define PHYDM_MP_SUPPORT
#endif
#if (RTL8822C_SUPPORT)
#define PHYDM_CCK_RX_PATHDIV_SUPPORT
#endif
#if (RTL8822B_SUPPORT)
#define PHYDM_TXA_CALIBRATION
#endif
@@ -96,7 +104,7 @@
#define CONFIG_ADAPTIVE_SOML
#endif
#if (RTL8192F_SUPPORT == 1)
#if (RTL8192F_SUPPORT)
#define CONFIG_8912F_SPUR_CALIBRATION
#endif
@@ -105,7 +113,7 @@
#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT || RTL8188F_SUPPORT ||\
RTL8821C_SUPPORT)
RTL8821C_SUPPORT || RTL8723D_SUPPORT)
#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
#endif
@@ -133,7 +141,7 @@
#endif
#if (RTL8822C_SUPPORT)
#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT || RTL8192F_SUPPORT)
#define CONFIG_PATH_DIVERSITY
#endif
@@ -159,7 +167,6 @@
#define CONFIG_PSD_TOOL
#define PHYDM_SUPPORT_ADAPTIVITY
#define PHYDM_SUPPORT_CCKPD
/*#define CONFIG_PATH_DIVERSITY*/
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
#define CONFIG_ANT_DETECTION
#define CONFIG_BB_TXBF_API
@@ -182,4 +189,12 @@
#endif
#endif
#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT)
/*#define CONFIG_DIRECTIONAL_BF*/
#endif
#if (RTL8822C_SUPPORT)
#define CONFIG_MU_RSOML
#endif
#endif

359
hal/phydm/phydm_hwconfig.c
View File

@@ -251,6 +251,8 @@ odm_config_rf_with_header_file(struct dm_struct *dm,
READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type17);
else if (dm->rfe_type == 18)
READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type18);
else if (dm->rfe_type == 19)
READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type19);
else
READ_AND_CONFIG_MP(8822b, _txpwr_lmt);
}
@@ -350,10 +352,25 @@ odm_config_rf_with_header_file(struct dm_struct *dm,
if (config_type == CONFIG_RF_RADIO) {
if (e_rf_path == RF_PATH_A)
READ_AND_CONFIG_MP(8721d, _radioa);
} else if (config_type == CONFIG_RF_TXPWR_LMT)
READ_AND_CONFIG_MP(8721d, _txpwr_lmt);
} else if (config_type == CONFIG_RF_TXPWR_LMT) {
if (dm->power_voltage == ODM_POWER_18V)
READ_AND_CONFIG_MP(8721d, _txpwr_lmt_type0);
else
READ_AND_CONFIG_MP(8721d, _txpwr_lmt_type1);
}
}
#endif
#if (RTL8710C_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8710C) {
if (config_type == CONFIG_RF_RADIO) {
if (e_rf_path == RF_PATH_A)
READ_AND_CONFIG_MP(8710c, _radioa);
} else if (config_type == CONFIG_RF_TXPWR_LMT)
READ_AND_CONFIG_MP(8710c, _txpwr_lmt);
}
#endif
#if (RTL8821C_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8821C) {
if (config_type == CONFIG_RF_RADIO) {
@@ -365,18 +382,14 @@ odm_config_rf_with_header_file(struct dm_struct *dm,
}
#endif
#if (RTL8195B_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8195B) {
if (config_type == CONFIG_RF_RADIO) {
if (e_rf_path == RF_PATH_A)
READ_AND_CONFIG(8195b, _radioa);
}
#if 0
else if (config_type == CONFIG_RF_TXPWR_LMT) {
READ_AND_CONFIG(8821c, _txpwr_lmt);
/*@*/
}
#endif
}
if (dm->support_ic_type == ODM_RTL8195B) {
if (config_type == CONFIG_RF_RADIO) {
if (e_rf_path == RF_PATH_A)
READ_AND_CONFIG(8195b, _radioa);
} else if (config_type == CONFIG_RF_TXPWR_LMT) {
READ_AND_CONFIG(8195b, _txpwr_lmt);
}
}
#endif
#if (RTL8198F_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8198F) {
@@ -414,6 +427,8 @@ odm_config_rf_with_header_file(struct dm_struct *dm,
READ_AND_CONFIG_MP(8822c, _radioa);
else if (e_rf_path == RF_PATH_B)
READ_AND_CONFIG_MP(8822c, _radiob);
} else if (config_type == CONFIG_RF_TXPWR_LMT) {
READ_AND_CONFIG_MP(8822c, _txpwr_lmt);
}
}
#endif
@@ -427,6 +442,16 @@ odm_config_rf_with_header_file(struct dm_struct *dm,
}
}
#endif
#if (RTL8197G_SUPPORT)
if (dm->support_ic_type == ODM_RTL8197G) {
if (config_type == CONFIG_RF_RADIO) {
if (e_rf_path == RF_PATH_A)
READ_AND_CONFIG_MP(8197g, _radioa);
else if (e_rf_path == RF_PATH_B)
READ_AND_CONFIG_MP(8197g, _radiob);
}
}
#endif
/*8814B need review, when phydm has related files*/
#if (RTL8814B_SUPPORT)
@@ -446,6 +471,8 @@ odm_config_rf_with_header_file(struct dm_struct *dm,
READ_AND_CONFIG_MP(8814b, _radiosyn0);
else if (e_rf_path == RF_SYN1)
READ_AND_CONFIG_MP(8814b, _radiosyn1);
} else if (config_type == CONFIG_RF_TXPWR_LMT) {
READ_AND_CONFIG_MP(8814b, _txpwr_lmt);
}
}
#endif
@@ -638,6 +665,8 @@ odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm)
READ_AND_CONFIG_MP(8822b, _txpowertrack_type17);
else if (dm->rfe_type == 18)
READ_AND_CONFIG_MP(8822b, _txpowertrack_type18);
else if (dm->rfe_type == 19)
READ_AND_CONFIG_MP(8822b, _txpowertrack_type19);
else
READ_AND_CONFIG_MP(8822b, _txpowertrack);
}
@@ -738,6 +767,20 @@ odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm)
READ_AND_CONFIG_MP(8721d, _txxtaltrack);
}
#endif
#if RTL8710C_SUPPORT
if (dm->support_ic_type == ODM_RTL8710C) {
#if 0
if (dm->package_type == 1)
READ_AND_CONFIG_MP(8710c, _txpowertrack_qfn48m_smic);
else if (dm->package_type == 5)
READ_AND_CONFIG_MP(8710c, _txpowertrack_qfn48m_umc);
#endif
READ_AND_CONFIG_MP(8710c, _txpowertrack);
READ_AND_CONFIG_MP(8710c, _txxtaltrack);
}
#endif
#if RTL8821C_SUPPORT
if (dm->support_ic_type == ODM_RTL8821C) {
if (dm->rfe_type == 0x5)
@@ -750,8 +793,16 @@ odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm)
#endif
#if RTL8198F_SUPPORT
if (dm->support_ic_type == ODM_RTL8198F)
READ_AND_CONFIG_MP(8198f, _txpowertrack);
if (dm->support_ic_type == ODM_RTL8198F) {
if (dm->rfe_type == 0)
READ_AND_CONFIG_MP(8198f, _txpowertrack_type0);
else if (dm->rfe_type == 1)
READ_AND_CONFIG_MP(8198f, _txpowertrack_type1);
else if (dm->rfe_type == 3)
READ_AND_CONFIG_MP(8198f, _txpowertrack_type3);
else
READ_AND_CONFIG_MP(8198f, _txpowertrack);
}
#endif
#if RTL8195B_SUPPORT
@@ -762,13 +813,51 @@ odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm)
#endif
#if (RTL8822C_SUPPORT)
if (dm->support_ic_type == ODM_RTL8822C)
READ_AND_CONFIG_MP(8822c, _txpowertrack);
if (dm->support_ic_type == ODM_RTL8822C) {
if (dm->en_tssi_mode)
READ_AND_CONFIG_MP(8822c, _txpowertracktssi);
else
READ_AND_CONFIG_MP(8822c, _txpowertrack);
}
#endif
#if (RTL8812F_SUPPORT)
if (dm->support_ic_type == ODM_RTL8812F)
READ_AND_CONFIG_MP(8812f, _txpowertrack);
if (dm->support_ic_type == ODM_RTL8812F) {
if (dm->rfe_type == 0)
READ_AND_CONFIG_MP(8812f, _txpowertrack_type0);
else if (dm->rfe_type == 1)
READ_AND_CONFIG_MP(8812f, _txpowertrack_type1);
else if (dm->rfe_type == 2)
READ_AND_CONFIG_MP(8812f, _txpowertrack_type2);
else if (dm->rfe_type == 3)
READ_AND_CONFIG_MP(8812f, _txpowertrack_type3);
else
READ_AND_CONFIG_MP(8812f, _txpowertrack);
}
#endif
#if (RTL8197G_SUPPORT)
if (dm->support_ic_type == ODM_RTL8197G)
READ_AND_CONFIG_MP(8197g, _txpowertrack);
#endif
#if RTL8814B_SUPPORT
if (dm->support_ic_type == ODM_RTL8814B) {
if (dm->rfe_type == 0)
READ_AND_CONFIG_MP(8814b, _txpowertrack_type0);
else if (dm->rfe_type == 1)
READ_AND_CONFIG_MP(8814b, _txpowertrack_type1);
else if (dm->rfe_type == 2)
READ_AND_CONFIG_MP(8814b, _txpowertrack_type2);
#if 0
else if (dm->rfe_type == 3)
READ_AND_CONFIG_MP(8814b, _txpowertrack_type3);
else if (dm->rfe_type == 6)
READ_AND_CONFIG_MP(8814b, _txpowertrack_type6);
#endif
else
READ_AND_CONFIG_MP(8814b, _txpowertrack);
}
#endif
return HAL_STATUS_SUCCESS;
@@ -979,6 +1068,8 @@ odm_config_bb_with_header_file(struct dm_struct *dm,
READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type17);
else if (dm->rfe_type == 18)
READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type18);
else if (dm->rfe_type == 19)
READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type19);
else
READ_AND_CONFIG_MP(8822b, _phy_reg_pg);
}
@@ -1078,10 +1169,26 @@ odm_config_bb_with_header_file(struct dm_struct *dm,
READ_AND_CONFIG_MP(8721d, _phy_reg);
else if (config_type == CONFIG_BB_AGC_TAB)
READ_AND_CONFIG_MP(8721d, _agc_tab);
else if (config_type == CONFIG_BB_PHY_REG_PG)
READ_AND_CONFIG_MP(8721d, _phy_reg_pg);
else if (config_type == CONFIG_BB_PHY_REG_PG) {
if (dm->power_voltage == ODM_POWER_18V)
READ_AND_CONFIG_MP(8721d, _phy_reg_pg_type0);
else
READ_AND_CONFIG_MP(8721d, _phy_reg_pg_type1);
}
}
#endif
#if (RTL8710C_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8710C) {
if (config_type == CONFIG_BB_PHY_REG)
READ_AND_CONFIG_MP(8710c, _phy_reg);
else if (config_type == CONFIG_BB_AGC_TAB)
READ_AND_CONFIG_MP(8710c, _agc_tab);
else if (config_type == CONFIG_BB_PHY_REG_PG)
READ_AND_CONFIG_MP(8710c, _phy_reg_pg);
}
#endif
#if (RTL8821C_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8821C) {
if (config_type == CONFIG_BB_PHY_REG) {
@@ -1143,6 +1250,12 @@ odm_config_bb_with_header_file(struct dm_struct *dm,
READ_AND_CONFIG_MP(8814b, _phy_reg);
else if (config_type == CONFIG_BB_AGC_TAB)
READ_AND_CONFIG_MP(8814b, _agc_tab);
else if (config_type == CONFIG_BB_PHY_REG_PG) {
if (dm->rfe_type == 1)
READ_AND_CONFIG(8814b, _phy_reg_pg_type1);
else
READ_AND_CONFIG(8814b, _phy_reg_pg);
}
}
#endif
#if (RTL8822C_SUPPORT)
@@ -1151,6 +1264,8 @@ odm_config_bb_with_header_file(struct dm_struct *dm,
READ_AND_CONFIG_MP(8822c, _phy_reg);
else if (config_type == CONFIG_BB_AGC_TAB)
READ_AND_CONFIG_MP(8822c, _agc_tab);
else if (config_type == CONFIG_BB_PHY_REG_PG)
READ_AND_CONFIG(8822c, _phy_reg_pg);
}
#endif
#if (RTL8812F_SUPPORT)
@@ -1159,6 +1274,18 @@ odm_config_bb_with_header_file(struct dm_struct *dm,
READ_AND_CONFIG_MP(8812f, _phy_reg);
else if (config_type == CONFIG_BB_AGC_TAB)
READ_AND_CONFIG_MP(8812f, _agc_tab);
else if (config_type == CONFIG_BB_PHY_REG_PG)
READ_AND_CONFIG(8812f, _phy_reg_pg);
}
#endif
#if (RTL8197G_SUPPORT)
if (dm->support_ic_type == ODM_RTL8197G) {
if (config_type == CONFIG_BB_PHY_REG)
READ_AND_CONFIG_MP(8197g, _phy_reg);
else if (config_type == CONFIG_BB_AGC_TAB)
READ_AND_CONFIG_MP(8197g, _agc_tab);
else if (config_type == CONFIG_BB_PHY_REG_PG)
READ_AND_CONFIG(8197g, _phy_reg_pg);
}
#endif
@@ -1190,6 +1317,14 @@ odm_config_mac_with_header_file(struct dm_struct *dm)
"support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n",
dm->support_platform, dm->support_interface, dm->board_type);
#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT)
if (dm->support_ic_type &
(ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8814B)) {
PHYDM_DBG(dm, ODM_COMP_INIT, "MAC para-package in HALMAC\n");
return result;
}
#endif
/* @1 AP doesn't use PHYDM initialization in these ICs */
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#if (RTL8812A_SUPPORT == 1)
@@ -1208,12 +1343,12 @@ odm_config_mac_with_header_file(struct dm_struct *dm)
if (dm->support_ic_type == ODM_RTL8723D)
READ_AND_CONFIG_MP(8723d, _mac_reg);
#endif
/* @JJ ADD 20161014 */
#if (RTL8710B_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8710B)
READ_AND_CONFIG_MP(8710b, _mac_reg);
#endif
#endif /* @(DM_ODM_SUPPORT_TYPE != ODM_AP) */
/* @1 All platforms support */
#if (RTL8188E_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8188E)
@@ -1243,17 +1378,20 @@ odm_config_mac_with_header_file(struct dm_struct *dm)
if (dm->support_ic_type == ODM_RTL8197F)
READ_AND_CONFIG_MP(8197f, _mac_reg);
#endif
/*@jj add 20170822*/
#if (RTL8192F_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8192F)
READ_AND_CONFIG_MP(8192f, _mac_reg);
#endif
#if (RTL8721D_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8721D)
READ_AND_CONFIG_MP(8721d, _mac_reg);
#endif
#if (RTL8710C_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8710C)
READ_AND_CONFIG_MP(8710c, _mac_reg);
#endif
#if (RTL8821C_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8821C)
READ_AND_CONFIG(8821c, _mac_reg);
@@ -1270,17 +1408,9 @@ odm_config_mac_with_header_file(struct dm_struct *dm)
if (dm->support_ic_type == ODM_RTL8198F)
READ_AND_CONFIG_MP(8198f, _mac_reg);
#endif
#if (RTL8814B_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8814B)
READ_AND_CONFIG_MP(8814b, _mac_reg);
#endif
#if (RTL8822C_SUPPORT)
if (dm->support_ic_type == ODM_RTL8822C)
READ_AND_CONFIG_MP(8822c, _mac_reg);
#endif
#if (RTL8812F_SUPPORT)
if (dm->support_ic_type == ODM_RTL8812F)
READ_AND_CONFIG_MP(8812f, _mac_reg);
#if (RTL8197G_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8197G)
READ_AND_CONFIG_MP(8197g, _mac_reg);
#endif
if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
@@ -1302,94 +1432,121 @@ u32 odm_get_hw_img_version(struct dm_struct *dm)
{
u32 version = 0;
switch (dm->support_ic_type) {
/* @1 AP doesn't use PHYDM initialization in these ICs */
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#if (RTL8821A_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8821)
version = GET_VERSION_MP(8821a, _mac_reg);
#if (RTL8821A_SUPPORT)
case ODM_RTL8821:
version = odm_get_version_mp_8821a_phy_reg();
break;
#endif
#if (RTL8192E_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8192E)
version = GET_VERSION_MP(8192e, _mac_reg);
#if (RTL8192E_SUPPORT)
case ODM_RTL8192E:
version = odm_get_version_mp_8192e_phy_reg();
break;
#endif
#if (RTL8812A_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8812)
version = GET_VERSION_MP(8812a, _mac_reg);
#endif
#if (RTL8723D_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8723D)
version = GET_VERSION_MP(8723d, _mac_reg);
#endif
/* @JJ ADD 20161014 */
#if (RTL8710B_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8710B)
version = GET_VERSION_MP(8710b, _mac_reg);
#if (RTL8812A_SUPPORT)
case ODM_RTL8812:
version = odm_get_version_mp_8812a_phy_reg();
break;
#endif
#endif /* @(DM_ODM_SUPPORT_TYPE != ODM_AP) */
/*@1 All platforms support*/
#if (RTL8188E_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8188E)
version = GET_VERSION_MP(8188e, _mac_reg);
#if (RTL8723D_SUPPORT)
case ODM_RTL8723D:
version = odm_get_version_mp_8723d_phy_reg();
break;
#endif
#if (RTL8723B_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8723B)
version = GET_VERSION_MP(8723b, _mac_reg);
#if (RTL8710B_SUPPORT)
case ODM_RTL8710B:
version = odm_get_version_mp_8710b_phy_reg();
break;
#endif
#if (RTL8814A_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8814A)
version = GET_VERSION_MP(8814a, _mac_reg);
#if (RTL8188E_SUPPORT)
case ODM_RTL8188E:
version = odm_get_version_mp_8188e_phy_reg();
break;
#endif
#if (RTL8703B_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8703B)
version = GET_VERSION_MP(8703b, _mac_reg);
#if (RTL8723B_SUPPORT)
case ODM_RTL8723B:
version = odm_get_version_mp_8723b_phy_reg();
break;
#endif
#if (RTL8188F_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8188F)
version = GET_VERSION_MP(8188f, _mac_reg);
#if (RTL8814A_SUPPORT)
case ODM_RTL8814A:
version = odm_get_version_mp_8814a_phy_reg();
break;
#endif
#if (RTL8822B_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8822B)
version = GET_VERSION_MP(8822b, _mac_reg);
#if (RTL8703B_SUPPORT)
case ODM_RTL8703B:
version = odm_get_version_mp_8703b_phy_reg();
break;
#endif
#if (RTL8197F_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8197F)
version = GET_VERSION_MP(8197f, _mac_reg);
#if (RTL8188F_SUPPORT)
case ODM_RTL8188F:
version = odm_get_version_mp_8188f_phy_reg();
break;
#endif
#if (RTL8822B_SUPPORT)
case ODM_RTL8822B:
version = odm_get_version_mp_8822b_phy_reg();
break;
#endif
#if (RTL8197F_SUPPORT)
case ODM_RTL8197F:
version = odm_get_version_mp_8197f_phy_reg();
break;
#endif
/*@jj add 20170822*/
#if (RTL8192F_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8192F)
version = GET_VERSION_MP(8192f, _mac_reg);
#if (RTL8192F_SUPPORT)
case ODM_RTL8192F:
version = odm_get_version_mp_8192f_phy_reg();
break;
#endif
#if (RTL8721D_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8721D)
version = GET_VERSION_MP(8721d, _mac_reg);
#if (RTL8721D_SUPPORT)
case ODM_RTL8721D:
version = odm_get_version_mp_8721d_phy_reg();
break;
#endif
#if (RTL8821C_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8821C)
version = GET_VERSION(8821c, _mac_reg);
#if (RTL8710C_SUPPORT)
case ODM_RTL8710C:
version = GET_VERSION_MP(8710c, _mac_reg);
#endif
#if (RTL8195B_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8195B)
version = GET_VERSION(8195b, _mac_reg);
#if (RTL8821C_SUPPORT)
case ODM_RTL8821C:
version = odm_get_version_mp_8821c_phy_reg();
break;
#endif
#if (RTL8198F_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8198F)
version = GET_VERSION_MP(8198f, _mac_reg);
#if (RTL8195B_SUPPORT)
case ODM_RTL8195B:
version = odm_get_version_mp_8195b_phy_reg();
break;
#endif
#if (RTL8198F_SUPPORT)
case ODM_RTL8198F:
version = odm_get_version_mp_8198f_phy_reg();
break;
#endif
#if (RTL8822C_SUPPORT)
if (dm->support_ic_type == ODM_RTL8822C)
version = GET_VERSION_MP(8822c, _mac_reg);
case ODM_RTL8822C:
version = odm_get_version_mp_8822c_phy_reg();
break;
#endif
#if (RTL8812F_SUPPORT)
if (dm->support_ic_type == ODM_RTL8812F)
version = GET_VERSION_MP(8812f, _mac_reg);
case ODM_RTL8812F:
version = odm_get_version_mp_8812f_phy_reg();
break;
#endif
#if (RTL8814B_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8814B)
version = GET_VERSION_MP(8814b, _mac_reg);
#if (RTL8197G_SUPPORT)
case ODM_RTL8197G:
version = odm_get_version_mp_8197g_phy_reg();
break;
#endif
#if (RTL8814B_SUPPORT)
case ODM_RTL8814B:
version = odm_get_version_mp_8814b_phy_reg();
break;
#endif
}
return version;
}

75
hal/phydm/phydm_interface.c
View File

@@ -136,6 +136,9 @@ void odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data)
rtw_write8(adapter, reg_addr, data);
#endif
if (dm->en_reg_mntr_byte)
pr_debug("1byte:addr=0x%x, data=0x%x\n", reg_addr, data);
}
void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data)
@@ -162,6 +165,9 @@ void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data)
rtw_write16(adapter, reg_addr, data);
#endif
if (dm->en_reg_mntr_byte)
pr_debug("2byte:addr=0x%x, data=0x%x\n", reg_addr, data);
}
void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data)
@@ -188,6 +194,9 @@ void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data)
rtw_write32(adapter, reg_addr, data);
#endif
if (dm->en_reg_mntr_byte)
pr_debug("4byte:addr=0x%x, data=0x%x\n", reg_addr, data);
}
void odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data)
@@ -210,6 +219,10 @@ void odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data)
#else
phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
#endif
if (dm->en_reg_mntr_mac)
pr_debug("MAC:addr=0x%x, mask=0x%x, data=0x%x\n",
reg_addr, bit_mask, data);
}
u32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask)
@@ -253,6 +266,10 @@ void odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data)
#else
phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
#endif
if (dm->en_reg_mntr_bb)
pr_debug("BB:addr=0x%x, mask=0x%x, data=0x%x\n",
reg_addr, bit_mask, data);
}
u32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask)
@@ -301,6 +318,10 @@ void odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
phy_set_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask, data);
ODM_delay_us(2);
#endif
if (dm->en_reg_mntr_rf)
pr_debug("RF:path=0x%x, addr=0x%x, mask=0x%x, data=0x%x\n",
e_rf_path, reg_addr, bit_mask, data);
}
u32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
@@ -1242,11 +1263,23 @@ odm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment)
return iqk_result;
}
void odm_cmn_info_ptr_array_hook(struct dm_struct *dm,
enum odm_cmninfo cmn_info, u16 index,
void *value)
enum hal_status
odm_dpk_by_fw(struct dm_struct *dm)
{
/*ODM_CMNINFO_STA_STATUS*/
enum hal_status dpk_result = HAL_STATUS_FAILURE;
#if 0
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
struct _ADAPTER *adapter = dm->adapter;
if (HAL_MAC_FWDPK_Trigger(&GET_HAL_MAC_INFO(adapter)) == 0)
dpk_result = HAL_STATUS_SUCCESS;
#else
dpk_result = rtw_phydm_fw_dpk(dm);
#endif
#endif
return dpk_result;
}
void phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 mac_id,
@@ -1416,13 +1449,13 @@ void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *),
#endif
}
u32 phydm_get_tx_rate(struct dm_struct *dm)
u8 phydm_get_tx_rate(struct dm_struct *dm)
{
struct _hal_rf_ *rf = &dm->rf_table;
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
struct _ADAPTER *adapter = dm->adapter;
#endif
u8 tx_rate = 0xFF;
u8 tx_rate = 0xff;
u8 mpt_rate_index = 0;
if (*dm->mp_mode == 1) {
@@ -1466,3 +1499,33 @@ u32 phydm_get_tx_rate(struct dm_struct *dm)
return tx_rate;
}
u8 phydm_get_tx_power_dbm(struct dm_struct *dm, u8 rf_path,
u8 rate, u8 bandwidth, u8 channel)
{
u8 tx_power_dbm = 0;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct _ADAPTER *adapter = dm->adapter;
tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValue(adapter, rf_path, rate, bandwidth, channel);
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
tx_power_dbm = phy_get_tx_power_final_absolute_value(dm->adapter, rf_path, rate, bandwidth, channel);
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValue(dm, rf_path, rate, bandwidth, channel);
#endif
return tx_power_dbm;
}
u64 phydm_division64(u64 x, u64 y)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
do_div(x, y);
return x;
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
return x / y;
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
return rtw_division64(x, y);
#endif
}

12
hal/phydm/phydm_interface.h
View File

@@ -309,9 +309,8 @@ void odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset,
enum hal_status
odm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment);
void odm_cmn_info_ptr_array_hook(struct dm_struct *dm,
enum odm_cmninfo cmn_info, u16 index,
void *value);
enum hal_status
odm_dpk_by_fw(struct dm_struct *dm);
void phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 index,
struct cmn_sta_info *pcmn_sta_info);
@@ -333,11 +332,14 @@ phydm_get_txbf_en(
#endif
void phydm_iqk_wait(struct dm_struct *dm, u32 timeout);
u8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate);
void phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap);
void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *),
void *context);
u32 phydm_get_tx_rate(struct dm_struct *dm);
u8 phydm_get_tx_rate(struct dm_struct *dm);
u8 phydm_get_tx_power_dbm(struct dm_struct *dm, u8 rf_path,
u8 rate, u8 bandwidth, u8 channel);
u64 phydm_division64(u64 x, u64 y);
#endif /* @__ODM_INTERFACE_H__ */

66
hal/phydm/phydm_lna_sat.c
View File

@@ -264,7 +264,7 @@ void phydm_lna_sat_chk(
#endif
phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0);
/*@open rf power detection ckt & set detection range */
#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
#if (RTL8198F_SUPPORT)
if (dm->support_ic_type & ODM_RTL8198F) {
/*@set rf detection range (threshold)*/
config_phydm_write_rf_reg_8198f(dm, RF_PATH_A, 0x85,
@@ -280,37 +280,34 @@ void phydm_lna_sat_chk(
config_phydm_write_rf_reg_8198f(dm, RF_PATH_B, 0x86, 0x10, 1);
config_phydm_write_rf_reg_8198f(dm, RF_PATH_C, 0x86, 0x10, 1);
config_phydm_write_rf_reg_8198f(dm, RF_PATH_D, 0x86, 0x10, 1);
} else if (dm->support_ic_type & ODM_RTL8814B) {
/*@set rf detection range (threshold)*/
#if 0
config_phydm_write_rf_reg_8814b(dm, RF_PATH_A, 0x87, 0x3, 0x3);
config_phydm_write_rf_reg_8814b(dm, RF_PATH_B, 0x87, 0x3, 0x3);
config_phydm_write_rf_reg_8814b(dm, RF_PATH_C, 0x87, 0x3, 0x3);
config_phydm_write_rf_reg_8814b(dm, RF_PATH_D, 0x87, 0x3, 0x3);
#endif
/*@open rf power detection ckt*/
#if 0
config_phydm_write_rf_reg_8814b(dm, RF_PATH_A, 0x87, 0x10, 1);
config_phydm_write_rf_reg_8814b(dm, RF_PATH_B, 0x87, 0x10, 1);
config_phydm_write_rf_reg_8814b(dm, RF_PATH_C, 0x87, 0x10, 1);
config_phydm_write_rf_reg_8814b(dm, RF_PATH_D, 0x87, 0x10, 1);
#endif
} else
#endif
{
odm_set_rf_reg(dm, RF_PATH_A, RF_0x86, 0x1f, 0x10);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x86, 0x1f, 0x10);
#ifdef PHYDM_IC_ABOVE_3SS
odm_set_rf_reg(dm, RF_PATH_C, RF_0x86, 0x1f, 0x10);
#endif
#ifdef PHYDM_IC_ABOVE_4SS
odm_set_rf_reg(dm, RF_PATH_D, RF_0x86, 0x1f, 0x10);
#endif
}
#elif (RTL8814B_SUPPORT)
if (dm->support_ic_type & ODM_RTL8814B) {
/*@set rf detection range (threshold)*/
config_phydm_write_rf_reg_8814b(dm, RF_PATH_A, 0x8B, 0x3, 0x3);
config_phydm_write_rf_reg_8814b(dm, RF_PATH_B, 0x8B, 0x3, 0x3);
config_phydm_write_rf_reg_8814b(dm, RF_PATH_C, 0x8B, 0x3, 0x3);
config_phydm_write_rf_reg_8814b(dm, RF_PATH_D, 0x8B, 0x3, 0x3);
/*@open rf power detection ckt*/
config_phydm_write_rf_reg_8814b(dm, RF_PATH_A, 0x8B, 0x4, 1);
config_phydm_write_rf_reg_8814b(dm, RF_PATH_B, 0x8B, 0x4, 1);
config_phydm_write_rf_reg_8814b(dm, RF_PATH_C, 0x8B, 0x4, 1);
config_phydm_write_rf_reg_8814b(dm, RF_PATH_D, 0x8B, 0x4, 1);
}
#else
odm_set_rf_reg(dm, RF_PATH_A, RF_0x86, 0x1f, 0x10);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x86, 0x1f, 0x10);
#ifdef PHYDM_IC_ABOVE_3SS
odm_set_rf_reg(dm, RF_PATH_C, RF_0x86, 0x1f, 0x10);
#endif
#ifdef PHYDM_IC_ABOVE_4SS
odm_set_rf_reg(dm, RF_PATH_D, RF_0x86, 0x1f, 0x10);
#endif
#endif
/*@check saturation status*/
for (i = 0; i < chk_cnt; i++) {
#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
#if (RTL8198F_SUPPORT)
if (dm->support_ic_type & ODM_RTL8198F) {
sat_status_a = config_phydm_read_rf_reg_8198f(dm, RF_PATH_A,
RF_0xae,
@@ -324,9 +321,10 @@ void phydm_lna_sat_chk(
sat_status_d = config_phydm_read_rf_reg_8198f(dm, RF_PATH_D,
RF_0xae,
0xe0000);
} else if (dm->support_ic_type & ODM_RTL8814B) {
}
#elif (RTL8814B_SUPPORT)
if (dm->support_ic_type & ODM_RTL8814B) {
/*@read peak detector info from 8814B rf reg*/
#if 0
sat_status_a = config_phydm_read_rf_reg_8814b(dm, RF_PATH_A,
RF_0xae,
0xc0000);
@@ -339,10 +337,8 @@ void phydm_lna_sat_chk(
sat_status_d = config_phydm_read_rf_reg_8814b(dm, RF_PATH_D,
RF_0xae,
0xc0000);
#endif
} else
#endif
{
}
#else
sat_status_a = odm_get_rf_reg(dm, RF_PATH_A, RF_0xae, 0xc0000);
sat_status_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0xae, 0xc0000);
#ifdef PHYDM_IC_ABOVE_3SS
@@ -351,7 +347,7 @@ void phydm_lna_sat_chk(
#ifdef PHYDM_IC_ABOVE_4SS
sat_status_d = odm_get_rf_reg(dm, RF_PATH_D, RF_0xae, 0xc0000);
#endif
}
#endif
if (sat_status_a != 0)
lna_info->sat_cnt_acc_patha++;

58
hal/phydm/phydm_math_lib.c
View File

@@ -142,10 +142,8 @@ u32 odm_convert_to_db(u64 value)
u8 j;
u32 dB;
if (value >= db_invert_table[11][7]) {
pr_debug("[%s] ====>\n", __func__);
if (value >= db_invert_table[11][7])
return 96; /* @maximum 96 dB */
}
for (i = 0; i < 12; i++) {
if (i <= 2 && (value << FRAC_BITS) <= db_invert_table[i][7])
@@ -193,14 +191,20 @@ end:
u64 phydm_db_2_linear(u32 value)
{
u8 i;
u8 j;
u64 linear;
/* @1dB~96dB */
u8 i = 0;
u8 j = 0;
u64 linear = 0;
value = value & 0xFF;
/* @1dB~96dB */
if (value > 96) {
value = 96;
} else if (value < 1) {
linear = 1;
return linear;
}
i = (u8)((value - 1) >> 3);
j = (u8)(value - 1) - (i << 3);
@@ -225,12 +229,27 @@ u16 phydm_show_fraction_num(u32 frac_val, u8 bit_num)
return val;
}
u32 phydm_gen_bitmask(u8 mask_num)
u16 phydm_ones_num_in_bitmap(u64 val, u8 size)
{
u8 i = 0;
u32 bitmask = 0;
u8 ones_num = 0;
if (mask_num > 32)
for (i = 0; i < size; i++) {
if (val & BIT(0))
ones_num++;
val = val >> 1;
}
return ones_num;
}
u64 phydm_gen_bitmask(u8 mask_num)
{
u8 i = 0;
u64 bitmask = 0;
if (mask_num > 64)
return 1;
for (i = 0; i < mask_num; i++)
@@ -241,9 +260,26 @@ u32 phydm_gen_bitmask(u8 mask_num)
s32 phydm_cnvrt_2_sign(u32 val, u8 bit_num)
{
if (bit_num >= 32)
return (s32)val;
if (val & BIT(bit_num - 1)) /*Sign BIT*/
val -= (1 << bit_num); /*@2's*/
return val;
}
s64 phydm_cnvrt_2_sign_64(u64 val, u8 bit_num)
{
u64 one = 1;
s64 val_sign = (s64)val;
if (bit_num >= 64)
return (s64)val;
if (val & (one << (bit_num - 1))) /*Sign BIT*/
val_sign = val - (one << bit_num); /*@2's*/
return val_sign;
}

10
hal/phydm/phydm_math_lib.h
View File

@@ -26,7 +26,8 @@
#ifndef __PHYDM_MATH_LIB_H__
#define __PHYDM_MATH_LIB_H__
#define AUTO_MATH_LIB_VERSION "1.0" /* @2017.06.06*/
/* @2019.01.24 remove linear2db debug log*/
#define AUTO_MATH_LIB_VERSION "1.2"
/*@
* 1 ============================================================
@@ -34,6 +35,7 @@
* 1 ============================================================
*/
#define PHYDM_DIV(a, b) ((b) ? ((a) / (b)) : 0)
#define DIVIDED_2(X) ((X) >> 1)
/*@1/3 ~ 11/32*/
#if defined(DM_ODM_CE_MAC80211)
@@ -108,7 +110,11 @@ u64 phydm_db_2_linear(u32 value);
u16 phydm_show_fraction_num(u32 frac_val, u8 bit_num);
u32 phydm_gen_bitmask(u8 mask_num);
u16 phydm_ones_num_in_bitmap(u64 val, u8 size);
u64 phydm_gen_bitmask(u8 mask_num);
s32 phydm_cnvrt_2_sign(u32 val, u8 bit_num);
s64 phydm_cnvrt_2_sign_64(u64 val, u8 bit_num);
#endif

18
hal/phydm/phydm_mp.c
View File

@@ -39,6 +39,7 @@ void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_mp *mp = &dm->dm_mp_table;
u8 start = RF_PATH_A, end = RF_PATH_A;
u8 i = 0;
switch (path) {
case RF_PATH_A:
@@ -109,15 +110,15 @@ void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
#endif
/* Disable CCK and OFDM */
odm_set_bb_reg(dm, R_0x1c3c, 0x3, 0x0);
for (start; start <= end; start++) {
for (i = start; i <= end; i++) {
/* @Tx mode: RF0x00[19:16]=4'b0010 */
odm_set_rf_reg(dm, start, RF_0x0, 0xF0000, 0x2);
odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);
/* @Lowest RF gain index: RF_0x0[4:0] = 0*/
odm_set_rf_reg(dm, start, RF_0x0, 0x1F, 0x0);
odm_set_rf_reg(dm, i, RF_0x0, 0x1F, 0x0);
/* @RF LO enabled */
odm_set_rf_reg(dm, start, RF_0x58, BIT(1), 0x1);
odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
}
#if (RTL8814B_SUPPORT == 1)
#if (RTL8814B_SUPPORT)
if (dm->support_ic_type & ODM_RTL8814B) {
/* @Tx mode: RF0x00[19:16]=4'b0010 */
config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
@@ -134,12 +135,11 @@ void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
/* Eable CCK and OFDM */
odm_set_bb_reg(dm, R_0x1c3c, 0x3, 0x3);
if (!(dm->support_ic_type & ODM_RTL8814B)) {
for (start; start <= end; start++) {
odm_set_rf_reg(dm, start, RF_0x00, 0xfffff,
for (i = start; i <= end; i++) {
odm_set_rf_reg(dm, i, RF_0x00, 0xfffff,
mp->rf_reg0);
/* RF LO disabled */
odm_set_rf_reg(dm, start, RF_0x58, BIT(1),
0x0);
odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
}
}
#if 0

10
hal/phydm/phydm_mp.h
View File

@@ -26,7 +26,7 @@
#ifndef __PHYDM_MP_H__
#define __PHYDM_MP_H__
#define MP_VERSION "1.0"
#define MP_VERSION "1.3"
/* @1 ============================================================
* 1 Definition
@@ -69,14 +69,6 @@ enum TX_MODE_OFDM {
* 1 function prototype
* 1 ============================================================
*/
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
u8 path);
void phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp,
u32 rate_index);
#endif
void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap);
void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path);

327
hal/phydm/phydm_pathdiv.c
View File

@@ -597,34 +597,13 @@ void phydm_path_diversity_init_8812a(void *dm_void)
#endif
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
void phydm_tx_path_diversity_init_jgr3(void *dm_void)
void phydm_set_resp_tx_path_by_fw_jgr3(void *dm_void, u8 macid,
enum bb_path path, boolean enable)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
u32 i;
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
p_div->path_sel[i] = BB_PATH_A; /* TxInfo default at path-A */
}
void phydm_tx_by_mac_or_reg_jgr3(void *dm_void, enum phydm_path_ctrl ctrl)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (ctrl == TX_PATH_BY_REG) {
odm_set_bb_reg(dm, R_0x1e24, BIT(16), 0);
} else {
odm_set_bb_reg(dm, R_0x1e24, BIT(16), 1);
}
}
void phydm_set_resp_tx_path_by_fw(void *dm_void, u8 macid, enum bb_path path,
boolean enable)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
u8 h2c_para[6] = {0};
u8 path_map[4];
u8 h2c_para[7] = {0};
u8 path_map[4] = {0}; /* tx logic map*/
u8 num_enable_path = 0;
u8 n_tx_path_ctrl_map = 0;
u8 i = 0, n_sts = 0;
@@ -662,28 +641,72 @@ void phydm_set_resp_tx_path_by_fw(void *dm_void, u8 macid, enum bb_path path,
h2c_para[2] = (path_map[3] << 6) | (path_map[2] << 4) |
(path_map[1] << 2) | path_map[0];
odm_fill_h2c_cmd(dm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, h2c_para);
odm_fill_h2c_cmd(dm, PHYDM_H2C_DYNAMIC_TX_PATH, 7, h2c_para);
}
void phydm_get_tx_path_txdesc_jgr3(void *dm_void, u8 macid,
struct path_txdesc_ctrl *desc)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
u8 ant_map_a = 0, ant_map_b = 0;
u8 ntx_map = 0;
if (p_div->path_sel[macid] == BB_PATH_A) {
desc->ant_map_a = 0; /*offest24[23:22]*/
desc->ant_map_b = 0; /*offest24[25:24]*/
desc->ntx_map = BB_PATH_A; /*offest28[23:20]*/
} else if (p_div->path_sel[macid] == BB_PATH_B) {
desc->ant_map_a = 0; /*offest24[23:22]*/
desc->ant_map_b = 0; /*offest24[25:24]*/
desc->ntx_map = BB_PATH_B; /*offest28[23:20]*/
} else {
desc->ant_map_a = 0; /*offest24[23:22]*/
desc->ant_map_b = 1; /*offest24[25:24]*/
desc->ntx_map = BB_PATH_AB; /*offest28[23:20]*/
}
}
#endif
void phydm_set_tx_path_by_bb_reg(void *dm_void, enum bb_path path)
void phydm_tx_path_by_mac_or_reg(void *dm_void, enum phydm_path_ctrl ctrl)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] path=%s\n",
__func__, (path == BB_PATH_A) ? "A" : "B");
PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] ctrl=%s\n",
__func__, (ctrl == TX_PATH_BY_REG) ? "REG" : "DESC");
if (ctrl == p_div->tx_path_ctrl)
return;
p_div->tx_path_ctrl = ctrl;
switch (dm->support_ic_type) {
#if RTL8822C_SUPPORT
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
case ODM_RTL8822B:
case ODM_RTL8822C:
phydm_config_tx_path_8822c(dm, path);
case ODM_RTL8812F:
case ODM_RTL8197G:
if (ctrl == TX_PATH_BY_REG) {
odm_set_bb_reg(dm, R_0x1e24, BIT(16), 0); /*OFDM*/
odm_set_bb_reg(dm, R_0x1a84, 0xe0, 0); /*CCK*/
} else {
odm_set_bb_reg(dm, R_0x1e24, BIT(16), 1); /*OFDM*/
odm_set_bb_reg(dm, R_0x1a84, 0xe0, 7); /*CCK*/
}
break;
#endif
#if 0 /*(RTL8822B_SUPPORT)*/ /*@ HW Bug*/
case ODM_RTL8822B:
if (ctrl == TX_PATH_BY_REG) {
odm_set_bb_reg(dm, R_0x93c, BIT(18), 0);
odm_set_bb_reg(dm, R_0xa84, 0xe0, 0); /*CCK*/
} else {
odm_set_bb_reg(dm, R_0x93c, BIT(18), 1);
odm_set_bb_reg(dm, R_0xa84, 0xe0, 7); /*CCK*/
}
#if RTL8812A_SUPPORT
case ODM_RTL8812:
phydm_update_tx_path_8812a(dm, path);
break;
#endif
default:
@@ -691,18 +714,106 @@ void phydm_set_tx_path_by_bb_reg(void *dm_void, enum bb_path path)
}
}
u8 phydm_get_tx_path_txdesc(void *dm_void, u8 macid)
void phydm_fix_1ss_tx_path_by_bb_reg(void *dm_void,
enum bb_path tx_path_sel_1ss,
enum bb_path tx_path_sel_cck)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
u8 rpt_val = 0;
if (p_div->path_sel[macid] == BB_PATH_A)
rpt_val = 1;
else if (p_div->path_sel[macid] == BB_PATH_B)
rpt_val = 2;
if (tx_path_sel_1ss != BB_PATH_AUTO) {
p_div->ofdm_fix_path_en = true;
p_div->ofdm_fix_path_sel = tx_path_sel_1ss;
} else {
p_div->ofdm_fix_path_en = false;
p_div->ofdm_fix_path_sel = dm->tx_1ss_status;
}
return rpt_val;
if (tx_path_sel_cck != BB_PATH_AUTO) {
p_div->cck_fix_path_en = true;
p_div->cck_fix_path_sel = tx_path_sel_cck;
} else {
p_div->cck_fix_path_en = false;
p_div->cck_fix_path_sel = dm->tx_1ss_status;
}
p_div->force_update = true;
PHYDM_DBG(dm, DBG_PATH_DIV,
"{OFDM_fix_en=%d, path=%d} {CCK_fix_en=%d, path=%d}\n",
p_div->ofdm_fix_path_en, p_div->ofdm_fix_path_sel,
p_div->cck_fix_path_en, p_div->cck_fix_path_sel);
}
void phydm_set_tx_path_by_bb_reg(void *dm_void, enum bb_path tx_path_sel_1ss)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
enum bb_path tx_path_sel_cck = tx_path_sel_1ss;
if (!p_div->force_update) {
if (tx_path_sel_1ss == p_div->default_tx_path) {
PHYDM_DBG(dm, DBG_PATH_DIV, "Stay in TX path=%s\n",
(tx_path_sel_1ss == BB_PATH_A) ? "A" : "B");
return;
}
}
p_div->force_update = false;
p_div->default_tx_path = tx_path_sel_1ss;
PHYDM_DBG(dm, DBG_PATH_DIV, "Switch TX path=%s\n",
(tx_path_sel_1ss == BB_PATH_A) ? "A" : "B");
/*Adv-ctrl mode*/
if (p_div->cck_fix_path_en) {
PHYDM_DBG(dm, DBG_PATH_DIV, "Fix CCK TX path=%d\n",
p_div->cck_fix_path_sel);
tx_path_sel_cck = p_div->cck_fix_path_sel;
}
if (p_div->ofdm_fix_path_en) {
PHYDM_DBG(dm, DBG_PATH_DIV, "Fix OFDM TX path=%d\n",
p_div->ofdm_fix_path_sel);
tx_path_sel_1ss = p_div->ofdm_fix_path_sel;
}
switch (dm->support_ic_type) {
#if RTL8822C_SUPPORT
case ODM_RTL8822C:
phydm_config_tx_path_8822c(dm, dm->tx_2ss_status,
tx_path_sel_1ss, tx_path_sel_cck);
break;
#endif
#if RTL8822B_SUPPORT
case ODM_RTL8822B:
if (dm->tx_ant_status != BB_PATH_AB)
return;
phydm_config_tx_path_8822b(dm, BB_PATH_AB,
tx_path_sel_1ss, tx_path_sel_cck);
break;
#endif
#if RTL8192F_SUPPORT
case ODM_RTL8192F:
if (dm->tx_ant_status != BB_PATH_AB)
return;
phydm_config_tx_path_8192f(dm, BB_PATH_AB,
tx_path_sel_1ss, tx_path_sel_cck);
break;
#endif
#if RTL8812A_SUPPORT
case ODM_RTL8812:
phydm_update_tx_path_8812a(dm, tx_path_sel_1ss);
break;
#endif
default:
break;
}
}
void phydm_tx_path_diversity_2ss(void *dm_void)
@@ -710,32 +821,39 @@ void phydm_tx_path_diversity_2ss(void *dm_void)
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
struct cmn_sta_info *sta;
enum bb_path default_path = BB_PATH_A, path = BB_PATH_A;
enum bb_path default_tx_path = BB_PATH_A, path = BB_PATH_A;
u32 rssi_a = 0, rssi_b = 0;
u32 local_max_rssi, min_rssi = 0xff;
u32 local_max_rssi, glb_min_rssi = 0xff;
u8 i = 0;
PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] =======>\n", __func__);
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
if (!dm->is_linked) {
if (dm->first_disconnect)
phydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_REG);
PHYDM_DBG(dm, DBG_PATH_DIV, "No Link\n");
return;
}
#if 0/*def PHYDM_IC_JGR3_SERIES_SUPPORT*/
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
if (dm->is_one_entry_only)
phydm_tx_by_mac_or_reg_jgr3(dm, TX_PATH_BY_REG);
if (dm->is_one_entry_only || p_div->cck_fix_path_en ||
p_div->ofdm_fix_path_en)
phydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_REG);
else
phydm_tx_by_mac_or_reg_jgr3(dm, TX_PATH_BY_DESC);
phydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_DESC);
}
#endif
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
sta = dm->phydm_sta_info[i];
if (is_sta_active(sta))
if (!is_sta_active(sta))
continue;
/* 2 Caculate RSSI per path */
rssi_a = (p_div->path_a_cnt[i]) ?
(p_div->path_a_sum[i] / p_div->path_a_cnt[i]) : 0;
rssi_b = (p_div->path_b_cnt[i]) ?
(p_div->path_b_sum[i] / p_div->path_b_cnt[i]) : 0;
rssi_a = PHYDM_DIV(p_div->path_a_sum[i], p_div->path_a_cnt[i]);
rssi_b = PHYDM_DIV(p_div->path_b_sum[i], p_div->path_b_cnt[i]);
if (rssi_a == rssi_b)
path = p_div->default_tx_path;
@@ -754,16 +872,17 @@ void phydm_tx_path_diversity_2ss(void *dm_void)
p_div->path_b_cnt[i], rssi_b);
/*Select default Tx path */
if (local_max_rssi < min_rssi) {
min_rssi = local_max_rssi;
default_path = path;
if (local_max_rssi < glb_min_rssi) {
glb_min_rssi = local_max_rssi;
default_tx_path = path;
}
if (p_div->path_sel[i] != path) {
p_div->path_sel[i] = path;
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_set_resp_tx_path_by_fw(dm, i, path, true);
phydm_set_resp_tx_path_by_fw_jgr3(dm, i,
path, true);
#endif
}
@@ -774,21 +893,48 @@ void phydm_tx_path_diversity_2ss(void *dm_void)
}
/* 2 Update default Tx path */
if (default_path != p_div->default_tx_path)
phydm_set_tx_path_by_bb_reg(dm, default_path);
phydm_set_tx_path_by_bb_reg(dm, default_tx_path);
PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] end\n\n", __func__);
}
void phydm_tx_path_diversity(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
p_div->path_div_in_progress = false;
if (!(dm->support_ability & ODM_BB_PATH_DIV))
return;
if (p_div->stop_path_div) {
PHYDM_DBG(dm, DBG_PATH_DIV,
"stop_path_div=1, tx_1ss_status=%d\n",
dm->tx_1ss_status);
return;
}
switch (dm->support_ic_type) {
#if (RTL8822C_SUPPORT || RTL8812A_SUPPORT)
case ODM_RTL8812:
#ifdef PHYDM_CONFIG_PATH_DIV_V2
case ODM_RTL8822B:
case ODM_RTL8822C:
case ODM_RTL8192F:
case ODM_RTL8812F:
case ODM_RTL8197G:
if (dm->rx_ant_status != BB_PATH_AB) {
PHYDM_DBG(dm, DBG_PATH_DIV,
"[Return] tx_Path_en=%d, rx_Path_en=%d\n",
dm->tx_ant_status, dm->rx_ant_status);
return;
}
p_div->path_div_in_progress = true;
phydm_tx_path_diversity_2ss(dm);
break;
#endif
#if (RTL8812A_SUPPORT)
case ODM_RTL8812:
phydm_tx_path_diversity_2ss(dm);
break;
#endif
@@ -801,6 +947,29 @@ void phydm_tx_path_diversity(void *dm_void)
}
}
void phydm_tx_path_diversity_init_v2(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
u32 i = 0;
PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] ====>\n", __func__);
/*BB_PATH_AB is a invalid value used for init state*/
p_div->default_tx_path = BB_PATH_A;
p_div->tx_path_ctrl = TX_PATH_CTRL_INIT;
p_div->path_div_in_progress = false;
p_div->cck_fix_path_en = false;
p_div->ofdm_fix_path_en = false;
p_div->force_update = false;
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
p_div->path_sel[i] = BB_PATH_A; /* TxInfo default at path-A */
phydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_REG);
}
void phydm_tx_path_diversity_init(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
@@ -809,9 +978,13 @@ void phydm_tx_path_diversity_init(void *dm_void)
return;
switch (dm->support_ic_type) {
#if RTL8822C_SUPPORT
#ifdef PHYDM_CONFIG_PATH_DIV_V2
case ODM_RTL8822C:
phydm_tx_path_diversity_init_jgr3(dm);
case ODM_RTL8822B:
case ODM_RTL8192F:
case ODM_RTL8812F:
case ODM_RTL8197G:
phydm_tx_path_diversity_init_v2(dm); /*@ After 8822B*/
break;
#endif
@@ -844,7 +1017,7 @@ void phydm_process_rssi_for_path_div(void *dm_void, void *phy_info_void,
if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_match_bssid))
return;
if (pktinfo->data_rate <= ODM_RATE11M)
if (pktinfo->is_cck_rate)
return;
id = pktinfo->station_id;
@@ -858,43 +1031,57 @@ void phydm_process_rssi_for_path_div(void *dm_void, void *phy_info_void,
void phydm_pathdiv_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
char help[] = "-h";
u32 used = *_used;
u32 out_len = *_out_len;
u32 val[10] = {0};
u8 i, input_idx = 0;
for (i = 0; i < 5; i++) {
if (input[i + 1]) {
PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
input_idx++;
}
}
if (input_idx == 0)
return;
PHYDM_SSCANF(input[1], DCMD_HEX, &val[0]);
PHYDM_SSCANF(input[2], DCMD_HEX, &val[1]);
if ((strcmp(input[1], "-h") == 0)) {
if ((strcmp(input[1], help) == 0)) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"{1:TX Ctrl Sig} {0:BB, 1:MAC}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"{2:BB Default TX REG} {path}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"{3:MAC DESC TX} {path} {macid}\n");
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
PDM_SNPF(out_len, used, output + used, out_len - used,
"{4:MAC Resp TX} {path} {macid}\n");
#endif
PDM_SNPF(out_len, used, output + used, out_len - used,
"{5:Fix 1ss path} {ofdm path} {cck path}\n");
} else if (val[0] == 1) {
phydm_tx_by_mac_or_reg_jgr3(dm, (enum phydm_path_ctrl)val[1]);
phydm_tx_path_by_mac_or_reg(dm, (enum phydm_path_ctrl)val[1]);
} else if (val[0] == 2) {
phydm_set_tx_path_by_bb_reg(dm, (enum bb_path)val[1]);
} else if (val[0] == 3) {
p_div->path_sel[val[2]] = (enum bb_path)val[1];
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
} else if (val[0] == 4) {
phydm_set_resp_tx_path_by_fw(dm, (u8)val[2],
(enum bb_path)val[1], true);
phydm_set_resp_tx_path_by_fw_jgr3(dm, (u8)val[2],
(enum bb_path)val[1], true);
#endif
} else if (val[0] == 5) {
phydm_fix_1ss_tx_path_by_bb_reg(dm, (enum bb_path)val[1],
(enum bb_path)val[2]);
}
*_used = used;
*_out_len = out_len;
#endif
}
void phydm_c2h_dtp_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)

30
hal/phydm/phydm_pathdiv.h
View File

@@ -27,7 +27,13 @@
#define __PHYDMPATHDIV_H__
#ifdef CONFIG_PATH_DIVERSITY
#define PATHDIV_VERSION "4.0"
/* @2019.03.07 open resp tx path h2c only for 1ss status*/
#define PATHDIV_VERSION "4.4"
#if (RTL8192F_SUPPORT || RTL8822B_SUPPORT || RTL8822C_SUPPORT ||\
RTL8812F_SUPPORT || RTL8197G_SUPPORT)
#define PHYDM_CONFIG_PATH_DIV_V2
#endif
#define USE_PATH_A_AS_DEFAULT_ANT /* @for 8814 dynamic TX path selection */
@@ -57,10 +63,24 @@ enum phydm_path_div_type {
enum phydm_path_ctrl {
TX_PATH_BY_REG = 0,
TX_PATH_BY_DESC = 1
TX_PATH_BY_DESC = 1,
TX_PATH_CTRL_INIT
};
struct path_txdesc_ctrl {
u8 ant_map_a : 2;
u8 ant_map_b : 2;
u8 ntx_map : 4;
};
struct _ODM_PATH_DIVERSITY_ {
boolean stop_path_div; /*@Limit by enabled path number*/
boolean path_div_in_progress;
boolean cck_fix_path_en; /*@ BB Reg for Adv-Ctrl (or debug mode)*/
boolean ofdm_fix_path_en; /*@ BB Reg for Adv-Ctrl (or debug mode)*/
enum bb_path cck_fix_path_sel; /*@ BB Reg for Adv-Ctrl (or debug mode)*/
enum bb_path ofdm_fix_path_sel;/*@ BB Reg for Adv-Ctrl (or debug mode)*/
enum phydm_path_ctrl tx_path_ctrl;
enum bb_path default_tx_path;
enum bb_path path_sel[ODM_ASSOCIATE_ENTRY_NUM];
u32 path_a_sum[ODM_ASSOCIATE_ENTRY_NUM];
@@ -68,6 +88,7 @@ struct _ODM_PATH_DIVERSITY_ {
u16 path_a_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u16 path_b_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u8 phydm_path_div_type;
boolean force_update;
#if RTL8814A_SUPPORT
u32 path_a_sum_all;
@@ -102,9 +123,10 @@ struct _ODM_PATH_DIVERSITY_ {
#endif
};
void phydm_set_tx_path_by_bb_reg(void *dm_void, u8 path);
void phydm_set_tx_path_by_bb_reg(void *dm_void, enum bb_path tx_path_sel_1ss);
u8 phydm_get_tx_path_txdesc(void *dm_void, u8 macid);
void phydm_get_tx_path_txdesc_jgr3(void *dm_void, u8 macid,
struct path_txdesc_ctrl *desc);
void phydm_c2h_dtp_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);

803
hal/phydm/phydm_phystatus.c
View File

File diff suppressed because it is too large Load Diff

3
hal/phydm/phydm_phystatus.h
View File

@@ -1134,4 +1134,7 @@ void odm_phy_status_query(struct dm_struct *dm,
void phydm_rx_phy_status_init(void *dm_void);
void phydm_physts_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif /*@#ifndef __HALHWOUTSRC_H__*/

29
hal/phydm/phydm_pmac_tx_setting.c
View File

@@ -129,6 +129,7 @@ void phydm_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
u8 start = RF_PATH_A, end = RF_PATH_A;
u8 i = 0;
switch (path) {
case RF_PATH_A:
@@ -196,13 +197,13 @@ void phydm_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
odm_set_bb_reg(dm, R_0x1c68, BIT(24), 0x1); /* @Disable CCA */
for (start; start <= end; start++) {
for (i = start; i <= end; i++) {
/* @Tx mode: RF0x00[19:16]=4'b0010 */
/* odm_set_rf_reg(dm, start, RF_0x0, 0xF0000, 0x2); */
/* @odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2); */
/* @Lowest RF gain index: RF_0x0[4:0] = 0*/
odm_set_rf_reg(dm, start, RF_0x0, 0x1F, 0x0);
odm_set_rf_reg(dm, i, RF_0x0, 0x1F, 0x0);
/* @RF LO enabled */
odm_set_rf_reg(dm, start, RF_0x58, BIT(1), 0x1);
odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
}
#if (RTL8814B_SUPPORT == 1)
if (dm->support_ic_type & ODM_RTL8814B) {
@@ -220,9 +221,9 @@ void phydm_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
#endif
odm_set_bb_reg(dm, R_0x81c, 0x001FC000, 0);
} else {
for (start; start <= end; start++) {
for (i = start; i <= end; i++) {
/* @RF LO disabled */
odm_set_rf_reg(dm, start, RF_0x58, BIT(1), 0x0);
odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
}
odm_set_bb_reg(dm, R_0x1c68, BIT(24), 0x0); /* @Enable CCA */
@@ -275,9 +276,15 @@ void phydm_set_mac_phy_txinfo_jgr3(void *dm_void,
/* @0x900[1] ndp_sound */
odm_set_bb_reg(dm, R_0x900, 0x2, tx_info->ndp_sound);
/* @0x900[27:24] txsc [29:28] bw [31:30] m_stbc */
tmp = (tx_info->tx_sc) | ((tx_info->bw) << 4) |
((tx_info->m_stbc - 1) << 6);
if (dm->support_ic_type & (ODM_RTL8812F | ODM_RTL8197G)) {
tmp = (tx_info->tx_sc) | ((tx_info->bw) << 4) |
((tx_info->m_stbc) << 6);
} else {
tmp = (tx_info->tx_sc) | ((tx_info->bw) << 4) |
((tx_info->m_stbc - 1) << 6);
}
odm_set_bb_reg(dm, R_0x900, 0xFF000000, tmp);
if (pmac_tx->is_ofdm_rate) {
@@ -415,10 +422,10 @@ void phydm_set_pmac_txon_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
odm_set_bb_reg(dm, R_0x1d08, BIT(0), 1); /* Turn on PMAC */
/* mac scramble seed setting, only in 8198F */
#if (RTL8198F_SUPPORT == 1)
#if (RTL8198F_SUPPORT)
if (dm->support_ic_type & ODM_RTL8198F)
if ~(odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
odm_set_bb_reg(dm, R_0x1d10, BIT(16), 1);
if (!odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
odm_set_bb_reg(dm, R_0x1d10, BIT(16), 1);
#endif
if (pmac_tx->is_cck_rate) {

37
hal/phydm/phydm_pmac_tx_setting.h
View File

@@ -26,7 +26,7 @@
#ifndef __PHYDM_PMAC_TX_SETTING_H__
#define __PHYDM_PMAC_TX_SETTING_H__
#define PMAC_TX_SETTING_VERSION "1.0"
#define PMAC_TX_SETTING_VERSION "1.3"
/* @1 ============================================================
* 1 Definition
@@ -98,41 +98,6 @@ enum phydm_pmac_mode {
* 1 function prototype
* 1 ============================================================
*/
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
void phydm_start_cck_cont_tx_jgr3(void *dm_void,
struct phydm_pmac_info *tx_info);
void phydm_stop_cck_cont_tx_jgr3(void *dm_void);
void phydm_start_ofdm_cont_tx_jgr3(void *dm_void);
void phydm_stop_ofdm_cont_tx_jgr3(void *dm_void);
void phydm_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
boolean en_pmac_tx, u8 path);
void phydm_stop_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info);
void phydm_set_mac_phy_txinfo_jgr3(void *dm_void,
struct phydm_pmac_info *tx_info);
void phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info);
void phydm_set_cck_preamble_hdr_jgr3(void *dm_void,
struct phydm_pmac_info *tx_info);
void phydm_set_mode_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
enum phydm_pmac_mode mode);
void phydm_set_pmac_txon_jgr3(void *dm_void, struct phydm_pmac_info *tx_info);
void phydm_set_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
enum rf_path mpt_rf_path);
void phydm_set_tmac_tx_jgr3(void *dm_void);
#endif
void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info);
void phydm_stop_cck_cont_tx(void *dm_void);

138
hal/phydm/phydm_pre_define.h
View File

@@ -32,8 +32,8 @@
* 1 ============================================================
***************************************************************/
#define PHYDM_CODE_BASE "PHYDM_V033"
#define PHYDM_RELEASE_DATE "20180906.0"
#define PHYDM_CODE_BASE "PHYDM_V039"
#define PHYDM_RELEASE_DATE "20190410.0"
/*PHYDM API status*/
#define PHYDM_SET_FAIL 0
@@ -58,6 +58,8 @@
#define MAX_PATH_NUM_8198F 4
#define MAX_PATH_NUM_8197G 2
#define MAX_PATH_NUM_8721D 1
#define MAX_PATH_NUM_8710C 1
/*@AC-IC*/
#define MAX_PATH_NUM_8821A 1
#define MAX_PATH_NUM_8881A 1
@@ -309,23 +311,44 @@ enum phydm_ctrl_info_rate {
ODM_RATEVHTSS4MCS9 = 0x53,
};
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9 + 1)
#define NUM_RATE_AC_4SS (ODM_RATEVHTSS4MCS9 + 1)
#define NUM_RATE_AC_3SS (ODM_RATEVHTSS3MCS9 + 1)
#define NUM_RATE_AC_2SS (ODM_RATEVHTSS2MCS9 + 1)
#define NUM_RATE_AC_1SS (ODM_RATEVHTSS1MCS9 + 1)
#define NUM_RATE_N_4SS (ODM_RATEMCS31 + 1)
#define NUM_RATE_N_3SS (ODM_RATEMCS23 + 1)
#define NUM_RATE_N_2SS (ODM_RATEMCS15 + 1)
#define NUM_RATE_N_1SS (ODM_RATEMCS7 + 1)
/*Define from larger rate size to small rate size, DO NOT change the position*/
/*[AC-4SS]*/
#if (RTL8814B_SUPPORT)
#define PHY_NUM_RATE_IDX NUM_RATE_AC_4SS
/*[AC-3SS]*/
#elif (RTL8814A_SUPPORT)
#define PHY_NUM_RATE_IDX NUM_RATE_AC_3SS
/*[AC-2SS]*/
#elif (RTL8812A_SUPPORT || RTL8822B_SUPPORT || RTL8822C_SUPPORT ||\
RTL8812F_SUPPORT)
#define PHY_NUM_RATE_IDX NUM_RATE_AC_2SS
/*[AC-1SS]*/
#elif (RTL8881A_SUPPORT || RTL8821A_SUPPORT || RTL8821C_SUPPORT ||\
RTL8195B_SUPPORT)
#define PHY_NUM_RATE_IDX NUM_RATE_AC_1SS
/*[N-4SS]*/
#elif (RTL8198F_SUPPORT)
#define PHY_NUM_RATE_IDX NUM_RATE_N_4SS
/*[N-2SS]*/
#elif (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\
RTL8197G_SUPPORT)
#define PHY_NUM_RATE_IDX NUM_RATE_N_2SS
/*[N-1SS]*/
#elif (RTL8723B_SUPPORT || RTL8703B_SUPPORT || RTL8188E_SUPPORT || \
RTL8188F_SUPPORT || RTL8723D_SUPPORT || RTL8195A_SUPPORT ||\
RTL8710B_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
#define PHY_NUM_RATE_IDX NUM_RATE_N_1SS
#else
#if (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
#define ODM_NUM_RATE_IDX (ODM_RATEMCS15 + 1)
#elif (RTL8723B_SUPPORT || RTL8188E_SUPPORT || \
RTL8188F_SUPPORT || RTL8721D_SUPPORT)
#define ODM_NUM_RATE_IDX (ODM_RATEMCS7 + 1)
#elif (RTL8821A_SUPPORT || RTL8881A_SUPPORT)
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS1MCS9 + 1)
#elif (RTL8812A_SUPPORT)
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS2MCS9 + 1)
#elif (RTL8814A_SUPPORT)
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS3MCS9 + 1)
#else
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9 + 1)
#endif
#define PHY_NUM_RATE_IDX NUM_RATE_AC_4SS
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
@@ -346,6 +369,11 @@ enum odm_interface {
ODM_ITRF_ALL = 0x7,
};
enum phydm_api_host {
RUN_IN_FW = 0,
RUN_IN_DRIVER = 1,
};
/*@========[Run time IC flag] ===================================*/
enum phydm_ic {
@@ -371,12 +399,13 @@ enum phydm_ic {
ODM_RTL8195B = BIT(19),
ODM_RTL8812F = BIT(20),
ODM_RTL8197G = BIT(21),
ODM_RTL8721D = BIT(22)
ODM_RTL8721D = BIT(22),
ODM_RTL8710C = BIT(23)
};
#define ODM_IC_N_1SS (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B |\
ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8195A |\
ODM_RTL8710B | ODM_RTL8721D)
ODM_RTL8710B | ODM_RTL8721D | ODM_RTL8710C)
#define ODM_IC_N_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F)
#define ODM_IC_N_3SS 0
#define ODM_IC_N_4SS 0
@@ -419,13 +448,14 @@ enum phydm_ic {
/*@[Phy status type]*/
#define PHYSTS_2ND_TYPE_IC (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D |\
ODM_RTL8821C | ODM_RTL8710B | ODM_RTL8195B |\
ODM_RTL8192F | ODM_RTL8721D)
ODM_RTL8192F | ODM_RTL8721D | ODM_RTL8710C)
#define PHYSTS_3RD_TYPE_IC (ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8822C |\
ODM_RTL8812F | ODM_RTL8197G)
/*@[FW Type]*/
#define PHYDM_IC_8051_SERIES (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 |\
ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B |\
ODM_RTL8188F | ODM_RTL8192F | ODM_RTL8721D)
ODM_RTL8188F | ODM_RTL8192F | ODM_RTL8721D |\
ODM_RTL8710C)
#define PHYDM_IC_3081_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\
ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\
ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8814B |\
@@ -453,7 +483,7 @@ enum phydm_ic {
#define CMN_API_SUPPORT_IC (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F |\
ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8822C |\
ODM_RTL8198F | ODM_RTL8812F | ODM_RTL8814B |\
ODM_RTL8197G | ODM_RTL8721D)
ODM_RTL8197G | ODM_RTL8721D | ODM_RTL8710C)
/*@========[Compile time IC flag] ========================*/
/*@========[AC-3/AC/N Support] ===========================*/
@@ -496,7 +526,7 @@ enum phydm_ic {
#if (RTL8188E_SUPPORT || RTL8723B_SUPPORT || RTL8192E_SUPPORT ||\
RTL8195A_SUPPORT || RTL8703B_SUPPORT || RTL8188F_SUPPORT ||\
RTL8723D_SUPPORT || RTL8197F_SUPPORT || RTL8710B_SUPPORT ||\
RTL8192F_SUPPORT || RTL8721D_SUPPORT)
RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
#define ODM_IC_11N_SERIES_SUPPORT 1
#define ODM_IC_11AC_SERIES_SUPPORT 0
#else
@@ -509,7 +539,8 @@ enum phydm_ic {
#if (RTL8188E_SUPPORT || RTL8188F_SUPPORT || RTL8723B_SUPPORT ||\
RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8881A_SUPPORT ||\
RTL8821A_SUPPORT || RTL8821C_SUPPORT || RTL8195A_SUPPORT ||\
RTL8710B_SUPPORT || RTL8195B_SUPPORT || RTL8721D_SUPPORT)
RTL8710B_SUPPORT || RTL8195B_SUPPORT || RTL8721D_SUPPORT ||\
RTL8710C_SUPPORT)
#define PHYDM_COMPILE_IC_1SS
#endif
@@ -545,17 +576,30 @@ enum phydm_ic {
#define PHYDM_COMPILE_ABOVE_4SS
#endif
/*@==[Max RF path number among all compiled ICs]==============================*/
/*@ ex: support 8814B & 8821C => size=4 */
/*@ ex: support 8822C & 8821C => size=2 */
#if (defined(PHYDM_COMPILE_IC_4SS))
#define RF_PATH_MEM_SIZE 4
#elif (defined(PHYDM_COMPILE_IC_3SS))
#define RF_PATH_MEM_SIZE 3
#elif (defined(PHYDM_COMPILE_IC_2SS))
#define RF_PATH_MEM_SIZE 2
#else
#define RF_PATH_MEM_SIZE 1
#endif
/*@========[New Phy-Status Support] ========================*/
#if (RTL8197F_SUPPORT || RTL8723D_SUPPORT || RTL8822B_SUPPORT ||\
RTL8821C_SUPPORT || RTL8710B_SUPPORT || RTL8195B_SUPPORT ||\
RTL8192F_SUPPORT || RTL8721D_SUPPORT)
RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 1
#else
#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 0
#endif
#if (RTL8198F_SUPPORT) || (RTL8814B_SUPPORT) || (RTL8822C_SUPPORT) ||\
(RTL8812F_SUPPORT) || (RTL8197G_SUPPORT)
#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8822C_SUPPORT ||\
RTL8812F_SUPPORT || RTL8197G_SUPPORT)
#define PHYSTS_3RD_TYPE_SUPPORT
#endif
@@ -569,15 +613,34 @@ enum phydm_ic {
RTL8198F_SUPPORT)
#define PHYDM_COMPILE_MU
#endif
#if (RTL8822B_SUPPORT)
#define CONFIG_MU_JAGUAR_2
#endif
#if (RTL8814B_SUPPORT || RTL8822C_SUPPORT)
#define CONFIG_MU_JAGUAR_3
#endif
#if (defined(CONFIG_MU_JAGUAR_2) || defined(CONFIG_MU_JAGUAR_3))
#if (RTL8814B_SUPPORT)
#define MU_EX_MACID 76
#elif (RTL8822B_SUPPORT || RTL8822C_SUPPORT)
#define MU_EX_MACID 30
#endif
#endif
/*@============================================================================*/
#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\
RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8822C_SUPPORT ||\
RTL8198F_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT ||\
RTL8197G_SUPPORT || RTL8721D_SUPPORT)
RTL8197G_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
#define PHYDM_COMMON_API_SUPPORT
#endif
#if (RTL8821C_SUPPORT || RTL8197F_SUPPORT || RTL8814B_SUPPORT)
#define CONFIG_RFE_BY_HW_INFO
#endif
#define CCK_RATE_NUM 4
#define OFDM_RATE_NUM 8
@@ -636,6 +699,10 @@ enum odm_cut_version {
ODM_CUT_I = 8,
ODM_CUT_J = 9,
ODM_CUT_K = 10,
ODM_CUT_L = 11,
ODM_CUT_M = 12,
ODM_CUT_N = 13,
ODM_CUT_O = 14,
ODM_CUT_TEST = 15,
};
@@ -817,6 +884,14 @@ enum odm_type_alna {
TYPE_ALNA15 = 0xFFFF,
};
#if (RTL8721D_SUPPORT)
/* ODM_CMNINFO_POWER_VOLTAGE */
enum odm_power_voltage {
ODM_POWER_18V = 0,
ODM_POWER_33V = 1,
};
#endif
#define PAUSE_FAIL 0
#define PAUSE_SUCCESS 1
@@ -832,6 +907,11 @@ enum phydm_pause_type {
PHYDM_RESUME = 3
};
enum phydm_backup_type {
PHYDM_BACKUP = 1,
PHYDM_RESTORE = 2
};
enum phydm_pause_level {
PHYDM_PAUSE_RELEASE = -1,
PHYDM_PAUSE_LEVEL_0 = 0, /* @Low Priority function */

188
hal/phydm/phydm_precomp.h
View File

@@ -45,14 +45,23 @@
#include "../8192cd_util.h"
#include "../8192cd_hw.h"
#ifdef _BIG_ENDIAN_
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#else
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#endif
#include "../8192cd_headers.h"
#include "../8192cd_debug.h"
#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
#define INIT_TIMER_EVENT_ENTRY(_entry, _func, _data) \
do { \
_rtw_init_listhead(&(_entry)->list); \
(_entry)->data = (_data); \
(_entry)->function = (_func); \
} while (0)
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#ifdef DM_ODM_CE_MAC80211
#include "../wifi.h"
@@ -88,6 +97,79 @@
#include "phydm_reg.h"
#include "halrf/halrf_debug.h"
#ifndef RTL8188E_SUPPORT
#define RTL8188E_SUPPORT 0
#endif
#ifndef RTL8812A_SUPPORT
#define RTL8812A_SUPPORT 0
#endif
#ifndef RTL8821A_SUPPORT
#define RTL8821A_SUPPORT 0
#endif
#ifndef RTL8192E_SUPPORT
#define RTL8192E_SUPPORT 0
#endif
#ifndef RTL8723B_SUPPORT
#define RTL8723B_SUPPORT 0
#endif
#ifndef RTL8814A_SUPPORT
#define RTL8814A_SUPPORT 0
#endif
#ifndef RTL8881A_SUPPORT
#define RTL8881A_SUPPORT 0
#endif
#ifndef RTL8822B_SUPPORT
#define RTL8822B_SUPPORT 0
#endif
#ifndef RTL8703B_SUPPORT
#define RTL8703B_SUPPORT 0
#endif
#ifndef RTL8195A_SUPPORT
#define RTL8195A_SUPPORT 0
#endif
#ifndef RTL8188F_SUPPORT
#define RTL8188F_SUPPORT 0
#endif
#ifndef RTL8723D_SUPPORT
#define RTL8723D_SUPPORT 0
#endif
#ifndef RTL8197F_SUPPORT
#define RTL8197F_SUPPORT 0
#endif
#ifndef RTL8821C_SUPPORT
#define RTL8821C_SUPPORT 0
#endif
#ifndef RTL8814B_SUPPORT
#define RTL8814B_SUPPORT 0
#endif
#ifndef RTL8198F_SUPPORT
#define RTL8198F_SUPPORT 0
#endif
#ifndef RTL8710B_SUPPORT
#define RTL8710B_SUPPORT 0
#endif
#ifndef RTL8192F_SUPPORT
#define RTL8192F_SUPPORT 0
#endif
#ifndef RTL8822C_SUPPORT
#define RTL8822C_SUPPORT 0
#endif
#ifndef RTL8195B_SUPPORT
#define RTL8195B_SUPPORT 0
#endif
#ifndef RTL8812F_SUPPORT
#define RTL8812F_SUPPORT 0
#endif
#ifndef RTL8197G_SUPPORT
#define RTL8197G_SUPPORT 0
#endif
#ifndef RTL8721D_SUPPORT
#define RTL8721D_SUPPORT 0
#endif
#ifndef RTL8710C_SUPPORT
#define RTL8710C_SUPPORT 0
#endif
#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && \
(!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))
@@ -107,6 +189,10 @@ rtw_phydm_fw_iqk(
u8 clear,
u8 segment);
enum hal_status
rtw_phydm_fw_dpk(
struct dm_struct *dm);
enum hal_status
rtw_phydm_cfg_phy_para(
struct dm_struct *dm,
@@ -119,11 +205,6 @@ rtw_phydm_cfg_phy_para(
#endif
/* @Judy ADD 20180125 */
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_IOT))
#define RTL8710B_SUPPORT 0
#endif
#if RTL8188E_SUPPORT == 1
#define RTL8188E_T_SUPPORT 1
#ifdef CONFIG_SFW_SUPPORTED
@@ -131,17 +212,7 @@ rtw_phydm_cfg_phy_para(
#else
#define RTL8188E_S_SUPPORT 0
#endif
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#define RTL8197F_SUPPORT 0 /*@Just for PHYDM API development*/
#define RTL8195B_SUPPORT 0 /*@Just for PHYDM API development*/
#define RTL8198F_SUPPORT 0 /*@Just for PHYDM API development*/
#define RTL8812F_SUPPORT 0 /*@Just for PHYDM API development*/
#define RTL8197G_SUPPORT 0 /*@Just for PHYDM API development*/
#endif
#if (RTL8188E_SUPPORT == 1)
#include "rtl8188e/hal8188erateadaptive.h" /* @for RA,Power training */
#include "rtl8188e/halhwimg8188e_mac.h"
#include "rtl8188e/halhwimg8188e_rf.h"
@@ -196,7 +267,6 @@ rtw_phydm_cfg_phy_para(
#include "halrf/rtl8812a/halrf_8812a_ce.h"
#endif
/* @#include "halrf/rtl8812a/halrf_8812a.h" */ /* @FOR_8812_IQK */
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#include "rtl8812a/halhwimg8812a_bb.h"
#include "rtl8812a/halhwimg8812a_mac.h"
@@ -215,10 +285,11 @@ rtw_phydm_cfg_phy_para(
#if (RTL8814A_SUPPORT == 1)
#include "rtl8814a/halhwimg8814a_mac.h"
#include "rtl8814a/halhwimg8814a_rf.h"
#include "rtl8814a/halhwimg8814a_bb.h"
#include "rtl8814a/version_rtl8814a.h"
#include "rtl8814a/phydm_rtl8814a.h"
#include "halrf/rtl8814a/halhwimg8814a_rf.h"
#include "halrf/rtl8814a/version_rtl8814a_rf.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "halrf/rtl8814a/halrf_8814a_win.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
@@ -241,10 +312,6 @@ rtw_phydm_cfg_phy_para(
#else
#include "halrf/rtl8821a/halrf_iqk_8821a_ap.h"
#endif
/* @#include "rtl8881a/HalHWImg8881A_BB.h" */
/* @#include "rtl8881a/HalHWImg8881A_MAC.h" */
/* @#include "rtl8881a/HalHWImg8881A_RF.h" */
/* @#include "rtl8881a/odm_RegConfig8881A.h" */
#endif
#if (RTL8723B_SUPPORT == 1)
@@ -293,10 +360,11 @@ rtw_phydm_cfg_phy_para(
#if (RTL8822B_SUPPORT == 1)
#include "rtl8822b/halhwimg8822b_mac.h"
#include "rtl8822b/halhwimg8822b_rf.h"
#include "rtl8822b/halhwimg8822b_bb.h"
#include "rtl8822b/phydm_regconfig8822b.h"
#include "halrf/rtl8822b/halrf_8822b.h"
#include "halrf/rtl8822b/halhwimg8822b_rf.h"
#include "halrf/rtl8822b/version_rtl8822b_rf.h"
#include "rtl8822b/phydm_rtl8822b.h"
#include "rtl8822b/phydm_hal_api8822b.h"
#include "rtl8822b/version_rtl8822b.h"
@@ -368,11 +436,12 @@ rtw_phydm_cfg_phy_para(
#include "rtl8710b/halhwimg8710b_bb.h"
#include "rtl8710b/halhwimg8710b_mac.h"
#include "rtl8710b/halhwimg8710b_rf.h"
#include "rtl8710b/phydm_regconfig8710b.h"
#include "rtl8710b/hal8710breg.h"
#include "rtl8710b/phydm_rtl8710b.h"
#include "halrf/rtl8710b/halrf_8710b.h"
#include "halrf/rtl8710b/halhwimg8710b_rf.h"
#include "halrf/rtl8710b/version_rtl8710b_rf.h"
#include "rtl8710b/version_rtl8710b.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
@@ -382,7 +451,6 @@ rtw_phydm_cfg_phy_para(
#if (RTL8197F_SUPPORT == 1)
#include "rtl8197f/halhwimg8197f_mac.h"
#include "rtl8197f/halhwimg8197f_rf.h"
#include "rtl8197f/halhwimg8197f_bb.h"
#include "rtl8197f/phydm_hal_api8197f.h"
#include "rtl8197f/version_rtl8197f.h"
@@ -391,15 +459,18 @@ rtw_phydm_cfg_phy_para(
#include "halrf/rtl8197f/halrf_8197f.h"
#include "halrf/rtl8197f/halrf_iqk_8197f.h"
#include "halrf/rtl8197f/halrf_dpk_8197f.h"
#include "halrf/rtl8197f/halhwimg8197f_rf.h"
#include "halrf/rtl8197f/version_rtl8197f_rf.h"
#endif
#if (RTL8821C_SUPPORT == 1)
#include "rtl8821c/phydm_hal_api8821c.h"
#include "rtl8821c/halhwimg8821c_mac.h"
#include "rtl8821c/halhwimg8821c_rf.h"
#include "rtl8821c/halhwimg8821c_bb.h"
#include "rtl8821c/phydm_regconfig8821c.h"
#include "halrf/rtl8821c/halrf_8821c.h"
#include "halrf/rtl8821c/halhwimg8821c_rf.h"
#include "halrf/rtl8821c/version_rtl8821c_rf.h"
#include "rtl8821c/version_rtl8821c.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#ifdef DM_ODM_CE_MAC80211
@@ -415,24 +486,29 @@ rtw_phydm_cfg_phy_para(
#include "rtl8192f_hal.h"/*need to before rf.h*/
#endif
#include "rtl8192f/halhwimg8192f_mac.h"
#include "rtl8192f/halhwimg8192f_rf.h"
#include "rtl8192f/halhwimg8192f_bb.h"
#include "rtl8192f/phydm_hal_api8192f.h"
#include "rtl8192f/version_rtl8192f.h"
#include "rtl8192f/phydm_rtl8192f.h"
#include "rtl8192f/phydm_regconfig8192f.h"
#include "halrf/rtl8192f/halrf_8192f.h"
#include "halrf/rtl8192f/halhwimg8192f_rf.h"
#include "halrf/rtl8192f/version_rtl8192f_rf.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "halrf/rtl8192f/halrf_dpk_8192f.h"
#endif
#endif
#if (RTL8721D_SUPPORT == 1)
#include "halrf/rtl8721d/halrf_btiqk_8721d.h"
#include "halrf/rtl8721d/halrf_rfk_init_8721d.h"
#include "halrf/rtl8721d/halrf_dpk_8721d.h"
#include "halrf/rtl8721d/halrf_8721d.h"
#include "halrf/rtl8721d/halhwimg8721d_rf.h"
#include "halrf/rtl8721d/version_rtl8721d_rf.h"
#include "rtl8721d/phydm_hal_api8721d.h"
#include "rtl8721d/phydm_regconfig8721d.h"
#include "rtl8721d/halhwimg8721d_mac.h"
#include "rtl8721d/halhwimg8721d_rf.h"
#include "rtl8721d/halhwimg8721d_bb.h"
#include "rtl8721d/version_rtl8721d.h"
#include "rtl8721d/phydm_rtl8721d.h"
@@ -440,19 +516,42 @@ rtw_phydm_cfg_phy_para(
#include <hal_data.h>
#if 0
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "halrf/rtl8721d/halrf_dpk_8721d.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8721d_hal.h"
#endif
#endif
#endif
#if (RTL8710C_SUPPORT == 1)
#include "halrf/rtl8710c/halrf_8710c.h"
#include "halrf/rtl8710c/halhwimg8710c_rf.h"
//#include "halrf/rtl8710c/version_rtl8710c_rf.h"
#include "rtl8710c/phydm_hal_api8710c.h"
#include "rtl8710c/phydm_regconfig8710c.h"
#include "rtl8710c/halhwimg8710c_mac.h"
#include "rtl8710c/halhwimg8710c_bb.h"
#include "rtl8710c/version_rtl8710c.h"
#include "rtl8710c/phydm_rtl8710c.h"
//#include "rtl8710c/hal87100creg.h"
#include <hal_data.h> /*@HAL_DATA_TYPE*/
#if 0
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "halrf/rtl8710c/halrf_dpk_8710c.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8710c_hal.h"
#endif
#endif
#endif
#if (RTL8195B_SUPPORT == 1)
#include "halrf/rtl8195b/halrf_8195b.h"
#include "halrf/rtl8195b/halhwimg8195b_rf.h"
#include "halrf/rtl8195b/version_rtl8195b_rf.h"
#include "rtl8195b/phydm_hal_api8195b.h"
#include "rtl8195b/phydm_regconfig8195b.h"
#include "rtl8195b/halhwimg8195b_mac.h"
#include "rtl8195b/halhwimg8195b_rf.h"
#include "rtl8195b/halhwimg8195b_bb.h"
#include "rtl8195b/version_rtl8195b.h"
#include <hal_data.h> /*@HAL_DATA_TYPE*/
@@ -462,21 +561,23 @@ rtw_phydm_cfg_phy_para(
#include "rtl8198f/phydm_regconfig8198f.h"
#include "rtl8198f/phydm_hal_api8198f.h"
#include "rtl8198f/halhwimg8198f_mac.h"
#include "rtl8198f/halhwimg8198f_rf.h"
#include "rtl8198f/halhwimg8198f_bb.h"
#include "rtl8198f/version_rtl8198f.h"
#include "halrf/rtl8198f/halrf_8198f.h"
#include "halrf/rtl8198f/halrf_iqk_8198f.h"
#include "halrf/rtl8198f/halhwimg8198f_rf.h"
#include "halrf/rtl8198f/version_rtl8198f_rf.h"
#endif
#if (RTL8822C_SUPPORT)
#include "rtl8822c/halhwimg8822c_mac.h"
#include "rtl8822c/halhwimg8822c_rf.h"
#include "rtl8822c/halhwimg8822c_bb.h"
#include "rtl8822c/phydm_regconfig8822c.h"
#include "halrf/rtl8822c/halrf_8822c.h"
#include "rtl8822c/phydm_hal_api8822c.h"
#include "rtl8822c/version_rtl8822c.h"
#include "rtl8822c/phydm_rtl8822c.h"
#include "halrf/rtl8822c/halrf_8822c.h"
#include "halrf/rtl8822c/halhwimg8822c_rf.h"
#include "halrf/rtl8822c/version_rtl8822c_rf.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
/* @struct HAL_DATA_TYPE */
#include <hal_data.h>
@@ -485,29 +586,34 @@ rtw_phydm_cfg_phy_para(
#endif
#endif
#if (RTL8814B_SUPPORT == 1)
#include "rtl8814b/halhwimg8814b_mac.h"
#include "rtl8814b/halhwimg8814b_rf.h"
#include "rtl8814b/halhwimg8814b_bb.h"
#include "rtl8814b/phydm_regconfig8814b.h"
#include "halrf/rtl8814b/halrf_8814b.h"
#include "halrf/rtl8814b/halhwimg8814b_rf.h"
#include "halrf/rtl8814b/version_rtl8814b_rf.h"
#include "rtl8814b/phydm_hal_api8814b.h"
#include "rtl8814b/version_rtl8814b.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include <hal_data.h> /* @struct HAL_DATA_TYPE */
#include <rtl8814b_hal.h> /* @RX_SMOOTH_FACTOR, reg definition and etc.*/
#endif
#endif
#if (RTL8812F_SUPPORT)
#include "rtl8812f/halhwimg8812f_mac.h"
#include "rtl8812f/halhwimg8812f_rf.h"
#include "rtl8812f/halhwimg8812f_bb.h"
#include "rtl8812f/phydm_regconfig8812f.h"
#include "halrf/rtl8812f/halrf_8812f.h"
#include "halrf/rtl8812f/halhwimg8812f_rf.h"
#include "halrf/rtl8812f/version_rtl8812f_rf.h"
#include "rtl8812f/phydm_hal_api8812f.h"
#include "rtl8812f/version_rtl8812f.h"
#endif
#if (RTL8197G_SUPPORT)
#include "rtl8197g/halhwimg8197g_mac.h"
#include "rtl8197g/halhwimg8197g_rf.h"
#include "rtl8197g/halhwimg8197g_bb.h"
#include "rtl8197g/halhwimg8197g_mac.h"
#include "rtl8197g/phydm_regconfig8197g.h"
#include "halrf/rtl8197g/halrf_8197g.h"
#include "halrf/rtl8197g/halhwimg8197g_rf.h"
#include "halrf/rtl8197g/version_rtl8197g_rf.h"
#include "rtl8197g/phydm_hal_api8197g.h"
#include "rtl8197g/version_rtl8197g.h"
#endif

31
hal/phydm/phydm_psd.c
View File

@@ -42,30 +42,29 @@ u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi)
psd_tone_idx >> 10);
/*PSD trigger start*/
odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 1);
ODM_delay_us(10);
ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
/*PSD trigger stop*/
odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 0);
} else if (dm->support_ic_type == ODM_RTL8721D) {
} else if (dm->support_ic_type & (ODM_RTL8721D |
ODM_RTL8710C)) {
odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0xfff, psd_tone_idx);
odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(28), 1);
/*PSD trigger start*/
ODM_delay_us(10);
ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(28), 0);
/*PSD trigger stop*/
psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
0xffffff);
psd_report = psd_report >> 5;
} else {
odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff, psd_tone_idx);
/*PSD trigger start*/
odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 1);
ODM_delay_us(10);
ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
/*PSD trigger stop*/
odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 0);
}
if (dm->support_ic_type & ODM_RTL8821C) {
/*Get PSD Report*/
if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
ODM_RTL8710C)) {
psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
0xffffff);
psd_report = psd_report >> 5;
@@ -139,7 +138,8 @@ u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)
if (psd_fc_channel > 14) {
is_5G = 1;
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) {
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
ODM_RTL8197G)) {
if (psd_fc_channel < 80)
ag_rf_mode_reg = 0x1;
else if (psd_fc_channel >= 80 && psd_fc_channel <= 140)
@@ -168,7 +168,8 @@ u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)
odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xff, psd_fc_channel);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x300, is_5G);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x300, is_5G);
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) {
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
ODM_RTL8197G)) {
/* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x3000,
dm_psd_table->psd_bw_rf_reg);
@@ -184,6 +185,12 @@ u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)
if (dm->support_ic_type == ODM_RTL8721D) {
odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x1c00,
dm_psd_table->psd_bw_rf_reg);
#if (RTL8710C_SUPPORT == 1)
} else if (dm->support_ic_type == ODM_RTL8710C) {
config_phydm_write_rf_reg_8710c(dm, RF_PATH_A,
RF_0x18, 0x1c00,
dm_psd_table->psd_bw_rf_reg);
#endif
} else {
odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xc00,
dm_psd_table->psd_bw_rf_reg);
@@ -328,7 +335,7 @@ void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,
fft_smp_point_idx);
odm_set_bb_reg(dm, R_0x910, BIT(17) | BIT(16), ant_sel);
odm_set_bb_reg(dm, R_0x910, BIT(23), psd_input);
} else if (dm->support_ic_type == ODM_RTL8721D) {
} else if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
odm_set_bb_reg(dm, 0x808, BIT(19) | BIT(18), i_q_setting);
odm_set_bb_reg(dm, 0x808, BIT(21) | BIT(20), hw_avg_time);
odm_set_bb_reg(dm, 0x808, BIT(23) | BIT(22), fft_smp_point_idx);

251
hal/phydm/phydm_rainfo.c
View File

@@ -204,6 +204,8 @@ void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
"{1} {100}: show offset\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"{2} {en} {macid} {bw} {rate}: fw fix rate\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"{3} {en}: Dynamic RRSR\n");
} else if (var[0] == 1) { /*@Adjust PCR offset*/
@@ -235,7 +237,10 @@ void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
var[1], macid, bw, rate);
phydm_fw_fix_rate(dm, (u8)var[1], macid, bw, rate);
} else if (var[0] == 3) { /*@FW fix rate*/
ra_tab->dynamic_rrsr_en = (boolean)var[1];
PDM_SNPF(out_len, used, output + used, out_len - used,
"[Dynamic RRSR] enable=%d", ra_tab->dynamic_rrsr_en);
} else {
PDM_SNPF(out_len, used, output + used, out_len - used,
"[Set] Error\n");
@@ -447,13 +452,12 @@ void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
phydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE);
PHYDM_DBG(dm, DBG_RA, "Tx Rate=%s (%d)", dbg_buf, rate);
if (macid >= 128) {
#ifdef MU_EX_MACID
if (macid >= 128 && macid < (128 + MU_EX_MACID)) {
gid_index = macid - 128;
ra_tab->mu1_rate[gid_index] = rate;
}
/*@ra_tab->link_tx_rate[macid] = rate;*/
#endif
if (is_sta_active(sta)) {
sta->ra_info.curr_tx_rate = rate;
sta->ra_info.curr_tx_bw = (enum channel_width)curr_bw;
@@ -812,6 +816,25 @@ void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used,
*_out_len = out_len;
}
u8 phydm_get_rx_stream_num(void *dm_void, enum rf_type type)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 rx_num = 1;
if (type == RF_1T1R)
rx_num = 1;
else if (type == RF_2T2R || type == RF_1T2R)
rx_num = 2;
else if (type == RF_3T3R || type == RF_2T3R)
rx_num = 3;
else if (type == RF_4T4R || type == RF_3T4R || type == RF_2T4R)
rx_num = 4;
else
pr_debug("[Warrning] %s\n", __func__);
return rx_num;
}
u8 phydm_get_tx_stream_num(void *dm_void, enum rf_type type)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
@@ -939,6 +962,9 @@ u64 phydm_get_bb_mod_ra_mask(void *dm_void, u8 sta_idx)
} else if (bw == CHANNEL_WIDTH_80) {
/* @AC 80MHz doesn't support 3SS MCS6*/
ra_mask_bitmap &= 0x000fffbffffff010;
} else if (bw == CHANNEL_WIDTH_160) {
/* @AC 80M+80M doesn't support 3SS & 4SS*/
ra_mask_bitmap &= 0xfffff010;
}
} else {
PHYDM_DBG(dm, DBG_RA, "[Warrning] RA mask is Not found\n");
@@ -1070,14 +1096,25 @@ u8 phydm_get_rate_id(void *dm_void, u8 sta_idx)
}
} else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) {
/*@AC mode*/
if (tx_stream_num == 1)
rate_id_idx = PHYDM_ARFR1_AC_1SS;
else if (tx_stream_num == 2)
rate_id_idx = PHYDM_ARFR0_AC_2SS;
else if (tx_stream_num == 3)
rate_id_idx = PHYDM_ARFR4_AC_3SS;
else if (tx_stream_num == 4)
rate_id_idx = PHYDM_ARFR6_AC_4SS;
if (bw == CHANNEL_WIDTH_160) {
if (tx_stream_num == 1)
rate_id_idx = PHYDM_ARFR1_AC_1SS;
else if (tx_stream_num == 2)
rate_id_idx = PHYDM_ARFR0_AC_2SS;
else if (tx_stream_num == 3)
rate_id_idx = PHYDM_ARFR0_AC_2SS;
else if (tx_stream_num == 4)
rate_id_idx = PHYDM_ARFR0_AC_2SS;
} else {
if (tx_stream_num == 1)
rate_id_idx = PHYDM_ARFR1_AC_1SS;
else if (tx_stream_num == 2)
rate_id_idx = PHYDM_ARFR0_AC_2SS;
else if (tx_stream_num == 3)
rate_id_idx = PHYDM_ARFR4_AC_3SS;
else if (tx_stream_num == 4)
rate_id_idx = PHYDM_ARFR6_AC_4SS;
}
} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) {
/*@AC 2.4G mode*/
if (bw >= CHANNEL_WIDTH_80) {
@@ -1268,6 +1305,7 @@ void phydm_ra_mask_watchdog(void *dm_void)
struct ra_table *ra_t = &dm->dm_ra_table;
struct cmn_sta_info *sta = NULL;
struct ra_sta_info *ra = NULL;
boolean force_ra_mask_en = false;
u8 sta_idx;
u64 ra_mask;
u8 rssi_lv_new;
@@ -1283,6 +1321,11 @@ void phydm_ra_mask_watchdog(void *dm_void)
ra_t->up_ramask_cnt++;
if (ra_t->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD) {
ra_t->up_ramask_cnt = 0;
force_ra_mask_en = true;
}
for (sta_idx = 0; sta_idx < ODM_ASSOCIATE_ENTRY_NUM; sta_idx++) {
sta = dm->phydm_sta_info[sta_idx];
@@ -1310,7 +1353,7 @@ void phydm_ra_mask_watchdog(void *dm_void)
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
set_ra_ldpc_8812(sta, true);
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
MgntSet_TX_LDPC(sta->mac_id, true);
MgntSet_TX_LDPC(dm->adapter, sta->mac_id, true);
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
/*to be added*/
#endif
@@ -1322,7 +1365,7 @@ void phydm_ra_mask_watchdog(void *dm_void)
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
set_ra_ldpc_8812(sta, false);
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
MgntSet_TX_LDPC(sta->mac_id, false);
MgntSet_TX_LDPC(dm->adapter, sta->mac_id, false);
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
/*to be added*/
#endif
@@ -1335,12 +1378,11 @@ void phydm_ra_mask_watchdog(void *dm_void)
rssi_lv_new = phydm_rssi_lv_dec(dm, (u32)rssi, ra->rssi_level);
if (ra->rssi_level != rssi_lv_new ||
ra_t->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD) {
(force_ra_mask_en && dm->number_linked_client < 10)) {
PHYDM_DBG(dm, DBG_RA_MASK, "RSSI LV:((%d))->((%d))\n",
ra->rssi_level, rssi_lv_new);
ra->rssi_level = rssi_lv_new;
ra_t->up_ramask_cnt = 0;
ra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx);
@@ -1542,25 +1584,82 @@ u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state)
return new_rssi_lv;
}
enum phydm_qam_order phydm_get_ofdm_qam_order(void *dm_void, u8 rate_idx)
{
u8 tmp_idx = rate_idx;
enum phydm_qam_order qam_order = PHYDM_QAM_BPSK;
enum phydm_qam_order qam[10] = {PHYDM_QAM_BPSK, PHYDM_QAM_QPSK,
PHYDM_QAM_QPSK, PHYDM_QAM_16QAM,
PHYDM_QAM_16QAM, PHYDM_QAM_64QAM,
PHYDM_QAM_64QAM, PHYDM_QAM_64QAM,
PHYDM_QAM_256QAM, PHYDM_QAM_256QAM};
if (rate_idx <= ODM_RATE11M)
return PHYDM_QAM_CCK;
if (rate_idx >= ODM_RATEVHTSS1MCS0) {
if (rate_idx >= ODM_RATEVHTSS4MCS0)
tmp_idx -= ODM_RATEVHTSS4MCS0;
else if (rate_idx >= ODM_RATEVHTSS3MCS0)
tmp_idx -= ODM_RATEVHTSS3MCS0;
else if (rate_idx >= ODM_RATEVHTSS2MCS0)
tmp_idx -= ODM_RATEVHTSS2MCS0;
else
tmp_idx -= ODM_RATEVHTSS1MCS0;
qam_order = qam[tmp_idx];
} else if (rate_idx >= ODM_RATEMCS0) {
if (rate_idx >= ODM_RATEMCS24)
tmp_idx -= ODM_RATEMCS24;
else if (rate_idx >= ODM_RATEMCS16)
tmp_idx -= ODM_RATEMCS16;
else if (rate_idx >= ODM_RATEMCS8)
tmp_idx -= ODM_RATEMCS8;
else
tmp_idx -= ODM_RATEMCS0;
qam_order = qam[tmp_idx];
} else {
if (rate_idx > ODM_RATE6M) {
tmp_idx -= ODM_RATE6M;
qam_order = qam[tmp_idx - 1];
} else {
qam_order = PHYDM_QAM_BPSK;
}
}
return qam_order;
}
u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx)
{
u8 rate_order = 0;
u8 rate_order = rate_idx & 0x7f;
rate_idx &= 0x7f;
if (rate_idx >= ODM_RATEVHTSS4MCS0)
rate_idx -= ODM_RATEVHTSS4MCS0;
rate_order -= ODM_RATEVHTSS4MCS0;
else if (rate_idx >= ODM_RATEVHTSS3MCS0)
rate_idx -= ODM_RATEVHTSS3MCS0;
rate_order -= ODM_RATEVHTSS3MCS0;
else if (rate_idx >= ODM_RATEVHTSS2MCS0)
rate_idx -= ODM_RATEVHTSS2MCS0;
rate_order -= ODM_RATEVHTSS2MCS0;
else if (rate_idx >= ODM_RATEVHTSS1MCS0)
rate_idx -= ODM_RATEVHTSS1MCS0;
rate_order -= ODM_RATEVHTSS1MCS0;
else if (rate_idx >= ODM_RATEMCS24)
rate_idx -= ODM_RATEMCS24;
rate_order -= ODM_RATEMCS24;
else if (rate_idx >= ODM_RATEMCS16)
rate_idx -= ODM_RATEMCS16;
rate_order -= ODM_RATEMCS16;
else if (rate_idx >= ODM_RATEMCS8)
rate_idx -= ODM_RATEMCS8;
rate_order = rate_idx;
rate_order -= ODM_RATEMCS8;
else if (rate_idx >= ODM_RATEMCS0)
rate_order -= ODM_RATEMCS0;
else if (rate_idx >= ODM_RATE6M)
rate_order -= ODM_RATE6M;
else
rate_order -= ODM_RATE1M;
if (rate_idx >= ODM_RATEMCS0)
rate_order++;
return rate_order;
}
@@ -1676,12 +1775,94 @@ void phydm_ra_common_info_update(void *dm_void)
ra_tab->highest_client_tx_order);
}
void phydm_rrsr_set_register(void *dm_void, u32 rrsr_val)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
odm_set_mac_reg(dm, R_0x440, 0xfffff, rrsr_val);
}
void phydm_masked_rrsr_set_register(void *dm_void, u32 rrsr_val)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct ra_table *ra_tab = &dm->dm_ra_table;
if (ra_tab->rrsr_val_curr == rrsr_val)
return;
ra_tab->rrsr_val_curr = rrsr_val;
odm_set_mac_reg(dm, R_0x440, 0xfffff, rrsr_val);
}
void phydm_rrsr_mask(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct ra_table *ra = &dm->dm_ra_table;
struct cmn_sta_info *sta = NULL;
u8 rate_order = 0;
u8 rate_order_min = 0xff;
u32 rrsr_mask = 0, rrsr_mask_ofdm = 0;
u8 tx_rate_idx = 0;
u8 i = 0, sta_cnt = 0;
if (!ra->dynamic_rrsr_en)
return;
if (!dm->is_linked) {
phydm_masked_rrsr_set_register(dm, ra->rrsr_val_init);
return;
}
#if 1
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
sta = dm->phydm_sta_info[i];
if (!is_sta_active(sta))
continue;
sta_cnt++;
tx_rate_idx = sta->ra_info.curr_tx_rate & 0x7f;
rate_order = phydm_rate_order_compute(dm, tx_rate_idx);
if (rate_order < rate_order_min)
rate_order_min = rate_order;
if (sta_cnt == dm->number_linked_client)
break;
}
#else
sta = dm->phydm_sta_info[dm->rssi_min_macid];
if (!is_sta_active(sta)) {
PHYDM_DBG(dm, DBG_DYN_ARFR, "[Warning] %s invalid STA\n",
__func__);
return;
}
rate_order = phydm_rate_order_compute(dm, sta->ra_info.curr_tx_rate);
#endif
if (rate_order_min == 0) {
rrsr_mask = 0x1f;
} else {
rrsr_mask_ofdm = (u32)phydm_gen_bitmask(rate_order_min);
rrsr_mask = (rrsr_mask_ofdm << 4) | 0xf;
}
/*ra->rrsr_val_init = 0x15d;*/
phydm_masked_rrsr_set_register(dm, ra->rrsr_val_init & rrsr_mask);
PHYDM_DBG(dm, DBG_DYN_ARFR,
"tx{rate, rate_order_min}={0x%x, %d}, rrsr_init=0x%x, ofdm_rrsr_mask=0x%x, rrsr_val=0x%x\n",
tx_rate_idx, rate_order_min, ra->rrsr_val_init,
rrsr_mask, ra->rrsr_val_curr);
}
void phydm_ra_info_watchdog(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
phydm_ra_common_info_update(dm);
phydm_ra_dynamic_retry_count(dm);
phydm_rrsr_mask(dm);
phydm_ra_mask_watchdog(dm);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
@@ -1689,6 +1870,14 @@ void phydm_ra_info_watchdog(void *dm_void)
#endif
}
void phydm_rrsr_en(void *dm_void, boolean en_rrsr)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct ra_table *ra_tab = &dm->dm_ra_table;
ra_tab->dynamic_rrsr_en = en_rrsr;
}
void phydm_ra_info_init(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
@@ -1698,6 +1887,8 @@ void phydm_ra_info_init(void *dm_void)
ra_tab->highest_client_tx_order = 0;
ra_tab->ra_th_ofst = 0;
ra_tab->ra_ofst_direc = 0;
ra_tab->rrsr_val_init = odm_get_mac_reg(dm, R_0x440, MASKDWORD);
ra_tab->dynamic_rrsr_en = true;
#if (RTL8822B_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8822B) {
@@ -1914,11 +2105,11 @@ void phydm_reset_retry_limit_table(
};
memcpy(&ra_t->per_rate_retrylimit_20M[0],
&per_rate_retrylimit_table_20M[0], ODM_NUM_RATE_IDX);
&per_rate_retrylimit_table_20M[0], PHY_NUM_RATE_IDX);
memcpy(&ra_t->per_rate_retrylimit_40M[0],
&per_rate_retrylimit_table_40M[0], ODM_NUM_RATE_IDX);
&per_rate_retrylimit_table_40M[0], PHY_NUM_RATE_IDX);
for (i = 0; i < ODM_NUM_RATE_IDX; i++) {
for (i = 0; i < PHY_NUM_RATE_IDX; i++) {
phydm_retry_limit_table_bound(dm,
&ra_t->per_rate_retrylimit_20M[i],
0);
@@ -1962,7 +2153,7 @@ void phydm_ra_dynamic_retry_limit(
} else {
retry_offset = dm->number_active_client * ra_tab->retry_descend_num;
for (i = 0; i < ODM_NUM_RATE_IDX; i++) {
for (i = 0; i < PHY_NUM_RATE_IDX; i++) {
phydm_retry_limit_table_bound(dm,
&ra_tab->per_rate_retrylimit_20M[i],
retry_offset);

34
hal/phydm/phydm_rainfo.h
View File

@@ -26,7 +26,8 @@
#ifndef __PHYDMRAINFO_H__
#define __PHYDMRAINFO_H__
#define RAINFO_VERSION "8.0"
/* 2019.3.5 add dynamic RRSR en API*/
#define RAINFO_VERSION "8.2"
#define FORCED_UPDATE_RAMASK_PERIOD 5
@@ -106,6 +107,15 @@ enum phydm_rateid_idx {
PHYDM_ARFR6_AC_4SS = 16
};
enum phydm_qam_order {
PHYDM_QAM_CCK = 0,
PHYDM_QAM_BPSK = 1,
PHYDM_QAM_QPSK = 2,
PHYDM_QAM_16QAM = 3,
PHYDM_QAM_64QAM = 4,
PHYDM_QAM_256QAM = 5
};
#if (RATE_ADAPTIVE_SUPPORT == 1)/* @88E RA */
struct _phydm_txstatistic_ {
@@ -166,9 +176,9 @@ struct _odm_ra_info_ {
struct ra_table {
u8 firstconnect;
/*@u8 link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];*/
u8 mu1_rate[30];
#ifdef MU_EX_MACID
u8 mu1_rate[MU_EX_MACID];
#endif
u8 highest_client_tx_order;
u16 highest_client_tx_rate_order;
u8 power_tracking_flag;
@@ -176,9 +186,12 @@ struct ra_table {
u8 ra_ofst_direc; /*RA_offset_direction*/
u8 up_ramask_cnt; /*@force update_ra_mask counter*/
u8 up_ramask_cnt_tmp; /*@Just for debug, should be removed latter*/
u32 rrsr_val_init; /*0x440*/
u32 rrsr_val_curr; /*0x440*/
boolean dynamic_rrsr_en;
#if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
u8 per_rate_retrylimit_20M[ODM_NUM_RATE_IDX];
u8 per_rate_retrylimit_40M[ODM_NUM_RATE_IDX];
u8 per_rate_retrylimit_20M[PHY_NUM_RATE_IDX];
u8 per_rate_retrylimit_40M[PHY_NUM_RATE_IDX];
u8 retry_descend_num;
u8 retrylimit_low;
u8 retrylimit_high;
@@ -212,9 +225,6 @@ void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
void phydm_ra_dynamic_retry_count(void *dm_void);
void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component);
void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size);
@@ -223,8 +233,12 @@ void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx);
void phydm_rrsr_set_register(void *dm_void, u32 rrsr_val);
void phydm_ra_info_watchdog(void *dm_void);
void phydm_rrsr_en(void *dm_void, boolean en_rrsr);
void phydm_ra_info_init(void *dm_void);
void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc,
@@ -252,6 +266,8 @@ u8 phydm_get_plcp(void *dm_void, u16 macid);
void phydm_refresh_rate_adaptive_mask(void *dm_void);
u8 phydm_get_rx_stream_num(void *dm_void, enum rf_type type);
u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state);
void odm_ra_post_action_on_assoc(void *dm);

6
hal/phydm/phydm_reg.h
View File

@@ -211,7 +211,9 @@
#define is_tx_agc_byte1_jaguar 0xff00
#define is_tx_agc_byte2_jaguar 0xff0000
#define is_tx_agc_byte3_jaguar 0xff000000
#if defined(CONFIG_WLAN_HAL_8198F) || defined(CONFIG_WLAN_HAL_8822CE)
#if defined(CONFIG_WLAN_HAL_8198F) || defined(CONFIG_WLAN_HAL_8822CE) ||\
defined(CONFIG_WLAN_HAL_8814BE) || defined(CONFIG_WLAN_HAL_8812FE) ||\
defined(CONFIG_WLAN_HAL_8197G)
#define REG_TX_AGC_CCK_11_CCK_1_JAGUAR3 0x3a00
#define REG_TX_AGC_OFDM_18_CCK_6_JAGUAR3 0x3a04
#define REG_TX_AGC_OFDM_54_CCK_24_JAGUAR3 0x3a08
@@ -233,7 +235,7 @@
#define REG_TX_AGC_VHT_Nss4_MCS1_Nss3_MCS8_JAGUAR3 0x3a48
#define REG_TX_AGC_VHT_Nss4_MCS5_2_JAGUAR3 0x3a4c
#define REG_TX_AGC_VHT_Nss4_MCS9_6_JAGUAR3 0x3a50
#endif
#endif
#endif
#define BIT_FA_RESET BIT(0)

1
hal/phydm/phydm_regdefine11n.h
View File

@@ -39,6 +39,7 @@
#define ODM_REG_RXRF_A3_11N 0x3C
#define ODM_REG_T_METER_92D_11N 0x42
#define ODM_REG_T_METER_88E_11N 0x42
#define ODM_REF_RF_DF_11N 0xDF

101
hal/phydm/phydm_regtable.h
View File

@@ -12,6 +12,7 @@
#define R_0x1040 0x1040
#define R_0x1048 0x1048
#define R_0x1080 0x1080
#define R_0x14 0x14
#define R_0x14c0 0x14c0
#define R_0x14c4 0x14c4
#define R_0x14c8 0x14c8
@@ -23,7 +24,13 @@
#define R_0x1700 0x1700
#define R_0x1704 0x1704
#define R_0x1800 0x1800
#define R_0x1804 0x1804
#define R_0x1808 0x1808
#define R_0x180c 0x180c
#define R_0x1810 0x1810
#define R_0x1814 0x1814
#define R_0x1818 0x1818
#define R_0x181c 0x181c
#define R_0x1830 0x1830
#define R_0x1834 0x1834
#define R_0x1838 0x1838
@@ -33,8 +40,10 @@
#define R_0x1848 0x1848
#define R_0x1860 0x1860
#define R_0x1864 0x1864
#define R_0x1868 0x1868
#define R_0x186c 0x186c
#define R_0x1870 0x1870
#define R_0x1880 0x1880
#define R_0x1884 0x1884
#define R_0x188c 0x188c
#define R_0x1894 0x1894
@@ -52,6 +61,7 @@
#define R_0x1900 0x1900
#define R_0x1904 0x1904
#define R_0x1908 0x1908
#define R_0x1910 0x1910
#define R_0x1918 0x1918
#define R_0x191c 0x191c
#define R_0x1928 0x1928
@@ -68,6 +78,7 @@
#define R_0x1991 0x1991
#define R_0x1998 0x1998
#define R_0x19a8 0x19a8
#define R_0x19b8 0x19b8
#define R_0x19d4 0x19d4
#define R_0x19d8 0x19d8
#define R_0x19e0 0x19e0
@@ -75,6 +86,7 @@
#define R_0x19f8 0x19f8
#define R_0x1a00 0x1a00
#define R_0x1a04 0x1a04
#define R_0x1a10 0x1a10
#define R_0x1a14 0x1a14
#define R_0x1a20 0x1a20
#define R_0x1a24 0x1a24
@@ -82,6 +94,7 @@
#define R_0x1a2c 0x1a2c
#define R_0x1a5c 0x1a5c
#define R_0x1a70 0x1a70
#define R_0x1a74 0x1a74
#define R_0x1a80 0x1a80
#define R_0x1a84 0x1a84
#define R_0x1a8c 0x1a8c
@@ -89,6 +102,7 @@
#define R_0x1a98 0x1a98
#define R_0x1a9c 0x1a9c
#define R_0x1aa0 0x1aa0
#define R_0x1aa8 0x1aa8
#define R_0x1aac 0x1aac
#define R_0x1ab0 0x1ab0
#define R_0x1abc 0x1abc
@@ -97,12 +111,22 @@
#define R_0x1acc 0x1acc
#define R_0x1ad0 0x1ad0
#define R_0x1ad4 0x1ad4
#define R_0x1ae8 0x1ae8
#define R_0x1aec 0x1aec
#define R_0x1b00 0x1b00
#define R_0x1b04 0x1b04
#define R_0x1b08 0x1b08
#define R_0x1b0c 0x1b0c
#define R_0x1b10 0x1b10
#define R_0x1b14 0x1b14
#define R_0x1b18 0x1b18
#define R_0x1b1c 0x1b1c
#define R_0x1b20 0x1b20
#define R_0x1b23 0x1b23
#define R_0x1b24 0x1b24
#define R_0x1b28 0x1b28
#define R_0x1b2c 0x1b2c
#define R_0x1b30 0x1b30
#define R_0x1b34 0x1b34
#define R_0x1b38 0x1b38
#define R_0x1b3c 0x1b3c
@@ -124,10 +148,14 @@
#define R_0x1b78 0x1b78
#define R_0x1b7c 0x1b7c
#define R_0x1b80 0x1b80
#define R_0x1b83 0x1b83
#define R_0x1b84 0x1b84
#define R_0x1b88 0x1b88
#define R_0x1b8c 0x1b8c
#define R_0x1b90 0x1b90
#define R_0x1b92 0x1b92
#define R_0x1b94 0x1b94
#define R_0x1b97 0x1b97
#define R_0x1b98 0x1b98
#define R_0x1b9c 0x1b9c
#define R_0x1ba0 0x1ba0
@@ -138,19 +166,33 @@
#define R_0x1bb4 0x1bb4
#define R_0x1bb8 0x1bb8
#define R_0x1bbc 0x1bbc
#define R_0x1bc0 0x1bc0
#define R_0x1bc8 0x1bc8
#define R_0x1bca 0x1bca
#define R_0x1bcb 0x1bcb
#define R_0x1bcc 0x1bcc
#define R_0x1bce 0x1bce
#define R_0x1bd0 0x1bd0
#define R_0x1bd4 0x1bd4
#define R_0x1bd6 0x1bd6
#define R_0x1bd8 0x1bd8
#define R_0x1bdc 0x1bdc
#define R_0x1be4 0x1be4
#define R_0x1be8 0x1be8
#define R_0x1beb 0x1beb
#define R_0x1bec 0x1bec
#define R_0x1bef 0x1bef
#define R_0x1bf0 0x1bf0
#define R_0x1bf4 0x1bf4
#define R_0x1bf8 0x1bf8
#define R_0x1bfc 0x1bfc
#define R_0x1c 0x1c
#define R_0x1c20 0x1c20
#define R_0x1c24 0x1c24
#define R_0x1c28 0x1c28
#define R_0x1c2c 0x1c2c
#define R_0x1c30 0x1c30
#define R_0x1c34 0x1c34
#define R_0x1c38 0x1c38
#define R_0x1c3c 0x1c3c
#define R_0x1c64 0x1c64
@@ -165,7 +207,9 @@
#define R_0x1c9c 0x1c9c
#define R_0x1ca0 0x1ca0
#define R_0x1ca4 0x1ca4
#define R_0x1cb0 0x1cb0
#define R_0x1cb8 0x1cb8
#define R_0x1cc0 0x1cc0
#define R_0x1cd0 0x1cd0
#define R_0x1ce4 0x1ce4
#define R_0x1ce8 0x1ce8
@@ -179,20 +223,26 @@
#define R_0x1d10 0x1d10
#define R_0x1d2c 0x1d2c
#define R_0x1d30 0x1d30
#define R_0x1d3c 0x1d3c
#define R_0x1d44 0x1d44
#define R_0x1d48 0x1d48
#define R_0x1d58 0x1d58
#define R_0x1d60 0x1d60
#define R_0x1d6c 0x1d6c
#define R_0x1d70 0x1d70
#define R_0x1d90 0x1d90
#define R_0x1d94 0x1d94
#define R_0x1d9c 0x1d9c
#define R_0x1da4 0x1da4
#define R_0x1da8 0x1da8
#define R_0x1de8 0x1de8
#define R_0x1e14 0x1e14
#define R_0x1e18 0x1e18
#define R_0x1e1c 0x1e1c
#define R_0x1e24 0x1e24
#define R_0x1e28 0x1e28
#define R_0x1e2c 0x1e2c
#define R_0x1e28 0x1e28
#define R_0x1e30 0x1e30
#define R_0x1e40 0x1e40
#define R_0x1e44 0x1e44
@@ -204,6 +254,7 @@
#define R_0x1e6c 0x1e6c
#define R_0x1e70 0x1e70
#define R_0x1e7c 0x1e7c
#define R_0x1e84 0x1e84
#define R_0x1e88 0x1e88
#define R_0x1e8c 0x1e8c
#define R_0x1ea4 0x1ea4
@@ -211,9 +262,12 @@
#define R_0x1ee8 0x1ee8
#define R_0x1eec 0x1eec
#define R_0x1ef0 0x1ef0
#define R_0x1ef4 0x1ef4
#define R_0x1efc 0x1efc
#define R_0x24 0x24
#define R_0x28 0x28
#define R_0x2c 0x2c
#define R_0x28a4 0x28a4
#define R_0x2c04 0x2c04
#define R_0x2c08 0x2c08
#define R_0x2c0c 0x2c0c
@@ -289,6 +343,7 @@
#define R_0x3a9c 0x3a9c
#define R_0x3aa0 0x3aa0
#define R_0x3aa4 0x3aa4
#define R_0x3c00 0x3c00
#define R_0x40 0x40
#define R_0x4000 0x4000
#define R_0x4008 0x4008
@@ -298,7 +353,13 @@
#define R_0x4040 0x4040
#define R_0x4044 0x4044
#define R_0x4100 0x4100
#define R_0x4104 0x4104
#define R_0x4108 0x4108
#define R_0x410c 0x410c
#define R_0x4110 0x4110
#define R_0x4114 0x4114
#define R_0x4118 0x4118
#define R_0x411c 0x411c
#define R_0x4130 0x4130
#define R_0x4134 0x4134
#define R_0x4138 0x4138
@@ -308,13 +369,16 @@
#define R_0x4148 0x4148
#define R_0x4160 0x4160
#define R_0x4164 0x4164
#define R_0x4168 0x4168
#define R_0x416c 0x416c
#define R_0x4180 0x4180
#define R_0x419c 0x419c
#define R_0x41a0 0x41a0
#define R_0x41a4 0x41a4
#define R_0x41a8 0x41a8
#define R_0x41ac 0x41ac
#define R_0x41e0 0x41e0
#define R_0x41e8 0x41e8
#define R_0x41ec 0x41ec
#define R_0x41f0 0x41f0
#define R_0x41f8 0x41f8
@@ -323,6 +387,7 @@
#define R_0x430 0x430
#define R_0x434 0x434
#define R_0x44 0x44
#define R_0x440 0x440
#define R_0x444 0x444
#define R_0x448 0x448
#define R_0x450 0x450
@@ -334,6 +399,8 @@
#define R_0x4c 0x4c
#define R_0x4c8 0x4c8
#define R_0x4cc 0x4cc
#define R_0x45a4 0x45a4
#define R_0x4c00 0x4c00
#define R_0x5000 0x5000
#define R_0x5008 0x5008
#define R_0x5018 0x5018
@@ -352,28 +419,35 @@
#define R_0x5200 0x5200
#define R_0x520c 0x520c
#define R_0x522 0x522
#define R_0x524 0x524
#define R_0x5230 0x5230
#define R_0x5234 0x5234
#define R_0x5238 0x5238
#define R_0x523c 0x523c
#define R_0x5240 0x5240
#define R_0x5244 0x5244
#define R_0x5248 0x5248
#define R_0x526c 0x526c
#define R_0x5280 0x5280
#define R_0x52a0 0x52a0
#define R_0x52a4 0x52a4
#define R_0x52ac 0x52ac
#define R_0x52e8 0x52e8
#define R_0x5300 0x5300
#define R_0x530c 0x530c
#define R_0x5330 0x5330
#define R_0x5334 0x5334
#define R_0x5338 0x5338
#define R_0x533c 0x533c
#define R_0x5340 0x5340
#define R_0x5344 0x5344
#define R_0x5348 0x5348
#define R_0x536c 0x536c
#define R_0x5380 0x5380
#define R_0x53a0 0x53a0
#define R_0x53a4 0x53a4
#define R_0x53ac 0x53ac
#define R_0x53e8 0x53e8
#define R_0x550 0x550
#define R_0x551 0x551
#define R_0x568 0x568
@@ -381,6 +455,7 @@
#define R_0x60 0x60
#define R_0x604 0x604
#define R_0x608 0x608
#define R_0x60c 0x60c
#define R_0x60f 0x60f
#define R_0x64 0x64
#define R_0x66 0x66
@@ -393,6 +468,8 @@
#define R_0x70 0x70
#define R_0x74 0x74
#define R_0x700 0x700
#define R_0x71c 0x71c
#define R_0x72c 0x72c
#define R_0x764 0x764
#define R_0x7b0 0x7b0
#define R_0x7b4 0x7b4
@@ -405,6 +482,7 @@
#define R_0x7f8 0x7f8
#define R_0x7fc 0x7fc
#define R_0x800 0x800
#define R_0x8000 0x8000
#define R_0x804 0x804
#define R_0x808 0x808
#define R_0x80c 0x80c
@@ -448,6 +526,7 @@
#define R_0x8a4 0x8a4
#define R_0x8ac 0x8ac
#define R_0x8b4 0x8b4
#define R_0x8b8 0x8b8
#define R_0x8c0 0x8c0
#define R_0x8c4 0x8c4
#define R_0x8c8 0x8c8
@@ -488,6 +567,7 @@
#define R_0x974 0x974
#define R_0x978 0x978
#define R_0x97c 0x97c
#define R_0x988 0x988
#define R_0x98c 0x98c
#define R_0x990 0x990
#define R_0x994 0x994
@@ -502,6 +582,8 @@
#define R_0x9cc 0x9cc
#define R_0x9d0 0x9d0
#define R_0x9e4 0x9e4
#define R_0x9e8 0x9e8
#define R_0x9f0 0x9f0
#define R_0xa0 0xa0
#define R_0xa00 0xa00
#define R_0xa04 0xa04
@@ -522,6 +604,7 @@
#define R_0xa54 0xa54
#define R_0xa58 0xa58
#define R_0xa68 0xa68
#define R_0xa6c 0xa6c
#define R_0xa70 0xa70
#define R_0xa74 0xa74
#define R_0xa78 0xa78
@@ -550,11 +633,13 @@
#define R_0xb20 0xb20
#define R_0xb24 0xb24
#define R_0xb28 0xb28
#define R_0xb2a 0xb2a
#define R_0xb2b 0xb2b
#define R_0xb2c 0xb2c
#define R_0xb30 0xb30
#define R_0xb34 0xb34
#define R_0xb38 0xb38
#define R_0xb3b 0xb3b
#define R_0xb3c 0xb3c
#define R_0xb40 0xb40
#define R_0xb44 0xb44
@@ -565,6 +650,7 @@
#define R_0xb64 0xb64
#define R_0xb68 0xb68
#define R_0xb6a 0xb6a
#define R_0xb6b 0xb6b
#define R_0xb6c 0xb6c
#define R_0xb6e 0xb6e
#define R_0xb70 0xb70
@@ -641,6 +727,7 @@
#define R_0xcbc 0xcbc
#define R_0xcbd 0xcbd
#define R_0xcbe 0xcbe
#define R_0xcc0 0xcc0
#define R_0xcc4 0xcc4
#define R_0xcc8 0xcc8
#define R_0xccc 0xccc
@@ -727,6 +814,7 @@
#define R_0xeb4 0xeb4
#define R_0xeb8 0xeb8
#define R_0xebc 0xebc
#define R_0xec 0xec
#define R_0xec0 0xec0
#define R_0xec4 0xec4
#define R_0xec8 0xec8
@@ -788,6 +876,7 @@
#define RF_0x0d 0x0d
#define RF_0x1 0x1
#define RF_0x18 0x18
#define RF_0x19 0x19
#define RF_0x1a 0x1a
#define RF_0x1bf0 0x1bf0
#define RF_0x2 0x2
@@ -804,29 +893,40 @@
#define RF_0x43 0x43
#define RF_0x51 0x51
#define RF_0x52 0x52
#define RF_0x53 0x53
#define RF_0x54 0x54
#define RF_0x55 0x55
#define RF_0x56 0x56
#define RF_0x57 0x57
#define RF_0x58 0x58
#define RF_0x5c 0x5c
#define RF_0x5d 0x5d
#define RF_0x61 0x61
#define RF_0x63 0x63
#define RF_0x64 0x64
#define RF_0x65 0x65
#define RF_0x66 0x66
#define RF_0x67 0x67
#define RF_0x6e 0x6e
#define RF_0x6f 0x6f
#define RF_0x75 0x75
#define RF_0x76 0x76
#define RF_0x78 0x78
#define RF_0x7c 0x7c
#define RF_0x7f 0x7f
#define RF_0x8 0x8
#define RF_0x80 0x80
#define RF_0x81 0x81
#define RF_0x82 0x82
#define RF_0x83 0x83
#define RF_0x85 0x85
#define RF_0x86 0x86
#define RF_0x87 0x87
#define RF_0x8a 0x8a
#define RF_0x8c 0x8c
#define RF_0x8d 0x8d
#define RF_0x8f 0x8f
#define RF_0x93 0x93
#define RF_0xa9 0xa9
#define RF_0xae 0xae
#define RF_0xb0 0xb0
@@ -847,3 +947,4 @@
#define RF_0xee 0xee
#define RF_0xef 0xef
#define RF_0xf5 0xf5
#define RF_0xf6 0xf6

1
hal/phydm/phydm_rssi_monitor.c
View File

@@ -161,7 +161,6 @@ void phydm_rssi_monitor_init(void *dm_void)
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct ra_table *ra_tab = &dm->dm_ra_table;
ra_tab->firstconnect = false;
dm->pre_rssi_min = 0;
dm->rssi_max = 0;
dm->rssi_min = 0;

470
hal/phydm/phydm_soml.c
View File

@@ -244,11 +244,23 @@ void phydm_soml_reset_rx_rate(void *dm_void)
for (order = 0; order < HT_RATE_IDX; order++) {
soml_tab->ht_cnt[order] = 0;
soml_tab->pre_ht_cnt[order] = 0;
soml_tab->ht_cnt_on[order] = 0;
soml_tab->ht_cnt_off[order] = 0;
soml_tab->ht_crc_ok_cnt_on[order] = 0;
soml_tab->ht_crc_fail_cnt_on[order] = 0;
soml_tab->ht_crc_ok_cnt_off[order] = 0;
soml_tab->ht_crc_fail_cnt_off[order] = 0;
}
for (order = 0; order < VHT_RATE_IDX; order++) {
soml_tab->vht_cnt[order] = 0;
soml_tab->pre_vht_cnt[order] = 0;
soml_tab->vht_cnt_on[order] = 0;
soml_tab->vht_cnt_off[order] = 0;
soml_tab->vht_crc_ok_cnt_on[order] = 0;
soml_tab->vht_crc_fail_cnt_on[order] = 0;
soml_tab->vht_crc_ok_cnt_off[order] = 0;
soml_tab->vht_crc_fail_cnt_off[order] = 0;
}
}
@@ -548,6 +560,11 @@ void phydm_adsl_init_state(void *dm_void)
}
soml_tab->is_soml_method_enable = 1;
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
odm_set_mac_reg(dm, R_0x608, BIT(8), 1);
/*RCR accepts CRC32-Error packets*/
#endif
soml_tab->get_stats = false;
soml_tab->soml_state_cnt++;
next_on_off = (soml_tab->soml_on_off == SOML_ON) ? SOML_ON : SOML_OFF;
phydm_soml_on_off(dm, next_on_off);
@@ -562,6 +579,7 @@ void phydm_adsl_odd_state(void *dm_void)
u16 ht_reset[HT_RATE_IDX] = {0}, vht_reset[VHT_RATE_IDX] = {0};
u8 size = sizeof(ht_reset[0]);
soml_tab->get_stats = true;
soml_tab->soml_state_cnt++;
odm_move_memory(dm, soml_tab->pre_ht_cnt, soml_tab->ht_cnt,
HT_RATE_IDX * size);
@@ -594,6 +612,7 @@ void phydm_adsl_even_state(void *dm_void)
struct adaptive_soml *soml_tab = &dm->dm_soml_table;
u8 next_on_off;
soml_tab->get_stats = false;
if (dm->support_ic_type == ODM_RTL8822B) {
soml_tab->cfo_cnt++;
phydm_soml_cfo_process(dm,
@@ -618,10 +637,18 @@ void phydm_adsl_decision_state(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct adaptive_soml *soml_tab = &dm->dm_soml_table;
u8 i;
u8 next_on_off, mcs0 = ODM_RATEMCS0, vht0 = ODM_RATEVHTSS1MCS0;
u8 rate_num = 1, rate_ss_shift = 0;
boolean on_above = false, off_above = false;
u8 i, max_idx_on = 0, max_idx_off = 0;
u8 next_on_off = soml_tab->soml_last_state;
u8 mcs0 = ODM_RATEMCS0, vht0 = ODM_RATEVHTSS1MCS0;
u8 crc_taget = soml_tab->soml_last_state;
u8 rate_num = 1, ss_shift = 0;
u16 ht_ok_max_on = 0, ht_fail_max_on = 0, utility_on = 0;
u16 ht_ok_max_off = 0, ht_fail_max_off = 0, utility_off = 0;
u16 vht_ok_max_on = 0, vht_fail_max_on = 0;
u16 vht_ok_max_off = 0, vht_fail_max_off = 0;
u16 num_total_qam = 0;
u16 cnt_max_on = 0, cnt_max_off = 0;
u32 ht_total_cnt_on = 0, ht_total_cnt_off = 0;
u32 total_ht_rate_on = 0, total_ht_rate_off = 0;
u32 vht_total_cnt_on = 0, vht_total_cnt_off = 0;
@@ -634,53 +661,137 @@ void phydm_adsl_decision_state(void *dm_void)
13, 26, 39, 52, 78, 104, 117, 130, 156, 180 /*@2SSMCS0~9*/
};
if (dm->support_ic_type & ODM_IC_4SS)
rate_num = 4;
else if (dm->support_ic_type & ODM_IC_3SS)
rate_num = 3;
if (dm->support_ic_type & ODM_IC_1SS)
rate_num = 1;
#ifdef PHYDM_COMPILE_ABOVE_2SS
else if (dm->support_ic_type & ODM_IC_2SS)
rate_num = 2;
#endif
#ifdef PHYDM_COMPILE_ABOVE_3SS
else if (dm->support_ic_type & ODM_IC_3SS)
rate_num = 3;
#endif
#ifdef PHYDM_COMPILE_ABOVE_4SS
else if (dm->support_ic_type & ODM_IC_4SS)
rate_num = 4;
#endif
else
pr_debug("%s: mismatch IC type %x\n", __func__,
dm->support_ic_type);
soml_tab->get_stats = false;
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
odm_set_mac_reg(dm, R_0x608, BIT(8), 0);
/* NOT Accept CRC32 Error packets. */
#endif
PHYDM_DBG(dm, DBG_ADPTV_SOML, "[Decisoin state ]\n");
phydm_soml_statistics(dm, soml_tab->soml_on_off);
if (*dm->channel <= 14) {
/* @[Search 1st and 2nd rate by counter] */
for (i = 0; i < rate_num; i++) {
rate_ss_shift = (i << 3);
ss_shift = (i << 3);
PHYDM_DBG(dm, DBG_ADPTV_SOML,
"*ht_cnt_on HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
(rate_ss_shift), (rate_ss_shift + 7),
soml_tab->ht_cnt_on[rate_ss_shift + 0],
soml_tab->ht_cnt_on[rate_ss_shift + 1],
soml_tab->ht_cnt_on[rate_ss_shift + 2],
soml_tab->ht_cnt_on[rate_ss_shift + 3],
soml_tab->ht_cnt_on[rate_ss_shift + 4],
soml_tab->ht_cnt_on[rate_ss_shift + 5],
soml_tab->ht_cnt_on[rate_ss_shift + 6],
soml_tab->ht_cnt_on[rate_ss_shift + 7]);
(ss_shift), (ss_shift + 7),
soml_tab->ht_cnt_on[ss_shift + 0],
soml_tab->ht_cnt_on[ss_shift + 1],
soml_tab->ht_cnt_on[ss_shift + 2],
soml_tab->ht_cnt_on[ss_shift + 3],
soml_tab->ht_cnt_on[ss_shift + 4],
soml_tab->ht_cnt_on[ss_shift + 5],
soml_tab->ht_cnt_on[ss_shift + 6],
soml_tab->ht_cnt_on[ss_shift + 7]);
}
for (i = 0; i < rate_num; i++) {
rate_ss_shift = (i << 3);
ss_shift = (i << 3);
PHYDM_DBG(dm, DBG_ADPTV_SOML,
"*ht_byte_off HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
(rate_ss_shift), (rate_ss_shift + 7),
soml_tab->ht_cnt_off[rate_ss_shift + 0],
soml_tab->ht_cnt_off[rate_ss_shift + 1],
soml_tab->ht_cnt_off[rate_ss_shift + 2],
soml_tab->ht_cnt_off[rate_ss_shift + 3],
soml_tab->ht_cnt_off[rate_ss_shift + 4],
soml_tab->ht_cnt_off[rate_ss_shift + 5],
soml_tab->ht_cnt_off[rate_ss_shift + 6],
soml_tab->ht_cnt_off[rate_ss_shift + 7]);
"*ht_cnt_off HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
(ss_shift), (ss_shift + 7),
soml_tab->ht_cnt_off[ss_shift + 0],
soml_tab->ht_cnt_off[ss_shift + 1],
soml_tab->ht_cnt_off[ss_shift + 2],
soml_tab->ht_cnt_off[ss_shift + 3],
soml_tab->ht_cnt_off[ss_shift + 4],
soml_tab->ht_cnt_off[ss_shift + 5],
soml_tab->ht_cnt_off[ss_shift + 6],
soml_tab->ht_cnt_off[ss_shift + 7]);
}
for (i = ODM_RATEMCS8; i <= ODM_RATEMCS15; i++) {
for (i = 0; i < rate_num; i++) {
ss_shift = (i << 3);
PHYDM_DBG(dm, DBG_ADPTV_SOML,
"*ht_crc_ok_cnt_on HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
(ss_shift), (ss_shift + 7),
soml_tab->ht_crc_ok_cnt_on[ss_shift + 0],
soml_tab->ht_crc_ok_cnt_on[ss_shift + 1],
soml_tab->ht_crc_ok_cnt_on[ss_shift + 2],
soml_tab->ht_crc_ok_cnt_on[ss_shift + 3],
soml_tab->ht_crc_ok_cnt_on[ss_shift + 4],
soml_tab->ht_crc_ok_cnt_on[ss_shift + 5],
soml_tab->ht_crc_ok_cnt_on[ss_shift + 6],
soml_tab->ht_crc_ok_cnt_on[ss_shift + 7]);
}
for (i = 0; i < rate_num; i++) {
ss_shift = (i << 3);
PHYDM_DBG(dm, DBG_ADPTV_SOML,
"*ht_crc_fail_cnt_on HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
(ss_shift), (ss_shift + 7),
soml_tab->ht_crc_fail_cnt_on[ss_shift + 0],
soml_tab->ht_crc_fail_cnt_on[ss_shift + 1],
soml_tab->ht_crc_fail_cnt_on[ss_shift + 2],
soml_tab->ht_crc_fail_cnt_on[ss_shift + 3],
soml_tab->ht_crc_fail_cnt_on[ss_shift + 4],
soml_tab->ht_crc_fail_cnt_on[ss_shift + 5],
soml_tab->ht_crc_fail_cnt_on[ss_shift + 6],
soml_tab->ht_crc_fail_cnt_on[ss_shift + 7]);
}
for (i = 0; i < rate_num; i++) {
ss_shift = (i << 3);
PHYDM_DBG(dm, DBG_ADPTV_SOML,
"*ht_crc_ok_cnt_off HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
(ss_shift), (ss_shift + 7),
soml_tab->ht_crc_ok_cnt_off[ss_shift + 0],
soml_tab->ht_crc_ok_cnt_off[ss_shift + 1],
soml_tab->ht_crc_ok_cnt_off[ss_shift + 2],
soml_tab->ht_crc_ok_cnt_off[ss_shift + 3],
soml_tab->ht_crc_ok_cnt_off[ss_shift + 4],
soml_tab->ht_crc_ok_cnt_off[ss_shift + 5],
soml_tab->ht_crc_ok_cnt_off[ss_shift + 6],
soml_tab->ht_crc_ok_cnt_off[ss_shift + 7]);
}
for (i = 0; i < rate_num; i++) {
ss_shift = (i << 3);
PHYDM_DBG(dm, DBG_ADPTV_SOML,
"*ht_crc_fail_cnt_off HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
(ss_shift), (ss_shift + 7),
soml_tab->ht_crc_fail_cnt_off[ss_shift + 0],
soml_tab->ht_crc_fail_cnt_off[ss_shift + 1],
soml_tab->ht_crc_fail_cnt_off[ss_shift + 2],
soml_tab->ht_crc_fail_cnt_off[ss_shift + 3],
soml_tab->ht_crc_fail_cnt_off[ss_shift + 4],
soml_tab->ht_crc_fail_cnt_off[ss_shift + 5],
soml_tab->ht_crc_fail_cnt_off[ss_shift + 6],
soml_tab->ht_crc_fail_cnt_off[ss_shift + 7]);
}
for (i = ODM_RATEMCS0; i <= ODM_RATEMCS15; i++) {
ht_total_cnt_on += soml_tab->ht_cnt_on[i - mcs0];
ht_total_cnt_off += soml_tab->ht_cnt_off[i - mcs0];
total_ht_rate_on += (soml_tab->ht_cnt_on[i - mcs0] *
(phy_rate_table[i] >> 1));
phy_rate_table[i]);
total_ht_rate_off += (soml_tab->ht_cnt_off[i - mcs0] *
(phy_rate_table[i] >> 1));
phy_rate_table[i]);
if (soml_tab->ht_cnt_on[i - mcs0] > cnt_max_on) {
cnt_max_on = soml_tab->ht_cnt_on[i - mcs0];
max_idx_on = i - mcs0;
}
if (soml_tab->ht_cnt_off[i - mcs0] > cnt_max_off) {
cnt_max_off = soml_tab->ht_cnt_off[i - mcs0];
max_idx_off = i - mcs0;
}
}
total_ht_rate_on = total_ht_rate_on << 3;
total_ht_rate_off = total_ht_rate_off << 3;
@@ -688,9 +799,50 @@ void phydm_adsl_decision_state(void *dm_void)
(total_ht_rate_on / ht_total_cnt_on) : 0;
rate_per_pkt_off = (ht_total_cnt_off != 0) ?
(total_ht_rate_off / ht_total_cnt_off) : 0;
}
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
ht_ok_max_on = soml_tab->ht_crc_ok_cnt_on[max_idx_on];
ht_fail_max_on = soml_tab->ht_crc_fail_cnt_on[max_idx_on];
ht_ok_max_off = soml_tab->ht_crc_ok_cnt_off[max_idx_off];
ht_fail_max_off = soml_tab->ht_crc_fail_cnt_off[max_idx_off];
if (dm->support_ic_type == ODM_RTL8822B) {
if (ht_fail_max_on == 0)
ht_fail_max_on = 1;
if (ht_fail_max_off == 0)
ht_fail_max_off = 1;
if (ht_ok_max_on > ht_fail_max_on)
on_above = true;
if (ht_ok_max_off > ht_fail_max_off)
off_above = true;
if (on_above && !off_above) {
crc_taget = SOML_ON;
} else if (!on_above && off_above) {
crc_taget = SOML_OFF;
} else if (on_above && off_above) {
utility_on = (ht_ok_max_on << 7) / ht_fail_max_on;
utility_off = (ht_ok_max_off << 7) / ht_fail_max_off;
crc_taget = (utility_on == utility_off) ?
(soml_tab->soml_last_state) :
((utility_on > utility_off) ? SOML_ON :
SOML_OFF);
} else if (!on_above && !off_above) {
if (ht_ok_max_on == 0)
ht_ok_max_on = 1;
if (ht_ok_max_off == 0)
ht_ok_max_off = 1;
utility_on = (ht_fail_max_on << 7) / ht_ok_max_on;
utility_off = (ht_fail_max_off << 7) / ht_ok_max_off;
crc_taget = (utility_on == utility_off) ?
(soml_tab->soml_last_state) :
((utility_on < utility_off) ? SOML_ON :
SOML_OFF);
}
#endif
} else if (dm->support_ic_type == ODM_RTL8822B) {
cfo_diff_avg_a = soml_tab->cfo_diff_sum_a / soml_tab->cfo_cnt;
cfo_diff_avg_b = soml_tab->cfo_diff_sum_b / soml_tab->cfo_cnt;
soml_tab->cfo_diff_avg_a = (soml_tab->cfo_cnt != 0) ?
@@ -758,48 +910,121 @@ void phydm_adsl_decision_state(void *dm_void)
}
for (i = 0; i < rate_num; i++) {
rate_ss_shift = 10 * i;
ss_shift = 10 * i;
PHYDM_DBG(dm, DBG_ADPTV_SOML,
"[ vht_cnt_on VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\n",
(i + 1),
soml_tab->vht_cnt_on[rate_ss_shift + 0],
soml_tab->vht_cnt_on[rate_ss_shift + 1],
soml_tab->vht_cnt_on[rate_ss_shift + 2],
soml_tab->vht_cnt_on[rate_ss_shift + 3],
soml_tab->vht_cnt_on[rate_ss_shift + 4],
soml_tab->vht_cnt_on[rate_ss_shift + 5],
soml_tab->vht_cnt_on[rate_ss_shift + 6],
soml_tab->vht_cnt_on[rate_ss_shift + 7],
soml_tab->vht_cnt_on[rate_ss_shift + 8],
soml_tab->vht_cnt_on[rate_ss_shift + 9]);
soml_tab->vht_cnt_on[ss_shift + 0],
soml_tab->vht_cnt_on[ss_shift + 1],
soml_tab->vht_cnt_on[ss_shift + 2],
soml_tab->vht_cnt_on[ss_shift + 3],
soml_tab->vht_cnt_on[ss_shift + 4],
soml_tab->vht_cnt_on[ss_shift + 5],
soml_tab->vht_cnt_on[ss_shift + 6],
soml_tab->vht_cnt_on[ss_shift + 7],
soml_tab->vht_cnt_on[ss_shift + 8],
soml_tab->vht_cnt_on[ss_shift + 9]);
}
for (i = 0; i < rate_num; i++) {
rate_ss_shift = 10 * i;
ss_shift = 10 * i;
PHYDM_DBG(dm, DBG_ADPTV_SOML,
"[ vht_cnt_off VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\n",
(i + 1),
soml_tab->vht_cnt_off[rate_ss_shift + 0],
soml_tab->vht_cnt_off[rate_ss_shift + 1],
soml_tab->vht_cnt_off[rate_ss_shift + 2],
soml_tab->vht_cnt_off[rate_ss_shift + 3],
soml_tab->vht_cnt_off[rate_ss_shift + 4],
soml_tab->vht_cnt_off[rate_ss_shift + 5],
soml_tab->vht_cnt_off[rate_ss_shift + 6],
soml_tab->vht_cnt_off[rate_ss_shift + 7],
soml_tab->vht_cnt_off[rate_ss_shift + 8],
soml_tab->vht_cnt_off[rate_ss_shift + 9]);
soml_tab->vht_cnt_off[ss_shift + 0],
soml_tab->vht_cnt_off[ss_shift + 1],
soml_tab->vht_cnt_off[ss_shift + 2],
soml_tab->vht_cnt_off[ss_shift + 3],
soml_tab->vht_cnt_off[ss_shift + 4],
soml_tab->vht_cnt_off[ss_shift + 5],
soml_tab->vht_cnt_off[ss_shift + 6],
soml_tab->vht_cnt_off[ss_shift + 7],
soml_tab->vht_cnt_off[ss_shift + 8],
soml_tab->vht_cnt_off[ss_shift + 9]);
}
for (i = 0; i < rate_num; i++) {
ss_shift = 10 * i;
PHYDM_DBG(dm, DBG_ADPTV_SOML,
"*vht_crc_ok_cnt_on VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
soml_tab->vht_crc_ok_cnt_on[ss_shift + 0],
soml_tab->vht_crc_ok_cnt_on[ss_shift + 1],
soml_tab->vht_crc_ok_cnt_on[ss_shift + 2],
soml_tab->vht_crc_ok_cnt_on[ss_shift + 3],
soml_tab->vht_crc_ok_cnt_on[ss_shift + 4],
soml_tab->vht_crc_ok_cnt_on[ss_shift + 5],
soml_tab->vht_crc_ok_cnt_on[ss_shift + 6],
soml_tab->vht_crc_ok_cnt_on[ss_shift + 7],
soml_tab->vht_crc_ok_cnt_on[ss_shift + 8],
soml_tab->vht_crc_ok_cnt_on[ss_shift + 9]);
}
for (i = 0; i < rate_num; i++) {
ss_shift = 10 * i;
PHYDM_DBG(dm, DBG_ADPTV_SOML,
"*vht_crc_fail_cnt_on VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
soml_tab->vht_crc_fail_cnt_on[ss_shift + 0],
soml_tab->vht_crc_fail_cnt_on[ss_shift + 1],
soml_tab->vht_crc_fail_cnt_on[ss_shift + 2],
soml_tab->vht_crc_fail_cnt_on[ss_shift + 3],
soml_tab->vht_crc_fail_cnt_on[ss_shift + 4],
soml_tab->vht_crc_fail_cnt_on[ss_shift + 5],
soml_tab->vht_crc_fail_cnt_on[ss_shift + 6],
soml_tab->vht_crc_fail_cnt_on[ss_shift + 7],
soml_tab->vht_crc_fail_cnt_on[ss_shift + 8],
soml_tab->vht_crc_fail_cnt_on[ss_shift + 9]);
}
for (i = 0; i < rate_num; i++) {
ss_shift = 10 * i;
PHYDM_DBG(dm, DBG_ADPTV_SOML,
"*vht_crc_ok_cnt_off VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
soml_tab->vht_crc_ok_cnt_off[ss_shift + 0],
soml_tab->vht_crc_ok_cnt_off[ss_shift + 1],
soml_tab->vht_crc_ok_cnt_off[ss_shift + 2],
soml_tab->vht_crc_ok_cnt_off[ss_shift + 3],
soml_tab->vht_crc_ok_cnt_off[ss_shift + 4],
soml_tab->vht_crc_ok_cnt_off[ss_shift + 5],
soml_tab->vht_crc_ok_cnt_off[ss_shift + 6],
soml_tab->vht_crc_ok_cnt_off[ss_shift + 7],
soml_tab->vht_crc_ok_cnt_off[ss_shift + 8],
soml_tab->vht_crc_ok_cnt_off[ss_shift + 9]);
}
for (i = 0; i < rate_num; i++) {
ss_shift = 10 * i;
PHYDM_DBG(dm, DBG_ADPTV_SOML,
"*vht_crc_fail_cnt_off VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
(i + 1),
soml_tab->vht_crc_fail_cnt_off[ss_shift + 0],
soml_tab->vht_crc_fail_cnt_off[ss_shift + 1],
soml_tab->vht_crc_fail_cnt_off[ss_shift + 2],
soml_tab->vht_crc_fail_cnt_off[ss_shift + 3],
soml_tab->vht_crc_fail_cnt_off[ss_shift + 4],
soml_tab->vht_crc_fail_cnt_off[ss_shift + 5],
soml_tab->vht_crc_fail_cnt_off[ss_shift + 6],
soml_tab->vht_crc_fail_cnt_off[ss_shift + 7],
soml_tab->vht_crc_fail_cnt_off[ss_shift + 8],
soml_tab->vht_crc_fail_cnt_off[ss_shift + 9]);
}
for (i = ODM_RATEVHTSS2MCS0; i <= ODM_RATEVHTSS2MCS9; i++) {
vht_total_cnt_on += soml_tab->vht_cnt_on[i - vht0];
vht_total_cnt_off += soml_tab->vht_cnt_off[i - vht0];
total_vht_rate_on += (soml_tab->vht_cnt_on[i - vht0] *
(vht_phy_rate_table[i - vht0] >> 1
));
vht_phy_rate_table[i - vht0]);
total_vht_rate_off += (soml_tab->vht_cnt_off[i - vht0] *
(vht_phy_rate_table[i - vht0] >> 1
));
vht_phy_rate_table[i - vht0]);
if (soml_tab->vht_cnt_on[i - vht0] > cnt_max_on) {
cnt_max_on = soml_tab->vht_cnt_on[i - vht0];
max_idx_on = i - vht0;
}
if (soml_tab->vht_cnt_off[i - vht0] > cnt_max_off) {
cnt_max_off = soml_tab->vht_cnt_off[i - vht0];
max_idx_off = i - vht0;
}
}
total_vht_rate_on = total_vht_rate_on << 3;
total_vht_rate_off = total_vht_rate_off << 3;
@@ -807,12 +1032,67 @@ void phydm_adsl_decision_state(void *dm_void)
(total_vht_rate_on / vht_total_cnt_on) : 0;
rate_per_pkt_off = (vht_total_cnt_off != 0) ?
(total_vht_rate_off / vht_total_cnt_off) : 0;
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
vht_ok_max_on = soml_tab->vht_crc_ok_cnt_on[max_idx_on];
vht_fail_max_on = soml_tab->vht_crc_fail_cnt_on[max_idx_on];
vht_ok_max_off = soml_tab->vht_crc_ok_cnt_off[max_idx_off];
vht_fail_max_off = soml_tab->vht_crc_fail_cnt_off[max_idx_off];
if (vht_fail_max_on == 0)
vht_fail_max_on = 1;
if (vht_fail_max_off == 0)
vht_fail_max_off = 1;
if (vht_ok_max_on > vht_fail_max_on)
on_above = true;
if (vht_ok_max_off > vht_fail_max_off)
off_above = true;
if (on_above && !off_above) {
crc_taget = SOML_ON;
} else if (!on_above && off_above) {
crc_taget = SOML_OFF;
} else if (on_above && off_above) {
utility_on = (vht_ok_max_on << 7) / vht_fail_max_on;
utility_off = (vht_ok_max_off << 7) / vht_fail_max_off;
crc_taget = (utility_on == utility_off) ?
(soml_tab->soml_last_state) :
((utility_on > utility_off) ? SOML_ON :
SOML_OFF);
} else if (!on_above && !off_above) {
if (vht_ok_max_on == 0)
vht_ok_max_on = 1;
if (vht_ok_max_off == 0)
vht_ok_max_off = 1;
utility_on = (vht_fail_max_on << 7) / vht_ok_max_on;
utility_off = (vht_fail_max_off << 7) / vht_ok_max_off;
crc_taget = (utility_on == utility_off) ?
(soml_tab->soml_last_state) :
((utility_on < utility_off) ? SOML_ON :
SOML_OFF);
}
#endif
}
/* @[Decision] */
PHYDM_DBG(dm, DBG_ADPTV_SOML,
"[ rate_per_pkt_on = %d ; rate_per_pkt_off = %d ]\n",
rate_per_pkt_on, rate_per_pkt_off);
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
if (max_idx_on == max_idx_off && max_idx_on != 0) {
PHYDM_DBG(dm, DBG_ADPTV_SOML,
"[ max_idx_on == max_idx_off ]\n");
PHYDM_DBG(dm, DBG_ADPTV_SOML,
"[ max_idx = %d, crc_utility_on = %d, crc_utility_off = %d, crc_target = %d]\n",
max_idx_on, utility_on, utility_off,
crc_taget);
next_on_off = crc_taget;
} else
#endif
if (rate_per_pkt_on > rate_per_pkt_off) {
next_on_off = SOML_ON;
PHYDM_DBG(dm, DBG_ADPTV_SOML,
@@ -877,32 +1157,82 @@ void phydm_set_adsl_val(void *dm_void, u32 *val_buf, u8 val_len)
phydm_soml_on_off(dm, (u8)val_buf[1]);
}
void phydm_soml_crc_acq(void *dm_void, u8 rate_id, boolean crc32, u32 length)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct adaptive_soml *soml_tab = &dm->dm_soml_table;
u8 offset = 0;
if (!soml_tab->get_stats)
return;
if (length < 1400)
return;
if (soml_tab->soml_on_off == SOML_ON) {
if (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS15) {
offset = rate_id - ODM_RATEMCS0;
if (crc32 == CRC_OK)
soml_tab->ht_crc_ok_cnt_on[offset]++;
else if (crc32 == CRC_FAIL)
soml_tab->ht_crc_fail_cnt_on[offset]++;
} else if (rate_id >= ODM_RATEVHTSS1MCS0 &&
rate_id <= ODM_RATEVHTSS2MCS9) {
offset = rate_id - ODM_RATEVHTSS1MCS0;
if (crc32 == CRC_OK)
soml_tab->vht_crc_ok_cnt_on[offset]++;
else if (crc32 == CRC_FAIL)
soml_tab->vht_crc_fail_cnt_on[offset]++;
}
} else if (soml_tab->soml_on_off == SOML_OFF) {
if (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS15) {
offset = rate_id - ODM_RATEMCS0;
if (crc32 == CRC_OK)
soml_tab->ht_crc_ok_cnt_off[offset]++;
else if (crc32 == CRC_FAIL)
soml_tab->ht_crc_fail_cnt_off[offset]++;
} else if (rate_id >= ODM_RATEVHTSS1MCS0 &&
rate_id <= ODM_RATEVHTSS2MCS9) {
offset = rate_id - ODM_RATEVHTSS1MCS0;
if (crc32 == CRC_OK)
soml_tab->vht_crc_ok_cnt_off[offset]++;
else if (crc32 == CRC_FAIL)
soml_tab->vht_crc_fail_cnt_off[offset]++;
}
}
}
void phydm_soml_bytes_acq(void *dm_void, u8 rate_id, u32 length)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct adaptive_soml *soml_tab = &dm->dm_soml_table;
u8 offset = 0;
if (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS31)
soml_tab->ht_byte[rate_id - ODM_RATEMCS0] += (u16)length;
else if (rate_id >= ODM_RATEVHTSS1MCS0 && rate_id <= ODM_RATEVHTSS4MCS9)
soml_tab->vht_byte[rate_id - ODM_RATEVHTSS1MCS0] += (u16)length;
if (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS31) {
offset = rate_id - ODM_RATEMCS0;
if (offset > (HT_RATE_IDX - 1))
offset = HT_RATE_IDX - 1;
soml_tab->ht_byte[offset] += (u16)length;
} else if (rate_id >= ODM_RATEVHTSS1MCS0 &&
rate_id <= ODM_RATEVHTSS4MCS9) {
offset = rate_id - ODM_RATEVHTSS1MCS0;
if (offset > (VHT_RATE_IDX - 1))
offset = VHT_RATE_IDX - 1;
soml_tab->vht_byte[offset] += (u16)length;
}
}
#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
#define INIT_TIMER_EVENT_ENTRY(_entry, _func, _data) \
do { \
_rtw_init_listhead(&(_entry)->list); \
(_entry)->data = (_data); \
(_entry)->function = (_func); \
} while (0)
static void pre_phydm_adaptive_soml_callback(unsigned long task_dm)
{
struct dm_struct *dm = (struct dm_struct *)task_dm;
struct rtl8192cd_priv *priv = dm->priv;
struct priv_shared_info *pshare = priv->pshare;
if (!(priv->drv_state & DRV_STATE_OPEN))
return;
if (pshare->bDriverStopped || pshare->bSurpriseRemoved) {
printk("[%s] bDriverStopped(%d) OR bSurpriseRemoved(%d)\n",
__FUNCTION__, pshare->bDriverStopped,

16
hal/phydm/phydm_soml.h
View File

@@ -44,6 +44,9 @@
#define HT_ORDER_TYPE 3
#define VHT_ORDER_TYPE 4
#define CRC_FAIL 1
#define CRC_OK 0
#if 0
#define CFO_QPSK_TH 20
#define CFO_QAM16_TH 20
@@ -64,8 +67,9 @@
#ifdef CONFIG_ADAPTIVE_SOML
struct adaptive_soml {
u8 rvrt_val;
u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
boolean is_soml_method_enable;
boolean get_stats;
u8 soml_on_off;
u8 soml_state_cnt;
u8 soml_delay_time;
@@ -94,6 +98,14 @@ struct adaptive_soml {
u16 pre_ht_cnt[HT_RATE_IDX];
u16 ht_cnt_on[HT_RATE_IDX];
u16 ht_cnt_off[HT_RATE_IDX];
u16 ht_crc_ok_cnt_on[HT_RATE_IDX];
u16 ht_crc_fail_cnt_on[HT_RATE_IDX];
u16 ht_crc_ok_cnt_off[HT_RATE_IDX];
u16 ht_crc_fail_cnt_off[HT_RATE_IDX];
u16 vht_crc_ok_cnt_on[VHT_RATE_IDX];
u16 vht_crc_fail_cnt_on[VHT_RATE_IDX];
u16 vht_crc_ok_cnt_off[VHT_RATE_IDX];
u16 vht_crc_fail_cnt_off[VHT_RATE_IDX];
u16 vht_cnt[VHT_RATE_IDX];
u16 pre_vht_cnt[VHT_RATE_IDX];
@@ -166,6 +178,8 @@ void phydm_adaptive_soml_reset(void *dm_void);
void phydm_set_adsl_val(void *dm_void, u32 *val_buf, u8 val_len);
void phydm_soml_crc_acq(void *dm_void, u8 rate_id, boolean crc32, u32 length);
void phydm_soml_bytes_acq(void *dm_void, u8 rate_id, u32 length);
void phydm_adaptive_soml_timers(void *dm_void, u8 state);

928
hal/phydm/rtl8822b/halhwimg8822b_bb.c
View File

File diff suppressed because it is too large Load Diff

11
hal/phydm/rtl8822b/halhwimg8822b_bb.h
View File

@@ -23,7 +23,7 @@
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.5.3*/
/*Image2HeaderVersion: R3 1.5.10*/
#if (RTL8822B_SUPPORT == 1)
#ifndef __INC_MP_BB_HW_IMG_8822B_H
#define __INC_MP_BB_HW_IMG_8822B_H
@@ -100,6 +100,15 @@ void
odm_read_and_config_mp_8822b_phy_reg_pg_type18(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_phy_reg_pg_type18(void);
/******************************************************************************
* phy_reg_pg_type19.TXT
******************************************************************************/
/* tc: Test Chip, mp: mp Chip*/
void
odm_read_and_config_mp_8822b_phy_reg_pg_type19(struct dm_struct *dm);
u32 odm_get_version_mp_8822b_phy_reg_pg_type19(void);
/******************************************************************************
* phy_reg_pg_type2.TXT
******************************************************************************/

12
hal/phydm/rtl8822b/halhwimg8822b_mac.c
View File

@@ -23,7 +23,7 @@
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.5.3*/
/*Image2HeaderVersion: R3 1.5.10*/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
@@ -104,14 +104,6 @@ check_positive(struct dm_struct *dm,
return false;
}
static boolean
check_negative(struct dm_struct *dm,
const u32 condition1,
const u32 condition2
)
{
return true;
}
/******************************************************************************
* mac_reg.TXT
@@ -309,7 +301,7 @@ odm_read_and_config_mp_8822b_mac_reg(struct dm_struct *dm)
u32
odm_get_version_mp_8822b_mac_reg(void)
{
return 113;
return 117;
}
#endif /* end of HWIMG_SUPPORT*/

2
hal/phydm/rtl8822b/halhwimg8822b_mac.h
View File

@@ -23,7 +23,7 @@
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.5.3*/
/*Image2HeaderVersion: R3 1.5.10*/
#if (RTL8822B_SUPPORT == 1)
#ifndef __INC_MP_MAC_HW_IMG_8822B_H
#define __INC_MP_MAC_HW_IMG_8822B_H

304
hal/phydm/rtl8822b/phydm_hal_api8822b.c
View File

@@ -77,16 +77,16 @@ void phydm_8822b_type18_rfe(struct dm_struct *dm, u8 channel)
/* signal source */
odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x177517);
odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x177517);
odm_set_bb_reg(dm, R_0xcb4, MASKLWORD, 0x7557);
odm_set_bb_reg(dm, R_0xeb4, MASKLWORD, 0x7557);
odm_set_bb_reg(dm, R_0xcb4, MASKLWORD, 0x7577);
odm_set_bb_reg(dm, R_0xeb4, MASKLWORD, 0x7577);
odm_set_bb_reg(dm, R_0xcb8, BIT(5), 0);
odm_set_bb_reg(dm, R_0xeb8, BIT(5), 0);
} else if (channel > 64) {
/* signal source */
odm_set_bb_reg(dm, R_0xcb0, 0xffffff, 0x177517);
odm_set_bb_reg(dm, R_0xeb0, 0xffffff, 0x177517);
odm_set_bb_reg(dm, R_0xcb4, MASKLWORD, 0x7575);
odm_set_bb_reg(dm, R_0xeb4, MASKLWORD, 0x7575);
odm_set_bb_reg(dm, R_0xcb4, MASKLWORD, 0x7577);
odm_set_bb_reg(dm, R_0xeb4, MASKLWORD, 0x7577);
odm_set_bb_reg(dm, R_0xcb8, BIT(5), 0);
odm_set_bb_reg(dm, R_0xeb8, BIT(5), 0);
}
@@ -124,6 +124,11 @@ void phydm_8822b_type18_rfe(struct dm_struct *dm, u8 channel)
odm_set_bb_reg(dm, R_0xebc, (BIT(11) | BIT(10) | BIT(9)
| BIT(8)), 0x0);
if (channel <= 64)
odm_set_bb_reg(dm, 0xcbc, BIT(9), 0x1);
else
odm_set_bb_reg(dm, 0xcbc, BIT(8), 0x1);
/* delay 400ns for PAPE */
/* odm_set_bb_reg(p_dm, 0x810, MASKBYTE3|BIT20|BIT21*/
/* |BIT22|BIT23, 0x211); */
@@ -132,16 +137,16 @@ void phydm_8822b_type18_rfe(struct dm_struct *dm, u8 channel)
if (dm->rx_ant_status == BB_PATH_AB ||
dm->tx_ant_status == BB_PATH_AB) {
/* 2TX or 2RX */
odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0x5501);
odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0x5501);
odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa501);
odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa501);
} else if (dm->rx_ant_status == dm->tx_ant_status) {
/* TXA+RXA or TXB+RXB */
odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0x5500);
odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0x5500);
odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa500);
odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa500);
} else {
/* TXB+RXA or TXA+RXB */
odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0x5005);
odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0x5005);
odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa005);
odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa005);
}
}
}
@@ -219,11 +224,9 @@ u32 phydm_check_bit_mask(u32 bit_mask, u32 data_original, u32 data)
}
__iram_odm_func__
void phydm_rfe_8822b_setting(void *dm_void, u8 rfe_n, u8 mux_sel,
void phydm_rfe_8822b_setting(struct dm_struct *dm, u8 rfe_n, u8 mux_sel,
u8 inv_en, u8 source_sel)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s ======>\n", __func__);
PHYDM_DBG(dm, ODM_PHY_CONFIG,
"RFE[%d]:{Path=0x%x}{inv_en=%d}{source=0x%x}\n", rfe_n,
@@ -280,7 +283,6 @@ __iram_odm_func__
void phydm_rfe_4_11(struct dm_struct *dm, u8 channel)
{
boolean is_channel_2g = (channel <= 14) ? true : false;
u8 rfe_type = dm->rfe_type;
/*TRSW=trsw_forced_BT ? 0x804[0]:(0xCB8[2]?0xCB8[0]:trsw_lut);*/
/*trsw_lut = TXON*/
@@ -435,7 +437,6 @@ __iram_odm_func__
void phydm_rfe_ifem(struct dm_struct *dm, u8 channel)
{
boolean is_channel_2g = (channel <= 14) ? true : false;
u8 rfe_type = dm->rfe_type;
if (is_channel_2g) {
/* signal source */
@@ -638,7 +639,7 @@ phydm_rfe_8822b(struct dm_struct *dm, u8 channel)
else if ((rfe_type == 0) || (rfe_type == 3) || (rfe_type == 5) ||
(rfe_type == 8) || (rfe_type == 10) || (rfe_type == 12) ||
(rfe_type == 13) || (rfe_type == 14) || (rfe_type == 16) ||
(rfe_type == 17))
(rfe_type == 17) || (rfe_type == 19))
/* @iFEM */
phydm_rfe_ifem(dm, channel);
else if (rfe_type == 15)
@@ -767,7 +768,8 @@ void phydm_ccapar_by_rfe_8822b(struct dm_struct *dm)
odm_move_memory(dm, cca_efem, cca_efem_ccut, 12 * 4);
if (dm->rfe_type == 3 || dm->rfe_type == 5 ||
dm->rfe_type == 12 || dm->rfe_type == 15 ||
dm->rfe_type == 16 || dm->rfe_type == 17) {
dm->rfe_type == 16 || dm->rfe_type == 17 ||
dm->rfe_type == 19) {
odm_move_memory(dm, cca_ifem, cca_ifem_ccut_rfe, 12 * 4);
is_rfe_type = true;
} else {
@@ -910,6 +912,7 @@ phydm_write_txagc_1byte_8822b(struct dm_struct *dm,
__iram_odm_func__
void phydm_get_condi_num_acc_8822b(void *dm_void)
{
#if (PHYDM_FW_API_FUNC_ENABLE_8822B)
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
u8 i = 0;
@@ -923,6 +926,7 @@ void phydm_get_condi_num_acc_8822b(void *dm_void)
/*@disable report condition number*/
/*odm_set_bb_reg(dm, R_0x1988, BIT(22), 0x0);*/
#endif
#endif
}
__iram_odm_func__
@@ -1184,6 +1188,7 @@ u8 phydm_dsde_ch_idx(struct dm_struct *dm)
__iram_odm_func__
void phydm_dsde_nbi(struct dm_struct *dm)
{
#if (PHYDM_FW_API_FUNC_ENABLE_8822B)
u8 set_nbi = PHYDM_SET_NO_NEED;
/* Modify CCA parameters due to NBI */
@@ -1191,7 +1196,7 @@ void phydm_dsde_nbi(struct dm_struct *dm)
odm_set_bb_reg(dm, 0x82c, 0xff000, 0x86);
else
odm_set_bb_reg(dm, 0x82c, 0xff000, 0x97);
if (dm->rfe_type == 12) {
if (dm->rfe_type == 12 || dm->rfe_type == 19) {
if (*dm->band_width == CHANNEL_WIDTH_20) {
if (*dm->channel >= 5 && *dm->channel <= 7)
odm_set_bb_reg(dm, 0x82c, 0xf000, 0x3);
@@ -1265,11 +1270,13 @@ void phydm_dsde_nbi(struct dm_struct *dm)
} else {
set_nbi = PHYDM_SET_NO_NEED;
}
#endif
}
__iram_odm_func__
void phydm_dsde_csi(struct dm_struct *dm)
{
#if (PHYDM_FW_API_FUNC_ENABLE_8822B)
u8 set_result_csi = PHYDM_SET_NO_NEED;
if (*dm->band_width == CHANNEL_WIDTH_20) {
@@ -1328,6 +1335,7 @@ void phydm_dsde_csi(struct dm_struct *dm)
} else {
set_result_csi = PHYDM_SET_NO_NEED;
}
#endif
}
__iram_odm_func__
@@ -1387,21 +1395,21 @@ void phydm_dynamic_spur_det_eliminate(struct dm_struct *dm)
if (k == 0) {
f_pt_2g = freq_2g_n1[idx];
f_pt_2g_b = freq_2g_n1[idx] | BIT(16);
if (idx <= 10) {
if (idx < 10) {
f_pt_5g = freq_5g_n1[idx];
f_pt_5g_b = freq_5g_n1[idx] | BIT(16);
}
} else if (k == 1) {
f_pt_2g = freq_2g[idx];
f_pt_2g_b = freq_2g[idx] | BIT(16);
if (idx <= 10) {
if (idx < 10) {
f_pt_5g = freq_5g[idx];
f_pt_5g_b = freq_5g[idx] | BIT(16);
}
} else if (k == 2) {
f_pt_2g = freq_2g_p1[idx];
f_pt_2g_b = freq_2g_p1[idx] | BIT(16);
if (idx <= 10) {
if (idx < 10) {
f_pt_5g = freq_5g_p1[idx];
f_pt_5g_b = freq_5g_p1[idx] | BIT(16);
}
@@ -1530,18 +1538,17 @@ void phydm_dynamic_spur_det_eliminate(struct dm_struct *dm)
__iram_odm_func__
void phydm_spur_calibration_8822b(struct dm_struct *dm)
{
#ifdef CONFIG_8822B_SPUR_CALIBRATION
if (*dm->is_scan_in_process)
return;
#ifdef CONFIG_8822B_SPUR_CALIBRATION
odm_set_bb_reg(dm, R_0x87c, BIT(13), 0x0);
odm_set_bb_reg(dm, R_0xc20, BIT(28), 0x0);
odm_set_bb_reg(dm, R_0xe20, BIT(28), 0x0);
phydm_dynamic_spur_det_eliminate(dm);
PHYDM_DBG(dm, ODM_COMP_API,
"Enable spur eliminator at normal\n");
odm_set_bb_reg(dm, R_0x87c, BIT(13), 0x0);
odm_set_bb_reg(dm, R_0xc20, BIT(28), 0x0);
odm_set_bb_reg(dm, R_0xe20, BIT(28), 0x0);
phydm_dynamic_spur_det_eliminate(dm);
PHYDM_DBG(dm, ODM_COMP_API, "Enable spur eliminator at normal\n");
#else
PHYDM_DBG(dm, ODM_COMP_API, "NBI and CSI notch at normal\n");
PHYDM_DBG(dm, ODM_COMP_API, "NBI and CSI notch at normal\n");
#endif
}
@@ -1624,7 +1631,7 @@ config_phydm_switch_band_8822b(struct dm_struct *dm,
}
}
if (dm->rfe_type == 12) {
if (dm->rfe_type == 12 || dm->rfe_type == 19) {
odm_set_rf_reg(dm, RF_PATH_A, RF_0xb3, RFREGOFFSETMASK,
0x3C360);
odm_set_rf_reg(dm, RF_PATH_B, RF_0xb3, RFREGOFFSETMASK,
@@ -1689,7 +1696,7 @@ config_phydm_switch_band_8822b(struct dm_struct *dm,
}
}
if (dm->rfe_type == 12) {
if (dm->rfe_type == 12 || dm->rfe_type == 19) {
odm_set_rf_reg(dm, RF_PATH_A, RF_0xb3, RFREGOFFSETMASK,
0xFC760);
odm_set_rf_reg(dm, RF_PATH_B, RF_0xb3, RFREGOFFSETMASK,
@@ -2290,46 +2297,60 @@ config_phydm_switch_channel_bw_8822b(struct dm_struct *dm,
return true;
}
__iram_odm_func__
boolean
config_phydm_trx_mode_8822b(struct dm_struct *dm,
enum bb_path tx_path,
enum bb_path rx_path,
boolean is_tx2_path)
__odm_func__
void
phydm_config_cck_tx_path_8822b(struct dm_struct *dm, enum bb_path tx_path)
{
u32 rf_reg33 = 0;
u16 counter = 0;
PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s ======> TX:0x%x, RX:0x%x\n", __func__,
tx_path, rx_path);
if (dm->is_disable_phy_api) {
PHYDM_DBG(dm, ODM_PHY_CONFIG, "disable PHY API\n");
return true;
}
if (((tx_path & ~BB_PATH_AB) != 0) || ((rx_path & ~BB_PATH_AB) != 0)) {
PHYDM_DBG(dm, ODM_PHY_CONFIG, "Wrong set\n");
return false;
}
/* @[mode table] RF mode of path-A and path-B */
/* @Cannot shut down path-A, beacause synthesizer will be shut down */
/* when path-A is in shut down mode */
/* @3-wire setting */
/* @0: shutdown, 1: standby, 2: TX, 3: RX */
if ((tx_path | rx_path) & BB_PATH_A)
odm_set_bb_reg(dm, R_0xc08, MASKLWORD, 0x3231);
if (tx_path == BB_PATH_A)
odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x8);
else if (tx_path == BB_PATH_B)
odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x4);
else
odm_set_bb_reg(dm, R_0xc08, MASKLWORD, 0x1111);
odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0xc);
}
if ((tx_path | rx_path) & BB_PATH_B)
odm_set_bb_reg(dm, R_0xe08, MASKLWORD, 0x3231);
else
odm_set_bb_reg(dm, R_0xe08, MASKLWORD, 0x1111);
__odm_func__
void
phydm_config_ofdm_tx_path_8822b(struct dm_struct *dm, enum bb_path tx_path_en,
enum bb_path tx_path_sel_1ss)
{
/* @Set TX logic map and TX path_en*/
if (tx_path_en == BB_PATH_A) { /* @1T, 1ss */
odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x001);
} else if (tx_path_en == BB_PATH_B) {
odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x002);
} else { /*BB_PATH_AB*/
if (tx_path_sel_1ss == BB_PATH_A) {
odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x001);
odm_set_bb_reg(dm, R_0x940, 0xfff0, 0x043);
} else if (tx_path_sel_1ss == BB_PATH_B) {
odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x002);
odm_set_bb_reg(dm, R_0x940, 0xfff0, 0x043);
} else { /*BB_PATH_AB*/
odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x043);
odm_set_bb_reg(dm, R_0x940, 0xfff0, 0x043);
}
}
#if 1
/* @TX logic map and TX path en for Nsts = 2*/
/*
* @Due to LO is stand-by while 1T at path-b in normal driver,
* @so 0x940 is the same setting btw path-A/B
*/
if (tx_path_en == BB_PATH_A || tx_path_en == BB_PATH_B) {
odm_set_bb_reg(dm, R_0x940, 0xf0, 0x1);
odm_set_bb_reg(dm, R_0x940, 0xff00, 0x0);
}
#endif
}
/*@[TX Antenna Setting] ==========================================*/
__iram_odm_func__
void phydm_config_tx_path_8822b(struct dm_struct *dm, enum bb_path tx_path,
enum bb_path tx_path_sel_1ss,
enum bb_path tx_path_sel_cck)
{
dm->tx_ant_status = (u8)tx_path;
dm->tx_1ss_status = tx_path_sel_1ss;
/* Set TX antenna by Nsts */
odm_set_bb_reg(dm, R_0x93c, (BIT(19) | BIT(18)), 0x3);
@@ -2337,7 +2358,16 @@ config_phydm_trx_mode_8822b(struct dm_struct *dm,
/* @Control CCK TX path by 0xa07[7] */
odm_set_bb_reg(dm, R_0x80c, BIT(30), 0x1);
/* TX path HW block enable */
odm_set_bb_reg(dm, R_0x80c, MASKBYTE0, (tx_path << 4) | tx_path);
/*---- [CCK] ----*/
phydm_config_cck_tx_path_8822b(dm, tx_path_sel_cck);
/*---- [OFDM] ----*/
#if 1
phydm_config_ofdm_tx_path_8822b(dm, tx_path, tx_path_sel_1ss);
#else
/* TX logic map and TX path en for Nsts = 1, and CCK TX path*/
if (tx_path & BB_PATH_A) {
odm_set_bb_reg(dm, R_0x93c, 0xfff00000, 0x001);
@@ -2355,8 +2385,6 @@ config_phydm_trx_mode_8822b(struct dm_struct *dm,
else
odm_set_bb_reg(dm, R_0x940, 0xfff0, 0x43);
/* TX path HW block enable */
odm_set_bb_reg(dm, R_0x80c, MASKBYTE0, ((tx_path << 4) | tx_path));
/* Tx2path for 1ss */
if (!(tx_path == BB_PATH_A || tx_path == BB_PATH_B)) {
@@ -2367,8 +2395,13 @@ config_phydm_trx_mode_8822b(struct dm_struct *dm,
odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0xc);
}
}
#endif
}
/*@[RX Antenna Setting] ==========================================*/
__iram_odm_func__
void phydm_config_rx_path_8822b(struct dm_struct *dm, enum bb_path rx_path)
{
dm->rx_ant_status = (u8)rx_path;
/*@Disable MRC for CCK CCA */
odm_set_bb_reg(dm, R_0xa2c, BIT(22), 0x0);
@@ -2382,66 +2415,93 @@ config_phydm_trx_mode_8822b(struct dm_struct *dm,
odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x5); /*@01,01*/
/* RX path enable */
odm_set_bb_reg(dm, R_0x808, MASKBYTE0, ((rx_path << 4) | rx_path));
odm_set_bb_reg(dm, R_0x808, MASKBYTE0, (rx_path << 4) | rx_path);
if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
/* @1R */
#if 0
/* @Disable MRC for CCA */
/* odm_set_bb_reg(dm, R_0xa2c, BIT22, 0x0); */
#endif
#if 0
/* @Disable MRC for barker */
/* odm_set_bb_reg(dm, R_0xa2c, BIT18, 0x0); */
#endif
#if 0
/* @Disable CCK antenna diversity */
/* odm_set_bb_reg(dm, R_0xa00, BIT15, 0x0); */
#endif
/* @Disable Antenna weighting */
/*@AntWgt_en*/
odm_set_bb_reg(dm, R_0x1904, BIT(16), 0x0);
/*@htstf ant-wgt enable = 0*/
/* @htstf ant-wgt enable = 0*/
odm_set_bb_reg(dm, R_0x800, BIT(28), 0x0);
/*@MRC_mode = 'original ZF eqz'*/
/* @MRC_mode = 'original ZF eqz'*/
odm_set_bb_reg(dm, R_0x850, BIT(23), 0x0);
} else {
/* @2R */
#if 0
/* @Enable MRC for CCA */
/* odm_set_bb_reg(dm, R_0xa2c, BIT22, 0x1); */
#endif
#if 0
/* @Enable MRC for barker */
/* odm_set_bb_reg(dm, R_0xa2c, BIT18, 0x1); */
#endif
#if 0
/* @Disable CCK antenna diversity */
/* odm_set_bb_reg(dm, R_0xa00, BIT15, 0x0); */
#endif
/* @Enable Antenna weighting */
/*@AntWgt_en*/
odm_set_bb_reg(dm, R_0x1904, BIT(16), 0x1);
/*@htstf ant-wgt enable = 1*/
/* @htstf ant-wgt enable = 1*/
odm_set_bb_reg(dm, R_0x800, BIT(28), 0x1);
/*@MRC_mode = 'modified ZF eqz'*/
/* @MRC_mode = 'modified ZF eqz'*/
odm_set_bb_reg(dm, R_0x850, BIT(23), 0x1);
}
}
/* Update TXRX antenna status for PHYDM */
dm->tx_ant_status = (tx_path & 0x3);
dm->rx_ant_status = (rx_path & 0x3);
__iram_odm_func__
boolean
config_phydm_trx_mode_8822b(struct dm_struct *dm,
enum bb_path tx_path_en,
enum bb_path rx_path,
enum bb_path tx_path_sel_1ss)
{
#ifdef CONFIG_PATH_DIVERSITY
struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
#endif
u32 rf_reg33 = 0;
u16 counter = 0;
PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s ======> TX:0x%x, RX:0x%x\n", __func__,
tx_path_en, rx_path);
if (dm->is_disable_phy_api) {
PHYDM_DBG(dm, ODM_PHY_CONFIG, "disable PHY API\n");
return true;
}
if ((tx_path_en & ~BB_PATH_AB) || (rx_path & ~BB_PATH_AB)) {
PHYDM_DBG(dm, ODM_PHY_CONFIG, "Wrong set\n");
return false;
}
/* @[mode table] RF mode of path-A and path-B
* Cannot shut down path-A, beacause synthesizer will be shut down
* when path-A is in shut down mode
*/
/* @[3-wire setting]
* 0:shutdown, 1:standby, 2:TX, 3:RX
*/
if ((tx_path_en | rx_path) & BB_PATH_A)
odm_set_bb_reg(dm, R_0xc08, MASKLWORD, 0x3231);
else
odm_set_bb_reg(dm, R_0xc08, MASKLWORD, 0x1111);
if ((tx_path_en | rx_path) & BB_PATH_B)
odm_set_bb_reg(dm, R_0xe08, MASKLWORD, 0x3231);
else
odm_set_bb_reg(dm, R_0xe08, MASKLWORD, 0x1111);
#ifdef CONFIG_PATH_DIVERSITY
if (tx_path_en == BB_PATH_A || tx_path_en == BB_PATH_B) {
p_div->stop_path_div = true;
tx_path_sel_1ss = tx_path_en;
} else if (tx_path_en == BB_PATH_AB) {
if (tx_path_sel_1ss == BB_PATH_AUTO) {
p_div->stop_path_div = false;
tx_path_sel_1ss = p_div->default_tx_path;
} else { /* @BB_PATH_AB, BB_PATH_A, BB_PATH_B*/
p_div->stop_path_div = true;
}
}
#else
tx_path_sel_1ss = tx_path_en;
#endif
/*@[TX Antenna Setting] ==========================================*/
phydm_config_tx_path_8822b(dm, tx_path_en,
tx_path_sel_1ss, tx_path_sel_1ss);
/*@[RX Antenna Setting] ==========================================*/
phydm_config_rx_path_8822b(dm, rx_path);
/* @MP driver need to support path-B TX\RX */
while (1) {
counter++;
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREG_MASK, 0x80000);
@@ -2461,7 +2521,8 @@ config_phydm_trx_mode_8822b(struct dm_struct *dm,
}
}
if (*dm->mp_mode || (*dm->antenna_test) || dm->normal_rx_path) {
if (*dm->mp_mode || *dm->antenna_test || dm->normal_rx_path ||
tx_path_sel_1ss == BB_PATH_B || tx_path_sel_1ss == BB_PATH_AUTO) {
/* @0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080e */
/* @0xef 0x00000 suggested by Lucas*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREG_MASK, 0x80000);
@@ -2512,17 +2573,6 @@ config_phydm_parameter_init_8822b(struct dm_struct *dm,
odm_set_bb_reg(dm, R_0x808, (BIT(28) | BIT(29)), 0x3);
PHYDM_DBG(dm, ODM_PHY_CONFIG,
"Post set: enable OFDM/CCK block\n");
#if (PHYDM_FW_API_FUNC_ENABLE_8822B == 1)
} else if (type == ODM_INIT_FW_SETTING) {
u8 h2c_content[4] = {0};
h2c_content[0] = dm->rfe_type;
h2c_content[1] = dm->rf_type;
h2c_content[2] = dm->cut_version;
h2c_content[3] = (dm->tx_ant_status << 4) | dm->rx_ant_status;
odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_GENERAL_INIT, 4, h2c_content);
#endif
} else {
PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: Wrong type!!\n", __func__);
return false;

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