RinCat/RTL88x2BU-Linux-Driver
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Update to 5.8.7.1

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Rin Cat
2020-08-02 05:12:24 -04:00
parent 314b662331
commit e3b09b28f7
449 changed files with 106089 additions and 83748 deletions
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53
hal/btc/btc_basic_types.h Normal file
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@@ -0,0 +1,53 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __BTC_BASIC_TYPES_H__
#define __BTC_BASIC_TYPES_H__
#define IN
#define OUT
#define VOID void
typedef void *PVOID;
#define u1Byte u8
#define pu1Byte u8*
#define u2Byte u16
#define pu2Byte u16*
#define u4Byte u32
#define pu4Byte u32*
#define u8Byte u64
#define pu8Byte u64*
#define s1Byte s8
#define ps1Byte s8*
#define s2Byte s16
#define ps2Byte s16*
#define s4Byte s32
#define ps4Byte s32*
#define s8Byte s64
#define ps8Byte s64*
#define UCHAR u8
#define USHORT u16
#define UINT u32
#define ULONG u32
#define PULONG u32*
#endif /* __BTC_BASIC_TYPES_H__ */

1836
hal/btc/halbtc8822b1ant.c
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File diff suppressed because it is too large Load Diff

23
hal/btc/halbtc8822b1ant.h
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@@ -78,6 +78,8 @@ enum bt_info_src_8822b_1ant {
BT_8822B_1ANT_INFO_SRC_WIFI_FW = 0x0,
BT_8822B_1ANT_INFO_SRC_BT_RSP = 0x1,
BT_8822B_1ANT_INFO_SRC_BT_ACT = 0x2,
BT_8822B_1ANT_INFO_SRC_BT_IQK = 0x3,
BT_8822B_1ANT_INFO_SRC_BT_SCBD = 0x4,
BT_8822B_1ANT_INFO_SRC_MAX
};
@@ -168,7 +170,9 @@ enum bt_8822b_1ant_scoreboard {
BT_8822B_1ANT_SCBD_RXGAIN = BIT(4),
BT_8822B_1ANT_SCBD_WLBUSY = BIT(6),
BT_8822B_1ANT_SCBD_EXTFEM = BIT(8),
BT_8822B_1ANT_SCBD_CQDDR = BIT(10)
BT_8822B_1ANT_SCBD_TDMA = BIT(9),
BT_8822B_1ANT_SCBD_CQDDR = BIT(10),
BT_8822B_1ANT_SCBD_ALL = 0xffff
};
enum bt_8822b_1ant_RUNREASON {
@@ -252,6 +256,7 @@ struct coex_sta_8822b_1ant {
boolean hid_exist;
boolean pan_exist;
boolean msft_mr_exist;
boolean bt_a2dp_active;
u8 num_of_profile;
boolean under_lps;
@@ -309,7 +314,7 @@ struct coex_sta_8822b_1ant {
u8 isolation_btween_wb; /* 0~ 50 */
u8 a2dp_bit_pool;
u8 cut_version;
u8 kt_ver;
boolean acl_busy;
boolean bt_create_connection;
@@ -324,6 +329,8 @@ struct coex_sta_8822b_1ant {
boolean is_A2DP_3M;
boolean voice_over_HOGP;
boolean bt_418_hid_exist;
boolean bt_ble_hid_exist;
u8 forbidden_slot;
u8 hid_busy_num;
u8 hid_pair_cnt;
@@ -334,6 +341,7 @@ struct coex_sta_8822b_1ant {
u32 cnt_ign_wlan_act;
u32 cnt_page;
u32 cnt_role_switch;
u32 cnt_wl_fw_notify;
u16 bt_reg_vendor_ac;
u16 bt_reg_vendor_ae;
@@ -344,12 +352,9 @@ struct coex_sta_8822b_1ant {
u8 bt_afh_map[10];
u8 bt_relink_downcount;
boolean is_tdma_btautoslot;
boolean is_tdma_btautoslot_hang;
u8 switch_band_notify_to;
boolean is_rf_state_off;
boolean is_hid_low_pri_tx_overhead;
boolean is_bt_multi_link;
boolean is_bt_a2dp_sink;
@@ -364,10 +369,13 @@ struct coex_sta_8822b_1ant {
u8 wl_tx_macid;
u8 wl_tx_retry_ratio;
boolean is_2g_freerun;
u16 score_board_WB;
boolean is_hid_rcu;
u8 bt_a2dp_vendor_id;
u32 bt_a2dp_device_name;
u32 bt_a2dp_flush_time;
boolean is_ble_scan_en;
boolean is_bt_opp_exist;
@@ -394,6 +402,10 @@ struct coex_sta_8822b_1ant {
boolean wl_rxagg_limit_en;
u8 wl_rxagg_size;
u8 coex_run_reason;
u8 tdma_timer_base;
boolean wl_slot_toggle;
boolean wl_slot_toggle_change; /* if toggle to no-toggle */
};
struct rfe_type_8822b_1ant {
@@ -410,6 +422,7 @@ struct wifi_link_info_8822b_1ant {
boolean is_all_under_5g;
boolean is_mcc_25g;
boolean is_p2p_connected;
boolean is_connected;
};
/* *******************************************

2056
hal/btc/halbtc8822b2ant.c
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File diff suppressed because it is too large Load Diff

25
hal/btc/halbtc8822b2ant.h
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@@ -100,6 +100,8 @@ enum bt_info_src_8822b_2ant {
BT_8822B_2ANT_INFO_SRC_WIFI_FW = 0x0,
BT_8822B_2ANT_INFO_SRC_BT_RSP = 0x1,
BT_8822B_2ANT_INFO_SRC_BT_ACT = 0x2,
BT_8822B_2ANT_INFO_SRC_BT_IQK = 0x3,
BT_8822B_2ANT_INFO_SRC_BT_SCBD = 0x4,
BT_8822B_2ANT_INFO_SRC_MAX
};
@@ -179,7 +181,9 @@ enum bt_8822b_2ant_scoreboard {
BT_8822B_2ANT_SCBD_RXGAIN = BIT(4),
BT_8822B_2ANT_SCBD_WLBUSY = BIT(6),
BT_8822B_2ANT_SCBD_EXTFEM = BIT(8),
BT_8822B_2ANT_SCBD_CQDDR = BIT(10)
BT_8822B_2ANT_SCBD_TDMA = BIT(9),
BT_8822B_2ANT_SCBD_CQDDR = BIT(10),
BT_8822B_2ANT_SCBD_ALL = 0xffff
};
enum bt_8822b_2ant_RUNREASON {
@@ -247,11 +251,9 @@ struct coex_dm_8822b_2ant {
u8 cur_lps;
u8 cur_rpwm;
boolean is_switch_to_1dot5_ant;
u32 arp_cnt;
u32 cur_ext_ant_switch_status;
u32 cur_switch_status;
u32 setting_tdma;
};
@@ -263,6 +265,7 @@ struct coex_sta_8822b_2ant {
boolean hid_exist;
boolean pan_exist;
boolean msft_mr_exist;
boolean bt_a2dp_active;
boolean under_lps;
boolean under_ips;
@@ -310,7 +313,7 @@ struct coex_sta_8822b_2ant {
u8 dis_ver_info_cnt;
u8 a2dp_bit_pool;
u8 cut_version;
u8 kt_ver;
boolean concurrent_rx_mode_on;
@@ -338,6 +341,8 @@ struct coex_sta_8822b_2ant {
boolean is_A2DP_3M;
boolean voice_over_HOGP;
boolean bt_418_hid_exist;
boolean bt_ble_hid_exist;
boolean is_autoslot;
u8 forbidden_slot;
u8 hid_busy_num;
@@ -349,6 +354,7 @@ struct coex_sta_8822b_2ant {
u32 cnt_ign_wlan_act;
u32 cnt_page;
u32 cnt_role_switch;
u32 cnt_wl_fw_notify;
u16 bt_reg_vendor_ac;
u16 bt_reg_vendor_ae;
@@ -360,13 +366,10 @@ struct coex_sta_8822b_2ant {
u8 bt_afh_map[10];
u8 bt_relink_downcount;
boolean is_tdma_btautoslot;
boolean is_tdma_btautoslot_hang;
boolean is_esco_mode;
u8 switch_band_notify_to;
boolean is_rf_state_off;
boolean is_hid_low_pri_tx_overhead;
boolean is_bt_multi_link;
boolean is_bt_a2dp_sink;
@@ -387,6 +390,7 @@ struct coex_sta_8822b_2ant {
boolean is_hid_rcu;
u8 bt_a2dp_vendor_id;
u32 bt_a2dp_device_name;
u32 bt_a2dp_flush_time;
boolean is_ble_scan_en;
boolean is_bt_opp_exist;
@@ -413,6 +417,10 @@ struct coex_sta_8822b_2ant {
boolean wl_rxagg_limit_en;
u8 wl_rxagg_size;
u8 coex_run_reason;
u8 tdma_timer_base;
boolean wl_slot_toggle;
boolean wl_slot_toggle_change; /* if toggle to no-toggle */
};
#define BT_8822B_2ANT_EXT_BAND_SWITCH_USE_DPDT 0
@@ -441,6 +449,7 @@ struct wifi_link_info_8822b_2ant {
boolean is_all_under_5g;
boolean is_mcc_25g;
boolean is_p2p_connected;
boolean is_connected;
};
/* *******************************************

6
hal/btc/halbtc8822bwifionly.c
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@@ -17,7 +17,7 @@
VOID
ex_hal8822b_wifi_only_hw_config(
IN struct wifi_only_cfg *pwifionlycfg
IN struct wifi_only_cfg *pwifionlycfg
)
{
/*BB control*/
@@ -35,9 +35,6 @@ ex_hal8822b_wifi_only_hw_config(
/*gnt_wl=1 , gnt_bt=0*/
halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff, 0x7700);
halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff, 0xc00f0038);
halwifionly_phy_set_bb_reg(pwifionlycfg, 0x6c0, 0xffffffff, 0xaaaaaaaa);
halwifionly_phy_set_bb_reg(pwifionlycfg, 0x6c4, 0xffffffff, 0xaaaaaaaa);
}
VOID
@@ -67,6 +64,7 @@ ex_hal8822b_wifi_only_connectnotify(
hal8822b_wifi_only_switch_antenna(pwifionlycfg, is_5g);
}
VOID
hal8822b_wifi_only_switch_antenna(IN struct wifi_only_cfg *pwifionlycfg,
IN u1Byte is_5g

759
hal/btc/halbtcoutsrc.h
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@@ -116,6 +116,7 @@ enum {
BTC_MULTIPORT_MAX
};
#define BTC_COEX_8822B_COMMON_CODE 0
#define BTC_COEX_OFFLOAD 0
#define BTC_TMP_BUF_SHORT 20
@@ -204,6 +205,13 @@ typedef enum _BTC_CHIP_TYPE {
BTC_CHIP_RTL8723A = 3,
BTC_CHIP_RTL8821 = 4,
BTC_CHIP_RTL8723B = 5,
BTC_CHIP_RTL8822B = 6,
BTC_CHIP_RTL8822C = 7,
BTC_CHIP_RTL8821C = 8,
BTC_CHIP_RTL8821A = 9,
BTC_CHIP_RTL8723D = 10,
BTC_CHIP_RTL8703B = 11,
BTC_CHIP_RTL8725A = 12,
BTC_CHIP_MAX
} BTC_CHIP_TYPE, *PBTC_CHIP_TYPE;
@@ -219,6 +227,397 @@ typedef enum _BTC_CHIP_TYPE {
#define CL_PRINTF DCMD_Printf
#define CL_STRNCAT(dst, dst_size, src, src_size) rstrncat(dst, src, src_size)
static const char *const glbt_info_src[] = {
"BT Info[wifi fw]",
"BT Info[bt rsp]",
"BT Info[bt auto report]",
};
#define TDMA_4SLOT BIT(8)
#define BTC_INFO_FTP BIT(7)
#define BTC_INFO_A2DP BIT(6)
#define BTC_INFO_HID BIT(5)
#define BTC_INFO_SCO_BUSY BIT(4)
#define BTC_INFO_ACL_BUSY BIT(3)
#define BTC_INFO_INQ_PAGE BIT(2)
#define BTC_INFO_SCO_ESCO BIT(1)
#define BTC_INFO_CONNECTION BIT(0)
#define BTC_BTINFO_LENGTH_MAX 10
enum btc_gnt_setup_state {
BTC_GNT_SET_SW_LOW = 0x0,
BTC_GNT_SET_SW_HIGH = 0x1,
BTC_GNT_SET_HW_PTA = 0x2,
BTC_GNT_SET_MAX
};
enum btc_gnt_setup_state_2 {
BTC_GNT_SW_LOW = 0x0,
BTC_GNT_SW_HIGH = 0x1,
BTC_GNT_HW_PTA = 0x2,
BTC_GNT_MAX
};
enum btc_path_ctrl_owner {
BTC_OWNER_BT = 0x0,
BTC_OWNER_WL = 0x1,
BTC_OWNER_MAX
};
enum btc_gnt_ctrl_type {
BTC_GNT_CTRL_BY_PTA = 0x0,
BTC_GNT_CTRL_BY_SW = 0x1,
BTC_GNT_CTRL_MAX
};
enum btc_gnt_ctrl_block {
BTC_GNT_BLOCK_RFC_BB = 0x0,
BTC_GNT_BLOCK_RFC = 0x1,
BTC_GNT_BLOCK_BB = 0x2,
BTC_GNT_BLOCK_MAX
};
enum btc_lte_coex_table_type {
BTC_CTT_WL_VS_LTE = 0x0,
BTC_CTT_BT_VS_LTE = 0x1,
BTC_CTT_MAX
};
enum btc_lte_break_table_type {
BTC_LBTT_WL_BREAK_LTE = 0x0,
BTC_LBTT_BT_BREAK_LTE = 0x1,
BTC_LBTT_LTE_BREAK_WL = 0x2,
BTC_LBTT_LTE_BREAK_BT = 0x3,
BTC_LBTT_MAX
};
enum btc_btinfo_src {
BTC_BTINFO_SRC_WL_FW = 0x0,
BTC_BTINFO_SRC_BT_RSP = 0x1,
BTC_BTINFO_SRC_BT_ACT = 0x2,
BTC_BTINFO_SRC_BT_IQK = 0x3,
BTC_BTINFO_SRC_BT_SCBD = 0x4,
BTC_BTINFO_SRC_H2C60 = 0x5,
BTC_BTINFO_SRC_MAX
};
enum btc_bt_profile {
BTC_BTPROFILE_NONE = 0,
BTC_BTPROFILE_HFP = BIT(0),
BTC_BTPROFILE_HID = BIT(1),
BTC_BTPROFILE_A2DP = BIT(2),
BTC_BTPROFILE_PAN = BIT(3),
BTC_BTPROFILE_MAX = 0xf
};
static const char *const bt_profile_string[] = {
"None",
"HFP",
"HID",
"HID + HFP",
"A2DP",
"A2DP + HFP",
"A2DP + HID",
"PAN + HID + HFP",
"PAN",
"PAN + HFP",
"PAN + HID",
"PAN + HID + HFP",
"PAN + A2DP",
"PAN + A2DP + HFP",
"PAN + A2DP + HID",
"PAN + A2DP + HID + HFP"
};
enum btc_bt_status {
BTC_BTSTATUS_NCON_IDLE = 0x0,
BTC_BTSTATUS_CON_IDLE = 0x1,
BTC_BTSTATUS_INQ_PAGE = 0x2,
BTC_BTSTATUS_ACL_BUSY = 0x3,
BTC_BTSTATUS_SCO_BUSY = 0x4,
BTC_BTSTATUS_ACL_SCO_BUSY = 0x5,
BTC_BTSTATUS_MAX
};
static const char *const bt_status_string[] = {
"BT Non-Connected-idle",
"BT Connected-idle",
"BT Inq-page",
"BT ACL-busy",
"BT SCO-busy",
"BT ACL-SCO-busy",
"BT Non-Defined-state"
};
enum btc_coex_algo {
BTC_COEX_NOPROFILE = 0x0,
BTC_COEX_HFP = 0x1,
BTC_COEX_HID = 0x2,
BTC_COEX_A2DP = 0x3,
BTC_COEX_PAN = 0x4,
BTC_COEX_A2DP_HID = 0x5,
BTC_COEX_A2DP_PAN = 0x6,
BTC_COEX_PAN_HID = 0x7,
BTC_COEX_A2DP_PAN_HID = 0x8,
BTC_COEX_MAX
};
static const char *const coex_algo_string[] = {
"No Profile",
"HFP",
"HID",
"A2DP",
"PAN",
"A2DP + HID",
"A2DP + PAN",
"PAN + HID",
"A2DP + PAN + HID"
};
enum btc_ext_ant_switch_type {
BTC_SWITCH_NONE = 0x0,
BTC_SWITCH_SPDT = 0x1,
BTC_SWITCH_SP3T = 0x2,
BTC_SWITCH_ANTMAX
};
enum btc_ext_ant_switch_ctrl_type {
BTC_SWITCH_CTRL_BY_BBSW = 0x0,
BTC_SWITCH_CTRL_BY_PTA = 0x1,
BTC_SWITCH_CTRL_BY_ANTDIV = 0x2,
BTC_SWITCH_CTRL_BY_MAC = 0x3,
BTC_SWITCH_CTRL_BY_BT = 0x4,
BTC_SWITCH_CTRL_BY_FW = 0x5,
BTC_SWITCH_CTRL_MAX
};
enum btc_ext_ant_switch_pos_type {
BTC_SWITCH_TO_BT = 0x0,
BTC_SWITCH_TO_WLG = 0x1,
BTC_SWITCH_TO_WLA = 0x2,
BTC_SWITCH_TO_NOCARE = 0x3,
BTC_SWITCH_TO_WLG_BT = 0x4,
BTC_SWITCH_TO_MAX
};
enum btx_set_ant_phase {
BTC_ANT_INIT = 0x0,
BTC_ANT_WONLY = 0x1,
BTC_ANT_WOFF = 0x2,
BTC_ANT_2G = 0x3,
BTC_ANT_5G = 0x4,
BTC_ANT_BTMP = 0x5,
BTC_ANT_POWERON = 0x6,
BTC_ANT_2G_WL = 0x7,
BTC_ANT_2G_BT = 0x8,
BTC_ANT_MCC = 0x9,
BTC_ANT_2G_WLBT = 0xa,
BTC_ANT_2G_FREERUN = 0xb,
BTC_ANT_MAX
};
/*ADD SCOREBOARD TO FIX BT LPS 32K ISSUE WHILE WL BUSY*/
enum btc_wl2bt_scoreboard {
BTC_SCBD_ACTIVE = BIT(0),
BTC_SCBD_ON = BIT(1),
BTC_SCBD_SCAN = BIT(2),
BTC_SCBD_UNDERTEST = BIT(3),
BTC_SCBD_RXGAIN = BIT(4),
BTC_SCBD_WLBUSY = BIT(7),
BTC_SCBD_EXTFEM = BIT(8),
BTC_SCBD_TDMA = BIT(9),
BTC_SCBD_FIX2M = BIT(10),
BTC_SCBD_ALL = 0xffff
};
enum btc_bt2wl_scoreboard {
BTC_SCBD_BT_ONOFF = BIT(1),
BTC_SCBD_BT_LPS = BIT(7)
};
enum btc_runreason {
BTC_RSN_2GSCANSTART = 0x0,
BTC_RSN_5GSCANSTART = 0x1,
BTC_RSN_SCANFINISH = 0x2,
BTC_RSN_2GSWITCHBAND = 0x3,
BTC_RSN_5GSWITCHBAND = 0x4,
BTC_RSN_2GCONSTART = 0x5,
BTC_RSN_5GCONSTART = 0x6,
BTC_RSN_2GCONFINISH = 0x7,
BTC_RSN_5GCONFINISH = 0x8,
BTC_RSN_2GMEDIA = 0x9,
BTC_RSN_5GMEDIA = 0xa,
BTC_RSN_MEDIADISCON = 0xb,
BTC_RSN_2GSPECIALPKT = 0xc,
BTC_RSN_5GSPECIALPKT = 0xd,
BTC_RSN_BTINFO = 0xe,
BTC_RSN_PERIODICAL = 0xf,
BTC_RSN_PNP = 0x10,
BTC_RSN_LPS = 0x11,
BTC_RSN_TIMERUP = 0x12,
BTC_RSN_WLSTATUS = 0x13,
BTC_RSN_MAX
};
static const char *const run_reason_string[] = {
"2G_SCAN_START",
"5G_SCAN_START",
"SCAN_FINISH",
"2G_SWITCH_BAND",
"5G_SWITCH_BAND",
"2G_CONNECT_START",
"5G_CONNECT_START",
"2G_CONNECT_FINISH",
"5G_CONNECT_FINISH",
"2G_MEDIA_STATUS",
"5G_MEDIA_STATUS",
"MEDIA_DISCONNECT",
"2G_SPECIALPKT",
"5G_SPECIALPKT",
"BTINFO",
"PERIODICAL",
"PNPNotify",
"LPSNotify",
"TimerUp",
"WL_STATUS_CHANGE",
};
enum btc_wl_link_mode {
BTC_WLINK_2G1PORT = 0x0,
BTC_WLINK_2GMPORT = 0x1,
BTC_WLINK_25GMPORT = 0x2,
BTC_WLINK_5G = 0x3,
BTC_WLINK_2GGO = 0x4,
BTC_WLINK_2GGC = 0x5,
BTC_WLINK_BTMR = 0x6,
BTC_WLINK_MAX
};
static const char *const coex_mode_string[] = {
"2G-SP",
"2G-MP",
"25G-MP",
"5G",
"2G-P2P-GO",
"2G-P2P-GC",
"BT-MR"
};
enum btc_bt_state_cnt {
BTC_CNT_BT_RETRY = 0x0,
BTC_CNT_BT_REINIT = 0x1,
BTC_CNT_BT_POPEVENT = 0x2,
BTC_CNT_BT_SETUPLINK = 0x3,
BTC_CNT_BT_IGNWLANACT = 0x4,
BTC_CNT_BT_INQ = 0x5,
BTC_CNT_BT_PAGE = 0x6,
BTC_CNT_BT_ROLESWITCH = 0x7,
BTC_CNT_BT_AFHUPDATE = 0x8,
BTC_CNT_BT_DISABLE = 0x9,
BTC_CNT_BT_INFOUPDATE = 0xa,
BTC_CNT_BT_IQK = 0xb,
BTC_CNT_BT_IQKFAIL = 0xc,
BTC_CNT_BT_MAX
};
enum btc_wl_state_cnt {
BTC_CNT_WL_SCANAP = 0x0,
BTC_CNT_WL_ARP = 0x1,
BTC_CNT_WL_GNTERR = 0x2,
BTC_CNT_WL_PSFAIL = 0x3,
BTC_CNT_WL_COEXRUN = 0x4,
BTC_CNT_WL_COEXINFO1 = 0x5,
BTC_CNT_WL_COEXINFO2 = 0x6,
BTC_CNT_WL_AUTOSLOT_HANG = 0x7,
BTC_CNT_WL_NOISY0 = 0x8,
BTC_CNT_WL_NOISY1 = 0x9,
BTC_CNT_WL_NOISY2 = 0xa,
BTC_CNT_WL_ACTIVEPORT = 0xb,
BTC_CNT_WL_5MS_NOEXTEND = 0xc,
BTC_CNT_WL_FW_NOTIFY = 0xd,
BTC_CNT_WL_MAX
};
enum btc_wl_crc_cnt {
BTC_WLCRC_11BOK = 0x0,
BTC_WLCRC_11GOK = 0x1,
BTC_WLCRC_11NOK = 0x2,
BTC_WLCRC_11VHTOK = 0x3,
BTC_WLCRC_11BERR = 0x4,
BTC_WLCRC_11GERR = 0x5,
BTC_WLCRC_11NERR = 0x6,
BTC_WLCRC_11VHTERR = 0x7,
BTC_WLCRC_MAX
};
enum btc_timer_cnt {
BTC_TIMER_WL_STAYBUSY = 0x0,
BTC_TIMER_WL_COEXFREEZE = 0x1,
BTC_TIMER_WL_SPECPKT = 0x2,
BTC_TIMER_WL_CONNPKT = 0x3,
BTC_TIMER_WL_PNPWAKEUP = 0x4,
BTC_TIMER_WL_CCKLOCK = 0x5,
BTC_TIMER_WL_FWDBG = 0x6,
BTC_TIMER_BT_RELINK = 0x7,
BTC_TIMER_BT_REENABLE = 0x8,
BTC_TIMER_BT_MULTILINK = 0x9,
BTC_TIMER_MAX
};
enum btc_wl_status_change {
BTC_WLSTATUS_CHANGE_TOIDLE = 0x0,
BTC_WLSTATUS_CHANGE_TOBUSY = 0x1,
BTC_WLSTATUS_CHANGE_RSSI = 0x2,
BTC_WLSTATUS_CHANGE_LINKINFO = 0x3,
BTC_WLSTATUS_CHANGE_DIR = 0x4,
BTC_WLSTATUS_CHANGE_NOISY = 0x5,
BTC_WLSTATUS_CHANGE_MAX
};
enum btc_commom_chip_setup {
BTC_CSETUP_INIT_HW = 0x0,
BTC_CSETUP_ANT_SWITCH = 0x1,
BTC_CSETUP_GNT_FIX = 0x2,
BTC_CSETUP_GNT_DEBUG = 0x3,
BTC_CSETUP_RFE_TYPE = 0x4,
BTC_CSETUP_COEXINFO_HW = 0x5,
BTC_CSETUP_WL_TX_POWER = 0x6,
BTC_CSETUP_WL_RX_GAIN = 0x7,
BTC_CSETUP_WLAN_ACT_IPS = 0x8,
BTC_CSETUP_MAX
};
enum btc_indirect_reg_type {
BTC_INDIRECT_1700 = 0x0,
BTC_INDIRECT_7C0 = 0x1,
BTC_INDIRECT_MAX
};
enum btc_pstdma_type {
BTC_PSTDMA_FORCE_LPSOFF = 0x0,
BTC_PSTDMA_FORCE_LPSON = 0x1,
BTC_PSTDMA_MAX
};
enum btc_btrssi_type {
BTC_BTRSSI_RATIO = 0x0,
BTC_BTRSSI_DBM = 0x1,
BTC_BTRSSI_MAX
};
enum btc_wl_priority_mask {
BTC_WLPRI_RX_RSP = 2,
BTC_WLPRI_TX_RSP = 3,
BTC_WLPRI_TX_BEACON = 4,
BTC_WLPRI_TX_OFDM = 11,
BTC_WLPRI_TX_CCK = 12,
BTC_WLPRI_TX_BEACONQ = 27,
BTC_WLPRI_RX_CCK = 28,
BTC_WLPRI_RX_OFDM = 29,
BTC_WLPRI_MAX
};
struct btc_board_info {
/* The following is some board information */
u8 bt_chip_type;
@@ -239,6 +638,231 @@ struct btc_board_info {
u32 antdetval;
u8 customerID;
u8 customer_id;
u8 ant_distance; /* WL-BT antenna space for non-shared antenna */
};
struct btc_coex_dm {
boolean cur_ignore_wlan_act;
boolean cur_ps_tdma_on;
boolean cur_low_penalty_ra;
boolean cur_wl_rx_low_gain_en;
u8 bt_rssi_state[4];
u8 wl_rssi_state[4];
u8 cur_ps_tdma;
u8 ps_tdma_para[5];
u8 fw_tdma_para[5];
u8 cur_lps;
u8 cur_rpwm;
u8 cur_bt_pwr_lvl;
u8 cur_bt_lna_lvl;
u8 cur_wl_pwr_lvl;
u8 cur_algorithm;
u8 bt_status;
u8 wl_chnl_info[3];
u8 cur_toggle_para[6];
u8 cur_val0x6cc;
u32 cur_val0x6c0;
u32 cur_val0x6c4;
u32 cur_val0x6c8;
u32 cur_ant_pos_type;
u32 cur_switch_status;
u32 setting_tdma;
};
struct btc_coex_sta {
boolean coex_freeze;
boolean coex_freerun;
boolean tdma_bt_autoslot;
boolean rf4ce_en;
boolean is_no_wl_5ms_extend;
boolean bt_disabled;
boolean bt_disabled_pre;
boolean bt_link_exist;
boolean bt_whck_test;
boolean bt_inq_page;
boolean bt_inq;
boolean bt_page;
boolean bt_ble_voice;
boolean bt_ble_exist;
boolean bt_hfp_exist;
boolean bt_a2dp_exist;
boolean bt_hid_exist;
boolean bt_pan_exist; // PAN or OPP
boolean bt_opp_exist; //OPP only
boolean bt_msft_mr_exist;
boolean bt_acl_busy;
boolean bt_fix_2M;
boolean bt_setup_link;
boolean bt_multi_link;
boolean bt_multi_link_pre;
boolean bt_multi_link_remain;
boolean bt_a2dp_sink;
boolean bt_reenable;
boolean bt_ble_scan_en;
boolean bt_slave;
boolean bt_a2dp_active;
boolean bt_slave_latency;
boolean bt_init_scan;
boolean bt_418_hid_exist;
boolean bt_ble_hid_exist;
boolean bt_mesh;
boolean wl_under_lps;
boolean wl_under_ips;
boolean wl_under_4way;
boolean wl_hi_pri_task1;
boolean wl_hi_pri_task2;
boolean wl_cck_lock;
boolean wl_cck_lock_pre;
boolean wl_cck_lock_ever;
boolean wl_force_lps_ctrl;
boolean wl_busy_pre;
boolean wl_gl_busy;
boolean wl_gl_busy_pre;
boolean wl_linkscan_proc;
boolean wl_mimo_ps;
boolean wl_ps_state_fail;
boolean wl_cck_dead_lock_ap;
boolean wl_tx_limit_en;
boolean wl_ampdu_limit_en;
boolean wl_rxagg_limit_en;
boolean wl_connecting;
boolean wl_pnp_wakeup;
boolean wl_slot_toggle;
boolean wl_slot_toggle_change; /* if toggle to no-toggle */
u8 coex_table_type;
u8 coex_run_reason;
u8 tdma_byte4_modify_pre;
u8 kt_ver;
u8 gnt_workaround_state;
u8 tdma_timer_base;
u8 bt_rssi;
u8 bt_profile_num;
u8 bt_profile_num_pre;
u8 bt_info_c2h[BTC_BTINFO_SRC_MAX][BTC_BTINFO_LENGTH_MAX];
u8 bt_info_lb2;
u8 bt_info_lb3;
u8 bt_info_hb0;
u8 bt_info_hb1;
u8 bt_info_hb2;
u8 bt_info_hb3;
u8 bt_ble_scan_type;
u8 bt_afh_map[10];
u8 bt_a2dp_vendor_id;
u8 bt_hid_pair_num;
u8 bt_hid_slot;
u8 bt_a2dp_bitpool;
u8 bt_iqk_state;
u8 bt_sut_pwr_lvl[4];
u8 bt_golden_rx_shift[4];
u8 bt_ext_autoslot_thres;
u8 wl_pnp_state_pre;
u8 wl_noisy_level;
u8 wl_fw_dbg_info[10];
u8 wl_fw_dbg_info_pre[10];
u8 wl_rx_rate;
u8 wl_tx_rate;
u8 wl_rts_rx_rate;
u8 wl_center_ch;
u8 wl_tx_macid;
u8 wl_tx_retry_ratio;
u8 wl_coex_mode;
u8 wl_iot_peer;
u8 wl_ra_thres;
u8 wl_ampdulen_backup;
u8 wl_rxagg_size;
u8 wl_toggle_para[6];
u16 score_board_BW;
u16 score_board_WB;
u16 bt_reg_vendor_ac;
u16 bt_reg_vendor_ae;
u16 bt_reg_modem_a;
u16 bt_reg_rf_2;
u16 wl_txlimit_backup;
u32 hi_pri_tx;
u32 hi_pri_rx;
u32 lo_pri_tx;
u32 lo_pri_rx;
u32 bt_supported_feature;
u32 bt_supported_version;
u32 bt_ble_scan_para[3];
u32 bt_a2dp_device_name;
u32 wl_arfb1_backup;
u32 wl_arfb2_backup;
u32 wl_traffic_dir;
u32 wl_bw;
u32 cnt_bt_info_c2h[BTC_BTINFO_SRC_MAX];
u32 cnt_bt[BTC_CNT_BT_MAX];
u32 cnt_wl[BTC_CNT_WL_MAX];
u32 cnt_timer[BTC_TIMER_MAX];
};
struct btc_rfe_type {
boolean ant_switch_exist;
boolean ant_switch_diversity; /* If diversity on */
boolean ant_switch_with_bt; /* If WL_2G/BT use ext-switch at shared-ant */
u8 rfe_module_type;
u8 ant_switch_type;
u8 ant_switch_polarity;
boolean band_switch_exist;
u8 band_switch_type; /* 0:DPDT, 1:SPDT */
u8 band_switch_polarity;
/* If TRUE: WLG at BTG, If FALSE: WLG at WLAG */
boolean wlg_at_btg;
};
struct btc_wifi_link_info_ext {
boolean is_all_under_5g;
boolean is_mcc_25g;
boolean is_p2p_connected;
boolean is_ap_mode;
boolean is_scan;
boolean is_link;
boolean is_roam;
boolean is_4way;
boolean is_32k;
boolean is_connected;
u8 num_of_active_port;
u32 port_connect_status;
u32 traffic_dir;
u32 wifi_bw;
};
struct btc_coex_table_para {
u32 bt; //0x6c0
u32 wl; //0x6c4
};
struct btc_tdma_para {
u8 para[5];
};
struct btc_reg_byte_modify {
u32 addr;
u8 bitmask;
u8 val;
};
struct btc_5g_afh_map {
u32 wl_5g_ch;
u8 bt_skip_ch;
u8 bt_skip_span;
};
struct btc_rf_para {
u8 wl_pwr_dec_lvl;
u8 bt_pwr_dec_lvl;
boolean wl_low_gain_en;
u8 bt_lna_lvl;
};
typedef enum _BTC_DBG_OPCODE {
@@ -383,7 +1007,9 @@ typedef enum _BTC_GET_TYPE {
/* type u4Byte */
BTC_GET_U4_WIFI_BW,
BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
BTC_GET_U4_WIFI_TRAFFIC_DIR,
BTC_GET_U4_WIFI_FW_VER,
BTC_GET_U4_WIFI_PHY_VER,
BTC_GET_U4_WIFI_LINK_STATUS,
BTC_GET_U4_BT_PATCH_VER,
BTC_GET_U4_VENDOR,
@@ -391,6 +1017,7 @@ typedef enum _BTC_GET_TYPE {
BTC_GET_U4_SUPPORTED_FEATURE,
BTC_GET_U4_BT_DEVICE_INFO,
BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL,
BTC_GET_U4_BT_A2DP_FLUSH_VAL,
BTC_GET_U4_WIFI_IQK_TOTAL,
BTC_GET_U4_WIFI_IQK_OK,
BTC_GET_U4_WIFI_IQK_FAIL,
@@ -428,6 +1055,7 @@ typedef enum _BTC_SET_TYPE {
BTC_SET_BL_BT_TX_RX_MASK,
BTC_SET_BL_MIRACAST_PLUS_BT,
BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL,
BTC_SET_BL_BT_GOLDEN_RX_RANGE,
/* type u1Byte */
BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
@@ -460,6 +1088,7 @@ typedef enum _BTC_SET_TYPE {
BTC_SET_ACT_CTRL_BT_INFO,
BTC_SET_ACT_CTRL_BT_COEX,
BTC_SET_ACT_CTRL_8723B_ANT,
BTC_SET_RESET_COEX_VAR,
/*=================*/
BTC_SET_MAX
} BTC_SET_TYPE, *PBTC_SET_TYPE;
@@ -675,6 +1304,7 @@ struct btc_wifi_link_info {
BOOLEAN bhotspot;
};
#if 0
typedef enum _BTC_MULTI_PORT_TDMA_MODE {
BTC_MULTI_PORT_TDMA_MODE_NONE=0,
BTC_MULTI_PORT_TDMA_MODE_2G_SCC_GO,
@@ -687,6 +1317,22 @@ typedef struct btc_multi_port_tdma_info {
u1Byte start_time_from_bcn;
u1Byte bt_time;
} BTC_MULTI_PORT_TDMA_INFO, *PBTC_MULTI_PORT_TDMA_INFO;
#endif
typedef enum _btc_concurrent_mode {
btc_concurrent_mode_none = 0,
btc_concurrent_mode_2g_go_miracast,
btc_concurrent_mode_2g_go_hotspot,
btc_concurrent_mode_2g_scc_go_miracast_sta,
btc_concurrent_mode_2g_scc_go_hotspot_sta,
btc_concurrent_mode_2g_gc,
} btc_concurrent_mode, *pbtc_concurrent_mode;
struct btc_concurrent_setting {
btc_concurrent_mode btc_concurrent_mode;
u1Byte start_time_from_bcn;
u1Byte bt_time;
};
typedef u1Byte
(*BFP_BTC_R1)(
@@ -734,6 +1380,29 @@ typedef VOID
IN u4Byte RegAddr,
IN u1Byte Data
);
typedef u4Byte
(*BFP_BTC_R_LINDIRECT)(
IN PVOID pBtcContext,
IN u2Byte reg_addr
);
typedef VOID
(*BFP_BTC_R_SCBD)(
IN PVOID pBtcContext,
IN pu2Byte score_board_val
);
typedef VOID
(*BFP_BTC_W_SCBD)(
IN PVOID pBtcContext,
IN u2Byte bitpos,
IN BOOLEAN state
);
typedef VOID
(*BFP_BTC_W_LINDIRECT)(
IN PVOID pBtcContext,
IN u2Byte reg_addr,
IN u4Byte bit_mask,
IN u4Byte reg_value
);
typedef VOID
(*BFP_BTC_SET_BB_REG)(
IN PVOID pBtcContext,
@@ -839,6 +1508,13 @@ typedef u4Byte
IN PVOID pBtcContext
);
typedef u1Byte
(*BFP_BTC_SET_TIMER) (
IN PVOID pBtcContext,
IN u4Byte type,
IN u4Byte val
);
typedef u4Byte
(*BFP_BTC_SET_ATOMIC) (
IN PVOID pBtcContext,
@@ -860,6 +1536,12 @@ typedef u4Byte
IN u1Byte info_type
);
typedef VOID
(*BTC_REDUCE_WL_TX_POWER)(
IN PVOID pDM_Odm,
IN s1Byte tx_power
);
typedef VOID
(*BTC_PHYDM_MODIFY_ANTDIV_HWSW)(
IN PVOID pDM_Odm,
@@ -906,8 +1588,7 @@ struct btc_bt_info {
boolean bt_busy;
boolean limited_dig;
u16 bt_hci_ver;
u16 bt_real_fw_ver;
u8 bt_fw_ver;
u32 bt_real_fw_ver;
u32 get_bt_fw_ver_cnt;
u32 bt_get_fw_ver;
boolean miracast_plus_bt;
@@ -989,6 +1670,11 @@ struct btc_coexist {
struct btc_stack_info stack_info;
struct btc_bt_link_info bt_link_info;
struct btc_wifi_link_info wifi_link_info;
struct btc_wifi_link_info_ext wifi_link_info_ext;
struct btc_coex_dm coex_dm;
struct btc_coex_sta coex_sta;
struct btc_rfe_type rfe_type;
const struct btc_chip_para *chip_para;
#ifdef CONFIG_RF4CE_COEXIST
struct btc_rf4ce_info rf4ce_info;
@@ -1005,6 +1691,8 @@ struct btc_coexist {
u1Byte pwrModeVal[10];
BOOLEAN dbg_mode;
BOOLEAN auto_report;
u8 chip_type;
BOOLEAN wl_rf_state_off;
/* function pointers */
/* io related */
@@ -1016,6 +1704,10 @@ struct btc_coexist {
BFP_BTC_R4 btc_read_4byte;
BFP_BTC_W4 btc_write_4byte;
BFP_BTC_LOCAL_REG_W1 btc_write_local_reg_1byte;
BFP_BTC_R_LINDIRECT btc_read_linderct;
BFP_BTC_W_LINDIRECT btc_write_linderct;
BFP_BTC_R_SCBD btc_read_scbd;
BFP_BTC_W_SCBD btc_write_scbd;
/* read/write bb related */
BFP_BTC_SET_BB_REG btc_set_bb_reg;
BFP_BTC_GET_BB_REG btc_get_bb_reg;
@@ -1042,9 +1734,11 @@ struct btc_coexist {
BFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE btc_get_bt_coex_supported_feature;
BFP_BTC_GET_BT_COEX_SUPPORTED_VERSION btc_get_bt_coex_supported_version;
BFP_BTC_GET_PHYDM_VERSION btc_get_bt_phydm_version;
BFP_BTC_SET_TIMER btc_set_timer;
BFP_BTC_SET_ATOMIC btc_set_atomic;
BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD btc_phydm_modify_RA_PCR_threshold;
BTC_PHYDM_CMNINFOQUERY btc_phydm_query_PHY_counter;
BTC_REDUCE_WL_TX_POWER btc_reduce_wl_tx_power;
BTC_PHYDM_MODIFY_ANTDIV_HWSW btc_phydm_modify_antdiv_hwsw;
BFP_BTC_GET_ANT_DET_VAL_FROM_BT btc_get_ant_det_val_from_bt;
BFP_BTC_GET_BLE_SCAN_TYPE_FROM_BT btc_get_ble_scan_type_from_bt;
@@ -1108,6 +1802,49 @@ typedef struct btc_coexist *PBTC_COEXIST;
extern struct btc_coexist GLBtCoexist;
typedef void
(*BFP_BTC_CHIP_SETUP)(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte setType
);
struct btc_chip_para {
const char *chip_name;
u32 para_ver_date;
u32 para_ver;
u32 bt_desired_ver;
boolean scbd_support;
boolean mailbox_support;
boolean lte_indirect_access;
boolean new_scbd10_def; /* TRUE: 1:fix 2M(8822c) */
u8 indirect_type; /* 0:17xx, 1:7cx */
u8 pstdma_type; /* 0: LPSoff, 1:LPSon */
u8 bt_rssi_type;
u8 ant_isolation;
u8 rssi_tolerance;
u8 rx_path_num;
u8 wl_rssi_step_num;
const u8 *wl_rssi_step;
u8 bt_rssi_step_num;
const u8 *bt_rssi_step;
u8 table_sant_num;
const struct btc_coex_table_para *table_sant;
u8 table_nsant_num;
const struct btc_coex_table_para *table_nsant;
u8 tdma_sant_num;
const struct btc_tdma_para *tdma_sant;
u8 tdma_nsant_num;
const struct btc_tdma_para *tdma_nsant;
u8 wl_rf_para_tx_num;
const struct btc_rf_para *wl_rf_para_tx;
const struct btc_rf_para *wl_rf_para_rx;
u8 bt_afh_span_bw20;
u8 bt_afh_span_bw40;
u8 afh_5g_num;
const struct btc_5g_afh_map *afh_5g;
BFP_BTC_CHIP_SETUP chip_setup;
};
BOOLEAN
EXhalbtcoutsrc_InitlizeVariables(
IN PVOID Adapter
@@ -1175,6 +1912,14 @@ EXhalbtcoutsrc_RfStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
u4Byte
EXhalbtcoutsrc_CoexTimerCheck(
IN PBTC_COEXIST pBtCoexist
);
u4Byte
EXhalbtcoutsrc_WLStatusCheck(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtcoutsrc_WlFwDbgInfoNotify(
IN PBTC_COEXIST pBtCoexist,
@@ -1202,6 +1947,16 @@ EXhalbtcoutsrc_PnpNotify(
IN u1Byte pnpState
);
VOID
EXhalbtcoutsrc_TimerNotify(
IN PBTC_COEXIST pBtCoexist,
IN u4Byte timer_type
);
VOID
EXhalbtcoutsrc_WLStatusChangeNotify(
IN PBTC_COEXIST pBtCoexist,
IN u4Byte change_type
);
VOID
EXhalbtcoutsrc_CoexDmSwitch(
IN PBTC_COEXIST pBtCoexist
);

27
hal/btc/mp_precomp.h
View File

@@ -17,6 +17,7 @@
#include <drv_types.h>
#include <hal_data.h>
#include "btc_basic_types.h"
#define BT_TMP_BUF_SIZE 100
@@ -111,6 +112,24 @@ struct btc_coexist;
#include "halbtc8821c2ant.h"
#endif
#ifdef CONFIG_RTL8814A
#include "halbtc8814a2ant.h"
#endif
#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
#include "halbtccommon.h"
#ifdef CONFIG_RTL8822C
#include "halbtc8822cwifionly.h"
#include "halbtc8822c.h"
#endif
#ifdef CONFIG_RTL8192F
#include "halbtc8192f.h"
#endif
#endif
#include "halbtcoutsrc.h"
#else /* CONFIG_BT_COEXIST */
@@ -127,6 +146,14 @@ struct btc_coexist;
#include "halbtc8821cwifionly.h"
#endif
#ifdef CONFIG_RTL8822C
#include "halbtc8822cwifionly.h"
#endif
#ifdef CONFIG_RTL8814B
#include "halbtc8814bwifionly.h"
#endif
#endif /* CONFIG_BT_COEXIST */
#endif /* __MP_PRECOMP_H__ */

17
hal/efuse/efuse_mask.h
View File

@@ -70,6 +70,12 @@
#if defined(CONFIG_RTL8192F)
#include "rtl8192f/HalEfuseMask8192F_USB.h"
#endif
#if defined(CONFIG_RTL8822C)
#include "rtl8822c/HalEfuseMask8822C_USB.h"
#endif
#if defined(CONFIG_RTL8814B)
#include "rtl8814b/HalEfuseMask8814B_USB.h"
#endif
#endif /*CONFIG_USB_HCI*/
#ifdef CONFIG_PCI_HCI
@@ -115,6 +121,12 @@
#if defined(CONFIG_RTL8192F)
#include "rtl8192f/HalEfuseMask8192F_PCIE.h"
#endif
#if defined(CONFIG_RTL8822C)
#include "rtl8822c/HalEfuseMask8822C_PCIE.h"
#endif
#if defined(CONFIG_RTL8814B)
#include "rtl8814b/HalEfuseMask8814B_PCIE.h"
#endif
#endif /*CONFIG_PCI_HCI*/
#ifdef CONFIG_SDIO_HCI
#if defined(CONFIG_RTL8723B)
@@ -161,4 +173,9 @@
#include "rtl8192f/HalEfuseMask8192F_SDIO.h"
#endif
#if defined(CONFIG_RTL8822C)
#include "rtl8822c/HalEfuseMask8822C_SDIO.h"
#endif
#endif /*CONFIG_SDIO_HCI*/

16
hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.c
View File

@@ -20,7 +20,7 @@
* MPCIE.TXT
******************************************************************************/
u1Byte Array_MP_8822B_MPCIE[] = {
u8 Array_MP_8822B_MPCIE[] = {
0xFF,
0xF7,
0xEF,
@@ -72,23 +72,23 @@ u1Byte Array_MP_8822B_MPCIE[] = {
};
u2Byte
EFUSE_GetArrayLen_MP_8822B_MPCIE(VOID)
u16
EFUSE_GetArrayLen_MP_8822B_MPCIE(void)
{
return sizeof(Array_MP_8822B_MPCIE) / sizeof(u1Byte);
return sizeof(Array_MP_8822B_MPCIE) / sizeof(u8);
}
VOID
EFUSE_GetMaskArray_MP_8822B_MPCIE(pu1Byte Array)
void
EFUSE_GetMaskArray_MP_8822B_MPCIE(u8 *Array)
{
u2Byte len = EFUSE_GetArrayLen_MP_8822B_MPCIE(), i = 0;
u16 len = EFUSE_GetArrayLen_MP_8822B_MPCIE(), i = 0;
for (i = 0; i < len; ++i)
Array[i] = Array_MP_8822B_MPCIE[i];
}
BOOLEAN
EFUSE_IsAddressMasked_MP_8822B_MPCIE(u2Byte Offset)
EFUSE_IsAddressMasked_MP_8822B_MPCIE(u16 Offset)
{
int r = Offset / 16;
int c = (Offset % 16) / 2;

6
hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.h
View File

@@ -19,8 +19,8 @@
******************************************************************************/
u2Byte EFUSE_GetArrayLen_MP_8822B_MPCIE(VOID);
u16 EFUSE_GetArrayLen_MP_8822B_MPCIE(void);
VOID EFUSE_GetMaskArray_MP_8822B_MPCIE(pu1Byte Array);
void EFUSE_GetMaskArray_MP_8822B_MPCIE(u8 *Array);
BOOLEAN EFUSE_IsAddressMasked_MP_8822B_MPCIE(u2Byte Offset);
BOOLEAN EFUSE_IsAddressMasked_MP_8822B_MPCIE(u16 Offset);

12
hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.c
View File

@@ -20,7 +20,7 @@
* MSDIO.TXT
******************************************************************************/
u1Byte Array_MP_8822B_MSDIO[] = {
u8 Array_MP_8822B_MSDIO[] = {
0xFF,
0xF7,
0xEF,
@@ -72,20 +72,20 @@ u1Byte Array_MP_8822B_MSDIO[] = {
};
u2Byte EFUSE_GetArrayLen_MP_8822B_MSDIO(VOID)
u16 EFUSE_GetArrayLen_MP_8822B_MSDIO(void)
{
return sizeof(Array_MP_8822B_MSDIO) / sizeof(u1Byte);
return sizeof(Array_MP_8822B_MSDIO) / sizeof(u8);
}
VOID EFUSE_GetMaskArray_MP_8822B_MSDIO(pu1Byte Array)
void EFUSE_GetMaskArray_MP_8822B_MSDIO(u8 *Array)
{
u2Byte len = EFUSE_GetArrayLen_MP_8822B_MSDIO(), i = 0;
u16 len = EFUSE_GetArrayLen_MP_8822B_MSDIO(), i = 0;
for (i = 0; i < len; ++i)
Array[i] = Array_MP_8822B_MSDIO[i];
}
BOOLEAN EFUSE_IsAddressMasked_MP_8822B_MSDIO(u2Byte Offset)
BOOLEAN EFUSE_IsAddressMasked_MP_8822B_MSDIO(u16 Offset)
{
int r = Offset / 16;
int c = (Offset % 16) / 2;

6
hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.h
View File

@@ -20,8 +20,8 @@
******************************************************************************/
u2Byte EFUSE_GetArrayLen_MP_8822B_MSDIO(VOID);
u16 EFUSE_GetArrayLen_MP_8822B_MSDIO(void);
VOID EFUSE_GetMaskArray_MP_8822B_MSDIO(pu1Byte Array);
void EFUSE_GetMaskArray_MP_8822B_MSDIO(u8 *Array);
BOOLEAN EFUSE_IsAddressMasked_MP_8822B_MSDIO(u2Byte Offset);
BOOLEAN EFUSE_IsAddressMasked_MP_8822B_MSDIO(u16 Offset);

12
hal/efuse/rtl8822b/HalEfuseMask8822B_USB.c
View File

@@ -20,7 +20,7 @@
* MUSB.TXT
******************************************************************************/
u1Byte Array_MP_8822B_MUSB[] = {
u8 Array_MP_8822B_MUSB[] = {
0xFF,
0xF7,
0xEF,
@@ -71,20 +71,20 @@ u1Byte Array_MP_8822B_MUSB[] = {
0x00,
};
u2Byte EFUSE_GetArrayLen_MP_8822B_MUSB(VOID)
u16 EFUSE_GetArrayLen_MP_8822B_MUSB(void)
{
return sizeof(Array_MP_8822B_MUSB) / sizeof(u1Byte);
return sizeof(Array_MP_8822B_MUSB) / sizeof(u8);
}
VOID EFUSE_GetMaskArray_MP_8822B_MUSB(pu1Byte Array)
void EFUSE_GetMaskArray_MP_8822B_MUSB(u8 *Array)
{
u2Byte len = EFUSE_GetArrayLen_MP_8822B_MUSB(), i = 0;
u16 len = EFUSE_GetArrayLen_MP_8822B_MUSB(), i = 0;
for (i = 0; i < len; ++i)
Array[i] = Array_MP_8822B_MUSB[i];
}
BOOLEAN EFUSE_IsAddressMasked_MP_8822B_MUSB(u2Byte Offset)
BOOLEAN EFUSE_IsAddressMasked_MP_8822B_MUSB(u16 Offset)
{
int r = Offset / 16;
int c = (Offset % 16) / 2;

6
hal/efuse/rtl8822b/HalEfuseMask8822B_USB.h
View File

@@ -20,8 +20,8 @@
******************************************************************************/
u2Byte EFUSE_GetArrayLen_MP_8822B_MUSB(VOID);
u16 EFUSE_GetArrayLen_MP_8822B_MUSB(void);
VOID EFUSE_GetMaskArray_MP_8822B_MUSB(pu1Byte Array);
void EFUSE_GetMaskArray_MP_8822B_MUSB(u8 *Array);
BOOLEAN EFUSE_IsAddressMasked_MP_8822B_MUSB(u2Byte Offset);
BOOLEAN EFUSE_IsAddressMasked_MP_8822B_MUSB(u16 Offset);

1020
hal/hal_btcoex.c
View File

File diff suppressed because it is too large Load Diff

58
hal/hal_btcoex_wifionly.c
View File

@@ -20,7 +20,7 @@
struct wifi_only_cfg GLBtCoexistWifiOnly;
void halwifionly_write1byte(PVOID pwifionlyContext, u32 RegAddr, u8 Data)
void halwifionly_write1byte(void *pwifionlyContext, u32 RegAddr, u8 Data)
{
struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
PADAPTER Adapter = pwifionlycfg->Adapter;
@@ -28,7 +28,7 @@ void halwifionly_write1byte(PVOID pwifionlyContext, u32 RegAddr, u8 Data)
rtw_write8(Adapter, RegAddr, Data);
}
void halwifionly_write2byte(PVOID pwifionlyContext, u32 RegAddr, u16 Data)
void halwifionly_write2byte(void *pwifionlyContext, u32 RegAddr, u16 Data)
{
struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
PADAPTER Adapter = pwifionlycfg->Adapter;
@@ -36,7 +36,7 @@ void halwifionly_write2byte(PVOID pwifionlyContext, u32 RegAddr, u16 Data)
rtw_write16(Adapter, RegAddr, Data);
}
void halwifionly_write4byte(PVOID pwifionlyContext, u32 RegAddr, u32 Data)
void halwifionly_write4byte(void *pwifionlyContext, u32 RegAddr, u32 Data)
{
struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
PADAPTER Adapter = pwifionlycfg->Adapter;
@@ -44,7 +44,7 @@ void halwifionly_write4byte(PVOID pwifionlyContext, u32 RegAddr, u32 Data)
rtw_write32(Adapter, RegAddr, Data);
}
u8 halwifionly_read1byte(PVOID pwifionlyContext, u32 RegAddr)
u8 halwifionly_read1byte(void *pwifionlyContext, u32 RegAddr)
{
struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
PADAPTER Adapter = pwifionlycfg->Adapter;
@@ -52,7 +52,7 @@ u8 halwifionly_read1byte(PVOID pwifionlyContext, u32 RegAddr)
return rtw_read8(Adapter, RegAddr);
}
u16 halwifionly_read2byte(PVOID pwifionlyContext, u32 RegAddr)
u16 halwifionly_read2byte(void * pwifionlyContext, u32 RegAddr)
{
struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
PADAPTER Adapter = pwifionlycfg->Adapter;
@@ -60,7 +60,7 @@ u16 halwifionly_read2byte(PVOID pwifionlyContext, u32 RegAddr)
return rtw_read16(Adapter, RegAddr);
}
u32 halwifionly_read4byte(PVOID pwifionlyContext, u32 RegAddr)
u32 halwifionly_read4byte(void *pwifionlyContext, u32 RegAddr)
{
struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
PADAPTER Adapter = pwifionlycfg->Adapter;
@@ -68,7 +68,7 @@ u32 halwifionly_read4byte(PVOID pwifionlyContext, u32 RegAddr)
return rtw_read32(Adapter, RegAddr);
}
void halwifionly_bitmaskwrite1byte(PVOID pwifionlyContext, u32 regAddr, u8 bitMask, u8 data)
void halwifionly_bitmaskwrite1byte(void *pwifionlyContext, u32 regAddr, u8 bitMask, u8 data)
{
u8 originalValue, bitShift = 0;
u8 i;
@@ -88,7 +88,7 @@ void halwifionly_bitmaskwrite1byte(PVOID pwifionlyContext, u32 regAddr, u8 bitMa
rtw_write8(Adapter, regAddr, data);
}
void halwifionly_phy_set_rf_reg(PVOID pwifionlyContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
void halwifionly_phy_set_rf_reg(void *pwifionlyContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
{
struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
PADAPTER Adapter = pwifionlycfg->Adapter;
@@ -96,7 +96,7 @@ void halwifionly_phy_set_rf_reg(PVOID pwifionlyContext, enum rf_path eRFPath, u3
phy_set_rf_reg(Adapter, eRFPath, RegAddr, BitMask, Data);
}
void halwifionly_phy_set_bb_reg(PVOID pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data)
void halwifionly_phy_set_bb_reg(void *pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data)
{
struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
PADAPTER Adapter = pwifionlycfg->Adapter;
@@ -122,6 +122,16 @@ void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter)
else if (IS_HARDWARE_TYPE_8821C(padapter))
ex_hal8821c_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);
#endif
#ifdef CONFIG_RTL8822C
else if (IS_HARDWARE_TYPE_8822C(padapter))
ex_hal8822c_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);
#endif
#ifdef CONFIG_RTL8814B
else if (IS_HARDWARE_TYPE_8814B(padapter))
ex_hal8814b_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);
#endif
}
void hal_btcoex_wifionly_scan_notify(PADAPTER padapter)
@@ -142,6 +152,16 @@ void hal_btcoex_wifionly_scan_notify(PADAPTER padapter)
else if (IS_HARDWARE_TYPE_8821C(padapter))
ex_hal8821c_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g);
#endif
#ifdef CONFIG_RTL8822C
else if (IS_HARDWARE_TYPE_8822C(padapter))
ex_hal8822c_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g);
#endif
#ifdef CONFIG_RTL8814B
else if (IS_HARDWARE_TYPE_8814B(padapter))
ex_hal8814b_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g);
#endif
}
void hal_btcoex_wifionly_connect_notify(PADAPTER padapter)
@@ -162,6 +182,16 @@ void hal_btcoex_wifionly_connect_notify(PADAPTER padapter)
else if (IS_HARDWARE_TYPE_8821C(padapter))
ex_hal8821c_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);
#endif
#ifdef CONFIG_RTL8822C
else if (IS_HARDWARE_TYPE_8822C(padapter))
ex_hal8822c_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);
#endif
#ifdef CONFIG_RTL8814B
else if (IS_HARDWARE_TYPE_8814B(padapter))
ex_hal8814b_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);
#endif
}
void hal_btcoex_wifionly_hw_config(PADAPTER padapter)
@@ -183,6 +213,16 @@ void hal_btcoex_wifionly_hw_config(PADAPTER padapter)
else if (IS_HARDWARE_TYPE_8821C(padapter))
ex_hal8821c_wifi_only_hw_config(pwifionlycfg);
#endif
#ifdef CONFIG_RTL8822C
else if (IS_HARDWARE_TYPE_8822C(padapter))
ex_hal8822c_wifi_only_hw_config(pwifionlycfg);
#endif
#ifdef CONFIG_RTL8814B
else if (IS_HARDWARE_TYPE_8814B(padapter))
ex_hal8814b_wifi_only_hw_config(pwifionlycfg);
#endif
}
void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter)

2308
hal/hal_com.c
View File

File diff suppressed because it is too large Load Diff

3
hal/hal_com_c2h.h
View File

@@ -100,6 +100,8 @@ int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len);
#define MAC_HIDDEN_RPT_2_LEN 5
int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len);
int hal_read_mac_hidden_rpt(_adapter *adapter);
#else
#define hal_read_mac_hidden_rpt(adapter) _SUCCESS
#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */
/* C2H_DEFEATURE_DBG, 0x22 */
@@ -126,5 +128,4 @@ int c2h_per_rate_rpt_hdl(_adapter *adapter, u8 *data, u8 len);
#define LPS_STATUS_RPT_LEN 2
int c2h_lps_status_rpt(PADAPTER adapter, u8 *data, u8 len);
#endif /* CONFIG_LPS_ACK */
#endif /* __COMMON_C2H_H__ */

1687
hal/hal_com_phycfg.c
View File

File diff suppressed because it is too large Load Diff

319
hal/hal_dm.c
View File

@@ -77,9 +77,16 @@ void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter)
phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
RTW_INFO("IQK FW offload:%s\n", hal->RegIQKFWOffload ? "enable" : "disable");
if (rtw_mi_check_status(adapter, MI_LINKED)) {
#ifdef CONFIG_LPS
LPS_Leave(adapter, "SWITCH_IQK_OFFLOAD");
#endif
halrf_iqk_trigger(p_dm_odm, _FALSE);
}
}
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
void rtw_phydm_iqk_trigger(_adapter *adapter)
{
struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
@@ -87,10 +94,15 @@ void rtw_phydm_iqk_trigger(_adapter *adapter)
u8 segment = _FALSE;
u8 rfk_forbidden = _FALSE;
/*segment = _rtw_phydm_iqk_segment_chk(adapter);*/
halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
#if (RTL8822C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1)
/* halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment); to do */
halrf_rf_k_connect_trigger(p_dm_odm, _TRUE, SEGMENT_FREE);
#else
/*segment = _rtw_phydm_iqk_segment_chk(adapter);*/
halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment);
halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
#endif
}
#endif
@@ -98,7 +110,7 @@ void rtw_phydm_iqk_trigger_dbg(_adapter *adapter, bool recovery, bool clear, boo
{
struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
#else
halrf_iqk_trigger(p_dm_odm, recovery);
@@ -229,6 +241,11 @@ void rtw_phydm_fill_desc_dpt(void *dm, u8 *desc, u8 dpt_lv)
break;
#endif
*/
#ifdef CONFIG_RTL8822B
case RTL8822B :
SET_TX_DESC_TXPWR_OFSET_8822B(desc, dpt_lv);
break;
#endif
#ifdef CONFIG_RTL8821C
case RTL8821C :
@@ -249,15 +266,34 @@ void rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id)
}
#endif
#ifdef CONFIG_RTW_TX_2PATH_EN
void rtw_phydm_tx_2path_en(_adapter *adapter)
#ifdef CONFIG_TDMADIG
void rtw_phydm_tdmadig(_adapter *adapter, u8 state)
{
struct registry_priv *pregistrypriv = &adapter->registrypriv;
struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
struct dm_struct *dm = adapter_to_phydm(adapter);
u8 tdma_dig_en;
phydm_tx_2path(dm);
switch (state) {
case TDMADIG_INIT:
phydm_tdma_dig_para_upd(dm, ENABLE_TDMA, pregistrypriv->tdmadig_en);
phydm_tdma_dig_para_upd(dm, MODE_DECISION, pregistrypriv->tdmadig_mode);
break;
case TDMADIG_NON_INIT:
if(pregistrypriv->tdmadig_dynamic) {
if(pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)
tdma_dig_en = 0;
else
tdma_dig_en = pregistrypriv->tdmadig_en;
phydm_tdma_dig_para_upd(dm, ENABLE_TDMA, tdma_dig_en);
}
break;
default:
break;
}
}
#endif
#endif/*CONFIG_TDMADIG*/
void rtw_phydm_ops_func_init(struct dm_struct *p_phydm)
{
struct ra_table *p_ra_t = &p_phydm->dm_ra_table;
@@ -334,7 +370,7 @@ void Init_ODM_ComInfo(_adapter *adapter)
rtw_hal_set_odm_var(adapter, HAL_ODM_REGULATION, NULL, _TRUE);
#ifdef CONFIG_DFS_MASTER
odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_DFS_REGION_DOMAIN, adapter->registrypriv.dfs_region_domain);
odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_DFS_REGION_DOMAIN, adapter_to_rfctl(adapter)->dfs_region_domain);
odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->radar_detect_enabled));
#endif
@@ -360,6 +396,8 @@ void Init_ODM_ComInfo(_adapter *adapter)
odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D7, pHalData->efuse0x3d7);
odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D8, pHalData->efuse0x3d8);
/* waiting for PhyDMV034 support*/
odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MANUAL_SUPPORTABILITY, &(adapter->registrypriv.phydm_ability));
/*Add by YuChen for adaptivity init*/
odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVITY, &(adapter->registrypriv.adaptivity_en));
phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, (adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE);
@@ -395,6 +433,13 @@ void Init_ODM_ComInfo(_adapter *adapter)
odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC));
odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm));
#ifdef CONFIG_NARROWBAND_SUPPORTING
if ((adapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_10)
|| (adapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_5)) {
odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(adapter->registrypriv.rtw_nb_config));
}
else
#endif
odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->current_channel_bw));
odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->current_channel));
odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed));
@@ -416,8 +461,14 @@ void Init_ODM_ComInfo(_adapter *adapter)
#ifdef CONFIG_DYNAMIC_SOML
odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVE_SOML, &(adapter->registrypriv.dyn_soml_en));
#endif
#ifdef CONFIG_RTW_PATH_DIV
odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_PATH_DIV, &(adapter->registrypriv.path_div));
#endif
odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FCS_MODE, &(pHalData->multi_ch_switch_mode));
/*halrf info hook*/
/* waiting for PhyDMV034 support*/
halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY, &(adapter->registrypriv.halrf_ability));
#ifdef CONFIG_MP_INCLUDED
halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CON_TX, &(adapter->mppriv.mpt_ctx.is_start_cont_tx));
halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_SINGLE_TONE, &(adapter->mppriv.mpt_ctx.is_single_tone));
@@ -425,10 +476,10 @@ void Init_ODM_ComInfo(_adapter *adapter)
halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MP_RATE_INDEX, &(adapter->mppriv.mpt_ctx.mpt_rate_index));
#endif/*CONFIG_MP_INCLUDED*/
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
odm_cmn_info_ptr_array_hook(pDM_Odm, ODM_CMNINFO_STA_STATUS, i, NULL);
phydm_cmn_sta_info_hook(pDM_Odm, i, NULL);
phydm_init_debug_setting(pDM_Odm);
rtw_phydm_ops_func_init(pDM_Odm);
phydm_dm_early_init(pDM_Odm);
/* TODO */
/* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_OPERATION, _FALSE); */
/* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_DISABLE_EDCA, _FALSE); */
@@ -630,7 +681,8 @@ void rtw_hal_turbo_edca(_adapter *adapter)
if (interface_type == RTW_PCIE &&
((ic_type == RTL8822B)
|| (ic_type == RTL8814A))) {
|| (ic_type == RTL8822C)
|| (ic_type == RTL8814A) || (ic_type == RTL8814B))) {
EDCA_BE_UL = 0x6ea42b;
EDCA_BE_DL = 0x6ea42b;
}
@@ -749,6 +801,26 @@ void rtw_hal_turbo_edca(_adapter *adapter)
}
s8 rtw_dm_get_min_rssi(_adapter *adapter)
{
struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
struct sta_info *sta;
s8 min_rssi = 127, rssi;
int i;
for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
sta = macid_ctl->sta[i];
if (!sta || !GET_H2CCMD_MSRRPT_PARM_OPMODE(macid_ctl->h2c_msr + i)
|| is_broadcast_mac_addr(sta->cmn.mac_addr))
continue;
rssi = sta->cmn.rssi_stat.rssi;
if (rssi >= 0 && min_rssi > rssi)
min_rssi = rssi;
}
return min_rssi == 127 ? 0 : min_rssi;
}
s8 rtw_phydm_get_min_rssi(_adapter *adapter)
{
struct dm_struct *phydm = adapter_to_phydm(adapter);
@@ -767,6 +839,15 @@ u8 rtw_phydm_get_cur_igi(_adapter *adapter)
return cur_igi;
}
bool rtw_phydm_get_edcca_flag(_adapter *adapter)
{
struct dm_struct *phydm = adapter_to_phydm(adapter);
bool cur_edcca_flag = 0;
cur_edcca_flag = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_EDCCA_FLAG);
return cur_edcca_flag;
}
u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt)
{
struct dm_struct *phydm = adapter_to_phydm(adapter);
@@ -821,7 +902,7 @@ u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter)
void SetHalODMVar(
PADAPTER Adapter,
HAL_ODM_VARIABLE eVariable,
PVOID pValue1,
void *pValue1,
BOOLEAN bSet)
{
struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
@@ -832,14 +913,12 @@ void SetHalODMVar(
if (bSet) {
RTW_INFO("### Set STA_(%d) info ###\n", psta->cmn.mac_id);
odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->cmn.mac_id, psta);
psta->cmn.dm_ctrl = STA_DM_CTRL_ACTIVE;
phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, &(psta->cmn));
} else {
RTW_INFO("### Clean STA_(%d) info ###\n", psta->cmn.mac_id);
/* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
psta->cmn.dm_ctrl = 0;
odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->cmn.mac_id, NULL);
phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, NULL);
/* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
@@ -880,7 +959,8 @@ void SetHalODMVar(
rssi_min = rtw_phydm_get_min_rssi(Adapter);
_RTW_PRINT_SEL(sel, "============ Rx Info dump ===================\n");
_RTW_PRINT_SEL(sel, "is_linked = %d, rssi_min = %d(%%), current_igi = 0x%x\n", podmpriv->is_linked, rssi_min, cur_igi);
_RTW_PRINT_SEL(sel, "is_linked = %d, rssi_min = %d(%%)(%d(%%)), current_igi = 0x%x\n"
, podmpriv->is_linked, rssi_min, rtw_dm_get_min_rssi(Adapter), cur_igi);
_RTW_PRINT_SEL(sel, "cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\n",
rtw_phydm_get_phy_cnt(Adapter, FA_CCK),
rtw_phydm_get_phy_cnt(Adapter, FA_OFDM),
@@ -931,8 +1011,8 @@ void SetHalODMVar(
void GetHalODMVar(
PADAPTER Adapter,
HAL_ODM_VARIABLE eVariable,
PVOID pValue1,
PVOID pValue2)
void *pValue1,
void *pValue2)
{
struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
@@ -1081,11 +1161,8 @@ void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter)
{
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
struct dm_struct *podmpriv = &(pHalData->odmpriv);
struct sta_priv *pstapriv = &adapter->stapriv;
struct sta_info *psta = NULL;
u8 rssi_min = 0;
u32 rssi_rpt = 0;
bool is_linked = _FALSE;
if (!rtw_is_hw_init_completed(adapter))
@@ -1110,21 +1187,14 @@ void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter)
{
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
struct sta_priv *pstapriv = &adapter->stapriv;
struct sta_info *psta = NULL;
u8 cur_igi = 0;
s8 min_rssi = 0;
if (!rtw_is_hw_init_completed(adapter))
return;
psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
if (psta == NULL)
return;
cur_igi = rtw_phydm_get_cur_igi(adapter);
min_rssi = rtw_phydm_get_min_rssi(adapter);
if (min_rssi <= 0)
min_rssi = psta->cmn.rssi_stat.rssi;
min_rssi = rtw_dm_get_min_rssi(adapter);
/*RTW_INFO("%s "ADPT_FMT" cur_ig_value=%d, min_rssi = %d\n", __func__, ADPT_ARG(adapter), cur_igi, min_rssi);*/
if (min_rssi <= 0)
@@ -1287,11 +1357,148 @@ static void init_phydm_info(_adapter *adapter)
odm_cmn_info_init(phydm, ODM_CMNINFO_FW_VER, hal_data->firmware_version);
odm_cmn_info_init(phydm, ODM_CMNINFO_FW_SUB_VER, hal_data->firmware_sub_version);
}
#ifdef CONFIG_CTRL_TXSS_BY_TP
void rtw_phydm_trx_cfg(_adapter *adapter, bool tx_1ss)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
enum bb_path txpath = BB_PATH_AB;
enum bb_path rxpath = BB_PATH_AB;
/*is_2tx = _FALSE for 8822B, or BB_PATH_AUTO for PATH_DIVERSITY for 8822B*/
enum bb_path txpath_1ss = BB_PATH_A;
rtw_hal_get_trx_path(adapter_to_dvobj(adapter), NULL, &txpath, &rxpath);
txpath = (tx_1ss) ? BB_PATH_A : txpath;
if (phydm_api_trx_mode(adapter_to_phydm(adapter), txpath, rxpath, txpath_1ss) == FALSE)
RTW_ERR("%s failed\n", __func__);
}
#endif
/*
* trx_mode init - 8822B / 8822C / 8192F
* 1ssNTx - 8192E / 8812A / 8822B / 8822C / 8192F
* Path-diversity - 8822B / 8822C / 8192F
* PHYDM API - phydm_api_trx_mode
*/
static u8 rtw_phydm_config_trx_path(_adapter *adapter)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
enum bb_path txpath;
enum bb_path rxpath;
int i;
u8 rst = _FAIL;
rtw_hal_get_trx_path(adapter_to_dvobj(adapter), NULL, &txpath, &rxpath);
if (!txpath) {
RTW_ERR("%s tx_path_bmp is empty\n", __func__);
rtw_warn_on(1);
goto exit;
}
if (!rxpath) {
RTW_ERR("%s rx_path_bmp is empty\n", __func__);
rtw_warn_on(1);
goto exit;
}
tx_path_nss_set_default(hal_data->txpath_nss, hal_data->txpath_num_nss
, GET_HAL_TX_PATH_BMP(adapter));
#if defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B) ||defined(CONFIG_RTL8822C)
{
enum bb_path txpath_1ss;
if (txpath == BB_PATH_AB) {
switch (hal_data->max_tx_cnt) {
case 2:
#ifdef CONFIG_RTW_TX_NPATH_EN
if (adapter->registrypriv.tx_npath == 1)
txpath_1ss = BB_PATH_AB;
else
#endif
#ifdef CONFIG_RTW_PATH_DIV
if (adapter->registrypriv.path_div == 1) /* path diversity, support 2sts TX */
txpath_1ss = BB_PATH_AUTO;
else
#endif
txpath_1ss = BB_PATH_A;
break;
case 1:
#ifdef CONFIG_RTW_PATH_DIV
if (adapter->registrypriv.path_div == 1) /* path diversity, no support 2sts TX */
txpath = txpath_1ss = BB_PATH_AUTO;
else
#endif
txpath = txpath_1ss = BB_PATH_A;
break;
default:
RTW_ERR("%s invalid max_tx_cnt:%u\n", __func__
, hal_data->max_tx_cnt);
rtw_warn_on(1);
goto exit;
}
} else
txpath_1ss = txpath;
if (phydm_api_trx_mode(adapter_to_phydm(adapter), txpath, rxpath, txpath_1ss) == FALSE) {
RTW_ERR("%s txpath=0x%x, rxpath=0x%x, txpath_1ss=0x%x fail\n", __func__
, txpath, rxpath, txpath_1ss);
rtw_warn_on(1);
goto exit;
}
if (hal_data->txpath_nss[0] != txpath_1ss) {
hal_data->txpath_nss[0] = txpath_1ss;
if (txpath_1ss == BB_PATH_AUTO)
hal_data->txpath_num_nss[0] = 1;
else {
hal_data->txpath_num_nss[0] = 0;
for (i = 0; i < RF_PATH_MAX; i++) {
if (txpath_1ss & BIT(i))
hal_data->txpath_num_nss[0]++;
}
}
}
}
#elif defined(CONFIG_RTL8814B)
{
if (config_phydm_trx_mode_8814b(adapter_to_phydm(adapter), txpath, rxpath) == FALSE) {
RTW_ERR("%s txpath=0x%x, rxpath=0x%x fail\n", __func__
, txpath, rxpath);
rtw_warn_on(1);
goto exit;
}
/* 8814B is always full-TX */
tx_path_nss_set_full_tx(hal_data->txpath_nss, hal_data->txpath_num_nss, txpath);
}
#elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8192E)
{
#ifdef CONFIG_RTW_TX_NPATH_EN
if (adapter->registrypriv.tx_npath == 1) {
phydm_tx_2path(adapter_to_phydm(adapter));
tx_path_nss_set_full_tx(hal_data->txpath_nss, hal_data->txpath_num_nss, txpath);
}
#endif
}
#endif
hal_data->txpath = txpath;
hal_data->rxpath = rxpath;
dump_hal_runtime_trx_mode(RTW_DBGDUMP, adapter);
rst = _SUCCESS;
exit:
return rst;
}
void rtw_phydm_init(_adapter *adapter)
{
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
struct dm_struct *phydm = &(hal_data->odmpriv);
rtw_phydm_config_trx_path(adapter);
init_phydm_info(adapter);
odm_dm_init(phydm);
#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
@@ -1299,6 +1506,14 @@ void rtw_phydm_init(_adapter *adapter)
#endif
}
bool rtw_phydm_set_crystal_cap(_adapter *adapter, u8 crystal_cap)
{
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
struct dm_struct *phydm = &(hal_data->odmpriv);
return phydm_set_crystal_cap_reg(phydm, crystal_cap);
}
#ifdef CONFIG_LPS_PG
/*
static void _lps_pg_state_update(_adapter *adapter)
@@ -1387,7 +1602,7 @@ static u8 _rtw_phydm_rfk_condition_check(_adapter *adapter, u8 is_scaning, u8 if
return rfk_allowed;
}
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
static u8 _rtw_phydm_iqk_segment_chk(_adapter *adapter, u8 ifs_linked)
{
u8 iqk_sgt = _FALSE;
@@ -1412,7 +1627,9 @@ static u8 _rtw_phydm_pwr_tracking_rate_check(_adapter *adapter)
u8 if_tx_rate = 0xFF;
u8 tx_rate = 0xFF;
struct mlme_ext_priv *pmlmeext = NULL;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
for (i = 0; i < dvobj->iface_nums; i++) {
iface = dvobj->padapters[i];
@@ -1424,12 +1641,24 @@ static u8 _rtw_phydm_pwr_tracking_rate_check(_adapter *adapter)
else
#endif
if_tx_rate = pmlmeext->tx_rate;
if(if_tx_rate < tx_rate)
tx_rate = if_tx_rate;
RTW_DBG("%s i=%d tx_rate =0x%x\n", __func__, i, if_tx_rate);
if (if_tx_rate < tx_rate) {
/*5G limit ofdm rate*/
if (pHalData->current_channel > 14) {
if (!IS_CCK_RATE(if_tx_rate))
tx_rate = if_tx_rate;
} else {
tx_rate = if_tx_rate;
}
}
RTW_DBG("%s i=%d if_tx_rate =0x%x\n", __func__, i, if_tx_rate);
}
}
/*suggest by RF James,unlinked setting ofdm rate*/
if (tx_rate == 0xFF)
tx_rate = IEEE80211_OFDM_RATE_6MB;
RTW_DBG("%s tx_low_rate (unlinked to any AP)=0x%x\n", __func__, tx_rate);
return tx_rate;
}
@@ -1481,7 +1710,15 @@ void rtw_dyn_soml_config(_adapter *adapter)
}
#endif
void rtw_phydm_set_rrsr(_adapter *adapter, u32 rrsr_value, bool write_rrsr)
{
struct dm_struct *phydm = adapter_to_phydm(adapter);
odm_cmn_info_update(phydm, ODM_CMNINFO_RRSR_VAL, rrsr_value);
if(write_rrsr)
phydm_rrsr_set_register(phydm, rrsr_value);
}
void rtw_phydm_read_efuse(_adapter *adapter)
{
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
@@ -1516,7 +1753,7 @@ void rtw_phydm_watchdog(_adapter *adapter, bool in_lps)
u8 bsta_state = _FALSE;
u8 bBtDisabled = _TRUE;
u8 rfk_forbidden = _FALSE;
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
u8 segment_iqk = _FALSE;
#endif
u8 tx_unlinked_low_rate = 0xFF;
@@ -1542,14 +1779,16 @@ void rtw_phydm_watchdog(_adapter *adapter, bool in_lps)
#ifdef CONFIG_BT_COEXIST
bBtDisabled = rtw_btcoex_IsBtDisabled(adapter);
#endif /* CONFIG_BT_COEXIST */
odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED,
(bBtDisabled == _TRUE) ? _FALSE : _TRUE);
(bBtDisabled == _TRUE) ? _FALSE : _TRUE);
#else
odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED, _FALSE);
#endif /* CONFIG_BT_COEXIST */
rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, pHalData->bScanInProcess, bLinked) == _TRUE) ? _FALSE : _TRUE;
halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
segment_iqk = _rtw_phydm_iqk_segment_chk(adapter, bLinked);
halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_IQK_SEGMENT, segment_iqk);
#endif
@@ -1570,6 +1809,10 @@ void rtw_phydm_watchdog(_adapter *adapter, bool in_lps)
goto _exit;
}*/
#ifdef CONFIG_TDMADIG
rtw_phydm_tdmadig(adapter, TDMADIG_NON_INIT);
#endif/*CONFIG_TDMADIG*/
if (in_lps)
phydm_watchdog_lps(&pHalData->odmpriv);
else
@@ -1579,7 +1822,7 @@ void rtw_phydm_watchdog(_adapter *adapter, bool in_lps)
rtw_acs_update_current_info(adapter);
#endif
_exit:
return;
}

31
hal/hal_dm.h
View File

@@ -17,7 +17,9 @@
#define adapter_to_phydm(adapter) (&(GET_HAL_DATA(adapter)->odmpriv))
#define dvobj_to_phydm(dvobj) adapter_to_phydm(dvobj_get_primary_adapter(dvobj))
#ifdef CONFIG_TDMADIG
void rtw_phydm_tdmadig(_adapter *adapter, u8 state);
#endif
void rtw_phydm_priv_init(_adapter *adapter);
void Init_ODM_ComInfo(_adapter *adapter);
void rtw_phydm_init(_adapter *adapter);
@@ -28,12 +30,12 @@ u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter);
void GetHalODMVar(
PADAPTER Adapter,
HAL_ODM_VARIABLE eVariable,
PVOID pValue1,
PVOID pValue2);
void *pValue1,
void *pValue2);
void SetHalODMVar(
PADAPTER Adapter,
HAL_ODM_VARIABLE eVariable,
PVOID pValue1,
void *pValue1,
BOOLEAN bSet);
void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta);
@@ -44,6 +46,7 @@ void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl,
u8 period, u8 delay);
void rtw_dyn_soml_config(_adapter *adapter);
#endif
void rtw_phydm_set_rrsr(_adapter *adapter, u32 rrsr_value, bool write_rrsr);
void rtw_phydm_watchdog(_adapter *adapter, bool in_lps);
void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter);
@@ -55,8 +58,10 @@ void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment
void rtw_hal_lck_test(_adapter *adapter);
#endif
s8 rtw_dm_get_min_rssi(_adapter *adapter);
s8 rtw_phydm_get_min_rssi(_adapter *adapter);
u8 rtw_phydm_get_cur_igi(_adapter *adapter);
bool rtw_phydm_get_edcca_flag(_adapter *adapter);
#ifdef CONFIG_LPS_LCLK_WD_TIMER
@@ -65,7 +70,12 @@ extern void phydm_rssi_monitor_check(void *p_dm_void);
void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter);
void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter);
#endif
#ifdef CONFIG_TDMADIG
enum rtw_tdmadig_state{
TDMADIG_INIT,
TDMADIG_NON_INIT,
};
#endif
enum phy_cnt {
FA_OFDM,
FA_CCK,
@@ -83,17 +93,16 @@ enum phy_cnt {
CRC32_ERROR_CCK,
};
u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt);
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
void rtw_phydm_iqk_trigger(_adapter *adapter);
#endif
void rtw_phydm_read_efuse(_adapter *adapter);
bool rtw_phydm_set_crystal_cap(_adapter *adapter, u8 crystal_cap);
#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
void rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id);
#endif
#ifdef CONFIG_RTW_TX_2PATH_EN
void rtw_phydm_tx_2path_en(_adapter *adapter);
#endif
#ifdef CONFIG_LPS_PG
void rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg);
#endif
@@ -101,4 +110,8 @@ void rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg
void rtw_phydm_pwr_tracking_directly(_adapter *adapter);
#endif
#ifdef CONFIG_CTRL_TXSS_BY_TP
void rtw_phydm_trx_cfg(_adapter *adapter, bool tx_1ss);
#endif
#endif /* __HAL_DM_H__ */

353
hal/hal_halmac.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2015 - 2018 Realtek Corporation.
* Copyright(c) 2015 - 2019 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -310,7 +310,7 @@ static u8 _halmac_reg_read_8(void *p, u32 offset)
d = (struct dvobj_priv *)p;
adapter = dvobj_get_primary_adapter(d);
return rtw_read8(adapter, offset);
return _rtw_read8(adapter, offset);
}
static u16 _halmac_reg_read_16(void *p, u32 offset)
@@ -322,7 +322,7 @@ static u16 _halmac_reg_read_16(void *p, u32 offset)
d = (struct dvobj_priv *)p;
adapter = dvobj_get_primary_adapter(d);
return rtw_read16(adapter, offset);
return _rtw_read16(adapter, offset);
}
static u32 _halmac_reg_read_32(void *p, u32 offset)
@@ -334,7 +334,7 @@ static u32 _halmac_reg_read_32(void *p, u32 offset)
d = (struct dvobj_priv *)p;
adapter = dvobj_get_primary_adapter(d);
return rtw_read32(adapter, offset);
return _rtw_read32(adapter, offset);
}
static void _halmac_reg_write_8(void *p, u32 offset, u8 val)
@@ -347,7 +347,7 @@ static void _halmac_reg_write_8(void *p, u32 offset, u8 val)
d = (struct dvobj_priv *)p;
adapter = dvobj_get_primary_adapter(d);
err = rtw_write8(adapter, offset, val);
err = _rtw_write8(adapter, offset, val);
if (err == _FAIL)
RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
}
@@ -362,7 +362,7 @@ static void _halmac_reg_write_16(void *p, u32 offset, u16 val)
d = (struct dvobj_priv *)p;
adapter = dvobj_get_primary_adapter(d);
err = rtw_write16(adapter, offset, val);
err = _rtw_write16(adapter, offset, val);
if (err == _FAIL)
RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
}
@@ -377,12 +377,32 @@ static void _halmac_reg_write_32(void *p, u32 offset, u32 val)
d = (struct dvobj_priv *)p;
adapter = dvobj_get_primary_adapter(d);
err = rtw_write32(adapter, offset, val);
err = _rtw_write32(adapter, offset, val);
if (err == _FAIL)
RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
}
#endif /* !CONFIG_SDIO_HCI */
#ifdef DBG_IO
static void _halmac_reg_read_monitor(void *p, u32 addr, u32 len, u32 val
, const char *caller, const u32 line)
{
struct dvobj_priv *d = (struct dvobj_priv *)p;
_adapter *adapter = dvobj_get_primary_adapter(d);
dbg_rtw_reg_read_monitor(adapter, addr, len, val, caller, line);
}
static void _halmac_reg_write_monitor(void *p, u32 addr, u32 len, u32 val
, const char *caller, const u32 line)
{
struct dvobj_priv *d = (struct dvobj_priv *)p;
_adapter *adapter = dvobj_get_primary_adapter(d);
dbg_rtw_reg_write_monitor(adapter, addr, len, val, caller, line);
}
#endif
static u8 _halmac_mfree(void *p, void *buffer, u32 size)
{
rtw_mfree(buffer, size);
@@ -538,7 +558,10 @@ const char *const RTW_HALMAC_FEATURE_NAME[] = {
"HALMAC_FEATURE_CFG_PARA",
"HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE",
"HALMAC_FEATURE_DUMP_LOGICAL_EFUSE",
"HALMAC_FEATURE_DUMP_LOGICAL_EFUSE_MASK",
"HALMAC_FEATURE_UPDATE_PACKET",
"HALMAC_FEATURE_SEND_SCAN_PACKET",
"HALMAC_FEATURE_DROP_SCAN_PACKET",
"HALMAC_FEATURE_UPDATE_DATAPACK",
"HALMAC_FEATURE_RUN_DATAPACK",
"HALMAC_FEATURE_CHANNEL_SWITCH",
@@ -760,6 +783,11 @@ struct halmac_platform_api rtw_halmac_platform_api = {
.REG_WRITE_32 = _halmac_reg_write_32,
#endif /* CONFIG_USB_HCI || CONFIG_PCI_HCI */
#ifdef DBG_IO
.READ_MONITOR = _halmac_reg_read_monitor,
.WRITE_MONITOR = _halmac_reg_write_monitor,
#endif
/* Write data */
#if 0
/* impletement in HAL-IC level */
@@ -1049,12 +1077,15 @@ static int init_write_rsvd_page_size(struct dvobj_priv *d)
size = MAX_CMDBUF_SZ - TXDESC_OFFSET;
#elif defined(CONFIG_SDIO_HCI)
size = 0x7000; /* 28KB */
#else
/* Use HALMAC default setting and don't call any function */
return 0;
#endif
#if 0 /* Fail to pass coverity DEADCODE check */
/* If size==0, use HALMAC default setting and don't call any function */
if (!size)
return 0;
#endif
err = rtw_halmac_set_max_dl_fw_size(d, size);
if (err) {
RTW_ERR("%s: Fail to set max download fw size!\n", __FUNCTION__);
@@ -1401,7 +1432,7 @@ int rtw_halmac_get_hw_value(struct dvobj_priv *d, enum halmac_hw_id hw_id, void
*
* Get TX FIFO size(byte) from HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size)
{
@@ -1430,7 +1461,7 @@ int rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size)
*
* Get RX FIFO size(byte) from HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size)
{
@@ -1459,7 +1490,7 @@ int rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size)
*
* Get reserve page boundary of driver from HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy)
{
@@ -1488,7 +1519,7 @@ int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy)
*
* Get TX/RX page size(byte) from HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size)
{
@@ -1517,7 +1548,7 @@ int rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size)
*
* Get TX aggregation align size(byte) from HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size)
{
@@ -1546,7 +1577,7 @@ int rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size)
*
* Get RX aggregation align size(byte) from HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size)
{
@@ -1588,7 +1619,7 @@ int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size)
* d pointer to struct dvobj_priv of driver
* sz rx driver info size in bytes.
*
* Rteurn:
* Return:
* 0 Success
* other Fail
*/
@@ -1614,7 +1645,7 @@ int rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *d, u8 *sz)
*
* Get TX descriptor size(byte) from HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size)
{
@@ -1643,7 +1674,7 @@ int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size)
*
* Get RX descriptor size(byte) from HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size)
{
@@ -1665,6 +1696,83 @@ int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size)
return 0;
}
/**
* rtw_halmac_get_tx_dma_ch_map() - Get TX DMA channel Map for tx desc
* @d: struct dvobj_priv*
* @dma_ch_map: return map of QSEL to DMA channel
* @map_size: size of dma_ch_map
* Suggest size to be last valid QSEL(QSLT_CMD)+1 or full QSLT
* size(0x20)
*
* 8814B would need this to get mapping of QSEL to DMA channel for TX desc.
*
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_get_tx_dma_ch_map(struct dvobj_priv *d, u8 *dma_ch_map, u8 map_size)
{
struct halmac_adapter *halmac;
struct halmac_api *api;
enum halmac_ret_status status;
struct halmac_rqpn_ch_map map;
enum halmac_dma_ch channel = HALMAC_DMA_CH_UNDEFINE;
u8 qsel;
halmac = dvobj_to_halmac(d);
api = HALMAC_GET_API(halmac);
status = api->halmac_get_hw_value(halmac, HALMAC_HW_RQPN_CH_MAPPING, &map);
if (status != HALMAC_RET_SUCCESS)
return -1;
for (qsel = 0; qsel < map_size; qsel++) {
switch (qsel) {
/*case QSLT_VO:*/
case 0x06:
case 0x07:
channel = map.dma_map_vo;
break;
/*case QSLT_VI:*/
case 0x04:
case 0x05:
channel = map.dma_map_vi;
break;
/*case QSLT_BE:*/
case 0x00:
case 0x03:
channel = map.dma_map_be;
break;
/*case QSLT_BK:*/
case 0x01:
case 0x02:
channel = map.dma_map_bk;
break;
/*case QSLT_BEACON:*/
case 0x10:
channel = HALMAC_DMA_CH_BCN;
break;
/*case QSLT_HIGH:*/
case 0x11:
channel = map.dma_map_hi;
break;
/*case QSLT_MGNT:*/
case 0x12:
channel = map.dma_map_mg;
break;
/*case QSLT_CMD:*/
case 0x13:
channel = HALMAC_DMA_CH_H2C;
break;
default:
/*RTW_ERR("%s: invalid qsel=0x%x\n", __FUNCTION__, qsel);*/
channel = HALMAC_DMA_CH_UNDEFINE;
break;
}
dma_ch_map[qsel] = (u8)channel;
}
return 0;
}
/**
* rtw_halmac_get_fw_max_size() - Firmware MAX size
@@ -1673,7 +1781,7 @@ int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size)
*
* Get Firmware MAX size(byte) from HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
static int rtw_halmac_get_fw_max_size(struct dvobj_priv *d, u32 *size)
{
@@ -1702,7 +1810,7 @@ static int rtw_halmac_get_fw_max_size(struct dvobj_priv *d, u32 *size)
*
* Get original H2C MAX size(byte) from HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size)
{
@@ -1776,7 +1884,7 @@ int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num)
*
* Get MAC address of specific port from HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
{
@@ -1815,7 +1923,7 @@ out:
*
* Get network type of specific port from HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type)
{
@@ -1900,7 +2008,7 @@ out:
*
* Get beacon control setting of specific port from HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport,
struct rtw_halmac_bcn_ctrl *bcn_ctrl)
@@ -1949,6 +2057,9 @@ int rtw_halmac_config_rx_info(struct dvobj_priv *d, enum halmac_drv_info info)
err = 0;
out:
/* Sync driver RCR cache with register setting */
rtw_hal_get_hwreg(dvobj_get_primary_adapter(d), HW_VAR_RCR, NULL);
return err;
}
@@ -2003,7 +2114,7 @@ int rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size)
*
* Set self mac address of specific port to HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
{
@@ -2039,7 +2150,7 @@ out:
*
* Set BSSID of specific port to HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
{
@@ -2074,7 +2185,7 @@ out:
*
* Set transmitter address of specific port to HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
{
@@ -2109,7 +2220,7 @@ out:
*
* Set network type of specific port to HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type)
{
@@ -2143,7 +2254,7 @@ out:
* Notice HALMAC to reset timing synchronization function(TSF) timer of
* specific port.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport)
{
@@ -2175,7 +2286,7 @@ out:
*
* Set beacon interval of specific port to HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport,
u32 interval)
@@ -2208,7 +2319,7 @@ out:
*
* Set beacon control setting of specific port to HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport,
struct rtw_halmac_bcn_ctrl *bcn_ctrl)
@@ -2244,7 +2355,7 @@ out:
*
* Set association identifier(AID) of specific port to HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid)
{
@@ -2949,10 +3060,13 @@ static int _send_general_info(struct dvobj_priv *d)
_rtw_memset(&info, 0, sizeof(info));
info.rfe_type = (u8)hal->rfe_type;
rtw_hal_get_rf_path(d, &rf, &txpath, &rxpath);
rtw_hal_get_trx_path(d, &rf, &txpath, &rxpath);
info.rf_type = _rf_type_drv2halmac(rf);
info.tx_ant_status = (u8)txpath;
info.rx_ant_status = (u8)rxpath;
info.ext_pa = 0; /* 2.4G or 5G? format not known */
info.package_type = hal->PackageType;
info.mp_mode = adapter->registrypriv.mp_mode;
status = api->halmac_send_general_info(halmac, &info);
switch (status) {
@@ -2961,7 +3075,7 @@ static int _send_general_info(struct dvobj_priv *d)
case HALMAC_RET_NO_DLFW:
RTW_WARN("%s: halmac_send_general_info() fail because fw not dl!\n",
__FUNCTION__);
/* go through */
/* fall through */
default:
return -1;
}
@@ -2985,6 +3099,7 @@ static int _cfg_drv_rsvd_pg_num(struct dvobj_priv *d)
enum halmac_drv_rsvd_pg_num rsvd_page_number;
enum halmac_ret_status status;
u16 drv_rsvd_num;
int ret = 0;
a = dvobj_get_primary_adapter(d);
@@ -2995,15 +3110,21 @@ static int _cfg_drv_rsvd_pg_num(struct dvobj_priv *d)
drv_rsvd_num = rtw_hal_get_rsvd_page_num(a);
rsvd_page_number = _rsvd_page_num_drv2halmac(drv_rsvd_num);
status = api->halmac_cfg_drv_rsvd_pg_num(halmac, rsvd_page_number);
if (status != HALMAC_RET_SUCCESS)
return -1;
if (status != HALMAC_RET_SUCCESS) {
ret = -1;
goto exit;
}
hal->drv_rsvd_page_number = _rsvd_page_num_halmac2drv(rsvd_page_number);
if (drv_rsvd_num != hal->drv_rsvd_page_number)
RTW_INFO("%s: request %d pages, but allocate %d pages\n",
__FUNCTION__, drv_rsvd_num, hal->drv_rsvd_page_number);
exit:
#ifndef DBG_RSVD_PAGE_CFG
if (drv_rsvd_num != _rsvd_page_num_halmac2drv(rsvd_page_number))
#endif
RTW_INFO("%s: request %d pages => halmac %d pages %s\n"
, __FUNCTION__, drv_rsvd_num, _rsvd_page_num_halmac2drv(rsvd_page_number)
, ret ? "fail" : "success");
return 0;
return ret;
}
static void _debug_dlfw_fail(struct dvobj_priv *d)
@@ -3011,7 +3132,6 @@ static void _debug_dlfw_fail(struct dvobj_priv *d)
struct _ADAPTER *a;
u32 addr;
u32 v32, i, n;
u8 data[0x100] = {0};
a = dvobj_get_primary_adapter(d);
@@ -3058,34 +3178,13 @@ static void _debug_dlfw_fail(struct dvobj_priv *d)
__FUNCTION__, addr, v32, i, n);
}
/* 0x00~0xFF, 0x1000~0x10FF */
addr = 0;
n = 0x100;
for (i = 0; i < n; i+=4)
*(u32*)&data[i] = cpu_to_le32(rtw_read32(a, addr+i));
for (i = 0; i < n; i++) {
if (i % 16 == 0)
RTW_PRINT("0x%04x\t", addr+i);
_RTW_PRINT("0x%02x", data[i]);
if (i % 16 == 15)
_RTW_PRINT("\n");
else
_RTW_PRINT(" ");
}
addr = 0x1000;
n = 0x100;
for (i = 0; i < n; i+=4)
*(u32*)&data[i] = cpu_to_le32(rtw_read32(a, addr+i));
for (i = 0; i < n; i++) {
if (i % 16 == 0)
RTW_PRINT("0x%04x\t", addr+i);
_RTW_PRINT("0x%02x", data[i]);
if (i % 16 == 15)
_RTW_PRINT("\n");
else
_RTW_PRINT(" ");
}
mac_reg_dump(NULL, a);
#ifdef CONFIG_SDIO_HCI
RTW_PRINT("======= SDIO Local REG =======\n");
sdio_local_reg_dump(NULL, a);
RTW_PRINT("======= SDIO CCCR REG =======\n");
sd_f0_reg_dump(NULL, a);
#endif /* CONFIG_SDIO_HCI */
/* read 0x80 after 10 secs */
rtw_msleep_os(10000);
@@ -3129,7 +3228,7 @@ static enum halmac_ret_status _enter_cpu_sleep_mode(struct dvobj_priv *d)
* @timeout: time limit of wait, unit is ms
* 0 for no limit
*
* Rteurn 0 for CPU in sleep mode, otherwise fail to enter sleep mode.
* Return 0 for CPU in sleep mode, otherwise fail to enter sleep mode.
* Error codes definition are as follow:
* -1 HALMAC enter sleep return fail
* -2 HALMAC get CPU mode return fail
@@ -3344,10 +3443,15 @@ static int init_mac_flow(struct dvobj_priv *d)
goto out;
#endif
#if 0 /* It is not necessary to call this in normal driver */
status = api->halmac_cfg_la_mode(halmac, HALMAC_LA_MODE_DISABLE);
if (status != HALMAC_RET_SUCCESS)
goto out;
#ifdef DBG_LA_MODE
if (dvobj_to_regsty(d)->la_mode_en) {
status = api->halmac_cfg_la_mode(halmac, HALMAC_LA_MODE_PARTIAL);
if (status != HALMAC_RET_SUCCESS) {
RTW_ERR("%s: Fail to enable LA mode!\n", __FUNCTION__);
goto out;
}
RTW_PRINT("%s: Enable LA mode OK.\n", __FUNCTION__);
}
#endif
err = _cfg_drv_rsvd_pg_num(d);
@@ -3364,7 +3468,13 @@ static int init_mac_flow(struct dvobj_priv *d)
status = api->halmac_init_mac_cfg(halmac, trx_mode);
if (status != HALMAC_RET_SUCCESS)
goto out;
/* Driver insert flow: Sync driver setting with register */
/* Sync driver RCR cache with register setting */
rtw_hal_get_hwreg(dvobj_get_primary_adapter(d), HW_VAR_RCR, NULL);
_init_trx_cfg_drv(d);
/* Driver inser flow end */
err = rtw_halmac_rx_agg_switch(d, _TRUE);
if (err)
@@ -3413,10 +3523,12 @@ static int _drv_enable_trx(struct dvobj_priv *d)
/*
* Notices:
* Make sure
* 1. rtw_hal_get_hwreg(HW_VAR_RF_TYPE)
* 2. HAL_DATA_TYPE.rfe_type
* already ready for use before calling this function.
* Make sure following information
* 1. GET_HAL_RFPATH
* 2. GET_HAL_DATA(dvobj_get_primary_adapter(d))->rfe_type
* 3. GET_HAL_DATA(dvobj_get_primary_adapter(d))->PackageType
* 4. dvobj_get_primary_adapter(d)->registrypriv.mp_mode
* are all ready before calling this function.
*/
static int _halmac_init_hal(struct dvobj_priv *d, u8 *fw, u32 fwsize)
{
@@ -3512,10 +3624,12 @@ int rtw_halmac_init_hal(struct dvobj_priv *d)
/*
* Notices:
* Make sure
* 1. rtw_hal_get_hwreg(HW_VAR_RF_TYPE)
* 2. HAL_DATA_TYPE.rfe_type
* already ready for use before calling this function.
* Make sure following information
* 1. GET_HAL_RFPATH
* 2. GET_HAL_DATA(dvobj_get_primary_adapter(d))->rfe_type
* 3. GET_HAL_DATA(dvobj_get_primary_adapter(d))->PackageType
* 4. dvobj_get_primary_adapter(d)->registrypriv.mp_mode
* are all ready before calling this function.
*/
int rtw_halmac_init_hal_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize)
{
@@ -3524,10 +3638,12 @@ int rtw_halmac_init_hal_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize)
/*
* Notices:
* Make sure
* 1. rtw_hal_get_hwreg(HW_VAR_RF_TYPE)
* 2. HAL_DATA_TYPE.rfe_type
* already ready for use before calling this function.
* Make sure following information
* 1. GET_HAL_RFPATH
* 2. GET_HAL_DATA(dvobj_get_primary_adapter(d))->rfe_type
* 3. GET_HAL_DATA(dvobj_get_primary_adapter(d))->PackageType
* 4. dvobj_get_primary_adapter(d)->registrypriv.mp_mode
* are all ready before calling this function.
*/
int rtw_halmac_init_hal_fw_file(struct dvobj_priv *d, u8 *fwpath)
{
@@ -3638,7 +3754,7 @@ static u8 rtw_halmac_txfifo_is_empty(struct dvobj_priv *d)
*
* Wait TX FIFO to be emtpy.
*
* Rteurn 0 for TX FIFO is empty, otherwise not empty.
* Return 0 for TX FIFO is empty, otherwise not empty.
*/
int rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout)
{
@@ -4598,7 +4714,7 @@ int rtw_halmac_p2pps(struct dvobj_priv *dvobj, struct hal_p2p_ps_para *pp2p_ps_p
*
* Process IQ Calibration(IQK).
*
* Rteurn: 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment)
{
@@ -4843,7 +4959,7 @@ static enum halmac_wlled_mode _led_mode_drv2halmac(u8 drv_mode)
* If want to change LED mode after enabled, need to disable LED first and
* enable again to set new mode.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode)
{
@@ -4927,7 +5043,7 @@ void rtw_halmac_led_switch(struct dvobj_priv *d, u8 on)
*
* Configure pinmux to allow BT to control BT wake host pin.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_bt_wake_cfg(struct dvobj_priv *d, u8 enable)
{
@@ -4971,7 +5087,7 @@ int rtw_halmac_bt_wake_cfg(struct dvobj_priv *d, u8 enable)
*
* Switch Channel and Send Porbe Request Offloaded by FW
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
static int _halmac_scanoffload(struct dvobj_priv *d, u32 enable, u8 nlo,
u8 *ssid, u8 ssid_len)
@@ -5151,7 +5267,7 @@ static int _halmac_scanoffload(struct dvobj_priv *d, u32 enable, u8 nlo,
* Switch firmware scan AP function for PNO(prefer network offload) or
* NLO(network list offload).
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_pno_scanoffload(struct dvobj_priv *d, u32 enable)
{
@@ -5168,7 +5284,7 @@ int rtw_halmac_pno_scanoffload(struct dvobj_priv *d, u32 enable)
* Parameter:
* d pointer to struct dvobj_priv of driver
*
* Rteurn:
* Return:
* 0 Success, "page" is valid.
* others Fail, "page" is invalid.
*/
@@ -5261,7 +5377,7 @@ int rtw_halmac_query_tx_page_num(struct dvobj_priv *d)
* queue target queue to query, VO/VI/BE/BK/.../TXCMD_QUEUE_INX
* page return allocated page number
*
* Rteurn:
* Return:
* 0 Success, "page" is valid.
* others Fail, "page" is invalid.
*/
@@ -5324,6 +5440,22 @@ u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *d, u8 *seq)
(*seq)++;
return RTW_SDIO_ADDR_RX_RX0FF_GEN(id);
}
int rtw_halmac_sdio_set_tx_format(struct dvobj_priv *d, enum halmac_sdio_tx_format format)
{
struct halmac_adapter *mac;
struct halmac_api *api;
enum halmac_ret_status status;
mac = dvobj_to_halmac(d);
api = HALMAC_GET_API(mac);
status = api->halmac_set_hw_value(mac, HALMAC_HW_SDIO_TX_FORMAT, &format);
if (HALMAC_RET_SUCCESS != status)
return -1;
return 0;
}
#endif /* CONFIG_SDIO_HCI */
#ifdef CONFIG_USB_HCI
@@ -5352,7 +5484,7 @@ u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *d, u8 *buf, u32 size)
*
* Get MAX descriptor number in one bulk out from HALMAC.
*
* Rteurn 0 for OK, otherwise fail.
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num)
{
@@ -5496,9 +5628,33 @@ int rtw_halmac_bf_del_sounding(struct dvobj_priv *d,
return 0;
}
int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d,
u8 rssi, u8 current_rate, u8 fixrate_en,
u8 *new_rate)
/**
* rtw_halmac_bf_cfg_csi_rate() - Config data rate for CSI report frame by RSSI
* @d: struct dvobj_priv*
* @rssi: RSSI vlaue, unit is percentage (0~100).
* @current_rate: Current CSI frame rate
* Valid value example
* 0 CCK 1M
* 3 CCK 11M
* 4 OFDM 6M
* and so on
* @fixrate_en: Enable to fix CSI frame in VHT rate, otherwise legacy OFDM rate.
* The value "0" for disable, otheriwse enable.
* @new_rate: Return new data rate, and value range is the same as
* current_rate
* @bmp_ofdm54: Return to suggest enabling OFDM 54M for CSI report frame or not,
* The valid values and meanings are:
* 0x00 disable
* 0x01 enable
* 0xFF Keep current setting
*
* According RSSI to config data rate for CSI report frame of Beamforming.
*
* Return 0 for OK, otherwise fail.
*/
int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, u8 rssi,
u8 current_rate, u8 fixrate_en, u8 *new_rate,
u8 *bmp_ofdm54)
{
struct halmac_adapter *mac;
struct halmac_api *api;
@@ -5509,7 +5665,8 @@ int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d,
api = HALMAC_GET_API(mac);
status = api->halmac_cfg_csi_rate(mac,
rssi, current_rate, fixrate_en, new_rate);
rssi, current_rate, fixrate_en, new_rate,
bmp_ofdm54);
if (status != HALMAC_RET_SUCCESS)
return -1;

4
hal/hal_halmac.h
View File

@@ -131,6 +131,7 @@ int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size);
int rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *, u8 *sz);
int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size);
int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size);
int rtw_halmac_get_tx_dma_ch_map(struct dvobj_priv *d, u8 *dma_ch_map, u8 map_size);
int rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size);
int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size);
int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num);
@@ -208,6 +209,7 @@ int rtw_halmac_get_tx_queue_page_num(struct dvobj_priv *, u8 queue, u32 *page);
u32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *, u8 *desc, u32 size);
int rtw_halmac_sdio_tx_allowed(struct dvobj_priv *, u8 *buf, u32 size);
u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *, u8 *seq);
int rtw_halmac_sdio_set_tx_format(struct dvobj_priv *d, enum halmac_sdio_tx_format format);
#endif /* CONFIG_SDIO_HCI */
#ifdef CONFIG_USB_HCI
@@ -231,7 +233,7 @@ int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d, enum halmac_snd_role role,
int rtw_halmac_bf_del_sounding(struct dvobj_priv *d, enum halmac_snd_role role);
int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, u8 rssi, u8 current_rate,
u8 fixrate_en, u8 *new_rate);
u8 fixrate_en, u8 *new_rate, u8 *bmp_ofdm54);
int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, enum halmac_snd_role role,
u8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en,

512
hal/hal_intf.c
View File

@@ -34,6 +34,8 @@ const u32 _chip_type_to_odm_ic_type[] = {
ODM_RTL8821C,
ODM_RTL8710B,
ODM_RTL8192F,
ODM_RTL8822C,
ODM_RTL8814B,
0,
};
@@ -129,16 +131,6 @@ void rtw_hal_def_value_init(_adapter *padapter)
adapter_to_dvobj(padapter)->p0_tsf.offset = 0;
#endif
{
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
/* hal_spec is ready here */
dvobj->macid_ctl.num = rtw_min(hal_spec->macid_num, MACID_NUM_SW_LIMIT);
dvobj->cam_ctl.sec_cap = hal_spec->sec_cap;
dvobj->cam_ctl.num = rtw_min(hal_spec->sec_cam_ent_num, SEC_CAM_ENT_NUM_SW_LIMIT);
}
GET_HAL_DATA(padapter)->rx_tsf_addr_filter_config = 0;
}
}
@@ -185,6 +177,10 @@ void rtw_hal_dm_init(_adapter *padapter)
_rtw_spinlock_init(&pHalData->IQKSpinLock);
#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
if (pHalData->txpwr_pg_mode == TXPWR_PG_WITH_PWR_IDX)
hal_load_txpwr_info(padapter);
#endif
phy_load_tx_power_ext_info(padapter, 1);
}
}
@@ -199,6 +195,229 @@ void rtw_hal_dm_deinit(_adapter *padapter)
}
}
enum rf_type rtw_chip_rftype_to_hal_rftype(_adapter *adapter, u8 limit)
{
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
u8 tx_num = 0, rx_num = 0;
/*get RF PATH from version_id.RF_TYPE */
if (IS_1T1R(hal_data->version_id)) {
tx_num = 1;
rx_num = 1;
} else if (IS_1T2R(hal_data->version_id)) {
tx_num = 1;
rx_num = 2;
} else if (IS_2T2R(hal_data->version_id)) {
tx_num = 2;
rx_num = 2;
} else if (IS_2T3R(hal_data->version_id)) {
tx_num = 2;
rx_num = 3;
} else if (IS_2T4R(hal_data->version_id)) {
tx_num = 2;
rx_num = 4;
} else if (IS_3T3R(hal_data->version_id)) {
tx_num = 3;
rx_num = 3;
} else if (IS_3T4R(hal_data->version_id)) {
tx_num = 3;
rx_num = 4;
} else if (IS_4T4R(hal_data->version_id)) {
tx_num = 4;
rx_num = 4;
}
if (limit) {
tx_num = rtw_min(tx_num, limit);
rx_num = rtw_min(rx_num, limit);
}
return trx_num_to_rf_type(tx_num, rx_num);
}
void dump_hal_runtime_trx_mode(void *sel, _adapter *adapter)
{
struct registry_priv *regpriv = &adapter->registrypriv;
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
int i;
RTW_PRINT_SEL(sel, "txpath=0x%x, rxpath=0x%x\n", hal_data->txpath, hal_data->rxpath);
for (i = 0; i < hal_data->tx_nss; i++)
RTW_PRINT_SEL(sel, "txpath_%uss:0x%x, num:%u\n"
, i + 1, hal_data->txpath_nss[i]
, hal_data->txpath_num_nss[i]);
}
void dump_hal_trx_mode(void *sel, _adapter *adapter)
{
struct registry_priv *regpriv = &adapter->registrypriv;
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
RTW_PRINT_SEL(sel, "trx_path_bmp:0x%02x(%s), NumTotalRFPath:%u, max_tx_cnt:%u\n"
, hal_data->trx_path_bmp
, rf_type_to_rfpath_str(hal_data->rf_type)
, hal_data->NumTotalRFPath
, hal_data->max_tx_cnt
);
RTW_PRINT_SEL(sel, "tx_nss:%u, rx_nss:%u\n"
, hal_data->tx_nss, hal_data->rx_nss);
RTW_PRINT_SEL(sel, "\n");
dump_hal_runtime_trx_mode(sel, adapter);
}
void _dump_rf_path(void *sel, _adapter *adapter)
{
struct registry_priv *regpriv = &adapter->registrypriv;
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
RTW_PRINT_SEL(sel, "[RF_PATH] ver_id.RF_TYPE:%s, rf_reg_path_num:%u, max_tx_cnt:%u\n"
, rf_type_to_rfpath_str(rtw_chip_rftype_to_hal_rftype(adapter, 0))
, GET_HAL_SPEC(adapter)->rf_reg_path_num
, GET_HAL_SPEC(adapter)->max_tx_cnt);
RTW_PRINT_SEL(sel, "[RF_PATH] PG's trx_path_bmp:0x%02x, max_tx_cnt:%u\n"
, hal_data->eeprom_trx_path_bmp, hal_data->eeprom_max_tx_cnt);
RTW_PRINT_SEL(sel, "[RF_PATH] Registry's RF PATH:%s\n"
, rf_type_to_rfpath_str(regpriv->rf_path));
RTW_PRINT_SEL(sel, "[RF_PATH] HALDATA's trx_path_bmp:0x%02x, max_tx_cnt:%u\n"
, hal_data->trx_path_bmp, hal_data->max_tx_cnt);
RTW_PRINT_SEL(sel, "[RF_PATH] HALDATA's rf_type:%s\n"
, rf_type_to_rfpath_str(hal_data->rf_type));
RTW_PRINT_SEL(sel, "[RF_PATH] NumTotalRFPath:%d\n"
, hal_data->NumTotalRFPath);
}
#ifdef CONFIG_RTL8814A
extern enum rf_type rtl8814a_rfpath_decision(_adapter *adapter);
#endif
u8 rtw_hal_rfpath_init(_adapter *adapter)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
#ifdef CONFIG_RTL8814A
if (IS_HARDWARE_TYPE_8814A(adapter)) {
enum bb_path tx_bmp, rx_bmp;
hal_data->rf_type = rtl8814a_rfpath_decision(adapter);
rf_type_to_default_trx_bmp(hal_data->rf_type, &tx_bmp, &rx_bmp);
hal_data->trx_path_bmp = (tx_bmp << 4) | rx_bmp;
hal_data->NumTotalRFPath = 4;
hal_data->max_tx_cnt = hal_spec->max_tx_cnt;
hal_data->max_tx_cnt = rtw_min(hal_data->max_tx_cnt, rf_type_to_rf_tx_cnt(hal_data->rf_type));
} else
#endif
{
struct registry_priv *regpriv = &adapter->registrypriv;
enum rf_type ic_cap;
enum rf_type type;
u8 tx_path_num;
u8 rx_path_num;
int i;
ic_cap = rtw_chip_rftype_to_hal_rftype(adapter, hal_spec->rf_reg_path_num);
if (!RF_TYPE_VALID(ic_cap)) {
RTW_ERR("%s rtw_chip_rftype_to_hal_rftype failed\n", __func__);
return _FAIL;
}
type = ic_cap;
if (RF_TYPE_VALID(regpriv->rf_path)) {
if (rf_type_is_a_in_b(regpriv->rf_path, ic_cap))
type = regpriv->rf_path;
else
RTW_WARN("%s invalid regpriv:%s > ic_cap:%s\n", __func__
, rf_type_to_rfpath_str(regpriv->rf_path)
, rf_type_to_rfpath_str(ic_cap));
}
if (hal_data->eeprom_trx_path_bmp != 0x00) {
/* specific trx path is defined, restrict it with rftype(TX and RX num) */
u8 trx_path_bmp = rtw_restrict_trx_path_bmp_by_rftype(
hal_data->eeprom_trx_path_bmp, type, &tx_path_num, &rx_path_num);
if (!trx_path_bmp) {
RTW_ERR("%s rtw_restrict_trx_path_bmp_by_rftype(0x%x, %s) failed\n"
, __func__, hal_data->eeprom_trx_path_bmp
, rf_type_to_rfpath_str(type));
return _FAIL;
}
hal_data->trx_path_bmp = trx_path_bmp;
hal_data->rf_type = trx_bmp_to_rf_type((trx_path_bmp & 0xF0) >> 4
, trx_path_bmp & 0x0F);
} else {
/* no specific trx path is defined, use default trx_bmp */
enum bb_path tx_bmp, rx_bmp;
rf_type_to_default_trx_bmp(type, &tx_bmp, &rx_bmp);
hal_data->trx_path_bmp = (tx_bmp << 4) | rx_bmp;
hal_data->rf_type = type;
tx_path_num = rf_type_to_rf_tx_cnt(hal_data->rf_type);
rx_path_num = rf_type_to_rf_rx_cnt(hal_data->rf_type);
}
hal_data->NumTotalRFPath = tx_path_num;
if (hal_data->NumTotalRFPath < rx_path_num)
hal_data->NumTotalRFPath = rx_path_num;
hal_data->max_tx_cnt = hal_spec->max_tx_cnt;
hal_data->max_tx_cnt = rtw_min(hal_data->max_tx_cnt, tx_path_num);
if (hal_data->eeprom_max_tx_cnt)
hal_data->max_tx_cnt = rtw_min(hal_data->max_tx_cnt, hal_data->eeprom_max_tx_cnt);
if (1)
_dump_rf_path(RTW_DBGDUMP, adapter);
}
RTW_INFO("%s trx_path_bmp:0x%02x(%s), NumTotalRFPath:%u, max_tx_cnt:%u\n"
, __func__
, hal_data->trx_path_bmp
, rf_type_to_rfpath_str(hal_data->rf_type)
, hal_data->NumTotalRFPath
, hal_data->max_tx_cnt);
return _SUCCESS;
}
void _dump_trx_nss(void *sel, _adapter *adapter)
{
struct registry_priv *regpriv = &adapter->registrypriv;
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
RTW_PRINT_SEL(sel, "[TRX_Nss] HALSPEC - tx_nss :%d, rx_nss:%d\n", hal_spec->tx_nss_num, hal_spec->rx_nss_num);
RTW_PRINT_SEL(sel, "[TRX_Nss] Registry - tx_nss :%d, rx_nss:%d\n", regpriv->tx_nss, regpriv->rx_nss);
RTW_PRINT_SEL(sel, "[TRX_Nss] HALDATA - tx_nss :%d, rx_nss:%d\n", GET_HAL_TX_NSS(adapter), GET_HAL_RX_NSS(adapter));
}
#define NSS_VALID(nss) (nss > 0)
u8 rtw_hal_trxnss_init(_adapter *adapter)
{
struct registry_priv *regpriv = &adapter->registrypriv;
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
enum rf_type rf_path = GET_HAL_RFPATH(adapter);
hal_data->tx_nss = hal_spec->tx_nss_num;
hal_data->rx_nss = hal_spec->rx_nss_num;
if (NSS_VALID(regpriv->tx_nss))
hal_data->tx_nss = rtw_min(hal_data->tx_nss, regpriv->tx_nss);
hal_data->tx_nss = rtw_min(hal_data->tx_nss, hal_data->max_tx_cnt);
if (NSS_VALID(regpriv->rx_nss))
hal_data->rx_nss = rtw_min(hal_data->rx_nss, regpriv->rx_nss);
hal_data->rx_nss = rtw_min(hal_data->rx_nss, rf_type_to_rf_rx_cnt(rf_path));
if (1)
_dump_trx_nss(RTW_DBGDUMP, adapter);
RTW_INFO("%s tx_nss:%u, rx_nss:%u\n", __func__
, hal_data->tx_nss, hal_data->rx_nss);
return _SUCCESS;
}
#ifdef CONFIG_RTW_SW_LED
void rtw_hal_sw_led_init(_adapter *padapter)
{
@@ -251,6 +470,11 @@ void rtw_hal_power_off(_adapter *padapter)
struct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl;
_rtw_memset(macid_ctl->h2c_msr, 0, MACID_NUM_SW_LIMIT);
_rtw_memset(macid_ctl->op_num, 0, H2C_MSR_ROLE_MAX);
#ifdef CONFIG_LPS_1T1R
GET_HAL_DATA(padapter)->lps_1t1r = 0;
#endif
#ifdef CONFIG_BT_COEXIST
rtw_btcoex_PowerOffSetting(padapter);
@@ -304,6 +528,8 @@ uint rtw_hal_init(_adapter *padapter)
{
uint status = _SUCCESS;
halrf_set_rfsupportability(adapter_to_phydm(padapter));
status = padapter->hal_func.hal_init(padapter);
if (status == _SUCCESS) {
@@ -327,9 +553,9 @@ uint rtw_hal_init(_adapter *padapter)
rtw_dyn_soml_config(padapter);
#endif
#endif
#ifdef CONFIG_RTW_TX_2PATH_EN
rtw_phydm_tx_2path_en(padapter);
#endif
#ifdef CONFIG_TDMADIG
rtw_phydm_tdmadig(padapter, TDMADIG_INIT);
#endif/*CONFIG_TDMADIG*/
} else {
rtw_set_hw_init_completed(padapter, _FALSE);
RTW_ERR("%s: hal_init fail\n", __func__);
@@ -343,6 +569,8 @@ uint rtw_hal_init(_adapter *padapter)
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
int i;
halrf_set_rfsupportability(adapter_to_phydm(padapter));
status = padapter->hal_func.hal_init(padapter);
if (status == _SUCCESS) {
@@ -376,10 +604,10 @@ uint rtw_hal_init(_adapter *padapter)
rtw_dyn_soml_config(padapter);
#endif
#endif
#ifdef CONFIG_TDMADIG
rtw_phydm_tdmadig(padapter, TDMADIG_INIT);
#endif/*CONFIG_TDMADIG*/
#ifdef CONFIG_RTW_TX_2PATH_EN
rtw_phydm_tx_2path_en(padapter);
#endif
} else {
rtw_set_hw_init_completed(padapter, _FALSE);
RTW_ERR("%s: fail\n", __func__);
@@ -394,8 +622,6 @@ uint rtw_hal_init(_adapter *padapter)
uint rtw_hal_deinit(_adapter *padapter)
{
uint status = _SUCCESS;
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
int i;
status = padapter->hal_func.hal_deinit(padapter);
@@ -419,20 +645,20 @@ void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val)
padapter->hal_func.GetHwRegHandler(padapter, variable, val);
}
u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue)
u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue)
{
return padapter->hal_func.SetHalDefVarHandler(padapter, eVariable, pValue);
}
u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue)
u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue)
{
return padapter->hal_func.get_hal_def_var_handler(padapter, eVariable, pValue);
}
void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet)
void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet)
{
padapter->hal_func.SetHalODMVarHandler(padapter, eVariable, pValue1, bSet);
}
void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, PVOID pValue2)
void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2)
{
padapter->hal_func.GetHalODMVarHandler(padapter, eVariable, pValue1, pValue2);
}
@@ -467,7 +693,15 @@ u8 rtw_hal_check_ips_status(_adapter *padapter)
s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan)
{
return padapter->hal_func.fw_dl(padapter, wowlan);
s32 ret;
ret = padapter->hal_func.fw_dl(padapter, wowlan);
#ifdef CONFIG_LPS_1T1R
GET_HAL_DATA(padapter)->lps_1t1r = 0;
#endif
return ret;
}
#ifdef RTW_HALMAC
@@ -610,7 +844,6 @@ s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe)
rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe);
#endif
no_mgmt_coalesce:
ret = padapter->hal_func.mgnt_xmit(padapter, pmgntframe);
return ret;
}
@@ -635,7 +868,6 @@ void rtw_hal_free_recv_priv(_adapter *padapter)
void rtw_sta_ra_registed(_adapter *padapter, struct sta_info *psta)
{
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
if (psta == NULL) {
@@ -714,10 +946,12 @@ u32 rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u3
if (padapter->hal_func.read_rfreg) {
data = padapter->hal_func.read_rfreg(padapter, eRFPath, RegAddr, BitMask);
if (match_rf_read_sniff_ranges(eRFPath, RegAddr, BitMask)) {
#ifdef DBG_IO
if (match_rf_read_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) {
RTW_INFO("DBG_IO rtw_hal_read_rfreg(%u, 0x%04x, 0x%08x) read:0x%08x(0x%08x)\n"
, eRFPath, RegAddr, BitMask, (data << PHY_CalculateBitShift(BitMask)), data);
}
#endif
}
return data;
@@ -727,10 +961,12 @@ void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr,
{
if (padapter->hal_func.write_rfreg) {
if (match_rf_write_sniff_ranges(eRFPath, RegAddr, BitMask)) {
#ifdef DBG_IO
if (match_rf_write_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) {
RTW_INFO("DBG_IO rtw_hal_write_rfreg(%u, 0x%04x, 0x%08x) write:0x%08x(0x%08x)\n"
, eRFPath, RegAddr, BitMask, (Data << PHY_CalculateBitShift(BitMask)), Data);
}
#endif
padapter->hal_func.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);
@@ -781,7 +1017,7 @@ void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf)
void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
u8 cch_160 = Bandwidth == CHANNEL_WIDTH_160 ? channel : 0;
/*u8 cch_160 = Bandwidth == CHANNEL_WIDTH_160 ? channel : 0;*/
u8 cch_80 = Bandwidth == CHANNEL_WIDTH_80 ? channel : 0;
u8 cch_40 = Bandwidth == CHANNEL_WIDTH_40 ? channel : 0;
u8 cch_20 = Bandwidth == CHANNEL_WIDTH_20 ? channel : 0;
@@ -816,27 +1052,11 @@ void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Band
padapter->hal_func.set_chnl_bw_handler(padapter, channel, Bandwidth, Offset40, Offset80);
}
void rtw_hal_set_tx_power_level(_adapter *padapter, u8 channel)
{
if (padapter->hal_func.set_tx_power_level_handler)
padapter->hal_func.set_tx_power_level_handler(padapter, channel);
}
void rtw_hal_get_tx_power_level(_adapter *padapter, s32 *powerlevel)
{
if (padapter->hal_func.get_tx_power_level_handler)
padapter->hal_func.get_tx_power_level_handler(padapter, powerlevel);
}
void rtw_hal_dm_watchdog(_adapter *padapter)
{
rtw_hal_turbo_edca(padapter);
padapter->hal_func.hal_dm_watchdog(padapter);
#ifdef CONFIG_PCI_DYNAMIC_ASPM
rtw_pci_aspm_config_dynamic_l1_ilde_time(padapter);
#endif
}
#ifdef CONFIG_LPS_LCLK_WD_TIMER
@@ -937,7 +1157,6 @@ void rtw_hal_notch_filter(_adapter *adapter, bool enable)
inline bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf)
{
HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
HAL_VERSION *hal_ver = &HalData->version_id;
bool ret = _FAIL;
ret = C2H_ID_88XX(buf) || C2H_PLEN_88XX(buf);
@@ -948,7 +1167,6 @@ inline bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf)
inline s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf)
{
HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
HAL_VERSION *hal_ver = &HalData->version_id;
s32 ret = _FAIL;
ret = c2h_evt_read_88xx(adapter, buf);
@@ -959,7 +1177,6 @@ inline s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf)
bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload)
{
HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
HAL_VERSION *hal_ver = &HalData->version_id;
bool ret = _FAIL;
*id = C2H_ID_88XX(buf);
@@ -976,7 +1193,6 @@ bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *
bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload)
{
HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
HAL_VERSION *hal_ver = &HalData->version_id;
bool ret = _FAIL;
if (!buf || len > 256 || len < 3)
@@ -1073,18 +1289,17 @@ s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
case C2H_LPS_STATUS_RPT:
c2h_lps_status_rpt(adapter, payload, plen);
break;
#endif
#endif
case C2H_EXTEND:
sub_id = payload[0];
/* no handle, goto default */
/* fall through */
default:
if (phydm_c2H_content_parsing(adapter_to_phydm(adapter), id, plen, payload) != TRUE)
ret = _FAIL;
break;
}
exit:
if (ret != _SUCCESS) {
if (id == C2H_EXTEND)
RTW_WARN("%s: unknown C2H(0x%02x, 0x%02x)\n", __func__, id, sub_id);
@@ -1130,6 +1345,74 @@ s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter)
return GET_HAL_DATA(padapter)->bDisableSWChannelPlan;
}
#ifdef CONFIG_PROTSEL_MACSLEEP
static s32 _rtw_hal_macid_sleep(_adapter *adapter, u8 macid, u8 sleep)
{
struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
u16 reg_sleep_info = macid_ctl->reg_sleep_info;
u16 reg_sleep_ctrl = macid_ctl->reg_sleep_ctrl;
const u32 sel_mask_sel = BIT(0) | BIT(1) | BIT(2);
u8 bit_shift;
u32 val32;
s32 ret = _FAIL;
if (macid >= macid_ctl->num) {
RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" , macid);
goto exit;
}
if (macid < 32) {
bit_shift = macid;
#if (MACID_NUM_SW_LIMIT > 32)
} else if (macid < 64) {
bit_shift = macid - 32;
#endif
#if (MACID_NUM_SW_LIMIT > 64)
} else if (macid < 96) {
bit_shift = macid - 64;
#endif
#if (MACID_NUM_SW_LIMIT > 96)
} else if (macid < 128) {
bit_shift = macid - 96;
#endif
} else {
rtw_warn_on(1);
goto exit;
}
if (!reg_sleep_ctrl || !reg_sleep_info) {
rtw_warn_on(1);
goto exit;
}
val32 = rtw_read32(adapter, reg_sleep_ctrl);
val32 = (val32 &~sel_mask_sel) | ((macid / 32) & sel_mask_sel);
rtw_write32(adapter, reg_sleep_ctrl, val32);
val32 = rtw_read32(adapter, reg_sleep_info);
RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
, macid, reg_sleep_info, val32);
ret = _SUCCESS;
if (sleep) {
if (val32 & BIT(bit_shift))
goto exit;
val32 |= BIT(bit_shift);
} else {
if (!(val32 & BIT(bit_shift)))
goto exit;
val32 &= ~BIT(bit_shift);
}
rtw_write32(adapter, reg_sleep_info, val32);
exit:
return ret;
}
#else
static s32 _rtw_hal_macid_sleep(_adapter *adapter, u8 macid, u8 sleep)
{
struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
@@ -1194,6 +1477,7 @@ static s32 _rtw_hal_macid_sleep(_adapter *adapter, u8 macid, u8 sleep)
exit:
return ret;
}
#endif
inline s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid)
{
@@ -1205,6 +1489,73 @@ inline s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid)
return _rtw_hal_macid_sleep(adapter, macid, 0);
}
#ifdef CONFIG_PROTSEL_MACSLEEP
static s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8 sleep)
{
struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
u16 reg_sleep_info = macid_ctl->reg_sleep_info;
u16 reg_sleep_ctrl = macid_ctl->reg_sleep_ctrl;
const u32 sel_mask_sel = BIT(0) | BIT(1) | BIT(2);
u32 m;
u8 mid = 0;
u32 val32;
do {
if (mid == 0) {
m = bmp->m0;
#if (MACID_NUM_SW_LIMIT > 32)
} else if (mid == 1) {
m = bmp->m1;
#endif
#if (MACID_NUM_SW_LIMIT > 64)
} else if (mid == 2) {
m = bmp->m2;
#endif
#if (MACID_NUM_SW_LIMIT > 96)
} else if (mid == 3) {
m = bmp->m3;
#endif
} else {
rtw_warn_on(1);
break;
}
if (m == 0)
goto move_next;
if (!reg_sleep_ctrl || !reg_sleep_info) {
rtw_warn_on(1);
break;
}
val32 = rtw_read32(adapter, reg_sleep_ctrl);
val32 = (val32 &~sel_mask_sel) | (mid & sel_mask_sel);
rtw_write32(adapter, reg_sleep_ctrl, val32);
val32 = rtw_read32(adapter, reg_sleep_info);
RTW_INFO(ADPT_FMT" %s m%u=0x%08x, ori reg_0x%03x=0x%08x\n"
, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
, mid, m, reg_sleep_info, val32);
if (sleep) {
if ((val32 & m) == m)
goto move_next;
val32 |= m;
} else {
if ((val32 & m) == 0)
goto move_next;
val32 &= ~m;
}
rtw_write32(adapter, reg_sleep_info, val32);
move_next:
mid++;
} while (mid * 32 < MACID_NUM_SW_LIMIT);
return _SUCCESS;
}
#else
static s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8 sleep)
{
struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
@@ -1268,6 +1619,7 @@ move_next:
return _SUCCESS;
}
#endif
inline s32 rtw_hal_macid_sleep_all_used(_adapter *adapter)
{
@@ -1350,14 +1702,53 @@ void rtw_hal_fw_correct_bcn(_adapter *padapter)
}
#endif
void rtw_hal_set_tx_power_index(PADAPTER padapter, u32 powerindex, enum rf_path rfpath, u8 rate)
void rtw_hal_set_tx_power_level(_adapter *adapter, u8 channel)
{
return padapter->hal_func.set_tx_power_index_handler(padapter, powerindex, rfpath, rate);
if (phy_chk_ch_setting_consistency(adapter, channel) != _SUCCESS)
return;
adapter->hal_func.set_tx_power_level_handler(adapter, channel);
rtw_hal_set_txpwr_done(adapter);
}
u8 rtw_hal_get_tx_power_index(PADAPTER padapter, enum rf_path rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic)
void rtw_hal_update_txpwr_level(_adapter *adapter)
{
return padapter->hal_func.get_tx_power_index_handler(padapter, rfpath, rate, bandwidth, channel, tic);
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
rtw_hal_set_tx_power_level(adapter, hal_data->current_channel);
}
void rtw_hal_set_txpwr_done(_adapter *adapter)
{
if (adapter->hal_func.set_txpwr_done)
adapter->hal_func.set_txpwr_done(adapter);
}
void rtw_hal_set_tx_power_index(_adapter *adapter, u32 powerindex
, enum rf_path rfpath, u8 rate)
{
adapter->hal_func.set_tx_power_index_handler(adapter, powerindex, rfpath, rate);
}
u8 rtw_hal_get_tx_power_index(_adapter *adapter, enum rf_path rfpath
, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch
, struct txpwr_idx_comp *tic)
{
return adapter->hal_func.get_tx_power_index_handler(adapter, rfpath
, rs, rate, bw, band, cch, opch, tic);
}
s8 rtw_hal_get_txpwr_target_extra_bias(_adapter *adapter, enum rf_path rfpath
, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch)
{
s8 val = 0;
if (adapter->hal_func.get_txpwr_target_extra_bias) {
val = adapter->hal_func.get_txpwr_target_extra_bias(adapter
, rfpath, rs, rate, bw, band, cch);
}
return val;
}
#ifdef RTW_HALMAC
@@ -1634,13 +2025,6 @@ u8 rtw_hal_ops_check(_adapter *padapter)
ret = _FAIL;
}
#if defined(RTW_HALMAC) && defined(CONFIG_LPS_PG)
if (NULL == padapter->hal_func.fw_mem_dl) {
rtw_hal_error_msg("fw_mem_dl");
ret = _FAIL;
}
#endif
#ifdef CONFIG_FW_CORRECT_BCN
if (IS_HARDWARE_TYPE_8814A(padapter)
&& NULL == padapter->hal_func.fw_correct_bcn) {
@@ -1649,6 +2033,10 @@ u8 rtw_hal_ops_check(_adapter *padapter)
}
#endif
if (!padapter->hal_func.set_tx_power_level_handler) {
rtw_hal_error_msg("set_tx_power_level_handler");
ret = _FAIL;
}
if (!padapter->hal_func.set_tx_power_index_handler) {
rtw_hal_error_msg("set_tx_power_index_handler");
ret = _FAIL;

723
hal/hal_mcc.c
View File

File diff suppressed because it is too large Load Diff

368
hal/hal_mp.c
View File

@@ -78,17 +78,16 @@ u8 MgntQuery_NssTxRate(u16 Rate)
void hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
u8 ChannelToSw = pMptCtx->MptChannelToSw;
ULONG ulRateIdx = pMptCtx->mpt_rate_index;
ULONG ulbandwidth = pMptCtx->MptBandWidth;
u32 ulRateIdx = pMptCtx->mpt_rate_index;
u32 ulbandwidth = pMptCtx->MptBandWidth;
/* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
(ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
pMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
pMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB);
@@ -149,13 +148,13 @@ void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
u8 i;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
u1Byte u1Channel = pHalData->current_channel;
ULONG ulRateIdx = pMptCtx->mpt_rate_index;
u1Byte DataRate = 0xFF;
u8 u1Channel = pHalData->current_channel;
u32 ulRateIdx = pMptCtx->mpt_rate_index;
u8 DataRate = 0xFF;
/* Do not modify CCK TX filter parameters for 8822B*/
if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) ||
IS_HARDWARE_TYPE_8723D(Adapter) || IS_HARDWARE_TYPE_8192F(Adapter))
IS_HARDWARE_TYPE_8723D(Adapter) || IS_HARDWARE_TYPE_8192F(Adapter) || IS_HARDWARE_TYPE_8822C(Adapter))
return;
DataRate = mpt_to_mgnt_rate(ulRateIdx);
@@ -318,9 +317,7 @@ void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
void hal_mpt_SetChannel(PADAPTER pAdapter)
{
enum rf_path eRFPath;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
struct mp_priv *pmp = &pAdapter->mppriv;
u8 channel = pmp->channel;
u8 bandwidth = pmp->bandwidth;
@@ -330,13 +327,11 @@ void hal_mpt_SetChannel(PADAPTER pAdapter)
pHalData->bSwChnl = _TRUE;
pHalData->bSetChnlBW = _TRUE;
#ifdef CONFIG_RTL8822B
if (bandwidth == 2) {
rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
} else if (bandwidth == 1) {
rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
} else
#endif
rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
@@ -359,13 +354,11 @@ void hal_mpt_SetBandwidth(PADAPTER pAdapter)
pHalData->bSwChnl = _TRUE;
pHalData->bSetChnlBW = _TRUE;
#ifdef CONFIG_RTL8822B
if (bandwidth == 2) {
rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
} else if (bandwidth == 1) {
rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
} else
#endif
rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
hal_mpt_SwitchRfSetting(pAdapter);
@@ -377,8 +370,7 @@ void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
{
switch (Rate) {
case MPT_CCK: {
u4Byte TxAGC = 0, pwr = 0;
u1Byte rf;
u32 TxAGC = 0, pwr = 0;
pwr = pTxPower[RF_PATH_A];
if (pwr < 0x3f) {
@@ -396,8 +388,8 @@ void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
break;
case MPT_OFDM_AND_HT: {
u4Byte TxAGC = 0;
u1Byte pwr = 0, rf;
u32 TxAGC = 0;
u8 pwr = 0;
pwr = pTxPower[0];
if (pwr < 0x3f) {
@@ -435,15 +427,15 @@ void
mpt_SetTxPower(
PADAPTER pAdapter,
MPT_TXPWR_DEF Rate,
pu1Byte pTxPower
u8 *pTxPower
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u1Byte path = 0 , i = 0, MaxRate = MGN_6M;
u1Byte StartPath = RF_PATH_A, EndPath = RF_PATH_B;
u8 path = 0 , i = 0, MaxRate = MGN_6M;
u8 StartPath = RF_PATH_A, EndPath = RF_PATH_B;
if (IS_HARDWARE_TYPE_8814A(pAdapter))
if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8814B(pAdapter))
EndPath = RF_PATH_D;
else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)
|| IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
@@ -451,7 +443,7 @@ mpt_SetTxPower(
switch (Rate) {
case MPT_CCK: {
u1Byte rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
u8 rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
for (path = StartPath; path <= EndPath; path++)
for (i = 0; i < sizeof(rate); ++i)
@@ -459,7 +451,7 @@ mpt_SetTxPower(
}
break;
case MPT_OFDM: {
u1Byte rate[] = {
u8 rate[] = {
MGN_6M, MGN_9M, MGN_12M, MGN_18M,
MGN_24M, MGN_36M, MGN_48M, MGN_54M,
};
@@ -470,7 +462,7 @@ mpt_SetTxPower(
}
break;
case MPT_HT: {
u1Byte rate[] = {
u8 rate[] = {
MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,
MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,
MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,
@@ -495,7 +487,7 @@ mpt_SetTxPower(
}
break;
case MPT_VHT: {
u1Byte rate[] = {
u8 rate[] = {
MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,
MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
@@ -541,7 +533,6 @@ void hal_mpt_SetTxPower(PADAPTER pAdapter)
IS_HARDWARE_TYPE_8188F(pAdapter) ||
IS_HARDWARE_TYPE_8188GTV(pAdapter)
) {
u8 path = (pHalData->antenna_tx_path == ANTENNA_A) ? (RF_PATH_A) : (RF_PATH_B);
RTW_INFO("===> MPT_ProSetTxPower: Old\n");
@@ -553,11 +544,13 @@ void hal_mpt_SetTxPower(PADAPTER pAdapter)
mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
if(IS_HARDWARE_TYPE_JAGUAR(pAdapter)||IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
if(IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n");
mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
}
}
rtw_hal_set_txpwr_done(pAdapter);
} else
RTW_INFO("RFChipID < RF_CHIP_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
@@ -603,12 +596,12 @@ void hal_mpt_SetDataRate(PADAPTER pAdapter)
#define RF_PATH_AB 22
#ifdef CONFIG_RTL8814A
VOID mpt_ToggleIG_8814A(PADAPTER pAdapter)
void mpt_ToggleIG_8814A(PADAPTER pAdapter)
{
u1Byte Path = 0;
u4Byte IGReg = rA_IGI_Jaguar, IGvalue = 0;
u8 Path;
u32 IGReg = rA_IGI_Jaguar, IGvalue = 0;
for (Path; Path <= RF_PATH_D; Path++) {
for (Path = 0; Path <= RF_PATH_D; Path++) {
switch (Path) {
case RF_PATH_B:
IGReg = rB_IGI_Jaguar;
@@ -630,7 +623,7 @@ VOID mpt_ToggleIG_8814A(PADAPTER pAdapter)
}
}
VOID mpt_SetRFPath_8814A(PADAPTER pAdapter)
void mpt_SetRFPath_8814A(PADAPTER pAdapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
@@ -861,18 +854,19 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter)
mpt_ToggleIG_8814A(pAdapter);
}
#endif /* CONFIG_RTL8814A */
#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
VOID
#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
void
mpt_SetSingleTone_8814A(
IN PADAPTER pAdapter,
IN BOOLEAN bSingleTone,
IN BOOLEAN bEnPMacTx)
PADAPTER pAdapter,
BOOLEAN bSingleTone,
BOOLEAN bEnPMacTx)
{
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
u1Byte StartPath = RF_PATH_A, EndPath = RF_PATH_A;
static u4Byte regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
u8 StartPath = RF_PATH_A, EndPath = RF_PATH_A, path;
static u32 regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
if (bSingleTone) {
regIG0 = phy_query_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/
@@ -914,11 +908,11 @@ mpt_SetSingleTone_8814A(
phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
for (StartPath; StartPath <= EndPath; StartPath++) {
phy_set_rf_reg(pAdapter, StartPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
phy_set_rf_reg(pAdapter, StartPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
for (path = StartPath; path <= EndPath; path++) {
phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
phy_set_rf_reg(pAdapter, StartPath, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
}
phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
@@ -952,13 +946,21 @@ mpt_SetSingleTone_8814A(
EndPath = RF_PATH_D;
break;
}
for (StartPath; StartPath <= EndPath; StartPath++)
phy_set_rf_reg(pAdapter, StartPath, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */
for (path = StartPath; path <= EndPath; path++)
phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */
phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
if (bEnPMacTx == FALSE)
hal_mpt_SetContinuousTx(pAdapter, _FALSE);
if (bEnPMacTx == FALSE) {
if(IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
#ifdef PHYDM_MP_SUPPORT
phydm_stop_ofdm_cont_tx(pAdapter);
pMptCtx->bCckContTx = FALSE;
pMptCtx->bOfdmContTx = FALSE;
#endif
} else
hal_mpt_SetContinuousTx(pAdapter, _FALSE);
}
phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
@@ -979,6 +981,7 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter)
u8 bandwidth = pmp->bandwidth;
u8 eLNA_2g = pHalData->ExternalLNA_2G;
u32 ulAntennaTx, ulAntennaRx;
u32 reg0xC50 = 0;
ulAntennaTx = pHalData->antenna_tx_path;
ulAntennaRx = pHalData->AntennaRxPath;
@@ -1009,7 +1012,6 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter)
}
switch (ulAntennaRx) {
u32 reg0xC50 = 0;
case ANTENNA_A:
phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
@@ -1096,6 +1098,7 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter)
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
struct dm_struct *pDM_Odm = &pHalData->odmpriv;
struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
u8 i;
ulAntennaTx = pHalData->antenna_tx_path;
ulAntennaRx = pHalData->AntennaRxPath;
@@ -1106,15 +1109,14 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter)
}
switch (pAdapter->mppriv.antenna_tx) {
u8 p = 0, i = 0;
case ANTENNA_A: { /*/ Actually path S1 (Wi-Fi)*/
pMptCtx->mpt_rf_path = RF_PATH_A;
phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
for (i = 0; i < 3; ++i) {
u4Byte offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
u4Byte data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][1];
u32 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
u32 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][1];
if (offset != 0) {
phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
@@ -1122,8 +1124,8 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter)
}
}
for (i = 0; i < 2; ++i) {
u4Byte offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
u4Byte data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][1];
u32 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
u32 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][1];
if (offset != 0) {
phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
@@ -1133,8 +1135,8 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter)
}
break;
case ANTENNA_B: { /*/ Actually path S0 (BT)*/
u4Byte offset;
u4Byte data;
u32 offset;
u32 data;
pMptCtx->mpt_rf_path = RF_PATH_B;
phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
@@ -1171,10 +1173,11 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter)
void mpt_SetRFPath_8703B(PADAPTER pAdapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u4Byte ulAntennaTx, ulAntennaRx;
u32 ulAntennaTx, ulAntennaRx;
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
struct dm_struct *pDM_Odm = &pHalData->odmpriv;
struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
u8 i;
ulAntennaTx = pHalData->antenna_tx_path;
ulAntennaRx = pHalData->AntennaRxPath;
@@ -1185,16 +1188,14 @@ void mpt_SetRFPath_8703B(PADAPTER pAdapter)
}
switch (pAdapter->mppriv.antenna_tx) {
u1Byte p = 0, i = 0;
case ANTENNA_A: { /* Actually path S1 (Wi-Fi) */
pMptCtx->mpt_rf_path = RF_PATH_A;
phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
for (i = 0; i < 3; ++i) {
u4Byte offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
u4Byte data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
if (offset != 0) {
phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
@@ -1203,8 +1204,8 @@ void mpt_SetRFPath_8703B(PADAPTER pAdapter)
}
for (i = 0; i < 2; ++i) {
u4Byte offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
u4Byte data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
if (offset != 0) {
phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
@@ -1219,8 +1220,8 @@ void mpt_SetRFPath_8703B(PADAPTER pAdapter)
phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
for (i = 0; i < 3; ++i) {
u4Byte offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
u4Byte data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
if (pRFCalibrateInfo->tx_iqc_8703b[i][0] != 0) {
phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
@@ -1228,8 +1229,8 @@ void mpt_SetRFPath_8703B(PADAPTER pAdapter)
}
}
for (i = 0; i < 2; ++i) {
u4Byte offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
u4Byte data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
if (pRFCalibrateInfo->rx_iqc_8703b[i][0] != 0) {
phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
@@ -1250,8 +1251,8 @@ void mpt_SetRFPath_8703B(PADAPTER pAdapter)
void mpt_SetRFPath_8723D(PADAPTER pAdapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u1Byte p = 0, i = 0;
u4Byte ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;
u8 p = 0, i = 0;
u32 ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
struct dm_struct *pDM_Odm = &pHalData->odmpriv;
struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
@@ -1285,16 +1286,16 @@ void mpt_SetRFPath_8723D(PADAPTER pAdapter)
}
#endif
VOID mpt_SetRFPath_819X(PADAPTER pAdapter)
void mpt_SetRFPath_819X(PADAPTER pAdapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
u4Byte ulAntennaTx, ulAntennaRx;
u32 ulAntennaTx, ulAntennaRx;
R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
R_ANTENNA_SELECT_CCK *p_cck_txrx;
u1Byte r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
u1Byte chgTx = 0, chgRx = 0;
u4Byte r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
u8 chgTx = 0, chgRx = 0;
u32 r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
ulAntennaTx = pHalData->antenna_tx_path;
ulAntennaRx = pHalData->AntennaRxPath;
@@ -1454,8 +1455,8 @@ void mpt_set_rfpath_8192f(PADAPTER pAdapter)
u16 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
u8 NssforRate, odmNssforRate;
u32 ulAntennaTx, ulAntennaRx;
u8 RxAntToPhyDm;
u8 TxAntToPhyDm;
enum bb_path RxAntToPhyDm;
enum bb_path TxAntToPhyDm;
ulAntennaTx = pHalData->antenna_tx_path;
ulAntennaRx = pHalData->AntennaRxPath;
@@ -1498,7 +1499,7 @@ void mpt_set_rfpath_8192f(PADAPTER pAdapter)
break;
}
config_phydm_trx_mode_8192f(GET_PDM_ODM(pAdapter), TxAntToPhyDm, RxAntToPhyDm, FALSE);
phydm_api_trx_mode(GET_PDM_ODM(pAdapter), TxAntToPhyDm, RxAntToPhyDm, TxAntToPhyDm);
}
@@ -1508,6 +1509,12 @@ void hal_mpt_SetAntenna(PADAPTER pAdapter)
{
RTW_INFO("Do %s\n", __func__);
#ifdef CONFIG_RTL8822C
if (IS_HARDWARE_TYPE_8822C(pAdapter)) {
rtl8822c_mp_config_rfpath(pAdapter);
return;
}
#endif
#ifdef CONFIG_RTL8814A
if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
mpt_SetRFPath_8814A(pAdapter);
@@ -1560,6 +1567,13 @@ void hal_mpt_SetAntenna(PADAPTER pAdapter)
}
#endif
#ifdef CONFIG_RTL8814B
if (IS_HARDWARE_TYPE_8814B(pAdapter)) {
rtl8814b_mp_config_rfpath(pAdapter);
return;
}
#endif
/* else if (IS_HARDWARE_TYPE_8821B(pAdapter))
mpt_SetRFPath_8821B(pAdapter);
Prepare for 8822B
@@ -1583,12 +1597,7 @@ s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
return _FAIL;
}
target_ther &= 0xff;
if (target_ther < 0x07)
target_ther = 0x07;
else if (target_ther > 0x1d)
target_ther = 0x1d;
pHalData->eeprom_thermal_meter = target_ther;
@@ -1598,20 +1607,33 @@ s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
{
phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x0);
phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
} else
phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
}
u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter)
u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter, u8 rf_path)
{
struct dm_struct *p_dm_odm = adapter_to_phydm(pAdapter);
u32 ThermalValue = 0;
s32 thermal_value_temp = 0;
s8 thermal_offset = 0;
u32 thermal_reg_mask = 0;
if (IS_8822C_SERIES(GET_HAL_DATA(pAdapter)->version_id))
thermal_reg_mask = 0x007e; /*0x42: RF Reg[6:1], 35332(themal K & bias k & power trim) & 35325(tssi )*/
else
thermal_reg_mask = 0xfc00; /*0x42: RF Reg[15:10]*/
ThermalValue = (u8)phy_query_rf_reg(pAdapter, rf_path, 0x42, thermal_reg_mask);
ThermalValue = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, 0x42, 0xfc00); /*0x42: RF Reg[15:10]*/
thermal_offset = phydm_get_thermal_offset(p_dm_odm);
thermal_value_temp = ThermalValue + thermal_offset;
@@ -1627,7 +1649,7 @@ u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter)
}
void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 *value)
void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 rfpath, u8 *value)
{
#if 0
fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
@@ -1637,7 +1659,7 @@ void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 *value)
#else
hal_mpt_TriggerRFThermalMeter(pAdapter);
rtw_msleep_os(1000);
*value = hal_mpt_ReadRFThermalMeter(pAdapter);
*value = hal_mpt_ReadRFThermalMeter(pAdapter, rfpath);
#endif
}
@@ -1663,7 +1685,7 @@ void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
/*/ 4. Turn On Continue Tx and turn off the other test modes.*/
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);
else
#endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
@@ -1674,7 +1696,7 @@ void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
/*/ Stop Single Carrier.*/
/*/ Turn off all test modes.*/
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
else
#endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
@@ -1693,10 +1715,32 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
struct dm_struct *pDM_Odm = &pHalData->odmpriv;
u4Byte ulAntennaTx = pHalData->antenna_tx_path;
static u4Byte regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
u32 ulAntennaTx = pHalData->antenna_tx_path;
static u32 regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
u8 rfPath;
if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
#ifdef PHYDM_MP_SUPPORT
#ifdef CONFIG_RTL8814B
if(pHalData->current_channel_bw == CHANNEL_WIDTH_80_80)
{
/* @Tx mode: RF0x00[19:16]=4'b0010 */
config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x0, 0xF0000, 0x2);
/* @Lowest RF gain index: RF_0x0[4:0] = 0*/
config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x0, 0x1F, 0x0);
/* @RF LO enabled */
config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x58, BIT(1), 0x1);
/* @SYN1 */
config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x0, 0xF0000, 0x2);
config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x0, 0x1F, 0x0);
config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x58, BIT(1), 0x1);
}
#endif
phydm_mp_set_single_tone(pDM_Odm, bStart, pMptCtx->mpt_rf_path);
#endif
return;
}
switch (ulAntennaTx) {
case ANTENNA_B:
rfPath = RF_PATH_B;
@@ -1771,7 +1815,7 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
}
} else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
u1Byte p = RF_PATH_A;
u8 p = RF_PATH_A;
regRF = phy_query_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
regBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
@@ -1893,7 +1937,7 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
}
} else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
u1Byte p = RF_PATH_A;
u8 p = RF_PATH_A;
phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/
@@ -1939,10 +1983,19 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
struct dm_struct *pdm_odm = &pHalData->odmpriv;
u8 Rate;
pAdapter->mppriv.mpt_ctx.is_carrier_suppression = bStart;
if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
#ifdef PHYDM_MP_SUPPORT
phydm_mp_set_carrier_supp(pdm_odm, bStart, pAdapter->mppriv.rateidx);
#endif
return;
}
Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
if (bStart) {/* Start Carrier Suppression.*/
if (Rate <= MPT_RATE_11M) {
@@ -1951,7 +2004,7 @@ void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
/*/Turn Off All Test Mode*/
if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
else
phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
@@ -1988,12 +2041,26 @@ u32 hal_mpt_query_phytxok(PADAPTER pAdapter)
{
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u16 count = 0;
#ifdef PHYDM_MP_SUPPORT
struct dm_struct *dm = (struct dm_struct *)&pHalData->odmpriv;
struct phydm_mp *mp = &dm->dm_mp_table;
if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
phydm_mp_get_tx_ok(&pHalData->odmpriv, pAdapter->mppriv.rateidx);
count = mp->tx_phy_ok_cnt;
} else
#endif
{
if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
count = phy_query_bb_reg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/
else
count = phy_query_bb_reg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/
}
if (count > 50000) {
rtw_reset_phy_trx_ok_counters(pAdapter);
@@ -2005,13 +2072,13 @@ u32 hal_mpt_query_phytxok(PADAPTER pAdapter)
}
static VOID mpt_StopCckContTx(
static void mpt_StopCckContTx(
PADAPTER pAdapter
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
u1Byte u1bReg;
u8 u1bReg;
pMptCtx->bCckContTx = FALSE;
pMptCtx->bOfdmContTx = FALSE;
@@ -2019,7 +2086,7 @@ static VOID mpt_StopCckContTx(
phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
if (!IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/
phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
@@ -2032,32 +2099,41 @@ static VOID mpt_StopCckContTx(
phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
}
if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);/* patch Count CCK adjust Rate*/
}
} /* mpt_StopCckContTx */
static VOID mpt_StopOfdmContTx(
static void mpt_StopOfdmContTx(
PADAPTER pAdapter
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
u1Byte u1bReg;
u4Byte data;
u8 u1bReg;
u32 data;
pMptCtx->bCckContTx = FALSE;
pMptCtx->bOfdmContTx = FALSE;
if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))
if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
else
phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
rtw_mdelay_os(10);
if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)){
phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/
phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
}
@@ -2066,25 +2142,27 @@ static VOID mpt_StopOfdmContTx(
phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
}
} /* mpt_StopOfdmContTx */
static VOID mpt_StartCckContTx(
static void mpt_StartCckContTx(
PADAPTER pAdapter
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
u4Byte cckrate;
u32 cckrate;
/* 1. if CCK block on */
if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn))
phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
/*Turn Off All Test Mode*/
if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
else
phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
@@ -2096,7 +2174,7 @@ static VOID mpt_StartCckContTx(
phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/
phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) {
if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/
phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
@@ -2104,8 +2182,20 @@ static VOID mpt_StartCckContTx(
phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1);
}
phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
}
if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
if (pAdapter->mppriv.rateidx == MPT_RATE_1M) /* patch Count CCK adjust Rate*/
phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);
else
phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bEnable);
}
pMptCtx->bCckContTx = TRUE;
pMptCtx->bOfdmContTx = FALSE;
@@ -2113,7 +2203,7 @@ static VOID mpt_StartCckContTx(
} /* mpt_StartCckContTx */
static VOID mpt_StartOfdmContTx(
static void mpt_StartOfdmContTx(
PADAPTER pAdapter
)
{
@@ -2130,33 +2220,67 @@ static VOID mpt_StartOfdmContTx(
/* 3. turn on scramble setting*/
phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/
phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/
}
/* 4. Turn On Continue Tx and turn off the other test modes.*/
if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))
if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
else
phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
}
pMptCtx->bCckContTx = FALSE;
pMptCtx->bOfdmContTx = TRUE;
} /* mpt_StartOfdmContTx */
#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
static void mpt_convert_phydm_txinfo_for_jaguar3(
RT_PMAC_TX_INFO pMacTxInfo, struct phydm_pmac_info *phydmtxinfo)
{
phydmtxinfo->en_pmac_tx = pMacTxInfo.bEnPMacTx;
phydmtxinfo->mode = pMacTxInfo.Mode;
phydmtxinfo->tx_rate = MRateToHwRate(mpt_to_mgnt_rate(pMacTxInfo.TX_RATE));
phydmtxinfo->tx_sc = pMacTxInfo.TX_SC;
phydmtxinfo->is_short_preamble = pMacTxInfo.bSPreamble;
phydmtxinfo->ndp_sound = pMacTxInfo.NDP_sound;
phydmtxinfo->bw = pMacTxInfo.BandWidth;
phydmtxinfo->m_stbc = pMacTxInfo.m_STBC;
phydmtxinfo->packet_period = pMacTxInfo.PacketPeriod;
phydmtxinfo->packet_count = pMacTxInfo.PacketCount;
phydmtxinfo->packet_pattern = pMacTxInfo.PacketPattern;
phydmtxinfo->sfd = pMacTxInfo.SFD;
phydmtxinfo->signal_field = pMacTxInfo.SignalField;
phydmtxinfo->service_field = pMacTxInfo.ServiceField;
phydmtxinfo->length = pMacTxInfo.LENGTH;
_rtw_memcpy(&phydmtxinfo->crc16,pMacTxInfo.CRC16, 2);
_rtw_memcpy(&phydmtxinfo->lsig , pMacTxInfo.LSIG,3);
_rtw_memcpy(&phydmtxinfo->ht_sig , pMacTxInfo.HT_SIG,6);
_rtw_memcpy(&phydmtxinfo->vht_sig_a , pMacTxInfo.VHT_SIG_A,6);
_rtw_memcpy(&phydmtxinfo->vht_sig_b , pMacTxInfo.VHT_SIG_B,4);
phydmtxinfo->vht_sig_b_crc = pMacTxInfo.VHT_SIG_B_CRC;
_rtw_memcpy(&phydmtxinfo->vht_delimiter,pMacTxInfo.VHT_Delimiter,4);
}
#endif
#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
/* for HW TX mode */
void mpt_ProSetPMacTx(PADAPTER Adapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
struct mp_priv *pmppriv = &Adapter->mppriv;
RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
u32 u4bTmp;
struct dm_struct *p_dm_odm;
p_dm_odm = &pHalData->odmpriv;
#if 0
PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);
@@ -2179,6 +2303,16 @@ void mpt_ProSetPMacTx(PADAPTER Adapter)
RTW_INFO("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
if (IS_HARDWARE_TYPE_JAGUAR3(Adapter)) {
#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
struct phydm_pmac_info phydm_mactxinfo;
mpt_convert_phydm_txinfo_for_jaguar3(PMacTxInfo, &phydm_mactxinfo);
phydm_set_pmac_tx(p_dm_odm, &phydm_mactxinfo, pMptCtx->mpt_rf_path);
#endif
return;
}
if (PMacTxInfo.bEnPMacTx == FALSE) {
if (pMptCtx->HWTxmode == CONTINUOUS_TX) {
phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
@@ -2336,7 +2470,7 @@ void mpt_ProSetPMacTx(PADAPTER Adapter)
phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp);
if (IS_HARDWARE_TYPE_JAGUAR2(Adapter)) {
u4Byte offset = 0xb44;
u32 offset = 0xb44;
if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
@@ -2346,7 +2480,7 @@ void mpt_ProSetPMacTx(PADAPTER Adapter)
phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
} else if(IS_HARDWARE_TYPE_JAGUAR(Adapter)) {
u4Byte offset = 0xb4c;
u32 offset = 0xb4c;
if(IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);

74
hal/hal_phy.c
View File

@@ -22,10 +22,10 @@
* OverView: Get shifted position of the BitMask
*
* Input:
* u4Byte BitMask,
* u32 BitMask,
*
* Output: none
* Return: u4Byte Return the shift bit bit position of the mask
* Return: u32 Return the shift bit bit position of the mask
*/
u32
PHY_CalculateBitShift(
@@ -80,21 +80,21 @@ static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
*---------------------------------------------------------------------------*/
u32
PHY_RFShadowRead(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 Offset)
PADAPTER Adapter,
enum rf_path eRFPath,
u32 Offset)
{
return RF_Shadow[eRFPath][Offset].Value;
} /* PHY_RFShadowRead */
VOID
void
PHY_RFShadowWrite(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 Offset,
IN u32 Data)
PADAPTER Adapter,
enum rf_path eRFPath,
u32 Offset,
u32 Data)
{
RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask);
RF_Shadow[eRFPath][Offset].Driver_Write = _TRUE;
@@ -104,9 +104,9 @@ PHY_RFShadowWrite(
BOOLEAN
PHY_RFShadowCompare(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 Offset)
PADAPTER Adapter,
enum rf_path eRFPath,
u32 Offset)
{
u32 reg;
/* Check if we need to check the register */
@@ -123,11 +123,11 @@ PHY_RFShadowCompare(
} /* PHY_RFShadowCompare */
VOID
void
PHY_RFShadowRecorver(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 Offset)
PADAPTER Adapter,
enum rf_path eRFPath,
u32 Offset)
{
/* Check if the address is error */
if (RF_Shadow[eRFPath][Offset].ErrorOrNot == _TRUE) {
@@ -141,9 +141,9 @@ PHY_RFShadowRecorver(
} /* PHY_RFShadowRecorver */
VOID
void
PHY_RFShadowCompareAll(
IN PADAPTER Adapter)
PADAPTER Adapter)
{
enum rf_path eRFPath = RF_PATH_A;
u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
@@ -156,9 +156,9 @@ PHY_RFShadowCompareAll(
} /* PHY_RFShadowCompareAll */
VOID
void
PHY_RFShadowRecorverAll(
IN PADAPTER Adapter)
PADAPTER Adapter)
{
enum rf_path eRFPath = RF_PATH_A;
u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
@@ -171,12 +171,12 @@ PHY_RFShadowRecorverAll(
} /* PHY_RFShadowRecorverAll */
VOID
void
PHY_RFShadowCompareFlagSet(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 Offset,
IN u8 Type)
PADAPTER Adapter,
enum rf_path eRFPath,
u32 Offset,
u8 Type)
{
/* Set True or False!!! */
RF_Shadow[eRFPath][Offset].Compare = Type;
@@ -184,12 +184,12 @@ PHY_RFShadowCompareFlagSet(
} /* PHY_RFShadowCompareFlagSet */
VOID
void
PHY_RFShadowRecorverFlagSet(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 Offset,
IN u8 Type)
PADAPTER Adapter,
enum rf_path eRFPath,
u32 Offset,
u8 Type)
{
/* Set True or False!!! */
RF_Shadow[eRFPath][Offset].Recorver = Type;
@@ -197,9 +197,9 @@ PHY_RFShadowRecorverFlagSet(
} /* PHY_RFShadowRecorverFlagSet */
VOID
void
PHY_RFShadowCompareFlagSetAll(
IN PADAPTER Adapter)
PADAPTER Adapter)
{
enum rf_path eRFPath = RF_PATH_A;
u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
@@ -217,9 +217,9 @@ PHY_RFShadowCompareFlagSetAll(
} /* PHY_RFShadowCompareFlagSetAll */
VOID
void
PHY_RFShadowRecorverFlagSetAll(
IN PADAPTER Adapter)
PADAPTER Adapter)
{
enum rf_path eRFPath = RF_PATH_A;
u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
@@ -236,9 +236,9 @@ PHY_RFShadowRecorverFlagSetAll(
} /* PHY_RFShadowCompareFlagSetAll */
VOID
void
PHY_RFShadowRefresh(
IN PADAPTER Adapter)
PADAPTER Adapter)
{
enum rf_path eRFPath = RF_PATH_A;
u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);

6
hal/halmac/halmac_2_platform.h
View File

@@ -73,6 +73,12 @@
*/
#define HALMAC_MSG_LEVEL HALMAC_MSG_LEVEL_TRACE
#ifdef DBG_IO
#define HALMAC_DBG_MONITOR_IO 1
#else
#define HALMAC_DBG_MONITOR_IO 0
#endif /*DBG_IO*/
/*[Driver] define the Rx FIFO expanding mode packet size unit for 8821C and 8822B */
/*Should be 8 Byte alignment*/
#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 80 /*Bytes*/

2
hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2017 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2017 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2017 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2017 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

205
hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -460,6 +460,15 @@ static enum halmac_ret_status
chk_pinmux_valid_8822b(struct halmac_adapter *adapter,
enum halmac_gpio_func gpio_func);
static enum halmac_ret_status
pinmux_switch_8822b(struct halmac_adapter *adapter,
const struct halmac_gpio_pimux_list *list, u32 size,
u32 gpio_id, enum halmac_gpio_func gpio_func);
static enum halmac_ret_status
pinmux_record_8822b(struct halmac_adapter *adapter,
enum halmac_gpio_func gpio_func, u8 val);
/**
* pinmux_get_func_8822b() -get current gpio status
* @adapter : the adapter of halmac
@@ -559,12 +568,12 @@ pinmux_set_func_8822b(struct halmac_adapter *adapter,
if (status != HALMAC_RET_SUCCESS)
return status;
status = pinmux_switch_88xx(adapter, list, list_size, gpio_id,
gpio_func);
status = pinmux_switch_8822b(adapter, list, list_size, gpio_id,
gpio_func);
if (status != HALMAC_RET_SUCCESS)
return status;
status = pinmux_record_88xx(adapter, gpio_func, 1);
status = pinmux_record_8822b(adapter, gpio_func, 1);
if (status != HALMAC_RET_SUCCESS)
return status;
@@ -646,6 +655,13 @@ pinmux_free_func_8822b(struct halmac_adapter *adapter,
case HALMAC_GPIO_FUNC_SW_IO_15:
info->sw_io_15 = 0;
break;
case HALMAC_GPIO_FUNC_S0_PAPE:
case HALMAC_GPIO_FUNC_S0_TRSW:
case HALMAC_GPIO_FUNC_S0_TRSWB:
case HALMAC_GPIO_FUNC_S1_PAPE:
case HALMAC_GPIO_FUNC_S1_TRSW:
case HALMAC_GPIO_FUNC_S1_TRSWB:
return HALMAC_RET_PINMUX_NOT_SUPPORT;
default:
return HALMAC_RET_SWITCH_CASE_ERROR;
}
@@ -747,6 +763,13 @@ get_pinmux_list_8822b(struct halmac_adapter *adapter,
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO15_8822B);
*gpio_id = HALMAC_GPIO15;
break;
case HALMAC_GPIO_FUNC_S0_PAPE:
case HALMAC_GPIO_FUNC_S0_TRSW:
case HALMAC_GPIO_FUNC_S0_TRSWB:
case HALMAC_GPIO_FUNC_S1_PAPE:
case HALMAC_GPIO_FUNC_S1_TRSW:
case HALMAC_GPIO_FUNC_S1_TRSWB:
return HALMAC_RET_PINMUX_NOT_SUPPORT;
default:
return HALMAC_RET_SWITCH_CASE_ERROR;
}
@@ -842,6 +865,13 @@ chk_pinmux_valid_8822b(struct halmac_adapter *adapter,
if (info->sw_io_15 == 1)
status = HALMAC_RET_PINMUX_USED;
break;
case HALMAC_GPIO_FUNC_S0_PAPE:
case HALMAC_GPIO_FUNC_S0_TRSW:
case HALMAC_GPIO_FUNC_S0_TRSWB:
case HALMAC_GPIO_FUNC_S1_PAPE:
case HALMAC_GPIO_FUNC_S1_TRSW:
case HALMAC_GPIO_FUNC_S1_TRSWB:
return HALMAC_RET_PINMUX_NOT_SUPPORT;
default:
return HALMAC_RET_SWITCH_CASE_ERROR;
}
@@ -852,4 +882,171 @@ chk_pinmux_valid_8822b(struct halmac_adapter *adapter,
return status;
}
static enum halmac_ret_status
pinmux_switch_8822b(struct halmac_adapter *adapter,
const struct halmac_gpio_pimux_list *list, u32 size,
u32 gpio_id, enum halmac_gpio_func gpio_func)
{
u32 i;
u8 value8;
u16 switch_func;
const struct halmac_gpio_pimux_list *cur_list = list;
enum halmac_gpio_cfg_state *state;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
state = &adapter->halmac_state.gpio_cfg_state;
if (*state == HALMAC_GPIO_CFG_STATE_BUSY)
return HALMAC_RET_BUSY_STATE;
switch (gpio_func) {
case HALMAC_GPIO_FUNC_WL_LED:
switch_func = HALMAC_WL_LED;
break;
case HALMAC_GPIO_FUNC_SDIO_INT:
switch_func = HALMAC_SDIO_INT;
break;
case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
switch_func = HALMAC_GPIO13_14_WL_CTRL_EN;
break;
case HALMAC_GPIO_FUNC_SW_IO_0:
case HALMAC_GPIO_FUNC_SW_IO_1:
case HALMAC_GPIO_FUNC_SW_IO_2:
case HALMAC_GPIO_FUNC_SW_IO_3:
case HALMAC_GPIO_FUNC_SW_IO_4:
case HALMAC_GPIO_FUNC_SW_IO_5:
case HALMAC_GPIO_FUNC_SW_IO_6:
case HALMAC_GPIO_FUNC_SW_IO_7:
case HALMAC_GPIO_FUNC_SW_IO_8:
case HALMAC_GPIO_FUNC_SW_IO_9:
case HALMAC_GPIO_FUNC_SW_IO_10:
case HALMAC_GPIO_FUNC_SW_IO_11:
case HALMAC_GPIO_FUNC_SW_IO_12:
case HALMAC_GPIO_FUNC_SW_IO_13:
case HALMAC_GPIO_FUNC_SW_IO_14:
case HALMAC_GPIO_FUNC_SW_IO_15:
switch_func = HALMAC_SW_IO;
break;
default:
return HALMAC_RET_SWITCH_CASE_ERROR;
}
for (i = 0; i < size; i++) {
if (gpio_id != cur_list->id) {
PLTFM_MSG_ERR("[ERR]offset:%X, value:%X, func:%X\n",
cur_list->offset, cur_list->value,
cur_list->func);
PLTFM_MSG_ERR("[ERR]id1 : %X, id2 : %X\n",
gpio_id, cur_list->id);
return HALMAC_RET_GET_PINMUX_ERR;
}
if (switch_func == cur_list->func)
break;
cur_list++;
}
if (i == size) {
PLTFM_MSG_ERR("[ERR]gpio func error:%X %X\n",
gpio_id, cur_list->id);
return HALMAC_RET_GET_PINMUX_ERR;
}
*state = HALMAC_GPIO_CFG_STATE_BUSY;
cur_list = list;
for (i = 0; i < size; i++) {
value8 = HALMAC_REG_R8(cur_list->offset);
value8 &= ~(cur_list->msk);
if (switch_func == cur_list->func) {
value8 |= (cur_list->value & cur_list->msk);
HALMAC_REG_W8(cur_list->offset, value8);
break;
}
value8 |= (~cur_list->value & cur_list->msk);
HALMAC_REG_W8(cur_list->offset, value8);
cur_list++;
}
*state = HALMAC_GPIO_CFG_STATE_IDLE;
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
pinmux_record_8822b(struct halmac_adapter *adapter,
enum halmac_gpio_func gpio_func, u8 val)
{
switch (gpio_func) {
case HALMAC_GPIO_FUNC_WL_LED:
adapter->pinmux_info.wl_led = val;
break;
case HALMAC_GPIO_FUNC_SDIO_INT:
adapter->pinmux_info.sdio_int = val;
break;
case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
adapter->pinmux_info.bt_host_wake = val;
break;
case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
adapter->pinmux_info.bt_dev_wake = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_0:
adapter->pinmux_info.sw_io_0 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_1:
adapter->pinmux_info.sw_io_1 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_2:
adapter->pinmux_info.sw_io_2 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_3:
adapter->pinmux_info.sw_io_3 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_4:
adapter->pinmux_info.sw_io_4 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_5:
adapter->pinmux_info.sw_io_5 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_6:
adapter->pinmux_info.sw_io_6 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_7:
adapter->pinmux_info.sw_io_7 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_8:
adapter->pinmux_info.sw_io_8 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_9:
adapter->pinmux_info.sw_io_9 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_10:
adapter->pinmux_info.sw_io_10 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_11:
adapter->pinmux_info.sw_io_11 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_12:
adapter->pinmux_info.sw_io_12 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_13:
adapter->pinmux_info.sw_io_13 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_14:
adapter->pinmux_info.sw_io_14 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_15:
adapter->pinmux_info.sw_io_15 = val;
break;
default:
return HALMAC_RET_GET_PINMUX_ERR;
}
return HALMAC_RET_SUCCESS;
}
#endif /* HALMAC_8822B_SUPPORT */

2
hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

26
hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -359,6 +359,8 @@ mount_api_8822b(struct halmac_adapter *adapter)
if (adapter->intf == HALMAC_INTERFACE_SDIO) {
#if HALMAC_SDIO_SUPPORT
api->halmac_init_interface_cfg = init_sdio_cfg_8822b;
api->halmac_init_sdio_cfg = init_sdio_cfg_8822b;
api->halmac_mac_power_switch = mac_pwr_switch_sdio_8822b;
api->halmac_phy_cfg = phy_cfg_sdio_8822b;
api->halmac_pcie_switch = pcie_switch_sdio_8822b;
@@ -417,6 +419,8 @@ init_trx_cfg_8822b(struct halmac_adapter *adapter, enum halmac_trx_mode mode)
u8 value8;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
u8 en_fwff;
u16 value16;
adapter->trx_mode = mode;
@@ -428,10 +432,22 @@ init_trx_cfg_8822b(struct halmac_adapter *adapter, enum halmac_trx_mode mode)
return status;
}
en_fwff = HALMAC_REG_R8(REG_WMAC_FWPKT_CR) & BIT_FWEN;
if (en_fwff) {
HALMAC_REG_W8_CLR(REG_WMAC_FWPKT_CR, BIT_FWEN);
if (fwff_is_empty_88xx(adapter) != HALMAC_RET_SUCCESS)
PLTFM_MSG_ERR("[ERR]fwff is not empty\n");
}
value8 = 0;
HALMAC_REG_W8(REG_CR, value8);
value16 = HALMAC_REG_R16(REG_FWFF_PKT_INFO);
HALMAC_REG_W16(REG_FWFF_CTRL, value16);
value8 = MAC_TRX_ENABLE;
HALMAC_REG_W8(REG_CR, value8);
if (en_fwff)
HALMAC_REG_W8_SET(REG_WMAC_FWPKT_CR, BIT_FWEN);
HALMAC_REG_W32(REG_H2CQ_CSR, BIT(31));
status = priority_queue_cfg_8822b(adapter, mode);
@@ -701,13 +717,15 @@ init_system_cfg_8822b(struct halmac_adapter *adapter)
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
u32 tmp = 0;
u32 value32;
u8 value8;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
value32 = HALMAC_REG_R32(REG_CPU_DMEM_CON) | BIT_WL_PLATFORM_RST;
HALMAC_REG_W32(REG_CPU_DMEM_CON, value32);
HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, SYS_FUNC_EN);
value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN + 1) | SYS_FUNC_EN;
HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, value8);
/*disable boot-from-flash for driver's DL FW*/
tmp = HALMAC_REG_R32(REG_MCUFW_CTRL);
@@ -890,6 +908,10 @@ init_wmac_cfg_8822b(struct halmac_adapter *adapter)
HALMAC_REG_W8(REG_TCR + 2, WLAN_TX_FUNC_CFG2);
HALMAC_REG_W8(REG_TCR + 1, WLAN_TX_FUNC_CFG1);
HALMAC_REG_W8_SET(REG_WMAC_TRXPTCL_CTL + 4, BIT(1));
HALMAC_REG_W8_SET(REG_SND_PTCL_CTRL, BIT_R_DISABLE_CHECK_VHTSIGB_CRC);
HALMAC_REG_W32(REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
if (adapter->hw_cfg_info.trx_mode == HALMAC_TRNSFER_NORMAL)

2
hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

56
hal/halmac/halmac_88xx/halmac_8822b/halmac_phy_8822b.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -42,7 +42,7 @@ struct halmac_intf_phy_para usb2_phy_param_8822b[] = {
{0xFFFF, 0x00,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_ALL,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
};
struct halmac_intf_phy_para usb3_phy_param_8822b[] = {
@@ -50,11 +50,11 @@ struct halmac_intf_phy_para usb3_phy_param_8822b[] = {
{0x0001, 0xA841,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_D,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0xFFFF, 0x0000,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_ALL,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
};
struct halmac_intf_phy_para pcie_gen1_phy_param_8822b[] = {
@@ -62,47 +62,51 @@ struct halmac_intf_phy_para pcie_gen1_phy_param_8822b[] = {
{0x0001, 0xA841,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0x0002, 0x60C6,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0x0008, 0x3596,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0x0009, 0x321C,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0x000A, 0x9623,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0x001B, 0xE029,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_ALL,
HALMAC_INTF_PHY_PLATFORM_ASUS},
{0x0020, 0x94FF,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0x0021, 0xFFCF,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0x0026, 0xC006,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0x0029, 0xFF0E,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0x002A, 0x1840,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0xFFFF, 0x0000,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_ALL,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
};
struct halmac_intf_phy_para pcie_gen2_phy_param_8822b[] = {
@@ -110,47 +114,47 @@ struct halmac_intf_phy_para pcie_gen2_phy_param_8822b[] = {
{0x0001, 0xA841,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0x0002, 0x60C6,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0x0008, 0x3597,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0x0009, 0x321C,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0x000A, 0x9623,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0x0020, 0x94FF,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0x0021, 0xFFCF,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0x0026, 0xC006,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0x0029, 0xFF0E,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0x002A, 0x3040,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
{0xFFFF, 0x0000,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_ALL,
HALMAC_INTF_PHY_PLATFORM_ALL},
HALMAC_INTF_PHY_PLATFORM_FOR_ALL},
};
#endif /* HALMAC_8822B_SUPPORT */

34
hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -58,6 +58,16 @@ static struct halmac_wlan_pwr_cfg TRANS_CARDDIS_TO_CARDEMU_8822B[] = {
static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_ACT_8822B[] = {
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
{0xFF0A,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0},
{0xFF0B,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0},
{0x0012,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK,
@@ -440,16 +450,6 @@ static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_SUS_8822B[] = {
static struct halmac_wlan_pwr_cfg TRANS_SUS_TO_CARDEMU_8822B[] = {
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
{0xFF0A,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0},
{0xFF0B,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0},
{0x0005,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK,
@@ -690,32 +690,32 @@ static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_DEEP_LPS_8822B[] = {
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0xDE},
HALMAC_PWR_CMD_WRITE, 0xFF, 0xDC},
{0x0092,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0x60},
HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
{0x0093,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0x9B},
HALMAC_PWR_CMD_WRITE, 0xFF, 0x8},
{0x0092,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0x60},
HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
{0x0093,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0xA},
HALMAC_PWR_CMD_WRITE, 0xFF, 0x8},
{0x0092,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0x60},
HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
{0x0090,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK,

4
hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -21,7 +21,7 @@
#if HALMAC_8822B_SUPPORT
#define HALMAC_8822B_PWR_SEQ_VER "V30"
#define HALMAC_8822B_PWR_SEQ_VER "V31"
extern struct halmac_wlan_pwr_cfg *card_en_flow_8822b[];
extern struct halmac_wlan_pwr_cfg *card_dis_flow_8822b[];

4
hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -38,7 +38,7 @@ mac_pwr_switch_usb_8822b(struct halmac_adapter *adapter,
PLTFM_MSG_TRACE("[TRACE]%s\n", __func__);
PLTFM_MSG_TRACE("[TRACE]%x\n", pwr);
PLTFM_MSG_TRACE("[TRACE]8821C pwr seq ver = %s\n",
PLTFM_MSG_TRACE("[TRACE]8822B pwr seq ver = %s\n",
HALMAC_8822B_PWR_SEQ_VER);
adapter->rpwm = HALMAC_REG_R8(0xFE58);

2
hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
hal/halmac/halmac_88xx/halmac_88xx_cfg.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

6
hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -588,10 +588,10 @@ cfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw)
switch (bw) {
case HALMAC_BW_80:
value32 |= BIT(8);
value32 = value32 | BIT(8);
break;
case HALMAC_BW_40:
value32 |= BIT(7);
value32 = value32 | BIT(7);
break;
case HALMAC_BW_20:
case HALMAC_BW_10:

2
hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

503
hal/halmac/halmac_88xx/halmac_common_88xx.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -90,6 +90,9 @@ get_c2h_dbg_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
static enum halmac_ret_status
get_h2c_ack_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
static enum halmac_ret_status
get_scan_ch_notify_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
static enum halmac_ret_status
get_scan_rpt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
@@ -99,6 +102,14 @@ get_h2c_ack_cfg_param_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
static enum halmac_ret_status
get_h2c_ack_update_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
static enum halmac_ret_status
get_h2c_ack_send_scan_pkt_88xx(struct halmac_adapter *adapter, u8 *buf,
u32 size);
static enum halmac_ret_status
get_h2c_ack_drop_scan_pkt_88xx(struct halmac_adapter *adapter, u8 *buf,
u32 size);
static enum halmac_ret_status
get_h2c_ack_update_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf,
u32 size);
@@ -138,6 +149,14 @@ static enum halmac_ret_status
send_h2c_update_packet_88xx(struct halmac_adapter *adapter,
enum halmac_packet_id pkt_id, u8 *pkt, u32 size);
static enum halmac_ret_status
send_h2c_send_scan_packet_88xx(struct halmac_adapter *adapter,
u8 index, u8 *pkt, u32 size);
static enum halmac_ret_status
send_h2c_drop_scan_packet_88xx(struct halmac_adapter *adapter,
struct halmac_drop_pkt_option *option);
static enum halmac_ret_status
send_bt_coex_cmd_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
u8 ack);
@@ -172,6 +191,14 @@ static enum halmac_ret_status
get_update_packet_status_88xx(struct halmac_adapter *adapter,
enum halmac_cmd_process_status *proc_status);
static enum halmac_ret_status
get_send_scan_packet_status_88xx(struct halmac_adapter *adapter,
enum halmac_cmd_process_status *proc_status);
static enum halmac_ret_status
get_drop_scan_packet_status_88xx(struct halmac_adapter *adapter,
enum halmac_cmd_process_status *proc_status);
static enum halmac_ret_status
pwr_sub_seq_parser_88xx(struct halmac_adapter *adapter, u8 cut, u8 intf,
struct halmac_wlan_pwr_cfg *cmd);
@@ -216,6 +243,9 @@ static enum halmac_packet_id
get_real_pkt_id_88xx(struct halmac_adapter *adapter,
enum halmac_packet_id pkt_id);
static u32
get_update_packet_page_size(struct halmac_adapter *adapter, u32 size);
/**
* ofld_func_cfg_88xx() - config offload function
* @adapter : the adapter of halmac
@@ -535,6 +565,40 @@ set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
case HALMAC_HW_TXFIFO_LIFETIME:
cfg_txfifo_lt_88xx(adapter,
(struct halmac_txfifo_lifetime_cfg *)value);
break;
default:
return HALMAC_RET_PARA_NOT_SUPPORT;
}
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* get_watcher_88xx() -get watcher value
* @adapter : the adapter of halmac
* @sel : id for driver to config
* @value : value, reference table to get data type
* Author :
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
get_watcher_88xx(struct halmac_adapter *adapter, enum halmac_watcher_sel sel,
void *value)
{
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (!value) {
PLTFM_MSG_ERR("[ERR]null ptr-set hw value\n");
return HALMAC_RET_NULL_POINTER;
}
switch (sel) {
case HALMAC_WATCHER_SDIO_RN_FOOL_PROOFING:
*(u32 *)value = adapter->watcher.get_watcher.sdio_rn_not_align;
break;
default:
return HALMAC_RET_PARA_NOT_SUPPORT;
}
@@ -694,6 +758,9 @@ parse_c2h_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
case C2H_SUB_CMD_ID_EFUSE_DATA:
status = get_efuse_data_88xx(adapter, c2h_pkt, c2h_size);
break;
case C2H_SUB_CMD_ID_SCAN_CH_NOTIFY:
status = get_scan_ch_notify_88xx(adapter, c2h_pkt, c2h_size);
break;
default:
PLTFM_MSG_WARN("[WARN]Sub cmd id!!\n");
status = HALMAC_RET_C2H_NOT_HANDLED;
@@ -800,6 +867,12 @@ get_h2c_ack_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
case H2C_SUB_CMD_ID_UPDATE_PKT_ACK:
status = get_h2c_ack_update_pkt_88xx(adapter, buf, size);
break;
case H2C_SUB_CMD_ID_SEND_SCAN_PKT_ACK:
status = get_h2c_ack_send_scan_pkt_88xx(adapter, buf, size);
break;
case H2C_SUB_CMD_ID_DROP_SCAN_PKT_ACK:
status = get_h2c_ack_drop_scan_pkt_88xx(adapter, buf, size);
break;
case H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK:
status = get_h2c_ack_update_datapkt_88xx(adapter, buf, size);
break;
@@ -828,11 +901,56 @@ get_h2c_ack_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
return status;
}
static enum halmac_ret_status
get_scan_ch_notify_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
{
struct halmac_scan_rpt_info *scan_rpt_info = &adapter->scan_rpt_info;
PLTFM_MSG_TRACE("[TRACE]scan mode:%d\n", adapter->ch_sw_info.scan_mode);
if (adapter->ch_sw_info.scan_mode == 1) {
if (scan_rpt_info->avl_buf_size < 12) {
PLTFM_MSG_ERR("[ERR]ch_notify buffer full!!\n");
return HALMAC_RET_CH_SW_NO_BUF;
}
SCAN_CH_NOTIFY_SET_CH_NUM(scan_rpt_info->buf_wptr,
(u8)SCAN_CH_NOTIFY_GET_CH_NUM(buf));
SCAN_CH_NOTIFY_SET_NOTIFY_ID(scan_rpt_info->buf_wptr,
SCAN_CH_NOTIFY_GET_NOTIFY_ID(buf));
SCAN_CH_NOTIFY_SET_STATUS(scan_rpt_info->buf_wptr,
(u8)SCAN_CH_NOTIFY_GET_STATUS(buf));
SCAN_CH_NOTIFY_SET_TSF_0(scan_rpt_info->buf_wptr,
(u8)SCAN_CH_NOTIFY_GET_TSF_0(buf));
SCAN_CH_NOTIFY_SET_TSF_1(scan_rpt_info->buf_wptr,
(u8)SCAN_CH_NOTIFY_GET_TSF_1(buf));
SCAN_CH_NOTIFY_SET_TSF_2(scan_rpt_info->buf_wptr,
(u8)SCAN_CH_NOTIFY_GET_TSF_2(buf));
SCAN_CH_NOTIFY_SET_TSF_3(scan_rpt_info->buf_wptr,
(u8)SCAN_CH_NOTIFY_GET_TSF_3(buf));
SCAN_CH_NOTIFY_SET_TSF_4(scan_rpt_info->buf_wptr,
(u8)SCAN_CH_NOTIFY_GET_TSF_4(buf));
SCAN_CH_NOTIFY_SET_TSF_5(scan_rpt_info->buf_wptr,
(u8)SCAN_CH_NOTIFY_GET_TSF_5(buf));
SCAN_CH_NOTIFY_SET_TSF_6(scan_rpt_info->buf_wptr,
(u8)SCAN_CH_NOTIFY_GET_TSF_6(buf));
SCAN_CH_NOTIFY_SET_TSF_7(scan_rpt_info->buf_wptr,
(u8)SCAN_CH_NOTIFY_GET_TSF_7(buf));
scan_rpt_info->avl_buf_size = scan_rpt_info->avl_buf_size - 12;
scan_rpt_info->total_size = scan_rpt_info->total_size + 12;
scan_rpt_info->buf_wptr = scan_rpt_info->buf_wptr + 12;
}
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
get_scan_rpt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
{
u8 fw_rc;
enum halmac_cmd_process_status proc_status;
struct halmac_scan_rpt_info *scan_rpt_info = &adapter->scan_rpt_info;
fw_rc = (u8)SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(buf);
proc_status = (HALMAC_H2C_RETURN_SUCCESS ==
@@ -843,6 +961,19 @@ get_scan_rpt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
adapter->halmac_state.scan_state.proc_status = proc_status;
if (adapter->ch_sw_info.scan_mode == 1) {
scan_rpt_info->rpt_tsf_low =
((SCAN_STATUS_RPT_GET_TSF_3(buf) << 24) |
(SCAN_STATUS_RPT_GET_TSF_2(buf) << 16) |
(SCAN_STATUS_RPT_GET_TSF_1(buf) << 8) |
(SCAN_STATUS_RPT_GET_TSF_0(buf)));
scan_rpt_info->rpt_tsf_high =
((SCAN_STATUS_RPT_GET_TSF_7(buf) << 24) |
(SCAN_STATUS_RPT_GET_TSF_6(buf) << 16) |
(SCAN_STATUS_RPT_GET_TSF_5(buf) << 8) |
(SCAN_STATUS_RPT_GET_TSF_4(buf)));
}
PLTFM_MSG_TRACE("[TRACE]scan : %X\n", proc_status);
return HALMAC_RET_SUCCESS;
@@ -946,24 +1077,13 @@ get_h2c_ack_update_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
}
static enum halmac_ret_status
get_h2c_ack_update_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf,
u32 size)
{
return HALMAC_RET_NOT_SUPPORT;
}
static enum halmac_ret_status
get_h2c_ack_run_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
{
return HALMAC_RET_NOT_SUPPORT;
}
static enum halmac_ret_status
get_h2c_ack_ch_switch_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
get_h2c_ack_send_scan_pkt_88xx(struct halmac_adapter *adapter,
u8 *buf, u32 size)
{
u8 seq_num;
u8 fw_rc;
struct halmac_scan_state *state = &adapter->halmac_state.scan_state;
struct halmac_scan_pkt_state *state =
&adapter->halmac_state.scan_pkt_state;
enum halmac_cmd_process_status proc_status;
seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
@@ -983,6 +1103,115 @@ get_h2c_ack_ch_switch_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
state->fw_rc = fw_rc;
if (HALMAC_H2C_RETURN_SUCCESS == (enum halmac_h2c_return_code)fw_rc) {
proc_status = HALMAC_CMD_PROCESS_DONE;
state->proc_status = proc_status;
PLTFM_EVENT_SIG(HALMAC_FEATURE_SEND_SCAN_PACKET, proc_status,
NULL, 0);
} else {
proc_status = HALMAC_CMD_PROCESS_ERROR;
state->proc_status = proc_status;
PLTFM_EVENT_SIG(HALMAC_FEATURE_SEND_SCAN_PACKET, proc_status,
&state->fw_rc, 1);
}
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
get_h2c_ack_drop_scan_pkt_88xx(struct halmac_adapter *adapter,
u8 *buf, u32 size)
{
u8 seq_num;
u8 fw_rc;
struct halmac_drop_pkt_state *state =
&adapter->halmac_state.drop_pkt_state;
enum halmac_cmd_process_status proc_status;
seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
state->seq_num, seq_num);
if (seq_num != state->seq_num) {
PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
state->seq_num, seq_num);
return HALMAC_RET_SUCCESS;
}
if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
PLTFM_MSG_ERR("[ERR]not cmd sending\n");
return HALMAC_RET_SUCCESS;
}
fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
state->fw_rc = fw_rc;
if (HALMAC_H2C_RETURN_SUCCESS == (enum halmac_h2c_return_code)fw_rc) {
proc_status = HALMAC_CMD_PROCESS_DONE;
state->proc_status = proc_status;
PLTFM_EVENT_SIG(HALMAC_FEATURE_DROP_SCAN_PACKET, proc_status,
NULL, 0);
} else {
proc_status = HALMAC_CMD_PROCESS_ERROR;
state->proc_status = proc_status;
PLTFM_EVENT_SIG(HALMAC_FEATURE_DROP_SCAN_PACKET, proc_status,
&state->fw_rc, 1);
}
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
get_h2c_ack_update_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf,
u32 size)
{
return HALMAC_RET_NOT_SUPPORT;
}
static enum halmac_ret_status
get_h2c_ack_run_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
{
return HALMAC_RET_NOT_SUPPORT;
}
static enum halmac_ret_status
get_h2c_ack_ch_switch_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
{
u8 seq_num;
u8 fw_rc;
struct halmac_scan_state *state = &adapter->halmac_state.scan_state;
struct halmac_scan_rpt_info *scan_rpt_info = &adapter->scan_rpt_info;
enum halmac_cmd_process_status proc_status;
seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
state->seq_num, seq_num);
if (seq_num != state->seq_num) {
PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
state->seq_num, seq_num);
return HALMAC_RET_SUCCESS;
}
if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
PLTFM_MSG_ERR("[ERR]not cmd sending\n");
return HALMAC_RET_SUCCESS;
}
fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
state->fw_rc = fw_rc;
if (adapter->ch_sw_info.scan_mode == 1) {
scan_rpt_info->ack_tsf_low =
((CH_SWITCH_ACK_GET_TSF_3(buf) << 24) |
(CH_SWITCH_ACK_GET_TSF_2(buf) << 16) |
(CH_SWITCH_ACK_GET_TSF_1(buf) << 8) |
(CH_SWITCH_ACK_GET_TSF_0(buf)));
scan_rpt_info->ack_tsf_high =
((CH_SWITCH_ACK_GET_TSF_7(buf) << 24) |
(CH_SWITCH_ACK_GET_TSF_6(buf) << 16) |
(CH_SWITCH_ACK_GET_TSF_5(buf) << 8) |
(CH_SWITCH_ACK_GET_TSF_4(buf)));
}
if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {
proc_status = HALMAC_CMD_PROCESS_RCVD;
state->proc_status = proc_status;
@@ -1442,6 +1671,7 @@ update_packet_88xx(struct halmac_adapter *adapter, enum halmac_packet_id pkt_id,
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
enum halmac_cmd_process_status *proc_status =
&adapter->halmac_state.update_pkt_state.proc_status;
u8 *used_page = &adapter->halmac_state.update_pkt_state.used_page;
if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_NO_DLFW;
@@ -1468,6 +1698,8 @@ update_packet_88xx(struct halmac_adapter *adapter, enum halmac_packet_id pkt_id,
return status;
}
*used_page = (u8)get_update_packet_page_size(adapter, size);
if (packet_in_nlo_88xx(adapter, pkt_id)) {
*proc_status = HALMAC_CMD_PROCESS_DONE;
adapter->nlo_flag = 1;
@@ -1503,7 +1735,7 @@ send_h2c_update_packet_88xx(struct halmac_adapter *adapter,
UPDATE_PKT_SET_LOC(h2c_buf, pg_offset);
hdr_info.sub_cmd_id = SUB_CMD_ID_UPDATE_PKT;
hdr_info.content_size = 8;
hdr_info.content_size = 4;
if (packet_in_nlo_88xx(adapter, pkt_id))
hdr_info.ack = 0;
else
@@ -1522,6 +1754,147 @@ send_h2c_update_packet_88xx(struct halmac_adapter *adapter,
return status;
}
enum halmac_ret_status
send_scan_packet_88xx(struct halmac_adapter *adapter, u8 index,
u8 *pkt, u32 size)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
enum halmac_cmd_process_status *proc_status =
&adapter->halmac_state.scan_pkt_state.proc_status;
if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_NO_DLFW;
if (adapter->fw_ver.h2c_version < 13)
return HALMAC_RET_FW_NO_SUPPORT;
if (size > UPDATE_PKT_RSVDPG_SIZE)
return HALMAC_RET_RSVD_PG_OVERFLOW_FAIL;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
PLTFM_MSG_TRACE("[TRACE]Wait event(send_scan)\n");
return HALMAC_RET_BUSY_STATE;
}
*proc_status = HALMAC_CMD_PROCESS_SENDING;
status = send_h2c_send_scan_packet_88xx(adapter, index, pkt, size);
if (status != HALMAC_RET_SUCCESS)
return status;
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
send_h2c_send_scan_packet_88xx(struct halmac_adapter *adapter,
u8 index, u8 *pkt, u32 size)
{
u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
u16 seq_num = 0;
u16 pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
u16 pg_offset;
struct halmac_h2c_header_info hdr_info;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
status = dl_rsvd_page_88xx(adapter, pg_addr, pkt, size);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n");
return status;
}
pg_offset = pg_addr - adapter->txff_alloc.rsvd_boundary;
SEND_SCAN_PKT_SET_SIZE(h2c_buf, size +
adapter->hw_cfg_info.txdesc_size);
SEND_SCAN_PKT_SET_INDEX(h2c_buf, index);
SEND_SCAN_PKT_SET_LOC(h2c_buf, pg_offset);
hdr_info.sub_cmd_id = SUB_CMD_ID_SEND_SCAN_PKT;
hdr_info.content_size = 8;
hdr_info.ack = 1;
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
adapter->halmac_state.scan_pkt_state.seq_num = seq_num;
status = send_h2c_pkt_88xx(adapter, h2c_buf);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]send h2c!!\n");
reset_ofld_feature_88xx(adapter,
HALMAC_FEATURE_SEND_SCAN_PACKET);
return status;
}
return status;
}
enum halmac_ret_status
drop_scan_packet_88xx(struct halmac_adapter *adapter,
struct halmac_drop_pkt_option *option)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
enum halmac_cmd_process_status *proc_status =
&adapter->halmac_state.drop_pkt_state.proc_status;
if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_NO_DLFW;
if (adapter->fw_ver.h2c_version < 13)
return HALMAC_RET_FW_NO_SUPPORT;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
PLTFM_MSG_TRACE("[TRACE]Wait event(drop_scan)\n");
return HALMAC_RET_BUSY_STATE;
}
*proc_status = HALMAC_CMD_PROCESS_SENDING;
status = send_h2c_drop_scan_packet_88xx(adapter, option);
if (status != HALMAC_RET_SUCCESS)
return status;
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
send_h2c_drop_scan_packet_88xx(struct halmac_adapter *adapter,
struct halmac_drop_pkt_option *option)
{
u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
u16 seq_num = 0;
struct halmac_h2c_header_info hdr_info;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
PLTFM_MSG_TRACE("[TRACE]%s\n", __func__);
DROP_SCAN_PKT_SET_DROP_ALL(h2c_buf, option->drop_all);
DROP_SCAN_PKT_SET_DROP_SINGLE(h2c_buf, option->drop_single);
DROP_SCAN_PKT_SET_DROP_IDX(h2c_buf, option->drop_index);
hdr_info.sub_cmd_id = SUB_CMD_ID_DROP_SCAN_PKT;
hdr_info.content_size = 8;
hdr_info.ack = 1;
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
adapter->halmac_state.drop_pkt_state.seq_num = seq_num;
status = send_h2c_pkt_88xx(adapter, h2c_buf);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]send h2c!!\n");
reset_ofld_feature_88xx(adapter,
HALMAC_FEATURE_DROP_SCAN_PACKET);
return status;
}
return status;
}
enum halmac_ret_status
bcn_ie_filter_88xx(struct halmac_adapter *adapter,
struct halmac_bcn_ie_info *info)
@@ -1954,6 +2327,12 @@ ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
if (adapter->fw_ver.h2c_version < 4)
return HALMAC_RET_FW_NO_SUPPORT;
if (adapter->ch_sw_info.total_size +
(adapter->halmac_state.update_pkt_state.used_page <<
TX_PAGE_SIZE_SHIFT_88XX) >
(u32)adapter->txff_alloc.rsvd_pg_num << TX_PAGE_SIZE_SHIFT_88XX)
return HALMAC_RET_RSVD_PG_OVERFLOW_FAIL;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (opt->switch_en == 0)
@@ -1997,6 +2376,7 @@ proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
u16 seq_num = 0;
u16 pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
struct halmac_h2c_header_info hdr_info;
struct halmac_scan_rpt_info *scan_rpt_info = &adapter->scan_rpt_info;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
enum halmac_cmd_process_status *proc_status;
@@ -2004,7 +2384,8 @@ proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (opt->nlo_en == 1 && adapter->nlo_flag != 1)
if (adapter->halmac_state.update_pkt_state.used_page > 0 &&
opt->nlo_en == 1 && adapter->nlo_flag != 1)
PLTFM_MSG_WARN("[WARN]probe req is NOT nlo pkt!!\n");
if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) !=
@@ -2014,6 +2395,7 @@ proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
*proc_status = HALMAC_CMD_PROCESS_SENDING;
if (opt->switch_en != 0) {
pg_addr += adapter->halmac_state.update_pkt_state.used_page;
status = dl_rsvd_page_88xx(adapter, pg_addr,
adapter->ch_sw_info.buf,
adapter->ch_sw_info.total_size);
@@ -2021,6 +2403,7 @@ proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n");
return status;
}
adapter->halmac_state.update_pkt_state.used_page = 0;
}
CH_SWITCH_SET_START(h2c_buf, opt->switch_en);
@@ -2038,6 +2421,7 @@ proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
CH_SWITCH_SET_SLOW_PERIOD(h2c_buf, opt->phase_2_period);
CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_buf, opt->normal_period_sel);
CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_buf, opt->phase_2_period_sel);
CH_SWITCH_SET_SCAN_MODE(h2c_buf, opt->scan_mode_en);
CH_SWITCH_SET_INFO_SIZE(h2c_buf, adapter->ch_sw_info.total_size);
hdr_info.sub_cmd_id = SUB_CMD_ID_CH_SWITCH;
@@ -2046,6 +2430,36 @@ proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
hdr_info.ack = 0;
else
hdr_info.ack = 1;
if (opt->scan_mode_en == 1) {
adapter->ch_sw_info.scan_mode = 1;
if (!scan_rpt_info->buf) {
scan_rpt_info->buf =
(u8 *)PLTFM_MALLOC(SCAN_INFO_RSVDPG_SIZE);
if (!scan_rpt_info->buf)
return HALMAC_RET_NULL_POINTER;
} else {
PLTFM_MEMSET(scan_rpt_info->buf, 0,
SCAN_INFO_RSVDPG_SIZE);
}
scan_rpt_info->buf_wptr = scan_rpt_info->buf;
scan_rpt_info->buf_size = SCAN_INFO_RSVDPG_SIZE;
scan_rpt_info->avl_buf_size = SCAN_INFO_RSVDPG_SIZE;
scan_rpt_info->total_size = 0;
scan_rpt_info->ack_tsf_high = 0;
scan_rpt_info->ack_tsf_low = 0;
scan_rpt_info->rpt_tsf_high = 0;
scan_rpt_info->rpt_tsf_low = 0;
} else {
adapter->ch_sw_info.scan_mode = 0;
if (!scan_rpt_info->buf)
PLTFM_FREE(scan_rpt_info->buf, scan_rpt_info->buf_size);
scan_rpt_info->buf_wptr = NULL;
scan_rpt_info->buf_size = 0;
scan_rpt_info->avl_buf_size = 0;
scan_rpt_info->total_size = 0;
}
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
adapter->halmac_state.scan_state.seq_num = seq_num;
@@ -2121,6 +2535,7 @@ enum halmac_ret_status
chk_txdesc_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
{
u32 mac_clk = 0;
u8 value8;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
@@ -2146,6 +2561,14 @@ chk_txdesc_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
status = HALMAC_RET_TXDESC_SET_FAIL;
}
if (GET_TX_DESC_USE_MAX_TIME_EN(buf) == 1) {
value8 = (u8)GET_TX_DESC_AMPDU_MAX_TIME(buf);
if (value8 > HALMAC_REG_R8(REG_AMPDU_MAX_TIME_V1)) {
PLTFM_MSG_ERR("[ERR]txdesc - ampdu_max_time\n");
status = HALMAC_RET_TXDESC_SET_FAIL;
}
}
switch (BIT_GET_MAC_CLK_SEL(HALMAC_REG_R32(REG_AFE_CTRL1))) {
case 0x0:
mac_clk = 80;
@@ -2401,12 +2824,23 @@ query_status_88xx(struct halmac_adapter *adapter,
status = get_dump_log_efuse_status_88xx(adapter, proc_status,
data, size);
break;
case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE_MASK:
status = get_dump_log_efuse_mask_status_88xx(adapter,
proc_status,
data, size);
break;
case HALMAC_FEATURE_CHANNEL_SWITCH:
status = get_ch_switch_status_88xx(adapter, proc_status);
break;
case HALMAC_FEATURE_UPDATE_PACKET:
status = get_update_packet_status_88xx(adapter, proc_status);
break;
case HALMAC_FEATURE_SEND_SCAN_PACKET:
status = get_send_scan_packet_status_88xx(adapter, proc_status);
break;
case HALMAC_FEATURE_DROP_SCAN_PACKET:
status = get_drop_scan_packet_status_88xx(adapter, proc_status);
break;
case HALMAC_FEATURE_IQK:
status = get_iqk_status_88xx(adapter, proc_status);
break;
@@ -2453,6 +2887,24 @@ get_update_packet_status_88xx(struct halmac_adapter *adapter,
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
get_send_scan_packet_status_88xx(struct halmac_adapter *adapter,
enum halmac_cmd_process_status *proc_status)
{
*proc_status = adapter->halmac_state.scan_pkt_state.proc_status;
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
get_drop_scan_packet_status_88xx(struct halmac_adapter *adapter,
enum halmac_cmd_process_status *proc_status)
{
*proc_status = adapter->halmac_state.drop_pkt_state.proc_status;
return HALMAC_RET_SUCCESS;
}
/**
* cfg_drv_rsvd_pg_num_88xx() -config reserved page number for driver
* @adapter : the adapter of halmac
@@ -2963,4 +3415,19 @@ get_real_pkt_id_88xx(struct halmac_adapter *adapter,
return real_pkt_id;
}
static u32
get_update_packet_page_size(struct halmac_adapter *adapter, u32 size)
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
u32 txdesc_size;
u32 total;
api->halmac_get_hw_value(adapter, HALMAC_HW_TX_DESC_SIZE, &txdesc_size);
total = size + txdesc_size;
return (total & 0x7f) > 0 ?
(total >> TX_PAGE_SIZE_SHIFT_88XX) + 1 :
total >> TX_PAGE_SIZE_SHIFT_88XX;
}
#endif /* HALMAC_88XX_SUPPORT */

14
hal/halmac/halmac_88xx/halmac_common_88xx.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -42,6 +42,10 @@ enum halmac_ret_status
set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
void *value);
enum halmac_ret_status
get_watcher_88xx(struct halmac_adapter *adapter, enum halmac_watcher_sel sel,
void *value);
enum halmac_ret_status
set_h2c_pkt_hdr_88xx(struct halmac_adapter *adapter, u8 *hdr,
struct halmac_h2c_header_info *info, u16 *seq_num);
@@ -66,6 +70,14 @@ enum halmac_ret_status
update_packet_88xx(struct halmac_adapter *adapter, enum halmac_packet_id pkt_id,
u8 *pkt, u32 size);
enum halmac_ret_status
send_scan_packet_88xx(struct halmac_adapter *adapter, u8 index,
u8 *pkt, u32 size);
enum halmac_ret_status
drop_scan_packet_88xx(struct halmac_adapter *adapter,
struct halmac_drop_pkt_option *option);
enum halmac_ret_status
bcn_ie_filter_88xx(struct halmac_adapter *adapter,
struct halmac_bcn_ie_info *info);

350
hal/halmac/halmac_88xx/halmac_efuse_88xx.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -24,6 +24,7 @@
#define RSVD_CS_EFUSE_SIZE 24
#define FEATURE_DUMP_PHY_EFUSE HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE
#define FEATURE_DUMP_LOG_EFUSE HALMAC_FEATURE_DUMP_LOGICAL_EFUSE
#define FEATURE_DUMP_LOG_EFUSE_MASK HALMAC_FEATURE_DUMP_LOGICAL_EFUSE_MASK
static enum halmac_cmd_construct_state
efuse_cmd_cnstr_state_88xx(struct halmac_adapter *adapter);
@@ -533,6 +534,84 @@ dump_log_efuse_map_88xx(struct halmac_adapter *adapter,
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status
dump_log_efuse_mask_88xx(struct halmac_adapter *adapter,
enum halmac_efuse_read_cfg cfg)
{
u8 *map = NULL;
u32 size = adapter->hw_cfg_info.eeprom_size;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
enum halmac_cmd_process_status *proc_status;
proc_status = &adapter->halmac_state.efuse_state.proc_status;
if (cfg == HALMAC_EFUSE_R_FW &&
halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_NO_DLFW;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
PLTFM_MSG_TRACE("[TRACE]cfg = %d\n", cfg);
if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
return HALMAC_RET_BUSY_STATE;
}
if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
return HALMAC_RET_ERROR_STATE;
}
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF)
PLTFM_MSG_ERR("[ERR]Dump efuse in suspend\n");
*proc_status = HALMAC_CMD_PROCESS_IDLE;
adapter->evnt.log_efuse_mask = 1;
status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
return status;
}
status = proc_dump_efuse_88xx(adapter, cfg);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]dump efuse\n");
return status;
}
if (adapter->efuse_map_valid == 1) {
*proc_status = HALMAC_CMD_PROCESS_DONE;
map = (u8 *)PLTFM_MALLOC(size);
if (!map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return HALMAC_RET_MALLOC_FAIL;
}
PLTFM_MEMSET(map, 0xFF, size);
if (eeprom_mask_parser_88xx(adapter, adapter->efuse_map, map) !=
HALMAC_RET_SUCCESS) {
PLTFM_FREE(map, size);
return HALMAC_RET_EEPROM_PARSING_FAIL;
}
PLTFM_EVENT_SIG(HALMAC_FEATURE_DUMP_LOGICAL_EFUSE_MASK,
*proc_status, map, size);
adapter->evnt.log_efuse_mask = 0;
PLTFM_FREE(map, size);
}
if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
HALMAC_RET_SUCCESS)
return HALMAC_RET_ERROR_STATE;
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* read_logical_efuse_88xx() - read logical efuse map 1 byte
* @adapter : the adapter of halmac
@@ -1075,6 +1154,92 @@ eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map)
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status
eeprom_mask_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map,
u8 *log_mask)
{
u8 i;
u8 value8;
u8 blk_idx;
u8 word_en;
u8 valid;
u8 hdr;
u8 hdr2 = 0;
u32 eeprom_idx;
u32 efuse_idx = 0;
u32 prtct_efuse_size = adapter->hw_cfg_info.prtct_efuse_size;
struct halmac_hw_cfg_info *hw_info = &adapter->hw_cfg_info;
PLTFM_MEMSET(log_mask, 0xFF, hw_info->eeprom_size);
do {
value8 = *(phy_map + efuse_idx);
hdr = value8;
if ((hdr & 0x1f) == 0x0f) {
efuse_idx++;
value8 = *(phy_map + efuse_idx);
hdr2 = value8;
if (hdr2 == 0xff)
break;
blk_idx = ((hdr2 & 0xF0) >> 1) | ((hdr >> 5) & 0x07);
word_en = hdr2 & 0x0F;
} else {
blk_idx = (hdr & 0xF0) >> 4;
word_en = hdr & 0x0F;
}
if (hdr == 0xff)
break;
efuse_idx++;
if (efuse_idx >= hw_info->efuse_size - prtct_efuse_size - 1)
return HALMAC_RET_EEPROM_PARSING_FAIL;
for (i = 0; i < 4; i++) {
valid = (u8)((~(word_en >> i)) & BIT(0));
if (valid == 1) {
eeprom_idx = (blk_idx << 3) + (i << 1);
if ((eeprom_idx + 1) > hw_info->eeprom_size) {
PLTFM_MSG_ERR("[ERR]efuse idx:0x%X\n",
efuse_idx - 1);
PLTFM_MSG_ERR("[ERR]read hdr:0x%X\n",
hdr);
PLTFM_MSG_ERR("[ERR]read hdr2:0x%X\n",
hdr2);
return HALMAC_RET_EEPROM_PARSING_FAIL;
}
*(log_mask + eeprom_idx) = 0x00;
eeprom_idx++;
efuse_idx++;
if (efuse_idx > hw_info->efuse_size -
prtct_efuse_size - 1)
return HALMAC_RET_EEPROM_PARSING_FAIL;
*(log_mask + eeprom_idx) = 0x00;
efuse_idx++;
if (efuse_idx > hw_info->efuse_size -
prtct_efuse_size)
return HALMAC_RET_EEPROM_PARSING_FAIL;
}
}
} while (1);
adapter->efuse_end = efuse_idx;
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
read_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map)
{
@@ -1755,6 +1920,19 @@ get_efuse_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
map, eeprom_size);
adapter->evnt.log_efuse_map = 0;
}
if (adapter->evnt.log_efuse_mask == 1) {
if (eeprom_mask_parser_88xx(adapter, adapter->efuse_map,
map)
!= HALMAC_RET_SUCCESS) {
PLTFM_FREE(map, eeprom_size);
return HALMAC_RET_EEPROM_PARSING_FAIL;
}
PLTFM_EVENT_SIG(FEATURE_DUMP_LOG_EFUSE_MASK,
proc_status, map, eeprom_size);
adapter->evnt.log_efuse_mask = 0;
}
} else {
proc_status = HALMAC_CMD_PROCESS_ERROR;
state->proc_status = proc_status;
@@ -1770,6 +1948,12 @@ get_efuse_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
&state->fw_rc, 1);
adapter->evnt.log_efuse_map = 0;
}
if (adapter->evnt.log_efuse_mask == 1) {
PLTFM_EVENT_SIG(FEATURE_DUMP_LOG_EFUSE_MASK,
proc_status, &state->fw_rc, 1);
adapter->evnt.log_efuse_mask = 0;
}
}
PLTFM_FREE(map, eeprom_size);
@@ -1810,6 +1994,9 @@ get_dump_phy_efuse_status_88xx(struct halmac_adapter *adapter,
}
PLTFM_MEMSET(map, 0xFF, efuse_size);
PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
#if HALMAC_PLATFORM_WINDOWS
PLTFM_MEMCPY(map, adapter->efuse_map, efuse_size);
#else
PLTFM_MEMCPY(map, adapter->efuse_map,
efuse_size - prtct_efuse_size);
PLTFM_MEMCPY(map + efuse_size - prtct_efuse_size +
@@ -1818,6 +2005,7 @@ get_dump_phy_efuse_status_88xx(struct halmac_adapter *adapter,
prtct_efuse_size + RSVD_CS_EFUSE_SIZE,
prtct_efuse_size - RSVD_EFUSE_SIZE -
RSVD_CS_EFUSE_SIZE);
#endif
PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
PLTFM_MEMCPY(data, map, *size);
@@ -1874,6 +2062,52 @@ get_dump_log_efuse_status_88xx(struct halmac_adapter *adapter,
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status
get_dump_log_efuse_mask_status_88xx(struct halmac_adapter *adapter,
enum halmac_cmd_process_status *proc_status,
u8 *data, u32 *size)
{
u8 *map = NULL;
u32 eeprom_size = adapter->hw_cfg_info.eeprom_size;
struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;
*proc_status = state->proc_status;
if (!data)
return HALMAC_RET_NULL_POINTER;
if (!size)
return HALMAC_RET_NULL_POINTER;
if (*proc_status == HALMAC_CMD_PROCESS_DONE) {
if (*size < eeprom_size) {
*size = eeprom_size;
return HALMAC_RET_BUFFER_TOO_SMALL;
}
*size = eeprom_size;
map = (u8 *)PLTFM_MALLOC(eeprom_size);
if (!map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return HALMAC_RET_MALLOC_FAIL;
}
PLTFM_MEMSET(map, 0xFF, eeprom_size);
if (eeprom_mask_parser_88xx(adapter, adapter->efuse_map, map) !=
HALMAC_RET_SUCCESS) {
PLTFM_FREE(map, eeprom_size);
return HALMAC_RET_EEPROM_PARSING_FAIL;
}
PLTFM_MEMCPY(data, map, *size);
PLTFM_FREE(map, eeprom_size);
}
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status
get_h2c_ack_phy_efuse_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
{
@@ -1907,4 +2141,118 @@ get_rsvd_efuse_size_88xx(struct halmac_adapter *adapter)
return adapter->hw_cfg_info.prtct_efuse_size;
}
/**
* write_wifi_phy_efuse_88xx() - write wifi physical efuse
* @adapter : the adapter of halmac
* @offset : the efuse offset to be written
* @value : the value to be written
* Author : Yong-Ching Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
write_wifi_phy_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
enum halmac_cmd_process_status *proc_status;
proc_status = &adapter->halmac_state.efuse_state.proc_status;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (offset >= adapter->hw_cfg_info.efuse_size) {
PLTFM_MSG_ERR("[ERR]Offset is too large\n");
return HALMAC_RET_EFUSE_SIZE_INCORRECT;
}
if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
return HALMAC_RET_BUSY_STATE;
}
if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
return HALMAC_RET_ERROR_STATE;
}
status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
return status;
}
status = write_hw_efuse_88xx(adapter, offset, value);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]write physical efuse\n");
return status;
}
if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
HALMAC_RET_SUCCESS)
return HALMAC_RET_ERROR_STATE;
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* read_wifi_phy_efuse_88xx() - read wifi physical efuse
* @adapter : the adapter of halmac
* @offset : the efuse offset to be read
* @size : the length to be read
* @value : pointer to the pre-allocated space where
the efuse content is to be copied
* Author : Yong-Ching Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
read_wifi_phy_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
u8 *value)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
enum halmac_cmd_process_status *proc_status;
proc_status = &adapter->halmac_state.efuse_state.proc_status;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (offset >= adapter->hw_cfg_info.efuse_size ||
offset + size >= adapter->hw_cfg_info.efuse_size) {
PLTFM_MSG_ERR("[ERR] Wrong efuse index\n");
return HALMAC_RET_EFUSE_SIZE_INCORRECT;
}
if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
return HALMAC_RET_BUSY_STATE;
}
if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
return HALMAC_RET_ERROR_STATE;
}
status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
return status;
}
status = read_hw_efuse_88xx(adapter, offset, size, value);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]read hw efuse\n");
return status;
}
if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
HALMAC_RET_SUCCESS)
return HALMAC_RET_ERROR_STATE;
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
#endif /* HALMAC_88XX_SUPPORT */

21
hal/halmac/halmac_88xx/halmac_efuse_88xx.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -27,6 +27,10 @@ dump_efuse_map_88xx(struct halmac_adapter *adapter,
enum halmac_ret_status
eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map);
enum halmac_ret_status
eeprom_mask_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map,
u8 *log_mask);
enum halmac_ret_status
dump_efuse_map_bt_88xx(struct halmac_adapter *adapter,
enum halmac_efuse_bank bank, u32 size, u8 *map);
@@ -54,6 +58,9 @@ get_log_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size);
enum halmac_ret_status
dump_log_efuse_map_88xx(struct halmac_adapter *adapter,
enum halmac_efuse_read_cfg cfg);
enum halmac_ret_status
dump_log_efuse_mask_88xx(struct halmac_adapter *adapter,
enum halmac_efuse_read_cfg cfg);
enum halmac_ret_status
read_logical_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value);
@@ -97,12 +104,24 @@ get_dump_log_efuse_status_88xx(struct halmac_adapter *adapter,
enum halmac_cmd_process_status *proc_status,
u8 *data, u32 *size);
enum halmac_ret_status
get_dump_log_efuse_mask_status_88xx(struct halmac_adapter *adapter,
enum halmac_cmd_process_status *proc_status,
u8 *data, u32 *size);
enum halmac_ret_status
get_h2c_ack_phy_efuse_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
u32
get_rsvd_efuse_size_88xx(struct halmac_adapter *adapter);
enum halmac_ret_status
write_wifi_phy_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
enum halmac_ret_status
read_wifi_phy_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
u8 *value);
#endif /* HALMAC_88XX_SUPPORT */
#endif/* _HALMAC_EFUSE_88XX_H_ */

51
hal/halmac/halmac_88xx/halmac_flash_88xx.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2017 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -43,6 +43,7 @@ download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
u16 h2c_info_offset;
u32 pkt_size;
u32 mem_offset;
u32 cnt;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
@@ -105,12 +106,14 @@ download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
mem_offset += pkt_size;
size -= pkt_size;
while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0)
cnt = 1000;
while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0) {
if (cnt == 0) {
PLTFM_MSG_ERR("[ERR]dl flash!!\n");
return HALMAC_RET_DLFW_FAIL;
}
cnt--;
PLTFM_DELAY_US(1000);
if (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0) {
PLTFM_MSG_ERR("[ERR]dl flash!!\n");
return HALMAC_RET_DLFW_FAIL;
}
}
@@ -131,7 +134,7 @@ download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
read_flash_88xx(struct halmac_adapter *adapter, u32 addr, u32 length)
read_flash_88xx(struct halmac_adapter *adapter, u32 addr, u32 length, u8 *data)
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
enum halmac_ret_status status;
@@ -140,8 +143,10 @@ read_flash_88xx(struct halmac_adapter *adapter, u32 addr, u32 length)
u8 restore[3];
u8 h2c_buf[H2C_PKT_SIZE_88XX] = {0};
u16 seq_num = 0;
u16 h2c_info_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
u16 h2c_pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
u16 rsvd_pg_addr = adapter->txff_alloc.rsvd_boundary;
u16 h2c_info_addr;
u32 cnt;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
@@ -160,14 +165,14 @@ read_flash_88xx(struct halmac_adapter *adapter, u32 addr, u32 length)
value8 = (u8)(value8 & ~(BIT(6)));
HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8);
HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, h2c_info_addr);
HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, h2c_pg_addr);
value8 = HALMAC_REG_R8(REG_MCUTST_I);
value8 |= BIT(0);
HALMAC_REG_W8(REG_MCUTST_I, value8);
/* Construct H2C Content */
DOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, 0x03);
DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, h2c_info_addr - rsvd_pg_addr);
DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, h2c_pg_addr - rsvd_pg_addr);
DOWNLOAD_FLASH_SET_SIZE(h2c_buf, length);
DOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, addr);
@@ -185,14 +190,30 @@ read_flash_88xx(struct halmac_adapter *adapter, u32 addr, u32 length)
return status;
}
while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0)
cnt = 5000;
while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0) {
if (cnt == 0) {
PLTFM_MSG_ERR("[ERR]read flash!!\n");
return HALMAC_RET_FAIL;
}
cnt--;
PLTFM_DELAY_US(1000);
}
HALMAC_REG_W8_CLR(REG_MCUTST_I, BIT(0));
HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, rsvd_pg_addr);
HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, restore[2]);
HALMAC_REG_W8(REG_BCN_CTRL, restore[1]);
HALMAC_REG_W8(REG_CR + 1, restore[0]);
h2c_info_addr = h2c_pg_addr << TX_PAGE_SIZE_SHIFT_88XX;
status = dump_fifo_88xx(adapter, HAL_FIFO_SEL_TX, h2c_info_addr,
length, data);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]dump fifo!!\n");
return status;
}
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
@@ -274,9 +295,12 @@ check_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
u32 pkt_size;
u32 start_page;
u32 cnt;
u8 *data;
pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
data = (u8 *)PLTFM_MALLOC(4096);
while (size != 0) {
start_page = ((pg_addr << 7) >> 12) + 0x780;
residue = (pg_addr << 7) & (4096 - 1);
@@ -286,7 +310,7 @@ check_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
else
pkt_size = size;
read_flash_88xx(adapter, addr, 4096);
read_flash_88xx(adapter, addr, 4096, data);
cnt = 0;
while (cnt < pkt_size) {
@@ -295,6 +319,7 @@ check_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
value8 = HALMAC_REG_R8(i);
if (*fw_bin != value8) {
PLTFM_MSG_ERR("[ERR]check flash!!\n");
PLTFM_FREE(data, 4096);
return HALMAC_RET_FAIL;
}
@@ -310,6 +335,8 @@ check_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
size -= pkt_size;
}
PLTFM_FREE(data, 4096);
return HALMAC_RET_SUCCESS;
}

4
hal/halmac/halmac_88xx/halmac_flash_88xx.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2017 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -25,7 +25,7 @@ download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
u32 rom_addr);
enum halmac_ret_status
read_flash_88xx(struct halmac_adapter *adapter, u32 addr, u32 length);
read_flash_88xx(struct halmac_adapter *adapter, u32 addr, u32 length, u8 *data);
enum halmac_ret_status
erase_flash_88xx(struct halmac_adapter *adapter, u8 erase_cmd, u32 addr);

50
hal/halmac/halmac_88xx/halmac_fw_88xx.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -475,13 +475,24 @@ DL_FREE_FW_END:
enum halmac_ret_status
reset_wifi_fw_88xx(struct halmac_adapter *adapter)
{
enum halmac_ret_status status;
u32 lte_coex_backup = 0;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
status = ltecoex_reg_read_88xx(adapter, 0x38, &lte_coex_backup);
if (status != HALMAC_RET_SUCCESS)
return status;
wlan_cpu_en_88xx(adapter, 0);
pltfm_reset_88xx(adapter);
init_ofld_feature_state_machine_88xx(adapter);
wlan_cpu_en_88xx(adapter, 1);
status = ltecoex_reg_write_88xx(adapter, 0x38, lte_coex_backup);
if (status != HALMAC_RET_SUCCESS)
return status;
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
@@ -1015,6 +1026,7 @@ get_cpu_mode_88xx(struct halmac_adapter *adapter,
if (HALMAC_REG_R8(REG_MCU_TST_CFG) == ID_CHECK_ENETR_CPU_SLEEP) {
*mode = HALMAC_WLCPU_SLEEP;
*cur_mode = HALMAC_WLCPU_SLEEP;
HALMAC_REG_W8(REG_MCU_TST_CFG, 0);
} else {
*mode = HALMAC_WLCPU_ENTER_SLEEP;
@@ -1038,6 +1050,7 @@ send_general_info_88xx(struct halmac_adapter *adapter,
u8 h2cq_ele[4] = {0};
u32 h2cq_addr;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
u8 cnt;
if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_NO_DLFW;
@@ -1045,6 +1058,9 @@ send_general_info_88xx(struct halmac_adapter *adapter,
if (adapter->fw_ver.h2c_version < 4)
return HALMAC_RET_FW_NO_SUPPORT;
if (adapter->fw_ver.h2c_version < 14)
PLTFM_MSG_WARN("[WARN]the H2C ver. does not match halmac\n");
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE) {
@@ -1066,17 +1082,26 @@ send_general_info_88xx(struct halmac_adapter *adapter,
h2cq_addr = adapter->txff_alloc.rsvd_h2cq_addr;
h2cq_addr <<= TX_PAGE_SIZE_SHIFT_88XX;
status = dump_fifo_88xx(adapter, HAL_FIFO_SEL_TX,
h2cq_addr, 4, h2cq_ele);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]dump h2cq!!\n");
return status;
}
if ((h2cq_ele[0] & 0x7F) != 0x01 || h2cq_ele[1] != 0xFF) {
PLTFM_MSG_ERR("[ERR]h2cq compare!!\n");
return HALMAC_RET_SEND_H2C_FAIL;
}
cnt = 100;
do {
status = dump_fifo_88xx(adapter, HAL_FIFO_SEL_TX,
h2cq_addr, 4, h2cq_ele);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]dump h2cq!!\n");
return status;
}
if ((h2cq_ele[0] & 0x7F) == 0x01 && h2cq_ele[1] == 0xFF)
break;
cnt--;
if (cnt == 0) {
PLTFM_MSG_ERR("[ERR]h2cq compare!!\n");
return HALMAC_RET_SEND_H2C_FAIL;
}
PLTFM_DELAY_US(5);
} while (1);
if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_DONE)
adapter->halmac_state.dlfw_state = HALMAC_GEN_INFO_SENT;
@@ -1130,6 +1155,9 @@ proc_send_phydm_info_88xx(struct halmac_adapter *adapter,
PHYDM_INFO_SET_CUT_VER(h2c_buf, adapter->chip_ver);
PHYDM_INFO_SET_RX_ANT_STATUS(h2c_buf, info->rx_ant_status);
PHYDM_INFO_SET_TX_ANT_STATUS(h2c_buf, info->tx_ant_status);
PHYDM_INFO_SET_EXT_PA(h2c_buf, info->ext_pa);
PHYDM_INFO_SET_PACKAGE_TYPE(h2c_buf, info->package_type);
PHYDM_INFO_SET_MP_MODE(h2c_buf, info->mp_mode);
hdr_info.sub_cmd_id = SUB_CMD_ID_PHYDM_INFO;
hdr_info.content_size = 8;

2
hal/halmac/halmac_88xx/halmac_fw_88xx.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

170
hal/halmac/halmac_88xx/halmac_gpio_88xx.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -249,173 +249,5 @@ pinmux_parser_88xx(struct halmac_adapter *adapter,
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status
pinmux_switch_88xx(struct halmac_adapter *adapter,
const struct halmac_gpio_pimux_list *list, u32 size,
u32 gpio_id, enum halmac_gpio_func gpio_func)
{
u32 i;
u8 value8;
u16 switch_func;
const struct halmac_gpio_pimux_list *cur_list = list;
enum halmac_gpio_cfg_state *state;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
state = &adapter->halmac_state.gpio_cfg_state;
if (*state == HALMAC_GPIO_CFG_STATE_BUSY)
return HALMAC_RET_BUSY_STATE;
switch (gpio_func) {
case HALMAC_GPIO_FUNC_WL_LED:
switch_func = HALMAC_WL_LED;
break;
case HALMAC_GPIO_FUNC_SDIO_INT:
switch_func = HALMAC_SDIO_INT;
break;
case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
switch_func = HALMAC_GPIO13_14_WL_CTRL_EN;
break;
case HALMAC_GPIO_FUNC_SW_IO_0:
case HALMAC_GPIO_FUNC_SW_IO_1:
case HALMAC_GPIO_FUNC_SW_IO_2:
case HALMAC_GPIO_FUNC_SW_IO_3:
case HALMAC_GPIO_FUNC_SW_IO_4:
case HALMAC_GPIO_FUNC_SW_IO_5:
case HALMAC_GPIO_FUNC_SW_IO_6:
case HALMAC_GPIO_FUNC_SW_IO_7:
case HALMAC_GPIO_FUNC_SW_IO_8:
case HALMAC_GPIO_FUNC_SW_IO_9:
case HALMAC_GPIO_FUNC_SW_IO_10:
case HALMAC_GPIO_FUNC_SW_IO_11:
case HALMAC_GPIO_FUNC_SW_IO_12:
case HALMAC_GPIO_FUNC_SW_IO_13:
case HALMAC_GPIO_FUNC_SW_IO_14:
case HALMAC_GPIO_FUNC_SW_IO_15:
switch_func = HALMAC_SW_IO;
break;
default:
return HALMAC_RET_SWITCH_CASE_ERROR;
}
for (i = 0; i < size; i++) {
if (gpio_id != cur_list->id) {
PLTFM_MSG_ERR("[ERR]offset:%X, value:%X, func:%X\n",
cur_list->offset, cur_list->value,
cur_list->func);
PLTFM_MSG_ERR("[ERR]id1 : %X, id2 : %X\n",
gpio_id, cur_list->id);
return HALMAC_RET_GET_PINMUX_ERR;
}
if (switch_func == cur_list->func)
break;
cur_list++;
}
if (i == size) {
PLTFM_MSG_ERR("[ERR]gpio func error:%X %X\n",
gpio_id, cur_list->id);
return HALMAC_RET_GET_PINMUX_ERR;
}
*state = HALMAC_GPIO_CFG_STATE_BUSY;
cur_list = list;
for (i = 0; i < size; i++) {
value8 = HALMAC_REG_R8(cur_list->offset);
value8 &= ~(cur_list->msk);
if (switch_func == cur_list->func) {
value8 |= (cur_list->value & cur_list->msk);
HALMAC_REG_W8(cur_list->offset, value8);
break;
}
value8 |= (~cur_list->value & cur_list->msk);
HALMAC_REG_W8(cur_list->offset, value8);
cur_list++;
}
*state = HALMAC_GPIO_CFG_STATE_IDLE;
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status
pinmux_record_88xx(struct halmac_adapter *adapter,
enum halmac_gpio_func gpio_func, u8 val)
{
switch (gpio_func) {
case HALMAC_GPIO_FUNC_WL_LED:
adapter->pinmux_info.wl_led = val;
break;
case HALMAC_GPIO_FUNC_SDIO_INT:
adapter->pinmux_info.sdio_int = val;
break;
case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
adapter->pinmux_info.bt_host_wake = val;
break;
case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
adapter->pinmux_info.bt_dev_wake = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_0:
adapter->pinmux_info.sw_io_0 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_1:
adapter->pinmux_info.sw_io_1 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_2:
adapter->pinmux_info.sw_io_2 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_3:
adapter->pinmux_info.sw_io_3 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_4:
adapter->pinmux_info.sw_io_4 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_5:
adapter->pinmux_info.sw_io_5 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_6:
adapter->pinmux_info.sw_io_6 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_7:
adapter->pinmux_info.sw_io_7 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_8:
adapter->pinmux_info.sw_io_8 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_9:
adapter->pinmux_info.sw_io_9 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_10:
adapter->pinmux_info.sw_io_10 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_11:
adapter->pinmux_info.sw_io_11 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_12:
adapter->pinmux_info.sw_io_12 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_13:
adapter->pinmux_info.sw_io_13 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_14:
adapter->pinmux_info.sw_io_14 = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_15:
adapter->pinmux_info.sw_io_15 = val;
break;
default:
return HALMAC_RET_GET_PINMUX_ERR;
}
return HALMAC_RET_SUCCESS;
}
#endif /* HALMAC_88XX_SUPPORT */

11
hal/halmac/halmac_88xx/halmac_gpio_88xx.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -45,15 +45,6 @@ pinmux_parser_88xx(struct halmac_adapter *adapter,
const struct halmac_gpio_pimux_list *list, u32 size,
u32 gpio_id, u32 *cur_func);
enum halmac_ret_status
pinmux_switch_88xx(struct halmac_adapter *adapter,
const struct halmac_gpio_pimux_list *list, u32 size,
u32 gpio_id, enum halmac_gpio_func gpio_func);
enum halmac_ret_status
pinmux_record_88xx(struct halmac_adapter *adapter,
enum halmac_gpio_func gpio_func, u8 val);
#endif /* HALMAC_88XX_SUPPORT */
#endif/* _HALMAC_GPIO_88XX_H_ */

48
hal/halmac/halmac_88xx/halmac_init_88xx.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -132,13 +132,16 @@ init_adapter_param_88xx(struct halmac_adapter *adapter)
adapter->sdio_cmd53_4byte = HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE;
adapter->sdio_hw_info.io_hi_speed_flag = 0;
adapter->sdio_hw_info.io_indir_flag = 0;
adapter->sdio_hw_info.io_indir_flag = 1;
adapter->sdio_hw_info.io_warn_flag = 0;
adapter->sdio_hw_info.spec_ver = HALMAC_SDIO_SPEC_VER_2_00;
adapter->sdio_hw_info.clock_speed = 50;
adapter->sdio_hw_info.block_size = 512;
adapter->sdio_hw_info.tx_seq = 1;
adapter->sdio_fs.macid_map = (u8 *)NULL;
adapter->watcher.get_watcher.sdio_rn_not_align = 0;
adapter->pinmux_info.wl_led = 0;
adapter->pinmux_info.sdio_int = 0;
adapter->pinmux_info.sw_io_0 = 0;
@@ -218,6 +221,7 @@ mount_api_88xx(struct halmac_adapter *adapter)
api->halmac_read_efuse_bt = read_efuse_bt_88xx;
api->halmac_cfg_efuse_auto_check = cfg_efuse_auto_check_88xx;
api->halmac_dump_logical_efuse_map = dump_log_efuse_map_88xx;
api->halmac_dump_logical_efuse_mask = dump_log_efuse_mask_88xx;
api->halmac_pg_efuse_by_map = pg_efuse_by_map_88xx;
api->halmac_mask_logical_efuse = mask_log_efuse_88xx;
api->halmac_get_efuse_size = get_efuse_size_88xx;
@@ -229,6 +233,9 @@ mount_api_88xx(struct halmac_adapter *adapter)
api->halmac_write_logical_efuse = write_log_efuse_88xx;
api->halmac_read_logical_efuse = read_logical_efuse_88xx;
api->halmac_write_wifi_phy_efuse = write_wifi_phy_efuse_88xx;
api->halmac_read_wifi_phy_efuse = read_wifi_phy_efuse_88xx;
api->halmac_ofld_func_cfg = ofld_func_cfg_88xx;
api->halmac_h2c_lb = h2c_lb_88xx;
api->halmac_debug = mac_debug_88xx;
@@ -258,6 +265,8 @@ mount_api_88xx(struct halmac_adapter *adapter)
api->halmac_p2pps = p2pps_88xx;
api->halmac_clear_ch_info = clear_ch_info_88xx;
api->halmac_send_general_info = send_general_info_88xx;
api->halmac_send_scan_packet = send_scan_packet_88xx;
api->halmac_drop_scan_packet = drop_scan_packet_88xx;
api->halmac_start_iqk = start_iqk_88xx;
api->halmac_ctrl_pwr_tracking = ctrl_pwr_tracking_88xx;
@@ -307,13 +316,12 @@ mount_api_88xx(struct halmac_adapter *adapter)
api->halmac_enter_cpu_sleep_mode = enter_cpu_sleep_mode_88xx;
api->halmac_get_cpu_mode = get_cpu_mode_88xx;
api->halmac_drv_fwctrl = drv_fwctrl_88xx;
api->halmac_get_watcher = get_watcher_88xx;
if (adapter->intf == HALMAC_INTERFACE_SDIO) {
#if HALMAC_SDIO_SUPPORT
api->halmac_init_sdio_cfg = init_sdio_cfg_88xx;
api->halmac_deinit_sdio_cfg = deinit_sdio_cfg_88xx;
api->halmac_cfg_rx_aggregation = cfg_sdio_rx_agg_88xx;
api->halmac_init_interface_cfg = init_sdio_cfg_88xx;
api->halmac_deinit_interface_cfg = deinit_sdio_cfg_88xx;
api->halmac_cfg_tx_agg_align = cfg_txagg_sdio_align_88xx;
api->halmac_set_bulkout_num = set_sdio_bulkout_num_88xx;
@@ -322,6 +330,7 @@ mount_api_88xx(struct halmac_adapter *adapter)
api->halmac_reg_sdio_cmd53_read_n = sdio_reg_rn_88xx;
api->halmac_sdio_cmd53_4byte = sdio_cmd53_4byte_88xx;
api->halmac_sdio_hw_info = sdio_hw_info_88xx;
api->halmac_en_ref_autok_pcie = en_ref_autok_sdio_88xx;
#endif
} else if (adapter->intf == HALMAC_INTERFACE_USB) {
@@ -344,6 +353,7 @@ mount_api_88xx(struct halmac_adapter *adapter)
api->halmac_reg_write_32 = reg_w32_usb_88xx;
api->halmac_reg_read_indirect_32 = usb_indirect_reg_r32_88xx;
api->halmac_reg_sdio_cmd53_read_n = usb_reg_rn_88xx;
api->halmac_en_ref_autok_pcie = en_ref_autok_usb_88xx;
#endif
} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
#if HALMAC_PCIE_SUPPORT
@@ -365,7 +375,7 @@ mount_api_88xx(struct halmac_adapter *adapter)
api->halmac_reg_write_32 = reg_w32_pcie_88xx;
api->halmac_reg_read_indirect_32 = pcie_indirect_reg_r32_88xx;
api->halmac_reg_sdio_cmd53_read_n = pcie_reg_rn_88xx;
api->halmac_en_ref_autok_pcie = en_ref_autok_88xx;
api->halmac_en_ref_autok_pcie = en_ref_autok_pcie_88xx;
#endif
} else {
PLTFM_MSG_ERR("[ERR]Set halmac io function Error!!\n");
@@ -548,6 +558,7 @@ reset_ofld_feature_88xx(struct halmac_adapter *adapter,
break;
case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE_MASK:
state->efuse_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
state->efuse_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
break;
@@ -558,6 +569,12 @@ reset_ofld_feature_88xx(struct halmac_adapter *adapter,
case HALMAC_FEATURE_UPDATE_PACKET:
state->update_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
break;
case HALMAC_FEATURE_SEND_SCAN_PACKET:
state->scan_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
break;
case HALMAC_FEATURE_DROP_SCAN_PACKET:
state->drop_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
break;
case HALMAC_FEATURE_IQK:
state->iqk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
break;
@@ -579,6 +596,8 @@ reset_ofld_feature_88xx(struct halmac_adapter *adapter,
state->scan_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
state->scan_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
state->update_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
state->scan_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
state->drop_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
state->iqk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
state->pwr_trk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
state->psd_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
@@ -867,4 +886,23 @@ rqpn_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode,
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status
fwff_is_empty_88xx(struct halmac_adapter *adapter)
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
u32 cnt;
cnt = 5000;
while (HALMAC_REG_R16(REG_FWFF_CTRL) !=
HALMAC_REG_R16(REG_FWFF_PKT_INFO)) {
if (cnt == 0) {
PLTFM_MSG_ERR("[ERR]polling fwff empty fail\n");
return HALMAC_RET_FWFF_NO_EMPTY;
}
cnt--;
PLTFM_DELAY_US(50);
}
return HALMAC_RET_SUCCESS;
}
#endif /* HALMAC_88XX_SUPPORT */

5
hal/halmac/halmac_88xx/halmac_init_88xx.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -57,6 +57,9 @@ rqpn_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode,
void
init_ofld_feature_state_machine_88xx(struct halmac_adapter *adapter);
enum halmac_ret_status
fwff_is_empty_88xx(struct halmac_adapter *adapter);
#endif /* HALMAC_88XX_SUPPORT */
#endif/* _HALMAC_INIT_88XX_H_ */

28
hal/halmac/halmac_88xx/halmac_mimo_88xx.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -22,7 +22,7 @@
#define TXBF_CTRL_CFG (BIT_R_ENABLE_NDPA | BIT_USE_NDPA_PARAMETER | \
BIT_R_EN_NDPA_INT | BIT_DIS_NDP_BFEN)
#define CSI_RATE_MAP 0x292911
#define CSI_RATE_MAP 0x55
static void
cfg_mu_bfee_88xx(struct halmac_adapter *adapter,
@@ -63,8 +63,10 @@ cfg_txbf_88xx(struct halmac_adapter *adapter, u8 userid, enum halmac_bw bw,
switch (bw) {
case HALMAC_BW_80:
tmp42c |= BIT_R_TXBF0_80M;
/* fall through */
case HALMAC_BW_40:
tmp42c |= BIT_R_TXBF0_40M;
/* fall through */
case HALMAC_BW_20:
tmp42c |= BIT_R_TXBF0_20M;
break;
@@ -234,7 +236,7 @@ cfg_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role,
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
u32 tmp6dc = 0;
u8 csi_rsc = 0x1;
u8 csi_rsc = 0x0;
/*use ndpa rx rate to decide csi rate*/
tmp6dc = HALMAC_REG_R32(REG_BBPSF_CTRL) | BIT_WMAC_USE_NDPARATE
@@ -244,13 +246,12 @@ cfg_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role,
case HAL_BFER:
HALMAC_REG_W32_SET(REG_TXBF_CTRL, TXBF_CTRL_CFG);
HALMAC_REG_W8(REG_NDPA_RATE, rate);
HALMAC_REG_W8_CLR(REG_NDPA_OPT_CTRL, BIT(0) | BIT(1));
HALMAC_REG_W8(REG_SND_PTCL_CTRL + 1, 0x2 | BIT(7));
HALMAC_REG_W8(REG_SND_PTCL_CTRL + 2, 0x2);
break;
case HAL_BFEE:
HALMAC_REG_W8(REG_SND_PTCL_CTRL, 0xDB);
HALMAC_REG_W8(REG_SND_PTCL_CTRL + 3, 0x26);
HALMAC_REG_W8(REG_SND_PTCL_CTRL + 3, 0x3A);
HALMAC_REG_W8_CLR(REG_RXFLTMAP1, BIT(4));
HALMAC_REG_W8_CLR(REG_RXFLTMAP4, BIT(4));
#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
@@ -619,14 +620,15 @@ mu_bfer_entry_del_88xx(struct halmac_adapter *adapter)
*/
enum halmac_ret_status
cfg_csi_rate_88xx(struct halmac_adapter *adapter, u8 rssi, u8 cur_rate,
u8 fixrate_en, u8 *new_rate)
u8 fixrate_en, u8 *new_rate, u8 *bmp_ofdm54)
{
u32 csi_cfg;
u16 cur_rrsr;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
*bmp_ofdm54 = 0xFF;
#if HALMAC_8821C_SUPPORT
if (adapter->chip_id == HALMAC_CHIP_ID_8821C && fixrate_en) {
csi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE;
@@ -643,22 +645,24 @@ cfg_csi_rate_88xx(struct halmac_adapter *adapter, u8 rssi, u8 cur_rate,
csi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE;
#endif
cur_rrsr = HALMAC_REG_R16(REG_RRSR);
#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
if (adapter->chip_id == HALMAC_CHIP_ID_8822C ||
adapter->chip_id == HALMAC_CHIP_ID_8812F)
HALMAC_REG_W32_SET(REG_BBPSF_CTRL, BIT(15));
#endif
if (rssi >= 40) {
if (cur_rate != HALMAC_OFDM54) {
cur_rrsr |= BIT(HALMAC_OFDM54);
csi_cfg |= BIT_WMAC_CSI_RATE(HALMAC_OFDM54);
HALMAC_REG_W16(REG_RRSR, cur_rrsr);
HALMAC_REG_W32(REG_BBPSF_CTRL, csi_cfg);
*bmp_ofdm54 = 1;
}
*new_rate = HALMAC_OFDM54;
} else {
if (cur_rate != HALMAC_OFDM24) {
cur_rrsr &= ~(BIT(HALMAC_OFDM54));
csi_cfg |= BIT_WMAC_CSI_RATE(HALMAC_OFDM24);
HALMAC_REG_W16(REG_RRSR, cur_rrsr);
HALMAC_REG_W32(REG_BBPSF_CTRL, csi_cfg);
*bmp_ofdm54 = 0;
}
*new_rate = HALMAC_OFDM24;
}

4
hal/halmac/halmac_88xx/halmac_mimo_88xx.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -64,7 +64,7 @@ mu_bfer_entry_del_88xx(struct halmac_adapter *adapter);
enum halmac_ret_status
cfg_csi_rate_88xx(struct halmac_adapter *adapter, u8 rssi, u8 cur_rate,
u8 fixrate_en, u8 *new_rate);
u8 fixrate_en, u8 *new_rate, u8 *bmp_ofdm54);
enum halmac_ret_status
fw_snding_88xx(struct halmac_adapter *adapter,

7
hal/halmac/halmac_88xx/halmac_usb_88xx.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -517,4 +517,9 @@ usbphy_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed)
return value;
}
enum halmac_ret_status
en_ref_autok_usb_88xx(struct halmac_adapter *adapter, u8 en)
{
return HALMAC_RET_NOT_SUPPORT;
}
#endif /* HALMAC_88XX_SUPPORT */

5
hal/halmac/halmac_88xx/halmac_usb_88xx.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -82,6 +82,9 @@ usbphy_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed);
u16
usbphy_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed);
enum halmac_ret_status
en_ref_autok_usb_88xx(struct halmac_adapter *adapter, u8 en);
#endif /* HALMAC_88XX_SUPPORT */
#endif/* _HALMAC_API_88XX_USB_H_ */

30
hal/halmac/halmac_api.c
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -34,6 +34,10 @@
#include "halmac_88xx/halmac_init_win8822c.h"
#endif
#if HALMAC_8812F_SUPPORT
#include "halmac_88xx/halmac_init_win8812f.h"
#endif
#else
#if HALMAC_88XX_SUPPORT
@@ -126,10 +130,10 @@ halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api,
pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS,
HALMAC_SVN_VER "\n"
"HALMAC_MAJOR_VER = %x\n"
"HALMAC_PROTOTYPE_VER = %x\n"
"HALMAC_MINOR_VER = %x\n"
"HALMAC_PATCH_VER = %x\n",
"HALMAC_MAJOR_VER = %d\n"
"HALMAC_PROTOTYPE_VER = %d\n"
"HALMAC_MINOR_VER = %d\n"
"HALMAC_PATCH_VER = %s\n",
HALMAC_MAJOR_VER, HALMAC_PROTOTYPE_VER,
HALMAC_MINOR_VER, HALMAC_PATCH_VER);
@@ -234,6 +238,9 @@ halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api,
#endif
*halmac_api = (struct halmac_api *)adapter->halmac_api;
#if HALMAC_DBG_MONITOR_IO
mount_api_dbg(adapter);
#endif
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return status;
@@ -449,7 +456,18 @@ chk_pltfm_api(void *drv_adapter, enum halmac_interface intf,
HALMAC_DBG_ERR, "[ERR]event-indication\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
#if HALMAC_DBG_MONITOR_IO
if (!pltfm_api->READ_MONITOR) {
pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
HALMAC_DBG_ERR, "[ERR]read-monitor\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!pltfm_api->WRITE_MONITOR) {
pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
HALMAC_DBG_ERR, "[ERR]write-monitor\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
#endif
return HALMAC_RET_SUCCESS;
}

18
hal/halmac/halmac_api.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -18,10 +18,10 @@
#define HALMAC_SVN_VER "11692M"
#define HALMAC_MAJOR_VER 0x0001
#define HALMAC_PROTOTYPE_VER 0x0005
#define HALMAC_MINOR_VER 0x0014
#define HALMAC_PATCH_VER 0x0015
#define HALMAC_MAJOR_VER 1
#define HALMAC_PROTOTYPE_VER 6
#define HALMAC_MINOR_VER 5
#define HALMAC_PATCH_VER "6*"
#define HALMAC_88XX_SUPPORT (HALMAC_8821C_SUPPORT || \
HALMAC_8822B_SUPPORT || \
@@ -71,6 +71,11 @@
#include "halmac_bit_8822c.h"
#endif
#if HALMAC_8812F_SUPPORT
#include "halmac_reg_8812f.h"
#include "halmac_bit_8812f.h"
#endif
#if (HALMAC_PLATFORM_WINDOWS || HALMAC_PLATFORM_LINUX)
#include "halmac_tx_desc_nic.h"
#include "halmac_tx_desc_buffer_nic.h"
@@ -97,6 +102,9 @@
#include "halmac_original_h2c_ap.h"
#endif
#if HALMAC_DBG_MONITOR_IO
#include "halmac_dbg.h"
#endif
#include "halmac_tx_desc_chip.h"
#include "halmac_rx_desc_chip.h"
#include "halmac_tx_desc_buffer_chip.h"

756
hal/halmac/halmac_bit2.h
View File

File diff suppressed because it is too large Load Diff

2
hal/halmac/halmac_bit_8197f.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

22057
hal/halmac/halmac_bit_8812f.h Normal file
View File

File diff suppressed because it is too large Load Diff

4
hal/halmac/halmac_bit_8814b.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -14517,6 +14517,7 @@
/* 2 REG_LIFETIME_EN_8814B */
#define BIT_BT_INT_CPU_8814B BIT(7)
#define BIT_BT_INT_PTA_8814B BIT(6)
#define BIT_BA_PARSER_EN_8814B BIT(5)
#define BIT_EN_CTRL_RTYBIT_8814B BIT(4)
#define BIT_LIFETIME_BK_EN_8814B BIT(3)
#define BIT_LIFETIME_BE_EN_8814B BIT(2)
@@ -25467,6 +25468,7 @@
BIT_R_WMAC_RX_FIL_LEN_2_8814B(v))
/* 2 REG_RX_FILTER_FUNCTION_8814B */
#define BIT_RXHANG_EN_8814B BIT(15)
#define BIT_R_WMAC_MHRDDY_LATCH_8814B BIT(14)
#define BIT_R_WMAC_MHRDDY_CLR_8814B BIT(13)
#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8814B BIT(12)

2
hal/halmac/halmac_bit_8821c.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
hal/halmac/halmac_bit_8822b.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

61
hal/halmac/halmac_bit_8822c.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2017 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -177,11 +177,11 @@
/* 2 REG_NOT_VALID_8822C */
/* 2 REG_NOT_VALID_8822C */
#define BIT_R_SYM_CTRL_SPS_PWMFREQ_8822C BIT(10)
#define BIT_HW_AUTO_CTRL_EXT_SWR_8822C BIT(9)
#define BIT_USE_INTERNAL_SWR_AND_LDO_8822C BIT(8)
#define BIT_MAC_ID_EN_8822C BIT(7)
/* 2 REG_NOT_VALID_8822C */
#define BIT_OPTION_DIS_XTAL_BG_8822C BIT(2)
/* 2 REG_SYS_SWR_CTRL2_8822C */
@@ -255,9 +255,9 @@
#define BIT_WLOCK_ALL_8822C BIT(0)
/* 2 REG_RF_CTRL_8822C */
#define BIT_RF_SDMRSTB_8822C BIT(2)
#define BIT_RF_RSTB_8822C BIT(1)
#define BIT_RF_EN_8822C BIT(0)
#define BIT_S0_RFC_WO_0_8822C BIT(7)
#define BIT_S0_RFC_WT_0_8822C BIT(6)
#define BIT_S0_RFC_RSTB_8822C BIT(1)
/* 2 REG_AFE_LDO_CTRL_8822C */
#define BIT_R_SYM_WLPON_EMEM1_EN_8822C BIT(31)
@@ -2047,18 +2047,9 @@
(BIT_CLEAR_PCIE_MIO_DATA_8822C(x) | BIT_PCIE_MIO_DATA_8822C(v))
/* 2 REG_WLRF1_8822C */
#define BIT_SHIFT_WLRF1_CTRL_8822C 24
#define BIT_MASK_WLRF1_CTRL_8822C 0xff
#define BIT_WLRF1_CTRL_8822C(x) \
(((x) & BIT_MASK_WLRF1_CTRL_8822C) << BIT_SHIFT_WLRF1_CTRL_8822C)
#define BITS_WLRF1_CTRL_8822C \
(BIT_MASK_WLRF1_CTRL_8822C << BIT_SHIFT_WLRF1_CTRL_8822C)
#define BIT_CLEAR_WLRF1_CTRL_8822C(x) ((x) & (~BITS_WLRF1_CTRL_8822C))
#define BIT_GET_WLRF1_CTRL_8822C(x) \
(((x) >> BIT_SHIFT_WLRF1_CTRL_8822C) & BIT_MASK_WLRF1_CTRL_8822C)
#define BIT_SET_WLRF1_CTRL_8822C(x, v) \
(BIT_CLEAR_WLRF1_CTRL_8822C(x) | BIT_WLRF1_CTRL_8822C(v))
#define BIT_S1_RFC_WO_0_8822C BIT(31)
#define BIT_S1_RFC_WT_0_8822C BIT(30)
#define BIT_S1_RFC_RSTB_8822C BIT(25)
/* 2 REG_SYS_CFG1_8822C */
@@ -3252,7 +3243,36 @@
/* 2 REG_NOT_VALID_8822C */
/* 2 REG_XTAL_AAC_OUTPUT_8822C */
/* 2 REG_NOT_VALID_8822C */
#define BIT_XTAL_PEAKDET_OUT_8822C BIT(9)
#define BIT_XAAC_BUSY_8822C BIT(8)
#define BIT_XAAC_READY_V1_8822C BIT(7)
#define BIT_SHIFT_XAAC_PK_SEL_8822C 5
#define BIT_MASK_XAAC_PK_SEL_8822C 0x3
#define BIT_XAAC_PK_SEL_8822C(x) \
(((x) & BIT_MASK_XAAC_PK_SEL_8822C) << BIT_SHIFT_XAAC_PK_SEL_8822C)
#define BITS_XAAC_PK_SEL_8822C \
(BIT_MASK_XAAC_PK_SEL_8822C << BIT_SHIFT_XAAC_PK_SEL_8822C)
#define BIT_CLEAR_XAAC_PK_SEL_8822C(x) ((x) & (~BITS_XAAC_PK_SEL_8822C))
#define BIT_GET_XAAC_PK_SEL_8822C(x) \
(((x) >> BIT_SHIFT_XAAC_PK_SEL_8822C) & BIT_MASK_XAAC_PK_SEL_8822C)
#define BIT_SET_XAAC_PK_SEL_8822C(x, v) \
(BIT_CLEAR_XAAC_PK_SEL_8822C(x) | BIT_XAAC_PK_SEL_8822C(v))
#define BIT_SHIFT_XTAL_GM_OUT_8822C 0
#define BIT_MASK_XTAL_GM_OUT_8822C 0x1f
#define BIT_XTAL_GM_OUT_8822C(x) \
(((x) & BIT_MASK_XTAL_GM_OUT_8822C) << BIT_SHIFT_XTAL_GM_OUT_8822C)
#define BITS_XTAL_GM_OUT_8822C \
(BIT_MASK_XTAL_GM_OUT_8822C << BIT_SHIFT_XTAL_GM_OUT_8822C)
#define BIT_CLEAR_XTAL_GM_OUT_8822C(x) ((x) & (~BITS_XTAL_GM_OUT_8822C))
#define BIT_GET_XTAL_GM_OUT_8822C(x) \
(((x) >> BIT_SHIFT_XTAL_GM_OUT_8822C) & BIT_MASK_XTAL_GM_OUT_8822C)
#define BIT_SET_XTAL_GM_OUT_8822C(x, v) \
(BIT_CLEAR_XTAL_GM_OUT_8822C(x) | BIT_XTAL_GM_OUT_8822C(v))
/* 2 REG_ANAPAR_XTAL_MODE_DECODER_8822C */
@@ -10134,6 +10154,7 @@
/* 2 REG_LIFETIME_EN_8822C */
#define BIT_BT_INT_CPU_8822C BIT(7)
#define BIT_BT_INT_PTA_8822C BIT(6)
#define BIT_BA_PARSER_EN_8822C BIT(5)
#define BIT_EN_CTRL_RTYBIT_8822C BIT(4)
#define BIT_LIFETIME_BK_EN_8822C BIT(3)
#define BIT_LIFETIME_BE_EN_8822C BIT(2)
@@ -10603,7 +10624,7 @@
(BIT_CLEAR_R_NDPA_RATE_V1_8822C(x) | BIT_R_NDPA_RATE_V1_8822C(v))
/* 2 REG_TX_HANG_CTRL_8822C */
#define BIT_R_EN_GNT_BT_AWAKE_8822C BIT(3)
#define BIT_EN_GNT_BT_AWAKE_8822C BIT(3)
#define BIT_EN_EOF_V1_8822C BIT(2)
#define BIT_DIS_OQT_BLOCK_8822C BIT(1)
#define BIT_SEARCH_QUEUE_EN_8822C BIT(0)
@@ -21419,6 +21440,7 @@
#define BIT_SDIO_CPWM1_MSK_8822C BIT(18)
#define BIT_SDIO_C2HCMD_INT_MSK_8822C BIT(17)
#define BIT_SDIO_BCNERLY_INT_MSK_8822C BIT(16)
#define BIT_BT_INT_MASK_8822C BIT(8)
#define BIT_SDIO_TXBCNERR_MSK_8822C BIT(7)
#define BIT_SDIO_TXBCNOK_MSK_8822C BIT(6)
#define BIT_SDIO_RXFOVW_MSK_8822C BIT(5)
@@ -21445,6 +21467,7 @@
#define BIT_SDIO_CPWM1_8822C BIT(18)
#define BIT_SDIO_C2HCMD_INT_8822C BIT(17)
#define BIT_SDIO_BCNERLY_INT_8822C BIT(16)
#define BIT_BT_INT_8822C BIT(8)
#define BIT_SDIO_TXBCNERR_8822C BIT(7)
#define BIT_SDIO_TXBCNOK_8822C BIT(6)
#define BIT_SDIO_RXFOVW_8822C BIT(5)

132
hal/halmac/halmac_dbg.c Normal file
View File

@@ -0,0 +1,132 @@
/******************************************************************************
*
* Copyright(c) 2018 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "halmac_dbg.h"
#if HALMAC_DBG_MONITOR_IO
static u8
monitor_reg_read_8(struct halmac_adapter *adapter, u32 offset,
const char *func, const u32 line);
static u16
monitor_reg_read_16(struct halmac_adapter *adapter, u32 offset,
const char *func, const u32 line);
static u32
monitor_reg_read_32(struct halmac_adapter *adapter, u32 offset,
const char *func, const u32 line);
static enum halmac_ret_status
monitor_reg_sdio_cmd53_read_n(struct halmac_adapter *adapter,
u32 offset, u32 size, u8 *value,
const char *func, const u32 line);
static enum halmac_ret_status
monitor_reg_write_8(struct halmac_adapter *adapter, u32 offset,
u8 value, const char *func, const u32 line);
static enum halmac_ret_status
monitor_reg_write_16(struct halmac_adapter *adapter, u32 offset,
u16 value, const char *func, const u32 line);
static enum halmac_ret_status
monitor_reg_write_32(struct halmac_adapter *adapter, u32 offset,
u32 value, const char *func, const u32 line);
enum halmac_ret_status
mount_api_dbg(struct halmac_adapter *adapter)
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
api->halmac_mon_reg_read_8 = monitor_reg_read_8;
api->halmac_mon_reg_read_16 = monitor_reg_read_16;
api->halmac_mon_reg_read_32 = monitor_reg_read_32;
api->halmac_mon_reg_sdio_cmd53_read_n = monitor_reg_sdio_cmd53_read_n;
api->halmac_mon_reg_write_8 = monitor_reg_write_8;
api->halmac_mon_reg_write_16 = monitor_reg_write_16;
api->halmac_mon_reg_write_32 = monitor_reg_write_32;
return HALMAC_RET_SUCCESS;
}
u8
monitor_reg_read_8(struct halmac_adapter *adapter, u32 offset,
const char *func, const u32 line)
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
u8 val;
val = api->halmac_reg_read_8(adapter, offset);
PLTFM_MONITOR_READ(offset, 1, val, func, line);
return val;
}
u16
monitor_reg_read_16(struct halmac_adapter *adapter, u32 offset,
const char *func, const u32 line)
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
u16 val;
val = api->halmac_reg_read_16(adapter, offset);
PLTFM_MONITOR_READ(offset, 2, val, func, line);
return val;
}
u32
monitor_reg_read_32(struct halmac_adapter *adapter, u32 offset,
const char *func, const u32 line)
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
u32 val;
val = api->halmac_reg_read_32(adapter, offset);
PLTFM_MONITOR_READ(offset, 4, val, func, line);
return val;
}
enum halmac_ret_status
monitor_reg_sdio_cmd53_read_n(struct halmac_adapter *adapter,
u32 offset, u32 size, u8 *value,
const char *func, const u32 line)
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MONITOR_READ(offset, size, 0, func, line);
return api->halmac_reg_sdio_cmd53_read_n(adapter, offset, size, value);
}
enum halmac_ret_status
monitor_reg_write_8(struct halmac_adapter *adapter, u32 offset,
u8 value, const char *func, const u32 line)
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MONITOR_WRITE(offset, 1, value, func, line);
return api->halmac_reg_write_8(adapter, offset, value);
}
enum halmac_ret_status
monitor_reg_write_16(struct halmac_adapter *adapter, u32 offset,
u16 value, const char *func, const u32 line)
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MONITOR_WRITE(offset, 2, value, func, line);
return api->halmac_reg_write_16(adapter, offset, value);
}
enum halmac_ret_status
monitor_reg_write_32(struct halmac_adapter *adapter, u32 offset,
u32 value, const char *func, const u32 line)
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MONITOR_WRITE(offset, 4, value, func, line);
return api->halmac_reg_write_32(adapter, offset, value);
}
#endif

26
hal/halmac/halmac_dbg.h Normal file
View File

@@ -0,0 +1,26 @@
/******************************************************************************
*
* Copyright(c) 2018 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _HALMAC_DBG_H_
#define _HALMAC_DBG_H_
#include "halmac_api.h"
#if HALMAC_DBG_MONITOR_IO
enum halmac_ret_status
mount_api_dbg(struct halmac_adapter *adapter);
#endif
#endif

84
hal/halmac/halmac_fw_info.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -16,39 +16,42 @@
#ifndef _HALMAC_FW_INFO_H_
#define _HALMAC_FW_INFO_H_
#define H2C_FORMAT_VERSION 12
#define H2C_FORMAT_VERSION 15
/* FW bin information */
#define WLAN_FW_HDR_SIZE 64
#define WLAN_FW_HDR_CHKSUM_SIZE 8
#define WLAN_FW_HDR_SIZE 64
#define WLAN_FW_HDR_CHKSUM_SIZE 8
#define WLAN_FW_HDR_VERSION 4
#define WLAN_FW_HDR_SUBVERSION 6
#define WLAN_FW_HDR_SUBINDEX 7
#define WLAN_FW_HDR_MONTH 16
#define WLAN_FW_HDR_DATE 17
#define WLAN_FW_HDR_HOUR 18
#define WLAN_FW_HDR_MIN 19
#define WLAN_FW_HDR_YEAR 20
#define WLAN_FW_HDR_MEM_USAGE 24
#define WLAN_FW_HDR_H2C_FMT_VER 28
#define WLAN_FW_HDR_DMEM_ADDR 32
#define WLAN_FW_HDR_DMEM_SIZE 36
#define WLAN_FW_HDR_IMEM_SIZE 48
#define WLAN_FW_HDR_EMEM_SIZE 52
#define WLAN_FW_HDR_EMEM_ADDR 56
#define WLAN_FW_HDR_IMEM_ADDR 60
#define WLAN_FW_HDR_VERSION 4
#define WLAN_FW_HDR_SUBVERSION 6
#define WLAN_FW_HDR_SUBINDEX 7
#define WLAN_FW_HDR_MONTH 16
#define WLAN_FW_HDR_DATE 17
#define WLAN_FW_HDR_HOUR 18
#define WLAN_FW_HDR_MIN 19
#define WLAN_FW_HDR_YEAR 20
#define WLAN_FW_HDR_MEM_USAGE 24
#define WLAN_FW_HDR_H2C_FMT_VER 28
#define WLAN_FW_HDR_DMEM_ADDR 32
#define WLAN_FW_HDR_DMEM_SIZE 36
#define WLAN_FW_HDR_IMEM_SIZE 48
#define WLAN_FW_HDR_EMEM_SIZE 52
#define WLAN_FW_HDR_EMEM_ADDR 56
#define WLAN_FW_HDR_IMEM_ADDR 60
#define H2C_ACK_HDR_CONTENT_LENGTH 8
#define H2C_ACK_HDR_CONTENT_LENGTH 8
#define CFG_PARAMETER_ACK_CONTENT_LENGTH 16
#define CH_SWITCH_ACK_CONTENT_LENGTH 16
#define SCAN_STATUS_RPT_CONTENT_LENGTH 4
#define C2H_DBG_HDR_LEN 4
#define C2H_DBG_CONTENT_MAX_LENGTH 228
#define C2H_DBG_CONTENT_SEQ_OFFSET 1
#define SCAN_STATUS_RPT_CONTENT_LENGTH_V2 12
#define SCAN_CH_NOTIFY_CONTENT_LENGTH 12
#define C2H_DBG_HDR_LEN 4
#define C2H_DBG_CONTENT_MAX_LENGTH 228
#define C2H_DBG_CONTENT_SEQ_OFFSET 1
/* Rename from FW SysHalCom_Debug_RAM.h */
#define FW_REG_H2CPKT_DONE_SEQ 0x1C8
#define FW_REG_WOW_REASON 0x1C7
#define FW_REG_H2CPKT_DONE_SEQ 0x1C8
#define FW_REG_WOW_REASON 0x1C7
enum halmac_data_type {
HALMAC_DATA_TYPE_MAC_REG = 0x00,
@@ -89,6 +92,7 @@ enum halmac_cs_extra_action_id {
HALMAC_CS_EXTRA_ACTION_NONE = 0x00,
HALMAC_CS_EXTRA_UPDATE_PROBE = 0x01,
HALMAC_CS_EXTRA_UPDATE_BEACON = 0x02,
HALMAC_CS_EXTRA_ACTION_SCAN = 0x03,
HALMAC_CS_EXTRA_ACTION_UNDEFINE = 0x7FFFFFFF,
};
@@ -108,6 +112,10 @@ enum halmac_h2c_return_code {
HALMAC_H2C_RETURN_SCAN_ERR_FULL = 0x0C,
HALMAC_H2C_RETURN_SCAN_ERR_PHYDM = 0x0D,
HALMAC_H2C_RETURN_ORIG_ERR_ID = 0x0E,
HALMAC_H2C_RETURN_SCAN_PKT_FULL = 0x0F,
HALMAC_H2C_RETURN_SCAN_PKT_BUF_BUSY = 0x10,
HALMAC_H2C_RETURN_SCAN_PKT_IDX_REUSE = 0x11,
HALMAC_H2C_RETURN_EFUSE_BUF_BUSY = 0x12,
HALMAC_H2C_RETURN_UNDEFINE = 0x7FFFFFFF,
};
@@ -119,4 +127,28 @@ enum halmac_scan_report_code {
HALMAC_SCAN_REPORT_UNDEFINE = 0x7FFFFFFF,
};
enum halmac_scan_notify_id {
HALMAC_SCAN_NOTIFY_ID_PRESWITCH = 0x00,
HALMAC_SCAN_NOTIFY_ID_POSTSWITCH = 0x01,
HALMAC_SCAN_NOTIFY_ID_PROBE_PRETX = 0x02,
HALMAC_SCAN_NOTIFY_ID_PROBE_POSTTX = 0x03,
HALMAC_SCAN_NOTIFY_ID_ACTION_PRETX = 0x04,
HALMAC_SCAN_NOTIFY_ID_ACTION_POSTTX = 0x05,
HALMAC_SCAN_NOTIFY_ID_DWELLEXT = 0x06,
HALMAC_SCAN_NOTIFY_ID_UNDEFINE = 0x7F,
};
enum halmac_scan_notify_status {
HALMAC_SCAN_NOTIFY_STATUS_NONE = 0x00,
HALMAC_SCAN_NOTIFY_STATUS_PHYDM_OK = 0x01,
HALMAC_SCAN_NOTIFY_STATUS_PHYDM_ERR = 0x02,
HALMAC_SCAN_NOTIFY_STATUS_NO_PROBE = 0x03,
HALMAC_SCAN_NOTIFY_STATUS_TX_PROBE_OK = 0x04,
HALMAC_SCAN_NOTIFY_STATUS_TX_PROBE_FAIL = 0x05,
HALMAC_SCAN_NOTIFY_STATUS_INVALID_ACTION_IDX = 0x06,
HALMAC_SCAN_NOTIFY_STATUS_TX_ACTION_OK = 0x07,
HALMAC_SCAN_NOTIFY_STATUS_TX_ACTION_FAIL = 0x08,
HALMAC_SCAN_NOTIFY_STATUS_UNDEFINE = 0x7F,
};
#endif

31
hal/halmac/halmac_fw_offload_c2h_ap.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -24,12 +24,16 @@
#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01
#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01
#define C2H_SUB_CMD_ID_UPDATE_PKT_ACK 0X01
#define C2H_SUB_CMD_ID_SEND_SCAN_PKT_ACK 0X01
#define C2H_SUB_CMD_ID_DROP_SCAN_PKT_ACK 0X01
#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01
#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01
#define C2H_SUB_CMD_ID_IQK_ACK 0X01
#define C2H_SUB_CMD_ID_PWR_TRK_ACK 0X01
#define C2H_SUB_CMD_ID_PSD_ACK 0X01
#define C2H_SUB_CMD_ID_FW_MEM_DUMP_ACK 0X01
#define C2H_SUB_CMD_ID_ACT_SCHEDULE_REQ_ACK 0X1
#define C2H_SUB_CMD_ID_NAN_FUNC_CTRL_ACK 0X1
#define C2H_SUB_CMD_ID_PSD_DATA 0X04
#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
#define C2H_SUB_CMD_ID_IQK_DATA 0X06
@@ -44,6 +48,8 @@
#define C2H_SUB_CMD_ID_CCX_RPT 0X0F
#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10
#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11
#define C2H_SUB_CMD_ID_C2H_PKT_SCC_CSA_RPT 0X1A
#define C2H_SUB_CMD_ID_C2H_PKT_FW_STATUS_NOTIFY 0X1B
#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C
#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D
#define C2H_SUB_CMD_ID_FW_DBG_MSG 0XFF
@@ -59,12 +65,16 @@
#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX
#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE
#define H2C_SUB_CMD_ID_UPDATE_PKT_ACK SUB_CMD_ID_UPDATE_PKT
#define H2C_SUB_CMD_ID_SEND_SCAN_PKT_ACK SUB_CMD_ID_SEND_SCAN_PKT
#define H2C_SUB_CMD_ID_DROP_SCAN_PKT_ACK SUB_CMD_ID_DROP_SCAN_PKT
#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK
#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK
#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK
#define H2C_SUB_CMD_ID_PWR_TRK_ACK SUB_CMD_ID_PWR_TRK
#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD
#define H2C_SUB_CMD_ID_FW_MEM_DUMP_ACK SUB_CMD_ID_FW_MEM_DUMP
#define H2C_SUB_CMD_ID_ACT_SCHEDULE_REQ_ACK SUB_CMD_ID_ACT_SCHEDULE_REQ
#define H2C_SUB_CMD_ID_NAN_FUNC_CTRL_ACK SUB_CMD_ID_NAN_FUNC_CTRL
#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT
#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG
#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING
@@ -76,12 +86,16 @@
#define H2C_CMD_ID_BT_COEX_ACK 0XFF
#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF
#define H2C_CMD_ID_UPDATE_PKT_ACK 0XFF
#define H2C_CMD_ID_SEND_SCAN_PKT_ACK 0XFF
#define H2C_CMD_ID_DROP_SCAN_PKT_ACK 0XFF
#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF
#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF
#define H2C_CMD_ID_IQK_ACK 0XFF
#define H2C_CMD_ID_PWR_TRK_ACK 0XFF
#define H2C_CMD_ID_PSD_ACK 0XFF
#define H2C_CMD_ID_FW_MEM_DUMP_ACK 0XFF
#define H2C_CMD_ID_ACT_SCHEDULE_REQ_ACK 0XFF
#define H2C_CMD_ID_NAN_FUNC_CTRL_ACK 0XFF
#define H2C_CMD_ID_CCX_RPT 0XFF
#define H2C_CMD_ID_FW_DBG_MSG 0XFF
#define H2C_CMD_ID_FW_SNDING_ACK 0XFF
@@ -430,6 +444,18 @@
SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 30, 2, value)
#define CCX_RPT_SET_BW_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 30, 2, value)
#define C2H_PKT_FW_STATUS_NOTIFY_GET_STATUS_CODE(c2h_pkt) \
GET_C2H_FIELD(c2h_pkt + 0X04, 0, 32)
#define C2H_PKT_FW_STATUS_NOTIFY_SET_STATUS_CODE(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 32, value)
#define C2H_PKT_FW_STATUS_NOTIFY_SET_STATUS_CODE_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 32, value)
#define C2H_PKT_DETECT_THERMAL_GET_THERMAL_VALUE(c2h_pkt) \
GET_C2H_FIELD(c2h_pkt + 0X04, 0, 32)
#define C2H_PKT_DETECT_THERMAL_SET_THERMAL_VALUE(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 32, value)
#define C2H_PKT_DETECT_THERMAL_SET_THERMAL_VALUE_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 32, value)
#define FW_DBG_MSG_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
#define FW_DBG_MSG_SET_CMD_ID(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
@@ -650,8 +676,7 @@
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
#define FW_TBTT_RPT_SET_PORT_NUMBER_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
#define BCN_OFFLOAD_GET_SUPPORT_VER(c2h_pkt) \
GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
#define BCN_OFFLOAD_GET_SUPPORT_VER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
#define BCN_OFFLOAD_SET_SUPPORT_VER(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
#define BCN_OFFLOAD_SET_SUPPORT_VER_NO_CLR(c2h_pkt, value) \

24
hal/halmac/halmac_fw_offload_c2h_nic.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -24,12 +24,16 @@
#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01
#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01
#define C2H_SUB_CMD_ID_UPDATE_PKT_ACK 0X01
#define C2H_SUB_CMD_ID_SEND_SCAN_PKT_ACK 0X01
#define C2H_SUB_CMD_ID_DROP_SCAN_PKT_ACK 0X01
#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01
#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01
#define C2H_SUB_CMD_ID_IQK_ACK 0X01
#define C2H_SUB_CMD_ID_PWR_TRK_ACK 0X01
#define C2H_SUB_CMD_ID_PSD_ACK 0X01
#define C2H_SUB_CMD_ID_FW_MEM_DUMP_ACK 0X01
#define C2H_SUB_CMD_ID_ACT_SCHEDULE_REQ_ACK 0X1
#define C2H_SUB_CMD_ID_NAN_FUNC_CTRL_ACK 0X1
#define C2H_SUB_CMD_ID_PSD_DATA 0X04
#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
#define C2H_SUB_CMD_ID_IQK_DATA 0X06
@@ -44,6 +48,8 @@
#define C2H_SUB_CMD_ID_CCX_RPT 0X0F
#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10
#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11
#define C2H_SUB_CMD_ID_C2H_PKT_SCC_CSA_RPT 0X1A
#define C2H_SUB_CMD_ID_C2H_PKT_FW_STATUS_NOTIFY 0X1B
#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C
#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D
#define C2H_SUB_CMD_ID_FW_DBG_MSG 0XFF
@@ -59,12 +65,16 @@
#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX
#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE
#define H2C_SUB_CMD_ID_UPDATE_PKT_ACK SUB_CMD_ID_UPDATE_PKT
#define H2C_SUB_CMD_ID_SEND_SCAN_PKT_ACK SUB_CMD_ID_SEND_SCAN_PKT
#define H2C_SUB_CMD_ID_DROP_SCAN_PKT_ACK SUB_CMD_ID_DROP_SCAN_PKT
#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK
#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK
#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK
#define H2C_SUB_CMD_ID_PWR_TRK_ACK SUB_CMD_ID_PWR_TRK
#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD
#define H2C_SUB_CMD_ID_FW_MEM_DUMP_ACK SUB_CMD_ID_FW_MEM_DUMP
#define H2C_SUB_CMD_ID_ACT_SCHEDULE_REQ_ACK SUB_CMD_ID_ACT_SCHEDULE_REQ
#define H2C_SUB_CMD_ID_NAN_FUNC_CTRL_ACK SUB_CMD_ID_NAN_FUNC_CTRL
#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT
#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG
#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING
@@ -76,12 +86,16 @@
#define H2C_CMD_ID_BT_COEX_ACK 0XFF
#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF
#define H2C_CMD_ID_UPDATE_PKT_ACK 0XFF
#define H2C_CMD_ID_SEND_SCAN_PKT_ACK 0XFF
#define H2C_CMD_ID_DROP_SCAN_PKT_ACK 0XFF
#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF
#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF
#define H2C_CMD_ID_IQK_ACK 0XFF
#define H2C_CMD_ID_PWR_TRK_ACK 0XFF
#define H2C_CMD_ID_PSD_ACK 0XFF
#define H2C_CMD_ID_FW_MEM_DUMP_ACK 0XFF
#define H2C_CMD_ID_ACT_SCHEDULE_REQ_ACK 0XFF
#define H2C_CMD_ID_NAN_FUNC_CTRL_ACK 0XFF
#define H2C_CMD_ID_CCX_RPT 0XFF
#define H2C_CMD_ID_FW_DBG_MSG 0XFF
#define H2C_CMD_ID_FW_SNDING_ACK 0XFF
@@ -320,6 +334,14 @@
#define CCX_RPT_GET_BW(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 30, 2)
#define CCX_RPT_SET_BW(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 30, 2, value)
#define C2H_PKT_FW_STATUS_NOTIFY_GET_STATUS_CODE(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 32)
#define C2H_PKT_FW_STATUS_NOTIFY_SET_STATUS_CODE(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 32, value)
#define C2H_PKT_DETECT_THERMAL_GET_THERMAL_VALUE(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 32)
#define C2H_PKT_DETECT_THERMAL_SET_THERMAL_VALUE(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 32, value)
#define FW_DBG_MSG_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
#define FW_DBG_MSG_SET_CMD_ID(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)

186
hal/halmac/halmac_fw_offload_h2c_ap.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -34,13 +34,16 @@
#define CMD_ID_FW_FWCTRL 0XFF
#define CMD_ID_H2C_LOOPBACK 0XFF
#define CMD_ID_FWCMD_LOOPBACK 0XFF
#define CMD_ID_UPDATE_SCAN_PKT 0XFF
#define CMD_ID_SEND_SCAN_PKT 0XFF
#define CMD_ID_BCN_OFFLOAD 0XFF
#define CMD_ID_DROP_SCAN_PKT 0XFF
#define CMD_ID_P2PPS 0XFF
#define CMD_ID_BT_COEX 0XFF
#define CMD_ID_ACT_SCHEDULE_REQ 0XFF
#define CMD_ID_NAN_CTRL 0XFF
#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF
#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF
#define CMD_ID_NAN_FUNC_CTRL 0XFF
#define CATEGORY_H2C_CMD_HEADER 0X00
#define CATEGORY_FW_OFFLOAD_H2C 0X01
#define CATEGORY_FW_ACCESS_TEST 0X01
@@ -61,13 +64,16 @@
#define CATEGORY_FW_FWCTRL 0X01
#define CATEGORY_H2C_LOOPBACK 0X01
#define CATEGORY_FWCMD_LOOPBACK 0X01
#define CATEGORY_UPDATE_SCAN_PKT 0X01
#define CATEGORY_SEND_SCAN_PKT 0X01
#define CATEGORY_BCN_OFFLOAD 0X01
#define CATEGORY_DROP_SCAN_PKT 0X01
#define CATEGORY_P2PPS 0X01
#define CATEGORY_BT_COEX 0X01
#define CATEGORY_ACT_SCHEDULE_REQ 0X01
#define CATEGORY_NAN_CTRL 0X01
#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01
#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01
#define CATEGORY_NAN_FUNC_CTRL 0X01
#define SUB_CMD_ID_FW_ACCESS_TEST 0X00
#define SUB_CMD_ID_CH_SWITCH 0X02
#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
@@ -86,13 +92,16 @@
#define SUB_CMD_ID_FW_FWCTRL 0X13
#define SUB_CMD_ID_H2C_LOOPBACK 0X14
#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15
#define SUB_CMD_ID_UPDATE_SCAN_PKT 0X16
#define SUB_CMD_ID_SEND_SCAN_PKT 0X16
#define SUB_CMD_ID_BCN_OFFLOAD 0X17
#define SUB_CMD_ID_DROP_SCAN_PKT 0X18
#define SUB_CMD_ID_P2PPS 0X24
#define SUB_CMD_ID_BT_COEX 0X60
#define SUB_CMD_ID_ACT_SCHEDULE_REQ 0X70
#define SUB_CMD_ID_NAN_CTRL 0XB2
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
#define SUB_CMD_ID_NAN_FUNC_CTRL 0XB6
#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 7)
#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 7, value)
@@ -626,6 +635,21 @@
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 28, 4, value)
#define PHYDM_INFO_SET_TX_ANT_STATUS_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 28, 4, value)
#define PHYDM_INFO_GET_EXT_PA(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 0, 8)
#define PHYDM_INFO_SET_EXT_PA(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 0, 8, value)
#define PHYDM_INFO_SET_EXT_PA_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 0, 8, value)
#define PHYDM_INFO_GET_PACKAGE_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 8, 8)
#define PHYDM_INFO_SET_PACKAGE_TYPE(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 8, 8, value)
#define PHYDM_INFO_SET_PACKAGE_TYPE_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 8, 8, value)
#define PHYDM_INFO_GET_MP_MODE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 16, 1)
#define PHYDM_INFO_SET_MP_MODE(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 16, 1, value)
#define PHYDM_INFO_SET_MP_MODE_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 16, 1, value)
#define FW_SNDING_GET_SU0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
#define FW_SNDING_SET_SU0(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
@@ -709,20 +733,20 @@
SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value)
#define FW_FWCTRL_SET_CONTENT_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value)
#define UPDATE_SCAN_PKT_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)
#define UPDATE_SCAN_PKT_SET_SIZE(h2c_pkt, value) \
#define SEND_SCAN_PKT_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)
#define SEND_SCAN_PKT_SET_SIZE(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)
#define UPDATE_SCAN_PKT_SET_SIZE_NO_CLR(h2c_pkt, value) \
#define SEND_SCAN_PKT_SET_SIZE_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)
#define UPDATE_SCAN_PKT_GET_INDEX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
#define UPDATE_SCAN_PKT_SET_INDEX(h2c_pkt, value) \
#define SEND_SCAN_PKT_GET_INDEX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
#define SEND_SCAN_PKT_SET_INDEX(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
#define UPDATE_SCAN_PKT_SET_INDEX_NO_CLR(h2c_pkt, value) \
#define SEND_SCAN_PKT_SET_INDEX_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
#define UPDATE_SCAN_PKT_GET_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
#define UPDATE_SCAN_PKT_SET_LOC(h2c_pkt, value) \
#define SEND_SCAN_PKT_GET_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
#define SEND_SCAN_PKT_SET_LOC(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
#define UPDATE_SCAN_PKT_SET_LOC_NO_CLR(h2c_pkt, value) \
#define SEND_SCAN_PKT_SET_LOC_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
#define BCN_OFFLOAD_GET_REQUEST_VERSION(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
@@ -764,6 +788,22 @@
SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
#define BCN_OFFLOAD_SET_RULE_CONTENT_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
#define DROP_SCAN_PKT_GET_DROP_ALL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
#define DROP_SCAN_PKT_SET_DROP_ALL(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
#define DROP_SCAN_PKT_SET_DROP_ALL_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
#define DROP_SCAN_PKT_GET_DROP_SINGLE(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
#define DROP_SCAN_PKT_SET_DROP_SINGLE(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
#define DROP_SCAN_PKT_SET_DROP_SINGLE_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
#define DROP_SCAN_PKT_GET_DROP_IDX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
#define DROP_SCAN_PKT_SET_DROP_IDX(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
#define DROP_SCAN_PKT_SET_DROP_IDX_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
#define P2PPS_GET_OFFLOAD_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
#define P2PPS_SET_OFFLOAD_EN(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
@@ -852,6 +892,65 @@
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
#define BT_COEX_SET_DATA_START_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
#define ACT_SCHEDULE_REQ_GET_MODULE_ID(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
#define ACT_SCHEDULE_REQ_SET_MODULE_ID(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
#define ACT_SCHEDULE_REQ_SET_MODULE_ID_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
#define ACT_SCHEDULE_REQ_GET_PRIORITY(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
#define ACT_SCHEDULE_REQ_SET_PRIORITY(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
#define ACT_SCHEDULE_REQ_SET_PRIORITY_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
#define ACT_SCHEDULE_REQ_GET_RSVD1(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 16, 16)
#define ACT_SCHEDULE_REQ_SET_RSVD1(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 16, value)
#define ACT_SCHEDULE_REQ_SET_RSVD1_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 16, value)
#define ACT_SCHEDULE_REQ_GET_START_TIME(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0XC, 0, 32)
#define ACT_SCHEDULE_REQ_SET_START_TIME(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 0, 32, value)
#define ACT_SCHEDULE_REQ_SET_START_TIME_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 0, 32, value)
#define ACT_SCHEDULE_REQ_GET_DURATION(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32)
#define ACT_SCHEDULE_REQ_SET_DURATION(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value)
#define ACT_SCHEDULE_REQ_SET_DURATION_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value)
#define ACT_SCHEDULE_REQ_GET_PERIOD(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X14, 0, 32)
#define ACT_SCHEDULE_REQ_SET_PERIOD(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value)
#define ACT_SCHEDULE_REQ_SET_PERIOD_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value)
#define ACT_SCHEDULE_REQ_GET_TSF_IDX(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X18, 0, 8)
#define ACT_SCHEDULE_REQ_SET_TSF_IDX(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value)
#define ACT_SCHEDULE_REQ_SET_TSF_IDX_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value)
#define ACT_SCHEDULE_REQ_GET_CHANNEL(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X18, 8, 8)
#define ACT_SCHEDULE_REQ_SET_CHANNEL(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value)
#define ACT_SCHEDULE_REQ_SET_CHANNEL_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value)
#define ACT_SCHEDULE_REQ_GET_BW(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 16, 8)
#define ACT_SCHEDULE_REQ_SET_BW(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 16, 8, value)
#define ACT_SCHEDULE_REQ_SET_BW_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 16, 8, value)
#define ACT_SCHEDULE_REQ_GET_PRIMART_CH_IDX(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X18, 24, 9)
#define ACT_SCHEDULE_REQ_SET_PRIMART_CH_IDX(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 24, 9, value)
#define ACT_SCHEDULE_REQ_SET_PRIMART_CH_IDX_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 24, 9, value)
#define NAN_CTRL_GET_NAN_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 2)
#define NAN_CTRL_SET_NAN_EN(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 2, value)
@@ -1052,4 +1151,65 @@
SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 16, 16, value)
#define NAN_CHANNEL_PLAN_1_SET_DURATION_5_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 16, 16, value)
#define NAN_FUNC_CTRL_GET_PORT_IDX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
#define NAN_FUNC_CTRL_SET_PORT_IDX(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
#define NAN_FUNC_CTRL_SET_PORT_IDX_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
#define NAN_FUNC_CTRL_GET_MAC_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
#define NAN_FUNC_CTRL_SET_MAC_ID(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
#define NAN_FUNC_CTRL_SET_MAC_ID_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
#define NAN_FUNC_CTRL_GET_MASTER_PREF(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
#define NAN_FUNC_CTRL_SET_MASTER_PREF(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
#define NAN_FUNC_CTRL_SET_MASTER_PREF_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
#define NAN_FUNC_CTRL_GET_RANDOM_FACTOR(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
#define NAN_FUNC_CTRL_SET_RANDOM_FACTOR(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
#define NAN_FUNC_CTRL_SET_RANDOM_FACTOR_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
#define NAN_FUNC_CTRL_GET_OP_CH_24G(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)
#define NAN_FUNC_CTRL_SET_OP_CH_24G(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
#define NAN_FUNC_CTRL_SET_OP_CH_24G_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
#define NAN_FUNC_CTRL_GET_OP_CH_5G(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 8)
#define NAN_FUNC_CTRL_SET_OP_CH_5G(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 8, value)
#define NAN_FUNC_CTRL_SET_OP_CH_5G_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 8, value)
#define NAN_FUNC_CTRL_GET_OPTIONS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 16)
#define NAN_FUNC_CTRL_SET_OPTIONS(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 16, value)
#define NAN_FUNC_CTRL_SET_OPTIONS_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 16, value)
#define NAN_FUNC_CTRL_GET_SYNC_BCN_RSVD_OFFSET(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X10, 0, 8)
#define NAN_FUNC_CTRL_SET_SYNC_BCN_RSVD_OFFSET(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value)
#define NAN_FUNC_CTRL_SET_SYNC_BCN_RSVD_OFFSET_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value)
#define NAN_FUNC_CTRL_GET_DISC_BCN_RSVD_OFFSET(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X10, 8, 8)
#define NAN_FUNC_CTRL_SET_DISC_BCN_RSVD_OFFSET(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value)
#define NAN_FUNC_CTRL_SET_DISC_BCN_RSVD_OFFSET_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value)
#define NAN_FUNC_CTRL_GET_DW_SCHDL_PRIORITY(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X10, 16, 8)
#define NAN_FUNC_CTRL_SET_DW_SCHDL_PRIORITY(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 16, 8, value)
#define NAN_FUNC_CTRL_SET_DW_SCHDL_PRIORITY_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 16, 8, value)
#define NAN_FUNC_CTRL_GET_TIME_INDICATE_PERIOD(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X10, 24, 8)
#define NAN_FUNC_CTRL_SET_TIME_INDICATE_PERIOD(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 24, 8, value)
#define NAN_FUNC_CTRL_SET_TIME_INDICATE_PERIOD_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 24, 8, value)
#endif

135
hal/halmac/halmac_fw_offload_h2c_nic.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -34,13 +34,16 @@
#define CMD_ID_FW_FWCTRL 0XFF
#define CMD_ID_H2C_LOOPBACK 0XFF
#define CMD_ID_FWCMD_LOOPBACK 0XFF
#define CMD_ID_UPDATE_SCAN_PKT 0XFF
#define CMD_ID_SEND_SCAN_PKT 0XFF
#define CMD_ID_BCN_OFFLOAD 0XFF
#define CMD_ID_DROP_SCAN_PKT 0XFF
#define CMD_ID_P2PPS 0XFF
#define CMD_ID_BT_COEX 0XFF
#define CMD_ID_ACT_SCHEDULE_REQ 0XFF
#define CMD_ID_NAN_CTRL 0XFF
#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF
#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF
#define CMD_ID_NAN_FUNC_CTRL 0XFF
#define CATEGORY_H2C_CMD_HEADER 0X00
#define CATEGORY_FW_OFFLOAD_H2C 0X01
#define CATEGORY_FW_ACCESS_TEST 0X01
@@ -61,13 +64,16 @@
#define CATEGORY_FW_FWCTRL 0X01
#define CATEGORY_H2C_LOOPBACK 0X01
#define CATEGORY_FWCMD_LOOPBACK 0X01
#define CATEGORY_UPDATE_SCAN_PKT 0X01
#define CATEGORY_SEND_SCAN_PKT 0X01
#define CATEGORY_BCN_OFFLOAD 0X01
#define CATEGORY_DROP_SCAN_PKT 0X01
#define CATEGORY_P2PPS 0X01
#define CATEGORY_BT_COEX 0X01
#define CATEGORY_ACT_SCHEDULE_REQ 0X01
#define CATEGORY_NAN_CTRL 0X01
#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01
#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01
#define CATEGORY_NAN_FUNC_CTRL 0X01
#define SUB_CMD_ID_FW_ACCESS_TEST 0X00
#define SUB_CMD_ID_CH_SWITCH 0X02
#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
@@ -86,13 +92,16 @@
#define SUB_CMD_ID_FW_FWCTRL 0X13
#define SUB_CMD_ID_H2C_LOOPBACK 0X14
#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15
#define SUB_CMD_ID_UPDATE_SCAN_PKT 0X16
#define SUB_CMD_ID_SEND_SCAN_PKT 0X16
#define SUB_CMD_ID_BCN_OFFLOAD 0X17
#define SUB_CMD_ID_DROP_SCAN_PKT 0X18
#define SUB_CMD_ID_P2PPS 0X24
#define SUB_CMD_ID_BT_COEX 0X60
#define SUB_CMD_ID_ACT_SCHEDULE_REQ 0X70
#define SUB_CMD_ID_NAN_CTRL 0XB2
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
#define SUB_CMD_ID_NAN_FUNC_CTRL 0XB6
#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 7)
#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value) \
@@ -454,6 +463,16 @@
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 28, 4)
#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 28, 4, value)
#define PHYDM_INFO_GET_EXT_PA(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 0, 8)
#define PHYDM_INFO_SET_EXT_PA(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 0, 8, value)
#define PHYDM_INFO_GET_PACKAGE_TYPE(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 8, 8)
#define PHYDM_INFO_SET_PACKAGE_TYPE(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 8, 8, value)
#define PHYDM_INFO_GET_MP_MODE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 16, 1)
#define PHYDM_INFO_SET_MP_MODE(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 16, 1, value)
#define FW_SNDING_GET_SU0(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
#define FW_SNDING_SET_SU0(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
@@ -510,16 +529,14 @@
#define FW_FWCTRL_GET_CONTENT(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32)
#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value)
#define UPDATE_SCAN_PKT_GET_SIZE(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)
#define UPDATE_SCAN_PKT_SET_SIZE(h2c_pkt, value) \
#define SEND_SCAN_PKT_GET_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)
#define SEND_SCAN_PKT_SET_SIZE(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)
#define UPDATE_SCAN_PKT_GET_INDEX(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
#define UPDATE_SCAN_PKT_SET_INDEX(h2c_pkt, value) \
#define SEND_SCAN_PKT_GET_INDEX(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
#define SEND_SCAN_PKT_SET_INDEX(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
#define UPDATE_SCAN_PKT_GET_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
#define UPDATE_SCAN_PKT_SET_LOC(h2c_pkt, value) \
#define SEND_SCAN_PKT_GET_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
#define SEND_SCAN_PKT_SET_LOC(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
#define BCN_OFFLOAD_GET_REQUEST_VERSION(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
@@ -548,6 +565,18 @@
LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
#define BCN_OFFLOAD_SET_RULE_CONTENT(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
#define DROP_SCAN_PKT_GET_DROP_ALL(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
#define DROP_SCAN_PKT_SET_DROP_ALL(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
#define DROP_SCAN_PKT_GET_DROP_SINGLE(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
#define DROP_SCAN_PKT_SET_DROP_SINGLE(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
#define DROP_SCAN_PKT_GET_DROP_IDX(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
#define DROP_SCAN_PKT_SET_DROP_IDX(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
#define P2PPS_GET_OFFLOAD_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
#define P2PPS_SET_OFFLOAD_EN(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
@@ -605,6 +634,45 @@
#define BT_COEX_GET_DATA_START(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
#define BT_COEX_SET_DATA_START(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
#define ACT_SCHEDULE_REQ_GET_MODULE_ID(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
#define ACT_SCHEDULE_REQ_SET_MODULE_ID(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
#define ACT_SCHEDULE_REQ_GET_PRIORITY(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
#define ACT_SCHEDULE_REQ_SET_PRIORITY(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
#define ACT_SCHEDULE_REQ_GET_RSVD1(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 16)
#define ACT_SCHEDULE_REQ_SET_RSVD1(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 16, value)
#define ACT_SCHEDULE_REQ_GET_START_TIME(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 0, 32)
#define ACT_SCHEDULE_REQ_SET_START_TIME(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 0, 32, value)
#define ACT_SCHEDULE_REQ_GET_DURATION(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32)
#define ACT_SCHEDULE_REQ_SET_DURATION(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value)
#define ACT_SCHEDULE_REQ_GET_PERIOD(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32)
#define ACT_SCHEDULE_REQ_SET_PERIOD(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value)
#define ACT_SCHEDULE_REQ_GET_TSF_IDX(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8)
#define ACT_SCHEDULE_REQ_SET_TSF_IDX(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value)
#define ACT_SCHEDULE_REQ_GET_CHANNEL(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8)
#define ACT_SCHEDULE_REQ_SET_CHANNEL(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value)
#define ACT_SCHEDULE_REQ_GET_BW(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 16, 8)
#define ACT_SCHEDULE_REQ_SET_BW(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 16, 8, value)
#define ACT_SCHEDULE_REQ_GET_PRIMART_CH_IDX(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 24, 9)
#define ACT_SCHEDULE_REQ_SET_PRIMART_CH_IDX(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 24, 9, value)
#define NAN_CTRL_GET_NAN_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 2)
#define NAN_CTRL_SET_NAN_EN(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 2, value)
@@ -738,4 +806,47 @@
LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 16, 16)
#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 16, 16, value)
#define NAN_FUNC_CTRL_GET_PORT_IDX(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
#define NAN_FUNC_CTRL_SET_PORT_IDX(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
#define NAN_FUNC_CTRL_GET_MAC_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
#define NAN_FUNC_CTRL_SET_MAC_ID(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
#define NAN_FUNC_CTRL_GET_MASTER_PREF(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
#define NAN_FUNC_CTRL_SET_MASTER_PREF(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
#define NAN_FUNC_CTRL_GET_RANDOM_FACTOR(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
#define NAN_FUNC_CTRL_SET_RANDOM_FACTOR(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
#define NAN_FUNC_CTRL_GET_OP_CH_24G(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
#define NAN_FUNC_CTRL_SET_OP_CH_24G(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
#define NAN_FUNC_CTRL_GET_OP_CH_5G(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 8)
#define NAN_FUNC_CTRL_SET_OP_CH_5G(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 8, value)
#define NAN_FUNC_CTRL_GET_OPTIONS(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 16)
#define NAN_FUNC_CTRL_SET_OPTIONS(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 16, value)
#define NAN_FUNC_CTRL_GET_SYNC_BCN_RSVD_OFFSET(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8)
#define NAN_FUNC_CTRL_SET_SYNC_BCN_RSVD_OFFSET(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value)
#define NAN_FUNC_CTRL_GET_DISC_BCN_RSVD_OFFSET(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8)
#define NAN_FUNC_CTRL_SET_DISC_BCN_RSVD_OFFSET(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value)
#define NAN_FUNC_CTRL_GET_DW_SCHDL_PRIORITY(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 16, 8)
#define NAN_FUNC_CTRL_SET_DW_SCHDL_PRIORITY(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 16, 8, value)
#define NAN_FUNC_CTRL_GET_TIME_INDICATE_PERIOD(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 24, 8)
#define NAN_FUNC_CTRL_SET_TIME_INDICATE_PERIOD(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 24, 8, value)
#endif

9
hal/halmac/halmac_gpio_cmd.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -88,6 +88,13 @@
#define HALMAC_BT_LNAON_SEL 42
#define HALMAC_WLBT_LNAON_SEL 43
#define HALMAC_SWR_CTRL_EN 44
#define HALMAC_UART_BRIDGE 45
#define HALMAC_BT_I2C 46
#define HALMAC_BTCOEX_CMD 47
#define HALMAC_BT_UART_INTF 48
#define HALMAC_DATA_CPU_JTAG 49
#define HALMAC_DATA_CPU_SFLASH 50
#define HALMAC_DATA_CPU_UART 51
struct halmac_gpio_pimux_list {
u16 func;

18
hal/halmac/halmac_h2c_extra_info_ap.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -15,6 +15,22 @@
#ifndef _HAL_H2CEXTRAINFO_H2C_C2H_AP_H_
#define _HAL_H2CEXTRAINFO_H2C_C2H_AP_H_
/* H2C extra info (rsvd page) usage, unit : page (128byte)*/
/* dlfw : not include txdesc size*/
/* update pkt : not include txdesc size*/
/* cfg param : not include txdesc size*/
/* scan info : not include txdesc size*/
/* dl flash : not include txdesc size*/
#define DLFW_RSVDPG_SIZE 2048
#define UPDATE_PKT_RSVDPG_SIZE 2048
#define CFG_PARAM_RSVDPG_SIZE 2048
#define SCAN_INFO_RSVDPG_SIZE 256
#define DL_FLASH_RSVDPG_SIZE 2048
/* su0 snding pkt : include txdesc size */
#define SU0_SNDING_PKT_OFFSET 0
#define SU0_SNDING_PKT_RSVDPG_SIZE 128
#define PARAM_INFO_GET_LEN(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 8)
#define PARAM_INFO_SET_LEN(extra_info, value) \
SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 8, value)

2
hal/halmac/halmac_h2c_extra_info_nic.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

11
hal/halmac/halmac_hw_cfg.h
View File

@@ -150,11 +150,6 @@
#define HALMAC_8197G_SUPPORT 0
#endif
#ifdef CONFIG_RTL8812F
#define HALMAC_8812F_SUPPORT 1
#else
#define HALMAC_8812F_SUPPORT 0
#endif
/* Halmac support IC version */
@@ -183,6 +178,12 @@
#define HALMAC_8822C_SUPPORT 0
#endif
#ifdef CONFIG_RTL8812F
#define HALMAC_8812F_SUPPORT 1
#else
#define HALMAC_8812F_SUPPORT 0
#endif
/* Interface support */
#ifdef CONFIG_SDIO_HCI

6
hal/halmac/halmac_intf_phy_cmd.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -39,7 +39,9 @@ enum halmac_ip_sel {
/* Platform mask */
enum halmac_intf_phy_platform {
HALMAC_INTF_PHY_PLATFORM_ALL = 0x7FFF,
HALMAC_INTF_PHY_PLATFORM_ALL = BIT(0),
HALMAC_INTF_PHY_PLATFORM_ASUS = BIT(1),
HALMAC_INTF_PHY_PLATFORM_FOR_ALL = 0x7FFF,
};
#endif

37
hal/halmac/halmac_original_c2h_ap.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -28,6 +28,7 @@
#define CMD_ID_C2H_CUR_CHANNEL 0X10
#define CMD_ID_C2H_GPIO_WAKEUP 0X14
#define CMD_ID_C2H_DROPID_RPT 0X2D
#define CMD_ID_C2H_LPS_STATUS_RPT 0X32
#define C2H_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
#define C2H_SET_CMD_ID(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
@@ -647,4 +648,38 @@
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
#define C2H_DROPID_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
#define C2H_LPS_STATUS_RPT_GET_CMD_ID(c2h_pkt) \
GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
#define C2H_LPS_STATUS_RPT_SET_CMD_ID(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
#define C2H_LPS_STATUS_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
#define C2H_LPS_STATUS_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
#define C2H_LPS_STATUS_RPT_SET_SEQ(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
#define C2H_LPS_STATUS_RPT_SET_SEQ_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
#define C2H_LPS_STATUS_RPT_GET_ACTION(c2h_pkt) \
GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
#define C2H_LPS_STATUS_RPT_SET_ACTION(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
#define C2H_LPS_STATUS_RPT_SET_ACTION_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
#define C2H_LPS_STATUS_RPT_GET_STATUSCODE(c2h_pkt) \
GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
#define C2H_LPS_STATUS_RPT_SET_STATUSCODE(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
#define C2H_LPS_STATUS_RPT_SET_STATUSCODE_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
#define C2H_LPS_STATUS_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
#define C2H_LPS_STATUS_RPT_SET_LEN(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
#define C2H_LPS_STATUS_RPT_SET_LEN_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
#define C2H_LPS_STATUS_RPT_GET_TRIGGER(c2h_pkt) \
GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
#define C2H_LPS_STATUS_RPT_SET_TRIGGER(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
#define C2H_LPS_STATUS_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
#endif

27
hal/halmac/halmac_original_c2h_nic.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -28,6 +28,7 @@
#define CMD_ID_C2H_CUR_CHANNEL 0X10
#define CMD_ID_C2H_GPIO_WAKEUP 0X14
#define CMD_ID_C2H_DROPID_RPT 0X2D
#define CMD_ID_C2H_LPS_STATUS_RPT 0X32
#define C2H_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
#define C2H_SET_CMD_ID(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
@@ -431,4 +432,28 @@
LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
#define C2H_DROPID_RPT_SET_TRIGGER(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
#define C2H_LPS_STATUS_RPT_GET_CMD_ID(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
#define C2H_LPS_STATUS_RPT_SET_CMD_ID(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
#define C2H_LPS_STATUS_RPT_GET_SEQ(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
#define C2H_LPS_STATUS_RPT_SET_SEQ(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
#define C2H_LPS_STATUS_RPT_GET_ACTION(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
#define C2H_LPS_STATUS_RPT_SET_ACTION(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
#define C2H_LPS_STATUS_RPT_GET_STATUSCODE(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
#define C2H_LPS_STATUS_RPT_SET_STATUSCODE(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
#define C2H_LPS_STATUS_RPT_GET_LEN(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
#define C2H_LPS_STATUS_RPT_SET_LEN(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
#define C2H_LPS_STATUS_RPT_GET_TRIGGER(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
#define C2H_LPS_STATUS_RPT_SET_TRIGGER(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
#endif

32
hal/halmac/halmac_original_h2c_ap.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -43,6 +43,7 @@
#define CMD_ID_IQK_OFFLOAD 0X05
#define CMD_ID_MACID_CFG_3SS 0X06
#define CMD_ID_RA_PARA_ADJUST 0X07
#define CMD_ID_REQ_TXRPT_ACQ 0X12
#define CMD_ID_WWLAN 0X00
#define CMD_ID_REMOTE_WAKE_CTRL 0X01
#define CMD_ID_AOAC_GLOBAL_INFO 0X02
@@ -80,6 +81,7 @@
#define CLASS_IQK_OFFLOAD 0X2
#define CLASS_MACID_CFG_3SS 0X2
#define CLASS_RA_PARA_ADJUST 0X02
#define CLASS_REQ_TXRPT_ACQ 0X02
#define CLASS_WWLAN 0X4
#define CLASS_REMOTE_WAKE_CTRL 0X4
#define CLASS_AOAC_GLOBAL_INFO 0X04
@@ -1221,6 +1223,28 @@
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)
#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)
#define REQ_TXRPT_ACQ_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
#define REQ_TXRPT_ACQ_SET_CMD_ID(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
#define REQ_TXRPT_ACQ_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
#define REQ_TXRPT_ACQ_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
#define REQ_TXRPT_ACQ_SET_CLASS(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
#define REQ_TXRPT_ACQ_SET_CLASS_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
#define REQ_TXRPT_ACQ_GET_STA1_MACID(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
#define REQ_TXRPT_ACQ_SET_STA1_MACID(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
#define REQ_TXRPT_ACQ_SET_STA1_MACID_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
#define REQ_TXRPT_ACQ_GET_PASS_DROP_SEL(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
#define REQ_TXRPT_ACQ_SET_PASS_DROP_SEL(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
#define REQ_TXRPT_ACQ_SET_PASS_DROP_SEL_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
#define WWLAN_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
#define WWLAN_SET_CMD_ID(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
@@ -1394,6 +1418,12 @@
SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 1, value)
#define REMOTE_WAKE_CTRL_SET_ARP_ACTION_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 1, value)
#define REMOTE_WAKE_CTRL_GET_TIM_PARSER_EN(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X00, 26, 1)
#define REMOTE_WAKE_CTRL_SET_TIM_PARSER_EN(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 26, 1, value)
#define REMOTE_WAKE_CTRL_SET_TIM_PARSER_EN_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 26, 1, value)
#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X00, 28, 1)
#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt, value) \

22
hal/halmac/halmac_original_h2c_nic.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -43,6 +43,7 @@
#define CMD_ID_IQK_OFFLOAD 0X05
#define CMD_ID_MACID_CFG_3SS 0X06
#define CMD_ID_RA_PARA_ADJUST 0X07
#define CMD_ID_REQ_TXRPT_ACQ 0X12
#define CMD_ID_WWLAN 0X00
#define CMD_ID_REMOTE_WAKE_CTRL 0X01
#define CMD_ID_AOAC_GLOBAL_INFO 0X02
@@ -80,6 +81,7 @@
#define CLASS_IQK_OFFLOAD 0X2
#define CLASS_MACID_CFG_3SS 0X2
#define CLASS_RA_PARA_ADJUST 0X02
#define CLASS_REQ_TXRPT_ACQ 0X02
#define CLASS_WWLAN 0X4
#define CLASS_REMOTE_WAKE_CTRL 0X4
#define CLASS_AOAC_GLOBAL_INFO 0X04
@@ -845,6 +847,20 @@
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)
#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)
#define REQ_TXRPT_ACQ_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
#define REQ_TXRPT_ACQ_SET_CMD_ID(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
#define REQ_TXRPT_ACQ_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
#define REQ_TXRPT_ACQ_SET_CLASS(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
#define REQ_TXRPT_ACQ_GET_STA1_MACID(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
#define REQ_TXRPT_ACQ_SET_STA1_MACID(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
#define REQ_TXRPT_ACQ_GET_PASS_DROP_SEL(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
#define REQ_TXRPT_ACQ_SET_PASS_DROP_SEL(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
#define WWLAN_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
#define WWLAN_SET_CMD_ID(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
@@ -961,6 +977,10 @@
LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 1)
#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 1, value)
#define REMOTE_WAKE_CTRL_GET_TIM_PARSER_EN(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 26, 1)
#define REMOTE_WAKE_CTRL_SET_TIM_PARSER_EN(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 26, 1, value)
#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 28, 1)
#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt, value) \

2
hal/halmac/halmac_pcie_reg.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
hal/halmac/halmac_pwr_seq_cmd.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

25
hal/halmac/halmac_reg2.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -95,6 +95,21 @@
HALMAC_8881A_SUPPORT)
#define REG_SYS_SWR_CTRL1 0x0010
#endif
#if (HALMAC_8812F_SUPPORT)
#define REG_SDIO_CTRL_2 0x10250010
#endif
#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8197G_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \
HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8881A_SUPPORT)
#define REG_SYS_SWR_CTRL2 0x0014
#endif
@@ -6132,7 +6147,7 @@
#if (HALMAC_8822C_SUPPORT)
#define REG_XTAL_AAC_OUTPUT 0x1060
#define REG_XTAL_AAC_OUTPUT 0x1060
#endif
@@ -8012,6 +8027,12 @@
#endif
#if (HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
#define REG_RXAI_CTRL 0x1668
#endif
#if (HALMAC_8814B_SUPPORT)
#define REG_FWPHYFF_RCR 0x1668

2
hal/halmac/halmac_reg_8197f.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

886
hal/halmac/halmac_reg_8812f.h Normal file
View File

@@ -0,0 +1,886 @@
/******************************************************************************
*
* Copyright(c) 2018 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef __INC_HALMAC_REG_8812F_H
#define __INC_HALMAC_REG_8812F_H
#define REG_SYS_ISO_CTRL_8812F 0x0000
#define REG_SYS_FUNC_EN_8812F 0x0002
#define REG_SYS_PW_CTRL_8812F 0x0004
#define REG_SYS_CLK_CTRL_8812F 0x0008
#define REG_SYS_EEPROM_CTRL_8812F 0x000A
#define REG_EE_VPD_8812F 0x000C
#define REG_SYS_SWR_CTRL1_8812F 0x0010
#define REG_SYS_SWR_CTRL2_8812F 0x0014
#define REG_SYS_SWR_CTRL3_8812F 0x0018
#define REG_RSV_CTRL_8812F 0x001C
#define REG_RF_CTRL_8812F 0x001F
#define REG_AFE_LDO_CTRL_8812F 0x0020
#define REG_AFE_CTRL1_8812F 0x0024
#define REG_ANAPARSW_POW_MAC_8812F 0x0028
#define REG_ANAPARLDO_POW_MAC_8812F 0x0029
#define REG_ANAPAR_POW_MAC_8812F 0x002A
#define REG_ANAPAR_POW_XTAL_8812F 0x002B
#define REG_ANAPARLDO_MAC_8812F 0x002C
#define REG_EFUSE_CTRL_8812F 0x0030
#define REG_LDO_EFUSE_CTRL_8812F 0x0034
#define REG_PWR_OPTION_CTRL_8812F 0x0038
#define REG_CAL_TIMER_8812F 0x003C
#define REG_ACLK_MON_8812F 0x003E
#define REG_GPIO_MUXCFG_2_8812F 0x003F
#define REG_GPIO_MUXCFG_8812F 0x0040
#define REG_GPIO_PIN_CTRL_8812F 0x0044
#define REG_GPIO_INTM_8812F 0x0048
#define REG_LED_CFG_8812F 0x004C
#define REG_FSIMR_8812F 0x0050
#define REG_FSISR_8812F 0x0054
#define REG_HSIMR_8812F 0x0058
#define REG_HSISR_8812F 0x005C
#define REG_GPIO_EXT_CTRL_8812F 0x0060
#define REG_PAD_CTRL1_8812F 0x0064
#define REG_WL_BT_PWR_CTRL_8812F 0x0068
#define REG_SDM_DEBUG_8812F 0x006C
#define REG_SYS_SDIO_CTRL_8812F 0x0070
#define REG_HCI_OPT_CTRL_8812F 0x0074
#define REG_HCI_BG_CTRL_8812F 0x0078
#define REG_HCI_LDO_CTRL_8812F 0x007A
#define REG_LDO_SWR_CTRL_8812F 0x007C
#define REG_MCUFW_CTRL_8812F 0x0080
#define REG_MCU_TST_CFG_8812F 0x0084
#define REG_HMEBOX_E0_E1_8812F 0x0088
#define REG_HMEBOX_E2_E3_8812F 0x008C
#define REG_WLLPS_CTRL_8812F 0x0090
#define REG_GPIO_DEBOUNCE_CTRL_8812F 0x0098
#define REG_RPWM2_8812F 0x009C
#define REG_SYSON_FSM_MON_8812F 0x00A0
#define REG_PMC_DBG_CTRL1_8812F 0x00A8
#define REG_HIMR0_8812F 0x00B0
#define REG_HISR0_8812F 0x00B4
#define REG_HIMR1_8812F 0x00B8
#define REG_HISR1_8812F 0x00BC
#define REG_DBG_PORT_SEL_8812F 0x00C0
#define REG_PAD_CTRL2_8812F 0x00C4
#define REG_PMC_DBG_CTRL2_8812F 0x00CC
#define REG_BIST_CTRL_8812F 0x00D0
#define REG_BIST_RPT_8812F 0x00D4
#define REG_MEM_CTRL_8812F 0x00D8
#define REG_USB_SIE_INTF_8812F 0x00E0
#define REG_PCIE_MIO_INTF_8812F 0x00E4
#define REG_PCIE_MIO_INTD_8812F 0x00E8
#define REG_WLRF1_8812F 0x00EC
#define REG_SYS_CFG1_8812F 0x00F0
#define REG_SYS_STATUS1_8812F 0x00F4
#define REG_SYS_STATUS2_8812F 0x00F8
#define REG_SYS_CFG2_8812F 0x00FC
#define REG_SYS_CFG3_8812F 0x1000
#define REG_ANAPARSW_MAC_0_8812F 0x1010
#define REG_ANAPARSW_MAC_1_8812F 0x1014
#define REG_ANAPAR_MAC_0_8812F 0x1018
#define REG_ANAPAR_MAC_1_8812F 0x101C
#define REG_ANAPAR_MAC_2_8812F 0x1020
#define REG_ANAPAR_XTAL_0_8812F 0x1040
#define REG_ANAPAR_XTAL_1_8812F 0x1044
#define REG_ANAPAR_XTAL_2_8812F 0x1048
#define REG_ANAPAR_XTAL_3_8812F 0x104C
#define REG_ANAPAR_XTAL_AACK_0_8812F 0x1054
#define REG_ANAPAR_XTAL_AACK_1_8812F 0x1058
#define REG_ANAPAR_XTAL_MODE_DECODER_8812F 0x1064
#define REG_SYS_CFG5_8812F 0x1070
#define REG_REGU_32K_1_8812F 0x1078
#define REG_REGU_32K_2_8812F 0x107C
#define REG_CPU_DMEM_CON_8812F 0x1080
#define REG_BOOT_REASON_8812F 0x1088
#define REG_HIMR2_8812F 0x10B0
#define REG_HISR2_8812F 0x10B4
#define REG_HIMR3_8812F 0x10B8
#define REG_HISR3_8812F 0x10BC
#define REG_SW_MDIO_8812F 0x10C0
#define REG_H2C_PKT_READADDR_8812F 0x10D0
#define REG_H2C_PKT_WRITEADDR_8812F 0x10D4
#define REG_MEM_PWR_CRTL_8812F 0x10D8
#define REG_FW_DBG6_8812F 0x10F8
#define REG_FW_DBG7_8812F 0x10FC
#define REG_CR_8812F 0x0100
#define REG_PG_SIZE_8812F 0x0104
#define REG_PKT_BUFF_ACCESS_CTRL_8812F 0x0106
#define REG_TSF_CLK_STATE_8812F 0x0108
#define REG_TXDMA_PQ_MAP_8812F 0x010C
#define REG_TRXFF_BNDY_8812F 0x0114
#define REG_PTA_I2C_MBOX_8812F 0x0118
#define REG_RXFF_BNDY_8812F 0x011C
#define REG_FE1IMR_8812F 0x0120
#define REG_FE1ISR_8812F 0x0124
#define REG_CPWM_8812F 0x012C
#define REG_FWIMR_8812F 0x0130
#define REG_FWISR_8812F 0x0134
#define REG_FTIMR_8812F 0x0138
#define REG_FTISR_8812F 0x013C
#define REG_PKTBUF_DBG_CTRL_8812F 0x0140
#define REG_PKTBUF_DBG_DATA_L_8812F 0x0144
#define REG_PKTBUF_DBG_DATA_H_8812F 0x0148
#define REG_CPWM2_8812F 0x014C
#define REG_TC0_CTRL_8812F 0x0150
#define REG_TC1_CTRL_8812F 0x0154
#define REG_TC2_CTRL_8812F 0x0158
#define REG_TC3_CTRL_8812F 0x015C
#define REG_TC4_CTRL_8812F 0x0160
#define REG_TCUNIT_BASE_8812F 0x0164
#define REG_TC5_CTRL_8812F 0x0168
#define REG_TC6_CTRL_8812F 0x016C
#define REG_MBIST_DRF_FAIL_8812F 0x0170
#define REG_MBIST_START_PAUSE_8812F 0x0174
#define REG_MBIST_DONE_8812F 0x0178
#define REG_MBIST_READ_BIST_RPT_8812F 0x017C
#define REG_AES_DECRPT_DATA_8812F 0x0180
#define REG_AES_DECRPT_CFG_8812F 0x0184
#define REG_HIOE_CTRL_8812F 0x0188
#define REG_HIOE_CFG_FILE_8812F 0x018C
#define REG_TMETER_8812F 0x0190
#define REG_OSC_32K_CTRL_8812F 0x0194
#define REG_32K_CAL_REG1_8812F 0x0198
#define REG_C2HEVT_8812F 0x01A0
#define REG_C2HEVT_1_8812F 0x01A4
#define REG_C2HEVT_2_8812F 0x01A8
#define REG_C2HEVT_3_8812F 0x01AC
#define REG_SW_DEFINED_PAGE1_8812F 0x01B8
#define REG_SW_DEFINED_PAGE2_8812F 0x01BC
#define REG_MCUTST_I_8812F 0x01C0
#define REG_MCUTST_II_8812F 0x01C4
#define REG_FMETHR_8812F 0x01C8
#define REG_HMETFR_8812F 0x01CC
#define REG_HMEBOX0_8812F 0x01D0
#define REG_HMEBOX1_8812F 0x01D4
#define REG_HMEBOX2_8812F 0x01D8
#define REG_HMEBOX3_8812F 0x01DC
#define REG_BB_ACCESS_CTRL_8812F 0x01E8
#define REG_BB_ACCESS_DATA_8812F 0x01EC
#define REG_HMEBOX_E0_8812F 0x01F0
#define REG_HMEBOX_E1_8812F 0x01F4
#define REG_HMEBOX_E2_8812F 0x01F8
#define REG_HMEBOX_E3_8812F 0x01FC
#define REG_CR_EXT_8812F 0x1100
#define REG_FWFF_8812F 0x1114
#define REG_RXFF_PTR_V1_8812F 0x1118
#define REG_RXFF_WTR_V1_8812F 0x111C
#define REG_FE2IMR_8812F 0x1120
#define REG_FE2ISR_8812F 0x1124
#define REG_FE3IMR_8812F 0x1128
#define REG_FE3ISR_8812F 0x112C
#define REG_FE4IMR_8812F 0x1130
#define REG_FE4ISR_8812F 0x1134
#define REG_FT1IMR_8812F 0x1138
#define REG_FT1ISR_8812F 0x113C
#define REG_SPWR0_8812F 0x1140
#define REG_SPWR1_8812F 0x1144
#define REG_SPWR2_8812F 0x1148
#define REG_SPWR3_8812F 0x114C
#define REG_POWSEQ_8812F 0x1150
#define REG_TC7_CTRL_V1_8812F 0x1158
#define REG_TC8_CTRL_V1_8812F 0x115C
#define REG_RX_BCN_TBTT_ITVL0_8812F 0x1160
#define REG_RX_BCN_TBTT_ITVL1_8812F 0x1164
#define REG_IO_WRAP_ERR_FLAG_8812F 0x1170
#define REG_SPEED_SENSOR_8812F 0x1180
#define REG_SPEED_SENSOR1_8812F 0x1184
#define REG_SPEED_SENSOR2_8812F 0x1188
#define REG_SPEED_SENSOR3_8812F 0x118C
#define REG_SPEED_SENSOR4_8812F 0x1190
#define REG_SPEED_SENSOR5_8812F 0x1194
#define REG_COUNTER_CTRL_8812F 0x11C4
#define REG_COUNTER_THRESHOLD_8812F 0x11C8
#define REG_COUNTER_SET_8812F 0x11CC
#define REG_COUNTER_OVERFLOW_8812F 0x11D0
#define REG_TXDMA_LEN_THRESHOLD_8812F 0x11D4
#define REG_RXDMA_LEN_THRESHOLD_8812F 0x11D8
#define REG_PCIE_EXEC_TIME_THRESHOLD_8812F 0x11DC
#define REG_FT2IMR_8812F 0x11E0
#define REG_FT2ISR_8812F 0x11E4
#define REG_MSG2_8812F 0x11F0
#define REG_MSG3_8812F 0x11F4
#define REG_MSG4_8812F 0x11F8
#define REG_MSG5_8812F 0x11FC
#define REG_FIFOPAGE_CTRL_1_8812F 0x0200
#define REG_FIFOPAGE_CTRL_2_8812F 0x0204
#define REG_AUTO_LLT_V1_8812F 0x0208
#define REG_TXDMA_OFFSET_CHK_8812F 0x020C
#define REG_TXDMA_STATUS_8812F 0x0210
#define REG_TX_DMA_DBG_8812F 0x0214
#define REG_TQPNT1_8812F 0x0218
#define REG_TQPNT2_8812F 0x021C
#define REG_TQPNT3_8812F 0x0220
#define REG_TQPNT4_8812F 0x0224
#define REG_RQPN_CTRL_1_8812F 0x0228
#define REG_RQPN_CTRL_2_8812F 0x022C
#define REG_FIFOPAGE_INFO_1_8812F 0x0230
#define REG_FIFOPAGE_INFO_2_8812F 0x0234
#define REG_FIFOPAGE_INFO_3_8812F 0x0238
#define REG_FIFOPAGE_INFO_4_8812F 0x023C
#define REG_FIFOPAGE_INFO_5_8812F 0x0240
#define REG_H2C_HEAD_8812F 0x0244
#define REG_H2C_TAIL_8812F 0x0248
#define REG_H2C_READ_ADDR_8812F 0x024C
#define REG_H2C_WR_ADDR_8812F 0x0250
#define REG_H2C_INFO_8812F 0x0254
#define REG_PGSUB_CNT_8812F 0x026C
#define REG_PGSUB_H_8812F 0x0270
#define REG_PGSUB_N_8812F 0x0274
#define REG_PGSUB_L_8812F 0x0278
#define REG_PGSUB_E_8812F 0x027C
#define REG_RXDMA_AGG_PG_TH_8812F 0x0280
#define REG_RXPKT_NUM_8812F 0x0284
#define REG_RXDMA_STATUS_8812F 0x0288
#define REG_RXDMA_DPR_8812F 0x028C
#define REG_RXDMA_MODE_8812F 0x0290
#define REG_C2H_PKT_8812F 0x0294
#define REG_FWFF_C2H_8812F 0x0298
#define REG_FWFF_CTRL_8812F 0x029C
#define REG_FWFF_PKT_INFO_8812F 0x02A0
#define REG_RXPKTNUM_8812F 0x02B0
#define REG_RXPKTNUM_TH_8812F 0x02B4
#define REG_FW_MSG1_8812F 0x02E0
#define REG_FW_MSG2_8812F 0x02E4
#define REG_FW_MSG3_8812F 0x02E8
#define REG_FW_MSG4_8812F 0x02EC
#define REG_DDMA_CH0SA_8812F 0x1200
#define REG_DDMA_CH0DA_8812F 0x1204
#define REG_DDMA_CH0CTRL_8812F 0x1208
#define REG_DDMA_CH1SA_8812F 0x1210
#define REG_DDMA_CH1DA_8812F 0x1214
#define REG_DDMA_CH1CTRL_8812F 0x1218
#define REG_DDMA_CH2SA_8812F 0x1220
#define REG_DDMA_CH2DA_8812F 0x1224
#define REG_DDMA_CH2CTRL_8812F 0x1228
#define REG_DDMA_CH3SA_8812F 0x1230
#define REG_DDMA_CH3DA_8812F 0x1234
#define REG_DDMA_CH3CTRL_8812F 0x1238
#define REG_DDMA_CH4SA_8812F 0x1240
#define REG_DDMA_CH4DA_8812F 0x1244
#define REG_DDMA_CH4CTRL_8812F 0x1248
#define REG_DDMA_CH5SA_8812F 0x1250
#define REG_DDMA_CH5DA_8812F 0x1254
#define REG_DDMA_CH5CTRL_8812F 0x1258
#define REG_DDMA_INT_MSK_8812F 0x12E0
#define REG_DDMA_CHSTATUS_8812F 0x12E8
#define REG_DDMA_CHKSUM_8812F 0x12F0
#define REG_DDMA_MONITOR_8812F 0x12FC
#define REG_PCIE_CTRL_8812F 0x0300
#define REG_INT_MIG_8812F 0x0304
#define REG_BCNQ_TXBD_DESA_8812F 0x0308
#define REG_MGQ_TXBD_DESA_8812F 0x0310
#define REG_VOQ_TXBD_DESA_8812F 0x0318
#define REG_VIQ_TXBD_DESA_8812F 0x0320
#define REG_BEQ_TXBD_DESA_8812F 0x0328
#define REG_BKQ_TXBD_DESA_8812F 0x0330
#define REG_RXQ_RXBD_DESA_8812F 0x0338
#define REG_HI0Q_TXBD_DESA_8812F 0x0340
#define REG_HI1Q_TXBD_DESA_8812F 0x0348
#define REG_HI2Q_TXBD_DESA_8812F 0x0350
#define REG_HI3Q_TXBD_DESA_8812F 0x0358
#define REG_HI4Q_TXBD_DESA_8812F 0x0360
#define REG_HI5Q_TXBD_DESA_8812F 0x0368
#define REG_HI6Q_TXBD_DESA_8812F 0x0370
#define REG_HI7Q_TXBD_DESA_8812F 0x0378
#define REG_MGQ_TXBD_NUM_8812F 0x0380
#define REG_RX_RXBD_NUM_8812F 0x0382
#define REG_VOQ_TXBD_NUM_8812F 0x0384
#define REG_VIQ_TXBD_NUM_8812F 0x0386
#define REG_BEQ_TXBD_NUM_8812F 0x0388
#define REG_BKQ_TXBD_NUM_8812F 0x038A
#define REG_HI0Q_TXBD_NUM_8812F 0x038C
#define REG_HI1Q_TXBD_NUM_8812F 0x038E
#define REG_HI2Q_TXBD_NUM_8812F 0x0390
#define REG_HI3Q_TXBD_NUM_8812F 0x0392
#define REG_HI4Q_TXBD_NUM_8812F 0x0394
#define REG_HI5Q_TXBD_NUM_8812F 0x0396
#define REG_HI6Q_TXBD_NUM_8812F 0x0398
#define REG_HI7Q_TXBD_NUM_8812F 0x039A
#define REG_TSFTIMER_HCI_8812F 0x039C
#define REG_BD_RWPTR_CLR_8812F 0x039C
#define REG_VOQ_TXBD_IDX_8812F 0x03A0
#define REG_VIQ_TXBD_IDX_8812F 0x03A4
#define REG_BEQ_TXBD_IDX_8812F 0x03A8
#define REG_BKQ_TXBD_IDX_8812F 0x03AC
#define REG_MGQ_TXBD_IDX_8812F 0x03B0
#define REG_RXQ_RXBD_IDX_8812F 0x03B4
#define REG_HI0Q_TXBD_IDX_8812F 0x03B8
#define REG_HI1Q_TXBD_IDX_8812F 0x03BC
#define REG_HI2Q_TXBD_IDX_8812F 0x03C0
#define REG_HI3Q_TXBD_IDX_8812F 0x03C4
#define REG_HI4Q_TXBD_IDX_8812F 0x03C8
#define REG_HI5Q_TXBD_IDX_8812F 0x03CC
#define REG_HI6Q_TXBD_IDX_8812F 0x03D0
#define REG_HI7Q_TXBD_IDX_8812F 0x03D4
#define REG_DBG_SEL_V1_8812F 0x03D8
#define REG_PCIE_HRPWM1_V1_8812F 0x03D9
#define REG_PCIE_HCPWM1_V1_8812F 0x03DA
#define REG_PCIE_CTRL2_8812F 0x03DB
#define REG_PCIE_HRPWM2_V1_8812F 0x03DC
#define REG_PCIE_HCPWM2_V1_8812F 0x03DE
#define REG_PCIE_H2C_MSG_V1_8812F 0x03E0
#define REG_PCIE_C2H_MSG_V1_8812F 0x03E4
#define REG_DBI_WDATA_V1_8812F 0x03E8
#define REG_DBI_RDATA_V1_8812F 0x03EC
#define REG_DBI_FLAG_V1_8812F 0x03F0
#define REG_MDIO_V1_8812F 0x03F4
#define REG_PCIE_MIX_CFG_8812F 0x03F8
#define REG_HCI_MIX_CFG_8812F 0x03FC
#define REG_STC_INT_CS_8812F 0x1300
#define REG_ST_INT_CFG_8812F 0x1304
#define REG_H2CQ_TXBD_DESA_8812F 0x1320
#define REG_H2CQ_TXBD_NUM_8812F 0x1328
#define REG_H2CQ_TXBD_IDX_8812F 0x132C
#define REG_H2CQ_CSR_8812F 0x1330
#define REG_CHANGE_PCIE_SPEED_8812F 0x1350
#define REG_DEBUG_STATE1_8812F 0x1354
#define REG_DEBUG_STATE2_8812F 0x1358
#define REG_DEBUG_STATE3_8812F 0x135C
#define REG_CHNL_DMA_CFG_V1_8812F 0x137C
#define REG_PCIE_HISR0_V1_8812F 0x13B4
#define REG_PCIE_HISR1_V1_8812F 0x13BC
#define REG_PCIE_HISR2_V1_8812F 0x23B4
#define REG_PCIE_HISR3_V1_8812F 0x23BC
#define REG_Q0_INFO_8812F 0x0400
#define REG_Q1_INFO_8812F 0x0404
#define REG_Q2_INFO_8812F 0x0408
#define REG_Q3_INFO_8812F 0x040C
#define REG_MGQ_INFO_8812F 0x0410
#define REG_HIQ_INFO_8812F 0x0414
#define REG_BCNQ_INFO_8812F 0x0418
#define REG_TXPKT_EMPTY_8812F 0x041A
#define REG_CPU_MGQ_INFO_8812F 0x041C
#define REG_FWHW_TXQ_CTRL_8812F 0x0420
#define REG_DATAFB_SEL_8812F 0x0423
#define REG_BCNQ_BDNY_V1_8812F 0x0424
#define REG_LIFETIME_EN_8812F 0x0426
#define REG_SPEC_SIFS_8812F 0x0428
#define REG_RETRY_LIMIT_8812F 0x042A
#define REG_TXBF_CTRL_8812F 0x042C
#define REG_DARFRC_8812F 0x0430
#define REG_DARFRCH_8812F 0x0434
#define REG_RARFRC_8812F 0x0438
#define REG_RARFRCH_8812F 0x043C
#define REG_RRSR_8812F 0x0440
#define REG_ARFR0_8812F 0x0444
#define REG_ARFRH0_8812F 0x0448
#define REG_ARFR1_V1_8812F 0x044C
#define REG_ARFRH1_V1_8812F 0x0450
#define REG_CCK_CHECK_8812F 0x0454
#define REG_AMPDU_MAX_TIME_V1_8812F 0x0455
#define REG_BCNQ1_BDNY_V1_8812F 0x0456
#define REG_AMPDU_MAX_LENGTH_HT_8812F 0x0458
#define REG_ACQ_STOP_8812F 0x045C
#define REG_NDPA_RATE_8812F 0x045D
#define REG_TX_HANG_CTRL_8812F 0x045E
#define REG_NDPA_OPT_CTRL_8812F 0x045F
#define REG_AMPDU_MAX_LENGTH_VHT_8812F 0x0460
#define REG_RD_RESP_PKT_TH_8812F 0x0463
#define REG_CMDQ_INFO_8812F 0x0464
#define REG_Q4_INFO_8812F 0x0468
#define REG_Q5_INFO_8812F 0x046C
#define REG_Q6_INFO_8812F 0x0470
#define REG_Q7_INFO_8812F 0x0474
#define REG_WMAC_LBK_BUF_HD_V1_8812F 0x0478
#define REG_MGQ_BDNY_V1_8812F 0x047A
#define REG_TXRPT_CTRL_8812F 0x047C
#define REG_INIRTS_RATE_SEL_8812F 0x0480
#define REG_BASIC_CFEND_RATE_8812F 0x0481
#define REG_STBC_CFEND_RATE_8812F 0x0482
#define REG_DATA_SC_8812F 0x0483
#define REG_MACID_SLEEP3_8812F 0x0484
#define REG_MACID_SLEEP1_8812F 0x0488
#define REG_ARFR2_V1_8812F 0x048C
#define REG_ARFRH2_V1_8812F 0x0490
#define REG_ARFR3_V1_8812F 0x0494
#define REG_ARFRH3_V1_8812F 0x0498
#define REG_ARFR4_8812F 0x049C
#define REG_ARFRH4_8812F 0x04A0
#define REG_ARFR5_8812F 0x04A4
#define REG_ARFRH5_8812F 0x04A8
#define REG_TXRPT_START_OFFSET_8812F 0x04AC
#define REG_RRSR_CTS_8812F 0x04B0
#define REG_POWER_STAGE1_8812F 0x04B4
#define REG_POWER_STAGE2_8812F 0x04B8
#define REG_SW_AMPDU_BURST_MODE_CTRL_8812F 0x04BC
#define REG_PKT_LIFE_TIME_8812F 0x04C0
#define REG_STBC_SETTING_8812F 0x04C4
#define REG_STBC_SETTING2_8812F 0x04C5
#define REG_QUEUE_CTRL_8812F 0x04C6
#define REG_SINGLE_AMPDU_CTRL_8812F 0x04C7
#define REG_PROT_MODE_CTRL_8812F 0x04C8
#define REG_BAR_MODE_CTRL_8812F 0x04CC
#define REG_RA_TRY_RATE_AGG_LMT_8812F 0x04CF
#define REG_MACID_SLEEP2_8812F 0x04D0
#define REG_MACID_SLEEP_8812F 0x04D4
#define REG_HW_SEQ0_8812F 0x04D8
#define REG_HW_SEQ1_8812F 0x04DA
#define REG_HW_SEQ2_8812F 0x04DC
#define REG_HW_SEQ3_8812F 0x04DE
#define REG_NULL_PKT_STATUS_V1_8812F 0x04E0
#define REG_PTCL_ERR_STATUS_8812F 0x04E2
#define REG_NULL_PKT_STATUS_EXTEND_8812F 0x04E3
#define REG_HQMGQ_DROP_8812F 0x04E4
#define REG_PRECNT_CTRL_8812F 0x04E5
#define REG_BT_POLLUTE_PKT_CNT_8812F 0x04E8
#define REG_PTCL_DBG_8812F 0x04EC
#define REG_CPUMGQ_TIMER_CTRL2_8812F 0x04F4
#define REG_DUMMY_PAGE4_V1_8812F 0x04FC
#define REG_MOREDATA_8812F 0x04FE
#define REG_Q0_Q1_INFO_8812F 0x1400
#define REG_Q2_Q3_INFO_8812F 0x1404
#define REG_Q4_Q5_INFO_8812F 0x1408
#define REG_Q6_Q7_INFO_8812F 0x140C
#define REG_MGQ_HIQ_INFO_8812F 0x1410
#define REG_CMDQ_BCNQ_INFO_8812F 0x1414
#define REG_LOOPBACK_OPTION_8812F 0x1420
#define REG_AESIV_SETTING_8812F 0x1424
#define REG_BF0_TIME_SETTING_8812F 0x1428
#define REG_BF1_TIME_SETTING_8812F 0x142C
#define REG_BF_TIMEOUT_EN_8812F 0x1430
#define REG_MACID_RELEASE0_8812F 0x1434
#define REG_MACID_RELEASE1_8812F 0x1438
#define REG_MACID_RELEASE2_8812F 0x143C
#define REG_MACID_RELEASE3_8812F 0x1440
#define REG_MACID_RELEASE_SETTING_8812F 0x1444
#define REG_FAST_EDCA_VOVI_SETTING_8812F 0x1448
#define REG_FAST_EDCA_BEBK_SETTING_8812F 0x144C
#define REG_MACID_DROP0_8812F 0x1450
#define REG_MACID_DROP1_8812F 0x1454
#define REG_MACID_DROP2_8812F 0x1458
#define REG_MACID_DROP3_8812F 0x145C
#define REG_R_MACID_RELEASE_SUCCESS_0_8812F 0x1460
#define REG_R_MACID_RELEASE_SUCCESS_1_8812F 0x1464
#define REG_R_MACID_RELEASE_SUCCESS_2_8812F 0x1468
#define REG_R_MACID_RELEASE_SUCCESS_3_8812F 0x146C
#define REG_MGQ_FIFO_WRITE_POINTER_8812F 0x1470
#define REG_MGQ_FIFO_READ_POINTER_8812F 0x1472
#define REG_MGQ_FIFO_ENABLE_8812F 0x1472
#define REG_MGQ_FIFO_RELEASE_INT_MASK_8812F 0x1474
#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8812F 0x1476
#define REG_MGQ_FIFO_VALID_MAP_8812F 0x1478
#define REG_MGQ_FIFO_LIFETIME_8812F 0x147A
#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8812F 0x147C
#define REG_SHCUT_SETTING_8812F 0x1480
#define REG_SHCUT_LLC_ETH_TYPE0_8812F 0x1484
#define REG_SHCUT_LLC_ETH_TYPE1_8812F 0x1488
#define REG_SHCUT_LLC_OUI0_8812F 0x148C
#define REG_SHCUT_LLC_OUI1_8812F 0x1490
#define REG_SHCUT_LLC_OUI2_8812F 0x1494
#define REG_MU_TX_CTL_8812F 0x14C0
#define REG_MU_STA_GID_VLD_8812F 0x14C4
#define REG_MU_STA_USER_POS_INFO_8812F 0x14C8
#define REG_MU_STA_USER_POS_INFO_H_8812F 0x14CC
#define REG_CHNL_INFO_CTRL_8812F 0x14D0
#define REG_CHNL_IDLE_TIME_8812F 0x14D4
#define REG_CHNL_BUSY_TIME_8812F 0x14D8
#define REG_MU_TRX_DBG_CNT_V1_8812F 0x14DC
#define REG_SU_DURATION_8812F 0x14F0
#define REG_MU_DURATION_8812F 0x14F2
#define REG_HW_NDPA_RTY_LIMIT_8812F 0x14F4
#define REG_EDCA_VO_PARAM_8812F 0x0500
#define REG_EDCA_VI_PARAM_8812F 0x0504
#define REG_EDCA_BE_PARAM_8812F 0x0508
#define REG_EDCA_BK_PARAM_8812F 0x050C
#define REG_BCNTCFG_8812F 0x0510
#define REG_PIFS_8812F 0x0512
#define REG_RDG_PIFS_8812F 0x0513
#define REG_SIFS_8812F 0x0514
#define REG_TSFTR_SYN_OFFSET_8812F 0x0518
#define REG_AGGR_BREAK_TIME_8812F 0x051A
#define REG_SLOT_8812F 0x051B
#define REG_NOA_ON_ERLY_TIME_8812F 0x051C
#define REG_NOA_OFF_ERLY_TIME_8812F 0x051D
#define REG_TX_PTCL_CTRL_8812F 0x0520
#define REG_TXPAUSE_8812F 0x0522
#define REG_DIS_TXREQ_CLR_8812F 0x0523
#define REG_RD_CTRL_8812F 0x0524
#define REG_MBSSID_CTRL_8812F 0x0526
#define REG_P2PPS_CTRL_8812F 0x0527
#define REG_PKT_LIFETIME_CTRL_8812F 0x0528
#define REG_P2PPS_SPEC_STATE_8812F 0x052B
#define REG_TXOP_LIMIT_CTRL_8812F 0x052C
#define REG_BAR_TX_CTRL_8812F 0x0530
#define REG_P2PON_DIS_TXTIME_8812F 0x0531
#define REG_CCA_TXEN_CNT_8812F 0x0534
#define REG_MAX_INTER_COLLISION_8812F 0x0538
#define REG_MAX_INTER_COLLISION_CNT_8812F 0x053C
#define REG_TBTT_PROHIBIT_8812F 0x0540
#define REG_P2PPS_STATE_8812F 0x0543
#define REG_RD_NAV_NXT_8812F 0x0544
#define REG_NAV_PROT_LEN_8812F 0x0546
#define REG_FTM_PTT_8812F 0x0548
#define REG_FTM_TSF_8812F 0x054C
#define REG_BCN_CTRL_8812F 0x0550
#define REG_BCN_CTRL_CLINT0_8812F 0x0551
#define REG_MBID_NUM_8812F 0x0552
#define REG_DUAL_TSF_RST_8812F 0x0553
#define REG_MBSSID_BCN_SPACE_8812F 0x0554
#define REG_DRVERLYINT_8812F 0x0558
#define REG_BCNDMATIM_8812F 0x0559
#define REG_ATIMWND_8812F 0x055A
#define REG_USTIME_TSF_8812F 0x055C
#define REG_BCN_MAX_ERR_8812F 0x055D
#define REG_RXTSF_OFFSET_CCK_8812F 0x055E
#define REG_RXTSF_OFFSET_OFDM_8812F 0x055F
#define REG_TSFTR_8812F 0x0560
#define REG_TSFTR_1_8812F 0x0564
#define REG_FREERUN_CNT_8812F 0x0568
#define REG_FREERUN_CNT_1_8812F 0x056C
#define REG_ATIMWND1_V1_8812F 0x0570
#define REG_TBTT_PROHIBIT_INFRA_8812F 0x0571
#define REG_CTWND_8812F 0x0572
#define REG_BCNIVLCUNT_8812F 0x0573
#define REG_BCNDROPCTRL_8812F 0x0574
#define REG_HGQ_TIMEOUT_PERIOD_8812F 0x0575
#define REG_TXCMD_TIMEOUT_PERIOD_8812F 0x0576
#define REG_MISC_CTRL_8812F 0x0577
#define REG_BCN_CTRL_CLINT1_8812F 0x0578
#define REG_BCN_CTRL_CLINT2_8812F 0x0579
#define REG_BCN_CTRL_CLINT3_8812F 0x057A
#define REG_EXTEND_CTRL_8812F 0x057B
#define REG_P2PPS1_SPEC_STATE_8812F 0x057C
#define REG_P2PPS1_STATE_8812F 0x057D
#define REG_P2PPS2_SPEC_STATE_8812F 0x057E
#define REG_P2PPS2_STATE_8812F 0x057F
#define REG_PS_TIMER0_8812F 0x0580
#define REG_PS_TIMER1_8812F 0x0584
#define REG_PS_TIMER2_8812F 0x0588
#define REG_TBTT_CTN_AREA_8812F 0x058C
#define REG_FORCE_BCN_IFS_8812F 0x058E
#define REG_TXOP_MIN_8812F 0x0590
#define REG_PRE_BKF_TIME_8812F 0x0592
#define REG_CROSS_TXOP_CTRL_8812F 0x0593
#define REG_RX_TBTT_SHIFT_V1_8812F 0x0598
#define REG_ATIMWND2_8812F 0x05A0
#define REG_ATIMWND3_8812F 0x05A1
#define REG_ATIMWND4_8812F 0x05A2
#define REG_ATIMWND5_8812F 0x05A3
#define REG_ATIMWND6_8812F 0x05A4
#define REG_ATIMWND7_8812F 0x05A5
#define REG_ATIMUGT_8812F 0x05A6
#define REG_HIQ_NO_LMT_EN_8812F 0x05A7
#define REG_DTIM_COUNTER_ROOT_8812F 0x05A8
#define REG_DTIM_COUNTER_VAP1_8812F 0x05A9
#define REG_DTIM_COUNTER_VAP2_8812F 0x05AA
#define REG_DTIM_COUNTER_VAP3_8812F 0x05AB
#define REG_DTIM_COUNTER_VAP4_8812F 0x05AC
#define REG_DTIM_COUNTER_VAP5_8812F 0x05AD
#define REG_DTIM_COUNTER_VAP6_8812F 0x05AE
#define REG_DTIM_COUNTER_VAP7_8812F 0x05AF
#define REG_DIS_ATIM_8812F 0x05B0
#define REG_EARLY_128US_8812F 0x05B1
#define REG_P2PPS1_CTRL_8812F 0x05B2
#define REG_P2PPS2_CTRL_8812F 0x05B3
#define REG_TIMER0_SRC_SEL_8812F 0x05B4
#define REG_NOA_UNIT_SEL_8812F 0x05B5
#define REG_P2POFF_DIS_TXTIME_8812F 0x05B7
#define REG_MBSSID_BCN_SPACE2_8812F 0x05B8
#define REG_MBSSID_BCN_SPACE3_8812F 0x05BC
#define REG_ACMHWCTRL_8812F 0x05C0
#define REG_ACMRSTCTRL_8812F 0x05C1
#define REG_ACMAVG_8812F 0x05C2
#define REG_VO_ADMTIME_8812F 0x05C4
#define REG_VI_ADMTIME_8812F 0x05C6
#define REG_BE_ADMTIME_8812F 0x05C8
#define REG_MAC_HEADER_NAV_OFFSET_8812F 0x05CA
#define REG_DIS_NDPA_NAV_CHECK_8812F 0x05CB
#define REG_EDCA_RANDOM_GEN_8812F 0x05CC
#define REG_TXCMD_NOA_SEL_8812F 0x05CF
#define REG_32K_CLK_SEL_8812F 0x05D0
#define REG_EARLYINT_ADJUST_8812F 0x05D4
#define REG_BCNERR_CNT_8812F 0x05D8
#define REG_BCNERR_CNT_2_8812F 0x05DC
#define REG_NOA_PARAM_8812F 0x05E0
#define REG_NOA_PARAM_1_8812F 0x05E4
#define REG_NOA_PARAM_2_8812F 0x05E8
#define REG_NOA_PARAM_3_8812F 0x05EC
#define REG_P2P_RST_8812F 0x05F0
#define REG_SCHEDULER_RST_8812F 0x05F1
#define REG_SCH_DBG_VALUE_8812F 0x05F4
#define REG_SCH_TXCMD_8812F 0x05F8
#define REG_PAGE5_DUMMY_8812F 0x05FC
#define REG_CPUMGQ_TX_TIMER_8812F 0x1500
#define REG_PS_TIMER_A_8812F 0x1504
#define REG_PS_TIMER_B_8812F 0x1508
#define REG_PS_TIMER_C_8812F 0x150C
#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8812F 0x1510
#define REG_CPUMGQ_TX_TIMER_EARLY_8812F 0x1514
#define REG_PS_TIMER_A_EARLY_8812F 0x1515
#define REG_PS_TIMER_B_EARLY_8812F 0x1516
#define REG_PS_TIMER_C_EARLY_8812F 0x1517
#define REG_CPUMGQ_PARAMETER_8812F 0x1518
#define REG_TSF_SYNC_ADJ_8812F 0x1520
#define REG_TSF_ADJ_VLAUE_8812F 0x1524
#define REG_TSF_ADJ_VLAUE_2_8812F 0x1528
#define REG_P2PPS_HW_AUTO_PAUSE_CTRL_8812F 0x156C
#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8812F 0x1570
#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8812F 0x1574
#define REG_WMAC_CR_8812F 0x0600
#define REG_WMAC_FWPKT_CR_8812F 0x0601
#define REG_FW_STS_FILTER_8812F 0x0602
#define REG_TCR_8812F 0x0604
#define REG_RCR_8812F 0x0608
#define REG_RX_PKT_LIMIT_8812F 0x060C
#define REG_RX_DLK_TIME_8812F 0x060D
#define REG_RX_DRVINFO_SZ_8812F 0x060F
#define REG_MACID_8812F 0x0610
#define REG_MACID_H_8812F 0x0614
#define REG_BSSID_8812F 0x0618
#define REG_BSSID_H_8812F 0x061C
#define REG_MAR_8812F 0x0620
#define REG_MAR_H_8812F 0x0624
#define REG_MBIDCAMCFG_1_8812F 0x0628
#define REG_MBIDCAMCFG_2_8812F 0x062C
#define REG_WMAC_TCR_TSFT_OFS_8812F 0x0630
#define REG_UDF_THSD_8812F 0x0632
#define REG_ZLD_NUM_8812F 0x0633
#define REG_STMP_THSD_8812F 0x0634
#define REG_WMAC_TXTIMEOUT_8812F 0x0635
#define REG_USTIME_EDCA_8812F 0x0638
#define REG_ACKTO_CCK_8812F 0x0639
#define REG_MAC_SPEC_SIFS_8812F 0x063A
#define REG_RESP_SIFS_CCK_8812F 0x063C
#define REG_RESP_SIFS_OFDM_8812F 0x063E
#define REG_ACKTO_8812F 0x0640
#define REG_CTS2TO_8812F 0x0641
#define REG_EIFS_8812F 0x0642
#define REG_RPFM_MAP0_8812F 0x0644
#define REG_RPFM_MAP1_V1_8812F 0x0646
#define REG_RPFM_CAM_CMD_8812F 0x0648
#define REG_RPFM_CAM_RWD_8812F 0x064C
#define REG_NAV_CTRL_8812F 0x0650
#define REG_BACAMCMD_8812F 0x0654
#define REG_BACAMCONTENT_8812F 0x0658
#define REG_BACAMCONTENT_H_8812F 0x065C
#define REG_LBDLY_8812F 0x0660
#define REG_WMAC_BACAM_RPMEN_8812F 0x0661
#define REG_TX_RX_8812F 0x0662
#define REG_WMAC_BITMAP_CTL_8812F 0x0663
#define REG_RXERR_RPT_8812F 0x0664
#define REG_WMAC_TRXPTCL_CTL_8812F 0x0668
#define REG_WMAC_TRXPTCL_CTL_H_8812F 0x066C
#define REG_CAMCMD_8812F 0x0670
#define REG_CAMWRITE_8812F 0x0674
#define REG_CAMREAD_8812F 0x0678
#define REG_CAMDBG_8812F 0x067C
#define REG_SECCFG_8812F 0x0680
#define REG_RXFILTER_CATEGORY_1_8812F 0x0682
#define REG_RXFILTER_ACTION_1_8812F 0x0683
#define REG_RXFILTER_CATEGORY_2_8812F 0x0684
#define REG_RXFILTER_ACTION_2_8812F 0x0685
#define REG_RXFILTER_CATEGORY_3_8812F 0x0686
#define REG_RXFILTER_ACTION_3_8812F 0x0687
#define REG_RXFLTMAP3_8812F 0x0688
#define REG_RXFLTMAP4_8812F 0x068A
#define REG_RXFLTMAP5_8812F 0x068C
#define REG_RXFLTMAP6_8812F 0x068E
#define REG_WOW_CTRL_8812F 0x0690
#define REG_NAN_RX_TSF_FILTER_8812F 0x0691
#define REG_PS_RX_INFO_8812F 0x0692
#define REG_WMMPS_UAPSD_TID_8812F 0x0693
#define REG_LPNAV_CTRL_8812F 0x0694
#define REG_WKFMCAM_CMD_8812F 0x0698
#define REG_WKFMCAM_RWD_8812F 0x069C
#define REG_RXFLTMAP0_8812F 0x06A0
#define REG_RXFLTMAP1_8812F 0x06A2
#define REG_RXFLTMAP2_8812F 0x06A4
#define REG_BCN_PSR_RPT_8812F 0x06A8
#define REG_FLC_RPC_8812F 0x06AC
#define REG_FLC_RPCT_8812F 0x06AD
#define REG_FLC_PTS_8812F 0x06AE
#define REG_FLC_TRPC_8812F 0x06AF
#define REG_RXPKTMON_CTRL_8812F 0x06B0
#define REG_STATE_MON_8812F 0x06B4
#define REG_ERROR_MON_8812F 0x06B8
#define REG_SEARCH_MACID_8812F 0x06BC
#define REG_BT_COEX_TABLE_8812F 0x06C0
#define REG_BT_COEX_TABLE2_8812F 0x06C4
#define REG_BT_COEX_BREAK_TABLE_8812F 0x06C8
#define REG_BT_COEX_TABLE_H_8812F 0x06CC
#define REG_RXCMD_0_8812F 0x06D0
#define REG_RXCMD_1_8812F 0x06D4
#define REG_WMAC_RESP_TXINFO_8812F 0x06D8
#define REG_BBPSF_CTRL_8812F 0x06DC
#define REG_P2P_RX_BCN_NOA_8812F 0x06E0
#define REG_ASSOCIATED_BFMER0_INFO_8812F 0x06E4
#define REG_ASSOCIATED_BFMER0_INFO_H_8812F 0x06E8
#define REG_ASSOCIATED_BFMER1_INFO_8812F 0x06EC
#define REG_ASSOCIATED_BFMER1_INFO_H_8812F 0x06F0
#define REG_TX_CSI_RPT_PARAM_BW20_8812F 0x06F4
#define REG_TX_CSI_RPT_PARAM_BW40_8812F 0x06F8
#define REG_CSI_PTR_8812F 0x06FC
#define REG_BCN_PSR_RPT2_8812F 0x1600
#define REG_BCN_PSR_RPT3_8812F 0x1604
#define REG_BCN_PSR_RPT4_8812F 0x1608
#define REG_A1_ADDR_MASK_8812F 0x160C
#define REG_RXPSF_CTRL_8812F 0x1610
#define REG_RXPSF_TYPE_CTRL_8812F 0x1614
#define REG_CAM_ACCESS_CTRL_8812F 0x1618
#define REG_HT_SND_REF_RATE_8812F 0x161C
#define REG_MACID2_8812F 0x1620
#define REG_MACID2_H_8812F 0x1624
#define REG_BSSID2_8812F 0x1628
#define REG_BSSID2_H_8812F 0x162C
#define REG_MACID3_8812F 0x1630
#define REG_MACID3_H_8812F 0x1634
#define REG_BSSID3_8812F 0x1638
#define REG_BSSID3_H_8812F 0x163C
#define REG_MACID4_8812F 0x1640
#define REG_MACID4_H_8812F 0x1644
#define REG_BSSID4_8812F 0x1648
#define REG_BSSID4_H_8812F 0x164C
#define REG_NOA_REPORT_8812F 0x1650
#define REG_NOA_REPORT_1_8812F 0x1654
#define REG_NOA_REPORT_2_8812F 0x1658
#define REG_NOA_REPORT_3_8812F 0x165C
#define REG_PWRBIT_SETTING_8812F 0x1660
#define REG_GENERAL_OPTION_8812F 0x1664
#define REG_RXAI_CTRL_8812F 0x1668
#define REG_CSI_RRSR_8812F 0x1678
#define REG_MU_BF_OPTION_8812F 0x167C
#define REG_WMAC_PAUSE_BB_CLR_TH_8812F 0x167D
#define REG__WMAC_MULBK_BUF_8812F 0x167E
#define REG_WMAC_MU_OPTION_8812F 0x167F
#define REG_WMAC_MU_BF_CTL_8812F 0x1680
#define REG_WMAC_MU_BFRPT_PARA_8812F 0x1682
#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8812F 0x1684
#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8812F 0x1686
#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8812F 0x1688
#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8812F 0x168A
#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8812F 0x168C
#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8812F 0x168E
#define REG_WMAC_BB_STOP_RX_COUNTER_8812F 0x1690
#define REG_WMAC_PLCP_MONITOR_8812F 0x1694
#define REG_WMAC_PLCP_MONITOR_MUTX_8812F 0x1698
#define REG_WMAC_CSIDMA_CFG_8812F 0x169C
#define REG_TRANSMIT_ADDRSS_0_8812F 0x16A0
#define REG_TRANSMIT_ADDRSS_0_H_8812F 0x16A4
#define REG_TRANSMIT_ADDRSS_1_8812F 0x16A8
#define REG_TRANSMIT_ADDRSS_1_H_8812F 0x16AC
#define REG_TRANSMIT_ADDRSS_2_8812F 0x16B0
#define REG_TRANSMIT_ADDRSS_2_H_8812F 0x16B4
#define REG_TRANSMIT_ADDRSS_3_8812F 0x16B8
#define REG_TRANSMIT_ADDRSS_3_H_8812F 0x16BC
#define REG_TRANSMIT_ADDRSS_4_8812F 0x16C0
#define REG_TRANSMIT_ADDRSS_4_H_8812F 0x16C4
#define REG_SND_AID12_8812F 0x16D0
#define REG_SND_PKT_INFO_8812F 0x16D2
#define REG_MACID1_8812F 0x0700
#define REG_MACID1_1_8812F 0x0704
#define REG_BSSID1_8812F 0x0708
#define REG_BSSID1_1_8812F 0x070C
#define REG_BCN_PSR_RPT1_8812F 0x0710
#define REG_ASSOCIATED_BFMEE_SEL_8812F 0x0714
#define REG_SND_PTCL_CTRL_8812F 0x0718
#define REG_RX_CSI_RPT_INFO_8812F 0x071C
#define REG_NS_ARP_CTRL_8812F 0x0720
#define REG_NS_ARP_INFO_8812F 0x0724
#define REG_BEAMFORMING_INFO_NSARP_V1_8812F 0x0728
#define REG_BEAMFORMING_INFO_NSARP_8812F 0x072C
#define REG_IPV6_8812F 0x0730
#define REG_IPV6_1_8812F 0x0734
#define REG_IPV6_2_8812F 0x0738
#define REG_IPV6_3_8812F 0x073C
#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8812F 0x0750
#define REG_WMAC_SWAES_DIO_B63_B32_8812F 0x0754
#define REG_WMAC_SWAES_DIO_B95_B64_8812F 0x0758
#define REG_WMAC_SWAES_DIO_B127_B96_8812F 0x075C
#define REG_WMAC_SWAES_CFG_8812F 0x0760
#define REG_BT_COEX_V2_8812F 0x0762
#define REG_BT_COEX_8812F 0x0764
#define REG_WLAN_ACT_MASK_CTRL_8812F 0x0768
#define REG_WLAN_ACT_MASK_CTRL_1_8812F 0x076C
#define REG_BT_COEX_ENHANCED_INTR_CTRL_8812F 0x076E
#define REG_BT_ACT_STATISTICS_8812F 0x0770
#define REG_BT_ACT_STATISTICS_1_8812F 0x0774
#define REG_BT_STATISTICS_CONTROL_REGISTER_8812F 0x0778
#define REG_BT_STATUS_REPORT_REGISTER_8812F 0x077C
#define REG_BT_INTERRUPT_CONTROL_REGISTER_8812F 0x0780
#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8812F 0x0784
#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8812F 0x0785
#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8812F 0x0788
#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8812F 0x078C
#define REG_BT_INTERRUPT_STATUS_REGISTER_8812F 0x078F
#define REG_BT_TDMA_TIME_REGISTER_8812F 0x0790
#define REG_BT_ACT_REGISTER_8812F 0x0794
#define REG_OBFF_CTRL_BASIC_8812F 0x0798
#define REG_OBFF_CTRL2_TIMER_8812F 0x079C
#define REG_LTR_CTRL_BASIC_8812F 0x07A0
#define REG_LTR_CTRL2_TIMER_THRESHOLD_8812F 0x07A4
#define REG_LTR_IDLE_LATENCY_V1_8812F 0x07A8
#define REG_LTR_ACTIVE_LATENCY_V1_8812F 0x07AC
#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8812F 0x07B0
#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8812F 0x07B4
#define REG_WMAC_PKTCNT_RWD_8812F 0x07B8
#define REG_WMAC_PKTCNT_CTRL_8812F 0x07BC
#define REG_IQ_DUMP_8812F 0x07C0
#define REG_IQ_DUMP_1_8812F 0x07C4
#define REG_IQ_DUMP_2_8812F 0x07C8
#define REG_WMAC_FTM_CTL_8812F 0x07CC
#define REG_WMAC_IQ_MDPK_FUNC_8812F 0x07CE
#define REG_WMAC_OPTION_FUNCTION_8812F 0x07D0
#define REG_WMAC_OPTION_FUNCTION_1_8812F 0x07D4
#define REG_WMAC_OPTION_FUNCTION_2_8812F 0x07D8
#define REG_RX_FILTER_FUNCTION_8812F 0x07DA
#define REG_NDP_SIG_8812F 0x07E0
#define REG_TXCMD_INFO_FOR_RSP_PKT_8812F 0x07E4
#define REG_TXCMD_INFO_FOR_RSP_PKT_1_8812F 0x07E8
#define REG_WSEC_OPTION_8812F 0x07EC
#define REG_RTS_ADDRESS_0_8812F 0x07F0
#define REG_RTS_ADDRESS_0_1_8812F 0x07F4
#define REG_RTS_ADDRESS_1_8812F 0x07F8
#define REG_RTS_ADDRESS_1_1_8812F 0x07FC
#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8812F 0x1700
#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8812F 0x1704
#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8812F 0x1708
#define REG_SDIO_TX_CTRL_8812F 0x10250000
#define REG_SDIO_CMD11_VOL_SWITCH_8812F 0x10250004
#define REG_SDIO_CTRL_8812F 0x10250005
#define REG_SDIO_DRIVING_8812F 0x10250006
#define REG_SDIO_MONITOR_8812F 0x10250008
#define REG_SDIO_MONITOR_2_8812F 0x1025000C
#define REG_SDIO_CTRL_2_8812F 0x10250010
#define REG_SDIO_HIMR_8812F 0x10250014
#define REG_SDIO_HISR_8812F 0x10250018
#define REG_SDIO_RX_REQ_LEN_8812F 0x1025001C
#define REG_SDIO_FREE_TXPG_SEQ_V1_8812F 0x1025001F
#define REG_SDIO_FREE_TXPG_8812F 0x10250020
#define REG_SDIO_FREE_TXPG2_8812F 0x10250024
#define REG_SDIO_OQT_FREE_TXPG_V1_8812F 0x10250028
#define REG_SDIO_TXPKT_EMPTY_8812F 0x1025002C
#define REG_SDIO_HTSFR_INFO_8812F 0x10250030
#define REG_SDIO_HCPWM1_V2_8812F 0x10250038
#define REG_SDIO_HCPWM2_V2_8812F 0x1025003A
#define REG_SDIO_INDIRECT_REG_CFG_8812F 0x10250040
#define REG_SDIO_INDIRECT_REG_DATA_8812F 0x10250044
#define REG_SDIO_H2C_8812F 0x10250060
#define REG_SDIO_C2H_8812F 0x10250064
#define REG_SDIO_HRPWM1_8812F 0x10250080
#define REG_SDIO_HRPWM2_8812F 0x10250082
#define REG_SDIO_HPS_CLKR_8812F 0x10250084
#define REG_SDIO_BUS_CTRL_8812F 0x10250085
#define REG_SDIO_HSUS_CTRL_8812F 0x10250086
#define REG_SDIO_RESPONSE_TIMER_8812F 0x10250088
#define REG_SDIO_CMD_CRC_8812F 0x1025008A
#define REG_SDIO_HSISR_8812F 0x10250090
#define REG_SDIO_HSIMR_8812F 0x10250091
#define REG_SDIO_DIOERR_RPT_8812F 0x102500C0
#define REG_SDIO_CMD_ERRCNT_8812F 0x102500C2
#define REG_SDIO_DATA_ERRCNT_8812F 0x102500C3
#define REG_SDIO_CMD_ERR_CONTENT_8812F 0x102500C4
#define REG_SDIO_CRC_ERR_IDX_8812F 0x102500C9
#define REG_SDIO_DATA_CRC_8812F 0x102500CA
#define REG_SDIO_TRANS_FIFO_STATUS_8812F 0x102500CC
#endif

2
hal/halmac/halmac_reg_8814b.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
hal/halmac/halmac_reg_8821c.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

2
hal/halmac/halmac_reg_8822b.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as

3
hal/halmac/halmac_reg_8822c.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2017 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -96,6 +96,7 @@
#define REG_ANAPAR_XTAL_3_8822C 0x104C
#define REG_ANAPAR_XTAL_AACK_0_8822C 0x1054
#define REG_ANAPAR_XTAL_AACK_1_8822C 0x1058
#define REG_XTAL_AAC_OUTPUT_8822C 0x1060
#define REG_ANAPAR_XTAL_MODE_DECODER_8822C 0x1064
#define REG_SYS_CFG5_8822C 0x1070
#define REG_CPU_DMEM_CON_8822C 0x1080

4
hal/halmac/halmac_rx_bd_nic.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -17,7 +17,7 @@
#define _HALMAC_RX_BD_NIC_H_
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||\
HALMAC_8812F_SUPPORT)
HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8814B_SUPPORT)
/*TXBD_DW0*/

89
hal/halmac/halmac_rx_desc_ap.h
View File

@@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -17,7 +17,7 @@
#define _HALMAC_RX_DESC_AP_H_
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
/*RXDESC_WORD0*/
@@ -29,7 +29,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_PHYPKTIDC(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \
@@ -47,7 +47,8 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_SWDEC(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \
@@ -90,7 +91,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_TY_PE(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x3, \
@@ -108,7 +109,8 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_MF(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
@@ -124,7 +126,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_PAM(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
@@ -142,7 +144,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_CHK_VLD(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
@@ -160,7 +162,8 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
@@ -173,7 +176,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_CHKERR(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
@@ -197,7 +200,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_PAGGR(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
@@ -215,7 +218,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RXID_MATCH(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
@@ -233,7 +236,8 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_AMSDU(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
@@ -243,7 +247,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_MACID_VLD(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
@@ -253,7 +257,8 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_TID(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0xf, 8)
@@ -262,7 +267,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_MACID(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x7f, \
@@ -286,7 +291,7 @@
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
HALMAC_8812F_SUPPORT)
HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_PPDU_CNT(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x3, \
@@ -296,7 +301,8 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_C2H(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
@@ -304,7 +310,7 @@
#endif
#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)
#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT)
#define GET_RX_DESC_HWRSVD_V1(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x7, \
@@ -331,7 +337,8 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_WLANHD_IV_LEN(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x3f, \
@@ -347,7 +354,7 @@
#endif
#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#if (HALMAC_8822C_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RX_STATISTICS(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
@@ -357,7 +364,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RX_IS_QOS(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
@@ -375,7 +382,8 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_FRAG(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0xf, \
@@ -384,6 +392,12 @@
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, \
0xfff, 0)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
/*RXDESC_WORD3*/
#define GET_RX_DESC_MAGIC_WAKE(rxdesc) \
@@ -427,7 +441,8 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_DMA_AGG_NUM(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0xff, \
@@ -437,7 +452,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_BSSID_FIT_1_0(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x3, \
@@ -458,7 +473,8 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_HTC(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \
@@ -477,7 +493,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_BSSID_FIT_4_2(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x7, 7)
@@ -493,7 +509,8 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RX_RATE(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x7f, \
@@ -521,7 +538,7 @@
#endif
#if (HALMAC_8198F_SUPPORT)
#if (HALMAC_8198F_SUPPORT || HALMAC_8197G_SUPPORT)
#define GET_RX_DESC_A1_FIT_A1(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \
@@ -539,7 +556,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_MACID_RPT_BUFF(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \
@@ -549,7 +566,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, \
@@ -586,7 +603,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RX_SCRAMBLER(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \
@@ -604,21 +621,21 @@
#endif
#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8197G_SUPPORT)
#define GET_RX_DESC_FC_POWER(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 7)
#endif
#if (HALMAC_8198F_SUPPORT)
#if (HALMAC_8198F_SUPPORT || HALMAC_8197G_SUPPORT)
#define GET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 6)
#endif
#if (HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT)
#if (HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8197G_SUPPORT)
#define GET_RX_DESC_SWPS_RPT(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 5)
@@ -652,7 +669,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
HALMAC_8192F_SUPPORT || HALMAC_8197G_SUPPORT || HALMAC_8812F_SUPPORT)
/*RXDESC_WORD5*/

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