RinCat/RTL88x2BU-Linux-Driver
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Update to 5.13.1 from upstream

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Rin Cat (鈴猫)
2021-12-04 07:42:09 -05:00
parent aab1daf818
commit c0e109d401
352 changed files with 50307 additions and 18938 deletions
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7
hal/phydm/txbf/haltxbfjaguar.c
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@@ -93,10 +93,9 @@ void hal_txbf_jaguar_download_ndpa(
#endif
PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
if (idx == 0)
head_page = 0xFE;
else
head_page = 0xFE;
/* if (idx == 0) head_page = 0xFE; */
/* else head_page = 0xFE;*/
head_page = 0xFE;
phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy);

116
hal/phydm/txbf/phydm_hal_txbf_api.c
View File

@@ -17,7 +17,7 @@
#include "phydm_precomp.h"
#if (defined(CONFIG_BB_TXBF_API))
#if (RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1 ||\
#if (RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8812F_SUPPORT == 1 ||\
RTL8822C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
/*@Add by YuChen for 8822B MU-MIMO API*/
@@ -121,7 +121,6 @@ u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num)
if (dm->support_ic_type & ODM_RTL8814A)
nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num);
else
#endif
nr_index = tx_bf_nr(1, bfer_str_num);
switch (nr_index) {
@@ -141,6 +140,9 @@ u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num)
ndp_tx_rate = ODM_MGN_MCS8;
break;
}
#else
ndp_tx_rate = ODM_MGN_MCS8;
#endif
return ndp_tx_rate;
}
@@ -155,7 +157,6 @@ u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num)
if (dm->support_ic_type & ODM_RTL8814A)
nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num);
else
#endif
nr_index = tx_bf_nr(1, bfer_str_num);
switch (nr_index) {
@@ -175,6 +176,9 @@ u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num)
ndp_tx_rate = ODM_MGN_VHT2SS_MCS0;
break;
}
#else
ndp_tx_rate = ODM_MGN_VHT2SS_MCS0;
#endif
return ndp_tx_rate;
}
@@ -338,16 +342,16 @@ void phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
/* logic mapping */
/* TX BF logic map and TX path en for Nsts = 1~4 */
odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0xffff);
//odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0xffff);
/*verification path-AC*/
odm_set_bb_reg(dm, R_0x1e30, 0xffffffff, 0xe4e4e4e4);
//odm_set_bb_reg(dm, R_0x1e30, 0xffffffff, 0xe4e4e4e4);
} else {
/*@Disable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
/*@1SS~4ss A, AB, ABC, ABCD*/
odm_set_bb_reg(dm, R_0x820, 0xffff, 0xf731);
odm_set_bb_reg(dm, R_0x1e2c, 0xffffffff, 0xe4240400);
//odm_set_bb_reg(dm, R_0x820, 0xffff, 0xf731);
//odm_set_bb_reg(dm, R_0x1e2c, 0xffffffff, 0xe4240400);
}
}
#endif
@@ -472,12 +476,27 @@ void phydm_mu_rsoml_init(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3;
u32 val = 0;
PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] %s - cnt init\n", __func__);
PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] %s\n", __func__);
/*OFDM Tx*/
val = odm_get_bb_reg(dm, R_0x820, MASKDWORD);
rateinfo->tx_path_en_ofdm_2sts = (u8)((val & 0xf0) >> 4);
rateinfo->tx_path_en_ofdm_1sts = (u8)(val & 0xf);
/*OFDM Rx*/
rateinfo->rx_path_en_ofdm = (u8)odm_get_bb_reg(dm, R_0x824, 0xf0000);
rateinfo->enable = 1;
rateinfo->mu_ratio_th = 30;
rateinfo->pre_mu_ratio = 0;
rateinfo->mu_set_trxpath = 0;
rateinfo->mu_been_iot = 0;
PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] %s tx1ss=%d, tx2ss=%d, rx=%d\n",
__func__, rateinfo->tx_path_en_ofdm_1sts,
rateinfo->tx_path_en_ofdm_2sts, rateinfo->rx_path_en_ofdm);
phydm_mu_rsoml_reset(dm);
}
@@ -485,12 +504,19 @@ void phydm_mu_rsoml_decision(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3;
struct phydm_iot_center *iot_table = &dm->iot_table;
u8 offset = 0;
u32 mu_ratio = 0;
u32 su_pkt = 0;
u32 mu_pkt = 0;
u32 total_pkt = 0;
if (rateinfo->tx_path_en_ofdm_2sts != 3 ||
rateinfo->rx_path_en_ofdm != 3) {
PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] Init Not 2T2R 22CE\n");
return;
}
PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML Decision eanble: %d\n",
rateinfo->enable);
@@ -512,28 +538,46 @@ void phydm_mu_rsoml_decision(void *dm_void)
mu_ratio, total_pkt);
if (mu_ratio > rateinfo->mu_ratio_th &&
rateinfo->pre_mu_ratio > rateinfo->mu_ratio_th)
rateinfo->pre_mu_ratio > rateinfo->mu_ratio_th) {
PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML status remain\n");
else if (mu_ratio <= rateinfo->mu_ratio_th &&
rateinfo->pre_mu_ratio <= rateinfo->mu_ratio_th)
} else if (mu_ratio <= rateinfo->mu_ratio_th &&
rateinfo->pre_mu_ratio <= rateinfo->mu_ratio_th) {
PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML status remain\n");
else if (mu_ratio > rateinfo->mu_ratio_th)
} else if (mu_ratio > rateinfo->mu_ratio_th) {
odm_set_bb_reg(dm, R_0xc00, BIT(26), 0);
else
PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML OFF\n");
} else {
odm_set_bb_reg(dm, R_0xc00, BIT(26), 1);
PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML ON\n");
}
PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] set_trxpath=%d, patch_10120200=%d\n",
rateinfo->mu_set_trxpath, iot_table->patch_id_10120200);
if (rateinfo->mu_set_trxpath && iot_table->patch_id_10120200) {
if (mu_ratio > rateinfo->mu_ratio_th) {
phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_A,
BB_PATH_AUTO);
PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] 22C IOT 2T1R\n");
rateinfo->mu_been_iot = 1;
} else {
phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB,
BB_PATH_AUTO);
PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] 22C IOT 2T2R\n");
rateinfo->mu_been_iot = 0;
}
} else if (rateinfo->mu_been_iot == 1) {
if (odm_get_bb_reg(dm, R_0x824, 0xf0000) == 1) {
phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB,
BB_PATH_AUTO);
PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] 22C IOT Restore\n");
rateinfo->mu_been_iot = 0;
}
}
rateinfo->pre_mu_ratio = mu_ratio;
phydm_mu_rsoml_reset(dm);
}
void phydm_txbf_avoid_hang(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
/* avoid CCK CCA hang when the BF mode */
odm_set_bb_reg(dm, R_0x1e6c, 0x100000, 0x1);
}
#if (RTL8814B_SUPPORT == 1)
void phydm_txbf_80p80_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
@@ -621,6 +665,21 @@ void phydm_txbf_80p80_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
#endif
#endif /*PHYSTS_3RD_TYPE_IC*/
void phydm_txbf_avoid_hang(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
/* avoid CCK CCA hang when the BF mode */
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
odm_set_bb_reg(dm, R_0x1e6c, 0x100000, 0x1);
#endif
/* avoid CCK CCA hang when the BFee mode for 92F */
#if (RTL8192F_SUPPORT == 1)
odm_set_bb_reg(dm, R_0xa70, 0xffff0000, 0x80ff);
#endif
}
void phydm_bf_debug(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len)
{
@@ -634,11 +693,12 @@ void phydm_bf_debug(void *dm_void, char input[][16], u32 *_used, char *output,
"{BF ver1 :0}, {NO applyV:0; applyV:1; default:2}\n");
PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{MU RSOML:1}, {MU enable:1/0}, {MU Ratio:40}\n");
PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
"{MU TRxPath:2}, {TRxPath enable:1/0}\n");
return;
}
for (i = 0; i < 3; i++) {
if (input[i + 1])
PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
}
if (var1[0] == 0) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
@@ -683,6 +743,16 @@ void phydm_bf_debug(void *dm_void, char input[][16], u32 *_used, char *output,
"[MU RSOML] enable= %d, MU ratio TH= %d\n",
bfinfo->enable, bfinfo->mu_ratio_th);
#endif
} else if (var1[0] == 2) {
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_bf_rate_info_jgr3 *bfinfo = &dm->bf_rate_info_jgr3;
bfinfo->mu_set_trxpath = (u8)var1[1];
PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
"[MU TRxPath] mu_set_trxpath = %d\n",
bfinfo->mu_set_trxpath);
#endif
}
}

8
hal/phydm/txbf/phydm_hal_txbf_api.h
View File

@@ -44,8 +44,7 @@ u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num);
#endif
#if (RTL8822B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8192F_SUPPORT == 1 ||\
RTL8814B_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
RTL8814B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 || RTL8812F_SUPPORT == 1)
u8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *throughput,
u8 total_bfee_num, u8 *tx_rate);
u8 phydm_get_ndpa_rate(void *dm_void);
@@ -66,6 +65,11 @@ struct phydm_bf_rate_info_jgr3 {
u32 pre_mu_ratio;
u16 num_mu_vht_pkt[VHT_RATE_NUM];
u16 num_qry_vht_pkt[VHT_RATE_NUM];
boolean mu_set_trxpath;
u8 tx_path_en_ofdm_1sts;
u8 tx_path_en_ofdm_2sts;
u8 rx_path_en_ofdm;
boolean mu_been_iot;
};
/*this function is only used for BFer*/