Update to 5.13.1 from upstream

2026-04-02 06:09:41 +00:00 · 2021-12-04 07:42:09 -05:00
parent aab1daf818
commit c0e109d401
352 changed files with 50307 additions and 18938 deletions
--- a/hal/phydm/ap_makefile.mk
+++ b/hal/phydm/ap_makefile.mk
@@ -122,7 +122,8 @@ ifeq ($(CONFIG_WLAN_HAL_8812FE),y)
 		_PHYDM_FILES += \
 		phydm/rtl8812f/halhwimg8812f_bb.o\
 		phydm/rtl8812f/phydm_regconfig8812f.o\
-		phydm/rtl8812f/phydm_hal_api8812f.o
+		phydm/rtl8812f/phydm_hal_api8812f.o\
+		phydm/rtl8812f/phydm_rtl8812f.o
 	endif
 endif

@@ -135,7 +136,8 @@ ifeq ($(CONFIG_WLAN_HAL_8821CE),y)
 		phydm/rtl8821c/halhwimg8821c_bb.o\
 		phydm/rtl8821c/halhwimg8821c_mac.o\
 		phydm/rtl8821c/phydm_regconfig8821c.o\
-		phydm/rtl8821c/phydm_hal_api8821c.o
+		phydm/rtl8821c/phydm_hal_api8821c.o\
+		phydm/rtl8821c/phydm_rtl8821c.o
 	endif
 endif

@@ -190,6 +192,7 @@ ifeq ($(CONFIG_WLAN_HAL_8814BE),y)
 		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_8814b.o
 		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_iqk_8814b.o
 		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_dpk_8814b.o
+		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_txgapk_8814b.o
 		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_rfk_init_8814b.o
 		_PHYDM_FILES += phydm/halrf/rtl8814b/halhwimg8814b_rf.o
 	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
@@ -197,6 +200,7 @@ ifeq ($(CONFIG_WLAN_HAL_8814BE),y)
 		phydm/rtl8814b/phydm_hal_api8814b.o\
 		phydm/rtl8814b/halhwimg8814b_bb.o\
 		phydm/rtl8814b/phydm_regconfig8814b.o \
+		phydm/rtl8814b/phydm_extraagc8814b.o \
 		phydm/halrf/rtl8814b/halrf_8814b.o
 	endif
 endif
@@ -214,7 +218,20 @@ ifeq ($(CONFIG_WLAN_HAL_8197G),y)
 		phydm/rtl8197g/halhwimg8197g_bb.o\
 		phydm/rtl8197g/halhwimg8197g_mac.o\
 		phydm/rtl8197g/phydm_regconfig8197g.o \
+		phydm/rtl8197g/phydm_rtl8197g.o \
 		phydm/halrf/rtl8197g/halrf_8197g.o
 	endif
 endif
-
+ifeq ($(CONFIG_WLAN_HAL_8723FE),y)
+	_PHYDM_FILES += phydm/halrf/rtl8723f/halrf_8723f.o
+	_PHYDM_FILES += phydm/halrf/rtl8723f/halrf_iqk_8723f.o
+	_PHYDM_FILES += phydm/halrf/rtl8723f/halrf_dpk_8723f.o
+	_PHYDM_FILES += phydm/halrf/rtl8723f/halrf_rfk_init_8723f.o
+	_PHYDM_FILES += phydm/halrf/rtl8723f/halhwimg8723f_rf.o
+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
+		_PHYDM_FILES += \
+		phydm/rtl8723f/halhwimg8723f_bb.o\
+		phydm/rtl8723f/phydm_regconfig8723f.o\
+		phydm/rtl8723f/phydm_hal_api8723f.o
+	endif
+endif
--- a/hal/phydm/halrf/halphyrf_ap.c
+++ b/hal/phydm/halrf/halphyrf_ap.c
@@ -433,17 +433,25 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series4(void *dm_void)
 			priv->pmib->dot11RFEntry.thermal[i] == 0x0)
 			return;
 	}
-	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)) {
+	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) {
 		for (i = 0; i < c.rf_path_count; i++)
 			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0x7e); /* 0x42: RF Reg[6:1] Thermal Trim*/
+	} else if (dm->support_ic_type == ODM_RTL8197G) {
+		for (i = 0; i < c.rf_path_count; i++)
+			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, RF_0xf6, 0x7E000);
 	} else {
 		for (i = 0; i < c.rf_path_count; i++) {
 			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */

-			thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_thermal_offset(dm);
-
-			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-				"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + power_time_thermal(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_thermal_offset(dm));
+			if (dm->support_ic_type == ODM_RTL8814B) {
+				thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_multi_thermal_offset(dm, i);
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + multi_thermal_trim(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_multi_thermal_offset(dm, i));
+			} else {
+				thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_thermal_offset(dm);
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + thermal_trim(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_thermal_offset(dm));
+			}

 			if (thermal_value_temp[i] > 63)
 				thermal_value[i] = 63;
@@ -591,7 +599,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series4(void *dm_void)

 #endif
 	/* Wait sacn to do IQK by RF Jenyu*/
-	if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
+	if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden) && (dm->is_linked || *dm->mp_mode)) {
 		/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
 		if (delta_IQK >= c.threshold_iqk) {
 			cali_info->thermal_value_iqk = thermal_value[RF_PATH_A];
@@ -838,9 +846,9 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series3(
 				if (GET_CHIP_VER(priv) == VERSION_8197F) {
 					for (p = RF_PATH_A; p < c.rf_path_count; p++)
 						(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
-				//}  else if (GET_CHIP_VER(priv) == VERSION_8192F) {
-				//	for (p = RF_PATH_A; p < c.rf_path_count; p++)
-				//		(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+				} else if (GET_CHIP_VER(priv) == VERSION_8192F) {
+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
 				} else if (GET_CHIP_VER(priv) == VERSION_8822B) {
 					for (p = RF_PATH_A; p < c.rf_path_count; p++)
 						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
@@ -850,15 +858,18 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series3(
 				}  else if (GET_CHIP_VER(priv) == VERSION_8198F) {
 					for (p = RF_PATH_A; p < c.rf_path_count; p++)
 						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+				} else if (GET_CHIP_VER(priv) == VERSION_8192F) {
+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
 				}
 			} else {
 				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power --->\n");
 				if (GET_CHIP_VER(priv) == VERSION_8197F) {
 					for (p = RF_PATH_A; p < c.rf_path_count; p++)
 						(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
-				//} else if (GET_CHIP_VER(priv) == VERSION_8192F) {
-				//	for (p = RF_PATH_A; p < c.rf_path_count; p++)
-				//		(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+				} else if (GET_CHIP_VER(priv) == VERSION_8192F) {
+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
 				} else if (GET_CHIP_VER(priv) == VERSION_8822B) {
 					for (p = RF_PATH_A; p < c.rf_path_count; p++)
 						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
@@ -868,13 +879,16 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series3(
 				} else if (GET_CHIP_VER(priv) == VERSION_8198F) {
 					for (p = RF_PATH_A; p < c.rf_path_count; p++)
 						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+				} else if (GET_CHIP_VER(priv) == VERSION_8192F) {
+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
 				}
 			}
 		}
 #endif

 		if (GET_CHIP_VER(priv) != VERSION_8198F) {
-			if ((delta_IQK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
+			if ((delta_IQK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden) && dm->is_linked) {
 				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
 				dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
 				if (!(dm->support_ic_type & ODM_RTL8197F)) {
--- a/hal/phydm/halrf/halphyrf_ap.h
+++ b/hal/phydm/halrf/halphyrf_ap.h
@@ -52,6 +52,7 @@
 #if (RTL8814B_SUPPORT == 1)
 	#include "halrf/rtl8814b/halrf_iqk_8814b.h"
 	#include "halrf/rtl8814b/halrf_dpk_8814b.h"
+	#include "halrf/rtl8814b/halrf_txgapk_8814b.h"
 #endif

 #if (RTL8197G_SUPPORT == 1)
--- a/hal/phydm/halrf/halphyrf_ce.c
+++ b/hal/phydm/halrf/halphyrf_ce.c
@@ -115,6 +115,10 @@ void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config)
 		configure_txpower_track_8814b(config);
 #endif

+#if RTL8723F_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8723F)
+		configure_txpower_track_8723f(config);
+#endif

 }

@@ -376,12 +380,20 @@ void odm_pwrtrk_method(void *dm_void)
 	if (dm->support_ic_type &
 		(ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8821 | ODM_RTL8812 |
 		ODM_RTL8723B | ODM_RTL8814A | ODM_RTL8703B | ODM_RTL8188F |
-		ODM_RTL8822B | ODM_RTL8723D | ODM_RTL8821C | ODM_RTL8710B |
+		ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8710B |
 		ODM_RTL8192F)) {
 		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
 		       "***Enter PwrTrk MIX_MODE***\n");
 		for (p = RF_PATH_A; p < c.rf_path_count; p++)
 			(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+	} else if (dm->support_ic_type & ODM_RTL8723D) {
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+		       "***Enter PwrTrk MIX_MODE***\n");
+		p = (u8)odm_get_bb_reg(dm, R_0x948, 0x00000080);
+		(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+		/*if open ant_div 0x948=140,do 2 path pwr_track*/
+		if (odm_get_bb_reg(dm, R_0x948, 0x00000040))
+			(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, 1, 0);
 	} else {
 		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
 		       "***Enter PwrTrk BBSWING_MODE***\n");
@@ -780,7 +792,7 @@ void odm_txpowertracking_callback_thermal_meter(void *adapter)

 	/* Wait sacn to do IQK by RF Jenyu*/
 	if (!(*dm->is_scan_in_process) && !iqk_info->rfk_forbidden &&
-	    !cali_info->is_iqk_in_progress) {
+	    !cali_info->is_iqk_in_progress && dm->is_linked) {
 		if (!(dm->support_ic_type & ODM_RTL8723B)) {
 			/*Delta temperature is equal or larger than 20 Celsius*/
 			/*When threshold is 8*/
@@ -840,7 +852,7 @@ void odm_txpowertracking_callback_thermal_meter(void *adapter)
 	cali_info->tx_powercount = 0;
 }

-#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
+#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1  || RTL8723F_SUPPORT == 1)
 void
 odm_txpowertracking_new_callback_thermal_meter(void *dm_void)
 {
@@ -895,11 +907,17 @@ odm_txpowertracking_new_callback_thermal_meter(void *dm_void)
 			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0x7e); /* 0x42: RF Reg[6:1] Thermal Trim*/
 	} else {
 		for (i = 0; i < c.rf_path_count; i++) {
-			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10]*/
-			thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_thermal_offset(dm);
+			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */

-			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-				"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + power_time_thermal(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_thermal_offset(dm));
+			if (dm->support_ic_type == ODM_RTL8814B) {
+				thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_multi_thermal_offset(dm, i);
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + multi_thermal_trim(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_multi_thermal_offset(dm, i));
+			} else {
+				thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_thermal_offset(dm);
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + thermal_trim(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_thermal_offset(dm));
+			}

 			if (thermal_value_temp[i] > 63)
 				thermal_value[i] = 63;
@@ -1048,7 +1066,7 @@ odm_txpowertracking_new_callback_thermal_meter(void *dm_void)
 			(*c.odm_tx_pwr_track_set_pwr)(dm, tracking_method, p, 0);

 	/* Wait sacn to do IQK by RF Jenyu*/
-	if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
+	if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden) && (dm->is_linked || *dm->mp_mode)) {
 		/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
 		if (delta_IQK >= c.threshold_iqk) {
 			cali_info->thermal_value_iqk = thermal_value[RF_PATH_A];
--- a/hal/phydm/halrf/halphyrf_ce.h
+++ b/hal/phydm/halrf/halphyrf_ce.h
@@ -49,6 +49,7 @@
 #if (RTL8814B_SUPPORT == 1)
 	#include "halrf/rtl8814b/halrf_iqk_8814b.h"	
 	#include "halrf/rtl8814b/halrf_dpk_8814b.h"
+	#include "halrf/rtl8814b/halrf_txgapk_8814b.h"
 #endif

 #include "halrf/halrf_powertracking_ce.h"
--- a/hal/phydm/halrf/halphyrf_iot.c
+++ b/hal/phydm/halrf/halphyrf_iot.c
@@ -125,6 +125,7 @@ odm_txpowertracking_callback_thermal_meter(
 	u8 power_tracking_type = rf->pwt_type;
 	u8 xtal_offset_eanble = 0;
 	s8 thermal_value_temp = 0;
+	u8 xtal_track_efuse = 0;

 	struct txpwrtrack_cfg	c = {0};

@@ -157,9 +158,12 @@ odm_txpowertracking_callback_thermal_meter(
 #endif

 	/*for Xtal Offset*/
+	odm_efuse_one_byte_read(dm, 0xf7, &xtal_track_efuse, false);
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Read efuse 0xf7=0x%x\n", xtal_track_efuse);
+	xtal_track_efuse = xtal_track_efuse & 0x3;
 	if (dm->support_ic_type == ODM_RTL8195B ||
 	    dm->support_ic_type == ODM_RTL8721D ||
-	    dm->support_ic_type == ODM_RTL8710C)
+	    (dm->support_ic_type == ODM_RTL8710C && xtal_track_efuse == 0x2))
 		(*c.get_delta_swing_xtal_table)(dm,
 		 (s8 **)&delta_swing_table_xtal_up,
 		 (s8 **)&delta_swing_table_xtal_down);
@@ -316,7 +320,7 @@ odm_txpowertracking_callback_thermal_meter(
 			/* JJ ADD 20161014 */
 			if (dm->support_ic_type == ODM_RTL8195B ||
 			    dm->support_ic_type == ODM_RTL8721D ||
-			    dm->support_ic_type == ODM_RTL8710C) {
+			    (dm->support_ic_type == ODM_RTL8710C && xtal_track_efuse == 0x2)) {
 				/*Save xtal_offset from Xtal table*/
 				cali_info->xtal_offset_last = cali_info->xtal_offset;	/*recording last Xtal offset*/
 				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
@@ -371,7 +375,7 @@ odm_txpowertracking_callback_thermal_meter(

 			if (dm->support_ic_type == ODM_RTL8195B ||
 			    dm->support_ic_type == ODM_RTL8721D ||
-			    dm->support_ic_type == ODM_RTL8710C) {
+			    (dm->support_ic_type == ODM_RTL8710C && xtal_track_efuse == 0x2)) {
 				/*Save xtal_offset from Xtal table*/
 				cali_info->xtal_offset_last = cali_info->xtal_offset;	/*recording last Xtal offset*/
 				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
@@ -539,9 +543,17 @@ odm_txpowertracking_callback_thermal_meter(
 	}
 #endif
 	/* JJ ADD 20161014 */
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			"cali_info->xtal_offset_last=%d   cali_info->xtal_offset=%d\n",
+			cali_info->xtal_offset_last, cali_info->xtal_offset);
+
+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+			"xtal_offset_eanble=%d   cali_info->txpowertrack_control=%d   rf->eeprom_thermal=%d xtal_track_efuse=%d\n",
+			xtal_offset_eanble, cali_info->txpowertrack_control, rf->eeprom_thermal, xtal_track_efuse);
+
 	if (dm->support_ic_type == ODM_RTL8195B ||
 	    dm->support_ic_type == ODM_RTL8721D ||
-	    dm->support_ic_type == ODM_RTL8710C) {
+	    (dm->support_ic_type == ODM_RTL8710C && xtal_track_efuse == 0x2)) {
 		if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (rf->eeprom_thermal != 0xff)) {
 			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");

@@ -559,7 +571,7 @@ odm_txpowertracking_callback_thermal_meter(
 	}
 #if (!RTL8721D_SUPPORT)
 	/* Wait sacn to do IQK by RF Jenyu*/
-	if ((!*dm->is_scan_in_process) && (!iqk_info->rfk_forbidden)) {
+	if ((!*dm->is_scan_in_process) && (!iqk_info->rfk_forbidden) && (dm->is_linked || *dm->mp_mode)) {
 		/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
 		if (delta_IQK >= c.threshold_iqk) {
 			cali_info->thermal_value_iqk = thermal_value;
--- a/hal/phydm/halrf/halphyrf_win.c
+++ b/hal/phydm/halrf/halphyrf_win.c
@@ -109,6 +109,10 @@ void configure_txpower_track(
 		configure_txpower_track_8814b(config);
 #endif

+#if RTL8723F_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8723F)
+		configure_txpower_track_8723f(config);
+#endif

 }

@@ -230,8 +234,11 @@ odm_txpowertracking_callback_thermal_meter(
 	<Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 #if (MP_DRIVER == 1)
+#ifndef RTL8723F_SUPPORT
 	cali_info->rega24 = 0x090e1317;
 #endif
+#endif
+
 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
 	if (*(dm->mp_mode) == true)
 		cali_info->rega24 = 0x090e1317;
@@ -700,7 +707,7 @@ odm_txpowertracking_callback_thermal_meter(
 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)

 	/* Wait sacn to do IQK by RF Jenyu*/
-	if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
+	if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden) && dm->is_linked) {
 		if (!IS_HARDWARE_TYPE_8723B(adapter)) {
 			/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
 			if (delta_IQK >= c.threshold_iqk) {
@@ -753,7 +760,7 @@ odm_txpowertracking_callback_thermal_meter(
 	cali_info->tx_powercount = 0;
 }

-#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
+#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1  || RTL8723F_SUPPORT == 1)
 void
 odm_txpowertracking_new_callback_thermal_meter(void *dm_void)
 {
@@ -808,11 +815,17 @@ odm_txpowertracking_new_callback_thermal_meter(void *dm_void)
 			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0x7e);	/* 0x42: RF Reg[6:1] Thermal Trim*/
 	} else {
 		for (i = 0; i < c.rf_path_count; i++) {
-			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10]*/
-			thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_thermal_offset(dm);
+			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */

-			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-				"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + power_time_thermal(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_thermal_offset(dm));
+			if (dm->support_ic_type == ODM_RTL8814B) {
+				thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_multi_thermal_offset(dm, i);
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + multi_thermal_trim(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_multi_thermal_offset(dm, i));
+			} else {
+				thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_thermal_offset(dm);
+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
+					"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + thermal_trim(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_thermal_offset(dm));
+			}

 			if (thermal_value_temp[i] > 63)
 				thermal_value[i] = 63;
@@ -871,7 +884,9 @@ odm_txpowertracking_new_callback_thermal_meter(void *dm_void)
 			cali_info->thermal_value_lck = thermal_value[RF_PATH_A];

 			/*Use RTLCK, so close power tracking driver LCK*/
-			if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
+			if ((!(dm->support_ic_type & ODM_RTL8814A)) &&
+			    (!(dm->support_ic_type & ODM_RTL8822B)) &&
+			    (!(dm->support_ic_type & ODM_RTL8723F))) {
 				if (c.phy_lc_calibrate)
 					(*c.phy_lc_calibrate)(dm);
 			} else
@@ -960,7 +975,7 @@ odm_txpowertracking_new_callback_thermal_meter(void *dm_void)
 			(*c.odm_tx_pwr_track_set_pwr)(dm, tracking_method, p, 0);

 	/* Wait sacn to do IQK by RF Jenyu*/
-	if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
+	if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden) && (dm->is_linked || *dm->mp_mode)) {
 		/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
 		if (delta_IQK >= c.threshold_iqk) {
 			cali_info->thermal_value_iqk = thermal_value[RF_PATH_A];
@@ -1026,26 +1041,39 @@ odm_iq_calibrate(
 	if (*dm->is_fcs_mode_enable)
 		return;
 #endif
+	if (dm->is_linked) {
+		RF_DBG(dm, DBG_RF_IQK,
+		       "interval=%d ch=%d prech=%d scan=%s rfk_f =%s\n",
+		       dm->linked_interval, *dm->channel,  dm->pre_channel,
+		       *dm->is_scan_in_process == TRUE ? "TRUE":"FALSE",
+		       iqk_info->rfk_forbidden == TRUE ? "TRUE":"FALSE");

-	if ((dm->is_linked) && (!iqk_info->rfk_forbidden)) {
-		RF_DBG(dm, DBG_RF_IQK, "interval=%d ch=%d prech=%d scan=%s\n", dm->linked_interval,
-		       *dm->channel,  dm->pre_channel, *dm->is_scan_in_process == TRUE ? "TRUE":"FALSE");
+		if (iqk_info->rfk_forbidden)	{
+			RF_DBG(dm, DBG_RF_IQK, "return by rfk_forbidden\n");
+			return;
+		}
+
+		if (*dm->is_scan_in_process)	{
+			RF_DBG(dm, DBG_RF_IQK, "return by is_scan_in_process\n");
+			return;
+		}

 		if (*dm->channel != dm->pre_channel) {
 			dm->pre_channel = *dm->channel;
 			dm->linked_interval = 0;
 		}

-		if ((dm->linked_interval < 3) && (!*dm->is_scan_in_process))
+		if (dm->linked_interval < 3)
 			dm->linked_interval++;

 		if (dm->linked_interval == 2)
 			PHY_IQCalibrate(adapter, false);
-	} else
+	} else {
 		dm->linked_interval = 0;
-
-		RF_DBG(dm, DBG_RF_IQK, "<=%s interval=%d ch=%d prech=%d scan=%s\n", __FUNCTION__, dm->linked_interval,
-			*dm->channel,  dm->pre_channel, *dm->is_scan_in_process == TRUE?"TRUE":"FALSE");
+		RF_DBG(dm, DBG_RF_IQK, "is_linked =%s, interval =%d\n",
+		       dm->is_linked == TRUE ? "TRUE":"FALSE",
+		       dm->linked_interval);		
+	}
 }

 void phydm_rf_init(struct dm_struct		*dm)
--- a/hal/phydm/halrf/halphyrf_win.h
+++ b/hal/phydm/halrf/halphyrf_win.h
@@ -40,6 +40,7 @@

 #if (RTL8814B_SUPPORT == 1)
 	#include "halrf/rtl8814b/halrf_iqk_8814b.h"
+	#include "halrf/rtl8814b/halrf_txgapk_8814b.h"
 #endif

 enum spur_cal_method {
--- a/hal/phydm/halrf/halrf.c
+++ b/hal/phydm/halrf/halrf.c
--- a/hal/phydm/halrf/halrf.h
+++ b/hal/phydm/halrf/halrf.h
@@ -38,6 +38,7 @@
 #include "halrf/rtl8822c/halrf_iqk_8822c.h"
 #include "halrf/rtl8822c/halrf_tssi_8822c.h"
 #include "halrf/rtl8822c/halrf_dpk_8822c.h"
+#include "halrf/rtl8822c/halrf_txgapk_8822c.h"
 #endif

 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
@@ -57,6 +58,7 @@
 #include "halrf/rtl8814b/halrf_rfk_init_8814b.h"
 #include "halrf/rtl8814b/halrf_iqk_8814b.h"
 #include "halrf/rtl8814b/halrf_dpk_8814b.h"
+#include "halrf/rtl8814b/halrf_txgapk_8814b.h"
 #endif

 /*@============================================================*/
@@ -69,12 +71,12 @@
 #define IQK_VER_8192F "0x01"
 #define IQK_VER_8723B "0x1e"
 #define IQK_VER_8812A "0x02"
-#define IQK_VER_8821A "0x01"
+#define IQK_VER_8821A "0x02"
 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
 #define IQK_VER_8188E "0x01"
 #define IQK_VER_8192E "0x01"
 #define IQK_VER_8192F "0x01"
-#define IQK_VER_8723B "0x1e"
+#define IQK_VER_8723B "0x1f"
 #define IQK_VER_8812A "0x01"
 #define IQK_VER_8821A "0x01"
 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
@@ -99,19 +101,21 @@
 #define IQK_VER_8710B "0x01"
 #define IQK_VER_8723D "0x02"
 #define IQK_VER_8822B "0x32"
-#define IQK_VER_8822C "0x0c"
+#define IQK_VER_8822C "0x14"
 #define IQK_VER_8821C "0x23"
-#define IQK_VER_8198F "0x0a"
-#define IQK_VER_8814B "0x0e"
-#define IQK_VER_8812F "0x08"
-#define IQK_VER_8710C "0x05"
-#define IQK_VER_8197G "0x02"
+#define IQK_VER_8198F "0x0b"
+#define IQK_VER_8814B "0x15"
+#define IQK_VER_8812F "0x0c"
+#define IQK_VER_8710C "0x0a"
+#define IQK_VER_8197G "0x03"
+#define IQK_VER_8723F "0x00"
+

 /*LCK version*/
-#define LCK_VER_8188E "0x01"
-#define LCK_VER_8192E "0x01"
+#define LCK_VER_8188E "0x02"
+#define LCK_VER_8192E "0x02"
 #define LCK_VER_8192F "0x01"
-#define LCK_VER_8723B "0x01"
+#define LCK_VER_8723B "0x02"
 #define LCK_VER_8812A "0x01"
 #define LCK_VER_8821A "0x01"
 #define LCK_VER_8814A "0x01"
@@ -122,11 +126,12 @@
 #define LCK_VER_8723D "0x01"
 #define LCK_VER_8822B "0x02"
 #define LCK_VER_8822C "0x00"
-#define LCK_VER_8821C "0x02"
-#define LCK_VER_8814B "0x01"
+#define LCK_VER_8821C "0x03"
+#define LCK_VER_8814B "0x02"
 #define LCK_VER_8195B "0x02"
-#define LCK_VER_8710C "0x01"
-#define LCK_VER_8197G "0x00"
+#define LCK_VER_8710C "0x02"
+#define LCK_VER_8197G "0x01"
+#define LCK_VER_8198F "0x01"

 /*power tracking version*/
 #define PWRTRK_VER_8188E "0x01"
@@ -160,27 +165,31 @@
 #define DPK_VER_8710B "NONE"
 #define DPK_VER_8723D "NONE"
 #define DPK_VER_8822B "NONE"
-#define DPK_VER_8822C "0x19"
+#define DPK_VER_8822C "0x20"
 #define DPK_VER_8821C "NONE"
-#define DPK_VER_8192F "0x0d"
+#define DPK_VER_8192F "0x11"
 #define DPK_VER_8198F "0x0e"
-#define DPK_VER_8814B "0x08"
-#define DPK_VER_8195B "0x0b"
-#define DPK_VER_8812F "0x06"
-#define DPK_VER_8197G "0x04"
+#define DPK_VER_8814B "0x0f"
+#define DPK_VER_8195B "0x0c"
+#define DPK_VER_8812F "0x0a"
+#define DPK_VER_8197G "0x09"

 /*RFK_INIT version*/
 #define RFK_INIT_VER_8822B "0x8"
-#define RFK_INIT_VER_8822C "0x7"
+#define RFK_INIT_VER_8822C "0x8"
 #define RFK_INIT_VER_8195B "0x1"
 #define RFK_INIT_VER_8198F "0x8"
 #define RFK_INIT_VER_8814B "0xa"
-#define RFK_INIT_VER_8812F "0x3"
-#define RFK_INIT_VER_8197G "0x3"
+#define RFK_INIT_VER_8812F "0x4"
+#define RFK_INIT_VER_8197G "0x4"

 /*DACK version*/
-#define DACK_VER_8822C "0x6"
-#define DACK_VER_8814B "0x3"
+#define DACK_VER_8822C "0xa"
+#define DACK_VER_8814B "0x4"
+
+/*TXGAPK version*/
+#define TXGAPK_VER_8814B "0x1"
+#define TXGAPK_VER_8195B "0x2"

 /*Kfree tracking version*/
 #define KFREE_VER_8188E \
@@ -223,6 +232,7 @@
 #define TSSI_VER_8821C "0x1"
 #define TSSI_VER_8814B "0x1"
 #define TSSI_VER_8197G "0x1"
+#define TSSI_VER_8723F "0x1"

 /*PA Bias Calibration version*/
 #define PABIASK_VER_8188E \
@@ -278,6 +288,7 @@
 	(dm->support_ic_type == ODM_RTL8821C) ? IQK_VER_8821C : \
 	(dm->support_ic_type == ODM_RTL8814B) ? IQK_VER_8814B : \
 	(dm->support_ic_type == ODM_RTL8710C) ? IQK_VER_8710C : \
+	(dm->support_ic_type == ODM_RTL8723F) ? IQK_VER_8723F : \
 	(dm->support_ic_type == ODM_RTL8197G) ? IQK_VER_8197G : "unknown"

 #define HALRF_LCK_VER \
@@ -333,6 +344,7 @@
 	(dm->support_ic_type == ODM_RTL8723D) ? DPK_VER_8723D : \
 	(dm->support_ic_type == ODM_RTL8822B) ? DPK_VER_8822B : \
 	(dm->support_ic_type == ODM_RTL8822C) ? DPK_VER_8822C : \
+	(dm->support_ic_type == ODM_RTL8812F) ? DPK_VER_8812F : \
 	(dm->support_ic_type == ODM_RTL8821C) ? DPK_VER_8821C : \
 	(dm->support_ic_type == ODM_RTL8814B) ? DPK_VER_8814B : \
 	(dm->support_ic_type == ODM_RTL8197G) ? DPK_VER_8197G : "unknown"
@@ -361,7 +373,8 @@
 	(dm->support_ic_type == ODM_RTL8822C) ? TSSI_VER_8822C : \
 	(dm->support_ic_type == ODM_RTL8821C) ? TSSI_VER_8821C : \
 	(dm->support_ic_type == ODM_RTL8814B) ? TSSI_VER_8814B : \
-	(dm->support_ic_type == ODM_RTL8197G) ? TSSI_VER_8197G : "unknown"
+	(dm->support_ic_type == ODM_RTL8197G) ? TSSI_VER_8197G : \
+	(dm->support_ic_type == ODM_RTL8723F) ? TSSI_VER_8723F : "unknown"

 #define HALRF_PABIASK_VER \
 	(dm->support_ic_type == ODM_RTL8188E) ? PABIASK_VER_8188E : \
@@ -385,6 +398,7 @@
 #define HALRF_RFK_INIT_VER \
 	(dm->support_ic_type == ODM_RTL8822B) ? RFK_INIT_VER_8822B : \
 	(dm->support_ic_type == ODM_RTL8822C) ? RFK_INIT_VER_8822C : \
+	(dm->support_ic_type == ODM_RTL8812F) ? RFK_INIT_VER_8812F : \
 	(dm->support_ic_type == ODM_RTL8198F) ? RFK_INIT_VER_8198F : \
 	(dm->support_ic_type == ODM_RTL8814B) ? RFK_INIT_VER_8814B : \
 	(dm->support_ic_type == ODM_RTL8197G) ? RFK_INIT_VER_8197G : "unknown"
@@ -423,7 +437,9 @@ enum halrf_func_idx { /*F_XXX = PHYDM XXX function*/
 	RF04_TXGAPK = 4,
 	RF05_DACK = 5,
 	RF06_DPK_TRK = 6,
-	RF07_2GBAND_SHIFT = 7
+	RF07_2GBAND_SHIFT = 7,
+	RF08_RXDCK = 8,
+	RF09_RFK = 9
 };

 enum halrf_ability {
@@ -434,7 +450,8 @@ enum halrf_ability {
 	HAL_RF_TXGAPK = BIT(RF04_TXGAPK),
 	HAL_RF_DACK = BIT(RF05_DACK),
 	HAL_RF_DPK_TRACK = BIT(RF06_DPK_TRK),
-	HAL_2GBAND_SHIFT = BIT(RF07_2GBAND_SHIFT)
+	HAL_2GBAND_SHIFT = BIT(RF07_2GBAND_SHIFT),
+	HAL_RF_RXDCK = BIT(RF08_RXDCK)
 };

 enum halrf_shift_band {
@@ -450,6 +467,8 @@ enum halrf_dbg_comp {
 	DBG_RF_DPK = BIT(RF03_DPK),
 	DBG_RF_TXGAPK = BIT(RF04_TXGAPK),
 	DBG_RF_DACK = BIT(RF05_DACK),
+	DBG_RF_DPK_TRACK = BIT(RF06_DPK_TRK),
+	DBG_RF_RFK = BIT(RF09_RFK),
 	DBG_RF_MP = BIT(29),
 	DBG_RF_TMP = BIT(30),
 	DBG_RF_INIT = BIT(31)
@@ -467,7 +486,9 @@ enum halrf_cmninfo_init {
 	HALRF_CMNINFO_MP_PSD_START_POINT,
 	HALRF_CMNINFO_MP_PSD_STOP_POINT,
 	HALRF_CMNINFO_MP_PSD_AVERAGE,
-	HALRF_CMNINFO_IQK_TIMES
+	HALRF_CMNINFO_IQK_TIMES,
+	HALRF_CMNINFO_MP_POWER_TRACKING_TYPE,
+	HALRF_CMNINFO_POWER_TRACK_CONTROL
 };

 enum halrf_cmninfo_hook {
@@ -500,6 +521,7 @@ enum halrf_k_segment_time {

 #define TSSI_EFUSE_NUM 25
 #define TSSI_EFUSE_KFREE_NUM 4
+#define TSSI_DE_DIFF_EFUSE_NUM 10

 struct _halrf_tssi_data {
 	s32 cck_offset_patha;
@@ -509,6 +531,7 @@ struct _halrf_tssi_data {
 	s16 txagc_codeword[TSSI_CODE_NUM];
 	u16 tssi_codeword[TSSI_CODE_NUM];
 	s8 tssi_efuse[PHYDM_MAX_RF_PATH][TSSI_EFUSE_NUM];
+	s8 tssi_de_diff_efuse[PHYDM_MAX_RF_PATH][TSSI_DE_DIFF_EFUSE_NUM];
 	s8 tssi_kfree_efuse[PHYDM_MAX_RF_PATH][TSSI_EFUSE_KFREE_NUM];
 	u8 thermal[PHYDM_MAX_RF_PATH];
 	u32 index[PHYDM_MAX_RF_PATH][14];
@@ -516,8 +539,18 @@ struct _halrf_tssi_data {
 	u8 get_thermal;
 	u8 tssi_finish_bit[PHYDM_MAX_RF_PATH];
 	u8 thermal_trigger;
+	s8 tssi_de;
 };

+struct _halrf_txgapk_info {
+	u32 txgapk_rf3f_bp[5][12][PHYDM_MAX_RF_PATH]; /* band(2Gcck/2GOFDM/5GL/5GM/5GH)/idx/path */
+	boolean txgapk_bp_done;
+	s8 offset[12][PHYDM_MAX_RF_PATH];
+	s8 fianl_offset[12][PHYDM_MAX_RF_PATH];
+	u8 read_txgain;
+};
+
+
 /*@============================================================*/
 /*@ structure */
 /*@============================================================*/
@@ -544,18 +577,29 @@ struct _hal_rf_ {
 	boolean is_dpk_in_progress;
 	boolean is_tssi_in_progress;
 	boolean is_bt_iqk_timeout;
+	boolean is_rfk_h2c_timeout;
 	boolean aac_checked;
+	boolean is_txgapk_in_progress;

 	u8 *mp_rate_index;
 	u32 *manual_rf_supportability;
 	u32 p_rate_index;
 	u8 pwt_type;
 	u32 rf_dbg_comp;
+	u8 rfk_type;
+	u32 gnt_control;
+
+	u8 ext_lna;		/*@with 2G external LNA  NO/Yes = 0/1*/
+	u8 ext_lna_5g;		/*@with 5G external LNA  NO/Yes = 0/1*/
+	u8 ext_pa;		/*@with 2G external PNA  NO/Yes = 0/1*/
+	u8 ext_pa_5g;		/*@with 5G external PNA  NO/Yes = 0/1*/
 #if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
 	struct _halrf_psd_data halrf_psd_data;
 	struct _halrf_tssi_data halrf_tssi_data;
 #endif
+	struct _halrf_txgapk_info halrf_txgapk_info;
 	u8 power_track_type;
+	u8 mp_pwt_type;
 	u8 pre_band_type;
 };

@@ -625,6 +669,8 @@ u32 halrf_psd_log2base(u32 val);

 void halrf_dpk_trigger(void *dm_void);

+void halrf_txgapk_trigger(void *dm_void);
+
 u8 halrf_dpk_result_check(void *dm_void);

 void halrf_dpk_sram_read(void *dm_void);
@@ -635,6 +681,13 @@ void halrf_dpk_track(void *dm_void);

 void halrf_dpk_reload(void *dm_void);

+void halrf_dpk_switch(void *dm_void, u8 enable);
+
+void halrf_dpk_debug_cmd(void *dm_void, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len);
+
+void halrf_dpk_c2h_report_transfer(void	*dm_void, boolean is_ok, u8 *buf, u8 buf_size);
+
 void halrf_dpk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size);

 /*Global function*/
@@ -677,6 +730,8 @@ void halrf_tssi_get_efuse(void *dm_void);

 void halrf_do_tssi(void *dm_void);

+void halrf_set_tssi_enable(void *dm_void, boolean enable);
+
 void halrf_do_thermal(void *dm_void);

 u32 halrf_set_tssi_value(void *dm_void, u32 tssi_value);
@@ -701,10 +756,22 @@ void halrf_set_tssi_codeword(void *dm_void);

 u8 halrf_get_tssi_codeword_for_txindex(void *dm_void);

+void halrf_tssi_clean_de(void *dm_void);
+
+u32 halrf_tssi_trigger_de(void *dm_void, u8 path);
+
 u32 halrf_tssi_get_de(void *dm_void, u8 path);

+u32 halrf_get_online_tssi_de(void *dm_void, u8 path, s32 pout);
+
 void halrf_tssi_trigger(void *dm_void);

+void halrf_txgapk_write_gain_table(void *dm_void);
+
+void halrf_txgapk_reload_tx_gain(void *dm_void);
+
+void halrf_txgap_enable_disable(void *dm_void, u8 enable);
+
 void halrf_set_dpk_track(void *dm_void, u8 enable);

 void halrf_set_dpkbychannel(void *dm_void, boolean dpk_by_ch);
@@ -725,7 +792,23 @@ void halrf_reload_iqk(void *dm_void, boolean reset);

 void halrf_dack_dbg(void *dm_void);

+void halrf_dack_trigger(void *dm_void, boolean force);
+
+void halrf_dack_restore(void *dm_void);
+
 void halrf_iqk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size);

 void halrf_set_rfsupportability(void *dm_void);
+
+void halrf_rxdck(void *dm_void);
+
+void halrf_delay_10us(u16 v1);
+
+void halrf_dump_rfk_reg(void *dm_void, char input[][16], u32 *_used,
+			      char *output, u32 *_out_len);
+
+void halrf_xtal_thermal_track(void *dm_void);
+
+void halrf_rfk_power_save(void *dm_void, boolean is_power_save);
+
 #endif /*__HALRF_H__*/
--- a/hal/phydm/halrf/halrf_debug.c
+++ b/hal/phydm/halrf/halrf_debug.c
@@ -89,7 +89,7 @@ void halrf_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len)
 #endif

 #if (RTL8192F_SUPPORT)
-	case ODM_RTL8197F:
+	case ODM_RTL8192F:
 		rf_release_ver = RF_RELEASE_VERSION_8192F;
 		break;
 #endif
@@ -173,6 +173,9 @@ void halrf_debug_trace(void *dm_void, char input[][16], u32 *_used,
 		PDM_SNPF(out_len, used, output + used, out_len - used,
 			 "04. (( %s ))TXGAPK\n",
 			 ((rf->rf_dbg_comp & DBG_RF_TXGAPK) ? ("V") : (".")));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "06. (( %s ))DPK_TRACK\n",
+			 ((rf->rf_dbg_comp & DBG_RF_DPK_TRACK) ? ("V") : (".")));
 		PDM_SNPF(out_len, used, output + used, out_len - used,
 			 "29. (( %s ))MP\n",
 			 ((rf->rf_dbg_comp & DBG_RF_MP) ? ("V") : (".")));
@@ -200,6 +203,23 @@ void halrf_debug_trace(void *dm_void, char input[][16], u32 *_used,
 	*_out_len = out_len;
 }

+void halrf_dack_debug_cmd(void *dm_void, char input[][16])
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct _hal_rf_ *rf = &dm->rf_table;
+	u32 dm_value[10] = {0};
+	u8 i;
+
+	for (i = 0; i < 7; i++)
+		if (input[i + 1])
+			PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &dm_value[i]);
+
+	if (dm_value[0] == 1)
+		halrf_dack_trigger(dm, true);
+	else			
+		halrf_dack_trigger(dm, false);	
+}
+
 struct halrf_command {
 	char name[16];
 	u8 id;
@@ -214,6 +234,9 @@ enum halrf_CMD_ID {
 	HALRF_IQK,
 	HALRF_IQK_DEBUG,
 	HALRF_DPK,
+	HALRF_DACK,
+	HALRF_DACK_DEBUG,
+	HALRF_DUMP_RFK_REG,
 #ifdef CONFIG_2G_BAND_SHIFT
 	HAL_BAND_SHIFT,
 #endif
@@ -226,8 +249,11 @@ struct halrf_command halrf_cmd_ary[] = {
 	{"profile", HALRF_PROFILE},
 	{"iqk_info", HALRF_IQK_INFO},
 	{"iqk", HALRF_IQK},
-	{"dpk", HALRF_DPK},
 	{"iqk_dbg", HALRF_IQK_DEBUG},
+	{"dpk", HALRF_DPK},
+	{"dack", HALRF_DACK},
+	{"dack_dbg", HALRF_DACK_DEBUG},
+	{"dump_rfk_reg", HALRF_DUMP_RFK_REG},
 #ifdef CONFIG_2G_BAND_SHIFT
 	{"band_shift", HAL_BAND_SHIFT},
 #endif
@@ -300,7 +326,8 @@ void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
 #endif
 		break;
 	case HALRF_IQK_DEBUG:
-
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "IQK DEBUG!!!!!\n");
 		for (i = 0; i < 5; i++) {
 			if (input[i + 1]) {
 				PHYDM_SSCANF(input[i + 2], DCMD_HEX,
@@ -310,17 +337,28 @@ void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
 		}

 		if (input_idx >= 1) {
-#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
-			if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C))
+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
+			if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8822C | ODM_RTL8814B))
 				halrf_iqk_debug(dm, (u32 *)rf_var, &used,
 						output, &out_len);
 #endif
 		}
 		break;
 	case HALRF_DPK:
+		halrf_dpk_debug_cmd(dm, input, &used, output, &out_len);
+		break;
+	case HALRF_DACK:
 		PDM_SNPF(out_len, used, output + used, out_len - used,
-			 "DPK Trigger\n");
-		halrf_dpk_trigger(dm);
+			 "DACK Trigger\n");
+		halrf_dack_debug_cmd(dm, &input[0]);
+		break;
+	case HALRF_DACK_DEBUG:
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "DACK DEBUG\n");
+		halrf_dack_dbg(dm);
+		break;
+	case HALRF_DUMP_RFK_REG:
+		halrf_dump_rfk_reg(dm, input, &used, output, &out_len);
 		break;
 	default:
 		break;
@@ -337,15 +375,18 @@ void halrf_init_debug_setting(void *dm_void)
 	struct _hal_rf_ *rf = &dm->rf_table;

 	rf->rf_dbg_comp =
+
+	DBG_RF_RFK		|
 #if DBG
-#if 0
-	/*DBG_RF_TX_PWR_TRACK	|*/
+#if 1
+	/*DBG_RF_TX_PWR_TRACK	| */
 	/*DBG_RF_IQK		| */
 	/*DBG_RF_LCK		| */
 	/*DBG_RF_DPK		| */
-	/*DBG_RF_DACK		| */
 	/*DBG_RF_TXGAPK		| */
-	/*DBG_RF_MP			| */
+	/*DBG_RF_DACK		| */
+	/*DBG_RF_DPK_TRACK	| */ 
+	/*DBG_RF_MP		| */
 	/*DBG_RF_TMP		| */
 	/*DBG_RF_INIT		| */
 #endif
--- a/hal/phydm/halrf/halrf_debug.h
+++ b/hal/phydm/halrf/halrf_debug.h
@@ -96,6 +96,23 @@ static __inline void RF_DBG(PDM_ODM_T dm, int comp, char *fmt, ...)
 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 static __inline void RF_DBG(struct dm_struct *dm, int comp, char *fmt, ...)
 {
+#if 0
+	RT_STATUS rt_status;
+	va_list args;
+	char buf[128] = {0};/*PRINT_MAX_SIZE*/
+
+	if ((comp & dm->rf_table.rf_dbg_comp) == 0)
+		return;
+
+	if (NULL != fmt) {
+		va_start(args, fmt);
+		rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, sizeof(buf), fmt, args);
+		va_end(args);
+		if (rt_status == RT_STATUS_SUCCESS) {
+			halrf_rt_trace(buf);
+		}
+	}
+#endif
 }
 #else
 #define RF_DBG(dm, comp, fmt, args...)
--- a/hal/phydm/halrf/halrf_dpk.h
+++ b/hal/phydm/halrf/halrf_dpk.h
@@ -43,6 +43,22 @@
 #define AVG_THERMAL_NUM_DPK 8
 #define THERMAL_DPK_AVG_NUM 4

+/*define RF path numer*/
+#if (RTL8198F_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
+#define KPATH 4
+#elif (RTL8192F_SUPPORT == 1 || RTL8197F_SUPPORT == 1 ||RTL8197G_SUPPORT == 1 ||\
+	RTL8822C_SUPPORT == 1 || RTL8812F_SUPPORT == 1 || RTL8723F_SUPPORT == 1)
+#define KPATH 2
+#else
+#define KPATH 1
+#endif
+
+#if (RTL8814B_SUPPORT == 1 || RTL8721D_SUPPORT == 1)
+#define GROUP_5G 6
+#elif (RTL8195B_SUPPORT == 1)
+#define GROUP_5G 13
+#endif
+
 /*@---------------------------End Define Parameters---------------------------*/

 struct dm_dpk_info {
@@ -51,19 +67,30 @@ struct dm_dpk_info {
 	boolean	is_dpk_pwr_on;
 	boolean	is_dpk_by_channel;
 	boolean is_tssi_mode;
-	boolean is_reload;
-	u16 dpk_path_ok;
+	u8	dpk_status;			/*bit[0]:reload;bit[1]:cal;bit[2]:cal_ok*/
+	u16	dpk_path_ok;
 	/*@BIT(15)~BIT(12) : 5G reserved, BIT(11)~BIT(8) 5G_S3~5G_S0*/
 	/*@BIT(7)~BIT(4) : 2G reserved, BIT(3)~BIT(0) 2G_S3~2G_S0*/
-	u8	thermal_dpk[4];					/*path*/	
-	u8	thermal_dpk_avg[4][AVG_THERMAL_NUM_DPK];	/*path*/
-	u8	pre_pwsf[4];	
+	u8	thermal_dpk[KPATH];					/*path*/	
+	u8	thermal_dpk_avg[KPATH][AVG_THERMAL_NUM_DPK];	/*path*/
+	u8	pre_pwsf[KPATH];
 	u8	thermal_dpk_avg_index;
 	u32	gnt_control;
 	u32	gnt_value;
 	u8	dpk_ch;
 	u8	dpk_band;
 	u8	dpk_bw;
+	u32	dpk_rf18[2];
+	u32	dpk_cal_cnt;
+	u32	dpk_ok_cnt;
+	u32	dpk_reload_cnt;
+
+#if (RTL8822C_SUPPORT == 1 || RTL8812F_SUPPORT == 1 || RTL8197G_SUPPORT == 1)
+	u16	dc_i[2];			/*MDPD DC I path*/
+	u16	dc_q[2];			/*MDPD DC Q path*/
+	u8	corr_val[2];			/*Corr value path*/
+	u8	corr_idx[2];			/*Corr index path*/
+#endif

 #if (RTL8822C_SUPPORT == 1 || RTL8812F_SUPPORT == 1)
 	u8	result[2];			/*path*/
@@ -74,52 +101,63 @@ struct dm_dpk_info {
 #endif

 #if (RTL8198F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8197F_SUPPORT == 1 ||\
-     RTL8814B_SUPPORT == 1 || RTL8197G_SUPPORT == 1)
+	RTL8814B_SUPPORT == 1 || RTL8197G_SUPPORT == 1)
 	/*2G DPK data*/
-	u8 	dpk_result[4][3];		/*path/group*/
-	u8 	pwsf_2g[4][3];			/*path/group*/	
-	u32	lut_2g_even[4][3][64];		/*path/group/LUT data*/
-	u32	lut_2g_odd[4][3][64];		/*path/group/LUT data*/
+	u8 	dpk_result[KPATH][3];			/*path/group*/
+	u8 	pwsf_2g[KPATH][3];			/*path/group*/	
+	u32	lut_2g_even[KPATH][3][64];		/*path/group/LUT data*/
+	u32	lut_2g_odd[KPATH][3][64];		/*path/group/LUT data*/
 	s16	tmp_pas_i[32];			/*PAScan I data*/
 	s16	tmp_pas_q[32];			/*PAScan Q data*/
+#endif
+
+#if (RTL8814B_SUPPORT == 1)
 	/*5G DPK data*/
-	u8	dpk_5g_result[4][6];		/*path/group*/
-	u8	pwsf_5g[4][6];			/*path/group*/
-	u32	lut_5g[4][6][64];		/*path/group/LUT data*/
-	u32	lut_2g[4][3][64];		/*path/group/LUT data*/
-	/*8814B*/
+	u8	dpk_5g_result[KPATH][GROUP_5G];			/*path/group*/
+	u8	pwsf_5g[KPATH][GROUP_5G];			/*path/group*/
+	u32	lut_5g[KPATH][GROUP_5G][64];			/*path/group/LUT data*/
+	u32	lut_2g[KPATH][3][64];			/*path/group/LUT data*/
 	u8	rxbb[4];			/*path/group*/
 	u8	txbb[4];			/*path/group*/
 	u8	tx_gain;
 #endif

-#if (RTL8195B_SUPPORT == 1)
-		/*2G DPK data*/
-		u8	dpk_2g_result[1][3];		/*path/group*/
-		u8	pwsf_2g[1][3];			/*path/group*/
-		u32	lut_2g_even[1][3][16];		/*path/group/LUT data*/
-		u32	lut_2g_odd[1][3][16];		/*path/group/LUT data*/
-		/*5G DPK data*/
-		u8	dpk_5g_result[1][13];		/*path/group*/
-		u8	pwsf_5g[1][13];			/*path/group*/
-		u32	lut_5g_even[1][13][16];		/*path/group/LUT data*/
-		u32	lut_5g_odd[1][13][16];		/*path/group/LUT data*/
-#endif
-
-#if (RTL8721D_SUPPORT == 1)
+#if (RTL8195B_SUPPORT == 1 || RTL8721D_SUPPORT == 1)
 		u8	dpk_txagc;
 		/*2G DPK data*/
-		u8	dpk_2g_result[1][3];		/*path/group*/
-		u8	pwsf_2g[1][3];			/*path/group*/
-		u32	lut_2g_even[1][3][16];		/*path/group/LUT data*/
-		u32	lut_2g_odd[1][3][16];		/*path/group/LUT data*/
+	u8	dpk_2g_result[KPATH][3];			/*path/group*/
+	u8	pwsf_2g[KPATH][3];			/*path/group*/
+	u32	lut_2g_even[KPATH][3][16];		/*path/group/LUT data*/
+	u32	lut_2g_odd[KPATH][3][16];		/*path/group/LUT data*/
 		/*5G DPK data*/
-		u8	dpk_5g_result[1][6];		/*path/group*/
-		u8	pwsf_5g[1][6];			/*path/group*/
-		u32	lut_5g_even[1][6][16];		/*path/group/LUT data*/
-		u32	lut_5g_odd[1][6][16];		/*path/group/LUT data*/
+	u8	dpk_5g_result[KPATH][GROUP_5G];			/*path/group*/
+	u8	pwsf_5g[KPATH][GROUP_5G];			/*path/group*/
+	u32	lut_5g_even[KPATH][GROUP_5G][16];		/*path/group/LUT data*/
+	u32	lut_5g_odd[KPATH][GROUP_5G][16];		/*path/group/LUT data*/
 #endif

+#if(RTL8723F_SUPPORT == 1)
+	u8	one_shot_cnt;
+	u8	dpk_current_path;
+	u8	thermal_init[KPATH];
+	u8	dpk_delta_thermal[KPATH];		/*path*/
+	s8	last_offset[KPATH];			/*path*/
+	u8	txagc[KPATH];				/*path*/
+	u8	tssi_txagc[KPATH][2];			/*path/0:txagc_rf,1:tssi_offset*/
+	u16	digital_bbgain[KPATH];			/*path*/
+	u16	pwsf[KPATH];				/*path*/
+
+#endif
 };

+#if (RTL8822C_SUPPORT == 1)
+struct dm_dpk_c2h_report {
+	u8	result[2];		/*ch0_result/ch1_result*/
+	u8	therm[2][2];		/*therm0_s0/therm0_s1/therm1_s0/therm1_s1*/
+	u8	therm_delta[2][2];	/*therm_delta0_s0/therm_delta0_s1/therm_delta1_s0/therm_delta1_s1*/
+	u32	dpk_rf18[2];		/*dpk_ch0/dpk_ch1*/
+	u8	dpk_status;		/*dpk_status*/
+};
+#endif
+
 #endif /*__HALRF_DPK_H__*/
--- a/hal/phydm/halrf/halrf_iqk.h
+++ b/hal/phydm/halrf/halrf_iqk.h
@@ -39,16 +39,24 @@
 #define rxiqk_gs_limit 6
 #define TXWBIQK_EN 1
 #define RXWBIQK_EN 1
+#if (RTL8814A_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
+	RTL8814B_SUPPORT)
 #define NUM 4
+#elif (RTL8822B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
+	RTL8812F_SUPPORT == 1 || RTL8197G_SUPPORT == 1 ||\
+	RTL8723F_SUPPORT == 1)
+#define NUM 2
+#else
+#define NUM 1
+#endif
+
 /*@-----------------------End Define Parameters-----------------------*/

 struct dm_dack_info {
-	u32 ic_a;
-	u32 qc_a;
-	u32 ic_b;
-	u32 qc_b;
 	boolean dack_en;
 	u16 msbk_d[2][2][15];
+	u8 dck_d[2][2][2];
+	u16 biask_d[2][2];
 };

 struct dm_iqk_info {
@@ -70,37 +78,52 @@ struct dm_iqk_info {
 	u8 rxbb;
 	u32 rf_reg58;
 	boolean segment_iqk;
+	boolean is_tssi_mode;
+	u8 iqk_band;
+	u8 iqk_ch;
+	u8 iqk_bw;
 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
 	RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
 	RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
 	RTL8812F_SUPPORT == 1 || RTL8197G_SUPPORT == 1 ||\
-	RTL8710C_SUPPORT == 1)
+	RTL8710C_SUPPORT == 1 || RTL8723F_SUPPORT == 1)
 	u32 iqk_channel[2];
-	boolean iqk_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */
+	boolean iqk_fail_report[2][NUM][2]; /*channel/path/TRX(TX:0, RX:1) */
 	/*channel / path / TRX(TX:0, RX:1) / CFIR_real*/
 	/*channel index = 2 is just for debug*/
-#if (RTL8812F_SUPPORT == 1 || RTL8822C_SUPPORT == 1 )
+#if (RTL8814B_SUPPORT == 1)
+	u16 iqk_cfir_real[3][NUM][2][19];
+	u16 iqk_cfir_imag[3][NUM][2][19];
+#elif (RTL8812F_SUPPORT == 1 || RTL8822C_SUPPORT == 1 )
 	u16 iqk_cfir_real[3][2][2][17];
 	/*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
 	/*channel index = 2 is just for debug*/
 	u16 iqk_cfir_imag[3][2][2][17];
+	/*times/path*/
+#elif (RTL8195B_SUPPORT == 1)
+	u32 iqk_cfir_real[3][NUM][2][9];
+	u32 iqk_cfir_imag[3][NUM][2][9];
+	/*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
+	/*channel index = 2 is just for debug*/
+#else
+	u32 iqk_cfir_real[3][NUM][2][8];
+	/*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
+	/*channel index = 2 is just for debug*/
+	u32 iqk_cfir_imag[3][NUM][2][8];
+#endif
+
+#if (RTL8812F_SUPPORT == 1 || RTL8822C_SUPPORT == 1 )
 	u32 rx_cfir_real[2][2][17];
 	u32 rx_cfir_imag[2][2][17];
 	u32 rx_cfir[2][2];
-	/*times/path*/
-#else
-	u32 iqk_cfir_real[3][4][2][8];
-	/*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
-	/*channel index = 2 is just for debug*/
-	u32 iqk_cfir_imag[3][4][2][8];
 #endif
-	u8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */
-	u8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */
+	u8 retry_count[2][NUM][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */
+	u8 gs_retry_count[2][NUM][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */
 	/* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */
-	u8 rxiqk_fail_code[2][4];
-	u32 lok_idac[2][4]; /*channel / path*/
-	u16 rxiqk_agc[2][4]; /*channel / path*/
-	u32 bypass_iqk[2][4]; /*channel / 0xc94/0xe94*/
+	u8 rxiqk_fail_code[2][NUM];
+	u32 lok_idac[2][NUM]; /*channel / path*/
+	u16 rxiqk_agc[2][NUM]; /*channel / path*/
+	u32 bypass_iqk[2][NUM]; /*channel / 0xc94/0xe94*/
 	u32 txgap_result[8]; /*txagpK result  */
 	u32 tmp_gntwl;
 	boolean is_btg;
@@ -109,13 +132,25 @@ struct dm_iqk_info {
 	boolean is_hwtx;
 	boolean xym_read;
 	boolean trximr_enable;
+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
+	RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
 	u32 rx_xym[2][10];
 	u32 tx_xym[2][10];
 	u32 gs1_xym[2][6];
 	u32 gs2_xym[2][6];
 	u32 rxk1_xym[2][6];
+	u32 nbtxk_1b38[2];
+	u32 nbrxk_1b3c[2];
+#endif
+#if (RTL8710C_SUPPORT == 1 || RTL8197G_SUPPORT == 1 )
 	u32 txxy[2][2];
 	u32 rxxy[2][2];
+#endif
+#if (RTL8723F_SUPPORT == 1)
+	u32 txxy[2][2];
+	u32 rxxy[2][2][2];
+#endif
+
 #endif
 };

--- a/hal/phydm/halrf/halrf_kfree.c
+++ b/hal/phydm/halrf/halrf_kfree.c
--- a/hal/phydm/halrf/halrf_kfree.h
+++ b/hal/phydm/halrf/halrf_kfree.h
@@ -164,10 +164,15 @@
 #define PPG_5GH1_TXA_8721D 0x1E9

 /*8197G*/
-#define PPG_THERMAL_OFFSET_97G 0x50
+#define PPG_THERMAL_A_OFFSET_97G 0x50
+#define PPG_THERMAL_B_OFFSET_97G 0x27
 #define PPG_2GM_TXAB_97G 0x51
 #define PPG_2GL_TXAB_97G 0x53
 #define PPG_2GH_TXAB_97G 0x55
+#define TSSI_2GL_TXA_97G 0x1c
+#define TSSI_2GL_TXB_97G 0x1d
+#define TSSI_2GH_TXA_97G 0x1e
+#define TSSI_2GH_TXB_97G 0x1f
 #define PPG_PABIAS_2GAB_97G 0x57
 #define PPG_LNA_2GA_97G 0x21
 #define PPG_LNA_2GB_97G 0x22
@@ -180,13 +185,83 @@
 #define PPG_PABIAS_10C 0x1D6
 #define PPG_LNA_10C 0x1D0

+/*8814B*/
+#define PPG_2GL_TXAB_14B 0x3ee
+#define PPG_2GL_TXCD_14B 0x3ed
+#define PPG_5GL1_TXA_14B 0x3ec
+#define PPG_5GL1_TXB_14B 0x3eb
+#define PPG_5GL1_TXC_14B 0x3ea
+#define PPG_5GL1_TXD_14B 0x3e9
+#define PPG_5GL2_TXA_14B 0x3e8
+#define PPG_5GL2_TXB_14B 0x3e7
+#define PPG_5GL2_TXC_14B 0x3e6
+#define PPG_5GL2_TXD_14B 0x3e5
+#define PPG_5GM1_TXA_14B 0x3e4
+#define PPG_5GM1_TXB_14B 0x3e3
+#define PPG_5GM1_TXC_14B 0x3e2
+#define PPG_5GM1_TXD_14B 0x3e1
+#define PPG_5GM2_TXA_14B 0x3e0
+#define PPG_5GM2_TXB_14B 0x3df
+#define PPG_5GM2_TXC_14B 0x3de
+#define PPG_5GM2_TXD_14B 0x3dd
+#define PPG_5GH1_TXA_14B 0x3dc
+#define PPG_5GH1_TXB_14B 0x3db
+#define PPG_5GH1_TXC_14B 0x3da
+#define PPG_5GH1_TXD_14B 0x3d9
+#define PPG_PABIAS_5GAC_14B 0x3d8
+#define PPG_PABIAS_5GBD_14B 0x3d7
+#define PPG_PABIAS_2GAC_14B 0x3d6
+#define PPG_PABIAS_2GBD_14B 0x3d5
+
+#define PPG_THERMAL_A_OFFSET_14B 0x3D4
+#define PPG_THERMAL_B_OFFSET_14B 0x3D3
+#define PPG_THERMAL_C_OFFSET_14B 0x3D2
+#define PPG_THERMAL_D_OFFSET_14B 0x3D1
+
+#define TSSI_2GM_TXA_14B 0x3c0
+#define TSSI_2GM_TXB_14B 0x3bf
+#define TSSI_2GM_TXC_14B 0x3be
+#define TSSI_2GM_TXD_14B 0x3bd
+#define TSSI_2GH_TXA_14B 0x3bc
+#define TSSI_2GH_TXB_14B 0x3bb
+#define TSSI_2GH_TXC_14B 0x3ba
+#define TSSI_2GH_TXD_14B 0x3b9
+#define TSSI_5GL1_TXA_14B 0x3b8
+#define TSSI_5GL1_TXB_14B 0x3b7
+#define TSSI_5GL1_TXC_14B 0x3b6
+#define TSSI_5GL1_TXD_14B 0x3b5
+#define TSSI_5GL2_TXA_14B 0x3b4
+#define TSSI_5GL2_TXB_14B 0x3b3
+#define TSSI_5GL2_TXC_14B 0x3b2
+#define TSSI_5GL2_TXD_14B 0x3b1
+#define TSSI_5GM1_TXA_14B 0x3b0
+#define TSSI_5GM1_TXB_14B 0x3af
+#define TSSI_5GM1_TXC_14B 0x3ae
+#define TSSI_5GM1_TXD_14B 0x3ad
+#define TSSI_5GM2_TXA_14B 0x3ac
+#define TSSI_5GM2_TXB_14B 0x3ab
+#define TSSI_5GM2_TXC_14B 0x3aa
+#define TSSI_5GM2_TXD_14B 0x3a9
+#define TSSI_5GH1_TXA_14B 0x3a8
+#define TSSI_5GH1_TXB_14B 0x3a7
+#define TSSI_5GH1_TXC_14B 0x3a6
+#define TSSI_5GH1_TXD_14B 0x3a5
+#define TSSI_5GH2_TXA_14B 0x3a4
+#define TSSI_5GH2_TXB_14B 0x3a3
+#define TSSI_5GH2_TXC_14B 0x3a2
+#define TSSI_5GH2_TXD_14B 0x3a1
+
+
 struct odm_power_trim_data {
 	u8 flag;
 	u8 pa_bias_flag;
 	u8 lna_flag;
 	s8 bb_gain[KFREE_BAND_NUM][MAX_RF_PATH];
 	s8 tssi_trim[KFREE_BAND_NUM][MAX_RF_PATH];
+	s8 pa_bias_trim[KFREE_BAND_NUM][MAX_RF_PATH];
+	s8 lna_trim[MAX_RF_PATH];
 	s8 thermal;
+	s8 multi_thermal[MAX_RF_PATH];
 };

 enum phydm_kfree_channeltosw {
@@ -206,6 +281,8 @@ void phydm_get_pa_bias_offset(void *dm_void);

 s8 phydm_get_thermal_offset(void *dm_void);

+s8 phydm_get_multi_thermal_offset(void *dm_void, u8 path);
+
 void phydm_clear_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data);

 void phydm_config_new_kfree(void *dm_void);
@@ -214,4 +291,6 @@ s8 phydm_get_tssi_trim_de(void *dm_void, u8 path);

 void phydm_config_kfree(void *dm_void, u8 channel_to_sw);

+void phydm_set_lna_trim_offset (void *dm_void, u8 path, u8 cg_cs, u8 enable);
+
 #endif /*__HALRF_KFREE_H__*/
--- a/hal/phydm/halrf/halrf_powertracking.c
+++ b/hal/phydm/halrf/halrf_powertracking.c
@@ -162,16 +162,39 @@ void halrf_set_pwr_track(void *dm_void, u8 enable)
 	configure_txpower_track(dm, &c);
 	if (enable) {
 		rf->rf_supportability = rf->rf_supportability | HAL_RF_TX_PWR_TRACK;
+#if !(RTL8723F_SUPPORT == 1)
 		if (cali_info->txpowertrack_control == 1 || cali_info->txpowertrack_control == 3)
 			halrf_do_tssi(dm);
+#else
+	halrf_tssi_get_efuse(dm);
+	halrf_do_tssi(dm);
+#endif
+
 	} else {
 		rf->rf_supportability = rf->rf_supportability & ~HAL_RF_TX_PWR_TRACK;
 		odm_clear_txpowertracking_state(dm);
 		halrf_do_tssi(dm);
 		halrf_calculate_tssi_codeword(dm);
 		halrf_set_tssi_codeword(dm);
+		
+//#if !(RTL8723F_SUPPORT == 1)
 		for (i = 0; i < c.rf_path_count; i++)
 			(*c.odm_tx_pwr_track_set_pwr)(dm, CLEAN_MODE, i, 0);
+//#endif
 	}
+
+#if (RTL8723F_SUPPORT == 1)
+	if (dm->mp_mode) {
+		if (*dm->mp_mode)
+			/*Re-do dpk when tssi mode is changed*/
+			halrf_dpk_trigger(dm);
+	}
+#endif
+
+	if (cali_info->txpowertrack_control == 2 ||
+		cali_info->txpowertrack_control == 3 ||
+		cali_info->txpowertrack_control == 4 ||
+		cali_info->txpowertrack_control == 5)
+		halrf_txgapk_reload_tx_gain(dm);
 }

--- a/hal/phydm/halrf/halrf_powertracking_ap.c
+++ b/hal/phydm/halrf/halrf_powertracking_ap.c
@@ -927,7 +927,7 @@ odm_txpowertracking_init(
 {
 	struct dm_struct		*dm = (struct dm_struct *)dm_void;
 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-	if (!(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_IC_11N_SERIES)))
+	if (!(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8814B | ODM_IC_11N_SERIES)))
 		return;
 #endif

@@ -987,6 +987,24 @@ get_swing_index(
 	return i;
 }

+s8
+get_txagc_default_index(
+	void *dm_void
+)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	s8 tmp;
+
+#if RTL8814B_SUPPORT
+	if (dm->support_ic_type == ODM_RTL8814B) {
+		tmp = (s8)(odm_get_bb_reg(dm, R_0x18a0, 0x7f) & 0xff);
+		if (tmp & BIT(6))
+			tmp = tmp | 0x80;
+		return tmp;
+	} else
+		return 0;
+#endif
+}

 void
 odm_txpowertracking_thermal_meter_init(
@@ -995,9 +1013,12 @@ odm_txpowertracking_thermal_meter_init(
 {
 	struct dm_struct		*dm = (struct dm_struct *)dm_void;
 	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
+	struct _hal_rf_ *rf = &dm->rf_table;
+	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
 	struct rtl8192cd_priv		*priv = dm->priv;
 	u8 p;
 	u8 default_swing_index;
+	u8 i;
 #if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1)
 	if ((GET_CHIP_VER(priv) == VERSION_8197F) || (GET_CHIP_VER(priv) == VERSION_8822B) ||(GET_CHIP_VER(priv) == VERSION_8192F))
 		default_swing_index = get_swing_index(dm);
@@ -1073,7 +1094,7 @@ odm_txpowertracking_thermal_meter_init(

 #if (RTL8192F_SUPPORT == 1)
 	if (GET_CHIP_VER(priv) == VERSION_8192F) {
-		cali_info->default_ofdm_index = 30;
+		cali_info->default_ofdm_index = (default_swing_index >= (OFDM_TABLE_SIZE_92D - 1)) ? 30 : default_swing_index;
 		cali_info->default_cck_index = 28;
 	}
 #endif
@@ -1087,10 +1108,27 @@ odm_txpowertracking_thermal_meter_init(


 #if RTL8188E_SUPPORT
-	cali_info->default_cck_index = 20;	/* -6 dB */
-#elif RTL8192E_SUPPORT
-	cali_info->default_cck_index = 8;	/* -12 dB */
+	if (GET_CHIP_VER(priv) == VERSION_8188E) {
+		cali_info->default_cck_index = 20;	/* -6 dB */
+	}
 #endif
+
+#if RTL8192E_SUPPORT
+	if (GET_CHIP_VER(priv) == VERSION_8192E) {
+		cali_info->default_cck_index = 8;	/* -12 dB */
+	}
+#endif
+
+#if RTL8814B_SUPPORT
+	if (GET_CHIP_VER(priv) == VERSION_8814B) {
+		cali_info->default_txagc_index = get_txagc_default_index(dm);
+
+		for (i = 0; i < MAX_PATH_NUM_8814B; i++)
+			tssi->tssi_trk_txagc_offset[i] =
+				cali_info->default_txagc_index;
+	}
+#endif
+
 	cali_info->bb_swing_idx_ofdm_base = cali_info->default_ofdm_index;
 	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
 	dm->rf_calibrate_info.CCK_index = cali_info->default_cck_index;
@@ -1207,7 +1245,7 @@ odm_txpowertracking_check_ap(
 	struct _hal_rf_ *rf = &dm->rf_table;
 	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;

-#if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1) || (RTL8198F_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8812F_SUPPORT == 1))
+#if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1) || (RTL8198F_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8812F_SUPPORT == 1) || (RTL8197G_SUPPORT == 1))
 	if (!dm->rf_calibrate_info.tm_trigger) {
 		if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8192F | ODM_RTL8198F)) {
 			odm_set_rf_reg(dm, RF_PATH_A, 0x42, (BIT(17) | BIT(16)), 0x3);
@@ -1224,6 +1262,14 @@ odm_txpowertracking_check_ap(
 			odm_set_rf_reg(dm, RF_PATH_B, 0x42, BIT(17), 0x1);
 			odm_set_rf_reg(dm, RF_PATH_C, 0x42, BIT(17), 0x1);
 			odm_set_rf_reg(dm, RF_PATH_D, 0x42, BIT(17), 0x1);
+		} else if (dm->support_ic_type & ODM_RTL8197G) {
+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x42, BIT(17), 0x1);
+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x42, BIT(17), 0x0);
+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x42, BIT(17), 0x1);
+
+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x42, BIT(17), 0x1);
+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x42, BIT(17), 0x0);
+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x42, BIT(17), 0x1);
 		}

 		if (dm->support_ic_type & ODM_RTL8814B) {
--- a/hal/phydm/halrf/halrf_powertracking_ap.h
+++ b/hal/phydm/halrf/halrf_powertracking_ap.h
@@ -228,6 +228,7 @@ struct dm_rf_calibration_struct {
 	u8			bb_swing_idx_cck_base;
 	u8			default_ofdm_index;
 	u8			default_cck_index;
+	s8			default_txagc_index;
 	boolean			bb_swing_flag_cck;

 	s8			absolute_ofdm_swing_idx[MAX_RF_PATH];
--- a/hal/phydm/halrf/halrf_powertracking_ce.c
+++ b/hal/phydm/halrf/halrf_powertracking_ce.c
@@ -664,6 +664,23 @@ u8 get_cck_swing_index(void *dm_void)
 	return i;
 }

+s8
+get_txagc_default_index(
+	void *dm_void
+)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	s8 tmp;
+
+	if (dm->support_ic_type == ODM_RTL8814B) {
+		tmp = (s8)(odm_get_bb_reg(dm, R_0x18a0, 0x7f) & 0xff);
+		if (tmp & BIT(6))
+			tmp = tmp | 0x80;
+		return tmp;
+	} else
+		return 0;
+}
+
 void odm_txpowertracking_thermal_meter_init(void *dm_void)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
@@ -696,8 +713,9 @@ void odm_txpowertracking_thermal_meter_init(void *dm_void)
 	cali_info->thermal_value_iqk = rf->eeprom_thermal;
 	cali_info->thermal_value_lck = rf->eeprom_thermal;

-#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
-	if (dm->support_ic_type == ODM_RTL8822C) {
+#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1 || RTL8723F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8822C || 
+	    dm->support_ic_type == ODM_RTL8723F) {
 		cali_info->thermal_value_path[RF_PATH_A] = tssi->thermal[RF_PATH_A];
 		cali_info->thermal_value_path[RF_PATH_B] = tssi->thermal[RF_PATH_B];
 		cali_info->thermal_value_iqk = tssi->thermal[RF_PATH_A];
@@ -748,6 +766,8 @@ void odm_txpowertracking_thermal_meter_init(void *dm_void)
 			else
 				cali_info->default_ofdm_index = swing_idx;

+			cali_info->default_txagc_index = get_txagc_default_index(dm);
+
 			cali_info->default_cck_index = 24;
 		}
 		cali_info->default_bb_swing_index_flag = true;
@@ -805,6 +825,12 @@ void odm_txpowertracking_check_ce(void *dm_void)
 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
 	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
 		return;
+#if (RTL8723F_SUPPORT == 1)
+	if (dm->support_ic_type & ODM_RTL8723F) {
+		/*RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF][TSSI] Pwrtrack return!\n");*/
+		return;
+	}
+#endif

 	if ((rf->power_track_type & 0xf0) >> 4 != 0) {
 		if (dm->support_ic_type & ODM_RTL8822C) {
@@ -868,10 +894,17 @@ odm_txpowertracking_direct_ce(void *dm_void)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	struct _hal_rf_ *rf = &dm->rf_table;
+
 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)

 	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
 		return;
+	if (dm->support_ic_type & ODM_RTL8723F) {
+#if (RTL8723F_SUPPORT == 1)
+		/*RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF]===>%s 8723F TSSI, return!\n", __func__);*/
+		return;
+#endif
+	}

 	if (dm->support_ic_type & ODM_RTL8822C) {
 		/*halrf_tssi_cck(dm);*/
--- a/hal/phydm/halrf/halrf_powertracking_ce.h
+++ b/hal/phydm/halrf/halrf_powertracking_ce.h
@@ -199,6 +199,7 @@ struct dm_rf_calibration_struct {
 	u8 bb_swing_idx_cck_base;
 	u8 default_ofdm_index;
 	u8 default_cck_index;
+	s8 default_txagc_index;
 	boolean bb_swing_flag_cck;

 	s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
--- a/hal/phydm/halrf/halrf_powertracking_iot.c
+++ b/hal/phydm/halrf/halrf_powertracking_iot.c
@@ -34,7 +34,7 @@
 * ************************************************************
 */

-u32	ofdm_swing_table[OFDM_TABLE_SIZE] = {
+const u32 ofdm_swing_table[OFDM_TABLE_SIZE] = {
 	0x7f8001fe,	/* 0, +6.0dB */
 	0x788001e2,	/* 1, +5.5dB */
 	0x71c001c7,	/* 2, +5.0dB*/
@@ -74,7 +74,7 @@ u32	ofdm_swing_table[OFDM_TABLE_SIZE] = {
 	0x10000040,	/* 36, -12.0dB*/
 };

-u8	cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
+const u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
 	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},	/* 0, +0dB */
 	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 1, -0.5dB */
 	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 2, -1.0dB*/
@@ -110,7 +110,7 @@ u8	cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
 	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}	/* 32, -16.0dB*/
 };

-u8	cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
+const u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
 	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},	/* 0, +0dB */
 	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 1, -0.5dB */
 	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 2, -1.0dB */
@@ -146,7 +146,7 @@ u8	cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
 	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}	/* 32, -16.0dB*/
 };

-u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
+const u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
 	0x0b40002d, /* 0,  -15.0dB	*/
 	0x0c000030, /* 1,  -14.5dB*/
 	0x0cc00033, /* 2,  -14.0dB*/
@@ -192,7 +192,7 @@ u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
 	0x7f8001fe  /* 42, +6.0dB*/
 };

-u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+const u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
 	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
 	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
 	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
@@ -216,7 +216,7 @@ u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
 	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
 };

-u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
+const u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
 	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
 	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
 	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
@@ -240,7 +240,7 @@ u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
 	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
 };

-u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+const u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
 	{0x44,	 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
 	{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
 	{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
@@ -264,7 +264,7 @@ u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
 	{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
 };

-u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
+const u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
 	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},	/*  0, -16.0dB*/
 	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/*   1, -15.5dB*/
 	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/*  2, -15.0dB*/
@@ -300,7 +300,7 @@ u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
 	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}	/*  32, +0dB*/
 };

-u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
+const u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
 	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},	/*  0, -16.0dB*/
 	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 1, -15.5dB*/
 	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/*  2, -15.0dB*/
@@ -336,7 +336,7 @@ u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
 	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}	/* 32, +0dB	*/
 };

-u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
+const u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
 	0x0CD,          /*0 ,    -20dB*/
 	0x0D9,
 	0x0E6,
@@ -381,7 +381,7 @@ u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
 };

 /* JJ ADD 20161014 */
-u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
+const u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
 	0x0CD,          /*0 ,    -20dB*/
 	0x0D9,
 	0x0E6,
@@ -426,7 +426,7 @@ u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
 };

 /* Winnita ADD 20171116 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/
-u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {
+const u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {
 	0x0CD,			 /*0 ,    -20dB*/
 	0x0D9,
 	0x0E6,
@@ -471,7 +471,7 @@ u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {
 };

 /* Winnita ADD 201805 PathA 0xAB4[10:0]*/
-u32 cck_swing_table_ch1_ch14_8721d[CCK_TABLE_SIZE_8721D] = {
+const u32 cck_swing_table_ch1_ch14_8721d[CCK_TABLE_SIZE_8721D] = {
 	0x0CD,			 /*0 ,    -20dB*/
 	0x0D9,
 	0x0E6,
@@ -515,7 +515,7 @@ u32 cck_swing_table_ch1_ch14_8721d[CCK_TABLE_SIZE_8721D] = {
 	0x7FF,
 };

-u32 cck_swing_table_ch1_ch14_8710c[CCK_TABLE_SIZE_8710C] = {
+const u32 cck_swing_table_ch1_ch14_8710c[CCK_TABLE_SIZE_8710C] = {
 	0x0CD,          /*0 ,    -20dB*/
 	0x0D9,
 	0x0E6,
@@ -559,7 +559,7 @@ u32 cck_swing_table_ch1_ch14_8710c[CCK_TABLE_SIZE_8710C] = {
 	0x7FF,
 };

-u32 cck_swing_table_03db_ch1_ch14_8710c[CCK_03DB_TABLE_SIZE_8710C] = {
+const u32 cck_swing_table_03db_ch1_ch14_8710c[CCK_03DB_TABLE_SIZE_8710C] = {
 	0x143,		/*0 ,    -4dB*/
 	0x14C,		/*1 ,    -3.75dB*/
 	0x156,		/*2 ,    -3.5dB*/
@@ -643,7 +643,7 @@ u32 cck_swing_table_03db_ch1_ch14_8710c[CCK_03DB_TABLE_SIZE_8710C] = {
 	0xCA3		/*80 ,    +16dB*/
 };

-u32 ofdm_swing_table_03DB_8710c[OFDM_03DB_TABLE_SIZE_8710C] = {
+const u32 ofdm_swing_table_03DB_8710c[OFDM_03DB_TABLE_SIZE_8710C] = {
 	0xE4,		/*0 ,    -7dB*/
 	0xEB,		/*1 ,    -6.75dB*/
 	0xF2,		/*2 ,    -6.5dB*/
@@ -729,7 +729,7 @@ u32 ofdm_swing_table_03DB_8710c[OFDM_03DB_TABLE_SIZE_8710C] = {



-u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
+const u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
 	0x081, /* 0,  -12.0dB*/
 	0x088, /* 1,  -11.5dB*/
 	0x090, /* 2,  -11.0dB*/
@@ -792,6 +792,7 @@ get_swing_index(
 	u32 *swing_table;
 	u32 table_value;

+#if (RTL8710C_SUPPORT == 1)
 	if (dm->support_ic_type == ODM_RTL8710C) {
 		bb_swing = odm_get_bb_reg(dm, R_0xcc8, 0x000007ff);

@@ -800,10 +801,10 @@ get_swing_index(
 				break;
 		}
 	}
-
+#elif (RTL8195B_SUPPORT == 1)
 	if (dm->support_ic_type == ODM_RTL8195B) {
 		bb_swing = odm_get_bb_reg(dm, R_0xc1c, 0xFFE00000);
-		swing_table = tx_scaling_table_jaguar;
+		swing_table = (u32*)tx_scaling_table_jaguar;
 		swing_table_size = TXSCALE_TABLE_SIZE;

 		for (i = 0; i < swing_table_size; i++) {
@@ -814,7 +815,7 @@ get_swing_index(
 				break;
 		}
 	}
-
+#endif
 	return i;
 }

@@ -828,6 +829,7 @@ get_cck_swing_index(
 	u8 i = 0;
 	u32 bb_cck_swing;

+#if (RTL8188E_SUPPORT == 1 || RTL8723B_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
 	if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
 	    dm->support_ic_type == ODM_RTL8192E) {
 		bb_cck_swing = odm_read_1byte(dm, 0xa22);
@@ -836,14 +838,18 @@ get_cck_swing_index(
 			if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
 				break;
 		}
-	} else if (dm->support_ic_type == ODM_RTL8703B) {
+	}
+#elif (RTL8703B_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8703B) {
 		bb_cck_swing = odm_read_1byte(dm, 0xa22);

 		for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
 			if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
 				break;
 		}
-	} else if (dm->support_ic_type == ODM_RTL8710C) {
+	}
+#elif (RTL8710C_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8710C) {
 		bb_cck_swing = odm_get_bb_reg(dm, R_0xab4, 0x7ff);

 		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
@@ -854,10 +860,28 @@ get_cck_swing_index(
 				break;
 		}
 	}
+#endif

 	return i;
 }

+s8
+get_txagc_default_index(
+	void *dm_void
+)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	s8 tmp;
+
+	if (dm->support_ic_type == ODM_RTL8814B) {
+		tmp = (s8)(odm_get_bb_reg(dm, R_0x18a0, 0x7f) & 0xff);
+		if (tmp & BIT(6))
+			tmp = tmp | 0x80;
+		return tmp;
+	} else
+		return 0;
+}
+
 void
 odm_txpowertracking_thermal_meter_init(
 	void	*dm_void
--- a/hal/phydm/halrf/halrf_powertracking_iot.h
+++ b/hal/phydm/halrf/halrf_powertracking_iot.h
@@ -62,26 +62,26 @@
 #define IQK_MATRIX_SETTINGS_NUM	(14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
 #endif

-extern	u32 ofdm_swing_table[OFDM_TABLE_SIZE];
-extern	u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
-extern	u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
+extern const u32 ofdm_swing_table[OFDM_TABLE_SIZE];
+extern const u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
+extern const u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];

-extern	u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
-extern	u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
-extern	u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
-extern	u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
-extern	u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
-extern	u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
-extern	u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
+extern const u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
+extern const u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
+extern const u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
+extern const u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
+extern const u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
+extern const u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
+extern const u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
 /* JJ ADD 20161014 */
-extern	u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
-extern	u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
-extern	u32 cck_swing_table_ch1_ch14_8721d[CCK_TABLE_SIZE_8721D];
-extern  u32 cck_swing_table_ch1_ch14_8710c[CCK_TABLE_SIZE_8710C];
-extern  u32 cck_swing_table_03db_ch1_ch14_8710c[CCK_03DB_TABLE_SIZE_8710C];
-extern  u32 ofdm_swing_table_03DB_8710c[OFDM_03DB_TABLE_SIZE_8710C];
+extern const u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
+extern const u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
+extern const u32 cck_swing_table_ch1_ch14_8721d[CCK_TABLE_SIZE_8721D];
+extern const u32 cck_swing_table_ch1_ch14_8710c[CCK_TABLE_SIZE_8710C];
+extern const u32 cck_swing_table_03db_ch1_ch14_8710c[CCK_03DB_TABLE_SIZE_8710C];
+extern const u32 ofdm_swing_table_03DB_8710c[OFDM_03DB_TABLE_SIZE_8710C];

-extern  u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
+extern const u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];

 /* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
@@ -221,6 +221,7 @@ struct dm_rf_calibration_struct {
 	u8			bb_swing_idx_cck_base;
 	u8			default_ofdm_index;
 	u8			default_cck_index;
+	s8			default_txagc_index;
 	boolean			bb_swing_flag_cck;

 	s8			absolute_ofdm_swing_idx[MAX_RF_PATH];
--- a/hal/phydm/halrf/halrf_powertracking_win.c
+++ b/hal/phydm/halrf/halrf_powertracking_win.c
@@ -532,8 +532,7 @@ get_swing_index(
 	if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
 	    dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8188F || 
 	    dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || 
-	    dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8710B ||
-	    dm->support_ic_type == ODM_RTL8821) {
+	    dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8710B) {
 		bb_swing = odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000);

 		for (i = 0; i < OFDM_TABLE_SIZE; i++) {
@@ -588,6 +587,22 @@ get_cck_swing_index(
 	return i;
 }

+s8
+get_txagc_default_index(
+	void *dm_void
+)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	s8 tmp;
+
+	if (dm->support_ic_type == ODM_RTL8814B) {
+		tmp = (s8)(odm_get_bb_reg(dm, R_0x18a0, 0x7f) & 0xff);
+		if (tmp & BIT(6))
+			tmp = tmp | 0x80;
+		return tmp;
+	} else
+		return 0;
+}

 void
 odm_txpowertracking_thermal_meter_init(
@@ -662,8 +677,9 @@ odm_txpowertracking_thermal_meter_init(
 	cali_info->thermal_value_iqk	= hal_data->eeprom_thermal_meter;
 	cali_info->thermal_value_lck	= hal_data->eeprom_thermal_meter;

-#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
-	if (dm->support_ic_type == ODM_RTL8822C) {
+#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1 || RTL8723F_SUPPORT == 1)
+	if (dm->support_ic_type == ODM_RTL8822C || 
+	    dm->support_ic_type == ODM_RTL8723F) {
 		cali_info->thermal_value_path[RF_PATH_A] = tssi->thermal[RF_PATH_A];
 		cali_info->thermal_value_path[RF_PATH_B] = tssi->thermal[RF_PATH_B];
 		cali_info->thermal_value_iqk = tssi->thermal[RF_PATH_A];
@@ -683,8 +699,7 @@ odm_txpowertracking_thermal_meter_init(
 	if (cali_info->default_bb_swing_index_flag != true) {
 		/*The index of "0 dB" in SwingTable.*/
 		if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
-		    dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8703B ||
-		    dm->support_ic_type == ODM_RTL8821) {
+		    dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8703B) {
 			cali_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index;
 			cali_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index;
 		} else if (dm->support_ic_type == ODM_RTL8188F) {          /*add by Mingzhi.Guo  2015-03-23*/
@@ -704,6 +719,7 @@ odm_txpowertracking_thermal_meter_init(
 		} else {
 			cali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
 			cali_info->default_cck_index = 24;
+			cali_info->default_txagc_index = get_txagc_default_index(dm);
 		}
 		cali_info->default_bb_swing_index_flag = true;
 	}
@@ -838,6 +854,12 @@ odm_txpowertracking_direct_call(
 	HAL_DATA_TYPE		*hal_data	= GET_HAL_DATA(((PADAPTER)adapter));
 	struct dm_struct			*dm = &hal_data->DM_OutSrc;

+	if (dm->support_ic_type & ODM_RTL8723F) {
+#if (RTL8723F_SUPPORT == 1)
+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "[RF]===>%s 8723F TSSI, return!\n", __func__);
+		return;
+#endif
+	}
 	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B)) {
 #if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
 		odm_txpowertracking_new_callback_thermal_meter(dm);
@@ -882,7 +904,12 @@ odm_txpowertracking_thermal_meter_check(
 			odm_set_rf_reg(dm, RF_PATH_B, 0x42, BIT(17), 0x1);
 			odm_set_rf_reg(dm, RF_PATH_C, 0x42, BIT(17), 0x1);
 			odm_set_rf_reg(dm, RF_PATH_D, 0x42, BIT(17), 0x1);
-		} else
+		} else if (IS_HARDWARE_TYPE_8723F(adapter)) {
+			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(16), 0x01);
+			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(16), 0x00);
+			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(16), 0x01);
+		}
+		else
 			PHY_SetRFReg(adapter, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);

 		if (dm->support_ic_type & ODM_RTL8814B) {
--- a/hal/phydm/halrf/halrf_powertracking_win.h
+++ b/hal/phydm/halrf/halrf_powertracking_win.h
@@ -216,6 +216,7 @@ struct dm_rf_calibration_struct {
 	u8			bb_swing_idx_cck_base;
 	u8			default_ofdm_index;
 	u8			default_cck_index;
+	s8			default_txagc_index;
 	boolean			bb_swing_flag_cck;

 	s8			absolute_ofdm_swing_idx[MAX_RF_PATH];
--- a/hal/phydm/halrf/halrf_psd.c
+++ b/hal/phydm/halrf/halrf_psd.c
@@ -260,19 +260,93 @@ void _halrf_psd_iqk_init(struct dm_struct *dm)
 	odm_set_bb_reg(dm, 0x1bcc, 0x3f, 0x3f);	
 }

-
-u32 halrf_get_iqk_psd_data(
-	struct dm_struct *dm,
-	u32 point)
+void _halrf_iqk_psd_init_8723f(void *dm_void,	 boolean onoff)
 {
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 s;
+
+	s = (u8)odm_get_bb_reg(dm, 0x1884, BIT(20));
+
+	if (onoff) {
+		/*01_8723F_AFE_ON_BB_settings.txt*/
+		odm_set_bb_reg(dm, 0x1c38, MASKDWORD, 0x0);
+		odm_set_bb_reg(dm, R_0x1830, BIT(30), 0x0);
+		odm_set_bb_reg(dm, R_0x1860, 0xF0000000, 0xf);
+		odm_set_bb_reg(dm, R_0x1860, 0x0FFFF000, 0x0041);
+		odm_set_bb_reg(dm, 0x09f0, 0x0000FFFF, 0xbbbb);
+		odm_set_bb_reg(dm, 0x1d40, BIT(3), 0x1);
+		odm_set_bb_reg(dm, 0x1d40, 0x00000007, 0x3);
+		odm_set_bb_reg(dm, 0x09b4, 0x00000700, 0x3);
+		odm_set_bb_reg(dm, 0x09b4, 0x00003800, 0x3);
+		odm_set_bb_reg(dm, 0x09b4, 0x0001C000, 0x3);
+		odm_set_bb_reg(dm, 0x09b4, 0x000E0000, 0x3);
+		odm_set_bb_reg(dm, R_0x1c20, BIT(5), 0x1);
+		odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0x0);
+		odm_set_bb_reg(dm, R_0x1e28, 0x0000000F, 0x1);
+		odm_set_bb_reg(dm, R_0x824, 0x000F0000, 0x1);
+		odm_set_bb_reg(dm, R_0x1cd0, 0xF0000000, 0x7);
+		odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x1);
+		odm_set_bb_reg(dm, R_0x1c68, BIT(24), 0x1);
+		odm_set_bb_reg(dm, R_0x1864, BIT(31), 0x1);
+		odm_set_bb_reg(dm, R_0x180c, BIT(27), 0x1);
+		odm_set_bb_reg(dm, R_0x180c, BIT(30), 0x1);
+		odm_set_bb_reg(dm, R_0x1e24, BIT(17), 0x1);
+		odm_set_bb_reg(dm, R_0x1880, BIT(21), 0x0);
+		odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xffffffff);
+		/*02_IQK_Preset.txt*/
+		//odm_set_rf_reg(dm, RF_PATH_A, 0x05, BIT(0), 0x0);
+		//odm_set_rf_reg(dm, RF_PATH_B, 0x05, BIT(0), 0x0);
+		odm_set_bb_reg(dm, R_0x1b08, MASKDWORD, 0x00000080);
+		//odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x00000002);
+		//switch path  10 od 0x1b38 0x1/0x3 [1:0]
+		if (s == 0)
+			odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x00000008);
+		else
+			odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x0000000a);
+
+		odm_set_bb_reg(dm, R_0x1b18, MASKDWORD, 0x40010101);
+		odm_set_bb_reg(dm, R_0x1b14, MASKDWORD, 0x40010100);
+		//odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, 0xA2103C00);
+		odm_set_bb_reg(dm, R_0x1b0c, 0x00000C00, 0x2);
+		odm_set_bb_reg(dm, R_0x1bcc, 0x0000003F, 0x3f);	
+		//DbgPrint("[PSD][8723F]iqkpsd init!\n");
+	} else {
+		/*10_IQK_Reg_PSD_Restore.txt*/
+		//odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, 0xA2103C00);
+		odm_set_bb_reg(dm, R_0x1b08, MASKDWORD, 0x00000000);
+		odm_set_bb_reg(dm, R_0x1b38, BIT(0), 0x0);
+		odm_set_bb_reg(dm, R_0x1bcc, 0x0000003F, 0x0);	
+		//odm_set_rf_reg(dm, RF_PATH_A, 0x05, BIT(0), 0x1);
+		//odm_set_rf_reg(dm, RF_PATH_B, 0x05, BIT(0), 0x1);
+		/*11_8723F_restore_AFE_BB_settings.txt*/
+		odm_set_bb_reg(dm, 0x1c38, MASKDWORD, 0x0);
+		odm_set_bb_reg(dm, R_0x1830, BIT(30), 0x1);
+		odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0x1);
+		odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x0);
+		odm_set_bb_reg(dm, R_0x1c68, BIT(24), 0x0);
+		odm_set_bb_reg(dm, R_0x1864, BIT(31), 0x0);
+		odm_set_bb_reg(dm, R_0x180c, BIT(27), 0x0);
+		odm_set_bb_reg(dm, R_0x180c, BIT(30), 0x0);
+		odm_set_bb_reg(dm, R_0x1880, BIT(21), 0x0);
+		odm_set_bb_reg(dm, R_0x1c38, MASKDWORD, 0xffa1005e);
+		//DbgPrint("[PSD][8723F]iqkpsd resotre!\n");
+	}
+}
+
+u64 halrf_get_iqk_psd_data(void *dm_void, u32 point)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	struct _hal_rf_ *rf = &(dm->rf_table);
 	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
-	u32 psd_val, psd_val1, psd_val2, psd_point, i, delay_time = 0;
+	u64 psd_val, psd_val1, psd_val2;
+	u32 psd_point, i, delay_time = 0;

 #if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
 	if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) {
 		if (dm->support_ic_type & ODM_RTL8822C)
 			delay_time = 1000;
+		else if (dm->support_ic_type & ODM_RTL8723F)
+			delay_time = 1000;
 		else
 			delay_time = 0;
 	}
@@ -320,6 +394,14 @@ u32 halrf_get_iqk_psd_data(
 		psd_val2 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);

 		psd_val = (psd_val1 << 27) + (psd_val2 >> 5);
+	} else if (dm->support_ic_type & ODM_RTL8723F) {
+		odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00210001);
+		psd_val1 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
+		psd_val1 = (psd_val1 & 0x00FF0000) >> 16;
+		odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00220001);
+		psd_val2 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
+		//psd_val = (psd_val1 << 27) + (psd_val2 >> 5);
+		psd_val = (psd_val1 << 32) + psd_val2;
 	} else {
 		odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00250001);

@@ -357,8 +439,8 @@ void halrf_iqk_psd(
 	mode = average >> 16;

 	if (mode == 2) {
-		if (dm->support_ic_type & ODM_RTL8822C)
-			average_tmp = 1;
+		if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8723F))
+			average_tmp = 1; //HW average
 		else {
 			reg_tmp = odm_get_bb_reg(dm, R_0x1b1c, 0x000e0000);
 			if (reg_tmp == 0)
@@ -381,18 +463,22 @@ void halrf_iqk_psd(
 			average_tmp = 16;
 		else if (reg_tmp == 5)
 			average_tmp = 32;
+#ifndef RTL8723F_SUPPORT
 		odm_set_bb_reg(dm, R_0x1b1c, 0x000e0000, 0x0);
+#endif
 	}

 #if 0
 	DbgPrint("[PSD]point=%d, start_point=%d, stop_point=%d, average=0x%x, average_tmp=%d, buf_size=%d, mode=%d\n",
-		point, start_point, stop_point, average, average_tmp, psd->buf_size, mode);
+				point, start_point, stop_point, average, average_tmp, psd->buf_size, mode);
 #endif

 	for (i = 0; i < psd->buf_size; i++)
 		psd->psd_data[i] = 0;

 	i = start_point;
+
+#ifndef RTL8723F_SUPPORT
 	while (i < stop_point) {
 		data_tatal = 0;

@@ -431,13 +517,32 @@ void halrf_iqk_psd(

 	if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8198F | ODM_RTL8197G))
 		odm_set_bb_reg(dm, R_0x1b1c, 0x000e0000, reg_tmp);
+#else
+	while (i < stop_point) {
+		data_tatal = 0;

+		if (i >= point)
+			point_temp = i - point;
+		else
+			point_temp = i + 0xB00;
+		//-640:0xD80,640:0x280,0x280+0xB00 =0xD80
+			//point_temp = i + 0xC00;
+		//-512:0xE00,512:0x200,0x200+0xC00 = 0xE00
+
+		data_temp[k] = halrf_get_iqk_psd_data(dm, point_temp);
+		data_tatal = data_temp[k];
+		psd->psd_data[j] = (u32)data_tatal;
+		i++;
+		j++;
+	}
+
+#endif
 #if 0
 	DbgPrint("\n [iqk psd]psd result:\n");

 	for (i = 0; i < psd->buf_size; i++) {
 		if ((i % 20) == 0)
-			DbgPrint("\n ");
+		DbgPrint("\n ");

 		DbgPrint("0x%x ", psd->psd_data[i]);
 	}
@@ -454,19 +559,30 @@ halrf_psd_init(
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	struct _hal_rf_ *rf = &(dm->rf_table);
 	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
-
+#ifndef RTL8723F_SUPPORT
 #if 0
 	u32 bb_backup[12];
 	u32 backup_bb_reg[12] = {0x1b04, 0x1b08, 0x1b0c, 0x1b14, 0x1b18,
 				0x1b1c, 0x1b28, 0x1bcc, 0x1b2c, 0x1b34,
 				0x1bd4, 0x1bfc};
 #endif
-
+#else
+	u32 bb_backup[11];
+	u32 backup_bb_reg[11] = {0x09f0, 0x09b4, 0x1c38, 0x1860, 0x1cd0,
+				 0x824, 0x2a24, 0x1d40, 0x1c20, 0x1880, 0x180c};
+#endif
 	if (psd->psd_progress) {
 		ret_status = RT_STATUS_PENDING;
 	} else {
 		psd->psd_progress = 1;
-		if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8198F | ODM_RTL8197G)) {
+		if (dm->support_ic_type & ODM_RTL8723F) {
+			backup_bb_register(dm, bb_backup, backup_bb_reg, 11);
+			_halrf_iqk_psd_init_8723f(dm, true);
+			halrf_iqk_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
+			_halrf_iqk_psd_init_8723f(dm, false);
+			restore_bb_register(dm, bb_backup, backup_bb_reg, 11);
+		} else if (dm->support_ic_type & 
+		(ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8198F | ODM_RTL8197G)) {
 			/*backup_bb_register(dm, bb_backup, backup_bb_reg, 12);*/
 			_halrf_psd_iqk_init(dm);
 			halrf_iqk_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
--- a/hal/phydm/halrf/halrf_psd.h
+++ b/hal/phydm/halrf/halrf_psd.h
@@ -31,6 +31,16 @@ u32
 halrf_psd_init(
 	void *dm_void);

+void
+_halrf_iqk_psd_init_8723f(
+	void *dm_void,
+	boolean onoff);
+
+u64
+halrf_get_iqk_psd_data(
+	void *dm_void,
+	u32 point);
+
 u32
 halrf_psd_query(
 	void *dm_void,
--- a/hal/phydm/halrf/rtl8822b/halhwimg8822b_rf.c
+++ b/hal/phydm/halrf/rtl8822b/halhwimg8822b_rf.c
@@ -23,11 +23,9 @@
 *
 *****************************************************************************/

-/*Image2HeaderVersion: R3 1.5.10*/
+/*Image2HeaderVersion: R3 1.5.8*/
 #include "mp_precomp.h"

-#define ODM_WIN 0x08
-
 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 #if RT_PLATFORM == PLATFORM_MACOSX
 #include "phydm_precomp.h"
--- a/hal/phydm/halrf/rtl8822b/halhwimg8822b_rf.h
+++ b/hal/phydm/halrf/rtl8822b/halhwimg8822b_rf.h
@@ -23,7 +23,7 @@
 *
 *****************************************************************************/

-/*Image2HeaderVersion: R3 1.5.10*/
+/*Image2HeaderVersion: R3 1.5.8*/
 #if (RTL8822B_SUPPORT == 1)
 #ifndef __INC_MP_RF_HW_IMG_8822B_H
 #define __INC_MP_RF_HW_IMG_8822B_H
--- a/hal/phydm/halrf/rtl8822b/halrf_8822b.c
+++ b/hal/phydm/halrf/rtl8822b/halrf_8822b.c
@@ -458,11 +458,13 @@ void _phy_lc_calibrate_8822b(struct dm_struct *dm)
 	odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK,
 		       lc_cal | 0x08000);
 	ODM_delay_ms(100);
-	for (cnt = 0; cnt < 100; cnt++) {
+	for (cnt = 0; cnt < 5; cnt++) {
 		if (odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
 			break;
 		ODM_delay_ms(10);
 	}
+	if (cnt == 5)
+		RF_DBG(dm, DBG_RF_LCK, "LCK time out\n");
 	/*Recover channel number*/
 	odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal);
 	/*enable RTK*/
--- a/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c
+++ b/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c
@@ -44,10 +44,10 @@ void phydm_get_read_counter_8822b(struct dm_struct *dm)

 	while (1) {
 		rf_reg = odm_get_rf_reg(dm, RF_PATH_A, RF_0x8, MASK20BITS);
-		if (rf_reg == 0xabcde || counter > 300)
+		if (rf_reg == 0xabcde || counter > 20000)
 			break;
 		counter++;
-		ODM_delay_ms(1);
+		ODM_delay_us(10);
 	}

 	odm_set_rf_reg(dm, RF_PATH_A, RF_0x8, MASK20BITS, 0x0);
@@ -184,11 +184,8 @@ void _iqk_fill_iqk_report_8822b(void *dm_void, u8 ch)
 	odm_write_4byte(dm, 0x1b00, 0xf8000008);
 	odm_set_bb_reg(dm, R_0x1bf0, 0x0000ffff, tmp1 | tmp2 | tmp3);

-	for (i = 0; i < 2; i++) {
-		data = ((iqk->rxiqk_agc[ch][(i * 2) + 1] << 16) |
-			iqk->rxiqk_agc[ch][i * 2]);
-		odm_write_4byte(dm, 0x1be8 + (i * 4), data);
-	}
+	data = (iqk->rxiqk_agc[ch][1] << 16) | iqk->rxiqk_agc[ch][0];
+	odm_write_4byte(dm, 0x1be8, data);
 }

 void _iqk_fail_count_8822b(void *dm_void)
@@ -298,11 +295,11 @@ void _iqk_bb_reset_8822b(struct dm_struct *dm)
 		odm_set_bb_reg(dm, R_0x198c, 0x7, 0x7);
 		cca_ing = (boolean)odm_get_bb_reg(dm, R_0xfa0, BIT(3));

-		if (count > 30)
+		if (count > 20000)
 			cca_ing = false;

 		if (cca_ing) {
-			ODM_delay_ms(1);
+			ODM_delay_us(10);
 			count++;
 		} else {
 			/*RX ant off*/
@@ -404,7 +401,7 @@ void _iqk_backup_iqk_8822b_subfunction(struct dm_struct *dm)
 	u8 i, j, k;

 	iqk->iqk_channel[1] = iqk->iqk_channel[0];
-	for (i = 0; i < 2; i++) {
+	for (i = 0; i < SS_8822B; i++) {
 		iqk->lok_idac[1][i] = iqk->lok_idac[0][i];
 		iqk->rxiqk_agc[1][i] = iqk->rxiqk_agc[0][i];
 		iqk->bypass_iqk[1][i] = iqk->bypass_iqk[0][i];
@@ -431,7 +428,7 @@ void _iqk_backup_iqk_8822b(struct dm_struct *dm, u8 step, u8 path)
 	case 0:
 		_iqk_backup_iqk_8822b_subfunction(dm);

-		for (i = 0; i < 4; i++) {
+		for (i = 0; i < SS_8822B; i++) {
 			iqk->rxiqk_fail_code[0][i] = 0x0;
 			iqk->rxiqk_agc[0][i] = 0x0;
 			for (j = 0; j < 2; j++) {
@@ -467,7 +464,7 @@ void _iqk_reload_iqk_setting_8822b(struct dm_struct *dm, u8 ch,
 	u32 bmask20_16 = (BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16));
 	boolean report;

-	for (path = 0; path < 2; path++) {
+	for (path = 0; path < SS_8822B; path++) {
 		if (reload_idx == 2) {
 #if 0
 			/*odm_set_rf_reg(dm, (enum rf_path)path, RF_0xdf, BIT(4), 0x1);*/
@@ -584,7 +581,7 @@ void _iqk_rf_setting_8822b(struct dm_struct *dm)
 	odm_write_4byte(dm, 0x1b00, 0xf8000008);
 	odm_write_4byte(dm, 0x1bb8, 0x00000000);

-	for (path = 0; path < 2; path++) {
+	for (path = 0; path < SS_8822B; path++) {
 		/*0xdf:B11 = 1,B4 = 0, B1 = 1*/
 		tmp = odm_get_rf_reg(dm, (enum rf_path)path,
 				     RF_0xdf, MASK20BITS);
@@ -830,11 +827,11 @@ _iqk_check_cal_8822b(struct dm_struct *dm, u8 path, u8 cmd)
 					odm_get_bb_reg(dm, R_0x1b08, BIT(26));
 			notready = false;
 		} else {
-			ODM_delay_ms(1);
+			ODM_delay_us(10);
 			delay_count++;
 		}

-		if (delay_count >= 50) {
+		if (delay_count >= 20000) {
 			fail = true;
 			RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK timeout!!!\n");
 			break;
@@ -864,7 +861,7 @@ _iqk_rxk_gsearch_fail_8822b(struct dm_struct *dm, u8 path, u8 step)
 		_iqk_ltec_write_8822b(dm, 0x38, 0xffff,0x7700);
 		odm_write_4byte(dm, 0x1b00, IQK_CMD);
 		odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
-		ODM_delay_ms(GS_delay_8822B);
+		ODM_delay_us(10);
 		fail = _iqk_check_cal_8822b(dm, path, 0x1);
 		_iqk_ltec_write_8822b(dm, 0x38, MASKDWORD, iqk->tmp_gntwl);
 	} else if (step == RXIQK2) {
@@ -872,6 +869,10 @@ _iqk_rxk_gsearch_fail_8822b(struct dm_struct *dm, u8 path, u8 step)
 			if (iqk->tmp1bcc == IQMUX[idx])
 				break;
 		}
+		if (idx == 4) {
+			RF_DBG(dm, DBG_RF_IQK, "[IQK] rx_gs overflow\n");
+			return fail;
+		}
 		odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
 		odm_write_4byte(dm, 0x1bcc, iqk->tmp1bcc);

@@ -882,7 +883,7 @@ _iqk_rxk_gsearch_fail_8822b(struct dm_struct *dm, u8 path, u8 step)
 		_iqk_ltec_write_8822b(dm, 0x38, 0xffff,0x7700);
 		odm_write_4byte(dm, 0x1b00, IQK_CMD);
 		odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
-		ODM_delay_ms(GS_delay_8822B);
+		ODM_delay_us(10);
 		fail = _iqk_check_cal_8822b(dm, path, 0x1);
 		_iqk_ltec_write_8822b(dm, 0x38, MASKDWORD, iqk->tmp_gntwl);

@@ -950,7 +951,7 @@ _lok_one_shot_8822b(void *dm_void, u8 path)
 	odm_write_4byte(dm, 0x1b00, IQK_CMD + 1);
 	/*LOK: CMD ID = 0	{0xf8000018, 0xf8000028}*/
 	/*LOK: CMD ID = 0	{0xf8000019, 0xf8000029}*/
-	ODM_delay_ms(LOK_delay_8822B);
+	ODM_delay_us(10);
 	LOK_notready = _iqk_check_cal_8822b(dm, path, 0x0);
 	_iqk_ltec_write_8822b(dm, 0x38, MASKDWORD, iqk->tmp_gntwl);

@@ -1023,7 +1024,7 @@ _iqk_one_shot_8822b(void *dm_void, u8 path, u8 idx)
 	_iqk_ltec_write_8822b(dm, 0x38, 0xffff,0x7700);
 	odm_write_4byte(dm, 0x1b00, IQK_CMD);
 	odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
-	ODM_delay_ms(WBIQK_delay_8822B);
+	ODM_delay_us(10);
 	fail = _iqk_check_cal_8822b(dm, path, 0x1);
 	_iqk_ltec_write_8822b(dm, 0x38, MASKDWORD, iqk->tmp_gntwl);

@@ -1297,7 +1298,7 @@ void _iqk_iqk_by_path_8822b(void *dm_void, boolean segment_iqk)
 			       "[IQK]B_GS1_retry = %d B_GS2_retry = %d\n",
 			       iqk->gs_retry_count[0][RF_PATH_B][0],
 			       iqk->gs_retry_count[0][RF_PATH_B][1]);
-			for (i = 0; i < 2; i++) {
+			for (i = 0; i < SS_8822B; i++) {
 				odm_write_4byte(dm, 0x1b00,
 						0xf8000008 | i << 1);
 				odm_write_4byte(dm, 0x1b2c, 0x7);
@@ -1425,7 +1426,7 @@ u32 _iqk_tximr_selfcheck_8822b(void *dm_void, u8 tone_index, u8 path)
 	odm_write_4byte(dm, 0x1b38, 0x20000000);
 	odm_write_4byte(dm, 0x1b3c, 0x20000000);
 	/* ======derive pwr1========*/
-	for (i = 0; i < 2; i++) {
+	for (i = 0; i < SS_8822B; i++) {
 		odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
 		if (i == 0)
 			odm_write_4byte(dm, 0x1bcc, 0x0f);
@@ -1463,7 +1464,7 @@ void _iqk_start_tximr_test_8822b(struct dm_struct *dm, u8 imr_limit)
 	u8 path, i, tone_index;
 	u32 imr_result;

-	for (path = 0; path < 2; path++) {
+	for (path = 0; path < SS_8822B; path++) {
 		_iqk_txk_setting_8822b(dm, path);
 		KFAIL = _iqk_one_shot_8822b(dm, path, TXIQK);
 		for (i = 0x0; i < imr_limit; i++) {
@@ -1765,7 +1766,7 @@ void _iqk_start_rximr_test_8822b(struct dm_struct *dm, u8 imr_limit)
 {
 	u8 path;

-	for (path = 0; path < 2; path++)
+	for (path = 0; path < SS_8822B; path++)
 		_iqk_rximr_test_8822b(dm, path, imr_limit);
 }

@@ -1800,6 +1801,7 @@ void _phy_iq_calibrate_8822b(struct dm_struct *dm, boolean reset,
 					       0xc5c, 0xc6c, 0xe58, 0xe5c,
 					       0xe6c};
 	u32 backup_rf_reg[RF_REG_NUM_8822B] = {0xdf, 0x8f, 0x65, 0x0, 0x1};
+	u32 i;
 	boolean is_mp = false;

 	struct dm_iqk_info *iqk = &dm->IQK_info;
@@ -1817,7 +1819,7 @@ void _phy_iq_calibrate_8822b(struct dm_struct *dm, boolean reset,
 	       "[IQK]band_type=%s band_width=%d ExtPA2G=%d ext_pa_5g=%d\n",
 	       (*dm->band_type == ODM_BAND_5G) ? "5G" : "2G", *dm->band_width,
 	       dm->ext_pa, dm->ext_pa_5g);
-	RF_DBG(dm, DBG_RF_IQK, "[IQK]Interface = %d, cut_version = %x\n",
+	RF_DBG(dm, DBG_RF_IQK, "[IQK]Interface = %d, Cv = %x\n",
 	       dm->support_interface, dm->cut_version);

 	iqk->iqk_times++;
@@ -1853,7 +1855,8 @@ void _phy_iq_calibrate_8822b(struct dm_struct *dm, boolean reset,
 			break;
 		iqk->kcount = 0;
 		RF_DBG(dm, DBG_RF_IQK, "[IQK]delay 50ms!!!\n");
-		ODM_delay_ms(50);
+		for (i = 0; i < 5000; i++)
+			ODM_delay_us(10);
 	};
 	if (segment_iqk)
 		_iqk_reload_iqk_setting_8822b(dm, 0x0, 0x1);
@@ -1889,17 +1892,17 @@ void _phy_iq_calibrate_by_fw_8822b(void *dm_void, u8 clear, u8 segment_iqk)
 		RF_DBG(dm, DBG_RF_IQK, "[IQK]FWIQK fail!!!\n");
 }

-/*IQK_version:0x2f, NCTL:0x8*/
-/*1.disable CCK block and OFDM CCA block while IQKing*/
 void phy_iq_calibrate_8822b(void *dm_void, boolean clear, boolean segment_iqk)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 i;

 	if (*dm->mp_mode)
 		halrf_iqk_hwtx_check(dm, true);
-	/*FW IQK*/
 	if (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) {
 		_phy_iq_calibrate_by_fw_8822b(dm, clear, (u8)(segment_iqk));
+		for (i = 0; i < 100; i++)
+			ODM_delay_us(10);
 		phydm_get_read_counter_8822b(dm);
 		halrf_iqk_check_if_reload(dm);
 	} else {
@@ -1982,8 +1985,8 @@ void phy_get_iqk_cfir_8822b(void *dm_void, u8 idx, u8 path, boolean debug)
 		odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001 + (i * 4));
 		tmp = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
 		iqk_info->iqk_cfir_real[ch][path][idx][i] =
-						(tmp & 0x0fff0000) >> 16;
-		iqk_info->iqk_cfir_imag[ch][path][idx][i] = tmp & 0xfff;
+						(u16)((tmp & 0x0fff0000) >> 16);
+		iqk_info->iqk_cfir_imag[ch][path][idx][i] = (u16)tmp & 0xfff;
 	}
 	odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
 	odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x0);
@@ -1997,11 +2000,11 @@ void phy_iqk_dbg_cfir_backup_8822b(void *dm_void)

 	RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "backup TX/RX CFIR");

-	for (path = 0; path < 2; path++)
+	for (path = 0; path < SS_8822B; path++)
 		for (idx = 0; idx < 2; idx++)
 			phydm_get_iqk_cfir(dm, idx, path, true);

-	for (path = 0; path < 2; path++) {
+	for (path = 0; path < SS_8822B; path++) {
 		for (idx = 0; idx < 2; idx++) {
 			for (i = 0; i < 8; i++) {
 				RF_DBG(dm, DBG_RF_IQK,
@@ -2036,7 +2039,7 @@ void phy_iqk_dbg_cfir_backup_update_8822b(void *dm_void)
 		RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "CFIR is invalid");
 		return;
 	}
-	for (path = 0; path < 2; path++) {
+	for (path = 0; path < SS_8822B; path++) {
 		for (idx = 0; idx < 2; idx++) {
 			odm_set_bb_reg(dm, R_0x1b00, MASKDWORD,
 				       0xf8000008 | path << 1);
@@ -2083,7 +2086,7 @@ void phy_iqk_dbg_cfir_reload_8822b(void *dm_void)
 		RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "CFIR is invalid");
 		return;
 	}
-	for (path = 0; path < 2; path++) {
+	for (path = 0; path < SS_8822B; path++) {
 		for (idx = 0; idx < 2; idx++) {
 			odm_set_bb_reg(dm, R_0x1b00, MASKDWORD,
 				       0xf8000008 | path << 1);
@@ -2137,7 +2140,7 @@ void phy_iqk_dbg_cfir_backup_show_8822b(void *dm_void)

 	RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "backup TX/RX CFIR");

-	for (path = 0; path < 2; path++) {
+	for (path = 0; path < SS_8822B; path++) {
 		for (idx = 0; idx < 2; idx++) {
 			for (i = 0; i < 8; i++) {
 				RF_DBG(dm, DBG_RF_IQK,
--- a/hal/phydm/phydm.c
+++ b/hal/phydm/phydm.c
@@ -136,6 +136,10 @@ void phydm_cck_new_agc_chk(struct dm_struct *dm)
 		/*@1: new agc  0: old agc*/
 	dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, new_agc_addr, BIT(17));
 #endif
+#if (RTL8723F_SUPPORT)
+	if (dm->support_ic_type & (ODM_RTL8723F)) 
+		dm->cck_new_agc = true;
+#endif
 }

 /*select 3 or 4 bit LNA */
@@ -224,9 +228,9 @@ void phydm_init_hw_info_by_rfe(struct dm_struct *dm)
 	if (dm->support_ic_type & ODM_RTL8197F)
 		phydm_init_hw_info_by_rfe_type_8197f(dm);
 	#endif
-	#if (RTL8814B_SUPPORT)
-	if (dm->support_ic_type & ODM_RTL8814B)
-		phydm_init_hw_info_by_rfe_type_8814b(dm);
+	#if (RTL8197G_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8197G)
+		phydm_init_hw_info_by_rfe_type_8197g(dm);
 	#endif
 }
 #endif
@@ -310,17 +314,64 @@ void phydm_common_info_self_init(struct dm_struct *dm)
 	dm->u8_dummy = 0xf;
 	dm->u16_dummy = 0xffff;
 	dm->u32_dummy = 0xffffffff;
-
-	dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE;
-	dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
+#if (RTL8814B_SUPPORT)
+/*@------------For spur detection Default Mode------------@*/
+	dm->dsde_sel = DET_CSI;
+	dm->csi_wgt = 4;
+/*@-------------------------------------------------------@*/
+#endif
 	dm->pre_is_linked = false;
 	dm->is_linked = false;
+/*dym bw thre and it can config by registry*/
+	if (dm->en_auto_bw_th == 0)
+		dm->en_auto_bw_th = 20;
+
 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 	if (!(dm->is_fcs_mode_enable)) {
 		dm->is_fcs_mode_enable = &dm->boolean_dummy;
 		pr_debug("[Warning] is_fcs_mode_enable=NULL\n");
 	}
 #endif
+	/*init IOT table*/
+	odm_memory_set(dm, &dm->iot_table, 0, sizeof(struct phydm_iot_center));
+}
+
+void phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_iot_center	*iot_table = &dm->iot_table;
+
+	PHYDM_DBG(dm, DBG_CMN, "[IOT] 0x%x = %d\n", iot_idx, en);
+	switch (iot_idx) {
+	case 0x100f0401:
+		iot_table->patch_id_100f0401 = en;
+		PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_100f0401 = %d\n",
+			  iot_table->patch_id_100f0401);
+		break;
+	case 0x10120200:
+		iot_table->patch_id_10120200 = en;
+		PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_10120200 = %d\n",
+			  iot_table->patch_id_10120200);
+		break;
+	case 0x40010700:
+		iot_table->patch_id_40010700 = en;
+		PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_40010700 = %d\n",
+			  iot_table->patch_id_40010700);
+		break;
+	case 0x021f0800:
+		iot_table->patch_id_021f0800 = en;
+		PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_021f0800 = %d\n",
+			  iot_table->patch_id_021f0800);
+		break;
+	case 0x011f0500:
+		iot_table->patch_id_011f0500 = en;
+		PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_011f0500 = %d\n",
+			  iot_table->patch_id_011f0500);
+		break;
+	default:
+		pr_debug("[%s] warning!\n", __func__);
+		break;
+	}
 }

 void phydm_cmn_sta_info_update(void *dm_void, u8 macid)
@@ -364,24 +415,6 @@ void phydm_common_info_self_update(struct dm_struct *dm)

 	sta = dm->phydm_sta_info[0];

-	#if 0
-	if (mgnt_info->mAssoc) {
-		sta->dm_ctrl |= STA_DM_CTRL_ACTIVE;
-		for (i = 0; i < 6; i++)
-			sta->mac_addr[i] = mgnt_info->Bssid[i];
-	} else if (GetFirstClientPort(adapter)) {
-		struct _ADAPTER *client_adapter = GetFirstClientPort(adapter);
-
-		sta->dm_ctrl |= STA_DM_CTRL_ACTIVE;
-		for (i = 0; i < 6; i++)
-			sta->mac_addr[i] = client_adapter->MgntInfo.Bssid[i];
-	} else {
-		sta->dm_ctrl = sta->dm_ctrl & (~STA_DM_CTRL_ACTIVE);
-		for (i = 0; i < 6; i++)
-			sta->mac_addr[i] = 0;
-	}
-	#endif
-
 	/* STA mode is linked to AP */
 	if (is_sta_active(sta) && !ACTING_AS_AP(adapter))
 		dm->bsta_state = true;
@@ -491,11 +524,11 @@ phydm_get_structure(struct dm_struct *dm, u8 structure_type)
 	case PHYDM_ADAPTIVITY:
 		structure = &dm->adaptivity;
 		break;
-
+#ifdef CONFIG_PHYDM_DFS_MASTER
 	case PHYDM_DFS:
 		structure = &dm->dfs;
 		break;
-
+#endif
 	default:
 		break;
 	}
@@ -548,11 +581,85 @@ void phydm_hw_setting(struct dm_struct *dm)
 		phydm_hwsetting_8822c(dm);
 #endif

+#if (RTL8197G_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8197G)
+		phydm_hwsetting_8197g(dm);
+#endif
+
+#if (RTL8723F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8723F)
+		phydm_hwsetting_8723f(dm);
+#endif
+
+#if (RTL8821C_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8821C)
+		phydm_hwsetting_8821c(dm);
+#endif
+
+#if (RTL8812F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8812F)
+		phydm_hwsetting_8812f(dm);
+#endif
+
 #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
 	phydm_cck_rx_pathdiv_watchdog(dm);
 #endif
 }

+__odm_func__
+boolean phydm_chk_bb_rf_pkg_set_valid(struct dm_struct *dm)
+{
+	boolean valid = true;
+
+	if (dm->support_ic_type == ODM_RTL8822C) {
+		#if (RTL8822C_SUPPORT)
+		valid = phydm_chk_pkg_set_valid_8822c(dm,
+						      RELEASE_VERSION_8822C,
+						      RF_RELEASE_VERSION_8822C);
+		#else
+		valid = true; /*@Just for preventing compile warnings*/
+		#endif
+	#if (RTL8812F_SUPPORT)
+	} else if (dm->support_ic_type == ODM_RTL8812F) {
+		valid = phydm_chk_pkg_set_valid_8812f(dm,
+						      RELEASE_VERSION_8812F,
+						      RF_RELEASE_VERSION_8812F);
+	#endif
+	#if (RTL8197G_SUPPORT)
+	} else if (dm->support_ic_type == ODM_RTL8197G) {
+		valid = phydm_chk_pkg_set_valid_8197g(dm,
+						      RELEASE_VERSION_8197G,
+						      RF_RELEASE_VERSION_8197G);
+	#endif
+	#if (RTL8812F_SUPPORT)
+	} else if (dm->support_ic_type == ODM_RTL8812F) {
+		valid = phydm_chk_pkg_set_valid_8812f(dm,
+						      RELEASE_VERSION_8812F,
+						      RF_RELEASE_VERSION_8812F);
+	#endif
+	#if (RTL8198F_SUPPORT)
+	} else if (dm->support_ic_type == ODM_RTL8198F) {
+		valid = phydm_chk_pkg_set_valid_8198f(dm,
+						      RELEASE_VERSION_8198F,
+						      RF_RELEASE_VERSION_8198F);
+	#endif
+	#if (RTL8814B_SUPPORT)
+	} else if (dm->support_ic_type == ODM_RTL8814B) {
+		valid = phydm_chk_pkg_set_valid_8814b(dm,
+						      RELEASE_VERSION_8814B,
+						      RF_RELEASE_VERSION_8814B);
+	#endif
+	#if (RTL8723F_SUPPORT)
+	} else if (dm->support_ic_type == ODM_RTL8723F) {
+		valid = phydm_chk_pkg_set_valid_8723f(dm,
+						      RELEASE_VERSION_8723F,
+							  RF_RELEASE_VERSION_8723F);
+	#endif
+	}
+
+	return valid;
+}
+
 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
 u64 phydm_supportability_init_win(
 	void *dm_void)
@@ -785,7 +892,7 @@ u64 phydm_supportability_init_win(
 		support_ability |=
 			ODM_BB_DIG |
 			ODM_BB_RA_MASK |
-			/* ODM_BB_DYNAMIC_TXPWR |*/
+			ODM_BB_DYNAMIC_TXPWR |
 			ODM_BB_FA_CNT |
 			ODM_BB_RSSI_MONITOR |
 			ODM_BB_CCK_PD |
@@ -814,6 +921,22 @@ u64 phydm_supportability_init_win(
 		break;
 #endif

+#if (RTL8723F_SUPPORT)
+	case ODM_RTL8723F:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			/* ODM_BB_DYNAMIC_TXPWR |*/
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN |*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_ADAPTIVITY |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
 	default:
 		support_ability |=
 			ODM_BB_DIG |
@@ -1045,7 +1168,7 @@ u64 phydm_supportability_init_ce(void *dm_void)
 		support_ability |=
 			ODM_BB_DIG |
 			ODM_BB_RA_MASK |
-			/*@ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_DYNAMIC_TXPWR |
 			ODM_BB_FA_CNT |
 			ODM_BB_RSSI_MONITOR |
 			ODM_BB_CCK_PD |
@@ -1064,12 +1187,12 @@ u64 phydm_supportability_init_ce(void *dm_void)
 		support_ability |=
 			ODM_BB_DIG |
 			ODM_BB_RA_MASK |
-			/* ODM_BB_DYNAMIC_TXPWR	|*/
+			ODM_BB_DYNAMIC_TXPWR	|
 			ODM_BB_FA_CNT |
 			ODM_BB_RSSI_MONITOR |
 			ODM_BB_CCK_PD |
 			ODM_BB_RATE_ADAPTIVE |
-			ODM_BB_PATH_DIV |
+			/* ODM_BB_PATH_DIV | */
 			ODM_BB_ADAPTIVITY |
 			ODM_BB_CFO_TRACKING |
 			ODM_BB_ENV_MONITOR;
@@ -1087,12 +1210,27 @@ u64 phydm_supportability_init_ce(void *dm_void)
 			ODM_BB_CCK_PD |
 			/*@ODM_BB_PWR_TRAIN |*/
 			/*ODM_BB_RATE_ADAPTIVE |*/
-			ODM_BB_ADAPTIVITY;
-			/*ODM_BB_CFO_TRACKING |*/
+			ODM_BB_ADAPTIVITY |
+			ODM_BB_CFO_TRACKING;
 			/*ODM_BB_ENV_MONITOR;*/
 		break;
 #endif
-
+#if (RTL8723F_SUPPORT)
+	case ODM_RTL8723F:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			ODM_BB_DYNAMIC_TXPWR	|
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			ODM_BB_RATE_ADAPTIVE |
+			/* ODM_BB_PATH_DIV | */
+			ODM_BB_ADAPTIVITY |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
 	default:
 		support_ability |=
 			ODM_BB_DIG |
@@ -1177,15 +1315,15 @@ u64 phydm_supportability_init_ap(
 #if (RTL8198F_SUPPORT || RTL8197F_SUPPORT)
 	case ODM_RTL8198F:
 		support_ability |=
-			/*ODM_BB_DIG |*/
+			ODM_BB_DIG |
 			ODM_BB_RA_MASK |
 			ODM_BB_FA_CNT |
 			ODM_BB_RSSI_MONITOR |
 			ODM_BB_CCK_PD |
 			/*ODM_BB_PWR_TRAIN |*/
 			/*ODM_BB_RATE_ADAPTIVE |*/
-			ODM_BB_ADAPTIVITY;
-			/*ODM_BB_CFO_TRACKING |*/
+			ODM_BB_ADAPTIVITY |
+			ODM_BB_CFO_TRACKING;
 			/*ODM_BB_ADAPTIVE_SOML |*/
 			/*ODM_BB_ENV_MONITOR |*/
 			/*ODM_BB_LNA_SAT_CHK |*/
@@ -1310,9 +1448,9 @@ u64 phydm_supportability_init_ap(
 			ODM_BB_CCK_PD |
 			/*ODM_BB_PWR_TRAIN |*/
 			/*ODM_BB_RATE_ADAPTIVE |*/
-			ODM_BB_ADAPTIVITY;
-			/*ODM_BB_CFO_TRACKING |*/
-			/*ODM_BB_ENV_MONITOR;*/
+			ODM_BB_ADAPTIVITY |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
 		break;
 #endif

@@ -1337,6 +1475,7 @@ u64 phydm_supportability_init_ap(
 		support_ability |=
 			ODM_BB_DIG |
 			ODM_BB_RA_MASK |
+			ODM_BB_DYNAMIC_TXPWR	|
 			ODM_BB_FA_CNT |
 			ODM_BB_RSSI_MONITOR |
 			/*ODM_BB_CCK_PD |*/
@@ -1348,6 +1487,21 @@ u64 phydm_supportability_init_ap(
 		break;
 #endif

+#if (RTL8723F_SUPPORT)
+	case ODM_RTL8723F:
+		support_ability |=
+			ODM_BB_DIG |
+			ODM_BB_RA_MASK |
+			ODM_BB_FA_CNT |
+			ODM_BB_RSSI_MONITOR |
+			ODM_BB_CCK_PD |
+			/*ODM_BB_PWR_TRAIN |*/
+			ODM_BB_RATE_ADAPTIVE |
+			ODM_BB_ADAPTIVITY |
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
+		break;
+#endif
 	default:
 		support_ability |=
 			ODM_BB_DIG |
@@ -1365,16 +1519,6 @@ u64 phydm_supportability_init_ap(
 		break;
 	}

-#if 0
-	/*@[Config Antenna Diveristy]*/
-	if (*dm->enable_antdiv)
-		support_ability |= ODM_BB_ANT_DIV;
-
-	/*@[Config Adaptivity]*/
-	if (*dm->edcca_mode)
-		support_ability |= ODM_BB_ADAPTIVITY;
-#endif
-
 	return support_ability;
 }
 #endif
@@ -1431,8 +1575,8 @@ u64 phydm_supportability_init_iot(
 			/*ODM_BB_PWR_TRAIN |*/
 			ODM_BB_RATE_ADAPTIVE |
 			ODM_BB_ADAPTIVITY |
-			ODM_BB_CFO_TRACKING;
-			/*ODM_BB_ENV_MONITOR*/
+			ODM_BB_CFO_TRACKING |
+			ODM_BB_ENV_MONITOR;
 		break;
 #endif

@@ -1495,8 +1639,7 @@ void phydm_fwoffload_ability_init(struct dm_struct *dm,
 {
 	switch (offload_ability) {
 	case PHYDM_PHY_PARAM_OFFLOAD:
-		if (dm->support_ic_type &
-		    (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
+		if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)
 			dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD;
 		break;

@@ -1504,6 +1647,10 @@ void phydm_fwoffload_ability_init(struct dm_struct *dm,
 		dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD;
 		break;

+	case PHYDM_RF_DPK_OFFLOAD:
+		dm->fw_offload_ability |= PHYDM_RF_DPK_OFFLOAD;
+		break;
+
 	default:
 		PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
 		break;
@@ -1518,8 +1665,7 @@ void phydm_fwoffload_ability_clear(struct dm_struct *dm,
 {
 	switch (offload_ability) {
 	case PHYDM_PHY_PARAM_OFFLOAD:
-		if (dm->support_ic_type &
-		    (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
+		if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)
 			dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD);
 		break;

@@ -1527,6 +1673,10 @@ void phydm_fwoffload_ability_clear(struct dm_struct *dm,
 		dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD);
 		break;

+	case PHYDM_RF_DPK_OFFLOAD:
+		dm->fw_offload_ability &= (~PHYDM_RF_DPK_OFFLOAD);
+		break;	
+
 	default:
 		PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
 		break;
@@ -1569,6 +1719,14 @@ void phydm_supportability_init(void *dm_void)
 		if (IS_FUNC_EN(dm->en_adap_soml))
 			support_ability |= ODM_BB_ADAPTIVE_SOML;

+		/*@[DYNAMIC_TXPWR and TSSI cannot coexist]*/
+		if(IS_FUNC_EN(&dm->en_tssi_mode) &&
+		    (dm->support_ic_type & ODM_RTL8822C))
+			support_ability &= ~ODM_BB_DYNAMIC_TXPWR;
+		/*@[DYNAMIC_TXPWR and TSSI cannot coexist]*/
+		if(IS_FUNC_EN(&dm->en_tssi_mode) &&
+		    (dm->support_ic_type & ODM_RTL8723F))
+			support_ability &= ~ODM_BB_DYNAMIC_TXPWR;
 	}
 	dm->support_ability = support_ability;
 	PHYDM_DBG(dm, ODM_COMP_INIT, "IC=0x%x, mp=%d, Supportability=0x%llx\n",
@@ -1586,6 +1744,41 @@ void phydm_rfe_init(void *dm_void)
 #endif
 }

+#ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
+void phydm_tx_collsion_th_init(void *dm_void)
+{
+
+struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+#if (RTL8197G_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8197G)
+		phydm_tx_collsion_th_init_8197g(dm);
+#endif
+
+#if (RTL8812F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8812F)
+		phydm_tx_collsion_th_init_8812f(dm);
+#endif
+
+}
+
+void phydm_tx_collsion_th_set(void *dm_void, u8 val_r2t, u8 val_t2r)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+#if (RTL8197G_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8197G)
+		phydm_tx_collsion_th_set_8197g(dm, val_r2t, val_t2r);
+#endif
+
+#if (RTL8812F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8812F)
+		phydm_tx_collsion_th_set_8812f(dm, val_r2t, val_t2r);
+#endif
+	
+}
+#endif
+
 void phydm_dm_early_init(struct dm_struct *dm)
 {
 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
@@ -1593,10 +1786,18 @@ void phydm_dm_early_init(struct dm_struct *dm)
 #endif
 }

-void odm_dm_init(struct dm_struct *dm)
+enum phydm_init_result odm_dm_init(struct dm_struct *dm)
 {
+	enum phydm_init_result result = PHYDM_INIT_SUCCESS;
+
+	if (!phydm_chk_bb_rf_pkg_set_valid(dm)) {
+		pr_debug("[Warning][%s] Init fail\n", __func__);
+		return PHYDM_INIT_FAIL_BBRF_REG_INVALID;
+	}
+
 	halrf_init(dm);
 	phydm_supportability_init(dm);
+	phydm_pause_func_init(dm);
 	phydm_rfe_init(dm);
 	phydm_common_info_self_init(dm);
 	phydm_rx_phy_status_init(dm);
@@ -1605,6 +1806,9 @@ void odm_dm_init(struct dm_struct *dm)
 #endif
 	phydm_dig_init(dm);
 #ifdef PHYDM_SUPPORT_CCKPD
+#ifdef PHYDM_DCC_ENHANCE
+	phydm_dig_cckpd_coex_init(dm);
+#endif
 	phydm_cck_pd_init(dm);
 #endif
 	phydm_env_monitor_init(dm);
@@ -1665,6 +1869,12 @@ void odm_dm_init(struct dm_struct *dm)
 #ifdef CONFIG_MU_RSOML
 	phydm_mu_rsoml_init(dm);
 #endif
+
+#ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
+	phydm_tx_collsion_th_init(dm);
+#endif
+
+	return result;
 }

 void odm_dm_reset(struct dm_struct *dm)
@@ -1687,8 +1897,7 @@ void phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
 	u8 i;

 	for (i = 0; i < 5; i++) {
-		if (input[i + 1])
-			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
 	}

 	pre_support_ability = dm->support_ability;
@@ -1759,7 +1968,6 @@ void phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
 		PDM_SNPF(out_len, used, output + used, out_len - used,
 			 "18. (( %s ))LNA_SAT_CHK\n",
 			 ((comp & ODM_BB_LNA_SAT_CHK) ? ("V") : (".")));
-
 		PDM_SNPF(out_len, used, output + used, out_len - used,
 			 "================================\n");
 		PDM_SNPF(out_len, used, output + used, out_len - used,
@@ -1828,6 +2036,9 @@ void phydm_watchdog_lps(struct dm_struct *dm)
 	phydm_cck_pd_th(dm);
 	#endif
 	phydm_adaptivity(dm);
+	#ifdef CONFIG_BW_INDICATION
+	phydm_dyn_bw_indication(dm);
+	#endif
 	#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
 	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
 	/*@enable AntDiv in PS mode, request from SD4 Jeff*/
@@ -1855,6 +2066,18 @@ void phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type)
 	}
 }

+void phydm_pause_func_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE;
+	dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
+	dm->pause_lv_table.lv_antdiv = PHYDM_PAUSE_RELEASE;
+	dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
+	dm->pause_lv_table.lv_adapt = PHYDM_PAUSE_RELEASE;
+	dm->pause_lv_table.lv_adsl = PHYDM_PAUSE_RELEASE;
+}
+
 u8 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
 		    enum phydm_pause_type pause_type,
 		    enum phydm_pause_level pause_lv, u8 val_lehgth,
@@ -2061,8 +2284,7 @@ void phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
 	}

 	for (i = 0; i < 10; i++) {
-		if (input[i + 1])
-			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
+		PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
 	}

 	func = (enum phydm_func_idx)var1[0];
@@ -2178,20 +2400,34 @@ void phydm_watchdog(struct dm_struct *dm)

 	phydm_hw_setting(dm);

-	#ifdef PHYDM_TDMA_DIG_SUPPORT
-	if (dm->original_dig_restore == 0)
+	phydm_env_mntr_result_watchdog(dm);
+
+#ifdef PHYDM_TDMA_DIG_SUPPORT
+	if (dm->original_dig_restore == 0) {
 		phydm_tdma_dig_timer_check(dm);
-	else
-	#endif
+	} else
+#endif
 	{
 		phydm_false_alarm_counter_statistics(dm);
-		phydm_noisy_detection(dm);
+	#if (ODM_IC_11N_SERIES_SUPPORT || ODM_IC_11AC_SERIES_SUPPORT)
+		if (dm->support_ic_type & (ODM_IC_11N_SERIES |
+					   ODM_IC_11AC_SERIES))
+			phydm_noisy_detection(dm);
+	#endif
+
+	#if defined(PHYDM_DCC_ENHANCE) && defined(PHYDM_SUPPORT_CCKPD)
+		phydm_dig_cckpd_coex(dm);
+	#else
 		phydm_dig(dm);
 		#ifdef PHYDM_SUPPORT_CCKPD
 		phydm_cck_pd_th(dm);
 		#endif
+	#endif
 	}

+#ifdef PHYDM_HW_IGI
+	phydm_hwigi(dm);
+#endif
 #ifdef PHYDM_POWER_TRAINING_SUPPORT
 	phydm_update_power_training_state(dm);
 #endif
@@ -2219,11 +2455,14 @@ void phydm_watchdog(struct dm_struct *dm)
 #ifdef PHYDM_PRIMARY_CCA
 	phydm_primary_cca(dm);
 #endif
+#ifdef CONFIG_BW_INDICATION
+	phydm_dyn_bw_indication(dm);
+#endif
 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
 	odm_dtc(dm);
 #endif

-	phydm_env_mntr_watchdog(dm);
+	phydm_env_mntr_set_watchdog(dm);

 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
 	phydm_lna_sat_chk_watchdog(dm);
@@ -2240,6 +2479,46 @@ void phydm_watchdog(struct dm_struct *dm)
 	phydm_common_info_self_reset(dm);
 }

+void phydm_fw_dm_ctrl_en(void *dm_void, enum phydm_func_idx fun_idx,
+			 boolean enable)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 h2c_val[H2C_MAX_LENGTH] = {0};
+	u8 para4[4]; /*4 bit*/
+	u8 para8[4]; /*8 bit*/
+	u8 i = 0;
+
+	for (i = 0; i < 4; i++) {
+		para4[i] = 0;
+		para8[i] = 0;
+	}
+
+	switch (fun_idx) {
+	case F00_DIG:
+		phydm_fill_fw_dig_info(dm, &enable, para4, para8);
+		break;
+	default:
+		pr_debug("[Warning] %s\n", __func__);
+		return;
+	}
+
+	h2c_val[0] = (u8)((fun_idx & 0x3f) | (enable << 6));
+	h2c_val[1] = para8[0];
+	h2c_val[2] = para8[1];
+	h2c_val[3] = para8[2];
+	h2c_val[4] = para8[3];
+	h2c_val[5] = (para4[0] & 0xf) | ((para4[1] & 0xf) << 3);
+	h2c_val[6] = (para4[2] & 0xf) | ((para4[3] & 0xf) << 3);
+
+	PHYDM_DBG(dm, DBG_FW_DM,
+		  "H2C[0x59] fun_idx=%d,en=%d,para8={%x %x %x %x},para4={%x %x %x %x}\n",
+		  fun_idx, enable,
+		  para8[0], para8[1], para8[2], para8[3],
+		  para4[0], para4[1], para4[2], para4[3]);
+
+	odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_DM_CTRL, H2C_MAX_LENGTH, h2c_val);
+}
+
 /*@
 * Init /.. Fixed HW value. Only init time.
 */
@@ -2439,10 +2718,19 @@ void odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info,
 	case ODM_CMNINFO_DIS_DPD:
 		dm->en_dis_dpd = (boolean)value;
 		break;
+	case ODM_CMNINFO_EN_AUTO_BW_TH:
+		dm->en_auto_bw_th = (u8)value;
+		break;
 #if (RTL8721D_SUPPORT)
 	case ODM_CMNINFO_POWER_VOLTAGE:
 		dm->power_voltage = (u8)value;
 		break;
+	case ODM_CMNINFO_ANTDIV_GPIO:
+		dm->antdiv_gpio = (u8)value;
+		break;
+	case ODM_CMNINFO_PEAK_DETECT_MODE:
+		dm->peak_detect_mode = (u8)value;
+		break;
 #endif
 	default:
 		break;
@@ -2594,6 +2882,8 @@ void odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info,
 	case ODM_CMNINFO_MANUAL_SUPPORTABILITY:
 		dm->manual_supportability = (u32 *)value;
 		break;
+	case ODM_CMNINFO_EN_DYM_BW_INDICATION:
+		dm->dis_dym_bw_indication = (u8 *)value;
 	default:
 		/*do nothing*/
 		break;
@@ -2640,7 +2930,9 @@ void odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value)
 		break;

 	case ODM_CMNINFO_RSSI_MIN:
+#if 0
 		dm->rssi_min = (u8)value;
+#endif
 		break;

 	case ODM_CMNINFO_RSSI_MIN_BY_PATH:
@@ -2699,6 +2991,12 @@ void odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value)
 	case ODM_CMNINFO_LINKED_BF_SUPPORT:
 		dm->linked_bf_support = (u8)value;
 		break;
+	case ODM_CMNINFO_FLATNESS_TYPE:
+		dm->flatness_type = (u8)value;
+		break;
+	case ODM_CMNINFO_TSSI_ENABLE:
+		dm->en_tssi_mode = (u8)value;
+		break;
 	default:
 		break;
 	}
@@ -2789,7 +3087,15 @@ u32 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type)
 	case PHYDM_INFO_NHM_RATIO:
 		return (u32)ccx_info->nhm_ratio;
 	case PHYDM_INFO_NHM_NOISE_PWR:
-		return (u32)ccx_info->nhm_noise_pwr;
+		return (u32)ccx_info->nhm_level;
+	case PHYDM_INFO_NHM_PWR:
+		return (u32)ccx_info->nhm_pwr;
+	case PHYDM_INFO_NHM_ENV_RATIO:
+		return (u32)ccx_info->nhm_env_ratio;
+	case PHYDM_INFO_TXEN_CCK:
+		return (u32)fa_t->cnt_cck_txen;
+	case PHYDM_INFO_TXEN_OFDM:
+		return (u32)fa_t->cnt_ofdm_txen;
 	default:
 		return 0xffffffff;
 	}
@@ -3146,12 +3452,6 @@ void odm_dtc(struct dm_struct *dm)
 	u8 sign;
 	u8 resp_txagc = 0;

-#if 0
-	/* @As DIG is disabled, DTC is also disable */
-	if (!(dm->support_ability & ODM_XXXXXX))
-		return;
-#endif
-
 	if (dm->rssi_min > DTC_BASE) {
 		/* need to decade the CTS TX power */
 		sign = 1;
@@ -3223,7 +3523,7 @@ void phydm_dc_cancellation(struct dm_struct *dm)
 		if (path > RF_PATH_A &&
 		    dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8188F |
 					  ODM_RTL8710B | ODM_RTL8721D |
-					  ODM_RTL8710C))
+					  ODM_RTL8710C | ODM_RTL8723D))
 			break;
 		else if (path > RF_PATH_B &&
 			 dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8192F))
@@ -3234,11 +3534,13 @@ void phydm_dc_cancellation(struct dm_struct *dm)
 		}
 		odm_write_dig(dm, 0x7e);
 		/*@Disable LNA*/
-		if (dm->support_ic_type & ODM_RTL8821C)
+		if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
+					   ODM_RTL8710C))
 			halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
 		/*Turn off 3-wire*/
 		phydm_stop_3_wire(dm, PHYDM_SET);
-		if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) {
+		if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D |
+			ODM_RTL8710B)) {
 			/*set debug port to 0x235*/
 			if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
 				PHYDM_DBG(dm, ODM_COMP_API,
@@ -3310,7 +3612,8 @@ void phydm_dc_cancellation(struct dm_struct *dm)
 		/* @Turn on 3-wire*/
 		phydm_stop_3_wire(dm, PHYDM_REVERT);
 		/* @Enable LNA*/
-		if (dm->support_ic_type & ODM_RTL8821C)
+		if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
+					   ODM_RTL8710C))
 			halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);

 		odm_write_dig(dm, 0x20);
@@ -3323,7 +3626,8 @@ void phydm_dc_cancellation(struct dm_struct *dm)
 	/*@DC_Cancellation*/
 	/*@DC compensation to CCK data path*/
 	odm_set_bb_reg(dm, R_0xa9c, BIT(20), 0x1);
-	if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) {
+	if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D |
+		ODM_RTL8710B)) {
 		offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
 		offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;

@@ -3419,12 +3723,18 @@ void phydm_dc_cancellation(struct dm_struct *dm)
 		offset_i_hex[0] = (reg_value32[0] & 0xff80000) >> 19;
 		offset_q_hex[0] = (reg_value32[0] & 0x3fe00) >> 9;

-		/*@Before filling into registers,
-		 *offset should be multiplexed (-1)
-		 */
-		offset_i_hex[0] = 0x200 - offset_i_hex[0];
-		offset_q_hex[0] = 0x200 - offset_q_hex[0];
-
+		if ((offset_i_hex[0] > 0xF && offset_i_hex[0] < 0x1F1)
+		    || (offset_q_hex[0] > 0xF && offset_q_hex[0] < 0x1F1)) {
+		    	/*@Discard outliers*/
+		   	 offset_i_hex[0] = 0x0;
+		   	 offset_q_hex[0] = 0x0;	
+		} else {
+			/*@Before filling into registers,
+		 	*offset should be multiplexed (-1)
+			 */
+			offset_i_hex[0] = 0x200 - offset_i_hex[0];
+			offset_q_hex[0] = 0x200 - offset_q_hex[0];
+		}
 		odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
 		odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
 	}
@@ -3488,3 +3798,29 @@ end:
 	}
 #endif
 }
+
+void phydm_dyn_bw_indication(void *dm_void)
+{
+#ifdef CONFIG_BW_INDICATION
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 en_auto_bw_th = dm->en_auto_bw_th;
+
+	if (!(dm->support_ic_type & ODM_DYM_BW_INDICATION_SUPPORT))
+		return;
+
+	/*driver decide bw cobime timing*/
+	if (dm->dis_dym_bw_indication) {
+		if (*dm->dis_dym_bw_indication)
+			return;
+	}
+
+	/*check for auto bw*/
+	if (dm->rssi_min <= en_auto_bw_th && dm->is_linked) {
+		phydm_bw_fixed_enable(dm, FUNC_DISABLE);
+		return;
+	}
+
+	phydm_bw_fixed_setting(dm);
+#endif
+}
+
--- a/hal/phydm/phydm.h
+++ b/hal/phydm/phydm.h
@@ -204,6 +204,8 @@ extern const u16	phy_rate_table[84];
 #define PHY_HIST_SIZE		12
 #define PHY_HIST_TH_SIZE	(PHY_HIST_SIZE - 1)

+#define	S_TO_US			1000000
+
 /*@============================================================*/
 /*structure and define*/
 /*@============================================================*/
@@ -211,6 +213,8 @@ extern const u16	phy_rate_table[84];
 #define		dm_type_by_fw		0
 #define		dm_type_by_driver	1

+#define		HW_IGI_TXINFO_TABLE_SIZE 64
+
 #ifdef BB_RAM_SUPPORT

 struct phydm_bb_ram_per_sta {
@@ -230,7 +234,7 @@ struct phydm_bb_ram_per_sta {

 struct phydm_bb_ram_ctrl {
 	/*@ For 98F/14B/22C/12F, each tx_pwr_ofst step will be 1dB*/
-	struct phydm_bb_ram_per_sta pram_sta_ctrl[ODM_ASSOCIATE_ENTRY_NUM];
+	struct phydm_bb_ram_per_sta pram_sta_ctrl[HW_IGI_TXINFO_TABLE_SIZE];
 	/*------------ For table2 do not set power offset by macid --------*/
 	/* For type == 2'b10, 0x1e70[22:16] = tx_pwr_offset_reg0, 0x1e70[23] = enable */
 	boolean			tx_pwr_ofst_reg0_en;
@@ -238,6 +242,9 @@ struct phydm_bb_ram_ctrl {
 	/* For type == 2'b11, 0x1e70[30:24] = tx_pwr_offset_reg1, 0x1e70[31] = enable */
 	boolean			tx_pwr_ofst_reg1_en;
 	u8			tx_pwr_ofst_reg1;
+	boolean			hwigi_watchdog_en;
+	u64			macid_is_linked;
+	u64			hwigi_macid_is_linked;
 };

 #endif
@@ -372,14 +379,14 @@ struct odm_phy_dbg_info {
 	#endif
 	u16			snr_hist_th[PHY_HIST_TH_SIZE];
 	u16			evm_hist_th[PHY_HIST_TH_SIZE];
-	#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
+	#ifdef PHYSTS_3RD_TYPE_SUPPORT
 	u16			cn_hist_th[PHY_HIST_TH_SIZE]; /*U(16,1)*/
-	#endif
-	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-	s16 cfo_tail[4]; /* per-path's cfo_tail */
+	u8			condition_num_seg0;
+	u8			eigen_val[4];
+	s16			cfo_tail[4]; /*per-path's cfo_tail */
 	#endif
 	struct phydm_phystatus_statistic	physts_statistic_info;
-	struct phydm_phystatus_avg	phystatus_statistic_avg;
+	struct phydm_phystatus_avg		phystatus_statistic_avg;
 };

 enum odm_cmninfo {
@@ -431,9 +438,12 @@ enum odm_cmninfo {
 	ODM_CMNINFO_X_CAP_SETTING,
 	ODM_CMNINFO_ADVANCE_OTA,
 	ODM_CMNINFO_HP_HWID,
-	ODM_CMNINFO_TSSI_ENABLE,
+	ODM_CMNINFO_TSSI_ENABLE, /*also for cmn_info_update*/
 	ODM_CMNINFO_DIS_DPD,
 	ODM_CMNINFO_POWER_VOLTAGE,
+	ODM_CMNINFO_ANTDIV_GPIO,
+	ODM_CMNINFO_EN_AUTO_BW_TH,
+	ODM_CMNINFO_PEAK_DETECT_MODE,
 	/*@-----------HOOK BEFORE REG INIT-----------*/

 	/*@Dynamic value:*/
@@ -472,6 +482,7 @@ enum odm_cmninfo {
 	ODM_CMNINFO_BB_OPERATION_MODE,
 	ODM_CMNINFO_BF_ANTDIV_DECISION,
 	ODM_CMNINFO_MANUAL_SUPPORTABILITY,
+	ODM_CMNINFO_EN_DYM_BW_INDICATION,
 	/*@--------- POINTER REFERENCE-----------*/

 	/*@------------CALL BY VALUE-------------*/
@@ -502,6 +513,7 @@ enum odm_cmninfo {
 	ODM_CMNINFO_PHYDM_PATCH_ID,
 	ODM_CMNINFO_RRSR_VAL,
 	ODM_CMNINFO_LINKED_BF_SUPPORT,
+	ODM_CMNINFO_FLATNESS_TYPE,
 	/*@------------CALL BY VALUE-------------*/

 	/*@Dynamic ptr array hook itms.*/
@@ -556,6 +568,11 @@ enum phydm_info_query {
 	PHYDM_INFO_CLM_RATIO,
 	PHYDM_INFO_NHM_RATIO,
 	PHYDM_INFO_NHM_NOISE_PWR,
+	PHYDM_INFO_NHM_PWR,
+	PHYDM_INFO_NHM_ENV_RATIO,
+	PHYDM_INFO_TXEN_CCK,
+	PHYDM_INFO_TXEN_OFDM,
+
 };

 enum phydm_api {
@@ -631,7 +648,6 @@ enum phydm_dbg_comp {
 	DBG_PRI_CCA		= BIT(F16_PRI_CCA),
 	DBG_ADPTV_SOML		= BIT(F17_ADPTV_SOML),
 	DBG_LNA_SAT_CHK		= BIT(F18_LNA_SAT_CHK),
-	/*BIT(19)*/
 	/*Neet to re-arrange*/
 	DBG_PHY_STATUS		= BIT(20),
 	DBG_TMP			= BIT(21),
@@ -639,7 +655,7 @@ enum phydm_dbg_comp {
 	DBG_TXBF		= BIT(23),
 	DBG_COMMON_FLOW		= BIT(24),
 	DBG_COMP_MCC		= BIT(25),
-	/*BIT(26)*/
+	DBG_FW_DM		= BIT(26),
 	DBG_DM_SUMMARY		= BIT(27),
 	ODM_PHY_CONFIG		= BIT(28),
 	ODM_COMP_INIT		= BIT(29),
@@ -667,6 +683,11 @@ enum phydm_offload_ability {
 	PHYDM_RF_DPK_OFFLOAD	= BIT(2),
 };

+enum phydm_init_result {
+	PHYDM_INIT_SUCCESS = 0,
+	PHYDM_INIT_FAIL_BBRF_REG_INVALID = 1
+};
+
 struct phydm_pause_lv {
 	s8			lv_dig;
 	s8			lv_cckpd;
@@ -687,6 +708,9 @@ struct pkt_process_info {
 	u8			phy_ppdu_cnt; /*change with phy cca cnt*/
 	u8			page_bitmap_target;
 	u8			page_bitmap_record;
+	u8			ppdu_phy_rate;
+	u8			ppdu_macid;
+	boolean			is_1st_mpdu;
 	#endif
 	u8			lna_idx;
 	u8			vga_idx;
@@ -704,9 +728,13 @@ struct	phydm_bt_info {

 struct	phydm_iot_center {
 	boolean			is_linked_cmw500;
-	u8			win_patch_id;		/*@Customer ID*/
-	u32			phydm_patch_id;
-
+	u8			win_patch_id;		/*Customer ID*/
+	boolean			patch_id_100f0401;
+	boolean			patch_id_10120200;
+	boolean			patch_id_40010700;
+	boolean			patch_id_021f0800;
+	boolean			patch_id_011f0500;
+	u32			phydm_patch_id;		/*temp for CCX IOT */
 };

 #if (RTL8822B_SUPPORT)
@@ -736,7 +764,7 @@ struct _phydm_mcc_dm_ {
 };
 #endif

-#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
+#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
 struct phydm_physts {
 	u8			cck_gi_u_bnd;
 	u8			cck_gi_l_bnd;
@@ -839,9 +867,23 @@ struct dm_struct {
 	boolean			is_download_fw;
 	boolean			en_dis_dpd;
 	u16			dis_dpd_rate;
+	u8			en_auto_bw_th;
+	boolean			is_pause_dig;
 	#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8197G_SUPPORT)
 	u8			txagc_buff[RF_PATH_MEM_SIZE][PHY_NUM_RATE_IDX];
 	u32			bp_0x9b0;
+	#elif (RTL8723F_SUPPORT)
+	u8			txagc_buff[2][PHY_NUM_RATE_IDX];
+	u32			bp_0x9b0;
+	#endif
+	#if (RTL8822C_SUPPORT || RTL8723F_SUPPORT)
+	u8			ofdm_rxagc_l_bnd[16];
+	boolean			l_bnd_detect[16];
+	u16			agc_rf_gain_ori[16][64];/*[table][mp_gain_idx]*/
+	u16			agc_rf_gain[16][64];/*[table][mp_gain_idx]*/
+	u8			agc_table_cnt;
+	boolean			is_agc_tab_pos_shift;
+	u8			agc_table_shift;
 	#endif
 /*@-----------HOOK BEFORE REG INIT-----------*/
 /*@===========================================================*/
@@ -882,6 +924,7 @@ struct dm_struct {
 	u32			*interrupt_mask;
 	u8			*bb_op_mode;
 	u32			*manual_supportability;
+	u8			*dis_dym_bw_indication;
 /*@===========================================================*/
 /*@====[ CALL BY VALUE ]===========================================*/
 /*@===========================================================*/
@@ -949,6 +992,7 @@ struct dm_struct {
 	u32			txagc_offset_value_b;
 	boolean			is_txagc_offset_positive_b;
 	u8			ap_total_num;
+	boolean			flatness_type;
 	/*@[traffic]*/
 	u8			traffic_load;
 	u8			pre_traffic_load;
@@ -971,7 +1015,7 @@ struct dm_struct {
 	u8			force_igi;		/*@for debug*/

 	/*@[TDMA-DIG]*/
-	u16			tdma_dig_timer_ms;
+	u8			tdma_dig_timer_ms;
 	u8			tdma_dig_state_number;
 	u8			tdma_dig_low_upper_bond;
 	u8			force_tdma_low_igi;
@@ -1039,13 +1083,17 @@ struct dm_struct {
 	boolean			en_reg_mntr_mac;
 	boolean			en_reg_mntr_byte;
 	/*@--------------------------------------------------------------*/
-#if (RTL8814B_SUPPORT)
-	/*@--- for spur detection ---------------------------------------*/
+#if (RTL8814B_SUPPORT || RTL8812F_SUPPORT || RTL8198F_SUPPORT)
 	u8			dsde_sel;
 	u8			nbi_path_sel;
 	u8			csi_wgt;
-	/*@------------------------------------------*/
 #endif
+#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT)
+	u8			csi_wgt_th_db[5]; /*@wgt 4,3,2,1,0 */
+						  /*    ^ ^ ^ ^ ^  */
+#endif
+	/*@------------------------------------------*/
+
 	/*@--- for noise detection ---------------------------------------*/
 	boolean			is_noisy_state;
 	boolean			noisy_decision; /*@b_noisy*/
@@ -1084,6 +1132,9 @@ struct dm_struct {
 	/*@-----------------------------------------------------------*/

 	boolean			bsomlenabled;	/* @D-SoML control */
+	u8			no_ndp_cnts;
+	u16			ndp_cnt_pre;
+	boolean			is_beamformed;
 	u8			linked_bf_support;
 	boolean			bhtstfdisabled;	/* @dynamic HTSTF gain control*/
 	u32			n_iqk_cnt;
@@ -1144,6 +1195,8 @@ struct dm_struct {
 	u8			power_voltage;
 	u8			cca_cbw20_lev;
 	u8			cca_cbw40_lev;
+	u8			antdiv_gpio;
+	u8			peak_detect_mode;
 #endif

 /*@=== PHYDM Timer ========================================== (start)*/
@@ -1182,10 +1235,14 @@ struct dm_struct {

 	struct	pkt_process_info	pkt_proc_struct;
 	struct phydm_adaptivity_struct	adaptivity;
+#ifdef CONFIG_PHYDM_DFS_MASTER
 	struct _DFS_STATISTICS		dfs;
+#endif
 	struct odm_noise_monitor	noise_level;
 	struct odm_phy_dbg_info		phy_dbg_info;
-
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+	struct odm_phy_dbg_info		phy_dbg_info_win_bkp;
+#endif
 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
 	struct phydm_bf_rate_info_jgr3 bf_rate_info_jgr3;
 #endif
@@ -1213,12 +1270,20 @@ struct dm_struct {
 	struct dm_iqk_info		IQK_info;
 	struct dm_dpk_info		dpk_info;
 	struct dm_dack_info		dack_info;
-
 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
 	struct phydm_fat_struct		dm_fat_table;
 	struct sw_antenna_switch	dm_swat_table;
 #endif
 	struct phydm_dig_struct		dm_dig_table;
+
+#ifdef PHYDM_SUPPORT_CCKPD
+	struct phydm_cckpd_struct	dm_cckpd_table;
+
+	#ifdef PHYDM_DCC_ENHANCE
+	struct phydm_dcc_struct		dm_dcc_info; /*dig cckpd coex*/
+	#endif
+#endif
+
 #ifdef PHYDM_LNA_SAT_CHK_SUPPORT
 	struct phydm_lna_sat_t		dm_lna_sat_info;
 #endif
@@ -1227,10 +1292,6 @@ struct dm_struct {
 	struct _phydm_mcc_dm_ mcc_dm;
 #endif

-#ifdef PHYDM_SUPPORT_CCKPD
-	struct phydm_cckpd_struct	dm_cckpd_table;
-#endif
-
 #ifdef PHYDM_PRIMARY_CCA
 	struct phydm_pricca_struct	dm_pri_cca;
 #endif
@@ -1295,7 +1356,7 @@ struct dm_struct {
 #endif
 /*@==========================================================*/

-#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
+#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
 	/*@-------------------phydm_phystatus report --------------------*/
 	struct phydm_physts dm_physts_table;
 #endif
@@ -1392,7 +1453,7 @@ phydm_txcurrentcalibration(struct dm_struct *dm);
 void
 phydm_dm_early_init(struct dm_struct *dm);

-void
+enum phydm_init_result
 odm_dm_init(struct dm_struct *dm);

 void
@@ -1419,6 +1480,9 @@ phydm_watchdog(struct dm_struct *dm);
 void
 phydm_watchdog_mp(struct dm_struct *dm);

+void
+phydm_pause_func_init(void *dm_void);
+
 u8
 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
 		 enum phydm_pause_type pause_type,
@@ -1431,6 +1495,9 @@ phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
 void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm,
 				enum phydm_pause_type pause_type, u8 rssi);

+void phydm_fw_dm_ctrl_en(void *dm_void, enum phydm_func_idx fun_idx,
+			 boolean enable);
+
 void
 odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info, u64 value);

@@ -1461,6 +1528,21 @@ phydm_dc_cancellation(struct dm_struct *dm);
 void
 phydm_receiver_blocking(void *dm_void);

+void
+phydm_dyn_bw_indication(void *dm_void);
+
+void
+phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en);
+
+
+#ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
+void
+phydm_tx_collsion_th_init(void *dm_void);
+
+void
+phydm_tx_collsion_th_set(void *dm_void, u8 val_r2t, u8 val_t2r);
+#endif
+
 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 void
 odm_init_all_work_items(
--- a/hal/phydm/phydm.mk
+++ b/hal/phydm/phydm.mk
@@ -180,6 +180,7 @@ _PHYDM_FILES +=	hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \
 								hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \
 								hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \
 								hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8821c.o\
 								hal/phydm/halrf/$(RTL871X)/halhwimg8821c_rf.o \
 								hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\
 								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o
@@ -214,6 +215,7 @@ _PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822c_bb.o\
 								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822c.o\
 								hal/phydm/halrf/$(RTL871X)/halrf_tssi_8822c.o\
 								hal/phydm/halrf/$(RTL871X)/halrf_dpk_8822c.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_txgapk_8822c.o\
 								hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822c.o\
 								hal/phydm/halrf/$(RTL871X)/halhwimg8822c_rf.o
 endif
@@ -223,9 +225,25 @@ RTL871X = rtl8814b
 _PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814b_bb.o\
 								hal/phydm/$(RTL871X)/phydm_hal_api8814b.o\
 								hal/phydm/$(RTL871X)/phydm_regconfig8814b.o\
+								hal/phydm/$(RTL871X)/phydm_extraagc8814b.o\
 								hal/phydm/halrf/$(RTL871X)/halhwimg8814b_rf.o\
 								hal/phydm/halrf/$(RTL871X)/halrf_8814b.o \
 								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814b.o \
 								hal/phydm/halrf/$(RTL871X)/halrf_dpk_8814b.o\
-								hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8814b.o
+								hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8814b.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_txgapk_8814b.o
+endif
+ifeq ($(CONFIG_RTL8723F), y)
+RTL871X = rtl8723f
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723f_bb.o\
+								hal/phydm/$(RTL871X)/phydm_hal_api8723f.o\
+								hal/phydm/$(RTL871X)/phydm_regconfig8723f.o\
+								hal/phydm/$(RTL871X)/phydm_rtl8723f.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_8723f.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8723f.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_tssi_8723f.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_dpk_8723f.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_txgapk_8723f.o\
+								hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8723f.o\
+								hal/phydm/halrf/$(RTL871X)/halhwimg8723f_rf.o
 endif
--- a/hal/phydm/phydm_adaptivity.c
+++ b/hal/phydm/phydm_adaptivity.c
@@ -146,6 +146,30 @@ void phydm_check_adaptivity(void *dm_void)
 		*dm->edcca_mode = PHYDM_EDCCA_ADAPT_MODE;
 }

+void phydm_set_l2h_th_ini_win(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	 /*@ [New Format: JGR3]IGI-idx:45 = RSSI:35 = -65dBm*/
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8723F))
+			dm->th_l2h_ini = 45;
+		else if (dm->support_ic_type & ODM_RTL8814B)
+			dm->th_l2h_ini = 49;
+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+	 /*@ [Old Format] -11+base(50) = IGI_idx:39 = RSSI:29 = -71dBm*/
+		if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812)) {
+			dm->th_l2h_ini = -17;
+		} else {
+			if (*dm->band_type == ODM_BAND_5G)
+				dm->th_l2h_ini = -14;
+			else if (*dm->band_type == ODM_BAND_2_4G)
+				dm->th_l2h_ini = -9;
+		}
+	} else { /*ODM_IC_11N_SERIES*/
+		dm->th_l2h_ini = -9;
+	}
+}
 #endif

 void phydm_dig_up_bound_lmt_en(void *dm_void)
@@ -305,7 +329,7 @@ void phydm_set_l2h_th_ini(void *dm_void)

 	 /*@ [New Format: JGR3]IGI-idx:45 = RSSI:35 = -65dBm*/
 	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-		if (dm->support_ic_type & ODM_RTL8822C)
+		if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8723F))
 			dm->th_l2h_ini = 45;
 		else if (dm->support_ic_type & ODM_RTL8814B)
 			dm->th_l2h_ini = 49;
@@ -374,10 +398,8 @@ void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,
 	s8 h2l_diff = 0;

 	for (i = 0; i < 5; i++) {
-		if (input[i + 1]) {
-			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
-			input_idx++;
-		}
+		PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
+		input_idx++;
 	}
 	if (strcmp(input[1], help) == 0) {
 		PDM_SNPF(out_len, used, output + used, out_len - used,
@@ -614,6 +636,9 @@ void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
 	case PHYDM_ADAPINFO_AP_NUM_TH:
 		adaptivity->ap_num_th = (u8)value;
 		break;
+	case PHYDM_ADAPINFO_SWITCH_TH_L2H_INI_IN_BAND:
+		adaptivity->switch_th_l2h_ini_in_band = (u8)value;
+		break;
 	default:
 		break;
 	}
@@ -654,7 +679,8 @@ void phydm_adaptivity_init(void *dm_void)

 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 	if (!dm->carrier_sense_enable) {
-		if (dm->th_l2h_ini == 0)
+		if (dm->th_l2h_ini == 0 &&
+		    !adaptivity->switch_th_l2h_ini_in_band)
 			phydm_set_l2h_th_ini(dm);
 	} else {
 		phydm_set_l2h_th_ini_carrier_sense(dm);
@@ -777,6 +803,11 @@ void phydm_adaptivity(void *dm_void)

 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 	phydm_check_adaptivity(dm); /*@Check adaptivity enable*/
+
+	if (!dm->carrier_sense_enable &&
+	    !adapt->debug_mode &&
+	    adapt->switch_th_l2h_ini_in_band)
+		phydm_set_l2h_th_ini_win(dm);
 #endif

 	PHYDM_DBG(dm, DBG_ADPTVTY, "%s ====>\n", __func__);
--- a/hal/phydm/phydm_adaptivity.h
+++ b/hal/phydm/phydm_adaptivity.h
@@ -66,7 +66,8 @@ enum phydm_adapinfo {
 	PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,
 	PHYDM_ADAPINFO_AP_NUM_TH,
 	PHYDM_ADAPINFO_DOMAIN_CODE_2G,
-	PHYDM_ADAPINFO_DOMAIN_CODE_5G
+	PHYDM_ADAPINFO_DOMAIN_CODE_5G,
+	PHYDM_ADAPINFO_SWITCH_TH_L2H_INI_IN_BAND
 };

 enum phydm_mac_edcca_type {
@@ -100,6 +101,7 @@ struct phydm_adaptivity_struct {
 	s8			th_h2l;
 	u8			regulation_2g;
 	u8			regulation_5g;
+	u8			switch_th_l2h_ini_in_band;
 };

 #ifdef PHYDM_SUPPORT_ADAPTIVITY
--- a/hal/phydm/phydm_adc_sampling.c
+++ b/hal/phydm/phydm_adc_sampling.c
@@ -135,6 +135,23 @@ phydm_la_clk_en(void *dm_void, boolean enable)
 }
 #endif

+#if (RTL8723F_SUPPORT)
+void
+phydm_la_mac_clk_en(void *dm_void, boolean enable)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 val = (enable) ? 1 : 0;
+
+	if (!(dm->support_ic_type & ODM_RTL8723F))
+		return;
+
+	odm_set_mac_reg(dm, R_0x1008, BIT(1), val);
+	/*Set IRAM2/3*/
+	odm_set_mac_reg(dm, R_0x1000, 0xc0, 0x0);
+	odm_set_mac_reg(dm, R_0x1000, 0x3000, 0x3);
+}
+#endif
+
 #if (RTL8197F_SUPPORT)
 void
 phydm_la_stop_dma_8197f(void *dm_void, enum phydm_backup_type opt)
@@ -190,6 +207,70 @@ phydm_la_mv_data_2_tx_buffer(void *dm_void)
 }
 #endif

+
+#if(RTL8723F_SUPPORT)
+void
+phydm_la_mv_data_2_tx_buffer_rtl8723f(void *dm_void,  u32	source, u32	dest, u32 	length)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct rt_adcsmp *smp = &dm->adcsmp;
+	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
+	//u32	ch0ctrl = (BIT(29)|BIT(31));
+	u32	ch0ctrl = BIT(31);
+	u32	cnt=25000;
+
+	pr_debug("GetTxPktBuf from iMEM\n");
+	/*Disable LA mode HW block*/
+	odm_set_mac_reg(dm, R_0x7c0, BIT(0), 0x0);
+
+	/* @move LA mode content from IMEM to TxPktBuffer
+	 * Source : OCPBASE_IMEM 0x14040000
+	 * Destination : OCPBASE_TXBUF 0x18780000
+	 * Length : 32K
+	 */
+	/*
+	OCPBASE_IMEM = 0x18600000;
+	OCPBASE_TXBUF = 0x18780000;
+	GET_HAL_INTERFACE(dm->priv)->init_ddma_handler(dm->priv,
+						       OCPBASE_IMEM,
+						       OCPBASE_TXBUF
+						       + buf->start_pos,
+						       0x8000);
+	*/
+
+	// TODO: Replace all register define & bit define
+
+
+	//check if ddma ch0 is idle
+	while(odm_get_mac_reg(dm, R_0x1208 , BIT(31))){
+		ODM_delay_ms(10);
+		cnt--;
+		if(cnt==0){
+            pr_debug("1 InitDDMA88XX polling fail \n");
+			return;
+		}
+	}
+
+	ch0ctrl |= length & 0x3FFFF;
+
+	//check if chksum continuous
+	//ch0ctrl |= BIT(24);
+
+	odm_set_mac_reg(dm, R_0x1200, MASKDWORD, source); /*0x1200[31:0]:Source Address*/
+	odm_set_mac_reg(dm, R_0x1204, MASKDWORD, dest); /*0x1204[31:0]:Destination Address*/
+	odm_set_mac_reg(dm, R_0x1208, MASKDWORD, ch0ctrl); /*0x1208[17:0]:DMA Length*/
+//check if ddma ch0 is idle
+        while(odm_get_mac_reg(dm, R_0x1208 , BIT(31))){
+                ODM_delay_ms(10);
+                cnt--;
+                if(cnt==0){
+            pr_debug("2 InitDDMA88XX polling fail \n");
+                        return ;
+                }
+        }
+}
+#endif
+
 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT

 void phydm_la_bb_adv_reset_jgr3(void *dm_void)
@@ -822,6 +903,15 @@ void phydm_la_get_tx_pkt_buf(void *dm_void)
 	boolean is_round_up = false;
 	u32 addr_8byte = 0;
 	u32 round_up_point = 0;
+	u32 index = 0;
+	u32 imem_base;
+	u32 txbuf_base;
+	u32 dma_len;
+	u32 imem_start_addr;
+	u32 imem_start_addr_offset;
+	u32 txbuff_start_addr;
+	u32 tx_buff_addr;
+
 	#if (RTL8814B_SUPPORT)
 	boolean recover_success = true;
 	#endif
@@ -872,6 +962,69 @@ void phydm_la_get_tx_pkt_buf(void *dm_void)

 	/*@==== [Get LA Patterns in TXFF] ====================================*/
 	pr_debug("Dump_Start\n");
+#if(RTL8723F_SUPPORT)
+	imem_base = 0x14040000;
+	txbuf_base = 0x18780000;
+	dma_len = 0x8000;
+	txbuff_start_addr = txbuf_base;
+	imem_start_addr_offset = addr;
+	if (is_round_up) {
+		for(index = 0;index < 4;index++) {
+			dma_len = 0x8000;
+			imem_start_addr= imem_base + (imem_start_addr_offset&0x1FFFF);
+
+			if((imem_start_addr_offset + 0x8000) >= buf->end_pos) {
+				dma_len = buf->end_pos-imem_start_addr_offset;
+
+				phydm_la_mv_data_2_tx_buffer_rtl8723f(dm, imem_start_addr, txbuff_start_addr, dma_len);
+
+				tx_buff_addr = 0;
+				for (i = 0; i < (dma_len >> 3); i++) {
+					phydm_la_access_tx_pkt_buf(dm, tx_buff_addr, i << 1);
+					tx_buff_addr += 8;
+				}
+				imem_start_addr = imem_base;
+				dma_len = 0x8000-dma_len;
+				phydm_la_mv_data_2_tx_buffer_rtl8723f(dm, imem_start_addr, txbuff_start_addr, dma_len);
+
+				tx_buff_addr = 0;
+				for (i = 0; i < (dma_len >> 3); i++) {
+					phydm_la_access_tx_pkt_buf(dm, tx_buff_addr, i << 1);
+					tx_buff_addr += 8;
+				}
+				imem_start_addr_offset = dma_len;
+			}
+			else {
+				dma_len = 0x8000;
+				phydm_la_mv_data_2_tx_buffer_rtl8723f(dm, imem_start_addr, txbuff_start_addr, dma_len);
+
+				tx_buff_addr = 0;
+				for (i = 0; i <4096; i++) {
+					phydm_la_access_tx_pkt_buf(dm, tx_buff_addr, i << 1);
+					tx_buff_addr += 8;
+				}
+				imem_start_addr_offset += 0x8000;
+			}
+		}
+	} else {
+		for(index = 0; index < 4;index++) {
+			imem_start_addr = imem_base + (imem_start_addr_offset & 0x1FFFF);
+			if ((imem_start_addr_offset + 0x8000) > (finish_addr << 3))
+				dma_len = (finish_addr << 3) - imem_start_addr_offset; /*0x1208[17:0]:DMA Length*/
+			phydm_la_mv_data_2_tx_buffer_rtl8723f(dm,imem_start_addr, txbuff_start_addr, dma_len);
+			tx_buff_addr = 0;
+			for (i = 0; i < (dma_len >> 3); i++) {
+				phydm_la_access_tx_pkt_buf(dm, tx_buff_addr, i << 1);
+				tx_buff_addr += 8;
+			}
+			dma_len = 0x8000;
+			imem_start_addr_offset += 0x8000;
+			if (imem_start_addr_offset > (finish_addr << 3))
+				break;
+		}
+	}
+#else
+
 	#ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM
 	phydm_la_mv_data_2_tx_buffer(dm);
 	#endif
@@ -894,6 +1047,7 @@ void phydm_la_get_tx_pkt_buf(void *dm_void)
 	#if (RTL8197F_SUPPORT)
 	phydm_la_stop_dma_8197f(dm, PHYDM_RESTORE);
 	#endif
+#endif
 	pr_debug("Dump_End\n");
 }

@@ -929,6 +1083,11 @@ void phydm_la_set_mac_iq_dump(void *dm_void, boolean impossible_trig_condi)
 	/*@Enable LA mode HW block*/
 	odm_set_mac_reg(dm, reg1, BIT(0), 1);

+	#if (RTL8723F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8723F)
+		phydm_la_mac_clk_en(dm, true);
+	#endif
+
 	if (smp->la_trig_mode == PHYDM_MAC_TRIG) {
 		smp->la_dump_mode = LA_MAC_DBG_DUMP;
 		/*polling bit for MAC mode*/
@@ -1130,6 +1289,9 @@ void phydm_la_set_mac_trigger_time(void *dm_void, u32 trigger_time_mu_sec)
 		unit = 5; /*unit: 32mu sec*/
 	else if (trigger_time_mu_sec < 8192)
 		unit = 6; /*unit: 64mu sec*/
+	else if (trigger_time_mu_sec < 16384)
+		if (dm->support_ic_type & ODM_RTL8723F)
+			unit = 7; /*unit: 128mu sec*/

 	time_unit_num = (u8)(trigger_time_mu_sec >> unit);

@@ -1145,6 +1307,9 @@ void phydm_la_set_mac_trigger_time(void *dm_void, u32 trigger_time_mu_sec)
 		odm_set_mac_reg(dm, R_0x7fc, BIT(2) | BIT(1) | BIT(0), unit);
 		odm_set_mac_reg(dm, R_0x7f0, 0x7f00, (time_unit_num & 0x7f));
 	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	} else if (dm->support_ic_type & ODM_RTL8814B) {
+		odm_set_mac_reg(dm, R_0x7cc, BIT(20) | BIT(19) | BIT(18), unit);
+		odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
 	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
 		odm_set_mac_reg(dm, R_0x7cc, BIT(18) | BIT(17) | BIT(16), unit);
 		odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
@@ -1203,6 +1368,10 @@ void phydm_la_set_buff_mode(void *dm_void, enum la_buff_mode mode)
 		buff_size_base = 0x4000;
 		end_pos_tmp = 0x8000;
 		break;
+	case ODM_RTL8723F:
+		buff_size_base = 0x20000;
+		end_pos_tmp = 0x20000;
+		break;
 	default:
 		pr_debug("[%s] Warning!", __func__);
 		break;
@@ -1210,7 +1379,14 @@ void phydm_la_set_buff_mode(void *dm_void, enum la_buff_mode mode)

 	buf->buffer_size = buff_size_base;

-	if (dm->support_ic_type & FULL_BUFF_MODE_SUPPORT) {
+	if (dm->support_ic_type & ODM_RTL8814B) {
+		if (mode == ADCSMP_BUFF_HALF) {
+			odm_set_mac_reg(dm, R_0x7cc, BIT(21), 0);
+		} else {
+			buf->buffer_size = buf->buffer_size << 1;
+			odm_set_mac_reg(dm, R_0x7cc, BIT(21), 1);
+		}
+	} else if (dm->support_ic_type & FULL_BUFF_MODE_SUPPORT) {
 		if (mode == ADCSMP_BUFF_HALF) {
 			odm_set_mac_reg(dm, R_0x7cc, BIT(30), 0);
 		} else {
@@ -1235,6 +1411,7 @@ void phydm_la_adc_smp_start(void *dm_void)
 	u8 tmp_u1b = 0;
 	u8 i = 0;
 	u8 polling_bit = 0;
+	u8 bkp_val = 0;
 	boolean polling_ok = false;
 	boolean impossible_trig_condi = (smp->en_fake_trig) ? true : false;

@@ -1248,6 +1425,9 @@ void phydm_la_adc_smp_start(void *dm_void)
 		 smp->la_trig_mode, smp->la_dbg_port, smp->la_trigger_edge,
 		 smp->la_smp_rate, smp->la_trig_sig_sel, smp->la_dma_type);

+	if(dm->support_ic_type & ODM_RTL8723F)
+		bkp_val = (u8)odm_get_mac_reg(dm, R_0x1008, BIT(1));
+
 	phydm_la_set_mac_trigger_time(dm, smp->la_trigger_time);
 	phydm_la_set_bb(dm);
 	phydm_la_set_bb_dbg_port(dm, impossible_trig_condi);
@@ -1323,6 +1503,10 @@ void phydm_la_adc_smp_start(void *dm_void)
 		#if (RTL8821C_SUPPORT || RTL8195B_SUPPORT)
 		phydm_la_clk_en(dm, false);
 		#endif
+		#if (RTL8723F_SUPPORT)
+		if(dm->support_ic_type & ODM_RTL8723F)
+			phydm_la_mac_clk_en(dm, (bkp_val == 1) ? true : false);
+		#endif
 	} else {
 		smp->la_count--;
 		pr_debug("LA Dump more ---------->\n\n\n");
@@ -1563,6 +1747,9 @@ void phydm_la_init(void *dm_void)
 	struct rt_adcsmp *smp = &dm->adcsmp;
 	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;

+	if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE))
+		return;
+
 	smp->adc_smp_state = ADCSMP_STATE_IDLE;
 	smp->is_la_print = true;
 	smp->en_fake_trig = false;
@@ -1578,6 +1765,9 @@ void adc_smp_de_init(void *dm_void)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;

+	if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE))
+		return;
+
 	phydm_la_stop(dm);
 	phydm_la_buffer_release(dm);
 }
@@ -1594,98 +1784,4 @@ void adc_smp_work_item_callback(void *context)
 	phydm_la_adc_smp_start(dm);
 }
 #endif
-
-#if 0
-#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-enum rt_status
-adc_smp_query(void *dm_void, ULONG info_buf_length, void *info_buf,
-	      PULONG bytes_written)
-{
-	struct dm_struct *dm = (struct dm_struct *)dm_void;
-	struct rt_adcsmp *smp = &dm->adcsmp;
-	enum rt_status ret_status = RT_STATUS_SUCCESS;
-	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
-
-	pr_debug("[%s] LA_State=((%d))", __func__, smp->adc_smp_state);
-
-	if (info_buf_length != buf->buffer_size) {
-		*bytes_written = 0;
-		ret_status = RT_STATUS_RESOURCE;
-	} else if (buf->length != buf->buffer_size) {
-		*bytes_written = 0;
-		ret_status = RT_STATUS_RESOURCE;
-	} else if (smp->adc_smp_state != ADCSMP_STATE_QUERY) {
-		*bytes_written = 0;
-		ret_status = RT_STATUS_PENDING;
-	} else {
-		odm_move_memory(dm, info_buf, buf->octet, buf->buffer_size);
-		*bytes_written = buf->buffer_size;
-
-		smp->adc_smp_state = ADCSMP_STATE_IDLE;
-	}
-
-	pr_debug("Return status %d\n", ret_status);
-
-	return ret_status;
-}
-#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-
-void adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused)
-{
-	struct dm_struct *dm = (struct dm_struct *)dm_void;
-	struct rt_adcsmp *smp = &dm->adcsmp;
-	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
-	u32 used = *pused;
-	u32 i = 0;
-#if 0
-	/* struct timespec t; */
-	/* rtw_get_current_timespec(&t); */
-#endif
-
-	pr_debug("%s adc_smp_state %d", __func__, smp->adc_smp_state);
-
-	for (i = 0; i < (buf->length >> 2) - 2; i += 2) {
-		PDM_SNPF(out_len, used, output + used, out_len - used,
-			 "%08x%08x\n", buf->octet[i], buf->octet[i + 1]);
-	}
-
-	PDM_SNPF(out_len, used, output + used, out_len - used, "\n");
-	/* PDM_SNPF(output + used, out_len - used, "\n[%lu.%06lu]\n", */
-	/*	    t.tv_sec, t.tv_nsec); */
-	*pused = used;
-}
-
-s32 adc_smp_get_sample_counts(void *dm_void)
-{
-	struct dm_struct *dm = (struct dm_struct *)dm_void;
-	struct rt_adcsmp *smp = &dm->adcsmp;
-	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
-
-	return (buf->length >> 2) - 2;
-}
-
-s32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len, u32 idx)
-{
-	struct dm_struct *dm = (struct dm_struct *)dm_void;
-	struct rt_adcsmp *smp = &dm->adcsmp;
-	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
-	u32 used = 0;
-
-	/* @dbg_print("%s adc_smp_state %d\n", __func__,*/
-	/*	      smp->adc_smp_state);*/
-	if (smp->adc_smp_state != ADCSMP_STATE_QUERY) {
-		PDM_SNPF(out_len, used, output + used, out_len - used,
-			 "Error: la data is not ready yet ...\n");
-		return -1;
-	}
-
-	if (idx < ((buf->length >> 2) - 2)) {
-		PDM_SNPF(out_len, used, output + used, out_len - used,
-			 "%08x%08x\n", buf->octet[idx], buf->octet[idx + 1]);
-	}
-	return 0;
-}
-#endif
-#endif
-
 #endif /*@endif PHYDM_LA_MODE_SUPPORT*/
--- a/hal/phydm/phydm_adc_sampling.h
+++ b/hal/phydm/phydm_adc_sampling.h
@@ -28,8 +28,8 @@

 #if (PHYDM_LA_MODE_SUPPORT)

-/* fix compile time flag*/
-#define DYNAMIC_LA_MODE "4.1"
+/* 2020.07.03 [8723F] Fix SD4 compile error*/
+#define DYNAMIC_LA_MODE "4.2"

 /* @1 ============================================================
 * 1  Definition
@@ -168,22 +168,5 @@ void adc_smp_de_init(void *dm_void);
 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 void adc_smp_work_item_callback(void *context);
 #endif
-
-#if 0
-#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-enum rt_status adc_smp_query(void *dm_void, ULONG info_buf_length,
-			     void *info_buf, PULONG bytes_written);
-
-#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-
-void adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused);
-
-s32 adc_smp_get_sample_counts(void *dm_void);
-
-s32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len,
-			      u32 idx);
-#endif
-#endif
-
 #endif
 #endif
--- a/hal/phydm/phydm_antdect.c
+++ b/hal/phydm/phydm_antdect.c
@@ -190,9 +190,6 @@ odm_single_dual_antenna_detection(

 	/* @change to Antenna B */
 	if (dm->support_ic_type & ODM_RTL8723B) {
-#if 0
-		/* odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x2); */
-#endif
 		odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
 		odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
 	}
--- a/hal/phydm/phydm_antdiv.c
+++ b/hal/phydm/phydm_antdiv.c
--- a/hal/phydm/phydm_antdiv.h
+++ b/hal/phydm/phydm_antdiv.h
@@ -84,20 +84,26 @@

 #define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B |\
 			ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A |\
-			ODM_RTL8197F | ODM_RTL8721D)
+			ODM_RTL8197F | ODM_RTL8721D | ODM_RTL8710C)
 #define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 |\
-			ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B)
-#define ODM_ANTDIV_SUPPORT	(ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT)
+			ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B |\
+			ODM_RTL8195B)
+#define ODM_JGR3_ANTDIV_SUPPORT (ODM_RTL8197G | ODM_RTL8723F)
+#define ODM_ANTDIV_SUPPORT	(ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT |\
+			ODM_JGR3_ANTDIV_SUPPORT)
 #define ODM_SMART_ANT_SUPPORT	(ODM_RTL8188E | ODM_RTL8192E)
 #define ODM_HL_SMART_ANT_TYPE1_SUPPORT		(ODM_RTL8821 | ODM_RTL8822B)

 #define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B |\
 			ODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D |\
-			ODM_RTL8197F)
+			ODM_RTL8197F | ODM_RTL8197G|ODM_RTL8723F)
 #define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 |\
-			ODM_RTL8821C | ODM_RTL8822B)
+			ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8195B|ODM_RTL8723F)

-#define ODM_EVM_ANTDIV_IC (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8822B)
+#define ODM_ANTDIV_SUPPORT_IC (ODM_ANTDIV_2G_SUPPORT_IC | ODM_ANTDIV_5G_SUPPORT_IC)
+
+#define ODM_EVM_ANTDIV_IC (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8822B |\
+			ODM_RTL8197G)

 #define ODM_ANTDIV_2G	BIT(0)
 #define ODM_ANTDIV_5G	BIT(1)
@@ -168,7 +174,7 @@
 /*@Hong Lin Smart antenna*/
 #define HL_SMTANT_2WIRE_DATA_LEN 24

-#if (RTL8723D_SUPPORT == 1)
+#if (RTL8723D_SUPPORT == 1 || RTL8710C_SUPPORT == 1)
 	#ifndef CONFIG_ANTDIV_PERIOD
 		#define CONFIG_ANTDIV_PERIOD 1
 	#endif
@@ -324,7 +330,7 @@ struct phydm_fat_struct {
 	u8	pre_antdiv_rssi;
 	u8	pre_antdiv_tp;
 #endif
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
 	u32    cck_ctrl_frame_cnt_main;
 	u32    cck_ctrl_frame_cnt_aux;
 	u32    ofdm_ctrl_frame_cnt_main;
@@ -334,6 +340,7 @@ struct phydm_fat_struct {
 	u32	main_ctrl_cnt;
 	u32	aux_ctrl_cnt;
 #endif
+
 	u8	b_fix_tx_ant;
 	boolean	fix_ant_bfee;
 	boolean	enable_ctrl_frame_antdiv;
@@ -347,6 +354,9 @@ struct phydm_fat_struct {
 	/*@A temp value, will hook to driver team's outer parameter later*/
 	u8	*p_default_s0_s1;
 	u8	default_s0_s1;
+	u8 ant_idx_vec[3]; /* for SP3T only, added by Jiao Qi on June.6,2020*/
+
+
 };

 /* @1 ============================================================
@@ -404,6 +414,8 @@ void phydm_antdiv_reset_statistic(void *dm_void, u32 macid);

 void odm_update_rx_idle_ant(void *dm_void, u8 ant);

+void odm_update_rx_idle_ant_sp3t(void *dm_void, u8 ant);
+
 void phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant);

 void phydm_set_antdiv_val(void *dm_void, u32 *val_buf,	u8 val_len);
@@ -439,6 +451,10 @@ void odm_sw_antdiv_workitem_callback(void *context);

 void odm_sw_antdiv_callback(void *function_context);

+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
+
+void odm_sw_antdiv_callback(void *dm_void);
+
 #endif

 void odm_s0s1_sw_ant_div_by_ctrl_frame(void *dm_void, u8 step);
--- a/hal/phydm/phydm_api.c
+++ b/hal/phydm/phydm_api.c
@@ -31,12 +31,36 @@
 #include "mp_precomp.h"
 #include "phydm_precomp.h"

+enum channel_width phydm_rxsc_2_bw(void *dm_void, u8 rxsc)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	enum channel_width bw = 0;
+
+	/* @Check RX bandwidth */
+	if (rxsc == 0)
+		bw = *dm->band_width; /*@full bw*/
+	else if (rxsc >= 1 && rxsc <= 8)
+		bw = CHANNEL_WIDTH_20;
+	else if (rxsc >= 9 && rxsc <= 12)
+		bw = CHANNEL_WIDTH_40;
+	else /*if (rxsc >= 13)*/
+		bw = CHANNEL_WIDTH_80;
+
+	return bw;
+}
+
 void phydm_reset_bb_hw_cnt(void *dm_void)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;

 	/*@ Reset all counter when 1 */
 	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		#if (RTL8723F_SUPPORT)
+		if (dm->support_ic_type & ODM_RTL8723F) {
+			odm_set_bb_reg(dm, R_0x2a44, BIT(21), 0);
+			odm_set_bb_reg(dm, R_0x2a44, BIT(21), 1);
+		}
+		#endif
 		odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 1);
 		odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 0);
 	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
@@ -83,6 +107,11 @@ void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used,
 	u32 used = *_used;
 	u32 out_len = *_out_len;

+	if (!(dm->support_ic_type &
+	    (ODM_RTL8192F | ODM_RTL8822B | ODM_RTL8812 | ODM_RTL8197F))) {
+		return;
+	}
+
 	if ((strcmp(input[1], help) == 0)) {
 		PDM_SNPF(out_len, used, output + used, out_len - used,
 			 "echo dis_dym_ant_weighting {0/1}\n");
@@ -112,9 +141,8 @@ void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path)
 	u8 path_bitmap = 1;

 	path_bitmap = (u8)phydm_gen_bitmask(num_rf_path);
-#if 0
+
 	/*PHYDM_DBG(dm, ODM_COMP_INIT, "path_bitmap=0x%x\n", path_bitmap);*/
-#endif

 	dm->tx_ant_status = path_bitmap;
 	dm->rx_ant_status = path_bitmap;
@@ -331,7 +359,7 @@ void phydm_config_trx_path_v2(void *dm_void, char input[][16], u32 *_used,
 {
 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\
 	RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8197G_SUPPORT ||\
-	RTL8812F_SUPPORT)
+	RTL8812F_SUPPORT || RTL8198F_SUPPORT)
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	u32 used = *_used;
 	u32 out_len = *_out_len;
@@ -343,14 +371,12 @@ void phydm_config_trx_path_v2(void *dm_void, char input[][16], u32 *_used,

 	if (!(dm->support_ic_type &
 	    (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8822C |
-	     ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8197G)))
+	     ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8197G | ODM_RTL8198F)))
 		return;

 	for (i = 0; i < 5; i++) {
-		if (input[i + 1]) {
-			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
-			input_idx++;
-		}
+		PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
+		input_idx++;
 	}

 	if (input_idx == 0)
@@ -476,11 +502,11 @@ void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used,
 		#endif
 	} else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F |
 		   ODM_RTL8192F | ODM_RTL8822C | ODM_RTL8812F |
-		   ODM_RTL8197G | ODM_RTL8814B)) {
+		   ODM_RTL8197G | ODM_RTL8814B | ODM_RTL8198F)) {
 		#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT ||\
 		     RTL8192F_SUPPORT || RTL8822C_SUPPORT ||\
 		     RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\
-		     RTL8197G_SUPPORT)
+		     RTL8197G_SUPPORT || RTL8198F_SUPPORT)
 		phydm_config_trx_path_v2(dm, input, _used, output, _out_len);
 		#endif
 	}
@@ -581,20 +607,22 @@ u8 phydm_stop_ic_trx(void *dm_void, u8 set_type)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	struct phydm_api_stuc *api = &dm->api_table;
-	u32 i = 0;
-	u8 trx_idle_success = false;
+	u8 i = 0;
+	boolean trx_idle_success = false;
 	u32 dbg_port_value = 0;

 	if (set_type == PHYDM_SET) {
-	/*@[Stop TRX]---------------------------------------------------------*/
-		/*set debug port to 0x0*/
-		if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0x0))
-			return PHYDM_SET_FAIL;
-
-		for (i = 0; i < 100; i++) {
-			dbg_port_value = phydm_get_bb_dbg_port_val(dm);
-
-			if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+	/*[Stop TRX]---------------------------------------------------------*/
+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+			#if (RTL8723F_SUPPORT)
+			/*Judy 2020-0515*/
+			/*set debug port to 0x0*/
+			if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0x0))
+				return PHYDM_SET_FAIL;
+			#endif
+			for (i = 0; i < 100; i++) {
+				dbg_port_value = odm_get_bb_reg(dm, R_0x2db4,
+								MASKDWORD);
 				/* BB idle */
 				if ((dbg_port_value & 0x1FFEFF3F) == 0 &&
 				    (dbg_port_value & 0xC0010000) ==
@@ -606,10 +634,17 @@ u8 phydm_stop_ic_trx(void *dm_void, u8 set_type)
 					trx_idle_success = true;
 					break;
 				}
-			} else {
+			}
+		} else {
+			/*set debug port to 0x0*/
+			if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0x0))
+				return PHYDM_SET_FAIL;
+			for (i = 0; i < 100; i++) {
+				dbg_port_value = phydm_get_bb_dbg_port_val(dm);
 				/* PHYTXON && CCA_all */
 				if (dm->support_ic_type & (ODM_RTL8721D |
-							    ODM_RTL8710C)) {
+					ODM_RTL8710B | ODM_RTL8710C |
+					ODM_RTL8188F | ODM_RTL8723D)) {
 					if ((dbg_port_value &
 					    (BIT(20) | BIT(15))) == 0) {
 						PHYDM_DBG(dm, ODM_COMP_API,
@@ -630,10 +665,10 @@ u8 phydm_stop_ic_trx(void *dm_void, u8 set_type)
 						break;
 					}
 				}
+				ODM_delay_ms(1);
 			}
-			ODM_delay_ms(1);
+			phydm_release_bb_dbg_port(dm);
 		}
-		phydm_release_bb_dbg_port(dm);

 		if (trx_idle_success) {
 			api->tx_queue_bitmap = odm_read_1byte(dm, R_0x522);
@@ -642,15 +677,15 @@ u8 phydm_stop_ic_trx(void *dm_void, u8 set_type)
 			odm_set_mac_reg(dm, R_0x520, 0xff0000, 0xff);

 			if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-				/*@disable OFDM RX CCA*/
-				odm_set_bb_reg(dm, R_0x1c68, BIT(24), 1);
+				/*disable OFDM RX CCA*/
+				odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x1ff);
 			} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-				/*@disable OFDM RX CCA*/
+				/*disable OFDM RX CCA*/
 				odm_set_bb_reg(dm, R_0x838, BIT(1), 1);
 			} else {
 				api->rxiqc_reg1 = odm_read_4byte(dm, R_0xc14);
 				api->rxiqc_reg2 = odm_read_4byte(dm, R_0xc1c);
-				/* @[ Set IQK Matrix = 0 ]
+				/* [ Set IQK Matrix = 0 ]
 				 * equivalent to [ Turn off CCA]
 				 */
 				odm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0);
@@ -669,7 +704,7 @@ u8 phydm_stop_ic_trx(void *dm_void, u8 set_type)

 		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
 			/*@enable OFDM RX CCA*/
-			odm_set_bb_reg(dm, R_0x1c68, BIT(24), 0);
+			odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x0);
 		} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 			/*@enable OFDM RX CCA*/
 			odm_set_bb_reg(dm, R_0x838, BIT(1), 0);
@@ -690,12 +725,20 @@ void phydm_dis_cck_trx(void *dm_void, u8 set_type)

 	if (set_type == PHYDM_SET) {
 		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-			api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0x1a04,
-							     0xf0000000);
-			/* @CCK RxIQ weighting = [0,0] */
-			odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
-			/* @disable CCK Tx */
-			odm_set_bb_reg(dm, R_0x1a04, 0xf0000000, 0x0);
+			if(dm->support_ic_type & ODM_RTL8723F) {
+				api->ccktx_path = 1;
+				/* @disable CCK CCA */
+				odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x1);
+				/* @disable CCK Tx */
+				odm_set_bb_reg(dm, R_0x2a00, BIT(1), 0x1);
+			} else {
+				api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0x1a04,
+							     	0xf0000000);
+				/* @CCK RxIQ weighting = [0,0] */
+				odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
+				/* @disable CCK Tx */
+				odm_set_bb_reg(dm, R_0x1a04, 0xf0000000, 0x0);
+			}
 		} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 			api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0xa04,
 							     0xf0000000);
@@ -713,11 +756,18 @@ void phydm_dis_cck_trx(void *dm_void, u8 set_type)
 		}
 	} else if (set_type == PHYDM_REVERT) {
 		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-			/* @CCK RxIQ weighting = [1,1] */
-			odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
-			/* @enable CCK Tx */
-			odm_set_bb_reg(dm, R_0x1a04, 0xf0000000,
-				       api->ccktx_path);
+			if(dm->support_ic_type & ODM_RTL8723F) {
+				/* @enable CCK CCA */
+				odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x0);
+				/* @enable CCK Tx */
+				odm_set_bb_reg(dm, R_0x2a00, BIT(1), 0x0);
+			} else {
+				/* @CCK RxIQ weighting = [1,1] */
+				odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
+				/* @enable CCK Tx */
+				odm_set_bb_reg(dm, R_0x1a04, 0xf0000000,
+				       	api->ccktx_path);
+			}
 		} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 			/* @enable CCK block */
 			odm_set_bb_reg(dm, R_0x808, BIT(28), 1);
@@ -733,6 +783,57 @@ void phydm_dis_cck_trx(void *dm_void, u8 set_type)
 		}
 	}
 }
+
+void phydm_bw_fixed_enable(void *dm_void, u8 enable)
+{
+#ifdef CONFIG_BW_INDICATION
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	boolean val = (enable == FUNC_ENABLE) ? 1 : 0;
+
+	if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8195B))
+		odm_set_bb_reg(dm, R_0x840, BIT(4), val);
+	else if (dm->support_ic_type & ODM_RTL8822C)
+		odm_set_bb_reg(dm, R_0x878, BIT(28), val);
+#endif
+}
+
+void phydm_bw_fixed_setting(void *dm_void)
+{
+#ifdef CONFIG_BW_INDICATION
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_api_stuc *api = &dm->api_table;
+	u8 bw = *dm->band_width;
+	u32 reg = 0, reg_mask = 0, reg_value = 0;
+
+	if (!(dm->support_ic_type & ODM_DYM_BW_INDICATION_SUPPORT))
+		return;
+
+	if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B |
+	    ODM_RTL8195B)) {
+		reg = R_0x840;
+		reg_mask = 0xf;
+		reg_value = api->pri_ch_idx;
+	} else if (dm->support_ic_type & ODM_RTL8822C) {
+		reg = R_0x878;
+		reg_mask = 0xc0000000;
+		reg_value = 0x0;
+	}
+
+	switch (bw) {
+	case CHANNEL_WIDTH_80:
+		odm_set_bb_reg(dm, reg, reg_mask, reg_value);
+		break;
+	case CHANNEL_WIDTH_40:
+		odm_set_bb_reg(dm, reg, reg_mask, reg_value);
+		break;
+	default:
+		odm_set_bb_reg(dm, reg, reg_mask, 0x0);
+	}
+
+	phydm_bw_fixed_enable(dm, FUNC_ENABLE);
+#endif
+}
+
 void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch)
 {
 #if (RTL8821A_SUPPORT || RTL8881A_SUPPORT)
@@ -968,7 +1069,8 @@ void phydm_nbi_enable(void *dm_void, u32 enable)
 			odm_set_bb_reg(dm, R_0xc40, BIT(9), val);
 		}
 	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-		if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
+		if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C |
+		    ODM_RTL8195B)) {
 			odm_set_bb_reg(dm, R_0x87c, BIT(13), val);
 			odm_set_bb_reg(dm, R_0xc20, BIT(28), val);
 			if (dm->rf_type > RF_1T1R)
@@ -1135,7 +1237,154 @@ u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw,
 	return set_result;
 }

+boolean phydm_spur_case_mapping(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 channel = *dm->channel, bw = *dm->band_width;
+	boolean mapping_result = false;
+#if (RTL8814B_SUPPORT == 1)
+	if (channel == 153 && bw == CHANNEL_WIDTH_20)
+		mapping_result =  true;
+	else if (channel == 151 && bw == CHANNEL_WIDTH_40)
+		mapping_result =  true;
+	else if (channel == 155 && bw == CHANNEL_WIDTH_80)
+		mapping_result =  true;
+#endif
+	return mapping_result;
+}
+
+enum odm_rf_band phydm_ch_to_rf_band(void *dm_void, u8 central_ch)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	enum odm_rf_band rf_band = ODM_RF_BAND_5G_LOW;
+
+	if (central_ch <= 14)
+		rf_band = ODM_RF_BAND_2G;
+	else if (central_ch >= 36 && central_ch <= 64)
+		rf_band = ODM_RF_BAND_5G_LOW;
+	else if ((central_ch >= 100) && (central_ch <= 144))
+		rf_band = ODM_RF_BAND_5G_MID;
+	else if (central_ch >= 149)
+		rf_band = ODM_RF_BAND_5G_HIGH;
+	else
+		PHYDM_DBG(dm, ODM_COMP_API, "mapping channel to band fail\n");
+
+	return rf_band;
+}
+
 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+u32 phydm_rf_psd_jgr3(void *dm_void, u8 path, u32 tone_idx)
+{
+#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 reg_1b04 = 0, reg_1b08 = 0, reg_1b0c_11_10 = 0;
+	u32 reg_1b14 = 0, reg_1b18 = 0, reg_1b1c = 0;
+	u32 reg_1b28 = 0;
+	u32 reg_1bcc_5_0 = 0;
+	u32 reg_1b2c_27_16 = 0, reg_1b34 = 0, reg_1bd4 = 0;
+	u32 reg_180c = 0, reg_410c = 0, reg_520c = 0, reg_530c = 0;
+	u32 igi = 0;
+	u32 i = 0;
+	u32 psd_val = 0, psd_val_msb = 0, psd_val_lsb = 0, psd_max = 0;
+	u32 psd_status_temp = 0;
+	u16 poll_cnt = 0;
+
+	/*read and record the ori. value*/
+	reg_1b04 = odm_get_bb_reg(dm, R_0x1b04, MASKDWORD);
+	reg_1b08 = odm_get_bb_reg(dm, R_0x1b08, MASKDWORD);
+	reg_1b0c_11_10 = odm_get_bb_reg(dm, R_0x1b0c, 0xc00);
+	reg_1b14 = odm_get_bb_reg(dm, R_0x1b14, MASKDWORD);
+	reg_1b18 = odm_get_bb_reg(dm, R_0x1b18, MASKDWORD);
+	reg_1b1c = odm_get_bb_reg(dm, R_0x1b1c, MASKDWORD);
+	reg_1b28 = odm_get_bb_reg(dm, R_0x1b28, MASKDWORD);
+	reg_1bcc_5_0 = odm_get_bb_reg(dm, R_0x1bcc, 0x3f);
+	reg_1b2c_27_16 = odm_get_bb_reg(dm, R_0x1b2c, 0xfff0000);
+	reg_1b34 = odm_get_bb_reg(dm, R_0x1b34, MASKDWORD);
+	reg_1bd4 = odm_get_bb_reg(dm, R_0x1bd4, MASKDWORD);
+	igi = odm_get_bb_reg(dm, R_0x1d70, MASKDWORD);
+	reg_180c = odm_get_bb_reg(dm, R_0x180c, 0x3);
+	reg_410c = odm_get_bb_reg(dm, R_0x410c, 0x3);
+	reg_520c = odm_get_bb_reg(dm, R_0x520c, 0x3);
+	reg_530c = odm_get_bb_reg(dm, R_0x530c, 0x3);
+
+	/*rf psd reg setting*/
+	odm_set_bb_reg(dm, R_0x1b00, 0x6, path); /*path is RF_path*/
+	odm_set_bb_reg(dm, R_0x1b04, MASKDWORD, 0x0);
+	odm_set_bb_reg(dm, R_0x1b08, MASKDWORD, 0x80);
+	odm_set_bb_reg(dm, R_0x1b0c, 0xc00, 0x3);
+	odm_set_bb_reg(dm, R_0x1b14, MASKDWORD, 0x0);
+	odm_set_bb_reg(dm, R_0x1b18, MASKDWORD, 0x1);
+/*#if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/
+	odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, 0x82103D21);
+/*#else*/
+	/*odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, 0x821A3D21);*/
+/*#endif*/
+	odm_set_bb_reg(dm, R_0x1b28, MASKDWORD, 0x0);
+	odm_set_bb_reg(dm, R_0x1bcc, 0x3f, 0x3f);
+	odm_set_bb_reg(dm, R_0x8a0, 0xf, 0x0); /* AGC off */
+	odm_set_bb_reg(dm, R_0x1d70, MASKDWORD, 0x20202020);
+
+	for (i = tone_idx - 1; i <= tone_idx + 1; i++) {
+		/*set psd tone_idx for detection*/
+		odm_set_bb_reg(dm, R_0x1b2c, 0xfff0000, i);
+		/*one shot for RXIQK psd*/
+		odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x1);
+		odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x0);
+
+		if (dm->support_ic_type & ODM_RTL8814B)
+			for (poll_cnt = 0; poll_cnt < 20; poll_cnt++) {
+				odm_set_bb_reg(dm, R_0x1bd4, 0x3f0000, 0x2b);
+				psd_status_temp = odm_get_bb_reg(dm, R_0x1bfc,
+								 BIT(1));
+				if (!psd_status_temp)
+					ODM_delay_us(10);
+				else
+					break;
+			}
+		else
+			ODM_delay_us(250);
+
+		/*read RxIQK power*/
+		odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00250001);
+		if (dm->support_ic_type & ODM_RTL8814B)
+			psd_val_msb = odm_get_bb_reg(dm, R_0x1bfc, 0x7ff0000);
+		else if (dm->support_ic_type & ODM_RTL8198F)
+			psd_val_msb = odm_get_bb_reg(dm, R_0x1bfc, 0x1f0000);
+
+		odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x002e0001);
+		psd_val_lsb = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
+		if (dm->support_ic_type & ODM_RTL8814B)
+			psd_val = (psd_val_msb << 21) + (psd_val_lsb >> 11);
+		else if (dm->support_ic_type & ODM_RTL8198F)
+			psd_val = (psd_val_msb << 27) + (psd_val_lsb >> 5);
+
+		if (psd_val > psd_max)
+			psd_max = psd_val;
+	}
+
+	/*refill the ori. value*/
+	odm_set_bb_reg(dm, R_0x1b00, 0x6, path);
+	odm_set_bb_reg(dm, R_0x1b04, MASKDWORD, reg_1b04);
+	odm_set_bb_reg(dm, R_0x1b08, MASKDWORD, reg_1b08);
+	odm_set_bb_reg(dm, R_0x1b0c, 0xc00, reg_1b0c_11_10);
+	odm_set_bb_reg(dm, R_0x1b14, MASKDWORD, reg_1b14);
+	odm_set_bb_reg(dm, R_0x1b18, MASKDWORD, reg_1b18);
+	odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, reg_1b1c);
+	odm_set_bb_reg(dm, R_0x1b28, MASKDWORD, reg_1b28);
+	odm_set_bb_reg(dm, R_0x1bcc, 0x3f, reg_1bcc_5_0);
+	odm_set_bb_reg(dm, R_0x1b2c, 0xfff0000, reg_1b2c_27_16);
+	odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, reg_1b34);
+	odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, reg_1bd4);
+	odm_set_bb_reg(dm, R_0x8a0, 0xf, 0xf); /* AGC on */
+	odm_set_bb_reg(dm, R_0x1d70, MASKDWORD, igi);
+	PHYDM_DBG(dm, ODM_COMP_API, "psd_max %d\n", psd_max);
+
+	return psd_max;
+#else
+	return 0;
+#endif
+}
+
 u8 phydm_find_intf_distance_jgr3(void *dm_void, u32 bw, u32 fc,
 				 u32 f_interference, u32 *tone_idx_tmp_in)
 {
@@ -1144,6 +1393,7 @@ u8 phydm_find_intf_distance_jgr3(void *dm_void, u32 bw, u32 fc,
 	u32 int_distance = 0;
 	u32 tone_idx_tmp = 0;
 	u8 set_result = PHYDM_SET_NO_NEED;
+	u8 channel = *dm->channel;

 	bw_up = 1000 * (fc + bw / 2);
 	bw_low = 1000 * (fc - bw / 2);
@@ -1156,7 +1406,11 @@ u8 phydm_find_intf_distance_jgr3(void *dm_void, u32 bw, u32 fc,
 	if (f_interference >= bw_low && f_interference <= bw_up) {
 		int_distance = DIFF_2(fc, f_interference);
 		/*@10*(int_distance /0.3125)*/
-		tone_idx_tmp = ((int_distance + 156) / 312);
+		if (channel < 15 &&
+		    (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8198F)))
+			tone_idx_tmp = int_distance / 312;
+		else
+			tone_idx_tmp = ((int_distance + 156) / 312);
 		PHYDM_DBG(dm, ODM_COMP_API,
 			  "int_distance = ((%d)) , tone_idx_tmp = ((%d))\n",
 			  int_distance, tone_idx_tmp);
@@ -1166,6 +1420,7 @@ u8 phydm_find_intf_distance_jgr3(void *dm_void, u32 bw, u32 fc,

 	return set_result;
 }
+
 u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw,
 			       u32 f_intf, u32 sec_ch, u8 wgt)
 {
@@ -1220,12 +1475,14 @@ void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
 			     u8 wgt)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
-	u32 reg_tmp_value = 0;
+	u32 multi_tone_idx_tmp = 0;
+	u32 reg_tmp = 0;
 	u32 tone_num = 64;
 	u32 table_addr = 0;
 	u32 addr = 0;
 	u8 rf_bw = 0;
 	u8 value = 0;
+	u8 channel = *dm->channel;

 	rf_bw = odm_read_1byte(dm, R_0x9b0);
 	if (((rf_bw & 0xc) >> 2) == 0x2)
@@ -1244,23 +1501,160 @@ void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
 	}
 	table_addr = tone_idx_tmp >> 1;

-	reg_tmp_value = odm_read_4byte(dm, R_0x1d94);
+	reg_tmp = odm_read_4byte(dm, R_0x1d94);
 	PHYDM_DBG(dm, ODM_COMP_API,
 		  "Pre Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
-		  tone_idx_tmp, reg_tmp_value);
+		  tone_idx_tmp, reg_tmp);
 	odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3);
 	odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1);
-	odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, (table_addr & 0xff));
-	if (tone_idx_tmp % 2)
-		value = (BIT(3) | (wgt & 0x7)) << 4;
-	else
-		value = BIT(3) | (wgt & 0x7);

-	odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
-	reg_tmp_value = odm_read_4byte(dm, R_0x1d94);
-	PHYDM_DBG(dm, ODM_COMP_API,
-		  "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
-		  tone_idx_tmp, reg_tmp_value);
+	if (channel < 15 &&
+	    (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8198F))) {
+		if (tone_idx_tmp % 2 == 1) {
+			if (tone_direction == FREQ_POSITIVE) {
+				/*===Tone 1===*/
+				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
+					       (table_addr & 0xff));
+				value = (BIT(3) | (wgt & 0x7)) << 4;
+				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
+				reg_tmp = odm_read_4byte(dm, R_0x1d94);
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "New Mask tone 1 idx[%d]: Reg0x1d94 = ((0x%x))\n",
+					  tone_idx_tmp, reg_tmp);
+				/*===Tone 2===*/
+				value = 0;
+				multi_tone_idx_tmp = tone_idx_tmp + 1;
+				table_addr = multi_tone_idx_tmp >> 1;
+				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
+					       (table_addr & 0xff));
+				value = (BIT(3) | (wgt & 0x7));
+				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
+				reg_tmp = odm_read_4byte(dm, R_0x1d94);
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "New Mask tone 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
+					  tone_idx_tmp, reg_tmp);
+			} else {
+				/*===Tone 1 & 2===*/
+				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
+					       (table_addr & 0xff));
+				value = ((BIT(3) | (wgt & 0x7)) << 4) |
+					(BIT(3) | (wgt & 0x7));
+				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
+				reg_tmp = odm_read_4byte(dm, R_0x1d94);
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "New Mask tone 1 & 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
+					  tone_idx_tmp, reg_tmp);
+			}
+		} else {
+			if (tone_direction == FREQ_POSITIVE) {
+				/*===Tone 1 & 2===*/
+				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
+					       (table_addr & 0xff));
+				value = ((BIT(3) | (wgt & 0x7)) << 4) |
+					(BIT(3) | (wgt & 0x7));
+				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
+				reg_tmp = odm_read_4byte(dm, R_0x1d94);
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "New Mask tone 1 & 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
+					  tone_idx_tmp, reg_tmp);
+			} else {
+				/*===Tone 1===*/
+				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
+					       (table_addr & 0xff));
+				value = (BIT(3) | (wgt & 0x7));
+				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
+				reg_tmp = odm_read_4byte(dm, R_0x1d94);
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "New Mask tone 1 idx[%d]: Reg0x1d94 = ((0x%x))\n",
+					  tone_idx_tmp, reg_tmp);
+
+				/*===Tone 2===*/
+				value = 0;
+				multi_tone_idx_tmp = tone_idx_tmp - 1;
+				table_addr = multi_tone_idx_tmp >> 1;
+				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
+					       (table_addr & 0xff));
+				value = (BIT(3) | (wgt & 0x7)) << 4;
+				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
+				reg_tmp = odm_read_4byte(dm, R_0x1d94);
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "New Mask tone 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
+					  tone_idx_tmp, reg_tmp);
+			}
+		}
+	} else {
+		if ((dm->support_ic_type & (ODM_RTL8814B)) &&
+		    phydm_spur_case_mapping(dm)) {
+			if (!(tone_idx_tmp % 2)) {
+				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
+					       (table_addr & 0xff));
+				value = ((BIT(3) | (((wgt + 4) <= 7 ? (wgt +
+					 4) : 7) & 0x7)) << 4) | (BIT(3) |
+					 (wgt & 0x7));
+				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
+				reg_tmp = odm_read_4byte(dm, R_0x1d94);
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
+					  tone_idx_tmp, reg_tmp);
+				if (tone_idx_tmp == 0)
+					table_addr = tone_num - 1;
+				else
+					table_addr = table_addr - 1;
+				if (tone_idx_tmp != tone_num) {
+					odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
+						       (table_addr & 0xff));
+					value = (BIT(3) | (((wgt + 4) <= 7 ?
+						 (wgt + 4) : 7) & 0x7)) << 4;
+					odm_set_bb_reg(dm, R_0x1d94, 0xff,
+						       value);
+					reg_tmp = odm_read_4byte(dm, R_0x1d94);
+					PHYDM_DBG(dm, ODM_COMP_API,
+						  "New Mask Reg0x1d94 = ((0x%x))\n",
+						  reg_tmp);
+				}
+			} else {
+				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
+					       (table_addr & 0xff));
+				value = ((BIT(3) | (wgt & 0x7)) << 4) |
+					 (BIT(3) | (((wgt + 4) <= 7 ? (wgt +
+					  4) : 7) & 0x7));
+				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
+				reg_tmp = odm_read_4byte(dm, R_0x1d94);
+				PHYDM_DBG(dm, ODM_COMP_API,
+					  "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
+					  tone_idx_tmp, reg_tmp);
+				if (tone_idx_tmp == (tone_num << 1) - 1)
+					table_addr = 0;
+				else
+					table_addr = table_addr + 1;
+				if (tone_idx_tmp != tone_num - 1) {
+					odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
+						       (table_addr & 0xff));
+					value = (BIT(3) | (((wgt + 4) <= 7 ?
+						 (wgt + 4) : 7) & 0x7));
+					odm_set_bb_reg(dm, R_0x1d94, 0xff,
+						       value);
+					reg_tmp = odm_read_4byte(dm, R_0x1d94);
+					PHYDM_DBG(dm, ODM_COMP_API,
+						  "New Mask Reg0x1d94 = ((0x%x))\n",
+						  reg_tmp);
+				}
+			}
+		} else {
+			odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, (table_addr &
+				       0xff));
+			if (tone_idx_tmp % 2)
+				value = (BIT(3) | (wgt & 0x7)) << 4;
+			else
+				value = BIT(3) | (wgt & 0x7);
+
+			odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
+			reg_tmp = odm_read_4byte(dm, R_0x1d94);
+			PHYDM_DBG(dm, ODM_COMP_API,
+				  "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
+				  tone_idx_tmp, reg_tmp);
+		}
+	}
 	odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0);
 }

@@ -1324,15 +1718,18 @@ u8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
 				set_result = PHYDM_SET_SUCCESS;
 			} else {
 				set_result = PHYDM_SET_NO_NEED;
+			}
 		}
 	}
-	}

 	if (set_result == PHYDM_SET_SUCCESS)
 		phydm_nbi_enable_jgr3(dm, enable, path);
 	else
 		phydm_nbi_enable_jgr3(dm, FUNC_DISABLE, path);

+	if (dm->support_ic_type & ODM_RTL8814B)
+		odm_set_bb_reg(dm, R_0x1d3c, BIT(19), 0);
+
 	return set_result;
 }

@@ -1364,7 +1761,11 @@ void phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
 	#if RTL8814B_SUPPORT
 	if (dm->support_ic_type & ODM_RTL8814B) {
 		odm_set_bb_reg(dm, R_0xc24, 0xff, 0xff);
-		odm_set_bb_reg(dm, R_0xc24, 0xff00, tone_idx_tmp);
+		if ((*dm->channel == 5) &&
+		    (*dm->band_width == CHANNEL_WIDTH_40))
+			odm_set_bb_reg(dm, R_0xc24, 0xff00, 0x1a);
+		else
+			odm_set_bb_reg(dm, R_0xc24, 0xff00, tone_idx_tmp);
 	}
 	#endif
 	switch (path) {
@@ -1455,6 +1856,12 @@ void phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path)
 		#if (defined(PHYDM_COMPILE_ABOVE_4SS))
 		odm_set_bb_reg(dm, R_0x5140, BIT(31), val);
 		#endif
+		#if RTL8812F_SUPPORT
+		if (dm->support_ic_type & ODM_RTL8812F) {
+			odm_set_bb_reg(dm, R_0x818, BIT(3), val);
+			odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0x0);
+		}
+		#endif
 	}
 }

@@ -1699,10 +2106,8 @@ void phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used, char *output,
 	else
 		idx_lmt = 5;
 	for (i = 0; i < idx_lmt; i++) {
-		if (input[i + 1]) {
-			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
-			input_idx++;
-		}
+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
+		input_idx++;
 	}

 	if (input_idx == 0)
@@ -1791,10 +2196,8 @@ void phydm_csi_debug(void *dm_void, char input[][16], u32 *_used, char *output,
 		idx_lmt = 5;

 	for (i = 0; i < idx_lmt; i++) {
-		if (input[i + 1]) {
-			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
-			input_idx++;
-		}
+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
+		input_idx++;
 	}

 	if (input_idx == 0)
@@ -1990,6 +2393,7 @@ phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path,
 	u32 txagc_ofdm = 0;
 	u32 r_txagc_ofdm[4] = {R_0x18e8, R_0x41e8, R_0x52e8, R_0x53e8};
 	u32 r_txagc_cck[4] = {R_0x18a0, R_0x41a0, R_0x52a0, R_0x53a0};
+	u32 r_new_txagc[1] = {R_0x4308};

 	#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
 	if (dm->support_ic_type &
@@ -2084,6 +2488,43 @@ phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path,
 	}
 	#endif

+	#if (RTL8723F_SUPPORT)
+	if (dm->support_ic_type & (ODM_RTL8723F)) {
+		if (path > RF_PATH_A) {
+			PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n",
+				  path);
+			return false;
+		}
+		txagc_cck = (u8)odm_get_bb_reg(dm, r_new_txagc[path],
+					       0x0000007f);
+		txagc_ofdm = (u8)odm_get_bb_reg(dm, r_new_txagc[path],
+						0x00007f00);
+		if (is_positive) {
+			if (((txagc_cck + pwr_offset) > 127) ||
+			    ((txagc_ofdm + pwr_offset) > 127))
+				return false;
+
+			txagc_cck += pwr_offset;
+			txagc_ofdm += pwr_offset;
+		} else {
+			if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm)
+				return false;
+
+			txagc_cck -= pwr_offset;
+			txagc_ofdm -= pwr_offset;
+		}
+		#if (RTL8723F_SUPPORT)
+		ret = config_phydm_write_txagc_ref_8723f(dm, (u8)txagc_cck,
+							 path, PDM_CCK);
+		ret &= config_phydm_write_txagc_ref_8723f(dm, (u8)txagc_ofdm,
+							 path, PDM_OFDM);
+		#endif
+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
+			  "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n",
+			  __func__, path, txagc_cck, txagc_ofdm);
+	}
+	#endif
+
 	return ret;
 }

@@ -2094,7 +2535,7 @@ phydm_api_set_txagc(void *dm_void, u32 pwr_idx, enum rf_path path,
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	boolean ret = false;
 	#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT ||\
-	     RTL8814B_SUPPORT || RTL8197G_SUPPORT)
+	     RTL8814B_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
 	u8 base = 0;
 	u8 txagc_tmp = 0;
 	s8 pw_by_rate_tmp = 0;
@@ -2288,6 +2729,30 @@ phydm_api_set_txagc(void *dm_void, u32 pwr_idx, enum rf_path path,
 			  __func__, path, rate, base, pw_by_rate_new);
 	}
 #endif
+#if (RTL8723F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8723F) {
+		if (rate < 0x4)
+			txagc_tmp = config_phydm_read_txagc_8723f(dm, path,
+								  rate,
+								  PDM_CCK);
+		else
+			txagc_tmp = config_phydm_read_txagc_8723f(dm, path,
+								  rate,
+								  PDM_OFDM);
+
+		pw_by_rate_tmp = config_phydm_read_txagc_diff_8723f(dm, rate);
+		base = txagc_tmp - pw_by_rate_tmp;
+		base = base & 0x7f;
+		if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
+			return false;
+
+		pw_by_rate_new = (s8)(pwr_idx - base);
+		ret = phydm_write_txagc_1byte_8723f(dm, pw_by_rate_new, rate);
+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
+			  "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
+			  __func__, path, rate, base, pw_by_rate_new);
+	}
+#endif

 #if (RTL8197F_SUPPORT)
 	if (dm->support_ic_type & ODM_RTL8197F)
@@ -2365,6 +2830,18 @@ u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate)
 	}
 #endif

+#if (RTL8723F_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8723F) {
+		if (hw_rate < 0x4) {
+			ret = config_phydm_read_txagc_8723f(dm, path, hw_rate,
+							    PDM_CCK);
+		} else {
+			ret = config_phydm_read_txagc_8723f(dm, path, hw_rate,
+							    PDM_OFDM);
+		}
+	}
+#endif
+
 #if (RTL8814B_SUPPORT)
 	if (dm->support_ic_type & ODM_RTL8814B) {
 		if (hw_rate < 0x4) {
@@ -2414,6 +2891,55 @@ u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate)
 	return ret;
 }

+#if (RTL8822C_SUPPORT)
+void phydm_shift_rxagc_table(void *dm_void, boolean is_pos_shift, u8 sft)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u8 i = 0;
+	u8 j = 0;
+	u32 reg = 0;
+	u16 max_rf_gain = 0;
+	u16 min_rf_gain = 0;
+
+	dm->is_agc_tab_pos_shift = is_pos_shift;
+	dm->agc_table_shift = sft;
+
+	for (i = 0; i <= dm->agc_table_cnt; i++) {
+		max_rf_gain = dm->agc_rf_gain_ori[i][0];
+		min_rf_gain = dm->agc_rf_gain_ori[i][63];
+
+		if (dm->support_ic_type & ODM_RTL8822C)
+			dm->l_bnd_detect[i] = false;
+
+		for (j = 0; j < 64; j++) {
+			if (is_pos_shift) {
+				if (j < sft)
+					reg = (max_rf_gain & 0x3ff);
+				else
+					reg = (dm->agc_rf_gain_ori[i][j - sft] &
+						 0x3ff);
+			} else {
+				if (j > 63 - sft)
+					reg = (min_rf_gain & 0x3ff);
+
+				else
+					reg = (dm->agc_rf_gain_ori[i][j + sft] &
+						 0x3ff);
+			}
+			dm->agc_rf_gain[i][j] = (u16)(reg & 0x3ff);
+
+			reg |= (j & 0x3f) << 16;/*mp_gain_idx*/
+			reg |= (i & 0xf) << 22;/*table*/
+			reg |= BIT(29) | BIT(28);/*write en*/
+			odm_set_bb_reg(dm, R_0x1d90, MASKDWORD, reg);
+		}
+	}
+
+	if (dm->support_ic_type & ODM_RTL8822C)
+		odm_set_bb_reg(dm, R_0x828, 0xf8, L_BND_DEFAULT_8822C);
+}
+#endif
+
 boolean
 phydm_api_switch_bw_channel(void *dm_void, u8 ch, u8 pri_ch,
 			    enum channel_width bw)
@@ -2440,6 +2966,12 @@ phydm_api_switch_bw_channel(void *dm_void, u8 ch, u8 pri_ch,
 	break;
 #endif

+#if (RTL8195B_SUPPORT)
+	case ODM_RTL8195B:
+		ret = config_phydm_switch_channel_bw_8195b(dm, ch, pri_ch, bw);
+	break;
+#endif
+
 #if (RTL8192F_SUPPORT)
 	case ODM_RTL8192F:
 		ret = config_phydm_switch_channel_bw_8192f(dm, ch, pri_ch, bw);
@@ -2458,6 +2990,12 @@ phydm_api_switch_bw_channel(void *dm_void, u8 ch, u8 pri_ch,
 	break;
 #endif

+#if (RTL8723F_SUPPORT)
+	case ODM_RTL8723F:
+		ret = config_phydm_switch_channel_bw_8723f(dm, ch, pri_ch, bw);
+	break;
+#endif
+
 #if (RTL8814B_SUPPORT)
 	case ODM_RTL8814B:
 		ret = config_phydm_switch_channel_bw_8814b(dm, ch, pri_ch, bw);
@@ -2570,7 +3108,9 @@ phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path,
 	}
 	return ret;
 }
-#else
+#endif
+
+#ifdef PHYDM_COMMON_API_NOT_SUPPORT
 u8 config_phydm_read_txagc_n(void *dm_void, enum rf_path path, u8 hw_rate)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
@@ -2671,7 +3211,6 @@ u8 config_phydm_read_txagc_n(void *dm_void, enum rf_path path, u8 hw_rate)
 			reg_txagc = R_0xe14;
 			reg_mask = 0x7f000000;
 			break;
-
 		case ODM_RATEMCS8:
 			reg_txagc = R_0xe18;
 			reg_mask = 0x0000007f;
--- a/hal/phydm/phydm_api.h
+++ b/hal/phydm/phydm_api.h
@@ -26,8 +26,8 @@
 #ifndef __PHYDM_API_H__
 #define __PHYDM_API_H__

-/* 2019.03.05 add reset txagc API for jgr3 ics*/
-#define PHYDM_API_VERSION "2.1"
+/* 2019.10.22 Add get/shift rxagc API for 8822C*/
+#define PHYDM_API_VERSION "2.3"

 /* @1 ============================================================
 * 1  Definition
@@ -87,6 +87,7 @@ struct phydm_api_stuc {
 	u32 rxiqc_reg2; /*N-mode: for pathB REG0xc1c*/
 	u8 tx_queue_bitmap; /*REG0x520[23:16]*/
 	u8 ccktx_path;
+	u8 pri_ch_idx;
 };

 /* @1 ============================================================
@@ -98,6 +99,8 @@ struct phydm_api_stuc {
 * 1  function prototype
 * 1 ============================================================
 */
+enum channel_width phydm_rxsc_2_bw(void *dm_void, u8 rxsc);
+
 void phydm_reset_bb_hw_cnt(void *dm_void);

 void phydm_dynamic_ant_weighting(void *dm_void);
@@ -130,6 +133,10 @@ u8 phydm_stop_ic_trx(void *dm_void, u8 set_type);

 void phydm_dis_cck_trx(void *dm_void, u8 set_type);

+void phydm_bw_fixed_enable(void *dm_void, u8 enable);
+
+void phydm_bw_fixed_setting(void *dm_void);
+
 void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch);

 void phydm_nbi_enable(void *dm_void, u32 enable);
@@ -150,7 +157,13 @@ void phydm_stop_ck320(void *dm_void, u8 enable);

 boolean
 phydm_set_bb_txagc_offset(void *dm_void, s8 power_offset, u8 add_half_db);
+
+boolean phydm_spur_case_mapping(void *dm_void);
+
+enum odm_rf_band phydm_ch_to_rf_band(void *dm_void, u8 central_ch);
 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+u32 phydm_rf_psd_jgr3(void *dm_void, u8 path, u32 tone_idx);
+
 u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw,
 			       u32 f_intf, u32 sec_ch, u8 wgt);

@@ -183,6 +196,10 @@ phydm_api_set_txagc(void *dm_void, u32 power_index, enum rf_path path,

 u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate);

+#if (RTL8822C_SUPPORT)
+void phydm_shift_rxagc_table(void *dm_void, boolean shift_up, u8 shift);
+#endif
+
 boolean
 phydm_api_switch_bw_channel(void *dm_void, u8 central_ch, u8 primary_ch_idx,
 			    enum channel_width bandwidth);
@@ -193,6 +210,10 @@ phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path,

 #endif

+#ifdef PHYDM_COMMON_API_NOT_SUPPORT
+u8 config_phydm_read_txagc_n(void *dm_void, enum rf_path path, u8 hw_rate);
+#endif
+
 #ifdef CONFIG_MCC_DM
 #ifdef DYN_ANT_WEIGHTING_SUPPORT
 void phydm_dynamic_ant_weighting_mcc_8822b(void *dm_void);
--- a/hal/phydm/phydm_beamforming.c
+++ b/hal/phydm/phydm_beamforming.c
@@ -48,6 +48,9 @@ void phydm_get_txbf_device_num(
 	u8 act_as_bfer = 0;
 	u8 act_as_bfee = 0;

+	if (!(dm->support_ability & ODM_BB_ANT_DIV))
+		return;
+
 	if (is_sta_active(sta)) {
 		bf = &(sta->bf_info);
 	} else {
@@ -71,7 +74,7 @@ void phydm_get_txbf_device_num(
 			act_as_bfee = 1;
 	}

-	if (act_as_bfer))
+	if (act_as_bfer)
 		{ /* Our Device act as BFer */
 			dm_bdc_table->w_bfee_client[macid] = true;
 			dm_bdc_table->num_txbfee_client++;
@@ -79,7 +82,7 @@ void phydm_get_txbf_device_num(
 	else
 		dm_bdc_table->w_bfee_client[macid] = false;

-	if (act_as_bfee))
+	if (act_as_bfee)
 		{ /* Our Device act as BFee */
 			dm_bdc_table->w_bfer_client[macid] = true;
 			dm_bdc_table->num_txbfer_client++;
@@ -460,41 +463,6 @@ beamforming_add_bfer_entry(
 		return NULL;
 }

-#if 0
-boolean
-beamforming_remove_entry(
-	void			*adapter,
-	u8		*RA,
-	u8		*idx
-)
-{
-	HAL_DATA_TYPE			*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-	struct dm_struct				*dm = &hal_data->DM_OutSrc;
-
-	struct _RT_BEAMFORMER_ENTRY	*bfer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, RA, idx);
-	struct _RT_BEAMFORMEE_ENTRY	*entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, idx);
-	boolean ret = false;
-
-	RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s Start!\n", __func__));
-	RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, bfer_entry=0x%x\n", __func__, bfer_entry));
-	RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, entry=0x%x\n", __func__, entry));
-
-	if (entry != NULL) {
-		entry->is_used = false;
-		entry->beamform_entry_cap = BEAMFORMING_CAP_NONE;
-		/*@entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;*/
-		entry->is_beamforming_in_progress = false;
-		ret = true;
-	}
-	if (bfer_entry != NULL) {
-		bfer_entry->is_used = false;
-		bfer_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE;
-		ret = true;
-	}
-	return ret;
-}
-#endif
-
 /* Used for beamforming_start_v1 */
 void phydm_beamforming_ndpa_rate(
 	void *dm_void,
@@ -1807,35 +1775,6 @@ void beamforming_leave(
 	PHYDM_DBG(dm, DBG_TXBF, "[%s] End!!\n", __func__);
 }

-#if 0
-/* Nobody calls this function */
-void
-phydm_beamforming_set_txbf_en(
-	void		*dm_void,
-	u8			mac_id,
-	boolean			is_txbf
-)
-{
-	struct dm_struct				*dm = (struct dm_struct *)dm_void;
-	u8					idx = 0;
-	struct _RT_BEAMFORMEE_ENTRY	*entry;
-
-	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
-
-	entry = phydm_beamforming_get_entry_by_mac_id(dm, mac_id, &idx);
-
-	if (entry == NULL)
-		return;
-	else
-		entry->is_txbf = is_txbf;
-
-	PHYDM_DBG(dm, DBG_TXBF, "%s mac_id %d TxBF %d\n", __func__,
-		  entry->mac_id, entry->is_txbf);
-
-	phydm_beamforming_notify(dm);
-}
-#endif
-
 enum beamforming_cap
 phydm_beamforming_get_beam_cap(
 	void *dm_void,
--- a/hal/phydm/phydm_beamforming.h
+++ b/hal/phydm/phydm_beamforming.h
@@ -45,7 +45,7 @@

 #define MAX_BEAMFORMEE_SU 2
 #define MAX_BEAMFORMER_SU 2
-#if (RTL8822B_SUPPORT == 1)
+#if ((RTL8822B_SUPPORT == 1) || (RTL8812F_SUPPORT == 1))
 #define MAX_BEAMFORMEE_MU 6
 #define MAX_BEAMFORMER_MU 1
 #else
--- a/hal/phydm/phydm_cck_pd.c
+++ b/hal/phydm/phydm_cck_pd.c
--- a/hal/phydm/phydm_cck_pd.h
+++ b/hal/phydm/phydm_cck_pd.h
@@ -26,7 +26,8 @@
 #ifndef __PHYDM_CCK_PD_H__
 #define __PHYDM_CCK_PD_H__

-#define CCK_PD_VERSION "3.3" /* @ modify invalid type4 API*/
+/* 2019.12.25 decrease CS_ratio in 8822C due to Lenovo test result(PCIE-5136).*/
+#define CCK_PD_VERSION "4.0"

 /*@
 * 1 ============================================================
@@ -35,10 +36,9 @@
 */
 #define CCK_FA_MA_RESET 0xffffffff

-#define INVALID_CS_RATIO_0 27 /* @ only for type4 ICs*/
-#define INVALID_CS_RATIO_1 29 /* @ only for type4 ICs*/
-#define MAXVALID_CS_RATIO 31
-#define MAXVALID_PD_THRES 255
+#define INVALID_CS_RATIO_0 0x1b /* @ only for type4 ICs*/
+#define INVALID_CS_RATIO_1 0x1d /* @ only for type4 ICs*/
+#define MAXVALID_CS_RATIO 0x1f
 /*@Run time flag of CCK_PD HW type*/
 #define CCK_PD_IC_TYPE1 (ODM_RTL8188E | ODM_RTL8812 | ODM_RTL8821 |\
 			ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8814A |\
@@ -52,6 +52,7 @@
 /*@extend for different bw & path*/

 #define CCK_PD_IC_TYPE4 ODM_IC_JGR3_SERIES /*@extend for different bw & path*/
+#define CCK_PD_IC_TYPE5 (ODM_RTL8723F) /*@extend for different CR*/

 /*@Compile time flag of CCK_PD HW type*/
 #if (RTL8188E_SUPPORT || RTL8812A_SUPPORT || RTL8821A_SUPPORT ||\
@@ -73,6 +74,10 @@
 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
 	#define PHYDM_COMPILE_CCKPD_TYPE4 /*@extend for different bw & path*/
 #endif
+#if (RTL8723F_SUPPORT)
+	#define PHYDM_COMPILE_CCKPD_TYPE5 /*@extend for different & path*/
+#endif
+
 /*@
 * 1 ============================================================
 * 1  enumeration
@@ -99,6 +104,17 @@ enum cckpd_mode {
 	CCK_BW40_4R = 7
 };

+enum dcc_mode {
+	DCC_DIG		= 0,
+	DCC_CCK_PD	= 1
+};
+
+enum phydm_cck_pd_trend {
+	CCKPD_STABLE			= 0,
+	CCKPD_INCREASING		= 1,
+	CCKPD_DECREASING		= 2
+};
+
 /*@
 * 1 ============================================================
 * 1  structure
@@ -106,6 +122,16 @@ enum cckpd_mode {
 */

 #ifdef PHYDM_SUPPORT_CCKPD
+
+#ifdef PHYDM_DCC_ENHANCE
+struct phydm_dcc_struct { /*DIG CCK_PD coexistence*/
+	boolean		dcc_en;
+	enum dcc_mode	dcc_mode;
+	u32		dig_execute_cnt;
+	u8		dcc_ratio;
+};
+#endif
+
 struct phydm_cckpd_struct {
 	u8		cckpd_hw_type;
 	u8		cur_cck_cca_thres; /*@current cck_pd value 0xa0a*/
@@ -113,6 +139,7 @@ struct phydm_cckpd_struct {
 	u32		rvrt_val; /*all rvrt_val for pause API must set to u32*/
 	u8		pause_lv;
 	u8		cck_n_rx;
+	u16		cck_fa_th[2];
 	enum channel_width cck_bw;
 	enum cckpd_lv	cck_pd_lv;
 	#ifdef PHYDM_COMPILE_CCKPD_TYPE2
@@ -129,6 +156,7 @@ struct phydm_cckpd_struct {
 	u8		cck_cs_ratio_20m_2r;
 	u8		cck_cs_ratio_40m_1r;
 	u8		cck_cs_ratio_40m_2r;
+    u8		cck_din_shift_opt;
 	/*Current value*/
 	u8		cur_cck_pd_20m_1r;
 	u8		cur_cck_pd_20m_2r;
@@ -141,6 +169,10 @@ struct phydm_cckpd_struct {
 	#endif
 	#ifdef PHYDM_COMPILE_CCKPD_TYPE4
 	/*@[bw][nrx][0:PD/1:CS][lv]*/
+	u8		cckpd_jgr3[2][4][2][CCK_PD_LV_MAX];
+	#endif
+	#ifdef PHYDM_COMPILE_CCKPD_TYPE5
+	/*@[bw][nrx][0:PD/1:CS][lv]*/
 	u8		cck_pd_table_jgr3[2][4][2][CCK_PD_LV_MAX];
 	#endif
 };
@@ -156,4 +188,15 @@ void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len);
 void phydm_cck_pd_th(void *dm_void);

 void phydm_cck_pd_init(void *dm_void);
+
+#ifdef PHYDM_DCC_ENHANCE
+void phydm_cckpd_type4_dcc(void *dm_void);
+
+void phydm_dig_cckpd_coex(void *dm_void);
+
+void phydm_dig_cckpd_coex_init(void *dm_void);
+
+void phydm_dig_cckpd_coex_dbg(void *dm_void, char input[][16], u32 *_used,
+			      char *output, u32 *_out_len);
+#endif
 #endif
--- a/hal/phydm/phydm_cck_rx_pathdiv.c
+++ b/hal/phydm/phydm_cck_rx_pathdiv.c
@@ -131,8 +131,7 @@ void phydm_cck_rx_pathdiv_dbg(void *dm_void, char input[][16], u32 *_used,
 		return;

 	for (i = 0; i < 3; i++) {
-		if (input[i + 1])
-			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
 	}

 	if ((strcmp(input[1], help) == 0)) {
--- a/hal/phydm/phydm_ccx.c
+++ b/hal/phydm/phydm_ccx.c
--- a/hal/phydm/phydm_ccx.h
+++ b/hal/phydm/phydm_ccx.h
@@ -26,8 +26,8 @@
 #ifndef __PHYDMCCX_H__
 #define __PHYDMCCX_H__

-/* 2019.03.27 add noise_pwr in env_mntr_rpt.*/
-#define CCX_VERSION "2.4"
+/* 2020.08.12 split env_mntr api into set_env_mntr and result_env_mntr api for dig_fa_source*/
+#define CCX_VERSION "4.7"

 /* @1 ============================================================
 * 1  Definition
@@ -36,39 +36,38 @@
 #define CCX_EN 1

 #define	MAX_ENV_MNTR_TIME	8	/*second*/
-#define	IGI_TO_NHM_TH_MULTIPLIER 2
+#define	MS_TO_US		1000
 #define	MS_TO_4US_RATIO		250
 #define	CCA_CAP			14
+/*CLM*/
 #define	CLM_MAX_REPORT_TIME	10
-#define	DEVIDER_ERROR		0xffff
-#define CLM_PERIOD_MAX		65535
-#define NHM_PERIOD_MAX		65534
+#define	CLM_PERIOD_MAX		65535
+/*NHM*/
+#define	NHM_PERIOD_MAX		65534
 #define	NHM_TH_NUM		11	/*threshold number of NHM*/
 #define	NHM_RPT_NUM		12
+#define NHM_IC_NOISE_TH		60	/*60/2 - 10 = 20 = -80 dBm*/
+#define NHM_RPT_MAX		255
 #ifdef NHM_DYM_PW_TH_SUPPORT
 #define	DYM_PWTH_CCA_CAP	24
-#define NHM_1PEAK_PS		1	/* @case1 : positive skew*/
-#define NHM_1PEAK_NS		2	/* @case2 : negative skew*/
-#define NHM_1PEAK_SYM		3	/* @case3 : symmetry*/
-#define NHM_TH1			33	/* @13%, for step2 decision*/
-#define NHM_TH2			35	/* @14%, for step3_c1_c2 decision*/
-#define NHM_TH3			31	/* @12%, for step3_c3 decision*/
-#define NHM_TH4			178	/* @70%, for step4 decision*/
-#define NHM_TH5			25	/* @10%, for step5_c1_c2 decision*/
-#define NHM_TH6			39	/* @15%, for step5_c3 decision*/
 #endif
-
-#define	IGI_2_NHM_TH(igi)	((igi) << 1)/*NHM_threshold = IGI * 2*/
+#define	IGI_2_NHM_TH(igi)	((igi) << 1)/*NHM/FAHM threshold = IGI * 2*/
 #define	NTH_TH_2_RSSI(th)	((th >> 1) - 10)
-
-/*@FAHM*/
-#define	FAHM_INCLD_FA		BIT(0)
-#define	FAHM_INCLD_CRC_OK	BIT(1)
-#define	FAHM_INCLD_CRC_ER	BIT(2)
+/*FAHM*/
+#define	FAHM_INCLU_FA		BIT(0)
+#define	FAHM_INCLU_CRC_OK	BIT(1)
+#define	FAHM_INCLU_CRC_ERR	BIT(2)
+#define	FAHM_PERIOD_MAX		65534
+#define	FAHM_TH_NUM		11	/*threshold number of FAHM*/
+#define	FAHM_RPT_NUM		12
+/*IFS-CLM*/
+#define	IFS_CLM_PERIOD_MAX	65535
+#define	IFS_CLM_NUM		4

 #define NHM_SUCCESS		BIT(0)
 #define CLM_SUCCESS		BIT(1)
 #define FAHM_SUCCESS		BIT(2)
+#define IFS_CLM_SUCCESS		BIT(3)
 #define	ENV_MNTR_FAIL		0xff

 /* @1 ============================================================
@@ -93,6 +92,24 @@ enum phydm_nhm_level {
 	NHM_MAX_NUM		= 5
 };

+enum phydm_fahm_level {
+	FAHM_RELEASE		= 0,
+	FAHM_LV_1		= 1,	/* Low Priority function */
+	FAHM_LV_2		= 2,	/* Middle Priority function */
+	FAHM_LV_3		= 3,	/* High priority function (ex: Check hang function) */
+	FAHM_LV_4		= 4,	/* Debug function (the highest priority) */
+	FAHM_MAX_NUM		= 5
+};
+
+enum phydm_ifs_clm_level {
+	IFS_CLM_RELEASE		= 0,
+	IFS_CLM_LV_1		= 1,	/* @Low Priority function */
+	IFS_CLM_LV_2		= 2,	/* @Middle Priority function */
+	IFS_CLM_LV_3		= 3,	/* @High priority function (ex: Check hang function) */
+	IFS_CLM_LV_4		= 4,	/* @Debug function (the highest priority) */
+	IFS_CLM_MAX_NUM		= 5
+};
+
 enum nhm_divider_opt_all {
 	NHM_CNT_ALL		= 0,	/*nhm SUM report <= 255*/
 	NHM_VALID		= 1,	/*nhm SUM report = 255*/
@@ -131,11 +148,32 @@ enum clm_application {
 	CLM_ACS			= 1,
 };

+enum fahm_application {
+	FAHM_BACKGROUND		= 0,/*default*/
+	FAHM_ACS		= 1,
+	FAHM_DBG		= 2, /*manual trigger*/
+};
+
+enum ifs_clm_application {
+	IFS_CLM_BACKGROUND		= 0,/*default*/
+	IFS_CLM_ACS			= 1,
+	IFS_CLM_HP_TAS			= 2,
+	IFS_CLM_DBG			= 3,
+};
+
 enum clm_monitor_mode {
 	CLM_DRIVER_MNTR		= 1,
 	CLM_FW_MNTR		= 2
 };

+enum phydm_ifs_clm_unit {
+	IFS_CLM_4		= 0,	/*4us*/
+	IFS_CLM_8		= 1,	/*8us*/
+	IFS_CLM_12		= 2,	/*12us*/
+	IFS_CLM_16		= 3,	/*16us*/
+	IFS_CLM_INIT
+};
+
 /* @1 ============================================================
 * 1  structure
 * 1 ============================================================
@@ -145,14 +183,46 @@ struct env_trig_rpt {
 	u8			clm_rpt_stamp;
 };

-
 struct env_mntr_rpt {
 	u8			nhm_ratio;
+	u8			nhm_env_ratio; /*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/
 	u8			nhm_result[NHM_RPT_NUM];
 	u8			clm_ratio;
 	u8			nhm_rpt_stamp;
 	u8			clm_rpt_stamp;
-	u8			nhm_noise_pwr;
+	u8			nhm_noise_pwr; /*including r[0]~r[10]*/
+	u8			nhm_pwr; /*including r[0]~r[11]*/
+};
+
+struct enhance_mntr_trig_rpt {
+	u8			nhm_rpt_stamp;
+	u8			clm_rpt_stamp;
+	u8			fahm_rpt_stamp;
+	u8			ifs_clm_rpt_stamp;
+};
+
+struct enhance_mntr_rpt {
+	u8			nhm_ratio;
+	u8			nhm_env_ratio; /*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/
+	u8			nhm_result[NHM_RPT_NUM];
+	u8			clm_ratio;
+	u8			nhm_rpt_stamp;
+	u8			clm_rpt_stamp;
+	u8			nhm_noise_pwr; /*including r[0]~r[10]*/
+	u8			nhm_pwr; /*including r[0]~r[11]*/
+	u16			fahm_result[NHM_RPT_NUM];
+	u8			fahm_rpt_stamp;
+	u8			fahm_pwr;
+	u8			fahm_ratio;
+	u8			fahm_denom_ratio;
+	u8			fahm_inclu_cck;
+	u8			ifs_clm_rpt_stamp;
+	u8			ifs_clm_tx_ratio;
+	u8			ifs_clm_edcca_excl_cca_ratio;
+	u8			ifs_clm_cck_fa_ratio;
+	u8			ifs_clm_cck_cca_excl_fa_ratio;
+	u8			ifs_clm_ofdm_fa_ratio;
+	u8			ifs_clm_ofdm_cca_excl_fa_ratio;
 };

 struct nhm_para_info {
@@ -162,6 +232,8 @@ struct nhm_para_info {
 	enum nhm_application		nhm_app;
 	enum phydm_nhm_level		nhm_lv;
 	u16				mntr_time;	/*@0~262 unit ms*/
+	boolean				en_1db_mode;
+	u8				nhm_th0_manual;	/* for 1-db mode*/
 };

 struct clm_para_info {
@@ -170,10 +242,34 @@ struct clm_para_info {
 	u16				mntr_time;	/*@0~262 unit ms*/
 };

+struct fahm_para_info {
+	enum fahm_application		app;
+	enum phydm_fahm_level		lv;
+	u16				mntr_time;	/*0~262 unit ms*/
+	u8				numer_opt;
+	u8				denom_opt;
+	boolean				en_1db_mode;
+	u8				th0_manual;/* for 1-db mode*/
+};
+
+struct ifs_clm_para_info {
+	enum ifs_clm_application	ifs_clm_app;
+	enum phydm_ifs_clm_level	ifs_clm_lv;
+	enum phydm_ifs_clm_unit		ifs_clm_ctrl_unit;	/*unit*/
+	u16				mntr_time;	/*ms*/
+	boolean				ifs_clm_th_en[IFS_CLM_NUM];
+	u16				ifs_clm_th_low[IFS_CLM_NUM];
+	u16				ifs_clm_th_high[IFS_CLM_NUM];
+	s16				th_shift;
+};
+
 struct ccx_info {
 	u32			nhm_trigger_time;
 	u32			clm_trigger_time;
+	u32			fahm_trigger_time;
+	u32			ifs_clm_trigger_time;
 	u64			start_time;	/*@monitor for the test duration*/
+	u8			ccx_watchdog_result;
 #ifdef NHM_SUPPORT
 	enum nhm_application		nhm_app;
 	enum nhm_option_txon_all	nhm_include_txon;
@@ -182,22 +278,24 @@ struct ccx_info {
 	/*Report*/
 	u8			nhm_th[NHM_TH_NUM];
 	u8			nhm_result[NHM_RPT_NUM];
+	u8			nhm_wgt[NHM_RPT_NUM];
 	u16			nhm_period;	/* @4us per unit */
 	u8			nhm_igi;
 	u8			nhm_manual_ctrl;
 	u8			nhm_ratio;	/*@1% per nuit, it means the interference igi can't overcome.*/
+	u8			nhm_env_ratio; /*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/
 	u8			nhm_rpt_sum;
-	u16			nhm_duration;	/*@Real time of NHM_VALID */
 	u8			nhm_set_lv;
 	boolean			nhm_ongoing;
 	u8			nhm_rpt_stamp;
-	u8			nhm_noise_pwr;
-	u8			nhm_noise_pwr_point;
+	u8			nhm_level; /*including r[0]~r[10]*/
+	u8			nhm_level_valid;
+	u8			nhm_pwr; /*including r[0]~r[11]*/
 #ifdef NHM_DYM_PW_TH_SUPPORT
 	boolean			nhm_dym_pw_th_en;
-	boolean			nhm_dym_1_peak_en;
 	boolean			dym_pwth_manual_ctrl;
-	u8			nhm_pw_th_rf20_dft;
+	u8			pw_th_rf20_ori;
+	u8			pw_th_rf20_cur;
 	u8			nhm_pw_th_max;
 	u8			nhm_period_decre;
 	u8			nhm_sl_pw_th;
@@ -218,11 +316,54 @@ struct ccx_info {
 	u8			clm_rpt_stamp;
 #endif
 #ifdef FAHM_SUPPORT
+	enum fahm_application	fahm_app;
 	boolean			fahm_ongoing;
-	u8			env_mntr_igi;
-	u8			fahm_nume_sel;	/*@fahm_numerator_sel: select {FA, CRCOK, CRC_fail} */
-	u8			fahm_denom_sel;	/*@fahm_denominator_sel: select {FA, CRCOK, CRC_fail} */
+	u8			fahm_numer_opt;
+	u8			fahm_denom_opt;
+	boolean			fahm_inclu_cck;
+	u8			fahm_th[NHM_TH_NUM];
+	u16			fahm_result[NHM_RPT_NUM];
+	u16			fahm_result_sum;
+	u16			fahm_denom_result;
 	u16			fahm_period;	/*unit: 4us*/
+	u8			fahm_igi;
+	u8			fahm_manual_ctrl;
+	u8			fahm_set_lv;
+	u8			fahm_rpt_stamp;
+	u8			fahm_pwr; /*including r[0]~r[11]*/
+	u8			fahm_ratio;
+	u8			fahm_denom_ratio;
+#endif
+#ifdef IFS_CLM_SUPPORT
+	enum ifs_clm_application	ifs_clm_app;
+	/*Control*/
+	enum phydm_ifs_clm_unit ifs_clm_ctrl_unit; /*4,8,12,16us per unit*/
+	u16			ifs_clm_period;
+	boolean			ifs_clm_th_en[IFS_CLM_NUM];
+	u16			ifs_clm_th_low[IFS_CLM_NUM];
+	u16			ifs_clm_th_high[IFS_CLM_NUM];
+	/*Flow control*/
+	u8			ifs_clm_set_lv;
+	u8			ifs_clm_manual_ctrl;
+	boolean			ifs_clm_ongoing;
+	/*Report*/
+	u8			ifs_clm_rpt_stamp;
+	u16			ifs_clm_tx;
+	u16			ifs_clm_edcca_excl_cca;
+	u16			ifs_clm_ofdmfa;
+	u16			ifs_clm_ofdmcca_excl_fa;
+	u16			ifs_clm_cckfa;
+	u16			ifs_clm_cckcca_excl_fa;
+	u8			ifs_clm_his[IFS_CLM_NUM];	/*trx_neg_edge to CCA/FA posedge per times*/
+	u16			ifs_clm_total_cca;
+	u16			ifs_clm_avg[IFS_CLM_NUM];	/*4,8,12,16us per unit*/
+	u16			ifs_clm_avg_cca[IFS_CLM_NUM];	/*4,8,12,16us per unit*/
+	u8			ifs_clm_tx_ratio;
+	u8			ifs_clm_edcca_excl_cca_ratio;
+	u8			ifs_clm_cck_fa_ratio;
+	u8			ifs_clm_cck_cca_excl_fa_ratio;
+	u8			ifs_clm_ofdm_fa_ratio;
+	u8			ifs_clm_ofdm_cca_excl_fa_ratio;
 #endif
 };

@@ -231,6 +372,8 @@ struct ccx_info {
 * 1 ============================================================
 */

+u8 phydm_env_mntr_get_802_11_k_rsni(void *dm_void, s8 rcpi, s8 anpi);
+
 #ifdef FAHM_SUPPORT
 void phydm_fahm_init(void *dm_void);

@@ -238,14 +381,12 @@ void phydm_fahm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
 		    u32 *_out_len);
 #endif

-/*@NHM*/
 #ifdef NHM_SUPPORT
 void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
 		   u32 *_out_len);
 u8 phydm_get_igi(void *dm_void, enum bb_path path);
 #endif

-/*@CLM*/
 #ifdef CLM_SUPPORT
 void phydm_clm_c2h_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);

@@ -259,10 +400,30 @@ u8 phydm_env_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para,

 u8 phydm_env_mntr_result(void *dm_void, struct env_mntr_rpt *rpt);

-void phydm_env_mntr_watchdog(void *dm_void);
+void phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used,
+			char *output, u32 *_out_len);
+
+#ifdef IFS_CLM_SUPPORT
+void phydm_ifs_clm_dbg(void *dm_void, char input[][16], u32 *_used,
+		       char *output, u32 *_out_len);
+#endif
+
+u8 phydm_enhance_mntr_trigger(void *dm_void,
+			      struct nhm_para_info *nhm_para,
+			      struct clm_para_info *clm_para,
+			      struct fahm_para_info *fahm_para,
+			      struct ifs_clm_para_info *ifs_clm_para,
+			      struct enhance_mntr_trig_rpt *trig_rpt);
+
+u8 phydm_enhance_mntr_result(void *dm_void, struct enhance_mntr_rpt *rpt);
+
+void phydm_enhance_mntr_dbg(void *dm_void, char input[][16], u32 *_used,
+			char *output, u32 *_out_len);
+
+void phydm_env_mntr_result_watchdog(void *dm_void);
+
+void phydm_env_mntr_set_watchdog(void *dm_void);

 void phydm_env_monitor_init(void *dm_void);

-void phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used,
-			char *output, u32 *_out_len);
 #endif
--- a/hal/phydm/phydm_cfotracking.c
+++ b/hal/phydm/phydm_cfotracking.c
@@ -211,7 +211,7 @@ phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap)
 	u32 reg_val = 0;

 	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |
-	    ODM_RTL8195B | ODM_RTL8812F | ODM_RTL8721D | ODM_RTL8710C)) {
+	    ODM_RTL8195B | ODM_RTL8812F | ODM_RTL8721D | ODM_RTL8710C|ODM_RTL8723F)) {
 		crystal_cap &= 0x7F;
 		reg_val = crystal_cap | (crystal_cap << 7);
 	} else {
@@ -249,9 +249,9 @@ phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap)
 	}
 	#endif
 	#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8197F_SUPPORT ||\
-	     RTL8192F_SUPPORT || RTL8197G_SUPPORT)
+	     RTL8192F_SUPPORT || RTL8197G_SUPPORT || RTL8198F_SUPPORT)
 	else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C |
-		 ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8197G)) {
+		 ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8197G | ODM_RTL8198F)) {
 		/* write 0x24[30:25] = 0x28[6:1] = crystal_cap */
 		odm_set_mac_reg(dm, R_0x24, 0x7e000000, crystal_cap);
 		odm_set_mac_reg(dm, R_0x28, 0x7e, crystal_cap);
@@ -289,7 +289,12 @@ phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap)
 		phydm_set_crystalcap(dm, (u8)(reg_val & 0x7f));
 	}
 	#endif
-
+	#if (RTL8723F_SUPPORT)
+	else if (dm->support_ic_type & ODM_RTL8723F) {
+		/* write 0x103c[23:17] = 0x103c[16:10] = crystal_cap */
+		odm_set_mac_reg(dm, R_0x103c, 0x00FFFC00, reg_val);
+	}
+	#endif
 #if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)
 	else if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |
 		 ODM_RTL8812F)) {
@@ -325,7 +330,7 @@ void phydm_cfo_tracking_reset(void *dm_void)
 	PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__);

 	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8195B |
-	    ODM_RTL8812F))
+	    ODM_RTL8812F | ODM_RTL8710C | ODM_RTL8721D | ODM_RTL8723F))
 		cfo_track->def_x_cap = cfo_track->crystal_cap_default & 0x7f;
 	else
 		cfo_track->def_x_cap = cfo_track->crystal_cap_default & 0x3f;
@@ -349,6 +354,14 @@ void phydm_cfo_tracking_reset(void *dm_void)
 		phydm_set_atc_status(dm, true);
 #endif
 #endif
+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_AP))
+	if (dm->support_ic_type & ODM_RTL8814B) {
+		/*Disable advance time for CFO residual*/
+		odm_set_bb_reg(dm, R_0xc2c, BIT29, 0x0);
+	}
+#endif
+#endif
 }

 void phydm_cfo_tracking_init(void *dm_void)
@@ -358,7 +371,7 @@ void phydm_cfo_tracking_init(void *dm_void)

 	PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]=========>\n", __func__);
 	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8195B |
-	    ODM_RTL8812F))
+	    ODM_RTL8812F | ODM_RTL8710C | ODM_RTL8721D | ODM_RTL8723F))
 		cfo_track->crystal_cap = cfo_track->crystal_cap_default & 0x7f;
 	else
 		cfo_track->crystal_cap = cfo_track->crystal_cap_default & 0x3f;
@@ -473,7 +486,7 @@ void phydm_cfo_tracking(void *dm_void)
 				crystal_cap -= 1;

 			if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |
-			    ODM_RTL8195B | ODM_RTL8812F)) {
+			    ODM_RTL8195B | ODM_RTL8812F | ODM_RTL8710C | ODM_RTL8721D | ODM_RTL8723F)) {
 				if (crystal_cap > 0x7F)
 					crystal_cap = 0x7F;
 			} else {
@@ -501,6 +514,14 @@ void phydm_cfo_tracking(void *dm_void)
 		}
 		#endif
 		#endif
+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_AP))
+		if (dm->support_ic_type & ODM_RTL8814B) {
+			//Disable advance time for CFO residual
+			odm_set_bb_reg(dm, R_0xc2c, BIT29, 0x0);
+		}
+		#endif
+		#endif
 	}
 }

--- a/hal/phydm/phydm_debug.c
+++ b/hal/phydm/phydm_debug.c
--- a/hal/phydm/phydm_debug.h
+++ b/hal/phydm/phydm_debug.h
@@ -31,8 +31,8 @@
 /*#define DEBUG_VERSION	"1.3"*/ /*2016.04.28 YuChen*/
 /*#define DEBUG_VERSION	"1.4"*/ /*2017.03.13 Dino*/
 /*#define DEBUG_VERSION "2.0"*/ /*2018.01.10 Dino*/
-/* 2019.03.25 fix nhm_r[11] debug msg error*/
-#define DEBUG_VERSION "2.6"
+/*2020.07.03 fix cck report bug due to 8723F coding error*/
+#define DEBUG_VERSION "4.6"

 /*@
 * ============================================================
--- a/hal/phydm/phydm_dfs.c
+++ b/hal/phydm/phydm_dfs.c
@@ -73,7 +73,7 @@ void phydm_radar_detect_reset(void *dm_void)
 	struct dm_struct *dm = (struct dm_struct *)dm_void;

 	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
-				   ODM_RTL8197G)) {
+				   ODM_RTL8197G | ODM_RTL8723F)) {
 		odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
 		odm_set_bb_reg(dm, R_0xa40, BIT(15), 1);
 	#if (RTL8721D_SUPPORT)
@@ -100,7 +100,7 @@ void phydm_radar_detect_disable(void *dm_void)
 	struct dm_struct *dm = (struct dm_struct *)dm_void;

 	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
-				   ODM_RTL8197G))
+				   ODM_RTL8197G | ODM_RTL8723F))
 		odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
 	else if (dm->support_ic_type & (ODM_RTL8814B)) {
 		if (dm->seg1_dfs_flag == 1) {
@@ -635,7 +635,7 @@ void phydm_dfs_parameter_init(void *dm_void)

 	/*@for dynamic dfs*/
 	dfs->pwdb_th = 8;
-	dfs->fa_mask_th = 30 * (dfs->dfs_polling_time / 100);
+	dfs->fa_mask_th = 30 * (dfs->dfs_polling_time) / 100;
 	dfs->st_l2h_min = 0x20;
 	dfs->st_l2h_max = 0x4e;
 	dfs->pwdb_scalar_factor = 12;
@@ -829,21 +829,18 @@ phydm_radar_detect_dm_check(
 	struct _DFS_STATISTICS *dfs = &dm->dfs;
 	u8 region_domain = dm->dfs_region_domain, index = 0;

-	u16 i = 0, j = 0, k = 0, fa_count_cur = 0, fa_count_inc = 0;
-	u16 total_fa_in_hist = 0, pre_post_now_acc_fa_in_hist = 0;
-	u16 max_fa_in_hist = 0, vht_crc_ok_cnt_cur = 0;
-	u16 vht_crc_ok_cnt_inc = 0, ht_crc_ok_cnt_cur = 0;
-	u16 ht_crc_ok_cnt_inc = 0, leg_crc_ok_cnt_cur = 0;
-	u16 leg_crc_ok_cnt_inc = 0;
-	u16 total_crc_ok_cnt_inc = 0, short_pulse_cnt_cur = 0;
-	u16 short_pulse_cnt_inc = 0, long_pulse_cnt_cur = 0;
-	u16 long_pulse_cnt_inc = 0, total_pulse_count_inc = 0;
+	u16 i = 0, j = 0, fa_count_cur = 0, fa_count_inc = 0;
+	u16 total_fa_in_hist = 0, total_pulse_count_inc = 0;
+	u16 short_pulse_cnt_inc = 0, short_pulse_cnt_cur = 0;
+	u16 long_pulse_cnt_inc = 0, long_pulse_cnt_cur = 0;
 	u32 regf98_value = 0, reg918_value = 0, reg91c_value = 0;
 	u32 reg920_value = 0, reg924_value = 0, radar_rpt_reg_value = 0;
 	u32 regf54_value = 0, regf58_value = 0, regf5c_value = 0;
 	u32 regdf4_value = 0, regf70_value = 0, regf74_value = 0;
+	#if (RTL8812F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT)
 	u32 rega40_value = 0, rega44_value = 0, rega48_value = 0;
 	u32 rega4c_value = 0, rega50_value = 0, rega54_value = 0;
+	#endif
 	#if (RTL8721D_SUPPORT)
 	u32 reg908_value = 0, regdf4_value = 0;
 	u32 regf54_value = 0, regf58_value = 0, regf5c_value = 0;
@@ -852,7 +849,7 @@ phydm_radar_detect_dm_check(
 	boolean tri_short_pulse = 0, tri_long_pulse = 0, radar_type = 0;
 	boolean fault_flag_det = 0, fault_flag_psd = 0, fa_flag = 0;
 	boolean radar_detected = 0;
-	u8 st_l2h_new = 0, fa_mask_th = 0, sum = 0;
+	u8 st_l2h_new = 0, fa_mask_th = 0, k = 0, sum = 0;
 	u8 c_channel = *dm->channel;

 	/*@Get FA count during past 100ms, R_0xf48 for AC series*/
@@ -893,116 +890,16 @@ phydm_radar_detect_dm_check(

 	dfs->fa_inc_hist[dfs->mask_idx] = fa_count_inc;

-	for (i = 0; i < 5; i++) {
+	for (i = 0; i < 5; i++)
 		total_fa_in_hist = total_fa_in_hist + dfs->fa_inc_hist[i];
-		if (dfs->fa_inc_hist[i] > max_fa_in_hist)
-			max_fa_in_hist = dfs->fa_inc_hist[i];
-	}
+
 	if (dfs->mask_idx >= 2)
 		index = dfs->mask_idx - 2;
 	else
 		index = 5 + dfs->mask_idx - 2;
-	if (index == 0) {
-		pre_post_now_acc_fa_in_hist = dfs->fa_inc_hist[index] +
-					      dfs->fa_inc_hist[index + 1] +
-					      dfs->fa_inc_hist[4];
-	} else if (index == 4) {
-		pre_post_now_acc_fa_in_hist = dfs->fa_inc_hist[index] +
-					      dfs->fa_inc_hist[0] +
-					      dfs->fa_inc_hist[index - 1];
-	} else {
-		pre_post_now_acc_fa_in_hist = dfs->fa_inc_hist[index] +
-					      dfs->fa_inc_hist[index + 1] +
-					      dfs->fa_inc_hist[index - 1];
-	}
-
-	/*@Get VHT CRC32 ok count during past 100ms*/
-	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-		vht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0x2c0c, 0xffff);
-	#if (RTL8721D_SUPPORT)
-	else if (dm->support_ic_type & ODM_RTL8721D)
-		vht_crc_ok_cnt_cur = 0;
-	#endif
-	else
-		vht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0xf0c,
-							 0x00003fff);
-
-	if (vht_crc_ok_cnt_cur >= dfs->vht_crc_ok_cnt_pre) {
-		vht_crc_ok_cnt_inc = vht_crc_ok_cnt_cur -
-				     dfs->vht_crc_ok_cnt_pre;
-	} else {
-		vht_crc_ok_cnt_inc = vht_crc_ok_cnt_cur;
-	}
-	dfs->vht_crc_ok_cnt_pre = vht_crc_ok_cnt_cur;
-
-	/*@Get HT CRC32 ok count during past 100ms*/
-	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-		ht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0x2c10, 0xffff);
-	#if (RTL8721D_SUPPORT)
-	else if (dm->support_ic_type & (ODM_RTL8721D))
-		ht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0xf90, MASKLWORD);
-	#endif
-	else
-		ht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0xf10,
-							0x00003fff);
-
-	if (ht_crc_ok_cnt_cur >= dfs->ht_crc_ok_cnt_pre)
-		ht_crc_ok_cnt_inc = ht_crc_ok_cnt_cur - dfs->ht_crc_ok_cnt_pre;
-	else
-		ht_crc_ok_cnt_inc = ht_crc_ok_cnt_cur;
-	dfs->ht_crc_ok_cnt_pre = ht_crc_ok_cnt_cur;
-
-	/*@Get Legacy CRC32 ok count during past 100ms*/
-	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-		leg_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0x2c14, 0xffff);
-	#if (RTL8721D_SUPPORT)
-	else if (dm->support_ic_type & ODM_RTL8721D)
-		leg_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm,
-							 R_0xf94, MASKLWORD);
-	#endif
-	else
-		leg_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0xf14,
-							 0x00003fff);
-
-	if (leg_crc_ok_cnt_cur >= dfs->leg_crc_ok_cnt_pre)
-		leg_crc_ok_cnt_inc = leg_crc_ok_cnt_cur - dfs->leg_crc_ok_cnt_pre;
-	else
-		leg_crc_ok_cnt_inc = leg_crc_ok_cnt_cur;
-	dfs->leg_crc_ok_cnt_pre = leg_crc_ok_cnt_cur;
-
-	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-		if (vht_crc_ok_cnt_cur == 0xffff ||
-			ht_crc_ok_cnt_cur == 0xffff ||
-			leg_crc_ok_cnt_cur == 0xffff) {
-			phydm_reset_bb_hw_cnt(dm);
-		}
-	#if (RTL8721D_SUPPORT)
-	} else if (dm->support_ic_type & (ODM_RTL8721D)) {
-		if (ht_crc_ok_cnt_cur == 0xffff ||
-		    leg_crc_ok_cnt_cur == 0xffff) {
-			odm_set_bb_reg(dm, R_0xf14, BIT(16), 1);
-			odm_set_bb_reg(dm, R_0xf14, BIT(16), 0);
-		}
-	#endif
-	} else {
-		if (vht_crc_ok_cnt_cur == 0x3fff ||
-		    ht_crc_ok_cnt_cur == 0x3fff ||
-		    leg_crc_ok_cnt_cur == 0x3fff) {
-			phydm_reset_bb_hw_cnt(dm);
-		}
-	}
-
-	total_crc_ok_cnt_inc = vht_crc_ok_cnt_inc +
-			       ht_crc_ok_cnt_inc +
-			       leg_crc_ok_cnt_inc;

 	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
-				   ODM_RTL8197G)) {
-		/* if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x3b0)) {
-		 *	odm_set_bb_reg(dm, 0x1e28, 0x03c00000, 8);
-		 *	dbgport2dbc_value = phydm_get_bb_dbg_port_val(dm);
-		 *	phydm_release_bb_dbg_port(dm); }
-		 */
+				   ODM_RTL8197G| ODM_RTL8723F)) {
 		radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e00, 0xffffffff);
 		short_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x000ff800)
 					    >> 11);
@@ -1041,7 +938,6 @@ phydm_radar_detect_dm_check(
 	}

 	/*@Get short pulse count, need carefully handle the counter overflow*/
-
 	if (short_pulse_cnt_cur >= dfs->short_pulse_cnt_pre) {
 		short_pulse_cnt_inc = short_pulse_cnt_cur -
 				      dfs->short_pulse_cnt_pre;
@@ -1051,7 +947,6 @@ phydm_radar_detect_dm_check(
 	dfs->short_pulse_cnt_pre = short_pulse_cnt_cur;

 	/*@Get long pulse count, need carefully handle the counter overflow*/
-
 	if (long_pulse_cnt_cur >= dfs->long_pulse_cnt_pre) {
 		long_pulse_cnt_inc = long_pulse_cnt_cur -
 				     dfs->long_pulse_cnt_pre;
@@ -1065,10 +960,7 @@ phydm_radar_detect_dm_check(
 	if (dfs->det_print) {
 		PHYDM_DBG(dm, DBG_DFS,
 			  "===============================================\n");
-		PHYDM_DBG(dm, DBG_DFS,
-			  "Total_CRC_OK_cnt_inc[%d] VHT_CRC_ok_cnt_inc[%d] HT_CRC_ok_cnt_inc[%d] LEG_CRC_ok_cnt_inc[%d] FA_count_inc[%d]\n",
-			  total_crc_ok_cnt_inc, vht_crc_ok_cnt_inc,
-			  ht_crc_ok_cnt_inc, leg_crc_ok_cnt_inc, fa_count_inc);
+		PHYDM_DBG(dm, DBG_DFS, "FA_count_inc[%d]\n", fa_count_inc);
 		if (dm->support_ic_type & (ODM_RTL8721D)) {
 			PHYDM_DBG(dm, DBG_DFS,
 				  "Init_Gain[%x] st_l2h_cur[%x] 0xdf4[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
@@ -1089,6 +981,7 @@ phydm_radar_detect_dm_check(
 				  dfs->igi_cur, dfs->st_l2h_cur,
 				  radar_rpt_reg_value, short_pulse_cnt_inc,
 				  long_pulse_cnt_inc);
+		#if (RTL8812F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT)
 			rega40_value = odm_get_bb_reg(dm, R_0xa40, MASKDWORD);
 			rega44_value = odm_get_bb_reg(dm, R_0xa44, MASKDWORD);
 			rega48_value = odm_get_bb_reg(dm, R_0xa48, MASKDWORD);
@@ -1099,6 +992,7 @@ phydm_radar_detect_dm_check(
 				  "0xa40[%08x] 0xa44[%08x] 0xa48[%08x] 0xa4c[%08x] 0xa50[%08x] 0xa54[%08x]\n",
 				  rega40_value, rega44_value, rega48_value,
 				  rega4c_value, rega50_value, rega54_value);
+		#endif
 		} else {
 			PHYDM_DBG(dm, DBG_DFS,
 				  "Init_Gain[%x] 0x91c[%x] 0xf98[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
@@ -1163,11 +1057,8 @@ phydm_radar_detect_dm_check(
 	} else {
 		fa_mask_th = dfs->fa_mask_th;
 	}
-	if (max_fa_in_hist >= fa_mask_th ||
-	    total_fa_in_hist >= fa_mask_th ||
-	    pre_post_now_acc_fa_in_hist >= fa_mask_th ||
-	    dfs->igi_cur >= 0x30) {
-		st_l2h_new = dfs->st_l2h_max;
+	if (total_fa_in_hist >= fa_mask_th || dfs->igi_cur >= 0x30) {
+		/* st_l2h_new = dfs->st_l2h_max; */
 		dfs->radar_det_mask_hist[index] = 1;
 		if (dfs->pulse_flag_hist[index] == 1) {
 			dfs->pulse_flag_hist[index] = 0;
@@ -1194,9 +1085,8 @@ phydm_radar_detect_dm_check(
 		for (i = 0; i < 5; i++)
 			PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->fa_inc_hist[i]);
 		PHYDM_DBG(dm, DBG_DFS,
-			  "\nfa_mask_th: %d max_fa_in_hist: %d total_fa_in_hist: %d pre_post_now_acc_fa_in_hist: %d ",
-			  fa_mask_th, max_fa_in_hist, total_fa_in_hist,
-			  pre_post_now_acc_fa_in_hist);
+			  "\nfa_mask_th: %d, total_fa_in_hist: %d ",
+			  fa_mask_th, total_fa_in_hist);
 	}

 	sum = 0;
@@ -1291,6 +1181,7 @@ phydm_radar_detect_dm_check(
 	return radar_detected;
 }

+#if (RTL8814A_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT)
 void phydm_dfs_histogram_radar_distinguish(
 	void *dm_void)
 {
@@ -1309,43 +1200,18 @@ void phydm_dfs_histogram_radar_distinguish(
 	u8 max_pri_cnt_fcc_g1_th = 0, max_pri_cnt_fcc_g3_th = 0;
 	u8 safe_pri_pw_diff_th = 0, safe_pri_pw_diff_fcc_th = 0;
 	u8 safe_pri_pw_diff_w53_th = 0, safe_pri_pw_diff_fcc_idle_th = 0;
-	u16 j = 0;
-	u32 dfs_hist1_peak_index = 0, dfs_hist2_peak_index = 0;
+	u8 j = 0;
 	u32 dfs_hist1_pw = 0, dfs_hist2_pw = 0, g_pw[6] = {0};
-	u32 g_peakindex[16] = {0}, g_mask_32 = 0, false_peak_hist1 = 0;
-	u32 false_peak_hist2_above10 = 0, false_peak_hist2_above0 = 0;
 	u32 dfs_hist1_pri = 0, dfs_hist2_pri = 0, g_pri[6] = {0};
-	u32 pw_sum_g0g5 = 0, pw_sum_g1g2g3g4 = 0;
-	u32 pri_sum_g0g5 = 0, pri_sum_g1g2g3g4 = 0;
-	u32 pw_sum_ss_g1g2g3g4 = 0, pri_sum_ss_g1g2g3g4 = 0;
-	u32 max_pri_cnt = 0, max_pw_cnt = 0;
+	u8 pw_sum_g0g5 = 0, pw_sum_g1g2g3g4 = 0;
+	u8 pri_sum_g0g5 = 0, pri_sum_g1g2g3g4 = 0;
+	u16 pw_sum_ss_g1g2g3g4 = 0, pri_sum_ss_g1g2g3g4 = 0;
+	u8 max_pri_cnt = 0, max_pw_cnt = 0;
 	#if (RTL8721D_SUPPORT)
 	if (dm->support_ic_type & (ODM_RTL8721D))
 		return;
 	#endif

-	/*read peak index hist report*/
-	odm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x0);
-	dfs_hist1_peak_index = odm_get_bb_reg(dm, 0xf5c, 0xffffffff);
-	dfs_hist2_peak_index = odm_get_bb_reg(dm, 0xf74, 0xffffffff);
-
-	g_peakindex[15] = ((dfs_hist1_peak_index & 0x0000000f) >> 0);
-	g_peakindex[14] = ((dfs_hist1_peak_index & 0x000000f0) >> 4);
-	g_peakindex[13] = ((dfs_hist1_peak_index & 0x00000f00) >> 8);
-	g_peakindex[12] = ((dfs_hist1_peak_index & 0x0000f000) >> 12);
-	g_peakindex[11] = ((dfs_hist1_peak_index & 0x000f0000) >> 16);
-	g_peakindex[10] = ((dfs_hist1_peak_index & 0x00f00000) >> 20);
-	g_peakindex[9] = ((dfs_hist1_peak_index & 0x0f000000) >> 24);
-	g_peakindex[8] = ((dfs_hist1_peak_index & 0xf0000000) >> 28);
-	g_peakindex[7] = ((dfs_hist2_peak_index & 0x0000000f) >> 0);
-	g_peakindex[6] = ((dfs_hist2_peak_index & 0x000000f0) >> 4);
-	g_peakindex[5] = ((dfs_hist2_peak_index & 0x00000f00) >> 8);
-	g_peakindex[4] = ((dfs_hist2_peak_index & 0x0000f000) >> 12);
-	g_peakindex[3] = ((dfs_hist2_peak_index & 0x000f0000) >> 16);
-	g_peakindex[2] = ((dfs_hist2_peak_index & 0x00f00000) >> 20);
-	g_peakindex[1] = ((dfs_hist2_peak_index & 0x0f000000) >> 24);
-	g_peakindex[0] = ((dfs_hist2_peak_index & 0xf0000000) >> 28);
-
 	/*read pulse width hist report*/
 	odm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x1);
 	dfs_hist1_pw = odm_get_bb_reg(dm, 0xf5c, 0xffffffff);
@@ -1395,8 +1261,6 @@ void phydm_dfs_histogram_radar_distinguish(
 	for (i = 0; i < 6; i++) {
 		dfs->pw_hold_sum[i] = 0;
 		dfs->pri_hold_sum[i] = 0;
-		dfs->pw_long_hold_sum[i] = 0;
-		dfs->pri_long_hold_sum[i] = 0;
 	}

 	if (dfs->idle_mode == 1)
@@ -1410,49 +1274,27 @@ void phydm_dfs_histogram_radar_distinguish(
 		/*@collect whole histogram report may take some time
 		 *so we add the counter of 2 time slots in FCC and ETSI
 		 */
-		if (region_domain == 1 || region_domain == 3) {
-			dfs->pw_hold_sum[i] = dfs->pw_hold_sum[i] +
-				dfs->pw_hold[(dfs->hist_idx + 1) % 3][i] +
-				dfs->pw_hold[(dfs->hist_idx + 2) % 3][i];
-			dfs->pri_hold_sum[i] = dfs->pri_hold_sum[i] +
-				dfs->pri_hold[(dfs->hist_idx + 1) % 3][i] +
-				dfs->pri_hold[(dfs->hist_idx + 2) % 3][i];
-		} else{
-		/*@collect whole histogram report may take some time,
-		 *so we add the counter of 3 time slots in MKK or else
-		 */
-			dfs->pw_hold_sum[i] = dfs->pw_hold_sum[i] +
-				dfs->pw_hold[(dfs->hist_idx + 1) % 4][i] +
-				dfs->pw_hold[(dfs->hist_idx + 2) % 4][i] +
-				dfs->pw_hold[(dfs->hist_idx + 3) % 4][i];
-			dfs->pri_hold_sum[i] = dfs->pri_hold_sum[i] +
-				dfs->pri_hold[(dfs->hist_idx + 1) % 4][i] +
-				dfs->pri_hold[(dfs->hist_idx + 2) % 4][i] +
-				dfs->pri_hold[(dfs->hist_idx + 3) % 4][i];
-		}
+		dfs->pw_hold_sum[i] = dfs->pw_hold_sum[i] +
+			dfs->pw_hold[(dfs->hist_idx + 1) % 3][i] +
+			dfs->pw_hold[(dfs->hist_idx + 2) % 3][i];
+		dfs->pri_hold_sum[i] = dfs->pri_hold_sum[i] +
+			dfs->pri_hold[(dfs->hist_idx + 1) % 3][i] +
+			dfs->pri_hold[(dfs->hist_idx + 2) % 3][i];
 	}
 	/*@For long radar type*/
-	for (i = 0; i < 6; i++) {
-		dfs->pw_long_hold[dfs->hist_long_idx][i] = (u8)g_pw[i];
-		dfs->pri_long_hold[dfs->hist_long_idx][i] = (u8)g_pri[i];
-		/*@collect whole histogram report may take some time,
-		 *so we add the counter of 299 time slots for long radar
-		 */
-		for (j = 1; j < 300; j++) {
+	for (j = 1; j < 4; j++) {
 		dfs->pw_long_hold_sum[i] = dfs->pw_long_hold_sum[i] +
-			dfs->pw_long_hold[(dfs->hist_long_idx + j) % 300][i];
+			dfs->pw_hold[(dfs->hist_long_idx + j) % 4][i];
 		dfs->pri_long_hold_sum[i] = dfs->pri_long_hold_sum[i] +
-			dfs->pri_long_hold[(dfs->hist_long_idx + j) % 300][i];
-		}
+			dfs->pri_hold[(dfs->hist_long_idx + j) % 4][i];
 	}
+
 	dfs->hist_idx++;
-	dfs->hist_long_idx++;
-	if (region_domain == 1 || region_domain == 3) {
-		if (dfs->hist_idx == 3)
-			dfs->hist_idx = 0;
-	} else if (dfs->hist_idx == 4) {
+	if (dfs->hist_idx == 3)
 		dfs->hist_idx = 0;
-	}
+	dfs->hist_long_idx++;
+	if (dfs->hist_long_idx == 4)
+		dfs->hist_long_idx = 0;

 	max_pri_cnt = 0;
 	max_pri_idx = 0;
@@ -1506,20 +1348,14 @@ void phydm_dfs_histogram_radar_distinguish(
 	/*The value may less than the normal variance,
 	 *since the variable type is int (not float)
 	 */
-		dfs->pw_std = (u16)(pw_sum_ss_g1g2g3g4 / 4);
-		dfs->pri_std = (u16)(pri_sum_ss_g1g2g3g4 / 4);
+		dfs->pw_std = (u8)(pw_sum_ss_g1g2g3g4 / 4);
+		dfs->pri_std = (u8)(pri_sum_ss_g1g2g3g4 / 4);

 	if (region_domain == 1) {
 		dfs->pri_type3_4_flag = 1;	/*@ETSI flag*/

-		/*PRI judgment conditions for short radar type*/
-		/*ratio of reasonable group and illegal group &&
-		 *pri variation of short radar should be large (=6)
-		 */
-		if (max_pri_idx != 4 && dfs->pri_hold_sum[5] > 0)
-			dfs->pri_cond2 = 0;
-		else
-			dfs->pri_cond2 = 1;
+		/*(OTA) Cancel long PRI case*/
+		dfs->pri_cond2 = 1;

 		/*reasonable group shouldn't large*/
 		if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2 &&
@@ -1533,12 +1369,8 @@ void phydm_dfs_histogram_radar_distinguish(
 			 max_pri_cnt >= max_pri_cnt_fcc_g1_th)
 			dfs->pri_cond4 = 1;

-		/*we set threshold = 7 (>4) for distinguishing type 3,4 (g3)*/
-		if (max_pri_idx == 1 && dfs->pri_hold_sum[3] +
-		    dfs->pri_hold_sum[4] + dfs->pri_hold_sum[5] > 0)
-			dfs->pri_cond5 = 0;
-		else
-			dfs->pri_cond5 = 1;
+		/*(OTA) Cancel the condition (type 3,4 distinction)*/
+		dfs->pri_cond5 = 1;

 		if (dfs->pri_cond1 && dfs->pri_cond2 && dfs->pri_cond3 &&
 		    dfs->pri_cond4 && dfs->pri_cond5)
@@ -1671,7 +1503,7 @@ void phydm_dfs_histogram_radar_distinguish(
 			dfs->pri_cond3 = 1;

 		/*@Cancel the condition that the abs between pri and pw*/
-		dfs->pri_cond4 = 1;
+			dfs->pri_cond4 = 1;

 		if (dfs->pri_hold_sum[5] <= dfs->pri_sum_g5_th)
 			dfs->pri_cond5 = 1;
@@ -1725,12 +1557,6 @@ void phydm_dfs_histogram_radar_distinguish(
 		dfs_pri_thd4 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x00ff0000);
 		dfs_pri_thd5 = (u8)odm_get_bb_reg(dm, 0x19ec, 0xff000000);

-		PHYDM_DBG(dm, DBG_DFS, "peak index hist\n");
-		PHYDM_DBG(dm, DBG_DFS, "dfs_hist_peak_index=%x %x\n",
-			  dfs_hist1_peak_index, dfs_hist2_peak_index);
-		PHYDM_DBG(dm, DBG_DFS, "g_peak_index_hist = ");
-		for (i = 0; i < 16; i++)
-			PHYDM_DBG(dm, DBG_DFS, " %x", g_peakindex[i]);
 		PHYDM_DBG(dm, DBG_DFS, "\ndfs_pw_thd=%d %d %d %d %d\n",
 			  dfs_pw_thd1, dfs_pw_thd2, dfs_pw_thd3,
 			  dfs_pw_thd4, dfs_pw_thd5);
@@ -1785,13 +1611,6 @@ void phydm_dfs_histogram_radar_distinguish(
 		PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n", dfs->idle_mode);
 		PHYDM_DBG(dm, DBG_DFS, "pw_standard = %d\n", dfs->pw_std);
 		PHYDM_DBG(dm, DBG_DFS, "pri_standard = %d\n", dfs->pri_std);
-		for (j = 0; j < 4; j++) {
-			for (i = 0; i < 6; i++) {
-				PHYDM_DBG(dm, DBG_DFS, "pri_hold = %d ",
-					  dfs->pri_hold[j][i]);
-			}
-			PHYDM_DBG(dm, DBG_DFS, "\n");
-		}
 		PHYDM_DBG(dm, DBG_DFS, "\n");
 		PHYDM_DBG(dm, DBG_DFS,
 			  "pri_cond1 = %d, pri_cond2 = %d, pri_cond3 = %d, pri_cond4 = %d, pri_cond5 = %d\n",
@@ -1803,7 +1622,7 @@ void phydm_dfs_histogram_radar_distinguish(
 			  safe_pri_pw_diff_th);
 	}
 }
-
+#endif
 boolean phydm_dfs_hist_log(void *dm_void, u8 index)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
@@ -1949,22 +1768,6 @@ boolean phydm_dfs_hist_log(void *dm_void, u8 index)
 			PHYDM_DBG(dm, DBG_DFS, "\n");
 			PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n",
 				  dfs->idle_mode);
-			PHYDM_DBG(dm, DBG_DFS,
-				  "long_radar_pw_hold_sum = %d %d %d %d %d %d\n",
-				  dfs->pw_long_hold_sum[0],
-				  dfs->pw_long_hold_sum[1],
-				  dfs->pw_long_hold_sum[2],
-				  dfs->pw_long_hold_sum[3],
-				  dfs->pw_long_hold_sum[4],
-				  dfs->pw_long_hold_sum[5]);
-			PHYDM_DBG(dm, DBG_DFS,
-				  "long_radar_pri_hold_sum = %d %d %d %d %d %d\n",
-				  dfs->pri_long_hold_sum[0],
-				  dfs->pri_long_hold_sum[1],
-				  dfs->pri_long_hold_sum[2],
-				  dfs->pri_long_hold_sum[3],
-				  dfs->pri_long_hold_sum[4],
-				  dfs->pri_long_hold_sum[5]);
 		}
 		/* @Long radar should satisfy three conditions */
 		if (dfs->long_radar_flag == 1) {
@@ -1993,7 +1796,6 @@ boolean phydm_radar_detect(void *dm_void)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	struct _DFS_STATISTICS *dfs = &dm->dfs;
-	boolean enable_DFS = false;
 	boolean radar_detected = false;

 	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
@@ -2032,38 +1834,18 @@ boolean phydm_radar_detect(void *dm_void)
 			odm_set_bb_reg(dm, R_0x918, 0x00001f00,
 				       dfs->pwdb_th_cur);
 	}
-
 	dfs->igi_pre = dfs->igi_cur;

 	phydm_dfs_dynamic_setting(dm);
+	#if (RTL8814A_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT)
 	if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
 		phydm_dfs_histogram_radar_distinguish(dm);
+	#endif
 	radar_detected = phydm_radar_detect_dm_check(dm);

-	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
-				   ODM_RTL8197G)) {
-		if (odm_get_bb_reg(dm, R_0xa40, BIT(15)))
-			enable_DFS = true;
-	#if (RTL8721D_SUPPORT)
-	} else if (dm->support_ic_type & (ODM_RTL8721D)) {
-		if (odm_get_bb_reg(dm, R_0xf58, BIT(29)))
-			enable_DFS = true;
-	#endif
-	} else if (dm->support_ic_type & (ODM_RTL8814B)) {
-		if (dm->seg1_dfs_flag == 1) {
-			if (odm_get_bb_reg(dm, R_0xa6c, BIT(15)))
-				enable_DFS = true;
-		} else if (odm_get_bb_reg(dm, R_0xa40, BIT(15)))
-			enable_DFS = true;
-	} else {
-		if (odm_get_bb_reg(dm, R_0x924, BIT(15)))
-			enable_DFS = true;
-	}
-
-	if (enable_DFS && radar_detected) {
+	if (radar_detected) {
 		PHYDM_DBG(dm, DBG_DFS,
-			  "Radar detect: enable_DFS:%d, radar_detected:%d\n",
-			  enable_DFS, radar_detected);
+			  "Radar detect: %d\n", radar_detected);
 		phydm_radar_detect_reset(dm);
 		if (dfs->dbg_mode == 1) {
 			PHYDM_DBG(dm, DBG_DFS,
@@ -2072,13 +1854,13 @@ boolean phydm_radar_detect(void *dm_void)
 		}
 	}

-	if (enable_DFS && dfs->sw_trigger_mode == 1) {
+	if (dfs->sw_trigger_mode) {
 		radar_detected = 1;
 		PHYDM_DBG(dm, DBG_DFS,
 			  "Radar is detected in DFS SW trigger mode.\n");
 	}

-	return enable_DFS && radar_detected;
+	return radar_detected;
 }

 void phydm_dfs_hist_dbg(void *dm_void, char input[][16], u32 *_used,
@@ -2087,7 +1869,7 @@ void phydm_dfs_hist_dbg(void *dm_void, char input[][16], u32 *_used,
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	struct _DFS_STATISTICS *dfs = &dm->dfs;
 	char help[] = "-h";
-	u32 argv[30] = {0};
+	u32 argv[5] = {0};
 	u32 used = *_used;
 	u32 out_len = *_out_len;
 	u8 i;
@@ -2167,10 +1949,9 @@ void phydm_dfs_hist_dbg(void *dm_void, char input[][16], u32 *_used,
 	} else {
 		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &argv[0]);

-		for (i = 1; i < 30; i++) {
-			if (input[i + 1])
-				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
-					     &argv[i]);
+		for (i = 1; i < 5; i++) {
+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
+				     &argv[i]);
 		}
 		if (argv[0] == 0) {
 			dfs->pri_hist_th = (u8)argv[1];
@@ -2329,10 +2110,8 @@ void phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used,
 	u8 i, input_idx = 0;

 	for (i = 0; i < 7; i++) {
-		if (input[i + 1]) {
-			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &argv[i]);
-			input_idx++;
-		}
+		PHYDM_SSCANF(input[i + 1], DCMD_HEX, &argv[i]);
+		input_idx++;
 	}

 	if (input_idx == 0)
@@ -2351,34 +2130,6 @@ void phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used,
 		 dfs->dbg_mode, dfs->sw_trigger_mode, dfs->force_TP_mode,
 		 dfs->det_print, dfs->det_print2, dfs->print_hist_rpt,
 		 dfs->hist_cond_on);
-
-	/*switch (argv[0]) {
-	case 1:
-#if defined(CONFIG_PHYDM_DFS_MASTER)
-		 set dbg parameters for radar detection instead of the default value
-		if (argv[1] == 1) {
-			dm->radar_detect_reg_918 = argv[2];
-			dm->radar_detect_reg_91c = argv[3];
-			dm->radar_detect_reg_920 = argv[4];
-			dm->radar_detect_reg_924 = argv[5];
-			dm->radar_detect_dbg_parm_en = 1;
-
-			PDM_SNPF((output + used, out_len - used, "Radar detection with dbg parameter\n"));
-			PDM_SNPF((output + used, out_len - used, "reg918:0x%08X\n", dm->radar_detect_reg_918));
-			PDM_SNPF((output + used, out_len - used, "reg91c:0x%08X\n", dm->radar_detect_reg_91c));
-			PDM_SNPF((output + used, out_len - used, "reg920:0x%08X\n", dm->radar_detect_reg_920));
-			PDM_SNPF((output + used, out_len - used, "reg924:0x%08X\n", dm->radar_detect_reg_924));
-		} else {
-			dm->radar_detect_dbg_parm_en = 0;
-			PDM_SNPF((output + used, out_len - used, "Radar detection with default parameter\n"));
-		}
-		phydm_radar_detect_enable(dm);
-#endif  defined(CONFIG_PHYDM_DFS_MASTER)
-
-		break;
-	default:
-		break;
-	}*/
 }

 u8 phydm_dfs_polling_time(void *dm_void)
--- a/hal/phydm/phydm_dfs.h
+++ b/hal/phydm/phydm_dfs.h
@@ -47,9 +47,6 @@ struct _DFS_STATISTICS {
 	u8		st_l2h_cur;
 	u16		fa_count_pre;
 	u16		fa_inc_hist[5];
-	u16		vht_crc_ok_cnt_pre;
-	u16		ht_crc_ok_cnt_pre;
-	u16		leg_crc_ok_cnt_pre;
 	u16		short_pulse_cnt_pre;
 	u16		long_pulse_cnt_pre;
 	u8		pwdb_th;
@@ -62,10 +59,10 @@ struct _DFS_STATISTICS {
 	u8		three_peak_opt;
 	u8		three_peak_th2;
 	u8		fa_mask_th;
-	u8		det_flag_offset;
 	u8		st_l2h_max;
 	u8		st_l2h_min;
-	u8		mask_hist_checked;
+	u8		dfs_polling_time;
+	u8		mask_hist_checked : 3;
 	boolean		pulse_flag_hist[5];
 	boolean		pulse_type_hist[5];
 	boolean		radar_det_mask_hist[5];
@@ -76,10 +73,9 @@ struct _DFS_STATISTICS {
 	boolean		det_print;
 	boolean		det_print2;
 	boolean		radar_type;
-	u8		dfs_polling_time;
-	/*@dfs histogram*/
 	boolean		print_hist_rpt;
 	boolean		hist_cond_on;
+	/*@dfs histogram*/
 	boolean		pri_cond1;
 	boolean		pri_cond2;
 	boolean		pri_cond3;
@@ -97,47 +93,45 @@ struct _DFS_STATISTICS {
 	boolean		pri_flag;
 	boolean		pri_type3_4_flag;	/*@for ETSI*/
 	boolean		long_radar_flag;
-	u16		pri_hold_sum[6];
-	u16		pw_hold_sum[6];
-	u16		pri_long_hold_sum[6];
-	u16		pw_long_hold_sum[6];
+	u8		pri_hold_sum[6];
+	u8		pw_hold_sum[6];
+	u8		pri_long_hold_sum[6];
+	u8		pw_long_hold_sum[6];
 	u8		hist_idx;
 	u8		hist_long_idx;
 	u8		pw_hold[4][6];
 	u8		pri_hold[4][6];
-	u8		pw_long_hold[300][6];
-	u8		pri_long_hold[300][6];
-	u16		pw_std;	/*@The std(var) of reasonable num of pw group*/
-	u16		pri_std;/*@The std(var) of reasonable num of pri group*/
+	u8		pw_std;	/*@The std(var) of reasonable num of pw group*/
+	u8		pri_std;/*@The std(var) of reasonable num of pri group*/
 	/*@dfs histogram threshold*/
-	u8		pri_hist_th;
-	u8		pri_sum_g1_th;
-	u8		pri_sum_g5_th;
-	u8		pri_sum_g1_fcc_th;
-	u8		pri_sum_g3_fcc_th;
-	u8		pri_sum_safe_fcc_th;
-	u8		pri_sum_type4_th;
-	u8		pri_sum_type6_th;
-	u8		pri_sum_safe_th;
-	u8		pri_sum_g5_under_g1_th;
-	u8		pri_pw_diff_th;
-	u8		pri_pw_diff_fcc_th;
-	u8		pri_pw_diff_fcc_idle_th;
-	u8		pri_pw_diff_w53_th;
-	u8		pri_type1_low_fcc_th;
-	u8		pri_type1_upp_fcc_th;
-	u8		pri_type1_cen_fcc_th;
-	u8		pw_g0_th;
-	u8		pw_long_lower_20m_th;
-	u8		pw_long_lower_th;
-	u8		pri_long_upper_th;
-	u8		pw_long_sum_upper_th;
-	u8		pw_std_th;
-	u8		pw_std_idle_th;
-	u8		pri_std_th;
-	u8		pri_std_idle_th;
-	u8		type4_pw_max_cnt;
-	u8		type4_safe_pri_sum_th;
+	u8		pri_hist_th : 3;
+	u8		pri_sum_g1_th : 4;
+	u8		pri_sum_g5_th : 4;
+	u8		pri_sum_g1_fcc_th : 3;
+	u8		pri_sum_g3_fcc_th : 3;
+	u8		pri_sum_safe_fcc_th : 7;
+	u8		pri_sum_type4_th : 5;
+	u8		pri_sum_type6_th : 5;
+	u8		pri_sum_safe_th : 6;
+	u8		pri_sum_g5_under_g1_th : 3;
+	u8		pri_pw_diff_th : 3;
+	u8		pri_pw_diff_fcc_th : 4;
+	u8		pri_pw_diff_fcc_idle_th : 2;
+	u8		pri_pw_diff_w53_th : 4;
+	u8		pri_type1_low_fcc_th : 7;
+	u8		pri_type1_upp_fcc_th : 7;
+	u8		pri_type1_cen_fcc_th : 7;
+	u8		pw_g0_th : 4;
+	u8		pw_long_lower_20m_th : 4;
+	u8		pw_long_lower_th : 3;
+	u8		pri_long_upper_th : 6;
+	u8		pw_long_sum_upper_th : 7;
+	u8		pw_std_th : 4;
+	u8		pw_std_idle_th : 4;
+	u8		pri_std_th : 4;
+	u8		pri_std_idle_th : 4;
+	u8		type4_pw_max_cnt : 4;
+	u8		type4_safe_pri_sum_th : 3;
 };

 /*@
--- a/hal/phydm/phydm_dig.c
+++ b/hal/phydm/phydm_dig.c
--- a/hal/phydm/phydm_dig.h
+++ b/hal/phydm/phydm_dig.h
@@ -26,10 +26,11 @@
 #ifndef __PHYDMDIG_H__
 #define __PHYDMDIG_H__

-#define DIG_VERSION "2.5" /* @Add new fa_cnt for VHT-SIGA/VHT-SIGB*/
+/* 2020.08.13 Add IFS-CLM/FAHM in dig fa source for more accurate fa info*/
+#define DIG_VERSION "3.9"

 #define	DIG_HW		0
-#define DIG_LIMIT_PERIOD 60 /*@60 sec*/
+#define DIG_LIMIT_PERIOD 60 /*60 sec*/

 /*@--------------------Define ---------------------------------------*/

@@ -80,18 +81,29 @@
 #define	RSSI_OFFSET_DIG_LPS		5
 #define DIG_RECORD_NUM			4

-/*@--------------------Enum-----------------------------------*/
-enum dig_goupcheck_level {
-	DIG_GOUPCHECK_LEVEL_0,
-	DIG_GOUPCHECK_LEVEL_1,
-	DIG_GOUPCHECK_LEVEL_2
-};
+/*==== [FA duration] =======================================*/
+/*[PHYDM-406]*/
+#define OFDM_FA_EXP_DURATION		12	/*us*/
+#define CCK_FA_EXP_DURATION		175	/*us*/

+/*@--------------------Enum-----------------------------------*/
 enum phydm_dig_mode {
 	PHYDM_DIG_PERFORAMNCE_MODE	= 0,
 	PHYDM_DIG_COVERAGE_MODE		= 1,
 };

+enum phydm_dig_trend {
+	DIG_STABLE			= 0,
+	DIG_INCREASING			= 1,
+	DIG_DECREASING			= 2
+};
+
+enum phydm_fw_dig_mode_e {
+	DIG_PERFORMANCE_MODE	= 0,
+	DIG_COVERAGE_MODE	= 1,
+	DIG_LPS_MODE		= 2
+};
+
 #ifdef PHYDM_TDMA_DIG_SUPPORT
 enum upd_type {
 	ENABLE_TDMA,
@@ -141,8 +153,11 @@ struct phydm_dig_struct {
 	struct phydm_dig_recorder_strcut dig_recorder_t;
 	u8		dig_dl_en; /*@damping limit function enable*/
 #endif
+	boolean		fw_dig_enable;
 	boolean		is_dbg_fa_th;
 	u8		cur_ig_value;
+	boolean		igi_dyn_up_hit;
+	u8		igi_trend;
 	u32		rvrt_val; /*all rvrt_val for pause API must set to u32*/
 	u8		igi_backup;
 	u8		rx_gain_range_max;	/*@dig_dynamic_max*/
@@ -152,12 +167,14 @@ struct phydm_dig_struct {
 	u8		dig_max_of_min;		/*@Absolutly max of min*/
 	u32		ant_div_rssi_max;
 	u8		*is_p2p_in_process;
-	enum dig_goupcheck_level	go_up_chk_lv;
-	u16		fa_th[3];
+	u32		fa_th[3];
+	u32		dm_dig_fa_th1;
+	u8		fa_source;
 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\
 	RTL8198F_SUPPORT || RTL8192F_SUPPORT || RTL8195B_SUPPORT ||\
 	RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8721D_SUPPORT ||\
-	RTL8710C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
+	RTL8710C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT ||\
+	RTL8723F_SUPPORT)
 	u8		rf_gain_idx;
 	u8		agc_table_idx;
 	u8		big_jump_lmt[16];
@@ -173,7 +190,7 @@ struct phydm_dig_struct {
 	u8		cur_ig_value_tdma;
 	u8		low_ig_value;
 	u8		tdma_dig_state;	/*@To distinguish which state is now.(L-sate or H-state)*/
-	u32		tdma_dig_cnt;	/*@for phydm_tdma_dig_timer_check use*/
+	u8		tdma_dig_cnt;	/*@for phydm_tdma_dig_timer_check use*/
 	u8		pre_tdma_dig_cnt;
 	u8		sec_factor;
 	u32		cur_timestamp;
@@ -189,6 +206,8 @@ struct phydm_dig_struct {
 	u8		tdma_rx_gain_min[DIG_NUM_OF_TDMA_STATES];
 			/*To distinguish current state(L-sate or H-state)*/
 #endif
+	u8		tdma_force_l_igi;
+	u8		tdma_force_h_igi;
 #endif
 };

@@ -226,10 +245,29 @@ struct phydm_fa_struct {
 	u32		cnt_crc32_error_all;
 	u32		cnt_crc32_ok_all;
 	u32		time_fa_all;
+	u32		time_fa_exp; /*FA duration, [PHYDM-406]*/
+	u32		time_fa_ifs_clm; /*FA duration, [PHYDM-406]*/
+	u32		time_fa_fahm; /*FA duration, [PHYDM-406]*/
 	boolean		cck_block_enable;
 	boolean		ofdm_block_enable;
 	u32		dbg_port0;
 	boolean		edcca_flag;
+	u8		ofdm2_rate_idx;
+	u32		cnt_ofdm2_crc32_error;
+	u32		cnt_ofdm2_crc32_ok;
+	u8		ofdm2_pcr;
+	u8		ht2_rate_idx;
+	u32		cnt_ht2_crc32_error;
+	u32		cnt_ht2_crc32_ok;
+	u8		ht2_pcr;
+	u8		vht2_rate_idx;
+	u32		cnt_vht2_crc32_error;
+	u32		cnt_vht2_crc32_ok;
+	u8		vht2_pcr;
+	u32		cnt_cck_txen;
+	u32		cnt_cck_txon;
+	u32		cnt_ofdm_txen;
+	u32		cnt_ofdm_txon;
 };

 #ifdef PHYDM_TDMA_DIG_SUPPORT
@@ -277,6 +315,13 @@ void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len);
 void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type,
 		   enum phydm_pause_level pause_level, u8 igi_value);

+#ifdef PHYDM_HW_IGI
+void phydm_hwigi(void *dm_void);
+
+void phydm_hwigi_dbg(void *dm_void, char input[][16], u32 *_used,
+		     char *output, u32 *_out_len);
+#endif
+
 void phydm_dig_init(void *dm_void);

 void phydm_dig(void *dm_void);
@@ -285,8 +330,14 @@ void phydm_dig_lps_32k(void *dm_void);

 void phydm_dig_by_rssi_lps(void *dm_void);

+void phydm_get_dig_coverage(void *dm_void, u8 *max, u8 *min);
+
+u8 phydm_get_igi_for_target_pin_scan(void *dm_void, u8 rssi);
+
 void phydm_false_alarm_counter_statistics(void *dm_void);

+u32 phydm_get_edcca_report(void * dm_void);
+
 #ifdef PHYDM_TDMA_DIG_SUPPORT
 void phydm_set_tdma_dig_timer(void *dm_void);

@@ -329,9 +380,14 @@ void phydm_set_ofdm_agc_tab(void *dm_void, u8 tab_sel);
 void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output,
 		     u32 *_out_len);

+void phydm_fill_fw_dig_info(void *dm_void, boolean *enable,
+			    u8 *para4, u8 *para8);
+
+void phydm_crc32_cnt_dbg(void *dm_void, char input[][16], u32 *_used,
+			 char *output, u32 *_out_len);
+
 #ifdef CONFIG_MCC_DM
 void phydm_mcc_igi_cal(void *dm_void);
 #endif

-
 #endif
--- a/hal/phydm/phydm_direct_bf.c
+++ b/hal/phydm/phydm_direct_bf.c
@@ -94,7 +94,7 @@ void phydm_iq_gen_en(void *dm_void)
 		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000);
 		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x000cf);
 		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x71fc2);
-		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000);
+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x08000);
 		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x000ef);
 		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x01042);
 		odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0);
--- a/hal/phydm/phydm_dynamictxpower.c
+++ b/hal/phydm/phydm_dynamictxpower.c
@@ -135,7 +135,7 @@ void phydm_wt_ram_pwr(void *dm_void, u8 macid, boolean is_ofst1,
 		dm_ram_per_sta->tx_pwr_offset1 = pwr_ofst;

 		pwr_ofst_ano_en = dm_ram_per_sta->tx_pwr_offset0_en;
-		pwr_ofst_ano = dm_ram_per_sta->tx_pwr_offset1;
+		pwr_ofst_ano = dm_ram_per_sta->tx_pwr_offset0;

 		reg_0x1e84 |= (pwr_ofst_ano_en << 15) +
 			      ((pwr_ofst_ano & 0x7f) << 8) +
@@ -199,29 +199,24 @@ void phydm_pwr_lv_ctrl(void *dm_void, u8 macid, u8 tx_pwr_lv)
 		pwr_offset = PHYDM_BBRAM_OFFSET_ZERO;

 	phydm_wt_ram_pwr(dm, macid, RAM_PWR_OFST0, true, pwr_offset);
-	/* still need to check with SD7*/
-	#if (RTL8822C_SUPPORT)
-	if (dm->support_ic_type & ODM_RTL8822C)
-		phydm_wt_ram_pwr(dm, 127, RAM_PWR_OFST0, true, pwr_offset);
-	#endif
 }

-void phydm_dtp_fill_cmninfo_2nd(void *dm_void, u8 macid, u8 dtp_lvl)
+void phydm_dtp_fill_cmninfo_2nd(void *dm_void, u8 sta_id, u8 dtp_lvl)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
-	struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_id];
 	struct dtp_info *dtp = NULL;

 	if (!is_sta_active(sta))
 		return;

-	dtp = &dm->phydm_sta_info[macid]->dtp_stat;
+	dtp = &dm->phydm_sta_info[sta_id]->dtp_stat;
 	dtp->dyn_tx_power = phydm_pwr_lv_mapping_2nd(dtp_lvl);
-	phydm_pwr_lv_ctrl(dm, macid, dtp_lvl);
+	phydm_pwr_lv_ctrl(dm, sta->mac_id, dtp_lvl);

 	PHYDM_DBG(dm, DBG_DYN_TXPWR,
-		  "Fill cmninfo TxPwr: macid=(%d), PwrLv (%d)\n", macid,
-		  dtp->dyn_tx_power);
+		  "Fill cmninfo TxPwr: sta_id=(%d), macid=(%d), PwrLv (%d)\n",
+		  sta_id, sta->mac_id, dtp->dyn_tx_power);
 }

 void phydm_dtp_init_2nd(void *dm_void)
@@ -231,8 +226,8 @@ void phydm_dtp_init_2nd(void *dm_void)
 	if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
 		return;

-	#if (RTL8822C_SUPPORT)
-	if (dm->support_ic_type & ODM_RTL8822C) {
+	#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT)
+	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) {
 		phydm_rst_ram_pwr(dm);
 		/* rsp tx use type 0*/
 		odm_set_mac_reg(dm, R_0x6d8, BIT(19) | BIT(18), RAM_PWR_OFST0);
@@ -323,15 +318,14 @@ phydm_check_paths(void *dm_void)
 	return max_path;
 }

-#ifndef PHYDM_COMMON_API_SUPPORT
+#ifdef PHYDM_COMMON_API_NOT_SUPPORT
 u8 phydm_dtp_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	u8 ret = 0xff;

-#if (RTL8192E_SUPPORT)
 	ret = config_phydm_read_txagc_n(dm, path, hw_rate);
-#endif
+
 	return ret;
 }
 #endif
@@ -342,21 +336,27 @@ u8 phydm_search_min_power_index(void *dm_void)
 	enum rf_path path;
 	enum rf_path max_path;
 	u8 min_gain_index = 0x3f;
-	u8 gain_index;
-	u8 rate_idx;
+	u8 gain_index = 0;
+	u8 i;

 	PHYDM_DBG(dm, DBG_DYN_TXPWR, "%s\n", __func__);
 	max_path = phydm_check_paths(dm);
 	for (path = 0; path <= max_path; path++)
-		for (rate_idx = 0; rate_idx < 84; rate_idx++)
-			if (phydm_check_rates(dm, rate_idx)) {
-#ifdef PHYDM_COMMON_API_SUPPORT
-				/*This is for API support IC : 97F,8822B,92F,8821C*/
-				gain_index = phydm_api_get_txagc(dm, path, rate_idx);
-#else
-				/*This is for API non-support IC : 92E */
-				gain_index = phydm_dtp_get_txagc(dm, path, rate_idx);
-#endif
+		for (i = 0; i < 84; i++)
+			if (phydm_check_rates(dm, i)) {
+
+				if (dm->support_ic_type & PHYDM_COMMON_API_IC) {
+				#ifdef PHYDM_COMMON_API_SUPPORT
+				/*97F,8822B,92F,8821C*/
+				gain_index = phydm_api_get_txagc(dm, path, i);
+				#endif
+				} else {
+				/*92E*/
+				#ifdef PHYDM_COMMON_API_NOT_SUPPORT
+				gain_index = phydm_dtp_get_txagc(dm, path, i);
+				#endif
+				}
+
 				if (gain_index == 0xff) {
 					min_gain_index = 0x20;
 					PHYDM_DBG(dm, DBG_DYN_TXPWR, 
@@ -366,7 +366,7 @@ u8 phydm_search_min_power_index(void *dm_void)
 				}
 				PHYDM_DBG(dm, DBG_DYN_TXPWR,
 					  "Support Rate: ((%d)) -> Gain idx: ((%d))\n",
-					  rate_idx, gain_index);
+					  i, gain_index);
 				if (gain_index < min_gain_index)
 					min_gain_index = gain_index;
 			}
@@ -423,34 +423,45 @@ void phydm_noisy_enhance_hp_th(void *dm_void, u8 noisy_state)
 		  dm->enhance_pwr_th[2]);
 }

-u8 phydm_pwr_lvl_check(void *dm_void, u8 input_rssi)
+u8 phydm_pwr_lvl_check(void *dm_void, u8 input_rssi, u8 last_pwr_lv)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
-	u8 th0, th1, th2;
+	u8 th[DTP_POWER_LEVEL_SIZE];
+	u8 i;

 	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-		th2 = dm->set_pwr_th[2];
-		th1 = dm->set_pwr_th[1];
-		th0 = dm->set_pwr_th[0];
+		for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++)
+			th[i] = dm->set_pwr_th[i];
+
 		PHYDM_DBG(dm, DBG_DYN_TXPWR,
-			  "DTP th: Lv1_th = %d, Lv2_th = %d, Lv3_th = %d\n",
-			  th0, th1, th2);
+			  "Ori-DTP th: Lv1_th = %d, Lv2_th = %d, Lv3_th = %d\n",
+			  th[0], th[1], th[2]);
+
+		for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++) {
+			if (i >= (last_pwr_lv))
+				th[i] += DTP_FLOOR_UP_GAP;
+		}
+
+		PHYDM_DBG(dm, DBG_DYN_TXPWR,
+			  "Mod-DTP th: Lv1_th = %d, Lv2_th = %d, Lv3_th = %d\n",
+			  th[0], th[1], th[2]);
 	} else {
-		th2 = dm->enhance_pwr_th[2];
-		th1 = dm->enhance_pwr_th[1];
-		th0 = dm->enhance_pwr_th[0];
+		for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++)
+			th[i] = dm->enhance_pwr_th[i];
+		for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++) {
+			if (i >= (last_pwr_lv))
+				th[i] += DTP_FLOOR_UP_GAP;
+		}
 	}

-	if (input_rssi >= th2)
+	if (input_rssi >= th[2])
 		return tx_high_pwr_level_level3;
-	else if (input_rssi < (th2 - 3) && input_rssi >= th1)
+	else if (input_rssi < th[2] && input_rssi >= th[1])
 		return tx_high_pwr_level_level2;
-	else if (input_rssi < (th1 - 3) && input_rssi >= th0)
+	else if (input_rssi < th[1] && input_rssi >= th[0])
 		return tx_high_pwr_level_level1;
-	else if (input_rssi < (th0 - 3))
-		return tx_high_pwr_level_normal;
 	else
-		return tx_high_pwr_level_unchange;
+		return tx_high_pwr_level_normal;
 }

 u8 phydm_pwr_lv_mapping(u8 tx_pwr_lv)
@@ -473,8 +484,7 @@ void phydm_dynamic_response_power(void *dm_void)
 	if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
 		return;

-	if (dm->dynamic_tx_high_power_lvl == tx_high_pwr_level_unchange) {
-		dm->dynamic_tx_high_power_lvl = dm->last_dtp_lvl;
+	if (dm->dynamic_tx_high_power_lvl == dm->last_dtp_lvl) {
 		PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr not change\n");
 		return;
 	}
@@ -489,10 +499,10 @@ void phydm_dynamic_response_power(void *dm_void)
 		  dm->dynamic_tx_high_power_lvl);
 }

-void phydm_dtp_fill_cmninfo(void *dm_void, u8 macid, u8 dtp_lvl)
+void phydm_dtp_fill_cmninfo(void *dm_void, u8 sta_id, u8 dtp_lvl)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
-	struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_id];
 	struct dtp_info *dtp = NULL;

 	if (!is_sta_active(sta))
@@ -501,61 +511,97 @@ void phydm_dtp_fill_cmninfo(void *dm_void, u8 macid, u8 dtp_lvl)
 	dtp = &sta->dtp_stat;
 	dtp->dyn_tx_power = phydm_pwr_lv_mapping(dtp_lvl);
 	PHYDM_DBG(dm, DBG_DYN_TXPWR,
-		  "Fill cmninfo TxPwr: macid=(%d), PwrLv (%d)\n", macid,
-		  dtp->dyn_tx_power);
+		  "Fill cmninfo TxPwr: sta_id=(%d), macid=(%d), PwrLv (%d)\n",
+		  sta_id, sta->mac_id, dtp->dyn_tx_power);
 }

-void phydm_dtp_per_sta(void *dm_void, u8 macid)
+void phydm_dtp_per_sta(void *dm_void)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
-	struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
+	struct cmn_sta_info *sta = NULL;
 	struct dtp_info *dtp = NULL;
 	struct rssi_info *rssi = NULL;
+	struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
+	u8 sta_cnt = 0;
+	u8 i = 0;
+	u8 curr_pwr_lv = 0;
+	u8 last_pwr_lv = 0;
+	u8 mac_id_cnt = 0;
+	u64 macid_cur = 0;
+	u64 macid_diff = 0;
+	u64 macid_mask = 0;

-	if (is_sta_active(sta)) {
-		dtp = &sta->dtp_stat;
-		rssi = &sta->rssi_stat;
-		dtp->sta_tx_high_power_lvl = phydm_pwr_lvl_check(dm,
-								 rssi->rssi);
-		PHYDM_DBG(dm, DBG_DYN_TXPWR,
-			  "STA=%d , RSSI: %d , GetPwrLv: %d\n", macid,
-			  rssi->rssi, dtp->sta_tx_high_power_lvl);
+	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
+		sta = dm->phydm_sta_info[i];
+		if (is_sta_active(sta)) {
+			sta_cnt++;

-		if (dtp->sta_tx_high_power_lvl == tx_high_pwr_level_unchange 
-			|| dtp->sta_tx_high_power_lvl == dtp->sta_last_dtp_lvl) {
-			dtp->sta_tx_high_power_lvl = dtp->sta_last_dtp_lvl;
+			dtp = &sta->dtp_stat;
+			rssi = &sta->rssi_stat;
+			macid_mask = (u64)BIT(sta->mac_id);
+			if (!(bb_ctrl->macid_is_linked & macid_mask))
+				dtp->sta_last_dtp_lvl = tx_high_pwr_level_normal;
+
+			last_pwr_lv = dtp->sta_last_dtp_lvl;
+			curr_pwr_lv = phydm_pwr_lvl_check(dm, rssi->rssi,
+							  last_pwr_lv);
+			dtp->sta_tx_high_power_lvl = curr_pwr_lv;
 			PHYDM_DBG(dm, DBG_DYN_TXPWR,
-				  "DTP_lv not change: ((%d))\n",
-				  dtp->sta_tx_high_power_lvl);
-			return;
-		}
-
-		PHYDM_DBG(dm, DBG_DYN_TXPWR,
-			  "DTP_lv update: ((%d)) -> ((%d))\n",
-			  dtp->sta_last_dtp_lvl, dtp->sta_tx_high_power_lvl);
-
-		dtp->sta_last_dtp_lvl = dtp->sta_tx_high_power_lvl;
-
-		switch (dm->ic_ip_series) {
-		#ifdef BB_RAM_SUPPORT
-		case PHYDM_IC_JGR3:
-			phydm_dtp_fill_cmninfo_2nd(dm, macid,
-						   dtp->sta_tx_high_power_lvl);
-			break;
-		#endif
-		default:
-			phydm_dtp_fill_cmninfo(dm, macid,
-					       dtp->sta_tx_high_power_lvl);
-			break;
+				  "STA_id=%d, MACID=%d , RSSI: %d , GetPwrLv: %d\n",
+				  i, sta->mac_id, rssi->rssi, curr_pwr_lv);
+
+			bb_ctrl->macid_is_linked |= macid_mask;
+			macid_cur |= macid_mask;
+			PHYDM_DBG(dm, DBG_DYN_TXPWR,
+				    "macid_is_linked: (0x%llx), macid_cur: (0x%llx)\n",
+				    bb_ctrl->macid_is_linked, macid_cur);
+
+			if (curr_pwr_lv == last_pwr_lv && dtp->sta_is_alive) {
+				dtp->sta_tx_high_power_lvl = last_pwr_lv;
+				PHYDM_DBG(dm, DBG_DYN_TXPWR,
+					  "DTP_lv not change: ((%d))\n",
+					  curr_pwr_lv);
+			} else {
+				PHYDM_DBG(dm, DBG_DYN_TXPWR,
+					  "DTP_lv update: ((%d)) -> ((%d))\n",
+					  last_pwr_lv, curr_pwr_lv);
+
+				dtp->sta_last_dtp_lvl = curr_pwr_lv;
+
+				switch (dm->ic_ip_series) {
+				#ifdef BB_RAM_SUPPORT
+				case PHYDM_IC_JGR3:
+					phydm_dtp_fill_cmninfo_2nd(dm, i, curr_pwr_lv);
+					break;
+				#endif
+				default:
+					phydm_dtp_fill_cmninfo(dm, i, curr_pwr_lv);
+					break;
+				}
+				if(!dtp->sta_is_alive)
+					dtp->sta_is_alive = true;
+			}
+
+			if (sta_cnt == dm->number_linked_client)
+				break;
 		}
+	}

+	macid_diff = bb_ctrl->macid_is_linked ^ macid_cur;
+	if (macid_diff)
+		bb_ctrl->macid_is_linked &= ~macid_diff;
+	while (macid_diff) {
+		if (macid_diff & 0x1)
+			phydm_pwr_lv_ctrl(dm, mac_id_cnt, tx_high_pwr_level_normal);
+		mac_id_cnt++;
+		macid_diff >>= 1;
 	}
 }

-void odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 macid)
+void odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 sta_id)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
-	struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_id];
 	struct dtp_info *dtp = NULL;

 	if (!is_sta_active(sta))
@@ -671,7 +717,7 @@ void phydm_dynamic_tx_power(void *dm_void)
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	struct cmn_sta_info *sta = NULL;
 	u8 i = 0;
-	u8 cnt = 0;
+
 	u8 rssi_min = dm->rssi_min;
 	u8 rssi_tmp = 0;

@@ -685,16 +731,12 @@ void phydm_dynamic_tx_power(void *dm_void)
 		phydm_noisy_enhance_hp_th(dm, dm->noisy_decision);
 		/* Response Power */
 		dm->dynamic_tx_high_power_lvl = phydm_pwr_lvl_check(dm,
-								    rssi_min);
+								    rssi_min,
+							    dm->last_dtp_lvl);
 		phydm_dynamic_response_power(dm);
 	}
 	/* Per STA Tx power */
-	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
-		phydm_dtp_per_sta(dm, i);
-		cnt++;
-		if (cnt >= dm->number_linked_client)
-			break;
-	}
+	phydm_dtp_per_sta(dm);
 }
 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)

--- a/hal/phydm/phydm_dynamictxpower.h
+++ b/hal/phydm/phydm_dynamictxpower.h
@@ -32,8 +32,10 @@
 * ============================================================
 */

-/* 2019.2.12, refine code structure and set macid 127 only for 22C*/
-#define DYNAMIC_TXPWR_VERSION "1.8"
+/* 2020.6.23, Let gain_idx be initialized to 0 for linux compile warning*/
+#define DYNAMIC_TXPWR_VERSION "2.1"
+
+#define DTP_POWER_LEVEL_SIZE 3

 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
@@ -48,9 +50,9 @@
 #endif

 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 255
-#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 74
-#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 60
+#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 80
+#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 63
+#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 55
 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 90
 #define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 85
@@ -66,6 +68,7 @@
 #define tx_high_pwr_level_level2 2
 #define tx_high_pwr_level_level3 3
 #define tx_high_pwr_level_unchange 4
+#define DTP_FLOOR_UP_GAP 3

 /* @============================================================
 * enumrate
@@ -122,6 +125,15 @@ void phydm_dynamic_tx_power_init(void *dm_void);
 void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output,
 			     u32 *_out_len);

+void phydm_rd_reg_pwr(void *dm_void, u32 *_used, char *output, u32 *_out_len);
+
+void phydm_wt_reg_pwr(void *dm_void, boolean is_ofst1, boolean pwr_ofst_en,
+            		     s8 pwr_ofst);
+
+void phydm_wt_ram_pwr(void *dm_void, u8 macid, boolean is_ofst1, 
+		             boolean pwr_ofst_en, s8 pwr_ofst);
+
+
 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 void odm_dynamic_tx_power_win(void *dm_void);
 #endif
--- a/hal/phydm/phydm_features.h
+++ b/hal/phydm/phydm_features.h
@@ -33,8 +33,12 @@
 						 ODM_RTL8821C | \
 						 ODM_RTL8822B | \
 						 ODM_RTL8721D | \
+						 ODM_RTL8723D | \
 						 ODM_RTL8710C)
 #define ODM_RECEIVER_BLOCKING_SUPPORT	(ODM_RTL8188E | ODM_RTL8192E)
+#define ODM_DYM_BW_INDICATION_SUPPORT	(ODM_RTL8821C | \
+					 ODM_RTL8822B | \
+					 ODM_RTL8822C)

 /*@20170103 YuChen add for FW API*/
 #define PHYDM_FW_API_ENABLE_8822B		1
@@ -53,6 +57,8 @@
 #define PHYDM_FW_API_FUNC_ENABLE_8812F 1
 #define PHYDM_FW_API_ENABLE_8197G 1
 #define PHYDM_FW_API_FUNC_ENABLE_8197G 1
+#define PHYDM_FW_API_ENABLE_8723F 1
+#define PHYDM_FW_API_FUNC_ENABLE_8723F 1

 #define CONFIG_POWERSAVING 0

--- a/hal/phydm/phydm_features_ap.h
+++ b/hal/phydm/phydm_features_ap.h
@@ -19,7 +19,7 @@
 #if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
 	RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
 	RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT ||\
-	RTL8197G_SUPPORT)
+	RTL8197G_SUPPORT || RTL8723F_SUPPORT)
 	#define PHYDM_LA_MODE_SUPPORT			1
 #else
 	#define PHYDM_LA_MODE_SUPPORT			0
@@ -30,9 +30,14 @@
 	#define DYN_ANT_WEIGHTING_SUPPORT
 #endif

-#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
+#if (RTL8822B_SUPPORT || RTL8198F_SUPPORT || RTL8814B_SUPPORT ||\
+     RTL8197G_SUPPORT || RTL8812F_SUPPORT || RTL8723F_SUPPORT)
 	#define FAHM_SUPPORT
 #endif
+
+#if (RTL8197G_SUPPORT || RTL8812F_SUPPORT || RTL8723F_SUPPORT)
+	#define IFS_CLM_SUPPORT
+#endif
 	#define NHM_SUPPORT
 	#define CLM_SUPPORT

@@ -45,7 +50,7 @@
 #endif

 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\
-	RTL8197G_SUPPORT)
+	RTL8197G_SUPPORT || RTL8723F_SUPPORT)
 	#define PHYDM_TDMA_DIG_SUPPORT 1
 	#ifdef PHYDM_TDMA_DIG_SUPPORT
 	#define IS_USE_NEW_TDMA /*new tdma dig test*/
@@ -76,12 +81,12 @@
 #endif

 #if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
-	RTL8812F_SUPPORT || RTL8197G_SUPPORT)
+	RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
 	#define PHYDM_PMAC_TX_SETTING_SUPPORT
 #endif

 #if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
-	RTL8812F_SUPPORT || RTL8197G_SUPPORT)
+	RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
 	#define PHYDM_MP_SUPPORT
 #endif

@@ -119,9 +124,18 @@
 	#define CONFIG_DIRECTIONAL_BF
 #endif

-#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
-#define CONFIG_DYNAMIC_TX_TWR
+#if (RTL8197G_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT)
+	#define CONFIG_DYNAMIC_TX_TWR
 #endif
+
+#if (RTL8197G_SUPPORT || RTL8812F_SUPPORT)
+	#define PHYDM_HW_IGI
+#endif
+
+#if (RTL8197G_SUPPORT || RTL8812F_SUPPORT)
+	#define CONFIG_DYNAMIC_TXCOLLISION_TH
+#endif
+
 /*#define	CONFIG_PSD_TOOL*/
 #define PHYDM_SUPPORT_CCKPD
 #define PHYDM_SUPPORT_ADAPTIVITY
@@ -143,7 +157,7 @@
 	#endif
 #endif

-#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) || defined(CONFIG_RTL_8197F_ANT_SWITCH)
+#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) || defined(CONFIG_RTL_8197F_ANT_SWITCH) || defined(CONFIG_RTL_8197G_ANT_SWITCH)
 	#define CONFIG_PHYDM_ANTENNA_DIVERSITY
 	#define ODM_EVM_ENHANCE_ANTDIV
 	/*#define SKIP_EVM_ANTDIV_TRAINING_PATCH*/
@@ -157,6 +171,15 @@
 		#define CONFIG_2G_CG_TRX_DIVERSITY
 	#endif

+	/*----------*/
+	#ifdef CONFIG_NO_2G_DIVERSITY_8197G
+		#define CONFIG_NO_2G_DIVERSITY
+	#elif defined(CONFIG_2G_CGCS_RX_DIVERSITY_8197G)
+		#define CONFIG_2G_CGCS_RX_DIVERSITY
+	#elif defined(CONFIG_2G_CG_TRX_DIVERSITY_8197G)
+		#define CONFIG_2G_CG_TRX_DIVERSITY
+	#endif
+
 	#if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
 		#define CONFIG_NO_2G_DIVERSITY
 	#endif
--- a/hal/phydm/phydm_features_ce.h
+++ b/hal/phydm/phydm_features_ce.h
@@ -28,7 +28,7 @@

 #if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
 	RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
-	RTL8822C_SUPPORT)
+	RTL8822C_SUPPORT || RTL8723F_SUPPORT)
 	#define PHYDM_LA_MODE_SUPPORT			1
 #else
 	#define PHYDM_LA_MODE_SUPPORT			0
@@ -39,9 +39,14 @@
 	#define DYN_ANT_WEIGHTING_SUPPORT
 #endif

-#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8822C_SUPPORT ||\
+	RTL8814B_SUPPORT || RTL8723F_SUPPORT)
 	#define FAHM_SUPPORT
 #endif
+
+#if (RTL8822C_SUPPORT || RTL8723F_SUPPORT)
+	#define IFS_CLM_SUPPORT
+#endif
 	#define NHM_SUPPORT
 	#define CLM_SUPPORT

@@ -56,7 +61,7 @@
 /*@#define PHYDM_TDMA_DIG_SUPPORT*/

 #if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8821C_SUPPORT ||\
-	RTL8822C_SUPPORT || RTL8723D_SUPPORT)
+	RTL8822C_SUPPORT || RTL8723D_SUPPORT )
 	#ifdef CONFIG_TDMADIG
 	#define PHYDM_TDMA_DIG_SUPPORT
 	#ifdef PHYDM_TDMA_DIG_SUPPORT
@@ -90,15 +95,15 @@
 	#endif
 #endif

-#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT)
+#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8723D_SUPPORT)
 	#define PHYDM_POWER_TRAINING_SUPPORT
 #endif

-#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT)
+#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT)
 	#define PHYDM_PMAC_TX_SETTING_SUPPORT
 #endif

-#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT)
+#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT)
 	#define PHYDM_MP_SUPPORT
 #endif

@@ -127,6 +132,10 @@
 	#define	CONFIG_RECEIVER_BLOCKING
 #endif

+#if (RTL8821C_SUPPORT || RTL8822C_SUPPORT || RTL8822B_SUPPORT)
+	#define CONFIG_BW_INDICATION
+#endif
+
 #if (RTL8192F_SUPPORT)
 	/*#define	CONFIG_8912F_SPUR_CALIBRATION*/
 #endif
@@ -138,6 +147,9 @@
 #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
 #define CONFIG_DYNAMIC_TX_TWR
 #endif
+#if (RTL8822C_SUPPORT)
+#define PHYDM_HW_IGI
+#endif
 #define PHYDM_SUPPORT_CCKPD
 #define PHYDM_SUPPORT_ADAPTIVITY

@@ -149,7 +161,7 @@

 		#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT ||\
 		     RTL8188F_SUPPORT || RTL8821C_SUPPORT ||\
-		     RTL8723D_SUPPORT)
+		     RTL8723D_SUPPORT||RTL8723F_SUPPORT)
 			#define	CONFIG_S0S1_SW_ANTENNA_DIVERSITY
 		#endif

@@ -226,4 +238,8 @@
 	#define CONFIG_DIRECTIONAL_BF
 #endif

+#if (RTL8822C_SUPPORT)
+	#define CONFIG_MU_RSOML
+#endif
+
 #endif
--- a/hal/phydm/phydm_features_iot.h
+++ b/hal/phydm/phydm_features_iot.h
@@ -114,10 +114,14 @@
 	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY

 		#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT ||\
-		     RTL8188F_SUPPORT || RTL8821C_SUPPORT)
+		     RTL8188F_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT)
 			#define	CONFIG_S0S1_SW_ANTENNA_DIVERSITY
 		#endif
-
+		
+		#if (RTL8710C_SUPPORT)
+			//#define	CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+		#endif
+		
 		#if (RTL8821A_SUPPORT)
 			/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
 		#endif
@@ -150,7 +154,9 @@
 /*#define	CONFIG_PATH_DIVERSITY*/
 /*#define	CONFIG_RA_DYNAMIC_RTY_LIMIT*/
 //#define	CONFIG_BB_TXBF_API
+#if DBG
 #define	CONFIG_PHYDM_DEBUG_FUNCTION
+#endif

 #ifdef CONFIG_BT_COEXIST
 	#define	ODM_CONFIG_BT_COEXIST
--- a/hal/phydm/phydm_features_win.h
+++ b/hal/phydm/phydm_features_win.h
@@ -18,7 +18,7 @@

 #if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
 	RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
-	RTL8822C_SUPPORT || RTL8814B_SUPPORT)
+	RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT)
 	#define PHYDM_LA_MODE_SUPPORT			1
 #else
 	#define PHYDM_LA_MODE_SUPPORT			0
@@ -29,9 +29,14 @@
 	#define DYN_ANT_WEIGHTING_SUPPORT
 #endif

-#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8822C_SUPPORT ||\
+     RTL8814B_SUPPORT || RTL8723F_SUPPORT)
 	#define FAHM_SUPPORT
 #endif
+
+#if (RTL8822C_SUPPORT || RTL8723F_SUPPORT)
+	#define IFS_CLM_SUPPORT
+#endif
 	#define NHM_SUPPORT
 	#define CLM_SUPPORT

@@ -40,7 +45,7 @@
 #endif

 #if (RTL8822C_SUPPORT)
-	/*#define PHYDM_PHYSTAUS_AUTO_SWITCH*/
+	#define PHYDM_PHYSTAUS_AUTO_SWITCH
 #endif

 /*#define PHYDM_TDMA_DIG_SUPPORT*/
@@ -75,11 +80,11 @@
 	#define	PHYDM_POWER_TRAINING_SUPPORT
 #endif

-#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT)
+#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT)
 	#define	PHYDM_PMAC_TX_SETTING_SUPPORT
 #endif

-#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT)
+#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT)
 	#define	PHYDM_MP_SUPPORT
 #endif

@@ -156,6 +161,10 @@
 	#define	CONFIG_RECEIVER_BLOCKING
 #endif

+#if (RTL8821C_SUPPORT || RTL8822C_SUPPORT || RTL8822B_SUPPORT)
+	#define CONFIG_BW_INDICATION
+#endif
+
 #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
 	RTL8192E_SUPPORT || RTL8723B_SUPPORT)
 	#define	CONFIG_RA_FW_DBG_CODE
@@ -164,9 +173,15 @@
 /* #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR */
 #define CONFIG_DYNAMIC_TX_TWR
 /* #endif */
+#if (RTL8822C_SUPPORT)
+#define PHYDM_HW_IGI
+#endif
 #define	CONFIG_PSD_TOOL
 #define PHYDM_SUPPORT_ADAPTIVITY
 #define	PHYDM_SUPPORT_CCKPD
+#if (defined(PHYDM_SUPPORT_CCKPD) && RTL8822C_SUPPORT)
+	#define PHYDM_DCC_ENHANCE
+#endif
 /*#define	CONFIG_RA_DYNAMIC_RTY_LIMIT*/
 #define CONFIG_ANT_DETECTION
 #define	CONFIG_BB_TXBF_API
--- a/hal/phydm/phydm_hwconfig.c
+++ b/hal/phydm/phydm_hwconfig.c
@@ -251,8 +251,8 @@ odm_config_rf_with_header_file(struct dm_struct *dm,
 				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type17);
 			else if (dm->rfe_type == 18)
 				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type18);
-			else if (dm->rfe_type == 19)
-				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type19);
+			//else if (dm->rfe_type == 19)
+				//READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type19);
 			else
 				READ_AND_CONFIG_MP(8822b, _txpwr_lmt);
 		}
@@ -428,10 +428,25 @@ odm_config_rf_with_header_file(struct dm_struct *dm,
 			else if (e_rf_path == RF_PATH_B)
 				READ_AND_CONFIG_MP(8822c, _radiob);
 		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
-			READ_AND_CONFIG_MP(8822c, _txpwr_lmt);
+			if (dm->rfe_type == 5)
+				READ_AND_CONFIG_MP(8822c, _txpwr_lmt_type5);
+			else
+				READ_AND_CONFIG_MP(8822c, _txpwr_lmt);
 		}
 	}
 #endif
+#if (RTL8723F_SUPPORT)
+		if (dm->support_ic_type == ODM_RTL8723F) {
+			if (config_type == CONFIG_RF_RADIO) {
+				if (e_rf_path == RF_PATH_A)
+					READ_AND_CONFIG_MP(8723f, _radioa);
+				else if (e_rf_path == RF_PATH_B)
+					READ_AND_CONFIG_MP(8723f, _radiob);
+			} else if (config_type == CONFIG_RF_TXPWR_LMT) {
+				READ_AND_CONFIG_MP(8723f, _txpwr_lmt);
+			}
+		}
+#endif
 #if (RTL8812F_SUPPORT)
 	if (dm->support_ic_type == ODM_RTL8812F) {
 		if (config_type == CONFIG_RF_RADIO) {
@@ -665,8 +680,8 @@ odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm)
 			READ_AND_CONFIG_MP(8822b, _txpowertrack_type17);
 		else if (dm->rfe_type == 18)
 			READ_AND_CONFIG_MP(8822b, _txpowertrack_type18);
-		else if (dm->rfe_type == 19)
-			READ_AND_CONFIG_MP(8822b, _txpowertrack_type19);
+		//else if (dm->rfe_type == 19)
+			//READ_AND_CONFIG_MP(8822b, _txpowertrack_type19);
 		else
 			READ_AND_CONFIG_MP(8822b, _txpowertrack);
 	}
@@ -807,8 +822,13 @@ odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm)

 #if RTL8195B_SUPPORT
 	if (dm->support_ic_type == ODM_RTL8195B) {
-		READ_AND_CONFIG_MP(8195b, _txpowertrack);
-		READ_AND_CONFIG_MP(8195b, _txxtaltrack);
+		if (dm->package_type == 1) {
+			READ_AND_CONFIG_MP(8195b, _txpowertrack_pkg1);
+			READ_AND_CONFIG_MP(8195b, _txxtaltrack_pkg1);
+		} else {
+			READ_AND_CONFIG_MP(8195b, _txpowertrack);
+			READ_AND_CONFIG_MP(8195b, _txxtaltrack);
+		}
 	}
 #endif

@@ -821,6 +841,15 @@ odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm)
 	}
 #endif

+#if (RTL8723F_SUPPORT)
+	if (dm->support_ic_type == ODM_RTL8723F) {
+		if (dm->en_tssi_mode)
+			READ_AND_CONFIG_MP(8723f, _txpowertracktssi);
+		else
+			READ_AND_CONFIG_MP(8723f, _txpowertrack);
+		READ_AND_CONFIG_MP(8723f, _txxtaltrack);
+	}
+#endif
 #if (RTL8812F_SUPPORT)
 	if (dm->support_ic_type == ODM_RTL8812F) {
 		if (dm->rfe_type == 0)
@@ -831,6 +860,10 @@ odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm)
 			READ_AND_CONFIG_MP(8812f, _txpowertrack_type2);
 		else if (dm->rfe_type == 3)
 			READ_AND_CONFIG_MP(8812f, _txpowertrack_type3);
+		else if (dm->rfe_type == 4)
+			READ_AND_CONFIG_MP(8812f, _txpowertrack_type4);
+		else if (dm->rfe_type == 5)
+			READ_AND_CONFIG_MP(8812f, _txpowertrack_type5);
 		else
 			READ_AND_CONFIG_MP(8812f, _txpowertrack);
 	}
@@ -1068,8 +1101,8 @@ odm_config_bb_with_header_file(struct dm_struct *dm,
 				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type17);
 			else if (dm->rfe_type == 18)
 				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type18);
-			else if (dm->rfe_type == 19)
-				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type19);
+			//else if (dm->rfe_type == 19)
+				//READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type19);
 			else
 				READ_AND_CONFIG_MP(8822b, _phy_reg_pg);
 		}
@@ -1228,12 +1261,18 @@ odm_config_bb_with_header_file(struct dm_struct *dm,
 #endif
 #if (RTL8195B_SUPPORT == 1)
 	if (dm->support_ic_type == ODM_RTL8195B) {
-		if (config_type == CONFIG_BB_PHY_REG)
+		if (config_type == CONFIG_BB_PHY_REG) {
 			READ_AND_CONFIG(8195b, _phy_reg);
-		else if (config_type == CONFIG_BB_AGC_TAB)
+		} else if (config_type == CONFIG_BB_AGC_TAB) {
 			READ_AND_CONFIG(8195b, _agc_tab);
-		else if (config_type == CONFIG_BB_PHY_REG_PG)
+		} else if (config_type == CONFIG_BB_PHY_REG_PG) {
 			READ_AND_CONFIG(8195b, _phy_reg_pg);
+		} else if (config_type == CONFIG_BB_PHY_REG_MP) {
+			if (dm->package_type == 1)
+				odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, 0x10);
+			else
+				odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, 0x12);
+		}
 	}
 #endif
 #if (RTL8198F_SUPPORT == 1)
@@ -1268,6 +1307,16 @@ odm_config_bb_with_header_file(struct dm_struct *dm,
 			READ_AND_CONFIG(8822c, _phy_reg_pg);
 	}
 #endif
+#if (RTL8723F_SUPPORT)
+		if (dm->support_ic_type == ODM_RTL8723F) {
+			if (config_type == CONFIG_BB_PHY_REG)
+				READ_AND_CONFIG_MP(8723f, _phy_reg);
+			else if (config_type == CONFIG_BB_AGC_TAB)
+				READ_AND_CONFIG_MP(8723f, _agc_tab);
+			else if (config_type == CONFIG_BB_PHY_REG_PG)
+				READ_AND_CONFIG(8723f, _phy_reg_pg);
+		}
+#endif
 #if (RTL8812F_SUPPORT)
 	if (dm->support_ic_type == ODM_RTL8812F) {
 		if (config_type == CONFIG_BB_PHY_REG)
@@ -1317,9 +1366,8 @@ odm_config_mac_with_header_file(struct dm_struct *dm)
 		  "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n",
 		  dm->support_platform, dm->support_interface, dm->board_type);

-#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT)
-	if (dm->support_ic_type &
-	    (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8814B)) {
+#ifdef PHYDM_IC_HALMAC_PARAM_SUPPORT
+	if (dm->support_ic_type & PHYDM_IC_SUPPORT_HALMAC_PARAM_OFFLOAD) {
 		PHYDM_DBG(dm, ODM_COMP_INIT, "MAC para-package in HALMAC\n");
 		return result;
 	}
@@ -1541,6 +1589,11 @@ u32 odm_get_hw_img_version(struct dm_struct *dm)
 		version = odm_get_version_mp_8197g_phy_reg();
 		break;
 #endif
+#if (RTL8723F_SUPPORT)
+	case ODM_RTL8723F:
+		version = odm_get_version_mp_8723f_phy_reg();
+		break;
+#endif
 #if (RTL8814B_SUPPORT)
 	case ODM_RTL8814B:
 		version = odm_get_version_mp_8814b_phy_reg();
--- a/hal/phydm/phydm_interface.c
+++ b/hal/phydm/phydm_interface.c
@@ -705,9 +705,6 @@ void odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
 	init_timer(timer);
 	timer->function = call_back_func;
 	timer->data = (unsigned long)dm;
-#if 0
-	/*@mod_timer(timer, jiffies+RTL_MILISECONDS_TO_JIFFIES(10));	*/
-#endif
 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
 	timer_setup(timer, call_back_func, 0);
 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
@@ -793,7 +790,7 @@ u8 phydm_trans_h2c_id(struct dm_struct *dm, u8 phydm_h2c_id)

 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
 #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/
-		if (dm->support_ic_type == ODM_RTL8881A || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type & PHYDM_IC_3081_SERIES)
+		if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8192F | PHYDM_IC_3081_SERIES))
 			platform_h2c_id = H2C_88XX_RSSI_REPORT;
 		else
 #endif
@@ -855,7 +852,7 @@ u8 phydm_trans_h2c_id(struct dm_struct *dm, u8 phydm_h2c_id)

 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
 #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/
-		if (dm->support_ic_type == ODM_RTL8881A || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type & PHYDM_IC_3081_SERIES)
+		if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8192F | PHYDM_IC_3081_SERIES))
 			platform_h2c_id = H2C_88XX_RA_PARA_ADJUST;
 		else
 #endif
@@ -906,7 +903,7 @@ u8 phydm_trans_h2c_id(struct dm_struct *dm, u8 phydm_h2c_id)

 #elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
 #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/
-		if (dm->support_ic_type == ODM_RTL8881A || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type & PHYDM_IC_3081_SERIES)
+		if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8192F | PHYDM_IC_3081_SERIES))
 			platform_h2c_id = H2C_88XX_FW_TRACE_EN;
 		else
 #endif
@@ -924,7 +921,8 @@ u8 phydm_trans_h2c_id(struct dm_struct *dm, u8 phydm_h2c_id)

 	case PHYDM_H2C_TXBF:
 #if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1))
-		platform_h2c_id = 0x41; /*@H2C_TxBF*/
+		if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812))
+			platform_h2c_id = 0x41; /*@H2C_TxBF*/
 #endif
 		break;

@@ -1272,7 +1270,7 @@ odm_dpk_by_fw(struct dm_struct *dm)
 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 	struct _ADAPTER *adapter = dm->adapter;

-	if (HAL_MAC_FWDPK_Trigger(&GET_HAL_MAC_INFO(adapter)) == 0)
+	if (hal_mac_fwdpk_trigger(&GET_HAL_MAC_INFO(adapter)) == 0)
 		dpk_result = HAL_STATUS_SUCCESS;
 #else
 	dpk_result = rtw_phydm_fw_dpk(dm);
@@ -1332,82 +1330,6 @@ void phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm)
 #endif
 }

-#if 0
-boolean
-phydm_get_txbf_en(
-	struct dm_struct		*dm,
-	u16							mac_id,
-	u8							i
-)
-{
-	boolean txbf_en = false;
-
-#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && !defined(DM_ODM_CE_MAC80211)
-
-#ifdef CONFIG_BEAMFORMING
-	enum beamforming_cap beamform_cap;
-	void *adapter = dm->adapter;
-	#ifdef PHYDM_BEAMFORMING_SUPPORT
-	beamform_cap =
-	phydm_beamforming_get_entry_beam_cap_by_mac_id(dm, mac_id);
-	#else/*@for drv beamforming*/
-	beamform_cap =
-	beamforming_get_entry_beam_cap_by_mac_id(&adapter->mlmepriv, mac_id);
-	#endif
-	if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU))
-		txbf_en = true;
-	else
-		txbf_en = false;
-#endif /*@#ifdef CONFIG_BEAMFORMING*/
-
-#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
-
-#ifdef PHYDM_BEAMFORMING_SUPPORT
-	u8 idx = 0xff;
-	boolean act_bfer = false;
-	BEAMFORMING_CAP beamform_cap = BEAMFORMING_CAP_NONE;
-	PRT_BEAMFORMING_ENTRY	entry = NULL;
-	struct rtl8192cd_priv *priv			= dm->priv;
-	#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-	struct _BF_DIV_COEX_	*dm_bdc_table = &dm->dm_bdc_table;
-
-	dm_bdc_table->num_txbfee_client = 0;
-	dm_bdc_table->num_txbfer_client = 0;
-	#endif
-#endif
-
-#ifdef PHYDM_BEAMFORMING_SUPPORT
-	beamform_cap = Beamforming_GetEntryBeamCapByMacId(priv, mac_id);
-	entry = Beamforming_GetEntryByMacId(priv, mac_id, &idx);
-	if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) {
-		if (entry->Sounding_En)
-			txbf_en = true;
-		else
-			txbf_en = false;
-		act_bfer = true;
-	}
-	#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*@BDC*/
-	if (act_bfer == true) {
-		dm_bdc_table->w_bfee_client[i] = true; /* @AP act as BFer */
-		dm_bdc_table->num_txbfee_client++;
-	} else
-		dm_bdc_table->w_bfee_client[i] = false; /* @AP act as BFer */
-
-	if (beamform_cap & (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP_VHT_SU)) {
-		dm_bdc_table->w_bfer_client[i] = true; /* @AP act as BFee */
-		dm_bdc_table->num_txbfer_client++;
-	} else
-		dm_bdc_table->w_bfer_client[i] = false; /* @AP act as BFer */
-
-	#endif
-#endif
-
-#endif
-	return txbf_en;
-}
-#endif
-
 void phydm_iqk_wait(struct dm_struct *dm, u32 timeout)
 {
 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
@@ -1518,6 +1440,33 @@ u8 phydm_get_tx_power_dbm(struct dm_struct *dm, u8 rf_path,
 	return tx_power_dbm;
 }

+s16 phydm_get_tx_power_mdbm(struct dm_struct *dm, u8 rf_path,
+					u8 rate, u8 bandwidth, u8 channel)
+{
+	s16 tx_power_dbm = 0;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+	struct _ADAPTER *adapter = dm->adapter;
+	tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValuemdBm(adapter, rf_path, rate, bandwidth, channel);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	tx_power_dbm = rtw_odm_get_tx_power_mbm(dm, rf_path, rate, bandwidth, channel);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValuembm(dm, rf_path, rate, bandwidth, channel);
+#endif
+	return tx_power_dbm;
+}
+
+u32 phydm_rfe_ctrl_gpio(struct dm_struct *dm, u8 gpio_num)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	return rtw_phydm_rfe_ctrl_gpio(dm->adapter, gpio_num);
+#endif
+	return 0;
+}
+
 u64 phydm_division64(u64 x, u64 y)
 {
 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
--- a/hal/phydm/phydm_interface.h
+++ b/hal/phydm/phydm_interface.h
@@ -48,6 +48,7 @@ enum phydm_h2c_cmd {
 	PHYDM_H2C_MCC			= 0x4f,
 	PHYDM_H2C_RESP_TX_PATH_CTRL	= 0x50,
 	PHYDM_H2C_RESP_TX_ANT_CTRL	= 0x51,
+	PHYDM_H2C_FW_DM_CTRL		= 0x55,
 	ODM_MAX_H2CCMD
 };

@@ -92,21 +93,6 @@ enum phydm_halmac_param {
 #define _bit_all(_name)			BIT_##_name
 #define _bit_ic(_name, _ic)		BIT_##_name##_ic

-/* @_cat: implemented by Token-Pasting Operator. */
-#if 0
-#define _cat(_name, _ic_type, _func) \
-	(                            \
-		_func##_all(_name))
-#endif
-
-#if 0
-
-#define ODM_REG_DIG_11N		0xC50
-#define ODM_REG_DIG_11AC	0xDDD
-
-ODM_REG(DIG,_pdm_odm)
-#endif
-
 #if defined(DM_ODM_CE_MAC80211)
 #define ODM_BIT(name, dm)				\
 	((dm->support_ic_type & ODM_IC_11N_SERIES) ?	\
@@ -322,15 +308,6 @@ void phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type);

 void phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm);

-#if 0
-boolean
-phydm_get_txbf_en(
-	struct dm_struct		*dm,
-	u16		mac_id,
-	u8		i
-);
-#endif
-
 void phydm_iqk_wait(struct dm_struct *dm, u32 timeout);
 u8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate);

@@ -340,6 +317,12 @@ void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *),
 u8 phydm_get_tx_rate(struct dm_struct *dm);
 u8 phydm_get_tx_power_dbm(struct dm_struct *dm, u8 rf_path,
 					u8 rate, u8 bandwidth, u8 channel);
+
+s16 phydm_get_tx_power_mdbm(struct dm_struct *dm, u8 rf_path,
+					u8 rate, u8 bandwidth, u8 channel);
+
+u32 phydm_rfe_ctrl_gpio(struct dm_struct *dm, u8 gpio_num);
+
 u64 phydm_division64(u64 x, u64 y);

 #endif /* @__ODM_INTERFACE_H__ */
--- a/hal/phydm/phydm_lna_sat.c
+++ b/hal/phydm/phydm_lna_sat.c
@@ -55,8 +55,7 @@ void phydm_lna_sat_chk_init(
 	lna_info->pre_timer_check_cnt = 0;

 	#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
-	if (dm->support_ic_type &
-	    (ODM_RTL8198F | ODM_RTL8814B))
+	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
 		phydm_lna_sat_chk_bb_init(dm);
 	#endif
 }
@@ -519,7 +518,7 @@ void phydm_lna_sat_chk_watchdog_type1(

 	u8 rssi_min = dm->rssi_min;

-	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n%s ==>\n", __func__);
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);

 	if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) {
 		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
@@ -540,13 +539,6 @@ void phydm_lna_sat_chk_watchdog_type1(
 		return;
 	}

-	if (!(dm->support_ic_type &
-	    (ODM_RTL8197F | ODM_RTL8198F | ODM_RTL8814B))) {
-		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-			  "support_ic_type not 97F/98F/14B, return\n");
-		return;
-	}
-
 	if (rssi_min == 0 || rssi_min == 0xff) {
 		/*@adapt agc table 0 */
 		phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0);
@@ -621,10 +613,6 @@ void phydm_snr_collect(
 	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;

 	if (pinfo->is_sm_done) {
-#if 0
-		/*PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);*/
-#endif
-
 		/* @adapt only path-A for calculation */
 		pinfo->snr_statistic[pinfo->cnt_snr_statistic] = rx_snr;

@@ -1160,16 +1148,365 @@ void phydm_lna_sat_type2_sm(
 		return;
 	}
 }
-
-
 #endif /*@#ifdef PHYDM_LNA_SAT_CHK_TYPE2*/

-void phydm_lna_sat_debug(
-	void *dm_void,
-	char input[][16],
-	u32 *_used,
-	char *output,
-	u32 *_out_len)
+#ifdef PHYDM_HW_SWITCH_AGC_TAB
+u32 phydm_get_lna_pd_reg(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 rf_pd_reg = RF_0x8b;
+
+#if (RTL8814B_SUPPORT)
+		if (dm->support_ic_type & ODM_RTL8814B) {
+			if (*dm->channel <= 14)
+				rf_pd_reg = RF_0x87;
+			else
+				rf_pd_reg = RF_0x8b;
+		}
+#endif
+	return rf_pd_reg;
+}
+
+u32 phydm_get_lna_pd_en_mask(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 rf_pd_en_msk = BIT(2);
+
+#if (RTL8814B_SUPPORT)
+		if (dm->support_ic_type & ODM_RTL8814B) {
+			if (*dm->channel <= 14)
+				rf_pd_en_msk = BIT(4);
+			else
+				rf_pd_en_msk = BIT(2);
+		}
+#endif
+	return rf_pd_en_msk;
+}
+
+boolean phydm_get_lna_pd_en(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 rf_pd_reg = RF_0x8b;
+	u32 rf_pd_en_msk = BIT(2);
+	u32 pd_en = 0;
+
+	rf_pd_reg = phydm_get_lna_pd_reg(dm);
+	rf_pd_en_msk = phydm_get_lna_pd_en_mask(dm);
+
+#if (RTL8814B_SUPPORT)
+		if (dm->support_ic_type & ODM_RTL8814B)
+			pd_en = config_phydm_read_rf_reg_8814b(dm, RF_PATH_A,
+							       rf_pd_reg,
+							       rf_pd_en_msk);
+#endif
+	return (boolean)pd_en;
+}
+
+void phydm_set_lna_pd_en(void *dm_void, boolean lna_pd_en)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	enum rf_path i = RF_PATH_A;
+	u32 rf_pd_reg = RF_0x8b;
+	u32 rf_pd_en_msk = BIT(2);
+
+	rf_pd_reg = phydm_get_lna_pd_reg(dm);
+	rf_pd_en_msk = phydm_get_lna_pd_en_mask(dm);
+
+#if (RTL8814B_SUPPORT)
+		if (dm->support_ic_type & ODM_RTL8814B)
+			for (i = RF_PATH_A; i < MAX_PATH_NUM_8814B; i++)
+				config_phydm_write_rf_reg_8814b(dm, i,
+								rf_pd_reg,
+								rf_pd_en_msk,
+								(u8)lna_pd_en);
+#endif
+}
+
+u32 phydm_get_lna_pd_th_mask(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 rf_pd_th_msk = 0x3;
+
+#if (RTL8814B_SUPPORT)
+		if (dm->support_ic_type & ODM_RTL8814B)
+			rf_pd_th_msk = 0x3;
+#endif
+	return rf_pd_th_msk;
+}
+
+enum lna_pd_th_level phydm_get_lna_pd_th_lv(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 rf_pd_reg = RF_0x8b;
+	u32 rf_pd_th_msk = 0x3;
+	u32 pd_th_lv = 0x0;
+
+	rf_pd_reg = phydm_get_lna_pd_reg(dm);
+	rf_pd_th_msk = phydm_get_lna_pd_th_mask(dm);
+
+#if (RTL8814B_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8814B)
+		pd_th_lv = config_phydm_read_rf_reg_8814b(dm, RF_PATH_A,
+							  rf_pd_reg,
+							  rf_pd_th_msk);
+#endif
+	return (enum lna_pd_th_level)pd_th_lv;
+}
+
+void phydm_set_lna_pd_th_lv(void *dm_void,
+			    enum lna_pd_th_level lna_pd_th_lv)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	enum rf_path i = RF_PATH_A;
+	u32 rf_pd_reg = RF_0x8b;
+	u32 rf_pd_th_msk = 0x3;
+
+	rf_pd_reg = phydm_get_lna_pd_reg(dm);
+	rf_pd_th_msk = phydm_get_lna_pd_th_mask(dm);
+
+#if (RTL8814B_SUPPORT)
+		if (dm->support_ic_type & ODM_RTL8814B)
+			for (i = RF_PATH_A; i < MAX_PATH_NUM_8814B; i++)
+				config_phydm_write_rf_reg_8814b(dm, i,
+								rf_pd_reg,
+								rf_pd_th_msk,
+								lna_pd_th_lv);
+#endif
+}
+
+u32 phydm_get_sat_agc_tab_version(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+#if (RTL8814B_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8814B)
+		return odm_get_version_mp_8814b_extra_agc_tab();
+#endif
+	return 0;
+}
+
+boolean phydm_get_auto_agc_config(void *dm_void,
+				  enum agc_tab_switch_state state_sel)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 state_en = 0;
+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	switch (state_sel) {
+	case AGC_SWH_IDLE:
+		state_en = odm_get_bb_reg(dm, R_0x18ac, BIT(16));
+		break;
+	case AGC_SWH_OFDM:
+		state_en = odm_get_bb_reg(dm, R_0x18ac, BIT(17));
+		break;
+	case AGC_SWH_CCK:
+		state_en = odm_get_bb_reg(dm, R_0x18ac, BIT(18));
+		break;
+	default:
+		state_en = 0;
+		break;
+	}
+#endif
+	return (boolean)state_en;
+}
+
+boolean phydm_is_auto_agc_on(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	boolean state_on = false;
+
+	state_on = ((phydm_get_auto_agc_config(dm, AGC_SWH_IDLE) ||
+		     phydm_get_auto_agc_config(dm, AGC_SWH_CCK) ||
+		     phydm_get_auto_agc_config(dm, AGC_SWH_OFDM)) &&
+		     phydm_get_lna_pd_en(dm));
+
+	return state_on;
+}
+
+void phydm_config_auto_agc(void *dm_void,
+			   boolean idle_en,
+			   boolean cck_cca_en,
+			   boolean ofdm_cca_en)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	u32 hwagc_opt = 0;
+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+	if (dm->support_ic_type & ~ODM_RTL8814B)
+		return;
+
+	if (idle_en)
+		hwagc_opt |= BIT(0);
+	else
+		hwagc_opt &= ~BIT(0);
+	if (ofdm_cca_en)
+		hwagc_opt |= BIT(1);
+	else
+		hwagc_opt &= ~BIT(1);
+	if (cck_cca_en)
+		hwagc_opt |= BIT(2);
+	else
+		hwagc_opt &= ~BIT(2);
+
+	odm_set_bb_reg(dm, R_0x18ac, BIT(18) | BIT(17) | BIT(16), hwagc_opt);
+#ifdef PHYDM_COMPILE_ABOVE_2SS
+	odm_set_bb_reg(dm, R_0x41ac, BIT(18) | BIT(17) | BIT(16), hwagc_opt);
+#endif
+#ifdef PHYDM_COMPILE_ABOVE_3SS
+	odm_set_bb_reg(dm, R_0x52ac, BIT(18) | BIT(17) | BIT(16), hwagc_opt);
+#endif
+#ifdef PHYDM_COMPILE_ABOVE_4SS
+	odm_set_bb_reg(dm, R_0x53ac, BIT(18) | BIT(17) | BIT(16), hwagc_opt);
+#endif
+#endif
+}
+
+void phydm_auto_agc_tab_reset(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	phydm_set_lna_pd_th_lv(dm, 0x0);
+	phydm_config_auto_agc(dm, true, false, true);
+	phydm_set_lna_pd_en(dm, true);
+}
+
+void phydm_auto_agc_tab_off(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	phydm_config_auto_agc(dm, false, false, false);
+	phydm_set_lna_pd_en(dm, false);
+}
+
+void phydm_switch_sat_agc_by_band(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*lna_sat = &dm->dm_lna_sat_info;
+
+#if (RTL8814B_SUPPORT)
+	if (dm->support_ic_type & ODM_RTL8814B)
+		odm_config_mp_8814b_extra_agc_tab(dm, lna_sat->cur_rf_band);
+#endif
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	pr_debug("%s ==> switch to band%d\n", __func__, lna_sat->cur_rf_band);
+#else
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==> switch to band%d\n",
+		  __func__, lna_sat->cur_rf_band);
+#endif
+}
+
+void phydm_auto_agc_tab_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*lna_sat = &dm->dm_lna_sat_info;
+	u8 channel = *dm->channel;
+
+	lna_sat->cur_rf_band = phydm_ch_to_rf_band(dm, channel);
+	phydm_switch_sat_agc_by_band(dm);
+
+	if ((dm->support_ability & ODM_BB_LNA_SAT_CHK)) {
+		phydm_auto_agc_tab_reset(dm);
+		lna_sat->hw_swh_tab_on = true;
+	} else {
+		phydm_auto_agc_tab_off(dm);
+		lna_sat->hw_swh_tab_on = false;
+	}
+}
+
+void phydm_auto_agc_tab_watchdog(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*lna_sat = &dm->dm_lna_sat_info;
+	boolean hw_swh_on = false;
+
+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
+
+	if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) {
+		if (lna_sat->hw_swh_tab_on) {
+			phydm_auto_agc_tab_off(dm);
+			lna_sat->hw_swh_tab_on = false;
+		}
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "Disabled LNA sat. check\n");
+		return;
+	}
+
+	if (!lna_sat->hw_swh_tab_on)
+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
+			  "[WARNING] HW switch AGC Tab not fully enabled\n");
+}
+
+void phydm_auto_agc_tab_debug(void *dm_void, char input[][16], u32 *_used,
+			      char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_lna_sat_t	*lna_sat = &dm->dm_lna_sat_info;
+	char help[] = "-h";
+	u32 var1[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u8 i;
+	u8 agc_tab = 0;
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "LNA sat. AGC Tab version : %d\n",
+			 phydm_get_sat_agc_tab_version(dm));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Enable LNA peak detector : {0} {lna_pd_en = %d}\n",
+			 phydm_get_lna_pd_en(dm));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Set LNA peak detector lv : {1} {lna_pd_th_lv = %d}\n",
+			 phydm_get_lna_pd_th_lv(dm));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Config hw switch AGC tab : {2} {hw_swh_en_rx_idle} {hw_swh_en_cck_cca} {hw_swh_en_ofdm_cca} = (%d, %d, %d)\n",
+			 phydm_get_auto_agc_config(dm, AGC_SWH_IDLE),
+			 phydm_get_auto_agc_config(dm, AGC_SWH_CCK),
+			 phydm_get_auto_agc_config(dm, AGC_SWH_OFDM));
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Reset to default setting : {3}\n",
+			 phydm_get_auto_agc_config(dm, AGC_SWH_IDLE),
+			 phydm_get_auto_agc_config(dm, AGC_SWH_CCK),
+			 phydm_get_auto_agc_config(dm, AGC_SWH_OFDM));
+
+	} else {
+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
+		for (i = 1; i < 10; i++) {
+			if (input[i + 1])
+				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
+					     &var1[i]);
+		}
+		
+		if (var1[0] == 0) {
+			phydm_set_lna_pd_en(dm, (boolean)var1[1]);
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "set lna_pd_en = %d\n",
+				 (u8)phydm_get_lna_pd_en(dm));
+		} else if (var1[0] == 1) {
+			phydm_set_lna_pd_th_lv(dm, (u8)var1[1]);
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "set lna_pd_th_lv = %d\n",
+				 phydm_get_lna_pd_th_lv(dm));
+		}  else if (var1[0] == 2) {
+			phydm_config_auto_agc(dm, (boolean)var1[1],
+					      (boolean)var1[2],
+					      (boolean)var1[3]);
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "set hw switch agc tab en: (rx_idle, cck_cca, ofdm_cca) = (%d, %d, %d)\n",
+				 phydm_get_auto_agc_config(dm, AGC_SWH_IDLE),
+				 phydm_get_auto_agc_config(dm, AGC_SWH_CCK),
+				 phydm_get_auto_agc_config(dm, AGC_SWH_OFDM));
+		}  else if (var1[0] == 3) {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "reset to default settings\n");
+			phydm_auto_agc_tab_reset(dm);
+		}
+		lna_sat->hw_swh_tab_on = phydm_is_auto_agc_on(dm);
+	}
+	*_used = used;
+	*_out_len = out_len;
+}
+#endif /*@#ifdef PHYDM_HW_SWITCH_AGC_TAB*/
+
+void phydm_lna_sat_debug(void *dm_void,	char input[][16], u32 *_used,
+			 char *output, u32 *_out_len)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	struct phydm_lna_sat_t	*lna_t = &dm->dm_lna_sat_info;
@@ -1264,8 +1601,7 @@ void phydm_lna_sat_debug(
 	*_out_len = out_len;
 }

-void phydm_lna_sat_chk_watchdog(
-	void *dm_void)
+void phydm_lna_sat_chk_watchdog(void *dm_void)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	struct phydm_lna_sat_t *lna_sat = &dm->dm_lna_sat_info;
@@ -1273,29 +1609,40 @@ void phydm_lna_sat_chk_watchdog(
 	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);

 	if (lna_sat->lna_sat_type == LNA_SAT_WITH_PEAK_DET) {
+		#ifdef PHYDM_HW_SWITCH_AGC_TAB
+		if (dm->support_ic_type & ODM_RTL8814B) {
+			phydm_auto_agc_tab_watchdog(dm);
+			return;
+		}
+		#endif
 		#ifdef PHYDM_LNA_SAT_CHK_TYPE1
-		phydm_lna_sat_chk_watchdog_type1(dm);
+		if (dm->support_ic_type &
+		    (ODM_RTL8197F | ODM_RTL8198F | ODM_RTL8814B)) {
+			phydm_lna_sat_chk_watchdog_type1(dm);
+			return;
+		}
 		#endif
 	} else if (lna_sat->lna_sat_type == LNA_SAT_WITH_TRAIN) {
 		#ifdef PHYDM_LNA_SAT_CHK_TYPE2
-
+		return;
 		#endif
 	}

+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "support_ic_type match fail, return\n");
 }

-void phydm_lna_sat_config(
-	void *dm_void)
+void phydm_lna_sat_config(void *dm_void)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	struct phydm_lna_sat_t	*lna_sat = &dm->dm_lna_sat_info;

+	lna_sat->lna_sat_type = 0;
 	#if (RTL8822B_SUPPORT == 1)
 	if (dm->support_ic_type & (ODM_RTL8822B))
 		lna_sat->lna_sat_type = LNA_SAT_WITH_TRAIN;
 	#endif

-	#if (RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\
+	#if (RTL8197F_SUPPORT || RTL8192F_SUPPORT || \
 	     RTL8198F_SUPPORT || RTL8814B_SUPPORT)
 	if (dm->support_ic_type &
 	    (ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8198F | ODM_RTL8814B))
@@ -1306,15 +1653,11 @@ void phydm_lna_sat_config(
 		  __func__, lna_sat->lna_sat_type);
 }

-void phydm_lna_sat_check_init(
-	void *dm_void)
+void phydm_lna_sat_check_init(void *dm_void)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	struct phydm_lna_sat_t	*lna_sat = &dm->dm_lna_sat_info;

-	if ((dm->support_ability & ODM_BB_LNA_SAT_CHK))
-		return;
-
 	/*@2018.04.17 Johnson*/
 	phydm_lna_sat_config(dm);
 	#ifdef PHYDM_LNA_SAT_CHK_TYPE1
@@ -1326,6 +1669,12 @@ void phydm_lna_sat_check_init(
 	/*@2018.04.17 Johnson end*/

 	if (lna_sat->lna_sat_type == LNA_SAT_WITH_PEAK_DET) {
+		#ifdef PHYDM_HW_SWITCH_AGC_TAB
+		if (dm->support_ic_type & ODM_RTL8814B) {
+			phydm_auto_agc_tab_init(dm);
+			return;
+		}
+		#endif
 		#ifdef PHYDM_LNA_SAT_CHK_TYPE1
 		phydm_lna_sat_chk_init(dm);
 		#endif
--- a/hal/phydm/phydm_lna_sat.h
+++ b/hal/phydm/phydm_lna_sat.h
@@ -31,7 +31,7 @@
 * 1 ============================================================
 */

-#define LNA_SAT_VERSION "1.0"
+#define LNA_SAT_VERSION "1.1"

 /*@LNA saturation check*/
 #define	OFDM_AGC_TAB_0			0
@@ -77,6 +77,21 @@ enum lna_sat_type {
 	LNA_SAT_WITH_TRAIN	= 2,	/*type2*/
 };

+#ifdef PHYDM_HW_SWITCH_AGC_TAB
+enum lna_pd_th_level {
+	LNA_PD_TH_LEVEL0	= 0,
+	LNA_PD_TH_LEVEL1	= 1,
+	LNA_PD_TH_LEVEL2	= 2,
+	LNA_PD_TH_LEVEL3	= 3
+};
+
+enum agc_tab_switch_state {
+	AGC_SWH_IDLE,
+	AGC_SWH_CCK,
+	AGC_SWH_OFDM
+};
+#endif
+
 /* @1 ============================================================
 * 1  structure
 * 1 ============================================================
@@ -130,6 +145,10 @@ struct phydm_lna_sat_t {
 	u32			check_time;
 	boolean			pre_sat_status;
 	boolean			cur_sat_status;
+#ifdef PHYDM_HW_SWITCH_AGC_TAB
+	boolean			hw_swh_tab_on;
+	enum odm_rf_band	cur_rf_band;
+#endif
 	struct phydm_timer_list	phydm_lna_sat_chk_timer;
 	u32			cur_timer_check_cnt;
 	u32			pre_timer_check_cnt;
@@ -169,5 +188,9 @@ void phydm_lna_sat_chk_watchdog(void *dm_void);

 void phydm_lna_sat_check_init(void *dm_void);

+#ifdef PHYDM_HW_SWITCH_AGC_TAB
+void phydm_auto_agc_tab_debug(void *dm_void, char input[][16], u32 *_used,
+			      char *output, u32 *_out_len);
+#endif
 #endif /*@#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/
 #endif
--- a/hal/phydm/phydm_math_lib.c
+++ b/hal/phydm/phydm_math_lib.c
@@ -159,22 +159,28 @@ u32 odm_convert_to_db(u64 value)
 			break;
 	}

+	/*special cases*/
 	if (j == 0 && i == 0)
 		goto end;

+	if (i == 3 && j == 0) {
+		if (db_invert_table[3][0] - value >
+		    value - (db_invert_table[2][7] >> FRAC_BITS)) {
+			i = 2;
+			j = 7;
+		}
+		goto end;
+	}
+
+	if (i < 3)
+		value = value << FRAC_BITS; /*@elements of row 0~2 shift left*/
+
+	/*compare difference to get precise dB*/
 	if (j == 0) {
-		if (i != 3) {
-			if (db_invert_table[i][0] - value >
-			    value - db_invert_table[i - 1][7]) {
-				i = i - 1;
-				j = 7;
-			}
-		} else {
-			if (db_invert_table[3][0] - value >
-			    value - db_invert_table[2][7]) {
-				i = 2;
-				j = 7;
-			}
+		if (db_invert_table[i][j] - value >
+		    value - db_invert_table[i - 1][7]) {
+			i = i - 1;
+			j = 7;
 		}
 	} else {
 		if (db_invert_table[i][j] - value >
--- a/hal/phydm/phydm_mp.c
+++ b/hal/phydm/phydm_mp.c
@@ -40,6 +40,8 @@ void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
 	struct phydm_mp *mp = &dm->dm_mp_table;
 	u8 start = RF_PATH_A, end = RF_PATH_A;
 	u8 i = 0;
+	u8 central_ch = 0;
+	boolean is_2g_ch = false;

 	switch (path) {
 	case RF_PATH_A:
@@ -53,7 +55,7 @@ void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
 		start = RF_PATH_A;
 		end = RF_PATH_B;
 		break;
-#if (RTL8814B_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
+#if (defined(PHYDM_COMPILE_IC_4SS))
 	case RF_PATH_AC:
 		start = RF_PATH_A;
 		end = RF_PATH_C;
@@ -96,62 +98,115 @@ void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
 		break;
 #endif
 	}
+
+	central_ch = (u8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, 0xff);
+	is_2g_ch = (central_ch <= 14) ? true : false;
+
 	if (is_single_tone) {
-		mp->rf_reg0 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, 0xfffff);
-#if 0
-		mp->rfe_sel_a_0 = odm_get_bb_reg(dm, R_0x1840, MASKDWORD);
-		mp->rfe_sel_b_0 = odm_get_bb_reg(dm, R_0x4140, MASKDWORD);
-		mp->rfe_sel_c_0 = odm_get_bb_reg(dm, R_0x5240, MASKDWORD);
-		mp->rfe_sel_d_0 = odm_get_bb_reg(dm, R_0x5340, MASKDWORD);
-		mp->rfe_sel_a_1 = odm_get_bb_reg(dm, R_0x1844, MASKDWORD);
-		mp->rfe_sel_b_1 = odm_get_bb_reg(dm, R_0x4144, MASKDWORD);
-		mp->rfe_sel_c_1 = odm_get_bb_reg(dm, R_0x5244, MASKDWORD);
-		mp->rfe_sel_d_1 = odm_get_bb_reg(dm, R_0x5344, MASKDWORD);
-#endif
-		/* Disable CCK and OFDM */
-		odm_set_bb_reg(dm, R_0x1c3c, 0x3, 0x0);
-		for (i = start; i <= end; i++) {
-			/* @Tx mode: RF0x00[19:16]=4'b0010 */
-			odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);
-			/* @Lowest RF gain index: RF_0x0[4:0] = 0*/
-			odm_set_rf_reg(dm, i, RF_0x0, 0x1F, 0x0);
-			/* @RF LO enabled */
-			odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
+		/*Disable CCA*/
+		if (is_2g_ch) { /*CCK RxIQ weighting = [0,0]*/
+			if(dm->support_ic_type & ODM_RTL8723F) {
+				odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x1); /*CCK*/
+			} else {
+				odm_set_bb_reg(dm, R_0x1a9c, BIT(20), 0x0);
+				odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
+			}
 		}
+		odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x1ff); /*OFDM*/
+		if (dm->support_ic_type & ODM_RTL8723F) {
+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x5, BIT(0), 0x0);
+			for (i = start; i <= end; i++) {
+				mp->rf0[i] = odm_get_rf_reg(dm, i, RF_0x0, RFREG_MASK);
+				/*Tx mode: RF0x00[19:16]=4'b0010 */
+				odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);
+				/*Lowest RF gain index: RF_0x1[5:0] TX power*/
+				mp->rf1[i] = odm_get_rf_reg(dm, i, RF_0x1, RFREG_MASK);
+				odm_set_rf_reg(dm, i, RF_0x1, 0x3f, 0x0);//TX power
+				/*RF LO enabled */
+				odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
+			}
+		} else {
+			for (i = start; i <= end; i++) {
+				mp->rf0[i] = odm_get_rf_reg(dm, i, RF_0x0, RFREG_MASK);
+				/*Tx mode: RF0x00[19:16]=4'b0010 */
+				odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);
+				/*Lowest RF gain index: RF_0x0[4:0] = 0*/
+				odm_set_rf_reg(dm, i, RF_0x0, 0x1f, 0x0);
+				/*RF LO enabled */
+				odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
+			}
+		}
+		
 		#if (RTL8814B_SUPPORT)
 		if (dm->support_ic_type & ODM_RTL8814B) {
-			/* @Tx mode: RF0x00[19:16]=4'b0010 */
+			mp->rf0_syn[RF_SYN0] = config_phydm_read_syn_reg_8814b(
+					       dm, RF_SYN0, RF_0x0, RFREG_MASK);
+			/*Lowest RF gain index: RF_0x0[4:0] = 0x0*/
 			config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
-							0xF0000, 0x2);
-			/* @Lowest RF gain index: RF_0x0[4:0] = 0*/
-			config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
-							0x1F, 0x0);
-			/* @RF LO enabled */
+							0x1f, 0x0);
+			/*RF LO enabled */
 			config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
 							BIT(1), 0x1);
+			/*SYN1*/
+			if (*dm->band_width == CHANNEL_WIDTH_80_80) {
+				mp->rf0_syn[RF_SYN1] = config_phydm_read_syn_reg_8814b(
+						       dm, RF_SYN1, RF_0x0,
+						       RFREG_MASK);
+				config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
+								RF_0x0, 0x1f,
+								0x0);
+				config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
+								RF_0x58, BIT(1),
+								0x1);
+			}
 		}
 		#endif
 	} else {
-		/* Eable CCK and OFDM */
-		odm_set_bb_reg(dm, R_0x1c3c, 0x3, 0x3);
-		if (!(dm->support_ic_type & ODM_RTL8814B)) {
+		/*Enable CCA*/
+		if (is_2g_ch) { /*CCK RxIQ weighting = [1,1]*/
+			if(dm->support_ic_type & ODM_RTL8723F) {
+				odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x0); /*CCK*/ 
+			} else {
+				odm_set_bb_reg(dm, R_0x1a9c, BIT(20), 0x1);
+				odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
+			}
+		}
+		odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x0); /*OFDM*/
+
+		if(dm->support_ic_type & ODM_RTL8723F) {
 			for (i = start; i <= end; i++) {
-				odm_set_rf_reg(dm, i, RF_0x00, 0xfffff,
-					       mp->rf_reg0);
-				/* RF LO disabled */
+				odm_set_rf_reg(dm, i, RF_0x0, RFREG_MASK, mp->rf0[i]);
+				odm_set_rf_reg(dm, i, RF_0x1, RFREG_MASK, mp->rf1[i]);
+				/*RF LO disabled */
+				odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
+			}
+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x5, BIT(0), 0x1);
+		} else {
+			for (i = start; i <= end; i++) {
+				odm_set_rf_reg(dm, i, RF_0x0, RFREG_MASK, mp->rf0[i]);
+				/*RF LO disabled */
 				odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
 			}
 		}
-#if 0
-		odm_set_bb_reg(dm, R_0x1840, MASKDWORD, mp->rfe_sel_a_0);
-		odm_set_bb_reg(dm, R_0x4140, MASKDWORD, mp->rfe_sel_b_0);
-		odm_set_bb_reg(dm, R_0x5240, MASKDWORD, mp->rfe_sel_c_0);
-		odm_set_bb_reg(dm, R_0x5340, MASKDWORD, mp->rfe_sel_d_0);
-		odm_set_bb_reg(dm, R_0x1844, MASKDWORD, mp->rfe_sel_a_1);
-		odm_set_bb_reg(dm, R_0x4144, MASKDWORD, mp->rfe_sel_b_1);
-		odm_set_bb_reg(dm, R_0x5244, MASKDWORD, mp->rfe_sel_c_1);
-		odm_set_bb_reg(dm, R_0x5344, MASKDWORD, mp->rfe_sel_d_1);
-#endif
+		#if (RTL8814B_SUPPORT)
+		if (dm->support_ic_type & ODM_RTL8814B) {
+			config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
+							RFREG_MASK,
+							mp->rf0_syn[RF_SYN0]);
+			config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
+							BIT(1), 0x0);
+			/*SYN1*/
+			if (*dm->band_width == CHANNEL_WIDTH_80_80) {
+				config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
+								RF_0x0,
+								RFREG_MASK,
+								mp->rf0_syn[RF_SYN1]);
+				config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
+								RF_0x58, BIT(1),
+								0x0);
+			}
+		}
+		#endif
 	}
 }

@@ -163,34 +218,140 @@ void phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp,

 	if (is_carrier_supp) {
 		if (phydm_is_cck_rate(dm, (u8)rate_index)) {
-			/* @if CCK block on? */
+			/*if CCK block on? */
 			if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
 				odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1);

-			/* @Turn Off All Test mode */
-			odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
-
-			/* @transmit mode */
-			odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2);
-			/* @turn off scramble setting */
-			odm_set_bb_reg(dm, R_0x1a00, 0x8, 0x0);
-			/* @Set CCK Tx Test Rate, set FTxRate to 1Mbps */
-			odm_set_bb_reg(dm, R_0x1a00, 0x3000, 0x0);
+			if(dm->support_ic_type & ODM_RTL8723F){
+				/* @Carrier suppress tx */
+				odm_set_bb_reg(dm, R_0x2a08, BIT(18), 0x1);
+				/*turn off scramble setting */
+				odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x1);
+				/*Set CCK Tx Test Rate, set TxRate to 2Mbps */
+				odm_set_bb_reg(dm, R_0x2a08, 0x300000, 0x1);
+				/* BB and PMAC cont tx */
+				odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x1);
+				odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x1);
+				/* TX CCK ON */
+				odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0);
+				odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1);
+			}
+			else {
+				/*Turn Off All Test mode */
+				odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
+				
+				/*transmit mode */
+				odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2);	
+				/*turn off scramble setting */
+				odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x0);
+				/*Set CCK Tx Test Rate, set TxRate to 1Mbps */
+				odm_set_bb_reg(dm, R_0x1a00, 0x3000, 0x0);
+			}
 		}
-	} else { /* @Stop Carrier Suppression. */
+	} else { /*Stop Carrier Suppression. */
 		if (phydm_is_cck_rate(dm, (u8)rate_index)) {
-			/* @normal mode */
-			odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);
-			/* @turn on scramble setting */
-			odm_set_bb_reg(dm, R_0x1a00, 0x8, 0x1);
-			/* @BB Reset */
-			odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0);
-			odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1);
+			if(dm->support_ic_type & ODM_RTL8723F) {
+				/* TX Stop */
+				odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x1);
+				/* Clear BB cont tx */
+				odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x0);
+				/* Clear PMAC cont tx */
+				odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x0);
+				/* Clear TX Stop */
+				odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x0);
+				/* normal mode */
+				odm_set_bb_reg(dm, R_0x2a08, BIT(18), 0x0);
+				/* turn on scramble setting */
+				odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0);
+			}
+			else {
+				/*normal mode */
+				odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);			
+				/*turn on scramble setting */
+				odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1);
+			}
+			/*BB Reset */
+			odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
+			odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
 		}
 	}
 }
-#endif

+void phydm_mp_set_single_carrier_jgr3(void *dm_void, boolean is_single_carrier)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_mp *mp = &dm->dm_mp_table;
+
+	if (is_single_carrier) {
+		/*1. if OFDM block on? */
+		if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
+			odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1);
+		
+		if (dm->support_ic_type & ODM_RTL8723F) {
+			/*3. turn on scramble setting */
+			odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0);
+			/*4. Turn On single carrier. */
+			odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
+		}
+		else {
+			/*2. set CCK test mode off, set to CCK normal mode */
+			odm_set_bb_reg(dm, R_0x1a00, 0x3, 0);
+			/*3. turn on scramble setting */
+			odm_set_bb_reg(dm, R_0x1a00, BIT(3), 1);
+			/*4. Turn On single carrier. */
+			odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
+		}
+	} else {
+		/*Turn off all test modes. */
+		odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_OFF);
+
+		/*Delay 10 ms */
+		ODM_delay_ms(10);
+
+		/*BB Reset*/
+		odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
+		odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
+	}
+}
+
+void phydm_mp_get_tx_ok_jgr3(void *dm_void, u32 rate_index)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_mp *mp = &dm->dm_mp_table;
+
+	if (phydm_is_cck_rate(dm, (u8)rate_index))
+		mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de4, MASKLWORD);
+	else
+		mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de0, MASKLWORD);
+}
+
+void phydm_mp_get_rx_ok_jgr3(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_mp *mp = &dm->dm_mp_table;
+
+	u32 cck_ok = 0, ofdm_ok = 0, ht_ok = 0, vht_ok = 0;
+	u32 cck_err = 0, ofdm_err = 0, ht_err = 0, vht_err = 0;
+	if(dm->support_ic_type & ODM_RTL8723F)
+		cck_ok = odm_get_bb_reg(dm, R_0x2aac, MASKLWORD);
+	else
+		cck_ok = odm_get_bb_reg(dm, R_0x2c04, MASKLWORD);
+	ofdm_ok = odm_get_bb_reg(dm, R_0x2c14, MASKLWORD);
+	ht_ok = odm_get_bb_reg(dm, R_0x2c10, MASKLWORD);
+	vht_ok = odm_get_bb_reg(dm, R_0x2c0c, MASKLWORD);
+	if(dm->support_ic_type & ODM_RTL8723F)
+		cck_err = odm_get_bb_reg(dm, R_0x2aac, MASKHWORD);
+	else
+		cck_err = odm_get_bb_reg(dm, R_0x2c04, MASKHWORD);
+	ofdm_err = odm_get_bb_reg(dm, R_0x2c14, MASKHWORD);
+	ht_err = odm_get_bb_reg(dm, R_0x2c10, MASKHWORD);
+	vht_err = odm_get_bb_reg(dm, R_0x2c0c, MASKHWORD);
+
+	mp->rx_phy_ok_cnt = cck_ok + ofdm_ok + ht_ok + vht_ok;
+	mp->rx_phy_crc_err_cnt = cck_err + ofdm_err + ht_err + vht_err;
+	mp->io_value = (u32)mp->rx_phy_ok_cnt;
+}
+#endif
 void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
@@ -218,61 +379,9 @@ void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,
 void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
-	struct phydm_mp *mp = &dm->dm_mp_table;

-	if (is_single_carrier) {
-		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-			/* @1. if OFDM block on? */
-			if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
-				odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1);
-
-			/* @2. set CCK test mode off, set to CCK normal mode */
-			odm_set_bb_reg(dm, R_0x1a00, 0x3, 0);
-
-			/* @3. turn on scramble setting */
-			odm_set_bb_reg(dm, R_0x1a00, 0x8, 1);
-
-			/* @4. Turn On single carrier. */
-			odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
-		} else {
-			/* @1. if OFDM block on? */
-			if (!odm_get_bb_reg(dm, R_0x800, 0x2000000))
-				odm_set_bb_reg(dm, R_0x800, 0x2000000, 1);
-
-			/* @2. set CCK test mode off, set to CCK normal mode */
-			odm_set_bb_reg(dm, R_0xa00, 0x3, 0);
-
-			/* @3. turn on scramble setting */
-			odm_set_bb_reg(dm, R_0xa00, 0x8, 1);
-
-			/* @4. Turn On single carrier. */
-			if (dm->support_ic_type & ODM_IC_11AC_SERIES)
-				odm_set_bb_reg(dm, R_0x914, 0x70000,
-					       OFDM_SINGLE_CARRIER);
-			else if (dm->support_ic_type & ODM_IC_11N_SERIES)
-				odm_set_bb_reg(dm, R_0xd00, 0x70000000,
-					       OFDM_SINGLE_CARRIER);
-		}
-	} else { /* @Stop Single Carrier. */
-	    /* @Turn off all test modes. */
-		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-			odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_OFF);
-		else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
-			odm_set_bb_reg(dm, R_0x914, 0x70000, OFDM_OFF);
-		else if (dm->support_ic_type & ODM_IC_11N_SERIES)
-			odm_set_bb_reg(dm, R_0xd00, 0x70000000, OFDM_OFF);
-		/* @Delay 10 ms */
-		ODM_delay_ms(10);
-
-		/* @BB Reset */
-		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-			odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0);
-			odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1);
-		} else {
-			odm_set_bb_reg(dm, R_0x100, 0x100, 0x0);
-			odm_set_bb_reg(dm, R_0x100, 0x100, 0x1);
-		}
-	} 
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		phydm_mp_set_single_carrier_jgr3(dm, is_single_carrier);
 }
 void phydm_mp_reset_rx_counters_phy(void *dm_void)
 {
@@ -284,65 +393,16 @@ void phydm_mp_reset_rx_counters_phy(void *dm_void)
 void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
-	struct phydm_mp *mp = &dm->dm_mp_table;

-	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-		if (phydm_is_cck_rate(dm, (u8)rate_index))
-			mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de4,
-							   0xffff);
-		else
-			mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de0,
-							   0xffff);
-	} else {
-		if (phydm_is_cck_rate(dm, (u8)rate_index))
-			mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0xf50,
-							   0xffff);
-		else
-			mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0xf50,
-							   0xffff0000);
-	}
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		phydm_mp_get_tx_ok_jgr3(dm, rate_index);
 }

 void phydm_mp_get_rx_ok(void *dm_void)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
-	struct phydm_mp *mp = &dm->dm_mp_table;	

-	u32 cck_ok = 0, ofdm_ok = 0, ht_ok = 0, vht_ok = 0;	
-	u32 cck_err = 0, ofdm_err = 0, ht_err = 0, vht_err = 0;
-
-	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-		cck_ok = odm_get_bb_reg(dm, R_0x2c04, 0xffff);
-		ofdm_ok = odm_get_bb_reg(dm, R_0x2c14, 0xffff);
-		ht_ok = odm_get_bb_reg(dm, R_0x2c10, 0xffff);
-		vht_ok = odm_get_bb_reg(dm, R_0x2c0c, 0xffff);
-  
-		cck_err = odm_get_bb_reg(dm, R_0x2c04, 0xffff0000);
-		ofdm_err = odm_get_bb_reg(dm, R_0x2c14, 0xffff0000);
-		ht_err = odm_get_bb_reg(dm, R_0x2c10, 0xffff0000);
-		vht_err = odm_get_bb_reg(dm, R_0x2c0c, 0xffff0000);
-	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-		cck_ok = odm_get_bb_reg(dm, R_0xf04, 0x3FFF);
-		ofdm_ok = odm_get_bb_reg(dm, R_0xf14, 0x3FFF);
-		ht_ok = odm_get_bb_reg(dm, R_0xf10, 0x3FFF);
-		vht_ok = odm_get_bb_reg(dm, R_0xf0c, 0x3FFF);
-  
-		cck_err = odm_get_bb_reg(dm, R_0xf04, 0x3FFF0000);
-		ofdm_err = odm_get_bb_reg(dm, R_0xf14, 0x3FFF0000);
-		ht_err = odm_get_bb_reg(dm, R_0xf10, 0x3FFF0000);
-		vht_err = odm_get_bb_reg(dm, R_0xf0c, 0x3FFF0000);
-	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-		cck_ok = odm_get_bb_reg(dm, R_0xf88, MASKDWORD);
-		ofdm_ok = odm_get_bb_reg(dm, R_0xf94, 0xffff);
-		ht_ok = odm_get_bb_reg(dm, R_0xf90, 0xffff);
-	    
-		cck_err = odm_get_bb_reg(dm, R_0xf84, MASKDWORD);
-		ofdm_err = odm_get_bb_reg(dm, R_0xf94, 0xffff0000);
-		ht_err = odm_get_bb_reg(dm, R_0xf90, 0xffff0000);
-	}
-
-	mp->rx_phy_ok_cnt = cck_ok + ofdm_ok + ht_ok + vht_ok;
-	mp->rx_phy_crc_err_cnt = cck_err + ofdm_err + ht_err + vht_err;
-	mp->io_value = (u32)mp->rx_phy_ok_cnt;
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+		phydm_mp_get_rx_ok_jgr3(dm);
 }
 #endif
--- a/hal/phydm/phydm_mp.h
+++ b/hal/phydm/phydm_mp.h
@@ -26,7 +26,8 @@
 #ifndef __PHYDM_MP_H__
 #define __PHYDM_MP_H__

-#define MP_VERSION "1.3"
+/*2020.04.27 Refine single tone Tx flow*/
+#define MP_VERSION "1.5"

 /* @1 ============================================================
 * 1  Definition
@@ -37,22 +38,18 @@
 * 1 ============================================================
 */
 struct phydm_mp {
-	/* @Rx OK count, statistics used in Mass Production Test.*/
+	/*Rx OK count, statistics used in Mass Production Test.*/
 	u64 tx_phy_ok_cnt;
 	u64 rx_phy_ok_cnt;
-	/* @Rx CRC32 error count, statistics used in Mass Production Test.*/
+	/*Rx CRC32 error count, statistics used in Mass Production Test.*/
 	u64 rx_phy_crc_err_cnt;
-	/* @The Value of IO operation is depend of MptActType.*/
+	/*The Value of IO operation is depend of MptActType.*/
 	u32 io_value;
-	u32 rf_reg0;
-	/* @u32 rfe_sel_a_0;*/
-	/* @u32 rfe_sel_b_0;*/
-	/* @u32 rfe_sel_c_0;*/
-	/* @u32 rfe_sel_d_0;*/
-	/* @u32 rfe_sel_a_1;*/
-	/* @u32 rfe_sel_b_1;*/
-	/* @u32 rfe_sel_c_1;*/
-	/* @u32 rfe_sel_d_1;*/
+	u32 rf0[RF_PATH_MEM_SIZE];
+	#if (RTL8814B_SUPPORT)
+	u32 rf0_syn[2];
+	#endif
+	u32 rf1[RF_PATH_MEM_SIZE];
 };

 /* @1 ============================================================
--- a/hal/phydm/phydm_noisemonitor.c
+++ b/hal/phydm/phydm_noisemonitor.c
@@ -258,7 +258,8 @@ s16 odm_inband_noise_monitor_ac(struct dm_struct *dm, u8 pause_dig, u8 igi,
 	s32 value32, pwdb_A = 0, sval, noise, sum = 0;
 	boolean pd_flag;
 	u8 valid_cnt = 0;
-	u64 start = 0, func_start = 0, func_end = 0;
+	u8 invalid_cnt = 0;
+	u64 start = 0, func_start = 0, func_end = 0, proc_time = 0;
 	s32 val_s32 = 0;
 	s16 rpt = 0;
 	u8 val_u8 = 0;
@@ -350,6 +351,15 @@ s16 odm_inband_noise_monitor_ac(struct dm_struct *dm, u8 pause_dig, u8 igi,
 					  "After divided, sum = %d\n", sum);
 				break;
 			}
+		} else {
+			/*Invalid sval and return -110 dBm*/
+			invalid_cnt++;
+			PHYDM_DBG(dm, DBG_ENV_MNTR, "Invalid sval\n");
+			if (invalid_cnt >= VALID_CNT + 5) {
+				PHYDM_DBG(dm, DBG_ENV_MNTR,
+					  "Invalid count > TH, Return -110, Break!!\n");
+				return -110;
+			}
 		}
 	}

--- a/hal/phydm/phydm_pathdiv.c
+++ b/hal/phydm/phydm_pathdiv.c
@@ -1040,10 +1040,8 @@ void phydm_pathdiv_debug(void *dm_void, char input[][16], u32 *_used,
 	u8 i, input_idx = 0;

 	for (i = 0; i < 5; i++) {
-		if (input[i + 1]) {
-			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
-			input_idx++;
-		}
+		PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
+		input_idx++;
 	}

 	if (input_idx == 0)
--- a/hal/phydm/phydm_phystatus.c
+++ b/hal/phydm/phydm_phystatus.c
--- a/hal/phydm/phydm_phystatus.h
+++ b/hal/phydm/phydm_phystatus.h
@@ -26,6 +26,9 @@
 #ifndef __PHYDM_PHYSTATUS_H__
 #define __PHYDM_PHYSTATUS_H__

+/* 2020.07.03 fix cck report bug due to 8723F coding error*/
+#define PHYSTS_VERSION "1.2"
+
 /*@--------------------------Define ------------------------------------------*/
 #define CCK_RSSI_INIT_COUNT 5

@@ -645,7 +648,79 @@ __PACK struct phy_sts_rpt_jgr3_type0 {
 	u8 gain_d : 6;
 #endif
 };
+#if(RTL8723F_SUPPORT)
+__PACK struct phy_sts_rpt_jgr3_type6 {
+	/* judy_add_8723F_0512 */
+/* @DW0 : Offset 0 */
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 pop_idx : 4;
+	u8 pkt_cnt : 2;
+	u8 channel_msb : 2;
+#else
+	u8 channel_msb : 2;
+	u8 pkt_cnt : 2;
+	u8 pop_idx : 4;
+#endif

+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 agc_table_a : 4;
+	u8 rsvd_0 : 4;
+#else
+	u8 rsvd_0 : 4;
+	u8 agc_table_a : 4;
+#endif
+	u8 rsvd_1 : 8;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 trsw : 1;
+	u8 hw_antsw_occur_keep_cck : 1;
+	u8 gnt_bt_keep_cck : 1;
+	u8 rssi_msb : 3;
+	u8 rsvd_2 : 2;	
+#else
+	u8 rsvd_2 : 2;
+	u8 rssi_msb : 3;
+	u8 gnt_bt_keep_cck : 1;
+	u8 hw_antsw_occur_keep_cck : 1;
+	u8 trsw : 1;
+#endif
+
+/* @DW1 : Offset 4 */
+	u8 channel;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 antidx_a : 4;
+	u8 rsvd_2_1 : 4;
+#else
+	u8 rsvd_2_1 : 4;
+	u8 antidx_a : 4;
+#endif
+	u8 rsvd_2_2;
+	u8 mp_gain_idx_a;
+
+/* @DW2 : Offset 8 */
+	u16 rsvd_3_1;
+	u8 rsvd_4_1;
+	u8 rssi;
+
+/* @DW3 : Offset 12 */
+	u16 rsvd_4_2;
+	u8 rsvd_5_1;
+	u8 avg_cfo;	
+/* @DW4 : Offset 16 */
+	u8 coarse_cfo;
+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 coarse_cfo_msb : 4;
+	u8 avg_cfo_msb : 4;
+#else
+	u8 avg_cfo_msb : 4;
+	u8 coarse_cfo_msb : 4;
+#endif
+	u8 evm_hdr;
+	u8 evm_pld;
+/* @DW5 : Offset 20 */
+	u32 rsvd_6_1;
+	u32 rsvd_7_1;
+};
+#endif
 __PACK struct phy_sts_rpt_jgr3_type1 {
 /* @DW0 : Offset 0 */
 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
@@ -1092,20 +1167,55 @@ __PACK struct phy_sts_rpt_jgr3_type5 {
 	u8 inf_pos_0_d;
 	u8 inf_pos_1_d;
 };
+
+__PACK struct phy_sts_rpt_jgr3_ofdm_cmn {
+	#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 page_num : 4;
+	u8 pkt_cnt : 2;
+	u8 channel_msb : 2;
+	#else
+	u8 channel_msb : 2;
+	u8 pkt_cnt : 2;
+	u8 page_num : 4;
+	#endif
+	u8 pwdb[4];
+	#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 l_rxsc : 4;
+	u8 ht_rxsc : 4;
+	#else
+	u8 ht_rxsc : 4;
+	u8 l_rxsc : 4;
+	#endif
+	u8 channel_lsb;
+	#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
+	u8 band : 2;
+	u8 rsvd_0 : 2;
+	u8 gnt_bt : 1;
+	u8 ldpc : 1;
+	u8 stbc : 1;
+	u8 beamformed : 1;
+	#else
+	u8 beamformed : 1;
+	u8 stbc : 1;
+	u8 ldpc : 1;
+	u8 gnt_bt : 1;
+	u8 rsvd_0 : 1;
+	u8 band : 2;
+	#endif
+};
 #endif /*@#ifdef PHYSTS_3RD_TYPE_SUPPORT*/

+#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
+void phydm_physts_auto_switch_jgr3_set(void *dm_void, boolean enable,
+				       u8 bitmap_en);
+#endif
+
 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
 boolean
 phydm_query_is_mu_api(struct dm_struct *phydm, u8 ppdu_idx, u8 *p_data_rate,
 		      u8 *p_gid);
 #endif

-#ifdef PHYSTS_3RD_TYPE_SUPPORT
-void phydm_rx_physts_3rd_type(void *dm_void, u8 *phy_sts,
-			      struct phydm_perpkt_info_struct *pktinfo,
-			      struct phydm_phyinfo_struct *phy_info);
-#endif
-
 void phydm_reset_phystatus_avg(struct dm_struct *dm);

 void phydm_reset_phystatus_statistic(struct dm_struct *dm);
@@ -1127,10 +1237,10 @@ void phydm_normal_driver_rx_sniffer(
 s32 phydm_signal_scale_mapping(struct dm_struct *dm, s32 curr_sig);
 #endif

-void odm_phy_status_query(struct dm_struct *dm,
-			  struct phydm_phyinfo_struct *phy_info,
-			  u8 *phy_status_inf,
-			  struct phydm_perpkt_info_struct *pktinfo);
+boolean odm_phy_status_query(struct dm_struct *dm,
+			     struct phydm_phyinfo_struct *phy_info,
+			     u8 *phy_sts,
+			     struct phydm_perpkt_info_struct *pktinfo);

 void phydm_rx_phy_status_init(void *dm_void);

--- a/hal/phydm/phydm_pmac_tx_setting.c
+++ b/hal/phydm/phydm_pmac_tx_setting.c
@@ -32,32 +32,34 @@

 #ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-
 void phydm_start_cck_cont_tx_jgr3(void *dm_void,
 				  struct phydm_pmac_info *tx_info)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
-	u8 rate = tx_info->tx_rate; /* @HW rate */
+	u8 rate = tx_info->tx_rate; /* HW rate */

-	/* @if CCK block on? */
+	/* if CCK block on? */
 	if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
-		odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1);
-
-	/* @Turn Off All Test mode */
+		odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 0x1);
+	if (dm->support_ic_type & ODM_RTL8723F) {
+		odm_set_bb_reg(dm, R_0x2a08, BIT(21)|BIT(20), rate);
+		odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0); /* turn on scrambler*/
+	} else {
+	/* Turn Off All Test mode */
 	odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);

 	odm_set_bb_reg(dm, R_0x1a00, 0x3000, rate);
-	odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2); /* @transmit mode */
-	odm_set_bb_reg(dm, R_0x1a00, 0x8, 0x1); /* @turn on scramble setting */
+	odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2); /* transmit mode */
+	odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1); /* turn on scrambler*/

-	/* @Fix rate selection issue */
-	odm_set_bb_reg(dm, R_0x1a70, 0x4000, 0x1);
-	/* @set RX weighting for path I & Q to 0 */
+	/* Fix rate selection issue */
+	odm_set_bb_reg(dm, R_0x1a70, BIT(14), 0x1);
+	/* set RX weighting for path I & Q to 0 */
 	odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
-	/* @set loopback mode */
-	odm_set_bb_reg(dm, R_0x1c3c, 0x10, 0x1);
-
+	/* set loopback mode */
+	odm_set_bb_reg(dm, R_0x1c3c, BIT(4), 0x1);
+	}
 	pmac_tx->cck_cont_tx = true;
 	pmac_tx->ofdm_cont_tx = false;
 }
@@ -70,16 +72,21 @@ void phydm_stop_cck_cont_tx_jgr3(void *dm_void)
 	pmac_tx->cck_cont_tx = false;
 	pmac_tx->ofdm_cont_tx = false;

-	odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0); /* @normal mode */
-	odm_set_bb_reg(dm, R_0x1a00, 0x8, 0x1); /* @turn on scramble setting */
+	if (dm->support_ic_type & ODM_RTL8723F) {
+		/* @Disable pmac tx_en*/
+		odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0); /* turn on scrambler*/
+	} else {
+		odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0); /* normal mode */
+		odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1); /* turn on scrambler*/

-	/* @back to default */
-	odm_set_bb_reg(dm, R_0x1a70, 0x4000, 0x0);
-	odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
-	odm_set_bb_reg(dm, R_0x1c3c, 0x10, 0x0);
-	/* @BB Reset */
-	odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0);
-	odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1);
+		/* back to default */
+		odm_set_bb_reg(dm, R_0x1a70, BIT(14), 0x0);
+		odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
+		odm_set_bb_reg(dm, R_0x1c3c, BIT(4), 0x0);
+	}
+	/* BB Reset */
+	odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
+	odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
 }

 void phydm_start_ofdm_cont_tx_jgr3(void *dm_void)
@@ -87,17 +94,18 @@ void phydm_start_ofdm_cont_tx_jgr3(void *dm_void)
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;

-	/* @1. if OFDM block on */
+	/* 1. if OFDM block on */
 	if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
-		odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1);
+		odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 0x1);
+	if (!(dm->support_ic_type & ODM_RTL8723F)) {

-	/* @2. set CCK test mode off, set to CCK normal mode */
-	odm_set_bb_reg(dm, R_0x1a00, 0x3, 0);
+		/* 2. set CCK test mode off, set to CCK normal mode */
+		odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);

-	/* @3. turn on scramble setting */
-	odm_set_bb_reg(dm, R_0x1a00, 0x8, 1);
-
-	/* @4. Turn On Continue Tx and turn off the other test modes. */
+		/* 3. turn on scramble setting */
+		odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1);
+	}
+	/* 4. Turn On Continue Tx and turn off the other test modes. */
 	odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x1);

 	pmac_tx->cck_cont_tx = false;
@@ -112,126 +120,15 @@ void phydm_stop_ofdm_cont_tx_jgr3(void *dm_void)
 	pmac_tx->cck_cont_tx = false;
 	pmac_tx->ofdm_cont_tx = false;

-	/* @Turn Off All Test mode */
+	/* Turn Off All Test mode */
 	odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);

-	/* @Delay 10 ms */
+	/* Delay 10 ms */
 	ODM_delay_ms(10);

-	/* @BB Reset */
-	odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0);
-	odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1);
-}
-
-void phydm_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
-				boolean en_pmac_tx, u8 path)
-{
-	struct dm_struct *dm = (struct dm_struct *)dm_void;
-	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
-	u8 start = RF_PATH_A, end = RF_PATH_A;
-	u8 i = 0;
-
-	switch (path) {
-	case RF_PATH_A:
-	case RF_PATH_B:
-	case RF_PATH_C:
-	case RF_PATH_D:
-		start = path;
-		end = path;
-		break;
-	case RF_PATH_AB:
-		start = RF_PATH_A;
-		end = RF_PATH_B;
-		break;
-#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT)
-	case RF_PATH_AC:
-		start = RF_PATH_A;
-		end = RF_PATH_C;
-		break;
-	case RF_PATH_AD:
-		start = RF_PATH_A;
-		end = RF_PATH_D;
-		break;
-	case RF_PATH_BC:
-		start = RF_PATH_B;
-		end = RF_PATH_C;
-		break;
-	case RF_PATH_BD:
-		start = RF_PATH_B;
-		end = RF_PATH_D;
-		break;
-	case RF_PATH_CD:
-		start = RF_PATH_C;
-		end = RF_PATH_D;
-		break;
-	case RF_PATH_ABC:
-		start = RF_PATH_A;
-		end = RF_PATH_C;
-		break;
-	case RF_PATH_ABD:
-		start = RF_PATH_A;
-		end = RF_PATH_D;
-		break;
-	case RF_PATH_ACD:
-		start = RF_PATH_A;
-		end = RF_PATH_D;
-		break;
-	case RF_PATH_BCD:
-		start = RF_PATH_B;
-		end = RF_PATH_D;
-		break;
-	case RF_PATH_ABCD:
-		start = RF_PATH_A;
-		end = RF_PATH_D;
-		break;
-#endif
-	}
-
-	if (is_single_tone) {
-		pmac_tx->tx_scailing = odm_get_bb_reg(dm, R_0x81c, MASKDWORD);
-
-		if (!en_pmac_tx) {
-			phydm_start_ofdm_cont_tx_jgr3(dm);
-			/*SendPSPoll(pAdapter);*/
-		}
-
-		odm_set_bb_reg(dm, R_0x1c68, BIT(24), 0x1); /* @Disable CCA */
-
-		for (i = start; i <= end; i++) {
-			/* @Tx mode: RF0x00[19:16]=4'b0010 */
-			/* @odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2); */
-			/* @Lowest RF gain index: RF_0x0[4:0] = 0*/
-			odm_set_rf_reg(dm, i, RF_0x0, 0x1F, 0x0);
-			/* @RF LO enabled */
-			odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
-		}
-		#if (RTL8814B_SUPPORT == 1)
-		if (dm->support_ic_type & ODM_RTL8814B) {
-			/* @Tx mode: RF0x00[19:16]=4'b0010 */
-			/* config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
-			 *				0xF0000, 0x2);
-			 */
-			/* @Lowest RF gain index: RF_0x0[4:0] = 0*/
-			config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
-							0x1F, 0x0);
-			/* @RF LO enabled */
-			config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
-							BIT(1), 0x1);
-		}
-		#endif
-		odm_set_bb_reg(dm, R_0x81c, 0x001FC000, 0);
-	} else {
-		for (i = start; i <= end; i++) {
-			/* @RF LO disabled */
-			odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
-		}
-		odm_set_bb_reg(dm, R_0x1c68, BIT(24), 0x0); /* @Enable CCA */
-
-		if (!en_pmac_tx)
-			phydm_stop_ofdm_cont_tx_jgr3(dm);
-
-		odm_set_bb_reg(dm, R_0x81c, MASKDWORD, pmac_tx->tx_scailing);
-	}
+	/* BB Reset */
+	odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
+	odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
 }

 void phydm_stop_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
@@ -240,28 +137,39 @@ void phydm_stop_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
 	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
 	u32 tmp = 0;

-	if (tx_info->mode == CONT_TX) {
-		odm_set_bb_reg(dm, R_0x1e70, 0xf, 2); /* TX Stop */
+	odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x2); /* TX Stop */
+	if (dm->support_ic_type & ODM_RTL8723F) {
+		if (tx_info->mode == CONT_TX) {
+			if (pmac_tx->is_cck_rate) {
+				/* TX Stop */
+				odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x1);
+				/* Clear BB cont tx */
+				odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x0);
+				/* Clear PMAC cont tx */
+				odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x0);
+				/* Clear TX Stop */
+				odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x0);
+				phydm_stop_cck_cont_tx_jgr3(dm);
+			} else 
+				phydm_stop_ofdm_cont_tx_jgr3(dm);
+		} else {
+			if (pmac_tx->is_cck_rate) {
+				/* packet_count = 0x1 */
+				odm_set_bb_reg(dm, R_0x2a04, 0x03ff0000, 0x1);
+				/* @Disable pmac tx_en*/
+				odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0);
+				/* @Enable pmac tx_en*/
+				odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1);
+				phydm_stop_cck_cont_tx_jgr3(dm);
+			}
+		} 
+	}else {
+		if (tx_info->mode == CONT_TX) {
 		if (pmac_tx->is_cck_rate)
 			phydm_stop_cck_cont_tx_jgr3(dm);
 		else
 			phydm_stop_ofdm_cont_tx_jgr3(dm);
-	} else {
-		if (pmac_tx->is_cck_rate) {
-			tmp = odm_get_bb_reg(dm, R_0x2de4, MASKLWORD);
-			odm_set_bb_reg(dm, R_0x1e64, MASKLWORD, tmp + 50);
 		}
-		odm_set_bb_reg(dm, R_0x1e70, 0xf, 2); /* TX Stop */
-	}
-
-	if (tx_info->mode == OFDM_SINGLE_TONE_TX) {
-		/* Stop HW TX -> Stop Continuous TX -> Stop RF Setting */
-		if (pmac_tx->is_cck_rate)
-			phydm_stop_cck_cont_tx_jgr3(dm);
-		else
-			phydm_stop_ofdm_cont_tx_jgr3(dm);
-
-		phydm_set_single_tone_jgr3(dm, false, true, pmac_tx->path);
 	}
 }

@@ -272,34 +180,39 @@ void phydm_set_mac_phy_txinfo_jgr3(void *dm_void,
 	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
 	u32 tmp = 0;

-	odm_set_bb_reg(dm, R_0xa58, 0x003F8000, tx_info->tx_rate);
+	odm_set_bb_reg(dm, R_0xa58, 0x003f8000, tx_info->tx_rate);

-	/* @0x900[1] ndp_sound */
-	odm_set_bb_reg(dm, R_0x900, 0x2, tx_info->ndp_sound);
+	/*0x900[1] ndp_sound */
+	odm_set_bb_reg(dm, R_0x900, BIT(1), tx_info->ndp_sound);

-	/* @0x900[27:24] txsc [29:28] bw [31:30] m_stbc */
-	if (dm->support_ic_type & (ODM_RTL8812F | ODM_RTL8197G)) {
-		tmp = (tx_info->tx_sc) | ((tx_info->bw) << 4) |
-			((tx_info->m_stbc) << 6);
-	} else {
-		tmp = (tx_info->tx_sc) | ((tx_info->bw) << 4) |
-			((tx_info->m_stbc - 1) << 6);
-	}
-	odm_set_bb_reg(dm, R_0x900, 0xFF000000, tmp);
+	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+	tx_info->m_stbc = tx_info->m_stbc - 1;
+	#endif
+	/*0x900[27:24] txsc [29:28] bw [31:30] m_stbc */
+	tmp = (tx_info->tx_sc) | ((tx_info->bw) << 4) |
+		((tx_info->m_stbc) << 6);
+	odm_set_bb_reg(dm, R_0x900, 0xff000000, tmp);

-	if (pmac_tx->is_ofdm_rate) {
-		odm_set_bb_reg(dm, R_0x900, 0x1, 0);
-		odm_set_bb_reg(dm, R_0x900, 0x4, 0);
-	} else if (pmac_tx->is_ht_rate) {
-		odm_set_bb_reg(dm, R_0x900, 0x1, 1);
-		odm_set_bb_reg(dm, R_0x900, 0x4, 0);
+	if (tx_info->tx_sc == 1) /*upper*/
+		odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x5);
+	else if (tx_info->tx_sc == 2) /*lower*/
+		odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x6);
+	else /* duplicate*/
+		odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x0);
+
+	if (pmac_tx->is_ht_rate) {
+		odm_set_bb_reg(dm, R_0x900, BIT(0), 0x1);
+		odm_set_bb_reg(dm, R_0x900, BIT(2), 0x0);
 	} else if (pmac_tx->is_vht_rate) {
-		odm_set_bb_reg(dm, R_0x900, 0x1, 0);
-		odm_set_bb_reg(dm, R_0x900, 0x4, 1);
+		odm_set_bb_reg(dm, R_0x900, BIT(0), 0x0);
+		odm_set_bb_reg(dm, R_0x900, BIT(2), 0x1);
+	} else {
+		odm_set_bb_reg(dm, R_0x900, BIT(0), 0x0);
+		odm_set_bb_reg(dm, R_0x900, BIT(2), 0x0);
 	}

-	tmp = tx_info->packet_period; /* @for TX interval */
-	odm_set_bb_reg(dm, R_0x9b8, 0xffff0000, tmp);
+	/* for TX interval */
+	odm_set_bb_reg(dm, R_0x9b8, MASKHWORD, tx_info->packet_period);
 }

 void phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
@@ -311,26 +224,14 @@ void phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
 	if (pmac_tx->is_cck_rate)
 		return;

-	/* @L-SIG */
 	odm_set_bb_reg(dm, R_0x1eb4, 0xfffff, tx_info->packet_count);

+	/* L-SIG */
 	tmp = BYTE_2_DWORD(0, tx_info->lsig[2], tx_info->lsig[1],
 			   tx_info->lsig[0]);
 	odm_set_bb_reg(dm, R_0x908, 0xffffff, tmp);
-#if 0
-	/* @0x924[7:0] = Data init octet */
-	tmp = tx_info->packet_pattern;
-	odm_set_bb_reg(dm, R_0x924, 0xff, tmp);
-
-	if (tx_info->packet_pattern == RANDOM_BY_PN32)
-		tmp = 0x3;
-	else
-		tmp = 0x0;
-
-	odm_set_bb_reg(dm, R_0x914, 0x60000000, tmp);
-#endif
 	if (pmac_tx->is_ht_rate) {
-	/* @HT SIG */
+	/* HT SIG */
 		tmp = BYTE_2_DWORD(0, tx_info->ht_sig[2], tx_info->ht_sig[1],
 				   tx_info->ht_sig[0]);
 		odm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp);
@@ -338,7 +239,7 @@ void phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
 				   tx_info->ht_sig[3]);
 		odm_set_bb_reg(dm, R_0x910, 0xffffff, tmp);
 	} else if (pmac_tx->is_vht_rate) {
-	/* @VHT SIG A/B/serv_field/delimiter */
+	/* VHT SIG A/B/serv_field/delimiter */
 		tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[2],
 				   tx_info->vht_sig_a[1],
 				   tx_info->vht_sig_a[0]);
@@ -350,10 +251,8 @@ void phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
 		tmp = BYTE_2_DWORD(tx_info->vht_sig_b[3], tx_info->vht_sig_b[2],
 				   tx_info->vht_sig_b[1],
 				   tx_info->vht_sig_b[0]);
-		odm_set_bb_reg(dm, R_0x914, 0x1FFFFFFF, tmp);
-
-		tmp = tx_info->vht_sig_b_crc;
-		odm_set_bb_reg(dm, R_0x938, 0xff00, tmp);
+		odm_set_bb_reg(dm, R_0x914, 0x1fffffff, tmp);
+		odm_set_bb_reg(dm, R_0x938, 0xff00, tx_info->vht_sig_b_crc);

 		tmp = BYTE_2_DWORD(tx_info->vht_delimiter[3],
 				   tx_info->vht_delimiter[2],
@@ -369,22 +268,39 @@ void phydm_set_cck_preamble_hdr_jgr3(void *dm_void,
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
 	u32 tmp = 0;
+	u8 rate = tx_info->tx_rate; /* HW rate */

 	if (!pmac_tx->is_cck_rate)
 		return;

-	tmp = tx_info->packet_count | (tx_info->sfd << 16);
-	odm_set_bb_reg(dm, R_0x1e64, MASKDWORD, tmp);
-	tmp = tx_info->signal_field | (tx_info->service_field << 8) |
-	      (tx_info->length << 16);
-	odm_set_bb_reg(dm, R_0x1e68, MASKDWORD, tmp);
-	tmp = BYTE_2_DWORD(0, 0, tx_info->crc16[1], tx_info->crc16[0]);
-	odm_set_bb_reg(dm, R_0x1e6c, 0xffff, tmp);
+	if (dm->support_ic_type & ODM_RTL8723F) {
+		#if (RTL8723F_SUPPORT)
+		odm_set_bb_reg(dm, R_0x2a04, 0x03ff0000, tx_info->packet_count);
+		odm_set_bb_reg(dm, R_0x2a08, BIT(22), tx_info->service_field_bit2);
+		odm_set_bb_reg(dm, R_0x2a08, BIT(21) | BIT(20), rate);
+		odm_set_bb_reg(dm, R_0x2a08, 0x1ffff, tx_info->packet_length);
+		/* turn on scrambler */
+		odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0);

-	if (tx_info->is_short_preamble)
-		odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0);
-	else
-		odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 1);
+		if (tx_info->is_short_preamble)
+			odm_set_bb_reg(dm, R_0x2a08, BIT(19), 0x1);
+		else
+			odm_set_bb_reg(dm, R_0x2a08, BIT(19), 0x0);
+		#endif
+	} else {
+		tmp = tx_info->packet_count | (tx_info->sfd << 16);
+		odm_set_bb_reg(dm, R_0x1e64, MASKDWORD, tmp);
+		tmp = tx_info->signal_field | (tx_info->service_field << 8) |
+	      	(tx_info->length << 16);
+		odm_set_bb_reg(dm, R_0x1e68, MASKDWORD, tmp);
+		tmp = BYTE_2_DWORD(0, 0, tx_info->crc16[1], tx_info->crc16[0]);
+		odm_set_bb_reg(dm, R_0x1e6c, MASKLWORD, tmp);
+
+		if (tx_info->is_short_preamble)
+			odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0x0);
+		else
+			odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0x1);
+	}
 }

 void phydm_set_mode_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
@@ -400,17 +316,6 @@ void phydm_set_mode_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
 			phydm_start_cck_cont_tx_jgr3(dm, tx_info);
 		else
 			phydm_start_ofdm_cont_tx_jgr3(dm);
-	} else if (mode == OFDM_SINGLE_TONE_TX) {
-		/* Continuous TX -> HW TX -> RF Setting */
-		tx_info->packet_count = 1;
-
-		if (pmac_tx->is_cck_rate)
-			phydm_start_cck_cont_tx_jgr3(dm, tx_info);
-		else
-			phydm_start_ofdm_cont_tx_jgr3(dm);
-	} else if (mode == PKTS_TX) {
-		if (pmac_tx->is_cck_rate && tx_info->packet_count == 0)
-			tx_info->packet_count = 0xffff;
 	}
 }

@@ -419,24 +324,37 @@ void phydm_set_pmac_txon_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;

-	odm_set_bb_reg(dm, R_0x1d08, BIT(0), 1); /* Turn on PMAC */
+	odm_set_bb_reg(dm, R_0x1d08, BIT(0), 0x1); /*Turn on PMAC */

-	/* mac scramble seed setting, only in 8198F */
-	#if (RTL8198F_SUPPORT)
-		if (dm->support_ic_type & ODM_RTL8198F)
-			if (!odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
-				odm_set_bb_reg(dm, R_0x1d10, BIT(16), 1);
-	#endif
-
-	if (pmac_tx->is_cck_rate) {
-		odm_set_bb_reg(dm, R_0x1e70, 0xf, 8); /* TX CCK ON */
-		odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0);
+	if (dm->support_ic_type & ODM_RTL8723F) {
+		if (pmac_tx->is_cck_rate) {
+			if (tx_info->mode == CONT_TX) {
+				/* BB and PMAC cont tx */
+				odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x1);
+				odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x1);
+			}
+			/* TX CCK ON */
+			odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0);
+			odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1);
+		} else {
+			odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x0); /*TX Ofdm OFF */
+			odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x4); /*TX Ofdm ON */
+		}
 	} else {
-		odm_set_bb_reg(dm, R_0x1e70, 0xf, 4); /* TX Ofdm ON */
+		/*mac scramble seed setting, only in 8198F */
+		#if (RTL8198F_SUPPORT)
+			if (dm->support_ic_type & ODM_RTL8198F)
+				if (!odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
+					odm_set_bb_reg(dm, R_0x1d10, BIT(16), 0x1);
+		#endif
+ 
+		if (pmac_tx->is_cck_rate){
+			odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x8); /*TX CCK ON */
+			odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0x0);
+		} else {
+			odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x4); /*TX Ofdm ON */
+		}
 	}
-
-	if (tx_info->mode == OFDM_SINGLE_TONE_TX)
-		phydm_set_single_tone_jgr3(dm, true, true, pmac_tx->path);
 }

 void phydm_set_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
@@ -473,18 +391,20 @@ void phydm_set_tmac_tx_jgr3(void *dm_void)

 	/* Turn on TMAC */
 	if (odm_get_bb_reg(dm, R_0x1d08, BIT(0)))
-		odm_set_bb_reg(dm, R_0x1d08, BIT(0), 0);
+		odm_set_bb_reg(dm, R_0x1d08, BIT(0), 0x0);

 	/* mac scramble seed setting, only in 8198F */
-	#if (RTL8198F_SUPPORT == 1)
+	#if (RTL8198F_SUPPORT)
 		if (dm->support_ic_type & ODM_RTL8198F)
 			if (odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
-				odm_set_bb_reg(dm, R_0x1d10, BIT(16), 0);
+				odm_set_bb_reg(dm, R_0x1d10, BIT(16), 0x0);
 	#endif

 	/* Turn on TMAC CCK */
-	if ((odm_get_bb_reg(dm, R_0x1a84, BIT(31))) == 0)
-		odm_set_bb_reg(dm, R_0x1a84, BIT(31), 1);
+	if (!(dm->support_ic_type & ODM_RTL8723F)) {
+		if (!odm_get_bb_reg(dm, R_0x1a84, BIT(31)))
+			odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0x1);
+	}
 }
 #endif

@@ -492,42 +412,40 @@ void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;

+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
 	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
 		phydm_start_cck_cont_tx_jgr3(dm, tx_info);
+	#endif
 }

 void phydm_stop_cck_cont_tx(void *dm_void)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;

+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
 	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
 		phydm_stop_cck_cont_tx_jgr3(dm);
+	#endif
 }

 void phydm_start_ofdm_cont_tx(void *dm_void)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;

+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
 	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
 		phydm_start_ofdm_cont_tx_jgr3(dm);
+	#endif
 }

 void phydm_stop_ofdm_cont_tx(void *dm_void)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;

+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
 	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
 		phydm_stop_ofdm_cont_tx_jgr3(dm);
-}
-
-void phydm_set_single_tone(void *dm_void, boolean is_single_tone,
-			   boolean en_pmac_tx, u8 path)
-{
-	struct dm_struct *dm = (struct dm_struct *)dm_void;
-
-	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-		phydm_set_single_tone_jgr3(dm, is_single_tone,
-					   en_pmac_tx, path);
+	#endif
 }

 void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info,
@@ -535,16 +453,132 @@ void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info,
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;

+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
 	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
 		phydm_set_pmac_tx_jgr3(dm, tx_info, mpt_rf_path);
+	#endif
 }

 void phydm_set_tmac_tx(void *dm_void)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;

+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
 	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
 		phydm_set_tmac_tx_jgr3(dm);
+	#endif
 }

-#endif
+void phydm_pmac_tx_dbg(void *dm_void, char input[][16], u32 *_used,
+		       char *output, u32 *_out_len)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_pmac_info tx_info;
+	char help[] = "-h";
+	char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
+	u32 var[10] = {0};
+	u32 used = *_used;
+	u32 out_len = *_out_len;
+	u8 i = 0;
+	u32 tx_cnt = 0x0;
+	u8 poll_cnt = 0x0;
+
+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var[0]);
+
+	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
+		return;
+
+	if ((strcmp(input[1], help) == 0)) {
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "[pmac_tx] basic : {1} {rate_idx}(only 1M & 6M) {count}\n");
+	} else {
+		for (i = 1; i < 7; i++) {
+			if (input[i + 1]) {
+				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
+					     &var[i]);
+			}
+		}
+
+		tx_info.en_pmac_tx = true;
+		tx_info.mode = PKTS_TX;
+		tx_info.ndp_sound = false;
+		tx_info.bw = CHANNEL_WIDTH_20;
+		tx_info.tx_sc = 0x0; /*duplicate*/
+		tx_info.m_stbc = 0x0; /*disable*/
+		tx_info.packet_period = 2000; /*d'500 us*/
+		tx_info.tx_rate = (u8)var[1];
+		tx_info.packet_count = (u32)var[2];
+
+		if (tx_info.tx_rate == ODM_RATE1M) {
+			tx_info.signal_field = 0xa; /*rate = 1M*/
+			tx_info.service_field = 0x0;
+			if (dm->support_ic_type & ODM_RTL8723F) {
+				tx_info.service_field_bit2= 0x1;
+				tx_info.packet_length = 1000; /*1000 bytes*/
+			}
+			tx_info.length = 8000; /*d'8000 us=1000 bytes*/
+			tx_info.crc16[0] = 0x60;
+			tx_info.crc16[1] = 0x8e;
+			/*long preamble*/
+			tx_info.is_short_preamble = false;
+			tx_info.sfd = 0xf3a0;
+		} else if (tx_info.tx_rate == ODM_RATE6M) {
+			/*l-sig[3:0] = rate = 6M = 0xb*/
+			/*l-sig[16:5] = length = 1000 bytes*/
+			/*l-sig[17] = parity = 1*/
+			tx_info.lsig[0] = 0xb;
+			tx_info.lsig[1] = 0x7d;
+			tx_info.lsig[2] = 0x2;
+		}
+		phydm_print_rate_2_buff(dm, tx_info.tx_rate, dbg_buf,
+					PHYDM_SNPRINT_SIZE);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "rate=%s, count=%d, pkt_interval=500(us), length=1000(bytes)\n",
+			 dbg_buf, tx_info.packet_count);
+
+		if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "check trx idle failed, please try again.\n");
+			return;
+		}
+
+		phydm_reset_bb_hw_cnt(dm);
+		phydm_set_pmac_tx_jgr3(dm, &tx_info, RF_PATH_A);
+
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "pmac_tx enabled, please wait for tx_cnt = %d\n",
+			 tx_info.packet_count);
+		while (1) {
+			if (phydm_is_cck_rate(dm, tx_info.tx_rate))
+				tx_cnt = odm_get_bb_reg(dm, R_0x2de4,
+							MASKLWORD);
+			else
+				tx_cnt = odm_get_bb_reg(dm, R_0x2de0,
+							MASKLWORD);
+
+			if (tx_cnt >= tx_info.packet_count || poll_cnt >= 10)
+				break;
+
+			ODM_delay_ms(100);
+			poll_cnt++;
+		}
+
+		if (tx_cnt < tx_info.packet_count)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "polling time out(1s), tx_cnt = %d\n", tx_cnt);
+		else
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "pmac_tx finished, poll_cnt = %d\n", poll_cnt);
+
+		tx_info.en_pmac_tx = false;
+		phydm_set_pmac_tx(dm, &tx_info, RF_PATH_A);
+		phydm_set_tmac_tx(dm);
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "Stop pmac_tx and turn on true mac mode.\n");
+
+		phydm_stop_ic_trx(dm, PHYDM_REVERT);
+	}
+	*_used = used;
+	*_out_len = out_len;
+}
+#endif
--- a/hal/phydm/phydm_pmac_tx_setting.h
+++ b/hal/phydm/phydm_pmac_tx_setting.h
@@ -26,38 +26,35 @@
 #ifndef __PHYDM_PMAC_TX_SETTING_H__
 #define __PHYDM_PMAC_TX_SETTING_H__

-#define PMAC_TX_SETTING_VERSION "1.3"
+/*2020.03.16 Fix TxInfo content in B mode*/
+#define PMAC_TX_SETTING_VERSION "2.1"

-/* @1 ============================================================
+/* 1 ============================================================
 * 1  Definition
 * 1 ============================================================
 */
-#define RANDOM_BY_PN32 0x12
-/* @1 ============================================================
+
+/* 1 ============================================================
 * 1  structure
 * 1 ============================================================
 */
 struct phydm_pmac_info {
-	u8 en_pmac_tx:1; /*@ disable pmac 1: enable pmac */
-	u8 mode:3; /*@ 0: Packet TX 3:Continuous TX */
-	/* @u8 Ntx:4; */
-	u8 tx_rate; /* @should be HW rate*/
-	/* @u8 TX_RATE_HEX; */
+	u8 en_pmac_tx:1; /*0: disable pmac 1: enable pmac */
+	u8 mode:3; /*0: Packet TX 3:Continuous TX */
+	u8 tx_rate; /*should be HW rate*/
 	u8 tx_sc;
-	/* @u8 bSGI:1; */
 	u8 is_short_preamble:1;
-	/* @u8 bSTBC:1; */
-	/* @u8 bLDPC:1; */
 	u8 ndp_sound:1;
-	u8 bw:3; /* @0:20 1:40 2:80Mhz */
-	u8 m_stbc; /* @bSTBC + 1 */
+	u8 bw:3; /* 0:20 1:40 2:80Mhz */
+	u8 m_stbc; /* bSTBC + 1 for WIN/CE, bSTBC for others*/
 	u16 packet_period;
 	u32 packet_count;
-	/* @u32 PacketLength; */
+	u32 packet_length;
 	u8 packet_pattern;
 	u16 sfd;
 	u8 signal_field;
 	u8 service_field;
+	u8 service_field_bit2:1;
 	u16 length;
 	u8 crc16[2];
 	u8 lsig[3];
@@ -66,7 +63,6 @@ struct phydm_pmac_info {
 	u8 vht_sig_b[4];
 	u8 vht_sig_b_crc;
 	u8 vht_delimiter[4];
-	/* @u8 mac_addr[6]; */
 };

 struct phydm_pmac_tx {
@@ -77,10 +73,9 @@ struct phydm_pmac_tx {
 	boolean cck_cont_tx;
 	boolean ofdm_cont_tx;
 	u8 path;
-	u32 tx_scailing;
 };

-/* @1 ============================================================
+/* 1 ============================================================
 * 1  enumeration
 * 1 ============================================================
 */
@@ -94,7 +89,7 @@ enum phydm_pmac_mode {
 	CCK_CARRIER_SIPPRESSION_TX
 };

-/* @1 ============================================================
+/* 1 ============================================================
 * 1  function prototype
 * 1 ============================================================
 */
@@ -106,12 +101,11 @@ void phydm_start_ofdm_cont_tx(void *dm_void);

 void phydm_stop_ofdm_cont_tx(void *dm_void);

-void phydm_set_single_tone(void *dm_void, boolean is_single_tone,
-			   boolean en_pmac_tx, u8 path);
-
 void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info,
 		       enum rf_path mpt_rf_path);

 void phydm_set_tmac_tx(void *dm_void);

+void phydm_pmac_tx_dbg(void *dm_void, char input[][16], u32 *_used,
+		       char *output, u32 *_out_len);
 #endif
--- a/hal/phydm/phydm_pre_define.h
+++ b/hal/phydm/phydm_pre_define.h
@@ -32,8 +32,8 @@
 * 1 ============================================================
 ***************************************************************/

-#define PHYDM_CODE_BASE			"PHYDM_V039"
-#define PHYDM_RELEASE_DATE		"20190410.0"
+#define PHYDM_CODE_BASE			"PHYDM_V050"
+#define PHYDM_RELEASE_DATE		"20201019.0"

 /*PHYDM API status*/
 #define	PHYDM_SET_FAIL			0
@@ -59,6 +59,7 @@
 #define MAX_PATH_NUM_8197G		2
 #define MAX_PATH_NUM_8721D		1
 #define MAX_PATH_NUM_8710C		1
+#define MAX_PATH_NUM_8723F		2

 /*@AC-IC*/
 #define MAX_PATH_NUM_8821A		1
@@ -311,6 +312,17 @@ enum phydm_ctrl_info_rate {
 	ODM_RATEVHTSS4MCS9	= 0x53,
 };

+enum phydm_legacy_spec_rate {
+	PHYDM_SPEC_RATE_6M	= 0xb,
+	PHYDM_SPEC_RATE_9M	= 0xf,
+	PHYDM_SPEC_RATE_12M	= 0xa,
+	PHYDM_SPEC_RATE_18M	= 0xe,
+	PHYDM_SPEC_RATE_24M	= 0x9,
+	PHYDM_SPEC_RATE_36M	= 0xd,
+	PHYDM_SPEC_RATE_48M	= 0x8,
+	PHYDM_SPEC_RATE_54M	= 0xc
+};
+
 #define NUM_RATE_AC_4SS (ODM_RATEVHTSS4MCS9 + 1)
 #define NUM_RATE_AC_3SS (ODM_RATEVHTSS3MCS9 + 1)
 #define NUM_RATE_AC_2SS (ODM_RATEVHTSS2MCS9 + 1)
@@ -345,7 +357,7 @@ enum phydm_ctrl_info_rate {
 /*[N-1SS]*/
 #elif (RTL8723B_SUPPORT || RTL8703B_SUPPORT || RTL8188E_SUPPORT || \
 	RTL8188F_SUPPORT || RTL8723D_SUPPORT || RTL8195A_SUPPORT ||\
-	RTL8710B_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
+	RTL8710B_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT || RTL8723F_SUPPORT)
 	#define PHY_NUM_RATE_IDX NUM_RATE_N_1SS
 #else
 	#define PHY_NUM_RATE_IDX NUM_RATE_AC_4SS
@@ -400,7 +412,8 @@ enum phydm_ic {
 	ODM_RTL8812F	=	BIT(20),
 	ODM_RTL8197G	=	BIT(21),
 	ODM_RTL8721D	=	BIT(22),
-	ODM_RTL8710C	=	BIT(23)	
+	ODM_RTL8710C	=	BIT(23),
+	ODM_RTL8723F	=	BIT(24)
 };

 #define ODM_IC_N_1SS		(ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B |\
@@ -416,7 +429,7 @@ enum phydm_ic {
 #define ODM_IC_AC_3SS		0
 #define ODM_IC_AC_4SS		(ODM_RTL8814A)

-#define ODM_IC_JGR3_1SS		0
+#define ODM_IC_JGR3_1SS		(ODM_RTL8723F)
 #define ODM_IC_JGR3_2SS		(ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)
 #define ODM_IC_JGR3_3SS		0
 #define ODM_IC_JGR3_4SS		(ODM_RTL8198F | ODM_RTL8814B)
@@ -450,7 +463,7 @@ enum phydm_ic {
 				 ODM_RTL8821C | ODM_RTL8710B | ODM_RTL8195B |\
 				 ODM_RTL8192F | ODM_RTL8721D | ODM_RTL8710C)
 #define PHYSTS_3RD_TYPE_IC	(ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8822C |\
-				 ODM_RTL8812F | ODM_RTL8197G)
+				 ODM_RTL8812F | ODM_RTL8197G | ODM_RTL8723F)
 /*@[FW Type]*/
 #define PHYDM_IC_8051_SERIES	(ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 |\
 				 ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B |\
@@ -459,12 +472,12 @@ enum phydm_ic {
 #define PHYDM_IC_3081_SERIES	(ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\
 				 ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\
 				 ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8814B |\
-				 ODM_RTL8197G)
+				 ODM_RTL8197G | ODM_RTL8723F)
 /*@[LA mode]*/
 #define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\
 				  ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\
 				  ODM_RTL8192F | ODM_RTL8822C | ODM_RTL8812F |\
-				  ODM_RTL8195B | ODM_RTL8814B | ODM_RTL8197G)
+				  ODM_RTL8195B | ODM_RTL8814B | ODM_RTL8197G | ODM_RTL8723F)
 /*@[BF]*/
 #define ODM_IC_TXBF_SUPPORT	(ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 |\
 				 ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B |\
@@ -473,7 +486,7 @@ enum phydm_ic {
 				 ODM_RTL8814B | ODM_RTL8197G)
 #define PHYDM_IC_SUPPORT_MU_BFEE (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814B |\
 				  ODM_RTL8195B | ODM_RTL8198F | ODM_RTL8822C |\
-				  ODM_RTL8812F)
+				  ODM_RTL8812F | ODM_RTL8723F)
 #define PHYDM_IC_SUPPORT_MU_BFER (ODM_RTL8822B | ODM_RTL8814B | ODM_RTL8198F |\
 				  ODM_RTL8822C | ODM_RTL8812F)

@@ -483,19 +496,43 @@ enum phydm_ic {
 #define CMN_API_SUPPORT_IC (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F |\
 			    ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8822C |\
 			    ODM_RTL8198F | ODM_RTL8812F | ODM_RTL8814B |\
-			    ODM_RTL8197G | ODM_RTL8721D | ODM_RTL8710C)
+			    ODM_RTL8197G | ODM_RTL8721D | ODM_RTL8710C | ODM_RTL8723F)
+
+/* fw offload ability*/
+#define PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD (ODM_RTL8814A | ODM_RTL8822B |\
+					   ODM_RTL8821C | ODM_RTL8822C)
+
+/* halmac offload ability*/
+#define PHYDM_IC_SUPPORT_HALMAC_PARAM_OFFLOAD (ODM_RTL8822C | ODM_RTL8812F |\
+					       ODM_RTL8814B | ODM_RTL8723F)
+
+/*[CCX]*/
+#define PHYDM_IC_SUPPORT_FAHM	(ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8198F |\
+				 ODM_RTL8814B | ODM_RTL8822C | ODM_RTL8812F |\
+				 ODM_RTL8197G | ODM_RTL8723F)
+#define PHYDM_IC_SUPPORT_IFS_CLM (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G | ODM_RTL8723F)
+
+/*[ARFR]*/
+/*for MAC HW control rate_id=0~12 and 2.4g vht mode(1ss/2ss) support*/
+#define PHYDM_IC_RATEID_IDX_TYPE2 (ODM_RTL8822B | ODM_RTL8822C | ODM_RTL8195B |\
+				  ODM_RTL8821C)

 /*@========[Compile time IC flag] ========================*/
 /*@========[AC-3/AC/N Support] ===========================*/

 #if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
-	RTL8812F_SUPPORT || RTL8197G_SUPPORT)
+	RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
 	#define PHYDM_IC_JGR3_SERIES_SUPPORT
 	#if (RTL8814B_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT)
 		#define PHYDM_IC_JGR3_80M_SUPPORT
 	#endif
 #endif

+#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT ||\
+	RTL8723F_SUPPORT)
+	#define PHYDM_IC_HALMAC_PARAM_SUPPORT
+#endif
+
 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)

 	#ifdef RTK_AC_SUPPORT
@@ -540,7 +577,7 @@ enum phydm_ic {
 	RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8881A_SUPPORT ||\
 	RTL8821A_SUPPORT || RTL8821C_SUPPORT || RTL8195A_SUPPORT ||\
 	RTL8710B_SUPPORT || RTL8195B_SUPPORT || RTL8721D_SUPPORT ||\
-	RTL8710C_SUPPORT)
+	RTL8710C_SUPPORT || RTL8723F_SUPPORT)

 	#define PHYDM_COMPILE_IC_1SS
 #endif
@@ -599,12 +636,16 @@ enum phydm_ic {
 #endif

 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8822C_SUPPORT ||\
-	RTL8812F_SUPPORT || RTL8197G_SUPPORT)
+	RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
 	#define PHYSTS_3RD_TYPE_SUPPORT
 #endif

+#ifdef PHYSTS_3RD_TYPE_SUPPORT
+	#define PHYSTS_AUTO_SWITCH_IC (ODM_RTL8822C)
+#endif
+
 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8822C_SUPPORT ||\
-	RTL8812F_SUPPORT || RTL8197G_SUPPORT)
+	RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
 	#define BB_RAM_SUPPORT
 #endif

@@ -618,14 +659,14 @@ enum phydm_ic {
 	#define CONFIG_MU_JAGUAR_2
 #endif

-#if (RTL8814B_SUPPORT || RTL8822C_SUPPORT)
+#if (RTL8814B_SUPPORT || RTL8822C_SUPPORT  || RTL8812F_SUPPORT)
 	#define CONFIG_MU_JAGUAR_3
 #endif

 #if (defined(CONFIG_MU_JAGUAR_2) || defined(CONFIG_MU_JAGUAR_3))
 	#if (RTL8814B_SUPPORT)
 		#define MU_EX_MACID		76
-	#elif (RTL8822B_SUPPORT || RTL8822C_SUPPORT)
+	#elif (RTL8822B_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT)
 		#define MU_EX_MACID		30
 	#endif
 #endif
@@ -634,11 +675,21 @@ enum phydm_ic {
 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\
 	RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8822C_SUPPORT ||\
 	RTL8198F_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT ||\
-	RTL8197G_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
+	RTL8197G_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT || RTL8723F_SUPPORT)
 #define PHYDM_COMMON_API_SUPPORT
 #endif

-#if (RTL8821C_SUPPORT || RTL8197F_SUPPORT || RTL8814B_SUPPORT)
+#define PHYDM_COMMON_API_IC (ODM_IC_JGR3_SERIES | ODM_RTL8822B  |\
+		ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8192F | ODM_RTL8195B |\
+		ODM_RTL8721D | ODM_RTL8710C)
+
+#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT || RTL8821A_SUPPORT ||\
+	RTL8812A_SUPPORT || RTL8723B_SUPPORT || RTL8703B_SUPPORT ||\
+	RTL8195A_SUPPORT || RTL8814A_SUPPORT)
+#define PHYDM_COMMON_API_NOT_SUPPORT
+#endif
+
+#if (RTL8821C_SUPPORT || RTL8197F_SUPPORT || RTL8197G_SUPPORT)
 	#define CONFIG_RFE_BY_HW_INFO
 #endif

@@ -674,6 +725,17 @@ enum phydm_ic {

 #define	LOW_BW_RATE_NUM		VHT_RATE_NUM

+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+#define	SECOND_CH_AT_LSB	2	/*@primary CH @ MSB,  SD4: HAL_PRIME_CHNL_OFFSET_UPPER*/
+#define	SECOND_CH_AT_USB	1	/*@primary CH @ LSB,   SD4: HAL_PRIME_CHNL_OFFSET_LOWER*/
+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#define	SECOND_CH_AT_LSB	2	/*@primary CH @ MSB,  SD7: HAL_PRIME_CHNL_OFFSET_UPPER*/
+#define	SECOND_CH_AT_USB	1	/*@primary CH @ LSB,   SD7: HAL_PRIME_CHNL_OFFSET_LOWER*/
+#else /*if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/
+#define	SECOND_CH_AT_LSB	1	/*@primary CH @ MSB,  SD8: HT_2NDCH_OFFSET_BELOW*/
+#define	SECOND_CH_AT_USB	2	/*@primary CH @ LSB,   SD8: HT_2NDCH_OFFSET_ABOVE*/
+#endif
+
 enum phydm_ic_ip {
 	PHYDM_IC_N		= 0,
 	PHYDM_IC_AC		= 1,
@@ -767,6 +829,13 @@ enum odm_band_type {
 #endif
 };

+enum odm_rf_band {
+	ODM_RF_BAND_2G		= 0,
+	ODM_RF_BAND_5G_LOW	= 1,
+	ODM_RF_BAND_5G_MID	= 2,
+	ODM_RF_BAND_5G_HIGH	= 3,
+};
+
 /* ODM_CMNINFO_SEC_CHNL_OFFSET */
 enum phydm_sec_chnl_offset {
 	PHYDM_DONT_CARE		= 0,
@@ -890,6 +959,26 @@ enum odm_power_voltage {
 	ODM_POWER_18V		= 0,
 	ODM_POWER_33V		= 1,
 };
+
+/* ODM_CMNINFO_ANTDIV_GPIO */
+enum odm_antdiv_gpio {
+	ANTDIV_GPIO_PA2PA4	= 0,
+	ANTDIV_GPIO_PA5PA6	= 1,
+	ANTDIV_GPIO_PA12PA13	= 2,
+	ANTDIV_GPIO_PA14PA15	= 3,
+	ANTDIV_GPIO_PA16PA17	= 4,
+	ANTDIV_GPIO_PB1PB2	= 5,
+	ANTDIV_GPIO_PB26PB29	= 6,
+	ANTDIV_GPIO_PB1PB2PB26 = 7, // add by Jiao Qi for AmebaD SP3T only
+};
+
+/* ODM_CMNINFO_PEAK_DETECT_MODE */
+enum odm_peak_detect_mode {
+	ODM_PD_DIS		= 0,
+	ODM_PD_ENG		= 1,
+	ODM_PD_ENA		= 2,
+	ODM_PD_ENALL		= 3,
+};
 #endif

 #define	PAUSE_FAIL		0
@@ -898,7 +987,9 @@ enum odm_power_voltage {
 enum odm_parameter_init {
 	ODM_PRE_SETTING		= 0,
 	ODM_POST_SETTING	= 1,
-	ODM_INIT_FW_SETTING
+	ODM_INIT_FW_SETTING	= 2,
+	ODM_PRE_RF_SET		= 3,
+	ODM_POST_RF_SET		= 4
 };

 enum phydm_pause_type {
--- a/hal/phydm/phydm_precomp.h
+++ b/hal/phydm/phydm_precomp.h
@@ -169,7 +169,9 @@
 #ifndef RTL8710C_SUPPORT
 	#define	RTL8710C_SUPPORT	0
 #endif
-
+#ifndef RTL8723F_SUPPORT
+	#define	RTL8723F_SUPPORT	0
+#endif
 #if (DM_ODM_SUPPORT_TYPE & ODM_CE) && \
 	(!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))

@@ -183,6 +185,10 @@ void phy_set_tx_power_limit(
 	u8 *channel,
 	u8 *power_limit);

+void phy_set_tx_power_limit_ex(struct dm_struct *dm, u8 regulation, u8 band,
+			       u8 bandwidth, u8 rate_section, u8 rf_path,
+			       u8 channel, s8 power_limit);
+
 enum hal_status
 rtw_phydm_fw_iqk(
 	struct dm_struct *dm,
@@ -468,6 +474,7 @@ rtw_phydm_cfg_phy_para(
 	#include "rtl8821c/halhwimg8821c_mac.h"
 	#include "rtl8821c/halhwimg8821c_bb.h"
 	#include "rtl8821c/phydm_regconfig8821c.h"
+	#include "rtl8821c/phydm_rtl8821c.h"
 	#include "halrf/rtl8821c/halrf_8821c.h"
 	#include "halrf/rtl8821c/halhwimg8821c_rf.h"
 	#include "halrf/rtl8821c/version_rtl8821c_rf.h"
@@ -593,6 +600,7 @@ rtw_phydm_cfg_phy_para(
 	#include "halrf/rtl8814b/version_rtl8814b_rf.h"
 	#include "rtl8814b/phydm_hal_api8814b.h"
 	#include "rtl8814b/version_rtl8814b.h"
+	#include "rtl8814b/phydm_extraagc8814b.h"
 	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
 		#include <hal_data.h>		/* @struct HAL_DATA_TYPE */
 		#include <rtl8814b_hal.h>	/* @RX_SMOOTH_FACTOR, reg definition and etc.*/
@@ -606,6 +614,7 @@ rtw_phydm_cfg_phy_para(
 	#include "halrf/rtl8812f/version_rtl8812f_rf.h"
 	#include "rtl8812f/phydm_hal_api8812f.h"
 	#include "rtl8812f/version_rtl8812f.h"
+	#include "rtl8812f/phydm_rtl8812f.h"
 #endif
 #if (RTL8197G_SUPPORT)
 	#include "rtl8197g/halhwimg8197g_bb.h"
@@ -616,5 +625,28 @@ rtw_phydm_cfg_phy_para(
 	#include "halrf/rtl8197g/version_rtl8197g_rf.h"
 	#include "rtl8197g/phydm_hal_api8197g.h"
 	#include "rtl8197g/version_rtl8197g.h"
+	#include "rtl8197g/phydm_rtl8197g.h"
+#endif
+#if (RTL8723F_SUPPORT)
+	#include "rtl8723f/halhwimg8723f_bb.h"
+	#include "rtl8723f/halhwimg8723f_mac.h"
+	#include "rtl8723f/phydm_regconfig8723f.h"
+	#include "halrf/rtl8723f/halrf_8723f.h"
+	#include "halrf/rtl8723f/halhwimg8723f_rf.h"
+	#include "halrf/rtl8723f/version_rtl8723f_rf.h"
+	#include "halrf/rtl8723f/halrf_iqk_8723f.h"
+	#include "halrf/rtl8723f/halrf_dpk_8723f.h"
+	#include "halrf/rtl8723f/halrf_txgapk_8723f.h"
+	#include "halrf/rtl8723f/halrf_tssi_8723f.h"
+	#include "halrf/rtl8723f/halrf_rfk_init_8723f.h"
+	#include "rtl8723f/phydm_hal_api8723f.h"
+	#include "rtl8723f/version_rtl8723f.h"
+	#include "rtl8723f/phydm_rtl8723f.h"
+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+	/* @struct HAL_DATA_TYPE */
+	#include <hal_data.h>
+	/* @RX_SMOOTH_FACTOR, reg definition and etc.*/
+	#include <rtl8723f_hal.h>
+	#endif
 #endif
 #endif /* @__ODM_PRECOMP_H__ */
--- a/hal/phydm/phydm_primary_cca.h
+++ b/hal/phydm/phydm_primary_cca.h
@@ -33,17 +33,6 @@
 /*@Definition */
 /*@============================================================*/

-#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-#define	SECOND_CH_AT_LSB	2	/*@primary CH @ MSB,  SD4: HAL_PRIME_CHNL_OFFSET_UPPER*/
-#define	SECOND_CH_AT_USB	1	/*@primary CH @ LSB,   SD4: HAL_PRIME_CHNL_OFFSET_LOWER*/
-#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-#define	SECOND_CH_AT_LSB	2	/*@primary CH @ MSB,  SD7: HAL_PRIME_CHNL_OFFSET_UPPER*/
-#define	SECOND_CH_AT_USB	1	/*@primary CH @ LSB,   SD7: HAL_PRIME_CHNL_OFFSET_LOWER*/
-#else /*if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/
-#define	SECOND_CH_AT_LSB	1	/*@primary CH @ MSB,  SD8: HT_2NDCH_OFFSET_BELOW*/
-#define	SECOND_CH_AT_USB	2	/*@primary CH @ LSB,   SD8: HT_2NDCH_OFFSET_ABOVE*/
-#endif
-
 #define	OFDMCCA_TH		500
 #define	bw_ind_bias		500
 #define	PRI_CCA_MONITOR_TIME	30
--- a/hal/phydm/phydm_psd.c
+++ b/hal/phydm/phydm_psd.c
@@ -37,6 +37,17 @@ u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi)
 	u32 psd_report = 0;

 	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		#if(RTL8723F_SUPPORT)
+		if (dm->support_ic_type & (ODM_RTL8723F)) {
+			odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff80000, psd_tone_idx & 0x7ff);
+			/*PSD trigger start*/
+			odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(16), 1);
+			ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
+			/*PSD trigger stop*/
+			odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(16), 0);
+		}
+		#endif
+		#if 0
 		odm_set_bb_reg(dm, R_0x1e8c, 0x3ff, psd_tone_idx & 0x3ff);
 		odm_set_bb_reg(dm, R_0x1e88, BIT(27) | BIT(26),
 			       psd_tone_idx >> 10);
@@ -45,6 +56,7 @@ u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi)
 		ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
 		/*PSD trigger stop*/
 		odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 0);
+		#endif
 	} else if (dm->support_ic_type & (ODM_RTL8721D |
 				ODM_RTL8710C)) {
 		odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0xfff, psd_tone_idx);
@@ -69,8 +81,16 @@ u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi)
 					    0xffffff);
 		psd_report = psd_report >> 5;
 	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		#if(RTL8723F_SUPPORT)
+		if (dm->support_ic_type & (ODM_RTL8723F)) {
+			psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
+					   	 0x1ffffff);
+		}
+		#endif
+		#if 0
 		psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
 					    0xffffff);
+		#endif
 	} else {
 		psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
 					    0xffff);
@@ -140,12 +160,21 @@ u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)
 		is_5G = 1;
 		if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
 					   ODM_RTL8197G)) {
+		#if 0
 			if (psd_fc_channel < 80)
 				ag_rf_mode_reg = 0x1;
 			else if (psd_fc_channel >= 80 && psd_fc_channel <= 140)
 				ag_rf_mode_reg = 0x3;
 			else if (psd_fc_channel > 140)
 				ag_rf_mode_reg = 0x5;
+		#endif
+		} else if (dm->support_ic_type & ODM_RTL8723F) {
+				if (psd_fc_channel < 80)
+					ag_rf_mode_reg = 0x1;
+				else if (psd_fc_channel >= 80 && psd_fc_channel <= 144)
+					ag_rf_mode_reg = 0x5;
+				else if (psd_fc_channel > 144)
+					ag_rf_mode_reg = 0x9;
 		} else if (dm->support_ic_type == ODM_RTL8721D) {
 			if (psd_fc_channel >= 36 && psd_fc_channel <= 64)
 				ag_rf_mode_reg = 0x1;
@@ -170,6 +199,7 @@ u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)
 	odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x300, is_5G);
 	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
 				   ODM_RTL8197G)) {
+		#if 0
 		/* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
 		odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x3000,
 			       dm_psd_table->psd_bw_rf_reg);
@@ -180,6 +210,28 @@ u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)
 			       ag_rf_mode_reg);
 		odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x70000,
 			       ag_rf_mode_reg);
+		#endif
+	} else if (dm->support_ic_type & ODM_RTL8723F) {
+			/* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x1c00,
+				       dm_psd_table->psd_bw_rf_reg);
+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x1c00,
+				       dm_psd_table->psd_bw_rf_reg);
+			/* Set RF ag fc mode*/
+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x30000,	1);
+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x30000,	1);
+			if(ag_rf_mode_reg == 1) {
+				odm_set_rf_reg(dm, RF_PATH_A, RF_0x19, 0xc0000, 0);
+				odm_set_rf_reg(dm, RF_PATH_B, RF_0x19, 0xc0000, 0);
+			}
+			else if(ag_rf_mode_reg == 5){
+				odm_set_rf_reg(dm, RF_PATH_A, RF_0x19, 0xc0000, 1);
+				odm_set_rf_reg(dm, RF_PATH_B, RF_0x19, 0xc0000, 1);
+			}
+			else {
+				odm_set_rf_reg(dm, RF_PATH_A, RF_0x19, 0xc0000, 2);	
+				odm_set_rf_reg(dm, RF_PATH_B, RF_0x19, 0xc0000, 2);	
+			}
 	} else {
 		/* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
 		if (dm->support_ic_type == ODM_RTL8721D) {
@@ -187,7 +239,7 @@ u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)
 				       dm_psd_table->psd_bw_rf_reg);
 #if (RTL8710C_SUPPORT == 1)
 		} else if (dm->support_ic_type == ODM_RTL8710C) {
-			config_phydm_write_rf_reg_8710c(dm, RF_PATH_A,
+			odm_set_rf_reg(dm, RF_PATH_A,
 							RF_0x18, 0x1c00,
 						dm_psd_table->psd_bw_rf_reg);
 #endif
@@ -203,10 +255,15 @@ u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)
 			odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xf0000,
 				       ag_rf_mode_reg);
 	}
-	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
+
+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES){
+		if (dm->support_ic_type & ODM_RTL8723F) {
 		PHYDM_DBG(dm, ODM_COMP_API, "0x1d70=((0x%x))\n",
 			  odm_get_bb_reg(dm, R_0x1d70, MASKDWORD));
-	else
+		PHYDM_DBG(dm, ODM_COMP_API, "RF0x19=((0x%x))\n",
+			 odm_get_rf_reg(dm, RF_PATH_A, RF_0x19, RFREG_MASK));
+		}
+	} else
 		PHYDM_DBG(dm, ODM_COMP_API, "0xc50=((0x%x))\n",
 			  odm_get_bb_reg(dm, R_0xc50, MASKDWORD));

@@ -303,17 +360,35 @@ void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,
 	dm_psd_table->sw_avg_time = sw_avg_time;
 	dm_psd_table->psd_fc_channel = channel;
 	dm_psd_table->noise_k_en = noise_k_en;
-
-	if (fft_smp_point == 128)
-		fft_smp_point_idx = 0;
-	else if (fft_smp_point == 256)
-		fft_smp_point_idx = 1;
-	else if (fft_smp_point == 512)
-		fft_smp_point_idx = 2;
-	else if (fft_smp_point == 1024)
-		fft_smp_point_idx = 3;
-
+	if (dm->support_ic_type & ODM_RTL8723F) {
+		if (fft_smp_point == 128)
+			fft_smp_point_idx = 3;
+		else if (fft_smp_point == 256)
+			fft_smp_point_idx = 2;
+		else if (fft_smp_point == 512)
+			fft_smp_point_idx = 1;
+		else if (fft_smp_point == 1024)
+			fft_smp_point_idx = 0;
+	} 
+	else {
+		if (fft_smp_point == 128)
+			fft_smp_point_idx = 0;
+		else if (fft_smp_point == 256)
+			fft_smp_point_idx = 1;
+		else if (fft_smp_point == 512)
+			fft_smp_point_idx = 2;
+		else if (fft_smp_point == 1024)
+			fft_smp_point_idx = 3;
+	}
 	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		#if (RTL8723F_SUPPORT)
+		odm_set_bb_reg(dm, R_0x1e8c, BIT(12) | BIT(11), hw_avg_time);
+		odm_set_bb_reg(dm, R_0x1e8c, BIT(14) | BIT(13),
+				       fft_smp_point_idx);
+		odm_set_bb_reg(dm, R_0x1e8c, BIT(18) | BIT(17), ant_sel);
+		odm_set_bb_reg(dm, R_0x1e88, BIT(25) | BIT(24), psd_input);
+		#else
+		#if 0
 		odm_set_bb_reg(dm, R_0x1e8c, BIT(11) | BIT(10), i_q_setting);
 		odm_set_bb_reg(dm, R_0x1e8c, BIT(13) | BIT(12), hw_avg_time);

@@ -328,6 +403,8 @@ void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,
 		}
 		odm_set_bb_reg(dm, R_0x1e8c, BIT(17) | BIT(16), ant_sel);
 		odm_set_bb_reg(dm, R_0x1e8c, BIT(23) | BIT(22), psd_input);
+		#endif
+		#endif
 	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 		odm_set_bb_reg(dm, R_0x910, BIT(11) | BIT(10), i_q_setting);
 		odm_set_bb_reg(dm, R_0x910, BIT(13) | BIT(12), hw_avg_time);
@@ -336,11 +413,12 @@ void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,
 		odm_set_bb_reg(dm, R_0x910, BIT(17) | BIT(16), ant_sel);
 		odm_set_bb_reg(dm, R_0x910, BIT(23), psd_input);
 	} else if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
-		odm_set_bb_reg(dm, 0x808, BIT(19) | BIT(18), i_q_setting);
-		odm_set_bb_reg(dm, 0x808, BIT(21) | BIT(20), hw_avg_time);
-		odm_set_bb_reg(dm, 0x808, BIT(23) | BIT(22), fft_smp_point_idx);
-		odm_set_bb_reg(dm, 0x804, BIT(5) | BIT(4), ant_sel);
-		odm_set_bb_reg(dm, 0x80C, BIT(23), psd_input);
+		odm_set_bb_reg(dm, R_0x808, BIT(19) | BIT(18), i_q_setting);
+		odm_set_bb_reg(dm, R_0x808, BIT(21) | BIT(20), hw_avg_time);
+		odm_set_bb_reg(dm, R_0x808, BIT(23) | BIT(22),
+			       fft_smp_point_idx);
+		odm_set_bb_reg(dm, R_0x804, BIT(5) | BIT(4), ant_sel);
+		odm_set_bb_reg(dm, R_0x80c, BIT(23), psd_input);

 #if 0
 	} else {	/*ODM_IC_11N_SERIES*/
@@ -360,11 +438,25 @@ void phydm_psd_init(void *dm_void)
 	dm_psd_table->psd_in_progress = false;

 	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
+		#if (RTL8723F_SUPPORT)
+		if (dm->support_ic_type & ODM_RTL8723F) {
+			dm_psd_table->psd_reg = R_0x1e8c;
+			dm_psd_table->psd_report_reg = R_0x2d90;
+
+			/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
+			dm_psd_table->psd_bw_rf_reg = 2;
+		}
+		#else
+		#if 0
 		dm_psd_table->psd_reg = R_0x1e8c;
 		dm_psd_table->psd_report_reg = R_0x2d90;

 		/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
 		dm_psd_table->psd_bw_rf_reg = 1;
+		#endif
+
+		return;
+		#endif
 	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 		dm_psd_table->psd_reg = R_0x910;
 		dm_psd_table->psd_report_reg = R_0xf44;
@@ -401,10 +493,17 @@ void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used,

 	if ((strcmp(input[1], help) == 0)) {
 		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+		#if (RTL8723F_SUPPORT)
+				if (dm->support_ic_type & ODM_RTL8723F)
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)}\n{path_sel 0~3} {0:ADC, 1:rxdata_fir_in, 2:rx_nbi_nf_stage2} {CH} {noise_k}\n\n");
+		#endif
+		#if 0
 		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
 			PDM_SNPF(out_len, used, output + used, out_len - used,
 				 "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4) 2048 4096}\n{path_sel 0~3} {0:ADC, 1:rxdata_fir_in, 2:rx_nbi_nf_stage2} {CH} {noise_k}\n\n");
 		else
+		#endif
 		#endif
 			PDM_SNPF(out_len, used, output + used, out_len - used,
 				 "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n");
@@ -418,9 +517,8 @@ void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used,

 	if (var1[0] == 0) {
 		for (i = 1; i < 10; i++) {
-			if (input[i + 1])
-				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
-					     &var1[i]);
+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
+				     &var1[i]);
 		}
 		PDM_SNPF(out_len, used, output + used, out_len - used,
 			 "sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n",
--- a/hal/phydm/phydm_psd.h
+++ b/hal/phydm/phydm_psd.h
@@ -27,7 +27,9 @@
 #define __PHYDMPSD_H__

 /*@#define PSD_VERSION	"1.0"*/ /*@2016.09.22  Dino*/
-#define PSD_VERSION "1.1" /*@2016.10.07  Dino, Add Option for PSD Tone index Selection */
+/*@2016.10.07  Dino, Add Option for PSD Tone index Selection */
+/*@2019.04.26  Early return & "IF0" for JGR3 ICs */
+#define PSD_VERSION "1.2"

 #ifdef CONFIG_PSD_TOOL

--- a/hal/phydm/phydm_rainfo.c
+++ b/hal/phydm/phydm_rainfo.c
@@ -51,6 +51,19 @@ boolean phydm_is_cck_rate(void *dm_void, u8 rate)
 	return ((rate & 0x7f) <= ODM_RATE11M) ? true : false;
 }

+u8 phydm_legacy_rate_2_spec_rate(void *dm_void, u8 rate)
+{
+	u8 rate_idx = 0x0;
+	u8 legacy_spec_rate_t[8] = {PHYDM_SPEC_RATE_6M, PHYDM_SPEC_RATE_9M,
+				    PHYDM_SPEC_RATE_12M, PHYDM_SPEC_RATE_18M,
+				    PHYDM_SPEC_RATE_24M, PHYDM_SPEC_RATE_36M,
+				    PHYDM_SPEC_RATE_48M, PHYDM_SPEC_RATE_54M};
+
+	if ((rate >= ODM_RATE6M) && (rate <= ODM_RATE54M))
+		rate_idx = rate - ODM_RATE6M;
+	return legacy_spec_rate_t[rate_idx];
+}
+
 u8 phydm_rate_2_rate_digit(void *dm_void, u8 rate)
 {
 	u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54};
@@ -125,10 +138,8 @@ void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used,
 	u8 phydm_h2c_id = 0;

 	for (i = 0; i < 8; i++) {
-		if (input[i + 1]) {
-			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
-			input_idx++;
-		}
+		PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
+		input_idx++;
 	}

 	if (input_idx == 0)
@@ -158,7 +169,7 @@ void phydm_fw_fix_rate(void *dm_void, u8 en, u8 macid, u8 bw, u8 rate)

 	if (dm->support_ic_type & PHYDM_IC_8051_SERIES) {
 		reg_u32_tmp = (bw << 24) | (rate << 16) | (macid << 8) | en;
-		odm_set_bb_reg(dm, R_0x4a0, MASKDWORD, reg_u32_tmp);
+		odm_set_mac_reg(dm, R_0x4a0, MASKDWORD, reg_u32_tmp);

 	} else {
 		if (en == 1)
@@ -166,9 +177,9 @@ void phydm_fw_fix_rate(void *dm_void, u8 en, u8 macid, u8 bw, u8 rate)
 		else
 			reg_u32_tmp = 0x40000000;
 		if (dm->support_ic_type & ODM_RTL8814B)
-			odm_set_bb_reg(dm, R_0x448, MASKDWORD, reg_u32_tmp);
+			odm_set_mac_reg(dm, R_0x448, MASKDWORD, reg_u32_tmp);
 		else
-			odm_set_bb_reg(dm, R_0x450, MASKDWORD, reg_u32_tmp);
+			odm_set_mac_reg(dm, R_0x450, MASKDWORD, reg_u32_tmp);
 	}
 	if (en == 1) {
 		PHYDM_DBG(dm, ODM_COMP_API,
@@ -190,11 +201,11 @@ void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
 	char help[] = "-h";
 	u32 var[5] = {0};
 	u8 macid = 0, bw = 0, rate = 0;
+	u8 tx_cls_en = 0, tx_cls_th = 0, tmp = 0;
 	u8 i = 0;

 	for (i = 0; i < 5; i++) {
-		if (input[i + 1])
-			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]);
+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]);
 	}

 	if ((strcmp(input[1], help) == 0)) {
@@ -206,7 +217,12 @@ void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
 			 "{2} {en} {macid} {bw} {rate}: fw fix rate\n");
 		PDM_SNPF(out_len, used, output + used, out_len - used,
 			 "{3} {en}: Dynamic RRSR\n");
-
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{4} {0:pkt RA, 1:TBTT RA, 100:query RA mode}\n");
+#ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+			 "{5} {0:dis, 1:en}{th; 255:auto, xx:dB}: Tx CLS\n");
+#endif
 	} else if (var[0] == 1) { /*@Adjust PCR offset*/

 		if (var[1] == 100) {
@@ -237,10 +253,46 @@ void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
 			 var[1], macid, bw, rate);

 		phydm_fw_fix_rate(dm, (u8)var[1], macid, bw, rate);
-	} else if (var[0] == 3) { /*@FW fix rate*/
+	} else if (var[0] == 3) { /*@Dynamic RRSR*/
 		ra_tab->dynamic_rrsr_en = (boolean)var[1];
 		PDM_SNPF(out_len, used, output + used, out_len - used,
 			 "[Dynamic RRSR] enable=%d", ra_tab->dynamic_rrsr_en);
+	} else if (var[0] == 4) { /*@RA trigger mode*/
+		if (var[1] == 0 || var[1] == 1)
+			ra_tab->ra_trigger_mode = (u8)var[1];
+		PDM_SNPF(out_len, used, output + used, out_len - used,
+		"[RA trigger] mode=%d\n", ra_tab->ra_trigger_mode);
+#ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
+	} else if (var[0] == 5) { /*@Tx Collision Detection*/
+		tx_cls_en = (u8)var[1];
+		ra_tab->ra_tx_cls_th = (u8)var[2];
+		tmp = (u8)var[2];
+		tx_cls_th = (tmp < 50) ? 0 : (tmp > 81) ? 31 : tmp - 50;
+		if (tx_cls_en) {
+			odm_set_bb_reg(dm, R_0x8f8, BIT(16), 1);
+			if (ra_tab->ra_tx_cls_th != 255) {
+				phydm_tx_collsion_th_set(dm, tx_cls_th,
+							 tx_cls_th);
+			}
+
+		} else {
+			odm_set_bb_reg(dm, R_0x8f8, BIT(16), 0);
+		}
+
+		if (tx_cls_en & ra_tab->ra_tx_cls_th != 255) {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[Tx Collision Detec] {en, th}={%d, %d}\n",
+				 tx_cls_en, tx_cls_th + 50);
+		} else if (tx_cls_en & ra_tab->ra_tx_cls_th == 255) {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[Tx Collision Detec] {en, th}={%d, auto}\n",
+				 tx_cls_en);
+		} else {
+			PDM_SNPF(out_len, used, output + used, out_len - used,
+				 "[Tx Collision Detec] {en, th}={%d, xx}\n",
+				 tx_cls_en);
+		}
+#endif
 	} else {
 		PDM_SNPF(out_len, used, output + used, out_len - used,
 			 "[Set] Error\n");
@@ -249,9 +301,31 @@ void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
 	*_out_len = out_len;
 }

+void phydm_ra_mask_report_h2c_trigger(void *dm_void,
+				      struct ra_mask_rpt_trig *trig_rpt)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_tab = &dm->dm_ra_table;
+
+	phydm_fw_trace_en_h2c(dm, true, 1, 2, trig_rpt->macid);
+
+	trig_rpt->ra_mask_rpt_stamp = ra_tab->ra_mask_rpt_stamp;
+}
+void phydm_ra_mask_report_c2h_result(void *dm_void, struct ra_mask_rpt *rpt)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_tab = &dm->dm_ra_table;
+	u8 i = 0;
+
+	rpt->ra_mask_rpt_stamp = ra_tab->ra_mask_rpt_stamp;
+
+	odm_move_memory(dm, &rpt->ra_mask_buf[0], &ra_tab->ra_mask_buf[0], 8);
+}
+
 void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_tab = &dm->dm_ra_table;
 	u8 mode = cmd_buf[0]; /*Retry Penalty, NH, NL*/
 	u8 i;

@@ -314,6 +388,9 @@ void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
 			for (i = 4; i <= 11; i++)
 				PHYDM_DBG(dm, DBG_FW_TRACE, "RAMASK =  0x%x\n",
 					  cmd_buf[i]);
+
+			odm_move_memory(dm, &ra_tab->ra_mask_buf[0], &cmd_buf[4], 8);
+			ra_tab->ra_mask_rpt_stamp++;
 		} else {
 			PHYDM_DBG(dm, DBG_FW_TRACE,
 				  "%5s  %x%x  %x%x  %x%x  %x%x\n", "RA Mask:",
@@ -353,9 +430,8 @@ void phydm_ra_dynamic_retry_count(void *dm_void)
 	if (!(dm->support_ability & ODM_BB_DYNAMIC_ARFR))
 		return;

-#if 0
 	/*PHYDM_DBG(dm, DBG_RA, "dm->pre_b_noisy = %d\n", dm->pre_b_noisy );*/
-#endif
+
 	if (dm->pre_b_noisy != dm->noisy_decision) {
 		if (dm->noisy_decision) {
 			PHYDM_DBG(dm, DBG_DYN_ARFR, "Noisy Env. RA fallback\n");
@@ -399,10 +475,11 @@ void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size)
 	u8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx);
 	u8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx);

-	PHYDM_SNPRINTF(buf, buf_size, "( %s%s%s%s%d%s%s)",
+	PHYDM_SNPRINTF(buf, buf_size, "( %s%s%s%s%s%d%s%s)",
 		       (vht_en && (rate_ss == 1)) ? "VHT 1ss " : "",
 		       (vht_en && (rate_ss == 2)) ? "VHT 2ss " : "",
 		       (vht_en && (rate_ss == 3)) ? "VHT 3ss " : "",
+		       (vht_en && (rate_ss == 4)) ? "VHT 4ss " : "",
 		       (rate_idx >= ODM_RATEMCS0) ? "MCS " : "",
 		       rate_digit,
 		       (b_sgi) ? "-S" : " ",
@@ -421,6 +498,7 @@ void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
 	u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
 	u8 rate_order;
 	u8 gid_index = 0;
+	u8 txcls_rate = 0;
 	char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};

 	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
@@ -429,10 +507,16 @@ void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
 	sta = dm->phydm_sta_info[macid];
 	#endif

-	if (cmd_len >= 7) {
+	if (cmd_len == 7) {
 		ra_ratio = cmd_buf[5];
 		curr_bw = cmd_buf[6];
 		PHYDM_DBG(dm, DBG_RA, "[%d] PER=%d\n", macid, ra_ratio);
+	} else if (cmd_len == 8) {
+		ra_ratio = cmd_buf[5];
+		curr_bw = cmd_buf[6];
+		txcls_rate = cmd_buf[7];
+		PHYDM_DBG(dm, DBG_RA, "[%d] PER=%d TxCLS=%d\n", macid, ra_ratio,
+			  txcls_rate);
 	}

 	if (cmd_buf[3] != 0) {
@@ -450,13 +534,15 @@ void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
 			PHYDM_DBG(dm, DBG_RA, "Try rate\n");
 	}
 	phydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE);
-	PHYDM_DBG(dm, DBG_RA, "Tx Rate=%s (%d)", dbg_buf, rate);
+	PHYDM_DBG(dm, DBG_RA, "Tx Rate=%s (%d)\n", dbg_buf, rate);

 #ifdef MU_EX_MACID
 	if (macid >= 128 && macid < (128 + MU_EX_MACID)) {
 		gid_index = macid - 128;
 		ra_tab->mu1_rate[gid_index] = rate;
 	}
+	if (macid >= ODM_ASSOCIATE_ENTRY_NUM)
+		return;
 #endif
 	if (is_sta_active(sta)) {
 		sta->ra_info.curr_tx_rate = rate;
@@ -487,13 +573,6 @@ void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)

 void odm_ra_post_action_on_assoc(void *dm_void)
 {
-#if 0
-	struct dm_struct	*dm = (struct dm_struct *)dm_void;
-
-	dm->h2c_rarpt_connect = 1;
-	phydm_rssi_monitor_check(dm);
-	dm->h2c_rarpt_connect = 0;
-#endif
 }

 void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc,
@@ -857,10 +936,14 @@ u8 phydm_get_tx_stream_num(void *dm_void, enum rf_type type)
 u64 phydm_get_bb_mod_ra_mask(void *dm_void, u8 sta_idx)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct phydm_iot_center	*iot_table = &dm->iot_table;
 	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
 	struct ra_sta_info *ra = NULL;
 	enum channel_width bw = 0;
 	enum wireless_set wrls_mode = 0;
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	struct rtl8192cd_priv *priv = dm->priv;
+#endif
 	u8 tx_stream_num = 1;
 	u8 rssi_lv = 0;
 	u64 ra_mask_bitmap = 0;
@@ -972,8 +1055,21 @@ u64 phydm_get_bb_mod_ra_mask(void *dm_void, u8 sta_idx)

 	PHYDM_DBG(dm, DBG_RA, "Mod by mode=0x%llx\n", ra_mask_bitmap);

+#if ((DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
+	if (priv->pshare->veriwave_sta_num > 0) {
+		PHYDM_DBG(dm, DBG_RA, "Mod by RSSI=0x%llx\n", ra_mask_bitmap);
+		return ra_mask_bitmap;
+	}
+#endif
 	/*@[Modify RA Mask by RSSI level]*/
 	if (wrls_mode != WIRELESS_CCK) {
+		if (iot_table->patch_id_40010700) {
+			ra_mask_bitmap &= (rssi_lv == 0 ?
+					  0xffffffffffffffff :
+					  0xfffffffffffffff0);
+			return ra_mask_bitmap;
+		}
+
 		if (rssi_lv == 0)
 			ra_mask_bitmap &= 0xffffffffffffffff;
 		else if (rssi_lv == 1)
@@ -1127,14 +1223,21 @@ u8 phydm_get_rate_id(void *dm_void, u8 sta_idx)
 			else if (tx_stream_num == 4)
 				rate_id_idx = PHYDM_ARFR6_AC_4SS;
 		} else {
-			if (tx_stream_num == 1)
-				rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
-			else if (tx_stream_num == 2)
-				rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
-			else if (tx_stream_num == 3)
+			if (tx_stream_num == 1) {
+				if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2)
+					rate_id_idx = PHYDM_TYPE2_ARFR5_AC_2G_1SS;
+				else
+					rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
+			} else if (tx_stream_num == 2) {
+				if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2)
+					rate_id_idx = PHYDM_TYPE2_ARFR3_AC_2G_2SS;
+				else
+					rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
+			} else if (tx_stream_num == 3) {
 				rate_id_idx = PHYDM_ARFR4_AC_3SS;
-			else if (tx_stream_num == 4)
+			} else if (tx_stream_num == 4) {
 				rate_id_idx = PHYDM_ARFR6_AC_4SS;
+			}
 		}
 	} else {
 		PHYDM_DBG(dm, DBG_RA, "[Warrning] No rate_id is found\n");
@@ -1146,6 +1249,24 @@ u8 phydm_get_rate_id(void *dm_void, u8 sta_idx)
 	return rate_id_idx;
 }

+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+void phydm_ra_mode_selection(void *dm_void, u8 mode)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct ra_table *ra_tab = &dm->dm_ra_table;
+	u8 pre_mode = ra_tab->ra_trigger_mode; /* 0:pkt RA, 1:TBTT RA */
+
+	if (mode >= 2) {
+		PHYDM_DBG(dm, DBG_RA, "RA mode selection Fail\n");
+	} else {
+		ra_tab->ra_trigger_mode = mode;
+		PHYDM_DBG(dm, DBG_RA, "RA mode, 0:pkt RA, 1:TBTT RA\n");
+		PHYDM_DBG(dm, DBG_RA, "PreMode=%d,CurMode=%d\n", pre_mode,
+			  mode);
+	}
+}
+#endif
+
 void phydm_ra_h2c(void *dm_void, u8 sta_idx, u8 dis_ra, u8 dis_pt,
 		  u8 no_update_bw, u8 init_ra_lv, u64 ra_mask)
 {
@@ -1153,6 +1274,7 @@ void phydm_ra_h2c(void *dm_void, u8 sta_idx, u8 dis_ra, u8 dis_pt,
 	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
 	struct ra_sta_info *ra = NULL;
 	u8 h2c_val[H2C_MAX_LENGTH] = {0};
+	u8 rate_id_idx = 0;

 	if (is_sta_active(sta)) {
 		ra = &sta->ra_info;
@@ -1164,14 +1286,30 @@ void phydm_ra_h2c(void *dm_void, u8 sta_idx, u8 dis_ra, u8 dis_pt,

 	PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__);
 	PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id);
+	

-	if (dm->is_disable_power_training)
-		dis_pt = true;
-	else if (!dm->is_disable_power_training)
+#ifdef PHYDM_POWER_TRAINING_SUPPORT
+	if ((dm->support_ability & ODM_BB_PWR_TRAIN) && !dm->is_disable_power_training)
 		dis_pt = false;
+	else 
+		dis_pt = true;
+	
+#else
+	dis_pt= true;
+#endif
+
+	rate_id_idx = ra->rate_id;
+
+	/*for compatibility issues with FW RA [PHYDM-405]*/
+	if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2) {
+		if (rate_id_idx == PHYDM_TYPE2_ARFR5_AC_2G_1SS) 
+			rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
+		else if (rate_id_idx == PHYDM_TYPE2_ARFR3_AC_2G_2SS)
+			rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
+	}

 	h2c_val[0] = sta->mac_id;
-	h2c_val[1] = (ra->rate_id & 0x1f) | ((init_ra_lv & 0x3) << 5) |
+	h2c_val[1] = (rate_id_idx & 0x1f) | ((init_ra_lv & 0x3) << 5) |
 		     (ra->is_support_sgi << 7);
 	h2c_val[2] = (u8)((ra->ra_bw_mode) | (((sta->ldpc_en) ? 1 : 0) << 2) |
 			  ((no_update_bw & 0x1) << 3) |
@@ -1878,6 +2016,21 @@ void phydm_rrsr_en(void *dm_void, boolean en_rrsr)
 	ra_tab->dynamic_rrsr_en = en_rrsr;
 }

+void phydm_arfr_table_init(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+	if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2) {
+		/*ARFR table3(2.4g ac 2ss) for rate_id = 16*/
+		odm_set_mac_reg(dm, R_0x494, MASKDWORD, 0xfe01f015);
+		odm_set_mac_reg(dm, R_0x498, MASKDWORD, 0x40000000);
+
+		/*ARFR table5(2.4g ac 1ss) for rate_id = 18*/
+		odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0x3ff015);
+		odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x40000000);
+	}
+}
+
 void phydm_ra_info_init(void *dm_void)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
@@ -1888,14 +2041,15 @@ void phydm_ra_info_init(void *dm_void)
 	ra_tab->ra_th_ofst = 0;
 	ra_tab->ra_ofst_direc = 0;
 	ra_tab->rrsr_val_init = odm_get_mac_reg(dm, R_0x440, MASKDWORD);
-	ra_tab->dynamic_rrsr_en = true;
-
+	ra_tab->dynamic_rrsr_en = false;
+	ra_tab->ra_trigger_mode = 1; // default TBTT RA
+	ra_tab->ra_tx_cls_th = 255;
 #if (RTL8822B_SUPPORT == 1)
 	if (dm->support_ic_type == ODM_RTL8822B) {
 		u32 ret_value;

-		ret_value = odm_get_bb_reg(dm, R_0x4c8, MASKBYTE2);
-		odm_set_bb_reg(dm, R_0x4cc, MASKBYTE3, (ret_value - 1));
+		ret_value = odm_get_mac_reg(dm, R_0x4c8, MASKBYTE2);
+		odm_set_mac_reg(dm, R_0x4cc, MASKBYTE3, (ret_value - 1));
 	}
 #endif

@@ -1907,6 +2061,8 @@ void phydm_ra_info_init(void *dm_void)
 	phydm_ra_dynamic_rate_id_init(dm);
 	#endif

+	phydm_arfr_table_init(dm);
+
 	phydm_rate_adaptive_mask_init(dm);
 }

--- a/hal/phydm/phydm_rainfo.h
+++ b/hal/phydm/phydm_rainfo.h
@@ -26,8 +26,8 @@
 #ifndef __PHYDMRAINFO_H__
 #define __PHYDMRAINFO_H__

-/* 2019.3.5 add dynamic RRSR en API*/
-#define RAINFO_VERSION "8.2"
+/* 2020.08.05 Fix ARFR bug due to rate_id error for 2.4G VHT mode*/
+#define RAINFO_VERSION "8.8"

 #define	FORCED_UPDATE_RAMASK_PERIOD	5

@@ -41,6 +41,9 @@
 #define	RA_RETRY_LIMIT_LOW	4
 #define	RA_RETRY_LIMIT_HIGH	32

+#define PHYDM_IS_LEGACY_RATE(rate) ((rate <= ODM_RATE54M) ? true : false)
+#define PHYDM_IS_CCK_RATE(rate) ((rate <= ODM_RATE11M) ? true : false)
+
 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
 	#define	FIRST_MACID	1
 #else
@@ -107,6 +110,16 @@ enum phydm_rateid_idx {
 	PHYDM_ARFR6_AC_4SS	= 16
 };

+/*ARFR4(0x49c/0x4a0) can not be used because FW BT would use.*/
+enum phydm_rateid_idx_type_2 {
+	PHYDM_TYPE2_AC_2SS		= 9,
+	PHYDM_TYPE2_AC_1SS		= 10,
+	PHYDM_TYPE2_MIX_1SS		= 11,
+	PHYDM_TYPE2_MIX_2SS		= 12,
+	PHYDM_TYPE2_ARFR3_AC_2G_2SS	= 16, /*0x494/0x498*/
+	PHYDM_TYPE2_ARFR5_AC_2G_1SS	= 18  /*0x4a4/0x4a8*/
+};
+
 enum phydm_qam_order {
 	PHYDM_QAM_CCK	= 0,
 	PHYDM_QAM_BPSK	= 1,
@@ -189,6 +202,8 @@ struct ra_table {
 	u32	rrsr_val_init; /*0x440*/
 	u32	rrsr_val_curr; /*0x440*/
 	boolean dynamic_rrsr_en;
+	u8	ra_trigger_mode; /*0: pkt RA, 1: TBTT RA*/
+	u8	ra_tx_cls_th;	 /*255: auto, xx: in dB*/
 #if 0	/*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
 	u8	per_rate_retrylimit_20M[PHY_NUM_RATE_IDX];
 	u8	per_rate_retrylimit_40M[PHY_NUM_RATE_IDX];
@@ -199,6 +214,18 @@ struct ra_table {
 	u8	ldpc_thres; /* @if RSSI > ldpc_th => switch from LPDC to BCC */
 	void (*record_ra_info)(void *dm_void, u8 macid,
 			       struct cmn_sta_info *sta, u64 ra_mask);
+	u8	ra_mask_rpt_stamp;
+	u8 	ra_mask_buf[8];
+};
+
+struct ra_mask_rpt_trig {
+	u8			ra_mask_rpt_stamp;
+	u8			macid;
+};
+
+struct ra_mask_rpt {
+	u8			ra_mask_rpt_stamp;
+	u8 			ra_mask_buf[8];
 };

 /* @1 ============================================================
@@ -213,6 +240,10 @@ boolean phydm_is_ht_rate(void *dm_void, u8 rate);

 boolean phydm_is_vht_rate(void *dm_void, u8 rate);

+u8 phydm_legacy_rate_2_spec_rate(void *dm_void, u8 rate);
+
+u8 phydm_rate_2_rate_digit(void *dm_void, u8 rate);
+
 u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type);

 u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate);
@@ -223,6 +254,11 @@ void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used,
 void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
 		    u32 *_out_len);

+void phydm_ra_mask_report_h2c_trigger(void *dm_void,
+				      struct ra_mask_rpt_trig *trig_rpt);
+
+void phydm_ra_mask_report_c2h_result(void *dm_void, struct ra_mask_rpt *rpt);
+
 void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);

 void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component);
@@ -289,4 +325,9 @@ void phydm_ra_mask_watchdog(void *dm_void);
 void odm_refresh_basic_rate_mask(
 	void *dm_void);
 #endif
+
+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+void phydm_ra_mode_selection(void *dm_void, u8 mode);
+#endif
+
 #endif /*@#ifndef __PHYDMRAINFO_H__*/
--- a/hal/phydm/phydm_regtable.h
+++ b/hal/phydm/phydm_regtable.h
@@ -1,5 +1,30 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2019  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ *
+ *****************************************************************************/
+
 #define R_0x0 0x0
 #define R_0x00 0x00
+#define R_0x08 0x08
 #define R_0x0106 0x0106
 #define R_0x0140 0x0140
 #define R_0x0144 0x0144
@@ -7,11 +32,23 @@
 #define R_0x040 0x040
 #define R_0x10 0x10
 #define R_0x100 0x100
+#define R_0x1000 0x1000
+#define R_0x1008 0x1008
 #define R_0x1038 0x1038
 #define R_0x103c 0x103c
 #define R_0x1040 0x1040
 #define R_0x1048 0x1048
+#define R_0x1064 0x1064
 #define R_0x1080 0x1080
+#define R_0x10d8 0x10d8
+#define R_0x10dc 0x10dc
+#define R_0x1200 0x1200
+#define R_0x1204 0x1204
+#define R_0x1208 0x1208
+#define R_0x1210 0x1210
+#define R_0x1214 0x1214
+#define R_0x1218 0x1218
+#define R_0x121c 0x121c
 #define R_0x14 0x14
 #define R_0x14c0 0x14c0
 #define R_0x14c4 0x14c4
@@ -65,6 +102,7 @@
 #define R_0x1918 0x1918
 #define R_0x191c 0x191c
 #define R_0x1928 0x1928
+#define R_0x1938 0x1938
 #define R_0x1940 0x1940
 #define R_0x1944 0x1944
 #define R_0x1950 0x1950
@@ -86,12 +124,20 @@
 #define R_0x19f8 0x19f8
 #define R_0x1a00 0x1a00
 #define R_0x1a04 0x1a04
+#define R_0x1a08 0x1a08
+#define R_0x1a0c 0x1a0c
 #define R_0x1a10 0x1a10
 #define R_0x1a14 0x1a14
+#define R_0x1a18 0x1a18
+#define R_0x1a1c 0x1a1c
 #define R_0x1a20 0x1a20
 #define R_0x1a24 0x1a24
 #define R_0x1a28 0x1a28
 #define R_0x1a2c 0x1a2c
+#define R_0x1a30 0x1a30
+#define R_0x1a34 0x1a34
+#define R_0x1a38 0x1a38
+#define R_0x1a48 0x1a48
 #define R_0x1a5c 0x1a5c
 #define R_0x1a70 0x1a70
 #define R_0x1a74 0x1a74
@@ -111,6 +157,7 @@
 #define R_0x1acc 0x1acc
 #define R_0x1ad0 0x1ad0
 #define R_0x1ad4 0x1ad4
+#define R_0x1ae0 0x1ae0
 #define R_0x1ae8 0x1ae8
 #define R_0x1aec 0x1aec
 #define R_0x1b00 0x1b00
@@ -167,6 +214,7 @@
 #define R_0x1bb8 0x1bb8
 #define R_0x1bbc 0x1bbc
 #define R_0x1bc0 0x1bc0
+#define R_0x1bc4 0x1bc4
 #define R_0x1bc8 0x1bc8
 #define R_0x1bca 0x1bca
 #define R_0x1bcb 0x1bcb
@@ -177,6 +225,7 @@
 #define R_0x1bd6 0x1bd6
 #define R_0x1bd8 0x1bd8
 #define R_0x1bdc 0x1bdc
+#define R_0x1be3 0x1be3
 #define R_0x1be4 0x1be4
 #define R_0x1be8 0x1be8
 #define R_0x1beb 0x1beb
@@ -197,10 +246,12 @@
 #define R_0x1c3c 0x1c3c
 #define R_0x1c64 0x1c64
 #define R_0x1c68 0x1c68
+#define R_0x1c6c 0x1c6c
 #define R_0x1c74 0x1c74
 #define R_0x1c78 0x1c78
 #define R_0x1c7c 0x1c7c
 #define R_0x1c80 0x1c80
+#define R_0x1c8c 0x1c8c
 #define R_0x1c90 0x1c90
 #define R_0x1c94 0x1c94
 #define R_0x1c98 0x1c98
@@ -209,8 +260,10 @@
 #define R_0x1ca4 0x1ca4
 #define R_0x1cb0 0x1cb0
 #define R_0x1cb8 0x1cb8
+#define R_0x1cbc 0x1cbc
 #define R_0x1cc0 0x1cc0
 #define R_0x1cd0 0x1cd0
+#define R_0x1cd8 0x1cd8
 #define R_0x1ce4 0x1ce4
 #define R_0x1ce8 0x1ce8
 #define R_0x1cec 0x1cec
@@ -224,6 +277,7 @@
 #define R_0x1d2c 0x1d2c
 #define R_0x1d30 0x1d30
 #define R_0x1d3c 0x1d3c
+#define R_0x1d40 0x1d40
 #define R_0x1d44 0x1d44
 #define R_0x1d48 0x1d48
 #define R_0x1d58 0x1d58
@@ -247,6 +301,10 @@
 #define R_0x1e40 0x1e40
 #define R_0x1e44 0x1e44
 #define R_0x1e48 0x1e48
+#define R_0x1e4c 0x1e4c
+#define R_0x1e50 0x1e50
+#define R_0x1e54 0x1e54
+#define R_0x1e58 0x1e58
 #define R_0x1e5c 0x1e5c
 #define R_0x1e60 0x1e60
 #define R_0x1e64 0x1e64
@@ -254,29 +312,54 @@
 #define R_0x1e6c 0x1e6c
 #define R_0x1e70 0x1e70
 #define R_0x1e7c 0x1e7c
+#define R_0x1e80 0x1e80
 #define R_0x1e84 0x1e84
 #define R_0x1e88 0x1e88
 #define R_0x1e8c 0x1e8c
 #define R_0x1ea4 0x1ea4
 #define R_0x1eb4 0x1eb4
+#define R_0x1eb8 0x1eb8
+#define R_0x1ed4 0x1ed4
+#define R_0x1ed8 0x1ed8
+#define R_0x1edc 0x1edc
+#define R_0x1ee0 0x1ee0
+#define R_0x1ee4 0x1ee4
 #define R_0x1ee8 0x1ee8
 #define R_0x1eec 0x1eec
 #define R_0x1ef0 0x1ef0
 #define R_0x1ef4 0x1ef4
+#define R_0x1ef8 0x1ef8
 #define R_0x1efc 0x1efc
+#define R_0x1f80 0x1f80
+#define R_0x1f98 0x1f98
 #define R_0x24 0x24
 #define R_0x28 0x28
+#define R_0x2a00 0x2a00
+#define R_0x2a04 0x2a04
+#define R_0x2a08 0x2a08
+#define R_0x2a24 0x2a24
+#define R_0x2a38 0x2a38
+#define R_0x2a3c 0x2a3c
+#define R_0x2a44 0x2a44
+#define R_0x2aa0 0x2aa0
+#define R_0x2aa8 0x2aa8
+#define R_0x2aac 0x2aac
+#define R_0x2ad0 0x2ad0
 #define R_0x2c 0x2c
 #define R_0x28a4 0x28a4
+#define R_0x28bc 0x28bc
 #define R_0x2c04 0x2c04
 #define R_0x2c08 0x2c08
 #define R_0x2c0c 0x2c0c
 #define R_0x2c10 0x2c10
 #define R_0x2c14 0x2c14
+#define R_0x2c18 0x2c18
+#define R_0x2c1c 0x2c1c
 #define R_0x2c20 0x2c20
 #define R_0x2c2c 0x2c2c
 #define R_0x2c30 0x2c30
 #define R_0x2c34 0x2c34
+#define R_0x2c54 0x2c54
 #define R_0x2d00 0x2d00
 #define R_0x2d04 0x2d04
 #define R_0x2d08 0x2d08
@@ -288,6 +371,8 @@
 #define R_0x2d44 0x2d44
 #define R_0x2d48 0x2d48
 #define R_0x2d4c 0x2d4c
+#define R_0x2d6c 0x2d6c
+#define R_0x2d84 0x2d84
 #define R_0x2d88 0x2d88
 #define R_0x2d90 0x2d90
 #define R_0x2d9c 0x2d9c
@@ -299,6 +384,15 @@
 #define R_0x2de8 0x2de8
 #define R_0x2e00 0x2e00
 #define R_0x2e20 0x2e20
+#define R_0x2e60 0x2e60
+#define R_0x2e64 0x2e64
+#define R_0x2e68 0x2e68
+#define R_0x2e6c 0x2e6c
+#define R_0x2e70 0x2e70
+#define R_0x2e74 0x2e74
+#define R_0x2e78 0x2e78
+#define R_0x2e7c 0x2e7c
+#define R_0x2e80 0x2e80
 #define R_0x300 0x300
 #define R_0x38 0x38
 #define R_0x3a00 0x3a00
@@ -386,12 +480,64 @@
 #define R_0x42 0x42
 #define R_0x430 0x430
 #define R_0x434 0x434
+#define R_0x42b0 0x42b0
+#define R_0x42b4 0x42b4
+#define R_0x42f0 0x42f0
+#define R_0x4300 0x4300
+#define R_0x4304 0x4304
+#define R_0x4308 0x4308
+#define R_0x430c 0x430c
+#define R_0x4310 0x4310
+#define R_0x4314 0x4314
+#define R_0x4318 0x4318
+#define R_0x431c 0x431c
+#define R_0x4320 0x4320
+#define R_0x4324 0x4324
+#define R_0x4328 0x4328
+#define R_0x432c 0x432c
+#define R_0x4330 0x4330
+#define R_0x4334 0x4334
+#define R_0x4338 0x4338
+#define R_0x433c 0x433c
+#define R_0x4340 0x4340
+#define R_0x4344 0x4344
+#define R_0x4348 0x4348
+#define R_0x434c 0x434c
+#define R_0x4350 0x4350
+#define R_0x4354 0x4354
+#define R_0x4358 0x4358
+#define R_0x435c 0x435c
+#define R_0x4360 0x4360
+#define R_0x4364 0x4364
+#define R_0x4368 0x4368
+#define R_0x436c 0x436c
+#define R_0x4370 0x4370
+#define R_0x4374 0x4374
+#define R_0x4378 0x4378
+#define R_0x437c 0x437c
+#define R_0x4380 0x4380
+#define R_0x4384 0x4384
+#define R_0x4388 0x4388
+#define R_0x438c 0x438c
+#define R_0x4390 0x4390
+#define R_0x4394 0x4394
+#define R_0x4398 0x4398
+#define R_0x439c 0x439c
+#define R_0x43a0 0x43a0
+#define R_0x43a4 0x43a4
+#define R_0x43a8 0x43a8
+#define R_0x43ac 0x43ac
+#define R_0x43b0 0x43b0
+#define R_0x43b4 0x43b4
+#define R_0x43b8 0x43b8
 #define R_0x44 0x44
 #define R_0x440 0x440
 #define R_0x444 0x444
 #define R_0x448 0x448
 #define R_0x450 0x450
 #define R_0x454 0x454
+#define R_0x494 0x494
+#define R_0x498 0x498
 #define R_0x49c 0x49c
 #define R_0x4a0 0x4a0
 #define R_0x4a4 0x4a4
@@ -465,6 +611,7 @@
 #define R_0x6a0 0x6a0
 #define R_0x6d8 0x6d8
 #define R_0x6dc 0x6dc
+#define R_0x6f8 0x6f8
 #define R_0x70 0x70
 #define R_0x74 0x74
 #define R_0x700 0x700
@@ -567,6 +714,7 @@
 #define R_0x974 0x974
 #define R_0x978 0x978
 #define R_0x97c 0x97c
+#define R_0x980 0x980
 #define R_0x988 0x988
 #define R_0x98c 0x98c
 #define R_0x990 0x990
@@ -581,6 +729,7 @@
 #define R_0x9b8 0x9b8
 #define R_0x9cc 0x9cc
 #define R_0x9d0 0x9d0
+#define R_0x9d8 0x9d8
 #define R_0x9e4 0x9e4
 #define R_0x9e8 0x9e8
 #define R_0x9f0 0x9f0
@@ -617,6 +766,7 @@
 #define R_0xaac 0xaac
 #define R_0xab4 0xab4
 #define R_0xabc 0xabc
+#define R_0xac 0xac
 #define R_0xac8 0xac8
 #define R_0xacc 0xacc
 #define R_0xad0 0xad0
@@ -695,7 +845,9 @@
 #define R_0xc1c 0xc1c
 #define R_0xc20 0xc20
 #define R_0xc24 0xc24
+#define R_0xc2c 0xc2c
 #define R_0xc30 0xc30
+#define R_0xc34 0xc34
 #define R_0xc38 0xc38
 #define R_0xc3c 0xc3c
 #define R_0xc40 0xc40
@@ -764,6 +916,7 @@
 #define R_0xdb4 0xdb4
 #define R_0xdb8 0xdb8
 #define R_0xdbc 0xdbc
+#define R_0xdc 0xdc
 #define R_0xdcc 0xdcc
 #define R_0xdd0 0xdd0
 #define R_0xdd4 0xdd4
@@ -833,7 +986,10 @@
 #define R_0xf0c 0xf0c
 #define R_0xf10 0xf10
 #define R_0xf14 0xf14
+#define R_0xf18 0xf18
+#define R_0xf1c 0xf1c
 #define R_0xf20 0xf20
+#define R_0xf24 0xf24
 #define R_0xf2c 0xf2c
 #define R_0xf30 0xf30
 #define R_0xf34 0xf34
@@ -855,6 +1011,7 @@
 #define R_0xf90 0xf90
 #define R_0xf94 0xf94
 #define R_0xf98 0xf98
+#define R_0xf9c 0xf9c
 #define R_0xfa0 0xfa0
 #define R_0xfa4 0xfa4
 #define R_0xfa8 0xfa8
@@ -872,6 +1029,7 @@
 #define RF_0x0 0x0
 #define RF_0x00 0x00
 #define RF_0x08 0x08
+#define RF_0x09 0x09
 #define RF_0x0c 0x0c
 #define RF_0x0d 0x0d
 #define RF_0x1 0x1
@@ -881,6 +1039,9 @@
 #define RF_0x1bf0 0x1bf0
 #define RF_0x2 0x2
 #define RF_0x3 0x3
+#define RF_0x1e 0x1e
+#define RF_0x1f 0x1f
+#define RF_0x20 0x20
 #define RF_0x30 0x30
 #define RF_0x31 0x31
 #define RF_0x32 0x32
@@ -891,6 +1052,7 @@
 #define RF_0x4 0x4
 #define RF_0x42 0x42
 #define RF_0x43 0x43
+#define RF_0x5 0x5
 #define RF_0x51 0x51
 #define RF_0x52 0x52
 #define RF_0x53 0x53
@@ -901,12 +1063,15 @@
 #define RF_0x58 0x58
 #define RF_0x5c 0x5c
 #define RF_0x5d 0x5d
+#define RF_0x5e 0x5e
+#define RF_0x60 0x60
 #define RF_0x61 0x61
 #define RF_0x63 0x63
 #define RF_0x64 0x64
 #define RF_0x65 0x65
 #define RF_0x66 0x66
 #define RF_0x67 0x67
+#define RF_0x6d 0x6d
 #define RF_0x6e 0x6e
 #define RF_0x6f 0x6f
 #define RF_0x75 0x75
@@ -922,11 +1087,17 @@
 #define RF_0x85 0x85
 #define RF_0x86 0x86
 #define RF_0x87 0x87
+#define RF_0x88 0x88
 #define RF_0x8a 0x8a
+#define RF_0x8b 0x8b
 #define RF_0x8c 0x8c
 #define RF_0x8d 0x8d
 #define RF_0x8f 0x8f
+#define RF_0x92 0x92
 #define RF_0x93 0x93
+#define RF_0x9e 0x9e
+#define RF_0x9f 0x9f
+#define RF_0xa3 0xa3
 #define RF_0xa9 0xa9
 #define RF_0xae 0xae
 #define RF_0xb0 0xb0
@@ -936,6 +1107,7 @@
 #define RF_0xbc 0xbc
 #define RF_0xbe 0xbe
 #define RF_0xc4 0xc4
+#define RF_0xc8 0xc8
 #define RF_0xc9 0xc9
 #define RF_0xca 0xca
 #define RF_0xcc 0xcc
--- a/hal/phydm/phydm_rssi_monitor.c
+++ b/hal/phydm/phydm_rssi_monitor.c
@@ -80,7 +80,7 @@ void phydm_rssi_monitor_h2c(void *dm_void, u8 macid)
 	h2c[4] = (ra_t->ra_th_ofst & 0x7f) |
 		     ((ra_t->ra_ofst_direc & 0x1) << 7);
 	h2c[5] = 0;
-	h2c[6] = 0;
+	h2c[6] = ((ra_t->ra_trigger_mode) << 2);

 	PHYDM_DBG(dm, DBG_RSSI_MNTR, "PHYDM h2c[0x42]=0x%x %x %x %x %x %x %x\n",
 		  h2c[6], h2c[5], h2c[4], h2c[3], h2c[2], h2c[1], h2c[0]);
@@ -95,6 +95,22 @@ void phydm_rssi_monitor_h2c(void *dm_void, u8 macid)
 	}
 }

+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+void phydm_sta_rssi_init(void *dm_void, u8 macid, u8 init_rssi)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	struct cmn_sta_info *sta = NULL;
+	struct rssi_info *rssi_t = NULL;
+
+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
+
+	sta = dm->phydm_sta_info[macid];
+	rssi_t = &sta->rssi_stat;
+
+	rssi_t->rssi_acc = (init_rssi << RSSI_MA);
+	rssi_t->rssi = init_rssi;
+}
+#endif
 void phydm_calculate_rssi_min_max(void *dm_void)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
@@ -133,6 +149,10 @@ void phydm_calculate_rssi_min_max(void *dm_void)
 	}
 	dm->pre_rssi_min = dm->rssi_min;

+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+	if (dm->number_linked_client == 0)
+		return;
+#endif
 	dm->rssi_max = (u8)rssi_max_tmp;
 	dm->rssi_min = (u8)rssi_min_tmp;
 }
--- a/hal/phydm/phydm_rssi_monitor.h
+++ b/hal/phydm/phydm_rssi_monitor.h
@@ -51,5 +51,8 @@
 void phydm_rssi_monitor_check(void *dm_void);

 void phydm_rssi_monitor_init(void *dm_void);
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+void phydm_sta_rssi_init(void *dm_void, u8 macid, u8 init_rssi);
+#endif

 #endif
--- a/hal/phydm/phydm_soml.c
+++ b/hal/phydm/phydm_soml.c
@@ -312,6 +312,9 @@ void phydm_soml_debug(void *dm_void, char input[][16], u32 *_used,
 	u32 dm_value[10] = {0};
 	u8 i = 0, input_idx = 0;

+	if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML))
+		return;
+
 	for (i = 0; i < 5; i++) {
 		if (input[i + 1]) {
 			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
@@ -560,10 +563,6 @@ void phydm_adsl_init_state(void *dm_void)
 	}

 	soml_tab->is_soml_method_enable = 1;
-	#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-	odm_set_mac_reg(dm, R_0x608, BIT(8), 1);
-	/*RCR accepts CRC32-Error packets*/
-	#endif
 	soml_tab->get_stats = false;
 	soml_tab->soml_state_cnt++;
 	next_on_off = (soml_tab->soml_on_off == SOML_ON) ? SOML_ON : SOML_OFF;
@@ -679,10 +678,6 @@ void phydm_adsl_decision_state(void *dm_void)
 		pr_debug("%s: mismatch IC type %x\n", __func__,
 			 dm->support_ic_type);
 	soml_tab->get_stats = false;
-	#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-	odm_set_mac_reg(dm, R_0x608, BIT(8), 0);
-	/* NOT Accept CRC32 Error packets. */
-	#endif
 	PHYDM_DBG(dm, DBG_ADPTV_SOML, "[Decisoin state ]\n");
 	phydm_soml_statistics(dm, soml_tab->soml_on_off);
 	if (*dm->channel <= 14) {
@@ -1149,6 +1144,9 @@ void phydm_set_adsl_val(void *dm_void, u32 *val_buf, u8 val_len)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;

+	if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML))
+		return;
+
 	if (val_len != 1) {
 		PHYDM_DBG(dm, ODM_COMP_API, "[Error][ADSL]Need val_len=1\n");
 		return;
@@ -1163,6 +1161,9 @@ void phydm_soml_crc_acq(void *dm_void, u8 rate_id, boolean crc32, u32 length)
 	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
 	u8 offset = 0;

+	if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML))
+		return;
+
 	if (!soml_tab->get_stats)
 		return;
 	if (length < 1400)
@@ -1207,6 +1208,8 @@ void phydm_soml_bytes_acq(void *dm_void, u8 rate_id, u32 length)
 	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
 	u8 offset = 0;

+	if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML))
+		return;

 	if (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS31) {
 		offset = rate_id - ODM_RATEMCS0;
@@ -1270,6 +1273,9 @@ void phydm_adaptive_soml_timers(void *dm_void, u8 state)
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	struct adaptive_soml *soml_tab = &dm->dm_soml_table;

+	if (!(dm->support_ic_type & PHYDM_ADAPTIVE_SOML_IC))
+		return;
+
 #if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
 	struct rtl8192cd_priv *priv = dm->priv;

@@ -1301,6 +1307,10 @@ void phydm_adaptive_soml_init(void *dm_void)
 		return;
 	}
 #endif
+
+	if (!(dm->support_ic_type & PHYDM_ADAPTIVE_SOML_IC))
+		return;
+
 	PHYDM_DBG(dm, DBG_ADPTV_SOML, "%s\n", __func__);

 	soml_tab->soml_state_cnt = 0;
--- a/hal/phydm/phydm_types.h
+++ b/hal/phydm/phydm_types.h
@@ -158,6 +158,46 @@ enum rt_spinlock_type {

 	#define	phydm_timer_list	_RT_TIMER

+	// for power limit table
+	enum odm_pw_lmt_regulation_type {
+		PW_LMT_REGU_FCC = 0,
+		PW_LMT_REGU_ETSI = 1,
+		PW_LMT_REGU_MKK = 2,
+		PW_LMT_REGU_WW13 = 3,
+		PW_LMT_REGU_IC = 4,
+		PW_LMT_REGU_KCC = 5,
+		PW_LMT_REGU_ACMA = 6,
+		PW_LMT_REGU_CHILE = 7,
+		PW_LMT_REGU_UKRAINE = 8,
+		PW_LMT_REGU_MEXICO = 9,
+		PW_LMT_REGU_CN = 10
+	};
+
+	enum odm_pw_lmt_band_type {
+		PW_LMT_BAND_2_4G = 0,
+		PW_LMT_BAND_5G = 1
+	};
+
+	enum odm_pw_lmt_bandwidth_type {
+		PW_LMT_BW_20M = 0,
+		PW_LMT_BW_40M = 1,
+		PW_LMT_BW_80M = 2,
+		PW_LMT_BW_160M = 3
+	};
+
+	enum odm_pw_lmt_ratesection_type {
+		PW_LMT_RS_CCK = 0,
+		PW_LMT_RS_OFDM = 1,
+		PW_LMT_RS_HT = 2,
+		PW_LMT_RS_VHT = 3
+	};
+
+	enum odm_pw_lmt_rfpath_type {
+		PW_LMT_PH_1T = 0,
+		PW_LMT_PH_2T = 1,
+		PW_LMT_PH_3T = 2,
+		PW_LMT_PH_4T = 3
+	};

 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
 	#include "../typedef.h"
@@ -180,7 +220,9 @@ enum rt_spinlock_type {
 	#define	boolean	bool

 	#define	phydm_timer_list	timer_list
-
+	#if defined(__ECOS)
+	#define s64	s8Byte
+	#endif 
 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)

 	#include <asm/byteorder.h>
@@ -251,6 +293,47 @@ enum rt_spinlock_type {

 	#define	phydm_timer_list	rtw_timer_list

+	// for power limit table
+	enum odm_pw_lmt_regulation_type {
+		PW_LMT_REGU_FCC = 0,
+		PW_LMT_REGU_ETSI = 1,
+		PW_LMT_REGU_MKK = 2,
+		PW_LMT_REGU_WW13 = 3,
+		PW_LMT_REGU_IC = 4,
+		PW_LMT_REGU_KCC = 5,
+		PW_LMT_REGU_ACMA = 6,
+		PW_LMT_REGU_CHILE = 7,
+		PW_LMT_REGU_UKRAINE = 8,
+		PW_LMT_REGU_MEXICO = 9,
+		PW_LMT_REGU_CN = 10
+	};
+
+	enum odm_pw_lmt_band_type {
+		PW_LMT_BAND_2_4G = 0,
+		PW_LMT_BAND_5G = 1
+	};
+
+	enum odm_pw_lmt_bandwidth_type {
+		PW_LMT_BW_20M = 0,
+		PW_LMT_BW_40M = 1,
+		PW_LMT_BW_80M = 2,
+		PW_LMT_BW_160M = 3
+	};
+
+	enum odm_pw_lmt_ratesection_type {
+		PW_LMT_RS_CCK = 0,
+		PW_LMT_RS_OFDM = 1,
+		PW_LMT_RS_HT = 2,
+		PW_LMT_RS_VHT = 3
+	};
+
+	enum odm_pw_lmt_rfpath_type {
+		PW_LMT_PH_1T = 0,
+		PW_LMT_PH_2T = 1,
+		PW_LMT_PH_3T = 2,
+		PW_LMT_PH_4T = 3
+	};
+
 #elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
 	#define	boolean	bool
 	#define true	_TRUE
--- a/hal/phydm/rtl8822b/phydm_hal_api8822b.c
+++ b/hal/phydm/rtl8822b/phydm_hal_api8822b.c
@@ -137,8 +137,8 @@ void phydm_8822b_type18_rfe(struct dm_struct *dm, u8 channel)
 			if (dm->rx_ant_status == BB_PATH_AB ||
 			    dm->tx_ant_status == BB_PATH_AB) {
 				/* 2TX or 2RX */
-				odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa501);
-				odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa501);
+				odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0x0501);
+				odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0x0501);
 			} else if (dm->rx_ant_status == dm->tx_ant_status) {
 				/* TXA+RXA or TXB+RXB */
 				odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa500);
@@ -775,7 +775,7 @@ void phydm_ccapar_by_rfe_8822b(struct dm_struct *dm)
 	} else {
 		odm_move_memory(dm, cca_ifem, cca_ifem_ccut, 12 * 4);
 	}
-	PHYDM_DBG(dm, ODM_PHY_CONFIG, "Update CCA para for Ccut\n");
+	PHYDM_DBG(dm, ODM_PHY_CONFIG, "Update CCA para for C-cart\n");

 	if (central_ch_8822b <= 14) {
 		if (dm->rx_ant_status == BB_PATH_A ||
@@ -835,7 +835,7 @@ void phydm_ccapar_by_rfe_8822b(struct dm_struct *dm)
 	if ((*dm->band_width == CHANNEL_WIDTH_20) &&
 	    (((*dm->channel >= 52) && (*dm->channel <= 64)) ||
 	     ((*dm->channel >= 100) && (*dm->channel <= 144))))
-		odm_set_bb_reg(dm, 0x838, 0xf0, 0x4);
+		odm_set_bb_reg(dm, 0x838, 0xf0, 0x5);
 	PHYDM_DBG(dm, ODM_PHY_CONFIG, "(Pkt%d, Intf%d, RFE%d), col=%d\n",
 		  dm->package_type, dm->support_interface, dm->rfe_type, col);
 }
@@ -1659,7 +1659,7 @@ config_phydm_switch_band_8822b(struct dm_struct *dm,
 			/*@CCA mask = 13.6us*/
 			odm_set_bb_reg(dm, R_0x814, 0x0000FC00, 34);
 		else
-			/*@default value*/
+			/*@default value = 6us*/
 			odm_set_bb_reg(dm, R_0x814, 0x0000FC00, 15);
 #endif

@@ -1829,7 +1829,9 @@ config_phydm_switch_channel_8822b(struct dm_struct *dm,
 	}
 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
 	/*@Make protection*/
-	if (central_ch == 165 && bw_8822b != CHANNEL_WIDTH_20)
+	if (central_ch == 165 &&
+	    bw_8822b != CHANNEL_WIDTH_20 &&
+	    !(*dm->mp_mode))
 		config_phydm_switch_bandwidth_8822b(dm, 0, CHANNEL_WIDTH_20);
 #endif
 	central_ch_8822b = central_ch;
@@ -2017,6 +2019,7 @@ config_phydm_switch_bandwidth_8822b(struct dm_struct *dm,
 				    u8 primary_ch_idx,
 				    enum channel_width bw)
 {
+	struct phydm_api_stuc *api = &dm->api_table;
 	u32 rf_reg18, val32;
 	boolean rf_reg_status = true;
 	u8 rfe_type = dm->rfe_type;
@@ -2043,6 +2046,7 @@ config_phydm_switch_bandwidth_8822b(struct dm_struct *dm,
 		bandwidth = CHANNEL_WIDTH_20;
 #endif
 	bw_8822b = bandwidth;
+	api->pri_ch_idx = primary_ch_idx;
 	rf_reg18 = config_phydm_read_rf_reg_8822b(dm, RF_PATH_A, 0x18,
 						  RFREG_MASK);
 	rf_reg_status = rf_reg_status &
@@ -2262,6 +2266,12 @@ config_phydm_switch_bandwidth_8822b(struct dm_struct *dm,
 		phydm_spur_calibration_8822b(dm);
 	}

+	/*fix bw setting*/
+	#ifdef CONFIG_BW_INDICATION
+	if (!(*dm->mp_mode))
+		phydm_bw_fixed_setting(dm);
+	#endif
+
 	/* Toggle RX path to avoid RX dead zone issue */
 	odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x0);
 	odm_set_bb_reg(dm, R_0x808, MASKBYTE0, (dm->rx_ant_status |
--- a/hal/phydm/txbf/haltxbfjaguar.c
+++ b/hal/phydm/txbf/haltxbfjaguar.c
@@ -93,10 +93,9 @@ void hal_txbf_jaguar_download_ndpa(
 #endif
 	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);

-	if (idx == 0)
-		head_page = 0xFE;
-	else
-		head_page = 0xFE;
+	/* if (idx == 0) head_page = 0xFE; */
+	/* else	head_page = 0xFE;*/
+	head_page = 0xFE;

 	phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy);

--- a/hal/phydm/txbf/phydm_hal_txbf_api.c
+++ b/hal/phydm/txbf/phydm_hal_txbf_api.c
@@ -17,7 +17,7 @@
 #include "phydm_precomp.h"

 #if (defined(CONFIG_BB_TXBF_API))
-#if (RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1 ||\
+#if (RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8812F_SUPPORT == 1 ||\
 	RTL8822C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
 /*@Add by YuChen for 8822B MU-MIMO API*/

@@ -121,7 +121,6 @@ u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num)
 	if (dm->support_ic_type & ODM_RTL8814A)
 		nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num);
 	else
-#endif
 		nr_index = tx_bf_nr(1, bfer_str_num);

 	switch (nr_index) {
@@ -141,6 +140,9 @@ u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num)
 		ndp_tx_rate = ODM_MGN_MCS8;
 		break;
 	}
+#else
+	ndp_tx_rate = ODM_MGN_MCS8;
+#endif

 	return ndp_tx_rate;
 }
@@ -155,7 +157,6 @@ u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num)
 	if (dm->support_ic_type & ODM_RTL8814A)
 		nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num);
 	else
-#endif
 		nr_index = tx_bf_nr(1, bfer_str_num);

 	switch (nr_index) {
@@ -175,6 +176,9 @@ u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num)
 		ndp_tx_rate = ODM_MGN_VHT2SS_MCS0;
 		break;
 	}
+#else
+	ndp_tx_rate = ODM_MGN_VHT2SS_MCS0;
+#endif

 	return ndp_tx_rate;
 }
@@ -338,16 +342,16 @@ void phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)

 			/* logic mapping */
 			/* TX BF logic map and TX path en for Nsts = 1~4 */
-			odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0xffff);
+			//odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0xffff);
 			/*verification path-AC*/
-			odm_set_bb_reg(dm, R_0x1e30, 0xffffffff, 0xe4e4e4e4);
+			//odm_set_bb_reg(dm, R_0x1e30, 0xffffffff, 0xe4e4e4e4);
 		} else {
 			/*@Disable BB TxBF ant mapping register*/
 			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
 			odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
 			/*@1SS~4ss A, AB, ABC, ABCD*/
-			odm_set_bb_reg(dm, R_0x820, 0xffff, 0xf731);
-			odm_set_bb_reg(dm, R_0x1e2c, 0xffffffff, 0xe4240400);
+			//odm_set_bb_reg(dm, R_0x820, 0xffff, 0xf731);
+			//odm_set_bb_reg(dm, R_0x1e2c, 0xffffffff, 0xe4240400);
 		}
 	}
 #endif
@@ -472,12 +476,27 @@ void phydm_mu_rsoml_init(void *dm_void)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	struct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3;
+	u32 val = 0;

-	PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] %s - cnt init\n", __func__);
+	PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] %s\n", __func__);
+
+	/*OFDM Tx*/
+	val = odm_get_bb_reg(dm, R_0x820, MASKDWORD);
+	rateinfo->tx_path_en_ofdm_2sts = (u8)((val & 0xf0) >> 4);
+	rateinfo->tx_path_en_ofdm_1sts = (u8)(val & 0xf);
+	/*OFDM Rx*/
+	rateinfo->rx_path_en_ofdm = (u8)odm_get_bb_reg(dm, R_0x824, 0xf0000);

 	rateinfo->enable = 1;
 	rateinfo->mu_ratio_th = 30;
 	rateinfo->pre_mu_ratio = 0;
+	rateinfo->mu_set_trxpath = 0;
+	rateinfo->mu_been_iot = 0;
+
+	PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] %s tx1ss=%d, tx2ss=%d, rx=%d\n",
+		  __func__, rateinfo->tx_path_en_ofdm_1sts,
+		  rateinfo->tx_path_en_ofdm_2sts, rateinfo->rx_path_en_ofdm);
+
 	phydm_mu_rsoml_reset(dm);
 }

@@ -485,12 +504,19 @@ void phydm_mu_rsoml_decision(void *dm_void)
 {
 	struct dm_struct *dm = (struct dm_struct *)dm_void;
 	struct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3;
+	struct phydm_iot_center	*iot_table = &dm->iot_table;
 	u8 offset = 0;
 	u32 mu_ratio = 0;
 	u32 su_pkt = 0;
 	u32 mu_pkt = 0;
 	u32 total_pkt = 0;

+	if (rateinfo->tx_path_en_ofdm_2sts != 3 ||
+	    rateinfo->rx_path_en_ofdm != 3) {
+		PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] Init Not 2T2R 22CE\n");
+		return;
+	}
+
 	PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML Decision eanble: %d\n",
 		  rateinfo->enable);

@@ -512,28 +538,46 @@ void phydm_mu_rsoml_decision(void *dm_void)
 		  mu_ratio, total_pkt);

 	if (mu_ratio > rateinfo->mu_ratio_th &&
-	    rateinfo->pre_mu_ratio > rateinfo->mu_ratio_th)
+	    rateinfo->pre_mu_ratio > rateinfo->mu_ratio_th) {
 		PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML status remain\n");
-	else if (mu_ratio <= rateinfo->mu_ratio_th &&
-		 rateinfo->pre_mu_ratio <= rateinfo->mu_ratio_th)
+	} else if (mu_ratio <= rateinfo->mu_ratio_th &&
+		 rateinfo->pre_mu_ratio <= rateinfo->mu_ratio_th) {
 		PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML status remain\n");
-	else if (mu_ratio > rateinfo->mu_ratio_th)
+	} else if (mu_ratio > rateinfo->mu_ratio_th) {
 		odm_set_bb_reg(dm, R_0xc00, BIT(26), 0);
-	else
+		PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML OFF\n");
+	} else {
 		odm_set_bb_reg(dm, R_0xc00, BIT(26), 1);
+		PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML ON\n");
+	}
+
+	PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] set_trxpath=%d, patch_10120200=%d\n",
+		  rateinfo->mu_set_trxpath, iot_table->patch_id_10120200);
+	if (rateinfo->mu_set_trxpath && iot_table->patch_id_10120200) {
+		if (mu_ratio > rateinfo->mu_ratio_th) {
+			phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_A,
+					   BB_PATH_AUTO);
+			PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] 22C IOT 2T1R\n");
+			rateinfo->mu_been_iot = 1;
+		} else {
+			phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB,
+					   BB_PATH_AUTO);
+			PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] 22C IOT 2T2R\n");
+			rateinfo->mu_been_iot = 0;
+		}
+	} else if (rateinfo->mu_been_iot == 1) {
+		if (odm_get_bb_reg(dm, R_0x824, 0xf0000) == 1) {
+			phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB,
+					   BB_PATH_AUTO);
+			PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] 22C IOT Restore\n");
+			rateinfo->mu_been_iot = 0;
+		}
+	}

 	rateinfo->pre_mu_ratio = mu_ratio;
-
 	phydm_mu_rsoml_reset(dm);
 }

-void phydm_txbf_avoid_hang(void *dm_void)
-{
-	struct dm_struct *dm = (struct dm_struct *)dm_void;
-
-	/* avoid CCK CCA hang when the BF mode */
-	odm_set_bb_reg(dm, R_0x1e6c, 0x100000, 0x1);
-}

 #if (RTL8814B_SUPPORT == 1)
 void phydm_txbf_80p80_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
@@ -621,6 +665,21 @@ void phydm_txbf_80p80_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
 #endif
 #endif /*PHYSTS_3RD_TYPE_IC*/

+void phydm_txbf_avoid_hang(void *dm_void)
+{
+	struct dm_struct *dm = (struct dm_struct *)dm_void;
+	
+	/* avoid CCK CCA hang when the BF mode */
+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT	
+	odm_set_bb_reg(dm, R_0x1e6c, 0x100000, 0x1);
+#endif
+
+	/* avoid CCK CCA hang when the BFee mode for 92F */
+#if (RTL8192F_SUPPORT == 1)
+	odm_set_bb_reg(dm, R_0xa70, 0xffff0000, 0x80ff);
+#endif
+}
+
 void phydm_bf_debug(void *dm_void, char input[][16], u32 *_used, char *output,
 		    u32 *_out_len)
 {
@@ -634,11 +693,12 @@ void phydm_bf_debug(void *dm_void, char input[][16], u32 *_used, char *output,
 			 "{BF ver1 :0}, {NO applyV:0; applyV:1; default:2}\n");
 		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
 			 "{MU RSOML:1}, {MU enable:1/0}, {MU Ratio:40}\n");
+		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
+			 "{MU TRxPath:2}, {TRxPath enable:1/0}\n");
 		return;
 	}
 	for (i = 0; i < 3; i++) {
-		if (input[i + 1])
-			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
 	}
 	if (var1[0] == 0) {
 		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
@@ -683,6 +743,16 @@ void phydm_bf_debug(void *dm_void, char input[][16], u32 *_used, char *output,
 			 "[MU RSOML] enable= %d, MU ratio TH= %d\n",
 			 bfinfo->enable, bfinfo->mu_ratio_th);
 		#endif
+	} else if (var1[0] == 2) {
+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
+		struct dm_struct *dm = (struct dm_struct *)dm_void;
+		struct phydm_bf_rate_info_jgr3 *bfinfo = &dm->bf_rate_info_jgr3;
+
+		bfinfo->mu_set_trxpath = (u8)var1[1];
+		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
+			 "[MU TRxPath] mu_set_trxpath = %d\n",
+			 bfinfo->mu_set_trxpath);
+		#endif
 	}
 }

--- a/hal/phydm/txbf/phydm_hal_txbf_api.h
+++ b/hal/phydm/txbf/phydm_hal_txbf_api.h
@@ -44,8 +44,7 @@ u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num);
 #endif

 #if (RTL8822B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8192F_SUPPORT == 1 ||\
-	RTL8814B_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
-
+	RTL8814B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 || RTL8812F_SUPPORT == 1)
 u8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *throughput,
 				       u8 total_bfee_num, u8 *tx_rate);
 u8 phydm_get_ndpa_rate(void *dm_void);
@@ -66,6 +65,11 @@ struct phydm_bf_rate_info_jgr3 {
 	u32			pre_mu_ratio;
 	u16			num_mu_vht_pkt[VHT_RATE_NUM];
 	u16			num_qry_vht_pkt[VHT_RATE_NUM];
+	boolean			mu_set_trxpath;
+	u8			tx_path_en_ofdm_1sts;
+	u8			tx_path_en_ofdm_2sts;
+	u8			rx_path_en_ofdm;
+	boolean			mu_been_iot;
 };

 /*this function is only used for BFer*/