RinCat/RTL88x2BU-Linux-Driver
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Update to 5.13.1 from upstream

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Rin Cat (鈴猫)
2021-12-04 07:42:09 -05:00
parent aab1daf818
commit c0e109d401
352 changed files with 50307 additions and 18938 deletions
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4
hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.c
View File

@@ -751,6 +751,7 @@ enum halmac_ret_status
init_protocol_cfg_8822b(struct halmac_adapter *adapter)
{
u32 value32;
u8 value8;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
@@ -773,6 +774,9 @@ init_protocol_cfg_8822b(struct halmac_adapter *adapter)
HALMAC_REG_W8(REG_FAST_EDCA_BEBK_SETTING, WLAN_FAST_EDCA_BE_TH);
HALMAC_REG_W8(REG_FAST_EDCA_BEBK_SETTING + 2, WLAN_FAST_EDCA_BK_TH);
value8 = HALMAC_REG_R8(REG_INIRTS_RATE_SEL);
HALMAC_REG_W8(REG_INIRTS_RATE_SEL, value8 | BIT(5));
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;

4
hal/halmac/halmac_88xx/halmac_8822b/halmac_phy_8822b.c
View File

@@ -83,6 +83,10 @@ struct halmac_intf_phy_para pcie_gen1_phy_param_8822b[] = {
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_ALL,
HALMAC_INTF_PHY_PLATFORM_ASUS},
{0x001B, 0xF029,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_ALL,
HALMAC_INTF_PHY_PLATFORM_LENOVO_V540},
{0x0020, 0x94FF,
HALMAC_IP_INTF_PHY,
HALMAC_INTF_PHY_CUT_C,

2
hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.c
View File

@@ -211,7 +211,7 @@ static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_CARDEMU_8822B[] = {
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(3), 0},
HALMAC_PWR_CMD_WRITE, 0xFF, 0xC4},
{0x001F,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK,

2
hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.h
View File

@@ -21,7 +21,7 @@
#if HALMAC_8822B_SUPPORT
#define HALMAC_8822B_PWR_SEQ_VER "V31"
#define HALMAC_8822B_PWR_SEQ_VER "V35"
extern struct halmac_wlan_pwr_cfg *card_en_flow_8822b[];
extern struct halmac_wlan_pwr_cfg *card_dis_flow_8822b[];

176
hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c
View File

@@ -19,6 +19,58 @@
#include "halmac_init_88xx.h"
#if HALMAC_88XX_SUPPORT
/**
* start_dpk_88xx() -trigger FW DPK
* @adapter : the adapter of halmac
* Author : Yong-Ching Lin/KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
start_dpk_88xx(struct halmac_adapter *adapter)
{
u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
u16 seq_num = 0;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
struct halmac_h2c_header_info hdr_info;
enum halmac_cmd_process_status *proc_status;
proc_status = &adapter->halmac_state.dpk_state.proc_status;
if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_NO_DLFW;
if (adapter->fw_ver.h2c_version < 15)
return HALMAC_RET_FW_NO_SUPPORT;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
PLTFM_MSG_TRACE("[TRACE]Wait event(dpk)\n");
return HALMAC_RET_BUSY_STATE;
}
*proc_status = HALMAC_CMD_PROCESS_SENDING;
hdr_info.sub_cmd_id = SUB_CMD_ID_DPK;
hdr_info.content_size = 1;
hdr_info.ack = 1;
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
adapter->halmac_state.dpk_state.seq_num = seq_num;
status = send_h2c_pkt_88xx(adapter, h2c_buf);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]send h2c pkt fail!!\n");
reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_DPK);
return status;
}
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* start_iqk_88xx() -trigger FW IQK
@@ -163,6 +215,34 @@ get_iqk_status_88xx(struct halmac_adapter *adapter,
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status
get_dpk_status_88xx(struct halmac_adapter *adapter,
enum halmac_cmd_process_status *proc_status, u8 *data,
u32 *size)
{
struct halmac_dpk_state *state = &adapter->halmac_state.dpk_state;
*proc_status = adapter->halmac_state.dpk_state.proc_status;
if (!data)
return HALMAC_RET_NULL_POINTER;
if (!size)
return HALMAC_RET_NULL_POINTER;
if (*proc_status == HALMAC_CMD_PROCESS_DONE) {
if (*size < state->data_size) {
*size = state->data_size;
return HALMAC_RET_BUFFER_TOO_SMALL;
}
*size = state->data_size;
PLTFM_MEMCPY(data, state->data, *size);
}
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status
get_pwr_trk_status_88xx(struct halmac_adapter *adapter,
enum halmac_cmd_process_status *proc_status)
@@ -300,6 +380,102 @@ get_h2c_ack_iqk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status
get_h2c_ack_dpk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
{
u8 seq_num;
u8 fw_rc;
struct halmac_dpk_state *state = &adapter->halmac_state.dpk_state;
enum halmac_cmd_process_status proc_status;
seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
state->seq_num, seq_num);
if (seq_num != state->seq_num) {
PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
state->seq_num, seq_num);
return HALMAC_RET_SUCCESS;
}
if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
PLTFM_MSG_ERR("[ERR]not cmd sending\n");
return HALMAC_RET_SUCCESS;
}
fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
state->fw_rc = fw_rc;
if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {
proc_status = HALMAC_CMD_PROCESS_RCVD;
state->proc_status = proc_status;
PLTFM_EVENT_SIG(HALMAC_FEATURE_DPK, proc_status, NULL, 0);
} else {
proc_status = HALMAC_CMD_PROCESS_ERROR;
state->proc_status = proc_status;
PLTFM_EVENT_SIG(HALMAC_FEATURE_DPK, proc_status, &fw_rc, 1);
}
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status
get_dpk_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
{
u8 seq_num;
u8 seg_id;
u8 seg_size;
u16 total_size;
enum halmac_cmd_process_status proc_status;
struct halmac_dpk_state *state = &adapter->halmac_state.dpk_state;
seq_num = (u8)DPK_DATA_GET_H2C_SEQ(buf);
PLTFM_MSG_TRACE("[TRACE]seq num : h2c->%d c2h->%d\n",
state->seq_num, seq_num);
if (seq_num != state->seq_num) {
PLTFM_MSG_ERR("[ERR]seq num mismatch : h2c->%d c2h->%d\n",
state->seq_num, seq_num);
return HALMAC_RET_SUCCESS;
}
if (state->proc_status != HALMAC_CMD_PROCESS_RCVD) {
PLTFM_MSG_ERR("[ERR]not receive dpk ack\n");
if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
PLTFM_MSG_ERR("[ERR]not cmd sending\n");
return HALMAC_RET_SUCCESS;
}
}
total_size = (u16)DPK_DATA_GET_TOTAL_SIZE(buf);
seg_id = (u8)DPK_DATA_GET_SEGMENT_ID(buf);
seg_size = (u8)DPK_DATA_GET_SEGMENT_SIZE(buf);
state->data_size = total_size;
if (!state->data) {
state->data = (u8 *)PLTFM_MALLOC(state->data_size);
if (!state->data) {
PLTFM_MSG_ERR("[ERR]malloc fail!!\n");
return HALMAC_RET_NULL_POINTER;
}
}
if (seg_id == 0)
state->seg_size = seg_size;
PLTFM_MEMCPY(state->data + seg_id * state->seg_size,
buf + C2H_DATA_OFFSET_88XX, seg_size);
if (DPK_DATA_GET_END_SEGMENT(buf) == 0)
return HALMAC_RET_SUCCESS;
proc_status = HALMAC_CMD_PROCESS_DONE;
state->proc_status = proc_status;
PLTFM_EVENT_SIG(HALMAC_FEATURE_DPK, state->proc_status, state->data,
state->data_size);
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status
get_h2c_ack_pwr_trk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
{

14
hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h
View File

@@ -52,6 +52,20 @@ get_h2c_ack_pwr_trk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
enum halmac_ret_status
get_psd_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
enum halmac_ret_status
start_dpk_88xx(struct halmac_adapter *adapter);
enum halmac_ret_status
get_h2c_ack_dpk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
enum halmac_ret_status
get_dpk_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
enum halmac_ret_status
get_dpk_status_88xx(struct halmac_adapter *adapter,
enum halmac_cmd_process_status *proc_status, u8 *data,
u32 *size);
#endif /* HALMAC_88XX_SUPPORT */
#endif/* _HALMAC_BB_RF_88XX_H_ */

28
hal/halmac/halmac_88xx/halmac_common_88xx.c
View File

@@ -500,7 +500,9 @@ set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
void *value)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
struct halmac_tx_page_threshold_info *th_info = NULL;
#if HALMAC_SDIO_SUPPORT
struct halmac_tx_page_threshold_info *th_info;
#endif
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
@@ -761,6 +763,9 @@ parse_c2h_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
case C2H_SUB_CMD_ID_SCAN_CH_NOTIFY:
status = get_scan_ch_notify_88xx(adapter, c2h_pkt, c2h_size);
break;
case C2H_SUB_CMD_ID_DPK_DATA:
status = get_dpk_data_88xx(adapter, c2h_pkt, c2h_size);
break;
default:
PLTFM_MSG_WARN("[WARN]Sub cmd id!!\n");
status = HALMAC_RET_C2H_NOT_HANDLED;
@@ -893,6 +898,9 @@ get_h2c_ack_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
case H2C_SUB_CMD_ID_FW_SNDING_ACK:
status = get_h2c_ack_fw_snding_88xx(adapter, buf, size);
break;
case H2C_SUB_CMD_ID_DPK_ACK:
status = get_h2c_ack_dpk_88xx(adapter, buf, size);
break;
default:
status = HALMAC_RET_C2H_NOT_HANDLED;
break;
@@ -2853,6 +2861,9 @@ query_status_88xx(struct halmac_adapter *adapter,
case HALMAC_FEATURE_FW_SNDING:
status = get_fw_snding_status_88xx(adapter, proc_status);
break;
case HALMAC_FEATURE_DPK:
status = get_dpk_status_88xx(adapter, proc_status, data, size);
break;
default:
return HALMAC_RET_INVALID_FEATURE_ID;
}
@@ -2998,7 +3009,7 @@ pwr_seq_parser_88xx(struct halmac_adapter *adapter,
cut = HALMAC_PWR_CUT_TESTCHIP_MSK;
break;
default:
PLTFM_MSG_ERR("[ERR]cut version!!\n");
PLTFM_MSG_ERR("[ERR]chip info!!\n");
return HALMAC_RET_SWITCH_CASE_ERROR;
}
@@ -3165,7 +3176,7 @@ parse_intf_phy_88xx(struct halmac_adapter *adapter,
u16 ip_sel;
struct halmac_intf_phy_para *cur_param;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
u8 result = HALMAC_RET_SUCCESS;
enum halmac_ret_status result = HALMAC_RET_SUCCESS;
switch (adapter->chip_ver) {
case HALMAC_CHIP_VER_A_CUT:
@@ -3210,6 +3221,15 @@ parse_intf_phy_88xx(struct halmac_adapter *adapter,
} else if (intf_phy == HAL_INTF_PHY_USB2 ||
intf_phy == HAL_INTF_PHY_USB3) {
#if HALMAC_USB_SUPPORT
if (offset > 0x100)
usb_page_switch_88xx(adapter,
intf_phy,
1);
else
usb_page_switch_88xx(adapter,
intf_phy,
0);
offset = offset & 0xFF;
result = usbphy_write_88xx(adapter, (u8)offset,
value, intf_phy);
if (result != HALMAC_RET_SUCCESS)
@@ -3236,7 +3256,7 @@ parse_intf_phy_88xx(struct halmac_adapter *adapter,
cur_param++;
} while (1);
return HALMAC_RET_SUCCESS;
return result;
}
/**

831
hal/halmac/halmac_88xx/halmac_efuse_88xx.c
View File

@@ -26,6 +26,15 @@
#define FEATURE_DUMP_LOG_EFUSE HALMAC_FEATURE_DUMP_LOGICAL_EFUSE
#define FEATURE_DUMP_LOG_EFUSE_MASK HALMAC_FEATURE_DUMP_LOGICAL_EFUSE_MASK
#define SUPER_USB_ZONE0_START 0x150
#define SUPER_USB_ZONE0_END 0x199
#define SUPER_USB_ZONE1_START 0x200
#define SUPER_USB_ZONE1_END 0x217
#define SUPER_USB_RE_PG_CK_ZONE0_START 0x15D
#define SUPER_USB_RE_PG_CK_ZONE0_END 0x164
static u8 bt_switch = 0;
static enum halmac_cmd_construct_state
efuse_cmd_cnstr_state_88xx(struct halmac_adapter *adapter);
@@ -54,6 +63,10 @@ dump_efuse_drv_88xx(struct halmac_adapter *adapter);
static enum halmac_ret_status
proc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
static enum halmac_ret_status
proc_write_log_efuse_word_88xx(struct halmac_adapter *adapter, u32 offset,
u16 value);
static enum halmac_ret_status
update_eeprom_mask_88xx(struct halmac_adapter *adapter,
struct halmac_pg_efuse_info *info, u8 *updated_mask);
@@ -72,6 +85,11 @@ proc_pg_efuse_88xx(struct halmac_adapter *adapter,
struct halmac_pg_efuse_info *info, u8 word_en,
u8 pre_word_en, u32 eeprom_offset);
static enum halmac_ret_status
pg_super_usb_efuse_88xx(struct halmac_adapter *adapter,
struct halmac_pg_efuse_info *info, u8 word_en,
u8 pre_word_en, u32 eeprom_offset);
static enum halmac_ret_status
program_efuse_88xx(struct halmac_adapter *adapter,
struct halmac_pg_efuse_info *info, u8 *updated_mask);
@@ -80,6 +98,28 @@ static void
mask_eeprom_88xx(struct halmac_adapter *adapter,
struct halmac_pg_efuse_info *info);
static enum halmac_ret_status
proc_gen_super_usb_map_88xx(struct halmac_adapter *adapter, u8 *drv_map,
u8 *updated_map, u8 *updated_mask);
static enum halmac_ret_status
super_usb_efuse_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map,
u8 *log_map, u8 *log_mask);
static enum halmac_ret_status
super_usb_chk_88xx(struct halmac_adapter *adapter, u8 *super_usb);
static enum halmac_ret_status
log_efuse_re_pg_chk_88xx(struct halmac_adapter *adapter, u8 *efuse_mask,
u32 addr, u8 *re_pg);
static enum halmac_ret_status
super_usb_fmt_chk_88xx(struct halmac_adapter *adapter, u8 *re_pg);
static enum halmac_ret_status
super_usb_re_pg_chk_88xx(struct halmac_adapter *adapter, u8 *phy_map,
u8 *re_pg);
/**
* dump_efuse_map_88xx() - dump "physical" efuse map
* @adapter : the adapter of halmac
@@ -220,13 +260,23 @@ dump_efuse_map_bt_88xx(struct halmac_adapter *adapter,
PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
return status;
}
bt_switch = 1;
status = read_hw_efuse_88xx(adapter, 0, size, map);
if (status != HALMAC_RET_SUCCESS) {
bt_switch = 0;
PLTFM_MSG_ERR("[ERR]read hw efuse\n");
return status;
}
status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
if (status != HALMAC_RET_SUCCESS) {
bt_switch = 0;
PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
return status;
}
bt_switch = 0;
if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
HALMAC_RET_SUCCESS)
return HALMAC_RET_ERROR_STATE;
@@ -282,13 +332,23 @@ write_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 value,
PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
return status;
}
bt_switch = 1;
status = write_hw_efuse_88xx(adapter, offset, value);
if (status != HALMAC_RET_SUCCESS) {
bt_switch = 0;
PLTFM_MSG_ERR("[ERR]write efuse\n");
return status;
}
status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
if (status != HALMAC_RET_SUCCESS) {
bt_switch = 0;
PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
return status;
}
bt_switch = 0;
if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
HALMAC_RET_SUCCESS)
return HALMAC_RET_ERROR_STATE;
@@ -344,13 +404,23 @@ read_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value,
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
return status;
}
bt_switch = 1;
status = read_efuse_88xx(adapter, offset, 1, value);
if (status != HALMAC_RET_SUCCESS) {
bt_switch = 0;
PLTFM_MSG_ERR("[ERR]read efuse\n");
return status;
}
status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
if (status != HALMAC_RET_SUCCESS) {
bt_switch = 0;
PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
return status;
}
bt_switch = 0;
if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
HALMAC_RET_SUCCESS)
return HALMAC_RET_ERROR_STATE;
@@ -737,6 +807,61 @@ write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
return HALMAC_RET_SUCCESS;
}
/**
* write_log_efuse_word_88xx() - write "logical" efuse offset word
* @adapter : the adapter of halmac
* @offset : offset
* @value : value
* Author : Soar
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
write_log_efuse_word_88xx(struct halmac_adapter *adapter, u32 offset, u16 value)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
enum halmac_cmd_process_status *proc_status;
proc_status = &adapter->halmac_state.efuse_state.proc_status;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (offset >= adapter->hw_cfg_info.eeprom_size) {
PLTFM_MSG_ERR("[ERR]Offset is too large\n");
return HALMAC_RET_EFUSE_SIZE_INCORRECT;
}
if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
return HALMAC_RET_BUSY_STATE;
}
if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
return HALMAC_RET_ERROR_STATE;
}
status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
return status;
}
status = proc_write_log_efuse_word_88xx(adapter, offset, value);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]write logical efuse\n");
return status;
}
if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
HALMAC_RET_SUCCESS)
return HALMAC_RET_ERROR_STATE;
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* pg_efuse_by_map_88xx() - pg logical efuse by map
* @adapter : the adapter of halmac
@@ -873,9 +998,11 @@ switch_efuse_bank_88xx(struct halmac_adapter *adapter,
u8 reg_value;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_BUSY) !=
HALMAC_RET_SUCCESS)
return HALMAC_RET_ERROR_STATE;
if (!bt_switch) {
if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_BUSY) !=
HALMAC_RET_SUCCESS)
return HALMAC_RET_ERROR_STATE;
}
reg_value = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 1);
@@ -1293,9 +1420,19 @@ proc_pg_efuse_by_map_88xx(struct halmac_adapter *adapter,
enum halmac_efuse_read_cfg cfg)
{
u8 *updated_mask = NULL;
u8 *updated_map = NULL;
u32 map_size = adapter->hw_cfg_info.eeprom_size;
u32 mask_size = adapter->hw_cfg_info.eeprom_size >> 4;
u8 super_usb;
struct halmac_pg_efuse_info local_info;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
status = super_usb_chk_88xx(adapter, &super_usb);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]super_usb_chk\n");
return status;
}
updated_mask = (u8 *)PLTFM_MALLOC(mask_size);
if (!updated_mask) {
PLTFM_MSG_ERR("[ERR]malloc updated mask\n");
@@ -1310,21 +1447,58 @@ proc_pg_efuse_by_map_88xx(struct halmac_adapter *adapter,
return status;
}
if (super_usb) {
updated_map = (u8 *)PLTFM_MALLOC(map_size);
if (!updated_map) {
PLTFM_MSG_ERR("[ERR]malloc updated map\n");
PLTFM_FREE(updated_mask, mask_size);
return HALMAC_RET_MALLOC_FAIL;
}
PLTFM_MEMSET(updated_map, 0xFF, map_size);
status = proc_gen_super_usb_map_88xx(adapter, info->efuse_map,
updated_map, updated_mask);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]gen eeprom mask/map\n");
PLTFM_FREE(updated_mask, mask_size);
PLTFM_FREE(updated_map, map_size);
return status;
}
local_info.efuse_map = updated_map;
local_info.efuse_mask = updated_mask;
local_info.efuse_map_size = map_size;
local_info.efuse_mask_size = mask_size;
}
if (super_usb)
status = check_efuse_enough_88xx(adapter, &local_info,
updated_mask);
else
status = check_efuse_enough_88xx(adapter, info, updated_mask);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]chk efuse enough\n");
PLTFM_FREE(updated_mask, mask_size);
if (super_usb)
PLTFM_FREE(updated_map, map_size);
return status;
}
if (super_usb)
status = program_efuse_88xx(adapter, &local_info, updated_mask);
else
status = program_efuse_88xx(adapter, info, updated_mask);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]pg efuse\n");
PLTFM_FREE(updated_mask, mask_size);
if (super_usb)
PLTFM_FREE(updated_map, map_size);
return status;
}
PLTFM_FREE(updated_mask, mask_size);
if (super_usb)
PLTFM_FREE(updated_map, map_size);
return HALMAC_RET_SUCCESS;
}
@@ -1520,6 +1694,117 @@ proc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
proc_write_log_efuse_word_88xx(struct halmac_adapter *adapter, u32 offset,
u16 value)
{
u8 byte1;
u8 byte2;
u8 blk;
u8 blk_idx;
u8 hdr;
u8 hdr2;
u8 *map = NULL;
u32 eeprom_size = adapter->hw_cfg_info.eeprom_size;
u32 prtct_efuse_size = adapter->hw_cfg_info.prtct_efuse_size;
u32 end;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
map = (u8 *)PLTFM_MALLOC(eeprom_size);
if (!map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return HALMAC_RET_MALLOC_FAIL;
}
PLTFM_MEMSET(map, 0xFF, eeprom_size);
status = read_log_efuse_map_88xx(adapter, map);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]read logical efuse\n");
PLTFM_FREE(map, eeprom_size);
return status;
}
end = adapter->efuse_end;
blk = (u8)(offset >> 3);
blk_idx = (u8)((offset & (8 - 1)) >> 1);
if (offset > 0x7f) {
hdr = (((blk & 0x07) << 5) & 0xE0) | 0x0F;
hdr2 = (u8)(((blk & 0x78) << 1) +
((0x1 << blk_idx) ^ 0x0F));
} else {
hdr = (u8)((blk << 4) + ((0x01 << blk_idx) ^ 0x0F));
}
if ((offset & 1) == 0) {
byte1 = (u8)(value & 0xFF);
byte2 = (u8)((value >> 8) & 0xFF);
} else {
PLTFM_FREE(map, eeprom_size);
return HALMAC_RET_ADR_NOT_ALIGN;
}
if (offset > 0x7f) {
if (adapter->hw_cfg_info.efuse_size <=
4 + prtct_efuse_size + end) {
PLTFM_FREE(map, eeprom_size);
return HALMAC_RET_EFUSE_NOT_ENOUGH;
}
status = write_hw_efuse_88xx(adapter, end, hdr);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_FREE(map, eeprom_size);
return status;
}
status = write_hw_efuse_88xx(adapter, end + 1, hdr2);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_FREE(map, eeprom_size);
return status;
}
status = write_hw_efuse_88xx(adapter, end + 2, byte1);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_FREE(map, eeprom_size);
return status;
}
status = write_hw_efuse_88xx(adapter, end + 3, byte2);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_FREE(map, eeprom_size);
return status;
}
} else {
if (adapter->hw_cfg_info.efuse_size <=
3 + prtct_efuse_size + end) {
PLTFM_FREE(map, eeprom_size);
return HALMAC_RET_EFUSE_NOT_ENOUGH;
}
status = write_hw_efuse_88xx(adapter, end, hdr);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_FREE(map, eeprom_size);
return status;
}
status = write_hw_efuse_88xx(adapter, end + 1, byte1);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_FREE(map, eeprom_size);
return status;
}
status = write_hw_efuse_88xx(adapter, end + 2, byte2);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_FREE(map, eeprom_size);
return status;
}
}
PLTFM_FREE(map, eeprom_size);
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status
read_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, u8 *map)
{
@@ -1629,6 +1914,14 @@ check_efuse_enough_88xx(struct halmac_adapter *adapter,
u16 j;
u32 eeprom_offset;
u32 pg_num = 0;
u8 super_usb;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
status = super_usb_chk_88xx(adapter, &super_usb);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]super_usb_chk\n");
return status;
}
for (i = 0; i < info->efuse_map_size; i = i + 8) {
eeprom_offset = i;
@@ -1639,14 +1932,21 @@ check_efuse_enough_88xx(struct halmac_adapter *adapter,
pre_word_en = (*(updated_mask + (i >> 4)) >> 4);
if (pre_word_en > 0) {
if (eeprom_offset > 0x7f) {
pg_num += 2;
if (super_usb &&
((eeprom_offset >= SUPER_USB_ZONE0_START &&
eeprom_offset <= SUPER_USB_ZONE0_END) ||
(eeprom_offset >= SUPER_USB_ZONE1_START &&
eeprom_offset <= SUPER_USB_ZONE1_END))) {
for (j = 0; j < 4; j++) {
if (((pre_word_en >> j) & 0x1) > 0)
pg_num += 2;
pg_num += 4;
}
} else {
pg_num++;
if (eeprom_offset > 0x7f)
pg_num += 2;
else
pg_num++;
for (j = 0; j < 4; j++) {
if (((pre_word_en >> j) & 0x1) > 0)
pg_num += 2;
@@ -1767,6 +2067,68 @@ proc_pg_efuse_88xx(struct halmac_adapter *adapter,
return status;
}
static enum halmac_ret_status
pg_super_usb_efuse_88xx(struct halmac_adapter *adapter,
struct halmac_pg_efuse_info *info, u8 word_en,
u8 pre_word_en, u32 eeprom_offset)
{
u8 blk;
u8 hdr;
u8 hdr2;
u16 i;
u32 efuse_end;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
efuse_end = adapter->efuse_end;
blk = (u8)(eeprom_offset >> 3);
hdr = (((blk & 0x07) << 5) & 0xE0) | 0x0F;
for (i = 0; i < 4; i++) {
hdr = (((blk & 0x07) << 5) & 0xE0) | 0x0F;
if (((pre_word_en >> i) & 0x1) > 0) {
hdr2 = (u8)(((blk & 0x78) << 1) +
((pre_word_en & BIT(i)) ^ 0x0F));
status = write_hw_efuse_88xx(adapter, efuse_end, hdr);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]write efuse\n");
return status;
}
status = write_hw_efuse_88xx(adapter, efuse_end + 1,
hdr2);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]write efuse(+1)\n");
return status;
}
efuse_end = efuse_end + 2;
status = write_hw_efuse_88xx(adapter, efuse_end,
*(info->efuse_map +
eeprom_offset +
(i << 1)));
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]write efuse(<<1)\n");
return status;
}
status = write_hw_efuse_88xx(adapter, efuse_end + 1,
*(info->efuse_map +
eeprom_offset + (i << 1)
+ 1));
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]write efuse(<<1)+1\n");
return status;
}
efuse_end = efuse_end + 2;
}
}
adapter->efuse_end = efuse_end;
return status;
}
static enum halmac_ret_status
program_efuse_88xx(struct halmac_adapter *adapter,
struct halmac_pg_efuse_info *info, u8 *updated_mask)
@@ -1775,8 +2137,15 @@ program_efuse_88xx(struct halmac_adapter *adapter,
u8 word_en;
u16 i;
u32 eeprom_offset;
u8 super_usb;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
status = super_usb_chk_88xx(adapter, &super_usb);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]super_usb_chk\n");
return status;
}
for (i = 0; i < info->efuse_map_size; i = i + 8) {
eeprom_offset = i;
@@ -1789,7 +2158,20 @@ program_efuse_88xx(struct halmac_adapter *adapter,
}
if (pre_word_en > 0) {
if (eeprom_offset > 0x7f) {
if (super_usb &&
((eeprom_offset >= SUPER_USB_ZONE0_START &&
eeprom_offset <= SUPER_USB_ZONE0_END) ||
(eeprom_offset >= SUPER_USB_ZONE1_START &&
eeprom_offset <= SUPER_USB_ZONE1_END))) {
status = pg_super_usb_efuse_88xx(adapter, info,
word_en,
pre_word_en,
eeprom_offset);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]super usb efuse\n");
return status;
}
} else if (eeprom_offset > 0x7f) {
status = pg_extend_efuse_88xx(adapter, info,
word_en,
pre_word_en,
@@ -2255,4 +2637,437 @@ read_wifi_phy_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
proc_gen_super_usb_map_88xx(struct halmac_adapter *adapter, u8 *drv_map,
u8 *updated_map, u8 *updated_mask)
{
u8 *local_map = NULL;
u8 *super_usb_map = NULL;
u8 *super_usb_mask = NULL;
u8 mask_val_0;
u8 mask_val_1;
u32 efuse_size;
u32 i;
u32 j;
u32 val32;
u32 map_size = adapter->hw_cfg_info.eeprom_size;
u32 mask_size = adapter->hw_cfg_info.eeprom_size >> 4;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (adapter->efuse_map_valid == 0) {
efuse_size = adapter->hw_cfg_info.efuse_size;
local_map = (u8 *)PLTFM_MALLOC(efuse_size);
if (!local_map) {
PLTFM_MSG_ERR("[ERR]local map\n");
return HALMAC_RET_MALLOC_FAIL;
}
status = read_efuse_88xx(adapter, 0, efuse_size, local_map);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]read efuse\n");
PLTFM_FREE(local_map, efuse_size);
return status;
}
if (!adapter->efuse_map) {
adapter->efuse_map = (u8 *)PLTFM_MALLOC(efuse_size);
if (!adapter->efuse_map) {
PLTFM_MSG_ERR("[ERR]malloc adapter map\n");
PLTFM_FREE(local_map, efuse_size);
return HALMAC_RET_MALLOC_FAIL;
}
}
PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
PLTFM_MEMCPY(adapter->efuse_map, local_map, efuse_size);
adapter->efuse_map_valid = 1;
PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
PLTFM_FREE(local_map, efuse_size);
}
super_usb_mask = (u8 *)PLTFM_MALLOC(mask_size);
if (!super_usb_mask) {
PLTFM_MSG_ERR("[ERR]malloc updated mask\n");
return HALMAC_RET_MALLOC_FAIL;
}
PLTFM_MEMSET(super_usb_mask, 0x00, mask_size);
super_usb_map = (u8 *)PLTFM_MALLOC(map_size);
if (!super_usb_map) {
PLTFM_MSG_ERR("[ERR]malloc updated map\n");
PLTFM_FREE(super_usb_mask, mask_size);
return HALMAC_RET_MALLOC_FAIL;
}
PLTFM_MEMSET(super_usb_map, 0xFF, map_size);
status = super_usb_efuse_parser_88xx(adapter, adapter->efuse_map,
super_usb_map, super_usb_mask);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_FREE(super_usb_mask, mask_size);
PLTFM_FREE(super_usb_map, map_size);
return HALMAC_RET_EEPROM_PARSING_FAIL;
}
for (i = 0; i < map_size; i = i + 16) {
mask_val_0 = *(updated_mask + (i >> 4));
mask_val_1 = *(super_usb_mask + (i >> 4));
if (mask_val_0 || mask_val_1) {
for (j = 0; j < 4; j++) {
val32 = i + (j << 1);
if (mask_val_0 & BIT(j + 4)) {
*(updated_map + val32) =
*(drv_map + val32);
*(updated_map + val32 + 1) =
*(drv_map + val32 + 1);
} else if (mask_val_1 & BIT(j + 4)) {
*(updated_map + val32) =
*(super_usb_map + val32);
*(updated_map + val32 + 1) =
*(super_usb_map + val32 + 1);
}
}
for (j = 0; j < 4; j++) {
val32 = i + (j << 1);
if (mask_val_0 & BIT(j)) {
*(updated_map + val32 + 8) =
*(drv_map + val32 + 8);
*(updated_map + val32 + 9) =
*(drv_map + val32 + 9);
} else if (mask_val_1 & BIT(j)) {
*(updated_map + val32 + 8) =
*(super_usb_map + val32 + 8);
*(updated_map + val32 + 9) =
*(super_usb_map + val32 + 9);
}
}
*(updated_mask + (i >> 4)) |= mask_val_1;
}
}
PLTFM_FREE(super_usb_mask, mask_size);
PLTFM_FREE(super_usb_map, map_size);
return status;
}
static enum halmac_ret_status
super_usb_efuse_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map,
u8 *log_map, u8 *log_mask)
{
u8 i;
u8 value8;
u8 blk_idx;
u8 word_en;
u8 valid;
u8 hdr;
u8 hdr2 = 0;
u8 usb_addr;
u32 eeprom_idx;
u32 efuse_idx = 0;
u32 start_offset;
u32 prtct_efuse_size = adapter->hw_cfg_info.prtct_efuse_size;
struct halmac_hw_cfg_info *hw_info = &adapter->hw_cfg_info;
do {
value8 = *(phy_map + efuse_idx);
hdr = value8;
if ((hdr & 0x1f) == 0x0f) {
efuse_idx++;
value8 = *(phy_map + efuse_idx);
hdr2 = value8;
if (hdr2 == 0xff)
break;
blk_idx = ((hdr2 & 0xF0) >> 1) | ((hdr >> 5) & 0x07);
word_en = hdr2 & 0x0F;
} else {
blk_idx = (hdr & 0xF0) >> 4;
word_en = hdr & 0x0F;
}
if (hdr == 0xff)
break;
efuse_idx++;
if (efuse_idx >= hw_info->efuse_size - prtct_efuse_size - 1)
return HALMAC_RET_EEPROM_PARSING_FAIL;
for (i = 0; i < 4; i++) {
valid = (u8)((~(word_en >> i)) & BIT(0));
if (valid == 1) {
eeprom_idx = (blk_idx << 3) + (i << 1);
if ((eeprom_idx + 1) > hw_info->eeprom_size) {
PLTFM_MSG_ERR("[ERR]efuse idx:0x%X\n",
efuse_idx - 1);
PLTFM_MSG_ERR("[ERR]read hdr:0x%X\n",
hdr);
PLTFM_MSG_ERR("[ERR]rad hdr2:0x%X\n",
hdr2);
return HALMAC_RET_EEPROM_PARSING_FAIL;
}
value8 = *(phy_map + efuse_idx);
*(log_map + eeprom_idx) = value8;
eeprom_idx++;
efuse_idx++;
if (efuse_idx > hw_info->efuse_size -
prtct_efuse_size - 1)
return HALMAC_RET_EEPROM_PARSING_FAIL;
value8 = *(phy_map + efuse_idx);
*(log_map + eeprom_idx) = value8;
efuse_idx++;
if (efuse_idx > hw_info->efuse_size -
prtct_efuse_size)
return HALMAC_RET_EEPROM_PARSING_FAIL;
}
}
start_offset = blk_idx << 3;
if ((start_offset >= SUPER_USB_ZONE0_START &&
start_offset <= SUPER_USB_ZONE0_END) ||
(start_offset >= SUPER_USB_ZONE1_START &&
start_offset <= SUPER_USB_ZONE1_END))
usb_addr = 1;
else
usb_addr = 0;
if (usb_addr) {
if (word_en != 0xE && word_en != 0xD &&
word_en != 0xB && word_en != 0x7) {
if (blk_idx & 1)
*(log_mask + (blk_idx >> 1)) |=
~word_en & 0x0F;
else
*(log_mask + (blk_idx >> 1)) |=
~(word_en << 4) & 0xF0;
} else {
if (blk_idx & 1)
*(log_mask + (blk_idx >> 1)) &=
word_en | 0xF0;
else
*(log_mask + (blk_idx >> 1)) &=
(word_en << 4) | 0x0F;
}
}
} while (1);
adapter->efuse_end = efuse_idx;
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
super_usb_chk_88xx(struct halmac_adapter *adapter, u8 *super_usb)
{
u8 *local_map = NULL;
u32 efuse_size;
u8 re_pg;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (adapter->chip_id == HALMAC_CHIP_ID_8822C &&
(adapter->intf == HALMAC_INTERFACE_PCIE ||
adapter->intf == HALMAC_INTERFACE_USB)) {
*super_usb = 1;
} else {
*super_usb = 0;
return HALMAC_RET_SUCCESS;
}
if (adapter->efuse_map_valid == 0) {
efuse_size = adapter->hw_cfg_info.efuse_size;
local_map = (u8 *)PLTFM_MALLOC(efuse_size);
if (!local_map) {
PLTFM_MSG_ERR("[ERR]local map\n");
return HALMAC_RET_MALLOC_FAIL;
}
status = read_efuse_88xx(adapter, 0, efuse_size, local_map);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]read efuse\n");
PLTFM_FREE(local_map, efuse_size);
return status;
}
if (!adapter->efuse_map) {
adapter->efuse_map = (u8 *)PLTFM_MALLOC(efuse_size);
if (!adapter->efuse_map) {
PLTFM_MSG_ERR("[ERR]malloc adapter map\n");
PLTFM_FREE(local_map, efuse_size);
return HALMAC_RET_MALLOC_FAIL;
}
}
PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
PLTFM_MEMCPY(adapter->efuse_map, local_map, efuse_size);
adapter->efuse_map_valid = 1;
PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
PLTFM_FREE(local_map, efuse_size);
}
status = super_usb_re_pg_chk_88xx(adapter, adapter->efuse_map, &re_pg);
if (status != HALMAC_RET_SUCCESS)
return status;
if (re_pg) {
status = super_usb_fmt_chk_88xx(adapter, &re_pg);
if (status != HALMAC_RET_SUCCESS)
return status;
if (re_pg == 1) {
*super_usb = 0;
return HALMAC_RET_SUCCESS;
}
}
return status;
}
static enum halmac_ret_status
log_efuse_re_pg_chk_88xx(struct halmac_adapter *adapter, u8 *efuse_mask,
u32 addr, u8 *re_pg)
{
u32 size = adapter->hw_cfg_info.eeprom_size;
u8 mask_val;
u8 mask_offset;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (addr >= size) {
PLTFM_MSG_ERR("[ERR]Offset is too large\n");
return HALMAC_RET_EFUSE_SIZE_INCORRECT;
}
mask_val = *(efuse_mask + (addr >> 4));
if (addr & 0x8)
mask_offset = BIT((addr & 0x7) >> 1);
else
mask_offset = BIT((addr & 0x7) >> 1) << 4;
if (mask_val & mask_offset)
*re_pg = 1;
else
*re_pg = 0;
return status;
}
static enum halmac_ret_status
super_usb_fmt_chk_88xx(struct halmac_adapter *adapter, u8 *re_pg)
{
u32 map_size = adapter->hw_cfg_info.eeprom_size;
u32 mask_size = adapter->hw_cfg_info.eeprom_size >> 4;
u32 addr;
u8 *super_usb_map = NULL;
u8 *super_usb_mask = NULL;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
super_usb_mask = (u8 *)PLTFM_MALLOC(mask_size);
if (!super_usb_mask) {
PLTFM_MSG_ERR("[ERR]malloc updated mask\n");
return HALMAC_RET_MALLOC_FAIL;
}
PLTFM_MEMSET(super_usb_mask, 0x00, mask_size);
super_usb_map = (u8 *)PLTFM_MALLOC(map_size);
if (!super_usb_map) {
PLTFM_MSG_ERR("[ERR]malloc updated map\n");
PLTFM_FREE(super_usb_mask, mask_size);
return HALMAC_RET_MALLOC_FAIL;
}
PLTFM_MEMSET(super_usb_map, 0xFF, map_size);
status = super_usb_efuse_parser_88xx(adapter, adapter->efuse_map,
super_usb_map, super_usb_mask);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_FREE(super_usb_mask, mask_size);
PLTFM_FREE(super_usb_map, map_size);
return HALMAC_RET_EEPROM_PARSING_FAIL;
}
for (addr = SUPER_USB_ZONE0_START;
addr <= SUPER_USB_ZONE0_END; addr++) {
status = log_efuse_re_pg_chk_88xx(adapter, super_usb_mask, addr,
re_pg);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_FREE(super_usb_mask, mask_size);
PLTFM_FREE(super_usb_map, map_size);
return status;
}
if (*re_pg == 1) {
PLTFM_FREE(super_usb_mask, mask_size);
PLTFM_FREE(super_usb_map, map_size);
return status;
}
}
for (addr = SUPER_USB_ZONE1_START;
addr <= SUPER_USB_ZONE1_END; addr++) {
status = log_efuse_re_pg_chk_88xx(adapter, super_usb_mask, addr,
re_pg);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_FREE(super_usb_mask, mask_size);
PLTFM_FREE(super_usb_map, map_size);
return status;
}
if (*re_pg == 1) {
PLTFM_FREE(super_usb_mask, mask_size);
PLTFM_FREE(super_usb_map, map_size);
return status;
}
}
*re_pg = 0;
PLTFM_FREE(super_usb_mask, mask_size);
PLTFM_FREE(super_usb_map, map_size);
return status;
}
static enum halmac_ret_status
super_usb_re_pg_chk_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *re_pg)
{
u32 size = adapter->hw_cfg_info.eeprom_size;
u32 addr;
u8 *map = NULL;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
map = (u8 *)PLTFM_MALLOC(size);
if (!map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return HALMAC_RET_MALLOC_FAIL;
}
PLTFM_MEMSET(map, 0xFF, size);
status = eeprom_mask_parser_88xx(adapter, phy_map, map);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_FREE(map, size);
return status;
}
for (addr = SUPER_USB_RE_PG_CK_ZONE0_START;
addr <= SUPER_USB_RE_PG_CK_ZONE0_END; addr++) {
if (*(map + addr) != 0xFF) {
PLTFM_FREE(map, size);
*re_pg = 1;
return status;
}
}
*re_pg = 0;
PLTFM_FREE(map, size);
return status;
}
#endif /* HALMAC_88XX_SUPPORT */

4
hal/halmac/halmac_88xx/halmac_efuse_88xx.h
View File

@@ -68,6 +68,10 @@ read_logical_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value);
enum halmac_ret_status
write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
enum halmac_ret_status
write_log_efuse_word_88xx(struct halmac_adapter *adapter, u32 offset,
u16 value);
enum halmac_ret_status
pg_efuse_by_map_88xx(struct halmac_adapter *adapter,
struct halmac_pg_efuse_info *info,

17
hal/halmac/halmac_88xx/halmac_gpio_88xx.c
View File

@@ -241,6 +241,23 @@ pinmux_parser_88xx(struct halmac_adapter *adapter,
cur_list++;
}
switch (*cur_func) {
case HALMAC_BT_DPDT_SEL:
*cur_func = (HALMAC_REG_R8(REG_LED_CFG + 3) & BIT(0)) ?
HALMAC_WL_DPDT_SEL : HALMAC_BT_DPDT_SEL;
break;
case HALMAC_BT_PAPE_SEL:
*cur_func = (HALMAC_REG_R8(REG_PAD_CTRL1 + 3) & BIT(5)) ?
HALMAC_WL_PAPE_SEL : HALMAC_BT_PAPE_SEL;
break;
case HALMAC_BT_LNAON_SEL:
*cur_func = (HALMAC_REG_R8(REG_PAD_CTRL1 + 3) & BIT(4)) ?
HALMAC_WL_LNAON_SEL : HALMAC_BT_LNAON_SEL;
break;
default:
break;
}
*state = HALMAC_GPIO_CFG_STATE_IDLE;
if (i == size)

15
hal/halmac/halmac_88xx/halmac_init_88xx.c
View File

@@ -231,6 +231,7 @@ mount_api_88xx(struct halmac_adapter *adapter)
api->halmac_get_logical_efuse_size = get_log_efuse_size_88xx;
api->halmac_write_logical_efuse = write_log_efuse_88xx;
api->halmac_write_logical_efuse_word = write_log_efuse_word_88xx;
api->halmac_read_logical_efuse = read_logical_efuse_88xx;
api->halmac_write_wifi_phy_efuse = write_wifi_phy_efuse_88xx;
@@ -269,6 +270,7 @@ mount_api_88xx(struct halmac_adapter *adapter)
api->halmac_drop_scan_packet = drop_scan_packet_88xx;
api->halmac_start_iqk = start_iqk_88xx;
api->halmac_start_dpk = start_dpk_88xx;
api->halmac_ctrl_pwr_tracking = ctrl_pwr_tracking_88xx;
api->halmac_psd = psd_88xx;
api->halmac_cfg_la_mode = cfg_la_mode_88xx;
@@ -588,6 +590,9 @@ reset_ofld_feature_88xx(struct halmac_adapter *adapter,
state->fw_snding_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
state->fw_snding_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
break;
case HALMAC_FEATURE_DPK:
state->dpk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
break;
case HALMAC_FEATURE_ALL:
state->cfg_param_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
state->cfg_param_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
@@ -673,14 +678,13 @@ verify_io_88xx(struct halmac_adapter *adapter)
enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;
if (adapter->intf == HALMAC_INTERFACE_SDIO) {
#if HALMAC_SDIO_SUPPORT
offset = REG_PAGE5_DUMMY;
if (0 == (offset & 0xFFFF0000))
offset |= WLAN_IOREG_OFFSET;
#if HALMAC_SDIO_SUPPORT
ret_status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
#else
return HALMAC_RET_WRONG_INTF;
#endif
/* Verify CMD52 R/W */
wvalue8 = 0xab;
PLTFM_SDIO_CMD52_W(offset, wvalue8);
@@ -727,6 +731,9 @@ verify_io_88xx(struct halmac_adapter *adapter)
PLTFM_MSG_ERR("[ERR]cmd52 is used\n");
ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
}
#else
return HALMAC_RET_WRONG_INTF;
#endif
} else {
wvalue32 = 0x77665511;
PLTFM_REG_W32(REG_PAGE5_DUMMY, wvalue32);

15
hal/halmac/halmac_88xx/halmac_usb_88xx.c
View File

@@ -25,6 +25,9 @@ enum usb_burst_size {
USB_BURST_SIZE_UNDEFINE = 0x7F,
};
#define USB_PHY_PAGE0 0x9B
#define USB_PHY_PAGE1 0xBB
/**
* init_usb_cfg_88xx() - init USB
* @adapter : the adapter of halmac
@@ -522,4 +525,16 @@ en_ref_autok_usb_88xx(struct halmac_adapter *adapter, u8 en)
{
return HALMAC_RET_NOT_SUPPORT;
}
enum halmac_ret_status
usb_page_switch_88xx(struct halmac_adapter *adapter, u8 speed, u8 page)
{
if (speed == HAL_INTF_PHY_USB3)
return HALMAC_RET_SUCCESS;
if (page == 0)
usbphy_write_88xx(adapter, USB_REG_PAGE, USB_PHY_PAGE0, speed);
else
usbphy_write_88xx(adapter, USB_REG_PAGE, USB_PHY_PAGE1, speed);
return HALMAC_RET_SUCCESS;
}
#endif /* HALMAC_88XX_SUPPORT */

3
hal/halmac/halmac_88xx/halmac_usb_88xx.h
View File

@@ -85,6 +85,9 @@ usbphy_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed);
enum halmac_ret_status
en_ref_autok_usb_88xx(struct halmac_adapter *adapter, u8 en);
enum halmac_ret_status
usb_page_switch_88xx(struct halmac_adapter *adapter, u8 speed, u8 page);
#endif /* HALMAC_88XX_SUPPORT */
#endif/* _HALMAC_API_88XX_USB_H_ */

2
hal/halmac/halmac_api.c
View File

@@ -133,7 +133,7 @@ halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api,
"HALMAC_MAJOR_VER = %d\n"
"HALMAC_PROTOTYPE_VER = %d\n"
"HALMAC_MINOR_VER = %d\n"
"HALMAC_PATCH_VER = %s\n",
"HALMAC_PATCH_VER = %d\n",
HALMAC_MAJOR_VER, HALMAC_PROTOTYPE_VER,
HALMAC_MINOR_VER, HALMAC_PATCH_VER);

6
hal/halmac/halmac_api.h
View File

@@ -16,12 +16,12 @@
#ifndef _HALMAC_API_H_
#define _HALMAC_API_H_
#define HALMAC_SVN_VER "11692M"
#define HALMAC_SVN_VER "55772M"
#define HALMAC_MAJOR_VER 1
#define HALMAC_PROTOTYPE_VER 6
#define HALMAC_MINOR_VER 5
#define HALMAC_PATCH_VER "6*"
#define HALMAC_MINOR_VER 6
#define HALMAC_PATCH_VER 23
#define HALMAC_88XX_SUPPORT (HALMAC_8821C_SUPPORT || \
HALMAC_8822B_SUPPORT || \

20
hal/halmac/halmac_bit2.h
View File

@@ -71499,6 +71499,26 @@
#endif
#if (HALMAC_8822B_SUPPORT)
/* 2 REG_MACRX_HANG_TIMER_CONTROL (Offset 0x1661) */
#define BIT_TIMEOUT_COUNTER_EN BIT(7)
#define BIT_RESET_FIFO_CONTROL BIT(5)
#define BIT_SHIFT_COUNT_TIMEOUT 0
#define BIT_MASK_COUNT_TIMEOUT 0x1f
#define BIT_COUNT_TIMEOUT(x) \
(((x) & BIT_MASK_COUNT_TIMEOUT) << BIT_SHIFT_COUNT_TIMEOUT)
#define BITS_COUNT_TIMEOUT (BIT_MASK_COUNT_TIMEOUT << BIT_SHIFT_COUNT_TIMEOUT)
#define BIT_CLEAR_COUNT_TIMEOUT(x) ((x) & (~BITS_COUNT_TIMEOUT))
#define BIT_GET_COUNT_TIMEOUT(x) \
(((x) >> BIT_SHIFT_COUNT_TIMEOUT) & BIT_MASK_COUNT_TIMEOUT)
#define BIT_SET_COUNT_TIMEOUT(x, v) \
(BIT_CLEAR_COUNT_TIMEOUT(x) | BIT_COUNT_TIMEOUT(v))
#endif
#if (HALMAC_8814B_SUPPORT)
/* 2 REG_GENERAL_OPTION (Offset 0x1664) */

16
hal/halmac/halmac_bit_8822b.h
View File

@@ -15380,6 +15380,22 @@
#define BIT_CLI0_PWRBIT_OW_EN_8822B BIT(1)
#define BIT_CLI0_PWR_ST_8822B BIT(0)
/* 2 REG_MACRX_HANG_TIMER_CONTROL_8822B */
#define BIT_TIMEOUT_COUNTER_EN_8822B BIT(7)
#define BIT_RESET_FIFO_CONTROL_8822B BIT(5)
#define BIT_SHIFT_COUNT_TIMEOUT_8822B 0
#define BIT_MASK_COUNT_TIMEOUT_8822B 0x1f
#define BIT_COUNT_TIMEOUT_8822B(x) \
(((x) & BIT_MASK_COUNT_TIMEOUT_8822B) << BIT_SHIFT_COUNT_TIMEOUT_8822B)
#define BITS_COUNT_TIMEOUT_8822B \
(BIT_MASK_COUNT_TIMEOUT_8822B << BIT_SHIFT_COUNT_TIMEOUT_8822B)
#define BIT_CLEAR_COUNT_TIMEOUT_8822B(x) ((x) & (~BITS_COUNT_TIMEOUT_8822B))
#define BIT_GET_COUNT_TIMEOUT_8822B(x) \
(((x) >> BIT_SHIFT_COUNT_TIMEOUT_8822B) & BIT_MASK_COUNT_TIMEOUT_8822B)
#define BIT_SET_COUNT_TIMEOUT_8822B(x, v) \
(BIT_CLEAR_COUNT_TIMEOUT_8822B(x) | BIT_COUNT_TIMEOUT_8822B(v))
/* 2 REG_WMAC_MU_BF_OPTION_8822B */
#define BIT_WMAC_RESP_NONSTA1_DIS_8822B BIT(7)
#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN_8822B BIT(6)

83
hal/halmac/halmac_fw_offload_c2h_ap.h
View File

@@ -34,6 +34,7 @@
#define C2H_SUB_CMD_ID_FW_MEM_DUMP_ACK 0X01
#define C2H_SUB_CMD_ID_ACT_SCHEDULE_REQ_ACK 0X1
#define C2H_SUB_CMD_ID_NAN_FUNC_CTRL_ACK 0X1
#define C2H_SUB_CMD_ID_DPK_ACK 0X1
#define C2H_SUB_CMD_ID_PSD_DATA 0X04
#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
#define C2H_SUB_CMD_ID_IQK_DATA 0X06
@@ -60,6 +61,7 @@
#define C2H_SUB_CMD_ID_SCAN_CH_NOTIFY 0X22
#define C2H_SUB_CMD_ID_FW_TBTT_RPT 0X23
#define C2H_SUB_CMD_ID_BCN_OFFLOAD 0X24
#define C2H_SUB_CMD_ID_DPK_DATA 0X25
#define H2C_SUB_CMD_ID_CFG_PARAM_ACK SUB_CMD_ID_CFG_PARAM
#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH
#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX
@@ -75,6 +77,7 @@
#define H2C_SUB_CMD_ID_FW_MEM_DUMP_ACK SUB_CMD_ID_FW_MEM_DUMP
#define H2C_SUB_CMD_ID_ACT_SCHEDULE_REQ_ACK SUB_CMD_ID_ACT_SCHEDULE_REQ
#define H2C_SUB_CMD_ID_NAN_FUNC_CTRL_ACK SUB_CMD_ID_NAN_FUNC_CTRL
#define H2C_SUB_CMD_ID_DPK_ACK SUB_CMD_ID_DPK
#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT
#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG
#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING
@@ -96,6 +99,7 @@
#define H2C_CMD_ID_FW_MEM_DUMP_ACK 0XFF
#define H2C_CMD_ID_ACT_SCHEDULE_REQ_ACK 0XFF
#define H2C_CMD_ID_NAN_FUNC_CTRL_ACK 0XFF
#define H2C_CMD_ID_DPK_ACK 0XFF
#define H2C_CMD_ID_CCX_RPT 0XFF
#define H2C_CMD_ID_FW_DBG_MSG 0XFF
#define H2C_CMD_ID_FW_SNDING_ACK 0XFF
@@ -686,4 +690,83 @@
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
#define BCN_OFFLOAD_SET_STATUS_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
#define DPK_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7)
#define DPK_DATA_SET_SEGMENT_ID(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value)
#define DPK_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value)
#define DPK_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1)
#define DPK_DATA_SET_END_SEGMENT(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value)
#define DPK_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value)
#define DPK_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
#define DPK_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
#define DPK_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
#define DPK_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
#define DPK_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
#define DPK_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
#define DPK_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 16)
#define DPK_DATA_SET_H2C_SEQ(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 16, value)
#define DPK_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 16, value)
#define DPK_DATA_GET_PATH0_OK(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)
#define DPK_DATA_SET_PATH0_OK(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)
#define DPK_DATA_SET_PATH0_OK_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)
#define DPK_DATA_GET_PATH1_OK(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 24, 8)
#define DPK_DATA_SET_PATH1_OK(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value)
#define DPK_DATA_SET_PATH1_OK_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value)
#define DPK_DATA_GET_THERM0_S0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8)
#define DPK_DATA_SET_THERM0_S0(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value)
#define DPK_DATA_SET_THERM0_S0_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value)
#define DPK_DATA_GET_THERM0_S1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8)
#define DPK_DATA_SET_THERM0_S1(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value)
#define DPK_DATA_SET_THERM0_S1_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value)
#define DPK_DATA_GET_THERM1_S0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
#define DPK_DATA_SET_THERM1_S0(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
#define DPK_DATA_SET_THERM1_S0_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
#define DPK_DATA_GET_THERM1_S1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
#define DPK_DATA_SET_THERM1_S1(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
#define DPK_DATA_SET_THERM1_S1_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
#define DPK_DATA_GET_THERM_DELTA0_S0(c2h_pkt) \
GET_C2H_FIELD(c2h_pkt + 0X10, 0, 8)
#define DPK_DATA_SET_THERM_DELTA0_S0(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 0, 8, value)
#define DPK_DATA_SET_THERM_DELTA0_S0_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 0, 8, value)
#define DPK_DATA_GET_THERM_DELTA0_S1(c2h_pkt) \
GET_C2H_FIELD(c2h_pkt + 0X10, 8, 8)
#define DPK_DATA_SET_THERM_DELTA0_S1(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 8, 8, value)
#define DPK_DATA_SET_THERM_DELTA0_S1_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 8, 8, value)
#define DPK_DATA_GET_THERM_DELTA1_S0(c2h_pkt) \
GET_C2H_FIELD(c2h_pkt + 0X10, 16, 8)
#define DPK_DATA_SET_THERM_DELTA1_S0(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 16, 8, value)
#define DPK_DATA_SET_THERM_DELTA1_S0_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 16, 8, value)
#define DPK_DATA_GET_THERM_DELTA1_S1(c2h_pkt) \
GET_C2H_FIELD(c2h_pkt + 0X10, 24, 8)
#define DPK_DATA_SET_THERM_DELTA1_S1(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 24, 8, value)
#define DPK_DATA_SET_THERM_DELTA1_S1_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 24, 8, value)
#endif

55
hal/halmac/halmac_fw_offload_c2h_nic.h
View File

@@ -34,6 +34,7 @@
#define C2H_SUB_CMD_ID_FW_MEM_DUMP_ACK 0X01
#define C2H_SUB_CMD_ID_ACT_SCHEDULE_REQ_ACK 0X1
#define C2H_SUB_CMD_ID_NAN_FUNC_CTRL_ACK 0X1
#define C2H_SUB_CMD_ID_DPK_ACK 0X1
#define C2H_SUB_CMD_ID_PSD_DATA 0X04
#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
#define C2H_SUB_CMD_ID_IQK_DATA 0X06
@@ -60,6 +61,7 @@
#define C2H_SUB_CMD_ID_SCAN_CH_NOTIFY 0X22
#define C2H_SUB_CMD_ID_FW_TBTT_RPT 0X23
#define C2H_SUB_CMD_ID_BCN_OFFLOAD 0X24
#define C2H_SUB_CMD_ID_DPK_DATA 0X25
#define H2C_SUB_CMD_ID_CFG_PARAM_ACK SUB_CMD_ID_CFG_PARAM
#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH
#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX
@@ -75,6 +77,7 @@
#define H2C_SUB_CMD_ID_FW_MEM_DUMP_ACK SUB_CMD_ID_FW_MEM_DUMP
#define H2C_SUB_CMD_ID_ACT_SCHEDULE_REQ_ACK SUB_CMD_ID_ACT_SCHEDULE_REQ
#define H2C_SUB_CMD_ID_NAN_FUNC_CTRL_ACK SUB_CMD_ID_NAN_FUNC_CTRL
#define H2C_SUB_CMD_ID_DPK_ACK SUB_CMD_ID_DPK
#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT
#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG
#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING
@@ -96,6 +99,7 @@
#define H2C_CMD_ID_FW_MEM_DUMP_ACK 0XFF
#define H2C_CMD_ID_ACT_SCHEDULE_REQ_ACK 0XFF
#define H2C_CMD_ID_NAN_FUNC_CTRL_ACK 0XFF
#define H2C_CMD_ID_DPK_ACK 0XFF
#define H2C_CMD_ID_CCX_RPT 0XFF
#define H2C_CMD_ID_FW_DBG_MSG 0XFF
#define H2C_CMD_ID_FW_SNDING_ACK 0XFF
@@ -501,4 +505,55 @@
#define BCN_OFFLOAD_GET_STATUS(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
#define BCN_OFFLOAD_SET_STATUS(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
#define DPK_DATA_GET_SEGMENT_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7)
#define DPK_DATA_SET_SEGMENT_ID(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value)
#define DPK_DATA_GET_END_SEGMENT(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1)
#define DPK_DATA_SET_END_SEGMENT(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value)
#define DPK_DATA_GET_SEGMENT_SIZE(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
#define DPK_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
#define DPK_DATA_GET_TOTAL_SIZE(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
#define DPK_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
#define DPK_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 16)
#define DPK_DATA_SET_H2C_SEQ(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 16, value)
#define DPK_DATA_GET_PATH0_OK(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)
#define DPK_DATA_SET_PATH0_OK(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)
#define DPK_DATA_GET_PATH1_OK(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8)
#define DPK_DATA_SET_PATH1_OK(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value)
#define DPK_DATA_GET_THERM0_S0(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8)
#define DPK_DATA_SET_THERM0_S0(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value)
#define DPK_DATA_GET_THERM0_S1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8)
#define DPK_DATA_SET_THERM0_S1(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value)
#define DPK_DATA_GET_THERM1_S0(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
#define DPK_DATA_SET_THERM1_S0(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
#define DPK_DATA_GET_THERM1_S1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
#define DPK_DATA_SET_THERM1_S1(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
#define DPK_DATA_GET_THERM_DELTA0_S0(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 0, 8)
#define DPK_DATA_SET_THERM_DELTA0_S0(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 0, 8, value)
#define DPK_DATA_GET_THERM_DELTA0_S1(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 8, 8)
#define DPK_DATA_SET_THERM_DELTA0_S1(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 8, 8, value)
#define DPK_DATA_GET_THERM_DELTA1_S0(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 16, 8)
#define DPK_DATA_SET_THERM_DELTA1_S0(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 16, 8, value)
#define DPK_DATA_GET_THERM_DELTA1_S1(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 24, 8)
#define DPK_DATA_SET_THERM_DELTA1_S1(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 24, 8, value)
#endif

3
hal/halmac/halmac_fw_offload_h2c_ap.h
View File

@@ -44,6 +44,7 @@
#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF
#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF
#define CMD_ID_NAN_FUNC_CTRL 0XFF
#define CMD_ID_DPK 0XFF
#define CATEGORY_H2C_CMD_HEADER 0X00
#define CATEGORY_FW_OFFLOAD_H2C 0X01
#define CATEGORY_FW_ACCESS_TEST 0X01
@@ -74,6 +75,7 @@
#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01
#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01
#define CATEGORY_NAN_FUNC_CTRL 0X01
#define CATEGORY_DPK 0X01
#define SUB_CMD_ID_FW_ACCESS_TEST 0X00
#define SUB_CMD_ID_CH_SWITCH 0X02
#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
@@ -102,6 +104,7 @@
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
#define SUB_CMD_ID_NAN_FUNC_CTRL 0XB6
#define SUB_CMD_ID_DPK 0XB7
#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 7)
#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 7, value)

3
hal/halmac/halmac_fw_offload_h2c_nic.h
View File

@@ -44,6 +44,7 @@
#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF
#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF
#define CMD_ID_NAN_FUNC_CTRL 0XFF
#define CMD_ID_DPK 0XFF
#define CATEGORY_H2C_CMD_HEADER 0X00
#define CATEGORY_FW_OFFLOAD_H2C 0X01
#define CATEGORY_FW_ACCESS_TEST 0X01
@@ -74,6 +75,7 @@
#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01
#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01
#define CATEGORY_NAN_FUNC_CTRL 0X01
#define CATEGORY_DPK 0X01
#define SUB_CMD_ID_FW_ACCESS_TEST 0X00
#define SUB_CMD_ID_CH_SWITCH 0X02
#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
@@ -102,6 +104,7 @@
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
#define SUB_CMD_ID_NAN_FUNC_CTRL 0XB6
#define SUB_CMD_ID_DPK 0XB7
#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 7)
#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value) \

4
hal/halmac/halmac_gpio_cmd.h
View File

@@ -83,10 +83,10 @@
#define HALMAC_WL_DPDT_SEL 37
#define HALMAC_BT_PAPE_SEL 38
#define HALMAC_SW_PAPE_SEL 39
#define HALMAC_WLBT_PAPE_SEL 40
#define HALMAC_WL_PAPE_SEL 40
#define HALMAC_SW_LNAON_SET 41
#define HALMAC_BT_LNAON_SEL 42
#define HALMAC_WLBT_LNAON_SEL 43
#define HALMAC_WL_LNAON_SEL 43
#define HALMAC_SWR_CTRL_EN 44
#define HALMAC_UART_BRIDGE 45
#define HALMAC_BT_I2C 46

2
hal/halmac/halmac_intf_phy_cmd.h
View File

@@ -41,6 +41,8 @@ enum halmac_ip_sel {
enum halmac_intf_phy_platform {
HALMAC_INTF_PHY_PLATFORM_ALL = BIT(0),
HALMAC_INTF_PHY_PLATFORM_ASUS = BIT(1),
HALMAC_INTF_PHY_PLATFORM_LENOVO_V540 = BIT(2),
HALMAC_INTF_PHY_PLATFORM_DHC = BIT(3),
HALMAC_INTF_PHY_PLATFORM_FOR_ALL = 0x7FFF,
};

6
hal/halmac/halmac_reg2.h
View File

@@ -8021,6 +8021,12 @@
#endif
#if (HALMAC_8822B_SUPPORT)
#define REG_MACRX_HANG_TIMER_CONTROL 0x1661
#endif
#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
#define REG_GENERAL_OPTION 0x1664

1
hal/halmac/halmac_reg_8822b.h
View File

@@ -636,6 +636,7 @@
#define REG_BSSID4_8822B 0x1648
#define REG_NOA_REPORT_8822B 0x1650
#define REG_PWRBIT_SETTING_8822B 0x1660
#define REG_MACRX_HANG_TIMER_CONTROL_8822B 0x1661
#define REG_WMAC_MU_BF_OPTION_8822B 0x167C
#define REG_WMAC_MU_ARB_8822B 0x167E
#define REG_WMAC_MU_OPTION_8822B 0x167F

10
hal/halmac/halmac_state_machine.h
View File

@@ -128,6 +128,15 @@ struct halmac_iqk_state {
u16 seq_num;
};
struct halmac_dpk_state {
enum halmac_cmd_process_status proc_status;
u16 data_size;
u16 seg_size;
u8 *data;
u8 fw_rc;
u16 seq_num;
};
struct halmac_pwr_tracking_state {
enum halmac_cmd_process_status proc_status;
u8 fw_rc;
@@ -158,6 +167,7 @@ struct halmac_state {
struct halmac_scan_pkt_state scan_pkt_state;
struct halmac_drop_pkt_state drop_pkt_state;
struct halmac_iqk_state iqk_state;
struct halmac_dpk_state dpk_state;
struct halmac_pwr_tracking_state pwr_trk_state;
struct halmac_psd_state psd_state;
struct halmac_fw_snding_state fw_snding_state;

24
hal/halmac/halmac_type.h
View File

@@ -546,6 +546,7 @@ enum halmac_ret_status {
HALMAC_RET_INIT_XTAL_AAC_FAIL = 0x76,
HALMAC_RET_PINMUX_NOT_SUPPORT = 0x77,
HALMAC_RET_FWFF_NO_EMPTY = 0x78,
HALMAC_RET_ADR_NOT_ALIGN = 0x79,
};
enum halmac_chip_id {
@@ -565,6 +566,13 @@ enum halmac_chip_ver {
HALMAC_CHIP_VER_D_CUT = 0x03,
HALMAC_CHIP_VER_E_CUT = 0x04,
HALMAC_CHIP_VER_F_CUT = 0x05,
HALMAC_CHIP_VER_G_CUT = 0x06,
HALMAC_CHIP_VER_H_CUT = 0x07,
HALMAC_CHIP_VER_I_CUT = 0x08,
HALMAC_CHIP_VER_J_CUT = 0x09,
HALMAC_CHIP_VER_K_CUT = 0x0A,
HALMAC_CHIP_VER_L_CUT = 0x0B,
HALMAC_CHIP_VER_M_CUT = 0x0C,
HALMAC_CHIP_VER_TEST = 0xFF,
HALMAC_CHIP_VER_UNDEFINE = 0x7FFF,
};
@@ -1285,6 +1293,7 @@ enum halmac_feature_id {
HALMAC_FEATURE_POWER_TRACKING, /* Support */
HALMAC_FEATURE_PSD, /* Support */
HALMAC_FEATURE_FW_SNDING, /* Support */
HALMAC_FEATURE_DPK, /* Support */
HALMAC_FEATURE_ALL, /* Support, only for reset */
};
@@ -1649,8 +1658,10 @@ enum halmac_api_id {
HALMAC_API_CFGSPC_SET_PCIE = 0x9E,
HALMAC_API_GET_WATCHER = 0x9F,
HALMAC_API_DUMP_LOGICAL_EFUSE_MASK = 0xA0,
HALMAC_API_READ_WIFI_PHY_EFUSE = 0xA1,
HALMAC_API_WRITE_WIFI_PHY_EFUSE = 0xA2,
HALMAC_API_WRITE_LOGICAL_EFUSE_WORD = 0xA1,
HALMAC_API_READ_WIFI_PHY_EFUSE = 0xA2,
HALMAC_API_WRITE_WIFI_PHY_EFUSE = 0xA3,
HALMAC_API_START_DPK = 0xA4,
HALMAC_API_MAX
};
@@ -1798,6 +1809,8 @@ enum halmac_gpio_func {
HALMAC_GPIO_FUNC_S1_TRSW = 23,
HALMAC_GPIO_FUNC_S0_TRSWB = 24,
HALMAC_GPIO_FUNC_S1_TRSWB = 25,
HALMAC_GPIO_FUNC_ANTSW = 26,
HALMAC_GPIO_FUNC_ANTSWB = 27,
HALMAC_GPIO_FUNC_UNDEFINE = 0X7F,
};
@@ -2095,6 +2108,8 @@ struct halmac_pinmux_info {
u8 s1_pape:1;
u8 s0_trswb:1;
u8 s1_trswb:1;
u8 antswb:1;
u8 antsw:1;
};
struct halmac_ofld_func_info {
@@ -2279,6 +2294,9 @@ struct halmac_api {
(*halmac_write_logical_efuse)(struct halmac_adapter *adapter,
u32 offset, u8 value);
enum halmac_ret_status
(*halmac_write_logical_efuse_word)(struct halmac_adapter *adapter,
u32 offset, u16 value);
enum halmac_ret_status
(*halmac_read_logical_efuse)(struct halmac_adapter *adapter, u32 offset,
u8 *value);
enum halmac_ret_status
@@ -2423,6 +2441,8 @@ struct halmac_api {
(*halmac_start_iqk)(struct halmac_adapter *adapter,
struct halmac_iqk_para *param);
enum halmac_ret_status
(*halmac_start_dpk)(struct halmac_adapter *adapter);
enum halmac_ret_status
(*halmac_ctrl_pwr_tracking)(struct halmac_adapter *adapter,
struct halmac_pwr_tracking_option *opt);
enum halmac_ret_status

2
hal/halmac/halmac_usb_reg.h
View File

@@ -16,4 +16,6 @@
#ifndef __HALMAC_USB_REG_H__
#define __HALMAC_USB_REG_H__
#define USB_REG_PAGE 0xF4
#endif/* __HALMAC_USB_REG_H__ */