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RTL88x2B Driver from Realtek. Version: 5.3.1

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Rin Cat
2018-11-23 15:19:44 -05:00
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12062
hal/phydm/rtl8822b/halhwimg8822b_bb.c Normal file
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hal/phydm/rtl8822b/halhwimg8822b_bb.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.0*/
#if (RTL8822B_SUPPORT == 1)
#ifndef __INC_MP_BB_HW_IMG_8822B_H
#define __INC_MP_BB_HW_IMG_8822B_H
/******************************************************************************
* agc_tab.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_agc_tab(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_agc_tab(void);
/******************************************************************************
* phy_reg.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_phy_reg(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_phy_reg(void);
/******************************************************************************
* phy_reg_pg.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_phy_reg_pg(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_phy_reg_pg(void);
/******************************************************************************
* phy_reg_pg_type12.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_phy_reg_pg_type12(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_phy_reg_pg_type12(void);
/******************************************************************************
* phy_reg_pg_type15.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_phy_reg_pg_type15(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_phy_reg_pg_type15(void);
/******************************************************************************
* phy_reg_pg_type16.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_phy_reg_pg_type16(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_phy_reg_pg_type16(void);
/******************************************************************************
* phy_reg_pg_type17.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_phy_reg_pg_type17(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_phy_reg_pg_type17(void);
/******************************************************************************
* phy_reg_pg_type2.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_phy_reg_pg_type2(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_phy_reg_pg_type2(void);
/******************************************************************************
* phy_reg_pg_type3.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_phy_reg_pg_type3(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_phy_reg_pg_type3(void);
/******************************************************************************
* phy_reg_pg_type4.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_phy_reg_pg_type4(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_phy_reg_pg_type4(void);
/******************************************************************************
* phy_reg_pg_type5.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_phy_reg_pg_type5(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_phy_reg_pg_type5(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

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hal/phydm/rtl8822b/halhwimg8822b_mac.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.0*/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8822B_SUPPORT == 1)
static boolean
check_positive(
struct dm_struct *dm,
const u32 condition1,
const u32 condition2,
const u32 condition3,
const u32 condition4
)
{
u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
u8 cut_version_for_para = (dm->cut_version == ODM_CUT_A) ? 15 : dm->cut_version;
u8 pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type;
u32 driver1 = cut_version_for_para << 24 |
(dm->support_interface & 0xF0) << 16 |
dm->support_platform << 16 |
pkg_type_for_para << 12 |
(dm->support_interface & 0x0F) << 8 |
dm->rfe_type;
u32 driver2 = (dm->type_glna & 0xFF) << 0 |
(dm->type_gpa & 0xFF) << 8 |
(dm->type_alna & 0xFF) << 16 |
(dm->type_apa & 0xFF) << 24;
u32 driver3 = 0;
u32 driver4 = (dm->type_glna & 0xFF00) >> 8 |
(dm->type_gpa & 0xFF00) |
(dm->type_alna & 0xFF00) << 8 |
(dm->type_apa & 0xFF00) << 16;
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4);
PHYDM_DBG(dm, ODM_COMP_INIT,
" (Platform, Interface) = (0x%X, 0x%X)\n", dm->support_platform, dm->support_interface);
PHYDM_DBG(dm, ODM_COMP_INIT,
" (RFE, Package) = (0x%X, 0x%X)\n", dm->rfe_type, dm->package_type);
/*============== value Defined Check ===============*/
/*cut version [27:24] need to do value check*/
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
return false;
/*pkg type [15:12] need to do value check*/
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return false;
/*interface [11:8] need to do value check*/
if (((cond1 & 0x00000F00) != 0) && ((cond1 & 0x00000F00) != (driver1 & 0x00000F00)))
return false;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x000000FF;
driver1 &= 0x000000FF;
if (cond1 == driver1)
return true;
else
return false;
}
static boolean
check_negative(
struct dm_struct *dm,
const u32 condition1,
const u32 condition2
)
{
return true;
}
/******************************************************************************
* mac_reg.TXT
******************************************************************************/
u32 array_mp_8822b_mac_reg[] = {
0x029, 0x000000F9,
0x420, 0x00000080,
0x421, 0x0000001F,
0x428, 0x0000000A,
0x429, 0x00000010,
0x430, 0x00000000,
0x431, 0x00000000,
0x432, 0x00000000,
0x433, 0x00000001,
0x434, 0x00000004,
0x435, 0x00000005,
0x436, 0x00000007,
0x437, 0x00000008,
0x43C, 0x00000004,
0x43D, 0x00000005,
0x43E, 0x00000007,
0x43F, 0x00000008,
0x440, 0x0000005D,
0x441, 0x00000001,
0x442, 0x00000000,
0x444, 0x00000010,
0x445, 0x000000F0,
0x446, 0x00000001,
0x447, 0x000000FE,
0x448, 0x00000000,
0x449, 0x00000000,
0x44A, 0x00000000,
0x44B, 0x00000040,
0x44C, 0x00000010,
0x44D, 0x000000F0,
0x44E, 0x0000003F,
0x44F, 0x00000000,
0x450, 0x00000000,
0x451, 0x00000000,
0x452, 0x00000000,
0x453, 0x00000040,
0x455, 0x00000070,
0x45E, 0x00000004,
0x49C, 0x00000010,
0x49D, 0x000000F0,
0x49E, 0x00000000,
0x49F, 0x00000006,
0x4A0, 0x000000E0,
0x4A1, 0x00000003,
0x4A2, 0x00000000,
0x4A3, 0x00000040,
0x4A4, 0x00000015,
0x4A5, 0x000000F0,
0x4A6, 0x00000000,
0x4A7, 0x00000006,
0x4A8, 0x000000E0,
0x4A9, 0x00000000,
0x4AA, 0x00000000,
0x4AB, 0x00000000,
0x7DA, 0x00000008,
0x1448, 0x00000006,
0x144A, 0x00000006,
0x144C, 0x00000006,
0x144E, 0x00000006,
0x4C8, 0x000000FF,
0x4C9, 0x00000008,
0x4CA, 0x00000020,
0x4CB, 0x00000020,
0x4CC, 0x000000FF,
0x4CD, 0x000000FF,
0x4CE, 0x00000001,
0x4CF, 0x00000008,
0x500, 0x00000026,
0x501, 0x000000A2,
0x502, 0x0000002F,
0x503, 0x00000000,
0x504, 0x00000028,
0x505, 0x000000A3,
0x506, 0x0000005E,
0x507, 0x00000000,
0x508, 0x0000002B,
0x509, 0x000000A4,
0x50A, 0x0000005E,
0x50B, 0x00000000,
0x50C, 0x0000004F,
0x50D, 0x000000A4,
0x50E, 0x00000000,
0x50F, 0x00000000,
0x512, 0x0000001C,
0x514, 0x0000000A,
0x516, 0x0000000A,
0x521, 0x0000002F,
0x525, 0x0000004F,
0x551, 0x00000010,
0x559, 0x00000002,
0x55C, 0x00000050,
0x55D, 0x000000FF,
0x577, 0x0000000B,
0x5BE, 0x00000064,
0x605, 0x00000030,
0x608, 0x0000000E,
0x609, 0x00000022,
0x60C, 0x00000018,
0x6A0, 0x000000FF,
0x6A1, 0x000000FF,
0x6A2, 0x000000FF,
0x6A3, 0x000000FF,
0x6A4, 0x000000FF,
0x6A5, 0x000000FF,
0x6DE, 0x00000084,
0x620, 0x000000FF,
0x621, 0x000000FF,
0x622, 0x000000FF,
0x623, 0x000000FF,
0x624, 0x000000FF,
0x625, 0x000000FF,
0x626, 0x000000FF,
0x627, 0x000000FF,
0x638, 0x00000050,
0x63C, 0x0000000A,
0x63D, 0x0000000A,
0x63E, 0x0000000E,
0x63F, 0x0000000E,
0x640, 0x00000040,
0x642, 0x00000040,
0x643, 0x00000000,
0x652, 0x000000C8,
0x66E, 0x00000005,
0x718, 0x00000040,
0x7D4, 0x00000098,
};
void
odm_read_and_config_mp_8822b_mac_reg(
struct dm_struct *dm
)
{
u32 i = 0;
u8 c_cond;
boolean is_matched = true, is_skipped = false;
u32 array_len = sizeof(array_mp_8822b_mac_reg)/sizeof(u32);
u32 *array = array_mp_8822b_mac_reg;
u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8822b_mac_reg\n");
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
if (v1 & BIT(31)) {/* positive condition*/
c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28);
if (c_cond == COND_ENDIF) {/*end*/
is_matched = true;
is_skipped = false;
PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
} else if (c_cond == COND_ELSE) { /*else*/
is_matched = is_skipped?false:true;
PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
} else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
}
} else if (v1 & BIT(30)) { /*negative condition*/
if (is_skipped == false) {
if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
is_matched = true;
is_skipped = true;
} else {
is_matched = false;
is_skipped = false;
}
} else
is_matched = false;
}
} else {
if (is_matched)
odm_config_mac_8822b(dm, v1, (u8)v2);
}
i = i + 2;
}
}
u32
odm_get_version_mp_8822b_mac_reg(void)
{
return 104;
}
#endif /* end of HWIMG_SUPPORT*/

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hal/phydm/rtl8822b/halhwimg8822b_mac.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.0*/
#if (RTL8822B_SUPPORT == 1)
#ifndef __INC_MP_MAC_HW_IMG_8822B_H
#define __INC_MP_MAC_HW_IMG_8822B_H
/******************************************************************************
* mac_reg.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_mac_reg(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_mac_reg(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

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hal/phydm/rtl8822b/halhwimg8822b_rf.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*Image2HeaderVersion: R3 1.0*/
#if (RTL8822B_SUPPORT == 1)
#ifndef __INC_MP_RF_HW_IMG_8822B_H
#define __INC_MP_RF_HW_IMG_8822B_H
/******************************************************************************
* radioa.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_radioa(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_radioa(void);
/******************************************************************************
* radiob.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_radiob(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_radiob(void);
/******************************************************************************
* txpowertrack.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpowertrack(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpowertrack(void);
/******************************************************************************
* txpowertrack_type0.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpowertrack_type0(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpowertrack_type0(void);
/******************************************************************************
* txpowertrack_type1.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpowertrack_type1(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpowertrack_type1(void);
/******************************************************************************
* txpowertrack_type10.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpowertrack_type10(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpowertrack_type10(void);
/******************************************************************************
* txpowertrack_type11.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpowertrack_type11(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpowertrack_type11(void);
/******************************************************************************
* txpowertrack_type12.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpowertrack_type12(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpowertrack_type12(void);
/******************************************************************************
* txpowertrack_type13.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpowertrack_type13(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpowertrack_type13(void);
/******************************************************************************
* txpowertrack_type14.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpowertrack_type14(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpowertrack_type14(void);
/******************************************************************************
* txpowertrack_type15.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpowertrack_type15(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpowertrack_type15(void);
/******************************************************************************
* txpowertrack_type16.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpowertrack_type16(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpowertrack_type16(void);
/******************************************************************************
* txpowertrack_type17.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpowertrack_type17(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpowertrack_type17(void);
/******************************************************************************
* txpowertrack_type2.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpowertrack_type2(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpowertrack_type2(void);
/******************************************************************************
* txpowertrack_type3_type5.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpowertrack_type3_type5(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpowertrack_type3_type5(void);
/******************************************************************************
* txpowertrack_type4.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpowertrack_type4(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpowertrack_type4(void);
/******************************************************************************
* txpowertrack_type6.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpowertrack_type6(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpowertrack_type6(void);
/******************************************************************************
* txpowertrack_type7.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpowertrack_type7(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpowertrack_type7(void);
/******************************************************************************
* txpowertrack_type8.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpowertrack_type8(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpowertrack_type8(void);
/******************************************************************************
* txpowertrack_type9.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpowertrack_type9(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpowertrack_type9(void);
/******************************************************************************
* txpwr_lmt.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpwr_lmt(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpwr_lmt(void);
/******************************************************************************
* txpwr_lmt_type12.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type12(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpwr_lmt_type12(void);
/******************************************************************************
* txpwr_lmt_type15.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type15(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpwr_lmt_type15(void);
/******************************************************************************
* txpwr_lmt_type16.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type16(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpwr_lmt_type16(void);
/******************************************************************************
* txpwr_lmt_type17.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type17(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpwr_lmt_type17(void);
/******************************************************************************
* txpwr_lmt_type2.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type2(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpwr_lmt_type2(void);
/******************************************************************************
* txpwr_lmt_type3.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type3(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpwr_lmt_type3(void);
/******************************************************************************
* txpwr_lmt_type4.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type4(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpwr_lmt_type4(void);
/******************************************************************************
* txpwr_lmt_type5.TXT
******************************************************************************/
void
odm_read_and_config_mp_8822b_txpwr_lmt_type5(/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8822b_txpwr_lmt_type5(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

14
hal/phydm/rtl8822b/mp_precomp.h Normal file
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/******************************************************************************
*
* Copyright(c) 2015 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/

2147
hal/phydm/rtl8822b/phydm_hal_api8822b.c Normal file
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167
hal/phydm/rtl8822b/phydm_hal_api8822b.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __INC_PHYDM_API_H_8822B__
#define __INC_PHYDM_API_H_8822B__
#if (RTL8822B_SUPPORT == 1)
#define PHY_CONFIG_VERSION_8822B "28.5.34" /*2017.01.18 (HW user guide version: R28, SW user guide version: R05, Modification: R34), remove A cut setting, refine CCK txfilter and OFDM CCA setting by YuChen*/
#define SMTANT_TMP_RFE_TYPE 100
#define INVALID_RF_DATA 0xffffffff
#define INVALID_TXAGC_DATA 0xff
#define PSD_VAL_NUM 5
#define PSD_SMP_NUM 3
#define FREQ_PT_2G_NUM 14
#define FREQ_PT_5G_NUM 10
#define number_channel_interferecne 4
#define config_phydm_read_rf_check_8822b(data) (data != INVALID_RF_DATA)
#define config_phydm_read_txagc_check_8822b(data) (data != INVALID_TXAGC_DATA)
void
phydm_rxagc_switch_8822b(
struct dm_struct *dm,
boolean enable_rxagc_swich
);
void
phydm_rfe_8822b_init(
struct dm_struct *dm
);
boolean
phydm_rfe_8822b(
struct dm_struct *dm,
u8 channel
);
u32
config_phydm_read_rf_reg_8822b(
struct dm_struct *dm,
enum rf_path path,
u32 reg_addr,
u32 bit_mask
);
boolean
config_phydm_write_rf_reg_8822b(
struct dm_struct *dm,
enum rf_path path,
u32 reg_addr,
u32 bit_mask,
u32 data
);
boolean
config_phydm_write_txagc_8822b(
struct dm_struct *dm,
u32 power_index,
enum rf_path path,
u8 hw_rate
);
u8
config_phydm_read_txagc_8822b(
struct dm_struct *dm,
enum rf_path path,
u8 hw_rate
);
void
phydm_dynamic_spur_det_eliminate(
struct dm_struct *dm
);
boolean
config_phydm_switch_band_8822b(
struct dm_struct *dm,
u8 central_ch
);
boolean
config_phydm_switch_channel_8822b(
struct dm_struct *dm,
u8 central_ch
);
boolean
config_phydm_switch_bandwidth_8822b(
struct dm_struct *dm,
u8 primary_ch_idx,
enum channel_width bandwidth
);
boolean
config_phydm_switch_channel_bw_8822b(
struct dm_struct *dm,
u8 central_ch,
u8 primary_ch_idx,
enum channel_width bandwidth
);
boolean
config_phydm_trx_mode_8822b(
struct dm_struct *dm,
enum bb_path tx_path,
enum bb_path rx_path,
boolean is_tx2_path
);
boolean
config_phydm_parameter_init_8822b(
struct dm_struct *dm,
enum odm_parameter_init type
);
/* ======================================================================== */
/* These following functions can be used for PHY DM only*/
boolean
phydm_write_txagc_1byte_8822b(
struct dm_struct *dm,
u32 power_index,
enum rf_path path,
u8 hw_rate
);
void
phydm_init_hw_info_by_rfe_type_8822b(
struct dm_struct *dm
);
s32
phydm_get_condition_number_8822B(
struct dm_struct *dm
);
/* ======================================================================== */
#endif /* RTL8822B_SUPPORT == 1 */
#endif /* __INC_PHYDM_API_H_8822B__ */

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hal/phydm/rtl8822b/phydm_regconfig8822b.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8822B_SUPPORT == 1)
void
odm_config_rf_reg_8822b(
struct dm_struct *dm,
u32 addr,
u32 data,
enum rf_path rf_path,
u32 reg_addr
)
{
if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
if (addr == 0xffe)
phydm_set_reg_by_fw(dm,
PHYDM_HALMAC_CMD_DELAY_MS,
reg_addr,
data,
RFREGOFFSETMASK,
rf_path,
50);
else if (addr == 0xfe)
phydm_set_reg_by_fw(dm,
PHYDM_HALMAC_CMD_DELAY_US,
reg_addr,
data,
RFREGOFFSETMASK,
rf_path,
100);
else {
phydm_set_reg_by_fw(dm,
PHYDM_HALMAC_CMD_RF_W,
reg_addr,
data,
RFREGOFFSETMASK,
rf_path,
0);
phydm_set_reg_by_fw(dm,
PHYDM_HALMAC_CMD_DELAY_US,
reg_addr,
data,
RFREGOFFSETMASK,
rf_path,
1);
}
} else {
if (addr == 0xffe) {
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
} else if (addr == 0xfe) {
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_us(100);
#else
ODM_delay_us(100);
#endif
} else {
odm_set_rf_reg(dm, rf_path, reg_addr, RFREGOFFSETMASK, data);
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
}
}
}
void
odm_config_rf_radio_a_8822b(
struct dm_struct *dm,
u32 addr,
u32 data
)
{
u32 content = 0x1000; /* RF_Content: radioa_txt */
u32 maskfor_phy_set = (u32)(content & 0xE000);
odm_config_rf_reg_8822b(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_rf: [RadioA] %08X %08X\n", addr, data);
}
void
odm_config_rf_radio_b_8822b(
struct dm_struct *dm,
u32 addr,
u32 data
)
{
u32 content = 0x1001; /* RF_Content: radiob_txt */
u32 maskfor_phy_set = (u32)(content & 0xE000);
odm_config_rf_reg_8822b(dm, addr, data, RF_PATH_B, addr | maskfor_phy_set);
PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_rf: [RadioB] %08X %08X\n", addr, data);
}
void
odm_config_mac_8822b(
struct dm_struct *dm,
u32 addr,
u8 data
)
{
if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD)
phydm_set_reg_by_fw(dm,
PHYDM_HALMAC_CMD_MAC_W8,
addr,
data,
0,
(enum rf_path)0,
0);
else
odm_write_1byte(dm, addr, data);
PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_mac: [MAC_REG] %08X %08X\n", addr, data);
}
void
odm_update_agc_big_jump_lmt_8822b(
struct dm_struct *dm,
u32 addr,
u32 data
)
{
struct phydm_dig_struct *dig_tab = &dm->dm_dig_table;
u8 rf_gain_idx = (u8)((data & 0xFF000000) >> 24);
u8 bb_gain_idx = (u8)((data & 0x00ff0000) >> 16);
u8 agc_table_idx = (u8)((data & 0x00000f00) >> 8);
static boolean is_limit;
if (addr != 0x81c)
return;
/*dbg_print("data = 0x%x, rf_gain_idx = 0x%x, bb_gain_idx = 0x%x, agc_table_idx = 0x%x\n", data, rf_gain_idx, bb_gain_idx, agc_table_idx);*/
/*dbg_print("rf_gain_idx = 0x%x, dig_tab->rf_gain_idx = 0x%x\n", rf_gain_idx, dig_tab->rf_gain_idx);*/
if (bb_gain_idx > 0x3c) {
if ((rf_gain_idx == dig_tab->rf_gain_idx) && !is_limit) {
is_limit = true;
dig_tab->big_jump_lmt[agc_table_idx] = bb_gain_idx - 2;
PHYDM_DBG(dm, DBG_DIG, "===> [AGC_TAB] big_jump_lmt [%d] = 0x%x\n", agc_table_idx, dig_tab->big_jump_lmt[agc_table_idx]);
}
} else
is_limit = false;
dig_tab->rf_gain_idx = rf_gain_idx;
}
void
odm_config_bb_agc_8822b(
struct dm_struct *dm,
u32 addr,
u32 bitmask,
u32 data
)
{
odm_update_agc_big_jump_lmt_8822b(dm, addr, data);
if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD)
phydm_set_reg_by_fw(dm,
PHYDM_HALMAC_CMD_BB_W32,
addr,
data,
bitmask,
(enum rf_path)0,
0);
else
odm_set_bb_reg(dm, addr, bitmask, data);
PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_bb: [AGC_TAB] %08X %08X\n", addr, data);
}
void
odm_config_bb_phy_reg_pg_8822b(
struct dm_struct *dm,
u32 band,
u32 rf_path,
u32 tx_num,
u32 addr,
u32 bitmask,
u32 data
)
{
if (addr == 0xfe || addr == 0xffe) {
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
} else {
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
PHY_StoreTxPowerByRate((PADAPTER)dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
#endif
}
PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_bb: [PHY_REG] %08X %08X %08X\n", addr, bitmask, data);
}
void
odm_config_bb_phy_8822b(
struct dm_struct *dm,
u32 addr,
u32 bitmask,
u32 data
)
{
if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
u32 delay_time = 0;
if (addr >= 0xf9 && addr <= 0xfe) {
if (addr == 0xfe || addr == 0xfb)
delay_time = 50;
else if (addr == 0xfd || addr == 0xfa)
delay_time = 5;
else
delay_time = 1;
if (addr >= 0xfc && addr <=0xfe)
phydm_set_reg_by_fw(dm,
PHYDM_HALMAC_CMD_DELAY_MS,
addr,
data,
bitmask,
(enum rf_path)0,
delay_time);
else
phydm_set_reg_by_fw(dm,
PHYDM_HALMAC_CMD_DELAY_US,
addr,
data,
bitmask,
(enum rf_path)0,
delay_time);
} else
phydm_set_reg_by_fw(dm,
PHYDM_HALMAC_CMD_BB_W32,
addr,
data,
bitmask,
(enum rf_path)0,
0);
} else {
if (addr == 0xfe)
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else if (addr == 0xfd)
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
else
odm_set_bb_reg(dm, addr, bitmask, data);
}
PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_bb: [PHY_REG] %08X %08X\n", addr, data);
}
void
odm_config_bb_txpwr_lmt_8822b(
struct dm_struct *dm,
u8 *regulation,
u8 *band,
u8 *bandwidth,
u8 *rate_section,
u8 *rf_path,
u8 *channel,
u8 *power_limit
)
{
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
phy_set_tx_power_limit(dm, regulation, band,
bandwidth, rate_section, rf_path, channel, power_limit);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
PHY_SetTxPowerLimit(dm, regulation, band,
bandwidth, rate_section, rf_path, channel, power_limit);
#endif
}
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __INC_ODM_REGCONFIG_H_8822B
#define __INC_ODM_REGCONFIG_H_8822B
#if (RTL8822B_SUPPORT == 1)
void
odm_config_rf_reg_8822b(
struct dm_struct *dm,
u32 addr,
u32 data,
enum rf_path rf_path,
u32 reg_addr
);
void
odm_config_rf_radio_a_8822b(
struct dm_struct *dm,
u32 addr,
u32 data
);
void
odm_config_rf_radio_b_8822b(
struct dm_struct *dm,
u32 addr,
u32 data
);
void
odm_config_mac_8822b(
struct dm_struct *dm,
u32 addr,
u8 data
);
void
odm_update_agc_big_jump_lmt_8822b(
struct dm_struct *dm,
u32 addr,
u32 data
);
void
odm_config_bb_agc_8822b(
struct dm_struct *dm,
u32 addr,
u32 bitmask,
u32 data
);
void
odm_config_bb_phy_reg_pg_8822b(
struct dm_struct *dm,
u32 band,
u32 rf_path,
u32 tx_num,
u32 addr,
u32 bitmask,
u32 data
);
void
odm_config_bb_phy_8822b(
struct dm_struct *dm,
u32 addr,
u32 bitmask,
u32 data
);
void
odm_config_bb_txpwr_lmt_8822b(
struct dm_struct *dm,
u8 *regulation,
u8 *band,
u8 *bandwidth,
u8 *rate_section,
u8 *rf_path,
u8 *channel,
u8 *power_limit
);
#endif
#endif /* RTL8822B_SUPPORT == 1*/

515
hal/phydm/rtl8822b/phydm_rtl8822b.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8822B_SUPPORT == 1)
void
phydm_dynamic_switch_htstf_mumimo_8822b(
struct dm_struct *dm
)
{
u8 rssi_l2h = 40, rssi_h2l = 35;
/*if Pin > -60dBm, enable HT-STF gain controller, otherwise, if rssi < -65dBm, disable the controller*/
if (dm->rssi_min >= rssi_l2h)
odm_set_bb_reg(dm, 0x8d8, BIT(17), 0x1);
else if (dm->rssi_min < rssi_h2l)
odm_set_bb_reg(dm, 0x8d8, BIT(17), 0x0);
}
void
phydm_dynamic_parameters_ota(
struct dm_struct *dm
)
{
u8 rssi_l2h = 40, rssi_h2l = 35;
if ((*dm->channel <= 14) && (*dm->band_width == CHANNEL_WIDTH_20)) {
if (dm->rssi_min >= rssi_l2h) {
/*if (dm->bhtstfdisabled == false)*/
odm_set_bb_reg(dm, 0x8d8, BIT(17), 0x1);
odm_set_bb_reg(dm, 0x98c, 0x7fc0000, 0x0);
odm_set_bb_reg(dm, 0x818, 0x7000000, 0x1);
odm_set_bb_reg(dm, 0xc04, BIT(18), 0x0);
odm_set_bb_reg(dm, 0xe04, BIT(18), 0x0);
if (dm->p_advance_ota & PHYDM_HP_OTA_SETTING_A) {
odm_set_bb_reg(dm, 0x19d8, MASKDWORD, 0x444);
odm_set_bb_reg(dm, 0x19d4, MASKDWORD, 0x4444aaaa);
} else if (dm->p_advance_ota & PHYDM_HP_OTA_SETTING_B) {
odm_set_bb_reg(dm, 0x19d8, MASKDWORD, 0x444);
odm_set_bb_reg(dm, 0x19d4, MASKDWORD, 0x444444aa);
}
} else if (dm->rssi_min < rssi_h2l) {
/*if (dm->bhtstfdisabled == true)*/
odm_set_bb_reg(dm, 0x8d8, BIT(17), 0x0);
odm_set_bb_reg(dm, 0x98c, MASKDWORD, 0x43440000);
odm_set_bb_reg(dm, 0x818, 0x7000000, 0x4);
odm_set_bb_reg(dm, 0xc04, (BIT(18)|BIT(21)), 0x0);
odm_set_bb_reg(dm, 0xe04, (BIT(18)|BIT(21)), 0x0);
odm_set_bb_reg(dm, 0x19d8, MASKDWORD, 0xaaa);
odm_set_bb_reg(dm, 0x19d4, MASKDWORD, 0xaaaaaaaa);
}
} else {
//odm_set_bb_reg(dm, 0x8d8, BIT(17), 0x0);
odm_set_bb_reg(dm, 0x98c, MASKDWORD, 0x43440000);
odm_set_bb_reg(dm, 0x818, 0x7000000, 0x4);
odm_set_bb_reg(dm, 0xc04, (BIT(18)|BIT(21)), 0x0);
odm_set_bb_reg(dm, 0xe04, (BIT(18)|BIT(21)), 0x0);
odm_set_bb_reg(dm, 0x19d8, MASKDWORD, 0xaaa);
odm_set_bb_reg(dm, 0x19d4, MASKDWORD, 0xaaaaaaaa);
}
}
static
void
_set_tx_a_cali_value(
struct dm_struct *dm,
enum rf_path rf_path,
u8 offset,
u8 tx_a_bias_offset
)
{
u32 modi_tx_a_value = 0;
u8 tmp1_byte = 0;
boolean is_minus = false;
u8 comp_value = 0;
switch (offset) {
case 0x0:
odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10124);
break;
case 0x1:
odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10524);
break;
case 0x2:
odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10924);
break;
case 0x3:
odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10D24);
break;
case 0x4:
odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30164);
break;
case 0x5:
odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30564);
break;
case 0x6:
odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30964);
break;
case 0x7:
odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30D64);
break;
case 0x8:
odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50195);
break;
case 0x9:
odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50595);
break;
case 0xa:
odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50995);
break;
case 0xb:
odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50D95);
break;
default:
PHYDM_DBG(dm, ODM_COMP_API, "Invalid TxA band offset...\n");
return;
break;
}
/* Get TxA value */
modi_tx_a_value = odm_get_rf_reg(dm, rf_path, 0x61, 0xFFFFF);
tmp1_byte = (u8)modi_tx_a_value&(BIT(3)|BIT(2)|BIT(1)|BIT(0));
/* check how much need to calibration */
switch (tx_a_bias_offset) {
case 0xF6:
is_minus = true;
comp_value = 3;
break;
case 0xF4:
is_minus = true;
comp_value = 2;
break;
case 0xF2:
is_minus = true;
comp_value = 1;
break;
case 0xF3:
is_minus = false;
comp_value = 1;
break;
case 0xF5:
is_minus = false;
comp_value = 2;
break;
case 0xF7:
is_minus = false;
comp_value = 3;
break;
case 0xF9:
is_minus = false;
comp_value = 4;
break;
/* do nothing case */
case 0xF0:
default:
PHYDM_DBG(dm, ODM_COMP_API, "No need to do TxA bias current calibration\n");
return;
break;
}
/* calc correct value to calibrate */
if (is_minus) {
if (tmp1_byte >= comp_value) {
tmp1_byte -= comp_value;
//modi_tx_a_value += tmp1_byte;
} else {
tmp1_byte = 0;
}
} else {
tmp1_byte += comp_value;
if (tmp1_byte >= 7) {
tmp1_byte = 7;
}
}
/* Write back to RF reg */
odm_set_rf_reg(dm, rf_path, 0x30, 0xFFFF, (offset<<12|(modi_tx_a_value&0xFF0)|tmp1_byte));
}
static
void
_txa_bias_cali_4_each_path(
struct dm_struct *dm,
u8 rf_path,
u8 efuse_value
)
{
/* switch on set TxA bias */
odm_set_rf_reg(dm, rf_path, 0xEF, 0xFFFFF, 0x200);
/* Set 12 sets of TxA value */
_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x0, efuse_value);
_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x1, efuse_value);
_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x2, efuse_value);
_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x3, efuse_value);
_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x4, efuse_value);
_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x5, efuse_value);
_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x6, efuse_value);
_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x7, efuse_value);
_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x8, efuse_value);
_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x9, efuse_value);
_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0xa, efuse_value);
_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0xb, efuse_value);
// switch off set TxA bias
odm_set_rf_reg(dm, rf_path, 0xEF, 0xFFFFF, 0x0);
}
/* for 8822B PCIE D-cut patch only */
/* Normal driver and MP driver need this patch */
void
phydm_txcurrentcalibration(
struct dm_struct *dm
)
{
u8 efuse0x3D8, efuse0x3D7;
u32 orig_rf0x18_path_a = 0, orig_rf0x18_path_b = 0;
if (!(dm->support_ic_type & ODM_RTL8822B))
return;
PHYDM_DBG(dm, ODM_COMP_MP, "8822b 5g tx current calibration 0x3d7=0x%X 0x3d8=0x%X\n", dm->efuse0x3d7, dm->efuse0x3d8);
/* save original 0x18 value */
orig_rf0x18_path_a = odm_get_rf_reg(dm, RF_PATH_A, 0x18, 0xFFFFF);
orig_rf0x18_path_b = odm_get_rf_reg(dm, RF_PATH_B, 0x18, 0xFFFFF);
/* define efuse content */
efuse0x3D8 = dm->efuse0x3d8;
efuse0x3D7 = dm->efuse0x3d7;
/* check efuse content to judge whether need to calibration or not */
if (0xFF == efuse0x3D7) {
PHYDM_DBG(dm, ODM_COMP_MP, "efuse content 0x3D7 == 0xFF, No need to do TxA cali\n");
return;
}
/* write RF register for calibration */
_txa_bias_cali_4_each_path(dm, RF_PATH_A, efuse0x3D7);
_txa_bias_cali_4_each_path(dm, RF_PATH_B, efuse0x3D8);
/* restore original 0x18 value */
odm_set_rf_reg(dm, RF_PATH_A, 0x18, 0xFFFFF, orig_rf0x18_path_a);
odm_set_rf_reg(dm, RF_PATH_B, 0x18, 0xFFFFF, orig_rf0x18_path_b);
}
void
phydm_1rcca_setting(
struct dm_struct *dm,
boolean enable_1rcca
)
{
u32 reg_32;
reg_32 = odm_get_bb_reg(dm, 0xa04, 0x0f000000);
/* Enable or disable 1RCCA setting accrodding to the control from driver */
if (enable_1rcca == true) {
if (reg_32 == 0x0) {
odm_set_bb_reg(dm, 0x808, MASKBYTE0, 0x13); /* CCK path-a */
} else if (reg_32 == 0x5) {
odm_set_bb_reg(dm, 0x808, MASKBYTE0, 0x23); /* CCK path-b */
}
} else {
odm_set_bb_reg(dm, 0x808, MASKBYTE0, 0x33); /* disable 1RCCA */
odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x0); /* CCK default is at path-a */
}
}
void
phydm_dynamic_select_cck_path_8822b(
struct dm_struct *dm
)
{
struct phydm_fa_struct *fa_cnt = (struct phydm_fa_struct *)phydm_get_structure(dm, PHYDM_FALSEALMCNT);
struct drp_rtl8822b_struct *drp_8822b = &dm->phydm_rtl8822b;
if (dm->ap_total_num > 10) {
if (drp_8822b->path_judge & BIT(2))
odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x0); /*fix CCK Path A if AP nums > 10*/
return;
}
if (drp_8822b->path_judge & BIT(2))
return;
PHYDM_DBG(dm, ODM_PHY_CONFIG,"phydm 8822b cck rx path selection start\n");
if (drp_8822b->path_judge & BB_PATH_A) {
drp_8822b->path_a_cck_fa = (u16)fa_cnt->cnt_cck_fail;
drp_8822b->path_judge = (enum bb_path)(drp_8822b->path_judge & ~BB_PATH_A);
odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x5); /*change to path B collect CCKFA*/
} else if (drp_8822b->path_judge & BB_PATH_B) {
drp_8822b->path_b_cck_fa = (u16)fa_cnt->cnt_cck_fail;
drp_8822b->path_judge =(enum bb_path)(drp_8822b->path_judge & ~BB_PATH_B);
if (drp_8822b->path_a_cck_fa <= drp_8822b->path_b_cck_fa)
odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x0); /*FA A<=B choose A*/
else
odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x5); /*FA B>A choose B*/
drp_8822b->path_judge = (enum bb_path)(drp_8822b->path_judge | BIT(2)); /*it means we have already choosed cck rx path*/
}
PHYDM_DBG(dm, ODM_PHY_CONFIG,"path_a_fa = %d, path_b_fa = %d\n", drp_8822b->path_a_cck_fa, drp_8822b->path_b_cck_fa);
}
void
phydm_somlrxhp_setting(
struct dm_struct *dm,
boolean switch_soml
)
{
if (switch_soml == true) {
odm_set_bb_reg(dm, 0x19a8, MASKDWORD, 0xd10a0000);
/* Following are RxHP settings for T2R as always low, workaround for OTA test, required to classify */
odm_set_bb_reg(dm, 0xc04, (BIT(21)|BIT(18)), 0x0);
odm_set_bb_reg(dm, 0xe04, (BIT(21)|BIT(18)), 0x0);
} else {
odm_set_bb_reg(dm, 0x19a8, MASKDWORD, 0x010a0000);
odm_set_bb_reg(dm, 0xc04, (BIT(21)|BIT(18)), 0x0);
odm_set_bb_reg(dm, 0xe04, (BIT(21)|BIT(18)), 0x0);
}
/* Dynamic RxHP setting with SoML on/off apply on all RFE type */
if (!switch_soml && ((dm->rfe_type == 1) || (dm->rfe_type == 6) || (dm->rfe_type == 7) || (dm->rfe_type == 9))) {
odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108000);
odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x0);
}
if (*dm->channel <= 14) {
if (switch_soml && (!((dm->rfe_type == 3) || (dm->rfe_type == 5) || (dm->rfe_type == 8) || (dm->rfe_type == 17)))) {
odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108000);
odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x0);
}
} else if (*dm->channel > 35) {
if (switch_soml == true) {
odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108000);
odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x0);
}
}
#if 0
if (!((dm->rfe_type == 1) || (dm->rfe_type == 6) || (dm->rfe_type == 7) || (dm->rfe_type == 9))) {
if (*dm->channel <= 14) {
/* TFBGA iFEM SoML on/off with RxHP always high-to-low */
if ((switch_soml == true) && (!((dm->rfe_type == 3) || (dm->rfe_type == 5)))) {
if (switch_soml == true) {
odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108000);
odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x0);
odm_set_bb_reg(dm, 0xc04, (BIT(21)|(BIT(18))), 0x0);
odm_set_bb_reg(dm, 0xe04, (BIT(21)|(BIT(18))), 0x0);
} else {
odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108492);
odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x1);
}
}
} else if (*dm->channel > 35) {
if (switch_soml == true) {
odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108000);
odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x0);
odm_set_bb_reg(dm, 0xc04, (BIT(21)|(BIT(18))), 0x0);
odm_set_bb_reg(dm, 0xe04, (BIT(21)|(BIT(18))), 0x0);
} else {
odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108492);
odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x1);
}
}
PHYDM_DBG(dm, ODM_COMP_API, "Dynamic RxHP control with SoML is enable !!\n");
}
#endif
}
void
phydm_config_tx2path_8822b(
struct dm_struct *dm,
enum wireless_set wireless_mode,
boolean is_tx2_path
)
{
if (wireless_mode == WIRELESS_CCK) {
if (is_tx2_path == true)
odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0xc);
else
odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x8);
} else {
if (is_tx2_path == true)
odm_set_bb_reg(dm, 0x93c, 0xf00000, 0x3);
else
odm_set_bb_reg(dm, 0x93c, 0xf00000, 0x1);
}
}
#ifdef DYN_ANT_WEIGHTING_SUPPORT
void
phydm_dynamic_ant_weighting_8822b(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 rssi_l2h = 43, rssi_h2l = 37;
u8 reg_8;
if (dm->is_disable_dym_ant_weighting)
return;
if (*dm->channel <= 14) {
if (dm->rssi_min >= rssi_l2h) {
odm_set_bb_reg(dm, 0x98c, 0x7fc0000, 0x0);
/*equal weighting*/
reg_8 = (u8)odm_get_bb_reg(dm, 0xf94, BIT(0)|BIT(1)|BIT(2));
PHYDM_DBG(dm, ODM_COMP_API, "Equal weighting ,rssi_min = %d\n, 0xf94[2:0] = 0x%x\n", dm->rssi_min, reg_8);
} else if (dm->rssi_min <= rssi_h2l) {
odm_set_bb_reg(dm, 0x98c, MASKDWORD, 0x43440000);
/*fix sec_min_wgt = 1/2*/
reg_8 = (u8)odm_get_bb_reg(dm, 0xf94, BIT(0)|BIT(1)|BIT(2));
PHYDM_DBG(dm, ODM_COMP_API, "AGC weighting ,rssi_min = %d\n, 0xf94[2:0] = 0x%x\n", dm->rssi_min, reg_8);
}
} else {
odm_set_bb_reg(dm, 0x98c, MASKDWORD, 0x43440000);
reg_8 = (u8)odm_get_bb_reg(dm, 0xf94, BIT(0)|BIT(1)|BIT(2));
PHYDM_DBG(dm, ODM_COMP_API, "AGC weighting ,rssi_min = %d\n, 0xf94[2:0] = 0x%x\n", dm->rssi_min, reg_8);
/*fix sec_min_wgt = 1/2*/
}
}
#endif
void
phydm_hwsetting_8822b(
struct dm_struct *dm
)
{
struct drp_rtl8822b_struct *drp_8822b = &dm->phydm_rtl8822b;
u8 set_result_nbi = PHYDM_SET_NO_NEED;
if ((dm->p_advance_ota & PHYDM_HP_OTA_SETTING_A) || (dm->p_advance_ota & PHYDM_HP_OTA_SETTING_B)) {
phydm_dynamic_parameters_ota(dm);
} else {
if (dm->bhtstfdisabled == false)
phydm_dynamic_switch_htstf_mumimo_8822b(dm);
else
PHYDM_DBG(dm, ODM_PHY_CONFIG, "Default HT-STF gain control setting\n");
}
phydm_dynamic_ant_weighting(dm);
if (dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) {
if (dm->rssi_min <= 20)
phydm_somlrxhp_setting(dm, false);
else if (dm->rssi_min >= 25)
phydm_somlrxhp_setting(dm, true);
}
if ((dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING_CCK_PATH) || (dm->p_advance_ota & PHYDM_HP_OTA_SETTING_CCK_PATH)) {
if (dm->is_linked)
phydm_dynamic_select_cck_path_8822b(dm);
else
drp_8822b->path_judge =(enum bb_path)(drp_8822b->path_judge | ((~ BIT(2)) | BB_PATH_A | BB_PATH_B));
}
if (dm->p_advance_ota & PHYDM_LENOVO_OTA_SETTING_NBI_CSI) {
if ((*dm->band_width == CHANNEL_WIDTH_80) && (*dm->channel == 157)) {
set_result_nbi = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 80, 5760, PHYDM_DONT_CARE);
PHYDM_DBG(dm, ODM_PHY_CONFIG, "Enable NBI\n");
}
}
}
#endif /* RTL8822B_SUPPORT == 1 */

61
hal/phydm/rtl8822b/phydm_rtl8822b.h Normal file
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@@ -0,0 +1,61 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#if (RTL8822B_SUPPORT == 1)
#ifndef __ODM_RTL8822B_H__
#define __ODM_RTL8822B_H__
#ifdef DYN_ANT_WEIGHTING_SUPPORT
void
phydm_dynamic_ant_weighting_8822b(
void *dm_void
);
#endif
void
phydm_1rcca_setting(
struct dm_struct *dm,
boolean enable_1rcca
);
void
phydm_somlrxhp_setting(
struct dm_struct *dm,
boolean switch_soml
);
void
phydm_hwsetting_8822b(
struct dm_struct *dm
);
void
phydm_config_tx2path_8822b(
struct dm_struct *dm,
enum wireless_set wireless_mode,
boolean is_tx2_path
);
#endif /* #define __ODM_RTL8822B_H__ */
#endif

33
hal/phydm/rtl8822b/version_rtl8822b.h Normal file
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@@ -0,0 +1,33 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*RTL8822B PHY Parameters*/
/*
[Caution]
Since 01/Aug/2015, the commit rules will be simplified. You do not need to fill up the version.h anymore,
only the maintenance supervisor fills it before formal release.
*/
#define RELEASE_DATE_8822B 20171201
#define COMMIT_BY_8822B "BB_JOE"
#define RELEASE_VERSION_8822B 104