RTL88x2B Driver from Realtek. Version: 5.3.1

hal/halmac/halmac_2_platform.h

@@ -0,0 +1,81 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2015 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_2_PLATFORM_H_
+#define _HALMAC_2_PLATFORM_H_
+
+/*[Driver] always set BUILD_TEST =0*/
+#define BUILD_TEST	0
+
+#if BUILD_TEST
+#include "../Platform/App/Test/halmac_2_platformapi.h"
+#else
+/*[Driver] use their own header files*/
+#include <drv_conf.h>			/* for basic_types.h and osdep_service.h */
+#include <basic_types.h>		/* u8, u16, u32 and etc.*/
+#include <osdep_service.h>		/* __BIG_ENDIAN, __LITTLE_ENDIAN, _sema, _mutex */
+#endif
+
+/*[Driver] provide the define of _TRUE, _FALSE, NULL, u8, u16, u32*/
+#ifndef NULL
+#define NULL		((void *)0)
+#endif
+
+#define HALMAC_INLINE	inline
+
+#define HALMAC_PLATFORM_LITTLE_ENDIAN	1
+#define HALMAC_PLATFORM_BIG_ENDIAN	0
+
+/* Note : Named HALMAC_PLATFORM_LITTLE_ENDIAN / HALMAC_PLATFORM_BIG_ENDIAN
+ * is not mandatory. But Little endian must be '1'. Big endian must be '0'
+ */
+/*[Driver] config the system endian*/
+#ifdef __LITTLE_ENDIAN
+#define HALMAC_SYSTEM_ENDIAN	HALMAC_PLATFORM_LITTLE_ENDIAN
+#else /* !__LITTLE_ENDIAN */
+#define HALMAC_SYSTEM_ENDIAN	HALMAC_PLATFORM_BIG_ENDIAN
+#endif /* !__LITTLE_ENDIAN */
+
+/*[Driver] config if the operating platform*/
+#define HALMAC_PLATFORM_WINDOWS		0
+#define HALMAC_PLATFORM_LINUX		1
+#define HALMAC_PLATFORM_AP		0
+/*[Driver] must set HALMAC_PLATFORM_TESTPROGRAM = 0*/
+#define HALMAC_PLATFORM_TESTPROGRAM	0
+
+/*[Driver] config if enable the dbg msg or notl*/
+#define HALMAC_DBG_MSG_ENABLE		1
+
+#define HALMAC_MSG_LEVEL_TRACE		3
+#define HALMAC_MSG_LEVEL_WARNING	2
+#define HALMAC_MSG_LEVEL_ERR		1
+#define HALMAC_MSG_LEVEL_NO_LOG		0
+/*[Driver] config halmac msg level
+ * Use HALMAC_MSG_LEVEL_XXXX
+ */
+#define HALMAC_MSG_LEVEL HALMAC_MSG_LEVEL_TRACE
+
+/*[Driver] define the Rx FIFO expanding mode packet size unit for 8821C and 8822B */
+/*Should be 8 Byte alignment*/
+#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE	80 /*Bytes*/
+
+#define HALMAC_USE_TYPEDEF		0
+
+/*[Driver] provide the type mutex*/
+/* Mutex type */
+typedef _mutex		HALMAC_MUTEX;
+
+#endif /* _HALMAC_2_PLATFORM_H_ */
+

hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h

@@ -0,0 +1,73 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_8822B_CFG_H_
+#define _HALMAC_8822B_CFG_H_
+
+#include "../../halmac_hw_cfg.h"
+#include "../halmac_88xx_cfg.h"
+
+#if HALMAC_8822B_SUPPORT
+
+#define TX_FIFO_SIZE_8822B	262144
+#define RX_FIFO_SIZE_8822B	24576
+#define TRX_SHARE_SIZE_8822B	65536
+
+#define RX_DESC_DUMMY_SIZE_8822B	72 /* 8 * 9 Bytes */
+#define RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B	80 /* 8 Byte alignment*/
+
+/* should be 8 Byte alignment*/
+#if (HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE <= \
+	RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B)
+#define RX_FIFO_EXPANDING_UNIT_8822B	(RX_DESC_SIZE_88XX + \
+	RX_DESC_DUMMY_SIZE_8822B + HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE)
+#else
+#define RX_FIFO_EXPANDING_UNIT_8822B (RX_DESC_SIZE_88XX + \
+	RX_DESC_DUMMY_SIZE_8822B + RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B)
+#endif
+
+#define TX_FIFO_SIZE_LA_8822B	(TX_FIFO_SIZE_8822B >>  1)
+#define TX_FIFO_SIZE_RX_EXPAND_1BLK_8822B	\
+		(TX_FIFO_SIZE_8822B - TRX_SHARE_SIZE_8822B)
+#define RX_FIFO_SIZE_RX_EXPAND_1BLK_8822B	\
+		((((RX_FIFO_EXPANDING_UNIT_8822B << 8) - 1) >> 10) << 10)
+#define TX_FIFO_SIZE_RX_EXPAND_2BLK_8822B	\
+		(TX_FIFO_SIZE_8822B - (2 * TRX_SHARE_SIZE_8822B))
+#define RX_FIFO_SIZE_RX_EXPAND_2BLK_8822B	\
+		(RX_FIFO_SIZE_8822B +  (2 * TRX_SHARE_SIZE_8822B))
+#define TX_FIFO_SIZE_RX_EXPAND_3BLK_8822B	\
+		(TX_FIFO_SIZE_8822B - (3 * TRX_SHARE_SIZE_8822B))
+#define RX_FIFO_SIZE_RX_EXPAND_3BLK_8822B	\
+		(RX_FIFO_SIZE_8822B +  (3 * TRX_SHARE_SIZE_8822B))
+
+#define EFUSE_SIZE_8822B		1024
+#define EEPROM_SIZE_8822B		768
+#define BT_EFUSE_SIZE_8822B		128
+
+#define SEC_CAM_NUM_8822B		64
+
+#define OQT_ENTRY_AC_8822B		32
+#define OQT_ENTRY_NOAC_8822B		32
+#define MACID_MAX_8822B			128
+
+#define WLAN_FW_IRAM_MAX_SIZE_8822B	196608
+#define WLAN_FW_DRAM_MAX_SIZE_8822B	49152
+#define WLAN_FW_ERAM_MAX_SIZE_8822B	0
+#define WLAN_FW_MAX_SIZE_8822B		(WLAN_FW_IRAM_MAX_SIZE_8822B + \
+	WLAN_FW_DRAM_MAX_SIZE_8822B + WLAN_FW_ERAM_MAX_SIZE_8822B)
+
+#endif /* HALMAC_8822B_SUPPORT*/
+
+#endif

hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.c

@@ -0,0 +1,168 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_cfg_wmac_8822b.h"
+#include "halmac_8822b_cfg.h"
+
+#if HALMAC_8822B_SUPPORT
+
+/**
+ * cfg_drv_info_8822b() - config driver info
+ * @adapter : the adapter of halmac
+ * @drv_info : driver information selection
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_drv_info_8822b(struct halmac_adapter *adapter,
+		   enum halmac_drv_info drv_info)
+{
+	u8 drv_info_size = 0;
+	u8 phy_status_en = 0;
+	u8 sniffer_en = 0;
+	u8 plcp_hdr_en = 0;
+	u8 value8;
+	u32 value32;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	struct halmac_mac_rx_ignore_cfg cfg;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+	PLTFM_MSG_TRACE("[TRACE]drv info = %d\n", drv_info);
+
+	switch (drv_info) {
+	case HALMAC_DRV_INFO_NONE:
+		drv_info_size = 0;
+		phy_status_en = 0;
+		sniffer_en = 0;
+		plcp_hdr_en = 0;
+		cfg.hdr_chk_en = _FALSE;
+		break;
+	case HALMAC_DRV_INFO_PHY_STATUS:
+		drv_info_size = 4;
+		phy_status_en = 1;
+		sniffer_en = 0;
+		plcp_hdr_en = 0;
+		cfg.hdr_chk_en = _FALSE;
+		break;
+	case HALMAC_DRV_INFO_PHY_SNIFFER:
+		drv_info_size = 5; /* phy status 4byte, sniffer info 1byte */
+		phy_status_en = 1;
+		sniffer_en = 1;
+		plcp_hdr_en = 0;
+		cfg.hdr_chk_en = _FALSE;
+		break;
+	case HALMAC_DRV_INFO_PHY_PLCP:
+		drv_info_size = 6; /* phy status 4byte, plcp header 2byte */
+		phy_status_en = 1;
+		sniffer_en = 0;
+		plcp_hdr_en = 1;
+		cfg.hdr_chk_en = _FALSE;
+		break;
+	default:
+		return HALMAC_RET_SW_CASE_NOT_SUPPORT;
+	}
+
+	if (adapter->txff_alloc.rx_fifo_exp_mode !=
+	    HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE)
+		drv_info_size = RX_DESC_DUMMY_SIZE_8822B >> 3;
+
+	api->halmac_set_hw_value(adapter, HALMAC_HW_RX_IGNORE, &cfg);
+
+	HALMAC_REG_W8(REG_RX_DRVINFO_SZ, drv_info_size);
+
+	value8 = HALMAC_REG_R8(REG_TRXFF_BNDY + 1);
+	value8 &= 0xF0;
+	/* For rxdesc len = 0 issue */
+	value8 |= 0xF;
+	HALMAC_REG_W8(REG_TRXFF_BNDY + 1, value8);
+
+	adapter->drv_info_size = drv_info_size;
+
+	value32 = HALMAC_REG_R32(REG_RCR);
+	value32 = (value32 & (~BIT_APP_PHYSTS));
+	if (phy_status_en == 1)
+		value32 = value32 | BIT_APP_PHYSTS;
+	HALMAC_REG_W32(REG_RCR, value32);
+
+	value32 = HALMAC_REG_R32(REG_WMAC_OPTION_FUNCTION + 4);
+	value32 = (value32 & (~(BIT(8) | BIT(9))));
+	if (sniffer_en == 1)
+		value32 = value32 | BIT(9);
+	if (plcp_hdr_en == 1)
+		value32 = value32 | BIT(8);
+	HALMAC_REG_W32(REG_WMAC_OPTION_FUNCTION + 4, value32);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_low_pwr_8822b() - config WMAC register
+ * @adapter
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_low_pwr_8822b(struct halmac_adapter *adapter)
+{
+	return HALMAC_RET_SUCCESS;
+}
+
+void
+cfg_rx_ignore_8822b(struct halmac_adapter *adapter,
+		    struct halmac_mac_rx_ignore_cfg *cfg)
+{
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	value8 = HALMAC_REG_R8(REG_BBPSF_CTRL);
+
+	/*mac header check enable*/
+	if (cfg->hdr_chk_en == _TRUE)
+		value8 |= BIT_BBPSF_MHCHKEN | BIT_BBPSF_MPDUCHKEN;
+	else
+		value8 &= ~(BIT_BBPSF_MHCHKEN) & (~(BIT_BBPSF_MPDUCHKEN));
+
+	HALMAC_REG_W8(REG_BBPSF_CTRL, value8);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+}
+
+enum halmac_ret_status
+cfg_ampdu_8822b(struct halmac_adapter *adapter,
+		struct halmac_ampdu_config *cfg)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (cfg->ht_max_len != cfg->vht_max_len) {
+		PLTFM_MSG_ERR("[ERR]max len ht != vht!!\n");
+		return HALMAC_RET_PARA_NOT_SUPPORT;
+	}
+
+	HALMAC_REG_W8(REG_PROT_MODE_CTRL + 2, cfg->max_agg_num);
+	HALMAC_REG_W8(REG_PROT_MODE_CTRL + 3, cfg->max_agg_num);
+
+	if (cfg->max_len_en == 1)
+		HALMAC_REG_W32(REG_AMPDU_MAX_LENGTH, cfg->ht_max_len);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_8822B_SUPPORT */

hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.h

@@ -0,0 +1,40 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_CFG_WMAC_8822B_H_
+#define _HALMAC_CFG_WMAC_8822B_H_
+
+#include "../../halmac_api.h"
+
+#if HALMAC_8822B_SUPPORT
+
+enum halmac_ret_status
+cfg_drv_info_8822b(struct halmac_adapter *adapter,
+		   enum halmac_drv_info drv_info);
+
+enum halmac_ret_status
+init_low_pwr_8822b(struct halmac_adapter *adapter);
+
+void
+cfg_rx_ignore_8822b(struct halmac_adapter *adapter,
+		    struct halmac_mac_rx_ignore_cfg *cfg);
+
+enum halmac_ret_status
+cfg_ampdu_8822b(struct halmac_adapter *adapter,
+		struct halmac_ampdu_config *cfg);
+
+#endif/* HALMAC_8822B_SUPPORT */
+
+#endif/* _HALMAC_CFG_WMAC_8822B_H_ */

hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.c

@@ -0,0 +1,168 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_8822b_cfg.h"
+#include "halmac_common_8822b.h"
+#include "../halmac_common_88xx.h"
+#include "halmac_cfg_wmac_8822b.h"
+
+#if HALMAC_8822B_SUPPORT
+
+static void
+cfg_ldo25_8822b(struct halmac_adapter *adapter, u8 enable);
+
+/**
+ * get_hw_value_8822b() -get hw config value
+ * @adapter : the adapter of halmac
+ * @hw_id : hw id for driver to query
+ * @pvalue : hw value, reference table to get data type
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_hw_value_8822b(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
+		   void *value)
+{
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (!value) {
+		PLTFM_MSG_ERR("[ERR]%s (NULL ==pvalue)\n", __func__);
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	if (get_hw_value_88xx(adapter, hw_id, value) == HALMAC_RET_SUCCESS)
+		return HALMAC_RET_SUCCESS;
+
+	switch (hw_id) {
+	case HALMAC_HW_FW_MAX_SIZE:
+		*(u32 *)value = WLAN_FW_MAX_SIZE_8822B;
+		break;
+	default:
+		return HALMAC_RET_PARA_NOT_SUPPORT;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * set_hw_value_8822b() -set hw config value
+ * @adapter : the adapter of halmac
+ * @hw_id : hw id for driver to config
+ * @pvalue : hw value, reference table to get data type
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+set_hw_value_8822b(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
+		   void *value)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (!value) {
+		PLTFM_MSG_ERR("[ERR]null pointer\n");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	if (set_hw_value_88xx(adapter, hw_id, value) == HALMAC_RET_SUCCESS)
+		return HALMAC_RET_SUCCESS;
+
+	switch (hw_id) {
+	case HALMAC_HW_AMPDU_CONFIG:
+		status = cfg_ampdu_8822b(adapter,
+					 (struct halmac_ampdu_config *)value);
+		break;
+	case HALMAC_HW_SDIO_TX_FORMAT:
+		break;
+	case HALMAC_HW_RXGCK_FIFO:
+		break;
+	case HALMAC_HW_RX_IGNORE:
+		cfg_rx_ignore_8822b(adapter,
+				    (struct halmac_mac_rx_ignore_cfg *)value);
+		break;
+	case HALMAC_HW_LDO25_EN:
+		cfg_ldo25_8822b(adapter, *(u8 *)value);
+		break;
+	case HALMAC_HW_PCIE_REF_AUTOK:
+		break;
+	default:
+		return HALMAC_RET_PARA_NOT_SUPPORT;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return status;
+}
+
+/**
+ * halmac_fill_txdesc_check_sum_88xx() -  fill in tx desc check sum
+ * @adapter : the adapter of halmac
+ * @txdesc : tx desc packet
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+fill_txdesc_check_sum_8822b(struct halmac_adapter *adapter, u8 *txdesc)
+{
+	u16 chksum = 0;
+	u16 *data = (u16 *)NULL;
+	u32 i;
+
+	if (!txdesc) {
+		PLTFM_MSG_ERR("[ERR]null pointer");
+		return HALMAC_RET_NULL_POINTER;
+	}
+
+	if (adapter->tx_desc_checksum != _TRUE)
+		PLTFM_MSG_TRACE("[TRACE]chksum disable");
+
+	SET_TX_DESC_TXDESC_CHECKSUM(txdesc, 0x0000);
+
+	data = (u16 *)(txdesc);
+
+	/* HW clculates only 32byte */
+	for (i = 0; i < 8; i++)
+		chksum ^= (*(data + 2 * i) ^ *(data + (2 * i + 1)));
+
+	/* *(data + 2 * i) & *(data + (2 * i + 1) have endain issue*/
+	/* Process eniadn issue after checksum calculation */
+	chksum = rtk_le16_to_cpu(chksum);
+
+	SET_TX_DESC_TXDESC_CHECKSUM(txdesc, chksum);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static void
+cfg_ldo25_8822b(struct halmac_adapter *adapter, u8 enable)
+{
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	value8 = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 3);
+
+	if (enable == _TRUE)
+		HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 3, (u8)(value8 | BIT(7)));
+	else
+		HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 3, (u8)(value8 & ~BIT(7)));
+}
+
+#endif /* HALMAC_8822B_SUPPORT */

hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.h

@@ -0,0 +1,36 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_COMMON_8822B_H_
+#define _HALMAC_COMMON_8822B_H_
+
+#include "../../halmac_api.h"
+
+#if HALMAC_8822B_SUPPORT
+
+enum halmac_ret_status
+get_hw_value_8822b(struct halmac_adapter *adapter,
+		   enum halmac_hw_id hw_id, void *value);
+
+enum halmac_ret_status
+set_hw_value_8822b(struct halmac_adapter *adapter,
+		   enum halmac_hw_id hw_id, void *value);
+
+enum halmac_ret_status
+fill_txdesc_check_sum_8822b(struct halmac_adapter *adapter, u8 *txdesc);
+
+#endif/* HALMAC_8822B_SUPPORT */
+
+#endif/* _HALMAC_COMMON_8822B_H_ */

hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.c

@@ -0,0 +1,831 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_gpio_8822b.h"
+#include "../halmac_gpio_88xx.h"
+
+#if HALMAC_8822B_SUPPORT
+
+/* GPIO0 definition */
+#define GPIO0_BT_GPIO0_8822B	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(2), BIT(2)}
+#define GPIO0_BT_ACT_8822B	\
+	{HALMAC_BT_PTA, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+	 0x41, BIT(1), 0}
+#define GPIO0_WL_ACT_8822B	\
+	{HALMAC_WL_PTA, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+	 0x41, BIT(2), BIT(2)}
+#define GPIO0_WLMAC_DBG_GPIO0_8822B	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO0, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO0_WLPHY_DBG_GPIO0_8822B	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO0_BT_DBG_GPIO0_8822B	\
+	{HALMAC_BT_DBG, HALMAC_GPIO0, HALMAC_GPIO_OUT, \
+	0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO0_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO1 definition */
+#define GPIO1_BT_GPIO1_8822B	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(2), BIT(2)}
+#define GPIO1_BT_3DD_SYNC_A_8822B	\
+	{HALMAC_BT_3DDLS_A, HALMAC_GPIO1, HALMAC_GPIO_IN, \
+	 0x66, BIT(2), BIT(2)}
+#define GPIO1_WL_CK_8822B	\
+	{HALMAC_BT_PTA, HALMAC_GPIO1, HALMAC_GPIO_OUT, \
+	 0x41, BIT(1), 0}
+#define GPIO1_BT_CK_8822B	\
+	{HALMAC_WL_PTA, HALMAC_GPIO1, HALMAC_GPIO_OUT, \
+	 0x41, BIT(2), BIT(2)}
+#define GPIO1_WLMAC_DBG_GPIO1_8822B	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO1, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO1_WLPHY_DBG_GPIO1_8822B	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO1_BT_DBG_GPIO1_8822B	\
+	{HALMAC_BT_DBG, HALMAC_GPIO1, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO1_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO2 definition */
+#define GPIO2_BT_GPIO2_8822B	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(2), BIT(2)}
+#define GPIO2_WL_STATE_8822B	\
+	{HALMAC_BT_PTA, HALMAC_GPIO2, HALMAC_GPIO_OUT, \
+	 0x41, BIT(1), 0}
+#define GPIO2_BT_STATE_8822B	\
+	{HALMAC_WL_PTA, HALMAC_GPIO2, HALMAC_GPIO_OUT, \
+	 0x41, BIT(2), BIT(2)}
+#define GPIO2_WLMAC_DBG_GPIO2_8822B	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO2, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO2_WLPHY_DBG_GPIO2_8822B	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO2_BT_DBG_GPIO2_8822B	\
+	{HALMAC_BT_DBG, HALMAC_GPIO2, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO2_RFE_CTRL_5_8822B	\
+	{HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(2), BIT(2)}
+#define GPIO2_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO3 definition */
+#define GPIO3_BT_GPIO3_8822B	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(2), BIT(2)}
+#define GPIO3_WL_PRI_8822B	\
+	{HALMAC_BT_PTA, HALMAC_GPIO3, HALMAC_GPIO_OUT, \
+	 0x41, BIT(1), 0}
+#define GPIO3_BT_PRI_8822B	\
+	{HALMAC_WL_PTA, HALMAC_GPIO3, HALMAC_GPIO_OUT, \
+	 0x41, BIT(2), BIT(2)}
+#define GPIO3_WLMAC_DBG_GPIO3_8822B	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO3, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO3_WLPHY_DBG_GPIO3_8822B	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO3_BT_DBG_GPIO3_8822B	\
+	{HALMAC_BT_DBG, HALMAC_GPIO3, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO3_RFE_CTRL_4_8822B	\
+	{HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(2), BIT(2)}
+#define GPIO3_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO4 definition */
+#define GPIO4_BT_SPI_D0_8822B	\
+	{HALMAC_BT_SFLASH, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(4), BIT(4)}
+#define GPIO4_WL_SPI_D0_8822B	\
+	{HALMAC_WL_SFLASH, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \
+	 0x42, BIT(3), BIT(3)}
+#define GPIO4_SDIO_INT_8822B	\
+	{HALMAC_SDIO_INT, HALMAC_GPIO4, HALMAC_GPIO_OUT, \
+	 0x72, BIT(2), BIT(2)}
+#define GPIO4_JTAG_TRST_8822B	\
+	{HALMAC_JTAG, HALMAC_GPIO4, HALMAC_GPIO_IN, \
+	 0x67, BIT(0), BIT(0)}
+#define GPIO4_DBG_GNT_WL_8822B	\
+	{HALMAC_DBG_GNT_WL_BT, HALMAC_GPIO4, HALMAC_GPIO_OUT, \
+	 0x73, BIT(3), BIT(3)}
+#define GPIO4_WLMAC_DBG_GPIO4_8822B	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO4, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO4_WLPHY_DBG_GPIO4_8822B	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO4_BT_DBG_GPIO4_8822B	\
+	{HALMAC_BT_DBG, HALMAC_GPIO4, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO4_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO5 definition */
+#define GPIO5_BT_SPI_D1_8822B	\
+	{HALMAC_BT_SFLASH, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(4), BIT(4)}
+#define GPIO5_WL_SPI_D1_8822B	\
+	{HALMAC_WL_SFLASH, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \
+	 0x42, BIT(3), BIT(3)}
+#define GPIO5_JTAG_TDI_8822B	\
+	{HALMAC_JTAG, HALMAC_GPIO5, HALMAC_GPIO_IN, \
+	 0x67, BIT(0), BIT(0)}
+#define GPIO5_DBG_GNT_BT_8822B	\
+	{HALMAC_DBG_GNT_WL_BT, HALMAC_GPIO5, HALMAC_GPIO_OUT, \
+	 0x73, BIT(3), BIT(3)}
+#define GPIO5_WLMAC_DBG_GPIO5_8822B	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO5, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO5_WLPHY_DBG_GPIO5_8822B	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO5_BT_DBG_GPIO5_8822B	\
+	{HALMAC_BT_DBG, HALMAC_GPIO5, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO5_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO6 definition */
+#define GPIO6_BT_SPI_D2_8822B	\
+	{HALMAC_BT_SFLASH, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(4), BIT(4)}
+#define GPIO6_WL_SPI_D2_8822B	\
+	{HALMAC_WL_SFLASH, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+	 0x42, BIT(3), BIT(3)}
+#define GPIO6_EEDO_8822B	\
+	{HALMAC_EEPROM, HALMAC_GPIO6, HALMAC_GPIO_IN, \
+	 0x40, BIT(4), BIT(4)}
+#define GPIO6_JTAG_TDO_8822B	\
+	{HALMAC_JTAG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \
+	 0x67, BIT(0), BIT(0)}
+#define GPIO6_BT_3DD_SYNC_B_8822B	\
+	{HALMAC_BT_3DDLS_B, HALMAC_GPIO6, HALMAC_GPIO_IN, \
+	 0x67, BIT(1), BIT(1)}
+#define GPIO6_BT_GPIO18_8822B	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+	 0x67, BIT(1), BIT(1)}
+#define GPIO6_SIN_8822B	\
+	{HALMAC_WL_UART, HALMAC_GPIO6, HALMAC_GPIO_IN, \
+	 0x41, BIT(0), BIT(0)}
+#define GPIO6_WLMAC_DBG_GPIO6_8822B	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO6_WLPHY_DBG_GPIO6_8822B	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO6_BT_DBG_GPIO6_8822B	\
+	{HALMAC_BT_DBG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO6_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO7 definition */
+#define GPIO7_BT_SPI_D3_8822B	\
+	{HALMAC_BT_SFLASH, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+	 0x66, BIT(4), BIT(4)}
+#define GPIO7_WL_SPI_D3_8822B	\
+	{HALMAC_WL_SFLASH, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+	 0x42, BIT(3), BIT(3)}
+#define GPIO7_EEDI_8822B	\
+	{HALMAC_EEPROM, HALMAC_GPIO7, HALMAC_GPIO_OUT, \
+	 0x40, BIT(4), BIT(4)}
+#define GPIO7_JTAG_TMS_8822B	\
+	{HALMAC_JTAG, HALMAC_GPIO7, HALMAC_GPIO_IN, \
+	 0x67, BIT(0), BIT(0)}
+#define GPIO7_BT_GPIO16_8822B	\
+	{HALMAC_BT_GPIO, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+	 0x67, BIT(2), BIT(2)}
+#define GPIO7_SOUT_8822B	\
+	{HALMAC_WL_UART, HALMAC_GPIO7, HALMAC_GPIO_OUT, \
+	 0x41, BIT(0), BIT(0)}
+#define GPIO7_WLMAC_DBG_GPIO7_8822B	\
+	{HALMAC_WLMAC_DBG, HALMAC_GPIO7, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO7_WLPHY_DBG_GPIO7_8822B	\
+	{HALMAC_WLPHY_DBG, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO7_BT_DBG_GPIO7_8822B	\
+	{HALMAC_BT_DBG, HALMAC_GPIO7, HALMAC_GPIO_OUT, \
+	 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO7_SW_IO_8822B \
+	{HALMAC_SW_IO, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO8 definition */
+#define GPIO8_WL_EXT_WOL_8822B	\
+	{HALMAC_WL_HW_EXTWOL, HALMAC_GPIO8, HALMAC_GPIO_IN, \
+	 0x4a, BIT(0) | BIT(1), BIT(0) | BIT(1)}
+#define GPIO8_WL_LED_8822B	\
+	{HALMAC_WL_LED, HALMAC_GPIO8, HALMAC_GPIO_OUT, \
+	 0x4e, BIT(5), BIT(5)}
+#define GPIO8_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO8, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO9 definition */
+#define GPIO9_DIS_WL_N_8822B	\
+	{HALMAC_WL_HWPDN, HALMAC_GPIO9, HALMAC_GPIO_IN, \
+	 0x68, BIT(3) | BIT(0), BIT(3) | BIT(0)}
+#define GPIO9_WL_EXT_WOL_8822B	\
+	{HALMAC_WL_HW_EXTWOL, HALMAC_GPIO9, HALMAC_GPIO_IN, \
+	 0x4a, BIT(0) | BIT(1), BIT(0)}
+#define GPIO9_USCTS0_8822B	\
+	{HALMAC_UART0, HALMAC_GPIO9, HALMAC_GPIO_IN, \
+	 0x66, BIT(6), BIT(6)}
+#define GPIO9_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO9, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO10 definition */
+#define GPIO10_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO10, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO11 definition */
+#define GPIO11_DIS_BT_N_8822B	\
+	{HALMAC_BT_HWPDN, HALMAC_GPIO11, HALMAC_GPIO_IN, \
+	 0x6a, BIT(0), BIT(0)}
+#define GPIO11_USOUT0_8822B	\
+	{HALMAC_UART0, HALMAC_GPIO11, HALMAC_GPIO_OUT, \
+	 0x66, BIT(6), BIT(6)}
+#define GPIO11_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO11, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO12 definition */
+#define GPIO12_USIN0_8822B	\
+	{HALMAC_UART0, HALMAC_GPIO12, HALMAC_GPIO_IN, \
+	 0x66, BIT(6), BIT(6)}
+#define GPIO12_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO12, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO13 definition */
+#define GPIO13_BT_WAKE_8822B	\
+	{HALMAC_GPIO13_14_WL_CTRL_EN, HALMAC_GPIO13, HALMAC_GPIO_IN, \
+	 0x4e, BIT(6), BIT(6)}
+#define GPIO13_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO13, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO14 definition */
+#define GPIO14_UART_WAKE_8822B	\
+	{HALMAC_GPIO13_14_WL_CTRL_EN, HALMAC_GPIO14, HALMAC_GPIO_OUT, \
+	 0x4e, BIT(6), BIT(6)}
+#define GPIO14_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO14, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO15 definition */
+#define GPIO15_EXT_XTAL_8822B	\
+	{HALMAC_EXT_XTAL, HALMAC_GPIO15, HALMAC_GPIO_OUT, \
+	 0x66, BIT(7), BIT(7)}
+#define GPIO15_SW_IO_8822B	\
+	{HALMAC_SW_IO, HALMAC_GPIO15, HALMAC_GPIO_IN_OUT, \
+	 0x40, BIT(1) | BIT(0), 0}
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO0_8822B[] = {
+	GPIO0_BT_GPIO0_8822B,
+	GPIO0_BT_ACT_8822B,
+	GPIO0_WL_ACT_8822B,
+	GPIO0_WLMAC_DBG_GPIO0_8822B,
+	GPIO0_WLPHY_DBG_GPIO0_8822B,
+	GPIO0_BT_DBG_GPIO0_8822B,
+	GPIO0_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO1_8822B[] = {
+	GPIO1_BT_GPIO1_8822B,
+	GPIO1_BT_3DD_SYNC_A_8822B,
+	GPIO1_WL_CK_8822B,
+	GPIO1_BT_CK_8822B,
+	GPIO1_WLMAC_DBG_GPIO1_8822B,
+	GPIO1_WLPHY_DBG_GPIO1_8822B,
+	GPIO1_BT_DBG_GPIO1_8822B,
+	GPIO1_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO2_8822B[] = {
+	GPIO2_BT_GPIO2_8822B,
+	GPIO2_WL_STATE_8822B,
+	GPIO2_BT_STATE_8822B,
+	GPIO2_WLMAC_DBG_GPIO2_8822B,
+	GPIO2_WLPHY_DBG_GPIO2_8822B,
+	GPIO2_BT_DBG_GPIO2_8822B,
+	GPIO2_RFE_CTRL_5_8822B,
+	GPIO2_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO3_8822B[] = {
+	GPIO3_BT_GPIO3_8822B,
+	GPIO3_WL_PRI_8822B,
+	GPIO3_BT_PRI_8822B,
+	GPIO3_WLMAC_DBG_GPIO3_8822B,
+	GPIO3_WLPHY_DBG_GPIO3_8822B,
+	GPIO3_BT_DBG_GPIO3_8822B,
+	GPIO3_RFE_CTRL_4_8822B,
+	GPIO3_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO4_8822B[] = {
+	GPIO4_BT_SPI_D0_8822B,
+	GPIO4_WL_SPI_D0_8822B,
+	GPIO4_SDIO_INT_8822B,
+	GPIO4_JTAG_TRST_8822B,
+	GPIO4_DBG_GNT_WL_8822B,
+	GPIO4_WLMAC_DBG_GPIO4_8822B,
+	GPIO4_WLPHY_DBG_GPIO4_8822B,
+	GPIO4_BT_DBG_GPIO4_8822B,
+	GPIO4_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO5_8822B[] = {
+	GPIO5_BT_SPI_D1_8822B,
+	GPIO5_WL_SPI_D1_8822B,
+	GPIO5_JTAG_TDI_8822B,
+	GPIO5_DBG_GNT_BT_8822B,
+	GPIO5_WLMAC_DBG_GPIO5_8822B,
+	GPIO5_WLPHY_DBG_GPIO5_8822B,
+	GPIO5_BT_DBG_GPIO5_8822B,
+	GPIO5_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO6_8822B[] = {
+	GPIO6_BT_SPI_D2_8822B,
+	GPIO6_WL_SPI_D2_8822B,
+	GPIO6_EEDO_8822B,
+	GPIO6_JTAG_TDO_8822B,
+	GPIO6_BT_3DD_SYNC_B_8822B,
+	GPIO6_BT_GPIO18_8822B,
+	GPIO6_SIN_8822B,
+	GPIO6_WLMAC_DBG_GPIO6_8822B,
+	GPIO6_WLPHY_DBG_GPIO6_8822B,
+	GPIO6_BT_DBG_GPIO6_8822B,
+	GPIO6_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO7_8822B[] = {
+	GPIO7_BT_SPI_D3_8822B,
+	GPIO7_WL_SPI_D3_8822B,
+	GPIO7_EEDI_8822B,
+	GPIO7_JTAG_TMS_8822B,
+	GPIO7_BT_GPIO16_8822B,
+	GPIO7_SOUT_8822B,
+	GPIO7_WLMAC_DBG_GPIO7_8822B,
+	GPIO7_WLPHY_DBG_GPIO7_8822B,
+	GPIO7_BT_DBG_GPIO7_8822B,
+	GPIO7_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO8_8822B[] = {
+	GPIO8_WL_EXT_WOL_8822B,
+	GPIO8_WL_LED_8822B,
+	GPIO8_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO9_8822B[] = {
+	GPIO9_DIS_WL_N_8822B,
+	GPIO9_WL_EXT_WOL_8822B,
+	GPIO9_USCTS0_8822B,
+	GPIO9_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO10_8822B[] = {
+	GPIO10_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO11_8822B[] = {
+	GPIO11_DIS_BT_N_8822B,
+	GPIO11_USOUT0_8822B,
+	GPIO11_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO12_8822B[] = {
+	GPIO12_USIN0_8822B,
+	GPIO12_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO13_8822B[] = {
+	GPIO13_BT_WAKE_8822B,
+	GPIO13_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO14_8822B[] = {
+	GPIO14_UART_WAKE_8822B,
+	GPIO14_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO15_8822B[] = {
+	GPIO15_EXT_XTAL_8822B,
+	GPIO15_SW_IO_8822B
+};
+
+static enum halmac_ret_status
+get_pinmux_list_8822b(struct halmac_adapter *adapter,
+		      enum halmac_gpio_func gpio_func,
+		      const struct halmac_gpio_pimux_list **list,
+		      u32 *list_size, u32 *gpio_id);
+
+static enum halmac_ret_status
+chk_pinmux_valid_8822b(struct halmac_adapter *adapter,
+		       enum halmac_gpio_func gpio_func);
+
+/**
+ * pinmux_get_func_8822b() -get current gpio status
+ * @adapter : the adapter of halmac
+ * @gpio_func : gpio function
+ * @enable : function is enable(1) or disable(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_get_func_8822b(struct halmac_adapter *adapter,
+		      enum halmac_gpio_func gpio_func, u8 *enable)
+{
+	u32 list_size;
+	u32 cur_func;
+	u32 gpio_id;
+	enum halmac_ret_status status;
+	const struct halmac_gpio_pimux_list *list = NULL;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	status = get_pinmux_list_8822b(adapter, gpio_func, &list, &list_size,
+				       &gpio_id);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	status = pinmux_parser_88xx(adapter, list, list_size, gpio_id,
+				    &cur_func);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	switch (gpio_func) {
+	case HALMAC_GPIO_FUNC_WL_LED:
+		*enable = (cur_func == HALMAC_WL_LED) ? 1 : 0;
+		break;
+	case HALMAC_GPIO_FUNC_SDIO_INT:
+		*enable = (cur_func == HALMAC_SDIO_INT) ? 1 : 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_0:
+	case HALMAC_GPIO_FUNC_SW_IO_1:
+	case HALMAC_GPIO_FUNC_SW_IO_2:
+	case HALMAC_GPIO_FUNC_SW_IO_3:
+	case HALMAC_GPIO_FUNC_SW_IO_4:
+	case HALMAC_GPIO_FUNC_SW_IO_5:
+	case HALMAC_GPIO_FUNC_SW_IO_6:
+	case HALMAC_GPIO_FUNC_SW_IO_7:
+	case HALMAC_GPIO_FUNC_SW_IO_8:
+	case HALMAC_GPIO_FUNC_SW_IO_9:
+	case HALMAC_GPIO_FUNC_SW_IO_10:
+	case HALMAC_GPIO_FUNC_SW_IO_11:
+	case HALMAC_GPIO_FUNC_SW_IO_12:
+	case HALMAC_GPIO_FUNC_SW_IO_13:
+	case HALMAC_GPIO_FUNC_SW_IO_14:
+	case HALMAC_GPIO_FUNC_SW_IO_15:
+		*enable = (cur_func == HALMAC_SW_IO) ? 1 : 0;
+		break;
+	default:
+		*enable = 0;
+		return HALMAC_RET_GET_PINMUX_ERR;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pinmux_set_func_8822b() -set gpio function
+ * @adapter : the adapter of halmac
+ * @gpio_func : gpio function
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_set_func_8822b(struct halmac_adapter *adapter,
+		      enum halmac_gpio_func gpio_func)
+{
+	u32 list_size;
+	u32 gpio_id;
+	enum halmac_ret_status status;
+	const struct halmac_gpio_pimux_list *list = NULL;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+	PLTFM_MSG_TRACE("[TRACE]func name : %d\n", gpio_func);
+
+	status = chk_pinmux_valid_8822b(adapter, gpio_func);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	status = get_pinmux_list_8822b(adapter, gpio_func, &list, &list_size,
+				       &gpio_id);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	status = pinmux_switch_88xx(adapter, list, list_size, gpio_id,
+				    gpio_func);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	status = pinmux_record_88xx(adapter, gpio_func, 1);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pinmux_free_func_8822b() -free locked gpio function
+ * @adapter : the adapter of halmac
+ * @gpio_func : gpio function
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_free_func_8822b(struct halmac_adapter *adapter,
+		       enum halmac_gpio_func gpio_func)
+{
+	struct halmac_pinmux_info *info = &adapter->pinmux_info;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	switch (gpio_func) {
+	case HALMAC_GPIO_FUNC_SW_IO_0:
+		info->sw_io_0 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_1:
+		info->sw_io_1 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_2:
+		info->sw_io_2 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_3:
+		info->sw_io_3 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_4:
+	case HALMAC_GPIO_FUNC_SDIO_INT:
+		info->sw_io_4 = 0;
+		info->sdio_int = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_5:
+		info->sw_io_5 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_6:
+		info->sw_io_6 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_7:
+		info->sw_io_7 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_8:
+	case HALMAC_GPIO_FUNC_WL_LED:
+		info->sw_io_8 = 0;
+		info->wl_led = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_9:
+		info->sw_io_9 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_10:
+		info->sw_io_10 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_11:
+		info->sw_io_11 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_12:
+		info->sw_io_12 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_13:
+		info->sw_io_13 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_14:
+		info->sw_io_14 = 0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_15:
+		info->sw_io_15 = 0;
+		break;
+	default:
+		return HALMAC_RET_SWITCH_CASE_ERROR;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]func : %X\n", gpio_func);
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+get_pinmux_list_8822b(struct halmac_adapter *adapter,
+		      enum halmac_gpio_func gpio_func,
+		      const struct halmac_gpio_pimux_list **list,
+		      u32 *list_size, u32 *gpio_id)
+{
+	switch (gpio_func) {
+	case HALMAC_GPIO_FUNC_SW_IO_0:
+		*list = PIMUX_LIST_GPIO0_8822B;
+		*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO0_8822B);
+		*gpio_id = HALMAC_GPIO0;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_1:
+		*list = PIMUX_LIST_GPIO1_8822B;
+		*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO1_8822B);
+		*gpio_id = HALMAC_GPIO1;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_2:
+		*list = PIMUX_LIST_GPIO2_8822B;
+		*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO2_8822B);
+		*gpio_id = HALMAC_GPIO2;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_3:
+		*list = PIMUX_LIST_GPIO3_8822B;
+		*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO3_8822B);
+		*gpio_id = HALMAC_GPIO3;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_4:
+	case HALMAC_GPIO_FUNC_SDIO_INT:
+		*list = PIMUX_LIST_GPIO4_8822B;
+		*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO4_8822B);
+		*gpio_id = HALMAC_GPIO4;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_5:
+		*list = PIMUX_LIST_GPIO5_8822B;
+		*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO5_8822B);
+		*gpio_id = HALMAC_GPIO5;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_6:
+		*list = PIMUX_LIST_GPIO6_8822B;
+		*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO6_8822B);
+		*gpio_id = HALMAC_GPIO6;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_7:
+		*list = PIMUX_LIST_GPIO7_8822B;
+		*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO7_8822B);
+		*gpio_id = HALMAC_GPIO7;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_8:
+	case HALMAC_GPIO_FUNC_WL_LED:
+		*list = PIMUX_LIST_GPIO8_8822B;
+		*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO8_8822B);
+		*gpio_id = HALMAC_GPIO8;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_9:
+		*list = PIMUX_LIST_GPIO9_8822B;
+		*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO9_8822B);
+		*gpio_id = HALMAC_GPIO9;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_10:
+		*list = PIMUX_LIST_GPIO10_8822B;
+		*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO10_8822B);
+		*gpio_id = HALMAC_GPIO10;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_11:
+		*list = PIMUX_LIST_GPIO11_8822B;
+		*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO11_8822B);
+		*gpio_id = HALMAC_GPIO11;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_12:
+		*list = PIMUX_LIST_GPIO12_8822B;
+		*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO12_8822B);
+		*gpio_id = HALMAC_GPIO12;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_13:
+		*list = PIMUX_LIST_GPIO13_8822B;
+		*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO13_8822B);
+		*gpio_id = HALMAC_GPIO13;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_14:
+		*list = PIMUX_LIST_GPIO14_8822B;
+		*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO14_8822B);
+		*gpio_id = HALMAC_GPIO14;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_15:
+		*list = PIMUX_LIST_GPIO15_8822B;
+		*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO15_8822B);
+		*gpio_id = HALMAC_GPIO15;
+		break;
+	default:
+		return HALMAC_RET_SWITCH_CASE_ERROR;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+chk_pinmux_valid_8822b(struct halmac_adapter *adapter,
+		       enum halmac_gpio_func gpio_func)
+{
+	struct halmac_pinmux_info *info = &adapter->pinmux_info;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	switch (gpio_func) {
+	case HALMAC_GPIO_FUNC_SW_IO_0:
+		if (info->sw_io_0 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_1:
+		if (info->sw_io_1 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_2:
+		if (info->sw_io_2 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_3:
+		if (info->sw_io_3 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_4:
+	case HALMAC_GPIO_FUNC_SDIO_INT:
+		if (info->sw_io_4 == 1 || info->sdio_int == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_5:
+		if (info->sw_io_5 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_6:
+		if (info->sw_io_6 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_7:
+		if (info->sw_io_7 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_8:
+	case HALMAC_GPIO_FUNC_WL_LED:
+		if (info->sw_io_8 == 1 || info->wl_led == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_9:
+		if (info->sw_io_9 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_10:
+		if (info->sw_io_10 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_11:
+		if (info->sw_io_11 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_12:
+		if (info->sw_io_12 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_13:
+		if (info->sw_io_13 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_14:
+		if (info->sw_io_14 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_15:
+		if (info->sw_io_15 == 1)
+			status = HALMAC_RET_PINMUX_USED;
+		break;
+	default:
+		return HALMAC_RET_SWITCH_CASE_ERROR;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]chk_pinmux_valid func : %X status : %X\n",
+			gpio_func, status);
+
+	return status;
+}
+
+#endif /* HALMAC_8822B_SUPPORT */

hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.h

@@ -0,0 +1,38 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_GPIO_8822B_H_
+#define _HALMAC_GPIO_8822B_H_
+
+#include "../../halmac_api.h"
+#include "../../halmac_gpio_cmd.h"
+
+#if HALMAC_8822B_SUPPORT
+
+enum halmac_ret_status
+pinmux_get_func_8822b(struct halmac_adapter *adapter,
+		      enum halmac_gpio_func gpio_func, u8 *enable);
+
+enum halmac_ret_status
+pinmux_set_func_8822b(struct halmac_adapter *adapter,
+		      enum halmac_gpio_func gpio_func);
+
+enum halmac_ret_status
+pinmux_free_func_8822b(struct halmac_adapter *adapter,
+		       enum halmac_gpio_func gpio_func);
+
+#endif /* HALMAC_8822B_SUPPORT */
+
+#endif/* _HALMAC_GPIO_8822B_H_ */

hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.c

@@ -0,0 +1,724 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_init_8822b.h"
+#include "halmac_8822b_cfg.h"
+#include "halmac_pcie_8822b.h"
+#include "halmac_sdio_8822b.h"
+#include "halmac_usb_8822b.h"
+#include "halmac_gpio_8822b.h"
+#include "halmac_common_8822b.h"
+#include "halmac_cfg_wmac_8822b.h"
+#include "../halmac_common_88xx.h"
+#include "../halmac_init_88xx.h"
+
+#if HALMAC_8822B_SUPPORT
+
+#define RSVD_PG_DRV_NUM			16
+#define RSVD_PG_H2C_EXTRAINFO_NUM	24
+#define RSVD_PG_H2C_STATICINFO_NUM	8
+#define RSVD_PG_H2CQ_NUM		8
+#define RSVD_PG_CPU_INSTRUCTION_NUM	0
+#define RSVD_PG_FW_TXBUF_NUM		4
+#define RSVD_PG_CSIBUF_NUM		0
+#define RSVD_PG_DLLB_NUM		32
+
+#define MAC_TRX_ENABLE	(BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \
+			BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \
+			BIT_MACTXEN | BIT_MACRXEN)
+
+#define BLK_DESC_NUM	0x3
+
+#define WLAN_AMPDU_MAX_TIME		0x70
+#define WLAN_RTS_LEN_TH			0xFF
+#define WLAN_RTS_TX_TIME_TH		0x08
+#define WLAN_MAX_AGG_PKT_LIMIT		0x20
+#define WLAN_RTS_MAX_AGG_PKT_LIMIT	0x20
+#define WALN_FAST_EDCA_VO_TH		0x06
+#define WLAN_FAST_EDCA_VI_TH		0x06
+#define WLAN_FAST_EDCA_BE_TH		0x06
+#define WLAN_FAST_EDCA_BK_TH		0x06
+#define WLAN_BAR_RETRY_LIMIT		0x01
+#define WLAN_RA_TRY_RATE_AGG_LIMIT	0x08
+
+#if HALMAC_PLATFORM_WINDOWS
+/*SDIO RQPN Mapping for Windows, extra queue is not implemented in Driver code*/
+struct halmac_rqpn HALMAC_RQPN_SDIO_8822B[] = {
+	/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+	{HALMAC_TRX_MODE_NORMAL,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_TRXSHARE,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_WMM,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_P2P,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_LOOPBACK,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+};
+#else
+/*SDIO RQPN Mapping*/
+struct halmac_rqpn HALMAC_RQPN_SDIO_8822B[] = {
+	/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+	{HALMAC_TRX_MODE_NORMAL,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_TRXSHARE,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_WMM,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_P2P,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_LOOPBACK,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+};
+#endif
+
+/*PCIE RQPN Mapping*/
+struct halmac_rqpn HALMAC_RQPN_PCIE_8822B[] = {
+	/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+	{HALMAC_TRX_MODE_NORMAL,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_TRXSHARE,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_WMM,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_P2P,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_LOOPBACK,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+};
+
+/*USB 2 Bulkout RQPN Mapping*/
+struct halmac_rqpn HALMAC_RQPN_2BULKOUT_8822B[] = {
+	/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+	{HALMAC_TRX_MODE_NORMAL,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_TRXSHARE,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_WMM,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_P2P,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_LOOPBACK,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+};
+
+/*USB 3 Bulkout RQPN Mapping*/
+struct halmac_rqpn HALMAC_RQPN_3BULKOUT_8822B[] = {
+	/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+	{HALMAC_TRX_MODE_NORMAL,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_TRXSHARE,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_WMM,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_P2P,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_LOOPBACK,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+};
+
+/*USB 4 Bulkout RQPN Mapping*/
+struct halmac_rqpn HALMAC_RQPN_4BULKOUT_8822B[] = {
+	/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+	{HALMAC_TRX_MODE_NORMAL,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_TRXSHARE,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_WMM,
+	 HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_P2P,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_LOOPBACK,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK,
+	 HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+	 HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+};
+
+#if HALMAC_PLATFORM_WINDOWS
+/*SDIO Page Number*/
+struct halmac_pg_num HALMAC_PG_NUM_SDIO_8822B[] = {
+	/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+	{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1},
+	{HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 0, 1},
+	{HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1},
+	{HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1},
+	{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 640},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 640},
+};
+#else
+/*SDIO Page Number*/
+struct halmac_pg_num HALMAC_PG_NUM_SDIO_8822B[] = {
+	/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+	{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
+	{HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 32, 1},
+	{HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
+	{HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
+	{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
+};
+#endif
+
+/*PCIE Page Number*/
+struct halmac_pg_num HALMAC_PG_NUM_PCIE_8822B[] = {
+	/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+	{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
+	{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1},
+	{HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
+	{HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
+	{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
+};
+
+/*USB 2 Bulkout Page Number*/
+struct halmac_pg_num HALMAC_PG_NUM_2BULKOUT_8822B[] = {
+	/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+	{HALMAC_TRX_MODE_NORMAL, 64, 64, 0, 0, 1},
+	{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 0, 0, 1},
+	{HALMAC_TRX_MODE_WMM, 64, 64, 0, 0, 1},
+	{HALMAC_TRX_MODE_P2P, 64, 64, 0, 0, 1},
+	{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 0, 0, 1024},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 0, 0, 1024},
+};
+
+/*USB 3 Bulkout Page Number*/
+struct halmac_pg_num HALMAC_PG_NUM_3BULKOUT_8822B[] = {
+	/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+	{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1},
+	{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 0, 1},
+	{HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1},
+	{HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1},
+	{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 1024},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 1024},
+};
+
+/*USB 4 Bulkout Page Number*/
+struct halmac_pg_num HALMAC_PG_NUM_4BULKOUT_8822B[] = {
+	/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+	{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
+	{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1},
+	{HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
+	{HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
+	{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
+	{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
+};
+
+static enum halmac_ret_status
+txdma_queue_mapping_8822b(struct halmac_adapter *adapter,
+			  enum halmac_trx_mode mode);
+
+static enum halmac_ret_status
+priority_queue_cfg_8822b(struct halmac_adapter *adapter,
+			 enum halmac_trx_mode mode);
+
+static enum halmac_ret_status
+set_trx_fifo_info_8822b(struct halmac_adapter *adapter,
+			enum halmac_trx_mode mode);
+enum halmac_ret_status
+mount_api_8822b(struct halmac_adapter *adapter)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	adapter->chip_id = HALMAC_CHIP_ID_8822B;
+	adapter->hw_cfg_info.efuse_size = EFUSE_SIZE_8822B;
+	adapter->hw_cfg_info.eeprom_size = EEPROM_SIZE_8822B;
+	adapter->hw_cfg_info.bt_efuse_size = BT_EFUSE_SIZE_8822B;
+	adapter->hw_cfg_info.cam_entry_num = SEC_CAM_NUM_8822B;
+	adapter->hw_cfg_info.tx_fifo_size = TX_FIFO_SIZE_8822B;
+	adapter->hw_cfg_info.rx_fifo_size = RX_FIFO_SIZE_8822B;
+	adapter->hw_cfg_info.ac_oqt_size = OQT_ENTRY_AC_8822B;
+	adapter->hw_cfg_info.non_ac_oqt_size = OQT_ENTRY_NOAC_8822B;
+	adapter->hw_cfg_info.usb_txagg_num = BLK_DESC_NUM;
+	adapter->txff_alloc.rsvd_drv_pg_num = RSVD_PG_DRV_NUM;
+
+	api->halmac_init_trx_cfg = init_trx_cfg_8822b;
+	api->halmac_init_protocol_cfg = init_protocol_cfg_8822b;
+	api->halmac_init_h2c = init_h2c_8822b;
+	api->halmac_pinmux_get_func = pinmux_get_func_8822b;
+	api->halmac_pinmux_set_func = pinmux_set_func_8822b;
+	api->halmac_pinmux_free_func = pinmux_free_func_8822b;
+	api->halmac_get_hw_value = get_hw_value_8822b;
+	api->halmac_set_hw_value = set_hw_value_8822b;
+	api->halmac_cfg_drv_info = cfg_drv_info_8822b;
+	api->halmac_fill_txdesc_checksum = fill_txdesc_check_sum_8822b;
+	api->halmac_init_low_pwr = init_low_pwr_8822b;
+
+	if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+		api->halmac_mac_power_switch = mac_pwr_switch_sdio_8822b;
+		api->halmac_phy_cfg = phy_cfg_sdio_8822b;
+		api->halmac_pcie_switch = pcie_switch_sdio_8822b;
+		api->halmac_interface_integration_tuning = intf_tun_sdio_8822b;
+		api->halmac_tx_allowed_sdio = tx_allowed_sdio_8822b;
+		api->halmac_get_sdio_tx_addr = get_sdio_tx_addr_8822b;
+		api->halmac_reg_read_8 = reg_r8_sdio_8822b;
+		api->halmac_reg_write_8 = reg_w8_sdio_8822b;
+		api->halmac_reg_read_16 = reg_r16_sdio_8822b;
+		api->halmac_reg_write_16 = reg_w16_sdio_8822b;
+		api->halmac_reg_read_32 = reg_r32_sdio_8822b;
+		api->halmac_reg_write_32 = reg_w32_sdio_8822b;
+
+		adapter->sdio_fs.macid_map_size = MACID_MAX_8822B * 2;
+		if (!adapter->sdio_fs.macid_map) {
+			adapter->sdio_fs.macid_map =
+			(u8 *)PLTFM_MALLOC(adapter->sdio_fs.macid_map_size);
+			if (!adapter->sdio_fs.macid_map)
+				PLTFM_MSG_ERR("[ERR]allocate macid_map!!\n");
+		}
+	} else if (adapter->intf == HALMAC_INTERFACE_USB) {
+		api->halmac_mac_power_switch = mac_pwr_switch_usb_8822b;
+		api->halmac_phy_cfg = phy_cfg_usb_8822b;
+		api->halmac_pcie_switch = pcie_switch_usb_8822b;
+		api->halmac_interface_integration_tuning = intf_tun_usb_8822b;
+	} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
+		api->halmac_mac_power_switch = mac_pwr_switch_pcie_8822b;
+		api->halmac_phy_cfg = phy_cfg_pcie_8822b;
+		api->halmac_pcie_switch = pcie_switch_8822b;
+		api->halmac_interface_integration_tuning = intf_tun_pcie_8822b;
+	} else {
+		PLTFM_MSG_ERR("[ERR]Undefined IC\n");
+		return HALMAC_RET_CHIP_NOT_SUPPORT;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_trx_cfg_8822b() - config trx dma register
+ * @adapter : the adapter of halmac
+ * @mode : trx mode selection
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_trx_cfg_8822b(struct halmac_adapter *adapter, enum halmac_trx_mode mode)
+{
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	adapter->trx_mode = mode;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	status = txdma_queue_mapping_8822b(adapter, mode);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]queue mapping\n");
+		return status;
+	}
+
+	value8 = 0;
+	HALMAC_REG_W8(REG_CR, value8);
+	value8 = MAC_TRX_ENABLE;
+	HALMAC_REG_W8(REG_CR, value8);
+	HALMAC_REG_W32(REG_H2CQ_CSR, BIT(31));
+
+	status = priority_queue_cfg_8822b(adapter, mode);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]halmac_txdma_queue_mapping fail!\n");
+		return status;
+	}
+
+	if (adapter->txff_alloc.rx_fifo_exp_mode !=
+	    HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE)
+		HALMAC_REG_W8(REG_RX_DRVINFO_SZ, RX_DESC_DUMMY_SIZE_8822B >> 3);
+
+	status = init_h2c_8822b(adapter);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]init h2cq!\n");
+		return status;
+	}
+
+	if (adapter->intf == HALMAC_INTERFACE_USB)
+		HALMAC_REG_W8_SET(REG_TXDMA_PQ_MAP, BIT(0));
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+txdma_queue_mapping_8822b(struct halmac_adapter *adapter,
+			  enum halmac_trx_mode mode)
+{
+	u16 value16;
+	struct halmac_rqpn *cur_rqpn_sel = NULL;
+	enum halmac_ret_status status;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+		cur_rqpn_sel = HALMAC_RQPN_SDIO_8822B;
+	} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
+		cur_rqpn_sel = HALMAC_RQPN_PCIE_8822B;
+	} else if (adapter->intf == HALMAC_INTERFACE_USB) {
+		if (adapter->bulkout_num == 2) {
+			cur_rqpn_sel = HALMAC_RQPN_2BULKOUT_8822B;
+		} else if (adapter->bulkout_num == 3) {
+			cur_rqpn_sel = HALMAC_RQPN_3BULKOUT_8822B;
+		} else if (adapter->bulkout_num == 4) {
+			cur_rqpn_sel = HALMAC_RQPN_4BULKOUT_8822B;
+		} else {
+			PLTFM_MSG_ERR("[ERR]invalid intf\n");
+			return HALMAC_RET_NOT_SUPPORT;
+		}
+	} else {
+		return HALMAC_RET_NOT_SUPPORT;
+	}
+
+	status = rqpn_parser_88xx(adapter, mode, cur_rqpn_sel);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	value16 = 0;
+	value16 |= BIT_TXDMA_HIQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_HI]);
+	value16 |= BIT_TXDMA_MGQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_MG]);
+	value16 |= BIT_TXDMA_BKQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_BK]);
+	value16 |= BIT_TXDMA_BEQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_BE]);
+	value16 |= BIT_TXDMA_VIQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_VI]);
+	value16 |= BIT_TXDMA_VOQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_VO]);
+	HALMAC_REG_W16(REG_TXDMA_PQ_MAP, value16);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+priority_queue_cfg_8822b(struct halmac_adapter *adapter,
+			 enum halmac_trx_mode mode)
+{
+	u8 transfer_mode = 0;
+	u8 value8;
+	u32 cnt;
+	struct halmac_txff_allocation *txff_info = &adapter->txff_alloc;
+	enum halmac_ret_status status;
+	struct halmac_pg_num *cur_pg_num = NULL;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	status = set_trx_fifo_info_8822b(adapter, mode);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]set trx fifo!!\n");
+		return status;
+	}
+	if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+		cur_pg_num = HALMAC_PG_NUM_SDIO_8822B;
+	} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
+		cur_pg_num = HALMAC_PG_NUM_PCIE_8822B;
+	} else if (adapter->intf == HALMAC_INTERFACE_USB) {
+		if (adapter->bulkout_num == 2) {
+			cur_pg_num = HALMAC_PG_NUM_2BULKOUT_8822B;
+		} else if (adapter->bulkout_num == 3) {
+			cur_pg_num = HALMAC_PG_NUM_3BULKOUT_8822B;
+		} else if (adapter->bulkout_num == 4) {
+			cur_pg_num = HALMAC_PG_NUM_4BULKOUT_8822B;
+		} else {
+			PLTFM_MSG_ERR("[ERR]interface not support\n");
+			return HALMAC_RET_NOT_SUPPORT;
+		}
+	} else {
+		return HALMAC_RET_NOT_SUPPORT;
+	}
+
+	status = pg_num_parser_88xx(adapter, mode, cur_pg_num);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	HALMAC_REG_W16(REG_FIFOPAGE_INFO_1, txff_info->high_queue_pg_num);
+	HALMAC_REG_W16(REG_FIFOPAGE_INFO_2, txff_info->low_queue_pg_num);
+	HALMAC_REG_W16(REG_FIFOPAGE_INFO_3, txff_info->normal_queue_pg_num);
+	HALMAC_REG_W16(REG_FIFOPAGE_INFO_4, txff_info->extra_queue_pg_num);
+	HALMAC_REG_W16(REG_FIFOPAGE_INFO_5, txff_info->pub_queue_pg_num);
+	HALMAC_REG_W32_SET(REG_RQPN_CTRL_2, BIT(31));
+
+	adapter->sdio_fs.hiq_pg_num = txff_info->high_queue_pg_num;
+	adapter->sdio_fs.miq_pg_num = txff_info->normal_queue_pg_num;
+	adapter->sdio_fs.lowq_pg_num = txff_info->low_queue_pg_num;
+	adapter->sdio_fs.pubq_pg_num = txff_info->pub_queue_pg_num;
+	adapter->sdio_fs.exq_pg_num = txff_info->extra_queue_pg_num;
+
+	HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, txff_info->rsvd_boundary);
+	HALMAC_REG_W8_SET(REG_FWHW_TXQ_CTRL + 2, BIT(4));
+
+	/*20170411 Soar*/
+	/* SDIO sometimes use two CMD52 to do HALMAC_REG_W16 */
+	/* and may cause a mismatch between HW status and Reg value. */
+	/* A patch is to write high byte first, suggested by Argis */
+	if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+		value8 = (u8)(txff_info->rsvd_boundary >> 8 & 0xFF);
+		HALMAC_REG_W8(REG_BCNQ_BDNY_V1 + 1, value8);
+		value8 = (u8)(txff_info->rsvd_boundary & 0xFF);
+		HALMAC_REG_W8(REG_BCNQ_BDNY_V1, value8);
+	} else {
+		HALMAC_REG_W16(REG_BCNQ_BDNY_V1, txff_info->rsvd_boundary);
+	}
+
+	HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2 + 2, txff_info->rsvd_boundary);
+
+	/*20170411 Soar*/
+	/* SDIO sometimes use two CMD52 to do HALMAC_REG_W16 */
+	/* and may cause a mismatch between HW status and Reg value. */
+	/* A patch is to write high byte first, suggested by Argis */
+	if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+		value8 = (u8)(txff_info->rsvd_boundary >> 8 & 0xFF);
+		HALMAC_REG_W8(REG_BCNQ1_BDNY_V1 + 1, value8);
+		value8 = (u8)(txff_info->rsvd_boundary & 0xFF);
+		HALMAC_REG_W8(REG_BCNQ1_BDNY_V1, value8);
+	} else {
+		HALMAC_REG_W16(REG_BCNQ1_BDNY_V1, txff_info->rsvd_boundary);
+	}
+
+	HALMAC_REG_W32(REG_RXFF_BNDY,
+		       adapter->hw_cfg_info.rx_fifo_size -
+		       C2H_PKT_BUF_88XX - 1);
+
+	if (adapter->intf == HALMAC_INTERFACE_USB) {
+		value8 = HALMAC_REG_R8(REG_AUTO_LLT_V1);
+		value8 &= ~(BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM);
+		value8 |= (BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM);
+		HALMAC_REG_W8(REG_AUTO_LLT_V1, value8);
+
+		HALMAC_REG_W8(REG_AUTO_LLT_V1 + 3, BLK_DESC_NUM);
+		HALMAC_REG_W8_SET(REG_TXDMA_OFFSET_CHK + 1, BIT(1));
+	}
+
+	HALMAC_REG_W8_SET(REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1);
+	cnt = 1000;
+	while (HALMAC_REG_R8(REG_AUTO_LLT_V1) & BIT_AUTO_INIT_LLT_V1) {
+		cnt--;
+		if (cnt == 0)
+			return HALMAC_RET_INIT_LLT_FAIL;
+	}
+
+	if (mode == HALMAC_TRX_MODE_DELAY_LOOPBACK) {
+		transfer_mode = HALMAC_TRNSFER_LOOPBACK_DELAY;
+		HALMAC_REG_W16(REG_WMAC_LBK_BUF_HD_V1,
+			       adapter->txff_alloc.rsvd_boundary);
+	} else if (mode == HALMAC_TRX_MODE_LOOPBACK) {
+		transfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT;
+	} else {
+		transfer_mode = HALMAC_TRNSFER_NORMAL;
+	}
+
+	adapter->hw_cfg_info.trx_mode = transfer_mode;
+	HALMAC_REG_W8(REG_CR + 3, transfer_mode);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+set_trx_fifo_info_8822b(struct halmac_adapter *adapter,
+			enum halmac_trx_mode mode)
+{
+	u16 cur_pg_addr;
+	u32 txff_size = TX_FIFO_SIZE_8822B;
+	u32 rxff_size = RX_FIFO_SIZE_8822B;
+	struct halmac_txff_allocation *info = &adapter->txff_alloc;
+
+	if (info->rx_fifo_exp_mode == HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK) {
+		txff_size = TX_FIFO_SIZE_RX_EXPAND_1BLK_8822B;
+		rxff_size = RX_FIFO_SIZE_RX_EXPAND_1BLK_8822B;
+	}
+
+	if (info->la_mode != HALMAC_LA_MODE_DISABLE) {
+		txff_size = TX_FIFO_SIZE_LA_8822B;
+		rxff_size = RX_FIFO_SIZE_8822B;
+	}
+
+	adapter->hw_cfg_info.tx_fifo_size = txff_size;
+	adapter->hw_cfg_info.rx_fifo_size = rxff_size;
+	info->tx_fifo_pg_num = (u16)(txff_size >> TX_PAGE_SIZE_SHIFT_88XX);
+
+	info->rsvd_pg_num = info->rsvd_drv_pg_num +
+					RSVD_PG_H2C_EXTRAINFO_NUM +
+					RSVD_PG_H2C_STATICINFO_NUM +
+					RSVD_PG_H2CQ_NUM +
+					RSVD_PG_CPU_INSTRUCTION_NUM +
+					RSVD_PG_FW_TXBUF_NUM +
+					RSVD_PG_CSIBUF_NUM;
+
+	if (mode == HALMAC_TRX_MODE_DELAY_LOOPBACK)
+		info->rsvd_pg_num += RSVD_PG_DLLB_NUM;
+
+	if (info->rsvd_pg_num > info->tx_fifo_pg_num)
+		return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;
+
+	info->acq_pg_num = info->tx_fifo_pg_num - info->rsvd_pg_num;
+	info->rsvd_boundary = info->tx_fifo_pg_num - info->rsvd_pg_num;
+
+	cur_pg_addr = info->tx_fifo_pg_num;
+	cur_pg_addr -= RSVD_PG_CSIBUF_NUM;
+	info->rsvd_csibuf_addr = cur_pg_addr;
+	cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM;
+	info->rsvd_fw_txbuf_addr = cur_pg_addr;
+	cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM;
+	info->rsvd_cpu_instr_addr = cur_pg_addr;
+	cur_pg_addr -= RSVD_PG_H2CQ_NUM;
+	info->rsvd_h2cq_addr = cur_pg_addr;
+	cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM;
+	info->rsvd_h2c_sta_info_addr = cur_pg_addr;
+	cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM;
+	info->rsvd_h2c_info_addr = cur_pg_addr;
+	cur_pg_addr -= info->rsvd_drv_pg_num;
+	info->rsvd_drv_addr = cur_pg_addr;
+
+	if (mode == HALMAC_TRX_MODE_DELAY_LOOPBACK)
+		info->rsvd_drv_addr -= RSVD_PG_DLLB_NUM;
+
+	if (info->rsvd_boundary != info->rsvd_drv_addr)
+		return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_protocol_cfg_8822b() - config protocol register
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_protocol_cfg_8822b(struct halmac_adapter *adapter)
+{
+	u32 value32;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	HALMAC_REG_W8_CLR(REG_SW_AMPDU_BURST_MODE_CTRL, BIT(6));
+
+	HALMAC_REG_W8(REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
+	HALMAC_REG_W8(REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
+
+	value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
+					(WLAN_MAX_AGG_PKT_LIMIT << 16) |
+					(WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
+	HALMAC_REG_W32(REG_PROT_MODE_CTRL, value32);
+
+	HALMAC_REG_W16(REG_BAR_MODE_CTRL + 2,
+		       WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
+
+	HALMAC_REG_W8(REG_FAST_EDCA_VOVI_SETTING, WALN_FAST_EDCA_VO_TH);
+	HALMAC_REG_W8(REG_FAST_EDCA_VOVI_SETTING + 2, WLAN_FAST_EDCA_VI_TH);
+	HALMAC_REG_W8(REG_FAST_EDCA_BEBK_SETTING, WLAN_FAST_EDCA_BE_TH);
+	HALMAC_REG_W8(REG_FAST_EDCA_BEBK_SETTING + 2, WLAN_FAST_EDCA_BK_TH);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_h2c_8822b() - config h2c packet buffer
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_h2c_8822b(struct halmac_adapter *adapter)
+{
+	u8 value8;
+	u32 value32;
+	u32 h2cq_addr;
+	u32 h2cq_size;
+	struct halmac_txff_allocation *txff_info = &adapter->txff_alloc;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	h2cq_addr = txff_info->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT_88XX;
+	h2cq_size = RSVD_PG_H2CQ_NUM << TX_PAGE_SIZE_SHIFT_88XX;
+
+	value32 = HALMAC_REG_R32(REG_H2C_HEAD);
+	value32 = (value32 & 0xFFFC0000) | h2cq_addr;
+	HALMAC_REG_W32(REG_H2C_HEAD, value32);
+
+	value32 = HALMAC_REG_R32(REG_H2C_READ_ADDR);
+	value32 = (value32 & 0xFFFC0000) | h2cq_addr;
+	HALMAC_REG_W32(REG_H2C_READ_ADDR, value32);
+
+	value32 = HALMAC_REG_R32(REG_H2C_TAIL);
+	value32 &= 0xFFFC0000;
+	value32 |= (h2cq_addr + h2cq_size);
+	HALMAC_REG_W32(REG_H2C_TAIL, value32);
+
+	value8 = HALMAC_REG_R8(REG_H2C_INFO);
+	value8 = (u8)((value8 & 0xFC) | 0x01);
+	HALMAC_REG_W8(REG_H2C_INFO, value8);
+
+	value8 = HALMAC_REG_R8(REG_H2C_INFO);
+	value8 = (u8)((value8 & 0xFB) | 0x04);
+	HALMAC_REG_W8(REG_H2C_INFO, value8);
+
+	value8 = HALMAC_REG_R8(REG_TXDMA_OFFSET_CHK + 1);
+	value8 = (u8)((value8 & 0x7f) | 0x80);
+	HALMAC_REG_W8(REG_TXDMA_OFFSET_CHK + 1, value8);
+
+	adapter->h2c_info.buf_size = h2cq_size;
+	get_h2c_buf_free_space_88xx(adapter);
+
+	if (adapter->h2c_info.buf_size != adapter->h2c_info.buf_fs) {
+		PLTFM_MSG_ERR("[ERR]get h2c free space error!\n");
+		return HALMAC_RET_GET_H2C_SPACE_ERR;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]h2c fs : %d\n", adapter->h2c_info.buf_fs);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_8822B_SUPPORT */

hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.h

@@ -0,0 +1,37 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_INIT_8822B_H_
+#define _HALMAC_INIT_8822B_H_
+
+#include "../../halmac_api.h"
+
+#if HALMAC_8822B_SUPPORT
+
+enum halmac_ret_status
+mount_api_8822b(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+init_trx_cfg_8822b(struct halmac_adapter *adapter, enum halmac_trx_mode mode);
+
+enum halmac_ret_status
+init_protocol_cfg_8822b(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+init_h2c_8822b(struct halmac_adapter *adapter);
+
+#endif /* HALMAC_8822B_SUPPORT */
+
+#endif/* _HALMAC_INIT_8822B_H_ */

hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.c

@@ -0,0 +1,214 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_pcie_8822b.h"
+#include "halmac_pwr_seq_8822b.h"
+#include "../halmac_init_88xx.h"
+#include "../halmac_common_88xx.h"
+#include "../halmac_pcie_88xx.h"
+#include "../halmac_88xx_cfg.h"
+
+#if HALMAC_8822B_SUPPORT
+
+/**
+ * mac_pwr_switch_pcie_8822b() - switch mac power
+ * @adapter : the adapter of halmac
+ * @pwr : power state
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mac_pwr_switch_pcie_8822b(struct halmac_adapter *adapter,
+			  enum halmac_mac_power pwr)
+{
+	u8 value8;
+	u8 rpwm;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_ret_status status;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+	PLTFM_MSG_TRACE("[TRACE]pwr = %x\n", pwr);
+	PLTFM_MSG_TRACE("[TRACE]8822B pwr seq ver = %s\n",
+			HALMAC_8822B_PWR_SEQ_VER);
+
+	adapter->rpwm = HALMAC_REG_R8(REG_PCIE_HRPWM1_V1);
+
+	/* Check FW still exist or not */
+	if (HALMAC_REG_R16(REG_MCUFW_CTRL) == 0xC078) {
+		/* Leave 32K */
+		rpwm = (u8)((adapter->rpwm ^ BIT(7)) & 0x80);
+		HALMAC_REG_W8(REG_PCIE_HRPWM1_V1, rpwm);
+	}
+
+	value8 = HALMAC_REG_R8(REG_CR);
+	if (value8 == 0xEA)
+		adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
+	else
+		adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
+
+	/* Check if power switch is needed */
+	if (pwr == HALMAC_MAC_POWER_ON &&
+	    adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_ON) {
+		PLTFM_MSG_WARN("[WARN]power state unchange!!\n");
+		return HALMAC_RET_PWR_UNCHANGE;
+	}
+
+	if (pwr == HALMAC_MAC_POWER_OFF) {
+		status = trxdma_check_idle_88xx(adapter);
+		if (status != HALMAC_RET_SUCCESS)
+			return status;
+		if (pwr_seq_parser_88xx(adapter, card_dis_flow_8822b) !=
+		    HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]Handle power off cmd error\n");
+			return HALMAC_RET_POWER_OFF_FAIL;
+		}
+
+		adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
+		adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
+		init_adapter_dynamic_param_88xx(adapter);
+	} else {
+		if (pwr_seq_parser_88xx(adapter, card_en_flow_8822b) !=
+		    HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]Handle power on cmd error\n");
+			return HALMAC_RET_POWER_ON_FAIL;
+		}
+
+		adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_pcie_switch_8822b() - pcie gen1/gen2 switch
+ * @adapter : the adapter of halmac
+ * @cfg : gen1/gen2 selection
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pcie_switch_8822b(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg)
+{
+	u8 value8;
+	u32 value32;
+	u8 speed = 0;
+	u32 cnt = 0;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (cfg == HALMAC_PCIE_GEN1) {
+		value8 = dbi_r8_88xx(adapter, LINK_CTRL2_REG_OFFSET) & 0xF0;
+		dbi_w8_88xx(adapter, LINK_CTRL2_REG_OFFSET, value8 | BIT(0));
+
+		value32 = dbi_r32_88xx(adapter, GEN2_CTRL_OFFSET);
+		dbi_w32_88xx(adapter, GEN2_CTRL_OFFSET, value32 | BIT(17));
+
+		speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET) & 0x0F;
+		cnt = 2000;
+
+		while ((speed != PCIE_GEN1_SPEED) && (cnt != 0)) {
+			PLTFM_DELAY_US(50);
+			speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET);
+			speed &= 0x0F;
+			cnt--;
+		}
+
+		if (speed != PCIE_GEN1_SPEED) {
+			PLTFM_MSG_ERR("[ERR]Speed change to GEN1 fail !\n");
+			return HALMAC_RET_FAIL;
+		}
+
+	} else if (cfg == HALMAC_PCIE_GEN2) {
+		value8 = dbi_r8_88xx(adapter, LINK_CTRL2_REG_OFFSET) & 0xF0;
+		dbi_w8_88xx(adapter, LINK_CTRL2_REG_OFFSET, value8 | BIT(1));
+
+		value32 = dbi_r32_88xx(adapter, GEN2_CTRL_OFFSET);
+		dbi_w32_88xx(adapter, GEN2_CTRL_OFFSET, value32 | BIT(17));
+
+		speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET) & 0x0F;
+		cnt = 2000;
+
+		while ((speed != PCIE_GEN2_SPEED) && (cnt != 0)) {
+			PLTFM_DELAY_US(50);
+			speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET);
+			speed &= 0x0F;
+			cnt--;
+		}
+
+		if (speed != PCIE_GEN2_SPEED) {
+			PLTFM_MSG_ERR("[ERR]Speed change to GEN1 fail !\n");
+			return HALMAC_RET_FAIL;
+		}
+
+	} else {
+		PLTFM_MSG_ERR("[ERR]Error Speed !\n");
+		return HALMAC_RET_FAIL;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * phy_cfg_pcie_8822b() - phy config
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+phy_cfg_pcie_8822b(struct halmac_adapter *adapter,
+		   enum halmac_intf_phy_platform pltfm)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	status = parse_intf_phy_88xx(adapter, pcie_gen1_phy_param_8822b, pltfm,
+				     HAL_INTF_PHY_PCIE_GEN1);
+
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	status = parse_intf_phy_88xx(adapter, pcie_gen2_phy_param_8822b, pltfm,
+				     HAL_INTF_PHY_PCIE_GEN2);
+
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * intf_tun_pcie_8822b() - pcie interface fine tuning
+ * @adapter : the adapter of halmac
+ * Author : Rick Liu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+intf_tun_pcie_8822b(struct halmac_adapter *adapter)
+{
+	return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_8822B_SUPPORT*/

hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.h

@@ -0,0 +1,42 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_API_8822B_PCIE_H_
+#define _HALMAC_API_8822B_PCIE_H_
+
+#include "../../halmac_api.h"
+
+#if HALMAC_8822B_SUPPORT
+
+extern struct halmac_intf_phy_para pcie_gen1_phy_param_8822b[];
+extern struct halmac_intf_phy_para pcie_gen2_phy_param_8822b[];
+
+enum halmac_ret_status
+mac_pwr_switch_pcie_8822b(struct halmac_adapter *adapter,
+			  enum halmac_mac_power pwr);
+
+enum halmac_ret_status
+pcie_switch_8822b(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg);
+
+enum halmac_ret_status
+phy_cfg_pcie_8822b(struct halmac_adapter *adapter,
+		   enum halmac_intf_phy_platform pltfm);
+
+enum halmac_ret_status
+intf_tun_pcie_8822b(struct halmac_adapter *adapter);
+
+#endif /* HALMAC_8822B_SUPPORT*/
+
+#endif/* _HALMAC_API_8822B_PCIE_H_ */

hal/halmac/halmac_88xx/halmac_8822b/halmac_phy_8822b.c

@@ -0,0 +1,150 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "../../halmac_type.h"
+
+/**
+ * ============ip sel item list============
+ * HALMAC_IP_INTF_PHY
+ *	USB2 : usb2 phy, 1byte value
+ *	USB3 : usb3 phy, 2byte value
+ *	PCIE1 : pcie gen1 mdio, 2byte value
+ *	PCIE2 : pcie gen2 mdio, 2byte value
+ * HALMAC_IP_SEL_MAC
+ *	USB2, USB3, PCIE1, PCIE2 : mac ip, 1byte value
+ * HALMAC_IP_PCIE_DBI
+ *	USB2 USB3 : none
+ *	PCIE1, PCIE2 : pcie dbi, 1byte value
+ */
+
+#if HALMAC_8822B_SUPPORT
+
+struct halmac_intf_phy_para usb2_phy_param_8822b[] = {
+	/* {offset, value, ip sel, cut mask, platform mask} */
+	{0xFFFF, 0x00,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_ALL,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+};
+
+struct halmac_intf_phy_para usb3_phy_8822b[] = {
+	/* {offset, value, ip sel, cut mask, platform mask} */
+	{0x0001, 0xA841,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_D,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0xFFFF, 0x0000,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_ALL,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+};
+
+struct halmac_intf_phy_para pcie_gen1_phy_param_8822b[] = {
+	/* {offset, value, ip sel, cut mask, platform mask} */
+	{0x0001, 0xA841,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0x0002, 0x60C6,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0x0008, 0x3596,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0x0009, 0x321C,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0x000A, 0x9623,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0x0020, 0x94FF,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0x0021, 0xFFCF,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0x0026, 0xC006,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0x0029, 0xFF0E,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0x002A, 0x1840,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0xFFFF, 0x0000,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_ALL,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+};
+
+struct halmac_intf_phy_para pcie_gen2_phy_param_8822b[] = {
+	/* {offset, value, ip sel, cut mask, platform mask} */
+	{0x0001, 0xA841,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0x0002, 0x60C6,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0x0008, 0x3597,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0x0009, 0x321C,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0x000A, 0x9623,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0x0020, 0x94FF,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0x0021, 0xFFCF,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0x0026, 0xC006,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0x0029, 0xFF0E,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0x002A, 0x3040,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_C,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+	{0xFFFF, 0x0000,
+	 HALMAC_IP_INTF_PHY,
+	 HALMAC_INTF_PHY_CUT_ALL,
+	 HALMAC_INTF_PHY_PLATFORM_ALL},
+};
+
+#endif /* HALMAC_8822B_SUPPORT*/

hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.c

@@ -0,0 +1,914 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_pwr_seq_8822b.h"
+
+#if HALMAC_8822B_SUPPORT
+
+struct halmac_wlan_pwr_cfg TRANS_CARDDIS_TO_CARDEMU_8822B[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},
+	{0x004A,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
+	{0x0300,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0x0301,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_ACT_8822B[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0012,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0012,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0020,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0001,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_DELAY, 1, HALMAC_PWR_DELAY_MS},
+	{0x0000,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), 0},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
+	{0x0075,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0006,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},
+	{0x0075,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0xFF1A,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0x0006,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), 0},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
+	{0x10C3,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, BIT(0), 0},
+	{0x0020,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)},
+	{0x10A8,
+	 HALMAC_PWR_CUT_C_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0x10A9,
+	 HALMAC_PWR_CUT_C_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xef},
+	{0x10AA,
+	 HALMAC_PWR_CUT_C_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x0c},
+	{0x0068,
+	 HALMAC_PWR_CUT_C_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)},
+	{0x0029,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xF9},
+	{0x0024,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(2), 0},
+	{0x0074,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},
+	{0x00AF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+struct halmac_wlan_pwr_cfg TRANS_ACT_TO_CARDEMU_8822B[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0003,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(2), 0},
+	{0x0093,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3), 0},
+	{0x001F,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0x00EF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0xFF1A,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x30},
+	{0x0049,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0006,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x10C3,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, BIT(1), 0},
+	{0x0020,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3), 0},
+	{0x0000,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_CARDDIS_8822B[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+	{0x0007,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
+	{0x0067,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), 0},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
+	{0x004A,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0067,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), 0},
+	{0x0067,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(4), 0},
+	{0x004F,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0067,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0046,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(6), BIT(6)},
+	{0x0067,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(2), 0},
+	{0x0046,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+	{0x0062,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)},
+	{0x0081,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), 0},
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_POLLING, BIT(1), 0},
+	{0x0090,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0044,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0x0040,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x90},
+	{0x0041,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x00},
+	{0x0042,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x04},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+/* Card Enable Array */
+struct halmac_wlan_pwr_cfg *card_en_flow_8822b[] = {
+	TRANS_CARDDIS_TO_CARDEMU_8822B,
+	TRANS_CARDEMU_TO_ACT_8822B,
+	NULL
+};
+
+/* Card Disable Array */
+struct halmac_wlan_pwr_cfg *card_dis_flow_8822b[] = {
+	TRANS_ACT_TO_CARDEMU_8822B,
+	TRANS_CARDEMU_TO_CARDDIS_8822B,
+	NULL
+};
+
+#if HALMAC_PLATFORM_TESTPROGRAM
+
+struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_SUS_8822B[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
+	{0x0007,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_POLLING, BIT(1), 0},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+struct halmac_wlan_pwr_cfg TRANS_SUS_TO_CARDEMU_8822B[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(7), 0},
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0086,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_PDN_8822B[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0007,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK | HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
+	{0x0006,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+struct halmac_wlan_pwr_cfg TRANS_PDN_TO_CARDEMU_8822B[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0005,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), 0},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+struct halmac_wlan_pwr_cfg TRANS_ACT_TO_LPS_8822B[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0101,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
+	{0x0199,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)},
+	{0x019B,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+	{0x1138,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)},
+	{0x0194,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0093,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x42},
+	{0x0092,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
+	{0x0090,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
+	{0x0301,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+	{0x0522,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+	{0x05F8,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+	{0x05F9,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+	{0x05FA,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+	{0x05FB,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_US},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0100,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F},
+	{0x0101,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0553,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},
+	{0x0008,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)},
+	{0x0109,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)},
+	{0x0090,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+struct halmac_wlan_pwr_cfg TRANS_ACT_TO_DEEP_LPS_8822B[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0101,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
+	{0x0199,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)},
+	{0x019B,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+	{0x1138,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)},
+	{0x0194,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0x0093,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x40},
+	{0x0092,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
+	{0x0090,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
+	{0x0301,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+	{0x0522,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+	{0x05F8,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+	{0x05F9,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+	{0x05FA,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+	{0x05FB,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_US},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0100,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F},
+	{0x0101,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0553,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},
+	{0x0008,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)},
+	{0x0109,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)},
+	{0x0090,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+struct halmac_wlan_pwr_cfg TRANS_LPS_TO_ACT_8822B[] = {
+	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+	{0x0080,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS},
+	{0x0080,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_SDIO_MSK,
+	 HALMAC_PWR_ADDR_SDIO,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), 0},
+	{0xFE58,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x84},
+	{0xFE58,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_USB_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x04},
+	{0x03D9,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS},
+	{0x03D9,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_PCI_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(7), 0},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS},
+	{0x0008,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(4), 0},
+	{0x0109,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_POLLING, BIT(7), 0},
+	{0x0101,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
+	{0x0100,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+	{0x0002,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)},
+	{0x0522,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+	{0x113C,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x03},
+	{0x0124,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+	{0x0125,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+	{0x0126,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+	{0x0127,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+	{0x0090,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+	{0x0101,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 HALMAC_PWR_ADDR_MAC,
+	 HALMAC_PWR_CMD_WRITE, BIT(2), 0},
+	{0xFFFF,
+	 HALMAC_PWR_CUT_ALL_MSK,
+	 HALMAC_PWR_INTF_ALL_MSK,
+	 0,
+	 HALMAC_PWR_CMD_END, 0, 0},
+};
+
+/* Suspend Array */
+struct halmac_wlan_pwr_cfg *suspend_flow_8822b[] = {
+	TRANS_ACT_TO_CARDEMU_8822B,
+	TRANS_CARDEMU_TO_SUS_8822B,
+	NULL
+};
+
+/* Resume Array */
+struct halmac_wlan_pwr_cfg *resume_flow_8822b[] = {
+	TRANS_SUS_TO_CARDEMU_8822B,
+	TRANS_CARDEMU_TO_ACT_8822B,
+	NULL
+};
+
+/* HWPDN Array - HW behavior */
+struct halmac_wlan_pwr_cfg *hwpdn_flow_8822b[] = {
+	NULL
+};
+
+/* Enter LPS - FW behavior */
+struct halmac_wlan_pwr_cfg *enter_lps_flow_8822b[] = {
+	TRANS_ACT_TO_LPS_8822B,
+	NULL
+};
+
+/* Enter Deep LPS - FW behavior */
+struct halmac_wlan_pwr_cfg *enter_dlps_flow_8822b[] = {
+	TRANS_ACT_TO_DEEP_LPS_8822B,
+	NULL
+};
+
+/* Leave LPS -FW behavior */
+struct halmac_wlan_pwr_cfg *leave_lps_flow_8822b[] = {
+	TRANS_LPS_TO_ACT_8822B,
+	NULL
+};
+
+#endif
+
+#endif /* HALMAC_8822B_SUPPORT*/

hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.h

@@ -0,0 +1,40 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef HALMAC_POWER_SEQUENCE_8822B
+#define HALMAC_POWER_SEQUENCE_8822B
+
+#include "../../halmac_pwr_seq_cmd.h"
+#include "../../halmac_hw_cfg.h"
+
+#if HALMAC_8822B_SUPPORT
+
+#define HALMAC_8822B_PWR_SEQ_VER  "V24"
+
+extern struct halmac_wlan_pwr_cfg *card_en_flow_8822b[];
+extern struct halmac_wlan_pwr_cfg *card_dis_flow_8822b[];
+
+#if HALMAC_PLATFORM_TESTPROGRAM
+extern struct halmac_wlan_pwr_cfg *suspend_flow_8822b[];
+extern struct halmac_wlan_pwr_cfg *resume_flow_8822b[];
+extern struct halmac_wlan_pwr_cfg *hwpdn_flow_8822b[];
+extern struct halmac_wlan_pwr_cfg *enter_lps_flow_8822b[];
+extern struct halmac_wlan_pwr_cfg *enter_dlps_flow_8822b[];
+extern struct halmac_wlan_pwr_cfg *leave_lps_flow_8822b[];
+#endif
+
+#endif /* HALMAC_8822B_SUPPORT*/
+
+#endif

hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.c

@@ -0,0 +1,868 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_sdio_8822b.h"
+#include "halmac_pwr_seq_8822b.h"
+#include "../halmac_init_88xx.h"
+#include "../halmac_common_88xx.h"
+#include "../halmac_sdio_88xx.h"
+
+#if HALMAC_8822B_SUPPORT
+
+#define WLAN_ACQ_NUM_MAX	8
+
+static enum halmac_ret_status
+chk_oqt_8822b(struct halmac_adapter *adapter, u32 tx_agg_num, u8 *buf,
+	      u8 macid_cnt);
+
+static enum halmac_ret_status
+update_oqt_free_space_8822b(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+update_sdio_free_page_8822b(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+chk_qsel_8822b(struct halmac_adapter *adapter, u8 qsel_first, u8 *pkt,
+	       u8 *macid_cnt);
+
+static enum halmac_ret_status
+chk_dma_mapping_8822b(struct halmac_adapter *adapter, u16 **cur_fs,
+		      u8 qsel_first);
+
+static enum halmac_ret_status
+chk_rqd_page_num_8822b(struct halmac_adapter *adapter, u8 *buf, u32 *rqd_pg_num,
+		       u16 **cur_fs, u8 *macid_cnt, u32 tx_agg_num);
+
+/**
+ * mac_pwr_switch_sdio_8822b() - switch mac power
+ * @adapter : the adapter of halmac
+ * @pwr : power state
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mac_pwr_switch_sdio_8822b(struct halmac_adapter *adapter,
+			  enum halmac_mac_power pwr)
+{
+	u8 value8;
+	u8 rpwm;
+	u32 imr_backup;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+	PLTFM_MSG_TRACE("[TRACE]8822B pwr seq ver = %s\n",
+			HALMAC_8822B_PWR_SEQ_VER);
+
+	adapter->rpwm = HALMAC_REG_R8(REG_SDIO_HRPWM1);
+
+	/* Check FW still exist or not */
+	if (HALMAC_REG_R16(REG_MCUFW_CTRL) == 0xC078) {
+		/* Leave 32K */
+		rpwm = (u8)((adapter->rpwm ^ BIT(7)) & 0x80);
+		HALMAC_REG_W8(REG_SDIO_HRPWM1, rpwm);
+	}
+
+	value8 = HALMAC_REG_R8(REG_CR);
+	if (value8 == 0xEA)
+		adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
+	else
+		adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
+
+	/*Check if power switch is needed*/
+	if (pwr == HALMAC_MAC_POWER_ON &&
+	    adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_ON) {
+		PLTFM_MSG_WARN("[WARN]power state unchange!!\n");
+		return HALMAC_RET_PWR_UNCHANGE;
+	}
+
+	imr_backup = HALMAC_REG_R32(REG_SDIO_HIMR);
+	HALMAC_REG_W32(REG_SDIO_HIMR, 0);
+
+	if (pwr == HALMAC_MAC_POWER_OFF) {
+		adapter->pwr_off_flow_flag = 1;
+		if (pwr_seq_parser_88xx(adapter, card_dis_flow_8822b) !=
+		    HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]Handle power off cmd error\n");
+			HALMAC_REG_W32(REG_SDIO_HIMR, imr_backup);
+			return HALMAC_RET_POWER_OFF_FAIL;
+		}
+
+		adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
+		adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
+		adapter->pwr_off_flow_flag = 0;
+		init_adapter_dynamic_param_88xx(adapter);
+	} else {
+		if (pwr_seq_parser_88xx(adapter, card_en_flow_8822b) !=
+		    HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]Handle power on cmd error\n");
+			HALMAC_REG_W32(REG_SDIO_HIMR, imr_backup);
+			return HALMAC_RET_POWER_ON_FAIL;
+		}
+
+		adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
+	}
+
+	HALMAC_REG_W32(REG_SDIO_HIMR, imr_backup);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_tx_allowed_sdio_88xx() - check tx status
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size, include txdesc
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+tx_allowed_sdio_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u16 *cur_fs = NULL;
+	u32 cnt;
+	u32 tx_agg_num;
+	u32 rqd_pg_num = 0;
+	u8 macid_cnt = 0;
+	struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (!fs_info->macid_map) {
+		PLTFM_MSG_ERR("[ERR]halmac allocate Macid_map Fail!!\n");
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+
+	PLTFM_MEMSET(fs_info->macid_map, 0x00, fs_info->macid_map_size);
+
+	tx_agg_num = GET_TX_DESC_DMA_TXAGG_NUM(buf);
+	tx_agg_num = (tx_agg_num == 0) ? 1 : tx_agg_num;
+
+	status = chk_rqd_page_num_8822b(adapter, buf, &rqd_pg_num, &cur_fs,
+					&macid_cnt, tx_agg_num);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	cnt = 10;
+	do {
+		if ((u32)(*cur_fs + fs_info->pubq_pg_num) > rqd_pg_num) {
+			status = chk_oqt_8822b(adapter, tx_agg_num, buf,
+					       macid_cnt);
+			if (status != HALMAC_RET_SUCCESS) {
+				PLTFM_MSG_WARN("[WARN]oqt buffer full!!\n");
+				return status;
+			}
+
+			if (*cur_fs >= rqd_pg_num) {
+				*cur_fs -= (u16)rqd_pg_num;
+			} else {
+				fs_info->pubq_pg_num -=
+						(u16)(rqd_pg_num - *cur_fs);
+				*cur_fs = 0;
+			}
+
+			break;
+		}
+
+		update_sdio_free_page_8822b(adapter);
+
+		cnt--;
+		if (cnt == 0)
+			return HALMAC_RET_FREE_SPACE_NOT_ENOUGH;
+	} while (1);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_reg_read_8_sdio_88xx() - read 1byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u8
+reg_r8_sdio_8822b(struct halmac_adapter *adapter, u32 offset)
+{
+	u8 value8;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if ((offset & 0xFFFF0000) == 0) {
+		value8 = (u8)r_indir_sdio_88xx(adapter, offset, HALMAC_IO_BYTE);
+	} else {
+		status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+		if (status != HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]convert offset\n");
+			return status;
+		}
+		value8 = PLTFM_SDIO_CMD52_R(offset);
+	}
+
+	return value8;
+}
+
+/**
+ * halmac_reg_write_8_sdio_88xx() - write 1byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w8_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u8 value)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if ((offset & 0xFFFF0000) == 0)
+		offset |= WLAN_IOREG_OFFSET;
+
+	status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]convert offset\n");
+		return status;
+	}
+
+	PLTFM_SDIO_CMD52_W(offset, value);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_reg_read_16_sdio_88xx() - read 2byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u16
+reg_r16_sdio_8822b(struct halmac_adapter *adapter, u32 offset)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	union {
+		u16 word;
+		u8 byte[2];
+	} value16 = { 0x0000 };
+
+	if ((offset & 0xFFFF0000) == 0)
+		return (u16)r_indir_sdio_88xx(adapter, offset, HALMAC_IO_WORD);
+
+	status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]convert offset\n");
+		return status;
+	}
+
+	if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF ||
+	    ((offset & (2 - 1)) != 0) ||
+	    adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_RW ||
+	    adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_R) {
+		value16.byte[0] = PLTFM_SDIO_CMD52_R(offset);
+		value16.byte[1] = PLTFM_SDIO_CMD52_R(offset + 1);
+		value16.word = rtk_le16_to_cpu(value16.word);
+	} else {
+		value16.word = PLTFM_SDIO_CMD53_R16(offset);
+	}
+
+	return value16.word;
+}
+
+/**
+ * halmac_reg_write_16_sdio_88xx() - write 2byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w16_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u16 value)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF ||
+	    ((offset & (2 - 1)) != 0) ||
+	    adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_RW ||
+	    adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_W) {
+		if ((offset & 0xFFFF0000) == 0 && ((offset & (2 - 1)) == 0)) {
+			status = w_indir_sdio_88xx(adapter, offset, value,
+						   HALMAC_IO_WORD);
+		} else {
+			if ((offset & 0xFFFF0000) == 0)
+				offset |= WLAN_IOREG_OFFSET;
+
+			status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+			if (status != HALMAC_RET_SUCCESS) {
+				PLTFM_MSG_ERR("[ERR]convert offset\n");
+				return status;
+			}
+			PLTFM_SDIO_CMD52_W(offset, (u8)(value & 0xFF));
+			PLTFM_SDIO_CMD52_W(offset + 1,
+					   (u8)((value & 0xFF00) >> 8));
+		}
+	} else {
+		if ((offset & 0xFFFF0000) == 0)
+			offset |= WLAN_IOREG_OFFSET;
+
+		status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+		if (status != HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]convert offset\n");
+			return status;
+		}
+
+		PLTFM_SDIO_CMD53_W16(offset, value);
+	}
+	return status;
+}
+
+/**
+ * halmac_reg_read_32_sdio_88xx() - read 4byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u32
+reg_r32_sdio_8822b(struct halmac_adapter *adapter, u32 offset)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	union {
+		u32 dword;
+		u8 byte[4];
+	} value32 = { 0x00000000 };
+
+	if ((offset & 0xFFFF0000) == 0)
+		return r_indir_sdio_88xx(adapter, offset, HALMAC_IO_DWORD);
+
+	status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]convert offset\n");
+		return status;
+	}
+
+	if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF ||
+	    (offset & (4 - 1)) != 0) {
+		value32.byte[0] = PLTFM_SDIO_CMD52_R(offset);
+		value32.byte[1] = PLTFM_SDIO_CMD52_R(offset + 1);
+		value32.byte[2] = PLTFM_SDIO_CMD52_R(offset + 2);
+		value32.byte[3] = PLTFM_SDIO_CMD52_R(offset + 3);
+		value32.dword = rtk_le32_to_cpu(value32.dword);
+	} else {
+		value32.dword = PLTFM_SDIO_CMD53_R32(offset);
+	}
+
+	return value32.dword;
+}
+
+/**
+ * halmac_reg_write_32_sdio_88xx() - write 4byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w32_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u32 value)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF ||
+	    (offset & (4 - 1)) !=  0) {
+		if ((offset & 0xFFFF0000) == 0 && ((offset & (4 - 1)) == 0)) {
+			status = w_indir_sdio_88xx(adapter, offset, value,
+						   HALMAC_IO_DWORD);
+		} else {
+			if ((offset & 0xFFFF0000) == 0)
+				offset |= WLAN_IOREG_OFFSET;
+
+			status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+			if (status != HALMAC_RET_SUCCESS) {
+				PLTFM_MSG_ERR("[ERR]convert offset\n");
+				return status;
+			}
+			PLTFM_SDIO_CMD52_W(offset, (u8)(value & 0xFF));
+			PLTFM_SDIO_CMD52_W(offset + 1,
+					   (u8)((value >> 8) & 0xFF));
+			PLTFM_SDIO_CMD52_W(offset + 2,
+					   (u8)((value >> 16) & 0xFF));
+			PLTFM_SDIO_CMD52_W(offset + 3,
+					   (u8)((value >> 24) & 0xFF));
+		}
+	} else {
+		if ((offset & 0xFFFF0000) == 0)
+			offset |= WLAN_IOREG_OFFSET;
+
+		status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+		if (status != HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]convert offset\n");
+			return status;
+		}
+		PLTFM_SDIO_CMD53_W32(offset, value);
+	}
+
+	return status;
+}
+
+static enum halmac_ret_status
+chk_oqt_8822b(struct halmac_adapter *adapter, u32 tx_agg_num, u8 *buf,
+	      u8 macid_cnt)
+{
+	u32 cnt = 10;
+	struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
+
+	/*S0, S1 are not allowed to use, 0x4E4[0] should be 0. Soar 20160323*/
+	/*no need to check non_ac_oqt_number*/
+	/*HI and MGQ blocked will cause protocal issue before H_OQT being full*/
+	switch ((enum halmac_qsel)GET_TX_DESC_QSEL(buf)) {
+	case HALMAC_QSEL_VO:
+	case HALMAC_QSEL_VO_V2:
+	case HALMAC_QSEL_VI:
+	case HALMAC_QSEL_VI_V2:
+	case HALMAC_QSEL_BE:
+	case HALMAC_QSEL_BE_V2:
+	case HALMAC_QSEL_BK:
+	case HALMAC_QSEL_BK_V2:
+		if (macid_cnt > WLAN_ACQ_NUM_MAX &&
+		    tx_agg_num > OQT_ENTRY_AC_8822B) {
+			PLTFM_MSG_WARN("[WARN]txagg num %d > oqt entry\n",
+				       tx_agg_num);
+			PLTFM_MSG_WARN("[WARN]macid cnt %d > acq max\n",
+				       macid_cnt);
+		}
+
+		cnt = 10;
+		do {
+			if (fs_info->ac_empty >= macid_cnt) {
+				fs_info->ac_empty -= macid_cnt;
+				break;
+			}
+
+			if (fs_info->ac_oqt_num >= tx_agg_num) {
+				fs_info->ac_empty = 0;
+				fs_info->ac_oqt_num -= (u8)tx_agg_num;
+				break;
+			}
+
+			update_oqt_free_space_8822b(adapter);
+
+			cnt--;
+			if (cnt == 0)
+				return HALMAC_RET_OQT_NOT_ENOUGH;
+		} while (1);
+		break;
+	case HALMAC_QSEL_MGNT:
+	case HALMAC_QSEL_HIGH:
+		if (tx_agg_num > OQT_ENTRY_NOAC_8822B)
+			PLTFM_MSG_WARN("[WARN]tx_agg_num %d > oqt entry\n",
+				       tx_agg_num, OQT_ENTRY_NOAC_8822B);
+
+		cnt = 10;
+		do {
+			if (fs_info->non_ac_oqt_num >= tx_agg_num) {
+				fs_info->non_ac_oqt_num -= (u8)tx_agg_num;
+				break;
+			}
+
+			update_oqt_free_space_8822b(adapter);
+
+			cnt--;
+			if (cnt == 0)
+				return HALMAC_RET_OQT_NOT_ENOUGH;
+		} while (1);
+		break;
+	default:
+		break;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+update_oqt_free_space_8822b(struct halmac_adapter *adapter)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
+	u8 value;
+	u32 oqt_free_page;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	oqt_free_page = HALMAC_REG_R32(REG_SDIO_OQT_FREE_TXPG_V1);
+	fs_info->ac_oqt_num = (u8)BIT_GET_AC_OQT_FREEPG_V1(oqt_free_page);
+	fs_info->non_ac_oqt_num = (u8)BIT_GET_NOAC_OQT_FREEPG_V1(oqt_free_page);
+	fs_info->ac_empty = 0;
+	if (fs_info->ac_oqt_num == OQT_ENTRY_AC_8822B) {
+		value = HALMAC_REG_R8(REG_TXPKT_EMPTY);
+		while (value > 0) {
+			value = value & (value - 1);
+			fs_info->ac_empty++;
+		};
+	} else {
+		PLTFM_MSG_TRACE("[TRACE]free_space->ac_oqt_num %d != %d\n",
+				fs_info->ac_oqt_num, OQT_ENTRY_AC_8822B);
+	}
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+update_sdio_free_page_8822b(struct halmac_adapter *adapter)
+{
+	u32 free_page = 0;
+	u32 free_page2 = 0;
+	u32 free_page3 = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
+	u8 data[12] = {0};
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	HALMAC_REG_SDIO_RN(REG_SDIO_FREE_TXPG, 12, data);
+
+	free_page = rtk_le32_to_cpu(*(u32 *)(data + 0));
+	free_page2 = rtk_le32_to_cpu(*(u32 *)(data + 4));
+	free_page3 = rtk_le32_to_cpu(*(u32 *)(data + 8));
+
+	fs_info->hiq_pg_num = (u16)BIT_GET_HIQ_FREEPG_V1(free_page);
+	fs_info->miq_pg_num = (u16)BIT_GET_MID_FREEPG_V1(free_page);
+	fs_info->lowq_pg_num = (u16)BIT_GET_LOW_FREEPG_V1(free_page2);
+	fs_info->pubq_pg_num = (u16)BIT_GET_PUB_FREEPG_V1(free_page2);
+	fs_info->exq_pg_num = (u16)BIT_GET_EXQ_FREEPG_V1(free_page3);
+	fs_info->ac_oqt_num = (u8)BIT_GET_AC_OQT_FREEPG_V1(free_page3);
+	fs_info->non_ac_oqt_num = (u8)BIT_GET_NOAC_OQT_FREEPG_V1(free_page3);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * phy_cfg_sdio_8822b() - phy config
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+phy_cfg_sdio_8822b(struct halmac_adapter *adapter,
+		   enum halmac_intf_phy_platform pltfm)
+{
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_pcie_switch_8821c() - pcie gen1/gen2 switch
+ * @adapter : the adapter of halmac
+ * @cfg : gen1/gen2 selection
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pcie_switch_sdio_8822b(struct halmac_adapter *adapter,
+		       enum halmac_pcie_cfg cfg)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * intf_tun_sdio_8822b() - sdio interface fine tuning
+ * @adapter : the adapter of halmac
+ * Author : Ivan
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+intf_tun_sdio_8822b(struct halmac_adapter *adapter)
+{
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_get_sdio_tx_addr_sdio_88xx() - get CMD53 addr for the TX packet
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size
+ * @cmd53_addr : cmd53 addr value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_sdio_tx_addr_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size,
+		       u32 *cmd53_addr)
+{
+	u32 len_unit4;
+	enum halmac_qsel queue_sel;
+	enum halmac_dma_mapping dma_mapping;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (!buf) {
+		PLTFM_MSG_ERR("[ERR]buf is NULL!!\n");
+		return HALMAC_RET_DATA_BUF_NULL;
+	}
+
+	if (size == 0) {
+		PLTFM_MSG_ERR("[ERR]size is 0!!\n");
+		return HALMAC_RET_DATA_SIZE_INCORRECT;
+	}
+
+	queue_sel = (enum halmac_qsel)GET_TX_DESC_QSEL(buf);
+
+	switch (queue_sel) {
+	case HALMAC_QSEL_VO:
+	case HALMAC_QSEL_VO_V2:
+		dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VO];
+		break;
+	case HALMAC_QSEL_VI:
+	case HALMAC_QSEL_VI_V2:
+		dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VI];
+		break;
+	case HALMAC_QSEL_BE:
+	case HALMAC_QSEL_BE_V2:
+		dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BE];
+		break;
+	case HALMAC_QSEL_BK:
+	case HALMAC_QSEL_BK_V2:
+		dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BK];
+		break;
+	case HALMAC_QSEL_MGNT:
+		dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_MG];
+		break;
+	case HALMAC_QSEL_HIGH:
+	case HALMAC_QSEL_BCN:
+	case HALMAC_QSEL_CMD:
+		dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_HI];
+		break;
+	default:
+		PLTFM_MSG_ERR("[ERR]Qsel is out of range\n");
+		return HALMAC_RET_QSEL_INCORRECT;
+	}
+
+	len_unit4 = (size >> 2) + ((size & (4 - 1)) ? 1 : 0);
+
+	switch (dma_mapping) {
+	case HALMAC_DMA_MAPPING_HIGH:
+		*cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_HIGH;
+		break;
+	case HALMAC_DMA_MAPPING_NORMAL:
+		*cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL;
+		break;
+	case HALMAC_DMA_MAPPING_LOW:
+		*cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_LOW;
+		break;
+	case HALMAC_DMA_MAPPING_EXTRA:
+		*cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA;
+		break;
+	default:
+		PLTFM_MSG_ERR("[ERR]DmaMapping is out of range\n");
+		return HALMAC_RET_DMA_MAP_INCORRECT;
+	}
+
+	*cmd53_addr = (*cmd53_addr << 13) |
+				(len_unit4 & HALMAC_SDIO_4BYTE_LEN_MASK);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+chk_qsel_8822b(struct halmac_adapter *adapter, u8 qsel_first, u8 *pkt,
+	       u8 *macid_cnt)
+{
+	u8 flag = 0;
+	u8 qsel_now;
+	u8 macid;
+	struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
+
+	macid = (u8)GET_TX_DESC_MACID(pkt);
+	qsel_now = (u8)GET_TX_DESC_QSEL(pkt);
+	if (qsel_first == qsel_now) {
+		if (*(fs_info->macid_map + macid) == 0) {
+			*(fs_info->macid_map + macid) = 1;
+			(*macid_cnt)++;
+		}
+	} else {
+		switch ((enum halmac_qsel)qsel_now) {
+		case HALMAC_QSEL_VO:
+			if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VO_V2)
+				flag = 1;
+			break;
+		case HALMAC_QSEL_VO_V2:
+			if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VO)
+				flag = 1;
+			break;
+		case HALMAC_QSEL_VI:
+			if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VI_V2)
+				flag = 1;
+			break;
+		case HALMAC_QSEL_VI_V2:
+			if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VI)
+				flag = 1;
+			break;
+		case HALMAC_QSEL_BE:
+			if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BE_V2)
+				flag = 1;
+			break;
+		case HALMAC_QSEL_BE_V2:
+			if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BE)
+				flag = 1;
+			break;
+		case HALMAC_QSEL_BK:
+			if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BK_V2)
+				flag = 1;
+			break;
+		case HALMAC_QSEL_BK_V2:
+			if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BK)
+				flag = 1;
+			break;
+		case HALMAC_QSEL_MGNT:
+		case HALMAC_QSEL_HIGH:
+		case HALMAC_QSEL_BCN:
+		case HALMAC_QSEL_CMD:
+			flag = 1;
+			break;
+		default:
+			PLTFM_MSG_ERR("[ERR]Qsel is out of range\n");
+			return HALMAC_RET_QSEL_INCORRECT;
+		}
+		if (flag == 1) {
+			PLTFM_MSG_ERR("[ERR]Multi-Qsel is not allowed\n");
+			PLTFM_MSG_ERR("[ERR]qsel = %d, %d\n",
+				      qsel_first, qsel_now);
+			return HALMAC_RET_QSEL_INCORRECT;
+		}
+		if (*(fs_info->macid_map + macid + MACID_MAX_8822B) == 0) {
+			*(fs_info->macid_map + macid + MACID_MAX_8822B) = 1;
+			(*macid_cnt)++;
+		}
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+chk_dma_mapping_8822b(struct halmac_adapter *adapter, u16 **cur_fs,
+		      u8 qsel_first)
+{
+	enum halmac_dma_mapping dma_mapping;
+
+	switch ((enum halmac_qsel)qsel_first) {
+	case HALMAC_QSEL_VO:
+	case HALMAC_QSEL_VO_V2:
+		dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VO];
+		break;
+	case HALMAC_QSEL_VI:
+	case HALMAC_QSEL_VI_V2:
+		dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VI];
+		break;
+	case HALMAC_QSEL_BE:
+	case HALMAC_QSEL_BE_V2:
+		dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BE];
+		break;
+	case HALMAC_QSEL_BK:
+	case HALMAC_QSEL_BK_V2:
+		dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BK];
+		break;
+	case HALMAC_QSEL_MGNT:
+		dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_MG];
+		break;
+	case HALMAC_QSEL_HIGH:
+		dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_HI];
+		break;
+	case HALMAC_QSEL_BCN:
+	case HALMAC_QSEL_CMD:
+		return HALMAC_RET_SUCCESS;
+	default:
+		PLTFM_MSG_ERR("[ERR]Qsel is out of range: %d\n", qsel_first);
+		return HALMAC_RET_QSEL_INCORRECT;
+	}
+
+	switch (dma_mapping) {
+	case HALMAC_DMA_MAPPING_HIGH:
+		*cur_fs = &adapter->sdio_fs.hiq_pg_num;
+		break;
+	case HALMAC_DMA_MAPPING_NORMAL:
+		*cur_fs = &adapter->sdio_fs.miq_pg_num;
+		break;
+	case HALMAC_DMA_MAPPING_LOW:
+		*cur_fs = &adapter->sdio_fs.lowq_pg_num;
+		break;
+	case HALMAC_DMA_MAPPING_EXTRA:
+		*cur_fs = &adapter->sdio_fs.exq_pg_num;
+		break;
+	default:
+		PLTFM_MSG_ERR("[ERR]DmaMapping is out of range\n");
+		return HALMAC_RET_DMA_MAP_INCORRECT;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+chk_rqd_page_num_8822b(struct halmac_adapter *adapter, u8 *buf, u32 *rqd_pg_num,
+		       u16 **cur_fs, u8 *macid_cnt, u32 tx_agg_num)
+{
+	u8 *pkt;
+	u8 qsel_first;
+	u32 i;
+	u32 pkt_size;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	pkt = buf;
+
+	qsel_first = (u8)GET_TX_DESC_QSEL(pkt);
+
+	status = chk_dma_mapping_8822b(adapter, cur_fs, qsel_first);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	for (i = 0; i < tx_agg_num; i++) {
+		/*QSEL parser*/
+		status = chk_qsel_8822b(adapter, qsel_first, pkt, macid_cnt);
+		if (status != HALMAC_RET_SUCCESS)
+			return status;
+
+		/*Page number parser*/
+		pkt_size = GET_TX_DESC_TXPKTSIZE(pkt) + GET_TX_DESC_OFFSET(pkt);
+		*rqd_pg_num += (pkt_size >> TX_PAGE_SIZE_SHIFT_88XX) +
+				((pkt_size & (TX_PAGE_SIZE_88XX - 1)) ? 1 : 0);
+
+		pkt += HALMAC_ALIGN(GET_TX_DESC_TXPKTSIZE(pkt) +
+				    (GET_TX_DESC_PKT_OFFSET(pkt) << 3) +
+				    TX_DESC_SIZE_88XX, 8);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_8822B_SUPPORT*/

hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.h

@@ -0,0 +1,66 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_API_8822B_SDIO_H_
+#define _HALMAC_API_8822B_SDIO_H_
+
+#include "../../halmac_api.h"
+#include "halmac_8822b_cfg.h"
+
+#if HALMAC_8822B_SUPPORT
+
+enum halmac_ret_status
+mac_pwr_switch_sdio_8822b(struct halmac_adapter *adapter,
+			  enum halmac_mac_power pwr);
+
+enum halmac_ret_status
+tx_allowed_sdio_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+u8
+reg_r8_sdio_8822b(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w8_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u8 value);
+
+u16
+reg_r16_sdio_8822b(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w16_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u16 value);
+
+u32
+reg_r32_sdio_8822b(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w32_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u32 value);
+
+enum halmac_ret_status
+phy_cfg_sdio_8822b(struct halmac_adapter *adapter,
+		   enum halmac_intf_phy_platform pltfm);
+
+enum halmac_ret_status
+pcie_switch_sdio_8822b(struct halmac_adapter *adapter,
+		       enum halmac_pcie_cfg cfg);
+
+enum halmac_ret_status
+intf_tun_sdio_8822b(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+get_sdio_tx_addr_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size,
+		       u32 *cmd53_addr);
+
+#endif /* HALMAC_8822B_SUPPORT*/
+
+#endif/* _HALMAC_API_8822B_SDIO_H_ */

hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.c

@@ -0,0 +1,159 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_usb_8822b.h"
+#include "halmac_pwr_seq_8822b.h"
+#include "../halmac_init_88xx.h"
+#include "../halmac_common_88xx.h"
+
+#if HALMAC_8822B_SUPPORT
+
+/**
+ * mac_pwr_switch_usb_8822b() - switch mac power
+ * @adapter : the adapter of halmac
+ * @pwr : power state
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mac_pwr_switch_usb_8822b(struct halmac_adapter *adapter,
+			 enum halmac_mac_power pwr)
+{
+	u8 value8;
+	u8 rpwm;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s\n", __func__);
+	PLTFM_MSG_TRACE("[TRACE]%x\n", pwr);
+	PLTFM_MSG_TRACE("[TRACE]8821C pwr seq ver = %s\n",
+			HALMAC_8822B_PWR_SEQ_VER);
+
+	adapter->rpwm = HALMAC_REG_R8(0xFE58);
+
+	/* Check FW still exist or not */
+	if (HALMAC_REG_R16(REG_MCUFW_CTRL) == 0xC078) {
+		/* Leave 32K */
+		rpwm = (u8)((adapter->rpwm ^ BIT(7)) & 0x80);
+		HALMAC_REG_W8(0xFE58, rpwm);
+	}
+
+	value8 = HALMAC_REG_R8(REG_CR);
+	if (value8 == 0xEA) {
+		adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
+	} else {
+		if (BIT(0) == (HALMAC_REG_R8(REG_SYS_STATUS1 + 1) & BIT(0)))
+			adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
+		else
+			adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
+	}
+
+	/*Check if power switch is needed*/
+	if (pwr == HALMAC_MAC_POWER_ON &&
+	    adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_ON) {
+		PLTFM_MSG_WARN("[WARN]power state unchange!!\n");
+		return HALMAC_RET_PWR_UNCHANGE;
+	}
+
+	if (pwr == HALMAC_MAC_POWER_OFF) {
+		if (pwr_seq_parser_88xx(adapter, card_dis_flow_8822b) !=
+		    HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]Handle power off cmd error\n");
+			return HALMAC_RET_POWER_OFF_FAIL;
+		}
+
+		adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
+		adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
+		init_adapter_dynamic_param_88xx(adapter);
+	} else {
+		if (pwr_seq_parser_88xx(adapter, card_en_flow_8822b) !=
+		    HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]Handle power on cmd error\n");
+			return HALMAC_RET_POWER_ON_FAIL;
+		}
+
+		HALMAC_REG_W8_CLR(REG_SYS_STATUS1 + 1, BIT(0));
+
+		if ((HALMAC_REG_R8(REG_SW_MDIO + 3) & BIT(0)) == BIT(0))
+			PLTFM_MSG_ALWAYS("[ALWAYS]shall R reg twice!!\n");
+
+		adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * phy_cfg_usb_8822b() - phy config
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+phy_cfg_usb_8822b(struct halmac_adapter *adapter,
+		  enum halmac_intf_phy_platform pltfm)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	status = parse_intf_phy_88xx(adapter, usb2_phy_param_8822b, pltfm,
+				     HAL_INTF_PHY_USB2);
+
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	status = parse_intf_phy_88xx(adapter, usb3_phy_8822b, pltfm,
+				     HAL_INTF_PHY_USB3);
+
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_pcie_switch_8822b() - pcie gen1/gen2 switch
+ * @adapter : the adapter of halmac
+ * @cfg : gen1/gen2 selection
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pcie_switch_usb_8822b(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * intf_tun_usb_8822b() - usb interface fine tuning
+ * @adapter : the adapter of halmac
+ * Author : Ivan
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+intf_tun_usb_8822b(struct halmac_adapter *adapter)
+{
+	return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_8822B_SUPPORT*/

hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.h

@@ -0,0 +1,42 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_API_8822B_USB_H_
+#define _HALMAC_API_8822B_USB_H_
+
+#include "../../halmac_api.h"
+
+#if HALMAC_8822B_SUPPORT
+
+extern struct halmac_intf_phy_para usb2_phy_param_8822b[];
+extern struct halmac_intf_phy_para usb3_phy_8822b[];
+
+enum halmac_ret_status
+mac_pwr_switch_usb_8822b(struct halmac_adapter *adapter,
+			 enum halmac_mac_power pwr);
+
+enum halmac_ret_status
+phy_cfg_usb_8822b(struct halmac_adapter *adapter,
+		  enum halmac_intf_phy_platform pltfm);
+
+enum halmac_ret_status
+pcie_switch_usb_8822b(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg);
+
+enum halmac_ret_status
+intf_tun_usb_8822b(struct halmac_adapter *adapter);
+
+#endif /* HALMAC_8822B_SUPPORT*/
+
+#endif/* _HALMAC_API_8822B_USB_H_ */

hal/halmac/halmac_88xx/halmac_88xx_cfg.h

@@ -0,0 +1,44 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_88XX_CFG_H_
+#define _HALMAC_88XX_CFG_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+#define TX_PAGE_SIZE_88XX		128
+#define TX_PAGE_SIZE_SHIFT_88XX		7 /* 128 = 2^7 */
+#define TX_ALIGN_SIZE_88XX		8
+#define SDIO_TX_MAX_SIZE_88XX		31744
+#define RX_BUF_FW_88XX			12288
+
+#define TX_DESC_SIZE_88XX		48
+#define RX_DESC_SIZE_88XX		24
+
+#define H2C_PKT_SIZE_88XX		32 /* Only support 32 byte packet now */
+#define H2C_PKT_HDR_SIZE_88XX		8
+#define C2H_DATA_OFFSET_88XX		10
+#define C2H_PKT_BUF_88XX		256
+
+/* HW memory address */
+#define OCPBASE_TXBUF_88XX		0x18780000
+#define OCPBASE_DMEM_88XX		0x00200000
+#define OCPBASE_EMEM_88XX		0x00100000
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif

hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c

@@ -0,0 +1,392 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_bb_rf_88xx.h"
+#include "halmac_88xx_cfg.h"
+#include "halmac_common_88xx.h"
+#include "halmac_init_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+/**
+ * start_iqk_88xx() -trigger FW IQK
+ * @adapter : the adapter of halmac
+ * @param : IQK parameter
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+start_iqk_88xx(struct halmac_adapter *adapter, struct halmac_iqk_para *param)
+{
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+	u16 seq_num = 0;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	struct halmac_h2c_header_info hdr_info;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.iqk_state.proc_status;
+
+	if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_TRACE("[TRACE]Wait event(iqk)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	*proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+	IQK_SET_CLEAR(h2c_buf, param->clear);
+	IQK_SET_SEGMENT_IQK(h2c_buf, param->segment_iqk);
+
+	hdr_info.sub_cmd_id = SUB_CMD_ID_IQK;
+	hdr_info.content_size = 1;
+	hdr_info.ack = _TRUE;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+	adapter->halmac_state.iqk_state.seq_num = seq_num;
+
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]send h2c pkt fail!!\n");
+		reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_IQK);
+		return status;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * ctrl_pwr_tracking_88xx() -trigger FW power tracking
+ * @adapter : the adapter of halmac
+ * @opt : power tracking option
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+ctrl_pwr_tracking_88xx(struct halmac_adapter *adapter,
+		       struct halmac_pwr_tracking_option *opt)
+{
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+	u16 seq_num = 0;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	struct halmac_h2c_header_info hdr_info;
+	struct halmac_pwr_tracking_para *param;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.pwr_trk_state.proc_status;
+
+	if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_TRACE("[TRACE]Wait event(pwr tracking)...\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	*proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+	PWR_TRK_SET_TYPE(h2c_buf, opt->type);
+	PWR_TRK_SET_BBSWING_INDEX(h2c_buf, opt->bbswing_index);
+
+	param = &opt->pwr_tracking_para[HALMAC_RF_PATH_A];
+	PWR_TRK_SET_ENABLE_A(h2c_buf, param->enable);
+	PWR_TRK_SET_TX_PWR_INDEX_A(h2c_buf, param->tx_pwr_index);
+	PWR_TRK_SET_TSSI_VALUE_A(h2c_buf, param->tssi_value);
+	PWR_TRK_SET_OFFSET_VALUE_A(h2c_buf, param->pwr_tracking_offset_value);
+
+	PWR_TRK_SET_ENABLE_B(h2c_buf, param->enable);
+	PWR_TRK_SET_TX_PWR_INDEX_B(h2c_buf, param->tx_pwr_index);
+	PWR_TRK_SET_TSSI_VALUE_B(h2c_buf, param->tssi_value);
+	PWR_TRK_SET_OFFSET_VALUE_B(h2c_buf, param->pwr_tracking_offset_value);
+
+	PWR_TRK_SET_ENABLE_C(h2c_buf, param->enable);
+	PWR_TRK_SET_TX_PWR_INDEX_C(h2c_buf, param->tx_pwr_index);
+	PWR_TRK_SET_TSSI_VALUE_C(h2c_buf, param->tssi_value);
+	PWR_TRK_SET_OFFSET_VALUE_C(h2c_buf, param->pwr_tracking_offset_value);
+
+	PWR_TRK_SET_ENABLE_D(h2c_buf, param->enable);
+	PWR_TRK_SET_TX_PWR_INDEX_D(h2c_buf, param->tx_pwr_index);
+	PWR_TRK_SET_TSSI_VALUE_D(h2c_buf, param->tssi_value);
+	PWR_TRK_SET_OFFSET_VALUE_D(h2c_buf, param->pwr_tracking_offset_value);
+
+	hdr_info.sub_cmd_id = SUB_CMD_ID_PWR_TRK;
+	hdr_info.content_size = 20;
+	hdr_info.ack = _TRUE;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+	adapter->halmac_state.pwr_trk_state.seq_num = seq_num;
+
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]send h2c pkt fail!!\n");
+		reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_POWER_TRACKING);
+		return status;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_iqk_status_88xx(struct halmac_adapter *adapter,
+		    enum halmac_cmd_process_status *proc_status)
+{
+	*proc_status = adapter->halmac_state.iqk_state.proc_status;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_pwr_trk_status_88xx(struct halmac_adapter *adapter,
+			enum halmac_cmd_process_status *proc_status)
+{
+	*proc_status = adapter->halmac_state.pwr_trk_state.proc_status;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_psd_status_88xx(struct halmac_adapter *adapter,
+		    enum halmac_cmd_process_status *proc_status, u8 *data,
+		    u32 *size)
+{
+	struct halmac_psd_state *state = &adapter->halmac_state.psd_state;
+
+	*proc_status = state->proc_status;
+
+	if (!data)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (!size)
+		return HALMAC_RET_NULL_POINTER;
+
+	if (*proc_status == HALMAC_CMD_PROCESS_DONE) {
+		if (*size < state->data_size) {
+			*size = state->data_size;
+			return HALMAC_RET_BUFFER_TOO_SMALL;
+		}
+
+		*size = state->data_size;
+		PLTFM_MEMCPY(data, state->data, *size);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * psd_88xx() - trigger fw psd
+ * @adapter : the adapter of halmac
+ * @start_psd : start PSD
+ * @end_psd : end PSD
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+psd_88xx(struct halmac_adapter *adapter, u16 start_psd, u16 end_psd)
+{
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+	u16 seq_num = 0;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	struct halmac_h2c_header_info hdr_info;
+	enum halmac_cmd_process_status *proc_status;
+
+	proc_status = &adapter->halmac_state.psd_state.proc_status;
+
+	if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_TRACE("[TRACE]Wait event(psd)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (adapter->halmac_state.psd_state.data) {
+		PLTFM_FREE(adapter->halmac_state.psd_state.data,
+			   adapter->halmac_state.psd_state.data_size);
+		adapter->halmac_state.psd_state.data = (u8 *)NULL;
+	}
+
+	adapter->halmac_state.psd_state.data_size = 0;
+	adapter->halmac_state.psd_state.seg_size = 0;
+
+	*proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+	PSD_SET_START_PSD(h2c_buf, start_psd);
+	PSD_SET_END_PSD(h2c_buf, end_psd);
+
+	hdr_info.sub_cmd_id = SUB_CMD_ID_PSD;
+	hdr_info.content_size = 4;
+	hdr_info.ack = _TRUE;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]send h2c pkt fail!!\n");
+		reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_PSD);
+		return status;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_h2c_ack_iqk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 seq_num;
+	u8 fw_rc;
+	struct halmac_iqk_state *state = &adapter->halmac_state.iqk_state;
+	enum halmac_cmd_process_status proc_status;
+
+	seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
+	PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
+			state->seq_num, seq_num);
+	if (seq_num != state->seq_num) {
+		PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
+			      state->seq_num, seq_num);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+	state->fw_rc = fw_rc;
+
+	if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {
+		proc_status = HALMAC_CMD_PROCESS_DONE;
+		state->proc_status = proc_status;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_IQK, proc_status, NULL, 0);
+	} else {
+		proc_status = HALMAC_CMD_PROCESS_ERROR;
+		state->proc_status = proc_status;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_IQK, proc_status, &fw_rc, 1);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_h2c_ack_pwr_trk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 seq_num;
+	u8 fw_rc;
+	struct halmac_pwr_tracking_state *state;
+	enum halmac_cmd_process_status proc_status;
+
+	state = &adapter->halmac_state.pwr_trk_state;
+
+	seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
+	PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
+			state->seq_num, seq_num);
+	if (seq_num != state->seq_num) {
+		PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
+			      state->seq_num, seq_num);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+	state->fw_rc = fw_rc;
+
+	if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {
+		proc_status = HALMAC_CMD_PROCESS_DONE;
+		state->proc_status = proc_status;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_POWER_TRACKING, proc_status,
+				NULL, 0);
+	} else {
+		proc_status = HALMAC_CMD_PROCESS_ERROR;
+		state->proc_status = proc_status;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_POWER_TRACKING, proc_status,
+				&fw_rc, 1);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_psd_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 seg_id;
+	u8 seg_size;
+	u8 seq_num;
+	u16 total_size;
+	enum halmac_cmd_process_status proc_status;
+	struct halmac_psd_state *state = &adapter->halmac_state.psd_state;
+
+	seq_num = (u8)PSD_DATA_GET_H2C_SEQ(buf);
+	PLTFM_MSG_TRACE("[TRACE]seq num : h2c->%d c2h->%d\n",
+			state->seq_num, seq_num);
+	if (seq_num != state->seq_num) {
+		PLTFM_MSG_ERR("[ERR]seq num mismatch : h2c->%d c2h->%d\n",
+			      state->seq_num, seq_num);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	total_size = (u16)PSD_DATA_GET_TOTAL_SIZE(buf);
+	seg_id = (u8)PSD_DATA_GET_SEGMENT_ID(buf);
+	seg_size = (u8)PSD_DATA_GET_SEGMENT_SIZE(buf);
+	state->data_size = total_size;
+
+	if (!state->data)
+		state->data = (u8 *)PLTFM_MALLOC(state->data_size);
+
+	if (seg_id == 0)
+		state->seg_size = seg_size;
+
+	PLTFM_MEMCPY(state->data + seg_id * state->seg_size,
+		     buf + C2H_DATA_OFFSET_88XX, seg_size);
+
+	if (PSD_DATA_GET_END_SEGMENT(buf) == _FALSE)
+		return HALMAC_RET_SUCCESS;
+
+	proc_status = HALMAC_CMD_PROCESS_DONE;
+	state->proc_status = proc_status;
+
+	PLTFM_EVENT_SIG(HALMAC_FEATURE_PSD, proc_status, state->data,
+			state->data_size);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */

hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h

@@ -0,0 +1,57 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_BB_RF_88XX_H_
+#define _HALMAC_BB_RF_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+start_iqk_88xx(struct halmac_adapter *adapter, struct halmac_iqk_para *param);
+
+enum halmac_ret_status
+ctrl_pwr_tracking_88xx(struct halmac_adapter *adapter,
+		       struct halmac_pwr_tracking_option *opt);
+
+enum halmac_ret_status
+get_iqk_status_88xx(struct halmac_adapter *adapter,
+		    enum halmac_cmd_process_status *proc_status);
+
+enum halmac_ret_status
+get_pwr_trk_status_88xx(struct halmac_adapter *adapter,
+			enum halmac_cmd_process_status *proc_status);
+
+enum halmac_ret_status
+get_psd_status_88xx(struct halmac_adapter *adapter,
+		    enum halmac_cmd_process_status *proc_status, u8 *data,
+		    u32 *size);
+
+enum halmac_ret_status
+psd_88xx(struct halmac_adapter *adapter, u16 start_psd, u16 end_psd);
+
+enum halmac_ret_status
+get_h2c_ack_iqk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+enum halmac_ret_status
+get_h2c_ack_pwr_trk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+enum halmac_ret_status
+get_psd_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_BB_RF_88XX_H_ */

hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h

@@ -0,0 +1,123 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_CFG_WMAC_88XX_H_
+#define _HALMAC_CFG_WMAC_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+cfg_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,
+		  union halmac_wlan_addr *addr);
+
+enum halmac_ret_status
+cfg_bssid_88xx(struct halmac_adapter *adapter, u8 port,
+	       union halmac_wlan_addr *addr);
+
+enum halmac_ret_status
+cfg_transmitter_addr_88xx(struct halmac_adapter *adapter, u8 port,
+			  union halmac_wlan_addr *addr);
+
+enum halmac_ret_status
+cfg_net_type_88xx(struct halmac_adapter *adapter, u8 port,
+		  enum halmac_network_type_select net_type);
+
+enum halmac_ret_status
+cfg_tsf_rst_88xx(struct halmac_adapter *adapter, u8 port);
+
+enum halmac_ret_status
+cfg_bcn_space_88xx(struct halmac_adapter *adapter, u8 port, u32 bcn_space);
+
+enum halmac_ret_status
+rw_bcn_ctrl_88xx(struct halmac_adapter *adapter, u8 port, u8 write_en,
+		 struct halmac_bcn_ctrl *ctrl);
+
+enum halmac_ret_status
+cfg_multicast_addr_88xx(struct halmac_adapter *adapter,
+			union halmac_wlan_addr *addr);
+
+enum halmac_ret_status
+cfg_operation_mode_88xx(struct halmac_adapter *adapter,
+			enum halmac_wireless_mode mode);
+
+enum halmac_ret_status
+cfg_ch_bw_88xx(struct halmac_adapter *adapter, u8 ch,
+	       enum halmac_pri_ch_idx idx, enum halmac_bw bw);
+
+enum halmac_ret_status
+cfg_ch_88xx(struct halmac_adapter *adapter, u8 ch);
+
+enum halmac_ret_status
+cfg_pri_ch_idx_88xx(struct halmac_adapter *adapter, enum halmac_pri_ch_idx idx);
+
+enum halmac_ret_status
+cfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw);
+
+void
+enable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable);
+
+enum halmac_ret_status
+cfg_la_mode_88xx(struct halmac_adapter *adapter, enum halmac_la_mode mode);
+
+enum halmac_ret_status
+cfg_rxfifo_expand_mode_88xx(struct halmac_adapter *adapter,
+			    enum halmac_rx_fifo_expanding_mode mode);
+
+enum halmac_ret_status
+config_security_88xx(struct halmac_adapter *adapter,
+		     struct halmac_security_setting *setting);
+
+u8
+get_used_cam_entry_num_88xx(struct halmac_adapter *adapter,
+			    enum hal_security_type sec_type);
+
+enum halmac_ret_status
+write_cam_88xx(struct halmac_adapter *adapter, u32 idx,
+	       struct halmac_cam_entry_info *info);
+
+enum halmac_ret_status
+read_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx,
+		    struct halmac_cam_entry_format *content);
+
+enum halmac_ret_status
+clear_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx);
+
+void
+rx_shift_88xx(struct halmac_adapter *adapter, u8 enable);
+
+enum halmac_ret_status
+cfg_edca_para_88xx(struct halmac_adapter *adapter, enum halmac_acq_id acq_id,
+		   struct halmac_edca_para *param);
+
+void
+rx_clk_gate_88xx(struct halmac_adapter *adapter, u8 enable);
+
+enum halmac_ret_status
+rx_cut_amsdu_cfg_88xx(struct halmac_adapter *adapter,
+		      struct halmac_cut_amsdu_cfg *cfg);
+
+enum halmac_ret_status
+fast_edca_cfg_88xx(struct halmac_adapter *adapter,
+		   struct halmac_fast_edca_cfg *cfg);
+
+enum halmac_ret_status
+get_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,
+		  union halmac_wlan_addr *addr);
+
+#endif/* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_CFG_WMAC_88XX_H_ */

hal/halmac/halmac_88xx/halmac_common_88xx.h

@@ -0,0 +1,155 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_COMMON_88XX_H_
+#define _HALMAC_COMMON_88XX_H_
+
+#include "../halmac_api.h"
+#include "../halmac_pwr_seq_cmd.h"
+#include "../halmac_gpio_cmd.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+ofld_func_cfg_88xx(struct halmac_adapter *adapter,
+		   struct halmac_ofld_func_info *info);
+
+enum halmac_ret_status
+dl_drv_rsvd_page_88xx(struct halmac_adapter *adapter, u8 pg_offset, u8 *buf,
+		      u32 size);
+
+enum halmac_ret_status
+dl_rsvd_page_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *buf,
+		  u32 size);
+
+enum halmac_ret_status
+get_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
+		  void *value);
+
+enum halmac_ret_status
+set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
+		  void *value);
+
+enum halmac_ret_status
+set_h2c_pkt_hdr_88xx(struct halmac_adapter *adapter, u8 *hdr,
+		     struct halmac_h2c_header_info *info, u16 *seq_num);
+
+enum halmac_ret_status
+send_h2c_pkt_88xx(struct halmac_adapter *adapter, u8 *pkt);
+
+enum halmac_ret_status
+get_h2c_buf_free_space_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+get_c2h_info_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+enum halmac_ret_status
+mac_debug_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+cfg_parameter_88xx(struct halmac_adapter *adapter,
+		   struct halmac_phy_parameter_info *info, u8 full_fifo);
+
+enum halmac_ret_status
+update_packet_88xx(struct halmac_adapter *adapter, enum halmac_packet_id pkt_id,
+		   u8 *pkt, u32 size);
+
+enum halmac_ret_status
+bcn_ie_filter_88xx(struct halmac_adapter *adapter,
+		   struct halmac_bcn_ie_info *info);
+
+enum halmac_ret_status
+update_datapack_88xx(struct halmac_adapter *adapter,
+		     enum halmac_data_type data_type,
+		     struct halmac_phy_parameter_info *info);
+
+enum halmac_ret_status
+run_datapack_88xx(struct halmac_adapter *adapter,
+		  enum halmac_data_type data_type);
+
+enum halmac_ret_status
+send_bt_coex_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, u8 ack);
+
+enum halmac_ret_status
+dump_fifo_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel,
+	       u32 start_addr, u32 size, u8 *data);
+
+u32
+get_fifo_size_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel);
+
+enum halmac_ret_status
+set_h2c_header_88xx(struct halmac_adapter *adapter, u8 *hdr, u16 *seq, u8 ack);
+
+enum halmac_ret_status
+add_ch_info_88xx(struct halmac_adapter *adapter, struct halmac_ch_info *info);
+
+enum halmac_ret_status
+add_extra_ch_info_88xx(struct halmac_adapter *adapter,
+		       struct halmac_ch_extra_info *info);
+
+enum halmac_ret_status
+ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
+		    struct halmac_ch_switch_option *opt);
+
+enum halmac_ret_status
+clear_ch_info_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+chk_txdesc_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+enum halmac_ret_status
+get_version_88xx(struct halmac_adapter *adapter, struct halmac_ver *ver);
+
+enum halmac_ret_status
+p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info);
+
+enum halmac_ret_status
+query_status_88xx(struct halmac_adapter *adapter,
+		  enum halmac_feature_id feature_id,
+		  enum halmac_cmd_process_status *proc_status, u8 *data,
+		  u32 *size);
+
+enum halmac_ret_status
+cfg_drv_rsvd_pg_num_88xx(struct halmac_adapter *adapter,
+			 enum halmac_drv_rsvd_pg_num pg_num);
+
+enum halmac_ret_status
+h2c_lb_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+pwr_seq_parser_88xx(struct halmac_adapter *adapter,
+		    struct halmac_wlan_pwr_cfg **cmd_seq);
+
+enum halmac_ret_status
+parse_intf_phy_88xx(struct halmac_adapter *adapter,
+		    struct halmac_intf_phy_para *param,
+		    enum halmac_intf_phy_platform pltfm,
+		    enum hal_intf_phy intf_phy);
+
+enum halmac_ret_status
+txfifo_is_empty_88xx(struct halmac_adapter *adapter, u32 chk_num);
+
+u8*
+smart_malloc_88xx(struct halmac_adapter *adapter, u32 size, u32 *new_size);
+
+enum halmac_ret_status
+ltecoex_reg_read_88xx(struct halmac_adapter *adapter, u16 offset, u32 *value);
+
+enum halmac_ret_status
+ltecoex_reg_write_88xx(struct halmac_adapter *adapter, u16 offset, u32 value);
+
+#endif/* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_COMMON_88XX_H_ */

hal/halmac/halmac_88xx/halmac_efuse_88xx.h

@@ -0,0 +1,105 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_EFUSE_88XX_H_
+#define _HALMAC_EFUSE_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+dump_efuse_map_88xx(struct halmac_adapter *adapter,
+		    enum halmac_efuse_read_cfg cfg);
+
+enum halmac_ret_status
+dump_efuse_map_bt_88xx(struct halmac_adapter *adapter,
+		       enum halmac_efuse_bank bank, u32 size, u8 *map);
+
+enum halmac_ret_status
+write_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 value,
+		    enum halmac_efuse_bank bank);
+
+enum halmac_ret_status
+read_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value,
+		   enum halmac_efuse_bank bank);
+
+enum halmac_ret_status
+cfg_efuse_auto_check_88xx(struct halmac_adapter *adapter, u8 enable);
+
+enum halmac_ret_status
+get_efuse_available_size_88xx(struct halmac_adapter *adapter, u32 *size);
+
+enum halmac_ret_status
+get_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size);
+
+enum halmac_ret_status
+get_log_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size);
+
+enum halmac_ret_status
+dump_log_efuse_map_88xx(struct halmac_adapter *adapter,
+			enum halmac_efuse_read_cfg cfg);
+
+enum halmac_ret_status
+read_logical_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value);
+
+enum halmac_ret_status
+write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
+
+enum halmac_ret_status
+pg_efuse_by_map_88xx(struct halmac_adapter *adapter,
+		     struct halmac_pg_efuse_info *info,
+		     enum halmac_efuse_read_cfg cfg);
+
+enum halmac_ret_status
+mask_log_efuse_88xx(struct halmac_adapter *adapter,
+		    struct halmac_pg_efuse_info *info);
+
+enum halmac_ret_status
+read_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, u8 *map);
+
+enum halmac_ret_status
+write_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
+
+enum halmac_ret_status
+switch_efuse_bank_88xx(struct halmac_adapter *adapter,
+		       enum halmac_efuse_bank bank);
+
+enum halmac_ret_status
+get_efuse_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+enum halmac_ret_status
+cnv_efuse_state_88xx(struct halmac_adapter *adapter,
+		     enum halmac_cmd_construct_state dest_state);
+
+enum halmac_ret_status
+get_dump_phy_efuse_status_88xx(struct halmac_adapter *adapter,
+			       enum halmac_cmd_process_status *proc_status,
+			       u8 *data, u32 *size);
+
+enum halmac_ret_status
+get_dump_log_efuse_status_88xx(struct halmac_adapter *adapter,
+			       enum halmac_cmd_process_status *proc_status,
+			       u8 *data, u32 *size);
+
+enum halmac_ret_status
+get_h2c_ack_phy_efuse_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+u32
+get_rsvd_efuse_size_88xx(struct halmac_adapter *adapter);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_EFUSE_88XX_H_ */

hal/halmac/halmac_88xx/halmac_flash_88xx.c

@@ -0,0 +1,316 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_flash_88xx.h"
+#include "halmac_88xx_cfg.h"
+#include "halmac_common_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+/**
+ * download_flash_88xx() -download firmware to flash
+ * @adapter : the adapter of halmac
+ * @fw_bin : pointer to fw
+ * @size : fw size
+ * @rom_addr : flash start address where fw should be download
+ * Author : Pablo Chiu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
+		    u32 rom_addr)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_ret_status rc;
+	struct halmac_h2c_header_info hdr_info;
+	u8 value8;
+	u8 restore[3];
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = {0};
+	u16 seq_num = 0;
+	u16 h2c_info_offset;
+	u32 pkt_size;
+	u32 mem_offset;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	value8 = HALMAC_REG_R8(REG_CR + 1);
+	restore[0] = value8;
+	value8 = (u8)(value8 | BIT(0));
+	HALMAC_REG_W8(REG_CR + 1, value8);
+
+	value8 = HALMAC_REG_R8(REG_BCN_CTRL);
+	restore[1] = value8;
+	value8 = (u8)((value8 & ~(BIT(3))) | BIT(4));
+	HALMAC_REG_W8(REG_BCN_CTRL, value8);
+
+	value8 = HALMAC_REG_R8(REG_FWHW_TXQ_CTRL + 2);
+	restore[2] = value8;
+	value8 = (u8)(value8 & ~(BIT(6)));
+	HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8);
+
+	/* Download FW to Flash flow */
+	h2c_info_offset = adapter->txff_alloc.rsvd_h2c_info_addr -
+					adapter->txff_alloc.rsvd_boundary;
+	mem_offset = 0;
+
+	while (size != 0) {
+		if (size >= (DL_FLASH_RSVDPG_SIZE - 48))
+			pkt_size = DL_FLASH_RSVDPG_SIZE - 48;
+		else
+			pkt_size = size;
+
+		rc = dl_rsvd_page_88xx(adapter,
+				       adapter->txff_alloc.rsvd_h2c_info_addr,
+				       fw_bin + mem_offset, pkt_size);
+		if (rc != HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n");
+			return rc;
+		}
+
+		DOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, 0x02);
+		DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, h2c_info_offset);
+		DOWNLOAD_FLASH_SET_SIZE(h2c_buf, pkt_size);
+		DOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, rom_addr);
+
+		hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH;
+		hdr_info.content_size = 20;
+		hdr_info.ack = _TRUE;
+		set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+		rc = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+		if (rc != HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+			return rc;
+		}
+
+		value8 = HALMAC_REG_R8(REG_MCUTST_I);
+		value8 |= BIT(0);
+		HALMAC_REG_W8(REG_MCUTST_I, value8);
+
+		rom_addr += pkt_size;
+		mem_offset += pkt_size;
+		size -= pkt_size;
+
+		while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0)
+			PLTFM_DELAY_US(1000);
+
+		if (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0) {
+			PLTFM_MSG_ERR("[ERR]dl flash!!\n");
+			return  HALMAC_RET_DLFW_FAIL;
+		}
+	}
+
+	HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, restore[2]);
+	HALMAC_REG_W8(REG_BCN_CTRL, restore[1]);
+	HALMAC_REG_W8(REG_CR + 1, restore[0]);
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * read_flash_88xx() -read data from flash
+ * @adapter : the adapter of halmac
+ * @addr : flash start address where fw should be read
+ * Author : Pablo Chiu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+read_flash_88xx(struct halmac_adapter *adapter, u32 addr)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_ret_status status;
+	struct halmac_h2c_header_info hdr_info;
+	u8 value8;
+	u8 restore[3];
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = {0};
+	u16 seq_num = 0;
+	u16 h2c_info_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
+	u16 rsvd_pg_addr = adapter->txff_alloc.rsvd_boundary;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	value8 = HALMAC_REG_R8(REG_CR + 1);
+	restore[0] = value8;
+	value8 = (u8)(value8 | BIT(0));
+	HALMAC_REG_W8(REG_CR + 1, value8);
+
+	value8 = HALMAC_REG_R8(REG_BCN_CTRL);
+	restore[1] = value8;
+	value8 = (u8)((value8 & ~(BIT(3))) | BIT(4));
+	HALMAC_REG_W8(REG_BCN_CTRL, value8);
+
+	value8 = HALMAC_REG_R8(REG_FWHW_TXQ_CTRL + 2);
+	restore[2] = value8;
+	value8 = (u8)(value8 & ~(BIT(6)));
+	HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8);
+
+	HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, h2c_info_addr);
+	value8 = HALMAC_REG_R8(REG_MCUTST_I);
+	value8 |= BIT(0);
+	HALMAC_REG_W8(REG_MCUTST_I, value8);
+
+	/* Construct H2C Content */
+	DOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, 0x03);
+	DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, h2c_info_addr - rsvd_pg_addr);
+	DOWNLOAD_FLASH_SET_SIZE(h2c_buf, 4096);
+	DOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, addr);
+
+	/* Fill in H2C Header */
+	hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH;
+	hdr_info.content_size = 16;
+	hdr_info.ack = _TRUE;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+	/* Send H2C Cmd Packet */
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+		return status;
+	}
+
+	while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0)
+		PLTFM_DELAY_US(1000);
+
+	HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, rsvd_pg_addr);
+	HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, restore[2]);
+	HALMAC_REG_W8(REG_BCN_CTRL, restore[1]);
+	HALMAC_REG_W8(REG_CR + 1, restore[0]);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * erase_flash_88xx() -erase flash data
+ * @adapter : the adapter of halmac
+ * @erase_cmd : erase command
+ * @addr : flash start address where fw should be erased
+ * Author : Pablo Chiu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+erase_flash_88xx(struct halmac_adapter *adapter, u8 erase_cmd, u32 addr)
+{
+	enum halmac_ret_status status;
+	struct halmac_h2c_header_info hdr_info;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	u8 value8;
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = {0};
+	u16 seq_num = 0;
+	u32 cnt;
+
+	/* Construct H2C Content */
+	DOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, erase_cmd);
+	DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, 0);
+	DOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, addr);
+	DOWNLOAD_FLASH_SET_SIZE(h2c_buf, 0);
+
+	value8 = HALMAC_REG_R8(REG_MCUTST_I);
+	value8 |= BIT(0);
+	HALMAC_REG_W8(REG_MCUTST_I, value8);
+
+	/* Fill in H2C Header */
+	hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH;
+	hdr_info.content_size = 16;
+	hdr_info.ack = _TRUE;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+	/* Send H2C Cmd Packet */
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+	if (status != HALMAC_RET_SUCCESS)
+		PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+
+	cnt = 5000;
+	while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0 && cnt != 0) {
+		PLTFM_DELAY_US(1000);
+		cnt--;
+	}
+
+	if (cnt == 0)
+		return HALMAC_RET_FAIL;
+	else
+		return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * check_flash_88xx() -check flash data
+ * @adapter : the adapter of halmac
+ * @fw_bin : pointer to fw
+ * @size : fw size
+ * @addr : flash start address where fw should be checked
+ * Author : Pablo Chiu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+check_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
+		 u32 addr)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	u8 value8;
+	u16 i;
+	u16 residue;
+	u16 pg_addr;
+	u32 pkt_size;
+	u32 start_page;
+	u32 cnt;
+
+	pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
+
+	while (size != 0) {
+		start_page = ((pg_addr << 7) >> 12) + 0x780;
+		residue = (pg_addr << 7) & (4096 - 1);
+
+		if (size >= DL_FLASH_RSVDPG_SIZE)
+			pkt_size = DL_FLASH_RSVDPG_SIZE;
+		else
+			pkt_size = size;
+
+		read_flash_88xx(adapter, addr);
+
+		cnt = 0;
+		while (cnt < pkt_size) {
+			HALMAC_REG_W16(REG_PKTBUF_DBG_CTRL, (u16)(start_page));
+			for (i = 0x8000 + residue; i <= 0x8FFF; i++) {
+				value8 = HALMAC_REG_R8(i);
+				if (*fw_bin != value8) {
+					PLTFM_MSG_ERR("[ERR]check flash!!\n");
+					return HALMAC_RET_FAIL;
+				}
+
+				fw_bin++;
+				cnt++;
+				if (cnt == pkt_size)
+					break;
+			}
+			residue = 0;
+			start_page++;
+		}
+		addr += pkt_size;
+		size -= pkt_size;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */

hal/halmac/halmac_88xx/halmac_flash_88xx.h

@@ -0,0 +1,39 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_FLASH_88XX_H_
+#define _HALMAC_FLASH_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
+		    u32 rom_addr);
+
+enum halmac_ret_status
+read_flash_88xx(struct halmac_adapter *adapter, u32 addr);
+
+enum halmac_ret_status
+erase_flash_88xx(struct halmac_adapter *adapter, u8 erase_cmd, u32 addr);
+
+enum halmac_ret_status
+check_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
+		 u32 addr);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_FLASH_88XX_H_ */

hal/halmac/halmac_88xx/halmac_fw_88xx.h

@@ -0,0 +1,61 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_FW_88XX_H_
+#define _HALMAC_FW_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+#define HALMC_DDMA_POLLING_COUNT		1000
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+enum halmac_ret_status
+download_firmware_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size);
+
+enum halmac_ret_status
+free_download_firmware_88xx(struct halmac_adapter *adapter,
+			    enum halmac_dlfw_mem mem_sel, u8 *fw_bin, u32 size);
+
+enum halmac_ret_status
+get_fw_version_88xx(struct halmac_adapter *adapter,
+		    struct halmac_fw_version *ver);
+
+enum halmac_ret_status
+check_fw_status_88xx(struct halmac_adapter *adapter, u8 *fw_status);
+
+enum halmac_ret_status
+dump_fw_dmem_88xx(struct halmac_adapter *adapter, u8 *dmem, u32 *size);
+
+enum halmac_ret_status
+cfg_max_dl_size_88xx(struct halmac_adapter *adapter, u32 size);
+
+enum halmac_ret_status
+enter_cpu_sleep_mode_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+get_cpu_mode_88xx(struct halmac_adapter *adapter,
+		  enum halmac_wlcpu_mode *mode);
+
+enum halmac_ret_status
+send_general_info_88xx(struct halmac_adapter *adapter,
+		       struct halmac_general_info *info);
+
+enum halmac_ret_status
+drv_fwctrl_88xx(struct halmac_adapter *adapter, u8 *payload, u32 size, u8 ack);
+
+#endif/* _HALMAC_FW_88XX_H_ */

hal/halmac/halmac_88xx/halmac_gpio_88xx.c

@@ -0,0 +1,411 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_gpio_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+/**
+ * pinmux_wl_led_mode_88xx() -control wlan led gpio function
+ * @adapter : the adapter of halmac
+ * @mode : wlan led mode
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_wl_led_mode_88xx(struct halmac_adapter *adapter,
+			enum halmac_wlled_mode mode)
+{
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	value8 = HALMAC_REG_R8(REG_LED_CFG + 2);
+	value8 &= ~(BIT(6));
+	value8 |= BIT(3);
+	value8 &= ~(BIT(0) | BIT(1) | BIT(2));
+
+	switch (mode) {
+	case HALMAC_WLLED_MODE_TRX:
+		value8 |= 2;
+		break;
+	case HALMAC_WLLED_MODE_TX:
+		value8 |= 4;
+		break;
+	case HALMAC_WLLED_MODE_RX:
+		value8 |= 6;
+		break;
+	case HALMAC_WLLED_MODE_SW_CTRL:
+		value8 |= 0;
+		break;
+	default:
+		return HALMAC_RET_SWITCH_CASE_ERROR;
+	}
+
+	HALMAC_REG_W8(REG_LED_CFG + 2, value8);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pinmux_wl_led_sw_ctrl_88xx() -control wlan led on/off
+ * @adapter : the adapter of halmac
+ * @on : on(1), off(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+void
+pinmux_wl_led_sw_ctrl_88xx(struct halmac_adapter *adapter, u8 on)
+{
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	value8 = HALMAC_REG_R8(REG_LED_CFG + 2);
+	value8 = (on == 0) ? value8 | BIT(3) : value8 & ~(BIT(3));
+
+	HALMAC_REG_W8(REG_LED_CFG + 2, value8);
+}
+
+/**
+ * pinmux_sdio_int_polarity_88xx() -control sdio int polarity
+ * @adapter : the adapter of halmac
+ * @low_active : low active(1), high active(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+void
+pinmux_sdio_int_polarity_88xx(struct halmac_adapter *adapter, u8 low_active)
+{
+	u8 value8;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	value8 = HALMAC_REG_R8(REG_SYS_SDIO_CTRL + 2);
+	value8 = (low_active == 0) ? value8 | BIT(3) : value8 & ~(BIT(3));
+
+	HALMAC_REG_W8(REG_SYS_SDIO_CTRL + 2, value8);
+}
+
+/**
+ * pinmux_gpio_mode_88xx() -control gpio io mode
+ * @adapter : the adapter of halmac
+ * @gpio_id : gpio0~15(0~15)
+ * @output : output(1), input(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_gpio_mode_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 output)
+{
+	u16 value16;
+	u8 in_out;
+	u32 offset;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (gpio_id <= 7)
+		offset = REG_GPIO_PIN_CTRL + 2;
+	else if (gpio_id >= 8 && gpio_id <= 15)
+		offset = REG_GPIO_EXT_CTRL + 2;
+	else
+		return HALMAC_RET_WRONG_GPIO;
+
+	in_out = (output == 0) ? 0 : 1;
+	gpio_id &= (8 - 1);
+
+	value16 = HALMAC_REG_R16(offset);
+	value16 &= ~((1 << gpio_id) | (1 << gpio_id << 8));
+	value16 |= (in_out << gpio_id);
+	HALMAC_REG_W16(offset, value16);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pinmux_gpio_output_88xx() -control gpio output high/low
+ * @adapter : the adapter of halmac
+ * @gpio_id : gpio0~15(0~15)
+ * @high : high(1), low(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_gpio_output_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 high)
+{
+	u8 value8;
+	u8 hi_low;
+	u32 offset;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (gpio_id <= 7)
+		offset = REG_GPIO_PIN_CTRL + 1;
+	else if (gpio_id >= 8 && gpio_id <= 15)
+		offset = REG_GPIO_EXT_CTRL + 1;
+	else
+		return HALMAC_RET_WRONG_GPIO;
+
+	hi_low = (high == 0) ? 0 : 1;
+	gpio_id &= (8 - 1);
+
+	value8 = HALMAC_REG_R8(offset);
+	value8 &= ~(1 << gpio_id);
+	value8 |= (hi_low << gpio_id);
+	HALMAC_REG_W8(offset, value8);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_pinmux_status_88xx() -get current gpio status(high/low)
+ * @adapter : the adapter of halmac
+ * @pin_id : 0~15(0~15)
+ * @phigh : high(1), low(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_pin_status_88xx(struct halmac_adapter *adapter, u8 pin_id, u8 *high)
+{
+	u8 value8;
+	u32 offset;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (pin_id <= 7)
+		offset = REG_GPIO_PIN_CTRL;
+	else if (pin_id >= 8 && pin_id <= 15)
+		offset = REG_GPIO_EXT_CTRL;
+	else
+		return HALMAC_RET_WRONG_GPIO;
+
+	pin_id &= (8 - 1);
+
+	value8 = HALMAC_REG_R8(offset);
+	*high = (value8 & (1 << pin_id)) >> pin_id;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+pinmux_parser_88xx(struct halmac_adapter *adapter,
+		   const struct halmac_gpio_pimux_list *list, u32 size,
+		   u32 gpio_id, u32 *cur_func)
+{
+	u32 i;
+	u8 value8;
+	const struct halmac_gpio_pimux_list *cur_list = list;
+	enum halmac_gpio_cfg_state *state;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	state = &adapter->halmac_state.gpio_cfg_state;
+
+	if (*state == HALMAC_GPIO_CFG_STATE_BUSY)
+		return HALMAC_RET_BUSY_STATE;
+
+	*state = HALMAC_GPIO_CFG_STATE_BUSY;
+
+	for (i = 0; i < size; i++) {
+		if (gpio_id != cur_list->id) {
+			PLTFM_MSG_ERR("[ERR]offset:%X, value:%X, func:%X\n",
+				      cur_list->offset, cur_list->value,
+				      cur_list->func);
+			PLTFM_MSG_ERR("[ERR]id1 : %X, id2 : %X\n",
+				      gpio_id, cur_list->id);
+			*state = HALMAC_GPIO_CFG_STATE_IDLE;
+			return HALMAC_RET_GET_PINMUX_ERR;
+		}
+		value8 = HALMAC_REG_R8(cur_list->offset);
+		value8 &= cur_list->msk;
+		if (value8 == cur_list->value) {
+			*cur_func = cur_list->func;
+			break;
+		}
+		cur_list++;
+	}
+
+	*state = HALMAC_GPIO_CFG_STATE_IDLE;
+
+	if (i == size)
+		return HALMAC_RET_GET_PINMUX_ERR;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+pinmux_switch_88xx(struct halmac_adapter *adapter,
+		   const struct halmac_gpio_pimux_list *list, u32 size,
+		   u32 gpio_id, enum halmac_gpio_func gpio_func)
+{
+	u32 i;
+	u8 value8;
+	u16 switch_func;
+	const struct halmac_gpio_pimux_list *cur_list = list;
+	enum halmac_gpio_cfg_state *state;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	state = &adapter->halmac_state.gpio_cfg_state;
+
+	if (*state == HALMAC_GPIO_CFG_STATE_BUSY)
+		return HALMAC_RET_BUSY_STATE;
+
+	switch (gpio_func) {
+	case HALMAC_GPIO_FUNC_WL_LED:
+		switch_func = HALMAC_WL_LED;
+		break;
+	case HALMAC_GPIO_FUNC_SDIO_INT:
+		switch_func = HALMAC_SDIO_INT;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_0:
+	case HALMAC_GPIO_FUNC_SW_IO_1:
+	case HALMAC_GPIO_FUNC_SW_IO_2:
+	case HALMAC_GPIO_FUNC_SW_IO_3:
+	case HALMAC_GPIO_FUNC_SW_IO_4:
+	case HALMAC_GPIO_FUNC_SW_IO_5:
+	case HALMAC_GPIO_FUNC_SW_IO_6:
+	case HALMAC_GPIO_FUNC_SW_IO_7:
+	case HALMAC_GPIO_FUNC_SW_IO_8:
+	case HALMAC_GPIO_FUNC_SW_IO_9:
+	case HALMAC_GPIO_FUNC_SW_IO_10:
+	case HALMAC_GPIO_FUNC_SW_IO_11:
+	case HALMAC_GPIO_FUNC_SW_IO_12:
+	case HALMAC_GPIO_FUNC_SW_IO_13:
+	case HALMAC_GPIO_FUNC_SW_IO_14:
+	case HALMAC_GPIO_FUNC_SW_IO_15:
+		switch_func = HALMAC_SW_IO;
+		break;
+	default:
+		return HALMAC_RET_SWITCH_CASE_ERROR;
+	}
+
+	for (i = 0; i < size; i++) {
+		if (gpio_id != cur_list->id) {
+			PLTFM_MSG_ERR("[ERR]offset:%X, value:%X, func:%X\n",
+				      cur_list->offset, cur_list->value,
+				      cur_list->func);
+			PLTFM_MSG_ERR("[ERR]id1 : %X, id2 : %X\n",
+				      gpio_id, cur_list->id);
+			return HALMAC_RET_GET_PINMUX_ERR;
+		}
+
+		if (switch_func == cur_list->func)
+			break;
+
+		cur_list++;
+	}
+
+	if (i == size) {
+		PLTFM_MSG_ERR("[ERR]gpio func error:%X %X\n",
+			      gpio_id, cur_list->id);
+		return HALMAC_RET_GET_PINMUX_ERR;
+	}
+
+	*state = HALMAC_GPIO_CFG_STATE_BUSY;
+
+	cur_list = list;
+	for (i = 0; i < size; i++) {
+		value8 = HALMAC_REG_R8(cur_list->offset);
+		value8 &= ~(cur_list->msk);
+
+		if (switch_func == cur_list->func) {
+			value8 |= (cur_list->value & cur_list->msk);
+			HALMAC_REG_W8(cur_list->offset, value8);
+			break;
+		}
+
+		value8 |= (~cur_list->value & cur_list->msk);
+		HALMAC_REG_W8(cur_list->offset, value8);
+
+		cur_list++;
+	}
+
+	*state = HALMAC_GPIO_CFG_STATE_IDLE;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+pinmux_record_88xx(struct halmac_adapter *adapter,
+		   enum halmac_gpio_func gpio_func, u8 val)
+{
+	switch (gpio_func) {
+	case HALMAC_GPIO_FUNC_WL_LED:
+		adapter->pinmux_info.wl_led = val;
+		break;
+	case HALMAC_GPIO_FUNC_SDIO_INT:
+		adapter->pinmux_info.sdio_int = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_0:
+		adapter->pinmux_info.sw_io_0 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_1:
+		adapter->pinmux_info.sw_io_1 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_2:
+		adapter->pinmux_info.sw_io_2 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_3:
+		adapter->pinmux_info.sw_io_3 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_4:
+		adapter->pinmux_info.sw_io_4 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_5:
+		adapter->pinmux_info.sw_io_5 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_6:
+		adapter->pinmux_info.sw_io_6 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_7:
+		adapter->pinmux_info.sw_io_7 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_8:
+		adapter->pinmux_info.sw_io_8 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_9:
+		adapter->pinmux_info.sw_io_9 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_10:
+		adapter->pinmux_info.sw_io_10 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_11:
+		adapter->pinmux_info.sw_io_11 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_12:
+		adapter->pinmux_info.sw_io_12 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_13:
+		adapter->pinmux_info.sw_io_13 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_14:
+		adapter->pinmux_info.sw_io_14 = val;
+		break;
+	case HALMAC_GPIO_FUNC_SW_IO_15:
+		adapter->pinmux_info.sw_io_15 = val;
+		break;
+	default:
+		return HALMAC_RET_GET_PINMUX_ERR;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
+

hal/halmac/halmac_88xx/halmac_gpio_88xx.h

@@ -0,0 +1,59 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_GPIO_88XX_H_
+#define _HALMAC_GPIO_88XX_H_
+
+#include "../halmac_api.h"
+#include "../halmac_gpio_cmd.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+pinmux_wl_led_mode_88xx(struct halmac_adapter *adapter,
+			enum halmac_wlled_mode mode);
+
+void
+pinmux_wl_led_sw_ctrl_88xx(struct halmac_adapter *adapter, u8 on);
+
+void
+pinmux_sdio_int_polarity_88xx(struct halmac_adapter *adapter, u8 low_active);
+
+enum halmac_ret_status
+pinmux_gpio_mode_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 output);
+
+enum halmac_ret_status
+pinmux_gpio_output_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 high);
+
+enum halmac_ret_status
+pinmux_pin_status_88xx(struct halmac_adapter *adapter, u8 pin_id, u8 *high);
+
+enum halmac_ret_status
+pinmux_parser_88xx(struct halmac_adapter *adapter,
+		   const struct halmac_gpio_pimux_list *list, u32 size,
+		   u32 gpio_id, u32 *cur_func);
+
+enum halmac_ret_status
+pinmux_switch_88xx(struct halmac_adapter *adapter,
+		   const struct halmac_gpio_pimux_list *list, u32 size,
+		   u32 gpio_id, enum halmac_gpio_func gpio_func);
+
+enum halmac_ret_status
+pinmux_record_88xx(struct halmac_adapter *adapter,
+		   enum halmac_gpio_func gpio_func, u8 val);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_GPIO_88XX_H_ */

hal/halmac/halmac_88xx/halmac_init_88xx.h

@@ -0,0 +1,74 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_INIT_88XX_H_
+#define _HALMAC_INIT_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+register_api_88xx(struct halmac_adapter *adapter,
+		  struct halmac_api_registry *registry);
+
+void
+init_adapter_param_88xx(struct halmac_adapter *adapter);
+
+void
+init_adapter_dynamic_param_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+mount_api_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+pre_init_system_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+init_system_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+init_edca_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+init_wmac_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+init_mac_cfg_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode);
+
+enum halmac_ret_status
+reset_ofld_feature_88xx(struct halmac_adapter *adapter,
+			enum halmac_feature_id feature_id);
+
+enum halmac_ret_status
+verify_platform_api_88xx(struct halmac_adapter *adapter);
+
+void
+tx_desc_chksum_88xx(struct halmac_adapter *adapter, u8 enable);
+
+enum halmac_ret_status
+pg_num_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode,
+		   struct halmac_pg_num *tbl);
+
+enum halmac_ret_status
+rqpn_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode,
+		 struct halmac_rqpn *tbl);
+
+void
+init_ofld_feature_state_machine_88xx(struct halmac_adapter *adapter);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_INIT_88XX_H_ */

hal/halmac/halmac_88xx/halmac_mimo_88xx.c

@@ -0,0 +1,876 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_mimo_88xx.h"
+#include "halmac_88xx_cfg.h"
+#include "halmac_common_88xx.h"
+#include "halmac_init_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+#define TXBF_CTRL_CFG	(BIT_R_ENABLE_NDPA | BIT_USE_NDPA_PARAMETER | \
+			 BIT_R_EN_NDPA_INT | BIT_DIS_NDP_BFEN)
+
+static void
+cfg_mu_bfee_88xx(struct halmac_adapter *adapter,
+		 struct halmac_cfg_mumimo_para *param);
+
+static void
+cfg_mu_bfer_88xx(struct halmac_adapter *adapter,
+		 struct halmac_cfg_mumimo_para *param);
+
+static enum halmac_cmd_construct_state
+fw_snding_cmd_cnstr_state_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+cnv_fw_snding_state_88xx(struct halmac_adapter *adapter,
+			 enum halmac_cmd_construct_state dest_state);
+
+static u8
+snding_pkt_chk_88xx(struct halmac_adapter *adapter, u8 *pkt);
+
+/**
+ * cfg_txbf_88xx() - enable/disable specific user's txbf
+ * @adapter : the adapter of halmac
+ * @userid : su bfee userid = 0 or 1 to apply TXBF
+ * @bw : the sounding bandwidth
+ * @txbf_en : 0: disable TXBF, 1: enable TXBF
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_txbf_88xx(struct halmac_adapter *adapter, u8 userid, enum halmac_bw bw,
+	      u8 txbf_en)
+{
+	u16 tmp42c = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (txbf_en) {
+		switch (bw) {
+		case HALMAC_BW_80:
+			tmp42c |= BIT_R_TXBF0_80M;
+		case HALMAC_BW_40:
+			tmp42c |= BIT_R_TXBF0_40M;
+		case HALMAC_BW_20:
+			tmp42c |= BIT_R_TXBF0_20M;
+			break;
+		default:
+			return HALMAC_RET_INVALID_SOUNDING_SETTING;
+		}
+	}
+
+	switch (userid) {
+	case 0:
+		tmp42c |= HALMAC_REG_R16(REG_TXBF_CTRL) &
+			~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+		HALMAC_REG_W16(REG_TXBF_CTRL, tmp42c);
+		break;
+	case 1:
+		tmp42c |= HALMAC_REG_R16(REG_TXBF_CTRL + 2) &
+			~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+		HALMAC_REG_W16(REG_TXBF_CTRL + 2, tmp42c);
+		break;
+	default:
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_mumimo_88xx() -config mumimo
+ * @adapter : the adapter of halmac
+ * @param : parameters to configure MU PPDU Tx/Rx
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_mumimo_88xx(struct halmac_adapter *adapter,
+		struct halmac_cfg_mumimo_para *param)
+{
+	if (param->role == HAL_BFEE)
+		cfg_mu_bfee_88xx(adapter, param);
+	else
+		cfg_mu_bfer_88xx(adapter, param);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static void
+cfg_mu_bfee_88xx(struct halmac_adapter *adapter,
+		 struct halmac_cfg_mumimo_para *param)
+{
+	u8 mu_tbl_sel;
+	u8 tmp14c0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	tmp14c0 = HALMAC_REG_R8(REG_MU_TX_CTL) & ~BIT_MASK_R_MU_TABLE_VALID;
+	HALMAC_REG_W8(REG_MU_TX_CTL, (tmp14c0 | BIT(0) | BIT(1)) & ~(BIT(7)));
+
+	/*config GID valid table and user position table*/
+	mu_tbl_sel = HALMAC_REG_R8(REG_MU_TX_CTL + 1) & 0xF8;
+
+	HALMAC_REG_W8(REG_MU_TX_CTL + 1, mu_tbl_sel);
+	HALMAC_REG_W32(REG_MU_STA_GID_VLD, param->given_gid_tab[0]);
+	HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO, param->given_user_pos[0]);
+	HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO + 4, param->given_user_pos[1]);
+
+	HALMAC_REG_W8(REG_MU_TX_CTL + 1, mu_tbl_sel | 1);
+	HALMAC_REG_W32(REG_MU_STA_GID_VLD, param->given_gid_tab[1]);
+	HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO, param->given_user_pos[2]);
+	HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO + 4, param->given_user_pos[3]);
+}
+
+static void
+cfg_mu_bfer_88xx(struct halmac_adapter *adapter,
+		 struct halmac_cfg_mumimo_para *param)
+{
+	u8 i;
+	u8 idx;
+	u8 id0;
+	u8 id1;
+	u8 gid;
+	u8 mu_tbl_sel;
+	u8 mu_tbl_valid = 0;
+	u32 gid_valid[6] = {0};
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (param->mu_tx_en == _FALSE) {
+		HALMAC_REG_W8(REG_MU_TX_CTL,
+			      HALMAC_REG_R8(REG_MU_TX_CTL) & ~(BIT(7)));
+		return;
+	}
+
+	for (idx = 0; idx < 15; idx++) {
+		if (idx < 5) {
+			/*grouping_bitmap bit0~4, MU_STA0 with MUSTA1~5*/
+			id0 = 0;
+			id1 = (u8)(idx + 1);
+		} else if (idx < 9) {
+			/*grouping_bitmap bit5~8, MU_STA1 with MUSTA2~5*/
+			id0 = 1;
+			id1 = (u8)(idx - 3);
+		} else if (idx < 12) {
+			/*grouping_bitmap bit9~11, MU_STA2 with MUSTA3~5*/
+			id0 = 2;
+			id1 = (u8)(idx - 6);
+		} else if (idx < 14) {
+			/*grouping_bitmap bit12~13, MU_STA3 with MUSTA4~5*/
+			id0 = 3;
+			id1 = (u8)(idx - 8);
+		} else {
+			/*grouping_bitmap bit14, MU_STA4 with MUSTA5*/
+			id0 = 4;
+			id1 = (u8)(idx - 9);
+		}
+		if (param->grouping_bitmap & BIT(idx)) {
+			/*Pair 1*/
+			gid = (idx << 1) + 1;
+			gid_valid[id0] |= (BIT(gid));
+			gid_valid[id1] |= (BIT(gid));
+			/*Pair 2*/
+			gid += 1;
+			gid_valid[id0] |= (BIT(gid));
+			gid_valid[id1] |= (BIT(gid));
+		} else {
+			/*Pair 1*/
+			gid = (idx << 1) + 1;
+			gid_valid[id0] &= ~(BIT(gid));
+			gid_valid[id1] &= ~(BIT(gid));
+			/*Pair 2*/
+			gid += 1;
+			gid_valid[id0] &= ~(BIT(gid));
+			gid_valid[id1] &= ~(BIT(gid));
+		}
+	}
+
+	/*set MU STA GID valid TABLE*/
+	mu_tbl_sel = HALMAC_REG_R8(REG_MU_TX_CTL + 1) & 0xF8;
+	for (idx = 0; idx < 6; idx++) {
+		HALMAC_REG_W8(REG_MU_TX_CTL + 1, idx | mu_tbl_sel);
+		HALMAC_REG_W32(REG_MU_STA_GID_VLD, gid_valid[idx]);
+	}
+
+	/*To validate the sounding successful MU STA and enable MU TX*/
+	for (i = 0; i < 6; i++) {
+		if (param->sounding_sts[i] == _TRUE)
+			mu_tbl_valid |= BIT(i);
+	}
+	HALMAC_REG_W8(REG_MU_TX_CTL, mu_tbl_valid | BIT(7));
+}
+
+/**
+ * cfg_sounding_88xx() - configure general sounding
+ * @adapter : the adapter of halmac
+ * @role : driver's role, BFer or BFee
+ * @rate : set ndpa tx rate if driver is BFer,
+ * or set csi response rate if driver is BFee
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role,
+		  enum halmac_data_rate rate)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	u32 tmp6dc = 0;
+	u8 csi_rsc = 0x1;
+
+	/*use ndpa rx rate to decide csi rate*/
+	tmp6dc = HALMAC_REG_R32(REG_BBPSF_CTRL) | BIT_WMAC_USE_NDPARATE
+							| (csi_rsc << 13);
+
+	switch (role) {
+	case HAL_BFER:
+		HALMAC_REG_W32_SET(REG_TXBF_CTRL, TXBF_CTRL_CFG);
+		HALMAC_REG_W8(REG_NDPA_RATE, rate);
+		HALMAC_REG_W8_CLR(REG_NDPA_OPT_CTRL, BIT(0) | BIT(1));
+		HALMAC_REG_W8(REG_SND_PTCL_CTRL + 1, 0x2 | BIT(7));
+		HALMAC_REG_W8(REG_SND_PTCL_CTRL + 2, 0x2);
+		break;
+	case HAL_BFEE:
+		HALMAC_REG_W8(REG_SND_PTCL_CTRL, 0xDB);
+		HALMAC_REG_W8(REG_SND_PTCL_CTRL + 3, 0x26);
+		HALMAC_REG_W8_CLR(REG_RXFLTMAP1, BIT(4));
+		HALMAC_REG_W8_CLR(REG_RXFLTMAP4, BIT(4));
+		break;
+	default:
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	/*AP mode set tx gid to 63*/
+	/*STA mode set tx gid to 0*/
+	if (BIT_GET_NETYPE0(HALMAC_REG_R32(REG_CR)) == 0x3)
+		HALMAC_REG_W32(REG_BBPSF_CTRL, tmp6dc | BIT(12));
+	else
+		HALMAC_REG_W32(REG_BBPSF_CTRL, tmp6dc & ~(BIT(12)));
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * del_sounding_88xx() - reset general sounding
+ * @adapter : the adapter of halmac
+ * @role : driver's role, BFer or BFee
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+del_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	switch (role) {
+	case HAL_BFER:
+		HALMAC_REG_W8(REG_TXBF_CTRL + 3, 0);
+		break;
+	case HAL_BFEE:
+		HALMAC_REG_W8(REG_SND_PTCL_CTRL, 0);
+		break;
+	default:
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * su_bfee_entry_init_88xx() - config SU beamformee's registers
+ * @adapter : the adapter of halmac
+ * @userid : SU bfee userid = 0 or 1 to be added
+ * @paid : partial AID of this bfee
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+su_bfee_entry_init_88xx(struct halmac_adapter *adapter, u8 userid, u16 paid)
+{
+	u16 tmp42c = 0;
+	u16 tmp168x = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	switch (userid) {
+	case 0:
+		tmp42c = HALMAC_REG_R16(REG_TXBF_CTRL) &
+				~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M |
+				BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+		HALMAC_REG_W16(REG_TXBF_CTRL, tmp42c | paid);
+		HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL, paid);
+		#if HALMAC_8822C_SUPPORT
+		if (adapter->chip_id == HALMAC_CHIP_ID_8822C)
+			HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL, paid | BIT(9));
+		#endif
+		break;
+	case 1:
+		tmp42c = HALMAC_REG_R16(REG_TXBF_CTRL + 2) &
+				~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M |
+				BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+		HALMAC_REG_W16(REG_TXBF_CTRL + 2, tmp42c | paid);
+		HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL + 2, paid | BIT(9));
+		break;
+	case 2:
+		tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE2);
+		tmp168x = BIT_CLEAR_WMAC_MU_BFEE2_AID(tmp168x);
+		tmp168x |= (paid | BIT(9));
+		HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE2, tmp168x);
+		break;
+	case 3:
+		tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE3);
+		tmp168x = BIT_CLEAR_WMAC_MU_BFEE3_AID(tmp168x);
+		tmp168x |= (paid | BIT(9));
+		HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE3, tmp168x);
+		break;
+	case 4:
+		tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE4);
+		tmp168x = BIT_CLEAR_WMAC_MU_BFEE4_AID(tmp168x);
+		tmp168x |= (paid | BIT(9));
+		HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE4, tmp168x);
+		break;
+	case 5:
+		tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE5);
+		tmp168x = BIT_CLEAR_WMAC_MU_BFEE5_AID(tmp168x);
+		tmp168x |= (paid | BIT(9));
+		HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE5, tmp168x);
+		break;
+	default:
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * su_bfee_entry_init_88xx() - config SU beamformer's registers
+ * @adapter : the adapter of halmac
+ * @param : parameters to configure SU BFER entry
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+su_bfer_entry_init_88xx(struct halmac_adapter *adapter,
+			struct halmac_su_bfer_init_para *param)
+{
+	u16 mac_addr_h;
+	u32 mac_addr_l;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	mac_addr_l = rtk_le32_to_cpu(param->bfer_address.addr_l_h.low);
+	mac_addr_h = rtk_le16_to_cpu(param->bfer_address.addr_l_h.high);
+
+	switch (param->userid) {
+	case 0:
+		HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, mac_addr_l);
+		HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 4, mac_addr_h);
+		HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 6, param->paid);
+		HALMAC_REG_W16(REG_TX_CSI_RPT_PARAM_BW20, param->csi_para);
+		break;
+	case 1:
+		HALMAC_REG_W32(REG_ASSOCIATED_BFMER1_INFO, mac_addr_l);
+		HALMAC_REG_W16(REG_ASSOCIATED_BFMER1_INFO + 4, mac_addr_h);
+		HALMAC_REG_W16(REG_ASSOCIATED_BFMER1_INFO + 6, param->paid);
+		HALMAC_REG_W16(REG_TX_CSI_RPT_PARAM_BW20 + 2, param->csi_para);
+		break;
+	default:
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * mu_bfee_entry_init_88xx() - config MU beamformee's registers
+ * @adapter : the adapter of halmac
+ * @param : parameters to configure MU BFEE entry
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mu_bfee_entry_init_88xx(struct halmac_adapter *adapter,
+			struct halmac_mu_bfee_init_para *param)
+{
+	u16 tmp168x = 0;
+	u16 tmp14c0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	tmp168x |= param->paid | BIT(9);
+	HALMAC_REG_W16((0x1680 + param->userid * 2), tmp168x);
+
+	tmp14c0 = HALMAC_REG_R16(REG_MU_TX_CTL) & ~(BIT(8) | BIT(9) | BIT(10));
+	HALMAC_REG_W16(REG_MU_TX_CTL, tmp14c0 | ((param->userid - 2) << 8));
+	HALMAC_REG_W32(REG_MU_STA_GID_VLD, 0);
+	HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO, param->user_position_l);
+	HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO + 4, param->user_position_h);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * mu_bfer_entry_init_88xx() - config MU beamformer's registers
+ * @adapter : the adapter of halmac
+ * @param : parameters to configure MU BFER entry
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mu_bfer_entry_init_88xx(struct halmac_adapter *adapter,
+			struct halmac_mu_bfer_init_para *param)
+{
+	u16 tmp1680 = 0;
+	u16 mac_addr_h;
+	u32 mac_addr_l;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	mac_addr_l = rtk_le32_to_cpu(param->bfer_address.addr_l_h.low);
+	mac_addr_h = rtk_le16_to_cpu(param->bfer_address.addr_l_h.high);
+
+	HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, mac_addr_l);
+	HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 4, mac_addr_h);
+	HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 6, param->paid);
+	HALMAC_REG_W16(REG_TX_CSI_RPT_PARAM_BW20, param->csi_para);
+
+	tmp1680 = HALMAC_REG_R16(0x1680) & 0xC000;
+	tmp1680 |= param->my_aid | (param->csi_length_sel << 12);
+	HALMAC_REG_W16(0x1680, tmp1680);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * su_bfee_entry_del_88xx() - reset SU beamformee's registers
+ * @adapter : the adapter of halmac
+ * @userid : the SU BFee userid to be deleted
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+su_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid)
+{
+	u16 value16;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	switch (userid) {
+	case 0:
+		value16 = HALMAC_REG_R16(REG_TXBF_CTRL);
+		value16 &= ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M |
+					BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+		HALMAC_REG_W16(REG_TXBF_CTRL, value16);
+		HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL, 0);
+		break;
+	case 1:
+		value16 = HALMAC_REG_R16(REG_TXBF_CTRL + 2);
+		value16 &= ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M |
+					BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+		HALMAC_REG_W16(REG_TXBF_CTRL + 2, value16);
+		HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL + 2, 0);
+		break;
+	case 2:
+		HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE2, 0);
+		break;
+	case 3:
+		HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE3, 0);
+		break;
+	case 4:
+		HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE4, 0);
+		break;
+	case 5:
+		HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE5, 0);
+		break;
+	default:
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * su_bfee_entry_del_88xx() - reset SU beamformer's registers
+ * @adapter : the adapter of halmac
+ * @userid : the SU BFer userid to be deleted
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+su_bfer_entry_del_88xx(struct halmac_adapter *adapter, u8 userid)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	switch (userid) {
+	case 0:
+		HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, 0);
+		HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO + 4, 0);
+		break;
+	case 1:
+		HALMAC_REG_W32(REG_ASSOCIATED_BFMER1_INFO, 0);
+		HALMAC_REG_W32(REG_ASSOCIATED_BFMER1_INFO + 4, 0);
+		break;
+	default:
+		return HALMAC_RET_INVALID_SOUNDING_SETTING;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * mu_bfee_entry_del_88xx() - reset MU beamformee's registers
+ * @adapter : the adapter of halmac
+ * @userid : the MU STA userid to be deleted
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mu_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	HALMAC_REG_W16(0x1680 + userid * 2, 0);
+	HALMAC_REG_W8_CLR(REG_MU_TX_CTL, BIT(userid - 2));
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * mu_bfer_entry_del_88xx() -reset MU beamformer's registers
+ * @adapter : the adapter of halmac
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mu_bfer_entry_del_88xx(struct halmac_adapter *adapter)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, 0);
+	HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO + 4, 0);
+	HALMAC_REG_W16(0x1680, 0);
+	HALMAC_REG_W8(REG_MU_TX_CTL, 0);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_csi_rate_88xx() - config CSI frame Tx rate
+ * @adapter : the adapter of halmac
+ * @rssi : rssi in decimal value
+ * @cur_rate : current CSI frame rate
+ * @fixrate_en : enable to fix CSI frame in VHT rate, otherwise legacy OFDM rate
+ * @new_rate : API returns the final CSI frame rate
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_csi_rate_88xx(struct halmac_adapter *adapter, u8 rssi, u8 cur_rate,
+		  u8 fixrate_en, u8 *new_rate)
+{
+	u32 csi_cfg;
+	u16 cur_rrsr;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+#if HALMAC_8821C_SUPPORT
+	if (adapter->chip_id == HALMAC_CHIP_ID_8821C && fixrate_en) {
+		csi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE;
+		HALMAC_REG_W32(REG_BBPSF_CTRL,
+			       csi_cfg | BIT_CSI_FORCE_RATE_EN |
+			       BIT_CSI_RSC(1) |
+			       BIT_WMAC_CSI_RATE(HALMAC_VHT_NSS1_MCS3));
+		*new_rate = HALMAC_VHT_NSS1_MCS3;
+		return HALMAC_RET_SUCCESS;
+	}
+	csi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE &
+							~BIT_CSI_FORCE_RATE_EN;
+#else
+	csi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE;
+#endif
+
+	cur_rrsr = HALMAC_REG_R16(REG_RRSR);
+
+	if (rssi >= 40) {
+		if (cur_rate != HALMAC_OFDM54) {
+			cur_rrsr |= BIT(HALMAC_OFDM54);
+			csi_cfg |= BIT_WMAC_CSI_RATE(HALMAC_OFDM54);
+			HALMAC_REG_W16(REG_RRSR, cur_rrsr);
+			HALMAC_REG_W32(REG_BBPSF_CTRL, csi_cfg);
+		}
+		*new_rate = HALMAC_OFDM54;
+	} else {
+		if (cur_rate != HALMAC_OFDM24) {
+			cur_rrsr &= ~(BIT(HALMAC_OFDM54));
+			csi_cfg |= BIT_WMAC_CSI_RATE(HALMAC_OFDM24);
+			HALMAC_REG_W16(REG_RRSR, cur_rrsr);
+			HALMAC_REG_W32(REG_BBPSF_CTRL, csi_cfg);
+		}
+		*new_rate = HALMAC_OFDM24;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * fw_snding_88xx() - fw sounding control
+ * @adapter : the adapter of halmac
+ * @su_info :
+ *	su0_en : enable/disable fw sounding
+ *	su0_ndpa_pkt : ndpa pkt, shall include txdesc
+ *	su0_pkt_sz : ndpa pkt size, shall include txdesc
+ * @mu_info : currently not in use, input NULL is acceptable
+ * @period : sounding period, unit is 5ms
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+fw_snding_88xx(struct halmac_adapter *adapter,
+	       struct halmac_su_snding_info *su_info,
+	       struct halmac_mu_snding_info *mu_info, u8 period)
+{
+	u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+	u16 seq_num;
+	u16 snding_info_addr;
+	struct halmac_h2c_header_info hdr_info;
+	enum halmac_cmd_process_status *proc_status;
+	enum halmac_ret_status status;
+
+	proc_status = &adapter->halmac_state.fw_snding_state.proc_status;
+
+	if (adapter->chip_id == HALMAC_CHIP_ID_8821C)
+		return HALMAC_RET_NOT_SUPPORT;
+
+	if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_NO_DLFW;
+
+	if (adapter->fw_ver.h2c_version < 9)
+		return HALMAC_RET_FW_NO_SUPPORT;
+
+	if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_TRACE("[TRACE]Wait event(snd)\n");
+		return HALMAC_RET_BUSY_STATE;
+	}
+
+	if (su_info->su0_en == 1) {
+		if (!su_info->su0_ndpa_pkt)
+			return HALMAC_RET_NULL_POINTER;
+
+		if (su_info->su0_pkt_sz > (u32)SU0_SNDING_PKT_RSVDPG_SIZE -
+		    adapter->hw_cfg_info.txdesc_size)
+			return HALMAC_RET_DATA_SIZE_INCORRECT;
+
+		if (!snding_pkt_chk_88xx(adapter, su_info->su0_ndpa_pkt))
+			return HALMAC_RET_TXDESC_SET_FAIL;
+
+		if (fw_snding_cmd_cnstr_state_88xx(adapter) !=
+		    HALMAC_CMD_CNSTR_IDLE) {
+			PLTFM_MSG_ERR("[ERR]Not idle(snd)\n");
+			return HALMAC_RET_ERROR_STATE;
+		}
+
+		snding_info_addr = adapter->txff_alloc.rsvd_h2c_sta_info_addr +
+				   SU0_SNDING_PKT_OFFSET;
+		status = dl_rsvd_page_88xx(adapter, snding_info_addr,
+					   su_info->su0_ndpa_pkt,
+					   su_info->su0_pkt_sz);
+		if (status != HALMAC_RET_SUCCESS) {
+			PLTFM_MSG_ERR("[ERR]dl rsvd page\n");
+			return status;
+		}
+
+		FW_SNDING_SET_SU0(h2c_buf, 1);
+		FW_SNDING_SET_PERIOD(h2c_buf, period);
+		FW_SNDING_SET_NDPA0_HEAD_PG(h2c_buf, snding_info_addr -
+					    adapter->txff_alloc.rsvd_boundary);
+	} else {
+		if (fw_snding_cmd_cnstr_state_88xx(adapter) !=
+		    HALMAC_CMD_CNSTR_BUSY) {
+			PLTFM_MSG_ERR("[ERR]Not snd(snd)\n");
+			return HALMAC_RET_ERROR_STATE;
+		}
+		FW_SNDING_SET_SU0(h2c_buf, 0);
+	}
+
+	*proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+	hdr_info.sub_cmd_id = SUB_CMD_ID_FW_SNDING;
+	hdr_info.content_size = 8;
+	hdr_info.ack = _TRUE;
+	set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+	adapter->halmac_state.fw_snding_state.seq_num = seq_num;
+
+	status = send_h2c_pkt_88xx(adapter, h2c_buf);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]send h2c\n");
+		reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_FW_SNDING);
+		return status;
+	}
+
+	if (cnv_fw_snding_state_88xx(adapter, su_info->su0_en == 1 ?
+				     HALMAC_CMD_CNSTR_BUSY :
+				     HALMAC_CMD_CNSTR_IDLE)
+				     != HALMAC_RET_SUCCESS)
+		return HALMAC_RET_ERROR_STATE;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static u8
+snding_pkt_chk_88xx(struct halmac_adapter *adapter, u8 *pkt)
+{
+	u8 data_rate;
+
+	if (GET_TX_DESC_NDPA(pkt) == 0) {
+		PLTFM_MSG_ERR("[ERR]txdesc ndpa = 0\n");
+		return _FALSE;
+	}
+
+	data_rate = (u8)GET_TX_DESC_DATARATE(pkt);
+	if (!(data_rate >= HALMAC_VHT_NSS2_MCS0 &&
+	      data_rate <= HALMAC_VHT_NSS2_MCS9)) {
+		if (!(data_rate >= HALMAC_MCS8 && data_rate <= HALMAC_MCS15)) {
+			PLTFM_MSG_ERR("[ERR]txdesc rate\n");
+			return _FALSE;
+		}
+	}
+
+	if (GET_TX_DESC_NAVUSEHDR(pkt) == 0) {
+		PLTFM_MSG_ERR("[ERR]txdesc navusehdr = 0\n");
+		return _FALSE;
+	}
+
+	if (GET_TX_DESC_USE_RATE(pkt) == 0) {
+		PLTFM_MSG_ERR("[ERR]txdesc userate = 0\n");
+		return _FALSE;
+	}
+
+	return _TRUE;
+}
+
+static enum halmac_cmd_construct_state
+fw_snding_cmd_cnstr_state_88xx(struct halmac_adapter *adapter)
+{
+	return adapter->halmac_state.fw_snding_state.cmd_cnstr_state;
+}
+
+enum halmac_ret_status
+get_h2c_ack_fw_snding_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	u8 seq_num = 0;
+	u8 fw_rc;
+	struct halmac_fw_snding_state *state;
+	enum halmac_cmd_process_status proc_status;
+
+	state = &adapter->halmac_state.fw_snding_state;
+
+	seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
+	PLTFM_MSG_TRACE("[TRACE]Seq num:h2c->%d c2h->%d\n",
+			state->seq_num, seq_num);
+	if (seq_num != state->seq_num) {
+		PLTFM_MSG_ERR("[ERR]Seq num mismatch:h2c->%d c2h->%d\n",
+			      state->seq_num, seq_num);
+		return HALMAC_RET_SUCCESS;
+	}
+
+	if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+		PLTFM_MSG_ERR("[ERR]not sending(snd)\n");
+		return HALMAC_RET_SUCCESS;
+	}
+
+	fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+	state->fw_rc = fw_rc;
+
+	if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {
+		proc_status = HALMAC_CMD_PROCESS_DONE;
+		state->proc_status = proc_status;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_FW_SNDING, proc_status,
+				NULL, 0);
+	} else {
+		proc_status = HALMAC_CMD_PROCESS_ERROR;
+		state->proc_status = proc_status;
+		PLTFM_EVENT_SIG(HALMAC_FEATURE_FW_SNDING, proc_status,
+				&fw_rc, 1);
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_fw_snding_status_88xx(struct halmac_adapter *adapter,
+			  enum halmac_cmd_process_status *proc_status)
+{
+	*proc_status = adapter->halmac_state.fw_snding_state.proc_status;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+cnv_fw_snding_state_88xx(struct halmac_adapter *adapter,
+			 enum halmac_cmd_construct_state dest_state)
+{
+	struct halmac_fw_snding_state *state;
+
+	state = &adapter->halmac_state.fw_snding_state;
+
+	if (state->cmd_cnstr_state != HALMAC_CMD_CNSTR_IDLE &&
+	    state->cmd_cnstr_state != HALMAC_CMD_CNSTR_BUSY)
+		return HALMAC_RET_ERROR_STATE;
+
+	if (dest_state == HALMAC_CMD_CNSTR_IDLE) {
+		if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_IDLE)
+			return HALMAC_RET_ERROR_STATE;
+	} else if (dest_state == HALMAC_CMD_CNSTR_BUSY) {
+		if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_BUSY)
+			return HALMAC_RET_ERROR_STATE;
+	}
+
+	state->cmd_cnstr_state = dest_state;
+
+	return HALMAC_RET_SUCCESS;
+}
+#endif /* HALMAC_88XX_SUPPORT */

hal/halmac/halmac_88xx/halmac_mimo_88xx.h

@@ -0,0 +1,83 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_MIMO_88XX_H_
+#define _HALMAC_MIMO_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+cfg_txbf_88xx(struct halmac_adapter *adapter, u8 userid, enum halmac_bw bw,
+	      u8 txbf_en);
+
+enum halmac_ret_status
+cfg_mumimo_88xx(struct halmac_adapter *adapter,
+		struct halmac_cfg_mumimo_para *param);
+
+enum halmac_ret_status
+cfg_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role,
+		  enum halmac_data_rate rate);
+
+enum halmac_ret_status
+del_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role);
+
+enum halmac_ret_status
+su_bfee_entry_init_88xx(struct halmac_adapter *adapter, u8 userid, u16 paid);
+
+enum halmac_ret_status
+su_bfer_entry_init_88xx(struct halmac_adapter *adapter,
+			struct halmac_su_bfer_init_para *param);
+
+enum halmac_ret_status
+mu_bfee_entry_init_88xx(struct halmac_adapter *adapter,
+			struct halmac_mu_bfee_init_para *param);
+
+enum halmac_ret_status
+mu_bfer_entry_init_88xx(struct halmac_adapter *adapter,
+			struct halmac_mu_bfer_init_para *param);
+
+enum halmac_ret_status
+su_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid);
+
+enum halmac_ret_status
+su_bfer_entry_del_88xx(struct halmac_adapter *adapter, u8 userid);
+
+enum halmac_ret_status
+mu_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid);
+
+enum halmac_ret_status
+mu_bfer_entry_del_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+cfg_csi_rate_88xx(struct halmac_adapter *adapter, u8 rssi, u8 cur_rate,
+		  u8 fixrate_en, u8 *new_rate);
+
+enum halmac_ret_status
+fw_snding_88xx(struct halmac_adapter *adapter,
+	       struct halmac_su_snding_info *su_info,
+	       struct halmac_mu_snding_info *mu_info, u8 period);
+
+enum halmac_ret_status
+get_h2c_ack_fw_snding_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+enum halmac_ret_status
+get_fw_snding_status_88xx(struct halmac_adapter *adapter,
+			  enum halmac_cmd_process_status *proc_status);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_MIMO_88XX_H_ */

hal/halmac/halmac_88xx/halmac_pcie_88xx.c

@@ -0,0 +1,543 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_pcie_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+/**
+ * init_pcie_cfg_88xx() -  init PCIe
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_pcie_cfg_88xx(struct halmac_adapter *adapter)
+{
+	if (adapter->intf != HALMAC_INTERFACE_PCIE)
+		return HALMAC_RET_WRONG_INTF;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * deinit_pcie_cfg_88xx() - deinit PCIE
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+deinit_pcie_cfg_88xx(struct halmac_adapter *adapter)
+{
+	if (adapter->intf != HALMAC_INTERFACE_PCIE)
+		return HALMAC_RET_WRONG_INTF;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_pcie_rx_agg_88xx() - config rx aggregation
+ * @adapter : the adapter of halmac
+ * @halmac_rx_agg_mode
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_pcie_rx_agg_88xx(struct halmac_adapter *adapter,
+		     struct halmac_rxagg_cfg *cfg)
+{
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * reg_r8_pcie_88xx() - read 1byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u8
+reg_r8_pcie_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+	return PLTFM_REG_R8(offset);
+}
+
+/**
+ * reg_w8_pcie_88xx() - write 1byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w8_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
+{
+	PLTFM_REG_W8(offset, value);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * reg_r16_pcie_88xx() - read 2byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u16
+reg_r16_pcie_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+	return PLTFM_REG_R16(offset);
+}
+
+/**
+ * reg_w16_pcie_88xx() - write 2byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w16_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u16 value)
+{
+	PLTFM_REG_W16(offset, value);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * reg_r32_pcie_88xx() - read 4byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u32
+reg_r32_pcie_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+	return PLTFM_REG_R32(offset);
+}
+
+/**
+ * reg_w32_pcie_88xx() - write 4byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w32_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u32 value)
+{
+	PLTFM_REG_W32(offset, value);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_txagg_pcie_align_88xx() -config sdio bus tx agg alignment
+ * @adapter : the adapter of halmac
+ * @enable : function enable(1)/disable(0)
+ * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
+ * Author : Soar Tu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_txagg_pcie_align_88xx(struct halmac_adapter *adapter, u8 enable,
+			  u16 align_size)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * tx_allowed_pcie_88xx() - check tx status
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size, include txdesc
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+tx_allowed_pcie_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * pcie_indirect_reg_r32_88xx() - read MAC reg by SDIO reg
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u32
+pcie_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+	return 0xFFFFFFFF;
+}
+
+/**
+ * pcie_reg_rn_88xx() - read n byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @size : register value size
+ * @value : register value
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pcie_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+		 u8 *value)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * set_pcie_bulkout_num_88xx() - inform bulk-out num
+ * @adapter : the adapter of halmac
+ * @num : usb bulk-out number
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+set_pcie_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * get_pcie_tx_addr_88xx() - get CMD53 addr for the TX packet
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size
+ * @cmd53_addr : cmd53 addr value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_pcie_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+		      u32 *cmd53_addr)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * get_pcie_bulkout_id_88xx() - get bulk out id for the TX packet
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size
+ * @id : usb bulk-out id
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_pcie_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+			 u8 *id)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+enum halmac_ret_status
+mdio_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed)
+{
+	u8 tmp_u1b = 0;
+	u32 cnt = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	u8 real_addr = 0;
+
+	HALMAC_REG_W16(REG_MDIO_V1, data);
+
+	real_addr = (addr & 0x1F);
+	HALMAC_REG_W8(REG_PCIE_MIX_CFG, real_addr);
+
+	if (speed == HAL_INTF_PHY_PCIE_GEN1) {
+		if (addr < 0x20)
+			HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x00);
+		else
+			HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x01);
+	} else if (speed == HAL_INTF_PHY_PCIE_GEN2) {
+		if (addr < 0x20)
+			HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x02);
+		else
+			HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x03);
+	} else {
+		PLTFM_MSG_ERR("[ERR]Error Speed !\n");
+	}
+
+	HALMAC_REG_W8_SET(REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1);
+
+	tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1;
+	cnt = 20;
+
+	while (tmp_u1b && (cnt != 0)) {
+		PLTFM_DELAY_US(10);
+		tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1;
+		cnt--;
+	}
+
+	if (tmp_u1b) {
+		PLTFM_MSG_ERR("[ERR]MDIO write fail!\n");
+		return HALMAC_RET_FAIL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+u16
+mdio_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed)
+{
+	u16 ret = 0;
+	u8 tmp_u1b = 0;
+	u32 cnt = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	u8 real_addr = 0;
+
+	real_addr = (addr & 0x1F);
+	HALMAC_REG_W8(REG_PCIE_MIX_CFG, real_addr);
+
+	if (speed == HAL_INTF_PHY_PCIE_GEN1) {
+		if (addr < 0x20)
+			HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x00);
+		else
+			HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x01);
+	} else if (speed == HAL_INTF_PHY_PCIE_GEN2) {
+		if (addr < 0x20)
+			HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x02);
+		else
+			HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x03);
+	} else {
+		PLTFM_MSG_ERR("[ERR]Error Speed !\n");
+	}
+
+	HALMAC_REG_W8_SET(REG_PCIE_MIX_CFG, BIT_MDIO_RFLAG_V1);
+
+	tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1;
+	cnt = 20;
+	while (tmp_u1b && (cnt != 0)) {
+		PLTFM_DELAY_US(10);
+		tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1;
+		cnt--;
+	}
+
+	if (tmp_u1b) {
+		ret  = 0xFFFF;
+		PLTFM_MSG_ERR("[ERR]MDIO read fail!\n");
+	} else {
+		ret = HALMAC_REG_R16(REG_MDIO_V1 + 2);
+		PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret);
+	}
+
+	return ret;
+}
+
+enum halmac_ret_status
+dbi_w32_88xx(struct halmac_adapter *adapter, u16 addr, u32 data)
+{
+	u8 tmp_u1b = 0;
+	u32 cnt = 0;
+	u16 write_addr = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	HALMAC_REG_W32(REG_DBI_WDATA_V1, data);
+
+	write_addr = ((addr & 0x0ffc) | (0x000F << 12));
+	HALMAC_REG_W16(REG_DBI_FLAG_V1, write_addr);
+
+	PLTFM_MSG_TRACE("[TRACE]Addr-W = %x\n", write_addr);
+
+	HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x01);
+	tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+
+	cnt = 20;
+	while (tmp_u1b && (cnt != 0)) {
+		PLTFM_DELAY_US(10);
+		tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+		cnt--;
+	}
+
+	if (tmp_u1b) {
+		PLTFM_MSG_ERR("[ERR]DBI write fail!\n");
+		return HALMAC_RET_FAIL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+u32
+dbi_r32_88xx(struct halmac_adapter *adapter, u16 addr)
+{
+	u16 read_addr = addr & 0x0ffc;
+	u8 tmp_u1b = 0;
+	u32 cnt = 0;
+	u32 ret = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	HALMAC_REG_W16(REG_DBI_FLAG_V1, read_addr);
+
+	HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x2);
+	tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+
+	cnt = 20;
+	while (tmp_u1b && (cnt != 0)) {
+		PLTFM_DELAY_US(10);
+		tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+		cnt--;
+	}
+
+	if (tmp_u1b) {
+		ret  = 0xFFFF;
+		PLTFM_MSG_ERR("[ERR]DBI read fail!\n");
+	} else {
+		ret = HALMAC_REG_R32(REG_DBI_RDATA_V1);
+		PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret);
+	}
+
+	return ret;
+}
+
+enum halmac_ret_status
+dbi_w8_88xx(struct halmac_adapter *adapter, u16 addr, u8 data)
+{
+	u8 tmp_u1b = 0;
+	u32 cnt = 0;
+	u16 write_addr = 0;
+	u16 remainder = addr & (4 - 1);
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	HALMAC_REG_W8(REG_DBI_WDATA_V1 + remainder, data);
+
+	write_addr = ((addr & 0x0ffc) | (BIT(0) << (remainder + 12)));
+
+	HALMAC_REG_W16(REG_DBI_FLAG_V1, write_addr);
+
+	PLTFM_MSG_TRACE("[TRACE]Addr-W = %x\n", write_addr);
+
+	HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x01);
+
+	tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+
+	cnt = 20;
+	while (tmp_u1b && (cnt != 0)) {
+		PLTFM_DELAY_US(10);
+		tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+		cnt--;
+	}
+
+	if (tmp_u1b) {
+		PLTFM_MSG_ERR("[ERR]DBI write fail!\n");
+		return HALMAC_RET_FAIL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+u8
+dbi_r8_88xx(struct halmac_adapter *adapter, u16 addr)
+{
+	u16 read_addr = addr & 0x0ffc;
+	u8 tmp_u1b = 0;
+	u32 cnt = 0;
+	u8 ret = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	HALMAC_REG_W16(REG_DBI_FLAG_V1, read_addr);
+	HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x2);
+
+	tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+
+	cnt = 20;
+	while (tmp_u1b && (cnt != 0)) {
+		PLTFM_DELAY_US(10);
+		tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+		cnt--;
+	}
+
+	if (tmp_u1b) {
+		ret  = 0xFF;
+		PLTFM_MSG_ERR("[ERR]DBI read fail!\n");
+	} else {
+		ret = HALMAC_REG_R8(REG_DBI_RDATA_V1 + (addr & (4 - 1)));
+		PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret);
+	}
+
+	return ret;
+}
+
+enum halmac_ret_status
+trxdma_check_idle_88xx(struct halmac_adapter *adapter)
+{
+	u32 cnt = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	/* Stop Tx & Rx DMA */
+	HALMAC_REG_W32_SET(REG_RXPKT_NUM, BIT(18));
+	HALMAC_REG_W16_SET(REG_PCIE_CTRL, ~(BIT(15) | BIT(8)));
+
+	/* Stop FW */
+	HALMAC_REG_W16_CLR(REG_SYS_FUNC_EN, BIT(10));
+
+	/* Check Tx DMA is idle */
+	cnt = 20;
+	while ((HALMAC_REG_R8(REG_SYS_CFG5) & BIT(2)) == BIT(2)) {
+		PLTFM_DELAY_US(10);
+		cnt--;
+		if (cnt == 0) {
+			PLTFM_MSG_ERR("[ERR]Chk tx idle\n");
+			return HALMAC_RET_POWER_OFF_FAIL;
+		}
+	}
+
+	/* Check Rx DMA is idle */
+	cnt = 20;
+	while ((HALMAC_REG_R32(REG_RXPKT_NUM) & BIT(17)) != BIT(17)) {
+		PLTFM_DELAY_US(10);
+		cnt--;
+		if (cnt == 0) {
+			PLTFM_MSG_ERR("[ERR]Chk rx idle\n");
+			return HALMAC_RET_POWER_OFF_FAIL;
+		}
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+void
+en_ref_autok_88xx(struct halmac_adapter *adapter, u8 en)
+{
+	if (en == 1)
+		adapter->pcie_refautok_en = 1;
+	else
+		adapter->pcie_refautok_en = 0;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */

hal/halmac/halmac_88xx/halmac_pcie_88xx.h

@@ -0,0 +1,102 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_PCIE_88XX_H_
+#define _HALMAC_PCIE_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+init_pcie_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+deinit_pcie_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+cfg_pcie_rx_agg_88xx(struct halmac_adapter *adapter,
+		     struct halmac_rxagg_cfg *cfg);
+
+u8
+reg_r8_pcie_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w8_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
+
+u16
+reg_r16_pcie_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w16_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u16 value);
+
+u32
+reg_r32_pcie_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w32_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u32 value);
+
+enum halmac_ret_status
+cfg_txagg_pcie_align_88xx(struct halmac_adapter *adapter, u8 enable,
+			  u16 align_size);
+
+enum halmac_ret_status
+tx_allowed_pcie_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+u32
+pcie_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+pcie_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+		 u8 *value);
+
+enum halmac_ret_status
+set_pcie_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num);
+
+enum halmac_ret_status
+get_pcie_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+		      u32 *cmd53_addr);
+
+enum halmac_ret_status
+get_pcie_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+			 u8 *id);
+
+enum halmac_ret_status
+mdio_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed);
+
+u16
+mdio_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed);
+
+enum halmac_ret_status
+dbi_w32_88xx(struct halmac_adapter *adapter, u16 addr, u32 data);
+
+u32
+dbi_r32_88xx(struct halmac_adapter *adapter, u16 addr);
+
+enum halmac_ret_status
+dbi_w8_88xx(struct halmac_adapter *adapter, u16 addr, u8 data);
+
+u8
+dbi_r8_88xx(struct halmac_adapter *adapter, u16 addr);
+
+enum halmac_ret_status
+trxdma_check_idle_88xx(struct halmac_adapter *adapter);
+
+void
+en_ref_autok_88xx(struct halmac_adapter *dapter, u8 en);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_PCIE_88XX_H_ */

hal/halmac/halmac_88xx/halmac_sdio_88xx.c

@@ -0,0 +1,892 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_sdio_88xx.h"
+#include "halmac_88xx_cfg.h"
+
+#if HALMAC_88XX_SUPPORT
+
+/* define the SDIO Bus CLK threshold */
+/* for avoiding CMD53 fails that result from SDIO CLK sync to ana_clk fail */
+#define SDIO_CLK_HIGH_SPEED_TH		50 /* 50MHz */
+#define SDIO_CLK_SPEED_MAX		208 /* 208MHz */
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u8
+r_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 offset);
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u32
+r_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 offset);
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u32
+r8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr);
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u32
+r16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr);
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u32
+r32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr);
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
+		   enum halmac_io_size size);
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
+		   enum halmac_io_size size);
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val);
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val);
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val);
+
+/**
+ * init_sdio_cfg_88xx() - init SDIO
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_sdio_cfg_88xx(struct halmac_adapter *adapter)
+{
+	u32 value32;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (adapter->intf != HALMAC_INTERFACE_SDIO)
+		return HALMAC_RET_WRONG_INTF;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	HALMAC_REG_R32(REG_SDIO_FREE_TXPG);
+
+	value32 = HALMAC_REG_R32(REG_SDIO_TX_CTRL) & 0xFFFF;
+	value32 &= ~(BIT_CMD_ERR_STOP_INT_EN | BIT_EN_MASK_TIMER |
+							BIT_EN_RXDMA_MASK_INT);
+	HALMAC_REG_W32(REG_SDIO_TX_CTRL, value32);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * deinit_sdio_cfg_88xx() - deinit SDIO
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+deinit_sdio_cfg_88xx(struct halmac_adapter *adapter)
+{
+	if (adapter->intf != HALMAC_INTERFACE_SDIO)
+		return HALMAC_RET_WRONG_INTF;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_sdio_rx_agg_88xx() - config rx aggregation
+ * @adapter : the adapter of halmac
+ * @halmac_rx_agg_mode
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_sdio_rx_agg_88xx(struct halmac_adapter *adapter,
+		     struct halmac_rxagg_cfg *cfg)
+{
+	u8 value8;
+	u8 size;
+	u8 timeout;
+	u8 agg_enable;
+	u32 value32;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	agg_enable = HALMAC_REG_R8(REG_TXDMA_PQ_MAP);
+
+	switch (cfg->mode) {
+	case HALMAC_RX_AGG_MODE_NONE:
+		agg_enable &= ~(BIT_RXDMA_AGG_EN);
+		break;
+	case HALMAC_RX_AGG_MODE_DMA:
+	case HALMAC_RX_AGG_MODE_USB:
+		agg_enable |= BIT_RXDMA_AGG_EN;
+		break;
+	default:
+		PLTFM_MSG_ERR("[ERR]unsupported mode\n");
+		agg_enable &= ~BIT_RXDMA_AGG_EN;
+		break;
+	}
+
+	if (cfg->threshold.drv_define == _FALSE) {
+		size = 0xFF;
+		timeout = 0x01;
+	} else {
+		size = cfg->threshold.size;
+		timeout = cfg->threshold.timeout;
+	}
+
+	value32 = HALMAC_REG_R32(REG_RXDMA_AGG_PG_TH);
+	if (cfg->threshold.size_limit_en == _FALSE)
+		HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 & ~BIT_EN_PRE_CALC);
+	else
+		HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 | BIT_EN_PRE_CALC);
+
+	HALMAC_REG_W8(REG_TXDMA_PQ_MAP, agg_enable);
+	HALMAC_REG_W16(REG_RXDMA_AGG_PG_TH,
+		       (u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO_V1)));
+
+	value8 = HALMAC_REG_R8(REG_RXDMA_MODE);
+	if (0 != (agg_enable & BIT_RXDMA_AGG_EN))
+		HALMAC_REG_W8(REG_RXDMA_MODE, value8 | BIT_DMA_MODE);
+	else
+		HALMAC_REG_W8(REG_RXDMA_MODE, value8 & ~(BIT_DMA_MODE));
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * sdio_reg_rn_88xx() - read n byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @halmac_size : register value size
+ * @value : register value
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+sdio_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+		 u8 *value)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if (0 == (offset & 0xFFFF0000)) {
+		PLTFM_MSG_ERR("[ERR]offset 0x%x\n", offset);
+		return HALMAC_RET_FAIL;
+	}
+
+	status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+	if (status != HALMAC_RET_SUCCESS) {
+		PLTFM_MSG_ERR("[ERR]convert offset\n");
+		return status;
+	}
+
+	if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
+		PLTFM_MSG_ERR("[ERR]power off\n");
+		return HALMAC_RET_FAIL;
+	}
+
+	PLTFM_SDIO_CMD53_RN(offset, size, value);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_txagg_sdio_align_88xx() -config sdio bus tx agg alignment
+ * @adapter : the adapter of halmac
+ * @enable : function enable(1)/disable(0)
+ * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
+ * Author : Soar Tu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_txagg_sdio_align_88xx(struct halmac_adapter *adapter, u8 enable,
+			  u16 align_size)
+{
+	u8 i;
+	u8 flag = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (adapter->chip_id == HALMAC_CHIP_ID_8822B)
+		return HALMAC_RET_NOT_SUPPORT;
+
+	if ((align_size & 0xF000) != 0) {
+		PLTFM_MSG_ERR("[ERR]out of range\n");
+		return HALMAC_RET_FAIL;
+	}
+
+	for (i = 3; i <= 11; i++) {
+		if (align_size == 1 << i) {
+			flag = 1;
+			break;
+		}
+	}
+
+	if (flag == 0) {
+		PLTFM_MSG_ERR("[ERR]not 2^3 ~ 2^11\n");
+		return HALMAC_RET_FAIL;
+	}
+
+	adapter->hw_cfg_info.tx_align_size = align_size;
+
+	if (enable)
+		HALMAC_REG_W16(REG_RQPN_CTRL_2, 0x8000 | align_size);
+	else
+		HALMAC_REG_W16(REG_RQPN_CTRL_2, align_size);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * sdio_indirect_reg_r32_88xx() - read MAC reg by SDIO reg
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u32
+sdio_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+	return r_indir_sdio_88xx(adapter, offset, HALMAC_IO_DWORD);
+}
+
+/**
+ * set_sdio_bulkout_num_88xx() - inform bulk-out num
+ * @adapter : the adapter of halmac
+ * @bulkout_num : usb bulk-out number
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+set_sdio_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * get_sdio_bulkout_id_88xx() - get bulk out id for the TX packet
+ * @adapter : the adapter of halmac
+ * @halmac_buf : tx packet, include txdesc
+ * @halmac_size : tx packet size
+ * @bulkout_id : usb bulk-out id
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_sdio_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+			 u8 *id)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * sdio_cmd53_4byte_88xx() - cmd53 only for 4byte len register IO
+ * @adapter : the adapter of halmac
+ * @enable : 1->CMD53 only use in 4byte reg, 0 : No limitation
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+sdio_cmd53_4byte_88xx(struct halmac_adapter *adapter,
+		      enum halmac_sdio_cmd53_4byte_mode mode)
+{
+	if (adapter->intf != HALMAC_INTERFACE_SDIO)
+		return HALMAC_RET_WRONG_INTF;
+
+	if (adapter->api_registry.sdio_cmd53_4byte_en == 0)
+		return HALMAC_RET_NOT_SUPPORT;
+
+	adapter->sdio_cmd53_4byte = mode;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * sdio_hw_info_88xx() - info sdio hw info
+ * @adapter : the adapter of halmac
+ * @HALMAC_SDIO_CMD53_4BYTE_MODE :
+ * clock_speed : sdio bus clock. Unit -> MHz
+ * spec_ver : sdio spec version
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+sdio_hw_info_88xx(struct halmac_adapter *adapter,
+		  struct halmac_sdio_hw_info *info)
+{
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (adapter->intf != HALMAC_INTERFACE_SDIO)
+		return HALMAC_RET_WRONG_INTF;
+
+	PLTFM_MSG_TRACE("[TRACE]SDIO clock:%d, spec:%d\n",
+			info->clock_speed, info->spec_ver);
+
+	if (info->clock_speed > SDIO_CLK_SPEED_MAX)
+		return HALMAC_RET_SDIO_CLOCK_ERR;
+
+	if (info->clock_speed > SDIO_CLK_HIGH_SPEED_TH)
+		adapter->sdio_hw_info.io_hi_speed_flag = 1;
+
+	adapter->sdio_hw_info.io_indir_flag = info->io_indir_flag;
+	if (info->clock_speed > SDIO_CLK_HIGH_SPEED_TH &&
+	    adapter->sdio_hw_info.io_indir_flag == 0)
+		PLTFM_MSG_WARN("[WARN]SDIO clock:%d, indir access is better\n",
+			       info->clock_speed);
+
+	adapter->sdio_hw_info.clock_speed = info->clock_speed;
+	adapter->sdio_hw_info.spec_ver = info->spec_ver;
+	adapter->sdio_hw_info.block_size = info->block_size;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+void
+cfg_sdio_tx_page_threshold_88xx(struct halmac_adapter *adapter,
+				struct halmac_tx_page_threshold_info *info)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	u32 threshold = info->threshold;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (info->enable == 1) {
+		threshold = BIT(31) | threshold;
+		PLTFM_MSG_TRACE("[TRACE]enable\n");
+	} else {
+		threshold = ~(BIT(31)) & threshold;
+		PLTFM_MSG_TRACE("[TRACE]disable\n");
+	}
+
+	switch (info->dma_queue_sel) {
+	case HALMAC_MAP2_HQ:
+		HALMAC_REG_W32(REG_TQPNT1, threshold);
+		break;
+	case HALMAC_MAP2_NQ:
+		HALMAC_REG_W32(REG_TQPNT2, threshold);
+		break;
+	case HALMAC_MAP2_LQ:
+		HALMAC_REG_W32(REG_TQPNT3, threshold);
+		break;
+	case HALMAC_MAP2_EXQ:
+		HALMAC_REG_W32(REG_TQPNT4, threshold);
+		break;
+	default:
+		break;
+	}
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+}
+
+enum halmac_ret_status
+cnv_to_sdio_bus_offset_88xx(struct halmac_adapter *adapter, u32 *offset)
+{
+	switch ((*offset) & 0xFFFF0000) {
+	case WLAN_IOREG_OFFSET:
+		*offset &= HALMAC_WLAN_MAC_REG_MSK;
+		*offset |= HALMAC_SDIO_CMD_ADDR_MAC_REG << 13;
+		break;
+	case SDIO_LOCAL_OFFSET:
+		*offset &= HALMAC_SDIO_LOCAL_MSK;
+		*offset |= HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13;
+		break;
+	default:
+		*offset = 0xFFFFFFFF;
+		PLTFM_MSG_ERR("[ERR]base address!!\n");
+		return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+leave_sdio_suspend_88xx(struct halmac_adapter *adapter)
+{
+	u8 value8;
+	u32 cnt;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	value8 = HALMAC_REG_R8(REG_SDIO_HSUS_CTRL);
+	HALMAC_REG_W8(REG_SDIO_HSUS_CTRL, value8 & ~(BIT(0)));
+
+	cnt = 10000;
+	while (!(HALMAC_REG_R8(REG_SDIO_HSUS_CTRL) & 0x02)) {
+		cnt--;
+		if (cnt == 0)
+			return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
+	}
+
+	value8 = HALMAC_REG_R8(REG_HCI_OPT_CTRL + 2);
+	if (adapter->sdio_hw_info.spec_ver == HALMAC_SDIO_SPEC_VER_3_00)
+		HALMAC_REG_W8(REG_HCI_OPT_CTRL + 2, value8 | BIT(2));
+	else
+		HALMAC_REG_W8(REG_HCI_OPT_CTRL + 2, value8 & ~(BIT(2)));
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u8
+r_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+	u8 value8, tmp, cnt = 50;
+	u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
+	u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_cfg);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+	status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_data);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	PLTFM_SDIO_CMD52_W(reg_cfg, (u8)offset);
+	PLTFM_SDIO_CMD52_W(reg_cfg + 1, (u8)(offset >> 8));
+	PLTFM_SDIO_CMD52_W(reg_cfg + 2, (u8)(BIT(3) | BIT(4)));
+
+	do {
+		tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
+		cnt--;
+	} while (((tmp & BIT(4)) == 0) && (cnt > 0));
+
+	if (((cnt & BIT(4)) == 0) && cnt == 0)
+		PLTFM_MSG_ERR("[ERR]sdio indirect CMD52 read\n");
+
+	value8 = PLTFM_SDIO_CMD52_R(reg_data);
+
+	return value8;
+}
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u32
+r_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+	u8 tmp, cnt = 50;
+	u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
+	u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	union {
+		u32 dword;
+		u8 byte[4];
+	} value32 = { 0x00000000 };
+
+	status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_cfg);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+	status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_data);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	PLTFM_SDIO_CMD53_W32(reg_cfg, offset | BIT(19) | BIT(20));
+
+	do {
+		tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
+		cnt--;
+	} while (((tmp & BIT(4)) == 0) && (cnt > 0));
+
+	if (((cnt & BIT(4)) == 0) && cnt == 0)
+		PLTFM_MSG_ERR("[ERR]sdio indirect CMD53 read\n");
+
+	value32.dword = PLTFM_SDIO_CMD53_R32(reg_data);
+
+	return value32.dword;
+}
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u32
+r8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr)
+{
+	union {
+		u32 dword;
+		u8 byte[4];
+	} val = { 0x00000000 };
+
+	if (adapter->pwr_off_flow_flag == 1 ||
+	    adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
+		val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
+		val.dword = rtk_le32_to_cpu(val.dword);
+	} else {
+		val.dword = r_indir_cmd53_88xx(adapter, adr);
+	}
+
+	return val.dword;
+}
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u32
+r16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr)
+{
+	u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	union {
+		u32 dword;
+		u8 byte[4];
+	} val = { 0x00000000 };
+
+	status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_data);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
+		if (0 != (adr & (2 - 1))) {
+			val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
+			val.byte[1] = r_indir_cmd52_88xx(adapter, adr + 1);
+		} else {
+			val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
+			val.byte[1] = PLTFM_SDIO_CMD52_R(reg_data + 1);
+		}
+		val.dword = rtk_le32_to_cpu(val.dword);
+	} else {
+		if (0 != (adr & (2 - 1))) {
+			val.byte[0] = (u8)r_indir_cmd53_88xx(adapter, adr);
+			val.byte[1] = (u8)r_indir_cmd53_88xx(adapter, adr + 1);
+			val.dword = rtk_le32_to_cpu(val.dword);
+		} else {
+			val.dword = r_indir_cmd53_88xx(adapter, adr);
+		}
+	}
+	return val.dword;
+}
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u32
+r32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr)
+{
+	u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	union {
+		u32 dword;
+		u8 byte[4];
+	} val = { 0x00000000 };
+
+	status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_data);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
+		if (0 != (adr & (4 - 1))) {
+			val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
+			val.byte[1] = r_indir_cmd52_88xx(adapter, adr + 1);
+			val.byte[2] = r_indir_cmd52_88xx(adapter, adr + 2);
+			val.byte[3] = r_indir_cmd52_88xx(adapter, adr + 3);
+		} else {
+			val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
+			val.byte[1] = PLTFM_SDIO_CMD52_R(reg_data + 1);
+			val.byte[2] = PLTFM_SDIO_CMD52_R(reg_data + 2);
+			val.byte[3] = PLTFM_SDIO_CMD52_R(reg_data + 3);
+		}
+		val.dword = rtk_le32_to_cpu(val.dword);
+	} else {
+		if (0 != (adr & (4 - 1))) {
+			val.byte[0] = (u8)r_indir_cmd53_88xx(adapter, adr);
+			val.byte[1] = (u8)r_indir_cmd53_88xx(adapter, adr + 1);
+			val.byte[2] = (u8)r_indir_cmd53_88xx(adapter, adr + 2);
+			val.byte[3] = (u8)r_indir_cmd53_88xx(adapter, adr + 3);
+			val.dword = rtk_le32_to_cpu(val.dword);
+		} else {
+			val.dword = r_indir_cmd53_88xx(adapter, adr);
+		}
+	}
+	return val.dword;
+}
+
+u32
+r_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr,
+		  enum halmac_io_size size)
+{
+	u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	union {
+		u32 dword;
+		u8 byte[4];
+	} val = { 0x00000000 };
+
+	status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_data);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	PLTFM_MUTEX_LOCK(&adapter->sdio_indir_mutex);
+
+	switch (size) {
+	case HALMAC_IO_BYTE:
+		val.dword = r8_indir_sdio_88xx(adapter, adr);
+		break;
+	case HALMAC_IO_WORD:
+		val.dword = r16_indir_sdio_88xx(adapter, adr);
+		break;
+	case HALMAC_IO_DWORD:
+		val.dword = r32_indir_sdio_88xx(adapter, adr);
+		break;
+	default:
+		break;
+	}
+
+	PLTFM_MUTEX_UNLOCK(&adapter->sdio_indir_mutex);
+
+	return val.dword;
+}
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
+		   enum halmac_io_size size)
+{
+	u8 tmp, cnt = 50;
+	u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
+	u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_cfg);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+	status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_data);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	PLTFM_SDIO_CMD52_W(reg_cfg, (u8)adr);
+	PLTFM_SDIO_CMD52_W(reg_cfg + 1, (u8)(adr >> 8));
+	switch (size) {
+	case HALMAC_IO_BYTE:
+		PLTFM_SDIO_CMD52_W(reg_data, (u8)val);
+		PLTFM_SDIO_CMD52_W(reg_cfg + 2, (u8)(BIT(2) | BIT(4)));
+		break;
+	case HALMAC_IO_WORD:
+		PLTFM_SDIO_CMD52_W(reg_data, (u8)val);
+		PLTFM_SDIO_CMD52_W(reg_data + 1, (u8)(val >> 8));
+		PLTFM_SDIO_CMD52_W(reg_cfg + 2,
+				   (u8)(BIT(0) | BIT(2) | BIT(4)));
+		break;
+	case HALMAC_IO_DWORD:
+		PLTFM_SDIO_CMD52_W(reg_data, (u8)val);
+		PLTFM_SDIO_CMD52_W(reg_data + 1, (u8)(val >> 8));
+		PLTFM_SDIO_CMD52_W(reg_data + 2, (u8)(val >> 16));
+		PLTFM_SDIO_CMD52_W(reg_data + 3, (u8)(val >> 24));
+		PLTFM_SDIO_CMD52_W(reg_cfg + 2,
+				   (u8)(BIT(1) | BIT(2) | BIT(4)));
+		break;
+	default:
+		break;
+	}
+
+	do {
+		tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
+		cnt--;
+	} while (((tmp & BIT(4)) == 0) && (cnt > 0));
+
+	if (((cnt & BIT(4)) == 0) && cnt == 0)
+		PLTFM_MSG_ERR("[ERR]sdio indirect CMD52 write\n");
+
+	return status;
+}
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
+		   enum halmac_io_size size)
+{
+	u8 tmp, cnt = 50;
+	u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
+	u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
+	u32 value32 = 0;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_cfg);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+	status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_data);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	switch (size) {
+	case HALMAC_IO_BYTE:
+		value32 = adr | BIT(18) | BIT(20);
+		break;
+	case HALMAC_IO_WORD:
+		value32 = adr | BIT(16) | BIT(18) | BIT(20);
+		break;
+	case HALMAC_IO_DWORD:
+		value32 = adr | BIT(17) | BIT(18) | BIT(20);
+		break;
+	default:
+		return HALMAC_RET_FAIL;
+	}
+
+	PLTFM_SDIO_CMD53_W32(reg_data, val);
+	PLTFM_SDIO_CMD53_W32(reg_cfg, value32);
+
+	do {
+		tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
+		cnt--;
+	} while (((tmp & BIT(4)) == 0) && (cnt > 0));
+
+	if (((cnt & BIT(4)) == 0) && cnt == 0)
+		PLTFM_MSG_ERR("[ERR]sdio indirect CMD53 read\n");
+
+	return status;
+}
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if (adapter->pwr_off_flow_flag == 1 ||
+	    adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF)
+		status = w_indir_cmd52_88xx(adapter, adr, val, HALMAC_IO_BYTE);
+	else
+		status = w_indir_cmd53_88xx(adapter, adr, val, HALMAC_IO_BYTE);
+	return status;
+}
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
+		if (0 != (adr & (2 - 1))) {
+			status = w_indir_cmd52_88xx(adapter, adr, val,
+						    HALMAC_IO_BYTE);
+			if (status != HALMAC_RET_SUCCESS)
+				return status;
+			status = w_indir_cmd52_88xx(adapter, adr + 1, val >> 8,
+						    HALMAC_IO_BYTE);
+		} else {
+			status = w_indir_cmd52_88xx(adapter, adr, val,
+						    HALMAC_IO_WORD);
+		}
+	} else {
+		if (0 != (adr & (2 - 1))) {
+			status = w_indir_cmd53_88xx(adapter, adr, val,
+						    HALMAC_IO_BYTE);
+			if (status != HALMAC_RET_SUCCESS)
+				return status;
+			status = w_indir_cmd53_88xx(adapter, adr + 1, val >> 8,
+						    HALMAC_IO_BYTE);
+		} else {
+			status = w_indir_cmd53_88xx(adapter, adr, val,
+						    HALMAC_IO_WORD);
+		}
+	}
+	return status;
+}
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
+		if (0 != (adr & (4 - 1))) {
+			status = w_indir_cmd52_88xx(adapter, adr, val,
+						    HALMAC_IO_BYTE);
+			if (status != HALMAC_RET_SUCCESS)
+				return status;
+			status = w_indir_cmd52_88xx(adapter, adr + 1, val >> 8,
+						    HALMAC_IO_BYTE);
+			if (status != HALMAC_RET_SUCCESS)
+				return status;
+			status = w_indir_cmd52_88xx(adapter, adr + 2, val >> 16,
+						    HALMAC_IO_BYTE);
+			if (status != HALMAC_RET_SUCCESS)
+				return status;
+			status = w_indir_cmd52_88xx(adapter, adr + 3, val >> 24,
+						    HALMAC_IO_BYTE);
+		} else {
+			status = w_indir_cmd52_88xx(adapter, adr, val,
+						    HALMAC_IO_DWORD);
+		}
+	} else {
+		if (0 != (adr & (4 - 1))) {
+			status = w_indir_cmd53_88xx(adapter, adr, val,
+						    HALMAC_IO_BYTE);
+			if (status != HALMAC_RET_SUCCESS)
+				return status;
+			status = w_indir_cmd53_88xx(adapter, adr + 1, val >> 8,
+						    HALMAC_IO_BYTE);
+			if (status != HALMAC_RET_SUCCESS)
+				return status;
+			status = w_indir_cmd53_88xx(adapter, adr + 2, val >> 16,
+						    HALMAC_IO_BYTE);
+			if (status != HALMAC_RET_SUCCESS)
+				return status;
+			status = w_indir_cmd53_88xx(adapter, adr + 3, val >> 24,
+						    HALMAC_IO_BYTE);
+		} else {
+			status = w_indir_cmd53_88xx(adapter, adr, val,
+						    HALMAC_IO_DWORD);
+		}
+	}
+	return status;
+}
+
+enum halmac_ret_status
+w_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
+		  enum halmac_io_size size)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	PLTFM_MUTEX_LOCK(&adapter->sdio_indir_mutex);
+
+	switch (size) {
+	case HALMAC_IO_BYTE:
+		status = w8_indir_sdio_88xx(adapter, adr, val);
+		break;
+	case HALMAC_IO_WORD:
+		status = w16_indir_sdio_88xx(adapter, adr, val);
+		break;
+	case HALMAC_IO_DWORD:
+		status = w32_indir_sdio_88xx(adapter, adr, val);
+		break;
+	default:
+		break;
+	}
+
+	PLTFM_MUTEX_UNLOCK(&adapter->sdio_indir_mutex);
+
+	return status;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */

hal/halmac/halmac_88xx/halmac_sdio_88xx.h

@@ -0,0 +1,79 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_SDIO_88XX_H_
+#define _HALMAC_SDIO_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+init_sdio_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+deinit_sdio_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+cfg_sdio_rx_agg_88xx(struct halmac_adapter *adapter,
+		     struct halmac_rxagg_cfg *cfg);
+
+enum halmac_ret_status
+cfg_txagg_sdio_align_88xx(struct halmac_adapter *adapter, u8 enable,
+			  u16 align_size);
+
+u32
+sdio_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+sdio_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+		 u8 *value);
+
+enum halmac_ret_status
+set_sdio_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num);
+
+enum halmac_ret_status
+get_sdio_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+			 u8 *id);
+
+enum halmac_ret_status
+sdio_cmd53_4byte_88xx(struct halmac_adapter *adapter,
+		      enum halmac_sdio_cmd53_4byte_mode mode);
+
+enum halmac_ret_status
+sdio_hw_info_88xx(struct halmac_adapter *adapter,
+		  struct halmac_sdio_hw_info *info);
+
+void
+cfg_sdio_tx_page_threshold_88xx(struct halmac_adapter *adapter,
+				struct halmac_tx_page_threshold_info *info);
+
+enum halmac_ret_status
+cnv_to_sdio_bus_offset_88xx(struct halmac_adapter *adapter, u32 *offset);
+
+enum halmac_ret_status
+leave_sdio_suspend_88xx(struct halmac_adapter *adapter);
+
+u32
+r_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr,
+		  enum halmac_io_size size);
+
+enum halmac_ret_status
+w_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
+		  enum halmac_io_size size);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_SDIO_88XX_H_ */

hal/halmac/halmac_88xx/halmac_usb_88xx.c

@@ -0,0 +1,533 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_usb_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum usb_burst_size {
+	USB_BURST_SIZE_3_0 = 0x0,
+	USB_BURST_SIZE_2_0_HS = 0x1,
+	USB_BURST_SIZE_2_0_FS = 0x2,
+	USB_BURST_SIZE_2_0_OTHERS = 0x3,
+	USB_BURST_SIZE_UNDEFINE = 0x7F,
+};
+
+/**
+ * init_usb_cfg_88xx() - init USB
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_usb_cfg_88xx(struct halmac_adapter *adapter)
+{
+	u8 value8 = 0;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	value8 |= (BIT_DMA_MODE | (0x3 << BIT_SHIFT_BURST_CNT));
+
+	if (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20) {
+		 /* usb3.0 */
+		value8 |= (USB_BURST_SIZE_3_0 << BIT_SHIFT_BURST_SIZE);
+	} else {
+		if ((HALMAC_REG_R8(REG_USB_USBSTAT) & 0x3) == 0x1)/* usb2.0 */
+			value8 |= USB_BURST_SIZE_2_0_HS << BIT_SHIFT_BURST_SIZE;
+		else /* usb1.1 */
+			value8 |= USB_BURST_SIZE_2_0_FS << BIT_SHIFT_BURST_SIZE;
+	}
+
+	HALMAC_REG_W8(REG_RXDMA_MODE, value8);
+	HALMAC_REG_W16(REG_TXDMA_OFFSET_CHK,
+		       HALMAC_REG_R16(REG_TXDMA_OFFSET_CHK) | BIT_DROP_DATA_EN);
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * deinit_usb_cfg_88xx() - deinit USB
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+deinit_usb_cfg_88xx(struct halmac_adapter *adapter)
+{
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_usb_rx_agg_88xx() - config rx aggregation
+ * @adapter : the adapter of halmac
+ * @halmac_rx_agg_mode
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_usb_rx_agg_88xx(struct halmac_adapter *adapter,
+		    struct halmac_rxagg_cfg *cfg)
+{
+	u8 dma_usb_agg;
+	u8 size;
+	u8 timeout;
+	u8 agg_enable;
+	u32 value32;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	dma_usb_agg = HALMAC_REG_R8(REG_RXDMA_AGG_PG_TH + 3);
+	agg_enable = HALMAC_REG_R8(REG_TXDMA_PQ_MAP);
+
+	switch (cfg->mode) {
+	case HALMAC_RX_AGG_MODE_NONE:
+		agg_enable &= ~BIT_RXDMA_AGG_EN;
+		break;
+	case HALMAC_RX_AGG_MODE_DMA:
+		agg_enable |= BIT_RXDMA_AGG_EN;
+		dma_usb_agg |= BIT(7);
+		break;
+
+	case HALMAC_RX_AGG_MODE_USB:
+		agg_enable |= BIT_RXDMA_AGG_EN;
+		dma_usb_agg &= ~BIT(7);
+		break;
+	default:
+		PLTFM_MSG_ERR("[ERR]unsupported mode\n");
+		agg_enable &= ~BIT_RXDMA_AGG_EN;
+		break;
+	}
+
+	if (cfg->threshold.drv_define == _FALSE) {
+		if (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20) {
+			/* usb3.0 */
+			size = 0x5;
+			timeout = 0xA;
+		} else {
+			/* usb2.0 */
+			size = 0x5;
+			timeout = 0x20;
+		}
+	} else {
+		size = cfg->threshold.size;
+		timeout = cfg->threshold.timeout;
+	}
+
+	value32 = HALMAC_REG_R32(REG_RXDMA_AGG_PG_TH);
+	if (cfg->threshold.size_limit_en == _FALSE)
+		HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 & ~BIT_EN_PRE_CALC);
+	else
+		HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 | BIT_EN_PRE_CALC);
+
+	HALMAC_REG_W8(REG_TXDMA_PQ_MAP, agg_enable);
+	HALMAC_REG_W8(REG_RXDMA_AGG_PG_TH + 3, dma_usb_agg);
+	HALMAC_REG_W16(REG_RXDMA_AGG_PG_TH,
+		       (u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO_V1)));
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * reg_r8_usb_88xx() - read 1byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u8
+reg_r8_usb_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+	u8 value8;
+
+	value8 = PLTFM_REG_R8(offset);
+
+	return value8;
+}
+
+/**
+ * reg_w8_usb_88xx() - write 1byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w8_usb_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
+{
+	PLTFM_REG_W8(offset, value);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * reg_r16_usb_88xx() - read 2byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u16
+reg_r16_usb_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+	u16 value16;
+
+	value16 = PLTFM_REG_R16(offset);
+
+	return value16;
+}
+
+/**
+ * reg_w16_usb_88xx() - write 2byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w16_usb_88xx(struct halmac_adapter *adapter, u32 offset, u16 value)
+{
+	PLTFM_REG_W16(offset, value);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * reg_r32_usb_88xx() - read 4byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u32
+reg_r32_usb_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+	u32 value32;
+
+	value32 = PLTFM_REG_R32(offset);
+
+	return value32;
+}
+
+/**
+ * reg_w32_usb_88xx() - write 4byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w32_usb_88xx(struct halmac_adapter *adapter, u32 offset, u32 value)
+{
+	PLTFM_REG_W32(offset, value);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * set_usb_bulkout_num_88xx() - inform bulk-out num
+ * @adapter : the adapter of halmac
+ * @bulkout_num : usb bulk-out number
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+set_usb_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num)
+{
+	adapter->bulkout_num = num;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_usb_bulkout_id_88xx() - get bulk out id for the TX packet
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size
+ * @id : usb bulk-out id
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_usb_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+			u8 *id)
+{
+	enum halmac_qsel queue_sel;
+	enum halmac_dma_mapping dma_mapping;
+
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	if (!buf) {
+		PLTFM_MSG_ERR("[ERR]buf is NULL!!\n");
+		return HALMAC_RET_DATA_BUF_NULL;
+	}
+
+	if (size == 0) {
+		PLTFM_MSG_ERR("[ERR]size is 0!!\n");
+		return HALMAC_RET_DATA_SIZE_INCORRECT;
+	}
+
+	queue_sel = (enum halmac_qsel)GET_TX_DESC_QSEL(buf);
+
+	switch (queue_sel) {
+	case HALMAC_QSEL_VO:
+	case HALMAC_QSEL_VO_V2:
+		dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VO];
+		break;
+	case HALMAC_QSEL_VI:
+	case HALMAC_QSEL_VI_V2:
+		dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VI];
+		break;
+	case HALMAC_QSEL_BE:
+	case HALMAC_QSEL_BE_V2:
+		dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BE];
+		break;
+	case HALMAC_QSEL_BK:
+	case HALMAC_QSEL_BK_V2:
+		dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BK];
+		break;
+	case HALMAC_QSEL_MGNT:
+		dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_MG];
+		break;
+	case HALMAC_QSEL_HIGH:
+	case HALMAC_QSEL_BCN:
+	case HALMAC_QSEL_CMD:
+		dma_mapping = HALMAC_DMA_MAPPING_HIGH;
+		break;
+	default:
+		PLTFM_MSG_ERR("[ERR]Qsel is out of range\n");
+		return HALMAC_RET_QSEL_INCORRECT;
+	}
+
+	switch (dma_mapping) {
+	case HALMAC_DMA_MAPPING_HIGH:
+		*id = 0;
+		break;
+	case HALMAC_DMA_MAPPING_NORMAL:
+		*id = 1;
+		break;
+	case HALMAC_DMA_MAPPING_LOW:
+		*id = 2;
+		break;
+	case HALMAC_DMA_MAPPING_EXTRA:
+		*id = 3;
+		break;
+	default:
+		PLTFM_MSG_ERR("[ERR]out of range\n");
+		return HALMAC_RET_DMA_MAP_INCORRECT;
+	}
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_txagg_usb_align_88xx() -config sdio bus tx agg alignment
+ * @adapter : the adapter of halmac
+ * @enable : function enable(1)/disable(0)
+ * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
+ * Author : Soar Tu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_txagg_usb_align_88xx(struct halmac_adapter *adapter, u8 enable,
+			 u16 align_size)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * tx_allowed_usb_88xx() - check tx status
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size, include txdesc
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+tx_allowed_usb_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * usb_indirect_reg_r32_88xx() - read MAC reg by SDIO reg
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u32
+usb_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+	return 0xFFFFFFFF;
+}
+
+/**
+ * usb_reg_rn_88xx() - read n byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @size : register value size
+ * @value : register value
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+usb_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+		u8 *value)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * get_usb_tx_addr_88xx() - get CMD53 addr for the TX packet
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size
+ * @pcmd53_addr : cmd53 addr value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_usb_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+		     u32 *cmd53_addr)
+{
+	return HALMAC_RET_NOT_SUPPORT;
+}
+
+enum halmac_ret_status
+set_usb_mode_88xx(struct halmac_adapter *adapter, enum halmac_usb_mode mode)
+{
+	u32 usb_tmp;
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	enum halmac_usb_mode cur_mode;
+
+	cur_mode = (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20) ?
+					HALMAC_USB_MODE_U3 : HALMAC_USB_MODE_U2;
+
+	/*check if HW supports usb2_usb3 switch*/
+	usb_tmp = HALMAC_REG_R32(REG_PAD_CTRL2);
+	if (_FALSE == (BIT_GET_USB23_SW_MODE_V1(usb_tmp) |
+	    (usb_tmp & BIT_USB3_USB2_TRANSITION))) {
+		PLTFM_MSG_ERR("[ERR]u2/u3 switch\n");
+		return HALMAC_RET_USB2_3_SWITCH_UNSUPPORT;
+	}
+
+	if (mode == cur_mode) {
+		PLTFM_MSG_ERR("[ERR]u2/u3 unchange\n");
+		return HALMAC_RET_USB_MODE_UNCHANGE;
+	}
+
+	/* Enable IO wrapper timeout */
+	if (adapter->chip_id == HALMAC_CHIP_ID_8822B ||
+	    adapter->chip_id == HALMAC_CHIP_ID_8821C)
+		HALMAC_REG_W8_CLR(REG_SW_MDIO + 3, BIT(0));
+
+	usb_tmp &= ~(BIT_USB23_SW_MODE_V1(0x3));
+
+	if (mode == HALMAC_USB_MODE_U2)
+		HALMAC_REG_W32(REG_PAD_CTRL2,
+			       usb_tmp |
+			       BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U2) |
+			       BIT_RSM_EN_V1);
+	else
+		HALMAC_REG_W32(REG_PAD_CTRL2,
+			       usb_tmp |
+			       BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U3) |
+			       BIT_RSM_EN_V1);
+
+	HALMAC_REG_W8(REG_PAD_CTRL2 + 1, 4);
+	HALMAC_REG_W16_SET(REG_SYS_PW_CTRL, BIT_APFM_OFFMAC);
+	PLTFM_DELAY_US(1000);
+	HALMAC_REG_W32_SET(REG_PAD_CTRL2, BIT_NO_PDN_CHIPOFF_V1);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+usbphy_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+	if (speed == HAL_INTF_PHY_USB3) {
+		HALMAC_REG_W8(0xff0d, (u8)data);
+		HALMAC_REG_W8(0xff0e, (u8)(data >> 8));
+		HALMAC_REG_W8(0xff0c, addr | BIT(7));
+	} else if (speed == HAL_INTF_PHY_USB2) {
+		HALMAC_REG_W8(0xfe41, (u8)data);
+		HALMAC_REG_W8(0xfe40, addr);
+		HALMAC_REG_W8(0xfe42, 0x81);
+	} else {
+		PLTFM_MSG_ERR("[ERR]Error USB Speed !\n");
+		return HALMAC_RET_NOT_SUPPORT;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+u16
+usbphy_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed)
+{
+	struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+	u16 value = 0;
+
+	if (speed == HAL_INTF_PHY_USB3) {
+		HALMAC_REG_W8(0xff0c, addr | BIT(6));
+		value = (u16)(HALMAC_REG_R32(0xff0c) >> 8);
+	} else if (speed == HAL_INTF_PHY_USB2) {
+		if (addr >= 0xE0 && addr <= 0xFF)
+			addr -= 0x20;
+		if (addr >= 0xC0 && addr <= 0xDF) {
+			HALMAC_REG_W8(0xfe40, addr);
+			HALMAC_REG_W8(0xfe42, 0x81);
+			value = HALMAC_REG_R8(0xfe43);
+		} else {
+			PLTFM_MSG_ERR("[ERR]phy offset\n");
+			return HALMAC_RET_NOT_SUPPORT;
+		}
+	} else {
+		PLTFM_MSG_ERR("[ERR]usb speed !\n");
+		return HALMAC_RET_NOT_SUPPORT;
+	}
+
+	return value;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */

hal/halmac/halmac_88xx/halmac_usb_88xx.h

@@ -0,0 +1,87 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_USB_88XX_H_
+#define _HALMAC_USB_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+init_usb_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+deinit_usb_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+cfg_usb_rx_agg_88xx(struct halmac_adapter *adapter,
+		    struct halmac_rxagg_cfg *cfg);
+
+u8
+reg_r8_usb_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w8_usb_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
+
+u16
+reg_r16_usb_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w16_usb_88xx(struct halmac_adapter *adapter, u32 offset, u16 value);
+
+u32
+reg_r32_usb_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w32_usb_88xx(struct halmac_adapter *adapter, u32 offset, u32 value);
+
+enum halmac_ret_status
+set_usb_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num);
+
+enum halmac_ret_status
+get_usb_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+			u8 *id);
+
+enum halmac_ret_status
+cfg_txagg_usb_align_88xx(struct halmac_adapter *adapter, u8 enable,
+			 u16 align_size);
+
+enum halmac_ret_status
+tx_allowed_usb_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+u32
+usb_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+usb_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+		u8 *value);
+
+enum halmac_ret_status
+get_usb_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+		     u32 *cmd53_addr);
+
+enum halmac_ret_status
+set_usb_mode_88xx(struct halmac_adapter *adapter, enum halmac_usb_mode mode);
+
+enum halmac_ret_status
+usbphy_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed);
+
+u16
+usbphy_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_API_88XX_USB_H_ */

hal/halmac/halmac_api.c

@@ -0,0 +1,602 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_type.h"
+#include "halmac_api.h"
+
+#if (HALMAC_PLATFORM_WINDOWS)
+
+#if HALMAC_8822B_SUPPORT
+#include "halmac_88xx/halmac_init_win8822b.h"
+#endif
+
+#if HALMAC_8821C_SUPPORT
+#include "halmac_88xx/halmac_init_win8821c.h"
+#endif
+
+#if HALMAC_8814B_SUPPORT
+#include "halmac_88xx_v1/halmac_init_win8814b_v1.h"
+#endif
+
+#if HALMAC_8822C_SUPPORT
+#include "halmac_88xx/halmac_init_win8822c.h"
+#endif
+
+#else
+
+#if HALMAC_88XX_SUPPORT
+#include "halmac_88xx/halmac_init_88xx.h"
+#endif
+#if HALMAC_88XX_V1_SUPPORT
+#include "halmac_88xx_v1/halmac_init_88xx_v1.h"
+#endif
+
+#endif
+/* Remove halmac_*/
+enum chip_id_hw_def {
+	CHIP_ID_HW_DEF_8723A = 0x01,
+	CHIP_ID_HW_DEF_8188E = 0x02,
+	CHIP_ID_HW_DEF_8881A = 0x03,
+	CHIP_ID_HW_DEF_8812A = 0x04,
+	CHIP_ID_HW_DEF_8821A = 0x05,
+	CHIP_ID_HW_DEF_8723B = 0x06,
+	CHIP_ID_HW_DEF_8192E = 0x07,
+	CHIP_ID_HW_DEF_8814A = 0x08,
+	CHIP_ID_HW_DEF_8821C = 0x09,
+	CHIP_ID_HW_DEF_8822B = 0x0A,
+	CHIP_ID_HW_DEF_8703B = 0x0B,
+	CHIP_ID_HW_DEF_8188F = 0x0C,
+	CHIP_ID_HW_DEF_8192F = 0x0D,
+	CHIP_ID_HW_DEF_8197F = 0x0E,
+	CHIP_ID_HW_DEF_8723D = 0x0F,
+	CHIP_ID_HW_DEF_8814B = 0x11,
+	CHIP_ID_HW_DEF_8822C = 0x13,
+	CHIP_ID_HW_DEF_UNDEFINE = 0x7F,
+	CHIP_ID_HW_DEF_PS = 0xEA,
+};
+
+static enum halmac_ret_status
+chk_pltfm_api(void *drv_adapter, enum halmac_interface intf,
+	      struct halmac_platform_api *pltfm_api);
+
+static enum halmac_ret_status
+get_chip_info(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+	      enum halmac_interface intf, struct halmac_adapter *adapter);
+
+static u8
+pltfm_reg_r8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+		  u32 offset);
+
+static enum halmac_ret_status
+pltfm_reg_w8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+		  u32 offset, u8 data);
+
+static u8
+pltfm_reg_r_indir_sdio(VOID *drv_adapter, struct halmac_platform_api *pltfm_api,
+		       u32 offset);
+
+static enum halmac_ret_status
+cnv_to_sdio_bus_offset(u32 *offset);
+
+/**
+ * halmac_init_adapter() - init halmac_adapter
+ * @drv_adapter : the adapter of caller
+ * @pltfm_api : the platform APIs which is used in halmac
+ * @intf : bus interface
+ * @halmac_adapter : the adapter of halmac
+ * @halmac_api : the function pointer of APIs
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+		    enum halmac_interface intf,
+		    struct halmac_adapter **halmac_adapter,
+		    struct halmac_api **halmac_api)
+{
+	struct halmac_adapter *adapter = NULL;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+	u8 *buf = NULL;
+
+	union {
+		u32 i;
+		u8 x[4];
+	} ENDIAN_CHECK = { 0x01000000 };
+
+	status = chk_pltfm_api(drv_adapter, intf, pltfm_api);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS,
+			     HALMAC_SVN_VER "\n"
+			     "HALMAC_MAJOR_VER = %x\n"
+			     "HALMAC_PROTOTYPE_VER = %x\n"
+			     "HALMAC_MINOR_VER = %x\n"
+			     "HALMAC_PATCH_VER = %x\n",
+			     HALMAC_MAJOR_VER, HALMAC_PROTOTYPE_VER,
+			     HALMAC_MINOR_VER, HALMAC_PATCH_VER);
+
+	if (ENDIAN_CHECK.x[0] == HALMAC_SYSTEM_ENDIAN) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR,
+				     "[ERR]Endian setting err!!\n");
+		return HALMAC_RET_ENDIAN_ERR;
+	}
+
+	buf = (u8 *)pltfm_api->RTL_MALLOC(drv_adapter, sizeof(*adapter));
+
+	if (!buf) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR,
+				     "[ERR]Malloc HAL adapter err!!\n");
+		return HALMAC_RET_MALLOC_FAIL;
+	}
+	pltfm_api->RTL_MEMSET(drv_adapter, buf, 0x00, sizeof(*adapter));
+	adapter = (struct halmac_adapter *)buf;
+
+	*halmac_adapter = adapter;
+
+	adapter->pltfm_api = pltfm_api;
+	adapter->drv_adapter = drv_adapter;
+	intf = (intf == HALMAC_INTERFACE_AXI) ? HALMAC_INTERFACE_PCIE : intf;
+	adapter->intf = intf;
+
+	if (get_chip_info(drv_adapter, pltfm_api, intf, adapter)
+	    != HALMAC_RET_SUCCESS) {
+		PLTFM_FREE(*halmac_adapter, sizeof(**halmac_adapter));
+		*halmac_adapter = NULL;
+		return HALMAC_RET_CHIP_NOT_SUPPORT;
+	}
+
+	PLTFM_MUTEX_INIT(&adapter->efuse_mutex);
+	PLTFM_MUTEX_INIT(&adapter->h2c_seq_mutex);
+	PLTFM_MUTEX_INIT(&adapter->sdio_indir_mutex);
+
+#if (HALMAC_PLATFORM_WINDOWS == 0)
+
+#if HALMAC_88XX_SUPPORT
+	if (adapter->chip_id == HALMAC_CHIP_ID_8822B ||
+	    adapter->chip_id == HALMAC_CHIP_ID_8821C ||
+	    adapter->chip_id == HALMAC_CHIP_ID_8822C) {
+		init_adapter_param_88xx(adapter);
+		status = mount_api_88xx(adapter);
+	}
+#endif
+
+#if HALMAC_88XX_V1_SUPPORT
+	if (adapter->chip_id == HALMAC_CHIP_ID_8814B) {
+		init_adapter_param_88xx_v1(adapter);
+		status = mount_api_88xx_v1(adapter);
+	}
+#endif
+
+#else
+
+#if HALMAC_8822B_SUPPORT
+	if (adapter->chip_id == HALMAC_CHIP_ID_8822B) {
+		init_adapter_param_win8822b(adapter);
+		status = mount_api_win8822b(adapter);
+	}
+#endif
+
+#if HALMAC_8821C_SUPPORT
+	if (adapter->chip_id == HALMAC_CHIP_ID_8821C) {
+		init_adapter_param_win8821c(adapter);
+		status = mount_api_win8821c(adapter);
+	}
+#endif
+
+#if HALMAC_8814B_SUPPORT
+	if (adapter->chip_id == HALMAC_CHIP_ID_8814B) {
+		init_adapter_param_win8814b_v1(adapter);
+		status = mount_api_win8814b_v1(adapter);
+	}
+#endif
+
+#if HALMAC_8822C_SUPPORT
+	if (adapter->chip_id == HALMAC_CHIP_ID_8822C) {
+		init_adapter_param_win8822c(adapter);
+		status = mount_api_win8822c(adapter);
+	}
+#endif
+
+#endif
+	*halmac_api = (struct halmac_api *)adapter->halmac_api;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return status;
+}
+
+/**
+ * halmac_halt_api() - stop halmac_api action
+ * @adapter : the adapter of halmac
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+halmac_halt_api(struct halmac_adapter *adapter)
+{
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	adapter->halmac_state.api_state = HALMAC_API_STATE_HALT;
+
+	PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_deinit_adapter() - deinit halmac adapter
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+halmac_deinit_adapter(struct halmac_adapter *adapter)
+{
+	PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+	PLTFM_MUTEX_DEINIT(&adapter->efuse_mutex);
+	PLTFM_MUTEX_DEINIT(&adapter->h2c_seq_mutex);
+	PLTFM_MUTEX_DEINIT(&adapter->sdio_indir_mutex);
+
+	if (adapter->efuse_map) {
+		PLTFM_FREE(adapter->efuse_map, adapter->hw_cfg_info.efuse_size);
+		adapter->efuse_map = (u8 *)NULL;
+	}
+
+	if (adapter->sdio_fs.macid_map) {
+		PLTFM_FREE(adapter->sdio_fs.macid_map,
+			   adapter->sdio_fs.macid_map_size);
+		adapter->sdio_fs.macid_map = (u8 *)NULL;
+	}
+
+	if (adapter->halmac_state.psd_state.data) {
+		PLTFM_FREE(adapter->halmac_state.psd_state.data,
+			   adapter->halmac_state.psd_state.data_size);
+		adapter->halmac_state.psd_state.data = (u8 *)NULL;
+	}
+
+	if (adapter->halmac_api) {
+		PLTFM_FREE(adapter->halmac_api, sizeof(struct halmac_api));
+		adapter->halmac_api = NULL;
+	}
+
+	PLTFM_FREE(adapter, sizeof(*adapter));
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+chk_pltfm_api(void *drv_adapter, enum halmac_interface intf,
+	      struct halmac_platform_api *pltfm_api)
+{
+	if (!pltfm_api)
+		return HALMAC_RET_PLATFORM_API_NULL;
+
+	if (!pltfm_api->MSG_PRINT)
+		return HALMAC_RET_PLATFORM_API_NULL;
+
+	if (intf == HALMAC_INTERFACE_SDIO) {
+		if (!pltfm_api->SDIO_CMD52_READ) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-r\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->SDIO_CMD53_READ_8) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-r8\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->SDIO_CMD53_READ_16) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-r16\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->SDIO_CMD53_READ_32) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-r32\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->SDIO_CMD53_READ_N) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-rn\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->SDIO_CMD52_WRITE) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-w\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->SDIO_CMD53_WRITE_8) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-w8\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->SDIO_CMD53_WRITE_16) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-w16\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->SDIO_CMD53_WRITE_32) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-w32\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->SDIO_CMD52_CIA_READ) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]sdio-cia\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+	}
+
+	if (intf == HALMAC_INTERFACE_USB || intf == HALMAC_INTERFACE_PCIE) {
+		if (!pltfm_api->REG_READ_8) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]reg-r8\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->REG_READ_16) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]reg-r16\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->REG_READ_32) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]reg-r32\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->REG_WRITE_8) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]reg-w8\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->REG_WRITE_16) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]reg-w16\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+		if (!pltfm_api->REG_WRITE_32) {
+			pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+					     HALMAC_DBG_ERR, "[ERR]reg-w32\n");
+			return HALMAC_RET_PLATFORM_API_NULL;
+		}
+	}
+
+	if (!pltfm_api->RTL_FREE) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]mem-free\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+
+	if (!pltfm_api->RTL_MALLOC) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]mem-malloc\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+	if (!pltfm_api->RTL_MEMCPY) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]mem-cpy\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+	if (!pltfm_api->RTL_MEMSET) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]mem-set\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+	if (!pltfm_api->RTL_DELAY_US) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]time-delay\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+
+	if (!pltfm_api->MUTEX_INIT) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]mutex-init\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+	if (!pltfm_api->MUTEX_DEINIT) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]mutex-deinit\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+	if (!pltfm_api->MUTEX_LOCK) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]mutex-lock\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+	if (!pltfm_api->MUTEX_UNLOCK) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]mutex-unlock\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+	if (!pltfm_api->EVENT_INDICATION) {
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]event-indication\n");
+		return HALMAC_RET_PLATFORM_API_NULL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_get_version() - get HALMAC version
+ * @version : return version of major, prototype and minor information
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+halmac_get_version(struct halmac_ver *version)
+{
+	version->major_ver = (u8)HALMAC_MAJOR_VER;
+	version->prototype_ver = (u8)HALMAC_PROTOTYPE_VER;
+	version->minor_ver = (u8)HALMAC_MINOR_VER;
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+get_chip_info(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+	      enum halmac_interface intf, struct halmac_adapter *adapter)
+{
+	u8 chip_id;
+	u8 chip_ver;
+	u32 cnt;
+
+	if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+		pltfm_reg_w8_sdio(drv_adapter, pltfm_api, REG_SDIO_HSUS_CTRL,
+				  pltfm_reg_r8_sdio(drv_adapter, pltfm_api,
+						    REG_SDIO_HSUS_CTRL) &
+						    ~(BIT(0)));
+
+		cnt = 10000;
+		while (!(pltfm_reg_r8_sdio(drv_adapter, pltfm_api,
+					   REG_SDIO_HSUS_CTRL) & BIT(1))) {
+			cnt--;
+			if (cnt == 0)
+				return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
+		}
+
+		chip_id = pltfm_reg_r_indir_sdio(drv_adapter, pltfm_api,
+						 REG_SYS_CFG2);
+		chip_ver = pltfm_reg_r_indir_sdio(drv_adapter, pltfm_api,
+						  REG_SYS_CFG1 + 1) >> 4;
+	} else {
+		chip_id = pltfm_api->REG_READ_8(drv_adapter, REG_SYS_CFG2);
+		chip_ver = pltfm_api->REG_READ_8(drv_adapter,
+						 REG_SYS_CFG1 + 1) >> 4;
+	}
+
+	adapter->chip_ver = (enum halmac_chip_ver)chip_ver;
+
+	if (chip_id == CHIP_ID_HW_DEF_8822B) {
+		adapter->chip_id = HALMAC_CHIP_ID_8822B;
+	} else if (chip_id == CHIP_ID_HW_DEF_8821C) {
+		adapter->chip_id = HALMAC_CHIP_ID_8821C;
+	} else if (chip_id == CHIP_ID_HW_DEF_8814B) {
+		adapter->chip_id = HALMAC_CHIP_ID_8814B;
+	} else if (chip_id == CHIP_ID_HW_DEF_8197F) {
+		adapter->chip_id = HALMAC_CHIP_ID_8197F;
+	} else if (chip_id == CHIP_ID_HW_DEF_8822C) {
+		adapter->chip_id = HALMAC_CHIP_ID_8822C;
+	} else {
+		adapter->chip_id = HALMAC_CHIP_ID_UNDEFINE;
+		PLTFM_MSG_ERR("[ERR]Chip id is undefined\n");
+		return HALMAC_RET_CHIP_NOT_SUPPORT;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static u8
+pltfm_reg_r8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+		  u32 offset)
+{
+	u8 value8;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if (0 == (offset & 0xFFFF0000))
+		offset |= WLAN_IOREG_OFFSET;
+
+	status = cnv_to_sdio_bus_offset(&offset);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	value8 = pltfm_api->SDIO_CMD52_READ(drv_adapter, offset);
+
+	return value8;
+}
+
+static enum halmac_ret_status
+pltfm_reg_w8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+		  u32 offset, u8 data)
+{
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	if (0 == (offset & 0xFFFF0000))
+		offset |= WLAN_IOREG_OFFSET;
+
+	status = cnv_to_sdio_bus_offset(&offset);
+
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	pltfm_api->SDIO_CMD52_WRITE(drv_adapter, offset, data);
+
+	return HALMAC_RET_SUCCESS;
+}
+
+static u8
+pltfm_reg_r_indir_sdio(VOID *drv_adapter, struct halmac_platform_api *pltfm_api,
+		       u32 offset)
+{
+	u8 value8, tmp, cnt = 50;
+	u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
+	u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+	status = cnv_to_sdio_bus_offset(&reg_cfg);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+	status = cnv_to_sdio_bus_offset(&reg_data);
+	if (status != HALMAC_RET_SUCCESS)
+		return status;
+
+	pltfm_api->SDIO_CMD52_WRITE(drv_adapter, reg_cfg, (u8)offset);
+	pltfm_api->SDIO_CMD52_WRITE(drv_adapter, reg_cfg + 1,
+				    (u8)(offset >> 8));
+	pltfm_api->SDIO_CMD52_WRITE(drv_adapter, reg_cfg + 2,
+				    (u8)(BIT(3) | BIT(4)));
+
+	do {
+		tmp = pltfm_api->SDIO_CMD52_READ(drv_adapter, reg_cfg + 2);
+		cnt--;
+	} while (((tmp & BIT(4)) == 0) && (cnt > 0));
+
+	if (((cnt & BIT(4)) == 0) && cnt == 0)
+		pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+				     HALMAC_DBG_ERR, "[ERR]sdio indir read\n");
+
+	value8 = pltfm_api->SDIO_CMD52_READ(drv_adapter, reg_data);
+
+	return value8;
+}
+
+/*Note: copy from cnv_to_sdio_bus_offset_88xx*/
+static enum halmac_ret_status
+cnv_to_sdio_bus_offset(u32 *offset)
+{
+	switch ((*offset) & 0xFFFF0000) {
+	case WLAN_IOREG_OFFSET:
+		*offset &= HALMAC_WLAN_MAC_REG_MSK;
+		*offset |= HALMAC_SDIO_CMD_ADDR_MAC_REG << 13;
+		break;
+	case SDIO_LOCAL_OFFSET:
+		*offset &= HALMAC_SDIO_LOCAL_MSK;
+		*offset |= HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13;
+		break;
+	default:
+		*offset = 0xFFFFFFFF;
+		return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL;
+	}
+
+	return HALMAC_RET_SUCCESS;
+}
+

hal/halmac/halmac_api.h

@@ -0,0 +1,119 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_API_H_
+#define _HALMAC_API_H_
+
+#define HALMAC_SVN_VER  "11692M"
+
+#define HALMAC_MAJOR_VER        0x0001
+#define HALMAC_PROTOTYPE_VER    0x0004
+#define HALMAC_MINOR_VER        0x0008
+#define HALMAC_PATCH_VER        0x0003
+
+#define HALMAC_88XX_SUPPORT	(HALMAC_8821C_SUPPORT || \
+				 HALMAC_8822B_SUPPORT || \
+				 HALMAC_8822C_SUPPORT)
+
+#define HALMAC_88XX_V1_SUPPORT	HALMAC_8814B_SUPPORT
+
+#include "halmac_2_platform.h"
+#include "halmac_type.h"
+#include "halmac_hw_cfg.h"
+#include "halmac_usb_reg.h"
+#include "halmac_sdio_reg.h"
+#include "halmac_pcie_reg.h"
+#include "halmac_bit2.h"
+#include "halmac_reg2.h"
+
+#if HALMAC_PLATFORM_TESTPROGRAM
+#include "halmac_type_testprogram.h"
+#endif
+
+#ifndef HALMAC_USE_TYPEDEF
+#define HALMAC_USE_TYPEDEF	1
+#endif
+
+#if HALMAC_USE_TYPEDEF
+#include "halmac_typedef.h"
+#endif
+
+#if HALMAC_8822B_SUPPORT
+#include "halmac_reg_8822b.h"
+#include "halmac_bit_8822b.h"
+#endif
+
+#if HALMAC_8821C_SUPPORT
+#include "halmac_reg_8821c.h"
+#include "halmac_bit_8821c.h"
+#endif
+
+#if HALMAC_8814B_SUPPORT
+#include "halmac_reg_8814b.h"
+#include "halmac_bit_8814b.h"
+#endif
+
+#if HALMAC_8822C_SUPPORT
+#include "halmac_reg_8822c.h"
+#include "halmac_bit_8822c.h"
+#endif
+
+#if (HALMAC_PLATFORM_WINDOWS || HALMAC_PLATFORM_LINUX)
+#include "halmac_tx_desc_nic.h"
+#include "halmac_tx_desc_buffer_nic.h"
+#include "halmac_tx_desc_ie_nic.h"
+#include "halmac_rx_desc_nic.h"
+#include "halmac_tx_bd_nic.h"
+#include "halmac_rx_bd_nic.h"
+#include "halmac_fw_offload_c2h_nic.h"
+#include "halmac_fw_offload_h2c_nic.h"
+#include "halmac_h2c_extra_info_nic.h"
+#include "halmac_original_c2h_nic.h"
+#include "halmac_original_h2c_nic.h"
+#endif
+
+#if (HALMAC_PLATFORM_AP)
+#include "halmac_rx_desc_ap.h"
+#include "halmac_tx_desc_ap.h"
+#include "halmac_tx_desc_buffer_ap.h"
+#include "halmac_tx_desc_ie_ap.h"
+#include "halmac_fw_offload_c2h_ap.h"
+#include "halmac_fw_offload_h2c_ap.h"
+#include "halmac_h2c_extra_info_ap.h"
+#include "halmac_original_c2h_ap.h"
+#include "halmac_original_h2c_ap.h"
+#endif
+
+#include "halmac_tx_desc_chip.h"
+#include "halmac_rx_desc_chip.h"
+#include "halmac_tx_desc_buffer_chip.h"
+#include "halmac_tx_desc_ie_chip.h"
+
+enum halmac_ret_status
+halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+		    enum halmac_interface intf,
+		    struct halmac_adapter **halmac_adapter,
+		    struct halmac_api **halmac_api);
+
+enum halmac_ret_status
+halmac_deinit_adapter(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+halmac_halt_api(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+halmac_get_version(struct halmac_ver *version);
+
+#endif

hal/halmac/halmac_fw_info.h

@@ -0,0 +1,119 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_FW_INFO_H_
+#define _HALMAC_FW_INFO_H_
+
+#define H2C_FORMAT_VERSION		11
+
+/* FW bin information */
+#define WLAN_FW_HDR_SIZE		64
+#define WLAN_FW_HDR_CHKSUM_SIZE		8
+
+#define WLAN_FW_HDR_VERSION		4
+#define WLAN_FW_HDR_SUBVERSION		6
+#define WLAN_FW_HDR_SUBINDEX		7
+#define WLAN_FW_HDR_MONTH		16
+#define WLAN_FW_HDR_DATE		17
+#define WLAN_FW_HDR_HOUR		18
+#define WLAN_FW_HDR_MIN			19
+#define WLAN_FW_HDR_YEAR		20
+#define WLAN_FW_HDR_MEM_USAGE		24
+#define WLAN_FW_HDR_H2C_FMT_VER		28
+#define WLAN_FW_HDR_DMEM_ADDR		32
+#define WLAN_FW_HDR_DMEM_SIZE		36
+#define WLAN_FW_HDR_IMEM_SIZE		48
+#define WLAN_FW_HDR_EMEM_SIZE		52
+#define WLAN_FW_HDR_EMEM_ADDR		56
+#define WLAN_FW_HDR_IMEM_ADDR		60
+
+#define H2C_ACK_HDR_CONTENT_LENGTH		8
+#define CFG_PARAMETER_ACK_CONTENT_LENGTH	16
+#define SCAN_STATUS_RPT_CONTENT_LENGTH		4
+#define C2H_DBG_HDR_LEN				4
+#define C2H_DBG_CONTENT_MAX_LENGTH		228
+#define C2H_DBG_CONTENT_SEQ_OFFSET		1
+
+/* Rename from FW SysHalCom_Debug_RAM.h */
+#define FW_REG_H2CPKT_DONE_SEQ		0x1C8
+#define FW_REG_WOW_REASON		0x1C7
+
+enum halmac_data_type {
+	HALMAC_DATA_TYPE_MAC_REG = 0x00,
+	HALMAC_DATA_TYPE_BB_REG = 0x01,
+	HALMAC_DATA_TYPE_RADIO_A = 0x02,
+	HALMAC_DATA_TYPE_RADIO_B = 0x03,
+	HALMAC_DATA_TYPE_RADIO_C = 0x04,
+	HALMAC_DATA_TYPE_RADIO_D = 0x05,
+
+	HALMAC_DATA_TYPE_DRV_DEFINE_0 = 0x80,
+	HALMAC_DATA_TYPE_DRV_DEFINE_1 = 0x81,
+	HALMAC_DATA_TYPE_DRV_DEFINE_2 = 0x82,
+	HALMAC_DATA_TYPE_DRV_DEFINE_3 = 0x83,
+	HALMAC_DATA_TYPE_UNDEFINE = 0x7FFFFFFF,
+};
+
+enum halmac_packet_id {
+	HALMAC_PACKET_PROBE_REQ = 0x00,
+	HALMAC_PACKET_SYNC_BCN = 0x01,
+	HALMAC_PACKET_DISCOVERY_BCN = 0x02,
+	HALMAC_PACKET_UNDEFINE = 0x7FFFFFFF,
+};
+
+enum halmac_cs_action_id {
+	HALMAC_CS_ACTION_NONE = 0x00,
+	HALMAC_CS_ACTIVE_SCAN = 0x01,
+	HALMAC_CS_NAN_NONMASTER_DW = 0x02,
+	HALMAC_CS_NAN_NONMASTER_NONDW = 0x03,
+	HALMAC_CS_NAN_MASTER_NONDW = 0x04,
+	HALMAC_CS_NAN_MASTER_DW = 0x05,
+	HALMAC_CS_ACTION_UNDEFINE = 0x7FFFFFFF,
+};
+
+enum halmac_cs_extra_action_id {
+	HALMAC_CS_EXTRA_ACTION_NONE = 0x00,
+	HALMAC_CS_EXTRA_UPDATE_PROBE = 0x01,
+	HALMAC_CS_EXTRA_UPDATE_BEACON = 0x02,
+	HALMAC_CS_EXTRA_ACTION_UNDEFINE = 0x7FFFFFFF,
+};
+
+enum halmac_h2c_return_code {
+	HALMAC_H2C_RETURN_SUCCESS = 0x00,
+	HALMAC_H2C_RETURN_CFG_ERR_LEN = 0x01,
+	HALMAC_H2C_RETURN_CFG_ERR_CMD = 0x02,
+	HALMAC_H2C_RETURN_EFUSE_ERR_DUMP = 0x03,
+	HALMAC_H2C_RETURN_DATAPACK_ERR_FULL = 0x04,
+	HALMAC_H2C_RETURN_DATAPACK_ERR_ID = 0x05,
+	HALMAC_H2C_RETURN_RUN_ERR_EMPTY = 0x06,
+	HALMAC_H2C_RETURN_RUN_ERR_LEN = 0x07,
+	HALMAC_H2C_RETURN_RUN_ERR_CMD = 0x08,
+	HALMAC_H2C_RETURN_RUN_ERR_ID = 0x09,
+	HALMAC_H2C_RETURN_PACKET_ERR_FULL = 0x0A,
+	HALMAC_H2C_RETURN_PACKET_ERR_ID = 0x0B,
+	HALMAC_H2C_RETURN_SCAN_ERR_FULL = 0x0C,
+	HALMAC_H2C_RETURN_SCAN_ERR_PHYDM = 0x0D,
+	HALMAC_H2C_RETURN_ORIG_ERR_ID = 0x0E,
+	HALMAC_H2C_RETURN_UNDEFINE = 0x7FFFFFFF,
+};
+
+enum halmac_scan_report_code {
+	HALMAC_SCAN_REPORT_DONE	= 0x00,
+	HALMAC_SCAN_REPORT_ERR_PHYDM = 0x01,
+	HALMAC_SCAN_REPORT_ERR_ID = 0x02,
+	HALMAC_SCAN_REPORT_ERR_TX = 0x03,
+	HALMAC_SCAN_REPORT_UNDEFINE = 0x7FFFFFFF,
+};
+
+#endif

hal/halmac/halmac_fw_offload_c2h_ap.h

@@ -0,0 +1,506 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_AP_H_
+#define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_AP_H_
+#define C2H_SUB_CMD_ID_C2H_DBG 0X00
+#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02
+#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03
+#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01
+#define C2H_SUB_CMD_ID_CFG_PARAM_ACK 0X01
+#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01
+#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01
+#define C2H_SUB_CMD_ID_UPDATE_PKT_ACK 0X01
+#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01
+#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01
+#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01
+#define C2H_SUB_CMD_ID_IQK_ACK 0X01
+#define C2H_SUB_CMD_ID_PWR_TRK_ACK 0X01
+#define C2H_SUB_CMD_ID_PSD_ACK 0X01
+#define C2H_SUB_CMD_ID_PSD_DATA 0X04
+#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
+#define C2H_SUB_CMD_ID_IQK_DATA 0X06
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A
+#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B
+#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C
+#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E
+#define C2H_SUB_CMD_ID_CCX_RPT 0X0F
+#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10
+#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11
+#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C
+#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D
+#define C2H_SUB_CMD_ID_FW_DBG_MSG 0XFF
+#define C2H_SUB_CMD_ID_FW_SNDING_ACK 0X01
+#define C2H_SUB_CMD_ID_FW_FWCTRL_RPT 0X1F
+#define C2H_SUB_CMD_ID_H2C_LOOPBACK_ACK 0X20
+#define C2H_SUB_CMD_ID_FWCMD_LOOPBACK_ACK 0X21
+#define H2C_SUB_CMD_ID_CFG_PARAM_ACK SUB_CMD_ID_CFG_PARAM
+#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX
+#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE
+#define H2C_SUB_CMD_ID_UPDATE_PKT_ACK SUB_CMD_ID_UPDATE_PKT
+#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK
+#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK
+#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH
+#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK
+#define H2C_SUB_CMD_ID_PWR_TRK_ACK SUB_CMD_ID_PWR_TRK
+#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD
+#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT
+#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG
+#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING
+#define H2C_SUB_CMD_ID_FW_FWCTRL_RPT SUB_CMD_ID_FW_FWCTRL_RPT
+#define H2C_SUB_CMD_ID_H2C_LOOPBACK_ACK SUB_CMD_ID_H2C_LOOPBACK
+#define H2C_SUB_CMD_ID_FWCMD_LOOPBACK_ACK SUB_CMD_ID_FWCMD_LOOPBACK
+#define H2C_CMD_ID_CFG_PARAM_ACK 0XFF
+#define H2C_CMD_ID_BT_COEX_ACK 0XFF
+#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF
+#define H2C_CMD_ID_UPDATE_PKT_ACK 0XFF
+#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF
+#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF
+#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF
+#define H2C_CMD_ID_IQK_ACK 0XFF
+#define H2C_CMD_ID_PWR_TRK_ACK 0XFF
+#define H2C_CMD_ID_PSD_ACK 0XFF
+#define H2C_CMD_ID_CCX_RPT 0XFF
+#define H2C_CMD_ID_FW_DBG_MSG 0XFF
+#define H2C_CMD_ID_FW_SNDING_ACK 0XFF
+#define H2C_CMD_ID_FW_FWCTRL_RPT 0XFF
+#define H2C_CMD_ID_H2C_LOOPBACK_ACK 0XFF
+#define H2C_CMD_ID_FWCMD_LOOPBACK_ACK 0XFF
+#define C2H_HDR_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_HDR_SET_CMD_ID(c2h_pkt, value)                                     \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_HDR_SET_CMD_ID_NO_CLR(c2h_pkt, value)                              \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_HDR_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_HDR_SET_SEQ(c2h_pkt, value)                                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_HDR_SET_SEQ_NO_CLR(c2h_pkt, value)                                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define C2H_HDR_SET_C2H_SUB_CMD_ID(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_HDR_SET_C2H_SUB_CMD_ID_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_HDR_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define C2H_HDR_SET_LEN(c2h_pkt, value)                                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_HDR_SET_LEN_NO_CLR(c2h_pkt, value)                                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_DBG_GET_DBG_MSG(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define C2H_DBG_SET_DBG_MSG(c2h_pkt, value)                                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_DBG_SET_DBG_MSG_NO_CLR(c2h_pkt, value)                             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define BT_COEX_INFO_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define BT_COEX_INFO_SET_DATA_START(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define BT_COEX_INFO_SET_DATA_START_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(c2h_pkt)                           \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(c2h_pkt, value)                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE_NO_CLR(c2h_pkt, value)             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define SCAN_STATUS_RPT_GET_H2C_SEQ(c2h_pkt)                                   \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
+#define SCAN_STATUS_RPT_SET_H2C_SEQ(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define SCAN_STATUS_RPT_SET_H2C_SEQ_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define H2C_ACK_HDR_SET_H2C_RETURN_CODE_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define H2C_ACK_HDR_GET_H2C_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define H2C_ACK_HDR_SET_H2C_CMD_ID(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define H2C_ACK_HDR_SET_H2C_CMD_ID_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(c2h_pkt)                                \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
+#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(c2h_pkt, value)                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID_NO_CLR(c2h_pkt, value)                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_ACK_HDR_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 16)
+#define H2C_ACK_HDR_SET_H2C_SEQ(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 16, value)
+#define H2C_ACK_HDR_SET_H2C_SEQ_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 16, value)
+#define CFG_PARAM_ACK_GET_OFFSET_ACCUMULATION(c2h_pkt)                         \
+	GET_C2H_FIELD(c2h_pkt + 0XC, 0, 32)
+#define CFG_PARAM_ACK_SET_OFFSET_ACCUMULATION(c2h_pkt, value)                  \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 32, value)
+#define CFG_PARAM_ACK_SET_OFFSET_ACCUMULATION_NO_CLR(c2h_pkt, value)           \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 32, value)
+#define CFG_PARAM_ACK_GET_VALUE_ACCUMULATION(c2h_pkt)                          \
+	GET_C2H_FIELD(c2h_pkt + 0X10, 0, 32)
+#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION(c2h_pkt, value)                   \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 0, 32, value)
+#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION_NO_CLR(c2h_pkt, value)            \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 0, 32, value)
+#define BT_COEX_ACK_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 0, 8)
+#define BT_COEX_ACK_SET_DATA_START(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 8, value)
+#define BT_COEX_ACK_SET_DATA_START_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 8, value)
+#define PSD_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7)
+#define PSD_DATA_SET_SEGMENT_ID(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value)
+#define PSD_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value)
+#define PSD_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1)
+#define PSD_DATA_SET_END_SEGMENT(c2h_pkt, value)                               \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value)
+#define PSD_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value)                        \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value)
+#define PSD_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define PSD_DATA_SET_SEGMENT_SIZE(c2h_pkt, value)                              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define PSD_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value)                       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define PSD_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
+#define PSD_DATA_SET_TOTAL_SIZE(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define PSD_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define PSD_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16)
+#define PSD_DATA_SET_H2C_SEQ(c2h_pkt, value)                                   \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define PSD_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value)                            \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define PSD_DATA_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)
+#define PSD_DATA_SET_DATA_START(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define PSD_DATA_SET_DATA_START_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define EFUSE_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7)
+#define EFUSE_DATA_SET_SEGMENT_ID(c2h_pkt, value)                              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value)
+#define EFUSE_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value)                       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value)
+#define EFUSE_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1)
+#define EFUSE_DATA_SET_END_SEGMENT(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value)
+#define EFUSE_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value)
+#define EFUSE_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define EFUSE_DATA_SET_SEGMENT_SIZE(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define EFUSE_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define EFUSE_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
+#define EFUSE_DATA_SET_TOTAL_SIZE(c2h_pkt, value)                              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define EFUSE_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value)                       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define EFUSE_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16)
+#define EFUSE_DATA_SET_H2C_SEQ(c2h_pkt, value)                                 \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define EFUSE_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value)                          \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define EFUSE_DATA_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)
+#define EFUSE_DATA_SET_DATA_START(c2h_pkt, value)                              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define EFUSE_DATA_SET_DATA_START_NO_CLR(c2h_pkt, value)                       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define IQK_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7)
+#define IQK_DATA_SET_SEGMENT_ID(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value)
+#define IQK_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value)
+#define IQK_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1)
+#define IQK_DATA_SET_END_SEGMENT(c2h_pkt, value)                               \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value)
+#define IQK_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value)                        \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value)
+#define IQK_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define IQK_DATA_SET_SEGMENT_SIZE(c2h_pkt, value)                              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define IQK_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value)                       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define IQK_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
+#define IQK_DATA_SET_TOTAL_SIZE(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define IQK_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define IQK_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16)
+#define IQK_DATA_SET_H2C_SEQ(c2h_pkt, value)                                   \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define IQK_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value)                            \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define IQK_DATA_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)
+#define IQK_DATA_SET_DATA_START(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define IQK_DATA_SET_DATA_START_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define CCX_RPT_GET_POLLUTED(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 0, 1)
+#define CCX_RPT_SET_POLLUTED(c2h_pkt, value)                                   \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 0, 1, value)
+#define CCX_RPT_SET_POLLUTED_NO_CLR(c2h_pkt, value)                            \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 0, 1, value)
+#define CCX_RPT_GET_RPT_SEL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 5, 3)
+#define CCX_RPT_SET_RPT_SEL(c2h_pkt, value)                                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 5, 3, value)
+#define CCX_RPT_SET_RPT_SEL_NO_CLR(c2h_pkt, value)                             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 5, 3, value)
+#define CCX_RPT_GET_QSEL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 8, 5)
+#define CCX_RPT_SET_QSEL(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 8, 5, value)
+#define CCX_RPT_SET_QSEL_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 8, 5, value)
+#define CCX_RPT_GET_MISSED_RPT_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 13, 3)
+#define CCX_RPT_SET_MISSED_RPT_NUM(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 13, 3, value)
+#define CCX_RPT_SET_MISSED_RPT_NUM_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 13, 3, value)
+#define CCX_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 16, 7)
+#define CCX_RPT_SET_MACID(c2h_pkt, value)                                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 16, 7, value)
+#define CCX_RPT_SET_MACID_NO_CLR(c2h_pkt, value)                               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 16, 7, value)
+#define CCX_RPT_GET_INITIAL_DATA_RATE(c2h_pkt)                                 \
+	GET_C2H_FIELD(c2h_pkt + 0X4, 24, 7)
+#define CCX_RPT_SET_INITIAL_DATA_RATE(c2h_pkt, value)                          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 24, 7, value)
+#define CCX_RPT_SET_INITIAL_DATA_RATE_NO_CLR(c2h_pkt, value)                   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 24, 7, value)
+#define CCX_RPT_GET_INITIAL_SGI(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 31, 1)
+#define CCX_RPT_SET_INITIAL_SGI(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 31, 1, value)
+#define CCX_RPT_SET_INITIAL_SGI_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 31, 1, value)
+#define CCX_RPT_GET_QUEUE_TIME(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16)
+#define CCX_RPT_SET_QUEUE_TIME(c2h_pkt, value)                                 \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define CCX_RPT_SET_QUEUE_TIME_NO_CLR(c2h_pkt, value)                          \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define CCX_RPT_GET_SW_DEFINE_BYTE0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)
+#define CCX_RPT_SET_SW_DEFINE_BYTE0(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define CCX_RPT_SET_SW_DEFINE_BYTE0_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define CCX_RPT_GET_RTS_RETRY_COUNT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 24, 4)
+#define CCX_RPT_SET_RTS_RETRY_COUNT(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 4, value)
+#define CCX_RPT_SET_RTS_RETRY_COUNT_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 4, value)
+#define CCX_RPT_GET_BMC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 29, 1)
+#define CCX_RPT_SET_BMC(c2h_pkt, value)                                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 29, 1, value)
+#define CCX_RPT_SET_BMC_NO_CLR(c2h_pkt, value)                                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 29, 1, value)
+#define CCX_RPT_GET_TX_STATE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 30, 2)
+#define CCX_RPT_SET_TX_STATE(c2h_pkt, value)                                   \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 30, 2, value)
+#define CCX_RPT_SET_TX_STATE_NO_CLR(c2h_pkt, value)                            \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 30, 2, value)
+#define CCX_RPT_GET_DATA_RETRY_COUNT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 0, 6)
+#define CCX_RPT_SET_DATA_RETRY_COUNT(c2h_pkt, value)                           \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 6, value)
+#define CCX_RPT_SET_DATA_RETRY_COUNT_NO_CLR(c2h_pkt, value)                    \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 6, value)
+#define CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 8, 7)
+#define CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 8, 7, value)
+#define CCX_RPT_SET_FINAL_DATA_RATE_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 8, 7, value)
+#define CCX_RPT_GET_FINAL_SGI(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 15, 1)
+#define CCX_RPT_SET_FINAL_SGI(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 15, 1, value)
+#define CCX_RPT_SET_FINAL_SGI_NO_CLR(c2h_pkt, value)                           \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 15, 1, value)
+#define CCX_RPT_GET_RF_CH_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 16, 10)
+#define CCX_RPT_SET_RF_CH_NUM(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 16, 10, value)
+#define CCX_RPT_SET_RF_CH_NUM_NO_CLR(c2h_pkt, value)                           \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 16, 10, value)
+#define CCX_RPT_GET_SC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 26, 4)
+#define CCX_RPT_SET_SC(c2h_pkt, value)                                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 26, 4, value)
+#define CCX_RPT_SET_SC_NO_CLR(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 26, 4, value)
+#define CCX_RPT_GET_BW(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 30, 2)
+#define CCX_RPT_SET_BW(c2h_pkt, value)                                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 30, 2, value)
+#define CCX_RPT_SET_BW_NO_CLR(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 30, 2, value)
+#define FW_DBG_MSG_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define FW_DBG_MSG_SET_CMD_ID(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define FW_DBG_MSG_SET_CMD_ID_NO_CLR(c2h_pkt, value)                           \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define FW_DBG_MSG_GET_C2H_SUB_CMD_ID(c2h_pkt)                                 \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define FW_DBG_MSG_SET_C2H_SUB_CMD_ID(c2h_pkt, value)                          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define FW_DBG_MSG_SET_C2H_SUB_CMD_ID_NO_CLR(c2h_pkt, value)                   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define FW_DBG_MSG_GET_FULL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 1)
+#define FW_DBG_MSG_SET_FULL(c2h_pkt, value)                                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 1, value)
+#define FW_DBG_MSG_SET_FULL_NO_CLR(c2h_pkt, value)                             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 1, value)
+#define FW_DBG_MSG_GET_OWN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 31, 1)
+#define FW_DBG_MSG_SET_OWN(c2h_pkt, value)                                     \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 31, 1, value)
+#define FW_DBG_MSG_SET_OWN_NO_CLR(c2h_pkt, value)                              \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 31, 1, value)
+#define FW_FWCTRL_RPT_GET_EVT_TYPE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define FW_FWCTRL_RPT_SET_EVT_TYPE(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define FW_FWCTRL_RPT_SET_EVT_TYPE_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define FW_FWCTRL_RPT_GET_LENGTH(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define FW_FWCTRL_RPT_SET_LENGTH(c2h_pkt, value)                               \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define FW_FWCTRL_RPT_SET_LENGTH_NO_CLR(c2h_pkt, value)                        \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define FW_FWCTRL_RPT_GET_SEQ_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define FW_FWCTRL_RPT_SET_SEQ_NUM(c2h_pkt, value)                              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define FW_FWCTRL_RPT_SET_SEQ_NUM_NO_CLR(c2h_pkt, value)                       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define FW_FWCTRL_RPT_GET_IS_ACK(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 1)
+#define FW_FWCTRL_RPT_SET_IS_ACK(c2h_pkt, value)                               \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 1, value)
+#define FW_FWCTRL_RPT_SET_IS_ACK_NO_CLR(c2h_pkt, value)                        \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 1, value)
+#define FW_FWCTRL_RPT_GET_MORE_CONTENT(c2h_pkt)                                \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 25, 1)
+#define FW_FWCTRL_RPT_SET_MORE_CONTENT(c2h_pkt, value)                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 25, 1, value)
+#define FW_FWCTRL_RPT_SET_MORE_CONTENT_NO_CLR(c2h_pkt, value)                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 25, 1, value)
+#define FW_FWCTRL_RPT_GET_CONTENT_IDX(c2h_pkt)                                 \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 26, 6)
+#define FW_FWCTRL_RPT_SET_CONTENT_IDX(c2h_pkt, value)                          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 26, 6, value)
+#define FW_FWCTRL_RPT_SET_CONTENT_IDX_NO_CLR(c2h_pkt, value)                   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 26, 6, value)
+#define FW_FWCTRL_RPT_GET_CLASS_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define FW_FWCTRL_RPT_SET_CLASS_ID(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define FW_FWCTRL_RPT_SET_CLASS_ID_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define FW_FWCTRL_RPT_GET_CONTENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
+#define FW_FWCTRL_RPT_SET_CONTENT(c2h_pkt, value)                              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define FW_FWCTRL_RPT_SET_CONTENT_NO_CLR(c2h_pkt, value)                       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_0_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_1_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_2_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_3_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X8, 0, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_4_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X8, 8, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 8, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_5_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 8, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_6_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X8, 24, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_7_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt)                             \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value)                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_0_NO_CLR(c2h_pkt, value)               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt)                             \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value)                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_1_NO_CLR(c2h_pkt, value)               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt)                             \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value)                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_2_NO_CLR(c2h_pkt, value)               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt)                             \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value)                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_3_NO_CLR(c2h_pkt, value)               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt)                             \
+	GET_C2H_FIELD(c2h_pkt + 0X8, 0, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value)                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_4_NO_CLR(c2h_pkt, value)               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt)                             \
+	GET_C2H_FIELD(c2h_pkt + 0X8, 8, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value)                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 8, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_5_NO_CLR(c2h_pkt, value)               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 8, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt)                             \
+	GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value)                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_6_NO_CLR(c2h_pkt, value)               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt)                             \
+	GET_C2H_FIELD(c2h_pkt + 0X8, 24, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value)                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7_NO_CLR(c2h_pkt, value)               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 8, value)
+#endif

hal/halmac/halmac_fw_offload_c2h_nic.h

@@ -0,0 +1,371 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_
+#define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_
+#define C2H_SUB_CMD_ID_C2H_DBG 0X00
+#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02
+#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03
+#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01
+#define C2H_SUB_CMD_ID_CFG_PARAM_ACK 0X01
+#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01
+#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01
+#define C2H_SUB_CMD_ID_UPDATE_PKT_ACK 0X01
+#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01
+#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01
+#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01
+#define C2H_SUB_CMD_ID_IQK_ACK 0X01
+#define C2H_SUB_CMD_ID_PWR_TRK_ACK 0X01
+#define C2H_SUB_CMD_ID_PSD_ACK 0X01
+#define C2H_SUB_CMD_ID_PSD_DATA 0X04
+#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
+#define C2H_SUB_CMD_ID_IQK_DATA 0X06
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A
+#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B
+#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C
+#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E
+#define C2H_SUB_CMD_ID_CCX_RPT 0X0F
+#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10
+#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11
+#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C
+#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D
+#define C2H_SUB_CMD_ID_FW_DBG_MSG 0XFF
+#define C2H_SUB_CMD_ID_FW_SNDING_ACK 0X01
+#define C2H_SUB_CMD_ID_FW_FWCTRL_RPT 0X1F
+#define C2H_SUB_CMD_ID_H2C_LOOPBACK_ACK 0X20
+#define C2H_SUB_CMD_ID_FWCMD_LOOPBACK_ACK 0X21
+#define H2C_SUB_CMD_ID_CFG_PARAM_ACK SUB_CMD_ID_CFG_PARAM
+#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX
+#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE
+#define H2C_SUB_CMD_ID_UPDATE_PKT_ACK SUB_CMD_ID_UPDATE_PKT
+#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK
+#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK
+#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH
+#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK
+#define H2C_SUB_CMD_ID_PWR_TRK_ACK SUB_CMD_ID_PWR_TRK
+#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD
+#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT
+#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG
+#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING
+#define H2C_SUB_CMD_ID_FW_FWCTRL_RPT SUB_CMD_ID_FW_FWCTRL_RPT
+#define H2C_SUB_CMD_ID_H2C_LOOPBACK_ACK SUB_CMD_ID_H2C_LOOPBACK
+#define H2C_SUB_CMD_ID_FWCMD_LOOPBACK_ACK SUB_CMD_ID_FWCMD_LOOPBACK
+#define H2C_CMD_ID_CFG_PARAM_ACK 0XFF
+#define H2C_CMD_ID_BT_COEX_ACK 0XFF
+#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF
+#define H2C_CMD_ID_UPDATE_PKT_ACK 0XFF
+#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF
+#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF
+#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF
+#define H2C_CMD_ID_IQK_ACK 0XFF
+#define H2C_CMD_ID_PWR_TRK_ACK 0XFF
+#define H2C_CMD_ID_PSD_ACK 0XFF
+#define H2C_CMD_ID_CCX_RPT 0XFF
+#define H2C_CMD_ID_FW_DBG_MSG 0XFF
+#define H2C_CMD_ID_FW_SNDING_ACK 0XFF
+#define H2C_CMD_ID_FW_FWCTRL_RPT 0XFF
+#define H2C_CMD_ID_H2C_LOOPBACK_ACK 0XFF
+#define H2C_CMD_ID_FWCMD_LOOPBACK_ACK 0XFF
+#define C2H_HDR_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_HDR_SET_CMD_ID(c2h_pkt, value)                                     \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_HDR_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_HDR_SET_SEQ(c2h_pkt, value)                                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define C2H_HDR_SET_C2H_SUB_CMD_ID(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_HDR_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define C2H_HDR_SET_LEN(c2h_pkt, value)                                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_DBG_GET_DBG_MSG(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define C2H_DBG_SET_DBG_MSG(c2h_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define BT_COEX_INFO_GET_DATA_START(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define BT_COEX_INFO_SET_DATA_START(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(c2h_pkt)                           \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(c2h_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define SCAN_STATUS_RPT_GET_H2C_SEQ(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
+#define SCAN_STATUS_RPT_SET_H2C_SEQ(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define H2C_ACK_HDR_GET_H2C_CMD_ID(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define H2C_ACK_HDR_SET_H2C_CMD_ID(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(c2h_pkt)                                \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
+#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(c2h_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_ACK_HDR_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 16)
+#define H2C_ACK_HDR_SET_H2C_SEQ(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 16, value)
+#define CFG_PARAM_ACK_GET_OFFSET_ACCUMULATION(c2h_pkt)                         \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 32)
+#define CFG_PARAM_ACK_SET_OFFSET_ACCUMULATION(c2h_pkt, value)                  \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 32, value)
+#define CFG_PARAM_ACK_GET_VALUE_ACCUMULATION(c2h_pkt)                          \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 0, 32)
+#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION(c2h_pkt, value)                   \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 0, 32, value)
+#define BT_COEX_ACK_GET_DATA_START(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 8)
+#define BT_COEX_ACK_SET_DATA_START(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 8, value)
+#define PSD_DATA_GET_SEGMENT_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7)
+#define PSD_DATA_SET_SEGMENT_ID(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value)
+#define PSD_DATA_GET_END_SEGMENT(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1)
+#define PSD_DATA_SET_END_SEGMENT(c2h_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value)
+#define PSD_DATA_GET_SEGMENT_SIZE(c2h_pkt)                                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define PSD_DATA_SET_SEGMENT_SIZE(c2h_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define PSD_DATA_GET_TOTAL_SIZE(c2h_pkt)                                       \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
+#define PSD_DATA_SET_TOTAL_SIZE(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
+#define PSD_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16)
+#define PSD_DATA_SET_H2C_SEQ(c2h_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value)
+#define PSD_DATA_GET_DATA_START(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)
+#define PSD_DATA_SET_DATA_START(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)
+#define EFUSE_DATA_GET_SEGMENT_ID(c2h_pkt)                                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7)
+#define EFUSE_DATA_SET_SEGMENT_ID(c2h_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value)
+#define EFUSE_DATA_GET_END_SEGMENT(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1)
+#define EFUSE_DATA_SET_END_SEGMENT(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value)
+#define EFUSE_DATA_GET_SEGMENT_SIZE(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define EFUSE_DATA_SET_SEGMENT_SIZE(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define EFUSE_DATA_GET_TOTAL_SIZE(c2h_pkt)                                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
+#define EFUSE_DATA_SET_TOTAL_SIZE(c2h_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
+#define EFUSE_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16)
+#define EFUSE_DATA_SET_H2C_SEQ(c2h_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value)
+#define EFUSE_DATA_GET_DATA_START(c2h_pkt)                                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)
+#define EFUSE_DATA_SET_DATA_START(c2h_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)
+#define IQK_DATA_GET_SEGMENT_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7)
+#define IQK_DATA_SET_SEGMENT_ID(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value)
+#define IQK_DATA_GET_END_SEGMENT(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1)
+#define IQK_DATA_SET_END_SEGMENT(c2h_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value)
+#define IQK_DATA_GET_SEGMENT_SIZE(c2h_pkt)                                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define IQK_DATA_SET_SEGMENT_SIZE(c2h_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define IQK_DATA_GET_TOTAL_SIZE(c2h_pkt)                                       \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
+#define IQK_DATA_SET_TOTAL_SIZE(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
+#define IQK_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16)
+#define IQK_DATA_SET_H2C_SEQ(c2h_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value)
+#define IQK_DATA_GET_DATA_START(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)
+#define IQK_DATA_SET_DATA_START(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)
+#define CCX_RPT_GET_POLLUTED(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 0, 1)
+#define CCX_RPT_SET_POLLUTED(c2h_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 0, 1, value)
+#define CCX_RPT_GET_RPT_SEL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 5, 3)
+#define CCX_RPT_SET_RPT_SEL(c2h_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 5, 3, value)
+#define CCX_RPT_GET_QSEL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 8, 5)
+#define CCX_RPT_SET_QSEL(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 8, 5, value)
+#define CCX_RPT_GET_MISSED_RPT_NUM(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 13, 3)
+#define CCX_RPT_SET_MISSED_RPT_NUM(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 13, 3, value)
+#define CCX_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 16, 7)
+#define CCX_RPT_SET_MACID(c2h_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 16, 7, value)
+#define CCX_RPT_GET_INITIAL_DATA_RATE(c2h_pkt)                                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 24, 7)
+#define CCX_RPT_SET_INITIAL_DATA_RATE(c2h_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 24, 7, value)
+#define CCX_RPT_GET_INITIAL_SGI(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 31, 1)
+#define CCX_RPT_SET_INITIAL_SGI(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 31, 1, value)
+#define CCX_RPT_GET_QUEUE_TIME(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16)
+#define CCX_RPT_SET_QUEUE_TIME(c2h_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value)
+#define CCX_RPT_GET_SW_DEFINE_BYTE0(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)
+#define CCX_RPT_SET_SW_DEFINE_BYTE0(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)
+#define CCX_RPT_GET_RTS_RETRY_COUNT(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 4)
+#define CCX_RPT_SET_RTS_RETRY_COUNT(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 4, value)
+#define CCX_RPT_GET_BMC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 29, 1)
+#define CCX_RPT_SET_BMC(c2h_pkt, value)                                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 29, 1, value)
+#define CCX_RPT_GET_TX_STATE(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 30, 2)
+#define CCX_RPT_SET_TX_STATE(c2h_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 30, 2, value)
+#define CCX_RPT_GET_DATA_RETRY_COUNT(c2h_pkt)                                  \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 6)
+#define CCX_RPT_SET_DATA_RETRY_COUNT(c2h_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 6, value)
+#define CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 8, 7)
+#define CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 8, 7, value)
+#define CCX_RPT_GET_FINAL_SGI(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 15, 1)
+#define CCX_RPT_SET_FINAL_SGI(c2h_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 15, 1, value)
+#define CCX_RPT_GET_RF_CH_NUM(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 16, 10)
+#define CCX_RPT_SET_RF_CH_NUM(c2h_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 16, 10, value)
+#define CCX_RPT_GET_SC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 26, 4)
+#define CCX_RPT_SET_SC(c2h_pkt, value)                                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 26, 4, value)
+#define CCX_RPT_GET_BW(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 30, 2)
+#define CCX_RPT_SET_BW(c2h_pkt, value)                                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 30, 2, value)
+#define FW_DBG_MSG_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define FW_DBG_MSG_SET_CMD_ID(c2h_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define FW_DBG_MSG_GET_C2H_SUB_CMD_ID(c2h_pkt)                                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define FW_DBG_MSG_SET_C2H_SUB_CMD_ID(c2h_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define FW_DBG_MSG_GET_FULL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 1)
+#define FW_DBG_MSG_SET_FULL(c2h_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 1, value)
+#define FW_DBG_MSG_GET_OWN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 31, 1)
+#define FW_DBG_MSG_SET_OWN(c2h_pkt, value)                                     \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 31, 1, value)
+#define FW_FWCTRL_RPT_GET_EVT_TYPE(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define FW_FWCTRL_RPT_SET_EVT_TYPE(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define FW_FWCTRL_RPT_GET_LENGTH(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define FW_FWCTRL_RPT_SET_LENGTH(c2h_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define FW_FWCTRL_RPT_GET_SEQ_NUM(c2h_pkt)                                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define FW_FWCTRL_RPT_SET_SEQ_NUM(c2h_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define FW_FWCTRL_RPT_GET_IS_ACK(c2h_pkt)                                      \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 1)
+#define FW_FWCTRL_RPT_SET_IS_ACK(c2h_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 1, value)
+#define FW_FWCTRL_RPT_GET_MORE_CONTENT(c2h_pkt)                                \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 25, 1)
+#define FW_FWCTRL_RPT_SET_MORE_CONTENT(c2h_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 25, 1, value)
+#define FW_FWCTRL_RPT_GET_CONTENT_IDX(c2h_pkt)                                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 26, 6)
+#define FW_FWCTRL_RPT_SET_CONTENT_IDX(c2h_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 26, 6, value)
+#define FW_FWCTRL_RPT_GET_CLASS_ID(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define FW_FWCTRL_RPT_SET_CLASS_ID(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define FW_FWCTRL_RPT_GET_CONTENT(c2h_pkt)                                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
+#define FW_FWCTRL_RPT_SET_CONTENT(c2h_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 8, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 8, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt)                             \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt)                             \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt)                             \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt)                             \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt)                             \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt)                             \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 8, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 8, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt)                             \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt)                             \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 8, value)
+#endif

hal/halmac/halmac_fw_offload_h2c_ap.h

@@ -0,0 +1,989 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_
+#define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_
+#define CMD_ID_FW_OFFLOAD_H2C 0XFF
+#define CMD_ID_CH_SWITCH 0XFF
+#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF
+#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF
+#define CMD_ID_CFG_PARAM 0XFF
+#define CMD_ID_UPDATE_DATAPACK 0XFF
+#define CMD_ID_RUN_DATAPACK 0XFF
+#define CMD_ID_DOWNLOAD_FLASH 0XFF
+#define CMD_ID_UPDATE_PKT 0XFF
+#define CMD_ID_GENERAL_INFO 0XFF
+#define CMD_ID_IQK 0XFF
+#define CMD_ID_PWR_TRK 0XFF
+#define CMD_ID_PSD 0XFF
+#define CMD_ID_P2PPS 0XFF
+#define CMD_ID_BT_COEX 0XFF
+#define CMD_ID_NAN_CTRL 0XFF
+#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF
+#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF
+#define CMD_ID_FW_ACCESS_TEST 0XFF
+#define CMD_ID_PHYDM_INFO 0XFF
+#define CMD_ID_FW_SNDING 0XFF
+#define CMD_ID_H2C_LOOPBACK 0XFF
+#define CMD_ID_FWCMD_LOOPBACK 0XFF
+#define CMD_ID_FW_FWCTRL 0XFF
+#define CATEGORY_H2C_CMD_HEADER 0X00
+#define CATEGORY_FW_OFFLOAD_H2C 0X01
+#define CATEGORY_CH_SWITCH 0X01
+#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01
+#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01
+#define CATEGORY_CFG_PARAM 0X01
+#define CATEGORY_UPDATE_DATAPACK 0X01
+#define CATEGORY_RUN_DATAPACK 0X01
+#define CATEGORY_DOWNLOAD_FLASH 0X01
+#define CATEGORY_UPDATE_PKT 0X01
+#define CATEGORY_GENERAL_INFO 0X01
+#define CATEGORY_IQK 0X01
+#define CATEGORY_PWR_TRK 0X01
+#define CATEGORY_PSD 0X01
+#define CATEGORY_P2PPS 0X01
+#define CATEGORY_BT_COEX 0X01
+#define CATEGORY_NAN_CTRL 0X01
+#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01
+#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01
+#define CATEGORY_FW_ACCESS_TEST 0X01
+#define CATEGORY_PHYDM_INFO 0X01
+#define CATEGORY_FW_SNDING 0X01
+#define CATEGORY_H2C_LOOPBACK 0X01
+#define CATEGORY_FWCMD_LOOPBACK 0X01
+#define CATEGORY_FW_FWCTRL 0X01
+#define SUB_CMD_ID_CH_SWITCH 0X02
+#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
+#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05
+#define SUB_CMD_ID_CFG_PARAM 0X08
+#define SUB_CMD_ID_UPDATE_DATAPACK 0X09
+#define SUB_CMD_ID_RUN_DATAPACK 0X0A
+#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B
+#define SUB_CMD_ID_UPDATE_PKT 0X0C
+#define SUB_CMD_ID_GENERAL_INFO 0X0D
+#define SUB_CMD_ID_IQK 0X0E
+#define SUB_CMD_ID_PWR_TRK 0X0F
+#define SUB_CMD_ID_PSD 0X10
+#define SUB_CMD_ID_P2PPS 0X24
+#define SUB_CMD_ID_BT_COEX 0X60
+#define SUB_CMD_ID_NAN_CTRL 0XB2
+#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
+#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
+#define SUB_CMD_ID_FW_ACCESS_TEST 0X00
+#define SUB_CMD_ID_PHYDM_INFO 0X11
+#define SUB_CMD_ID_FW_SNDING 0X12
+#define SUB_CMD_ID_H2C_LOOPBACK 0X14
+#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15
+#define SUB_CMD_ID_FW_FWCTRL 0X13
+#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 7)
+#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 7, value)
+#define H2C_CMD_HEADER_SET_CATEGORY_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 7, value)
+#define H2C_CMD_HEADER_GET_ACK(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 7, 1)
+#define H2C_CMD_HEADER_SET_ACK(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 7, 1, value)
+#define H2C_CMD_HEADER_SET_ACK_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 7, 1, value)
+#define H2C_CMD_HEADER_GET_TOTAL_LEN(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 0, 16)
+#define H2C_CMD_HEADER_SET_TOTAL_LEN(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 16, value)
+#define H2C_CMD_HEADER_SET_TOTAL_LEN_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 16, value)
+#define H2C_CMD_HEADER_GET_SEQ_NUM(h2c_pkt)                                    \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 16, 16)
+#define H2C_CMD_HEADER_SET_SEQ_NUM(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 16, value)
+#define H2C_CMD_HEADER_SET_SEQ_NUM_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 16, value)
+#define FW_OFFLOAD_H2C_GET_CATEGORY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 7)
+#define FW_OFFLOAD_H2C_SET_CATEGORY(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 7, value)
+#define FW_OFFLOAD_H2C_SET_CATEGORY_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 7, value)
+#define FW_OFFLOAD_H2C_GET_ACK(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 7, 1)
+#define FW_OFFLOAD_H2C_SET_ACK(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 7, 1, value)
+#define FW_OFFLOAD_H2C_SET_ACK_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 7, 1, value)
+#define FW_OFFLOAD_H2C_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define FW_OFFLOAD_H2C_SET_CMD_ID(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define FW_OFFLOAD_H2C_SET_CMD_ID_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(h2c_pkt)                                 \
+	GET_H2C_FIELD(h2c_pkt + 0X00, 16, 16)
+#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(h2c_pkt, value)                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 16, value)
+#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID_NO_CLR(h2c_pkt, value)                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 16, value)
+#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 0, 16)
+#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 16, value)
+#define FW_OFFLOAD_H2C_SET_TOTAL_LEN_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 16, value)
+#define FW_OFFLOAD_H2C_GET_SEQ_NUM(h2c_pkt)                                    \
+	GET_H2C_FIELD(h2c_pkt + 0X04, 16, 16)
+#define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 16, value)
+#define FW_OFFLOAD_H2C_SET_SEQ_NUM_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 16, value)
+#define CH_SWITCH_GET_START(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define CH_SWITCH_SET_START(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define CH_SWITCH_SET_START_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define CH_SWITCH_GET_DEST_CH_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
+#define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define CH_SWITCH_SET_DEST_CH_EN_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define CH_SWITCH_GET_ABSOLUTE_TIME(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
+#define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define CH_SWITCH_SET_ABSOLUTE_TIME_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define CH_SWITCH_GET_PERIODIC_OPT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 3, 2)
+#define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 2, value)
+#define CH_SWITCH_SET_PERIODIC_OPT_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 2, value)
+#define CH_SWITCH_GET_INFO_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define CH_SWITCH_SET_INFO_LOC_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define CH_SWITCH_GET_CH_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define CH_SWITCH_SET_CH_NUM(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define CH_SWITCH_SET_CH_NUM_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define CH_SWITCH_GET_PRI_CH_IDX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 4)
+#define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 4, value)
+#define CH_SWITCH_SET_PRI_CH_IDX_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 4, value)
+#define CH_SWITCH_GET_DEST_BW(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 28, 4)
+#define CH_SWITCH_SET_DEST_BW(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 28, 4, value)
+#define CH_SWITCH_SET_DEST_BW_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 28, 4, value)
+#define CH_SWITCH_GET_DEST_CH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)
+#define CH_SWITCH_SET_DEST_CH(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define CH_SWITCH_SET_DEST_CH_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define CH_SWITCH_GET_NORMAL_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 6)
+#define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 6, value)
+#define CH_SWITCH_SET_NORMAL_PERIOD_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 6, value)
+#define CH_SWITCH_GET_NORMAL_PERIOD_SEL(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 14, 2)
+#define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 14, 2, value)
+#define CH_SWITCH_SET_NORMAL_PERIOD_SEL_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 14, 2, value)
+#define CH_SWITCH_GET_SLOW_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 6)
+#define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 6, value)
+#define CH_SWITCH_SET_SLOW_PERIOD_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 6, value)
+#define CH_SWITCH_GET_SLOW_PERIOD_SEL(h2c_pkt)                                 \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 22, 2)
+#define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value)                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 22, 2, value)
+#define CH_SWITCH_SET_SLOW_PERIOD_SEL_NO_CLR(h2c_pkt, value)                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 22, 2, value)
+#define CH_SWITCH_GET_NORMAL_CYCLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 24, 8)
+#define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 24, 8, value)
+#define CH_SWITCH_SET_NORMAL_CYCLE_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 24, 8, value)
+#define CH_SWITCH_GET_TSF_HIGH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32)
+#define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define CH_SWITCH_SET_TSF_HIGH_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define CH_SWITCH_GET_TSF_LOW(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 0, 32)
+#define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value)
+#define CH_SWITCH_SET_TSF_LOW_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value)
+#define CH_SWITCH_GET_INFO_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 0, 16)
+#define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 16, value)
+#define CH_SWITCH_SET_INFO_SIZE_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 16, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 8, 4)
+#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 4, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 4, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 12, 4)
+#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 12, 4, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 12, 4, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(h2c_pkt)                    \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(h2c_pkt, value)             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0_NO_CLR(h2c_pkt, value)      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(h2c_pkt)                    \
+	GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(h2c_pkt, value)             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1_NO_CLR(h2c_pkt, value)      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(h2c_pkt)                    \
+	GET_H2C_FIELD(h2c_pkt + 0X14, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(h2c_pkt, value)             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2_NO_CLR(h2c_pkt, value)      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(h2c_pkt)                    \
+	GET_H2C_FIELD(h2c_pkt + 0X18, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(h2c_pkt, value)             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3_NO_CLR(h2c_pkt, value)      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(h2c_pkt)                    \
+	GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(h2c_pkt, value)             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4_NO_CLR(h2c_pkt, value)      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 32, value)
+#define CFG_PARAM_GET_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)
+#define CFG_PARAM_SET_NUM(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define CFG_PARAM_SET_NUM_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define CFG_PARAM_GET_INIT_CASE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 1)
+#define CFG_PARAM_SET_INIT_CASE(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 1, value)
+#define CFG_PARAM_SET_INIT_CASE_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 1, value)
+#define CFG_PARAM_GET_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define CFG_PARAM_SET_LOC(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define CFG_PARAM_SET_LOC_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define UPDATE_DATAPACK_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)
+#define UPDATE_DATAPACK_SET_SIZE(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define UPDATE_DATAPACK_SET_SIZE_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define UPDATE_DATAPACK_GET_DATAPACK_ID(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define UPDATE_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define UPDATE_DATAPACK_SET_DATAPACK_ID_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define UPDATE_DATAPACK_GET_DATAPACK_LOC(h2c_pkt)                              \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define UPDATE_DATAPACK_SET_DATAPACK_LOC(h2c_pkt, value)                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define UPDATE_DATAPACK_SET_DATAPACK_LOC_NO_CLR(h2c_pkt, value)                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(h2c_pkt)                          \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)
+#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(h2c_pkt, value)                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT_NO_CLR(h2c_pkt, value)            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define UPDATE_DATAPACK_GET_END_SEGMENT(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 1)
+#define UPDATE_DATAPACK_SET_END_SEGMENT(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 1, value)
+#define UPDATE_DATAPACK_SET_END_SEGMENT_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 1, value)
+#define RUN_DATAPACK_GET_DATAPACK_ID(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define RUN_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define RUN_DATAPACK_SET_DATAPACK_ID_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define DOWNLOAD_FLASH_GET_SPI_CMD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define DOWNLOAD_FLASH_SET_SPI_CMD(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define DOWNLOAD_FLASH_SET_SPI_CMD_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define DOWNLOAD_FLASH_GET_LOCATION(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 8, 16)
+#define DOWNLOAD_FLASH_SET_LOCATION(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 16, value)
+#define DOWNLOAD_FLASH_SET_LOCATION_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 16, value)
+#define DOWNLOAD_FLASH_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32)
+#define DOWNLOAD_FLASH_SET_SIZE(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value)
+#define DOWNLOAD_FLASH_SET_SIZE_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value)
+#define DOWNLOAD_FLASH_GET_START_ADDR(h2c_pkt)                                 \
+	GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32)
+#define DOWNLOAD_FLASH_SET_START_ADDR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define DOWNLOAD_FLASH_SET_START_ADDR_NO_CLR(h2c_pkt, value)                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define UPDATE_PKT_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)
+#define UPDATE_PKT_SET_SIZE(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define UPDATE_PKT_SET_SIZE_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define UPDATE_PKT_GET_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define UPDATE_PKT_SET_ID(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define UPDATE_PKT_SET_ID_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define UPDATE_PKT_GET_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define UPDATE_PKT_SET_LOC(h2c_pkt, value)                                     \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define UPDATE_PKT_SET_LOC_NO_CLR(h2c_pkt, value)                              \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define GENERAL_INFO_GET_FW_TX_BOUNDARY(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define GENERAL_INFO_SET_FW_TX_BOUNDARY_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define IQK_GET_CLEAR(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define IQK_SET_CLEAR(h2c_pkt, value)                                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define IQK_SET_CLEAR_NO_CLR(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define IQK_GET_SEGMENT_IQK(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
+#define IQK_SET_SEGMENT_IQK(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define IQK_SET_SEGMENT_IQK_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define PWR_TRK_GET_ENABLE_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define PWR_TRK_SET_ENABLE_A(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define PWR_TRK_SET_ENABLE_A_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define PWR_TRK_GET_ENABLE_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
+#define PWR_TRK_SET_ENABLE_B(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define PWR_TRK_SET_ENABLE_B_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define PWR_TRK_GET_ENABLE_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
+#define PWR_TRK_SET_ENABLE_C(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define PWR_TRK_SET_ENABLE_C_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define PWR_TRK_GET_ENABLE_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)
+#define PWR_TRK_SET_ENABLE_D(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)
+#define PWR_TRK_SET_ENABLE_D_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)
+#define PWR_TRK_GET_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 4, 3)
+#define PWR_TRK_SET_TYPE(h2c_pkt, value)                                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 3, value)
+#define PWR_TRK_SET_TYPE_NO_CLR(h2c_pkt, value)                                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 3, value)
+#define PWR_TRK_GET_BBSWING_INDEX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define PWR_TRK_SET_BBSWING_INDEX(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define PWR_TRK_SET_BBSWING_INDEX_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_A(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define PWR_TRK_SET_TX_PWR_INDEX_A_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_A(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 8, value)
+#define PWR_TRK_SET_OFFSET_VALUE_A_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_A(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 8, value)
+#define PWR_TRK_SET_TSSI_VALUE_A_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_B(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value)
+#define PWR_TRK_SET_TX_PWR_INDEX_B_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_B(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value)
+#define PWR_TRK_SET_OFFSET_VALUE_B_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_B(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 16, 8, value)
+#define PWR_TRK_SET_TSSI_VALUE_B_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 16, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_C(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 8, value)
+#define PWR_TRK_SET_TX_PWR_INDEX_C_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_C(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 8, 8, value)
+#define PWR_TRK_SET_OFFSET_VALUE_C_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_C(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 16, 8, value)
+#define PWR_TRK_SET_TSSI_VALUE_C_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 16, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_D(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value)
+#define PWR_TRK_SET_TX_PWR_INDEX_D_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_D(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value)
+#define PWR_TRK_SET_OFFSET_VALUE_D_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_D(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 16, 8, value)
+#define PWR_TRK_SET_TSSI_VALUE_D_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 16, 8, value)
+#define PSD_GET_START_PSD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)
+#define PSD_SET_START_PSD(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define PSD_SET_START_PSD_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define PSD_GET_END_PSD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 16)
+#define PSD_SET_END_PSD(h2c_pkt, value)                                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 16, value)
+#define PSD_SET_END_PSD_NO_CLR(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 16, value)
+#define P2PPS_GET_OFFLOAD_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define P2PPS_SET_OFFLOAD_EN(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define P2PPS_SET_OFFLOAD_EN_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define P2PPS_GET_ROLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
+#define P2PPS_SET_ROLE(h2c_pkt, value)                                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define P2PPS_SET_ROLE_NO_CLR(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define P2PPS_GET_CTWINDOW_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
+#define P2PPS_SET_CTWINDOW_EN(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define P2PPS_SET_CTWINDOW_EN_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define P2PPS_GET_NOA_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)
+#define P2PPS_SET_NOA_EN(h2c_pkt, value)                                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)
+#define P2PPS_SET_NOA_EN_NO_CLR(h2c_pkt, value)                                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)
+#define P2PPS_GET_NOA_SEL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 4, 1)
+#define P2PPS_SET_NOA_SEL(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 1, value)
+#define P2PPS_SET_NOA_SEL_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 1, value)
+#define P2PPS_GET_ALLSTASLEEP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 5, 1)
+#define P2PPS_SET_ALLSTASLEEP(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value)
+#define P2PPS_SET_ALLSTASLEEP_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value)
+#define P2PPS_GET_DISCOVERY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 6, 1)
+#define P2PPS_SET_DISCOVERY(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 6, 1, value)
+#define P2PPS_SET_DISCOVERY_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 6, 1, value)
+#define P2PPS_GET_DISABLE_CLOSERF(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 7, 1)
+#define P2PPS_SET_DISABLE_CLOSERF(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 7, 1, value)
+#define P2PPS_SET_DISABLE_CLOSERF_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 7, 1, value)
+#define P2PPS_GET_P2P_PORT_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define P2PPS_SET_P2P_PORT_ID(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define P2PPS_SET_P2P_PORT_ID_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define P2PPS_GET_P2P_GROUP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define P2PPS_SET_P2P_GROUP(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define P2PPS_SET_P2P_GROUP_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define P2PPS_GET_P2P_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define P2PPS_SET_P2P_MACID(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define P2PPS_SET_P2P_MACID_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define P2PPS_GET_CTWINDOW_LENGTH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)
+#define P2PPS_SET_CTWINDOW_LENGTH(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define P2PPS_SET_CTWINDOW_LENGTH_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define P2PPS_GET_NOA_DURATION_PARA(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32)
+#define P2PPS_SET_NOA_DURATION_PARA(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define P2PPS_SET_NOA_DURATION_PARA_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define P2PPS_GET_NOA_INTERVAL_PARA(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X14, 0, 32)
+#define P2PPS_SET_NOA_INTERVAL_PARA(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value)
+#define P2PPS_SET_NOA_INTERVAL_PARA_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value)
+#define P2PPS_GET_NOA_START_TIME_PARA(h2c_pkt)                                 \
+	GET_H2C_FIELD(h2c_pkt + 0X18, 0, 32)
+#define P2PPS_SET_NOA_START_TIME_PARA(h2c_pkt, value)                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 32, value)
+#define P2PPS_SET_NOA_START_TIME_PARA_NO_CLR(h2c_pkt, value)                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 32, value)
+#define P2PPS_GET_NOA_COUNT_PARA(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 32)
+#define P2PPS_SET_NOA_COUNT_PARA(h2c_pkt, value)                               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 32, value)
+#define P2PPS_SET_NOA_COUNT_PARA_NO_CLR(h2c_pkt, value)                        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 32, value)
+#define BT_COEX_GET_DATA_START(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define BT_COEX_SET_DATA_START(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define BT_COEX_SET_DATA_START_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CTRL_GET_NAN_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 2)
+#define NAN_CTRL_SET_NAN_EN(h2c_pkt, value)                                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 2, value)
+#define NAN_CTRL_SET_NAN_EN_NO_CLR(h2c_pkt, value)                             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 2, value)
+#define NAN_CTRL_GET_WARMUP_TIMER_FLAG(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
+#define NAN_CTRL_SET_WARMUP_TIMER_FLAG(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define NAN_CTRL_SET_WARMUP_TIMER_FLAG_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define NAN_CTRL_GET_SUPPORT_BAND(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 2)
+#define NAN_CTRL_SET_SUPPORT_BAND(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 2, value)
+#define NAN_CTRL_SET_SUPPORT_BAND_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 2, value)
+#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(h2c_pkt)                              \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 10, 1)
+#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(h2c_pkt, value)                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 10, 1, value)
+#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN_NO_CLR(h2c_pkt, value)                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 10, 1, value)
+#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(h2c_pkt)                              \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 11, 1)
+#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(h2c_pkt, value)                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 11, 1, value)
+#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN_NO_CLR(h2c_pkt, value)                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 11, 1, value)
+#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define NAN_CTRL_GET_CHANNEL_2G(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define NAN_CTRL_SET_CHANNEL_2G(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define NAN_CTRL_SET_CHANNEL_2G_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define NAN_CTRL_GET_CHANNEL_5G(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)
+#define NAN_CTRL_SET_CHANNEL_5G(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define NAN_CTRL_SET_CHANNEL_5G_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define NAN_CTRL_GET_MASTERPREFERENCE_VALUE(h2c_pkt)                           \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 8)
+#define NAN_CTRL_SET_MASTERPREFERENCE_VALUE(h2c_pkt, value)                    \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 8, value)
+#define NAN_CTRL_SET_MASTERPREFERENCE_VALUE_NO_CLR(h2c_pkt, value)             \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 8, value)
+#define NAN_CTRL_GET_RANDOMFACTOR_VALUE(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 8)
+#define NAN_CTRL_SET_RANDOMFACTOR_VALUE(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 8, value)
+#define NAN_CTRL_SET_RANDOMFACTOR_VALUE_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(h2c_pkt)                       \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(h2c_pkt, value)                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0_NO_CLR(h2c_pkt, value)         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(h2c_pkt)                      \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 16)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(h2c_pkt, value)               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0_NO_CLR(h2c_pkt, value)        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 16)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_0_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(h2c_pkt)                       \
+	GET_H2C_FIELD(h2c_pkt + 0X10, 0, 8)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(h2c_pkt, value)                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1_NO_CLR(h2c_pkt, value)         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X10, 8, 8)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(h2c_pkt)                      \
+	GET_H2C_FIELD(h2c_pkt + 0X14, 0, 16)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(h2c_pkt, value)               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1_NO_CLR(h2c_pkt, value)        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X14, 16, 16)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_1_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(h2c_pkt)                       \
+	GET_H2C_FIELD(h2c_pkt + 0X18, 0, 8)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(h2c_pkt, value)                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2_NO_CLR(h2c_pkt, value)         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X18, 8, 8)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(h2c_pkt)                      \
+	GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 16)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(h2c_pkt, value)               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2_NO_CLR(h2c_pkt, value)        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X1C, 16, 16)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_2_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(h2c_pkt)                       \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(h2c_pkt, value)                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3_NO_CLR(h2c_pkt, value)         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(h2c_pkt)                      \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 16)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(h2c_pkt, value)               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3_NO_CLR(h2c_pkt, value)        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 16)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_3_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(h2c_pkt)                       \
+	GET_H2C_FIELD(h2c_pkt + 0X10, 0, 8)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(h2c_pkt, value)                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4_NO_CLR(h2c_pkt, value)         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X10, 8, 8)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(h2c_pkt)                      \
+	GET_H2C_FIELD(h2c_pkt + 0X14, 0, 16)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(h2c_pkt, value)               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4_NO_CLR(h2c_pkt, value)        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X14, 16, 16)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_4_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(h2c_pkt)                       \
+	GET_H2C_FIELD(h2c_pkt + 0X18, 0, 8)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(h2c_pkt, value)                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5_NO_CLR(h2c_pkt, value)         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(h2c_pkt)                        \
+	GET_H2C_FIELD(h2c_pkt + 0X18, 8, 8)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(h2c_pkt, value)                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5_NO_CLR(h2c_pkt, value)          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(h2c_pkt)                      \
+	GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 16)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(h2c_pkt, value)               \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5_NO_CLR(h2c_pkt, value)        \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X1C, 16, 16)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_5_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 16, 16, value)
+#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_TXFF_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_RXFF_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt)                                \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value)                         \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_FWFF_NO_CLR(h2c_pkt, value)                  \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PHYFF_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 4, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt)                                 \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 5, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value)                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_CAM_NO_CLR(h2c_pkt, value)                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt)                             \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 6, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value)                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 6, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM_NO_CLR(h2c_pkt, value)               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 6, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt)                              \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 7, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value)                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 7, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM_NO_CLR(h2c_pkt, value)                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 7, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt)                              \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value)                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM_NO_CLR(h2c_pkt, value)                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt)                          \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 9, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value)                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM_NO_CLR(h2c_pkt, value)            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 16, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE0_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 17, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 17, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE1_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 17, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 18, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 18, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE2_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 18, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 19, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 19, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE3_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 19, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 20, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 20, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE4_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 20, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 21, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 21, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE5_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 21, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 22, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 22, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE6_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 22, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt)                               \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 23, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value)                        \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 23, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE7_NO_CLR(h2c_pkt, value)                 \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 23, 1, value)
+#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value)                                \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define PHYDM_INFO_SET_REF_TYPE_NO_CLR(h2c_pkt, value)                         \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define PHYDM_INFO_SET_RF_TYPE_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define PHYDM_INFO_SET_CUT_VER_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 24, 4)
+#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 4, value)
+#define PHYDM_INFO_SET_RX_ANT_STATUS_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 4, value)
+#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt)                                  \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 28, 4)
+#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value)                           \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 28, 4, value)
+#define PHYDM_INFO_SET_TX_ANT_STATUS_NO_CLR(h2c_pkt, value)                    \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 28, 4, value)
+#define FW_SNDING_GET_SU0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define FW_SNDING_SET_SU0(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define FW_SNDING_SET_SU0_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define FW_SNDING_GET_SU1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
+#define FW_SNDING_SET_SU1(h2c_pkt, value)                                      \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define FW_SNDING_SET_SU1_NO_CLR(h2c_pkt, value)                               \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define FW_SNDING_GET_MU(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
+#define FW_SNDING_SET_MU(h2c_pkt, value)                                       \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define FW_SNDING_SET_MU_NO_CLR(h2c_pkt, value)                                \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define FW_SNDING_GET_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define FW_SNDING_SET_PERIOD(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define FW_SNDING_SET_PERIOD_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define FW_SNDING_SET_NDPA0_HEAD_PG_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt)                                   \
+	GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value)                            \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define FW_SNDING_SET_NDPA1_HEAD_PG_NO_CLR(h2c_pkt, value)                     \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt)                                 \
+	GET_H2C_FIELD(h2c_pkt + 0XC, 0, 8)
+#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value)                          \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 0, 8, value)
+#define FW_SNDING_SET_MU_NDPA_HEAD_PG_NO_CLR(h2c_pkt, value)                   \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 0, 8, value)
+#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 8, 8)
+#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 8, 8, value)
+#define FW_SNDING_SET_RPT0_HEAD_PG_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 8, 8, value)
+#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 16, 8)
+#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 16, 8, value)
+#define FW_SNDING_SET_RPT1_HEAD_PG_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 16, 8, value)
+#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 24, 8)
+#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 24, 8, value)
+#define FW_SNDING_SET_RPT2_HEAD_PG_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 24, 8, value)
+#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define FW_FWCTRL_SET_SEQ_NUM_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1)
+#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value)                             \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value)
+#define FW_FWCTRL_SET_MORE_CONTENT_NO_CLR(h2c_pkt, value)                      \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value)
+#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 9, 7)
+#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value)                              \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 7, value)
+#define FW_FWCTRL_SET_CONTENT_IDX_NO_CLR(h2c_pkt, value)                       \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 7, value)
+#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value)                                 \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define FW_FWCTRL_SET_CLASS_ID_NO_CLR(h2c_pkt, value)                          \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define FW_FWCTRL_GET_LENGTH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value)                                   \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define FW_FWCTRL_SET_LENGTH_NO_CLR(h2c_pkt, value)                            \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define FW_FWCTRL_GET_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32)
+#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value)                                  \
+	SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value)
+#define FW_FWCTRL_SET_CONTENT_NO_CLR(h2c_pkt, value)                           \
+	SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value)
+#endif

hal/halmac/halmac_fw_offload_h2c_nic.h

@@ -0,0 +1,694 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_
+#define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_
+#define CMD_ID_FW_OFFLOAD_H2C 0XFF
+#define CMD_ID_CH_SWITCH 0XFF
+#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF
+#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF
+#define CMD_ID_CFG_PARAM 0XFF
+#define CMD_ID_UPDATE_DATAPACK 0XFF
+#define CMD_ID_RUN_DATAPACK 0XFF
+#define CMD_ID_DOWNLOAD_FLASH 0XFF
+#define CMD_ID_UPDATE_PKT 0XFF
+#define CMD_ID_GENERAL_INFO 0XFF
+#define CMD_ID_IQK 0XFF
+#define CMD_ID_PWR_TRK 0XFF
+#define CMD_ID_PSD 0XFF
+#define CMD_ID_P2PPS 0XFF
+#define CMD_ID_BT_COEX 0XFF
+#define CMD_ID_NAN_CTRL 0XFF
+#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF
+#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF
+#define CMD_ID_FW_ACCESS_TEST 0XFF
+#define CMD_ID_PHYDM_INFO 0XFF
+#define CMD_ID_FW_SNDING 0XFF
+#define CMD_ID_H2C_LOOPBACK 0XFF
+#define CMD_ID_FWCMD_LOOPBACK 0XFF
+#define CMD_ID_FW_FWCTRL 0XFF
+#define CATEGORY_H2C_CMD_HEADER 0X00
+#define CATEGORY_FW_OFFLOAD_H2C 0X01
+#define CATEGORY_CH_SWITCH 0X01
+#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01
+#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01
+#define CATEGORY_CFG_PARAM 0X01
+#define CATEGORY_UPDATE_DATAPACK 0X01
+#define CATEGORY_RUN_DATAPACK 0X01
+#define CATEGORY_DOWNLOAD_FLASH 0X01
+#define CATEGORY_UPDATE_PKT 0X01
+#define CATEGORY_GENERAL_INFO 0X01
+#define CATEGORY_IQK 0X01
+#define CATEGORY_PWR_TRK 0X01
+#define CATEGORY_PSD 0X01
+#define CATEGORY_P2PPS 0X01
+#define CATEGORY_BT_COEX 0X01
+#define CATEGORY_NAN_CTRL 0X01
+#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01
+#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01
+#define CATEGORY_FW_ACCESS_TEST 0X01
+#define CATEGORY_PHYDM_INFO 0X01
+#define CATEGORY_FW_SNDING 0X01
+#define CATEGORY_H2C_LOOPBACK 0X01
+#define CATEGORY_FWCMD_LOOPBACK 0X01
+#define CATEGORY_FW_FWCTRL 0X01
+#define SUB_CMD_ID_CH_SWITCH 0X02
+#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
+#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05
+#define SUB_CMD_ID_CFG_PARAM 0X08
+#define SUB_CMD_ID_UPDATE_DATAPACK 0X09
+#define SUB_CMD_ID_RUN_DATAPACK 0X0A
+#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B
+#define SUB_CMD_ID_UPDATE_PKT 0X0C
+#define SUB_CMD_ID_GENERAL_INFO 0X0D
+#define SUB_CMD_ID_IQK 0X0E
+#define SUB_CMD_ID_PWR_TRK 0X0F
+#define SUB_CMD_ID_PSD 0X10
+#define SUB_CMD_ID_P2PPS 0X24
+#define SUB_CMD_ID_BT_COEX 0X60
+#define SUB_CMD_ID_NAN_CTRL 0XB2
+#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
+#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
+#define SUB_CMD_ID_FW_ACCESS_TEST 0X00
+#define SUB_CMD_ID_PHYDM_INFO 0X11
+#define SUB_CMD_ID_FW_SNDING 0X12
+#define SUB_CMD_ID_FW_FWCTRL 0X13
+#define SUB_CMD_ID_H2C_LOOPBACK 0X14
+#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15
+#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 7)
+#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 7, value)
+#define H2C_CMD_HEADER_GET_ACK(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 7, 1)
+#define H2C_CMD_HEADER_SET_ACK(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 7, 1, value)
+#define H2C_CMD_HEADER_GET_TOTAL_LEN(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 16)
+#define H2C_CMD_HEADER_SET_TOTAL_LEN(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 16, value)
+#define H2C_CMD_HEADER_GET_SEQ_NUM(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 16)
+#define H2C_CMD_HEADER_SET_SEQ_NUM(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 16, value)
+#define FW_OFFLOAD_H2C_GET_CATEGORY(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 7)
+#define FW_OFFLOAD_H2C_SET_CATEGORY(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 7, value)
+#define FW_OFFLOAD_H2C_GET_ACK(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 7, 1)
+#define FW_OFFLOAD_H2C_SET_ACK(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 7, 1, value)
+#define FW_OFFLOAD_H2C_GET_CMD_ID(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define FW_OFFLOAD_H2C_SET_CMD_ID(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(h2c_pkt)                                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 16)
+#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(h2c_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 16, value)
+#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 16)
+#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 16, value)
+#define FW_OFFLOAD_H2C_GET_SEQ_NUM(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 16)
+#define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 16, value)
+#define CH_SWITCH_GET_START(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define CH_SWITCH_SET_START(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define CH_SWITCH_GET_DEST_CH_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
+#define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
+#define CH_SWITCH_GET_ABSOLUTE_TIME(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
+#define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
+#define CH_SWITCH_GET_PERIODIC_OPT(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 2)
+#define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 2, value)
+#define CH_SWITCH_GET_INFO_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define CH_SWITCH_GET_CH_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define CH_SWITCH_SET_CH_NUM(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define CH_SWITCH_GET_PRI_CH_IDX(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 4)
+#define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 4, value)
+#define CH_SWITCH_GET_DEST_BW(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 28, 4)
+#define CH_SWITCH_SET_DEST_BW(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 28, 4, value)
+#define CH_SWITCH_GET_DEST_CH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
+#define CH_SWITCH_SET_DEST_CH(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
+#define CH_SWITCH_GET_NORMAL_PERIOD(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 6)
+#define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 6, value)
+#define CH_SWITCH_GET_NORMAL_PERIOD_SEL(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 14, 2)
+#define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 14, 2, value)
+#define CH_SWITCH_GET_SLOW_PERIOD(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 6)
+#define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 6, value)
+#define CH_SWITCH_GET_SLOW_PERIOD_SEL(h2c_pkt)                                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 22, 2)
+#define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 22, 2, value)
+#define CH_SWITCH_GET_NORMAL_CYCLE(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 24, 8)
+#define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 24, 8, value)
+#define CH_SWITCH_GET_TSF_HIGH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32)
+#define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value)
+#define CH_SWITCH_GET_TSF_LOW(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32)
+#define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value)
+#define CH_SWITCH_GET_INFO_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 16)
+#define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 16, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 4)
+#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 4, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 12, 4)
+#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 12, 4, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(h2c_pkt)                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(h2c_pkt, value)             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(h2c_pkt)                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(h2c_pkt, value)             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(h2c_pkt)                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(h2c_pkt, value)             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(h2c_pkt)                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(h2c_pkt, value)             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(h2c_pkt)                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(h2c_pkt, value)             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 32, value)
+#define CFG_PARAM_GET_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)
+#define CFG_PARAM_SET_NUM(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)
+#define CFG_PARAM_GET_INIT_CASE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 1)
+#define CFG_PARAM_SET_INIT_CASE(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 1, value)
+#define CFG_PARAM_GET_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define CFG_PARAM_SET_LOC(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define UPDATE_DATAPACK_GET_SIZE(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)
+#define UPDATE_DATAPACK_SET_SIZE(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)
+#define UPDATE_DATAPACK_GET_DATAPACK_ID(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define UPDATE_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define UPDATE_DATAPACK_GET_DATAPACK_LOC(h2c_pkt)                              \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define UPDATE_DATAPACK_SET_DATAPACK_LOC(h2c_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(h2c_pkt)                          \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
+#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(h2c_pkt, value)                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
+#define UPDATE_DATAPACK_GET_END_SEGMENT(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 1)
+#define UPDATE_DATAPACK_SET_END_SEGMENT(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 1, value)
+#define RUN_DATAPACK_GET_DATAPACK_ID(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define RUN_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define DOWNLOAD_FLASH_GET_SPI_CMD(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define DOWNLOAD_FLASH_SET_SPI_CMD(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define DOWNLOAD_FLASH_GET_LOCATION(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 16)
+#define DOWNLOAD_FLASH_SET_LOCATION(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 16, value)
+#define DOWNLOAD_FLASH_GET_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32)
+#define DOWNLOAD_FLASH_SET_SIZE(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value)
+#define DOWNLOAD_FLASH_GET_START_ADDR(h2c_pkt)                                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32)
+#define DOWNLOAD_FLASH_SET_START_ADDR(h2c_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value)
+#define UPDATE_PKT_GET_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)
+#define UPDATE_PKT_SET_SIZE(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)
+#define UPDATE_PKT_GET_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define UPDATE_PKT_SET_ID(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define UPDATE_PKT_GET_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define UPDATE_PKT_SET_LOC(h2c_pkt, value)                                     \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define GENERAL_INFO_GET_FW_TX_BOUNDARY(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define IQK_GET_CLEAR(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define IQK_SET_CLEAR(h2c_pkt, value)                                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define IQK_GET_SEGMENT_IQK(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
+#define IQK_SET_SEGMENT_IQK(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
+#define PWR_TRK_GET_ENABLE_A(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define PWR_TRK_SET_ENABLE_A(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define PWR_TRK_GET_ENABLE_B(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
+#define PWR_TRK_SET_ENABLE_B(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
+#define PWR_TRK_GET_ENABLE_C(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
+#define PWR_TRK_SET_ENABLE_C(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
+#define PWR_TRK_GET_ENABLE_D(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)
+#define PWR_TRK_SET_ENABLE_D(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)
+#define PWR_TRK_GET_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 3)
+#define PWR_TRK_SET_TYPE(h2c_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 3, value)
+#define PWR_TRK_GET_BBSWING_INDEX(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define PWR_TRK_SET_BBSWING_INDEX(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_A(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_A(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_A(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_A(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_A(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_A(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_B(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_B(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_B(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_B(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_B(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_B(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 16, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_C(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_C(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_C(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_C(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_C(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_C(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 16, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_D(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_D(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_D(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_D(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_D(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_D(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 16, 8, value)
+#define PSD_GET_START_PSD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)
+#define PSD_SET_START_PSD(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)
+#define PSD_GET_END_PSD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 16)
+#define PSD_SET_END_PSD(h2c_pkt, value)                                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 16, value)
+#define P2PPS_GET_OFFLOAD_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define P2PPS_SET_OFFLOAD_EN(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define P2PPS_GET_ROLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
+#define P2PPS_SET_ROLE(h2c_pkt, value)                                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
+#define P2PPS_GET_CTWINDOW_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
+#define P2PPS_SET_CTWINDOW_EN(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
+#define P2PPS_GET_NOA_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)
+#define P2PPS_SET_NOA_EN(h2c_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)
+#define P2PPS_GET_NOA_SEL(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 1)
+#define P2PPS_SET_NOA_SEL(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 1, value)
+#define P2PPS_GET_ALLSTASLEEP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1)
+#define P2PPS_SET_ALLSTASLEEP(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value)
+#define P2PPS_GET_DISCOVERY(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 6, 1)
+#define P2PPS_SET_DISCOVERY(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 6, 1, value)
+#define P2PPS_GET_DISABLE_CLOSERF(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 7, 1)
+#define P2PPS_SET_DISABLE_CLOSERF(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 7, 1, value)
+#define P2PPS_GET_P2P_PORT_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define P2PPS_SET_P2P_PORT_ID(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define P2PPS_GET_P2P_GROUP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define P2PPS_SET_P2P_GROUP(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define P2PPS_GET_P2P_MACID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define P2PPS_SET_P2P_MACID(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define P2PPS_GET_CTWINDOW_LENGTH(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
+#define P2PPS_SET_CTWINDOW_LENGTH(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
+#define P2PPS_GET_NOA_DURATION_PARA(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32)
+#define P2PPS_SET_NOA_DURATION_PARA(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value)
+#define P2PPS_GET_NOA_INTERVAL_PARA(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32)
+#define P2PPS_SET_NOA_INTERVAL_PARA(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value)
+#define P2PPS_GET_NOA_START_TIME_PARA(h2c_pkt)                                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 32)
+#define P2PPS_SET_NOA_START_TIME_PARA(h2c_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 32, value)
+#define P2PPS_GET_NOA_COUNT_PARA(h2c_pkt)                                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 32)
+#define P2PPS_SET_NOA_COUNT_PARA(h2c_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 32, value)
+#define BT_COEX_GET_DATA_START(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define BT_COEX_SET_DATA_START(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CTRL_GET_NAN_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 2)
+#define NAN_CTRL_SET_NAN_EN(h2c_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 2, value)
+#define NAN_CTRL_GET_WARMUP_TIMER_FLAG(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
+#define NAN_CTRL_SET_WARMUP_TIMER_FLAG(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
+#define NAN_CTRL_GET_SUPPORT_BAND(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 2)
+#define NAN_CTRL_SET_SUPPORT_BAND(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 2, value)
+#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(h2c_pkt)                              \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 10, 1)
+#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(h2c_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 10, 1, value)
+#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(h2c_pkt)                              \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 11, 1)
+#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(h2c_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 11, 1, value)
+#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define NAN_CTRL_GET_CHANNEL_2G(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define NAN_CTRL_SET_CHANNEL_2G(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define NAN_CTRL_GET_CHANNEL_5G(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
+#define NAN_CTRL_SET_CHANNEL_5G(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
+#define NAN_CTRL_GET_MASTERPREFERENCE_VALUE(h2c_pkt)                           \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 8)
+#define NAN_CTRL_SET_MASTERPREFERENCE_VALUE(h2c_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 8, value)
+#define NAN_CTRL_GET_RANDOMFACTOR_VALUE(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 8)
+#define NAN_CTRL_SET_RANDOMFACTOR_VALUE(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(h2c_pkt)                       \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(h2c_pkt, value)                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(h2c_pkt)                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 16)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(h2c_pkt, value)               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 16)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(h2c_pkt)                       \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(h2c_pkt, value)                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(h2c_pkt)                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 16)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(h2c_pkt, value)               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 16, 16)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(h2c_pkt)                       \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(h2c_pkt, value)                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(h2c_pkt)                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 16)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(h2c_pkt, value)               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 16, 16)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(h2c_pkt)                       \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(h2c_pkt, value)                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(h2c_pkt)                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 16)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(h2c_pkt, value)               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 16)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(h2c_pkt)                       \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(h2c_pkt, value)                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(h2c_pkt)                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 16)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(h2c_pkt, value)               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 16, 16)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(h2c_pkt)                       \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(h2c_pkt, value)                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(h2c_pkt)                        \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(h2c_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(h2c_pkt)                      \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 16)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(h2c_pkt, value)               \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 16, 16)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 16, 16, value)
+#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt)                                \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt)                                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt)                             \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 6, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 6, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt)                              \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 7, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 7, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt)                              \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt)                          \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value)                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 17, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 17, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 18, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 18, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 19, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 19, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 20, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 20, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 21, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 21, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 22, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 22, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt)                               \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 23, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 23, 1, value)
+#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 4)
+#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 4, value)
+#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt)                                  \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 28, 4)
+#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 28, 4, value)
+#define FW_SNDING_GET_SU0(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define FW_SNDING_SET_SU0(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define FW_SNDING_GET_SU1(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
+#define FW_SNDING_SET_SU1(h2c_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
+#define FW_SNDING_GET_MU(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
+#define FW_SNDING_SET_MU(h2c_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
+#define FW_SNDING_GET_PERIOD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define FW_SNDING_SET_PERIOD(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt)                                   \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt)                                 \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 0, 8)
+#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 0, 8, value)
+#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 8, 8)
+#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 8, 8, value)
+#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 16, 8)
+#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 16, 8, value)
+#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 24, 8)
+#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 24, 8, value)
+#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt)                                    \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1)
+#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value)
+#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt)                                     \
+	LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 7)
+#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 7, value)
+#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define FW_FWCTRL_GET_LENGTH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define FW_FWCTRL_GET_CONTENT(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32)
+#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value)
+#endif

hal/halmac/halmac_gpio_cmd.h

@@ -0,0 +1,84 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef HALMAC_GPIO_CMD
+#define HALMAC_GPIO_CMD
+
+#include "halmac_2_platform.h"
+
+/* GPIO ID */
+#define HALMAC_GPIO0		0
+#define HALMAC_GPIO1		1
+#define HALMAC_GPIO2		2
+#define HALMAC_GPIO3		3
+#define HALMAC_GPIO4		4
+#define HALMAC_GPIO5		5
+#define HALMAC_GPIO6		6
+#define HALMAC_GPIO7		7
+#define HALMAC_GPIO8		8
+#define HALMAC_GPIO9		9
+#define HALMAC_GPIO10		10
+#define HALMAC_GPIO11		11
+#define HALMAC_GPIO12		12
+#define HALMAC_GPIO13		13
+#define HALMAC_GPIO14		14
+#define HALMAC_GPIO15		15
+#define HALMAC_GPIO_NUM		16
+
+/* GPIO type */
+#define HALMAC_GPIO_IN		0
+#define HALMAC_GPIO_OUT		1
+#define HALMAC_GPIO_IN_OUT	2
+
+/* Function name */
+#define HALMAC_WL_HWPDN			0
+#define HALMAC_BT_HWPDN			1
+#define HALMAC_BT_GPIO			2
+#define HALMAC_WL_HW_EXTWOL		3
+#define HALMAC_BT_HW_EXTWOL		4
+#define HALMAC_BT_SFLASH		5
+#define HALMAC_WL_SFLASH		6
+#define HALMAC_WL_LED			7
+#define HALMAC_SDIO_INT			8
+#define HALMAC_UART0			9
+#define HALMAC_EEPROM			10
+#define HALMAC_JTAG			11
+#define HALMAC_LTE_COEX_UART		12
+#define HALMAC_3W_LTE_WL_GPIO		13
+#define HALMAC_GPIO2_3_WL_CTRL_EN	14
+#define HALMAC_GPIO13_14_WL_CTRL_EN	15
+#define HALMAC_DBG_GNT_WL_BT		16
+#define HALMAC_BT_3DDLS_A		17
+#define HALMAC_BT_3DDLS_B		18
+#define HALMAC_BT_PTA			19
+#define HALMAC_WL_PTA			20
+#define HALMAC_WL_UART			21
+#define HALMAC_WLMAC_DBG		22
+#define HALMAC_WLPHY_DBG		23
+#define HALMAC_BT_DBG			24
+#define HALMAC_WLPHY_RFE_CTRL2GPIO	25
+#define HALMAC_EXT_XTAL			26
+#define HALMAC_SW_IO			27
+
+struct halmac_gpio_pimux_list {
+	u16 func;
+	u8 id;
+	u8 type;
+	u16 offset;
+	u8 msk;
+	u8 value;
+};
+
+#endif

hal/halmac/halmac_h2c_extra_info_ap.h

@@ -0,0 +1,220 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HAL_H2CEXTRAINFO_H2C_C2H_AP_H_
+#define _HAL_H2CEXTRAINFO_H2C_C2H_AP_H_
+#define PARAM_INFO_GET_LEN(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 8)
+#define PARAM_INFO_SET_LEN(extra_info, value)                                  \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 8, value)
+#define PARAM_INFO_SET_LEN_NO_CLR(extra_info, value)                           \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 8, value)
+#define PARAM_INFO_GET_IO_CMD(extra_info) GET_C2H_FIELD(extra_info + 0X00, 8, 7)
+#define PARAM_INFO_SET_IO_CMD(extra_info, value)                               \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 8, 7, value)
+#define PARAM_INFO_SET_IO_CMD_NO_CLR(extra_info, value)                        \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 8, 7, value)
+#define PARAM_INFO_GET_MSK_EN(extra_info)                                      \
+	GET_C2H_FIELD(extra_info + 0X00, 15, 1)
+#define PARAM_INFO_SET_MSK_EN(extra_info, value)                               \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 15, 1, value)
+#define PARAM_INFO_SET_MSK_EN_NO_CLR(extra_info, value)                        \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 15, 1, value)
+#define PARAM_INFO_GET_LLT_PG_BNDY(extra_info)                                 \
+	GET_C2H_FIELD(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_LLT_PG_BNDY(extra_info, value)                          \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_SET_LLT_PG_BNDY_NO_CLR(extra_info, value)                   \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_EFUSE_RSVDPAGE_LOC(extra_info)                          \
+	GET_C2H_FIELD(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_EFUSE_RSVDPAGE_LOC(extra_info, value)                   \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_SET_EFUSE_RSVDPAGE_LOC_NO_CLR(extra_info, value)            \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_EFUSE_PATCH_EN(extra_info)                              \
+	GET_C2H_FIELD(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_EFUSE_PATCH_EN(extra_info, value)                       \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_SET_EFUSE_PATCH_EN_NO_CLR(extra_info, value)                \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_RF_ADDR(extra_info)                                     \
+	GET_C2H_FIELD(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_RF_ADDR(extra_info, value)                              \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_SET_RF_ADDR_NO_CLR(extra_info, value)                       \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_IO_ADDR(extra_info)                                     \
+	GET_C2H_FIELD(extra_info + 0X00, 16, 16)
+#define PARAM_INFO_SET_IO_ADDR(extra_info, value)                              \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value)
+#define PARAM_INFO_SET_IO_ADDR_NO_CLR(extra_info, value)                       \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value)
+#define PARAM_INFO_GET_DELAY_VAL(extra_info)                                   \
+	GET_C2H_FIELD(extra_info + 0X00, 16, 16)
+#define PARAM_INFO_SET_DELAY_VAL(extra_info, value)                            \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value)
+#define PARAM_INFO_SET_DELAY_VAL_NO_CLR(extra_info, value)                     \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value)
+#define PARAM_INFO_GET_RF_PATH(extra_info)                                     \
+	GET_C2H_FIELD(extra_info + 0X00, 24, 8)
+#define PARAM_INFO_SET_RF_PATH(extra_info, value)                              \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 24, 8, value)
+#define PARAM_INFO_SET_RF_PATH_NO_CLR(extra_info, value)                       \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 24, 8, value)
+#define PARAM_INFO_GET_DATA(extra_info) GET_C2H_FIELD(extra_info + 0X04, 0, 32)
+#define PARAM_INFO_SET_DATA(extra_info, value)                                 \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 0, 32, value)
+#define PARAM_INFO_SET_DATA_NO_CLR(extra_info, value)                          \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 0, 32, value)
+#define PARAM_INFO_GET_MASK(extra_info) GET_C2H_FIELD(extra_info + 0X08, 0, 32)
+#define PARAM_INFO_SET_MASK(extra_info, value)                                 \
+	SET_C2H_FIELD_CLR(extra_info + 0X08, 0, 32, value)
+#define PARAM_INFO_SET_MASK_NO_CLR(extra_info, value)                          \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X08, 0, 32, value)
+#define CH_INFO_GET_CH(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 8)
+#define CH_INFO_SET_CH(extra_info, value)                                      \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 8, value)
+#define CH_INFO_SET_CH_NO_CLR(extra_info, value)                               \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 8, value)
+#define CH_INFO_GET_PRI_CH_IDX(extra_info)                                     \
+	GET_C2H_FIELD(extra_info + 0X00, 8, 4)
+#define CH_INFO_SET_PRI_CH_IDX(extra_info, value)                              \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 8, 4, value)
+#define CH_INFO_SET_PRI_CH_IDX_NO_CLR(extra_info, value)                       \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 8, 4, value)
+#define CH_INFO_GET_BW(extra_info) GET_C2H_FIELD(extra_info + 0X00, 12, 4)
+#define CH_INFO_SET_BW(extra_info, value)                                      \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 12, 4, value)
+#define CH_INFO_SET_BW_NO_CLR(extra_info, value)                               \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 12, 4, value)
+#define CH_INFO_GET_TIMEOUT(extra_info) GET_C2H_FIELD(extra_info + 0X00, 16, 8)
+#define CH_INFO_SET_TIMEOUT(extra_info, value)                                 \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)
+#define CH_INFO_SET_TIMEOUT_NO_CLR(extra_info, value)                          \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)
+#define CH_INFO_GET_ACTION_ID(extra_info)                                      \
+	GET_C2H_FIELD(extra_info + 0X00, 24, 7)
+#define CH_INFO_SET_ACTION_ID(extra_info, value)                               \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 24, 7, value)
+#define CH_INFO_SET_ACTION_ID_NO_CLR(extra_info, value)                        \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 24, 7, value)
+#define CH_INFO_GET_EXTRA_INFO(extra_info)                                     \
+	GET_C2H_FIELD(extra_info + 0X00, 31, 1)
+#define CH_INFO_SET_EXTRA_INFO(extra_info, value)                              \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 31, 1, value)
+#define CH_INFO_SET_EXTRA_INFO_NO_CLR(extra_info, value)                       \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 31, 1, value)
+#define CH_EXTRA_INFO_GET_ID(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 7)
+#define CH_EXTRA_INFO_SET_ID(extra_info, value)                                \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 7, value)
+#define CH_EXTRA_INFO_SET_ID_NO_CLR(extra_info, value)                         \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 7, value)
+#define CH_EXTRA_INFO_GET_INFO(extra_info)                                     \
+	GET_C2H_FIELD(extra_info + 0X00, 7, 1)
+#define CH_EXTRA_INFO_SET_INFO(extra_info, value)                              \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 7, 1, value)
+#define CH_EXTRA_INFO_SET_INFO_NO_CLR(extra_info, value)                       \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 7, 1, value)
+#define CH_EXTRA_INFO_GET_SIZE(extra_info)                                     \
+	GET_C2H_FIELD(extra_info + 0X00, 8, 8)
+#define CH_EXTRA_INFO_SET_SIZE(extra_info, value)                              \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 8, 8, value)
+#define CH_EXTRA_INFO_SET_SIZE_NO_CLR(extra_info, value)                       \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 8, 8, value)
+#define CH_EXTRA_INFO_GET_DATA(extra_info)                                     \
+	GET_C2H_FIELD(extra_info + 0X00, 16, 1)
+#define CH_EXTRA_INFO_SET_DATA(extra_info, value)                              \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 1, value)
+#define CH_EXTRA_INFO_SET_DATA_NO_CLR(extra_info, value)                       \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_L(extra_info)                       \
+	GET_C2H_FIELD(extra_info + 0X00, 0, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_L(extra_info, value)                \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 16, value)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_L_NO_CLR(extra_info, value)         \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_BITDATA(extra_info)                          \
+	GET_C2H_FIELD(extra_info + 0X00, 0, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BITDATA(extra_info, value)                   \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 16, value)
+#define HIOE_INSTRUCTION_INFO_SET_BITDATA_NO_CLR(extra_info, value)            \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_H(extra_info)                       \
+	GET_C2H_FIELD(extra_info + 0X00, 16, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_H(extra_info, value)                \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_H_NO_CLR(extra_info, value)         \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_BITMASK(extra_info)                          \
+	GET_C2H_FIELD(extra_info + 0X00, 16, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BITMASK(extra_info, value)                   \
+	SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value)
+#define HIOE_INSTRUCTION_INFO_SET_BITMASK_NO_CLR(extra_info, value)            \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_REG_ADDR(extra_info)                         \
+	GET_C2H_FIELD(extra_info + 0X04, 0, 22)
+#define HIOE_INSTRUCTION_INFO_SET_REG_ADDR(extra_info, value)                  \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 0, 22, value)
+#define HIOE_INSTRUCTION_INFO_SET_REG_ADDR_NO_CLR(extra_info, value)           \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 0, 22, value)
+#define HIOE_INSTRUCTION_INFO_GET_DELAY_VALUE(extra_info)                      \
+	GET_C2H_FIELD(extra_info + 0X04, 0, 22)
+#define HIOE_INSTRUCTION_INFO_SET_DELAY_VALUE(extra_info, value)               \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 0, 22, value)
+#define HIOE_INSTRUCTION_INFO_SET_DELAY_VALUE_NO_CLR(extra_info, value)        \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 0, 22, value)
+#define HIOE_INSTRUCTION_INFO_GET_MODE_SELECT(extra_info)                      \
+	GET_C2H_FIELD(extra_info + 0X04, 22, 1)
+#define HIOE_INSTRUCTION_INFO_SET_MODE_SELECT(extra_info, value)               \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 22, 1, value)
+#define HIOE_INSTRUCTION_INFO_SET_MODE_SELECT_NO_CLR(extra_info, value)        \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 22, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_IO_DELAY(extra_info)                         \
+	GET_C2H_FIELD(extra_info + 0X04, 23, 1)
+#define HIOE_INSTRUCTION_INFO_SET_IO_DELAY(extra_info, value)                  \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 23, 1, value)
+#define HIOE_INSTRUCTION_INFO_SET_IO_DELAY_NO_CLR(extra_info, value)           \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 23, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_BYTEMASK(extra_info)                         \
+	GET_C2H_FIELD(extra_info + 0X04, 24, 4)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEMASK(extra_info, value)                  \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 24, 4, value)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEMASK_NO_CLR(extra_info, value)           \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 24, 4, value)
+#define HIOE_INSTRUCTION_INFO_GET_RD_EN(extra_info)                            \
+	GET_C2H_FIELD(extra_info + 0X04, 28, 1)
+#define HIOE_INSTRUCTION_INFO_SET_RD_EN(extra_info, value)                     \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 28, 1, value)
+#define HIOE_INSTRUCTION_INFO_SET_RD_EN_NO_CLR(extra_info, value)              \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 28, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_WR_EN(extra_info)                            \
+	GET_C2H_FIELD(extra_info + 0X04, 29, 1)
+#define HIOE_INSTRUCTION_INFO_SET_WR_EN(extra_info, value)                     \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 29, 1, value)
+#define HIOE_INSTRUCTION_INFO_SET_WR_EN_NO_CLR(extra_info, value)              \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 29, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_RAW_R(extra_info)                            \
+	GET_C2H_FIELD(extra_info + 0X04, 30, 1)
+#define HIOE_INSTRUCTION_INFO_SET_RAW_R(extra_info, value)                     \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 30, 1, value)
+#define HIOE_INSTRUCTION_INFO_SET_RAW_R_NO_CLR(extra_info, value)              \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 30, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_RAW(extra_info)                              \
+	GET_C2H_FIELD(extra_info + 0X04, 31, 1)
+#define HIOE_INSTRUCTION_INFO_SET_RAW(extra_info, value)                       \
+	SET_C2H_FIELD_CLR(extra_info + 0X04, 31, 1, value)
+#define HIOE_INSTRUCTION_INFO_SET_RAW_NO_CLR(extra_info, value)                \
+	SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 31, 1, value)
+#endif

hal/halmac/halmac_h2c_extra_info_nic.h

@@ -0,0 +1,171 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_
+#define _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_
+
+/* H2C extra info (rsvd page) usage, unit : page (128byte)*/
+/* dlfw : not include txdesc size*/
+/* update pkt : not include txdesc size*/
+/* cfg param : not include txdesc size*/
+/* scan info : not include txdesc size*/
+/* dl flash : not include txdesc size*/
+#define DLFW_RSVDPG_SIZE 2048
+#define UPDATE_PKT_RSVDPG_SIZE 2048
+#define CFG_PARAM_RSVDPG_SIZE 2048
+#define SCAN_INFO_RSVDPG_SIZE 256
+#define DL_FLASH_RSVDPG_SIZE 2048
+/* su0 snding pkt : include txdesc size */
+#define SU0_SNDING_PKT_OFFSET 0
+#define SU0_SNDING_PKT_RSVDPG_SIZE 128
+
+#define PARAM_INFO_GET_LEN(extra_info) LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 8)
+#define PARAM_INFO_SET_LEN(extra_info, value)                                  \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 8, value)
+#define PARAM_INFO_GET_IO_CMD(extra_info)                                      \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 8, 7)
+#define PARAM_INFO_SET_IO_CMD(extra_info, value)                               \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 8, 7, value)
+#define PARAM_INFO_GET_MSK_EN(extra_info)                                      \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 15, 1)
+#define PARAM_INFO_SET_MSK_EN(extra_info, value)                               \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 15, 1, value)
+#define PARAM_INFO_GET_LLT_PG_BNDY(extra_info)                                 \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_LLT_PG_BNDY(extra_info, value)                          \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_EFUSE_RSVDPAGE_LOC(extra_info)                          \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_EFUSE_RSVDPAGE_LOC(extra_info, value)                   \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_EFUSE_PATCH_EN(extra_info)                              \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_EFUSE_PATCH_EN(extra_info, value)                       \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_RF_ADDR(extra_info)                                     \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_RF_ADDR(extra_info, value)                              \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_IO_ADDR(extra_info)                                     \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16)
+#define PARAM_INFO_SET_IO_ADDR(extra_info, value)                              \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value)
+#define PARAM_INFO_GET_DELAY_VAL(extra_info)                                   \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16)
+#define PARAM_INFO_SET_DELAY_VAL(extra_info, value)                            \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value)
+#define PARAM_INFO_GET_RF_PATH(extra_info)                                     \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 24, 8)
+#define PARAM_INFO_SET_RF_PATH(extra_info, value)                              \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 24, 8, value)
+#define PARAM_INFO_GET_DATA(extra_info)                                        \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 0, 32)
+#define PARAM_INFO_SET_DATA(extra_info, value)                                 \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 0, 32, value)
+#define PARAM_INFO_GET_MASK(extra_info)                                        \
+	LE_BITS_TO_4BYTE(extra_info + 0X08, 0, 32)
+#define PARAM_INFO_SET_MASK(extra_info, value)                                 \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X08, 0, 32, value)
+#define CH_INFO_GET_CH(extra_info) LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 8)
+#define CH_INFO_SET_CH(extra_info, value)                                      \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 8, value)
+#define CH_INFO_GET_PRI_CH_IDX(extra_info)                                     \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 8, 4)
+#define CH_INFO_SET_PRI_CH_IDX(extra_info, value)                              \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 8, 4, value)
+#define CH_INFO_GET_BW(extra_info) LE_BITS_TO_4BYTE(extra_info + 0X00, 12, 4)
+#define CH_INFO_SET_BW(extra_info, value)                                      \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 12, 4, value)
+#define CH_INFO_GET_TIMEOUT(extra_info)                                        \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)
+#define CH_INFO_SET_TIMEOUT(extra_info, value)                                 \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)
+#define CH_INFO_GET_ACTION_ID(extra_info)                                      \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 24, 7)
+#define CH_INFO_SET_ACTION_ID(extra_info, value)                               \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 24, 7, value)
+#define CH_INFO_GET_EXTRA_INFO(extra_info)                                     \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 31, 1)
+#define CH_INFO_SET_EXTRA_INFO(extra_info, value)                              \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 31, 1, value)
+#define CH_EXTRA_INFO_GET_ID(extra_info)                                       \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 7)
+#define CH_EXTRA_INFO_SET_ID(extra_info, value)                                \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 7, value)
+#define CH_EXTRA_INFO_GET_INFO(extra_info)                                     \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 7, 1)
+#define CH_EXTRA_INFO_SET_INFO(extra_info, value)                              \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 7, 1, value)
+#define CH_EXTRA_INFO_GET_SIZE(extra_info)                                     \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 8, 8)
+#define CH_EXTRA_INFO_SET_SIZE(extra_info, value)                              \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 8, 8, value)
+#define CH_EXTRA_INFO_GET_DATA(extra_info)                                     \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 1)
+#define CH_EXTRA_INFO_SET_DATA(extra_info, value)                              \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_L(extra_info)                       \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_L(extra_info, value)                \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_BITDATA(extra_info)                          \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BITDATA(extra_info, value)                   \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_H(extra_info)                       \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_H(extra_info, value)                \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_BITMASK(extra_info)                          \
+	LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BITMASK(extra_info, value)                   \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_REG_ADDR(extra_info)                         \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 0, 22)
+#define HIOE_INSTRUCTION_INFO_SET_REG_ADDR(extra_info, value)                  \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 0, 22, value)
+#define HIOE_INSTRUCTION_INFO_GET_DELAY_VALUE(extra_info)                      \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 0, 22)
+#define HIOE_INSTRUCTION_INFO_SET_DELAY_VALUE(extra_info, value)               \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 0, 22, value)
+#define HIOE_INSTRUCTION_INFO_GET_MODE_SELECT(extra_info)                      \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 22, 1)
+#define HIOE_INSTRUCTION_INFO_SET_MODE_SELECT(extra_info, value)               \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 22, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_IO_DELAY(extra_info)                         \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 23, 1)
+#define HIOE_INSTRUCTION_INFO_SET_IO_DELAY(extra_info, value)                  \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 23, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_BYTEMASK(extra_info)                         \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 24, 4)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEMASK(extra_info, value)                  \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 24, 4, value)
+#define HIOE_INSTRUCTION_INFO_GET_RD_EN(extra_info)                            \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 28, 1)
+#define HIOE_INSTRUCTION_INFO_SET_RD_EN(extra_info, value)                     \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 28, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_WR_EN(extra_info)                            \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 29, 1)
+#define HIOE_INSTRUCTION_INFO_SET_WR_EN(extra_info, value)                     \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 29, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_RAW_R(extra_info)                            \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 30, 1)
+#define HIOE_INSTRUCTION_INFO_SET_RAW_R(extra_info, value)                     \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 30, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_RAW(extra_info)                              \
+	LE_BITS_TO_4BYTE(extra_info + 0X04, 31, 1)
+#define HIOE_INSTRUCTION_INFO_SET_RAW(extra_info, value)                       \
+	SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 31, 1, value)
+#endif

hal/halmac/halmac_hw_cfg.h

@@ -0,0 +1,170 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __HALMAC__HW_CFG_H__
+#define __HALMAC__HW_CFG_H__
+
+#include <drv_conf.h>	/* CONFIG_[IC] */
+
+#ifdef CONFIG_RTL8723A
+#define HALMAC_8723A_SUPPORT	1
+#else
+#define HALMAC_8723A_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8188E
+#define HALMAC_8188E_SUPPORT	1
+#else
+#define HALMAC_8188E_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8821A
+#define HALMAC_8821A_SUPPORT	1
+#else
+#define HALMAC_8821A_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8723B
+#define HALMAC_8723B_SUPPORT	1
+#else
+#define HALMAC_8723B_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8812A
+#define HALMAC_8812A_SUPPORT	1
+#else
+#define HALMAC_8812A_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8192E
+#define HALMAC_8192E_SUPPORT	1
+#else
+#define HALMAC_8192E_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8881A
+#define HALMAC_8881A_SUPPORT	1
+#else
+#define HALMAC_8881A_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8821B
+#define HALMAC_8821B_SUPPORT	1
+#else
+#define HALMAC_8821B_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8814A
+#define HALMAC_8814A_SUPPORT	1
+#else
+#define HALMAC_8814A_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8881A
+#define HALMAC_8881A_SUPPORT	1
+#else
+#define HALMAC_8881A_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8703B
+#define HALMAC_8703B_SUPPORT	1
+#else
+#define HALMAC_8703B_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8723D
+#define HALMAC_8723D_SUPPORT	1
+#else
+#define HALMAC_8723D_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8188F
+#define HALMAC_8188F_SUPPORT	1
+#else
+#define HALMAC_8188F_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8821BMP
+#define HALMAC_8821BMP_SUPPORT	1
+#else
+#define HALMAC_8821BMP_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8814AMP
+#define HALMAC_8814AMP_SUPPORT	1
+#else
+#define HALMAC_8814AMP_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8195A
+#define HALMAC_8195A_SUPPORT	1
+#else
+#define HALMAC_8195A_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8821B
+#define HALMAC_8821B_SUPPORT	1
+#else
+#define HALMAC_8821B_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8196F
+#define HALMAC_8196F_SUPPORT	1
+#else
+#define HALMAC_8196F_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8197F
+#define HALMAC_8197F_SUPPORT	1
+#else
+#define HALMAC_8197F_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8198F
+#define HALMAC_8198F_SUPPORT	1
+#else
+#define HALMAC_8198F_SUPPORT	0
+#endif
+
+
+/* Halmac support IC version */
+
+#ifdef CONFIG_RTL8814B
+#define HALMAC_8814B_SUPPORT	1
+#else
+#define HALMAC_8814B_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8821C
+#define HALMAC_8821C_SUPPORT	1
+#else
+#define HALMAC_8821C_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8822B
+#define HALMAC_8822B_SUPPORT	1
+#else
+#define HALMAC_8822B_SUPPORT	0
+#endif
+
+#ifdef CONFIG_RTL8822C
+#define HALMAC_8822C_SUPPORT	1
+#else
+#define HALMAC_8822C_SUPPORT	0
+#endif
+
+#endif /* __HALMAC__HW_CFG_H__ */
+
+

hal/halmac/halmac_intf_phy_cmd.h

@@ -0,0 +1,45 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef HALMAC_INTF_PHY_CMD
+#define HALMAC_INTF_PHY_CMD
+
+/* Cut mask */
+enum halmac_intf_phy_cut {
+	HALMAC_INTF_PHY_CUT_TESTCHIP = BIT(0),
+	HALMAC_INTF_PHY_CUT_A = BIT(1),
+	HALMAC_INTF_PHY_CUT_B = BIT(2),
+	HALMAC_INTF_PHY_CUT_C = BIT(3),
+	HALMAC_INTF_PHY_CUT_D = BIT(4),
+	HALMAC_INTF_PHY_CUT_E = BIT(5),
+	HALMAC_INTF_PHY_CUT_F = BIT(6),
+	HALMAC_INTF_PHY_CUT_G = BIT(7),
+	HALMAC_INTF_PHY_CUT_ALL = 0x7FFF,
+};
+
+/* IP selection */
+enum halmac_ip_sel {
+	HALMAC_IP_INTF_PHY = 0,
+	HALMAC_IP_SEL_MAC = 1,
+	HALMAC_IP_PCIE_DBI = 2,
+	HALMAC_IP_SEL_UNDEFINE = 0x7FFF,
+};
+
+/* Platform mask */
+enum halmac_intf_phy_platform {
+	HALMAC_INTF_PHY_PLATFORM_ALL = 0x7FFF,
+};
+
+#endif

hal/halmac/halmac_original_c2h_ap.h

@@ -0,0 +1,612 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_AP_H_
+#define _HAL_ORIGINALC2HFORMAT_H2C_C2H_AP_H_
+#define CMD_ID_C2H 0X00
+#define CMD_ID_DBG 0X00
+#define CMD_ID_C2H_LB 0X01
+#define CMD_ID_C2H_SND_TXBF 0X02
+#define CMD_ID_C2H_CCX_RPT 0X03
+#define CMD_ID_C2H_AP_REQ_TXRPT 0X04
+#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05
+#define CMD_ID_C2H_RA_RPT 0X0C
+#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D
+#define CMD_ID_C2H_RA_PARA_RPT 0X0E
+#define CMD_ID_C2H_CUR_CHANNEL 0X10
+#define CMD_ID_C2H_GPIO_WAKEUP 0X14
+#define C2H_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_SET_CMD_ID(c2h_pkt, value)                                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SET_CMD_ID_NO_CLR(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_SET_SEQ(c2h_pkt, value)                                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SET_SEQ_NO_CLR(c2h_pkt, value)                                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define DBG_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define DBG_SET_CMD_ID(c2h_pkt, value)                                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define DBG_SET_CMD_ID_NO_CLR(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define DBG_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define DBG_SET_SEQ(c2h_pkt, value)                                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define DBG_SET_SEQ_NO_CLR(c2h_pkt, value)                                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define DBG_GET_DBG_STR1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define DBG_SET_DBG_STR1(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define DBG_SET_DBG_STR1_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define DBG_GET_DBG_STR2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define DBG_SET_DBG_STR2(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define DBG_SET_DBG_STR2_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define DBG_GET_DBG_STR3(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define DBG_SET_DBG_STR3(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define DBG_SET_DBG_STR3_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define DBG_GET_DBG_STR4(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define DBG_SET_DBG_STR4(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define DBG_SET_DBG_STR4_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define DBG_GET_DBG_STR5(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define DBG_SET_DBG_STR5(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define DBG_SET_DBG_STR5_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define DBG_GET_DBG_STR6(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define DBG_SET_DBG_STR6(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define DBG_SET_DBG_STR6_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define DBG_GET_DBG_STR7(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
+#define DBG_SET_DBG_STR7(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define DBG_SET_DBG_STR7_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define DBG_GET_DBG_STR8(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)
+#define DBG_SET_DBG_STR8(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define DBG_SET_DBG_STR8_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define DBG_GET_DBG_STR9(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)
+#define DBG_SET_DBG_STR9(c2h_pkt, value)                                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)
+#define DBG_SET_DBG_STR9_NO_CLR(c2h_pkt, value)                                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)
+#define DBG_GET_DBG_STR10(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 24, 8)
+#define DBG_SET_DBG_STR10(c2h_pkt, value)                                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value)
+#define DBG_SET_DBG_STR10_NO_CLR(c2h_pkt, value)                               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value)
+#define DBG_GET_DBG_STR11(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8)
+#define DBG_SET_DBG_STR11(c2h_pkt, value)                                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value)
+#define DBG_SET_DBG_STR11_NO_CLR(c2h_pkt, value)                               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value)
+#define DBG_GET_DBG_STR12(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8)
+#define DBG_SET_DBG_STR12(c2h_pkt, value)                                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value)
+#define DBG_SET_DBG_STR12_NO_CLR(c2h_pkt, value)                               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value)
+#define DBG_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define DBG_SET_LEN(c2h_pkt, value)                                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define DBG_SET_LEN_NO_CLR(c2h_pkt, value)                                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define DBG_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define DBG_SET_TRIGGER(c2h_pkt, value)                                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define DBG_SET_TRIGGER_NO_CLR(c2h_pkt, value)                                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_LB_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_LB_SET_CMD_ID(c2h_pkt, value)                                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_LB_SET_CMD_ID_NO_CLR(c2h_pkt, value)                               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_LB_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_LB_SET_SEQ(c2h_pkt, value)                                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_LB_SET_SEQ_NO_CLR(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_LB_GET_PAYLOAD1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 16)
+#define C2H_LB_SET_PAYLOAD1(c2h_pkt, value)                                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 16, value)
+#define C2H_LB_SET_PAYLOAD1_NO_CLR(c2h_pkt, value)                             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 16, value)
+#define C2H_LB_GET_PAYLOAD2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 32)
+#define C2H_LB_SET_PAYLOAD2(c2h_pkt, value)                                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 32, value)
+#define C2H_LB_SET_PAYLOAD2_NO_CLR(c2h_pkt, value)                             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 32, value)
+#define C2H_LB_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_LB_SET_LEN(c2h_pkt, value)                                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_LB_SET_LEN_NO_CLR(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_LB_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_LB_SET_TRIGGER(c2h_pkt, value)                                     \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_LB_SET_TRIGGER_NO_CLR(c2h_pkt, value)                              \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_SND_TXBF_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_SND_TXBF_SET_CMD_ID(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SND_TXBF_SET_CMD_ID_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SND_TXBF_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_SND_TXBF_SET_SEQ(c2h_pkt, value)                                   \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SND_TXBF_SET_SEQ_NO_CLR(c2h_pkt, value)                            \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SND_TXBF_GET_SND_RESULT(c2h_pkt)                                   \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 16, 1)
+#define C2H_SND_TXBF_SET_SND_RESULT(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 1, value)
+#define C2H_SND_TXBF_SET_SND_RESULT_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 1, value)
+#define C2H_SND_TXBF_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_SND_TXBF_SET_LEN(c2h_pkt, value)                                   \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_SND_TXBF_SET_LEN_NO_CLR(c2h_pkt, value)                            \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_SND_TXBF_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_SND_TXBF_SET_TRIGGER(c2h_pkt, value)                               \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_SND_TXBF_SET_TRIGGER_NO_CLR(c2h_pkt, value)                        \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_CCX_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_CCX_RPT_SET_CMD_ID(c2h_pkt, value)                                 \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_CCX_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value)                          \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_CCX_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_CCX_RPT_SET_SEQ(c2h_pkt, value)                                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_CCX_RPT_SET_SEQ_NO_CLR(c2h_pkt, value)                             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_CCX_RPT_GET_QSEL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 5)
+#define C2H_CCX_RPT_SET_QSEL(c2h_pkt, value)                                   \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 5, value)
+#define C2H_CCX_RPT_SET_QSEL_NO_CLR(c2h_pkt, value)                            \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 5, value)
+#define C2H_CCX_RPT_GET_BMC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 21, 1)
+#define C2H_CCX_RPT_SET_BMC(c2h_pkt, value)                                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 21, 1, value)
+#define C2H_CCX_RPT_SET_BMC_NO_CLR(c2h_pkt, value)                             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 21, 1, value)
+#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(c2h_pkt)                                \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 22, 1)
+#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(c2h_pkt, value)                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 22, 1, value)
+#define C2H_CCX_RPT_SET_LIFE_TIME_OVER_NO_CLR(c2h_pkt, value)                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 22, 1, value)
+#define C2H_CCX_RPT_GET_RETRY_OVER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 23, 1)
+#define C2H_CCX_RPT_SET_RETRY_OVER(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 23, 1, value)
+#define C2H_CCX_RPT_SET_RETRY_OVER_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 23, 1, value)
+#define C2H_CCX_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define C2H_CCX_RPT_SET_MACID(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_CCX_RPT_SET_MACID_NO_CLR(c2h_pkt, value)                           \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(c2h_pkt)                                \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 0, 6)
+#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(c2h_pkt, value)                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 6, value)
+#define C2H_CCX_RPT_SET_DATA_RETRY_CNT_NO_CLR(c2h_pkt, value)                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 6, value)
+#define C2H_CCX_RPT_GET_QUEUE7_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define C2H_CCX_RPT_SET_QUEUE7_0(c2h_pkt, value)                               \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_CCX_RPT_SET_QUEUE7_0_NO_CLR(c2h_pkt, value)                        \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_CCX_RPT_GET_QUEUE15_8(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define C2H_CCX_RPT_SET_QUEUE15_8(c2h_pkt, value)                              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_CCX_RPT_SET_QUEUE15_8_NO_CLR(c2h_pkt, value)                       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_CCX_RPT_SET_FINAL_DATA_RATE_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_CCX_RPT_GET_SW_DEFINE_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
+#define C2H_CCX_RPT_SET_SW_DEFINE_0(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_CCX_RPT_SET_SW_DEFINE_0_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_CCX_RPT_GET_SW_DEFINE_1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 8, 4)
+#define C2H_CCX_RPT_SET_SW_DEFINE_1(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 4, value)
+#define C2H_CCX_RPT_SET_SW_DEFINE_1_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 4, value)
+#define C2H_CCX_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_CCX_RPT_SET_LEN(c2h_pkt, value)                                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_CCX_RPT_SET_LEN_NO_CLR(c2h_pkt, value)                             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_CCX_RPT_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_CCX_RPT_SET_TRIGGER(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_CCX_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_CMD_ID(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_SEQ(c2h_pkt, value)                               \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_SEQ_NO_CLR(c2h_pkt, value)                        \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(c2h_pkt)                                 \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(c2h_pkt, value)                          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0_NO_CLR(c2h_pkt, value)                   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(c2h_pkt)                                 \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(c2h_pkt, value)                          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1_NO_CLR(c2h_pkt, value)                   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(c2h_pkt)                            \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(c2h_pkt, value)                     \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1_NO_CLR(c2h_pkt, value)              \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(c2h_pkt)                                 \
+	GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(c2h_pkt, value)                          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0_NO_CLR(c2h_pkt, value)                   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(c2h_pkt)                                 \
+	GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(c2h_pkt, value)                          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1_NO_CLR(c2h_pkt, value)                   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X08, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(c2h_pkt)                            \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(c2h_pkt, value)                     \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2_NO_CLR(c2h_pkt, value)              \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_LEN(c2h_pkt, value)                               \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_LEN_NO_CLR(c2h_pkt, value)                        \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TRIGGER(c2h_pkt)                                  \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_TRIGGER(c2h_pkt, value)                           \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TRIGGER_NO_CLR(c2h_pkt, value)                    \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(c2h_pkt)                        \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(c2h_pkt, value)                 \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID_NO_CLR(c2h_pkt, value)          \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(c2h_pkt)                           \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(c2h_pkt, value)                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ_NO_CLR(c2h_pkt, value)             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(c2h_pkt)                 \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 16, 7)
+#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(c2h_pkt, value)          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 7, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP_NO_CLR(c2h_pkt, value)   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 7, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(c2h_pkt)                 \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(c2h_pkt, value)          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1_NO_CLR(c2h_pkt, value)   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(c2h_pkt)                 \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(c2h_pkt, value)          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2_NO_CLR(c2h_pkt, value)   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(c2h_pkt)                 \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(c2h_pkt, value)          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3_NO_CLR(c2h_pkt, value)   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(c2h_pkt)                 \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(c2h_pkt, value)          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4_NO_CLR(c2h_pkt, value)   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(c2h_pkt)                 \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(c2h_pkt, value)          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5_NO_CLR(c2h_pkt, value)   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(c2h_pkt)                 \
+	GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(c2h_pkt, value)          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6_NO_CLR(c2h_pkt, value)   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(c2h_pkt)                 \
+	GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(c2h_pkt, value)          \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7_NO_CLR(c2h_pkt, value)   \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(c2h_pkt)                           \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(c2h_pkt, value)                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_LEN_NO_CLR(c2h_pkt, value)             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(c2h_pkt)                       \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(c2h_pkt, value)                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER_NO_CLR(c2h_pkt, value)         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_RA_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_RA_RPT_SET_CMD_ID(c2h_pkt, value)                                  \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_RA_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value)                           \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_RA_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_RA_RPT_SET_SEQ(c2h_pkt, value)                                     \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_RA_RPT_SET_SEQ_NO_CLR(c2h_pkt, value)                              \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_RA_RPT_GET_RATE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define C2H_RA_RPT_SET_RATE(c2h_pkt, value)                                    \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_RA_RPT_SET_RATE_NO_CLR(c2h_pkt, value)                             \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_RA_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define C2H_RA_RPT_SET_MACID(c2h_pkt, value)                                   \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_RA_RPT_SET_MACID_NO_CLR(c2h_pkt, value)                            \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_RA_RPT_GET_USE_LDPC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 1)
+#define C2H_RA_RPT_SET_USE_LDPC(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 1, value)
+#define C2H_RA_RPT_SET_USE_LDPC_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 1, value)
+#define C2H_RA_RPT_GET_USE_TXBF(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 1, 1)
+#define C2H_RA_RPT_SET_USE_TXBF(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 1, 1, value)
+#define C2H_RA_RPT_SET_USE_TXBF_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 1, 1, value)
+#define C2H_RA_RPT_GET_COLLISION_STATE(c2h_pkt)                                \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define C2H_RA_RPT_SET_COLLISION_STATE(c2h_pkt, value)                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_RA_RPT_SET_COLLISION_STATE_NO_CLR(c2h_pkt, value)                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_RA_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_RA_RPT_SET_LEN(c2h_pkt, value)                                     \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_RA_RPT_SET_LEN_NO_CLR(c2h_pkt, value)                              \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_RA_RPT_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_RA_RPT_SET_TRIGGER(c2h_pkt, value)                                 \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_RA_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value)                          \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(c2h_pkt)                             \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(c2h_pkt, value)                      \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_CMD_ID_NO_CLR(c2h_pkt, value)               \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_SEQ(c2h_pkt)                                \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_SPECIAL_STATISTICS_SET_SEQ(c2h_pkt, value)                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_SEQ_NO_CLR(c2h_pkt, value)                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(c2h_pkt)                     \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(c2h_pkt, value)              \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX_NO_CLR(c2h_pkt, value)       \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA0(c2h_pkt)                              \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA0(c2h_pkt, value)                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA0_NO_CLR(c2h_pkt, value)                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA1(c2h_pkt)                              \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA1(c2h_pkt, value)                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA1_NO_CLR(c2h_pkt, value)                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA2(c2h_pkt)                              \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA2(c2h_pkt, value)                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA2_NO_CLR(c2h_pkt, value)                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA3(c2h_pkt)                              \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA3(c2h_pkt, value)                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA3_NO_CLR(c2h_pkt, value)                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA4(c2h_pkt)                              \
+	GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA4(c2h_pkt, value)                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA4_NO_CLR(c2h_pkt, value)                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA5(c2h_pkt)                              \
+	GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA5(c2h_pkt, value)                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA5_NO_CLR(c2h_pkt, value)                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA6(c2h_pkt)                              \
+	GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA6(c2h_pkt, value)                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA6_NO_CLR(c2h_pkt, value)                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA7(c2h_pkt)                              \
+	GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA7(c2h_pkt, value)                       \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA7_NO_CLR(c2h_pkt, value)                \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_LEN(c2h_pkt)                                \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_LEN(c2h_pkt, value)                         \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_LEN_NO_CLR(c2h_pkt, value)                  \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(c2h_pkt)                            \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(c2h_pkt, value)                     \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_TRIGGER_NO_CLR(c2h_pkt, value)              \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_RA_PARA_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_RA_PARA_RPT_SET_CMD_ID(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_RA_PARA_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_RA_PARA_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_RA_PARA_RPT_SET_SEQ(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_RA_PARA_RPT_SET_SEQ_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_RA_PARA_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_RA_PARA_RPT_SET_LEN(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_RA_PARA_RPT_SET_LEN_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_RA_PARA_RPT_GET_TRIGGER(c2h_pkt)                                   \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_RA_PARA_RPT_SET_TRIGGER(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_RA_PARA_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_CUR_CHANNEL_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_CUR_CHANNEL_SET_CMD_ID(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_CUR_CHANNEL_SET_CMD_ID_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_CUR_CHANNEL_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_CUR_CHANNEL_SET_SEQ(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_CUR_CHANNEL_SET_SEQ_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(c2h_pkt)                               \
+	GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(c2h_pkt, value)                        \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM_NO_CLR(c2h_pkt, value)                 \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_CUR_CHANNEL_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_CUR_CHANNEL_SET_LEN(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_CUR_CHANNEL_SET_LEN_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_CUR_CHANNEL_GET_TRIGGER(c2h_pkt)                                   \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_CUR_CHANNEL_SET_TRIGGER(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_CUR_CHANNEL_SET_TRIGGER_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_GPIO_WAKEUP_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_GPIO_WAKEUP_SET_CMD_ID(c2h_pkt, value)                             \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_GPIO_WAKEUP_SET_CMD_ID_NO_CLR(c2h_pkt, value)                      \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_GPIO_WAKEUP_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_GPIO_WAKEUP_SET_SEQ(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_GPIO_WAKEUP_SET_SEQ_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_GPIO_WAKEUP_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_GPIO_WAKEUP_SET_LEN(c2h_pkt, value)                                \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_GPIO_WAKEUP_SET_LEN_NO_CLR(c2h_pkt, value)                         \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_GPIO_WAKEUP_GET_TRIGGER(c2h_pkt)                                   \
+	GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_GPIO_WAKEUP_SET_TRIGGER(c2h_pkt, value)                            \
+	SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_GPIO_WAKEUP_SET_TRIGGER_NO_CLR(c2h_pkt, value)                     \
+	SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#endif

hal/halmac/halmac_original_c2h_nic.h

@@ -0,0 +1,408 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_
+#define _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_
+#define CMD_ID_C2H 0X00
+#define CMD_ID_DBG 0X00
+#define CMD_ID_C2H_LB 0X01
+#define CMD_ID_C2H_SND_TXBF 0X02
+#define CMD_ID_C2H_CCX_RPT 0X03
+#define CMD_ID_C2H_AP_REQ_TXRPT 0X04
+#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05
+#define CMD_ID_C2H_RA_RPT 0X0C
+#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D
+#define CMD_ID_C2H_RA_PARA_RPT 0X0E
+#define CMD_ID_C2H_CUR_CHANNEL 0X10
+#define CMD_ID_C2H_GPIO_WAKEUP 0X14
+#define C2H_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_SET_CMD_ID(c2h_pkt, value)                                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_SET_SEQ(c2h_pkt, value)                                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define DBG_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define DBG_SET_CMD_ID(c2h_pkt, value)                                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define DBG_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define DBG_SET_SEQ(c2h_pkt, value)                                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define DBG_GET_DBG_STR1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define DBG_SET_DBG_STR1(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define DBG_GET_DBG_STR2(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define DBG_SET_DBG_STR2(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define DBG_GET_DBG_STR3(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define DBG_SET_DBG_STR3(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define DBG_GET_DBG_STR4(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define DBG_SET_DBG_STR4(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define DBG_GET_DBG_STR5(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define DBG_SET_DBG_STR5(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define DBG_GET_DBG_STR6(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define DBG_SET_DBG_STR6(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define DBG_GET_DBG_STR7(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
+#define DBG_SET_DBG_STR7(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
+#define DBG_GET_DBG_STR8(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)
+#define DBG_SET_DBG_STR8(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)
+#define DBG_GET_DBG_STR9(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)
+#define DBG_SET_DBG_STR9(c2h_pkt, value)                                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)
+#define DBG_GET_DBG_STR10(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8)
+#define DBG_SET_DBG_STR10(c2h_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value)
+#define DBG_GET_DBG_STR11(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8)
+#define DBG_SET_DBG_STR11(c2h_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value)
+#define DBG_GET_DBG_STR12(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8)
+#define DBG_SET_DBG_STR12(c2h_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value)
+#define DBG_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define DBG_SET_LEN(c2h_pkt, value)                                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define DBG_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define DBG_SET_TRIGGER(c2h_pkt, value)                                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_LB_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_LB_SET_CMD_ID(c2h_pkt, value)                                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_LB_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_LB_SET_SEQ(c2h_pkt, value)                                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_LB_GET_PAYLOAD1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 16)
+#define C2H_LB_SET_PAYLOAD1(c2h_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 16, value)
+#define C2H_LB_GET_PAYLOAD2(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 32)
+#define C2H_LB_SET_PAYLOAD2(c2h_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 32, value)
+#define C2H_LB_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_LB_SET_LEN(c2h_pkt, value)                                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_LB_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_LB_SET_TRIGGER(c2h_pkt, value)                                     \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_SND_TXBF_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_SND_TXBF_SET_CMD_ID(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SND_TXBF_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_SND_TXBF_SET_SEQ(c2h_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SND_TXBF_GET_SND_RESULT(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 1)
+#define C2H_SND_TXBF_SET_SND_RESULT(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 1, value)
+#define C2H_SND_TXBF_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_SND_TXBF_SET_LEN(c2h_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_SND_TXBF_GET_TRIGGER(c2h_pkt)                                      \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_SND_TXBF_SET_TRIGGER(c2h_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_CCX_RPT_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_CCX_RPT_SET_CMD_ID(c2h_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_CCX_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_CCX_RPT_SET_SEQ(c2h_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_CCX_RPT_GET_QSEL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 5)
+#define C2H_CCX_RPT_SET_QSEL(c2h_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 5, value)
+#define C2H_CCX_RPT_GET_BMC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 21, 1)
+#define C2H_CCX_RPT_SET_BMC(c2h_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 21, 1, value)
+#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(c2h_pkt)                                \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 22, 1)
+#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(c2h_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 22, 1, value)
+#define C2H_CCX_RPT_GET_RETRY_OVER(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 23, 1)
+#define C2H_CCX_RPT_SET_RETRY_OVER(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 23, 1, value)
+#define C2H_CCX_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define C2H_CCX_RPT_SET_MACID(c2h_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(c2h_pkt)                                \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 6)
+#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(c2h_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 6, value)
+#define C2H_CCX_RPT_GET_QUEUE7_0(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define C2H_CCX_RPT_SET_QUEUE7_0(c2h_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_CCX_RPT_GET_QUEUE15_8(c2h_pkt)                                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define C2H_CCX_RPT_SET_QUEUE15_8(c2h_pkt, value)                              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_CCX_RPT_GET_SW_DEFINE_0(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
+#define C2H_CCX_RPT_SET_SW_DEFINE_0(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_CCX_RPT_GET_SW_DEFINE_1(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 4)
+#define C2H_CCX_RPT_SET_SW_DEFINE_1(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 4, value)
+#define C2H_CCX_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_CCX_RPT_SET_LEN(c2h_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_CCX_RPT_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_CCX_RPT_SET_TRIGGER(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_CMD_ID(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_CMD_ID(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_SEQ(c2h_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(c2h_pkt)                                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(c2h_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(c2h_pkt)                                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(c2h_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(c2h_pkt)                            \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(c2h_pkt, value)                     \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(c2h_pkt)                                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(c2h_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(c2h_pkt)                                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(c2h_pkt, value)                          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(c2h_pkt)                            \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(c2h_pkt, value)                     \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_LEN(c2h_pkt)                                      \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_LEN(c2h_pkt, value)                               \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TRIGGER(c2h_pkt)                                  \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_TRIGGER(c2h_pkt, value)                           \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(c2h_pkt)                        \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(c2h_pkt, value)                 \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(c2h_pkt)                           \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(c2h_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(c2h_pkt)                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 7)
+#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(c2h_pkt, value)          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 7, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(c2h_pkt)                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(c2h_pkt, value)          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(c2h_pkt)                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(c2h_pkt, value)          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(c2h_pkt)                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(c2h_pkt, value)          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(c2h_pkt)                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(c2h_pkt, value)          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(c2h_pkt)                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(c2h_pkt, value)          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(c2h_pkt)                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(c2h_pkt, value)          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(c2h_pkt)                 \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(c2h_pkt, value)          \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(c2h_pkt)                           \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(c2h_pkt, value)                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(c2h_pkt)                       \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(c2h_pkt, value)                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_RA_RPT_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_RA_RPT_SET_CMD_ID(c2h_pkt, value)                                  \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_RA_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_RA_RPT_SET_SEQ(c2h_pkt, value)                                     \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_RA_RPT_GET_RATE(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define C2H_RA_RPT_SET_RATE(c2h_pkt, value)                                    \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_RA_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define C2H_RA_RPT_SET_MACID(c2h_pkt, value)                                   \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_RA_RPT_GET_USE_LDPC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 1)
+#define C2H_RA_RPT_SET_USE_LDPC(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 1, value)
+#define C2H_RA_RPT_GET_USE_TXBF(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 1, 1)
+#define C2H_RA_RPT_SET_USE_TXBF(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 1, 1, value)
+#define C2H_RA_RPT_GET_COLLISION_STATE(c2h_pkt)                                \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define C2H_RA_RPT_SET_COLLISION_STATE(c2h_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_RA_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_RA_RPT_SET_LEN(c2h_pkt, value)                                     \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_RA_RPT_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_RA_RPT_SET_TRIGGER(c2h_pkt, value)                                 \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(c2h_pkt)                             \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(c2h_pkt, value)                      \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_SEQ(c2h_pkt)                                \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_SPECIAL_STATISTICS_SET_SEQ(c2h_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(c2h_pkt)                     \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(c2h_pkt, value)              \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA0(c2h_pkt)                              \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA0(c2h_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA1(c2h_pkt)                              \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA1(c2h_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA2(c2h_pkt)                              \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA2(c2h_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA3(c2h_pkt)                              \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA3(c2h_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA4(c2h_pkt)                              \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA4(c2h_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA5(c2h_pkt)                              \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA5(c2h_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA6(c2h_pkt)                              \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA6(c2h_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA7(c2h_pkt)                              \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA7(c2h_pkt, value)                       \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_LEN(c2h_pkt)                                \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_LEN(c2h_pkt, value)                         \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(c2h_pkt)                            \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(c2h_pkt, value)                     \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_RA_PARA_RPT_GET_CMD_ID(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_RA_PARA_RPT_SET_CMD_ID(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_RA_PARA_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_RA_PARA_RPT_SET_SEQ(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_RA_PARA_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_RA_PARA_RPT_SET_LEN(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_RA_PARA_RPT_GET_TRIGGER(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_RA_PARA_RPT_SET_TRIGGER(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_CUR_CHANNEL_GET_CMD_ID(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_CUR_CHANNEL_SET_CMD_ID(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_CUR_CHANNEL_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_CUR_CHANNEL_SET_SEQ(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(c2h_pkt)                               \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(c2h_pkt, value)                        \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_CUR_CHANNEL_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_CUR_CHANNEL_SET_LEN(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_CUR_CHANNEL_GET_TRIGGER(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_CUR_CHANNEL_SET_TRIGGER(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_GPIO_WAKEUP_GET_CMD_ID(c2h_pkt)                                    \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_GPIO_WAKEUP_SET_CMD_ID(c2h_pkt, value)                             \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_GPIO_WAKEUP_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_GPIO_WAKEUP_SET_SEQ(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_GPIO_WAKEUP_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_GPIO_WAKEUP_SET_LEN(c2h_pkt, value)                                \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_GPIO_WAKEUP_GET_TRIGGER(c2h_pkt)                                   \
+	LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_GPIO_WAKEUP_SET_TRIGGER(c2h_pkt, value)                            \
+	SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#endif

hal/halmac/halmac_pcie_reg.h

@@ -0,0 +1,36 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __HALMAC_PCIE_REG_H__
+#define __HALMAC_PCIE_REG_H__
+
+/* PCIE PHY register */
+#define RAC_CTRL_PPR		0x00
+#define RAC_SET_PPR		0x20
+#define RAC_TRG_PPR		0x21
+
+/* PCIE CFG register */
+#define PCIE_L1_BACKDOOR		0x719
+#define PCIE_ASPM_CTRL			0x70F
+
+/* PCIE MAC register */
+#define LINK_CTRL2_REG_OFFSET		0xA0
+#define GEN2_CTRL_OFFSET		0x80C
+#define LINK_STATUS_REG_OFFSET		0x82
+
+#define PCIE_GEN1_SPEED			0x01
+#define PCIE_GEN2_SPEED			0x02
+
+#endif/* __HALMAC_PCIE_REG_H__ */

hal/halmac/halmac_pwr_seq_cmd.h

@@ -0,0 +1,111 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef HALMAC_POWER_SEQUENCE_CMD
+#define HALMAC_POWER_SEQUENCE_CMD
+
+#include "halmac_2_platform.h"
+
+#define HALMAC_PWR_POLLING_CNT 20000
+
+/*
+ * The value of cmd : 4 bits
+ */
+
+/*
+ * offset : the read register offset
+ * msk : the mask of the read value
+ * value : N/A, left by 0
+ * Note : dirver shall implement this function by read & msk
+ */
+#define	HALMAC_PWR_CMD_READ		0x00
+/*
+ * offset: the read register offset
+ * msk: the mask of the write bits
+ * value: write value
+ * Note: driver shall implement this cmd by read & msk after write
+ */
+#define	HALMAC_PWR_CMD_WRITE	0x01
+/*
+ * offset: the read register offset
+ * msk: the mask of the polled value
+ * value: the value to be polled, masked by the msd field.
+ * Note: driver shall implement this cmd by
+ * do{
+ * if( (Read(offset) & msk) == (value & msk) )
+ * break;
+ * } while(not timeout);
+ */
+#define	HALMAC_PWR_CMD_POLLING	0x02
+/*
+ * offset: the value to delay
+ * msk: N/A
+ * value: the unit of delay, 0: us, 1: ms
+ */
+#define	HALMAC_PWR_CMD_DELAY	0x03
+/*
+ * offset: N/A
+ * msk: N/A
+ * value: N/A
+ */
+#define	HALMAC_PWR_CMD_END	0x04
+
+/*
+ * The value of base : 4 bits
+ */
+
+/* define the base address of each block */
+#define   HALMAC_PWR_ADDR_MAC	0x00
+#define   HALMAC_PWR_ADDR_USB	0x01
+#define   HALMAC_PWR_ADDR_PCIE	0x02
+#define   HALMAC_PWR_ADDR_SDIO	0x03
+
+/*
+ * The value of interface_msk : 4 bits
+ */
+#define	HALMAC_PWR_INTF_SDIO_MSK	BIT(0)
+#define	HALMAC_PWR_INTF_USB_MSK		BIT(1)
+#define	HALMAC_PWR_INTF_PCI_MSK		BIT(2)
+#define	HALMAC_PWR_INTF_ALL_MSK		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
+
+/*
+ * The value of cut_msk : 8 bits
+ */
+#define	HALMAC_PWR_CUT_TESTCHIP_MSK		BIT(0)
+#define	HALMAC_PWR_CUT_A_MSK			BIT(1)
+#define	HALMAC_PWR_CUT_B_MSK			BIT(2)
+#define	HALMAC_PWR_CUT_C_MSK			BIT(3)
+#define	HALMAC_PWR_CUT_D_MSK			BIT(4)
+#define	HALMAC_PWR_CUT_E_MSK			BIT(5)
+#define	HALMAC_PWR_CUT_F_MSK			BIT(6)
+#define	HALMAC_PWR_CUT_G_MSK			BIT(7)
+#define	HALMAC_PWR_CUT_ALL_MSK			0xFF
+
+enum halmac_pwrseq_cmd_delay_unit {
+	HALMAC_PWR_DELAY_US,
+	HALMAC_PWR_DELAY_MS,
+};
+
+struct halmac_wlan_pwr_cfg {
+	u16 offset;
+	u8 cut_msk;
+	u8 interface_msk;
+	u8 base:4;
+	u8 cmd:4;
+	u8 msk;
+	u8 value;
+};
+
+#endif

hal/halmac/halmac_reg_8197f.h

@@ -0,0 +1,700 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_REG_8197F_H
+#define __INC_HALMAC_REG_8197F_H
+
+#define REG_SYS_ISO_CTRL_8197F 0x0000
+#define REG_SYS_FUNC_EN_8197F 0x0002
+#define REG_SYS_PW_CTRL_8197F 0x0004
+#define REG_SYS_CLK_CTRL_8197F 0x0008
+#define REG_SYS_EEPROM_CTRL_8197F 0x000A
+#define REG_EE_VPD_8197F 0x000C
+#define REG_SYS_SWR_CTRL1_8197F 0x0010
+#define REG_SYS_SWR_CTRL2_8197F 0x0014
+#define REG_SYS_SWR_CTRL3_8197F 0x0018
+#define REG_RSV_CTRL_8197F 0x001C
+#define REG_RF0_CTRL_8197F 0x001F
+#define REG_AFE_LDO_CTRL_8197F 0x0020
+#define REG_AFE_CTRL1_8197F 0x0024
+#define REG_AFE_CTRL2_8197F 0x0028
+#define REG_AFE_CTRL3_8197F 0x002C
+#define REG_EFUSE_CTRL_8197F 0x0030
+#define REG_LDO_EFUSE_CTRL_8197F 0x0034
+#define REG_PWR_OPTION_CTRL_8197F 0x0038
+#define REG_CAL_TIMER_8197F 0x003C
+#define REG_ACLK_MON_8197F 0x003E
+#define REG_GPIO_MUXCFG_8197F 0x0040
+#define REG_GPIO_PIN_CTRL_8197F 0x0044
+#define REG_GPIO_INTM_8197F 0x0048
+#define REG_LED_CFG_8197F 0x004C
+#define REG_FSIMR_8197F 0x0050
+#define REG_FSISR_8197F 0x0054
+#define REG_HSIMR_8197F 0x0058
+#define REG_HSISR_8197F 0x005C
+#define REG_GPIO_EXT_CTRL_8197F 0x0060
+#define REG_PAD_CTRL1_8197F 0x0064
+#define REG_WL_BT_PWR_CTRL_8197F 0x0068
+#define REG_SDM_DEBUG_8197F 0x006C
+#define REG_SYS_SDIO_CTRL_8197F 0x0070
+#define REG_HCI_OPT_CTRL_8197F 0x0074
+#define REG_AFE_CTRL4_8197F 0x0078
+#define REG_LDO_SWR_CTRL_8197F 0x007C
+#define REG_MCUFW_CTRL_8197F 0x0080
+#define REG_MCU_TST_CFG_8197F 0x0084
+#define REG_HMEBOX_E0_E1_8197F 0x0088
+#define REG_HMEBOX_E2_E3_8197F 0x008C
+#define REG_WLLPS_CTRL_8197F 0x0090
+#define REG_AFE_CTRL5_8197F 0x0094
+#define REG_GPIO_DEBOUNCE_CTRL_8197F 0x0098
+#define REG_RPWM2_8197F 0x009C
+#define REG_SYSON_FSM_MON_8197F 0x00A0
+#define REG_AFE_CTRL6_8197F 0x00A4
+#define REG_PMC_DBG_CTRL1_8197F 0x00A8
+#define REG_AFE_CTRL7_8197F 0x00AC
+#define REG_HIMR0_8197F 0x00B0
+#define REG_HISR0_8197F 0x00B4
+#define REG_HIMR1_8197F 0x00B8
+#define REG_HISR1_8197F 0x00BC
+#define REG_DBG_PORT_SEL_8197F 0x00C0
+#define REG_PAD_CTRL2_8197F 0x00C4
+#define REG_PMC_DBG_CTRL2_8197F 0x00CC
+#define REG_BIST_CTRL_8197F 0x00D0
+#define REG_BIST_RPT_8197F 0x00D4
+#define REG_MEM_CTRL_8197F 0x00D8
+#define REG_AFE_CTRL8_8197F 0x00DC
+#define REG_USB_SIE_INTF_8197F 0x00E0
+#define REG_PCIE_MIO_INTF_8197F 0x00E4
+#define REG_PCIE_MIO_INTD_8197F 0x00E8
+#define REG_WLRF1_8197F 0x00EC
+#define REG_SYS_CFG1_8197F 0x00F0
+#define REG_SYS_STATUS1_8197F 0x00F4
+#define REG_SYS_STATUS2_8197F 0x00F8
+#define REG_SYS_CFG2_8197F 0x00FC
+#define REG_SYS_CFG3_8197F 0x1000
+#define REG_SYS_CFG4_8197F 0x1034
+#define REG_CPU_DMEM_CON_8197F 0x1080
+#define REG_HIMR2_8197F 0x10B0
+#define REG_HISR2_8197F 0x10B4
+#define REG_HIMR3_8197F 0x10B8
+#define REG_HISR3_8197F 0x10BC
+#define REG_SW_MDIO_8197F 0x10C0
+#define REG_SW_FLUSH_8197F 0x10C4
+#define REG_DBG_GPIO_BMUX_8197F 0x10C8
+#define REG_FPGA_TAG_8197F 0x10CC
+#define REG_WL_DSS_CTRL0_8197F 0x10D0
+#define REG_WL_DSS_CTRL1_8197F 0x10D8
+#define REG_WL_DSS_STATUS1_8197F 0x10DC
+#define REG_FW_DBG0_8197F 0x10E0
+#define REG_FW_DBG1_8197F 0x10E4
+#define REG_FW_DBG2_8197F 0x10E8
+#define REG_FW_DBG3_8197F 0x10EC
+#define REG_FW_DBG4_8197F 0x10F0
+#define REG_FW_DBG5_8197F 0x10F4
+#define REG_FW_DBG6_8197F 0x10F8
+#define REG_FW_DBG7_8197F 0x10FC
+#define REG_CR_8197F 0x0100
+#define REG_TSF_CLK_STATE_8197F 0x0108
+#define REG_TXDMA_PQ_MAP_8197F 0x010C
+#define REG_TRXFF_BNDY_8197F 0x0114
+#define REG_PTA_I2C_MBOX_8197F 0x0118
+#define REG_RXFF_BNDY_8197F 0x011C
+#define REG_FE1IMR_8197F 0x0120
+#define REG_FE1ISR_8197F 0x0124
+#define REG_CPWM_8197F 0x012C
+#define REG_FWIMR_8197F 0x0130
+#define REG_FWISR_8197F 0x0134
+#define REG_FTIMR_8197F 0x0138
+#define REG_FTISR_8197F 0x013C
+#define REG_PKTBUF_DBG_CTRL_8197F 0x0140
+#define REG_PKTBUF_DBG_DATA_L_8197F 0x0144
+#define REG_PKTBUF_DBG_DATA_H_8197F 0x0148
+#define REG_CPWM2_8197F 0x014C
+#define REG_TC0_CTRL_8197F 0x0150
+#define REG_TC1_CTRL_8197F 0x0154
+#define REG_TC2_CTRL_8197F 0x0158
+#define REG_TC3_CTRL_8197F 0x015C
+#define REG_TC4_CTRL_8197F 0x0160
+#define REG_TCUNIT_BASE_8197F 0x0164
+#define REG_TC5_CTRL_8197F 0x0168
+#define REG_TC6_CTRL_8197F 0x016C
+#define REG_MBIST_FAIL_8197F 0x0170
+#define REG_MBIST_START_PAUSE_8197F 0x0174
+#define REG_MBIST_DONE_8197F 0x0178
+#define REG_MBIST_FAIL_NRML_8197F 0x017C
+#define REG_AES_DECRPT_DATA_8197F 0x0180
+#define REG_AES_DECRPT_CFG_8197F 0x0184
+#define REG_MACCLKFRQ_8197F 0x018C
+#define REG_TMETER_8197F 0x0190
+#define REG_OSC_32K_CTRL_8197F 0x0194
+#define REG_32K_CAL_REG1_8197F 0x0198
+#define REG_C2HEVT_8197F 0x01A0
+#define REG_SW_DEFINED_PAGE1_8197F 0x01B8
+#define REG_MCUTST_I_8197F 0x01C0
+#define REG_MCUTST_II_8197F 0x01C4
+#define REG_FMETHR_8197F 0x01C8
+#define REG_HMETFR_8197F 0x01CC
+#define REG_HMEBOX0_8197F 0x01D0
+#define REG_HMEBOX1_8197F 0x01D4
+#define REG_HMEBOX2_8197F 0x01D8
+#define REG_HMEBOX3_8197F 0x01DC
+#define REG_LLT_INIT_8197F 0x01E0
+#define REG_LLT_INIT_ADDR_8197F 0x01E4
+#define REG_BB_ACCESS_CTRL_8197F 0x01E8
+#define REG_BB_ACCESS_DATA_8197F 0x01EC
+#define REG_HMEBOX_E0_8197F 0x01F0
+#define REG_HMEBOX_E1_8197F 0x01F4
+#define REG_HMEBOX_E2_8197F 0x01F8
+#define REG_HMEBOX_E3_8197F 0x01FC
+#define REG_CR_EXT_8197F 0x1100
+#define REG_FWFF_8197F 0x1114
+#define REG_RXFF_PTR_V1_8197F 0x1118
+#define REG_RXFF_WTR_V1_8197F 0x111C
+#define REG_FE2IMR_8197F 0x1120
+#define REG_FE2ISR_8197F 0x1124
+#define REG_FE3IMR_8197F 0x1128
+#define REG_FE3ISR_8197F 0x112C
+#define REG_FE4IMR_8197F 0x1130
+#define REG_FE4ISR_8197F 0x1134
+#define REG_FT1IMR_8197F 0x1138
+#define REG_FT1ISR_8197F 0x113C
+#define REG_SPWR0_8197F 0x1140
+#define REG_SPWR1_8197F 0x1144
+#define REG_SPWR2_8197F 0x1148
+#define REG_SPWR3_8197F 0x114C
+#define REG_POWSEQ_8197F 0x1150
+#define REG_TC7_CTRL_V1_8197F 0x1158
+#define REG_TC8_CTRL_V1_8197F 0x115C
+#define REG_RXBCN_TBTT_INTERVAL_PORT0TO3_8197F 0x1160
+#define REG_RXBCN_TBTT_INTERVAL_PORT4_8197F 0x1164
+#define REG_EXT_QUEUE_REG_8197F 0x11C0
+#define REG_COUNTER_CONTROL_8197F 0x11C4
+#define REG_COUNTER_TH_8197F 0x11C8
+#define REG_COUNTER_SET_8197F 0x11CC
+#define REG_COUNTER_OVERFLOW_8197F 0x11D0
+#define REG_TDE_LEN_TH_8197F 0x11D4
+#define REG_RDE_LEN_TH_8197F 0x11D8
+#define REG_PCIE_EXEC_TIME_8197F 0x11DC
+#define REG_FT2IMR_8197F 0x11E0
+#define REG_FT2ISR_8197F 0x11E4
+#define REG_MSG2_8197F 0x11F0
+#define REG_MSG3_8197F 0x11F4
+#define REG_MSG4_8197F 0x11F8
+#define REG_MSG5_8197F 0x11FC
+#define REG_FIFOPAGE_CTRL_1_8197F 0x0200
+#define REG_FIFOPAGE_CTRL_2_8197F 0x0204
+#define REG_AUTO_LLT_V1_8197F 0x0208
+#define REG_TXDMA_OFFSET_CHK_8197F 0x020C
+#define REG_TXDMA_STATUS_8197F 0x0210
+#define REG_TX_DMA_DBG_8197F 0x0214
+#define REG_TQPNT1_8197F 0x0218
+#define REG_TQPNT2_8197F 0x021C
+#define REG_TQPNT3_8197F 0x0220
+#define REG_TQPNT4_8197F 0x0224
+#define REG_RQPN_CTRL_1_8197F 0x0228
+#define REG_RQPN_CTRL_2_8197F 0x022C
+#define REG_FIFOPAGE_INFO_1_8197F 0x0230
+#define REG_FIFOPAGE_INFO_2_8197F 0x0234
+#define REG_FIFOPAGE_INFO_3_8197F 0x0238
+#define REG_FIFOPAGE_INFO_4_8197F 0x023C
+#define REG_FIFOPAGE_INFO_5_8197F 0x0240
+#define REG_H2C_HEAD_8197F 0x0244
+#define REG_H2C_TAIL_8197F 0x0248
+#define REG_H2C_READ_ADDR_8197F 0x024C
+#define REG_H2C_WR_ADDR_8197F 0x0250
+#define REG_H2C_INFO_8197F 0x0254
+#define REG_RXDMA_AGG_PG_TH_8197F 0x0280
+#define REG_RXPKT_NUM_8197F 0x0284
+#define REG_RXDMA_STATUS_8197F 0x0288
+#define REG_RXDMA_DPR_8197F 0x028C
+#define REG_RXDMA_MODE_8197F 0x0290
+#define REG_C2H_PKT_8197F 0x0294
+#define REG_FWFF_C2H_8197F 0x0298
+#define REG_FWFF_CTRL_8197F 0x029C
+#define REG_FWFF_PKT_INFO_8197F 0x02A0
+#define REG_FC2H_INFO_8197F 0x02A4
+#define REG_DDMA_CH0SA_8197F 0x1200
+#define REG_DDMA_CH0DA_8197F 0x1204
+#define REG_DDMA_CH0CTRL_8197F 0x1208
+#define REG_DDMA_CH1SA_8197F 0x1210
+#define REG_DDMA_CH1DA_8197F 0x1214
+#define REG_DDMA_CH1CTRL_8197F 0x1218
+#define REG_DDMA_CH2SA_8197F 0x1220
+#define REG_DDMA_CH2DA_8197F 0x1224
+#define REG_DDMA_CH2CTRL_8197F 0x1228
+#define REG_DDMA_CH3SA_8197F 0x1230
+#define REG_DDMA_CH3DA_8197F 0x1234
+#define REG_DDMA_CH3CTRL_8197F 0x1238
+#define REG_DDMA_CH4SA_8197F 0x1240
+#define REG_DDMA_CH4DA_8197F 0x1244
+#define REG_DDMA_CH4CTRL_8197F 0x1248
+#define REG_DDMA_CH5SA_8197F 0x1250
+#define REG_DDMA_CH5DA_8197F 0x1254
+#define REG_REG_DDMA_CH5CTRL_8197F 0x1258
+#define REG_DDMA_INT_MSK_8197F 0x12E0
+#define REG_DDMA_CHSTATUS_8197F 0x12E8
+#define REG_DDMA_CHKSUM_8197F 0x12F0
+#define REG_DDMA_MONITOR_8197F 0x12FC
+#define REG_HCI_CTRL_8197F 0x0300
+#define REG_INT_MIG_8197F 0x0304
+#define REG_BCNQ_TXBD_DESA_8197F 0x0308
+#define REG_MGQ_TXBD_DESA_8197F 0x0310
+#define REG_VOQ_TXBD_DESA_8197F 0x0318
+#define REG_VIQ_TXBD_DESA_8197F 0x0320
+#define REG_BEQ_TXBD_DESA_8197F 0x0328
+#define REG_BKQ_TXBD_DESA_8197F 0x0330
+#define REG_RXQ_RXBD_DESA_8197F 0x0338
+#define REG_HI0Q_TXBD_DESA_8197F 0x0340
+#define REG_HI1Q_TXBD_DESA_8197F 0x0348
+#define REG_HI2Q_TXBD_DESA_8197F 0x0350
+#define REG_HI3Q_TXBD_DESA_8197F 0x0358
+#define REG_HI4Q_TXBD_DESA_8197F 0x0360
+#define REG_HI5Q_TXBD_DESA_8197F 0x0368
+#define REG_HI6Q_TXBD_DESA_8197F 0x0370
+#define REG_HI7Q_TXBD_DESA_8197F 0x0378
+#define REG_MGQ_TXBD_NUM_8197F 0x0380
+#define REG_RX_RXBD_NUM_8197F 0x0382
+#define REG_VOQ_TXBD_NUM_8197F 0x0384
+#define REG_VIQ_TXBD_NUM_8197F 0x0386
+#define REG_BEQ_TXBD_NUM_8197F 0x0388
+#define REG_BKQ_TXBD_NUM_8197F 0x038A
+#define REG_HI0Q_TXBD_NUM_8197F 0x038C
+#define REG_HI1Q_TXBD_NUM_8197F 0x038E
+#define REG_HI2Q_TXBD_NUM_8197F 0x0390
+#define REG_HI3Q_TXBD_NUM_8197F 0x0392
+#define REG_HI4Q_TXBD_NUM_8197F 0x0394
+#define REG_HI5Q_TXBD_NUM_8197F 0x0396
+#define REG_HI6Q_TXBD_NUM_8197F 0x0398
+#define REG_HI7Q_TXBD_NUM_8197F 0x039A
+#define REG_TSFTIMER_HCI_8197F 0x039C
+#define REG_BD_RWPTR_CLR_8197F 0x039C
+#define REG_VOQ_TXBD_IDX_8197F 0x03A0
+#define REG_VIQ_TXBD_IDX_8197F 0x03A4
+#define REG_BEQ_TXBD_IDX_8197F 0x03A8
+#define REG_BKQ_TXBD_IDX_8197F 0x03AC
+#define REG_MGQ_TXBD_IDX_8197F 0x03B0
+#define REG_RXQ_RXBD_IDX_8197F 0x03B4
+#define REG_HI0Q_TXBD_IDX_8197F 0x03B8
+#define REG_HI1Q_TXBD_IDX_8197F 0x03BC
+#define REG_HI2Q_TXBD_IDX_8197F 0x03C0
+#define REG_HI3Q_TXBD_IDX_8197F 0x03C4
+#define REG_HI4Q_TXBD_IDX_8197F 0x03C8
+#define REG_HI5Q_TXBD_IDX_8197F 0x03CC
+#define REG_HI6Q_TXBD_IDX_8197F 0x03D0
+#define REG_HI7Q_TXBD_IDX_8197F 0x03D4
+#define REG_DBG_SEL_V1_8197F 0x03D8
+#define REG_HCI_HRPWM1_V1_8197F 0x03D9
+#define REG_HCI_HCPWM1_V1_8197F 0x03DA
+#define REG_HCI_CTRL2_8197F 0x03DB
+#define REG_HCI_HRPWM2_V1_8197F 0x03DC
+#define REG_HCI_HCPWM2_V1_8197F 0x03DE
+#define REG_HCI_H2C_MSG_V1_8197F 0x03E0
+#define REG_HCI_C2H_MSG_V1_8197F 0x03E4
+#define REG_DBI_WDATA_V1_8197F 0x03E8
+#define REG_DBI_RDATA_V1_8197F 0x03EC
+#define REG_STUCK_FLAG_V1_8197F 0x03F0
+#define REG_MDIO_V1_8197F 0x03F4
+#define REG_WDT_CFG_8197F 0x03F8
+#define REG_HCI_MIX_CFG_8197F 0x03FC
+#define REG_STC_INT_CS_8197F 0x1300
+#define REG_ST_INT_CFG_8197F 0x1304
+#define REG_CMU_DLY_CTRL_8197F 0x1310
+#define REG_CMU_DLY_CFG_8197F 0x1314
+#define REG_H2CQ_TXBD_DESA_8197F 0x1320
+#define REG_H2CQ_TXBD_NUM_8197F 0x1328
+#define REG_H2CQ_TXBD_IDX_8197F 0x132C
+#define REG_H2CQ_CSR_8197F 0x1330
+#define REG_AXI_EXCEPT_CS_8197F 0x1350
+#define REG_AXI_EXCEPT_TIME_8197F 0x1354
+#define REG_Q0_INFO_8197F 0x0400
+#define REG_Q1_INFO_8197F 0x0404
+#define REG_Q2_INFO_8197F 0x0408
+#define REG_Q3_INFO_8197F 0x040C
+#define REG_MGQ_INFO_8197F 0x0410
+#define REG_HIQ_INFO_8197F 0x0414
+#define REG_BCNQ_INFO_8197F 0x0418
+#define REG_TXPKT_EMPTY_8197F 0x041A
+#define REG_CPU_MGQ_INFO_8197F 0x041C
+#define REG_FWHW_TXQ_CTRL_8197F 0x0420
+#define REG_BCNQ_BDNY_V1_8197F 0x0424
+#define REG_LIFETIME_EN_8197F 0x0426
+#define REG_SPEC_SIFS_8197F 0x0428
+#define REG_RETRY_LIMIT_8197F 0x042A
+#define REG_TXBF_CTRL_8197F 0x042C
+#define REG_DARFRC_8197F 0x0430
+#define REG_RARFRC_8197F 0x0438
+#define REG_RRSR_8197F 0x0440
+#define REG_ARFR0_8197F 0x0444
+#define REG_ARFR1_V1_8197F 0x044C
+#define REG_CCK_CHECK_8197F 0x0454
+#define REG_AMPDU_MAX_TIME_V1_8197F 0x0455
+#define REG_BCNQ1_BDNY_V1_8197F 0x0456
+#define REG_AMPDU_MAX_LENGTH_8197F 0x0458
+#define REG_ACQ_STOP_8197F 0x045C
+#define REG_NDPA_RATE_8197F 0x045D
+#define REG_TX_HANG_CTRL_8197F 0x045E
+#define REG_NDPA_OPT_CTRL_8197F 0x045F
+#define REG_RD_RESP_PKT_TH_8197F 0x0463
+#define REG_CMDQ_INFO_8197F 0x0464
+#define REG_Q4_INFO_8197F 0x0468
+#define REG_Q5_INFO_8197F 0x046C
+#define REG_Q6_INFO_8197F 0x0470
+#define REG_Q7_INFO_8197F 0x0474
+#define REG_WMAC_LBK_BUF_HD_V1_8197F 0x0478
+#define REG_MGQ_BDNY_V1_8197F 0x047A
+#define REG_TXRPT_CTRL_8197F 0x047C
+#define REG_INIRTS_RATE_SEL_8197F 0x0480
+#define REG_BASIC_CFEND_RATE_8197F 0x0481
+#define REG_STBC_CFEND_RATE_8197F 0x0482
+#define REG_DATA_SC_8197F 0x0483
+#define REG_MACID_SLEEP3_8197F 0x0484
+#define REG_MACID_SLEEP1_8197F 0x0488
+#define REG_ARFR2_V1_8197F 0x048C
+#define REG_ARFR3_V1_8197F 0x0494
+#define REG_ARFR4_8197F 0x049C
+#define REG_ARFR5_8197F 0x04A4
+#define REG_TXRPT_START_OFFSET_8197F 0x04AC
+#define REG_POWER_STAGE1_8197F 0x04B4
+#define REG_POWER_STAGE2_8197F 0x04B8
+#define REG_SW_AMPDU_BURST_MODE_CTRL_8197F 0x04BC
+#define REG_PKT_LIFE_TIME_8197F 0x04C0
+#define REG_STBC_SETTING_8197F 0x04C4
+#define REG_STBC_SETTING2_8197F 0x04C5
+#define REG_QUEUE_CTRL_8197F 0x04C6
+#define REG_SINGLE_AMPDU_CTRL_8197F 0x04C7
+#define REG_PROT_MODE_CTRL_8197F 0x04C8
+#define REG_BAR_MODE_CTRL_8197F 0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT_8197F 0x04CF
+#define REG_MACID_SLEEP2_8197F 0x04D0
+#define REG_MACID_SLEEP_8197F 0x04D4
+#define REG_HW_SEQ0_8197F 0x04D8
+#define REG_HW_SEQ1_8197F 0x04DA
+#define REG_HW_SEQ2_8197F 0x04DC
+#define REG_HW_SEQ3_8197F 0x04DE
+#define REG_NULL_PKT_STATUS_V1_8197F 0x04E0
+#define REG_PTCL_ERR_STATUS_8197F 0x04E2
+#define REG_NULL_PKT_STATUS_EXTEND_8197F 0x04E3
+#define REG_VIDEO_ENHANCEMENT_FUN_8197F 0x04E4
+#define REG_BT_POLLUTE_PKT_CNT_8197F 0x04E8
+#define REG_PTCL_DBG_8197F 0x04EC
+#define REG_TXOP_EXTRA_CTRL_8197F 0x04F0
+#define REG_CPUMGQ_TIMER_CTRL2_8197F 0x04F4
+#define REG_DUMMY_PAGE4_8197F 0x04FC
+#define REG_Q0_Q1_INFO_8197F 0x1400
+#define REG_Q2_Q3_INFO_8197F 0x1404
+#define REG_Q4_Q5_INFO_8197F 0x1408
+#define REG_Q6_Q7_INFO_8197F 0x140C
+#define REG_MGQ_HIQ_INFO_8197F 0x1410
+#define REG_CMDQ_BCNQ_INFO_8197F 0x1414
+#define REG_USEREG_SETTING_8197F 0x1420
+#define REG_AESIV_SETTING_8197F 0x1424
+#define REG_BF0_TIME_SETTING_8197F 0x1428
+#define REG_BF1_TIME_SETTING_8197F 0x142C
+#define REG_BF_TIMEOUT_EN_8197F 0x1430
+#define REG_MACID_RELEASE0_8197F 0x1434
+#define REG_MACID_RELEASE1_8197F 0x1438
+#define REG_MACID_RELEASE2_8197F 0x143C
+#define REG_MACID_RELEASE3_8197F 0x1440
+#define REG_MACID_RELEASE_SETTING_8197F 0x1444
+#define REG_FAST_EDCA_VOVI_SETTING_8197F 0x1448
+#define REG_FAST_EDCA_BEBK_SETTING_8197F 0x144C
+#define REG_MACID_DROP0_8197F 0x1450
+#define REG_MACID_DROP1_8197F 0x1454
+#define REG_MACID_DROP2_8197F 0x1458
+#define REG_MACID_DROP3_8197F 0x145C
+#define REG_R_MACID_RELEASE_SUCCESS_0_8197F 0x1460
+#define REG_R_MACID_RELEASE_SUCCESS_1_8197F 0x1464
+#define REG_R_MACID_RELEASE_SUCCESS_2_8197F 0x1468
+#define REG_R_MACID_RELEASE_SUCCESS_3_8197F 0x146C
+#define REG_MGG_FIFO_CRTL_8197F 0x1470
+#define REG_MGG_FIFO_INT_8197F 0x1474
+#define REG_MGG_FIFO_LIFETIME_8197F 0x1478
+#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0x147C
+#define REG_SHCUT_SETTING_8197F 0x1480
+#define REG_SHCUT_LLC_ETH_TYPE0_8197F 0x1484
+#define REG_SHCUT_LLC_ETH_TYPE1_8197F 0x1488
+#define REG_SHCUT_LLC_OUI0_8197F 0x148C
+#define REG_SHCUT_LLC_OUI1_8197F 0x1490
+#define REG_SHCUT_LLC_OUI2_8197F 0x1494
+#define REG_SHCUT_LLC_OUI3_8197F 0x1498
+#define REG_CHNL_INFO_CTRL_8197F 0x14D0
+#define REG_CHNL_IDLE_TIME_8197F 0x14D4
+#define REG_CHNL_BUSY_TIME_8197F 0x14D8
+#define REG_EDCA_VO_PARAM_8197F 0x0500
+#define REG_EDCA_VI_PARAM_8197F 0x0504
+#define REG_EDCA_BE_PARAM_8197F 0x0508
+#define REG_EDCA_BK_PARAM_8197F 0x050C
+#define REG_BCNTCFG_8197F 0x0510
+#define REG_PIFS_8197F 0x0512
+#define REG_RDG_PIFS_8197F 0x0513
+#define REG_SIFS_8197F 0x0514
+#define REG_TSFTR_SYN_OFFSET_8197F 0x0518
+#define REG_AGGR_BREAK_TIME_8197F 0x051A
+#define REG_SLOT_8197F 0x051B
+#define REG_TX_PTCL_CTRL_8197F 0x0520
+#define REG_TXPAUSE_8197F 0x0522
+#define REG_DIS_TXREQ_CLR_8197F 0x0523
+#define REG_RD_CTRL_8197F 0x0524
+#define REG_MBSSID_CTRL_8197F 0x0526
+#define REG_P2PPS_CTRL_8197F 0x0527
+#define REG_PKT_LIFETIME_CTRL_8197F 0x0528
+#define REG_P2PPS_SPEC_STATE_8197F 0x052B
+#define REG_QUEUE_INCOL_THR_8197F 0x0538
+#define REG_QUEUE_INCOL_EN_8197F 0x053C
+#define REG_TBTT_PROHIBIT_8197F 0x0540
+#define REG_P2PPS_STATE_8197F 0x0543
+#define REG_RD_NAV_NXT_8197F 0x0544
+#define REG_NAV_PROT_LEN_8197F 0x0546
+#define REG_FTM_CTRL_8197F 0x0548
+#define REG_FTM_TSF_CNT_8197F 0x054C
+#define REG_BCN_CTRL_8197F 0x0550
+#define REG_BCN_CTRL_CLINT0_8197F 0x0551
+#define REG_MBID_NUM_8197F 0x0552
+#define REG_DUAL_TSF_RST_8197F 0x0553
+#define REG_MBSSID_BCN_SPACE_8197F 0x0554
+#define REG_DRVERLYINT_8197F 0x0558
+#define REG_BCNDMATIM_8197F 0x0559
+#define REG_ATIMWND_8197F 0x055A
+#define REG_USTIME_TSF_8197F 0x055C
+#define REG_BCN_MAX_ERR_8197F 0x055D
+#define REG_RXTSF_OFFSET_CCK_8197F 0x055E
+#define REG_RXTSF_OFFSET_OFDM_8197F 0x055F
+#define REG_TSFTR_8197F 0x0560
+#define REG_FREERUN_CNT_8197F 0x0568
+#define REG_ATIMWND1_8197F 0x0570
+#define REG_TBTT_PROHIBIT_INFRA_8197F 0x0571
+#define REG_CTWND_8197F 0x0572
+#define REG_BCNIVLCUNT_8197F 0x0573
+#define REG_BCNDROPCTRL_8197F 0x0574
+#define REG_HGQ_TIMEOUT_PERIOD_8197F 0x0575
+#define REG_TXCMD_TIMEOUT_PERIOD_8197F 0x0576
+#define REG_MISC_CTRL_8197F 0x0577
+#define REG_BCN_CTRL_CLINT1_8197F 0x0578
+#define REG_BCN_CTRL_CLINT2_8197F 0x0579
+#define REG_BCN_CTRL_CLINT3_8197F 0x057A
+#define REG_EXTEND_CTRL_8197F 0x057B
+#define REG_P2PPS1_SPEC_STATE_8197F 0x057C
+#define REG_P2PPS1_STATE_8197F 0x057D
+#define REG_P2PPS2_SPEC_STATE_8197F 0x057E
+#define REG_P2PPS2_STATE_8197F 0x057F
+#define REG_PS_TIMER0_8197F 0x0580
+#define REG_PS_TIMER1_8197F 0x0584
+#define REG_PS_TIMER2_8197F 0x0588
+#define REG_TBTT_CTN_AREA_8197F 0x058C
+#define REG_FORCE_BCN_IFS_8197F 0x058E
+#define REG_TXOP_MIN_8197F 0x0590
+#define REG_PRE_BKF_TIME_8197F 0x0592
+#define REG_CROSS_TXOP_CTRL_8197F 0x0593
+#define REG_TBTT_INT_SHIFT_CLI0_8197F 0x0594
+#define REG_TBTT_INT_SHIFT_CLI1_8197F 0x0595
+#define REG_TBTT_INT_SHIFT_CLI2_8197F 0x0596
+#define REG_TBTT_INT_SHIFT_CLI3_8197F 0x0597
+#define REG_TBTT_INT_SHIFT_ENABLE_8197F 0x0598
+#define REG_ATIMWND2_8197F 0x05A0
+#define REG_ATIMWND3_8197F 0x05A1
+#define REG_ATIMWND4_8197F 0x05A2
+#define REG_ATIMWND5_8197F 0x05A3
+#define REG_ATIMWND6_8197F 0x05A4
+#define REG_ATIMWND7_8197F 0x05A5
+#define REG_ATIMUGT_8197F 0x05A6
+#define REG_HIQ_NO_LMT_EN_8197F 0x05A7
+#define REG_DTIM_COUNTER_ROOT_8197F 0x05A8
+#define REG_DTIM_COUNTER_VAP1_8197F 0x05A9
+#define REG_DTIM_COUNTER_VAP2_8197F 0x05AA
+#define REG_DTIM_COUNTER_VAP3_8197F 0x05AB
+#define REG_DTIM_COUNTER_VAP4_8197F 0x05AC
+#define REG_DTIM_COUNTER_VAP5_8197F 0x05AD
+#define REG_DTIM_COUNTER_VAP6_8197F 0x05AE
+#define REG_DTIM_COUNTER_VAP7_8197F 0x05AF
+#define REG_DIS_ATIM_8197F 0x05B0
+#define REG_EARLY_128US_8197F 0x05B1
+#define REG_P2PPS1_CTRL_8197F 0x05B2
+#define REG_P2PPS2_CTRL_8197F 0x05B3
+#define REG_TIMER0_SRC_SEL_8197F 0x05B4
+#define REG_NOA_UNIT_SEL_8197F 0x05B5
+#define REG_P2POFF_DIS_TXTIME_8197F 0x05B7
+#define REG_MBSSID_BCN_SPACE2_8197F 0x05B8
+#define REG_MBSSID_BCN_SPACE3_8197F 0x05BC
+#define REG_ACMHWCTRL_8197F 0x05C0
+#define REG_ACMRSTCTRL_8197F 0x05C1
+#define REG_ACMAVG_8197F 0x05C2
+#define REG_VO_ADMTIME_8197F 0x05C4
+#define REG_VI_ADMTIME_8197F 0x05C6
+#define REG_BE_ADMTIME_8197F 0x05C8
+#define REG_EDCA_RANDOM_GEN_8197F 0x05CC
+#define REG_TXCMD_NOA_SEL_8197F 0x05CF
+#define REG_NOA_PARAM_8197F 0x05E0
+#define REG_P2P_RST_8197F 0x05F0
+#define REG_SCHEDULER_RST_8197F 0x05F1
+#define REG_SCH_TXCMD_8197F 0x05F8
+#define REG_PAGE5_DUMMY_8197F 0x05FC
+#define REG_CPUMGQ_TX_TIMER_8197F 0x1500
+#define REG_PS_TIMER_A_8197F 0x1504
+#define REG_PS_TIMER_B_8197F 0x1508
+#define REG_PS_TIMER_C_8197F 0x150C
+#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8197F 0x1510
+#define REG_CPUMGQ_TX_TIMER_EARLY_8197F 0x1514
+#define REG_PS_TIMER_A_EARLY_8197F 0x1515
+#define REG_PS_TIMER_B_EARLY_8197F 0x1516
+#define REG_PS_TIMER_C_EARLY_8197F 0x1517
+#define REG_WMAC_CR_8197F 0x0600
+#define REG_WMAC_FWPKT_CR_8197F 0x0601
+#define REG_BWOPMODE_8197F 0x0603
+#define REG_TCR_8197F 0x0604
+#define REG_RCR_8197F 0x0608
+#define REG_RX_PKT_LIMIT_8197F 0x060C
+#define REG_RX_DLK_TIME_8197F 0x060D
+#define REG_RX_DRVINFO_SZ_8197F 0x060F
+#define REG_MACID_8197F 0x0610
+#define REG_BSSID_8197F 0x0618
+#define REG_MAR_8197F 0x0620
+#define REG_MBIDCAMCFG_1_8197F 0x0628
+#define REG_MBIDCAMCFG_2_8197F 0x062C
+#define REG_WMAC_TCR_TSFT_OFS_8197F 0x0630
+#define REG_UDF_THSD_8197F 0x0632
+#define REG_ZLD_NUM_8197F 0x0633
+#define REG_STMP_THSD_8197F 0x0634
+#define REG_WMAC_TXTIMEOUT_8197F 0x0635
+#define REG_MCU_TEST_2_V1_8197F 0x0636
+#define REG_USTIME_EDCA_8197F 0x0638
+#define REG_MAC_SPEC_SIFS_8197F 0x063A
+#define REG_RESP_SIFS_CCK_8197F 0x063C
+#define REG_RESP_SIFS_OFDM_8197F 0x063E
+#define REG_ACKTO_8197F 0x0640
+#define REG_CTS2TO_8197F 0x0641
+#define REG_EIFS_8197F 0x0642
+#define REG_NAV_CTRL_8197F 0x0650
+#define REG_BACAMCMD_8197F 0x0654
+#define REG_BACAMCONTENT_8197F 0x0658
+#define REG_LBDLY_8197F 0x0660
+#define REG_WMAC_BACAM_RPMEN_8197F 0x0661
+#define REG_WMAC_BITMAP_CTL_8197F 0x0663
+#define REG_RXERR_RPT_8197F 0x0664
+#define REG_WMAC_TRXPTCL_CTL_8197F 0x0668
+#define REG_CAMCMD_8197F 0x0670
+#define REG_CAMWRITE_8197F 0x0674
+#define REG_CAMREAD_8197F 0x0678
+#define REG_CAMDBG_8197F 0x067C
+#define REG_SECCFG_8197F 0x0680
+#define REG_RXFILTER_CATEGORY_1_8197F 0x0682
+#define REG_RXFILTER_ACTION_1_8197F 0x0683
+#define REG_RXFILTER_CATEGORY_2_8197F 0x0684
+#define REG_RXFILTER_ACTION_2_8197F 0x0685
+#define REG_RXFILTER_CATEGORY_3_8197F 0x0686
+#define REG_RXFILTER_ACTION_3_8197F 0x0687
+#define REG_RXFLTMAP3_8197F 0x0688
+#define REG_RXFLTMAP4_8197F 0x068A
+#define REG_RXFLTMAP5_8197F 0x068C
+#define REG_RXFLTMAP6_8197F 0x068E
+#define REG_WOW_CTRL_8197F 0x0690
+#define REG_PS_RX_INFO_8197F 0x0692
+#define REG_WMMPS_UAPSD_TID_8197F 0x0693
+#define REG_LPNAV_CTRL_8197F 0x0694
+#define REG_WKFMCAM_CMD_8197F 0x0698
+#define REG_WKFMCAM_RWD_8197F 0x069C
+#define REG_RXFLTMAP0_8197F 0x06A0
+#define REG_RXFLTMAP1_8197F 0x06A2
+#define REG_RXFLTMAP_8197F 0x06A4
+#define REG_BCN_PSR_RPT_8197F 0x06A8
+#define REG_RXPKTMON_CTRL_8197F 0x06B0
+#define REG_STATE_MON_8197F 0x06B4
+#define REG_ERROR_MON_8197F 0x06B8
+#define REG_SEARCH_MACID_8197F 0x06BC
+#define REG_BT_COEX_TABLE_8197F 0x06C0
+#define REG_RXCMD_0_8197F 0x06D0
+#define REG_RXCMD_1_8197F 0x06D4
+#define REG_WMAC_RESP_TXINFO_8197F 0x06D8
+#define REG_BBPSF_CTRL_8197F 0x06DC
+#define REG_P2P_RX_BCN_NOA_8197F 0x06E0
+#define REG_ASSOCIATED_BFMER0_INFO_8197F 0x06E4
+#define REG_ASSOCIATED_BFMER1_INFO_8197F 0x06EC
+#define REG_TX_CSI_RPT_PARAM_BW20_8197F 0x06F4
+#define REG_TX_CSI_RPT_PARAM_BW40_8197F 0x06F8
+#define REG_TX_CSI_RPT_PARAM_BW80_8197F 0x06FC
+#define REG_BCN_PSR_RPT2_8197F 0x1600
+#define REG_BCN_PSR_RPT3_8197F 0x1604
+#define REG_BCN_PSR_RPT4_8197F 0x1608
+#define REG_A1_ADDR_MASK_8197F 0x160C
+#define REG_MACID2_8197F 0x1620
+#define REG_BSSID2_8197F 0x1628
+#define REG_MACID3_8197F 0x1630
+#define REG_BSSID3_8197F 0x1638
+#define REG_MACID4_8197F 0x1640
+#define REG_BSSID4_8197F 0x1648
+#define REG_NOA_REPORT_8197F 0x1650
+#define REG_PWRBIT_SETTING_8197F 0x1660
+#define REG_WMAC_MU_BF_OPTION_8197F 0x167C
+#define REG_WMAC_PAUSE_BB_CLR_TH_8197F 0x167D
+#define REG_WMAC_MU_ARB_8197F 0x167E
+#define REG_WMAC_MU_OPTION_8197F 0x167F
+#define REG_WMAC_MU_BF_CTL_8197F 0x1680
+#define REG_WMAC_MU_BFRPT_PARA_8197F 0x1682
+#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8197F 0x1684
+#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8197F 0x1686
+#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8197F 0x1688
+#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8197F 0x168A
+#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8197F 0x168C
+#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8197F 0x168E
+#define REG_TRANSMIT_ADDRSS_0_8197F 0x16A0
+#define REG_TRANSMIT_ADDRSS_1_8197F 0x16A8
+#define REG_TRANSMIT_ADDRSS_2_8197F 0x16B0
+#define REG_TRANSMIT_ADDRSS_3_8197F 0x16B8
+#define REG_TRANSMIT_ADDRSS_4_8197F 0x16C0
+#define REG_MACID1_8197F 0x0700
+#define REG_BSSID1_8197F 0x0708
+#define REG_BCN_PSR_RPT1_8197F 0x0710
+#define REG_ASSOCIATED_BFMEE_SEL_8197F 0x0714
+#define REG_SND_PTCL_CTRL_8197F 0x0718
+#define REG_RX_CSI_RPT_INFO_8197F 0x071C
+#define REG_NS_ARP_CTRL_8197F 0x0720
+#define REG_NS_ARP_INFO_8197F 0x0724
+#define REG_BEAMFORMING_INFO_NSARP_V1_8197F 0x0728
+#define REG_BEAMFORMING_INFO_NSARP_8197F 0x072C
+#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8197F 0x0750
+#define REG_WMAC_SWAES_CFG_8197F 0x0760
+#define REG_BT_COEX_V2_8197F 0x0762
+#define REG_BT_COEX_8197F 0x0764
+#define REG_WLAN_ACT_MASK_CTRL_8197F 0x0768
+#define REG_BT_COEX_ENHANCED_INTR_CTRL_8197F 0x076E
+#define REG_BT_ACT_STATISTICS_8197F 0x0770
+#define REG_BT_STATISTICS_CONTROL_REGISTER_8197F 0x0778
+#define REG_BT_STATUS_REPORT_REGISTER_8197F 0x077C
+#define REG_BT_INTERRUPT_CONTROL_REGISTER_8197F 0x0780
+#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8197F 0x0784
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8197F 0x0785
+#define REG_BT_INTERRUPT_STATUS_REGISTER_8197F 0x078F
+#define REG_BT_TDMA_TIME_REGISTER_8197F 0x0790
+#define REG_BT_ACT_REGISTER_8197F 0x0794
+#define REG_OBFF_CTRL_BASIC_8197F 0x0798
+#define REG_OBFF_CTRL2_TIMER_8197F 0x079C
+#define REG_LTR_CTRL_BASIC_8197F 0x07A0
+#define REG_LTR_CTRL2_TIMER_THRESHOLD_8197F 0x07A4
+#define REG_LTR_IDLE_LATENCY_V1_8197F 0x07A8
+#define REG_LTR_ACTIVE_LATENCY_V1_8197F 0x07AC
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8197F 0x07B0
+#define REG_WMAC_PKTCNT_RWD_8197F 0x07B8
+#define REG_WMAC_PKTCNT_CTRL_8197F 0x07BC
+#define REG_IQ_DUMP_8197F 0x07C0
+#define REG_WMAC_FTM_CTL_8197F 0x07CC
+#define REG_IQ_DUMP_EXT_8197F 0x07CF
+#define REG_OFDM_CCK_LEN_MASK_8197F 0x07D0
+#define REG_RX_FILTER_FUNCTION_8197F 0x07DA
+#define REG_NDP_SIG_8197F 0x07E0
+#define REG_TXCMD_INFO_FOR_RSP_PKT_8197F 0x07E4
+#define REG_SEC_OPT_V2_8197F 0x07EC
+#define REG_RTS_ADDRESS_0_8197F 0x07F0
+#define REG_RTS_ADDRESS_1_8197F 0x07F8
+
+#endif

hal/halmac/halmac_reg_8821c.h

@@ -0,0 +1,803 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_REG_8821C_H
+#define __INC_HALMAC_REG_8821C_H
+
+#define REG_SYS_ISO_CTRL_8821C 0x0000
+#define REG_SYS_FUNC_EN_8821C 0x0002
+#define REG_SYS_PW_CTRL_8821C 0x0004
+#define REG_SYS_CLK_CTRL_8821C 0x0008
+#define REG_SYS_EEPROM_CTRL_8821C 0x000A
+#define REG_EE_VPD_8821C 0x000C
+#define REG_SYS_SWR_CTRL1_8821C 0x0010
+#define REG_SYS_SWR_CTRL2_8821C 0x0014
+#define REG_SYS_SWR_CTRL3_8821C 0x0018
+#define REG_RSV_CTRL_8821C 0x001C
+#define REG_RF_CTRL_8821C 0x001F
+#define REG_AFE_LDO_CTRL_8821C 0x0020
+#define REG_AFE_CTRL1_8821C 0x0024
+#define REG_AFE_CTRL2_8821C 0x0028
+#define REG_AFE_CTRL3_8821C 0x002C
+#define REG_EFUSE_CTRL_8821C 0x0030
+#define REG_LDO_EFUSE_CTRL_8821C 0x0034
+#define REG_PWR_OPTION_CTRL_8821C 0x0038
+#define REG_CAL_TIMER_8821C 0x003C
+#define REG_ACLK_MON_8821C 0x003E
+#define REG_GPIO_MUXCFG_8821C 0x0040
+#define REG_GPIO_PIN_CTRL_8821C 0x0044
+#define REG_GPIO_INTM_8821C 0x0048
+#define REG_LED_CFG_8821C 0x004C
+#define REG_FSIMR_8821C 0x0050
+#define REG_FSISR_8821C 0x0054
+#define REG_HSIMR_8821C 0x0058
+#define REG_HSISR_8821C 0x005C
+#define REG_GPIO_EXT_CTRL_8821C 0x0060
+#define REG_PAD_CTRL1_8821C 0x0064
+#define REG_WL_BT_PWR_CTRL_8821C 0x0068
+#define REG_SDM_DEBUG_8821C 0x006C
+#define REG_SYS_SDIO_CTRL_8821C 0x0070
+#define REG_HCI_OPT_CTRL_8821C 0x0074
+#define REG_AFE_CTRL4_8821C 0x0078
+#define REG_LDO_SWR_CTRL_8821C 0x007C
+#define REG_MCUFW_CTRL_8821C 0x0080
+#define REG_MCU_TST_CFG_8821C 0x0084
+#define REG_HMEBOX_E0_E1_8821C 0x0088
+#define REG_HMEBOX_E2_E3_8821C 0x008C
+#define REG_WLLPS_CTRL_8821C 0x0090
+#define REG_AFE_CTRL5_8821C 0x0094
+#define REG_GPIO_DEBOUNCE_CTRL_8821C 0x0098
+#define REG_RPWM2_8821C 0x009C
+#define REG_SYSON_FSM_MON_8821C 0x00A0
+#define REG_AFE_CTRL6_8821C 0x00A4
+#define REG_PMC_DBG_CTRL1_8821C 0x00A8
+#define REG_AFE_CTRL7_8821C 0x00AC
+#define REG_HIMR0_8821C 0x00B0
+#define REG_HISR0_8821C 0x00B4
+#define REG_HIMR1_8821C 0x00B8
+#define REG_HISR1_8821C 0x00BC
+#define REG_DBG_PORT_SEL_8821C 0x00C0
+#define REG_PAD_CTRL2_8821C 0x00C4
+#define REG_PMC_DBG_CTRL2_8821C 0x00CC
+#define REG_BIST_CTRL_8821C 0x00D0
+#define REG_BIST_RPT_8821C 0x00D4
+#define REG_MEM_CTRL_8821C 0x00D8
+#define REG_AFE_CTRL8_8821C 0x00DC
+#define REG_USB_SIE_INTF_8821C 0x00E0
+#define REG_PCIE_MIO_INTF_8821C 0x00E4
+#define REG_PCIE_MIO_INTD_8821C 0x00E8
+#define REG_WLRF1_8821C 0x00EC
+#define REG_SYS_CFG1_8821C 0x00F0
+#define REG_SYS_STATUS1_8821C 0x00F4
+#define REG_SYS_STATUS2_8821C 0x00F8
+#define REG_SYS_CFG2_8821C 0x00FC
+#define REG_SYS_CFG3_8821C 0x1000
+#define REG_SYS_CFG5_8821C 0x1070
+#define REG_CPU_DMEM_CON_8821C 0x1080
+#define REG_BOOT_REASON_8821C 0x1088
+#define REG_NFCPAD_CTRL_8821C 0x10A8
+#define REG_HIMR2_8821C 0x10B0
+#define REG_HISR2_8821C 0x10B4
+#define REG_HIMR3_8821C 0x10B8
+#define REG_HISR3_8821C 0x10BC
+#define REG_SW_MDIO_8821C 0x10C0
+#define REG_H2C_PKT_READADDR_8821C 0x10D0
+#define REG_H2C_PKT_WRITEADDR_8821C 0x10D4
+#define REG_MEM_PWR_CRTL_8821C 0x10D8
+#define REG_FW_DBG6_8821C 0x10F8
+#define REG_FW_DBG7_8821C 0x10FC
+#define REG_CR_8821C 0x0100
+#define REG_PG_SIZE_8821C 0x0104
+#define REG_PKT_BUFF_ACCESS_CTRL_8821C 0x0106
+#define REG_TSF_CLK_STATE_8821C 0x0108
+#define REG_TXDMA_PQ_MAP_8821C 0x010C
+#define REG_TRXFF_BNDY_8821C 0x0114
+#define REG_PTA_I2C_MBOX_8821C 0x0118
+#define REG_RXFF_BNDY_8821C 0x011C
+#define REG_FE1IMR_8821C 0x0120
+#define REG_FE1ISR_8821C 0x0124
+#define REG_CPWM_8821C 0x012C
+#define REG_FWIMR_8821C 0x0130
+#define REG_FWISR_8821C 0x0134
+#define REG_FTIMR_8821C 0x0138
+#define REG_FTISR_8821C 0x013C
+#define REG_PKTBUF_DBG_CTRL_8821C 0x0140
+#define REG_PKTBUF_DBG_DATA_L_8821C 0x0144
+#define REG_PKTBUF_DBG_DATA_H_8821C 0x0148
+#define REG_CPWM2_8821C 0x014C
+#define REG_TC0_CTRL_8821C 0x0150
+#define REG_TC1_CTRL_8821C 0x0154
+#define REG_TC2_CTRL_8821C 0x0158
+#define REG_TC3_CTRL_8821C 0x015C
+#define REG_TC4_CTRL_8821C 0x0160
+#define REG_TCUNIT_BASE_8821C 0x0164
+#define REG_TC5_CTRL_8821C 0x0168
+#define REG_TC6_CTRL_8821C 0x016C
+#define REG_MBIST_DRF_FAIL_8821C 0x0170
+#define REG_MBIST_START_PAUSE_8821C 0x0174
+#define REG_MBIST_DONE_8821C 0x0178
+#define REG_MBIST_READ_BIST_RPT_8821C 0x017C
+#define REG_AES_DECRPT_DATA_8821C 0x0180
+#define REG_AES_DECRPT_CFG_8821C 0x0184
+#define REG_TMETER_8821C 0x0190
+#define REG_OSC_32K_CTRL_8821C 0x0194
+#define REG_32K_CAL_REG1_8821C 0x0198
+#define REG_C2HEVT_8821C 0x01A0
+#define REG_C2HEVT_1_8821C 0x01A4
+#define REG_C2HEVT_2_8821C 0x01A8
+#define REG_C2HEVT_3_8821C 0x01AC
+#define REG_SW_DEFINED_PAGE1_8821C 0x01B8
+#define REG_SW_DEFINED_PAGE2_8821C 0x01BC
+#define REG_MCUTST_I_8821C 0x01C0
+#define REG_MCUTST_II_8821C 0x01C4
+#define REG_FMETHR_8821C 0x01C8
+#define REG_HMETFR_8821C 0x01CC
+#define REG_HMEBOX0_8821C 0x01D0
+#define REG_HMEBOX1_8821C 0x01D4
+#define REG_HMEBOX2_8821C 0x01D8
+#define REG_HMEBOX3_8821C 0x01DC
+#define REG_BB_ACCESS_CTRL_8821C 0x01E8
+#define REG_BB_ACCESS_DATA_8821C 0x01EC
+#define REG_HMEBOX_E0_8821C 0x01F0
+#define REG_HMEBOX_E1_8821C 0x01F4
+#define REG_HMEBOX_E2_8821C 0x01F8
+#define REG_HMEBOX_E3_8821C 0x01FC
+#define REG_CR_EXT_8821C 0x1100
+#define REG_FWFF_8821C 0x1114
+#define REG_RXFF_PTR_V1_8821C 0x1118
+#define REG_RXFF_WTR_V1_8821C 0x111C
+#define REG_FE2IMR_8821C 0x1120
+#define REG_FE2ISR_8821C 0x1124
+#define REG_FE3IMR_8821C 0x1128
+#define REG_FE3ISR_8821C 0x112C
+#define REG_FE4IMR_8821C 0x1130
+#define REG_FE4ISR_8821C 0x1134
+#define REG_FT1IMR_8821C 0x1138
+#define REG_FT1ISR_8821C 0x113C
+#define REG_SPWR0_8821C 0x1140
+#define REG_SPWR1_8821C 0x1144
+#define REG_SPWR2_8821C 0x1148
+#define REG_SPWR3_8821C 0x114C
+#define REG_POWSEQ_8821C 0x1150
+#define REG_TC7_CTRL_V1_8821C 0x1158
+#define REG_TC8_CTRL_V1_8821C 0x115C
+#define REG_RX_BCN_TBTT_ITVL0_8821C 0x1160
+#define REG_RX_BCN_TBTT_ITVL1_8821C 0x1164
+#define REG_IO_WRAP_ERR_FLAG_8821C 0x1170
+#define REG_SPEED_SENSOR_8821C 0x1180
+#define REG_SPEED_SENSOR1_8821C 0x1184
+#define REG_SPEED_SENSOR2_8821C 0x1188
+#define REG_SPEED_SENSOR3_8821C 0x118C
+#define REG_SPEED_SENSOR4_8821C 0x1190
+#define REG_SPEED_SENSOR5_8821C 0x1194
+#define REG_COUNTER_CTRL_8821C 0x11C4
+#define REG_COUNTER_THRESHOLD_8821C 0x11C8
+#define REG_COUNTER_SET_8821C 0x11CC
+#define REG_COUNTER_OVERFLOW_8821C 0x11D0
+#define REG_TXDMA_LEN_THRESHOLD_8821C 0x11D4
+#define REG_RXDMA_LEN_THRESHOLD_8821C 0x11D8
+#define REG_PCIE_EXEC_TIME_THRESHOLD_8821C 0x11DC
+#define REG_FT2IMR_8821C 0x11E0
+#define REG_FT2ISR_8821C 0x11E4
+#define REG_MSG2_8821C 0x11F0
+#define REG_MSG3_8821C 0x11F4
+#define REG_MSG4_8821C 0x11F8
+#define REG_MSG5_8821C 0x11FC
+#define REG_FIFOPAGE_CTRL_1_8821C 0x0200
+#define REG_FIFOPAGE_CTRL_2_8821C 0x0204
+#define REG_AUTO_LLT_V1_8821C 0x0208
+#define REG_TXDMA_OFFSET_CHK_8821C 0x020C
+#define REG_TXDMA_STATUS_8821C 0x0210
+#define REG_TX_DMA_DBG_8821C 0x0214
+#define REG_TQPNT1_8821C 0x0218
+#define REG_TQPNT2_8821C 0x021C
+#define REG_TQPNT3_8821C 0x0220
+#define REG_TQPNT4_8821C 0x0224
+#define REG_RQPN_CTRL_1_8821C 0x0228
+#define REG_RQPN_CTRL_2_8821C 0x022C
+#define REG_FIFOPAGE_INFO_1_8821C 0x0230
+#define REG_FIFOPAGE_INFO_2_8821C 0x0234
+#define REG_FIFOPAGE_INFO_3_8821C 0x0238
+#define REG_FIFOPAGE_INFO_4_8821C 0x023C
+#define REG_FIFOPAGE_INFO_5_8821C 0x0240
+#define REG_H2C_HEAD_8821C 0x0244
+#define REG_H2C_TAIL_8821C 0x0248
+#define REG_H2C_READ_ADDR_8821C 0x024C
+#define REG_H2C_WR_ADDR_8821C 0x0250
+#define REG_H2C_INFO_8821C 0x0254
+#define REG_RXDMA_AGG_PG_TH_8821C 0x0280
+#define REG_RXPKT_NUM_8821C 0x0284
+#define REG_RXDMA_STATUS_8821C 0x0288
+#define REG_RXDMA_DPR_8821C 0x028C
+#define REG_RXDMA_MODE_8821C 0x0290
+#define REG_C2H_PKT_8821C 0x0294
+#define REG_FWFF_C2H_8821C 0x0298
+#define REG_FWFF_CTRL_8821C 0x029C
+#define REG_FWFF_PKT_INFO_8821C 0x02A0
+#define REG_DDMA_CH0SA_8821C 0x1200
+#define REG_DDMA_CH0DA_8821C 0x1204
+#define REG_DDMA_CH0CTRL_8821C 0x1208
+#define REG_DDMA_CH1SA_8821C 0x1210
+#define REG_DDMA_CH1DA_8821C 0x1214
+#define REG_DDMA_CH1CTRL_8821C 0x1218
+#define REG_DDMA_CH2SA_8821C 0x1220
+#define REG_DDMA_CH2DA_8821C 0x1224
+#define REG_DDMA_CH2CTRL_8821C 0x1228
+#define REG_DDMA_CH3SA_8821C 0x1230
+#define REG_DDMA_CH3DA_8821C 0x1234
+#define REG_DDMA_CH3CTRL_8821C 0x1238
+#define REG_DDMA_CH4SA_8821C 0x1240
+#define REG_DDMA_CH4DA_8821C 0x1244
+#define REG_DDMA_CH4CTRL_8821C 0x1248
+#define REG_DDMA_CH5SA_8821C 0x1250
+#define REG_DDMA_CH5DA_8821C 0x1254
+#define REG_DDMA_CH5CTRL_8821C 0x1258
+#define REG_DDMA_INT_MSK_8821C 0x12E0
+#define REG_DDMA_CHSTATUS_8821C 0x12E8
+#define REG_DDMA_CHKSUM_8821C 0x12F0
+#define REG_DDMA_MONITOR_8821C 0x12FC
+#define REG_PCIE_CTRL_8821C 0x0300
+#define REG_INT_MIG_8821C 0x0304
+#define REG_BCNQ_TXBD_DESA_8821C 0x0308
+#define REG_MGQ_TXBD_DESA_8821C 0x0310
+#define REG_VOQ_TXBD_DESA_8821C 0x0318
+#define REG_VIQ_TXBD_DESA_8821C 0x0320
+#define REG_BEQ_TXBD_DESA_8821C 0x0328
+#define REG_BKQ_TXBD_DESA_8821C 0x0330
+#define REG_RXQ_RXBD_DESA_8821C 0x0338
+#define REG_HI0Q_TXBD_DESA_8821C 0x0340
+#define REG_HI1Q_TXBD_DESA_8821C 0x0348
+#define REG_HI2Q_TXBD_DESA_8821C 0x0350
+#define REG_HI3Q_TXBD_DESA_8821C 0x0358
+#define REG_HI4Q_TXBD_DESA_8821C 0x0360
+#define REG_HI5Q_TXBD_DESA_8821C 0x0368
+#define REG_HI6Q_TXBD_DESA_8821C 0x0370
+#define REG_HI7Q_TXBD_DESA_8821C 0x0378
+#define REG_MGQ_TXBD_NUM_8821C 0x0380
+#define REG_RX_RXBD_NUM_8821C 0x0382
+#define REG_VOQ_TXBD_NUM_8821C 0x0384
+#define REG_VIQ_TXBD_NUM_8821C 0x0386
+#define REG_BEQ_TXBD_NUM_8821C 0x0388
+#define REG_BKQ_TXBD_NUM_8821C 0x038A
+#define REG_HI0Q_TXBD_NUM_8821C 0x038C
+#define REG_HI1Q_TXBD_NUM_8821C 0x038E
+#define REG_HI2Q_TXBD_NUM_8821C 0x0390
+#define REG_HI3Q_TXBD_NUM_8821C 0x0392
+#define REG_HI4Q_TXBD_NUM_8821C 0x0394
+#define REG_HI5Q_TXBD_NUM_8821C 0x0396
+#define REG_HI6Q_TXBD_NUM_8821C 0x0398
+#define REG_HI7Q_TXBD_NUM_8821C 0x039A
+#define REG_TSFTIMER_HCI_8821C 0x039C
+#define REG_BD_RWPTR_CLR_8821C 0x039C
+#define REG_VOQ_TXBD_IDX_8821C 0x03A0
+#define REG_VIQ_TXBD_IDX_8821C 0x03A4
+#define REG_BEQ_TXBD_IDX_8821C 0x03A8
+#define REG_BKQ_TXBD_IDX_8821C 0x03AC
+#define REG_MGQ_TXBD_IDX_8821C 0x03B0
+#define REG_RXQ_RXBD_IDX_8821C 0x03B4
+#define REG_HI0Q_TXBD_IDX_8821C 0x03B8
+#define REG_HI1Q_TXBD_IDX_8821C 0x03BC
+#define REG_HI2Q_TXBD_IDX_8821C 0x03C0
+#define REG_HI3Q_TXBD_IDX_8821C 0x03C4
+#define REG_HI4Q_TXBD_IDX_8821C 0x03C8
+#define REG_HI5Q_TXBD_IDX_8821C 0x03CC
+#define REG_HI6Q_TXBD_IDX_8821C 0x03D0
+#define REG_HI7Q_TXBD_IDX_8821C 0x03D4
+#define REG_DBG_SEL_V1_8821C 0x03D8
+#define REG_PCIE_HRPWM1_V1_8821C 0x03D9
+#define REG_PCIE_HCPWM1_V1_8821C 0x03DA
+#define REG_PCIE_CTRL2_8821C 0x03DB
+#define REG_PCIE_HRPWM2_V1_8821C 0x03DC
+#define REG_PCIE_HCPWM2_V1_8821C 0x03DE
+#define REG_PCIE_H2C_MSG_V1_8821C 0x03E0
+#define REG_PCIE_C2H_MSG_V1_8821C 0x03E4
+#define REG_DBI_WDATA_V1_8821C 0x03E8
+#define REG_DBI_RDATA_V1_8821C 0x03EC
+#define REG_DBI_FLAG_V1_8821C 0x03F0
+#define REG_MDIO_V1_8821C 0x03F4
+#define REG_PCIE_MIX_CFG_8821C 0x03F8
+#define REG_HCI_MIX_CFG_8821C 0x03FC
+#define REG_STC_INT_CS_8821C 0x1300
+#define REG_ST_INT_CFG_8821C 0x1304
+#define REG_CMU_DLY_CTRL_8821C 0x1310
+#define REG_CMU_DLY_CFG_8821C 0x1314
+#define REG_H2CQ_TXBD_DESA_8821C 0x1320
+#define REG_H2CQ_TXBD_NUM_8821C 0x1328
+#define REG_H2CQ_TXBD_IDX_8821C 0x132C
+#define REG_H2CQ_CSR_8821C 0x1330
+#define REG_Q0_INFO_8821C 0x0400
+#define REG_Q1_INFO_8821C 0x0404
+#define REG_Q2_INFO_8821C 0x0408
+#define REG_Q3_INFO_8821C 0x040C
+#define REG_MGQ_INFO_8821C 0x0410
+#define REG_HIQ_INFO_8821C 0x0414
+#define REG_BCNQ_INFO_8821C 0x0418
+#define REG_TXPKT_EMPTY_8821C 0x041A
+#define REG_CPU_MGQ_INFO_8821C 0x041C
+#define REG_FWHW_TXQ_CTRL_8821C 0x0420
+#define REG_DATAFB_SEL_8821C 0x0423
+#define REG_BCNQ_BDNY_V1_8821C 0x0424
+#define REG_LIFETIME_EN_8821C 0x0426
+#define REG_SPEC_SIFS_8821C 0x0428
+#define REG_RETRY_LIMIT_8821C 0x042A
+#define REG_TXBF_CTRL_8821C 0x042C
+#define REG_DARFRC_8821C 0x0430
+#define REG_DARFRCH_8821C 0x0434
+#define REG_RARFRC_8821C 0x0438
+#define REG_RARFRCH_8821C 0x043C
+#define REG_RRSR_8821C 0x0440
+#define REG_ARFR0_8821C 0x0444
+#define REG_ARFRH0_8821C 0x0448
+#define REG_ARFR1_V1_8821C 0x044C
+#define REG_ARFRH1_V1_8821C 0x0450
+#define REG_CCK_CHECK_8821C 0x0454
+#define REG_AMPDU_MAX_TIME_V1_8821C 0x0455
+#define REG_BCNQ1_BDNY_V1_8821C 0x0456
+#define REG_AMPDU_MAX_LENGTH_8821C 0x0458
+#define REG_ACQ_STOP_8821C 0x045C
+#define REG_NDPA_RATE_8821C 0x045D
+#define REG_TX_HANG_CTRL_8821C 0x045E
+#define REG_NDPA_OPT_CTRL_8821C 0x045F
+#define REG_RD_RESP_PKT_TH_8821C 0x0463
+#define REG_CMDQ_INFO_8821C 0x0464
+#define REG_Q4_INFO_8821C 0x0468
+#define REG_Q5_INFO_8821C 0x046C
+#define REG_Q6_INFO_8821C 0x0470
+#define REG_Q7_INFO_8821C 0x0474
+#define REG_WMAC_LBK_BUF_HD_V1_8821C 0x0478
+#define REG_MGQ_BDNY_V1_8821C 0x047A
+#define REG_TXRPT_CTRL_8821C 0x047C
+#define REG_INIRTS_RATE_SEL_8821C 0x0480
+#define REG_BASIC_CFEND_RATE_8821C 0x0481
+#define REG_STBC_CFEND_RATE_8821C 0x0482
+#define REG_DATA_SC_8821C 0x0483
+#define REG_MACID_SLEEP3_8821C 0x0484
+#define REG_MACID_SLEEP1_8821C 0x0488
+#define REG_ARFR2_V1_8821C 0x048C
+#define REG_ARFRH2_V1_8821C 0x0490
+#define REG_ARFR3_V1_8821C 0x0494
+#define REG_ARFRH3_V1_8821C 0x0498
+#define REG_ARFR4_8821C 0x049C
+#define REG_ARFRH4_8821C 0x04A0
+#define REG_ARFR5_8821C 0x04A4
+#define REG_ARFRH5_8821C 0x04A8
+#define REG_TXRPT_START_OFFSET_8821C 0x04AC
+#define REG_POWER_STAGE1_8821C 0x04B4
+#define REG_POWER_STAGE2_8821C 0x04B8
+#define REG_SW_AMPDU_BURST_MODE_CTRL_8821C 0x04BC
+#define REG_PKT_LIFE_TIME_8821C 0x04C0
+#define REG_STBC_SETTING_8821C 0x04C4
+#define REG_STBC_SETTING2_8821C 0x04C5
+#define REG_QUEUE_CTRL_8821C 0x04C6
+#define REG_SINGLE_AMPDU_CTRL_8821C 0x04C7
+#define REG_PROT_MODE_CTRL_8821C 0x04C8
+#define REG_BAR_MODE_CTRL_8821C 0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT_8821C 0x04CF
+#define REG_MACID_SLEEP2_8821C 0x04D0
+#define REG_MACID_SLEEP_8821C 0x04D4
+#define REG_HW_SEQ0_8821C 0x04D8
+#define REG_HW_SEQ1_8821C 0x04DA
+#define REG_HW_SEQ2_8821C 0x04DC
+#define REG_HW_SEQ3_8821C 0x04DE
+#define REG_NULL_PKT_STATUS_V1_8821C 0x04E0
+#define REG_PTCL_ERR_STATUS_8821C 0x04E2
+#define REG_NULL_PKT_STATUS_EXTEND_8821C 0x04E3
+#define REG_VIDEO_ENHANCEMENT_FUN_8821C 0x04E4
+#define REG_PRECNT_CTRL_8821C 0x04E5
+#define REG_BT_POLLUTE_PKT_CNT_8821C 0x04E8
+#define REG_PTCL_DBG_8821C 0x04EC
+#define REG_CPUMGQ_TIMER_CTRL2_8821C 0x04F4
+#define REG_DUMMY_PAGE4_V1_8821C 0x04FC
+#define REG_MOREDATA_8821C 0x04FE
+#define REG_Q0_Q1_INFO_8821C 0x1400
+#define REG_Q2_Q3_INFO_8821C 0x1404
+#define REG_Q4_Q5_INFO_8821C 0x1408
+#define REG_Q6_Q7_INFO_8821C 0x140C
+#define REG_MGQ_HIQ_INFO_8821C 0x1410
+#define REG_CMDQ_BCNQ_INFO_8821C 0x1414
+#define REG_USEREG_SETTING_8821C 0x1420
+#define REG_AESIV_SETTING_8821C 0x1424
+#define REG_BF0_TIME_SETTING_8821C 0x1428
+#define REG_BF1_TIME_SETTING_8821C 0x142C
+#define REG_BF_TIMEOUT_EN_8821C 0x1430
+#define REG_MACID_RELEASE0_8821C 0x1434
+#define REG_MACID_RELEASE1_8821C 0x1438
+#define REG_MACID_RELEASE2_8821C 0x143C
+#define REG_MACID_RELEASE3_8821C 0x1440
+#define REG_MACID_RELEASE_SETTING_8821C 0x1444
+#define REG_FAST_EDCA_VOVI_SETTING_8821C 0x1448
+#define REG_FAST_EDCA_BEBK_SETTING_8821C 0x144C
+#define REG_MACID_DROP0_8821C 0x1450
+#define REG_MACID_DROP1_8821C 0x1454
+#define REG_MACID_DROP2_8821C 0x1458
+#define REG_MACID_DROP3_8821C 0x145C
+#define REG_R_MACID_RELEASE_SUCCESS_0_8821C 0x1460
+#define REG_R_MACID_RELEASE_SUCCESS_1_8821C 0x1464
+#define REG_R_MACID_RELEASE_SUCCESS_2_8821C 0x1468
+#define REG_R_MACID_RELEASE_SUCCESS_3_8821C 0x146C
+#define REG_MGQ_FIFO_WRITE_POINTER_8821C 0x1470
+#define REG_MGQ_FIFO_READ_POINTER_8821C 0x1472
+#define REG_MGQ_FIFO_ENABLE_8821C 0x1472
+#define REG_MGQ_FIFO_RELEASE_INT_MASK_8821C 0x1474
+#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8821C 0x1476
+#define REG_MGQ_FIFO_VALID_MAP_8821C 0x1478
+#define REG_MGQ_FIFO_LIFETIME_8821C 0x147A
+#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0x147C
+#define REG_SHCUT_SETTING_8821C 0x1480
+#define REG_SHCUT_LLC_ETH_TYPE0_8821C 0x1484
+#define REG_SHCUT_LLC_ETH_TYPE1_8821C 0x1488
+#define REG_SHCUT_LLC_OUI0_8821C 0x148C
+#define REG_SHCUT_LLC_OUI1_8821C 0x1490
+#define REG_SHCUT_LLC_OUI2_8821C 0x1494
+#define REG_MU_TX_CTL_8821C 0x14C0
+#define REG_MU_STA_GID_VLD_8821C 0x14C4
+#define REG_MU_STA_USER_POS_INFO_8821C 0x14C8
+#define REG_MU_STA_USER_POS_INFO_H_8821C 0x14CC
+#define REG_MU_TRX_DBG_CNT_8821C 0x14D0
+#define REG_EDCA_VO_PARAM_8821C 0x0500
+#define REG_EDCA_VI_PARAM_8821C 0x0504
+#define REG_EDCA_BE_PARAM_8821C 0x0508
+#define REG_EDCA_BK_PARAM_8821C 0x050C
+#define REG_BCNTCFG_8821C 0x0510
+#define REG_PIFS_8821C 0x0512
+#define REG_RDG_PIFS_8821C 0x0513
+#define REG_SIFS_8821C 0x0514
+#define REG_TSFTR_SYN_OFFSET_8821C 0x0518
+#define REG_AGGR_BREAK_TIME_8821C 0x051A
+#define REG_SLOT_8821C 0x051B
+#define REG_NOA_ON_ERLY_TIME_8821C 0x051C
+#define REG_NOA_OFF_ERLY_TIME_8821C 0x051D
+#define REG_TX_PTCL_CTRL_8821C 0x0520
+#define REG_TXPAUSE_8821C 0x0522
+#define REG_DIS_TXREQ_CLR_8821C 0x0523
+#define REG_RD_CTRL_8821C 0x0524
+#define REG_MBSSID_CTRL_8821C 0x0526
+#define REG_P2PPS_CTRL_8821C 0x0527
+#define REG_PKT_LIFETIME_CTRL_8821C 0x0528
+#define REG_P2PPS_SPEC_STATE_8821C 0x052B
+#define REG_BAR_TX_CTRL_8821C 0x0530
+#define REG_P2PON_DIS_TXTIME_8821C 0x0531
+#define REG_TBTT_PROHIBIT_8821C 0x0540
+#define REG_P2PPS_STATE_8821C 0x0543
+#define REG_RD_NAV_NXT_8821C 0x0544
+#define REG_NAV_PROT_LEN_8821C 0x0546
+#define REG_BCN_CTRL_8821C 0x0550
+#define REG_BCN_CTRL_CLINT0_8821C 0x0551
+#define REG_MBID_NUM_8821C 0x0552
+#define REG_DUAL_TSF_RST_8821C 0x0553
+#define REG_MBSSID_BCN_SPACE_8821C 0x0554
+#define REG_DRVERLYINT_8821C 0x0558
+#define REG_BCNDMATIM_8821C 0x0559
+#define REG_ATIMWND_8821C 0x055A
+#define REG_USTIME_TSF_8821C 0x055C
+#define REG_BCN_MAX_ERR_8821C 0x055D
+#define REG_RXTSF_OFFSET_CCK_8821C 0x055E
+#define REG_RXTSF_OFFSET_OFDM_8821C 0x055F
+#define REG_TSFTR_8821C 0x0560
+#define REG_TSFTR_1_8821C 0x0564
+#define REG_FREERUN_CNT_8821C 0x0568
+#define REG_FREERUN_CNT_1_8821C 0x056C
+#define REG_ATIMWND1_V1_8821C 0x0570
+#define REG_TBTT_PROHIBIT_INFRA_8821C 0x0571
+#define REG_CTWND_8821C 0x0572
+#define REG_BCNIVLCUNT_8821C 0x0573
+#define REG_BCNDROPCTRL_8821C 0x0574
+#define REG_HGQ_TIMEOUT_PERIOD_8821C 0x0575
+#define REG_TXCMD_TIMEOUT_PERIOD_8821C 0x0576
+#define REG_MISC_CTRL_8821C 0x0577
+#define REG_BCN_CTRL_CLINT1_8821C 0x0578
+#define REG_BCN_CTRL_CLINT2_8821C 0x0579
+#define REG_BCN_CTRL_CLINT3_8821C 0x057A
+#define REG_EXTEND_CTRL_8821C 0x057B
+#define REG_P2PPS1_SPEC_STATE_8821C 0x057C
+#define REG_P2PPS1_STATE_8821C 0x057D
+#define REG_P2PPS2_SPEC_STATE_8821C 0x057E
+#define REG_P2PPS2_STATE_8821C 0x057F
+#define REG_PS_TIMER0_8821C 0x0580
+#define REG_PS_TIMER1_8821C 0x0584
+#define REG_PS_TIMER2_8821C 0x0588
+#define REG_TBTT_CTN_AREA_8821C 0x058C
+#define REG_FORCE_BCN_IFS_8821C 0x058E
+#define REG_TXOP_MIN_8821C 0x0590
+#define REG_PRE_BKF_TIME_8821C 0x0592
+#define REG_CROSS_TXOP_CTRL_8821C 0x0593
+#define REG_ATIMWND2_8821C 0x05A0
+#define REG_ATIMWND3_8821C 0x05A1
+#define REG_ATIMWND4_8821C 0x05A2
+#define REG_ATIMWND5_8821C 0x05A3
+#define REG_ATIMWND6_8821C 0x05A4
+#define REG_ATIMWND7_8821C 0x05A5
+#define REG_ATIMUGT_8821C 0x05A6
+#define REG_HIQ_NO_LMT_EN_8821C 0x05A7
+#define REG_DTIM_COUNTER_ROOT_8821C 0x05A8
+#define REG_DTIM_COUNTER_VAP1_8821C 0x05A9
+#define REG_DTIM_COUNTER_VAP2_8821C 0x05AA
+#define REG_DTIM_COUNTER_VAP3_8821C 0x05AB
+#define REG_DTIM_COUNTER_VAP4_8821C 0x05AC
+#define REG_DTIM_COUNTER_VAP5_8821C 0x05AD
+#define REG_DTIM_COUNTER_VAP6_8821C 0x05AE
+#define REG_DTIM_COUNTER_VAP7_8821C 0x05AF
+#define REG_DIS_ATIM_8821C 0x05B0
+#define REG_EARLY_128US_8821C 0x05B1
+#define REG_P2PPS1_CTRL_8821C 0x05B2
+#define REG_P2PPS2_CTRL_8821C 0x05B3
+#define REG_TIMER0_SRC_SEL_8821C 0x05B4
+#define REG_NOA_UNIT_SEL_8821C 0x05B5
+#define REG_P2POFF_DIS_TXTIME_8821C 0x05B7
+#define REG_MBSSID_BCN_SPACE2_8821C 0x05B8
+#define REG_MBSSID_BCN_SPACE3_8821C 0x05BC
+#define REG_ACMHWCTRL_8821C 0x05C0
+#define REG_ACMRSTCTRL_8821C 0x05C1
+#define REG_ACMAVG_8821C 0x05C2
+#define REG_VO_ADMTIME_8821C 0x05C4
+#define REG_VI_ADMTIME_8821C 0x05C6
+#define REG_BE_ADMTIME_8821C 0x05C8
+#define REG_EDCA_RANDOM_GEN_8821C 0x05CC
+#define REG_TXCMD_NOA_SEL_8821C 0x05CF
+#define REG_NOA_PARAM_8821C 0x05E0
+#define REG_NOA_PARAM_1_8821C 0x05E4
+#define REG_NOA_PARAM_2_8821C 0x05E8
+#define REG_NOA_PARAM_3_8821C 0x05EC
+#define REG_P2P_RST_8821C 0x05F0
+#define REG_SCHEDULER_RST_8821C 0x05F1
+#define REG_SCH_TXCMD_8821C 0x05F8
+#define REG_PAGE5_DUMMY_8821C 0x05FC
+#define REG_CPUMGQ_TX_TIMER_8821C 0x1500
+#define REG_PS_TIMER_A_8821C 0x1504
+#define REG_PS_TIMER_B_8821C 0x1508
+#define REG_PS_TIMER_C_8821C 0x150C
+#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8821C 0x1510
+#define REG_CPUMGQ_TX_TIMER_EARLY_8821C 0x1514
+#define REG_PS_TIMER_A_EARLY_8821C 0x1515
+#define REG_PS_TIMER_B_EARLY_8821C 0x1516
+#define REG_PS_TIMER_C_EARLY_8821C 0x1517
+#define REG_CPUMGQ_PARAMETER_8821C 0x1518
+#define REG_WMAC_CR_8821C 0x0600
+#define REG_WMAC_FWPKT_CR_8821C 0x0601
+#define REG_FW_STS_FILTER_8821C 0x0602
+#define REG_TCR_8821C 0x0604
+#define REG_RCR_8821C 0x0608
+#define REG_RX_PKT_LIMIT_8821C 0x060C
+#define REG_RX_DLK_TIME_8821C 0x060D
+#define REG_RX_DRVINFO_SZ_8821C 0x060F
+#define REG_MACID_8821C 0x0610
+#define REG_MACID_H_8821C 0x0614
+#define REG_BSSID_8821C 0x0618
+#define REG_BSSID_H_8821C 0x061C
+#define REG_MAR_8821C 0x0620
+#define REG_MAR_H_8821C 0x0624
+#define REG_MBIDCAMCFG_1_8821C 0x0628
+#define REG_MBIDCAMCFG_2_8821C 0x062C
+#define REG_WMAC_TCR_TSFT_OFS_8821C 0x0630
+#define REG_UDF_THSD_8821C 0x0632
+#define REG_ZLD_NUM_8821C 0x0633
+#define REG_STMP_THSD_8821C 0x0634
+#define REG_WMAC_TXTIMEOUT_8821C 0x0635
+#define REG_MCU_TEST_2_V1_8821C 0x0636
+#define REG_USTIME_EDCA_8821C 0x0638
+#define REG_ACKTO_CCK_8821C 0x0639
+#define REG_MAC_SPEC_SIFS_8821C 0x063A
+#define REG_RESP_SIFS_CCK_8821C 0x063C
+#define REG_RESP_SIFS_OFDM_8821C 0x063E
+#define REG_ACKTO_8821C 0x0640
+#define REG_CTS2TO_8821C 0x0641
+#define REG_EIFS_8821C 0x0642
+#define REG_RPFM_MAP0_8821C 0x0644
+#define REG_RPFM_MAP1_V1_8821C 0x0646
+#define REG_RPFM_CAM_CMD_8821C 0x0648
+#define REG_RPFM_CAM_RWD_8821C 0x064C
+#define REG_NAV_CTRL_8821C 0x0650
+#define REG_BACAMCMD_8821C 0x0654
+#define REG_BACAMCONTENT_8821C 0x0658
+#define REG_BACAMCONTENT_H_8821C 0x065C
+#define REG_LBDLY_8821C 0x0660
+#define REG_WMAC_BACAM_RPMEN_8821C 0x0661
+#define REG_TX_RX_8821C 0x0662
+#define REG_WMAC_BITMAP_CTL_8821C 0x0663
+#define REG_RXERR_RPT_8821C 0x0664
+#define REG_WMAC_TRXPTCL_CTL_8821C 0x0668
+#define REG_WMAC_TRXPTCL_CTL_H_8821C 0x066C
+#define REG_CAMCMD_8821C 0x0670
+#define REG_CAMWRITE_8821C 0x0674
+#define REG_CAMREAD_8821C 0x0678
+#define REG_CAMDBG_8821C 0x067C
+#define REG_SECCFG_8821C 0x0680
+#define REG_RXFILTER_CATEGORY_1_8821C 0x0682
+#define REG_RXFILTER_ACTION_1_8821C 0x0683
+#define REG_RXFILTER_CATEGORY_2_8821C 0x0684
+#define REG_RXFILTER_ACTION_2_8821C 0x0685
+#define REG_RXFILTER_CATEGORY_3_8821C 0x0686
+#define REG_RXFILTER_ACTION_3_8821C 0x0687
+#define REG_RXFLTMAP3_8821C 0x0688
+#define REG_RXFLTMAP4_8821C 0x068A
+#define REG_RXFLTMAP5_8821C 0x068C
+#define REG_RXFLTMAP6_8821C 0x068E
+#define REG_WOW_CTRL_8821C 0x0690
+#define REG_NAN_RX_TSF_FILTER_8821C 0x0691
+#define REG_PS_RX_INFO_8821C 0x0692
+#define REG_WMMPS_UAPSD_TID_8821C 0x0693
+#define REG_LPNAV_CTRL_8821C 0x0694
+#define REG_WKFMCAM_CMD_8821C 0x0698
+#define REG_WKFMCAM_RWD_8821C 0x069C
+#define REG_RXFLTMAP0_8821C 0x06A0
+#define REG_RXFLTMAP1_8821C 0x06A2
+#define REG_RXFLTMAP2_8821C 0x06A4
+#define REG_BCN_PSR_RPT_8821C 0x06A8
+#define REG_FLC_RPC_8821C 0x06AC
+#define REG_FLC_RPCT_8821C 0x06AD
+#define REG_FLC_PTS_8821C 0x06AE
+#define REG_FLC_TRPC_8821C 0x06AF
+#define REG_RXPKTMON_CTRL_8821C 0x06B0
+#define REG_STATE_MON_8821C 0x06B4
+#define REG_ERROR_MON_8821C 0x06B8
+#define REG_SEARCH_MACID_8821C 0x06BC
+#define REG_BT_COEX_TABLE_8821C 0x06C0
+#define REG_BT_COEX_TABLE2_8821C 0x06C4
+#define REG_BT_COEX_BREAK_TABLE_8821C 0x06C8
+#define REG_BT_COEX_TABLE_H_8821C 0x06CC
+#define REG_RXCMD_0_8821C 0x06D0
+#define REG_RXCMD_1_8821C 0x06D4
+#define REG_WMAC_RESP_TXINFO_8821C 0x06D8
+#define REG_BBPSF_CTRL_8821C 0x06DC
+#define REG_P2P_RX_BCN_NOA_8821C 0x06E0
+#define REG_ASSOCIATED_BFMER0_INFO_8821C 0x06E4
+#define REG_ASSOCIATED_BFMER0_INFO_H_8821C 0x06E8
+#define REG_ASSOCIATED_BFMER1_INFO_8821C 0x06EC
+#define REG_ASSOCIATED_BFMER1_INFO_H_8821C 0x06F0
+#define REG_TX_CSI_RPT_PARAM_BW20_8821C 0x06F4
+#define REG_TX_CSI_RPT_PARAM_BW40_8821C 0x06F8
+#define REG_BCN_PSR_RPT2_8821C 0x1600
+#define REG_BCN_PSR_RPT3_8821C 0x1604
+#define REG_BCN_PSR_RPT4_8821C 0x1608
+#define REG_A1_ADDR_MASK_8821C 0x160C
+#define REG_MACID2_8821C 0x1620
+#define REG_MACID2_H_8821C 0x1624
+#define REG_BSSID2_8821C 0x1628
+#define REG_BSSID2_H_8821C 0x162C
+#define REG_MACID3_8821C 0x1630
+#define REG_MACID3_H_8821C 0x1634
+#define REG_BSSID3_8821C 0x1638
+#define REG_BSSID3_H_8821C 0x163C
+#define REG_MACID4_8821C 0x1640
+#define REG_MACID4_H_8821C 0x1644
+#define REG_BSSID4_8821C 0x1648
+#define REG_BSSID4_H_8821C 0x164C
+#define REG_NOA_REPORT_8821C 0x1650
+#define REG_NOA_REPORT_1_8821C 0x1654
+#define REG_NOA_REPORT_2_8821C 0x1658
+#define REG_NOA_REPORT_3_8821C 0x165C
+#define REG_PWRBIT_SETTING_8821C 0x1660
+#define REG_MU_BF_OPTION_8821C 0x167C
+#define REG_WMAC_PAUSE_BB_CLR_TH_8821C 0x167D
+#define REG_WMAC_MU_ARB_8821C 0x167E
+#define REG_WMAC_MU_OPTION_8821C 0x167F
+#define REG_WMAC_MU_BF_CTL_8821C 0x1680
+#define REG_WMAC_MU_BFRPT_PARA_8821C 0x1682
+#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8821C 0x1684
+#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8821C 0x1686
+#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8821C 0x1688
+#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8821C 0x168A
+#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8821C 0x168C
+#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8821C 0x168E
+#define REG_WMAC_BB_STOP_RX_COUNTER_8821C 0x1690
+#define REG_WMAC_PLCP_MONITOR_8821C 0x1694
+#define REG_WMAC_PLCP_MONITOR_MUTX_8821C 0x1698
+#define REG_TRANSMIT_ADDRSS_0_8821C 0x16A0
+#define REG_TRANSMIT_ADDRSS_0_H_8821C 0x16A4
+#define REG_TRANSMIT_ADDRSS_1_8821C 0x16A8
+#define REG_TRANSMIT_ADDRSS_1_H_8821C 0x16AC
+#define REG_TRANSMIT_ADDRSS_2_8821C 0x16B0
+#define REG_TRANSMIT_ADDRSS_2_H_8821C 0x16B4
+#define REG_TRANSMIT_ADDRSS_3_8821C 0x16B8
+#define REG_TRANSMIT_ADDRSS_3_H_8821C 0x16BC
+#define REG_TRANSMIT_ADDRSS_4_8821C 0x16C0
+#define REG_TRANSMIT_ADDRSS_4_H_8821C 0x16C4
+#define REG_MACID1_8821C 0x0700
+#define REG_MACID1_1_8821C 0x0704
+#define REG_BSSID1_8821C 0x0708
+#define REG_BSSID1_1_8821C 0x070C
+#define REG_BCN_PSR_RPT1_8821C 0x0710
+#define REG_ASSOCIATED_BFMEE_SEL_8821C 0x0714
+#define REG_SND_PTCL_CTRL_8821C 0x0718
+#define REG_RX_CSI_RPT_INFO_8821C 0x071C
+#define REG_NS_ARP_CTRL_8821C 0x0720
+#define REG_NS_ARP_INFO_8821C 0x0724
+#define REG_BEAMFORMING_INFO_NSARP_V1_8821C 0x0728
+#define REG_BEAMFORMING_INFO_NSARP_8821C 0x072C
+#define REG_IPV6_8821C 0x0730
+#define REG_IPV6_1_8821C 0x0734
+#define REG_IPV6_2_8821C 0x0738
+#define REG_IPV6_3_8821C 0x073C
+#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8821C 0x0750
+#define REG_WMAC_SWAES_CFG_8821C 0x0760
+#define REG_BT_COEX_V2_8821C 0x0762
+#define REG_BT_COEX_8821C 0x0764
+#define REG_WLAN_ACT_MASK_CTRL_8821C 0x0768
+#define REG_WLAN_ACT_MASK_CTRL_1_8821C 0x076C
+#define REG_BT_COEX_ENHANCED_INTR_CTRL_8821C 0x076E
+#define REG_BT_ACT_STATISTICS_8821C 0x0770
+#define REG_BT_ACT_STATISTICS_1_8821C 0x0774
+#define REG_BT_STATISTICS_CONTROL_REGISTER_8821C 0x0778
+#define REG_BT_STATUS_REPORT_REGISTER_8821C 0x077C
+#define REG_BT_INTERRUPT_CONTROL_REGISTER_8821C 0x0780
+#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8821C 0x0784
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8821C 0x0785
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8821C 0x0788
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8821C 0x078C
+#define REG_BT_INTERRUPT_STATUS_REGISTER_8821C 0x078F
+#define REG_BT_TDMA_TIME_REGISTER_8821C 0x0790
+#define REG_BT_ACT_REGISTER_8821C 0x0794
+#define REG_OBFF_CTRL_BASIC_8821C 0x0798
+#define REG_OBFF_CTRL2_TIMER_8821C 0x079C
+#define REG_LTR_CTRL_BASIC_8821C 0x07A0
+#define REG_LTR_CTRL2_TIMER_THRESHOLD_8821C 0x07A4
+#define REG_LTR_IDLE_LATENCY_V1_8821C 0x07A8
+#define REG_LTR_ACTIVE_LATENCY_V1_8821C 0x07AC
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8821C 0x07B0
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8821C 0x07B4
+#define REG_WMAC_PKTCNT_RWD_8821C 0x07B8
+#define REG_WMAC_PKTCNT_CTRL_8821C 0x07BC
+#define REG_IQ_DUMP_8821C 0x07C0
+#define REG_IQ_DUMP_1_8821C 0x07C4
+#define REG_IQ_DUMP_2_8821C 0x07C8
+#define REG_WMAC_FTM_CTL_8821C 0x07CC
+#define REG_WMAC_IQ_MDPK_FUNC_8821C 0x07CE
+#define REG_WMAC_OPTION_FUNCTION_8821C 0x07D0
+#define REG_WMAC_OPTION_FUNCTION_1_8821C 0x07D4
+#define REG_WMAC_OPTION_FUNCTION_2_8821C 0x07D8
+#define REG_RX_FILTER_FUNCTION_8821C 0x07DA
+#define REG_NDP_SIG_8821C 0x07E0
+#define REG_TXCMD_INFO_FOR_RSP_PKT_8821C 0x07E4
+#define REG_TXCMD_INFO_FOR_RSP_PKT_1_8821C 0x07E8
+#define REG_WSEC_OPTION_8821C 0x07EC
+#define REG_RTS_ADDRESS_0_8821C 0x07F0
+#define REG_RTS_ADDRESS_0_1_8821C 0x07F4
+#define REG_RTS_ADDRESS_1_8821C 0x07F8
+#define REG_RTS_ADDRESS_1_1_8821C 0x07FC
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8821C 0x1700
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8821C 0x1704
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8821C 0x1708
+#define REG_SDIO_TX_CTRL_8821C 0x10250000
+#define REG_SDIO_HIMR_8821C 0x10250014
+#define REG_SDIO_HISR_8821C 0x10250018
+#define REG_SDIO_RX_REQ_LEN_8821C 0x1025001C
+#define REG_SDIO_FREE_TXPG_SEQ_V1_8821C 0x1025001F
+#define REG_SDIO_FREE_TXPG_8821C 0x10250020
+#define REG_SDIO_FREE_TXPG2_8821C 0x10250024
+#define REG_SDIO_OQT_FREE_TXPG_V1_8821C 0x10250028
+#define REG_SDIO_HTSFR_INFO_8821C 0x10250030
+#define REG_SDIO_HCPWM1_V2_8821C 0x10250038
+#define REG_SDIO_HCPWM2_V2_8821C 0x1025003A
+#define REG_SDIO_INDIRECT_REG_CFG_8821C 0x10250040
+#define REG_SDIO_INDIRECT_REG_DATA_8821C 0x10250044
+#define REG_SDIO_H2C_8821C 0x10250060
+#define REG_SDIO_C2H_8821C 0x10250064
+#define REG_SDIO_HRPWM1_8821C 0x10250080
+#define REG_SDIO_HRPWM2_8821C 0x10250082
+#define REG_SDIO_HPS_CLKR_8821C 0x10250084
+#define REG_SDIO_BUS_CTRL_8821C 0x10250085
+#define REG_SDIO_HSUS_CTRL_8821C 0x10250086
+#define REG_SDIO_RESPONSE_TIMER_8821C 0x10250088
+#define REG_SDIO_CMD_CRC_8821C 0x1025008A
+#define REG_SDIO_HSISR_8821C 0x10250090
+#define REG_SDIO_ERR_RPT_8821C 0x102500C0
+#define REG_SDIO_CMD_ERRCNT_8821C 0x102500C2
+#define REG_SDIO_DATA_ERRCNT_8821C 0x102500C3
+#define REG_SDIO_CMD_ERR_CONTENT_8821C 0x102500C4
+#define REG_SDIO_CRC_ERR_IDX_8821C 0x102500C9
+#define REG_SDIO_DATA_CRC_8821C 0x102500CA
+#define REG_SDIO_DATA_REPLY_TIME_8821C 0x102500CB
+
+#endif

hal/halmac/halmac_reg_8822b.h

@@ -0,0 +1,733 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_REG_8822B_H
+#define __INC_HALMAC_REG_8822B_H
+
+#define REG_SYS_ISO_CTRL_8822B 0x0000
+#define REG_SYS_FUNC_EN_8822B 0x0002
+#define REG_SYS_PW_CTRL_8822B 0x0004
+#define REG_SYS_CLK_CTRL_8822B 0x0008
+#define REG_SYS_EEPROM_CTRL_8822B 0x000A
+#define REG_EE_VPD_8822B 0x000C
+#define REG_SYS_SWR_CTRL1_8822B 0x0010
+#define REG_SYS_SWR_CTRL2_8822B 0x0014
+#define REG_SYS_SWR_CTRL3_8822B 0x0018
+#define REG_RSV_CTRL_8822B 0x001C
+#define REG_RF_CTRL_8822B 0x001F
+#define REG_AFE_LDO_CTRL_8822B 0x0020
+#define REG_AFE_CTRL1_8822B 0x0024
+#define REG_AFE_CTRL2_8822B 0x0028
+#define REG_AFE_CTRL3_8822B 0x002C
+#define REG_EFUSE_CTRL_8822B 0x0030
+#define REG_LDO_EFUSE_CTRL_8822B 0x0034
+#define REG_PWR_OPTION_CTRL_8822B 0x0038
+#define REG_CAL_TIMER_8822B 0x003C
+#define REG_ACLK_MON_8822B 0x003E
+#define REG_GPIO_MUXCFG_8822B 0x0040
+#define REG_GPIO_PIN_CTRL_8822B 0x0044
+#define REG_GPIO_INTM_8822B 0x0048
+#define REG_LED_CFG_8822B 0x004C
+#define REG_FSIMR_8822B 0x0050
+#define REG_FSISR_8822B 0x0054
+#define REG_HSIMR_8822B 0x0058
+#define REG_HSISR_8822B 0x005C
+#define REG_GPIO_EXT_CTRL_8822B 0x0060
+#define REG_PAD_CTRL1_8822B 0x0064
+#define REG_WL_BT_PWR_CTRL_8822B 0x0068
+#define REG_SDM_DEBUG_8822B 0x006C
+#define REG_SYS_SDIO_CTRL_8822B 0x0070
+#define REG_HCI_OPT_CTRL_8822B 0x0074
+#define REG_AFE_CTRL4_8822B 0x0078
+#define REG_LDO_SWR_CTRL_8822B 0x007C
+#define REG_MCUFW_CTRL_8822B 0x0080
+#define REG_MCU_TST_CFG_8822B 0x0084
+#define REG_HMEBOX_E0_E1_8822B 0x0088
+#define REG_HMEBOX_E2_E3_8822B 0x008C
+#define REG_WLLPS_CTRL_8822B 0x0090
+#define REG_AFE_CTRL5_8822B 0x0094
+#define REG_GPIO_DEBOUNCE_CTRL_8822B 0x0098
+#define REG_RPWM2_8822B 0x009C
+#define REG_SYSON_FSM_MON_8822B 0x00A0
+#define REG_AFE_CTRL6_8822B 0x00A4
+#define REG_PMC_DBG_CTRL1_8822B 0x00A8
+#define REG_AFE_CTRL7_8822B 0x00AC
+#define REG_HIMR0_8822B 0x00B0
+#define REG_HISR0_8822B 0x00B4
+#define REG_HIMR1_8822B 0x00B8
+#define REG_HISR1_8822B 0x00BC
+#define REG_DBG_PORT_SEL_8822B 0x00C0
+#define REG_PAD_CTRL2_8822B 0x00C4
+#define REG_PMC_DBG_CTRL2_8822B 0x00CC
+#define REG_BIST_CTRL_8822B 0x00D0
+#define REG_BIST_RPT_8822B 0x00D4
+#define REG_MEM_CTRL_8822B 0x00D8
+#define REG_AFE_CTRL8_8822B 0x00DC
+#define REG_USB_SIE_INTF_8822B 0x00E0
+#define REG_PCIE_MIO_INTF_8822B 0x00E4
+#define REG_PCIE_MIO_INTD_8822B 0x00E8
+#define REG_WLRF1_8822B 0x00EC
+#define REG_SYS_CFG1_8822B 0x00F0
+#define REG_SYS_STATUS1_8822B 0x00F4
+#define REG_SYS_STATUS2_8822B 0x00F8
+#define REG_SYS_CFG2_8822B 0x00FC
+#define REG_SYS_CFG3_8822B 0x1000
+#define REG_SYS_CFG4_8822B 0x1034
+#define REG_SYS_CFG5_8822B 0x1070
+#define REG_CPU_DMEM_CON_8822B 0x1080
+#define REG_BOOT_REASON_8822B 0x1088
+#define REG_NFCPAD_CTRL_8822B 0x10A8
+#define REG_HIMR2_8822B 0x10B0
+#define REG_HISR2_8822B 0x10B4
+#define REG_HIMR3_8822B 0x10B8
+#define REG_HISR3_8822B 0x10BC
+#define REG_SW_MDIO_8822B 0x10C0
+#define REG_SW_FLUSH_8822B 0x10C4
+#define REG_H2C_PKT_READADDR_8822B 0x10D0
+#define REG_H2C_PKT_WRITEADDR_8822B 0x10D4
+#define REG_MEM_PWR_CRTL_8822B 0x10D8
+#define REG_FW_DBG0_8822B 0x10E0
+#define REG_FW_DBG1_8822B 0x10E4
+#define REG_FW_DBG2_8822B 0x10E8
+#define REG_FW_DBG3_8822B 0x10EC
+#define REG_FW_DBG4_8822B 0x10F0
+#define REG_FW_DBG5_8822B 0x10F4
+#define REG_FW_DBG6_8822B 0x10F8
+#define REG_FW_DBG7_8822B 0x10FC
+#define REG_CR_8822B 0x0100
+#define REG_TSF_CLK_STATE_8822B 0x0108
+#define REG_TXDMA_PQ_MAP_8822B 0x010C
+#define REG_TRXFF_BNDY_8822B 0x0114
+#define REG_PTA_I2C_MBOX_8822B 0x0118
+#define REG_RXFF_BNDY_8822B 0x011C
+#define REG_FE1IMR_8822B 0x0120
+#define REG_FE1ISR_8822B 0x0124
+#define REG_CPWM_8822B 0x012C
+#define REG_FWIMR_8822B 0x0130
+#define REG_FWISR_8822B 0x0134
+#define REG_FTIMR_8822B 0x0138
+#define REG_FTISR_8822B 0x013C
+#define REG_PKTBUF_DBG_CTRL_8822B 0x0140
+#define REG_PKTBUF_DBG_DATA_L_8822B 0x0144
+#define REG_PKTBUF_DBG_DATA_H_8822B 0x0148
+#define REG_CPWM2_8822B 0x014C
+#define REG_TC0_CTRL_8822B 0x0150
+#define REG_TC1_CTRL_8822B 0x0154
+#define REG_TC2_CTRL_8822B 0x0158
+#define REG_TC3_CTRL_8822B 0x015C
+#define REG_TC4_CTRL_8822B 0x0160
+#define REG_TCUNIT_BASE_8822B 0x0164
+#define REG_TC5_CTRL_8822B 0x0168
+#define REG_TC6_CTRL_8822B 0x016C
+#define REG_MBIST_FAIL_8822B 0x0170
+#define REG_MBIST_START_PAUSE_8822B 0x0174
+#define REG_MBIST_DONE_8822B 0x0178
+#define REG_MBIST_FAIL_NRML_8822B 0x017C
+#define REG_AES_DECRPT_DATA_8822B 0x0180
+#define REG_AES_DECRPT_CFG_8822B 0x0184
+#define REG_TMETER_8822B 0x0190
+#define REG_OSC_32K_CTRL_8822B 0x0194
+#define REG_32K_CAL_REG1_8822B 0x0198
+#define REG_C2HEVT_8822B 0x01A0
+#define REG_C2HEVT_1_8822B 0x01A4
+#define REG_C2HEVT_2_8822B 0x01A8
+#define REG_C2HEVT_3_8822B 0x01AC
+#define REG_SW_DEFINED_PAGE1_8822B 0x01B8
+#define REG_MCUTST_I_8822B 0x01C0
+#define REG_MCUTST_II_8822B 0x01C4
+#define REG_FMETHR_8822B 0x01C8
+#define REG_HMETFR_8822B 0x01CC
+#define REG_HMEBOX0_8822B 0x01D0
+#define REG_HMEBOX1_8822B 0x01D4
+#define REG_HMEBOX2_8822B 0x01D8
+#define REG_HMEBOX3_8822B 0x01DC
+#define REG_LLT_INIT_8822B 0x01E0
+#define REG_LLT_INIT_ADDR_8822B 0x01E4
+#define REG_BB_ACCESS_CTRL_8822B 0x01E8
+#define REG_BB_ACCESS_DATA_8822B 0x01EC
+#define REG_HMEBOX_E0_8822B 0x01F0
+#define REG_HMEBOX_E1_8822B 0x01F4
+#define REG_HMEBOX_E2_8822B 0x01F8
+#define REG_HMEBOX_E3_8822B 0x01FC
+#define REG_CR_EXT_8822B 0x1100
+#define REG_FWFF_8822B 0x1114
+#define REG_RXFF_PTR_V1_8822B 0x1118
+#define REG_RXFF_WTR_V1_8822B 0x111C
+#define REG_FE2IMR_8822B 0x1120
+#define REG_FE2ISR_8822B 0x1124
+#define REG_FE3IMR_8822B 0x1128
+#define REG_FE3ISR_8822B 0x112C
+#define REG_FE4IMR_8822B 0x1130
+#define REG_FE4ISR_8822B 0x1134
+#define REG_FT1IMR_8822B 0x1138
+#define REG_FT1ISR_8822B 0x113C
+#define REG_SPWR0_8822B 0x1140
+#define REG_SPWR1_8822B 0x1144
+#define REG_SPWR2_8822B 0x1148
+#define REG_SPWR3_8822B 0x114C
+#define REG_POWSEQ_8822B 0x1150
+#define REG_TC7_CTRL_V1_8822B 0x1158
+#define REG_TC8_CTRL_V1_8822B 0x115C
+#define REG_FT2IMR_8822B 0x11E0
+#define REG_FT2ISR_8822B 0x11E4
+#define REG_MSG2_8822B 0x11F0
+#define REG_MSG3_8822B 0x11F4
+#define REG_MSG4_8822B 0x11F8
+#define REG_MSG5_8822B 0x11FC
+#define REG_FIFOPAGE_CTRL_1_8822B 0x0200
+#define REG_FIFOPAGE_CTRL_2_8822B 0x0204
+#define REG_AUTO_LLT_V1_8822B 0x0208
+#define REG_TXDMA_OFFSET_CHK_8822B 0x020C
+#define REG_TXDMA_STATUS_8822B 0x0210
+#define REG_TX_DMA_DBG_8822B 0x0214
+#define REG_TQPNT1_8822B 0x0218
+#define REG_TQPNT2_8822B 0x021C
+#define REG_TQPNT3_8822B 0x0220
+#define REG_TQPNT4_8822B 0x0224
+#define REG_RQPN_CTRL_1_8822B 0x0228
+#define REG_RQPN_CTRL_2_8822B 0x022C
+#define REG_FIFOPAGE_INFO_1_8822B 0x0230
+#define REG_FIFOPAGE_INFO_2_8822B 0x0234
+#define REG_FIFOPAGE_INFO_3_8822B 0x0238
+#define REG_FIFOPAGE_INFO_4_8822B 0x023C
+#define REG_FIFOPAGE_INFO_5_8822B 0x0240
+#define REG_H2C_HEAD_8822B 0x0244
+#define REG_H2C_TAIL_8822B 0x0248
+#define REG_H2C_READ_ADDR_8822B 0x024C
+#define REG_H2C_WR_ADDR_8822B 0x0250
+#define REG_H2C_INFO_8822B 0x0254
+#define REG_RXDMA_AGG_PG_TH_8822B 0x0280
+#define REG_RXPKT_NUM_8822B 0x0284
+#define REG_RXDMA_STATUS_8822B 0x0288
+#define REG_RXDMA_DPR_8822B 0x028C
+#define REG_RXDMA_MODE_8822B 0x0290
+#define REG_C2H_PKT_8822B 0x0294
+#define REG_FWFF_C2H_8822B 0x0298
+#define REG_FWFF_CTRL_8822B 0x029C
+#define REG_FWFF_PKT_INFO_8822B 0x02A0
+#define REG_DDMA_CH0SA_8822B 0x1200
+#define REG_DDMA_CH0DA_8822B 0x1204
+#define REG_DDMA_CH0CTRL_8822B 0x1208
+#define REG_DDMA_CH1SA_8822B 0x1210
+#define REG_DDMA_CH1DA_8822B 0x1214
+#define REG_DDMA_CH1CTRL_8822B 0x1218
+#define REG_DDMA_CH2SA_8822B 0x1220
+#define REG_DDMA_CH2DA_8822B 0x1224
+#define REG_DDMA_CH2CTRL_8822B 0x1228
+#define REG_DDMA_CH3SA_8822B 0x1230
+#define REG_DDMA_CH3DA_8822B 0x1234
+#define REG_DDMA_CH3CTRL_8822B 0x1238
+#define REG_DDMA_CH4SA_8822B 0x1240
+#define REG_DDMA_CH4DA_8822B 0x1244
+#define REG_DDMA_CH4CTRL_8822B 0x1248
+#define REG_DDMA_CH5SA_8822B 0x1250
+#define REG_DDMA_CH5DA_8822B 0x1254
+#define REG_REG_DDMA_CH5CTRL_8822B 0x1258
+#define REG_DDMA_INT_MSK_8822B 0x12E0
+#define REG_DDMA_CHSTATUS_8822B 0x12E8
+#define REG_DDMA_CHKSUM_8822B 0x12F0
+#define REG_DDMA_MONITOR_8822B 0x12FC
+#define REG_PCIE_CTRL_8822B 0x0300
+#define REG_INT_MIG_8822B 0x0304
+#define REG_BCNQ_TXBD_DESA_8822B 0x0308
+#define REG_MGQ_TXBD_DESA_8822B 0x0310
+#define REG_VOQ_TXBD_DESA_8822B 0x0318
+#define REG_VIQ_TXBD_DESA_8822B 0x0320
+#define REG_BEQ_TXBD_DESA_8822B 0x0328
+#define REG_BKQ_TXBD_DESA_8822B 0x0330
+#define REG_RXQ_RXBD_DESA_8822B 0x0338
+#define REG_HI0Q_TXBD_DESA_8822B 0x0340
+#define REG_HI1Q_TXBD_DESA_8822B 0x0348
+#define REG_HI2Q_TXBD_DESA_8822B 0x0350
+#define REG_HI3Q_TXBD_DESA_8822B 0x0358
+#define REG_HI4Q_TXBD_DESA_8822B 0x0360
+#define REG_HI5Q_TXBD_DESA_8822B 0x0368
+#define REG_HI6Q_TXBD_DESA_8822B 0x0370
+#define REG_HI7Q_TXBD_DESA_8822B 0x0378
+#define REG_MGQ_TXBD_NUM_8822B 0x0380
+#define REG_RX_RXBD_NUM_8822B 0x0382
+#define REG_VOQ_TXBD_NUM_8822B 0x0384
+#define REG_VIQ_TXBD_NUM_8822B 0x0386
+#define REG_BEQ_TXBD_NUM_8822B 0x0388
+#define REG_BKQ_TXBD_NUM_8822B 0x038A
+#define REG_HI0Q_TXBD_NUM_8822B 0x038C
+#define REG_HI1Q_TXBD_NUM_8822B 0x038E
+#define REG_HI2Q_TXBD_NUM_8822B 0x0390
+#define REG_HI3Q_TXBD_NUM_8822B 0x0392
+#define REG_HI4Q_TXBD_NUM_8822B 0x0394
+#define REG_HI5Q_TXBD_NUM_8822B 0x0396
+#define REG_HI6Q_TXBD_NUM_8822B 0x0398
+#define REG_HI7Q_TXBD_NUM_8822B 0x039A
+#define REG_TSFTIMER_HCI_8822B 0x039C
+#define REG_BD_RWPTR_CLR_8822B 0x039C
+#define REG_VOQ_TXBD_IDX_8822B 0x03A0
+#define REG_VIQ_TXBD_IDX_8822B 0x03A4
+#define REG_BEQ_TXBD_IDX_8822B 0x03A8
+#define REG_BKQ_TXBD_IDX_8822B 0x03AC
+#define REG_MGQ_TXBD_IDX_8822B 0x03B0
+#define REG_RXQ_RXBD_IDX_8822B 0x03B4
+#define REG_HI0Q_TXBD_IDX_8822B 0x03B8
+#define REG_HI1Q_TXBD_IDX_8822B 0x03BC
+#define REG_HI2Q_TXBD_IDX_8822B 0x03C0
+#define REG_HI3Q_TXBD_IDX_8822B 0x03C4
+#define REG_HI4Q_TXBD_IDX_8822B 0x03C8
+#define REG_HI5Q_TXBD_IDX_8822B 0x03CC
+#define REG_HI6Q_TXBD_IDX_8822B 0x03D0
+#define REG_HI7Q_TXBD_IDX_8822B 0x03D4
+#define REG_DBG_SEL_V1_8822B 0x03D8
+#define REG_PCIE_HRPWM1_V1_8822B 0x03D9
+#define REG_PCIE_HCPWM1_V1_8822B 0x03DA
+#define REG_PCIE_CTRL2_8822B 0x03DB
+#define REG_PCIE_HRPWM2_V1_8822B 0x03DC
+#define REG_PCIE_HCPWM2_V1_8822B 0x03DE
+#define REG_PCIE_H2C_MSG_V1_8822B 0x03E0
+#define REG_PCIE_C2H_MSG_V1_8822B 0x03E4
+#define REG_DBI_WDATA_V1_8822B 0x03E8
+#define REG_DBI_RDATA_V1_8822B 0x03EC
+#define REG_DBI_FLAG_V1_8822B 0x03F0
+#define REG_MDIO_V1_8822B 0x03F4
+#define REG_PCIE_MIX_CFG_8822B 0x03F8
+#define REG_HCI_MIX_CFG_8822B 0x03FC
+#define REG_STC_INT_CS_8822B 0x1300
+#define REG_ST_INT_CFG_8822B 0x1304
+#define REG_CMU_DLY_CTRL_8822B 0x1310
+#define REG_CMU_DLY_CFG_8822B 0x1314
+#define REG_H2CQ_TXBD_DESA_8822B 0x1320
+#define REG_H2CQ_TXBD_NUM_8822B 0x1328
+#define REG_H2CQ_TXBD_IDX_8822B 0x132C
+#define REG_H2CQ_CSR_8822B 0x1330
+#define REG_CHANGE_PCIE_SPEED_8822B 0x1350
+#define REG_OLD_DEHANG_8822B 0x13F4
+#define REG_Q0_INFO_8822B 0x0400
+#define REG_Q1_INFO_8822B 0x0404
+#define REG_Q2_INFO_8822B 0x0408
+#define REG_Q3_INFO_8822B 0x040C
+#define REG_MGQ_INFO_8822B 0x0410
+#define REG_HIQ_INFO_8822B 0x0414
+#define REG_BCNQ_INFO_8822B 0x0418
+#define REG_TXPKT_EMPTY_8822B 0x041A
+#define REG_CPU_MGQ_INFO_8822B 0x041C
+#define REG_FWHW_TXQ_CTRL_8822B 0x0420
+#define REG_DATAFB_SEL_8822B 0x0423
+#define REG_BCNQ_BDNY_V1_8822B 0x0424
+#define REG_LIFETIME_EN_8822B 0x0426
+#define REG_SPEC_SIFS_8822B 0x0428
+#define REG_RETRY_LIMIT_8822B 0x042A
+#define REG_TXBF_CTRL_8822B 0x042C
+#define REG_DARFRC_8822B 0x0430
+#define REG_RARFRC_8822B 0x0438
+#define REG_RRSR_8822B 0x0440
+#define REG_ARFR0_8822B 0x0444
+#define REG_ARFR1_V1_8822B 0x044C
+#define REG_CCK_CHECK_8822B 0x0454
+#define REG_AMPDU_MAX_TIME_V1_8822B 0x0455
+#define REG_BCNQ1_BDNY_V1_8822B 0x0456
+#define REG_AMPDU_MAX_LENGTH_8822B 0x0458
+#define REG_ACQ_STOP_8822B 0x045C
+#define REG_NDPA_RATE_8822B 0x045D
+#define REG_TX_HANG_CTRL_8822B 0x045E
+#define REG_NDPA_OPT_CTRL_8822B 0x045F
+#define REG_RD_RESP_PKT_TH_8822B 0x0463
+#define REG_CMDQ_INFO_8822B 0x0464
+#define REG_Q4_INFO_8822B 0x0468
+#define REG_Q5_INFO_8822B 0x046C
+#define REG_Q6_INFO_8822B 0x0470
+#define REG_Q7_INFO_8822B 0x0474
+#define REG_WMAC_LBK_BUF_HD_V1_8822B 0x0478
+#define REG_MGQ_BDNY_V1_8822B 0x047A
+#define REG_TXRPT_CTRL_8822B 0x047C
+#define REG_INIRTS_RATE_SEL_8822B 0x0480
+#define REG_BASIC_CFEND_RATE_8822B 0x0481
+#define REG_STBC_CFEND_RATE_8822B 0x0482
+#define REG_DATA_SC_8822B 0x0483
+#define REG_MACID_SLEEP3_8822B 0x0484
+#define REG_MACID_SLEEP1_8822B 0x0488
+#define REG_ARFR2_V1_8822B 0x048C
+#define REG_ARFR3_V1_8822B 0x0494
+#define REG_ARFR4_8822B 0x049C
+#define REG_ARFR5_8822B 0x04A4
+#define REG_TXRPT_START_OFFSET_8822B 0x04AC
+#define REG_POWER_STAGE1_8822B 0x04B4
+#define REG_POWER_STAGE2_8822B 0x04B8
+#define REG_SW_AMPDU_BURST_MODE_CTRL_8822B 0x04BC
+#define REG_PKT_LIFE_TIME_8822B 0x04C0
+#define REG_STBC_SETTING_8822B 0x04C4
+#define REG_STBC_SETTING2_8822B 0x04C5
+#define REG_QUEUE_CTRL_8822B 0x04C6
+#define REG_SINGLE_AMPDU_CTRL_8822B 0x04C7
+#define REG_PROT_MODE_CTRL_8822B 0x04C8
+#define REG_BAR_MODE_CTRL_8822B 0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT_8822B 0x04CF
+#define REG_MACID_SLEEP2_8822B 0x04D0
+#define REG_MACID_SLEEP_8822B 0x04D4
+#define REG_HW_SEQ0_8822B 0x04D8
+#define REG_HW_SEQ1_8822B 0x04DA
+#define REG_HW_SEQ2_8822B 0x04DC
+#define REG_HW_SEQ3_8822B 0x04DE
+#define REG_NULL_PKT_STATUS_V1_8822B 0x04E0
+#define REG_PTCL_ERR_STATUS_8822B 0x04E2
+#define REG_NULL_PKT_STATUS_EXTEND_8822B 0x04E3
+#define REG_VIDEO_ENHANCEMENT_FUN_8822B 0x04E4
+#define REG_BT_POLLUTE_PKT_CNT_8822B 0x04E8
+#define REG_PTCL_DBG_8822B 0x04EC
+#define REG_CPUMGQ_TIMER_CTRL2_8822B 0x04F4
+#define REG_DUMMY_PAGE4_V1_8822B 0x04FC
+#define REG_MOREDATA_8822B 0x04FE
+#define REG_Q0_Q1_INFO_8822B 0x1400
+#define REG_Q2_Q3_INFO_8822B 0x1404
+#define REG_Q4_Q5_INFO_8822B 0x1408
+#define REG_Q6_Q7_INFO_8822B 0x140C
+#define REG_MGQ_HIQ_INFO_8822B 0x1410
+#define REG_CMDQ_BCNQ_INFO_8822B 0x1414
+#define REG_USEREG_SETTING_8822B 0x1420
+#define REG_AESIV_SETTING_8822B 0x1424
+#define REG_BF0_TIME_SETTING_8822B 0x1428
+#define REG_BF1_TIME_SETTING_8822B 0x142C
+#define REG_BF_TIMEOUT_EN_8822B 0x1430
+#define REG_MACID_RELEASE0_8822B 0x1434
+#define REG_MACID_RELEASE1_8822B 0x1438
+#define REG_MACID_RELEASE2_8822B 0x143C
+#define REG_MACID_RELEASE3_8822B 0x1440
+#define REG_MACID_RELEASE_SETTING_8822B 0x1444
+#define REG_FAST_EDCA_VOVI_SETTING_8822B 0x1448
+#define REG_FAST_EDCA_BEBK_SETTING_8822B 0x144C
+#define REG_MACID_DROP0_8822B 0x1450
+#define REG_MACID_DROP1_8822B 0x1454
+#define REG_MACID_DROP2_8822B 0x1458
+#define REG_MACID_DROP3_8822B 0x145C
+#define REG_R_MACID_RELEASE_SUCCESS_0_8822B 0x1460
+#define REG_R_MACID_RELEASE_SUCCESS_1_8822B 0x1464
+#define REG_R_MACID_RELEASE_SUCCESS_2_8822B 0x1468
+#define REG_R_MACID_RELEASE_SUCCESS_3_8822B 0x146C
+#define REG_MGG_FIFO_CRTL_8822B 0x1470
+#define REG_MGG_FIFO_INT_8822B 0x1474
+#define REG_MGG_FIFO_LIFETIME_8822B 0x1478
+#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0x147C
+#define REG_SHCUT_SETTING_8822B 0x1480
+#define REG_SHCUT_LLC_ETH_TYPE0_8822B 0x1484
+#define REG_SHCUT_LLC_ETH_TYPE1_8822B 0x1488
+#define REG_SHCUT_LLC_OUI0_8822B 0x148C
+#define REG_SHCUT_LLC_OUI1_8822B 0x1490
+#define REG_SHCUT_LLC_OUI2_8822B 0x1494
+#define REG_SHCUT_LLC_OUI3_8822B 0x1498
+#define REG_MU_TX_CTL_8822B 0x14C0
+#define REG_MU_TX_CTL_8822B 0x14C0
+#define REG_MU_STA_GID_VLD_8822B 0x14C4
+#define REG_MU_STA_GID_VLD_8822B 0x14C4
+#define REG_MU_STA_USER_POS_INFO_8822B 0x14C8
+#define REG_MU_STA_USER_POS_INFO_8822B 0x14C8
+#define REG_MU_TRX_DBG_CNT_8822B 0x14D0
+#define REG_MU_TRX_DBG_CNT_8822B 0x14D0
+#define REG_EDCA_VO_PARAM_8822B 0x0500
+#define REG_EDCA_VI_PARAM_8822B 0x0504
+#define REG_EDCA_BE_PARAM_8822B 0x0508
+#define REG_EDCA_BK_PARAM_8822B 0x050C
+#define REG_BCNTCFG_8822B 0x0510
+#define REG_PIFS_8822B 0x0512
+#define REG_RDG_PIFS_8822B 0x0513
+#define REG_SIFS_8822B 0x0514
+#define REG_TSFTR_SYN_OFFSET_8822B 0x0518
+#define REG_AGGR_BREAK_TIME_8822B 0x051A
+#define REG_SLOT_8822B 0x051B
+#define REG_TX_PTCL_CTRL_8822B 0x0520
+#define REG_TXPAUSE_8822B 0x0522
+#define REG_DIS_TXREQ_CLR_8822B 0x0523
+#define REG_RD_CTRL_8822B 0x0524
+#define REG_MBSSID_CTRL_8822B 0x0526
+#define REG_P2PPS_CTRL_8822B 0x0527
+#define REG_PKT_LIFETIME_CTRL_8822B 0x0528
+#define REG_P2PPS_SPEC_STATE_8822B 0x052B
+#define REG_TXOP_LIMIT_CTRL_8822B 0x052C
+#define REG_BAR_TX_CTRL_8822B 0x0530
+#define REG_P2PON_DIS_TXTIME_8822B 0x0531
+#define REG_QUEUE_INCOL_THR_8822B 0x0538
+#define REG_QUEUE_INCOL_EN_8822B 0x053C
+#define REG_TBTT_PROHIBIT_8822B 0x0540
+#define REG_P2PPS_STATE_8822B 0x0543
+#define REG_RD_NAV_NXT_8822B 0x0544
+#define REG_NAV_PROT_LEN_8822B 0x0546
+#define REG_BCN_CTRL_8822B 0x0550
+#define REG_BCN_CTRL_CLINT0_8822B 0x0551
+#define REG_MBID_NUM_8822B 0x0552
+#define REG_DUAL_TSF_RST_8822B 0x0553
+#define REG_MBSSID_BCN_SPACE_8822B 0x0554
+#define REG_DRVERLYINT_8822B 0x0558
+#define REG_BCNDMATIM_8822B 0x0559
+#define REG_ATIMWND_8822B 0x055A
+#define REG_USTIME_TSF_8822B 0x055C
+#define REG_BCN_MAX_ERR_8822B 0x055D
+#define REG_RXTSF_OFFSET_CCK_8822B 0x055E
+#define REG_RXTSF_OFFSET_OFDM_8822B 0x055F
+#define REG_TSFTR_8822B 0x0560
+#define REG_FREERUN_CNT_8822B 0x0568
+#define REG_ATIMWND1_V1_8822B 0x0570
+#define REG_TBTT_PROHIBIT_INFRA_8822B 0x0571
+#define REG_CTWND_8822B 0x0572
+#define REG_BCNIVLCUNT_8822B 0x0573
+#define REG_BCNDROPCTRL_8822B 0x0574
+#define REG_HGQ_TIMEOUT_PERIOD_8822B 0x0575
+#define REG_TXCMD_TIMEOUT_PERIOD_8822B 0x0576
+#define REG_MISC_CTRL_8822B 0x0577
+#define REG_BCN_CTRL_CLINT1_8822B 0x0578
+#define REG_BCN_CTRL_CLINT2_8822B 0x0579
+#define REG_BCN_CTRL_CLINT3_8822B 0x057A
+#define REG_EXTEND_CTRL_8822B 0x057B
+#define REG_P2PPS1_SPEC_STATE_8822B 0x057C
+#define REG_P2PPS1_STATE_8822B 0x057D
+#define REG_P2PPS2_SPEC_STATE_8822B 0x057E
+#define REG_P2PPS2_STATE_8822B 0x057F
+#define REG_PS_TIMER0_8822B 0x0580
+#define REG_PS_TIMER1_8822B 0x0584
+#define REG_PS_TIMER2_8822B 0x0588
+#define REG_TBTT_CTN_AREA_8822B 0x058C
+#define REG_FORCE_BCN_IFS_8822B 0x058E
+#define REG_TXOP_MIN_8822B 0x0590
+#define REG_PRE_BKF_TIME_8822B 0x0592
+#define REG_CROSS_TXOP_CTRL_8822B 0x0593
+#define REG_ATIMWND2_8822B 0x05A0
+#define REG_ATIMWND3_8822B 0x05A1
+#define REG_ATIMWND4_8822B 0x05A2
+#define REG_ATIMWND5_8822B 0x05A3
+#define REG_ATIMWND6_8822B 0x05A4
+#define REG_ATIMWND7_8822B 0x05A5
+#define REG_ATIMUGT_8822B 0x05A6
+#define REG_HIQ_NO_LMT_EN_8822B 0x05A7
+#define REG_DTIM_COUNTER_ROOT_8822B 0x05A8
+#define REG_DTIM_COUNTER_VAP1_8822B 0x05A9
+#define REG_DTIM_COUNTER_VAP2_8822B 0x05AA
+#define REG_DTIM_COUNTER_VAP3_8822B 0x05AB
+#define REG_DTIM_COUNTER_VAP4_8822B 0x05AC
+#define REG_DTIM_COUNTER_VAP5_8822B 0x05AD
+#define REG_DTIM_COUNTER_VAP6_8822B 0x05AE
+#define REG_DTIM_COUNTER_VAP7_8822B 0x05AF
+#define REG_DIS_ATIM_8822B 0x05B0
+#define REG_EARLY_128US_8822B 0x05B1
+#define REG_P2PPS1_CTRL_8822B 0x05B2
+#define REG_P2PPS2_CTRL_8822B 0x05B3
+#define REG_TIMER0_SRC_SEL_8822B 0x05B4
+#define REG_NOA_UNIT_SEL_8822B 0x05B5
+#define REG_P2POFF_DIS_TXTIME_8822B 0x05B7
+#define REG_MBSSID_BCN_SPACE2_8822B 0x05B8
+#define REG_MBSSID_BCN_SPACE3_8822B 0x05BC
+#define REG_ACMHWCTRL_8822B 0x05C0
+#define REG_ACMRSTCTRL_8822B 0x05C1
+#define REG_ACMAVG_8822B 0x05C2
+#define REG_VO_ADMTIME_8822B 0x05C4
+#define REG_VI_ADMTIME_8822B 0x05C6
+#define REG_BE_ADMTIME_8822B 0x05C8
+#define REG_EDCA_RANDOM_GEN_8822B 0x05CC
+#define REG_TXCMD_NOA_SEL_8822B 0x05CF
+#define REG_NOA_PARAM_8822B 0x05E0
+#define REG_P2P_RST_8822B 0x05F0
+#define REG_SCHEDULER_RST_8822B 0x05F1
+#define REG_SCH_TXCMD_8822B 0x05F8
+#define REG_PAGE5_DUMMY_8822B 0x05FC
+#define REG_CPUMGQ_TX_TIMER_8822B 0x1500
+#define REG_PS_TIMER_A_8822B 0x1504
+#define REG_PS_TIMER_B_8822B 0x1508
+#define REG_PS_TIMER_C_8822B 0x150C
+#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822B 0x1510
+#define REG_CPUMGQ_TX_TIMER_EARLY_8822B 0x1514
+#define REG_PS_TIMER_A_EARLY_8822B 0x1515
+#define REG_PS_TIMER_B_EARLY_8822B 0x1516
+#define REG_PS_TIMER_C_EARLY_8822B 0x1517
+#define REG_CPUMGQ_PARAMETER_8822B 0x1518
+#define REG_WMAC_CR_8822B 0x0600
+#define REG_WMAC_FWPKT_CR_8822B 0x0601
+#define REG_BWOPMODE_8822B 0x0603
+#define REG_TCR_8822B 0x0604
+#define REG_RCR_8822B 0x0608
+#define REG_RX_PKT_LIMIT_8822B 0x060C
+#define REG_RX_DLK_TIME_8822B 0x060D
+#define REG_RX_DRVINFO_SZ_8822B 0x060F
+#define REG_MACID_8822B 0x0610
+#define REG_BSSID_8822B 0x0618
+#define REG_MAR_8822B 0x0620
+#define REG_MBIDCAMCFG_1_8822B 0x0628
+#define REG_MBIDCAMCFG_2_8822B 0x062C
+#define REG_WMAC_TCR_TSFT_OFS_8822B 0x0630
+#define REG_UDF_THSD_8822B 0x0632
+#define REG_ZLD_NUM_8822B 0x0633
+#define REG_STMP_THSD_8822B 0x0634
+#define REG_WMAC_TXTIMEOUT_8822B 0x0635
+#define REG_MCU_TEST_2_V1_8822B 0x0636
+#define REG_USTIME_EDCA_8822B 0x0638
+#define REG_MAC_SPEC_SIFS_8822B 0x063A
+#define REG_RESP_SIFS_CCK_8822B 0x063C
+#define REG_RESP_SIFS_OFDM_8822B 0x063E
+#define REG_ACKTO_8822B 0x0640
+#define REG_CTS2TO_8822B 0x0641
+#define REG_EIFS_8822B 0x0642
+#define REG_NAV_CTRL_8822B 0x0650
+#define REG_BACAMCMD_8822B 0x0654
+#define REG_BACAMCONTENT_8822B 0x0658
+#define REG_LBDLY_8822B 0x0660
+#define REG_WMAC_BACAM_RPMEN_8822B 0x0661
+#define REG_TX_RX_8822B 0x0662
+#define REG_WMAC_BITMAP_CTL_8822B 0x0663
+#define REG_RXERR_RPT_8822B 0x0664
+#define REG_WMAC_TRXPTCL_CTL_8822B 0x0668
+#define REG_CAMCMD_8822B 0x0670
+#define REG_CAMWRITE_8822B 0x0674
+#define REG_CAMREAD_8822B 0x0678
+#define REG_CAMDBG_8822B 0x067C
+#define REG_SECCFG_8822B 0x0680
+#define REG_RXFILTER_CATEGORY_1_8822B 0x0682
+#define REG_RXFILTER_ACTION_1_8822B 0x0683
+#define REG_RXFILTER_CATEGORY_2_8822B 0x0684
+#define REG_RXFILTER_ACTION_2_8822B 0x0685
+#define REG_RXFILTER_CATEGORY_3_8822B 0x0686
+#define REG_RXFILTER_ACTION_3_8822B 0x0687
+#define REG_RXFLTMAP3_8822B 0x0688
+#define REG_RXFLTMAP4_8822B 0x068A
+#define REG_RXFLTMAP5_8822B 0x068C
+#define REG_RXFLTMAP6_8822B 0x068E
+#define REG_WOW_CTRL_8822B 0x0690
+#define REG_NAN_RX_TSF_FILTER_8822B 0x0691
+#define REG_PS_RX_INFO_8822B 0x0692
+#define REG_WMMPS_UAPSD_TID_8822B 0x0693
+#define REG_LPNAV_CTRL_8822B 0x0694
+#define REG_WKFMCAM_CMD_8822B 0x0698
+#define REG_WKFMCAM_RWD_8822B 0x069C
+#define REG_RXFLTMAP0_8822B 0x06A0
+#define REG_RXFLTMAP1_8822B 0x06A2
+#define REG_RXFLTMAP2_8822B 0x06A4
+#define REG_BCN_PSR_RPT_8822B 0x06A8
+#define REG_FLC_RPC_8822B 0x06AC
+#define REG_FLC_RPCT_8822B 0x06AD
+#define REG_FLC_PTS_8822B 0x06AE
+#define REG_FLC_TRPC_8822B 0x06AF
+#define REG_RXPKTMON_CTRL_8822B 0x06B0
+#define REG_STATE_MON_8822B 0x06B4
+#define REG_ERROR_MON_8822B 0x06B8
+#define REG_SEARCH_MACID_8822B 0x06BC
+#define REG_BT_COEX_TABLE_8822B 0x06C0
+#define REG_RXCMD_0_8822B 0x06D0
+#define REG_RXCMD_1_8822B 0x06D4
+#define REG_WMAC_RESP_TXINFO_8822B 0x06D8
+#define REG_BBPSF_CTRL_8822B 0x06DC
+#define REG_P2P_RX_BCN_NOA_8822B 0x06E0
+#define REG_ASSOCIATED_BFMER0_INFO_8822B 0x06E4
+#define REG_ASSOCIATED_BFMER1_INFO_8822B 0x06EC
+#define REG_TX_CSI_RPT_PARAM_BW20_8822B 0x06F4
+#define REG_TX_CSI_RPT_PARAM_BW40_8822B 0x06F8
+#define REG_TX_CSI_RPT_PARAM_BW80_8822B 0x06FC
+#define REG_BCN_PSR_RPT2_8822B 0x1600
+#define REG_BCN_PSR_RPT3_8822B 0x1604
+#define REG_BCN_PSR_RPT4_8822B 0x1608
+#define REG_A1_ADDR_MASK_8822B 0x160C
+#define REG_MACID2_8822B 0x1620
+#define REG_BSSID2_8822B 0x1628
+#define REG_MACID3_8822B 0x1630
+#define REG_BSSID3_8822B 0x1638
+#define REG_MACID4_8822B 0x1640
+#define REG_BSSID4_8822B 0x1648
+#define REG_NOA_REPORT_8822B 0x1650
+#define REG_PWRBIT_SETTING_8822B 0x1660
+#define REG_WMAC_MU_BF_OPTION_8822B 0x167C
+#define REG_WMAC_MU_ARB_8822B 0x167E
+#define REG_WMAC_MU_OPTION_8822B 0x167F
+#define REG_WMAC_MU_BF_CTL_8822B 0x1680
+#define REG_WMAC_MU_BFRPT_PARA_8822B 0x1682
+#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B 0x1684
+#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8822B 0x1686
+#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8822B 0x1688
+#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8822B 0x168A
+#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8822B 0x168C
+#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8822B 0x168E
+#define REG_TRANSMIT_ADDRSS_0_8822B 0x16A0
+#define REG_TRANSMIT_ADDRSS_1_8822B 0x16A8
+#define REG_TRANSMIT_ADDRSS_2_8822B 0x16B0
+#define REG_TRANSMIT_ADDRSS_3_8822B 0x16B8
+#define REG_TRANSMIT_ADDRSS_4_8822B 0x16C0
+#define REG_MACID1_8822B 0x0700
+#define REG_BSSID1_8822B 0x0708
+#define REG_BCN_PSR_RPT1_8822B 0x0710
+#define REG_ASSOCIATED_BFMEE_SEL_8822B 0x0714
+#define REG_SND_PTCL_CTRL_8822B 0x0718
+#define REG_RX_CSI_RPT_INFO_8822B 0x071C
+#define REG_NS_ARP_CTRL_8822B 0x0720
+#define REG_NS_ARP_INFO_8822B 0x0724
+#define REG_BEAMFORMING_INFO_NSARP_V1_8822B 0x0728
+#define REG_BEAMFORMING_INFO_NSARP_8822B 0x072C
+#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822B 0x0750
+#define REG_WMAC_SWAES_CFG_8822B 0x0760
+#define REG_BT_COEX_V2_8822B 0x0762
+#define REG_BT_COEX_8822B 0x0764
+#define REG_WLAN_ACT_MASK_CTRL_8822B 0x0768
+#define REG_BT_COEX_ENHANCED_INTR_CTRL_8822B 0x076E
+#define REG_BT_ACT_STATISTICS_8822B 0x0770
+#define REG_BT_STATISTICS_CONTROL_REGISTER_8822B 0x0778
+#define REG_BT_STATUS_REPORT_REGISTER_8822B 0x077C
+#define REG_BT_INTERRUPT_CONTROL_REGISTER_8822B 0x0780
+#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822B 0x0784
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822B 0x0785
+#define REG_BT_INTERRUPT_STATUS_REGISTER_8822B 0x078F
+#define REG_BT_TDMA_TIME_REGISTER_8822B 0x0790
+#define REG_BT_ACT_REGISTER_8822B 0x0794
+#define REG_OBFF_CTRL_BASIC_8822B 0x0798
+#define REG_OBFF_CTRL2_TIMER_8822B 0x079C
+#define REG_LTR_CTRL_BASIC_8822B 0x07A0
+#define REG_LTR_CTRL2_TIMER_THRESHOLD_8822B 0x07A4
+#define REG_LTR_IDLE_LATENCY_V1_8822B 0x07A8
+#define REG_LTR_ACTIVE_LATENCY_V1_8822B 0x07AC
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822B 0x07B0
+#define REG_WMAC_PKTCNT_RWD_8822B 0x07B8
+#define REG_WMAC_PKTCNT_CTRL_8822B 0x07BC
+#define REG_IQ_DUMP_8822B 0x07C0
+#define REG_WMAC_FTM_CTL_8822B 0x07CC
+#define REG_WMAC_IQ_MDPK_FUNC_8822B 0x07CE
+#define REG_WMAC_OPTION_FUNCTION_8822B 0x07D0
+#define REG_RX_FILTER_FUNCTION_8822B 0x07DA
+#define REG_NDP_SIG_8822B 0x07E0
+#define REG_TXCMD_INFO_FOR_RSP_PKT_8822B 0x07E4
+#define REG_RTS_ADDRESS_0_8822B 0x07F0
+#define REG_RTS_ADDRESS_1_8822B 0x07F8
+#define REG__RPFM_MAP1_8822B 0x07FE
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822B 0x1700
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822B 0x1704
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822B 0x1708
+#define REG_SDIO_TX_CTRL_8822B 0x10250000
+#define REG_SDIO_HIMR_8822B 0x10250014
+#define REG_SDIO_HISR_8822B 0x10250018
+#define REG_SDIO_RX_REQ_LEN_8822B 0x1025001C
+#define REG_SDIO_FREE_TXPG_SEQ_V1_8822B 0x1025001F
+#define REG_SDIO_FREE_TXPG_8822B 0x10250020
+#define REG_SDIO_FREE_TXPG2_8822B 0x10250024
+#define REG_SDIO_OQT_FREE_TXPG_V1_8822B 0x10250028
+#define REG_SDIO_HTSFR_INFO_8822B 0x10250030
+#define REG_SDIO_HCPWM1_V2_8822B 0x10250038
+#define REG_SDIO_HCPWM2_V2_8822B 0x1025003A
+#define REG_SDIO_INDIRECT_REG_CFG_8822B 0x10250040
+#define REG_SDIO_INDIRECT_REG_DATA_8822B 0x10250044
+#define REG_SDIO_H2C_8822B 0x10250060
+#define REG_SDIO_C2H_8822B 0x10250064
+#define REG_SDIO_HRPWM1_8822B 0x10250080
+#define REG_SDIO_HRPWM2_8822B 0x10250082
+#define REG_SDIO_HPS_CLKR_8822B 0x10250084
+#define REG_SDIO_BUS_CTRL_8822B 0x10250085
+#define REG_SDIO_HSUS_CTRL_8822B 0x10250086
+#define REG_SDIO_RESPONSE_TIMER_8822B 0x10250088
+#define REG_SDIO_CMD_CRC_8822B 0x1025008A
+#define REG_SDIO_HSISR_8822B 0x10250090
+#define REG_SDIO_ERR_RPT_8822B 0x102500C0
+#define REG_SDIO_CMD_ERRCNT_8822B 0x102500C2
+#define REG_SDIO_DATA_ERRCNT_8822B 0x102500C3
+#define REG_SDIO_CMD_ERR_CONTENT_8822B 0x102500C4
+#define REG_SDIO_CRC_ERR_IDX_8822B 0x102500C9
+#define REG_SDIO_DATA_CRC_8822B 0x102500CA
+#define REG_SDIO_DATA_REPLY_TIME_8822B 0x102500CB
+
+#endif

hal/halmac/halmac_reg_8822c.h

@@ -0,0 +1,875 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_REG_8822C_H
+#define __INC_HALMAC_REG_8822C_H
+
+#define REG_SYS_ISO_CTRL_8822C 0x0000
+#define REG_SYS_FUNC_EN_8822C 0x0002
+#define REG_SYS_PW_CTRL_8822C 0x0004
+#define REG_SYS_CLK_CTRL_8822C 0x0008
+#define REG_SYS_EEPROM_CTRL_8822C 0x000A
+#define REG_EE_VPD_8822C 0x000C
+#define REG_SYS_SWR_CTRL1_8822C 0x0010
+#define REG_SYS_SWR_CTRL2_8822C 0x0014
+#define REG_SYS_SWR_CTRL3_8822C 0x0018
+#define REG_RSV_CTRL_8822C 0x001C
+#define REG_RF_CTRL_8822C 0x001F
+#define REG_AFE_LDO_CTRL_8822C 0x0020
+#define REG_AFE_CTRL1_8822C 0x0024
+#define REG_ANAPARSW_POW_MAC_8822C 0x0028
+#define REG_ANAPARLDO_POW_MAC_8822C 0x0029
+#define REG_ANAPAR_POW_MAC_8822C 0x002A
+#define REG_ANAPAR_POW_XTAL_8822C 0x002B
+#define REG_ANAPARLDO_MAC_8822C 0x002C
+#define REG_EFUSE_CTRL_8822C 0x0030
+#define REG_LDO_EFUSE_CTRL_8822C 0x0034
+#define REG_PWR_OPTION_CTRL_8822C 0x0038
+#define REG_CAL_TIMER_8822C 0x003C
+#define REG_ACLK_MON_8822C 0x003E
+#define REG_GPIO_MUXCFG_2_8822C 0x003F
+#define REG_GPIO_MUXCFG_8822C 0x0040
+#define REG_GPIO_PIN_CTRL_8822C 0x0044
+#define REG_GPIO_INTM_8822C 0x0048
+#define REG_LED_CFG_8822C 0x004C
+#define REG_FSIMR_8822C 0x0050
+#define REG_FSISR_8822C 0x0054
+#define REG_HSIMR_8822C 0x0058
+#define REG_HSISR_8822C 0x005C
+#define REG_GPIO_EXT_CTRL_8822C 0x0060
+#define REG_PAD_CTRL1_8822C 0x0064
+#define REG_WL_BT_PWR_CTRL_8822C 0x0068
+#define REG_SDM_DEBUG_8822C 0x006C
+#define REG_SYS_SDIO_CTRL_8822C 0x0070
+#define REG_HCI_OPT_CTRL_8822C 0x0074
+#define REG_HCI_BG_CTRL_8822C 0x0078
+#define REG_HCI_LDO_CTRL_8822C 0x007A
+#define REG_LDO_SWR_CTRL_8822C 0x007C
+#define REG_MCUFW_CTRL_8822C 0x0080
+#define REG_MCU_TST_CFG_8822C 0x0084
+#define REG_HMEBOX_E0_E1_8822C 0x0088
+#define REG_HMEBOX_E2_E3_8822C 0x008C
+#define REG_WLLPS_CTRL_8822C 0x0090
+#define REG_GPIO_DEBOUNCE_CTRL_8822C 0x0098
+#define REG_RPWM2_8822C 0x009C
+#define REG_SYSON_FSM_MON_8822C 0x00A0
+#define REG_PMC_DBG_CTRL1_8822C 0x00A8
+#define REG_HIMR0_8822C 0x00B0
+#define REG_HISR0_8822C 0x00B4
+#define REG_HIMR1_8822C 0x00B8
+#define REG_HISR1_8822C 0x00BC
+#define REG_DBG_PORT_SEL_8822C 0x00C0
+#define REG_PAD_CTRL2_8822C 0x00C4
+#define REG_PMC_DBG_CTRL2_8822C 0x00CC
+#define REG_BIST_CTRL_8822C 0x00D0
+#define REG_BIST_RPT_8822C 0x00D4
+#define REG_MEM_CTRL_8822C 0x00D8
+#define REG_USB_SIE_INTF_8822C 0x00E0
+#define REG_PCIE_MIO_INTF_8822C 0x00E4
+#define REG_PCIE_MIO_INTD_8822C 0x00E8
+#define REG_WLRF1_8822C 0x00EC
+#define REG_SYS_CFG1_8822C 0x00F0
+#define REG_SYS_STATUS1_8822C 0x00F4
+#define REG_SYS_STATUS2_8822C 0x00F8
+#define REG_SYS_CFG2_8822C 0x00FC
+#define REG_SYS_CFG3_8822C 0x1000
+#define REG_ANAPARSW_MAC_0_8822C 0x1010
+#define REG_ANAPARSW_MAC_1_8822C 0x1014
+#define REG_ANAPAR_MAC_0_8822C 0x1018
+#define REG_ANAPAR_MAC_1_8822C 0x101C
+#define REG_ANAPAR_MAC_2_8822C 0x1020
+#define REG_ANAPAR_XTAL_0_8822C 0x1040
+#define REG_ANAPAR_XTAL_1_8822C 0x1044
+#define REG_ANAPAR_XTAL_2_8822C 0x1048
+#define REG_ANAPAR_XTAL_3_8822C 0x104C
+#define REG_ANAPAR_XTAL_AACK_0_8822C 0x1054
+#define REG_ANAPAR_XTAL_AACK_1_8822C 0x1058
+#define REG_ANAPAR_XTAL_MODE_DECODER_8822C 0x1064
+#define REG_SYS_CFG5_8822C 0x1070
+#define REG_CPU_DMEM_CON_8822C 0x1080
+#define REG_BOOT_REASON_8822C 0x1088
+#define REG_HIMR2_8822C 0x10B0
+#define REG_HISR2_8822C 0x10B4
+#define REG_HIMR3_8822C 0x10B8
+#define REG_HISR3_8822C 0x10BC
+#define REG_SW_MDIO_8822C 0x10C0
+#define REG_H2C_PKT_READADDR_8822C 0x10D0
+#define REG_H2C_PKT_WRITEADDR_8822C 0x10D4
+#define REG_MEM_PWR_CRTL_8822C 0x10D8
+#define REG_FW_DBG6_8822C 0x10F8
+#define REG_FW_DBG7_8822C 0x10FC
+#define REG_CR_8822C 0x0100
+#define REG_PG_SIZE_8822C 0x0104
+#define REG_PKT_BUFF_ACCESS_CTRL_8822C 0x0106
+#define REG_TSF_CLK_STATE_8822C 0x0108
+#define REG_TXDMA_PQ_MAP_8822C 0x010C
+#define REG_TRXFF_BNDY_8822C 0x0114
+#define REG_PTA_I2C_MBOX_8822C 0x0118
+#define REG_RXFF_BNDY_8822C 0x011C
+#define REG_FE1IMR_8822C 0x0120
+#define REG_FE1ISR_8822C 0x0124
+#define REG_CPWM_8822C 0x012C
+#define REG_FWIMR_8822C 0x0130
+#define REG_FWISR_8822C 0x0134
+#define REG_FTIMR_8822C 0x0138
+#define REG_FTISR_8822C 0x013C
+#define REG_PKTBUF_DBG_CTRL_8822C 0x0140
+#define REG_PKTBUF_DBG_DATA_L_8822C 0x0144
+#define REG_PKTBUF_DBG_DATA_H_8822C 0x0148
+#define REG_CPWM2_8822C 0x014C
+#define REG_TC0_CTRL_8822C 0x0150
+#define REG_TC1_CTRL_8822C 0x0154
+#define REG_TC2_CTRL_8822C 0x0158
+#define REG_TC3_CTRL_8822C 0x015C
+#define REG_TC4_CTRL_8822C 0x0160
+#define REG_TCUNIT_BASE_8822C 0x0164
+#define REG_TC5_CTRL_8822C 0x0168
+#define REG_TC6_CTRL_8822C 0x016C
+#define REG_MBIST_DRF_FAIL_8822C 0x0170
+#define REG_MBIST_START_PAUSE_8822C 0x0174
+#define REG_MBIST_DONE_8822C 0x0178
+#define REG_MBIST_READ_BIST_RPT_8822C 0x017C
+#define REG_AES_DECRPT_DATA_8822C 0x0180
+#define REG_AES_DECRPT_CFG_8822C 0x0184
+#define REG_HIOE_CTRL_8822C 0x0188
+#define REG_HIOE_CFG_FILE_8822C 0x018C
+#define REG_TMETER_8822C 0x0190
+#define REG_OSC_32K_CTRL_8822C 0x0194
+#define REG_32K_CAL_REG1_8822C 0x0198
+#define REG_C2HEVT_8822C 0x01A0
+#define REG_C2HEVT_1_8822C 0x01A4
+#define REG_C2HEVT_2_8822C 0x01A8
+#define REG_C2HEVT_3_8822C 0x01AC
+#define REG_SW_DEFINED_PAGE1_8822C 0x01B8
+#define REG_SW_DEFINED_PAGE2_8822C 0x01BC
+#define REG_MCUTST_I_8822C 0x01C0
+#define REG_MCUTST_II_8822C 0x01C4
+#define REG_FMETHR_8822C 0x01C8
+#define REG_HMETFR_8822C 0x01CC
+#define REG_HMEBOX0_8822C 0x01D0
+#define REG_HMEBOX1_8822C 0x01D4
+#define REG_HMEBOX2_8822C 0x01D8
+#define REG_HMEBOX3_8822C 0x01DC
+#define REG_BB_ACCESS_CTRL_8822C 0x01E8
+#define REG_BB_ACCESS_DATA_8822C 0x01EC
+#define REG_HMEBOX_E0_8822C 0x01F0
+#define REG_HMEBOX_E1_8822C 0x01F4
+#define REG_HMEBOX_E2_8822C 0x01F8
+#define REG_HMEBOX_E3_8822C 0x01FC
+#define REG_CR_EXT_8822C 0x1100
+#define REG_FWFF_8822C 0x1114
+#define REG_RXFF_PTR_V1_8822C 0x1118
+#define REG_RXFF_WTR_V1_8822C 0x111C
+#define REG_FE2IMR_8822C 0x1120
+#define REG_FE2ISR_8822C 0x1124
+#define REG_FE3IMR_8822C 0x1128
+#define REG_FE3ISR_8822C 0x112C
+#define REG_FE4IMR_8822C 0x1130
+#define REG_FE4ISR_8822C 0x1134
+#define REG_FT1IMR_8822C 0x1138
+#define REG_FT1ISR_8822C 0x113C
+#define REG_SPWR0_8822C 0x1140
+#define REG_SPWR1_8822C 0x1144
+#define REG_SPWR2_8822C 0x1148
+#define REG_SPWR3_8822C 0x114C
+#define REG_POWSEQ_8822C 0x1150
+#define REG_TC7_CTRL_V1_8822C 0x1158
+#define REG_TC8_CTRL_V1_8822C 0x115C
+#define REG_RX_BCN_TBTT_ITVL0_8822C 0x1160
+#define REG_RX_BCN_TBTT_ITVL1_8822C 0x1164
+#define REG_IO_WRAP_ERR_FLAG_8822C 0x1170
+#define REG_SPEED_SENSOR_8822C 0x1180
+#define REG_SPEED_SENSOR1_8822C 0x1184
+#define REG_SPEED_SENSOR2_8822C 0x1188
+#define REG_SPEED_SENSOR3_8822C 0x118C
+#define REG_SPEED_SENSOR4_8822C 0x1190
+#define REG_SPEED_SENSOR5_8822C 0x1194
+#define REG_COUNTER_CTRL_8822C 0x11C4
+#define REG_COUNTER_THRESHOLD_8822C 0x11C8
+#define REG_COUNTER_SET_8822C 0x11CC
+#define REG_COUNTER_OVERFLOW_8822C 0x11D0
+#define REG_TXDMA_LEN_THRESHOLD_8822C 0x11D4
+#define REG_RXDMA_LEN_THRESHOLD_8822C 0x11D8
+#define REG_PCIE_EXEC_TIME_THRESHOLD_8822C 0x11DC
+#define REG_FT2IMR_8822C 0x11E0
+#define REG_FT2ISR_8822C 0x11E4
+#define REG_MSG2_8822C 0x11F0
+#define REG_MSG3_8822C 0x11F4
+#define REG_MSG4_8822C 0x11F8
+#define REG_MSG5_8822C 0x11FC
+#define REG_FIFOPAGE_CTRL_1_8822C 0x0200
+#define REG_FIFOPAGE_CTRL_2_8822C 0x0204
+#define REG_AUTO_LLT_V1_8822C 0x0208
+#define REG_TXDMA_OFFSET_CHK_8822C 0x020C
+#define REG_TXDMA_STATUS_8822C 0x0210
+#define REG_TX_DMA_DBG_8822C 0x0214
+#define REG_TQPNT1_8822C 0x0218
+#define REG_TQPNT2_8822C 0x021C
+#define REG_TQPNT3_8822C 0x0220
+#define REG_TQPNT4_8822C 0x0224
+#define REG_RQPN_CTRL_1_8822C 0x0228
+#define REG_RQPN_CTRL_2_8822C 0x022C
+#define REG_FIFOPAGE_INFO_1_8822C 0x0230
+#define REG_FIFOPAGE_INFO_2_8822C 0x0234
+#define REG_FIFOPAGE_INFO_3_8822C 0x0238
+#define REG_FIFOPAGE_INFO_4_8822C 0x023C
+#define REG_FIFOPAGE_INFO_5_8822C 0x0240
+#define REG_H2C_HEAD_8822C 0x0244
+#define REG_H2C_TAIL_8822C 0x0248
+#define REG_H2C_READ_ADDR_8822C 0x024C
+#define REG_H2C_WR_ADDR_8822C 0x0250
+#define REG_H2C_INFO_8822C 0x0254
+#define REG_PGSUB_CNT_8822C 0x026C
+#define REG_PGSUB_H_8822C 0x0270
+#define REG_PGSUB_N_8822C 0x0274
+#define REG_PGSUB_L_8822C 0x0278
+#define REG_PGSUB_E_8822C 0x027C
+#define REG_RXDMA_AGG_PG_TH_8822C 0x0280
+#define REG_RXPKT_NUM_8822C 0x0284
+#define REG_RXDMA_STATUS_8822C 0x0288
+#define REG_RXDMA_DPR_8822C 0x028C
+#define REG_RXDMA_MODE_8822C 0x0290
+#define REG_C2H_PKT_8822C 0x0294
+#define REG_FWFF_C2H_8822C 0x0298
+#define REG_FWFF_CTRL_8822C 0x029C
+#define REG_FWFF_PKT_INFO_8822C 0x02A0
+#define REG_RXPKTNUM_8822C 0x02B0
+#define REG_RXPKTNUM_TH_8822C 0x02B4
+#define REG_FW_MSG1_8822C 0x02E0
+#define REG_FW_MSG2_8822C 0x02E4
+#define REG_FW_MSG3_8822C 0x02E8
+#define REG_FW_MSG4_8822C 0x02EC
+#define REG_DDMA_CH0SA_8822C 0x1200
+#define REG_DDMA_CH0DA_8822C 0x1204
+#define REG_DDMA_CH0CTRL_8822C 0x1208
+#define REG_DDMA_CH1SA_8822C 0x1210
+#define REG_DDMA_CH1DA_8822C 0x1214
+#define REG_DDMA_CH1CTRL_8822C 0x1218
+#define REG_DDMA_CH2SA_8822C 0x1220
+#define REG_DDMA_CH2DA_8822C 0x1224
+#define REG_DDMA_CH2CTRL_8822C 0x1228
+#define REG_DDMA_CH3SA_8822C 0x1230
+#define REG_DDMA_CH3DA_8822C 0x1234
+#define REG_DDMA_CH3CTRL_8822C 0x1238
+#define REG_DDMA_CH4SA_8822C 0x1240
+#define REG_DDMA_CH4DA_8822C 0x1244
+#define REG_DDMA_CH4CTRL_8822C 0x1248
+#define REG_DDMA_CH5SA_8822C 0x1250
+#define REG_DDMA_CH5DA_8822C 0x1254
+#define REG_DDMA_CH5CTRL_8822C 0x1258
+#define REG_DDMA_INT_MSK_8822C 0x12E0
+#define REG_DDMA_CHSTATUS_8822C 0x12E8
+#define REG_DDMA_CHKSUM_8822C 0x12F0
+#define REG_DDMA_MONITOR_8822C 0x12FC
+#define REG_PCIE_CTRL_8822C 0x0300
+#define REG_INT_MIG_8822C 0x0304
+#define REG_BCNQ_TXBD_DESA_8822C 0x0308
+#define REG_MGQ_TXBD_DESA_8822C 0x0310
+#define REG_VOQ_TXBD_DESA_8822C 0x0318
+#define REG_VIQ_TXBD_DESA_8822C 0x0320
+#define REG_BEQ_TXBD_DESA_8822C 0x0328
+#define REG_BKQ_TXBD_DESA_8822C 0x0330
+#define REG_RXQ_RXBD_DESA_8822C 0x0338
+#define REG_HI0Q_TXBD_DESA_8822C 0x0340
+#define REG_HI1Q_TXBD_DESA_8822C 0x0348
+#define REG_HI2Q_TXBD_DESA_8822C 0x0350
+#define REG_HI3Q_TXBD_DESA_8822C 0x0358
+#define REG_HI4Q_TXBD_DESA_8822C 0x0360
+#define REG_HI5Q_TXBD_DESA_8822C 0x0368
+#define REG_HI6Q_TXBD_DESA_8822C 0x0370
+#define REG_HI7Q_TXBD_DESA_8822C 0x0378
+#define REG_MGQ_TXBD_NUM_8822C 0x0380
+#define REG_RX_RXBD_NUM_8822C 0x0382
+#define REG_VOQ_TXBD_NUM_8822C 0x0384
+#define REG_VIQ_TXBD_NUM_8822C 0x0386
+#define REG_BEQ_TXBD_NUM_8822C 0x0388
+#define REG_BKQ_TXBD_NUM_8822C 0x038A
+#define REG_HI0Q_TXBD_NUM_8822C 0x038C
+#define REG_HI1Q_TXBD_NUM_8822C 0x038E
+#define REG_HI2Q_TXBD_NUM_8822C 0x0390
+#define REG_HI3Q_TXBD_NUM_8822C 0x0392
+#define REG_HI4Q_TXBD_NUM_8822C 0x0394
+#define REG_HI5Q_TXBD_NUM_8822C 0x0396
+#define REG_HI6Q_TXBD_NUM_8822C 0x0398
+#define REG_HI7Q_TXBD_NUM_8822C 0x039A
+#define REG_TSFTIMER_HCI_8822C 0x039C
+#define REG_BD_RWPTR_CLR_8822C 0x039C
+#define REG_VOQ_TXBD_IDX_8822C 0x03A0
+#define REG_VIQ_TXBD_IDX_8822C 0x03A4
+#define REG_BEQ_TXBD_IDX_8822C 0x03A8
+#define REG_BKQ_TXBD_IDX_8822C 0x03AC
+#define REG_MGQ_TXBD_IDX_8822C 0x03B0
+#define REG_RXQ_RXBD_IDX_8822C 0x03B4
+#define REG_HI0Q_TXBD_IDX_8822C 0x03B8
+#define REG_HI1Q_TXBD_IDX_8822C 0x03BC
+#define REG_HI2Q_TXBD_IDX_8822C 0x03C0
+#define REG_HI3Q_TXBD_IDX_8822C 0x03C4
+#define REG_HI4Q_TXBD_IDX_8822C 0x03C8
+#define REG_HI5Q_TXBD_IDX_8822C 0x03CC
+#define REG_HI6Q_TXBD_IDX_8822C 0x03D0
+#define REG_HI7Q_TXBD_IDX_8822C 0x03D4
+#define REG_DBG_SEL_V1_8822C 0x03D8
+#define REG_PCIE_HRPWM1_V1_8822C 0x03D9
+#define REG_PCIE_HCPWM1_V1_8822C 0x03DA
+#define REG_PCIE_CTRL2_8822C 0x03DB
+#define REG_PCIE_HRPWM2_V1_8822C 0x03DC
+#define REG_PCIE_HCPWM2_V1_8822C 0x03DE
+#define REG_PCIE_H2C_MSG_V1_8822C 0x03E0
+#define REG_PCIE_C2H_MSG_V1_8822C 0x03E4
+#define REG_DBI_WDATA_V1_8822C 0x03E8
+#define REG_DBI_RDATA_V1_8822C 0x03EC
+#define REG_DBI_FLAG_V1_8822C 0x03F0
+#define REG_MDIO_V1_8822C 0x03F4
+#define REG_PCIE_MIX_CFG_8822C 0x03F8
+#define REG_HCI_MIX_CFG_8822C 0x03FC
+#define REG_STC_INT_CS_8822C 0x1300
+#define REG_ST_INT_CFG_8822C 0x1304
+#define REG_H2CQ_TXBD_DESA_8822C 0x1320
+#define REG_H2CQ_TXBD_NUM_8822C 0x1328
+#define REG_H2CQ_TXBD_IDX_8822C 0x132C
+#define REG_H2CQ_CSR_8822C 0x1330
+#define REG_CHANGE_PCIE_SPEED_8822C 0x1350
+#define REG_DEBUG_STATE1_8822C 0x1354
+#define REG_DEBUG_STATE2_8822C 0x1358
+#define REG_DEBUG_STATE3_8822C 0x135C
+#define REG_CHNL_DMA_CFG_V1_8822C 0x137C
+#define REG_PCIE_HISR0_V1_8822C 0x13B4
+#define REG_PCIE_HISR1_V1_8822C 0x13BC
+#define REG_PCIE_HISR2_V1_8822C 0x23B4
+#define REG_PCIE_HISR3_V1_8822C 0x23BC
+#define REG_Q0_INFO_8822C 0x0400
+#define REG_Q1_INFO_8822C 0x0404
+#define REG_Q2_INFO_8822C 0x0408
+#define REG_Q3_INFO_8822C 0x040C
+#define REG_MGQ_INFO_8822C 0x0410
+#define REG_HIQ_INFO_8822C 0x0414
+#define REG_BCNQ_INFO_8822C 0x0418
+#define REG_TXPKT_EMPTY_8822C 0x041A
+#define REG_CPU_MGQ_INFO_8822C 0x041C
+#define REG_FWHW_TXQ_CTRL_8822C 0x0420
+#define REG_DATAFB_SEL_8822C 0x0423
+#define REG_BCNQ_BDNY_V1_8822C 0x0424
+#define REG_LIFETIME_EN_8822C 0x0426
+#define REG_SPEC_SIFS_8822C 0x0428
+#define REG_RETRY_LIMIT_8822C 0x042A
+#define REG_TXBF_CTRL_8822C 0x042C
+#define REG_DARFRC_8822C 0x0430
+#define REG_DARFRCH_8822C 0x0434
+#define REG_RARFRC_8822C 0x0438
+#define REG_RARFRCH_8822C 0x043C
+#define REG_RRSR_8822C 0x0440
+#define REG_ARFR0_8822C 0x0444
+#define REG_ARFRH0_8822C 0x0448
+#define REG_ARFR1_V1_8822C 0x044C
+#define REG_ARFRH1_V1_8822C 0x0450
+#define REG_CCK_CHECK_8822C 0x0454
+#define REG_AMPDU_MAX_TIME_V1_8822C 0x0455
+#define REG_BCNQ1_BDNY_V1_8822C 0x0456
+#define REG_AMPDU_MAX_LENGTH_HT_8822C 0x0458
+#define REG_ACQ_STOP_8822C 0x045C
+#define REG_NDPA_RATE_8822C 0x045D
+#define REG_TX_HANG_CTRL_8822C 0x045E
+#define REG_NDPA_OPT_CTRL_8822C 0x045F
+#define REG_AMPDU_MAX_LENGTH_VHT_8822C 0x0460
+#define REG_RD_RESP_PKT_TH_8822C 0x0463
+#define REG_CMDQ_INFO_8822C 0x0464
+#define REG_Q4_INFO_8822C 0x0468
+#define REG_Q5_INFO_8822C 0x046C
+#define REG_Q6_INFO_8822C 0x0470
+#define REG_Q7_INFO_8822C 0x0474
+#define REG_WMAC_LBK_BUF_HD_V1_8822C 0x0478
+#define REG_MGQ_BDNY_V1_8822C 0x047A
+#define REG_TXRPT_CTRL_8822C 0x047C
+#define REG_INIRTS_RATE_SEL_8822C 0x0480
+#define REG_BASIC_CFEND_RATE_8822C 0x0481
+#define REG_STBC_CFEND_RATE_8822C 0x0482
+#define REG_DATA_SC_8822C 0x0483
+#define REG_MACID_SLEEP3_8822C 0x0484
+#define REG_MACID_SLEEP1_8822C 0x0488
+#define REG_ARFR2_V1_8822C 0x048C
+#define REG_ARFRH2_V1_8822C 0x0490
+#define REG_ARFR3_V1_8822C 0x0494
+#define REG_ARFRH3_V1_8822C 0x0498
+#define REG_ARFR4_8822C 0x049C
+#define REG_ARFRH4_8822C 0x04A0
+#define REG_ARFR5_8822C 0x04A4
+#define REG_ARFRH5_8822C 0x04A8
+#define REG_TXRPT_START_OFFSET_8822C 0x04AC
+#define REG_POWER_STAGE1_8822C 0x04B4
+#define REG_POWER_STAGE2_8822C 0x04B8
+#define REG_SW_AMPDU_BURST_MODE_CTRL_8822C 0x04BC
+#define REG_PKT_LIFE_TIME_8822C 0x04C0
+#define REG_STBC_SETTING_8822C 0x04C4
+#define REG_STBC_SETTING2_8822C 0x04C5
+#define REG_QUEUE_CTRL_8822C 0x04C6
+#define REG_SINGLE_AMPDU_CTRL_8822C 0x04C7
+#define REG_PROT_MODE_CTRL_8822C 0x04C8
+#define REG_BAR_MODE_CTRL_8822C 0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT_8822C 0x04CF
+#define REG_MACID_SLEEP2_8822C 0x04D0
+#define REG_MACID_SLEEP_8822C 0x04D4
+#define REG_HW_SEQ0_8822C 0x04D8
+#define REG_HW_SEQ1_8822C 0x04DA
+#define REG_HW_SEQ2_8822C 0x04DC
+#define REG_HW_SEQ3_8822C 0x04DE
+#define REG_NULL_PKT_STATUS_V1_8822C 0x04E0
+#define REG_PTCL_ERR_STATUS_8822C 0x04E2
+#define REG_NULL_PKT_STATUS_EXTEND_8822C 0x04E3
+#define REG_HQMGQ_DROP_8822C 0x04E4
+#define REG_PRECNT_CTRL_8822C 0x04E5
+#define REG_BT_POLLUTE_PKT_CNT_8822C 0x04E8
+#define REG_PTCL_DBG_8822C 0x04EC
+#define REG_CPUMGQ_TIMER_CTRL2_8822C 0x04F4
+#define REG_DUMMY_PAGE4_V1_8822C 0x04FC
+#define REG_MOREDATA_8822C 0x04FE
+#define REG_Q0_Q1_INFO_8822C 0x1400
+#define REG_Q2_Q3_INFO_8822C 0x1404
+#define REG_Q4_Q5_INFO_8822C 0x1408
+#define REG_Q6_Q7_INFO_8822C 0x140C
+#define REG_MGQ_HIQ_INFO_8822C 0x1410
+#define REG_CMDQ_BCNQ_INFO_8822C 0x1414
+#define REG_USEREG_SETTING_8822C 0x1420
+#define REG_AESIV_SETTING_8822C 0x1424
+#define REG_BF0_TIME_SETTING_8822C 0x1428
+#define REG_BF1_TIME_SETTING_8822C 0x142C
+#define REG_BF_TIMEOUT_EN_8822C 0x1430
+#define REG_MACID_RELEASE0_8822C 0x1434
+#define REG_MACID_RELEASE1_8822C 0x1438
+#define REG_MACID_RELEASE2_8822C 0x143C
+#define REG_MACID_RELEASE3_8822C 0x1440
+#define REG_MACID_RELEASE_SETTING_8822C 0x1444
+#define REG_FAST_EDCA_VOVI_SETTING_8822C 0x1448
+#define REG_FAST_EDCA_BEBK_SETTING_8822C 0x144C
+#define REG_MACID_DROP0_8822C 0x1450
+#define REG_MACID_DROP1_8822C 0x1454
+#define REG_MACID_DROP2_8822C 0x1458
+#define REG_MACID_DROP3_8822C 0x145C
+#define REG_R_MACID_RELEASE_SUCCESS_0_8822C 0x1460
+#define REG_R_MACID_RELEASE_SUCCESS_1_8822C 0x1464
+#define REG_R_MACID_RELEASE_SUCCESS_2_8822C 0x1468
+#define REG_R_MACID_RELEASE_SUCCESS_3_8822C 0x146C
+#define REG_MGQ_FIFO_WRITE_POINTER_8822C 0x1470
+#define REG_MGQ_FIFO_READ_POINTER_8822C 0x1472
+#define REG_MGQ_FIFO_ENABLE_8822C 0x1472
+#define REG_MGQ_FIFO_RELEASE_INT_MASK_8822C 0x1474
+#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8822C 0x1476
+#define REG_MGQ_FIFO_VALID_MAP_8822C 0x1478
+#define REG_MGQ_FIFO_LIFETIME_8822C 0x147A
+#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C 0x147C
+#define REG_SHCUT_SETTING_8822C 0x1480
+#define REG_SHCUT_LLC_ETH_TYPE0_8822C 0x1484
+#define REG_SHCUT_LLC_ETH_TYPE1_8822C 0x1488
+#define REG_SHCUT_LLC_OUI0_8822C 0x148C
+#define REG_SHCUT_LLC_OUI1_8822C 0x1490
+#define REG_SHCUT_LLC_OUI2_8822C 0x1494
+#define REG_MU_TX_CTL_8822C 0x14C0
+#define REG_MU_STA_GID_VLD_8822C 0x14C4
+#define REG_MU_STA_USER_POS_INFO_8822C 0x14C8
+#define REG_MU_STA_USER_POS_INFO_H_8822C 0x14CC
+#define REG_CHNL_INFO_CTRL_8822C 0x14D0
+#define REG_CHNL_IDLE_TIME_8822C 0x14D4
+#define REG_CHNL_BUSY_TIME_8822C 0x14D8
+#define REG_MU_TRX_DBG_CNT_V1_8822C 0x14DC
+#define REG_EDCA_VO_PARAM_8822C 0x0500
+#define REG_EDCA_VI_PARAM_8822C 0x0504
+#define REG_EDCA_BE_PARAM_8822C 0x0508
+#define REG_EDCA_BK_PARAM_8822C 0x050C
+#define REG_BCNTCFG_8822C 0x0510
+#define REG_PIFS_8822C 0x0512
+#define REG_RDG_PIFS_8822C 0x0513
+#define REG_SIFS_8822C 0x0514
+#define REG_TSFTR_SYN_OFFSET_8822C 0x0518
+#define REG_AGGR_BREAK_TIME_8822C 0x051A
+#define REG_SLOT_8822C 0x051B
+#define REG_NOA_ON_ERLY_TIME_8822C 0x051C
+#define REG_NOA_OFF_ERLY_TIME_8822C 0x051D
+#define REG_TX_PTCL_CTRL_8822C 0x0520
+#define REG_TXPAUSE_8822C 0x0522
+#define REG_DIS_TXREQ_CLR_8822C 0x0523
+#define REG_RD_CTRL_8822C 0x0524
+#define REG_MBSSID_CTRL_8822C 0x0526
+#define REG_P2PPS_CTRL_8822C 0x0527
+#define REG_PKT_LIFETIME_CTRL_8822C 0x0528
+#define REG_P2PPS_SPEC_STATE_8822C 0x052B
+#define REG_TXOP_LIMIT_CTRL_8822C 0x052C
+#define REG_BAR_TX_CTRL_8822C 0x0530
+#define REG_P2PON_DIS_TXTIME_8822C 0x0531
+#define REG_CCA_TXEN_CNT_8822C 0x0534
+#define REG_MAX_INTER_COLLISION_8822C 0x0538
+#define REG_MAX_INTER_COLLISION_CNT_8822C 0x053C
+#define REG_TBTT_PROHIBIT_8822C 0x0540
+#define REG_P2PPS_STATE_8822C 0x0543
+#define REG_RD_NAV_NXT_8822C 0x0544
+#define REG_NAV_PROT_LEN_8822C 0x0546
+#define REG_FTM_PTT_8822C 0x0548
+#define REG_FTM_TSF_8822C 0x054C
+#define REG_BCN_CTRL_8822C 0x0550
+#define REG_BCN_CTRL_CLINT0_8822C 0x0551
+#define REG_MBID_NUM_8822C 0x0552
+#define REG_DUAL_TSF_RST_8822C 0x0553
+#define REG_MBSSID_BCN_SPACE_8822C 0x0554
+#define REG_DRVERLYINT_8822C 0x0558
+#define REG_BCNDMATIM_8822C 0x0559
+#define REG_ATIMWND_8822C 0x055A
+#define REG_USTIME_TSF_8822C 0x055C
+#define REG_BCN_MAX_ERR_8822C 0x055D
+#define REG_RXTSF_OFFSET_CCK_8822C 0x055E
+#define REG_RXTSF_OFFSET_OFDM_8822C 0x055F
+#define REG_TSFTR_8822C 0x0560
+#define REG_TSFTR_1_8822C 0x0564
+#define REG_FREERUN_CNT_8822C 0x0568
+#define REG_FREERUN_CNT_1_8822C 0x056C
+#define REG_ATIMWND1_V1_8822C 0x0570
+#define REG_TBTT_PROHIBIT_INFRA_8822C 0x0571
+#define REG_CTWND_8822C 0x0572
+#define REG_BCNIVLCUNT_8822C 0x0573
+#define REG_BCNDROPCTRL_8822C 0x0574
+#define REG_HGQ_TIMEOUT_PERIOD_8822C 0x0575
+#define REG_TXCMD_TIMEOUT_PERIOD_8822C 0x0576
+#define REG_MISC_CTRL_8822C 0x0577
+#define REG_BCN_CTRL_CLINT1_8822C 0x0578
+#define REG_BCN_CTRL_CLINT2_8822C 0x0579
+#define REG_BCN_CTRL_CLINT3_8822C 0x057A
+#define REG_EXTEND_CTRL_8822C 0x057B
+#define REG_P2PPS1_SPEC_STATE_8822C 0x057C
+#define REG_P2PPS1_STATE_8822C 0x057D
+#define REG_P2PPS2_SPEC_STATE_8822C 0x057E
+#define REG_P2PPS2_STATE_8822C 0x057F
+#define REG_PS_TIMER0_8822C 0x0580
+#define REG_PS_TIMER1_8822C 0x0584
+#define REG_PS_TIMER2_8822C 0x0588
+#define REG_TBTT_CTN_AREA_8822C 0x058C
+#define REG_FORCE_BCN_IFS_8822C 0x058E
+#define REG_TXOP_MIN_8822C 0x0590
+#define REG_PRE_BKF_TIME_8822C 0x0592
+#define REG_CROSS_TXOP_CTRL_8822C 0x0593
+#define REG_RX_TBTT_SHIFT_V1_8822C 0x0598
+#define REG_ATIMWND2_8822C 0x05A0
+#define REG_ATIMWND3_8822C 0x05A1
+#define REG_ATIMWND4_8822C 0x05A2
+#define REG_ATIMWND5_8822C 0x05A3
+#define REG_ATIMWND6_8822C 0x05A4
+#define REG_ATIMWND7_8822C 0x05A5
+#define REG_ATIMUGT_8822C 0x05A6
+#define REG_HIQ_NO_LMT_EN_8822C 0x05A7
+#define REG_DTIM_COUNTER_ROOT_8822C 0x05A8
+#define REG_DTIM_COUNTER_VAP1_8822C 0x05A9
+#define REG_DTIM_COUNTER_VAP2_8822C 0x05AA
+#define REG_DTIM_COUNTER_VAP3_8822C 0x05AB
+#define REG_DTIM_COUNTER_VAP4_8822C 0x05AC
+#define REG_DTIM_COUNTER_VAP5_8822C 0x05AD
+#define REG_DTIM_COUNTER_VAP6_8822C 0x05AE
+#define REG_DTIM_COUNTER_VAP7_8822C 0x05AF
+#define REG_DIS_ATIM_8822C 0x05B0
+#define REG_EARLY_128US_8822C 0x05B1
+#define REG_P2PPS1_CTRL_8822C 0x05B2
+#define REG_P2PPS2_CTRL_8822C 0x05B3
+#define REG_TIMER0_SRC_SEL_8822C 0x05B4
+#define REG_NOA_UNIT_SEL_8822C 0x05B5
+#define REG_P2POFF_DIS_TXTIME_8822C 0x05B7
+#define REG_MBSSID_BCN_SPACE2_8822C 0x05B8
+#define REG_MBSSID_BCN_SPACE3_8822C 0x05BC
+#define REG_ACMHWCTRL_8822C 0x05C0
+#define REG_ACMRSTCTRL_8822C 0x05C1
+#define REG_ACMAVG_8822C 0x05C2
+#define REG_VO_ADMTIME_8822C 0x05C4
+#define REG_VI_ADMTIME_8822C 0x05C6
+#define REG_BE_ADMTIME_8822C 0x05C8
+#define REG_MAC_HEADER_NAV_OFFSET_8822C 0x05CA
+#define REG_DIS_NDPA_NAV_CHECK_8822C 0x05CB
+#define REG_EDCA_RANDOM_GEN_8822C 0x05CC
+#define REG_TXCMD_NOA_SEL_8822C 0x05CF
+#define REG_32K_CLK_SEL_8822C 0x05D0
+#define REG_EARLYINT_ADJUST_8822C 0x05D4
+#define REG_BCNERR_CNT_8822C 0x05D8
+#define REG_BCNERR_CNT_2_8822C 0x05DC
+#define REG_NOA_PARAM_8822C 0x05E0
+#define REG_NOA_PARAM_1_8822C 0x05E4
+#define REG_NOA_PARAM_2_8822C 0x05E8
+#define REG_NOA_PARAM_3_8822C 0x05EC
+#define REG_P2P_RST_8822C 0x05F0
+#define REG_SCHEDULER_RST_8822C 0x05F1
+#define REG_SCH_DBG_VALUE_8822C 0x05F4
+#define REG_SCH_TXCMD_8822C 0x05F8
+#define REG_PAGE5_DUMMY_8822C 0x05FC
+#define REG_CPUMGQ_TX_TIMER_8822C 0x1500
+#define REG_PS_TIMER_A_8822C 0x1504
+#define REG_PS_TIMER_B_8822C 0x1508
+#define REG_PS_TIMER_C_8822C 0x150C
+#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822C 0x1510
+#define REG_CPUMGQ_TX_TIMER_EARLY_8822C 0x1514
+#define REG_PS_TIMER_A_EARLY_8822C 0x1515
+#define REG_PS_TIMER_B_EARLY_8822C 0x1516
+#define REG_PS_TIMER_C_EARLY_8822C 0x1517
+#define REG_CPUMGQ_PARAMETER_8822C 0x1518
+#define REG_TSF_SYNC_ADJ_8822C 0x1520
+#define REG_TSF_ADJ_VLAUE_8822C 0x1524
+#define REG_TSF_ADJ_VLAUE_2_8822C 0x1528
+#define REG_P2PPS_HW_AUTO_PAUSE_CTRL_8822C 0x156C
+#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8822C 0x1570
+#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8822C 0x1574
+#define REG_WMAC_CR_8822C 0x0600
+#define REG_WMAC_FWPKT_CR_8822C 0x0601
+#define REG_FW_STS_FILTER_8822C 0x0602
+#define REG_TCR_8822C 0x0604
+#define REG_RCR_8822C 0x0608
+#define REG_RX_PKT_LIMIT_8822C 0x060C
+#define REG_RX_DLK_TIME_8822C 0x060D
+#define REG_RX_DRVINFO_SZ_8822C 0x060F
+#define REG_MACID_8822C 0x0610
+#define REG_MACID_H_8822C 0x0614
+#define REG_BSSID_8822C 0x0618
+#define REG_BSSID_H_8822C 0x061C
+#define REG_MAR_8822C 0x0620
+#define REG_MAR_H_8822C 0x0624
+#define REG_MBIDCAMCFG_1_8822C 0x0628
+#define REG_MBIDCAMCFG_2_8822C 0x062C
+#define REG_WMAC_TCR_TSFT_OFS_8822C 0x0630
+#define REG_UDF_THSD_8822C 0x0632
+#define REG_ZLD_NUM_8822C 0x0633
+#define REG_STMP_THSD_8822C 0x0634
+#define REG_WMAC_TXTIMEOUT_8822C 0x0635
+#define REG_USTIME_EDCA_8822C 0x0638
+#define REG_ACKTO_CCK_8822C 0x0639
+#define REG_MAC_SPEC_SIFS_8822C 0x063A
+#define REG_RESP_SIFS_CCK_8822C 0x063C
+#define REG_RESP_SIFS_OFDM_8822C 0x063E
+#define REG_ACKTO_8822C 0x0640
+#define REG_CTS2TO_8822C 0x0641
+#define REG_EIFS_8822C 0x0642
+#define REG_RPFM_MAP0_8822C 0x0644
+#define REG_RPFM_MAP1_V1_8822C 0x0646
+#define REG_RPFM_CAM_CMD_8822C 0x0648
+#define REG_RPFM_CAM_RWD_8822C 0x064C
+#define REG_NAV_CTRL_8822C 0x0650
+#define REG_BACAMCMD_8822C 0x0654
+#define REG_BACAMCONTENT_8822C 0x0658
+#define REG_BACAMCONTENT_H_8822C 0x065C
+#define REG_LBDLY_8822C 0x0660
+#define REG_WMAC_BACAM_RPMEN_8822C 0x0661
+#define REG_TX_RX_8822C 0x0662
+#define REG_WMAC_BITMAP_CTL_8822C 0x0663
+#define REG_RXERR_RPT_8822C 0x0664
+#define REG_WMAC_TRXPTCL_CTL_8822C 0x0668
+#define REG_WMAC_TRXPTCL_CTL_H_8822C 0x066C
+#define REG_CAMCMD_8822C 0x0670
+#define REG_CAMWRITE_8822C 0x0674
+#define REG_CAMREAD_8822C 0x0678
+#define REG_CAMDBG_8822C 0x067C
+#define REG_SECCFG_8822C 0x0680
+#define REG_RXFILTER_CATEGORY_1_8822C 0x0682
+#define REG_RXFILTER_ACTION_1_8822C 0x0683
+#define REG_RXFILTER_CATEGORY_2_8822C 0x0684
+#define REG_RXFILTER_ACTION_2_8822C 0x0685
+#define REG_RXFILTER_CATEGORY_3_8822C 0x0686
+#define REG_RXFILTER_ACTION_3_8822C 0x0687
+#define REG_RXFLTMAP3_8822C 0x0688
+#define REG_RXFLTMAP4_8822C 0x068A
+#define REG_RXFLTMAP5_8822C 0x068C
+#define REG_RXFLTMAP6_8822C 0x068E
+#define REG_WOW_CTRL_8822C 0x0690
+#define REG_NAN_RX_TSF_FILTER_8822C 0x0691
+#define REG_PS_RX_INFO_8822C 0x0692
+#define REG_WMMPS_UAPSD_TID_8822C 0x0693
+#define REG_LPNAV_CTRL_8822C 0x0694
+#define REG_WKFMCAM_CMD_8822C 0x0698
+#define REG_WKFMCAM_RWD_8822C 0x069C
+#define REG_RXFLTMAP0_8822C 0x06A0
+#define REG_RXFLTMAP1_8822C 0x06A2
+#define REG_RXFLTMAP2_8822C 0x06A4
+#define REG_BCN_PSR_RPT_8822C 0x06A8
+#define REG_FLC_RPC_8822C 0x06AC
+#define REG_FLC_RPCT_8822C 0x06AD
+#define REG_FLC_PTS_8822C 0x06AE
+#define REG_FLC_TRPC_8822C 0x06AF
+#define REG_RXPKTMON_CTRL_8822C 0x06B0
+#define REG_STATE_MON_8822C 0x06B4
+#define REG_ERROR_MON_8822C 0x06B8
+#define REG_SEARCH_MACID_8822C 0x06BC
+#define REG_BT_COEX_TABLE_8822C 0x06C0
+#define REG_BT_COEX_TABLE2_8822C 0x06C4
+#define REG_BT_COEX_BREAK_TABLE_8822C 0x06C8
+#define REG_BT_COEX_TABLE_H_8822C 0x06CC
+#define REG_RXCMD_0_8822C 0x06D0
+#define REG_RXCMD_1_8822C 0x06D4
+#define REG_WMAC_RESP_TXINFO_8822C 0x06D8
+#define REG_BBPSF_CTRL_8822C 0x06DC
+#define REG_P2P_RX_BCN_NOA_8822C 0x06E0
+#define REG_ASSOCIATED_BFMER0_INFO_8822C 0x06E4
+#define REG_ASSOCIATED_BFMER0_INFO_H_8822C 0x06E8
+#define REG_ASSOCIATED_BFMER1_INFO_8822C 0x06EC
+#define REG_ASSOCIATED_BFMER1_INFO_H_8822C 0x06F0
+#define REG_TX_CSI_RPT_PARAM_BW20_8822C 0x06F4
+#define REG_TX_CSI_RPT_PARAM_BW40_8822C 0x06F8
+#define REG_CSI_PTR_8822C 0x06FC
+#define REG_BCN_PSR_RPT2_8822C 0x1600
+#define REG_BCN_PSR_RPT3_8822C 0x1604
+#define REG_BCN_PSR_RPT4_8822C 0x1608
+#define REG_A1_ADDR_MASK_8822C 0x160C
+#define REG_RXPSF_CTRL_8822C 0x1610
+#define REG_RXPSF_TYPE_CTRL_8822C 0x1614
+#define REG_CAM_ACCESS_CTRL_8822C 0x1618
+#define REG_HT_SND_REF_RATE_8822C 0x161C
+#define REG_MACID2_8822C 0x1620
+#define REG_MACID2_H_8822C 0x1624
+#define REG_BSSID2_8822C 0x1628
+#define REG_BSSID2_H_8822C 0x162C
+#define REG_MACID3_8822C 0x1630
+#define REG_MACID3_H_8822C 0x1634
+#define REG_BSSID3_8822C 0x1638
+#define REG_BSSID3_H_8822C 0x163C
+#define REG_MACID4_8822C 0x1640
+#define REG_MACID4_H_8822C 0x1644
+#define REG_BSSID4_8822C 0x1648
+#define REG_BSSID4_H_8822C 0x164C
+#define REG_NOA_REPORT_8822C 0x1650
+#define REG_NOA_REPORT_1_8822C 0x1654
+#define REG_NOA_REPORT_2_8822C 0x1658
+#define REG_NOA_REPORT_3_8822C 0x165C
+#define REG_PWRBIT_SETTING_8822C 0x1660
+#define REG_GENERAL_OPTION_8822C 0x1664
+#define REG_CSI_RRSR_8822C 0x1678
+#define REG_MU_BF_OPTION_8822C 0x167C
+#define REG_WMAC_PAUSE_BB_CLR_TH_8822C 0x167D
+#define REG__WMAC_MULBK_BUF_8822C 0x167E
+#define REG_WMAC_MU_OPTION_8822C 0x167F
+#define REG_WMAC_MU_BF_CTL_8822C 0x1680
+#define REG_WMAC_MU_BFRPT_PARA_8822C 0x1682
+#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8822C 0x1684
+#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8822C 0x1686
+#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8822C 0x1688
+#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8822C 0x168A
+#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8822C 0x168C
+#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8822C 0x168E
+#define REG_WMAC_BB_STOP_RX_COUNTER_8822C 0x1690
+#define REG_WMAC_PLCP_MONITOR_8822C 0x1694
+#define REG_WMAC_PLCP_MONITOR_MUTX_8822C 0x1698
+#define REG_WMAC_CSIDMA_CFG_8822C 0x169C
+#define REG_TRANSMIT_ADDRSS_0_8822C 0x16A0
+#define REG_TRANSMIT_ADDRSS_0_H_8822C 0x16A4
+#define REG_TRANSMIT_ADDRSS_1_8822C 0x16A8
+#define REG_TRANSMIT_ADDRSS_1_H_8822C 0x16AC
+#define REG_TRANSMIT_ADDRSS_2_8822C 0x16B0
+#define REG_TRANSMIT_ADDRSS_2_H_8822C 0x16B4
+#define REG_TRANSMIT_ADDRSS_3_8822C 0x16B8
+#define REG_TRANSMIT_ADDRSS_3_H_8822C 0x16BC
+#define REG_TRANSMIT_ADDRSS_4_8822C 0x16C0
+#define REG_TRANSMIT_ADDRSS_4_H_8822C 0x16C4
+#define REG_MACID1_8822C 0x0700
+#define REG_MACID1_1_8822C 0x0704
+#define REG_BSSID1_8822C 0x0708
+#define REG_BSSID1_1_8822C 0x070C
+#define REG_BCN_PSR_RPT1_8822C 0x0710
+#define REG_ASSOCIATED_BFMEE_SEL_8822C 0x0714
+#define REG_SND_PTCL_CTRL_8822C 0x0718
+#define REG_RX_CSI_RPT_INFO_8822C 0x071C
+#define REG_NS_ARP_CTRL_8822C 0x0720
+#define REG_NS_ARP_INFO_8822C 0x0724
+#define REG_BEAMFORMING_INFO_NSARP_V1_8822C 0x0728
+#define REG_BEAMFORMING_INFO_NSARP_8822C 0x072C
+#define REG_IPV6_8822C 0x0730
+#define REG_IPV6_1_8822C 0x0734
+#define REG_IPV6_2_8822C 0x0738
+#define REG_IPV6_3_8822C 0x073C
+#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822C 0x0750
+#define REG_WMAC_SWAES_DIO_B63_B32_8822C 0x0754
+#define REG_WMAC_SWAES_DIO_B95_B64_8822C 0x0758
+#define REG_WMAC_SWAES_DIO_B127_B96_8822C 0x075C
+#define REG_WMAC_SWAES_CFG_8822C 0x0760
+#define REG_BT_COEX_V2_8822C 0x0762
+#define REG_BT_COEX_8822C 0x0764
+#define REG_WLAN_ACT_MASK_CTRL_8822C 0x0768
+#define REG_WLAN_ACT_MASK_CTRL_1_8822C 0x076C
+#define REG_BT_COEX_ENHANCED_INTR_CTRL_8822C 0x076E
+#define REG_BT_ACT_STATISTICS_8822C 0x0770
+#define REG_BT_ACT_STATISTICS_1_8822C 0x0774
+#define REG_BT_STATISTICS_CONTROL_REGISTER_8822C 0x0778
+#define REG_BT_STATUS_REPORT_REGISTER_8822C 0x077C
+#define REG_BT_INTERRUPT_CONTROL_REGISTER_8822C 0x0780
+#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822C 0x0784
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822C 0x0785
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8822C 0x0788
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8822C 0x078C
+#define REG_BT_INTERRUPT_STATUS_REGISTER_8822C 0x078F
+#define REG_BT_TDMA_TIME_REGISTER_8822C 0x0790
+#define REG_BT_ACT_REGISTER_8822C 0x0794
+#define REG_OBFF_CTRL_BASIC_8822C 0x0798
+#define REG_OBFF_CTRL2_TIMER_8822C 0x079C
+#define REG_LTR_CTRL_BASIC_8822C 0x07A0
+#define REG_LTR_CTRL2_TIMER_THRESHOLD_8822C 0x07A4
+#define REG_LTR_IDLE_LATENCY_V1_8822C 0x07A8
+#define REG_LTR_ACTIVE_LATENCY_V1_8822C 0x07AC
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822C 0x07B0
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8822C 0x07B4
+#define REG_WMAC_PKTCNT_RWD_8822C 0x07B8
+#define REG_WMAC_PKTCNT_CTRL_8822C 0x07BC
+#define REG_IQ_DUMP_8822C 0x07C0
+#define REG_IQ_DUMP_1_8822C 0x07C4
+#define REG_IQ_DUMP_2_8822C 0x07C8
+#define REG_WMAC_FTM_CTL_8822C 0x07CC
+#define REG_WMAC_IQ_MDPK_FUNC_8822C 0x07CE
+#define REG_WMAC_OPTION_FUNCTION_8822C 0x07D0
+#define REG_WMAC_OPTION_FUNCTION_1_8822C 0x07D4
+#define REG_WMAC_OPTION_FUNCTION_2_8822C 0x07D8
+#define REG_RX_FILTER_FUNCTION_8822C 0x07DA
+#define REG_NDP_SIG_8822C 0x07E0
+#define REG_TXCMD_INFO_FOR_RSP_PKT_8822C 0x07E4
+#define REG_TXCMD_INFO_FOR_RSP_PKT_1_8822C 0x07E8
+#define REG_WSEC_OPTION_8822C 0x07EC
+#define REG_RTS_ADDRESS_0_8822C 0x07F0
+#define REG_RTS_ADDRESS_0_1_8822C 0x07F4
+#define REG_RTS_ADDRESS_1_8822C 0x07F8
+#define REG_RTS_ADDRESS_1_1_8822C 0x07FC
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822C 0x1700
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822C 0x1704
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822C 0x1708
+#define REG_SDIO_TX_CTRL_8822C 0x10250000
+#define REG_SDIO_CMD11_VOL_SWITCH_8822C 0x10250004
+#define REG_SDIO_DRIVING_8822C 0x10250006
+#define REG_SDIO_MONITOR_8822C 0x10250008
+#define REG_SDIO_MONITOR_2_8822C 0x1025000C
+#define REG_SDIO_HIMR_8822C 0x10250014
+#define REG_SDIO_HISR_8822C 0x10250018
+#define REG_SDIO_RX_REQ_LEN_8822C 0x1025001C
+#define REG_SDIO_FREE_TXPG_SEQ_V1_8822C 0x1025001F
+#define REG_SDIO_FREE_TXPG_8822C 0x10250020
+#define REG_SDIO_FREE_TXPG2_8822C 0x10250024
+#define REG_SDIO_OQT_FREE_TXPG_V1_8822C 0x10250028
+#define REG_SDIO_TXPKT_EMPTY_8822C 0x1025002C
+#define REG_SDIO_HTSFR_INFO_8822C 0x10250030
+#define REG_SDIO_HCPWM1_V2_8822C 0x10250038
+#define REG_SDIO_HCPWM2_V2_8822C 0x1025003A
+#define REG_SDIO_INDIRECT_REG_CFG_8822C 0x10250040
+#define REG_SDIO_INDIRECT_REG_DATA_8822C 0x10250044
+#define REG_SDIO_H2C_8822C 0x10250060
+#define REG_SDIO_C2H_8822C 0x10250064
+#define REG_SDIO_HRPWM1_8822C 0x10250080
+#define REG_SDIO_HRPWM2_8822C 0x10250082
+#define REG_SDIO_HPS_CLKR_8822C 0x10250084
+#define REG_SDIO_BUS_CTRL_8822C 0x10250085
+#define REG_SDIO_HSUS_CTRL_8822C 0x10250086
+#define REG_SDIO_RESPONSE_TIMER_8822C 0x10250088
+#define REG_SDIO_CMD_CRC_8822C 0x1025008A
+#define REG_SDIO_HSISR_8822C 0x10250090
+#define REG_SDIO_HSIMR_8822C 0x10250091
+#define REG_SDIO_DIOERR_RPT_8822C 0x102500C0
+#define REG_SDIO_CMD_ERRCNT_8822C 0x102500C2
+#define REG_SDIO_DATA_ERRCNT_8822C 0x102500C3
+#define REG_SDIO_CMD_ERR_CONTENT_8822C 0x102500C4
+#define REG_SDIO_CRC_ERR_IDX_8822C 0x102500C9
+#define REG_SDIO_DATA_CRC_8822C 0x102500CA
+#define REG_SDIO_TRANS_FIFO_STATUS_8822C 0x102500CC
+
+#endif

hal/halmac/halmac_rx_bd_nic.h

@@ -0,0 +1,40 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_RX_BD_NIC_H_
+#define _HALMAC_RX_BD_NIC_H_
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+	HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*TXBD_DW0*/
+
+#define GET_RX_BD_RXFAIL(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 31, 1)
+#define GET_RX_BD_TOTALRXPKTSIZE(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 16, 13)
+#define GET_RX_BD_RXTAG(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 16, 13)
+#define GET_RX_BD_FS(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 15, 1)
+#define GET_RX_BD_LS(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 14, 1)
+#define GET_RX_BD_RXBUFFSIZE(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 0, 14)
+
+/*TXBD_DW1*/
+
+#define GET_RX_BD_PHYSICAL_ADDR_LOW(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x04, 0, 32)
+
+/*TXBD_DW2*/
+
+#define GET_RX_BD_PHYSICAL_ADDR_HIGH(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x08, 0, 32)
+
+#endif
+
+#endif

hal/halmac/halmac_rx_desc_ap.h

@@ -0,0 +1,614 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_RX_DESC_AP_H_
+#define _HALMAC_RX_DESC_AP_H_
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EOR(rxdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \
+			      30)
+#define GET_RX_DESC_PHYPKTIDC(rxdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \
+			      28)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_EVT_PKT(rxdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \
+			      28)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_SWDEC(rxdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \
+			      27)
+#define GET_RX_DESC_PHYST(rxdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \
+			      26)
+#define GET_RX_DESC_SHIFT(rxdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x3,  \
+			      24)
+#define GET_RX_DESC_QOS(rxdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \
+			      23)
+#define GET_RX_DESC_SECURITY(rxdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x7,  \
+			      20)
+#define GET_RX_DESC_DRV_INFO_SIZE(rxdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0xf,  \
+			      16)
+#define GET_RX_DESC_ICV_ERR(rxdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \
+			      15)
+#define GET_RX_DESC_CRC32(rxdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1,  \
+			      14)
+#define GET_RX_DESC_PKT_LEN(rxdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0,       \
+			      0x3fff, 0)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC(rxdesc)                                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      31)
+#define GET_RX_DESC_MC(rxdesc)                                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      30)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_TY_PE(rxdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x3,  \
+			      28)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_TYPE(rxdesc)                                               \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x3,  \
+			      28)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_MF(rxdesc)                                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      27)
+#define GET_RX_DESC_MD(rxdesc)                                                 \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      26)
+#define GET_RX_DESC_PWR(rxdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      25)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PAM(rxdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_A1_MATCH(rxdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_CHK_VLD(rxdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      23)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_TCP_CHKSUM_VLD(rxdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      23)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      22)
+#define GET_RX_DESC_RX_IPV(rxdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      21)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_CHKERR(rxdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      20)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_TCP_CHKSUM_ERR(rxdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      20)
+#define GET_RX_DESC_PHY_PKT_IDC(rxdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      17)
+#define GET_RX_DESC_FW_FIFO_FULL(rxdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PAGGR(rxdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      15)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_AMPDU(rxdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      15)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RXID_MATCH(rxdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      14)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_RXCMD_IDC(rxdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      14)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_AMSDU(rxdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      13)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_MACID_VLD(rxdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1,  \
+			      12)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_TID(rxdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0xf, 8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_MACID(rxdesc)                                              \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x7f, \
+			      0)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK(rxdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \
+			      31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_AMSDU_CUT(rxdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \
+			      31)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PPDU_CNT(rxdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x3,  \
+			      29)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_C2H(rxdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \
+			      28)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_HWRSVD_V1(rxdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x7,  \
+			      25)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_HWRSVD(rxdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0xf,  \
+			      24)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_RXMAGPKT(rxdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \
+			      24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_WLANHD_IV_LEN(rxdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x3f, \
+			      18)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_LAST_MSDU(rxdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \
+			      17)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_STATISTICS(rxdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \
+			      17)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_IS_QOS(rxdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \
+			      16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_EXT_SEC_TYPE(rxdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1,  \
+			      16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_FRAG(rxdesc)                                               \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0xf,  \
+			      12)
+#define GET_RX_DESC_SEQ(rxdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2,       \
+			      0xfff, 0)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE(rxdesc)                                         \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \
+			      31)
+#define GET_RX_DESC_UNICAST_WAKE(rxdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \
+			      30)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_MATCH(rxdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \
+			      29)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_WAKE(rxdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \
+			      29)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \
+			      28)
+#define GET_RX_DESC_RXPAYLOAD_ID(rxdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0xf,  \
+			      24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_DMA_AGG_NUM(rxdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0xff, \
+			      16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_BSSID_FIT_1_0(rxdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x3,  \
+			      12)
+#define GET_RX_DESC_EOSP(rxdesc)                                               \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \
+			      11)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_BSSID_FIT(rxdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1f, \
+			      11)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_HTC(rxdesc)                                                \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1,  \
+			      10)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_AMPDU_END_PKT(rxdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, 9)
+#define GET_RX_DESC_ADDRESS_CAM_VLD(rxdesc)                                    \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, 8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_BSSID_FIT_4_2(rxdesc)                                      \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x7, 7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_EOSP_V1(rxdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, 7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_RATE(rxdesc)                                            \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x7f, \
+			      0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT(rxdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1f, \
+			      24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_ADDRESS_CAM(rxdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \
+			      24)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_A1_FIT_A1(rxdesc)                                          \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \
+			      24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_MACID_VLD_V1(rxdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1,  \
+			      23)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_MACID_RPT_BUFF(rxdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \
+			      17)
+#define GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1,  \
+			      16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_MACID_V1(rxdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \
+			      15)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_SCRAMBLER(rxdesc)                                       \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \
+			      9)
+#define GET_RX_DESC_RX_EOF(rxdesc)                                             \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_FC_POWER(rxdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 7)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc)                                  \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_SWPS_RPT(rxdesc)                                           \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_IDX(rxdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \
+			      0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_IDX_V1(rxdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1f, \
+			      0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_IDX_V2(rxdesc)                                     \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1f, \
+			      0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL(rxdesc)                                               \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword5,       \
+			      0xffffffff, 0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_FREERUN_CNT(rxdesc)                                        \
+	HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword5,       \
+			      0xffffffff, 0)
+
+#endif
+
+#endif

hal/halmac/halmac_rx_desc_chip.h

@@ -0,0 +1,611 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_RX_DESC_CHIP_H_
+#define _HALMAC_RX_DESC_CHIP_H_
+#if (HALMAC_8814A_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EOR_8814A(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8814A(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8814A(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8814A(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8814A(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8814A(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8814A(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8814A(rxdesc)                                \
+	GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8814A(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8814A(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8814A(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC_8814A(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8814A(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8814A(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8814A(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8814A(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8814A(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8814A(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8814A(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8814A(rxdesc)                                \
+	GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8814A(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8814A(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8814A(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8814A(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8814A(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8814A(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8814A(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8814A(rxdesc) GET_RX_DESC_MACID(rxdesc)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK_8814A(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_C2H_8814A(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8814A(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8814A(rxdesc)                                \
+	GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8814A(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8814A(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8814A(rxdesc) GET_RX_DESC_SEQ(rxdesc)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE_8814A(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8814A(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8814A(rxdesc)                                \
+	GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8814A(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8814A(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8814A(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8814A(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8814A(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8814A(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT_8814A(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8814A(rxdesc)                               \
+	GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8814A(rxdesc)                               \
+	GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8814A(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8814A(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8814A(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL_8814A(rxdesc) GET_RX_DESC_TSFL(rxdesc)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EOR_8822B(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8822B(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8822B(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8822B(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8822B(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8822B(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8822B(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8822B(rxdesc)                                \
+	GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8822B(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8822B(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8822B(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC_8822B(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8822B(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8822B(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8822B(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8822B(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8822B(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8822B(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8822B(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8822B(rxdesc)                                \
+	GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8822B(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8822B(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8822B(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8822B(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8822B(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8822B(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8822B(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8822B(rxdesc) GET_RX_DESC_MACID(rxdesc)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK_8822B(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_PPDU_CNT_8822B(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
+#define GET_RX_DESC_C2H_8822B(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8822B(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8822B(rxdesc)                                \
+	GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8822B(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8822B(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8822B(rxdesc) GET_RX_DESC_SEQ(rxdesc)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE_8822B(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8822B(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8822B(rxdesc)                                \
+	GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_MATCH_8822B(rxdesc)                              \
+	GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_ID_8822B(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8822B(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8822B(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8822B(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8822B(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8822B(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8822B(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT_8822B(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8822B(rxdesc)                               \
+	GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8822B(rxdesc)                               \
+	GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8822B(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8822B(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8822B(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL_8822B(rxdesc) GET_RX_DESC_TSFL(rxdesc)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EOR_8197F(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8197F(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8197F(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8197F(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8197F(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8197F(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8197F(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8197F(rxdesc)                                \
+	GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8197F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8197F(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8197F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC_8197F(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8197F(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8197F(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8197F(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8197F(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8197F(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8197F(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8197F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8197F(rxdesc)                                \
+	GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8197F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8197F(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8197F(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8197F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8197F(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8197F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8197F(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8197F(rxdesc) GET_RX_DESC_MACID(rxdesc)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK_8197F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_C2H_8197F(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8197F(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8197F(rxdesc)                                \
+	GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8197F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8197F(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8197F(rxdesc) GET_RX_DESC_SEQ(rxdesc)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE_8197F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8197F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8197F(rxdesc)                                \
+	GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8197F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8197F(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8197F(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8197F(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8197F(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8197F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT_8197F(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8197F(rxdesc)                               \
+	GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8197F(rxdesc)                               \
+	GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8197F(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8197F(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_FC_POWER_8197F(rxdesc) GET_RX_DESC_FC_POWER(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8197F(rxdesc) GET_RX_DESC_PATTERN_IDX_V1(rxdesc)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL_8197F(rxdesc) GET_RX_DESC_TSFL(rxdesc)
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EOR_8821C(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8821C(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8821C(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8821C(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8821C(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8821C(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8821C(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8821C(rxdesc)                                \
+	GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8821C(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8821C(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8821C(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC_8821C(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8821C(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8821C(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8821C(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8821C(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8821C(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8821C(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8821C(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8821C(rxdesc)                                \
+	GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8821C(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8821C(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8821C(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8821C(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8821C(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8821C(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8821C(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8821C(rxdesc) GET_RX_DESC_MACID(rxdesc)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK_8821C(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_PPDU_CNT_8821C(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
+#define GET_RX_DESC_C2H_8821C(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8821C(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8821C(rxdesc)                                \
+	GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8821C(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8821C(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8821C(rxdesc) GET_RX_DESC_SEQ(rxdesc)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE_8821C(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8821C(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8821C(rxdesc)                                \
+	GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_MATCH_8821C(rxdesc)                              \
+	GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_ID_8821C(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8821C(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8821C(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8821C(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8821C(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8821C(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8821C(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT_8821C(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8821C(rxdesc)                               \
+	GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8821C(rxdesc)                               \
+	GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8821C(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8821C(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8821C(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL_8821C(rxdesc) GET_RX_DESC_TSFL(rxdesc)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EVT_PKT_8814B(rxdesc) GET_RX_DESC_EVT_PKT(rxdesc)
+#define GET_RX_DESC_SWDEC_8814B(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8814B(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8814B(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8814B(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8814B(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8814B(rxdesc)                                \
+	GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8814B(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8814B(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8814B(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC_8814B(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8814B(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TYPE_8814B(rxdesc) GET_RX_DESC_TYPE(rxdesc)
+#define GET_RX_DESC_MF_8814B(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8814B(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8814B(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_A1_MATCH_8814B(rxdesc) GET_RX_DESC_A1_MATCH(rxdesc)
+#define GET_RX_DESC_TCP_CHKSUM_VLD_8814B(rxdesc)                               \
+	GET_RX_DESC_TCP_CHKSUM_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8814B(rxdesc)                                \
+	GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8814B(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_TCP_CHKSUM_ERR_8814B(rxdesc)                               \
+	GET_RX_DESC_TCP_CHKSUM_ERR(rxdesc)
+#define GET_RX_DESC_PHY_PKT_IDC_8814B(rxdesc) GET_RX_DESC_PHY_PKT_IDC(rxdesc)
+#define GET_RX_DESC_FW_FIFO_FULL_8814B(rxdesc) GET_RX_DESC_FW_FIFO_FULL(rxdesc)
+#define GET_RX_DESC_AMPDU_8814B(rxdesc) GET_RX_DESC_AMPDU(rxdesc)
+#define GET_RX_DESC_RXCMD_IDC_8814B(rxdesc) GET_RX_DESC_RXCMD_IDC(rxdesc)
+#define GET_RX_DESC_AMSDU_8814B(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_TID_8814B(rxdesc) GET_RX_DESC_TID(rxdesc)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_AMSDU_CUT_8814B(rxdesc) GET_RX_DESC_AMSDU_CUT(rxdesc)
+#define GET_RX_DESC_PPDU_CNT_8814B(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
+#define GET_RX_DESC_C2H_8814B(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8814B(rxdesc)                                \
+	GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_LAST_MSDU_8814B(rxdesc) GET_RX_DESC_LAST_MSDU(rxdesc)
+#define GET_RX_DESC_EXT_SEC_TYPE_8814B(rxdesc) GET_RX_DESC_EXT_SEC_TYPE(rxdesc)
+#define GET_RX_DESC_FRAG_8814B(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8814B(rxdesc) GET_RX_DESC_SEQ(rxdesc)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE_8814B(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8814B(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_WAKE_8814B(rxdesc) GET_RX_DESC_PATTERN_WAKE(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_MATCH_8814B(rxdesc)                              \
+	GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_ID_8814B(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8814B(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_8814B(rxdesc) GET_RX_DESC_BSSID_FIT(rxdesc)
+#define GET_RX_DESC_HTC_8814B(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_AMPDU_END_PKT_8814B(rxdesc)                                \
+	GET_RX_DESC_AMPDU_END_PKT(rxdesc)
+#define GET_RX_DESC_ADDRESS_CAM_VLD_8814B(rxdesc)                              \
+	GET_RX_DESC_ADDRESS_CAM_VLD(rxdesc)
+#define GET_RX_DESC_EOSP_8814B(rxdesc) GET_RX_DESC_EOSP_V1(rxdesc)
+#define GET_RX_DESC_RX_RATE_8814B(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_ADDRESS_CAM_8814B(rxdesc) GET_RX_DESC_ADDRESS_CAM(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8814B(rxdesc) GET_RX_DESC_MACID_VLD_V1(rxdesc)
+#define GET_RX_DESC_MACID_8814B(rxdesc) GET_RX_DESC_MACID_V1(rxdesc)
+#define GET_RX_DESC_SWPS_RPT_8814B(rxdesc) GET_RX_DESC_SWPS_RPT(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8814B(rxdesc) GET_RX_DESC_PATTERN_IDX_V2(rxdesc)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_FREERUN_CNT_8814B(rxdesc) GET_RX_DESC_FREERUN_CNT(rxdesc)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EOR_8198F(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8198F(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8198F(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8198F(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8198F(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8198F(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8198F(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8198F(rxdesc)                                \
+	GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8198F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8198F(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8198F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC_8198F(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8198F(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8198F(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8198F(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8198F(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8198F(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8198F(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8198F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8198F(rxdesc)                                \
+	GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8198F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8198F(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8198F(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8198F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8198F(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8198F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8198F(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8198F(rxdesc) GET_RX_DESC_MACID(rxdesc)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK_8198F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_PPDU_CNT_8198F(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
+#define GET_RX_DESC_C2H_8198F(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8198F(rxdesc) GET_RX_DESC_HWRSVD_V1(rxdesc)
+#define GET_RX_DESC_RXMAGPKT_8198F(rxdesc) GET_RX_DESC_RXMAGPKT(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8198F(rxdesc)                                \
+	GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8198F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8198F(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8198F(rxdesc) GET_RX_DESC_SEQ(rxdesc)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE_8198F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8198F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8198F(rxdesc)                                \
+	GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_MATCH_8198F(rxdesc)                              \
+	GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_ID_8198F(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8198F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8198F(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8198F(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8198F(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8198F(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8198F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT_A1_8198F(rxdesc) GET_RX_DESC_A1_FIT_A1(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8198F(rxdesc)                               \
+	GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8198F(rxdesc)                               \
+	GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8198F(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8198F(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_FC_POWER_8198F(rxdesc) GET_RX_DESC_FC_POWER(rxdesc)
+#define GET_RX_DESC_TXRPTMID_CTL_MASK_8198F(rxdesc)                            \
+	GET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc)
+#define GET_RX_DESC_SWPS_RPT_8198F(rxdesc) GET_RX_DESC_SWPS_RPT(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8198F(rxdesc) GET_RX_DESC_PATTERN_IDX_V1(rxdesc)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL_8198F(rxdesc) GET_RX_DESC_TSFL(rxdesc)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EOR_8822C(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8822C(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8822C(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8822C(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8822C(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8822C(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8822C(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8822C(rxdesc)                                \
+	GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8822C(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8822C(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8822C(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC_8822C(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8822C(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8822C(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8822C(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8822C(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8822C(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8822C(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8822C(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8822C(rxdesc)                                \
+	GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8822C(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8822C(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8822C(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8822C(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8822C(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8822C(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8822C(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8822C(rxdesc) GET_RX_DESC_MACID(rxdesc)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK_8822C(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_PPDU_CNT_8822C(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
+#define GET_RX_DESC_C2H_8822C(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8822C(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8822C(rxdesc)                                \
+	GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_STATISTICS_8822C(rxdesc)                                \
+	GET_RX_DESC_RX_STATISTICS(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8822C(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8822C(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8822C(rxdesc) GET_RX_DESC_SEQ(rxdesc)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE_8822C(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8822C(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8822C(rxdesc)                                \
+	GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_MATCH_8822C(rxdesc)                              \
+	GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_ID_8822C(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8822C(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8822C(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8822C(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8822C(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8822C(rxdesc)                                \
+	GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8822C(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT_8822C(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8822C(rxdesc)                               \
+	GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8822C(rxdesc)                               \
+	GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8822C(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8822C(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8822C(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL_8822C(rxdesc) GET_RX_DESC_TSFL(rxdesc)
+
+#endif
+
+#endif

hal/halmac/halmac_rx_desc_nic.h

@@ -0,0 +1,462 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_RX_DESC_NIC_H_
+#define _HALMAC_RX_DESC_NIC_H_
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EOR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 30, 1)
+#define GET_RX_DESC_PHYPKTIDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 28, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_EVT_PKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 28, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_SWDEC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 27, 1)
+#define GET_RX_DESC_PHYST(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 26, 1)
+#define GET_RX_DESC_SHIFT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 24, 2)
+#define GET_RX_DESC_QOS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 23, 1)
+#define GET_RX_DESC_SECURITY(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 20, 3)
+#define GET_RX_DESC_DRV_INFO_SIZE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 16, 4)
+#define GET_RX_DESC_ICV_ERR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 15, 1)
+#define GET_RX_DESC_CRC32(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 14, 1)
+#define GET_RX_DESC_PKT_LEN(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 0, 14)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 31, 1)
+#define GET_RX_DESC_MC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 30, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_TY_PE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 28, 2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_TYPE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 28, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_MF(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 27, 1)
+#define GET_RX_DESC_MD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 26, 1)
+#define GET_RX_DESC_PWR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 25, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PAM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 24, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_A1_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 24, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_CHK_VLD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 23, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_TCP_CHKSUM_VLD(rxdesc)                                     \
+	LE_BITS_TO_4BYTE(rxdesc + 0x04, 23, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 22, 1)
+#define GET_RX_DESC_RX_IPV(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 21, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_CHKERR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 20, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_TCP_CHKSUM_ERR(rxdesc)                                     \
+	LE_BITS_TO_4BYTE(rxdesc + 0x04, 20, 1)
+#define GET_RX_DESC_PHY_PKT_IDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 17, 1)
+#define GET_RX_DESC_FW_FIFO_FULL(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 16, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PAGGR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 15, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_AMPDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 15, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RXID_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 14, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_RXCMD_IDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 14, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_AMSDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 13, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_MACID_VLD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 12, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_TID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 8, 4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_MACID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 0, 7)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 31, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_AMSDU_CUT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 31, 1)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PPDU_CNT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 29, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_C2H(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 28, 1)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_HWRSVD_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 25, 3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_HWRSVD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 24, 4)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_RXMAGPKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 24, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_WLANHD_IV_LEN(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 18, 6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_LAST_MSDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 17, 1)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_STATISTICS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 17, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_IS_QOS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 16, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_EXT_SEC_TYPE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 16, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_FRAG(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 12, 4)
+#define GET_RX_DESC_SEQ(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 0, 12)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 31, 1)
+#define GET_RX_DESC_UNICAST_WAKE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 30, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 29, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_WAKE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 29, 1)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)                                    \
+	LE_BITS_TO_4BYTE(rxdesc + 0x0C, 28, 1)
+#define GET_RX_DESC_RXPAYLOAD_ID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 24, 4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_DMA_AGG_NUM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 16, 8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_BSSID_FIT_1_0(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 12, 2)
+#define GET_RX_DESC_EOSP(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 11, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_BSSID_FIT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 11, 5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_HTC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 10, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_AMPDU_END_PKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 9, 1)
+#define GET_RX_DESC_ADDRESS_CAM_VLD(rxdesc)                                    \
+	LE_BITS_TO_4BYTE(rxdesc + 0x0C, 8, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_BSSID_FIT_4_2(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 7, 3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_EOSP_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 7, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_RATE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 0, 7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 24, 5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_ADDRESS_CAM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 24, 8)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_A1_FIT_A1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 24, 7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_MACID_VLD_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 23, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_MACID_RPT_BUFF(rxdesc)                                     \
+	LE_BITS_TO_4BYTE(rxdesc + 0x10, 17, 7)
+#define GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)                                     \
+	LE_BITS_TO_4BYTE(rxdesc + 0x10, 16, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_MACID_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 15, 8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_SCRAMBLER(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 9, 7)
+#define GET_RX_DESC_RX_EOF(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 8, 1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_FC_POWER(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 7, 1)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc)                                  \
+	LE_BITS_TO_4BYTE(rxdesc + 0x10, 6, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_SWPS_RPT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 5, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_IDX(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_IDX_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_IDX_V2(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x14, 0, 32)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_FREERUN_CNT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x14, 0, 32)
+
+#endif
+
+#endif

hal/halmac/halmac_sdio_reg.h

@@ -0,0 +1,55 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __HALMAC_SDIO_REG_H__
+#define __HALMAC_SDIO_REG_H__
+
+/* SDIO CMD address mapping */
+
+#define HALMAC_SDIO_4BYTE_LEN_MASK      0x1FFF
+#define HALMAC_SDIO_LOCAL_MSK           0x0FFF
+#define HALMAC_WLAN_MAC_REG_MSK		0xFFFF
+#define	HALMAC_WLAN_IOREG_MSK		0xFFFF
+
+/* Sdio Address for SDIO Local Reg, TRX FIFO, MAC Reg */
+enum halmac_sdio_cmd_addr {
+	HALMAC_SDIO_CMD_ADDR_SDIO_REG = 0,
+	HALMAC_SDIO_CMD_ADDR_MAC_REG = 8,
+	HALMAC_SDIO_CMD_ADDR_TXFF_HIGH = 4,
+	HALMAC_SDIO_CMD_ADDR_TXFF_LOW = 6,
+	HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL = 5,
+	HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA = 7,
+	HALMAC_SDIO_CMD_ADDR_RXFF = 7,
+};
+
+/* IO Bus domain address mapping */
+#define SDIO_LOCAL_OFFSET		0x10250000
+#define WLAN_IOREG_OFFSET		0x10260000
+#define FW_FIFO_OFFSET			0x10270000
+#define TX_HIQ_OFFSET			0x10310000
+#define TX_MIQ_OFFSET			0x10320000
+#define TX_LOQ_OFFSET			0x10330000
+#define TX_EXQ_OFFSET			0x10350000
+#define RX_RXOFF_OFFSET			0x10340000
+
+/* Get TX WLAN FIFO information in CMD53 addr  */
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT)
+#define GET_WLAN_TXFF_DEVICE_ID(cmd53_addr) \
+			LE_BITS_TO_4BYTE((u32 *)cmd53_addr, 13, 4)
+#define GET_WLAN_TXFF_PKT_SIZE(cmd53_addr) \
+			(LE_BITS_TO_4BYTE((u32 *)cmd53_addr, 0, 13) << 2)
+#endif
+
+#endif/* __HALMAC_SDIO_REG_H__ */

hal/halmac/halmac_state_machine.h

@@ -0,0 +1,157 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_STATE_MACHINE_H_
+#define _HALMAC_STATE_MACHINE_H_
+
+enum halmac_dlfw_state {
+	HALMAC_DLFW_NONE = 0,
+	HALMAC_DLFW_DONE = 1,
+	HALMAC_GEN_INFO_SENT = 2,
+
+	/* Data CPU firmware download framework */
+	HALMAC_DLFW_INIT = 0x11,
+	HALMAC_DLFW_START = 0x12,
+	HALMAC_DLFW_CONF_READY = 0x13,
+	HALMAC_DLFW_CPU_READY = 0x14,
+	HALMAC_DLFW_MEM_READY = 0x15,
+	HALMAC_DLFW_SW_READY = 0x16,
+	HALMAC_DLFW_OFLD_READY = 0x17,
+
+	HALMAC_DLFW_UNDEFINED = 0x7F,
+};
+
+enum halmac_gpio_cfg_state {
+	HALMAC_GPIO_CFG_STATE_IDLE = 0,
+	HALMAC_GPIO_CFG_STATE_BUSY = 1,
+	HALMAC_GPIO_CFG_STATE_UNDEFINED = 0x7F,
+};
+
+enum halmac_rsvd_pg_state {
+	HALMAC_RSVD_PG_STATE_IDLE = 0,
+	HALMAC_RSVD_PG_STATE_BUSY = 1,
+	HALMAC_RSVD_PG_STATE_UNDEFINED = 0x7F,
+};
+
+enum halmac_api_state {
+	HALMAC_API_STATE_INIT = 0,
+	HALMAC_API_STATE_HALT = 1,
+	HALMAC_API_STATE_UNDEFINED = 0x7F,
+};
+
+enum halmac_cmd_construct_state {
+	HALMAC_CMD_CNSTR_IDLE = 0,
+	HALMAC_CMD_CNSTR_BUSY = 1,
+	HALMAC_CMD_CNSTR_H2C_SENT = 2,
+	HALMAC_CMD_CNSTR_CNSTR = 3,
+	HALMAC_CMD_CNSTR_BUF_CLR = 4,
+	HALMAC_CMD_CNSTR_UNDEFINED = 0x7F,
+};
+
+enum halmac_cmd_process_status {
+	HALMAC_CMD_PROCESS_IDLE = 0x01, /* Init status */
+	HALMAC_CMD_PROCESS_SENDING = 0x02, /* Wait ack */
+	HALMAC_CMD_PROCESS_RCVD = 0x03, /* Rcvd ack */
+	HALMAC_CMD_PROCESS_DONE = 0x04, /* Event done */
+	HALMAC_CMD_PROCESS_ERROR = 0x05, /* Return code error */
+	HALMAC_CMD_PROCESS_UNDEFINE = 0x7F,
+};
+
+enum halmac_mac_power {
+	HALMAC_MAC_POWER_OFF = 0x0,
+	HALMAC_MAC_POWER_ON = 0x1,
+	HALMAC_MAC_POWER_UNDEFINE = 0x7F,
+};
+
+enum halmac_wlcpu_mode {
+	HALMAC_WLCPU_ACTIVE = 0x0,
+	HALMAC_WLCPU_ENTER_SLEEP = 0x1,
+	HALMAC_WLCPU_SLEEP = 0x2,
+	HALMAC_WLCPU_UNDEFINE = 0x7F,
+};
+
+struct halmac_efuse_state {
+	enum halmac_cmd_construct_state cmd_cnstr_state;
+	enum halmac_cmd_process_status proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_cfg_param_state {
+	enum halmac_cmd_construct_state cmd_cnstr_state;
+	enum halmac_cmd_process_status proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_scan_state {
+	enum halmac_cmd_construct_state cmd_cnstr_state;
+	enum halmac_cmd_process_status proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_update_pkt_state {
+	enum halmac_cmd_process_status proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_iqk_state {
+	enum halmac_cmd_process_status proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_pwr_tracking_state {
+	enum halmac_cmd_process_status	proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_psd_state {
+	enum halmac_cmd_process_status proc_status;
+	u16 data_size;
+	u16 seg_size;
+	u8 *data;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_fw_snding_state {
+	enum halmac_cmd_construct_state cmd_cnstr_state;
+	enum halmac_cmd_process_status proc_status;
+	u8 fw_rc;
+	u16 seq_num;
+};
+
+struct halmac_state {
+	struct halmac_efuse_state efuse_state;
+	struct halmac_cfg_param_state cfg_param_state;
+	struct halmac_scan_state scan_state;
+	struct halmac_update_pkt_state update_pkt_state;
+	struct halmac_iqk_state iqk_state;
+	struct halmac_pwr_tracking_state pwr_trk_state;
+	struct halmac_psd_state psd_state;
+	struct halmac_fw_snding_state fw_snding_state;
+	enum halmac_api_state api_state;
+	enum halmac_mac_power mac_pwr;
+	enum halmac_dlfw_state dlfw_state;
+	enum halmac_wlcpu_mode wlcpu_mode;
+	enum halmac_gpio_cfg_state gpio_cfg_state;
+	enum halmac_rsvd_pg_state rsvd_pg_state;
+};
+
+#endif

hal/halmac/halmac_tx_bd_nic.h

@@ -0,0 +1,110 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_BD_NIC_H_
+#define _HALMAC_TX_BD_NIC_H_
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+	HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*TXBD_DW0*/
+
+#define SET_TX_BD_OWN(txbd, value)                                             \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x00, 31, 1, value)
+#define GET_TX_BD_OWN(txbd) LE_BITS_TO_4BYTE(txbd + 0x00, 31, 1)
+#define SET_TX_BD_PSB(txbd, value)                                             \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x00, 16, 8, value)
+#define GET_TX_BD_PSB(txbd) LE_BITS_TO_4BYTE(txbd + 0x00, 16, 8)
+#define SET_TX_BD_TX_BUFF_SIZE0(txbd, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x00, 0, 16, value)
+#define GET_TX_BD_TX_BUFF_SIZE0(txbd) LE_BITS_TO_4BYTE(txbd + 0x00, 0, 16)
+
+/*TXBD_DW1*/
+
+#define SET_TX_BD_PHYSICAL_ADDR0_LOW(txbd, value)                              \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x04, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR0_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x04, 0, 32)
+
+/*TXBD_DW2*/
+
+#define SET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd, value)                             \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x08, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x08, 0, 32)
+
+/*TXBD_DW4*/
+
+#define SET_TX_BD_A1(txbd, value)                                              \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x10, 31, 1, value)
+#define GET_TX_BD_A1(txbd) LE_BITS_TO_4BYTE(txbd + 0x10, 31, 1)
+#define SET_TX_BD_TX_BUFF_SIZE1(txbd, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x10, 0, 16, value)
+#define GET_TX_BD_TX_BUFF_SIZE1(txbd) LE_BITS_TO_4BYTE(txbd + 0x10, 0, 16)
+
+/*TXBD_DW5*/
+
+#define SET_TX_BD_PHYSICAL_ADDR1_LOW(txbd, value)                              \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x14, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR1_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x14, 0, 32)
+
+/*TXBD_DW6*/
+
+#define SET_TX_BD_PHYSICAL_ADDR1_HIGH(txbd, value)                             \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x18, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR1_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x18, 0, 32)
+
+/*TXBD_DW8*/
+
+#define SET_TX_BD_A2(txbd, value)                                              \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x20, 31, 1, value)
+#define GET_TX_BD_A2(txbd) LE_BITS_TO_4BYTE(txbd + 0x20, 31, 1)
+#define SET_TX_BD_TX_BUFF_SIZE2(txbd, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x20, 0, 16, value)
+#define GET_TX_BD_TX_BUFF_SIZE2(txbd) LE_BITS_TO_4BYTE(txbd + 0x20, 0, 16)
+
+/*TXBD_DW9*/
+
+#define SET_TX_BD_PHYSICAL_ADDR2_LOW(txbd, value)                              \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x24, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR2_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x24, 0, 32)
+
+/*TXBD_DW10*/
+
+#define SET_TX_BD_PHYSICAL_ADDR2_HIGH(txbd, value)                             \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x28, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR2_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x28, 0, 32)
+
+/*TXBD_DW12*/
+
+#define SET_TX_BD_A3(txbd, value)                                              \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x30, 31, 1, value)
+#define GET_TX_BD_A3(txbd) LE_BITS_TO_4BYTE(txbd + 0x30, 31, 1)
+#define SET_TX_BD_TX_BUFF_SIZE3(txbd, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x30, 0, 16, value)
+#define GET_TX_BD_TX_BUFF_SIZE3(txbd) LE_BITS_TO_4BYTE(txbd + 0x30, 0, 16)
+
+/*TXBD_DW13*/
+
+#define SET_TX_BD_PHYSICAL_ADDR3_LOW(txbd, value)                              \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x34, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR3_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x34, 0, 32)
+
+/*TXBD_DW14*/
+
+#define SET_TX_BD_PHYSICAL_ADDR3_HIGH(txbd, value)                             \
+	SET_BITS_TO_LE_4BYTE(txbd + 0x38, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR3_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x38, 0, 32)
+
+#endif
+
+#endif

hal/halmac/halmac_tx_desc_buffer_chip.h

@@ -0,0 +1,509 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_BUFFER_CHIP_H_
+#define _HALMAC_TX_DESC_BUFFER_CHIP_H_
+#if (HALMAC_8814B_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_BUFFER_RDG_EN_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_RDG_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_RDG_EN_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_RDG_EN(txdesc)
+#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL_8814B(txdesc, value)                \
+	SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc, value)
+#define GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL_8814B(txdesc)                       \
+	GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc)
+#define SET_TX_DESC_BUFFER_AGG_EN_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_AGG_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_AGG_EN_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_AGG_EN(txdesc)
+#define SET_TX_DESC_BUFFER_PKT_OFFSET_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_PKT_OFFSET(txdesc, value)
+#define GET_TX_DESC_BUFFER_PKT_OFFSET_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_PKT_OFFSET(txdesc)
+#define SET_TX_DESC_BUFFER_OFFSET_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_OFFSET(txdesc, value)
+#define GET_TX_DESC_BUFFER_OFFSET_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_OFFSET(txdesc)
+#define SET_TX_DESC_BUFFER_TXPKTSIZE_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_TXPKTSIZE(txdesc, value)
+#define GET_TX_DESC_BUFFER_TXPKTSIZE_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_TXPKTSIZE(txdesc)
+
+/*TXDESC_WORD1*/
+
+#define SET_TX_DESC_BUFFER_USERATE_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_USERATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_USERATE_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_USERATE(txdesc)
+#define SET_TX_DESC_BUFFER_AMSDU_8814B(txdesc, value)                          \
+	SET_TX_DESC_BUFFER_AMSDU(txdesc, value)
+#define GET_TX_DESC_BUFFER_AMSDU_8814B(txdesc) GET_TX_DESC_BUFFER_AMSDU(txdesc)
+#define SET_TX_DESC_BUFFER_EN_HWSEQ_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_EN_HWSEQ(txdesc, value)
+#define GET_TX_DESC_BUFFER_EN_HWSEQ_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_EN_HWSEQ(txdesc)
+#define SET_TX_DESC_BUFFER_EN_HWEXSEQ_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc, value)
+#define GET_TX_DESC_BUFFER_EN_HWEXSEQ_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc)
+#define SET_TX_DESC_BUFFER_SW_SEQ_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_SW_SEQ(txdesc, value)
+#define GET_TX_DESC_BUFFER_SW_SEQ_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_SW_SEQ(txdesc)
+#define SET_TX_DESC_BUFFER_DROP_ID_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_DROP_ID(txdesc, value)
+#define GET_TX_DESC_BUFFER_DROP_ID_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_DROP_ID(txdesc)
+#define SET_TX_DESC_BUFFER_MOREDATA_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_MOREDATA(txdesc, value)
+#define GET_TX_DESC_BUFFER_MOREDATA_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_MOREDATA(txdesc)
+#define SET_TX_DESC_BUFFER_QSEL_8814B(txdesc, value)                           \
+	SET_TX_DESC_BUFFER_QSEL(txdesc, value)
+#define GET_TX_DESC_BUFFER_QSEL_8814B(txdesc) GET_TX_DESC_BUFFER_QSEL(txdesc)
+#define SET_TX_DESC_BUFFER_MACID_8814B(txdesc, value)                          \
+	SET_TX_DESC_BUFFER_MACID(txdesc, value)
+#define GET_TX_DESC_BUFFER_MACID_8814B(txdesc) GET_TX_DESC_BUFFER_MACID(txdesc)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_BUFFER_CHK_EN_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_CHK_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_CHK_EN_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_CHK_EN(txdesc)
+#define SET_TX_DESC_BUFFER_DISQSELSEQ_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_DISQSELSEQ(txdesc, value)
+#define GET_TX_DESC_BUFFER_DISQSELSEQ_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_DISQSELSEQ(txdesc)
+#define SET_TX_DESC_BUFFER_SND_PKT_SEL_8814B(txdesc, value)                    \
+	SET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc, value)
+#define GET_TX_DESC_BUFFER_SND_PKT_SEL_8814B(txdesc)                           \
+	GET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc)
+#define SET_TX_DESC_BUFFER_DMA_PRI_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_DMA_PRI(txdesc, value)
+#define GET_TX_DESC_BUFFER_DMA_PRI_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_DMA_PRI(txdesc)
+#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE_8814B(txdesc, value)                 \
+	SET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc, value)
+#define GET_TX_DESC_BUFFER_MAX_AMSDU_MODE_8814B(txdesc)                        \
+	GET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc)
+#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM_8814B(txdesc, value)                  \
+	SET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc, value)
+#define GET_TX_DESC_BUFFER_DMA_TXAGG_NUM_8814B(txdesc)                         \
+	GET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc)
+#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM_8814B(txdesc, value)                \
+	SET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc, value)
+#define GET_TX_DESC_BUFFER_TXDESC_CHECKSUM_8814B(txdesc)                       \
+	GET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE_8814B(txdesc, value)                   \
+	SET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc, value)
+#define GET_TX_DESC_BUFFER_OFFLOAD_SIZE_8814B(txdesc)                          \
+	GET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc)
+#define SET_TX_DESC_BUFFER_CHANNEL_DMA_8814B(txdesc, value)                    \
+	SET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc, value)
+#define GET_TX_DESC_BUFFER_CHANNEL_DMA_8814B(txdesc)                           \
+	GET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc)
+#define SET_TX_DESC_BUFFER_MBSSID_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_MBSSID(txdesc, value)
+#define GET_TX_DESC_BUFFER_MBSSID_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_MBSSID(txdesc)
+#define SET_TX_DESC_BUFFER_BK_8814B(txdesc, value)                             \
+	SET_TX_DESC_BUFFER_BK(txdesc, value)
+#define GET_TX_DESC_BUFFER_BK_8814B(txdesc) GET_TX_DESC_BUFFER_BK(txdesc)
+#define SET_TX_DESC_BUFFER_WHEADER_LEN_8814B(txdesc, value)                    \
+	SET_TX_DESC_BUFFER_WHEADER_LEN(txdesc, value)
+#define GET_TX_DESC_BUFFER_WHEADER_LEN_8814B(txdesc)                           \
+	GET_TX_DESC_BUFFER_WHEADER_LEN(txdesc)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_BUFFER_TRY_RATE_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_TRY_RATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_TRY_RATE_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_TRY_RATE(txdesc)
+#define SET_TX_DESC_BUFFER_DATA_BW_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_DATA_BW(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATA_BW_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_DATA_BW(txdesc)
+#define SET_TX_DESC_BUFFER_DATA_SHORT_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_DATA_SHORT(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATA_SHORT_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_DATA_SHORT(txdesc)
+#define SET_TX_DESC_BUFFER_DATARATE_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_DATARATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATARATE_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_DATARATE(txdesc)
+#define SET_TX_DESC_BUFFER_TXBF_PATH_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_TXBF_PATH(txdesc, value)
+#define GET_TX_DESC_BUFFER_TXBF_PATH_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_TXBF_PATH(txdesc)
+#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET_8814B(txdesc, value)            \
+	SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc, value)
+#define GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET_8814B(txdesc)                   \
+	GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_BUFFER_RTY_LMT_EN_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_RTY_LMT_EN_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc)
+#define SET_TX_DESC_BUFFER_HW_RTS_EN_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_HW_RTS_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_HW_RTS_EN_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_HW_RTS_EN(txdesc)
+#define SET_TX_DESC_BUFFER_RTS_EN_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_RTS_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_RTS_EN_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_RTS_EN(txdesc)
+#define SET_TX_DESC_BUFFER_CTS2SELF_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_CTS2SELF(txdesc, value)
+#define GET_TX_DESC_BUFFER_CTS2SELF_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_CTS2SELF(txdesc)
+#define SET_TX_DESC_BUFFER_TAILPAGE_H_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_TAILPAGE_H(txdesc, value)
+#define GET_TX_DESC_BUFFER_TAILPAGE_H_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_TAILPAGE_H(txdesc)
+#define SET_TX_DESC_BUFFER_TAILPAGE_L_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_TAILPAGE_L(txdesc, value)
+#define GET_TX_DESC_BUFFER_TAILPAGE_L_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_TAILPAGE_L(txdesc)
+#define SET_TX_DESC_BUFFER_NAVUSEHDR_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_NAVUSEHDR(txdesc, value)
+#define GET_TX_DESC_BUFFER_NAVUSEHDR_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_NAVUSEHDR(txdesc)
+#define SET_TX_DESC_BUFFER_BMC_8814B(txdesc, value)                            \
+	SET_TX_DESC_BUFFER_BMC(txdesc, value)
+#define GET_TX_DESC_BUFFER_BMC_8814B(txdesc) GET_TX_DESC_BUFFER_BMC(txdesc)
+#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT_8814B(txdesc, value)               \
+	SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc, value)
+#define GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT_8814B(txdesc)                      \
+	GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc)
+#define SET_TX_DESC_BUFFER_HW_AES_IV_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_HW_AES_IV(txdesc, value)
+#define GET_TX_DESC_BUFFER_HW_AES_IV_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_HW_AES_IV(txdesc)
+#define SET_TX_DESC_BUFFER_BT_NULL_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_BT_NULL(txdesc, value)
+#define GET_TX_DESC_BUFFER_BT_NULL_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_BT_NULL(txdesc)
+#define SET_TX_DESC_BUFFER_EN_DESC_ID_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_EN_DESC_ID(txdesc, value)
+#define GET_TX_DESC_BUFFER_EN_DESC_ID_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_EN_DESC_ID(txdesc)
+#define SET_TX_DESC_BUFFER_SECTYPE_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_SECTYPE(txdesc, value)
+#define GET_TX_DESC_BUFFER_SECTYPE_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_SECTYPE(txdesc)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_BUFFER_MULTIPLE_PORT_8814B(txdesc, value)                  \
+	SET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc, value)
+#define GET_TX_DESC_BUFFER_MULTIPLE_PORT_8814B(txdesc)                         \
+	GET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc)
+#define SET_TX_DESC_BUFFER_POLLUTED_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_POLLUTED(txdesc, value)
+#define GET_TX_DESC_BUFFER_POLLUTED_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_POLLUTED(txdesc)
+#define SET_TX_DESC_BUFFER_NULL_1_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_NULL_1(txdesc, value)
+#define GET_TX_DESC_BUFFER_NULL_1_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_NULL_1(txdesc)
+#define SET_TX_DESC_BUFFER_NULL_0_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_NULL_0(txdesc, value)
+#define GET_TX_DESC_BUFFER_NULL_0_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_NULL_0(txdesc)
+#define SET_TX_DESC_BUFFER_TRI_FRAME_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_TRI_FRAME(txdesc, value)
+#define GET_TX_DESC_BUFFER_TRI_FRAME_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_TRI_FRAME(txdesc)
+#define SET_TX_DESC_BUFFER_SPE_RPT_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_SPE_RPT(txdesc, value)
+#define GET_TX_DESC_BUFFER_SPE_RPT_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_SPE_RPT(txdesc)
+#define SET_TX_DESC_BUFFER_FTM_EN_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_FTM_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_FTM_EN_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_FTM_EN(txdesc)
+#define SET_TX_DESC_BUFFER_MU_DATARATE_8814B(txdesc, value)                    \
+	SET_TX_DESC_BUFFER_MU_DATARATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_MU_DATARATE_8814B(txdesc)                           \
+	GET_TX_DESC_BUFFER_MU_DATARATE(txdesc)
+#define SET_TX_DESC_BUFFER_CCA_RTS_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_CCA_RTS(txdesc, value)
+#define GET_TX_DESC_BUFFER_CCA_RTS_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_CCA_RTS(txdesc)
+#define SET_TX_DESC_BUFFER_NDPA_8814B(txdesc, value)                           \
+	SET_TX_DESC_BUFFER_NDPA(txdesc, value)
+#define GET_TX_DESC_BUFFER_NDPA_8814B(txdesc) GET_TX_DESC_BUFFER_NDPA(txdesc)
+#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE_8814B(txdesc, value)               \
+	SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc, value)
+#define GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE_8814B(txdesc)                      \
+	GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc)
+#define SET_TX_DESC_BUFFER_P_AID_8814B(txdesc, value)                          \
+	SET_TX_DESC_BUFFER_P_AID(txdesc, value)
+#define GET_TX_DESC_BUFFER_P_AID_8814B(txdesc) GET_TX_DESC_BUFFER_P_AID(txdesc)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_BUFFER_SW_DEFINE_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_SW_DEFINE(txdesc, value)
+#define GET_TX_DESC_BUFFER_SW_DEFINE_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_SW_DEFINE(txdesc)
+#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID_8814B(txdesc, value)                 \
+	SET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc, value)
+#define GET_TX_DESC_BUFFER_CTRL_CNT_VALID_8814B(txdesc)                        \
+	GET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc)
+#define SET_TX_DESC_BUFFER_CTRL_CNT_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_CTRL_CNT(txdesc, value)
+#define GET_TX_DESC_BUFFER_CTRL_CNT_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_CTRL_CNT(txdesc)
+#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE_8814B(txdesc, value)           \
+	SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE_8814B(txdesc)                  \
+	GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_BUFFER_PATH_MAPA_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_PATH_MAPA(txdesc, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPA_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_PATH_MAPA(txdesc)
+#define SET_TX_DESC_BUFFER_PATH_MAPB_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_PATH_MAPB(txdesc, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPB_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_PATH_MAPB(txdesc)
+#define SET_TX_DESC_BUFFER_PATH_MAPC_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_PATH_MAPC(txdesc, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPC_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_PATH_MAPC(txdesc)
+#define SET_TX_DESC_BUFFER_PATH_MAPD_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_PATH_MAPD(txdesc, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPD_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_PATH_MAPD(txdesc)
+#define SET_TX_DESC_BUFFER_ANTSEL_A_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_ANTSEL_A(txdesc, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_A_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_ANTSEL_A(txdesc)
+#define SET_TX_DESC_BUFFER_ANTSEL_B_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_ANTSEL_B(txdesc, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_B_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_ANTSEL_B(txdesc)
+#define SET_TX_DESC_BUFFER_ANTSEL_C_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_ANTSEL_C(txdesc, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_C_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_ANTSEL_C(txdesc)
+#define SET_TX_DESC_BUFFER_ANTSEL_D_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_ANTSEL_D(txdesc, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_D_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_ANTSEL_D(txdesc)
+#define SET_TX_DESC_BUFFER_NTX_PATH_EN_8814B(txdesc, value)                    \
+	SET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_NTX_PATH_EN_8814B(txdesc)                           \
+	GET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc)
+#define SET_TX_DESC_BUFFER_ANTLSEL_EN_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_ANTLSEL_EN_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc)
+#define SET_TX_DESC_BUFFER_AMPDU_DENSITY_8814B(txdesc, value)                  \
+	SET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc, value)
+#define GET_TX_DESC_BUFFER_AMPDU_DENSITY_8814B(txdesc)                         \
+	GET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_BUFFER_VCS_STBC_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_VCS_STBC(txdesc, value)
+#define GET_TX_DESC_BUFFER_VCS_STBC_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_VCS_STBC(txdesc)
+#define SET_TX_DESC_BUFFER_DATA_STBC_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_DATA_STBC(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATA_STBC_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_DATA_STBC(txdesc)
+#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE_8814B(txdesc, value)            \
+	SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE_8814B(txdesc)                   \
+	GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN_8814B(txdesc, value)            \
+	SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN_8814B(txdesc)                   \
+	GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc)
+#define SET_TX_DESC_BUFFER_MHR_CP_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_MHR_CP(txdesc, value)
+#define GET_TX_DESC_BUFFER_MHR_CP_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_MHR_CP(txdesc)
+#define SET_TX_DESC_BUFFER_SMH_EN_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_SMH_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_SMH_EN_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_SMH_EN(txdesc)
+#define SET_TX_DESC_BUFFER_RTSRATE_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_RTSRATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_RTSRATE_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_RTSRATE(txdesc)
+#define SET_TX_DESC_BUFFER_SMH_CAM_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_SMH_CAM(txdesc, value)
+#define GET_TX_DESC_BUFFER_SMH_CAM_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_SMH_CAM(txdesc)
+#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL_8814B(txdesc, value)                 \
+	SET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc, value)
+#define GET_TX_DESC_BUFFER_ARFR_TABLE_SEL_8814B(txdesc)                        \
+	GET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc)
+#define SET_TX_DESC_BUFFER_ARFR_HT_EN_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_ARFR_HT_EN_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc)
+#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN_8814B(txdesc, value)                   \
+	SET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_ARFR_OFDM_EN_8814B(txdesc)                          \
+	GET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc)
+#define SET_TX_DESC_BUFFER_ARFR_CCK_EN_8814B(txdesc, value)                    \
+	SET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_ARFR_CCK_EN_8814B(txdesc)                           \
+	GET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc)
+#define SET_TX_DESC_BUFFER_RTS_SHORT_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_RTS_SHORT(txdesc, value)
+#define GET_TX_DESC_BUFFER_RTS_SHORT_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_RTS_SHORT(txdesc)
+#define SET_TX_DESC_BUFFER_DISDATAFB_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_DISDATAFB(txdesc, value)
+#define GET_TX_DESC_BUFFER_DISDATAFB_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_DISDATAFB(txdesc)
+#define SET_TX_DESC_BUFFER_DISRTSFB_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_DISRTSFB(txdesc, value)
+#define GET_TX_DESC_BUFFER_DISRTSFB_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_DISRTSFB(txdesc)
+#define SET_TX_DESC_BUFFER_EXT_EDCA_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_EXT_EDCA(txdesc, value)
+#define GET_TX_DESC_BUFFER_EXT_EDCA_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_EXT_EDCA(txdesc)
+
+/*TXDESC_WORD10*/
+
+#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME_8814B(txdesc, value)                 \
+	SET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc, value)
+#define GET_TX_DESC_BUFFER_AMPDU_MAX_TIME_8814B(txdesc)                        \
+	GET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc)
+#define SET_TX_DESC_BUFFER_SPECIAL_CW_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_SPECIAL_CW(txdesc, value)
+#define GET_TX_DESC_BUFFER_SPECIAL_CW_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_SPECIAL_CW(txdesc)
+#define SET_TX_DESC_BUFFER_RDG_NAV_EXT_8814B(txdesc, value)                    \
+	SET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc, value)
+#define GET_TX_DESC_BUFFER_RDG_NAV_EXT_8814B(txdesc)                           \
+	GET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc)
+#define SET_TX_DESC_BUFFER_RAW_8814B(txdesc, value)                            \
+	SET_TX_DESC_BUFFER_RAW(txdesc, value)
+#define GET_TX_DESC_BUFFER_RAW_8814B(txdesc) GET_TX_DESC_BUFFER_RAW(txdesc)
+#define SET_TX_DESC_BUFFER_MAX_AGG_NUM_8814B(txdesc, value)                    \
+	SET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc, value)
+#define GET_TX_DESC_BUFFER_MAX_AGG_NUM_8814B(txdesc)                           \
+	GET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc)
+#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE_8814B(txdesc, value)                \
+	SET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_FINAL_DATA_RATE_8814B(txdesc)                       \
+	GET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc)
+#define SET_TX_DESC_BUFFER_GF_8814B(txdesc, value)                             \
+	SET_TX_DESC_BUFFER_GF(txdesc, value)
+#define GET_TX_DESC_BUFFER_GF_8814B(txdesc) GET_TX_DESC_BUFFER_GF(txdesc)
+#define SET_TX_DESC_BUFFER_MOREFRAG_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_MOREFRAG(txdesc, value)
+#define GET_TX_DESC_BUFFER_MOREFRAG_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_MOREFRAG(txdesc)
+#define SET_TX_DESC_BUFFER_NOACM_8814B(txdesc, value)                          \
+	SET_TX_DESC_BUFFER_NOACM(txdesc, value)
+#define GET_TX_DESC_BUFFER_NOACM_8814B(txdesc) GET_TX_DESC_BUFFER_NOACM(txdesc)
+#define SET_TX_DESC_BUFFER_HTC_8814B(txdesc, value)                            \
+	SET_TX_DESC_BUFFER_HTC(txdesc, value)
+#define GET_TX_DESC_BUFFER_HTC_8814B(txdesc) GET_TX_DESC_BUFFER_HTC(txdesc)
+#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS_8814B(txdesc, value)              \
+	SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc, value)
+#define GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS_8814B(txdesc)                     \
+	GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc)
+#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN_8814B(txdesc, value)                \
+	SET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_USE_MAX_TIME_EN_8814B(txdesc)                       \
+	GET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc)
+#define SET_TX_DESC_BUFFER_HW_SSN_SEL_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc, value)
+#define GET_TX_DESC_BUFFER_HW_SSN_SEL_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc)
+
+/*TXDESC_WORD11*/
+
+#define SET_TX_DESC_BUFFER_ADDR_CAM_8814B(txdesc, value)                       \
+	SET_TX_DESC_BUFFER_ADDR_CAM(txdesc, value)
+#define GET_TX_DESC_BUFFER_ADDR_CAM_8814B(txdesc)                              \
+	GET_TX_DESC_BUFFER_ADDR_CAM(txdesc)
+#define SET_TX_DESC_BUFFER_SND_TARGET_8814B(txdesc, value)                     \
+	SET_TX_DESC_BUFFER_SND_TARGET(txdesc, value)
+#define GET_TX_DESC_BUFFER_SND_TARGET_8814B(txdesc)                            \
+	GET_TX_DESC_BUFFER_SND_TARGET(txdesc)
+#define SET_TX_DESC_BUFFER_DATA_LDPC_8814B(txdesc, value)                      \
+	SET_TX_DESC_BUFFER_DATA_LDPC(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATA_LDPC_8814B(txdesc)                             \
+	GET_TX_DESC_BUFFER_DATA_LDPC(txdesc)
+#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN_8814B(txdesc, value)                   \
+	SET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_LSIG_TXOP_EN_8814B(txdesc)                          \
+	GET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc)
+#define SET_TX_DESC_BUFFER_G_ID_8814B(txdesc, value)                           \
+	SET_TX_DESC_BUFFER_G_ID(txdesc, value)
+#define GET_TX_DESC_BUFFER_G_ID_8814B(txdesc) GET_TX_DESC_BUFFER_G_ID(txdesc)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC_8814B(txdesc, value)            \
+	SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc, value)
+#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC_8814B(txdesc)                   \
+	GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc)
+#define SET_TX_DESC_BUFFER_DATA_SC_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_DATA_SC(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATA_SC_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_DATA_SC(txdesc)
+
+/*TXDESC_WORD12*/
+
+#define SET_TX_DESC_BUFFER_LEN1_L_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_LEN1_L(txdesc, value)
+#define GET_TX_DESC_BUFFER_LEN1_L_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_LEN1_L(txdesc)
+#define SET_TX_DESC_BUFFER_LEN0_8814B(txdesc, value)                           \
+	SET_TX_DESC_BUFFER_LEN0(txdesc, value)
+#define GET_TX_DESC_BUFFER_LEN0_8814B(txdesc) GET_TX_DESC_BUFFER_LEN0(txdesc)
+#define SET_TX_DESC_BUFFER_PKT_NUM_8814B(txdesc, value)                        \
+	SET_TX_DESC_BUFFER_PKT_NUM(txdesc, value)
+#define GET_TX_DESC_BUFFER_PKT_NUM_8814B(txdesc)                               \
+	GET_TX_DESC_BUFFER_PKT_NUM(txdesc)
+
+/*TXDESC_WORD13*/
+
+#define SET_TX_DESC_BUFFER_LEN3_8814B(txdesc, value)                           \
+	SET_TX_DESC_BUFFER_LEN3(txdesc, value)
+#define GET_TX_DESC_BUFFER_LEN3_8814B(txdesc) GET_TX_DESC_BUFFER_LEN3(txdesc)
+#define SET_TX_DESC_BUFFER_LEN2_8814B(txdesc, value)                           \
+	SET_TX_DESC_BUFFER_LEN2(txdesc, value)
+#define GET_TX_DESC_BUFFER_LEN2_8814B(txdesc) GET_TX_DESC_BUFFER_LEN2(txdesc)
+#define SET_TX_DESC_BUFFER_LEN1_H_8814B(txdesc, value)                         \
+	SET_TX_DESC_BUFFER_LEN1_H(txdesc, value)
+#define GET_TX_DESC_BUFFER_LEN1_H_8814B(txdesc)                                \
+	GET_TX_DESC_BUFFER_LEN1_H(txdesc)
+
+#endif
+
+#endif

hal/halmac/halmac_tx_desc_buffer_nic.h

@@ -0,0 +1,491 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_BUFFER_NIC_H_
+#define _HALMAC_TX_DESC_BUFFER_NIC_H_
+#if (HALMAC_8814B_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_BUFFER_RDG_EN(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 31, 1, value)
+#define GET_TX_DESC_BUFFER_RDG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 31, 1)
+#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc, value)                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value)
+#define GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc)                             \
+	LE_BITS_TO_4BYTE(txdesc + 0x00, 30, 1)
+#define SET_TX_DESC_BUFFER_AGG_EN(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value)
+#define GET_TX_DESC_BUFFER_AGG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 29, 1)
+#define SET_TX_DESC_BUFFER_PKT_OFFSET(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 24, 5, value)
+#define GET_TX_DESC_BUFFER_PKT_OFFSET(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x00, 24, 5)
+#define SET_TX_DESC_BUFFER_OFFSET(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 16, 8, value)
+#define GET_TX_DESC_BUFFER_OFFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 16, 8)
+#define SET_TX_DESC_BUFFER_TXPKTSIZE(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 0, 16, value)
+#define GET_TX_DESC_BUFFER_TXPKTSIZE(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x00, 0, 16)
+
+/*TXDESC_WORD1*/
+
+#define SET_TX_DESC_BUFFER_USERATE(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 31, 1, value)
+#define GET_TX_DESC_BUFFER_USERATE(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x04, 31, 1)
+#define SET_TX_DESC_BUFFER_AMSDU(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value)
+#define GET_TX_DESC_BUFFER_AMSDU(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1)
+#define SET_TX_DESC_BUFFER_EN_HWSEQ(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value)
+#define GET_TX_DESC_BUFFER_EN_HWSEQ(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x04, 29, 1)
+#define SET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 28, 1, value)
+#define GET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x04, 28, 1)
+#define SET_TX_DESC_BUFFER_SW_SEQ(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 16, 12, value)
+#define GET_TX_DESC_BUFFER_SW_SEQ(txdesc)                                      \
+	LE_BITS_TO_4BYTE(txdesc + 0x04, 16, 12)
+#define SET_TX_DESC_BUFFER_DROP_ID(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 14, 2, value)
+#define GET_TX_DESC_BUFFER_DROP_ID(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x04, 14, 2)
+#define SET_TX_DESC_BUFFER_MOREDATA(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 13, 1, value)
+#define GET_TX_DESC_BUFFER_MOREDATA(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x04, 13, 1)
+#define SET_TX_DESC_BUFFER_QSEL(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 8, 5, value)
+#define GET_TX_DESC_BUFFER_QSEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 8, 5)
+#define SET_TX_DESC_BUFFER_MACID(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 8, value)
+#define GET_TX_DESC_BUFFER_MACID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 0, 8)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_BUFFER_CHK_EN(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 31, 1, value)
+#define GET_TX_DESC_BUFFER_CHK_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 31, 1)
+#define SET_TX_DESC_BUFFER_DISQSELSEQ(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 30, 1, value)
+#define GET_TX_DESC_BUFFER_DISQSELSEQ(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x08, 30, 1)
+#define SET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 28, 2, value)
+#define GET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x08, 28, 2)
+#define SET_TX_DESC_BUFFER_DMA_PRI(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 27, 1, value)
+#define GET_TX_DESC_BUFFER_DMA_PRI(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x08, 27, 1)
+#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc, value)                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 3, value)
+#define GET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc)                              \
+	LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 3)
+#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc, value)                        \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 16, 8, value)
+#define GET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc)                               \
+	LE_BITS_TO_4BYTE(txdesc + 0x08, 16, 8)
+#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc, value)                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 16, value)
+#define GET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc)                             \
+	LE_BITS_TO_4BYTE(txdesc + 0x08, 0, 16)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc, value)                         \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 16, 15, value)
+#define GET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc)                                \
+	LE_BITS_TO_4BYTE(txdesc + 0x0C, 16, 15)
+#define SET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 11, 5, value)
+#define GET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x0C, 11, 5)
+#define SET_TX_DESC_BUFFER_MBSSID(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 7, 4, value)
+#define GET_TX_DESC_BUFFER_MBSSID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 7, 4)
+#define SET_TX_DESC_BUFFER_BK(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 6, 1, value)
+#define GET_TX_DESC_BUFFER_BK(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 6, 1)
+#define SET_TX_DESC_BUFFER_WHEADER_LEN(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value)
+#define GET_TX_DESC_BUFFER_WHEADER_LEN(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x0C, 0, 5)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_BUFFER_TRY_RATE(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 26, 1, value)
+#define GET_TX_DESC_BUFFER_TRY_RATE(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x10, 26, 1)
+#define SET_TX_DESC_BUFFER_DATA_BW(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 24, 2, value)
+#define GET_TX_DESC_BUFFER_DATA_BW(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x10, 24, 2)
+#define SET_TX_DESC_BUFFER_DATA_SHORT(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 23, 1, value)
+#define GET_TX_DESC_BUFFER_DATA_SHORT(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x10, 23, 1)
+#define SET_TX_DESC_BUFFER_DATARATE(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 16, 7, value)
+#define GET_TX_DESC_BUFFER_DATARATE(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x10, 16, 7)
+#define SET_TX_DESC_BUFFER_TXBF_PATH(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 11, 1, value)
+#define GET_TX_DESC_BUFFER_TXBF_PATH(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x10, 11, 1)
+#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc, value)                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 0, 11, value)
+#define GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc)                         \
+	LE_BITS_TO_4BYTE(txdesc + 0x10, 0, 11)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 31, 1, value)
+#define GET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 31, 1)
+#define SET_TX_DESC_BUFFER_HW_RTS_EN(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 30, 1, value)
+#define GET_TX_DESC_BUFFER_HW_RTS_EN(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 30, 1)
+#define SET_TX_DESC_BUFFER_RTS_EN(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 29, 1, value)
+#define GET_TX_DESC_BUFFER_RTS_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 29, 1)
+#define SET_TX_DESC_BUFFER_CTS2SELF(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 1, value)
+#define GET_TX_DESC_BUFFER_CTS2SELF(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 28, 1)
+#define SET_TX_DESC_BUFFER_TAILPAGE_H(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 4, value)
+#define GET_TX_DESC_BUFFER_TAILPAGE_H(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 24, 4)
+#define SET_TX_DESC_BUFFER_TAILPAGE_L(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 16, 8, value)
+#define GET_TX_DESC_BUFFER_TAILPAGE_L(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 16, 8)
+#define SET_TX_DESC_BUFFER_NAVUSEHDR(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 15, 1, value)
+#define GET_TX_DESC_BUFFER_NAVUSEHDR(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 15, 1)
+#define SET_TX_DESC_BUFFER_BMC(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 14, 1, value)
+#define GET_TX_DESC_BUFFER_BMC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 14, 1)
+#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc, value)                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 8, 6, value)
+#define GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc)                            \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 8, 6)
+#define SET_TX_DESC_BUFFER_HW_AES_IV(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 7, 1, value)
+#define GET_TX_DESC_BUFFER_HW_AES_IV(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 7, 1)
+#define SET_TX_DESC_BUFFER_BT_NULL(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 3, 1, value)
+#define GET_TX_DESC_BUFFER_BT_NULL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 3, 1)
+#define SET_TX_DESC_BUFFER_EN_DESC_ID(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 2, 1, value)
+#define GET_TX_DESC_BUFFER_EN_DESC_ID(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 2, 1)
+#define SET_TX_DESC_BUFFER_SECTYPE(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 0, 2, value)
+#define GET_TX_DESC_BUFFER_SECTYPE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 0, 2)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc, value)                        \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 29, 3, value)
+#define GET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc)                               \
+	LE_BITS_TO_4BYTE(txdesc + 0x18, 29, 3)
+#define SET_TX_DESC_BUFFER_POLLUTED(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 1, value)
+#define GET_TX_DESC_BUFFER_POLLUTED(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 1)
+#define SET_TX_DESC_BUFFER_NULL_1(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 27, 1, value)
+#define GET_TX_DESC_BUFFER_NULL_1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 27, 1)
+#define SET_TX_DESC_BUFFER_NULL_0(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 1, value)
+#define GET_TX_DESC_BUFFER_NULL_0(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 1)
+#define SET_TX_DESC_BUFFER_TRI_FRAME(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 25, 1, value)
+#define GET_TX_DESC_BUFFER_TRI_FRAME(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x18, 25, 1)
+#define SET_TX_DESC_BUFFER_SPE_RPT(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 1, value)
+#define GET_TX_DESC_BUFFER_SPE_RPT(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 1)
+#define SET_TX_DESC_BUFFER_FTM_EN(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 23, 1, value)
+#define GET_TX_DESC_BUFFER_FTM_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 23, 1)
+#define SET_TX_DESC_BUFFER_MU_DATARATE(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 7, value)
+#define GET_TX_DESC_BUFFER_MU_DATARATE(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 7)
+#define SET_TX_DESC_BUFFER_CCA_RTS(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 14, 2, value)
+#define GET_TX_DESC_BUFFER_CCA_RTS(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x18, 14, 2)
+#define SET_TX_DESC_BUFFER_NDPA(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 12, 2, value)
+#define GET_TX_DESC_BUFFER_NDPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 12, 2)
+#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc, value)                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 9, 2, value)
+#define GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc)                            \
+	LE_BITS_TO_4BYTE(txdesc + 0x18, 9, 2)
+#define SET_TX_DESC_BUFFER_P_AID(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 9, value)
+#define GET_TX_DESC_BUFFER_P_AID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 0, 9)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_BUFFER_SW_DEFINE(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 16, 12, value)
+#define GET_TX_DESC_BUFFER_SW_DEFINE(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x1C, 16, 12)
+#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc, value)                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 9, 1, value)
+#define GET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc)                              \
+	LE_BITS_TO_4BYTE(txdesc + 0x1C, 9, 1)
+#define SET_TX_DESC_BUFFER_CTRL_CNT(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 5, 4, value)
+#define GET_TX_DESC_BUFFER_CTRL_CNT(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x1C, 5, 4)
+#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc, value)                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 5, value)
+#define GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc)                        \
+	LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 5)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_BUFFER_PATH_MAPA(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 30, 2, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPA(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 30, 2)
+#define SET_TX_DESC_BUFFER_PATH_MAPB(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 28, 2, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPB(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 28, 2)
+#define SET_TX_DESC_BUFFER_PATH_MAPC(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 26, 2, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPC(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 26, 2)
+#define SET_TX_DESC_BUFFER_PATH_MAPD(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 2, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPD(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 2)
+#define SET_TX_DESC_BUFFER_ANTSEL_A(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 20, 4, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_A(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 20, 4)
+#define SET_TX_DESC_BUFFER_ANTSEL_B(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 4, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_B(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 16, 4)
+#define SET_TX_DESC_BUFFER_ANTSEL_C(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 12, 4, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_C(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 12, 4)
+#define SET_TX_DESC_BUFFER_ANTSEL_D(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 8, 4, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_D(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 8, 4)
+#define SET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 4, 4, value)
+#define GET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 4, 4)
+#define SET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 3, 1, value)
+#define GET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 3, 1)
+#define SET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc, value)                        \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 0, 3, value)
+#define GET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc)                               \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 0, 3)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_BUFFER_VCS_STBC(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 30, 2, value)
+#define GET_TX_DESC_BUFFER_VCS_STBC(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 30, 2)
+#define SET_TX_DESC_BUFFER_DATA_STBC(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 28, 2, value)
+#define GET_TX_DESC_BUFFER_DATA_STBC(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 28, 2)
+#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc, value)                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 24, 4, value)
+#define GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc)                         \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 24, 4)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc, value)                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 23, 1, value)
+#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc)                         \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 23, 1)
+#define SET_TX_DESC_BUFFER_MHR_CP(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 22, 1, value)
+#define GET_TX_DESC_BUFFER_MHR_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 22, 1)
+#define SET_TX_DESC_BUFFER_SMH_EN(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 21, 1, value)
+#define GET_TX_DESC_BUFFER_SMH_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 21, 1)
+#define SET_TX_DESC_BUFFER_RTSRATE(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 16, 5, value)
+#define GET_TX_DESC_BUFFER_RTSRATE(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 16, 5)
+#define SET_TX_DESC_BUFFER_SMH_CAM(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 8, 8, value)
+#define GET_TX_DESC_BUFFER_SMH_CAM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 8, 8)
+#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc, value)                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 7, 1, value)
+#define GET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc)                              \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 7, 1)
+#define SET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 6, 1, value)
+#define GET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 6, 1)
+#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc, value)                         \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 5, 1, value)
+#define GET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc)                                \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 5, 1)
+#define SET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 4, 1, value)
+#define GET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 4, 1)
+#define SET_TX_DESC_BUFFER_RTS_SHORT(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 3, 1, value)
+#define GET_TX_DESC_BUFFER_RTS_SHORT(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 3, 1)
+#define SET_TX_DESC_BUFFER_DISDATAFB(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 2, 1, value)
+#define GET_TX_DESC_BUFFER_DISDATAFB(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 2, 1)
+#define SET_TX_DESC_BUFFER_DISRTSFB(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 1, 1, value)
+#define GET_TX_DESC_BUFFER_DISRTSFB(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 1, 1)
+#define SET_TX_DESC_BUFFER_EXT_EDCA(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 1, value)
+#define GET_TX_DESC_BUFFER_EXT_EDCA(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 0, 1)
+
+/*TXDESC_WORD10*/
+
+#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc, value)                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 24, 8, value)
+#define GET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc)                              \
+	LE_BITS_TO_4BYTE(txdesc + 0x28, 24, 8)
+#define SET_TX_DESC_BUFFER_SPECIAL_CW(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 23, 1, value)
+#define GET_TX_DESC_BUFFER_SPECIAL_CW(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x28, 23, 1)
+#define SET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 22, 1, value)
+#define GET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x28, 22, 1)
+#define SET_TX_DESC_BUFFER_RAW(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 21, 1, value)
+#define GET_TX_DESC_BUFFER_RAW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 21, 1)
+#define SET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 16, 5, value)
+#define GET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x28, 16, 5)
+#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc, value)                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 8, 8, value)
+#define GET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc)                             \
+	LE_BITS_TO_4BYTE(txdesc + 0x28, 8, 8)
+#define SET_TX_DESC_BUFFER_GF(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 7, 1, value)
+#define GET_TX_DESC_BUFFER_GF(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 7, 1)
+#define SET_TX_DESC_BUFFER_MOREFRAG(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 6, 1, value)
+#define GET_TX_DESC_BUFFER_MOREFRAG(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x28, 6, 1)
+#define SET_TX_DESC_BUFFER_NOACM(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 5, 1, value)
+#define GET_TX_DESC_BUFFER_NOACM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 5, 1)
+#define SET_TX_DESC_BUFFER_HTC(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 4, 1, value)
+#define GET_TX_DESC_BUFFER_HTC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 4, 1)
+#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc, value)                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 3, 1, value)
+#define GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc)                           \
+	LE_BITS_TO_4BYTE(txdesc + 0x28, 3, 1)
+#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc, value)                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 2, 1, value)
+#define GET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc)                             \
+	LE_BITS_TO_4BYTE(txdesc + 0x28, 2, 1)
+#define SET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 0, 2, value)
+#define GET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x28, 0, 2)
+
+/*TXDESC_WORD11*/
+
+#define SET_TX_DESC_BUFFER_ADDR_CAM(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 24, 8, value)
+#define GET_TX_DESC_BUFFER_ADDR_CAM(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x2C, 24, 8)
+#define SET_TX_DESC_BUFFER_SND_TARGET(txdesc, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 16, 8, value)
+#define GET_TX_DESC_BUFFER_SND_TARGET(txdesc)                                  \
+	LE_BITS_TO_4BYTE(txdesc + 0x2C, 16, 8)
+#define SET_TX_DESC_BUFFER_DATA_LDPC(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 15, 1, value)
+#define GET_TX_DESC_BUFFER_DATA_LDPC(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x2C, 15, 1)
+#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc, value)                         \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 14, 1, value)
+#define GET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc)                                \
+	LE_BITS_TO_4BYTE(txdesc + 0x2C, 14, 1)
+#define SET_TX_DESC_BUFFER_G_ID(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 8, 6, value)
+#define GET_TX_DESC_BUFFER_G_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x2C, 8, 6)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc, value)                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 4, 4, value)
+#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc)                         \
+	LE_BITS_TO_4BYTE(txdesc + 0x2C, 4, 4)
+#define SET_TX_DESC_BUFFER_DATA_SC(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 0, 4, value)
+#define GET_TX_DESC_BUFFER_DATA_SC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x2C, 0, 4)
+
+/*TXDESC_WORD12*/
+
+#define SET_TX_DESC_BUFFER_LEN1_L(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x30, 17, 7, value)
+#define GET_TX_DESC_BUFFER_LEN1_L(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x30, 17, 7)
+#define SET_TX_DESC_BUFFER_LEN0(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x30, 4, 13, value)
+#define GET_TX_DESC_BUFFER_LEN0(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x30, 4, 13)
+#define SET_TX_DESC_BUFFER_PKT_NUM(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x30, 0, 4, value)
+#define GET_TX_DESC_BUFFER_PKT_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x30, 0, 4)
+
+/*TXDESC_WORD13*/
+
+#define SET_TX_DESC_BUFFER_LEN3(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x34, 19, 13, value)
+#define GET_TX_DESC_BUFFER_LEN3(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x34, 19, 13)
+#define SET_TX_DESC_BUFFER_LEN2(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x34, 6, 13, value)
+#define GET_TX_DESC_BUFFER_LEN2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x34, 6, 13)
+#define SET_TX_DESC_BUFFER_LEN1_H(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x34, 0, 6, value)
+#define GET_TX_DESC_BUFFER_LEN1_H(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x34, 0, 6)
+
+#endif
+
+#endif

hal/halmac/halmac_tx_desc_ie_chip.h

@@ -0,0 +1,438 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_IE_CHIP_H_
+#define _HALMAC_TX_DESC_IE_CHIP_H_
+#if (HALMAC_8814B_SUPPORT)
+
+#define IE0_GET_TX_DESC_IE_END_8814B(txdesc_ie)                                \
+	IE0_GET_TX_DESC_IE_END(txdesc_ie)
+#define IE0_SET_TX_DESC_IE_END_8814B(txdesc_ie, value)                         \
+	IE0_SET_TX_DESC_IE_END(txdesc_ie, value)
+#define IE0_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE0_GET_TX_DESC_IE_UP(txdesc_ie)
+#define IE0_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value)                          \
+	IE0_SET_TX_DESC_IE_UP(txdesc_ie, value)
+#define IE0_GET_TX_DESC_IE_NUM_8814B(txdesc_ie)                                \
+	IE0_GET_TX_DESC_IE_NUM(txdesc_ie)
+#define IE0_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value)                         \
+	IE0_SET_TX_DESC_IE_NUM(txdesc_ie, value)
+#define IE0_GET_TX_DESC_ARFR_TABLE_SEL_8814B(txdesc_ie)                        \
+	IE0_GET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie)
+#define IE0_SET_TX_DESC_ARFR_TABLE_SEL_8814B(txdesc_ie, value)                 \
+	IE0_SET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie, value)
+#define IE0_GET_TX_DESC_ARFR_HT_EN_8814B(txdesc_ie)                            \
+	IE0_GET_TX_DESC_ARFR_HT_EN(txdesc_ie)
+#define IE0_SET_TX_DESC_ARFR_HT_EN_8814B(txdesc_ie, value)                     \
+	IE0_SET_TX_DESC_ARFR_HT_EN(txdesc_ie, value)
+#define IE0_GET_TX_DESC_ARFR_OFDM_EN_8814B(txdesc_ie)                          \
+	IE0_GET_TX_DESC_ARFR_OFDM_EN(txdesc_ie)
+#define IE0_SET_TX_DESC_ARFR_OFDM_EN_8814B(txdesc_ie, value)                   \
+	IE0_SET_TX_DESC_ARFR_OFDM_EN(txdesc_ie, value)
+#define IE0_GET_TX_DESC_ARFR_CCK_EN_8814B(txdesc_ie)                           \
+	IE0_GET_TX_DESC_ARFR_CCK_EN(txdesc_ie)
+#define IE0_SET_TX_DESC_ARFR_CCK_EN_8814B(txdesc_ie, value)                    \
+	IE0_SET_TX_DESC_ARFR_CCK_EN(txdesc_ie, value)
+#define IE0_GET_TX_DESC_HW_RTS_EN_8814B(txdesc_ie)                             \
+	IE0_GET_TX_DESC_HW_RTS_EN(txdesc_ie)
+#define IE0_SET_TX_DESC_HW_RTS_EN_8814B(txdesc_ie, value)                      \
+	IE0_SET_TX_DESC_HW_RTS_EN(txdesc_ie, value)
+#define IE0_GET_TX_DESC_RTS_EN_8814B(txdesc_ie)                                \
+	IE0_GET_TX_DESC_RTS_EN(txdesc_ie)
+#define IE0_SET_TX_DESC_RTS_EN_8814B(txdesc_ie, value)                         \
+	IE0_SET_TX_DESC_RTS_EN(txdesc_ie, value)
+#define IE0_GET_TX_DESC_CTS2SELF_8814B(txdesc_ie)                              \
+	IE0_GET_TX_DESC_CTS2SELF(txdesc_ie)
+#define IE0_SET_TX_DESC_CTS2SELF_8814B(txdesc_ie, value)                       \
+	IE0_SET_TX_DESC_CTS2SELF(txdesc_ie, value)
+#define IE0_GET_TX_DESC_RTY_LMT_EN_8814B(txdesc_ie)                            \
+	IE0_GET_TX_DESC_RTY_LMT_EN(txdesc_ie)
+#define IE0_SET_TX_DESC_RTY_LMT_EN_8814B(txdesc_ie, value)                     \
+	IE0_SET_TX_DESC_RTY_LMT_EN(txdesc_ie, value)
+#define IE0_GET_TX_DESC_RTS_SHORT_8814B(txdesc_ie)                             \
+	IE0_GET_TX_DESC_RTS_SHORT(txdesc_ie)
+#define IE0_SET_TX_DESC_RTS_SHORT_8814B(txdesc_ie, value)                      \
+	IE0_SET_TX_DESC_RTS_SHORT(txdesc_ie, value)
+#define IE0_GET_TX_DESC_DISDATAFB_8814B(txdesc_ie)                             \
+	IE0_GET_TX_DESC_DISDATAFB(txdesc_ie)
+#define IE0_SET_TX_DESC_DISDATAFB_8814B(txdesc_ie, value)                      \
+	IE0_SET_TX_DESC_DISDATAFB(txdesc_ie, value)
+#define IE0_GET_TX_DESC_DISRTSFB_8814B(txdesc_ie)                              \
+	IE0_GET_TX_DESC_DISRTSFB(txdesc_ie)
+#define IE0_SET_TX_DESC_DISRTSFB_8814B(txdesc_ie, value)                       \
+	IE0_SET_TX_DESC_DISRTSFB(txdesc_ie, value)
+#define IE0_GET_TX_DESC_DATA_SHORT_8814B(txdesc_ie)                            \
+	IE0_GET_TX_DESC_DATA_SHORT(txdesc_ie)
+#define IE0_SET_TX_DESC_DATA_SHORT_8814B(txdesc_ie, value)                     \
+	IE0_SET_TX_DESC_DATA_SHORT(txdesc_ie, value)
+#define IE0_GET_TX_DESC_TRY_RATE_8814B(txdesc_ie)                              \
+	IE0_GET_TX_DESC_TRY_RATE(txdesc_ie)
+#define IE0_SET_TX_DESC_TRY_RATE_8814B(txdesc_ie, value)                       \
+	IE0_SET_TX_DESC_TRY_RATE(txdesc_ie, value)
+#define IE0_GET_TX_DESC_USERATE_8814B(txdesc_ie)                               \
+	IE0_GET_TX_DESC_USERATE(txdesc_ie)
+#define IE0_SET_TX_DESC_USERATE_8814B(txdesc_ie, value)                        \
+	IE0_SET_TX_DESC_USERATE(txdesc_ie, value)
+#define IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE_8814B(txdesc_ie)                   \
+	IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie)
+#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE_8814B(txdesc_ie, value)            \
+	IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie, value)
+#define IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE_8814B(txdesc_ie)                  \
+	IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie)
+#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE_8814B(txdesc_ie, value)           \
+	IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie, value)
+#define IE0_GET_TX_DESC_RTS_DATA_RTY_LMT_8814B(txdesc_ie)                      \
+	IE0_GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie)
+#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT_8814B(txdesc_ie, value)               \
+	IE0_SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie, value)
+#define IE0_GET_TX_DESC_DATA_BW_8814B(txdesc_ie)                               \
+	IE0_GET_TX_DESC_DATA_BW(txdesc_ie)
+#define IE0_SET_TX_DESC_DATA_BW_8814B(txdesc_ie, value)                        \
+	IE0_SET_TX_DESC_DATA_BW(txdesc_ie, value)
+#define IE0_GET_TX_DESC_RTSRATE_8814B(txdesc_ie)                               \
+	IE0_GET_TX_DESC_RTSRATE(txdesc_ie)
+#define IE0_SET_TX_DESC_RTSRATE_8814B(txdesc_ie, value)                        \
+	IE0_SET_TX_DESC_RTSRATE(txdesc_ie, value)
+#define IE0_GET_TX_DESC_DATARATE_8814B(txdesc_ie)                              \
+	IE0_GET_TX_DESC_DATARATE(txdesc_ie)
+#define IE0_SET_TX_DESC_DATARATE_8814B(txdesc_ie, value)                       \
+	IE0_SET_TX_DESC_DATARATE(txdesc_ie, value)
+#define IE1_GET_TX_DESC_IE_END_8814B(txdesc_ie)                                \
+	IE1_GET_TX_DESC_IE_END(txdesc_ie)
+#define IE1_SET_TX_DESC_IE_END_8814B(txdesc_ie, value)                         \
+	IE1_SET_TX_DESC_IE_END(txdesc_ie, value)
+#define IE1_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE1_GET_TX_DESC_IE_UP(txdesc_ie)
+#define IE1_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value)                          \
+	IE1_SET_TX_DESC_IE_UP(txdesc_ie, value)
+#define IE1_GET_TX_DESC_IE_NUM_8814B(txdesc_ie)                                \
+	IE1_GET_TX_DESC_IE_NUM(txdesc_ie)
+#define IE1_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value)                         \
+	IE1_SET_TX_DESC_IE_NUM(txdesc_ie, value)
+#define IE1_GET_TX_DESC_AMPDU_DENSITY_8814B(txdesc_ie)                         \
+	IE1_GET_TX_DESC_AMPDU_DENSITY(txdesc_ie)
+#define IE1_SET_TX_DESC_AMPDU_DENSITY_8814B(txdesc_ie, value)                  \
+	IE1_SET_TX_DESC_AMPDU_DENSITY(txdesc_ie, value)
+#define IE1_GET_TX_DESC_MAX_AGG_NUM_8814B(txdesc_ie)                           \
+	IE1_GET_TX_DESC_MAX_AGG_NUM(txdesc_ie)
+#define IE1_SET_TX_DESC_MAX_AGG_NUM_8814B(txdesc_ie, value)                    \
+	IE1_SET_TX_DESC_MAX_AGG_NUM(txdesc_ie, value)
+#define IE1_GET_TX_DESC_SECTYPE_8814B(txdesc_ie)                               \
+	IE1_GET_TX_DESC_SECTYPE(txdesc_ie)
+#define IE1_SET_TX_DESC_SECTYPE_8814B(txdesc_ie, value)                        \
+	IE1_SET_TX_DESC_SECTYPE(txdesc_ie, value)
+#define IE1_GET_TX_DESC_MOREFRAG_8814B(txdesc_ie)                              \
+	IE1_GET_TX_DESC_MOREFRAG(txdesc_ie)
+#define IE1_SET_TX_DESC_MOREFRAG_8814B(txdesc_ie, value)                       \
+	IE1_SET_TX_DESC_MOREFRAG(txdesc_ie, value)
+#define IE1_GET_TX_DESC_NOACM_8814B(txdesc_ie) IE1_GET_TX_DESC_NOACM(txdesc_ie)
+#define IE1_SET_TX_DESC_NOACM_8814B(txdesc_ie, value)                          \
+	IE1_SET_TX_DESC_NOACM(txdesc_ie, value)
+#define IE1_GET_TX_DESC_BCNPKT_TSF_CTRL_8814B(txdesc_ie)                       \
+	IE1_GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie)
+#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL_8814B(txdesc_ie, value)                \
+	IE1_SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie, value)
+#define IE1_GET_TX_DESC_NAVUSEHDR_8814B(txdesc_ie)                             \
+	IE1_GET_TX_DESC_NAVUSEHDR(txdesc_ie)
+#define IE1_SET_TX_DESC_NAVUSEHDR_8814B(txdesc_ie, value)                      \
+	IE1_SET_TX_DESC_NAVUSEHDR(txdesc_ie, value)
+#define IE1_GET_TX_DESC_HTC_8814B(txdesc_ie) IE1_GET_TX_DESC_HTC(txdesc_ie)
+#define IE1_SET_TX_DESC_HTC_8814B(txdesc_ie, value)                            \
+	IE1_SET_TX_DESC_HTC(txdesc_ie, value)
+#define IE1_GET_TX_DESC_BMC_8814B(txdesc_ie) IE1_GET_TX_DESC_BMC(txdesc_ie)
+#define IE1_SET_TX_DESC_BMC_8814B(txdesc_ie, value)                            \
+	IE1_SET_TX_DESC_BMC(txdesc_ie, value)
+#define IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS_8814B(txdesc_ie)                     \
+	IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie)
+#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS_8814B(txdesc_ie, value)              \
+	IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie, value)
+#define IE1_GET_TX_DESC_USE_MAX_TIME_EN_8814B(txdesc_ie)                       \
+	IE1_GET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie)
+#define IE1_SET_TX_DESC_USE_MAX_TIME_EN_8814B(txdesc_ie, value)                \
+	IE1_SET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie, value)
+#define IE1_GET_TX_DESC_HW_SSN_SEL_8814B(txdesc_ie)                            \
+	IE1_GET_TX_DESC_HW_SSN_SEL(txdesc_ie)
+#define IE1_SET_TX_DESC_HW_SSN_SEL_8814B(txdesc_ie, value)                     \
+	IE1_SET_TX_DESC_HW_SSN_SEL(txdesc_ie, value)
+#define IE1_GET_TX_DESC_DISQSELSEQ_8814B(txdesc_ie)                            \
+	IE1_GET_TX_DESC_DISQSELSEQ(txdesc_ie)
+#define IE1_SET_TX_DESC_DISQSELSEQ_8814B(txdesc_ie, value)                     \
+	IE1_SET_TX_DESC_DISQSELSEQ(txdesc_ie, value)
+#define IE1_GET_TX_DESC_EN_HWSEQ_8814B(txdesc_ie)                              \
+	IE1_GET_TX_DESC_EN_HWSEQ(txdesc_ie)
+#define IE1_SET_TX_DESC_EN_HWSEQ_8814B(txdesc_ie, value)                       \
+	IE1_SET_TX_DESC_EN_HWSEQ(txdesc_ie, value)
+#define IE1_GET_TX_DESC_EN_HWEXSEQ_8814B(txdesc_ie)                            \
+	IE1_GET_TX_DESC_EN_HWEXSEQ(txdesc_ie)
+#define IE1_SET_TX_DESC_EN_HWEXSEQ_8814B(txdesc_ie, value)                     \
+	IE1_SET_TX_DESC_EN_HWEXSEQ(txdesc_ie, value)
+#define IE1_GET_TX_DESC_EN_DESC_ID_8814B(txdesc_ie)                            \
+	IE1_GET_TX_DESC_EN_DESC_ID(txdesc_ie)
+#define IE1_SET_TX_DESC_EN_DESC_ID_8814B(txdesc_ie, value)                     \
+	IE1_SET_TX_DESC_EN_DESC_ID(txdesc_ie, value)
+#define IE1_GET_TX_DESC_AMPDU_MAX_TIME_8814B(txdesc_ie)                        \
+	IE1_GET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie)
+#define IE1_SET_TX_DESC_AMPDU_MAX_TIME_8814B(txdesc_ie, value)                 \
+	IE1_SET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie, value)
+#define IE1_GET_TX_DESC_P_AID_8814B(txdesc_ie) IE1_GET_TX_DESC_P_AID(txdesc_ie)
+#define IE1_SET_TX_DESC_P_AID_8814B(txdesc_ie, value)                          \
+	IE1_SET_TX_DESC_P_AID(txdesc_ie, value)
+#define IE1_GET_TX_DESC_MOREDATA_8814B(txdesc_ie)                              \
+	IE1_GET_TX_DESC_MOREDATA(txdesc_ie)
+#define IE1_SET_TX_DESC_MOREDATA_8814B(txdesc_ie, value)                       \
+	IE1_SET_TX_DESC_MOREDATA(txdesc_ie, value)
+#define IE1_GET_TX_DESC_SW_SEQ_8814B(txdesc_ie)                                \
+	IE1_GET_TX_DESC_SW_SEQ(txdesc_ie)
+#define IE1_SET_TX_DESC_SW_SEQ_8814B(txdesc_ie, value)                         \
+	IE1_SET_TX_DESC_SW_SEQ(txdesc_ie, value)
+#define IE2_GET_TX_DESC_IE_END_8814B(txdesc_ie)                                \
+	IE2_GET_TX_DESC_IE_END(txdesc_ie)
+#define IE2_SET_TX_DESC_IE_END_8814B(txdesc_ie, value)                         \
+	IE2_SET_TX_DESC_IE_END(txdesc_ie, value)
+#define IE2_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE2_GET_TX_DESC_IE_UP(txdesc_ie)
+#define IE2_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value)                          \
+	IE2_SET_TX_DESC_IE_UP(txdesc_ie, value)
+#define IE2_GET_TX_DESC_IE_NUM_8814B(txdesc_ie)                                \
+	IE2_GET_TX_DESC_IE_NUM(txdesc_ie)
+#define IE2_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value)                         \
+	IE2_SET_TX_DESC_IE_NUM(txdesc_ie, value)
+#define IE2_GET_TX_DESC_ADDR_CAM_8814B(txdesc_ie)                              \
+	IE2_GET_TX_DESC_ADDR_CAM(txdesc_ie)
+#define IE2_SET_TX_DESC_ADDR_CAM_8814B(txdesc_ie, value)                       \
+	IE2_SET_TX_DESC_ADDR_CAM(txdesc_ie, value)
+#define IE2_GET_TX_DESC_MULTIPLE_PORT_8814B(txdesc_ie)                         \
+	IE2_GET_TX_DESC_MULTIPLE_PORT(txdesc_ie)
+#define IE2_SET_TX_DESC_MULTIPLE_PORT_8814B(txdesc_ie, value)                  \
+	IE2_SET_TX_DESC_MULTIPLE_PORT(txdesc_ie, value)
+#define IE2_GET_TX_DESC_RAW_8814B(txdesc_ie) IE2_GET_TX_DESC_RAW(txdesc_ie)
+#define IE2_SET_TX_DESC_RAW_8814B(txdesc_ie, value)                            \
+	IE2_SET_TX_DESC_RAW(txdesc_ie, value)
+#define IE2_GET_TX_DESC_RDG_EN_8814B(txdesc_ie)                                \
+	IE2_GET_TX_DESC_RDG_EN(txdesc_ie)
+#define IE2_SET_TX_DESC_RDG_EN_8814B(txdesc_ie, value)                         \
+	IE2_SET_TX_DESC_RDG_EN(txdesc_ie, value)
+#define IE2_GET_TX_DESC_SPECIAL_CW_8814B(txdesc_ie)                            \
+	IE2_GET_TX_DESC_SPECIAL_CW(txdesc_ie)
+#define IE2_SET_TX_DESC_SPECIAL_CW_8814B(txdesc_ie, value)                     \
+	IE2_SET_TX_DESC_SPECIAL_CW(txdesc_ie, value)
+#define IE2_GET_TX_DESC_POLLUTED_8814B(txdesc_ie)                              \
+	IE2_GET_TX_DESC_POLLUTED(txdesc_ie)
+#define IE2_SET_TX_DESC_POLLUTED_8814B(txdesc_ie, value)                       \
+	IE2_SET_TX_DESC_POLLUTED(txdesc_ie, value)
+#define IE2_GET_TX_DESC_BT_NULL_8814B(txdesc_ie)                               \
+	IE2_GET_TX_DESC_BT_NULL(txdesc_ie)
+#define IE2_SET_TX_DESC_BT_NULL_8814B(txdesc_ie, value)                        \
+	IE2_SET_TX_DESC_BT_NULL(txdesc_ie, value)
+#define IE2_GET_TX_DESC_NULL_1_8814B(txdesc_ie)                                \
+	IE2_GET_TX_DESC_NULL_1(txdesc_ie)
+#define IE2_SET_TX_DESC_NULL_1_8814B(txdesc_ie, value)                         \
+	IE2_SET_TX_DESC_NULL_1(txdesc_ie, value)
+#define IE2_GET_TX_DESC_NULL_0_8814B(txdesc_ie)                                \
+	IE2_GET_TX_DESC_NULL_0(txdesc_ie)
+#define IE2_SET_TX_DESC_NULL_0_8814B(txdesc_ie, value)                         \
+	IE2_SET_TX_DESC_NULL_0(txdesc_ie, value)
+#define IE2_GET_TX_DESC_TRI_FRAME_8814B(txdesc_ie)                             \
+	IE2_GET_TX_DESC_TRI_FRAME(txdesc_ie)
+#define IE2_SET_TX_DESC_TRI_FRAME_8814B(txdesc_ie, value)                      \
+	IE2_SET_TX_DESC_TRI_FRAME(txdesc_ie, value)
+#define IE2_GET_TX_DESC_SPE_RPT_8814B(txdesc_ie)                               \
+	IE2_GET_TX_DESC_SPE_RPT(txdesc_ie)
+#define IE2_SET_TX_DESC_SPE_RPT_8814B(txdesc_ie, value)                        \
+	IE2_SET_TX_DESC_SPE_RPT(txdesc_ie, value)
+#define IE2_GET_TX_DESC_FTM_EN_8814B(txdesc_ie)                                \
+	IE2_GET_TX_DESC_FTM_EN(txdesc_ie)
+#define IE2_SET_TX_DESC_FTM_EN_8814B(txdesc_ie, value)                         \
+	IE2_SET_TX_DESC_FTM_EN(txdesc_ie, value)
+#define IE2_GET_TX_DESC_MBSSID_8814B(txdesc_ie)                                \
+	IE2_GET_TX_DESC_MBSSID(txdesc_ie)
+#define IE2_SET_TX_DESC_MBSSID_8814B(txdesc_ie, value)                         \
+	IE2_SET_TX_DESC_MBSSID(txdesc_ie, value)
+#define IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET_8814B(txdesc_ie)                   \
+	IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie)
+#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET_8814B(txdesc_ie, value)            \
+	IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie, value)
+#define IE2_GET_TX_DESC_RDG_NAV_EXT_8814B(txdesc_ie)                           \
+	IE2_GET_TX_DESC_RDG_NAV_EXT(txdesc_ie)
+#define IE2_SET_TX_DESC_RDG_NAV_EXT_8814B(txdesc_ie, value)                    \
+	IE2_SET_TX_DESC_RDG_NAV_EXT(txdesc_ie, value)
+#define IE2_GET_TX_DESC_DROP_ID_8814B(txdesc_ie)                               \
+	IE2_GET_TX_DESC_DROP_ID(txdesc_ie)
+#define IE2_SET_TX_DESC_DROP_ID_8814B(txdesc_ie, value)                        \
+	IE2_SET_TX_DESC_DROP_ID(txdesc_ie, value)
+#define IE2_GET_TX_DESC_SW_DEFINE_8814B(txdesc_ie)                             \
+	IE2_GET_TX_DESC_SW_DEFINE(txdesc_ie)
+#define IE2_SET_TX_DESC_SW_DEFINE_8814B(txdesc_ie, value)                      \
+	IE2_SET_TX_DESC_SW_DEFINE(txdesc_ie, value)
+#define IE3_GET_TX_DESC_IE_END_8814B(txdesc_ie)                                \
+	IE3_GET_TX_DESC_IE_END(txdesc_ie)
+#define IE3_SET_TX_DESC_IE_END_8814B(txdesc_ie, value)                         \
+	IE3_SET_TX_DESC_IE_END(txdesc_ie, value)
+#define IE3_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE3_GET_TX_DESC_IE_UP(txdesc_ie)
+#define IE3_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value)                          \
+	IE3_SET_TX_DESC_IE_UP(txdesc_ie, value)
+#define IE3_GET_TX_DESC_IE_NUM_8814B(txdesc_ie)                                \
+	IE3_GET_TX_DESC_IE_NUM(txdesc_ie)
+#define IE3_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value)                         \
+	IE3_SET_TX_DESC_IE_NUM(txdesc_ie, value)
+#define IE3_GET_TX_DESC_DATA_SC_8814B(txdesc_ie)                               \
+	IE3_GET_TX_DESC_DATA_SC(txdesc_ie)
+#define IE3_SET_TX_DESC_DATA_SC_8814B(txdesc_ie, value)                        \
+	IE3_SET_TX_DESC_DATA_SC(txdesc_ie, value)
+#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC_8814B(txdesc_ie)                   \
+	IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC_8814B(txdesc_ie, value)            \
+	IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie, value)
+#define IE3_GET_TX_DESC_CTRL_CNT_8814B(txdesc_ie)                              \
+	IE3_GET_TX_DESC_CTRL_CNT(txdesc_ie)
+#define IE3_SET_TX_DESC_CTRL_CNT_8814B(txdesc_ie, value)                       \
+	IE3_SET_TX_DESC_CTRL_CNT(txdesc_ie, value)
+#define IE3_GET_TX_DESC_CTRL_CNT_VALID_8814B(txdesc_ie)                        \
+	IE3_GET_TX_DESC_CTRL_CNT_VALID(txdesc_ie)
+#define IE3_SET_TX_DESC_CTRL_CNT_VALID_8814B(txdesc_ie, value)                 \
+	IE3_SET_TX_DESC_CTRL_CNT_VALID(txdesc_ie, value)
+#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN_8814B(txdesc_ie)                   \
+	IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN_8814B(txdesc_ie, value)            \
+	IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie, value)
+#define IE3_GET_TX_DESC_G_ID_8814B(txdesc_ie) IE3_GET_TX_DESC_G_ID(txdesc_ie)
+#define IE3_SET_TX_DESC_G_ID_8814B(txdesc_ie, value)                           \
+	IE3_SET_TX_DESC_G_ID(txdesc_ie, value)
+#define IE3_GET_TX_DESC_SND_TARGET_8814B(txdesc_ie)                            \
+	IE3_GET_TX_DESC_SND_TARGET(txdesc_ie)
+#define IE3_SET_TX_DESC_SND_TARGET_8814B(txdesc_ie, value)                     \
+	IE3_SET_TX_DESC_SND_TARGET(txdesc_ie, value)
+#define IE3_GET_TX_DESC_CCA_RTS_8814B(txdesc_ie)                               \
+	IE3_GET_TX_DESC_CCA_RTS(txdesc_ie)
+#define IE3_SET_TX_DESC_CCA_RTS_8814B(txdesc_ie, value)                        \
+	IE3_SET_TX_DESC_CCA_RTS(txdesc_ie, value)
+#define IE3_GET_TX_DESC_SND_PKT_SEL_8814B(txdesc_ie)                           \
+	IE3_GET_TX_DESC_SND_PKT_SEL(txdesc_ie)
+#define IE3_SET_TX_DESC_SND_PKT_SEL_8814B(txdesc_ie, value)                    \
+	IE3_SET_TX_DESC_SND_PKT_SEL(txdesc_ie, value)
+#define IE3_GET_TX_DESC_NDPA_8814B(txdesc_ie) IE3_GET_TX_DESC_NDPA(txdesc_ie)
+#define IE3_SET_TX_DESC_NDPA_8814B(txdesc_ie, value)                           \
+	IE3_SET_TX_DESC_NDPA(txdesc_ie, value)
+#define IE3_GET_TX_DESC_MU_DATARATE_8814B(txdesc_ie)                           \
+	IE3_GET_TX_DESC_MU_DATARATE(txdesc_ie)
+#define IE3_SET_TX_DESC_MU_DATARATE_8814B(txdesc_ie, value)                    \
+	IE3_SET_TX_DESC_MU_DATARATE(txdesc_ie, value)
+#define IE4_GET_TX_DESC_IE_END_8814B(txdesc_ie)                                \
+	IE4_GET_TX_DESC_IE_END(txdesc_ie)
+#define IE4_SET_TX_DESC_IE_END_8814B(txdesc_ie, value)                         \
+	IE4_SET_TX_DESC_IE_END(txdesc_ie, value)
+#define IE4_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE4_GET_TX_DESC_IE_UP(txdesc_ie)
+#define IE4_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value)                          \
+	IE4_SET_TX_DESC_IE_UP(txdesc_ie, value)
+#define IE4_GET_TX_DESC_IE_NUM_8814B(txdesc_ie)                                \
+	IE4_GET_TX_DESC_IE_NUM(txdesc_ie)
+#define IE4_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value)                         \
+	IE4_SET_TX_DESC_IE_NUM(txdesc_ie, value)
+#define IE4_GET_TX_DESC_VCS_STBC_8814B(txdesc_ie)                              \
+	IE4_GET_TX_DESC_VCS_STBC(txdesc_ie)
+#define IE4_SET_TX_DESC_VCS_STBC_8814B(txdesc_ie, value)                       \
+	IE4_SET_TX_DESC_VCS_STBC(txdesc_ie, value)
+#define IE4_GET_TX_DESC_DATA_STBC_8814B(txdesc_ie)                             \
+	IE4_GET_TX_DESC_DATA_STBC(txdesc_ie)
+#define IE4_SET_TX_DESC_DATA_STBC_8814B(txdesc_ie, value)                      \
+	IE4_SET_TX_DESC_DATA_STBC(txdesc_ie, value)
+#define IE4_GET_TX_DESC_DATA_LDPC_8814B(txdesc_ie)                             \
+	IE4_GET_TX_DESC_DATA_LDPC(txdesc_ie)
+#define IE4_SET_TX_DESC_DATA_LDPC_8814B(txdesc_ie, value)                      \
+	IE4_SET_TX_DESC_DATA_LDPC(txdesc_ie, value)
+#define IE4_GET_TX_DESC_GF_8814B(txdesc_ie) IE4_GET_TX_DESC_GF(txdesc_ie)
+#define IE4_SET_TX_DESC_GF_8814B(txdesc_ie, value)                             \
+	IE4_SET_TX_DESC_GF(txdesc_ie, value)
+#define IE4_GET_TX_DESC_LSIG_TXOP_EN_8814B(txdesc_ie)                          \
+	IE4_GET_TX_DESC_LSIG_TXOP_EN(txdesc_ie)
+#define IE4_SET_TX_DESC_LSIG_TXOP_EN_8814B(txdesc_ie, value)                   \
+	IE4_SET_TX_DESC_LSIG_TXOP_EN(txdesc_ie, value)
+#define IE4_GET_TX_DESC_PATH_MAPA_8814B(txdesc_ie)                             \
+	IE4_GET_TX_DESC_PATH_MAPA(txdesc_ie)
+#define IE4_SET_TX_DESC_PATH_MAPA_8814B(txdesc_ie, value)                      \
+	IE4_SET_TX_DESC_PATH_MAPA(txdesc_ie, value)
+#define IE4_GET_TX_DESC_PATH_MAPB_8814B(txdesc_ie)                             \
+	IE4_GET_TX_DESC_PATH_MAPB(txdesc_ie)
+#define IE4_SET_TX_DESC_PATH_MAPB_8814B(txdesc_ie, value)                      \
+	IE4_SET_TX_DESC_PATH_MAPB(txdesc_ie, value)
+#define IE4_GET_TX_DESC_PATH_MAPC_8814B(txdesc_ie)                             \
+	IE4_GET_TX_DESC_PATH_MAPC(txdesc_ie)
+#define IE4_SET_TX_DESC_PATH_MAPC_8814B(txdesc_ie, value)                      \
+	IE4_SET_TX_DESC_PATH_MAPC(txdesc_ie, value)
+#define IE4_GET_TX_DESC_PATH_MAPD_8814B(txdesc_ie)                             \
+	IE4_GET_TX_DESC_PATH_MAPD(txdesc_ie)
+#define IE4_SET_TX_DESC_PATH_MAPD_8814B(txdesc_ie, value)                      \
+	IE4_SET_TX_DESC_PATH_MAPD(txdesc_ie, value)
+#define IE4_GET_TX_DESC_ANTSEL_A_8814B(txdesc_ie)                              \
+	IE4_GET_TX_DESC_ANTSEL_A(txdesc_ie)
+#define IE4_SET_TX_DESC_ANTSEL_A_8814B(txdesc_ie, value)                       \
+	IE4_SET_TX_DESC_ANTSEL_A(txdesc_ie, value)
+#define IE4_GET_TX_DESC_ANTSEL_B_8814B(txdesc_ie)                              \
+	IE4_GET_TX_DESC_ANTSEL_B(txdesc_ie)
+#define IE4_SET_TX_DESC_ANTSEL_B_8814B(txdesc_ie, value)                       \
+	IE4_SET_TX_DESC_ANTSEL_B(txdesc_ie, value)
+#define IE4_GET_TX_DESC_ANTSEL_C_8814B(txdesc_ie)                              \
+	IE4_GET_TX_DESC_ANTSEL_C(txdesc_ie)
+#define IE4_SET_TX_DESC_ANTSEL_C_8814B(txdesc_ie, value)                       \
+	IE4_SET_TX_DESC_ANTSEL_C(txdesc_ie, value)
+#define IE4_GET_TX_DESC_ANTSEL_D_8814B(txdesc_ie)                              \
+	IE4_GET_TX_DESC_ANTSEL_D(txdesc_ie)
+#define IE4_SET_TX_DESC_ANTSEL_D_8814B(txdesc_ie, value)                       \
+	IE4_SET_TX_DESC_ANTSEL_D(txdesc_ie, value)
+#define IE4_GET_TX_DESC_NTX_PATH_EN_8814B(txdesc_ie)                           \
+	IE4_GET_TX_DESC_NTX_PATH_EN(txdesc_ie)
+#define IE4_SET_TX_DESC_NTX_PATH_EN_8814B(txdesc_ie, value)                    \
+	IE4_SET_TX_DESC_NTX_PATH_EN(txdesc_ie, value)
+#define IE4_GET_TX_DESC_ANTLSEL_EN_8814B(txdesc_ie)                            \
+	IE4_GET_TX_DESC_ANTLSEL_EN(txdesc_ie)
+#define IE4_SET_TX_DESC_ANTLSEL_EN_8814B(txdesc_ie, value)                     \
+	IE4_SET_TX_DESC_ANTLSEL_EN(txdesc_ie, value)
+#define IE4_GET_TX_DESC_TXPWR_OFSET_TYPE_8814B(txdesc_ie)                      \
+	IE4_GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie)
+#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE_8814B(txdesc_ie, value)               \
+	IE4_SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie, value)
+#define IE5_GET_TX_DESC_IE_END_8814B(txdesc_ie)                                \
+	IE5_GET_TX_DESC_IE_END(txdesc_ie)
+#define IE5_SET_TX_DESC_IE_END_8814B(txdesc_ie, value)                         \
+	IE5_SET_TX_DESC_IE_END(txdesc_ie, value)
+#define IE5_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE5_GET_TX_DESC_IE_UP(txdesc_ie)
+#define IE5_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value)                          \
+	IE5_SET_TX_DESC_IE_UP(txdesc_ie, value)
+#define IE5_GET_TX_DESC_IE_NUM_8814B(txdesc_ie)                                \
+	IE5_GET_TX_DESC_IE_NUM(txdesc_ie)
+#define IE5_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value)                         \
+	IE5_SET_TX_DESC_IE_NUM(txdesc_ie, value)
+#define IE5_GET_TX_DESC_LEN1_L_8814B(txdesc_ie)                                \
+	IE5_GET_TX_DESC_LEN1_L(txdesc_ie)
+#define IE5_SET_TX_DESC_LEN1_L_8814B(txdesc_ie, value)                         \
+	IE5_SET_TX_DESC_LEN1_L(txdesc_ie, value)
+#define IE5_GET_TX_DESC_LEN0_8814B(txdesc_ie) IE5_GET_TX_DESC_LEN0(txdesc_ie)
+#define IE5_SET_TX_DESC_LEN0_8814B(txdesc_ie, value)                           \
+	IE5_SET_TX_DESC_LEN0(txdesc_ie, value)
+#define IE5_GET_TX_DESC_PKT_NUM_8814B(txdesc_ie)                               \
+	IE5_GET_TX_DESC_PKT_NUM(txdesc_ie)
+#define IE5_SET_TX_DESC_PKT_NUM_8814B(txdesc_ie, value)                        \
+	IE5_SET_TX_DESC_PKT_NUM(txdesc_ie, value)
+#define IE5_GET_TX_DESC_LEN3_8814B(txdesc_ie) IE5_GET_TX_DESC_LEN3(txdesc_ie)
+#define IE5_SET_TX_DESC_LEN3_8814B(txdesc_ie, value)                           \
+	IE5_SET_TX_DESC_LEN3(txdesc_ie, value)
+#define IE5_GET_TX_DESC_LEN2_8814B(txdesc_ie) IE5_GET_TX_DESC_LEN2(txdesc_ie)
+#define IE5_SET_TX_DESC_LEN2_8814B(txdesc_ie, value)                           \
+	IE5_SET_TX_DESC_LEN2(txdesc_ie, value)
+#define IE5_GET_TX_DESC_LEN1_H_8814B(txdesc_ie)                                \
+	IE5_GET_TX_DESC_LEN1_H(txdesc_ie)
+#define IE5_SET_TX_DESC_LEN1_H_8814B(txdesc_ie, value)                         \
+	IE5_SET_TX_DESC_LEN1_H(txdesc_ie, value)
+
+#endif
+
+#endif

hal/halmac/halmac_tx_desc_ie_nic.h

@@ -0,0 +1,450 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_IE_NIC_H_
+#define _HALMAC_TX_DESC_IE_NIC_H_
+#if (HALMAC_8814B_SUPPORT)
+
+#define IE0_GET_TX_DESC_IE_END(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)
+#define IE0_SET_TX_DESC_IE_END(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)
+#define IE0_GET_TX_DESC_IE_UP(txdesc_ie)                                       \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)
+#define IE0_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)
+#define IE0_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)
+#define IE0_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)
+#define IE0_GET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie)                              \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 19, 1)
+#define IE0_SET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie, value)                       \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 19, 1, value)
+#define IE0_GET_TX_DESC_ARFR_HT_EN(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 18, 1)
+#define IE0_SET_TX_DESC_ARFR_HT_EN(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 18, 1, value)
+#define IE0_GET_TX_DESC_ARFR_OFDM_EN(txdesc_ie)                                \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 17, 1)
+#define IE0_SET_TX_DESC_ARFR_OFDM_EN(txdesc_ie, value)                         \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 17, 1, value)
+#define IE0_GET_TX_DESC_ARFR_CCK_EN(txdesc_ie)                                 \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 1)
+#define IE0_SET_TX_DESC_ARFR_CCK_EN(txdesc_ie, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 1, value)
+#define IE0_GET_TX_DESC_HW_RTS_EN(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 9, 1)
+#define IE0_SET_TX_DESC_HW_RTS_EN(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 9, 1, value)
+#define IE0_GET_TX_DESC_RTS_EN(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 1)
+#define IE0_SET_TX_DESC_RTS_EN(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 1, value)
+#define IE0_GET_TX_DESC_CTS2SELF(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 7, 1)
+#define IE0_SET_TX_DESC_CTS2SELF(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 7, 1, value)
+#define IE0_GET_TX_DESC_RTY_LMT_EN(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 6, 1)
+#define IE0_SET_TX_DESC_RTY_LMT_EN(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 6, 1, value)
+#define IE0_GET_TX_DESC_RTS_SHORT(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 5, 1)
+#define IE0_SET_TX_DESC_RTS_SHORT(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 5, 1, value)
+#define IE0_GET_TX_DESC_DISDATAFB(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 1)
+#define IE0_SET_TX_DESC_DISDATAFB(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 1, value)
+#define IE0_GET_TX_DESC_DISRTSFB(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 3, 1)
+#define IE0_SET_TX_DESC_DISRTSFB(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 3, 1, value)
+#define IE0_GET_TX_DESC_DATA_SHORT(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1)
+#define IE0_SET_TX_DESC_DATA_SHORT(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value)
+#define IE0_GET_TX_DESC_TRY_RATE(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)
+#define IE0_SET_TX_DESC_TRY_RATE(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)
+#define IE0_GET_TX_DESC_USERATE(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)
+#define IE0_SET_TX_DESC_USERATE(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)
+#define IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie)                         \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 27, 4)
+#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie, value)                  \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 27, 4, value)
+#define IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie)                        \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 22, 5)
+#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie, value)                 \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 22, 5, value)
+#define IE0_GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie)                            \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 6)
+#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie, value)                     \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 6, value)
+#define IE0_GET_TX_DESC_DATA_BW(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 12, 2)
+#define IE0_SET_TX_DESC_DATA_BW(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 12, 2, value)
+#define IE0_GET_TX_DESC_RTSRATE(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 7, 4)
+#define IE0_SET_TX_DESC_RTSRATE(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 7, 4, value)
+#define IE0_GET_TX_DESC_DATARATE(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 7)
+#define IE0_SET_TX_DESC_DATARATE(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 7, value)
+#define IE1_GET_TX_DESC_IE_END(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)
+#define IE1_SET_TX_DESC_IE_END(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)
+#define IE1_GET_TX_DESC_IE_UP(txdesc_ie)                                       \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)
+#define IE1_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)
+#define IE1_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)
+#define IE1_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)
+#define IE1_GET_TX_DESC_AMPDU_DENSITY(txdesc_ie)                               \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 21, 3)
+#define IE1_SET_TX_DESC_AMPDU_DENSITY(txdesc_ie, value)                        \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 21, 3, value)
+#define IE1_GET_TX_DESC_MAX_AGG_NUM(txdesc_ie)                                 \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 5)
+#define IE1_SET_TX_DESC_MAX_AGG_NUM(txdesc_ie, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 5, value)
+#define IE1_GET_TX_DESC_SECTYPE(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 14, 2)
+#define IE1_SET_TX_DESC_SECTYPE(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 14, 2, value)
+#define IE1_GET_TX_DESC_MOREFRAG(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 13, 1)
+#define IE1_SET_TX_DESC_MOREFRAG(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 13, 1, value)
+#define IE1_GET_TX_DESC_NOACM(txdesc_ie)                                       \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 12, 1)
+#define IE1_SET_TX_DESC_NOACM(txdesc_ie, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 12, 1, value)
+#define IE1_GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie)                             \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 11, 1)
+#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie, value)                      \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 11, 1, value)
+#define IE1_GET_TX_DESC_NAVUSEHDR(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 10, 1)
+#define IE1_SET_TX_DESC_NAVUSEHDR(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 10, 1, value)
+#define IE1_GET_TX_DESC_HTC(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 9, 1)
+#define IE1_SET_TX_DESC_HTC(txdesc_ie, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 9, 1, value)
+#define IE1_GET_TX_DESC_BMC(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 1)
+#define IE1_SET_TX_DESC_BMC(txdesc_ie, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 1, value)
+#define IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie)                           \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 7, 1)
+#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie, value)                    \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 7, 1, value)
+#define IE1_GET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie)                             \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 6, 1)
+#define IE1_SET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie, value)                      \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 6, 1, value)
+#define IE1_GET_TX_DESC_HW_SSN_SEL(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 2)
+#define IE1_SET_TX_DESC_HW_SSN_SEL(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 2, value)
+#define IE1_GET_TX_DESC_DISQSELSEQ(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 3, 1)
+#define IE1_SET_TX_DESC_DISQSELSEQ(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 3, 1, value)
+#define IE1_GET_TX_DESC_EN_HWSEQ(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1)
+#define IE1_SET_TX_DESC_EN_HWSEQ(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value)
+#define IE1_GET_TX_DESC_EN_HWEXSEQ(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)
+#define IE1_SET_TX_DESC_EN_HWEXSEQ(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)
+#define IE1_GET_TX_DESC_EN_DESC_ID(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)
+#define IE1_SET_TX_DESC_EN_DESC_ID(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)
+#define IE1_GET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie)                              \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 24, 8)
+#define IE1_SET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie, value)                       \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 24, 8, value)
+#define IE1_GET_TX_DESC_P_AID(txdesc_ie)                                       \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 15, 9)
+#define IE1_SET_TX_DESC_P_AID(txdesc_ie, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 15, 9, value)
+#define IE1_GET_TX_DESC_MOREDATA(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 14, 1)
+#define IE1_SET_TX_DESC_MOREDATA(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 14, 1, value)
+#define IE1_GET_TX_DESC_SW_SEQ(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 12)
+#define IE1_SET_TX_DESC_SW_SEQ(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 12, value)
+#define IE2_GET_TX_DESC_IE_END(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)
+#define IE2_SET_TX_DESC_IE_END(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)
+#define IE2_GET_TX_DESC_IE_UP(txdesc_ie)                                       \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)
+#define IE2_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)
+#define IE2_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)
+#define IE2_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)
+#define IE2_GET_TX_DESC_ADDR_CAM(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 8)
+#define IE2_SET_TX_DESC_ADDR_CAM(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 8, value)
+#define IE2_GET_TX_DESC_MULTIPLE_PORT(txdesc_ie)                               \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 12, 3)
+#define IE2_SET_TX_DESC_MULTIPLE_PORT(txdesc_ie, value)                        \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 12, 3, value)
+#define IE2_GET_TX_DESC_RAW(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 11, 1)
+#define IE2_SET_TX_DESC_RAW(txdesc_ie, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 11, 1, value)
+#define IE2_GET_TX_DESC_RDG_EN(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 10, 1)
+#define IE2_SET_TX_DESC_RDG_EN(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 10, 1, value)
+#define IE2_GET_TX_DESC_SPECIAL_CW(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 7, 1)
+#define IE2_SET_TX_DESC_SPECIAL_CW(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 7, 1, value)
+#define IE2_GET_TX_DESC_POLLUTED(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 6, 1)
+#define IE2_SET_TX_DESC_POLLUTED(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 6, 1, value)
+#define IE2_GET_TX_DESC_BT_NULL(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 5, 1)
+#define IE2_SET_TX_DESC_BT_NULL(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 5, 1, value)
+#define IE2_GET_TX_DESC_NULL_1(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 1)
+#define IE2_SET_TX_DESC_NULL_1(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 1, value)
+#define IE2_GET_TX_DESC_NULL_0(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 3, 1)
+#define IE2_SET_TX_DESC_NULL_0(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 3, 1, value)
+#define IE2_GET_TX_DESC_TRI_FRAME(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1)
+#define IE2_SET_TX_DESC_TRI_FRAME(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value)
+#define IE2_GET_TX_DESC_SPE_RPT(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)
+#define IE2_SET_TX_DESC_SPE_RPT(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)
+#define IE2_GET_TX_DESC_FTM_EN(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)
+#define IE2_SET_TX_DESC_FTM_EN(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)
+#define IE2_GET_TX_DESC_MBSSID(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 27, 4)
+#define IE2_SET_TX_DESC_MBSSID(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 27, 4, value)
+#define IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie)                         \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 11)
+#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie, value)                  \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 11, value)
+#define IE2_GET_TX_DESC_RDG_NAV_EXT(txdesc_ie)                                 \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 15, 1)
+#define IE2_SET_TX_DESC_RDG_NAV_EXT(txdesc_ie, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 15, 1, value)
+#define IE2_GET_TX_DESC_DROP_ID(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 12, 2)
+#define IE2_SET_TX_DESC_DROP_ID(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 12, 2, value)
+#define IE2_GET_TX_DESC_SW_DEFINE(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 12)
+#define IE2_SET_TX_DESC_SW_DEFINE(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 12, value)
+#define IE3_GET_TX_DESC_IE_END(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)
+#define IE3_SET_TX_DESC_IE_END(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)
+#define IE3_GET_TX_DESC_IE_UP(txdesc_ie)                                       \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)
+#define IE3_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)
+#define IE3_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)
+#define IE3_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)
+#define IE3_GET_TX_DESC_DATA_SC(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 20, 4)
+#define IE3_SET_TX_DESC_DATA_SC(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 20, 4, value)
+#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie)                         \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 4)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie, value)                  \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 4, value)
+#define IE3_GET_TX_DESC_CTRL_CNT(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 4)
+#define IE3_SET_TX_DESC_CTRL_CNT(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 4, value)
+#define IE3_GET_TX_DESC_CTRL_CNT_VALID(txdesc_ie)                              \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)
+#define IE3_SET_TX_DESC_CTRL_CNT_VALID(txdesc_ie, value)                       \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)
+#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie)                         \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie, value)                  \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)
+#define IE3_GET_TX_DESC_G_ID(txdesc_ie)                                        \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 24, 6)
+#define IE3_SET_TX_DESC_G_ID(txdesc_ie, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 24, 6, value)
+#define IE3_GET_TX_DESC_SND_TARGET(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 8)
+#define IE3_SET_TX_DESC_SND_TARGET(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 8, value)
+#define IE3_GET_TX_DESC_CCA_RTS(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 11, 2)
+#define IE3_SET_TX_DESC_CCA_RTS(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 11, 2, value)
+#define IE3_GET_TX_DESC_SND_PKT_SEL(txdesc_ie)                                 \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 9, 2)
+#define IE3_SET_TX_DESC_SND_PKT_SEL(txdesc_ie, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 9, 2, value)
+#define IE3_GET_TX_DESC_NDPA(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 7, 2)
+#define IE3_SET_TX_DESC_NDPA(txdesc_ie, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 7, 2, value)
+#define IE3_GET_TX_DESC_MU_DATARATE(txdesc_ie)                                 \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 7)
+#define IE3_SET_TX_DESC_MU_DATARATE(txdesc_ie, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 7, value)
+#define IE4_GET_TX_DESC_IE_END(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)
+#define IE4_SET_TX_DESC_IE_END(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)
+#define IE4_GET_TX_DESC_IE_UP(txdesc_ie)                                       \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)
+#define IE4_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)
+#define IE4_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)
+#define IE4_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)
+#define IE4_GET_TX_DESC_VCS_STBC(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 10, 2)
+#define IE4_SET_TX_DESC_VCS_STBC(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 10, 2, value)
+#define IE4_GET_TX_DESC_DATA_STBC(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 2)
+#define IE4_SET_TX_DESC_DATA_STBC(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 2, value)
+#define IE4_GET_TX_DESC_DATA_LDPC(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1)
+#define IE4_SET_TX_DESC_DATA_LDPC(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value)
+#define IE4_GET_TX_DESC_GF(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)
+#define IE4_SET_TX_DESC_GF(txdesc_ie, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)
+#define IE4_GET_TX_DESC_LSIG_TXOP_EN(txdesc_ie)                                \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)
+#define IE4_SET_TX_DESC_LSIG_TXOP_EN(txdesc_ie, value)                         \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)
+#define IE4_GET_TX_DESC_PATH_MAPA(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 30, 2)
+#define IE4_SET_TX_DESC_PATH_MAPA(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 30, 2, value)
+#define IE4_GET_TX_DESC_PATH_MAPB(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 28, 2)
+#define IE4_SET_TX_DESC_PATH_MAPB(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 28, 2, value)
+#define IE4_GET_TX_DESC_PATH_MAPC(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 26, 2)
+#define IE4_SET_TX_DESC_PATH_MAPC(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 26, 2, value)
+#define IE4_GET_TX_DESC_PATH_MAPD(txdesc_ie)                                   \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 24, 2)
+#define IE4_SET_TX_DESC_PATH_MAPD(txdesc_ie, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 24, 2, value)
+#define IE4_GET_TX_DESC_ANTSEL_A(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 20, 4)
+#define IE4_SET_TX_DESC_ANTSEL_A(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 20, 4, value)
+#define IE4_GET_TX_DESC_ANTSEL_B(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 4)
+#define IE4_SET_TX_DESC_ANTSEL_B(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 4, value)
+#define IE4_GET_TX_DESC_ANTSEL_C(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 12, 4)
+#define IE4_SET_TX_DESC_ANTSEL_C(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 12, 4, value)
+#define IE4_GET_TX_DESC_ANTSEL_D(txdesc_ie)                                    \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 8, 4)
+#define IE4_SET_TX_DESC_ANTSEL_D(txdesc_ie, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 8, 4, value)
+#define IE4_GET_TX_DESC_NTX_PATH_EN(txdesc_ie)                                 \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 4, 4)
+#define IE4_SET_TX_DESC_NTX_PATH_EN(txdesc_ie, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 4, 4, value)
+#define IE4_GET_TX_DESC_ANTLSEL_EN(txdesc_ie)                                  \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 3, 1)
+#define IE4_SET_TX_DESC_ANTLSEL_EN(txdesc_ie, value)                           \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 3, 1, value)
+#define IE4_GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie)                            \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 2)
+#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie, value)                     \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 2, value)
+#define IE5_GET_TX_DESC_IE_END(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)
+#define IE5_SET_TX_DESC_IE_END(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)
+#define IE5_GET_TX_DESC_IE_UP(txdesc_ie)                                       \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)
+#define IE5_SET_TX_DESC_IE_UP(txdesc_ie, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)
+#define IE5_GET_TX_DESC_IE_NUM(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)
+#define IE5_SET_TX_DESC_IE_NUM(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)
+#define IE5_GET_TX_DESC_LEN1_L(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 17, 7)
+#define IE5_SET_TX_DESC_LEN1_L(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 17, 7, value)
+#define IE5_GET_TX_DESC_LEN0(txdesc_ie)                                        \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 13)
+#define IE5_SET_TX_DESC_LEN0(txdesc_ie, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 13, value)
+#define IE5_GET_TX_DESC_PKT_NUM(txdesc_ie)                                     \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 4)
+#define IE5_SET_TX_DESC_PKT_NUM(txdesc_ie, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 4, value)
+#define IE5_GET_TX_DESC_LEN3(txdesc_ie)                                        \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 19, 13)
+#define IE5_SET_TX_DESC_LEN3(txdesc_ie, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 19, 13, value)
+#define IE5_GET_TX_DESC_LEN2(txdesc_ie)                                        \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 6, 13)
+#define IE5_SET_TX_DESC_LEN2(txdesc_ie, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 6, 13, value)
+#define IE5_GET_TX_DESC_LEN1_H(txdesc_ie)                                      \
+	LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 6)
+#define IE5_SET_TX_DESC_LEN1_H(txdesc_ie, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 6, value)
+
+#endif
+
+#endif

hal/halmac/halmac_tx_desc_nic.h

@@ -0,0 +1,951 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_NIC_H_
+#define _HALMAC_TX_DESC_NIC_H_
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_DISQSELSEQ(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 31, 1, value)
+#define GET_TX_DESC_DISQSELSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 31, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_IE_END_BODY(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 31, 1, value)
+#define GET_TX_DESC_IE_END_BODY(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 31, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_GF(txdesc, value)                                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value)
+#define GET_TX_DESC_GF(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 30, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_AGG_EN_V1(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value)
+#define GET_TX_DESC_AGG_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 30, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_NO_ACM(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value)
+#define GET_TX_DESC_NO_ACM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 29, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_BK_V1(txdesc, value)                                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value)
+#define GET_TX_DESC_BK_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 29, 1)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 28, 1, value)
+#define GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x00, 28, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 27, 1, value)
+#define GET_TX_DESC_AMSDU_PAD_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 27, 1)
+#define SET_TX_DESC_LS(txdesc, value)                                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 26, 1, value)
+#define GET_TX_DESC_LS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 26, 1)
+#define SET_TX_DESC_HTC(txdesc, value)                                         \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 25, 1, value)
+#define GET_TX_DESC_HTC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 25, 1)
+#define SET_TX_DESC_BMC(txdesc, value)                                         \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 24, 1, value)
+#define GET_TX_DESC_BMC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 24, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_PKT_OFFSET_V1(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 24, 5, value)
+#define GET_TX_DESC_PKT_OFFSET_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 24, 5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_OFFSET(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 16, 8, value)
+#define GET_TX_DESC_OFFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 16, 8)
+#define SET_TX_DESC_TXPKTSIZE(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 0, 16, value)
+#define GET_TX_DESC_TXPKTSIZE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 0, 16)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/*WORD1*/
+
+#define SET_TX_DESC_HW_AES_IV_V2(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 31, 1, value)
+#define GET_TX_DESC_HW_AES_IV_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 31, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_AMSDU(txdesc, value)                                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value)
+#define GET_TX_DESC_AMSDU(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_FTM_EN_V1(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value)
+#define GET_TX_DESC_FTM_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_MOREDATA(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value)
+#define GET_TX_DESC_MOREDATA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 29, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_HW_AES_IV_V1(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value)
+#define GET_TX_DESC_HW_AES_IV_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 29, 1)
+#define SET_TX_DESC_MHR_CP(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 25, 1, value)
+#define GET_TX_DESC_MHR_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 25, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_PKT_OFFSET(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 24, 5, value)
+#define GET_TX_DESC_PKT_OFFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 24, 5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_SMH_EN_V1(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 24, 1, value)
+#define GET_TX_DESC_SMH_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 24, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_SEC_TYPE(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 22, 2, value)
+#define GET_TX_DESC_SEC_TYPE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 22, 2)
+#define SET_TX_DESC_EN_DESC_ID(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 21, 1, value)
+#define GET_TX_DESC_EN_DESC_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 21, 1)
+#define SET_TX_DESC_RATE_ID(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 16, 5, value)
+#define GET_TX_DESC_RATE_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 16, 5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_SMH_CAM(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 16, 8, value)
+#define GET_TX_DESC_SMH_CAM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 16, 8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_PIFS(txdesc, value)                                        \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 15, 1, value)
+#define GET_TX_DESC_PIFS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 15, 1)
+#define SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 14, 1, value)
+#define GET_TX_DESC_LSIG_TXOP_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 14, 1)
+#define SET_TX_DESC_RD_NAV_EXT(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 13, 1, value)
+#define GET_TX_DESC_RD_NAV_EXT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 13, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_EXT_EDCA(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 13, 1, value)
+#define GET_TX_DESC_EXT_EDCA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 13, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_QSEL(txdesc, value)                                        \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 8, 5, value)
+#define GET_TX_DESC_QSEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 8, 5)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_SPECIAL_CW(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 7, 1, value)
+#define GET_TX_DESC_SPECIAL_CW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 7, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_MACID(txdesc, value)                                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 7, value)
+#define GET_TX_DESC_MACID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 0, 7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_MACID_V1(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 7, value)
+#define GET_TX_DESC_MACID_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 0, 7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_HW_AES_IV(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 31, 1, value)
+#define GET_TX_DESC_HW_AES_IV(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 31, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_CHK_EN_V1(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 31, 1, value)
+#define GET_TX_DESC_CHK_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 31, 1)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_FTM_EN(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 30, 1, value)
+#define GET_TX_DESC_FTM_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 30, 1)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTCEL_D_V1(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 28, 4, value)
+#define GET_TX_DESC_ANTCEL_D_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 28, 4)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_DMA_PRI(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 27, 1, value)
+#define GET_TX_DESC_DMA_PRI(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 27, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_G_ID(txdesc, value)                                        \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 6, value)
+#define GET_TX_DESC_G_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_MAX_AMSDU_MODE(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 3, value)
+#define GET_TX_DESC_MAX_AMSDU_MODE(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 3)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_C_V1(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 4, value)
+#define GET_TX_DESC_ANTSEL_C_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_BT_NULL(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 23, 1, value)
+#define GET_TX_DESC_BT_NULL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 23, 1)
+#define SET_TX_DESC_AMPDU_DENSITY(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 20, 3, value)
+#define GET_TX_DESC_AMPDU_DENSITY(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 20, 3)
+#define SET_TX_DESC_SPE_RPT(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 19, 1, value)
+#define GET_TX_DESC_SPE_RPT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 19, 1)
+#define SET_TX_DESC_RAW(txdesc, value)                                         \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 18, 1, value)
+#define GET_TX_DESC_RAW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 18, 1)
+#define SET_TX_DESC_MOREFRAG(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 17, 1, value)
+#define GET_TX_DESC_MOREFRAG(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 17, 1)
+#define SET_TX_DESC_BK(txdesc, value)                                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 16, 1, value)
+#define GET_TX_DESC_BK(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 16, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 16, 8, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x08, 16, 8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_NULL_1(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 15, 1, value)
+#define GET_TX_DESC_NULL_1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 15, 1)
+#define SET_TX_DESC_NULL_0(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 14, 1, value)
+#define GET_TX_DESC_NULL_0(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 14, 1)
+#define SET_TX_DESC_RDG_EN(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 13, 1, value)
+#define GET_TX_DESC_RDG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 13, 1)
+#define SET_TX_DESC_AGG_EN(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 12, 1, value)
+#define GET_TX_DESC_AGG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 12, 1)
+#define SET_TX_DESC_CCA_RTS(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 10, 2, value)
+#define GET_TX_DESC_CCA_RTS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 10, 2)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_TRI_FRAME(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 9, 1, value)
+#define GET_TX_DESC_TRI_FRAME(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 9, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_P_AID(txdesc, value)                                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 9, value)
+#define GET_TX_DESC_P_AID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 0, 9)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 16, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x08, 0, 16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 24, 8, value)
+#define GET_TX_DESC_AMPDU_MAX_TIME(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x0C, 24, 8)
+#define SET_TX_DESC_NDPA(txdesc, value)                                        \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 22, 2, value)
+#define GET_TX_DESC_NDPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 22, 2)
+#define SET_TX_DESC_MAX_AGG_NUM(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 17, 5, value)
+#define GET_TX_DESC_MAX_AGG_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 17, 5)
+#define SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 16, 1, value)
+#define GET_TX_DESC_USE_MAX_TIME_EN(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x0C, 16, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_OFFLOAD_SIZE(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 16, 15, value)
+#define GET_TX_DESC_OFFLOAD_SIZE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 16, 15)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_NAVUSEHDR(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 15, 1, value)
+#define GET_TX_DESC_NAVUSEHDR(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 15, 1)
+#define SET_TX_DESC_CHK_EN(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 14, 1, value)
+#define GET_TX_DESC_CHK_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 14, 1)
+#define SET_TX_DESC_HW_RTS_EN(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 13, 1, value)
+#define GET_TX_DESC_HW_RTS_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 13, 1)
+#define SET_TX_DESC_RTSEN(txdesc, value)                                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 12, 1, value)
+#define GET_TX_DESC_RTSEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 12, 1)
+#define SET_TX_DESC_CTS2SELF(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 11, 1, value)
+#define GET_TX_DESC_CTS2SELF(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 11, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_CHANNEL_DMA(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 11, 5, value)
+#define GET_TX_DESC_CHANNEL_DMA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 11, 5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_DISDATAFB(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 10, 1, value)
+#define GET_TX_DESC_DISDATAFB(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 10, 1)
+#define SET_TX_DESC_DISRTSFB(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 9, 1, value)
+#define GET_TX_DESC_DISRTSFB(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 9, 1)
+#define SET_TX_DESC_USE_RATE(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 8, 1, value)
+#define GET_TX_DESC_USE_RATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 8, 1)
+#define SET_TX_DESC_HW_SSN_SEL(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 6, 2, value)
+#define GET_TX_DESC_HW_SSN_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 6, 2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_IE_CNT(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 6, 3, value)
+#define GET_TX_DESC_IE_CNT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 6, 3)
+#define SET_TX_DESC_IE_CNT_EN(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 5, 1, value)
+#define GET_TX_DESC_IE_CNT_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 5, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_WHEADER_LEN(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value)
+#define GET_TX_DESC_WHEADER_LEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 0, 5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_WHEADER_LEN_V1(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value)
+#define GET_TX_DESC_WHEADER_LEN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 0, 5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 30, 2, value)
+#define GET_TX_DESC_PCTS_MASK_IDX(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 30, 2)
+#define SET_TX_DESC_PCTS_EN(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 29, 1, value)
+#define GET_TX_DESC_PCTS_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 29, 1)
+#define SET_TX_DESC_RTSRATE(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 24, 5, value)
+#define GET_TX_DESC_RTSRATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 24, 5)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 18, 6, value)
+#define GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x10, 18, 6)
+#define SET_TX_DESC_RTY_LMT_EN(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 17, 1, value)
+#define GET_TX_DESC_RTY_LMT_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 17, 1)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)                         \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 13, 4, value)
+#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)                                \
+	LE_BITS_TO_4BYTE(txdesc + 0x10, 13, 4)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)                        \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 8, 5, value)
+#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)                               \
+	LE_BITS_TO_4BYTE(txdesc + 0x10, 8, 5)
+#define SET_TX_DESC_TRY_RATE(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 7, 1, value)
+#define GET_TX_DESC_TRY_RATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 7, 1)
+#define SET_TX_DESC_DATARATE(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 0, 7, value)
+#define GET_TX_DESC_DATARATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 0, 7)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_POLLUTED(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 31, 1, value)
+#define GET_TX_DESC_POLLUTED(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 31, 1)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_EN_V1(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 30, 1, value)
+#define GET_TX_DESC_ANTSEL_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 30, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_TXPWR_OFSET(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 3, value)
+#define GET_TX_DESC_TXPWR_OFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 28, 3)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value)                            \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 2, value)
+#define GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc)                                   \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 28, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_TX_ANT(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 4, value)
+#define GET_TX_DESC_TX_ANT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 24, 4)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_DROP_ID(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 2, value)
+#define GET_TX_DESC_DROP_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 24, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_PORT_ID(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 21, 3, value)
+#define GET_TX_DESC_PORT_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 21, 3)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT ||   \
+     HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_MULTIPLE_PORT(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 18, 3, value)
+#define GET_TX_DESC_MULTIPLE_PORT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 18, 3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)                          \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 17, 1, value)
+#define GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)                                 \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 17, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_RTS_SC(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 13, 4, value)
+#define GET_TX_DESC_RTS_SC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 13, 4)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value)                         \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 13, 4, value)
+#define GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc)                                \
+	LE_BITS_TO_4BYTE(txdesc + 0x14, 13, 4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_RTS_SHORT(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 12, 1, value)
+#define GET_TX_DESC_RTS_SHORT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 12, 1)
+#define SET_TX_DESC_VCS_STBC(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 10, 2, value)
+#define GET_TX_DESC_VCS_STBC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 10, 2)
+#define SET_TX_DESC_DATA_STBC(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 8, 2, value)
+#define GET_TX_DESC_DATA_STBC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 8, 2)
+#define SET_TX_DESC_DATA_LDPC(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 7, 1, value)
+#define GET_TX_DESC_DATA_LDPC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 7, 1)
+#define SET_TX_DESC_DATA_BW(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 5, 2, value)
+#define GET_TX_DESC_DATA_BW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 5, 2)
+#define SET_TX_DESC_DATA_SHORT(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 4, 1, value)
+#define GET_TX_DESC_DATA_SHORT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 4, 1)
+#define SET_TX_DESC_DATA_SC(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 0, 4, value)
+#define GET_TX_DESC_DATA_SC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 0, 4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_ANTSEL_D(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 30, 2, value)
+#define GET_TX_DESC_ANTSEL_D(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 30, 2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPD_V1(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 30, 2, value)
+#define GET_TX_DESC_ANT_MAPD_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 30, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPD(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 2, value)
+#define GET_TX_DESC_ANT_MAPD(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPC_V1(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 2, value)
+#define GET_TX_DESC_ANT_MAPC_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPC(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 2, value)
+#define GET_TX_DESC_ANT_MAPC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPB_V1(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 2, value)
+#define GET_TX_DESC_ANT_MAPB_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPB(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 2, value)
+#define GET_TX_DESC_ANT_MAPB(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPA_V1(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 2, value)
+#define GET_TX_DESC_ANT_MAPA_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPA(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 22, 2, value)
+#define GET_TX_DESC_ANT_MAPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 22, 2)
+#define SET_TX_DESC_ANTSEL_C(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 20, 2, value)
+#define GET_TX_DESC_ANTSEL_C(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 20, 2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_B_V1(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 20, 4, value)
+#define GET_TX_DESC_ANTSEL_B_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 20, 4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_B(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 18, 2, value)
+#define GET_TX_DESC_ANTSEL_B(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 18, 2)
+#define SET_TX_DESC_ANTSEL_A(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 2, value)
+#define GET_TX_DESC_ANTSEL_A(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 2)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_A_V1(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 4, value)
+#define GET_TX_DESC_ANTSEL_A_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_MBSSID(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 12, 4, value)
+#define GET_TX_DESC_MBSSID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 12, 4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_SW_DEFINE(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 12, value)
+#define GET_TX_DESC_SW_DEFINE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 0, 12)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_SWPS_SEQ(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 12, value)
+#define GET_TX_DESC_SWPS_SEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 0, 12)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 24, 8, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 24, 8)
+#define SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 24, 8, value)
+#define GET_TX_DESC_FINAL_DATA_RATE(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x1C, 24, 8)
+#define SET_TX_DESC_NTX_MAP(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 20, 4, value)
+#define GET_TX_DESC_NTX_MAP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 20, 4)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_EN(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 19, 1, value)
+#define GET_TX_DESC_ANTSEL_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 19, 1)
+#define SET_TX_DESC_MBSSID_EX(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 16, 3, value)
+#define GET_TX_DESC_MBSSID_EX(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 16, 3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT ||   \
+     HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value)
+#define GET_TX_DESC_TX_BUFF_SIZE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16)
+#define SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)                             \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM(txdesc)                                    \
+	LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16)
+#define SET_TX_DESC_TIMESTAMP(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value)
+#define GET_TX_DESC_TIMESTAMP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_TXWIFI_CP(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 31, 1, value)
+#define GET_TX_DESC_TXWIFI_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 31, 1)
+#define SET_TX_DESC_MAC_CP(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 30, 1, value)
+#define GET_TX_DESC_MAC_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 30, 1)
+#define SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)                               \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 29, 1, value)
+#define GET_TX_DESC_STW_PKTRE_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 29, 1)
+#define SET_TX_DESC_STW_RB_DIS(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 28, 1, value)
+#define GET_TX_DESC_STW_RB_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 28, 1)
+#define SET_TX_DESC_STW_RATE_DIS(txdesc, value)                                \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 27, 1, value)
+#define GET_TX_DESC_STW_RATE_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 27, 1)
+#define SET_TX_DESC_STW_ANT_DIS(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 26, 1, value)
+#define GET_TX_DESC_STW_ANT_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 26, 1)
+#define SET_TX_DESC_STW_EN(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 25, 1, value)
+#define GET_TX_DESC_STW_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 25, 1)
+#define SET_TX_DESC_SMH_EN(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 1, value)
+#define GET_TX_DESC_SMH_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 1)
+#define SET_TX_DESC_TAILPAGE_L(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 8, value)
+#define GET_TX_DESC_TAILPAGE_L(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 8)
+#define SET_TX_DESC_SDIO_DMASEQ(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 8, value)
+#define GET_TX_DESC_SDIO_DMASEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 16, 8)
+#define SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 8, value)
+#define GET_TX_DESC_NEXTHEADPAGE_L(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x20, 16, 8)
+#define SET_TX_DESC_EN_HWSEQ(txdesc, value)                                    \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 15, 1, value)
+#define GET_TX_DESC_EN_HWSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 15, 1)
+#define SET_TX_DESC_EN_HWEXSEQ(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 14, 1, value)
+#define GET_TX_DESC_EN_HWEXSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 14, 1)
+#define SET_TX_DESC_DATA_RC(txdesc, value)                                     \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 8, 6, value)
+#define GET_TX_DESC_DATA_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 8, 6)
+#define SET_TX_DESC_BAR_RTY_TH(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 6, 2, value)
+#define GET_TX_DESC_BAR_RTY_TH(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 6, 2)
+#define SET_TX_DESC_RTS_RC(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 0, 6, value)
+#define GET_TX_DESC_RTS_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 0, 6)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_TAILPAGE_H(txdesc, value)                                  \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 28, 4, value)
+#define GET_TX_DESC_TAILPAGE_H(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 28, 4)
+#define SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)                              \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 24, 4, value)
+#define GET_TX_DESC_NEXTHEADPAGE_H(txdesc)                                     \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 24, 4)
+#define SET_TX_DESC_SW_SEQ(txdesc, value)                                      \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 12, 12, value)
+#define GET_TX_DESC_SW_SEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 12, 12)
+#define SET_TX_DESC_TXBF_PATH(txdesc, value)                                   \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 11, 1, value)
+#define GET_TX_DESC_TXBF_PATH(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 11, 1)
+#define SET_TX_DESC_PADDING_LEN(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 11, value)
+#define GET_TX_DESC_PADDING_LEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 0, 11)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)                         \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 8, value)
+#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)                                \
+	LE_BITS_TO_4BYTE(txdesc + 0x24, 0, 8)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*WORD10*/
+
+#define SET_TX_DESC_MU_DATARATE(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 8, 8, value)
+#define GET_TX_DESC_MU_DATARATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 8, 8)
+#define SET_TX_DESC_MU_RC(txdesc, value)                                       \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 4, 4, value)
+#define GET_TX_DESC_MU_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 4, 4)
+#define SET_TX_DESC_SND_PKT_SEL(txdesc, value)                                 \
+	SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 0, 2, value)
+#define GET_TX_DESC_SND_PKT_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 0, 2)
+
+#endif
+
+#endif

hal/halmac/halmac_usb_reg.h

@@ -0,0 +1,19 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __HALMAC_USB_REG_H__
+#define __HALMAC_USB_REG_H__
+
+#endif/* __HALMAC_USB_REG_H__ */