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Rin Cat
2019-09-21 05:30:30 -04:00
parent 953142179e
commit 0644d0b316
413 changed files with 179115 additions and 110562 deletions
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131
include/Hal8192FPhyCfg.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __INC_HAL8192FPHYCFG_H__
#define __INC_HAL8192FPHYCFG_H__
/*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50 /* us */
#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#ifdef CONFIG_PCI_HCI
#define MAX_AGGR_NUM 0x0B
#else
#define MAX_AGGR_NUM 0x07
#endif /* CONFIG_PCI_HCI */
/*--------------------------Define Parameters End-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure End----------------------------*/
/*--------------------------Exported Function prototype---------------------*/
u32
PHY_QueryBBReg_8192F(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask
);
VOID
PHY_SetBBReg_8192F(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
u32
PHY_QueryRFReg_8192F(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask
);
VOID
PHY_SetRFReg_8192F(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
/* MAC/BB/RF HAL config */
int PHY_BBConfig8192F(PADAPTER Adapter );
int PHY_RFConfig8192F(PADAPTER Adapter);
s32 PHY_MACConfig8192F(PADAPTER padapter);
int
PHY_ConfigRFWithParaFile_8192F(
IN PADAPTER Adapter,
IN u8 *pFileName,
enum rf_path eRFPath
);
VOID
PHY_SetTxPowerIndex_8192F(
IN PADAPTER Adapter,
IN u32 PowerIndex,
IN enum rf_path RFPath,
IN u8 Rate
);
u8
PHY_GetTxPowerIndex_8192F(
IN PADAPTER pAdapter,
IN enum rf_path RFPath,
IN u8 Rate,
IN u8 BandWidth,
IN u8 Channel,
struct txpwr_idx_comp *tic
);
VOID
PHY_GetTxPowerLevel8192F(
IN PADAPTER Adapter,
OUT s32 *powerlevel
);
VOID
PHY_SetTxPowerLevel8192F(
IN PADAPTER Adapter,
IN u8 channel
);
VOID
PHY_SetSwChnlBWMode8192F(
IN PADAPTER Adapter,
IN u8 channel,
IN enum channel_width Bandwidth,
IN u8 Offset40,
IN u8 Offset80
);
VOID phy_set_rf_path_switch_8192f(
IN PADAPTER pAdapter,
IN bool bMain
);
/*--------------------------Exported Function prototype End---------------------*/
#endif

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include/Hal8192FPhyReg.h Normal file
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include/Hal8192FPwrSeq.h Normal file
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/******************************************************************************
*
* Copyright(c) 2016 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef REALTEK_POWER_SEQUENCE_8192F
#define REALTEK_POWER_SEQUENCE_8192F
#define POWER_SEQUENCE_8192F_VER 04
/* #include "PwrSeqCmd.h" */
#include "HalPwrSeqCmd.h"
/*
Check document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transition from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
*/
#define RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS 38
#define RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS 8
#define RTL8192F_TRANS_CARDEMU_TO_SUS_STEPS 7
#define RTL8192F_TRANS_SUS_TO_CARDEMU_STEPS 5
#define RTL8192F_TRANS_CARDEMU_TO_CARDDIS_STEPS 8
#define RTL8192F_TRANS_CARDDIS_TO_CARDEMU_STEPS 8
#define RTL8192F_TRANS_CARDEMU_TO_PDN_STEPS 4
#define RTL8192F_TRANS_PDN_TO_CARDEMU_STEPS 1
#define RTL8192F_TRANS_ACT_TO_LPS_STEPS 13
#define RTL8192F_TRANS_LPS_TO_ACT_STEPS 11
#define RTL8192F_TRANS_END_STEPS 1
#define RTL8192F_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, (BIT1|BIT0), 0}, \
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},/* SWR OCP enable 0x10[18]=1*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
{0x007f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x7c[31]=1,LDO has max output capability*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \
{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 data mode*/\
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
{0x0068, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0},/*RF HW ON/OFF Enable*/\
{0x001C, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/*Register Lock Disable*/\
{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\
{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S1*/\
{0x007B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S0*/\
{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/*enable RF path S1*/\
{0x007B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/*enalbe RF path S0*/\
{0x0097, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*AFE_Ctrl*/\
{0x00DC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xCC},/*AFE_Ctrl*/\
{0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x18, 0x00},/*AFE_Ctrl 0x24[4:3]=00 for xtal gmn*/\
{0x1050, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[7:0] Pull down software register*/\
{0x1051, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[15:8] Pull down software register*/\
{0x1052, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[23:16] Pull down software register*/\
{0x1053, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[31:24] Pull down software register*/\
{0x105B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_B[7:0] Pull down software register*/\
{0x001C, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*Register Lock Enable*/\
{0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT7|BIT6), 0x3},/*set HCI Power sequence state delay time:0*/
#define RTL8192F_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x2[0]=0 Reset BB,RF enter Power Down mode*/ \
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x10[18] = 0 to disable ocp*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
#define RTL8192F_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 USB|SDIO SOP option to disable BG/MB/ACK/SWR*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8192F_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8192F_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend*/ \
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8192F_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x10[18] = 1 to enable ocp*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
#define RTL8192F_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8192F_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
#define RTL8192F_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
#define RTL8192F_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8192F_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
extern WLAN_PWR_CFG rtl8192F_power_on_flow[RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8192F_radio_off_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8192F_card_disable_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_CARDDIS_STEPS+RTL8192F_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8192F_card_enable_flow[RTL8192F_TRANS_CARDDIS_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8192F_suspend_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_SUS_STEPS+RTL8192F_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8192F_resume_flow[RTL8192F_TRANS_SUS_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8192F_hwpdn_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192F_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8192F_enter_lps_flow[RTL8192F_TRANS_ACT_TO_LPS_STEPS+RTL8192F_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8192F_leave_lps_flow[RTL8192F_TRANS_LPS_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __INC_HAL8710BPHYCFG_H__
#define __INC_HAL8710BPHYCFG_H__
/*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50 /* us */
#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#ifdef CONFIG_PCI_HCI
#define MAX_AGGR_NUM 0x0B
#else
#define MAX_AGGR_NUM 0x07
#endif /* CONFIG_PCI_HCI */
/*--------------------------Define Parameters End-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure End----------------------------*/
/*--------------------------Exported Function prototype---------------------*/
u32
PHY_QueryBBReg_8710B(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask
);
VOID
PHY_SetBBReg_8710B(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
u32
PHY_QueryRFReg_8710B(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask
);
VOID
PHY_SetRFReg_8710B(
IN PADAPTER Adapter,
IN enum rf_path eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
/* MAC/BB/RF HAL config */
int PHY_BBConfig8710B(PADAPTER Adapter);
int PHY_RFConfig8710B(PADAPTER Adapter);
s32 PHY_MACConfig8710B(PADAPTER padapter);
int
PHY_ConfigRFWithParaFile_8710B(
IN PADAPTER Adapter,
IN u8 *pFileName,
enum rf_path eRFPath
);
VOID
PHY_SetTxPowerIndex_8710B(
IN PADAPTER Adapter,
IN u32 PowerIndex,
IN enum rf_path RFPath,
IN u8 Rate
);
u8
PHY_GetTxPowerIndex_8710B(
IN PADAPTER pAdapter,
IN enum rf_path RFPath,
IN u8 Rate,
IN u8 BandWidth,
IN u8 Channel,
struct txpwr_idx_comp *tic
);
VOID
PHY_GetTxPowerLevel8710B(
IN PADAPTER Adapter,
OUT s32 *powerlevel
);
VOID
PHY_SetTxPowerLevel8710B(
IN PADAPTER Adapter,
IN u8 channel
);
VOID
PHY_SetSwChnlBWMode8710B(
IN PADAPTER Adapter,
IN u8 channel,
IN enum channel_width Bandwidth,
IN u8 Offset40,
IN u8 Offset80
);
/*--------------------------Exported Function prototype End---------------------*/
#endif

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include/Hal8710BPwrSeq.h Normal file
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/******************************************************************************
*
* Copyright(c) 2016 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef REALTEK_POWER_SEQUENCE_8710B
#define REALTEK_POWER_SEQUENCE_8710B
/* #include "PwrSeqCmd.h" */
#include "HalPwrSeqCmd.h"
/*
Check document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transition from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
*/
#define RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS 5
#define RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS 4
#define RTL8710B_TRANS_CARDEMU_TO_SUS_STEPS 7
#define RTL8710B_TRANS_SUS_TO_CARDEMU_STEPS 15
#define RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS 15
#define RTL8710B_TRANS_PDN_TO_CARDEMU_STEPS 15
#define RTL8710B_TRANS_ACT_TO_LPS_STEPS 15
#define RTL8710B_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8710B_TRANS_ACT_TO_SWLPS_STEPS 22
#define RTL8710B_TRANS_SWLPS_TO_ACT_STEPS 15
#define RTL8710B_TRANS_END_STEPS 1
#define RTL8710B_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x005D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*AFE power mode selection:1: LDO mode ,0: Power-cut mode*/\
{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},\
{0x0056, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x0E},\
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},\
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/
#define RTL8710B_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT0|BIT1|BIT2), 0},/*0x04[24:26] = 0 turn off RF*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT0|BIT1), 0},/*0x04[16:17] = 0 BB reset*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x20[1] = 1 turn off MAC by HW state machine*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x20[1] = 0 polling until return 0 to disable*/ \
#define RTL8710B_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8710B_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8710B_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
#define RTL8710B_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
#define RTL8710B_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8710B_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
#define RTL8710B_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
#define RTL8710B_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8710B_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
extern WLAN_PWR_CFG rtl8710B_power_on_flow[RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8710B_radio_off_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8710B_card_disable_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8710B_card_enable_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8710B_suspend_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8710B_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8710B_resume_flow[RTL8710B_TRANS_SUS_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8710B_hwpdn_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8710B_enter_lps_flow[RTL8710B_TRANS_ACT_TO_LPS_STEPS+RTL8710B_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8710B_leave_lps_flow[RTL8710B_TRANS_LPS_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS];
#endif

13
include/HalVerDef.h
View File

@@ -35,7 +35,10 @@ typedef enum tag_HAL_IC_Type_Definition {
CHIP_8188F = 12,
CHIP_8822B = 13,
CHIP_8723D = 14,
CHIP_8821C = 15
CHIP_8821C = 15,
CHIP_8710B = 16,
CHIP_8192F = 17,
CHIP_8188GTV = 18,
} HAL_IC_TYPE_E;
/* HAL_CHIP_TYPE_E */
@@ -112,6 +115,7 @@ typedef struct tag_HAL_VERSION {
#define IS_8188E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188E) ? TRUE : FALSE)
#define IS_8188F(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188F) ? TRUE : FALSE)
#define IS_8188GTV(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188GTV) ? TRUE : FALSE)
#define IS_8192E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192E) ? TRUE : FALSE)
#define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812) ? TRUE : FALSE)
#define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821) ? TRUE : FALSE)
@@ -120,8 +124,11 @@ typedef struct tag_HAL_VERSION {
#define IS_8703B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8703B) ? TRUE : FALSE)
#define IS_8822B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8822B) ? TRUE : FALSE)
#define IS_8821C_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821C) ? TRUE : FALSE)
#define IS_8723D_SERIES(version)\
((GET_CVID_IC_TYPE(version) == CHIP_8723D) ? TRUE : FALSE)
#define IS_8723D_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723D) ? TRUE : FALSE)
#define IS_8710B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8710B) ? TRUE : FALSE)
#define IS_8192F_SERIES(version)\
((GET_CVID_IC_TYPE(version) == CHIP_8192F) ? TRUE : FALSE)
/* HAL_CHIP_TYPE_E */
#define IS_TEST_CHIP(version) ((GET_CVID_CHIP_TYPE(version) == TEST_CHIP) ? TRUE : FALSE)
#define IS_NORMAL_CHIP(version) ((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE)

21
include/autoconf.h
View File

@@ -34,10 +34,15 @@
*/
#define CONFIG_IEEE80211_BAND_5GHZ 1
#define CONFIG_80211N_HT 1
#ifdef CONFIG_80211N_HT
#define CONFIG_80211AC_VHT 1
#define CONFIG_80211N_HT
#define CONFIG_80211AC_VHT
#ifdef CONFIG_80211AC_VHT
#ifndef CONFIG_80211N_HT
#define CONFIG_80211N_HT
#endif
#endif
#ifdef CONFIG_80211AC_VHT
#define CONFIG_BEAMFORMING
#endif
@@ -82,7 +87,7 @@
#endif /* CONFIG_SUPPORT_USB_INT */
#ifdef CONFIG_POWER_SAVING
/* #define CONFIG_IPS 1 */
#define CONFIG_IPS 1
#ifdef CONFIG_IPS
/* #define CONFIG_IPS_LEVEL_2 1*/ /*enable this to set default IPS mode to IPS_LEVEL_2*/
#define CONFIG_IPS_CHECK_IN_WD /* Do IPS Check in WatchDog. */
@@ -92,12 +97,12 @@
#define CONFIG_LPS 1
#if defined(CONFIG_LPS)
/* #define CONFIG_LPS_LCLK 1 */
#define CONFIG_LPS_LCLK 1
#endif
#ifdef CONFIG_LPS_LCLK
#ifdef CONFIG_POWER_SAVING
#define CONFIG_XMIT_THREAD_MODE
/* #define CONFIG_XMIT_THREAD_MODE */
#endif /* CONFIG_POWER_SAVING */
#ifndef CONFIG_SUPPORT_USB_INT
#define LPS_RPWM_WAIT_MS 300
@@ -300,8 +305,7 @@
#endif
#define RTL8188E_EARLY_MODE_PKT_NUM_10 0
#define CONFIG_ATTEMPT_TO_FIX_AP_BEACON_ERROR
/*#define CONFIG_CUSTOMER01_SMART_ANTENNA */
/*
* Debug Related Config
@@ -312,6 +316,7 @@
#define DBG_CONFIG_ERROR_DETECT
/* #define CONFIG_DIS_UPHY */
/*
#define DBG_CONFIG_ERROR_DETECT_INT
#define DBG_CONFIG_ERROR_RESET

70
include/cmn_info/rtw_sta_info.h
View File

@@ -121,11 +121,17 @@ enum rf_path {
RF_PATH_BD,
RF_PATH_CD,
RF_PATH_ABC,
RF_PATH_ABD,
RF_PATH_ACD,
RF_PATH_BCD,
RF_PATH_ABCD,
};
enum rf_syn {
RF_SYN0 = 0,
RF_SYN1 = 1,
};
enum wireless_set {
WIRELESS_CCK = 0x00000001,
WIRELESS_OFDM = 0x00000002,
@@ -159,51 +165,48 @@ struct rssi_info {
};
struct ra_sta_info {
u8 rate_id; /*ratr_idx*/
u8 rssi_level;
/*New*/
u8 is_first_connect:1; /*CE: ra_rpt_linked, AP: H2C_rssi_rpt*/
u8 is_support_sgi:1; /*driver*/
u8 is_vht_enable:2; /*driver*/
u8 disable_ra:1; /*driver*/
u8 disable_pt:1; /*driver*/ /*remove is_disable_power_training*/
u8 txrx_state:2; /*0: Tx, 1:Rx, 2:bi-direction*/
u8 is_noisy:1;
u8 curr_tx_rate; /*FW->Driver*/
enum channel_width ra_bw_mode; /*max bandwidth, for RA only*/
enum channel_width curr_tx_bw; /*FW->Driver*/
u8 curr_retry_ratio; /*FW->Driver*/
u8 rate_id; /*[PHYDM] ratr_idx*/
u8 rssi_level; /*[PHYDM]*/
u8 is_first_connect:1; /*[PHYDM] CE: ra_rpt_linked, AP: H2C_rssi_rpt*/
u8 is_support_sgi:1; /*[driver]*/
u8 is_vht_enable:2; /*[driver]*/
u8 disable_ra:1; /*[driver]*/
u8 disable_pt:1; /*[driver] remove is_disable_power_training*/
u8 txrx_state:2; /*[PHYDM] 0: Tx, 1:Rx, 2:bi-direction*/
u8 is_noisy:1; /*[PHYDM]*/
u8 curr_tx_rate; /*[PHYDM] FW->Driver*/
enum channel_width ra_bw_mode; /*[Driver] max bandwidth, for RA only*/
enum channel_width curr_tx_bw; /*[PHYDM] FW->Driver*/
u8 curr_retry_ratio; /*[PHYDM] FW->Driver*/
u64 ramask;
};
struct dtp_info {
u8 dyn_tx_power; /*Dynamic Tx power offset*/
u8 last_tx_power;
u8 sta_tx_high_power_lvl:4;
u8 sta_last_dtp_lvl:4;
};
struct cmn_sta_info {
u16 dm_ctrl;
enum channel_width bw_mode; /*max bandwidth*/
u8 mac_id;
u8 mac_addr[6];
u16 aid;
enum rf_type mimo_type; /*sta XTXR*/
struct rssi_info rssi_stat;
struct ra_sta_info ra_info;
u16 tx_moving_average_tp; /*tx average MBps*/
u16 rx_moving_average_tp; /*rx average MBps*/
u8 stbc_en:2; /*Driver : really use stbc!!*/
u8 ldpc_en:2;
enum wireless_set support_wireless_set;
u16 dm_ctrl; /*[Driver]*/
enum channel_width bw_mode; /*[Driver] max support BW*/
u8 mac_id; /*[Driver]*/
u8 mac_addr[6]; /*[Driver]*/
u16 aid; /*[Driver]*/
enum rf_type mimo_type; /*[Driver] sta XTXR*/
struct rssi_info rssi_stat; /*[PHYDM]*/
struct ra_sta_info ra_info; /*[Driver&PHYDM]*/
u16 tx_moving_average_tp; /*[Driver] tx average MBps*/
u16 rx_moving_average_tp; /*[Driver] rx average MBps*/
u8 stbc_en:2; /*[Driver] really transmitt STBC*/
u8 ldpc_en:2; /*[Driver] really transmitt LDPC*/
enum wireless_set support_wireless_set;/*[Driver]*/
#ifdef CONFIG_BEAMFORMING
struct bf_cmn_info bf_info;
struct bf_cmn_info bf_info; /*[Driver]*/
#endif
u8 sm_ps:2;
struct dtp_info dtp_stat; /*Dynamic Tx power offset*/
u8 sm_ps:2; /*[Driver]*/
struct dtp_info dtp_stat; /*[PHYDM] Dynamic Tx power offset*/
/*u8 pw2cca_over_TH_cnt;*/
/*u8 total_pw2cca_cnt;*/
};
@@ -222,6 +225,7 @@ struct phydm_phyinfo_struct {
u8 signal_strength; /* in 0-100 index. */
s8 rx_pwr[4]; /* per-path's pwdb */
s8 rx_snr[4]; /* per-path's SNR */
u8 ant_idx[4]; /*per-path's antenna index*/
/*ODM_PHY_STATUS_NEW_TYPE_SUPPORT*/
u8 rx_count:2; /* RX path counter---*/
u8 band_width:2;

114
include/drv_conf.h
View File

@@ -16,13 +16,12 @@
#define __DRV_CONF_H__
#include "autoconf.h"
#include "hal_ic_cfg.h"
#if defined(PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
#error "Shall be Linux or Windows, but not both!\n"
#endif
#define CONFIG_RSSI_PRIORITY
#ifdef CONFIG_RTW_REPEATER_SON
#ifndef CONFIG_AP
#define CONFIG_AP
@@ -115,12 +114,44 @@
#define CONFIG_USB_VENDOR_REQ_MUTEX
#endif
#if defined(CONFIG_DFS_SLAVE_WITH_RADAR_DETECT) && !defined(CONFIG_DFS_MASTER)
#define CONFIG_DFS_MASTER
#endif
#if !defined(CONFIG_AP_MODE) && defined(CONFIG_DFS_MASTER)
#warning "undef CONFIG_DFS_MASTER because CONFIG_AP_MODE is not defined"
#undef CONFIG_DFS_MASTER
#error "enable CONFIG_DFS_MASTER without CONFIG_AP_MODE"
#endif
#ifdef CONFIG_WIFI_MONITOR
/* #define CONFIG_MONITOR_MODE_XMIT */
#endif
#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL
#ifndef CONFIG_WIFI_MONITOR
#define CONFIG_WIFI_MONITOR
#endif
#ifndef CONFIG_MONITOR_MODE_XMIT
#define CONFIG_MONITOR_MODE_XMIT
#endif
#ifdef CONFIG_POWER_SAVING
#undef CONFIG_POWER_SAVING
#endif
#endif
#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
#ifdef CONFIG_POWER_SAVING
#undef CONFIG_POWER_SAVING
#endif
#ifdef CONFIG_BEAMFORMING
#undef CONFIG_BEAMFORMING
#endif
#endif
#ifdef CONFIG_RTW_MESH
#ifndef CONFIG_RTW_MESH_ACNODE_PREVENT
#define CONFIG_RTW_MESH_ACNODE_PREVENT 1
#endif
#ifndef CONFIG_RTW_MESH_OFFCH_CAND
#define CONFIG_RTW_MESH_OFFCH_CAND 1
#endif
@@ -167,14 +198,6 @@
#define CONFIG_RTW_ADAPTIVITY_MODE 0
#endif
#ifndef CONFIG_RTW_ADAPTIVITY_DML
#define CONFIG_RTW_ADAPTIVITY_DML 0
#endif
#ifndef CONFIG_RTW_ADAPTIVITY_DC_BACKOFF
#define CONFIG_RTW_ADAPTIVITY_DC_BACKOFF 2
#endif
#ifndef CONFIG_RTW_ADAPTIVITY_TH_L2H_INI
#define CONFIG_RTW_ADAPTIVITY_TH_L2H_INI 0
#endif
@@ -237,8 +260,11 @@
#define CONFIG_RTW_CUSTOMIZE_BEEDCA 0x0000431C
#define CONFIG_RTW_CUSTOMIZE_BWMODE 0x00
#define CONFIG_RTW_CUSTOMIZE_RLSTA 0x7
#if defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B)
#define CONFIG_RTW_TX_2PATH_EN /* mutually incompatible with STBC_TX & Beamformer */
#endif
#endif
/*#define CONFIG_EXTEND_LOWRATE_TXOP */
#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS
#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS {0xFF, 0xFF, 0xFF, 0xFF}
@@ -320,11 +346,11 @@
#endif
#if (CONFIG_IFACE_NUMBER == 0)
#error "CONFIG_IFACE_NUMBER cound not equel to 0 !!"
#error "CONFIG_IFACE_NUMBER cound not be 0 !!"
#endif
#if (CONFIG_IFACE_NUMBER > 3)
#error "Not support over 3 interfaces yet !!"
#if (CONFIG_IFACE_NUMBER > 4)
#error "Not support over 4 interfaces yet !!"
#endif
#if (CONFIG_IFACE_NUMBER > 8) /*IFACE_ID_MAX*/
@@ -342,10 +368,29 @@
#endif
#ifdef CONFIG_AP_MODE
#define CONFIG_SUPPORT_MULTI_BCN
#define CONFIG_SWTIMER_BASED_TXBCN
/*#define CONFIG_FW_BASED_BCN*/
#endif
#endif
#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) /* || defined(CONFIG_RTL8822C)*/
#define CONFIG_FW_HANDLE_TXBCN
#ifdef CONFIG_FW_HANDLE_TXBCN
#ifdef CONFIG_SWTIMER_BASED_TXBCN
#undef CONFIG_SWTIMER_BASED_TXBCN
#endif
#define CONFIG_LIMITED_AP_NUM 4
#endif
#endif /*defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) */ /*|| defined(CONFIG_RTL8822C)*/
#endif /*CONFIG_AP_MODE*/
#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
#define CONFIG_CLIENT_PORT_CFG
#define CONFIG_NEW_NETDEV_HDL
#endif/*defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)*/
#endif/*(CONFIG_IFACE_NUMBER > 2)*/
#define MACID_NUM_SW_LIMIT 32
#define SEC_CAM_ENT_NUM_SW_LIMIT 32
@@ -354,10 +399,18 @@
#define CONFIG_IEEE80211_BAND_5GHZ
#endif
#if defined(CONFIG_WOWLAN) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C))
#if defined(CONFIG_WOWLAN) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8814A))
#define CONFIG_WOW_PATTERN_HW_CAM
#endif
#ifndef CONFIG_TSF_UPDATE_PAUSE_FACTOR
#define CONFIG_TSF_UPDATE_PAUSE_FACTOR 200
#endif
#ifndef CONFIG_TSF_UPDATE_RESTORE_FACTOR
#define CONFIG_TSF_UPDATE_RESTORE_FACTOR 5
#endif
/*
Mark CONFIG_DEAUTH_BEFORE_CONNECT by Arvin 2015/07/20
If the failure of Wi-Fi connection is due to some irregular disconnection behavior (like unplug dongle,
@@ -370,6 +423,7 @@
/*#define CONFIG_DOSCAN_IN_BUSYTRAFFIC */
/*#define CONFIG_PHDYM_FW_FIXRATE */ /* Another way to fix tx rate */
/*Don't release SDIO irq in suspend/resume procedure*/
#define CONFIG_RTW_SDIO_KEEP_IRQ 0
@@ -411,4 +465,24 @@
#define CONFIG_IPS
#endif
#endif
#ifdef RTW_REDUCE_SCAN_SWITCH_CH_TIME
#ifndef CONFIG_RTL8822B
#error "Only 8822B support RTW_REDUCE_SCAN_SWITCH_CH_TIME"
#endif
#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
#define RTW_CHANNEL_SWITCH_OFFLOAD
#endif
#endif
#define CONFIG_RTW_TPT_MODE
#ifdef CONFIG_PCI_BCN_POLLING
#define CONFIG_BCN_ICF
#endif
#ifndef CONFIG_PCI_MSI
#define CONFIG_RTW_PCI_MSI_DISABLE
#endif
#endif /* __DRV_CONF_H__ */

158
include/drv_types.h
View File

@@ -60,6 +60,7 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER;
#include <rtw_debug.h>
#include <cmn_info/rtw_sta_info.h>
#include <rtw_rf.h>
#include "../core/rtw_chplan.h"
#ifdef CONFIG_80211N_HT
#include <rtw_ht.h>
@@ -197,6 +198,7 @@ struct registry_priv {
u8 power_mgnt;
u8 ips_mode;
u8 lps_level;
u8 lps_chk_by_tp;
u8 smart_ps;
#ifdef CONFIG_WMMPS_STA
u8 wmm_smart_ps;
@@ -206,6 +208,7 @@ struct registry_priv {
u8 long_retry_lmt;
u8 short_retry_lmt;
u16 busy_thresh;
u16 max_bss_cnt;
u8 ack_policy;
u8 mp_mode;
#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)
@@ -343,6 +346,9 @@ struct registry_priv {
s8 target_tx_pwr_5g[RF_PATH_MAX][RATE_SECTION_NUM - 1];
#endif
u8 tsf_update_pause_factor;
u8 tsf_update_restore_factor;
s8 TxBBSwing_2G;
s8 TxBBSwing_5G;
u8 AmplifierType_2G;
@@ -366,8 +372,6 @@ struct registry_priv {
u8 hiq_filter;
u8 adaptivity_en;
u8 adaptivity_mode;
u8 adaptivity_dml;
u8 adaptivity_dc_backoff;
s8 adaptivity_th_l2h_ini;
s8 adaptivity_th_edcca_hl_diff;
@@ -416,13 +420,14 @@ struct registry_priv {
#ifdef CONFIG_WOWLAN
u8 wakeup_event;
u8 suspend_type;
#endif
#ifdef CONFIG_SUPPORT_TRX_SHARED
u8 trx_share_mode;
#endif
u8 check_hw_status;
u8 wowlan_sta_mix_mode;
u32 pci_aspm_config;
u8 iqk_fw_offload;
@@ -446,6 +451,13 @@ struct registry_priv {
u8 dyn_soml_period;
u8 dyn_soml_delay;
#endif
#ifdef CONFIG_FW_HANDLE_TXBCN
u8 fw_tbtt_rpt;
#endif
#ifdef DBG_LA_MODE
u8 la_mode_en;
#endif
};
/* For registry parameters */
@@ -463,13 +475,19 @@ struct registry_priv {
#define GetRegGLNAType(_Adapter) (_Adapter->registrypriv.GLNA_Type)
#define GetRegPowerTrackingType(_Adapter) (_Adapter->registrypriv.PowerTracking_Type)
#define WOWLAN_IS_STA_MIX_MODE(_Adapter) (_Adapter->registrypriv.wowlan_sta_mix_mode)
#define BSSID_OFT(field) ((ULONG)FIELD_OFFSET(WLAN_BSSID_EX, field))
#define BSSID_SZ(field) sizeof(((PWLAN_BSSID_EX) 0)->field)
#define BW_MODE_2G(bw_mode) ((bw_mode) & 0x0F)
#define BW_MODE_5G(bw_mode) ((bw_mode) >> 4)
#ifdef CONFIG_80211N_HT
#define REGSTY_BW_2G(regsty) BW_MODE_2G((regsty)->bw_mode)
#define REGSTY_BW_5G(regsty) BW_MODE_5G((regsty)->bw_mode)
#else
#define REGSTY_BW_2G(regsty) CHANNEL_WIDTH_20
#define REGSTY_BW_5G(regsty) CHANNEL_WIDTH_20
#endif
#define REGSTY_IS_BW_2G_SUPPORT(regsty, bw) (REGSTY_BW_2G((regsty)) >= (bw))
#define REGSTY_IS_BW_5G_SUPPORT(regsty, bw) (REGSTY_BW_5G((regsty)) >= (bw))
@@ -691,7 +709,7 @@ struct rtw_traffic_statistics {
u64 tx_drop;
u64 cur_tx_bytes;
u64 last_tx_bytes;
u32 cur_tx_tp; /* Tx throughput in MBps. */
u32 cur_tx_tp; /* Tx throughput in Mbps. */
/* rx statistics */
u64 rx_bytes;
@@ -699,7 +717,7 @@ struct rtw_traffic_statistics {
u64 rx_drop;
u64 cur_rx_bytes;
u64 last_rx_bytes;
u32 cur_rx_tp; /* Rx throughput in MBps. */
u32 cur_rx_tp; /* Rx throughput in Mbps. */
};
#define SEC_CAP_CHK_BMC BIT0
@@ -757,6 +775,15 @@ struct macid_bmp {
#endif
};
#ifdef CONFIG_CLIENT_PORT_CFG
struct clt_port_t{
_lock lock;
u8 bmp;
s8 num;
};
#define get_clt_num(adapter) (adapter_to_dvobj(adapter)->clt_port.num)
#endif
struct macid_ctl_t {
_lock lock;
u8 num;
@@ -874,9 +901,13 @@ struct rf_ctl_t {
u8 ch_sel_same_band_prefer;
#ifdef CONFIG_DFS
u8 csa_ch;
#ifdef CONFIG_DFS_MASTER
_timer radar_detect_timer;
bool radar_detect_by_others;
u8 dfs_master_enabled;
u8 radar_detect_enabled;
bool radar_detected;
u8 radar_detect_ch;
@@ -887,12 +918,16 @@ struct rf_ctl_t {
systime cac_end_time;
u8 cac_force_stop;
#ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
u8 dfs_slave_with_rd;
#endif
u8 dfs_ch_sel_d_flags;
u8 dbg_dfs_master_fake_radar_detect_cnt;
u8 dbg_dfs_master_radar_detect_trigger_non;
u8 dbg_dfs_master_choose_dfs_ch_first;
#endif
u8 dbg_dfs_fake_radar_detect_cnt;
u8 dbg_dfs_radar_detect_trigger_non;
u8 dbg_dfs_choose_dfs_ch_first;
#endif /* CONFIG_DFS_MASTER */
#endif /* CONFIG_DFS */
};
#define RTW_CAC_STOPPED 0
@@ -900,12 +935,20 @@ struct rf_ctl_t {
#define IS_CAC_STOPPED(rfctl) ((rfctl)->cac_end_time == RTW_CAC_STOPPED)
#define IS_CH_WAITING(rfctl) (!IS_CAC_STOPPED(rfctl) && rtw_time_after((rfctl)->cac_end_time, rtw_get_current_time()))
#define IS_UNDER_CAC(rfctl) (IS_CH_WAITING(rfctl) && rtw_time_after(rtw_get_current_time(), (rfctl)->cac_start_time))
#define IS_RADAR_DETECTED(rfctl) ((rfctl)->radar_detected)
#else
#define IS_CAC_STOPPED(rfctl) 1
#define IS_CH_WAITING(rfctl) 0
#define IS_UNDER_CAC(rfctl) 0
#define IS_RADAR_DETECTED(rfctl) 0
#endif /* CONFIG_DFS_MASTER */
#ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
#define IS_DFS_SLAVE_WITH_RD(rfctl) ((rfctl)->dfs_slave_with_rd)
#else
#define IS_DFS_SLAVE_WITH_RD(rfctl) 0
#endif
#ifdef CONFIG_MBSSID_CAM
#define TOTAL_MBID_CAM_NUM 8
#define INVALID_CAM_ID 0xFF
@@ -944,6 +987,21 @@ struct halmacpriv {
};
#endif /* RTW_HALMAC */
#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
/*info for H2C-0x2C*/
struct dft_info {
u8 port_id;
u8 mac_id;
};
#endif
#ifdef CONFIG_HW_P0_TSF_SYNC
struct tsf_info {
u8 sync_port;/*port_x's tsf sync to port_0*/
u8 offset; /*tsf timer offset*/
};
#endif
struct dvobj_priv {
/*-------- below is common data --------*/
u8 chip_type;
@@ -973,6 +1031,10 @@ struct dvobj_priv {
_mutex sd_indirect_access_mutex;
#endif
#ifdef CONFIG_SYSON_INDIRECT_ACCESS
_mutex syson_indirect_access_mutex; /* System On Reg R/W */
#endif
unsigned char oper_channel; /* saved channel info when call set_channel_bw */
unsigned char oper_bwmode;
unsigned char oper_ch_offset;/* PRIME_CHNL_OFFSET */
@@ -983,14 +1045,27 @@ struct dvobj_priv {
struct mi_state iface_state;
#ifdef CONFIG_AP_MODE
u8 nr_ap_if; /* total interface s number of ap/go mode. */
u16 inter_bcn_space; /* unit:ms */
#ifdef CONFIG_SUPPORT_MULTI_BCN
u8 nr_ap_if; /* total interface number of ap /go /mesh / nan mode. */
u16 inter_bcn_space; /* unit:ms */
_queue ap_if_q;
#ifdef CONFIG_RTW_REPEATER_SON
u8 vap_map;
u8 fw_bcn_offload;
u8 vap_tbtt_rpt_map;
#endif /*CONFIG_SUPPORT_MULTI_BCN*/
#ifdef CONFIG_RTW_REPEATER_SON
struct rtw_rson_struct rson_data;
#endif
#endif
#ifdef CONFIG_CLIENT_PORT_CFG
struct clt_port_t clt_port;
#endif
#ifdef CONFIG_HW_P0_TSF_SYNC
struct tsf_info p0_tsf;
#endif
systime periodic_tsf_update_etime;
_timer periodic_tsf_update_end_timer;
struct macid_ctl_t macid_ctl;
@@ -1048,8 +1123,14 @@ struct dvobj_priv {
#endif /* RTW_HALMAC */
#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
u8 default_port_id;
/*info for H2C-0x2C*/
struct dft_info dft;
#endif
#ifdef CONFIG_RTW_WIFI_HAL
u32 nodfs;
#endif
/*-------- below is for SDIO INTERFACE --------*/
#ifdef INTF_DATA
@@ -1172,6 +1253,15 @@ struct dvobj_priv {
#ifdef CONFIG_MCC_MODE
struct mcc_obj_priv mcc_objpriv;
#endif /*CONFIG_MCC_MODE */
#ifdef CONFIG_RTW_TPT_MODE
u8 tpt_mode; /* RTK T/P Testing Mode, 0:default mode */
u32 edca_be_ul;
u32 edca_be_dl;
#endif
/* also for RTK T/P Testing Mode */
u8 scan_deny;
};
#define DEV_STA_NUM(_dvobj) MSTATE_STA_NUM(&((_dvobj)->iface_state))
@@ -1185,6 +1275,9 @@ struct dvobj_priv {
#define DEV_ADHOC_LD_NUM(_dvobj) MSTATE_ADHOC_LD_NUM(&((_dvobj)->iface_state))
#define DEV_MESH_NUM(_dvobj) MSTATE_MESH_NUM(&((_dvobj)->iface_state))
#define DEV_MESH_LD_NUM(_dvobj) MSTATE_MESH_LD_NUM(&((_dvobj)->iface_state))
#define DEV_P2P_DV_NUM(_dvobj) MSTATE_P2P_DV_NUM(&((_dvobj)->iface_state))
#define DEV_P2P_GC_NUM(_dvobj) MSTATE_P2P_GC_NUM(&((_dvobj)->iface_state))
#define DEV_P2P_GO_NUM(_dvobj) MSTATE_P2P_GO_NUM(&((_dvobj)->iface_state))
#define DEV_SCAN_NUM(_dvobj) MSTATE_SCAN_NUM(&((_dvobj)->iface_state))
#define DEV_WPS_NUM(_dvobj) MSTATE_WPS_NUM(&((_dvobj)->iface_state))
#define DEV_ROCH_NUM(_dvobj) MSTATE_ROCH_NUM(&((_dvobj)->iface_state))
@@ -1224,7 +1317,7 @@ static inline void dev_clr_drv_stopped(struct dvobj_priv *dvobj)
#define dev_is_drv_stopped(dvobj) (ATOMIC_READ(&dvobj->bDriverStopped) == _TRUE)
#ifdef PLATFORM_LINUX
static struct device *dvobj_to_dev(struct dvobj_priv *dvobj)
static inline struct device *dvobj_to_dev(struct dvobj_priv *dvobj)
{
/* todo: get interface type from dvobj and the return the dev accordingly */
#ifdef RTW_DVOBJ_CHIP_HW_TYPE
@@ -1259,6 +1352,19 @@ enum _hw_port {
MAX_HW_PORT,
};
#ifdef CONFIG_CLIENT_PORT_CFG
enum _client_port {
CLT_PORT0 = HW_PORT1,
CLT_PORT1 = HW_PORT2,
CLT_PORT2 = HW_PORT3,
CLT_PORT3 = HW_PORT4,
CLT_PORT_INVALID = HW_PORT0,
};
#define MAX_CLIENT_PORT_NUM 4
#define get_clt_port(adapter) (adapter->client_port)
#endif
enum _ADAPTER_TYPE {
PRIMARY_ADAPTER,
VIRTUAL_ADAPTER,
@@ -1306,11 +1412,6 @@ typedef struct loopbackdata {
} LOOPBACKDATA, *PLOOPBACKDATA;
#endif
struct tsf_info {
u8 sync_port;/*tsf sync from portx*/
u8 offset; /*tsf timer offset*/
};
#define ADAPTER_TX_BW_2G(adapter) BW_MODE_2G((adapter)->driver_tx_bw_mode)
#define ADAPTER_TX_BW_5G(adapter) BW_MODE_5G((adapter)->driver_tx_bw_mode)
@@ -1319,8 +1420,10 @@ struct _ADAPTER {
int pid[3];/* process id from UI, 0:wps, 1:hostapd, 2:dhcpcd */
int bDongle;/* build-in module or external dongle */
#if defined(CONFIG_AP_MODE) && defined(CONFIG_SUPPORT_MULTI_BCN)
_list list;
u8 vap_id;
#endif
struct dvobj_priv *dvobj;
struct mlme_priv mlmepriv;
struct mlme_ext_priv mlmeextpriv;
@@ -1502,12 +1605,14 @@ struct _ADAPTER {
** refer to iface_id if iface_nums>2 and isprimary is false and the adapter_type value is 0xff.*/
u8 adapter_type;/*be used in Multi-interface to recognize whether is PRIMARY_ADAPTER or not(PRIMARY_ADAPTER/VIRTUAL_ADAPTER) .*/
u8 hw_port; /*interface port type, it depends on HW port */
struct tsf_info tsf;
#ifdef CONFIG_CLIENT_PORT_CFG
u8 client_id;
u8 client_port;
#endif
/*struct tsf_info tsf;*//*reserve define for 8814B*/
/*extend to support multi interface*/
/*IFACE_ID0 is equals to PRIMARY_ADAPTER
IFACE_ID1 is equals to VIRTUAL_ADAPTER*/
u8 iface_id;
#ifdef CONFIG_BR_EXT
@@ -1607,6 +1712,11 @@ struct _ADAPTER {
#define adapter_to_macidctl(adapter) dvobj_to_macidctl(adapter_to_dvobj((adapter)))
#define adapter_mac_addr(adapter) (adapter->mac_addr)
#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
#define adapter_pno_mac_addr(adapter) \
((adapter_wdev_data(adapter))->pno_mac_addr)
#endif
#define adapter_to_chset(adapter) (adapter_to_rfctl((adapter))->channel_set)
#define mlme_to_adapter(mlme) container_of((mlme), struct _ADAPTER, mlmepriv)

2
include/hal_btcoex_wifionly.h
View File

@@ -65,12 +65,14 @@ void halwifionly_phy_set_rf_reg(PVOID pwifionlyContext, enum rf_path eRFPath, u3
void halwifionly_phy_set_bb_reg(PVOID pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data);
void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter);
void hal_btcoex_wifionly_scan_notify(PADAPTER padapter);
void hal_btcoex_wifionly_connect_notify(PADAPTER padapter);
void hal_btcoex_wifionly_hw_config(PADAPTER padapter);
void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter);
void hal_btcoex_wifionly_AntInfoSetting(PADAPTER padapter);
#else
#define hal_btcoex_wifionly_switchband_notify(padapter)
#define hal_btcoex_wifionly_scan_notify(padapter)
#define hal_btcoex_wifionly_connect_notify(padapter)
#define hal_btcoex_wifionly_hw_config(padapter)
#define hal_btcoex_wifionly_initlizevariables(padapter)
#define hal_btcoex_wifionly_AntInfoSetting(padapter)

65
include/hal_com.h
View File

@@ -265,6 +265,8 @@ struct dbg_rx_counter {
u32 rx_ht_fa;
};
u8 rtw_hal_get_port(_adapter *adapter);
#ifdef CONFIG_MBSSID_CAM
#define DBG_MBID_CAM_DUMP
@@ -275,7 +277,10 @@ struct dbg_rx_counter {
u8 rtw_get_mbid_cam_entry_num(_adapter *adapter);
int rtw_mbid_cam_cache_dump(void *sel, const char *fun_name , _adapter *adapter);
int rtw_mbid_cam_dump(void *sel, const char *fun_name, _adapter *adapter);
void rtw_mbid_cam_restore(_adapter *adapter);
void rtw_mi_set_mbid_cam(_adapter *adapter);
u8 rtw_mbid_camid_alloc(_adapter *adapter, u8 *mac_addr);
void rtw_ap_set_mbid_num(_adapter *adapter, u8 ap_num);
void rtw_mbid_cam_enable(_adapter *adapter);
#endif
#ifdef CONFIG_MI_WITH_MBSSID_CAM
@@ -284,6 +289,7 @@ struct dbg_rx_counter {
#ifdef CONFIG_SWTIMER_BASED_TXBCN
u16 rtw_hal_bcn_interval_adjust(_adapter *adapter, u16 bcn_interval);
#endif
void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode);
#endif
void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter);
@@ -343,6 +349,7 @@ bool hal_chk_proto_cap(_adapter *adapter, u8 cap);
bool hal_is_band_support(_adapter *adapter, u8 band);
bool hal_is_bw_support(_adapter *adapter, u8 bw);
bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode);
bool hal_is_mimo_support(_adapter *adapter);
u8 hal_largest_bw(_adapter *adapter, u8 in_bw);
bool hal_chk_wl_func(_adapter *adapter, u8 func);
@@ -358,6 +365,10 @@ void hal_com_config_channel_plan(
);
int hal_config_macaddr(_adapter *adapter, bool autoload_fail);
#ifdef RTW_HALMAC
void rtw_hal_hw_port_enable(_adapter *adapter);
void rtw_hal_hw_port_disable(_adapter *adapter);
#endif
BOOLEAN
HAL_IsLegalChannel(
@@ -382,7 +393,7 @@ Hal_MappingOutPipe(
void rtw_dump_fw_info(void *sel, _adapter *adapter);
void rtw_restore_hw_port_cfg(_adapter *adapter);
void rtw_restore_mac_addr(_adapter *adapter);/*set mac addr when hal_init for all iface*/
void rtw_mi_set_mac_addr(_adapter *adapter);/*set mac addr when hal_init for all iface*/
void rtw_hal_dump_macaddr(void *sel, _adapter *adapter);
void rtw_init_hal_com_default_value(PADAPTER Adapter);
@@ -418,6 +429,11 @@ u8 rtw_hal_rcr_add(_adapter *adapter, u32 add);
u8 rtw_hal_rcr_clear(_adapter *adapter, u32 clear);
void rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action);
void rtw_iface_enable_tsf_update(_adapter *adapter);
void rtw_iface_disable_tsf_update(_adapter *adapter);
void rtw_hal_periodic_tsf_update_chk(_adapter *adapter);
void rtw_hal_periodic_tsf_update_end_timer_hdl(void *ctx);
void hw_var_port_switch(_adapter *adapter);
u8 SetHwReg(PADAPTER padapter, u8 variable, u8 *val);
@@ -511,13 +527,16 @@ u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qsel);
u8 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta);
u8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta);
#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
void rtw_hal_set_pathb_phase(_adapter *adapter, u8 phase_idx);
#endif
void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished);
u8 rtw_hal_get_rsvd_page_num(struct _ADAPTER *adapter);
#ifdef CONFIG_TSF_RESET_OFFLOAD
int rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port);
#endif
u64 rtw_hal_get_tsftr_by_port(_adapter *adapter, u8 port);
#ifdef CONFIG_TDLS
#ifdef CONFIG_TDLS_CH_SW
@@ -525,7 +544,7 @@ int rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port);
#endif
#endif
#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
s32 rtw_hal_set_wifi_port_id_cmd(_adapter *adapter);
s32 rtw_hal_set_wifi_btc_port_id_cmd(_adapter *adapter);
#endif
#ifdef CONFIG_GPIO_API
@@ -553,16 +572,13 @@ void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case);
#endif
void update_IOT_info(_adapter *padapter);
#ifdef CONFIG_RTS_FULL_BW
void rtw_set_rts_bw(_adapter *padapter);
#endif/*CONFIG_RTS_FULL_BW*/
void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap);
void rtw_hal_correct_tsf(_adapter *padapter, u8 hw_port, u64 tsf);
void ResumeTxBeacon(_adapter *padapter);
void StopTxBeacon(_adapter *padapter);
#ifdef CONFIG_MI_WITH_MBSSID_CAM /*HW port0 - MBSS*/
void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode);
u8 rtw_mbid_camid_alloc(_adapter *adapter, u8 *mac_addr);
#endif
#ifdef CONFIG_ANTENNA_DIVERSITY
u8 rtw_hal_antdiv_before_linked(_adapter *padapter);
@@ -592,7 +608,8 @@ void StopTxBeacon(_adapter *padapter);
enum lps_pg_hdl_id {
LPS_PG_INFO_CFG = 0,
LPS_PG_REDLEMEM,
LPS_PG_RESEND_H2C,
LPS_PG_PHYDM_DIS,
LPS_PG_PHYDM_EN,
};
u8 rtw_hal_set_lps_pg_info(_adapter *adapter);
@@ -601,7 +618,7 @@ enum lps_pg_hdl_id {
int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, u32 page_num, u8 *buffer, u32 buffer_size);
void rtw_hal_construct_beacon(_adapter *padapter, u8 *pframe, u32 *pLength);
void rtw_hal_construct_NullFunctionData(PADAPTER, u8 *pframe, u32 *pLength,
u8 *StaAddr, u8 bQoS, u8 AC, u8 bEosp, u8 bForcePowerSave);
u8 bQoS, u8 AC, u8 bEosp, u8 bForcePowerSave);
#ifdef CONFIG_WOWLAN
struct rtl_wow_pattern {
@@ -645,6 +662,11 @@ void rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32
s32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id);
s32 rtw_set_default_port_id(_adapter *adapter);
s32 rtw_set_ps_rsvd_page(_adapter *adapter);
#define get_dft_portid(adapter) (adapter_to_dvobj(adapter)->dft.port_id)
#define get_dft_macid(adapter) (adapter_to_dvobj(adapter)->dft.mac_id)
/*void rtw_search_default_port(_adapter *adapter);*/
#endif
#ifdef CONFIG_P2P_PS
@@ -659,6 +681,10 @@ void rtw_hal_switch_chnl_and_set_bw_offload(_adapter *adapter, u8 central_ch, u8
s16 translate_dbm_to_percentage(s16 signal);
#ifdef CONFIG_SUPPORT_MULTI_BCN
void rtw_ap_multi_bcn_cfg(_adapter *adapter);
#endif
#ifdef CONFIG_SWTIMER_BASED_TXBCN
#ifdef CONFIG_BCN_RECOVERY
u8 rtw_ap_bcn_recovery(_adapter *padapter);
@@ -668,6 +694,11 @@ u8 rtw_ap_bcn_queue_empty_check(_adapter *padapter, u32 txbcn_timer_ms);
#endif
#endif /*CONFIG_SWTIMER_BASED_TXBCN*/
#ifdef CONFIG_FW_HANDLE_TXBCN
void rtw_ap_mbid_bcn_en(_adapter *adapter, u8 mbcn_id);
void rtw_ap_mbid_bcn_dis(_adapter *adapter, u8 mbcn_id);
#endif
void rtw_hal_get_rf_path(struct dvobj_priv *d, enum rf_type *type,
enum bb_path *tx, enum bb_path *rx);
#ifdef CONFIG_BEAMFORMING
@@ -675,4 +706,14 @@ void rtw_hal_get_rf_path(struct dvobj_priv *d, enum rf_type *type,
void rtw_hal_beamforming_config_csirate(PADAPTER adapter);
#endif
#endif
#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8812A) ||\
defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8192E) ||\
defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821A)
u8 phy_get_current_tx_num(IN PADAPTER pAdapter, IN u8 Rate);
#endif
#ifdef CONFIG_RTL8812A
u8 * rtw_hal_set_8812a_vendor_ie(_adapter *padapter , u8 *pframe ,uint *frlen );
#endif
#endif /* __HAL_COMMON_H__ */

58
include/hal_com_h2c.h
View File

@@ -110,9 +110,13 @@ enum h2c_cmd {
H2C_AOAC_RSVDPAGE3 = 0x88,
H2C_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
H2C_P2P_OFFLOAD = 0x8B,
#ifdef CONFIG_FW_HANDLE_TXBCN
H2C_FW_BCN_OFFLOAD = 0xBA,
#endif
H2C_RESET_TSF = 0xC0,
#ifdef CONFIG_FW_CORRECT_BCN
H2C_BCNHWSEQ = 0xC5,
#endif
H2C_CUSTOMER_STR_W1 = 0xC6,
H2C_CUSTOMER_STR_W2 = 0xC7,
H2C_CUSTOMER_STR_W3 = 0xC8,
@@ -122,7 +126,7 @@ enum h2c_cmd {
H2C_MAXID,
};
#define H2C_INACTIVE_PS_LEN 3
#define H2C_INACTIVE_PS_LEN 4
#define H2C_RSVDPAGE_LOC_LEN 5
#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
#define H2C_DEFAULT_PORT_ID_LEN 2
@@ -139,7 +143,7 @@ enum h2c_cmd {
#define H2C_PSTUNEPARAM_LEN 4
#define H2C_MACID_CFG_LEN 7
#define H2C_BTMP_OPER_LEN 5
#define H2C_WOWLAN_LEN 6
#define H2C_WOWLAN_LEN 7
#define H2C_REMOTE_WAKE_CTRL_LEN 3
#define H2C_AOAC_GLOBAL_INFO_LEN 2
#define H2C_AOAC_RSVDPAGE_LOC_LEN 7
@@ -189,29 +193,6 @@ enum h2c_cmd {
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
/*
* ARP packet
*
* LLC Header */
#define GET_ARP_PKT_LLC_TYPE(__pHeader) ReadLE2Byte(((u8 *)(__pHeader)) + 6)
/* ARP element */
#define GET_ARP_PKT_OPERATION(__pHeader) ReadLE2Byte(((u8 *)(__pHeader)) + 6)
#define GET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cp_mac_addr((u8 *)(_val), ((u8 *)(__pHeader))+8)
#define GET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr((u8 *)(_val), ((u8 *)(__pHeader))+14)
#define GET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cp_mac_addr((u8 *)(_val), ((u8 *)(__pHeader))+18)
#define GET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr((u8 *)(_val), ((u8 *)(__pHeader))+24)
#define SET_ARP_PKT_HW(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 0, __Value)
#define SET_ARP_PKT_PROTOCOL(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 2, __Value)
#define SET_ARP_PKT_HW_ADDR_LEN(__pHeader, __Value) WriteLE1Byte(((u8 *)(__pHeader)) + 4, __Value)
#define SET_ARP_PKT_PROTOCOL_ADDR_LEN(__pHeader, __Value) WriteLE1Byte(((u8 *)(__pHeader)) + 5, __Value)
#define SET_ARP_PKT_OPERATION(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 6, __Value)
#define SET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cp_mac_addr(((u8 *)(__pHeader))+8, (u8 *)(_val))
#define SET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr(((u8 *)(__pHeader))+14, (u8 *)(_val))
#define SET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cp_mac_addr(((u8 *)(__pHeader))+18, (u8 *)(_val))
#define SET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr(((u8 *)(__pHeader))+24, (u8 *)(_val))
#define FW_WOWLAN_FUN_EN BIT(0)
#define FW_WOWLAN_PATTERN_MATCH BIT(1)
#define FW_WOWLAN_MAGIC_PKT BIT(2)
@@ -236,6 +217,9 @@ enum h2c_cmd {
#define FW_REALWOWLAN_EN BIT(5)
#define FW_WOW_FW_UNICAST_EN BIT(7)
#define FW_IPS_DISABLE_BBRF BIT(0)
#define FW_IPS_WRC BIT(1)
#endif /* CONFIG_WOWLAN */
/* _RSVDPAGE_LOC_CMD_0x00 */
@@ -293,9 +277,12 @@ s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool
/* _DISCONNECT_DECISION_CMD_0x04 */
#define SET_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_H2CCMD_DISCONDECISION_PARM_TRY_BCN_FAIL_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
#define SET_H2CCMD_DISCONDECISION_PARM_DISCONNECT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
#define SET_H2CCMD_DISCONDECISION_PORT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 3, __Value)
#define SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
#define SET_H2CCMD_DISCONDECISION_PARM_TRY_OK_BCN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
#ifdef CONFIG_RTW_CUSTOMER_STR
#define RTW_CUSTOMER_STR_LEN 16
@@ -348,6 +335,22 @@ s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs);
#define SET_H2CCMD_AP_WOW_PS_RF(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
#define SET_H2CCMD_AP_WOW_PS_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
/* INACTIVE_PS 0x27, duration unit is TBTT */
#define SET_H2CCMD_INACTIVE_PS_EN(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_H2CCMD_INACTIVE_IGNORE_PS(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_H2CCMD_INACTIVE_PERIOD_SCAN_EN(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
#define SET_H2CCMD_INACTIVE_DISBBRF(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
#define SET_H2CCMD_INACTIVE_PS_FREQ(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd + 1, 0, 8, __Value)
#define SET_H2CCMD_INACTIVE_PS_DURATION(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd + 2, 0, 8, __Value)
#define SET_H2CCMD_INACTIVE_PS_PERIOD_SCAN_TIME(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd + 3, 0, 8, __Value)
#ifdef CONFIG_LPS_POFF
/*PARTIAL OFF Control 0x29*/
#define SET_H2CCMD_LPS_POFF_CTRL_EN(__pH2CCmd, __Value) \
@@ -485,6 +488,9 @@ s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs);
#define SET_H2CCMD_WOWLAN_UNIT_FOR_UPHY_DISABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value)
#define SET_H2CCMD_WOWLAN_TAKE_PDN_UPHY_DIS_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 1, __Value)
#define SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 5, 1, __Value)
#define SET_H2CCMD_WOWLAN_DEV2HST_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 7, 1, __Value)
#define SET_H2CCMD_WOWLAN_TIME_FOR_UPHY_DISABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
#define SET_H2CCMD_WOWLAN_RISE_HST2DEV(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 2, 1, __Value)
/* _REMOTE_WAKEUP_CMD_0x81 */
#define SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)

10
include/hal_com_phycfg.h
View File

@@ -29,8 +29,6 @@ typedef enum _RF_TX_NUM {
RF_TX_NUM_NONIMPLEMENT,
} RF_TX_NUM;
#define MAX_POWER_INDEX 0x3F
/*------------------------------Define structure----------------------------*/
typedef struct _BB_REGISTER_DEFINITION {
u32 rfintfs; /* set software control: */
@@ -182,9 +180,9 @@ s8 PHY_GetTxPowerLimit(_adapter *adapter
, u8 rfpath, u8 rate, u8 ntx_idx, u8 cch
);
#else
#define phy_get_txpwr_lmt_abs(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock) MAX_POWER_INDEX
#define phy_get_txpwr_lmt(adapter, regd_name, band, bw, rfpath, rs, ntx_idx, cch, lock) MAX_POWER_INDEX
#define PHY_GetTxPowerLimit(adapter, regd_name, band, bw, rfpath, rate, ntx_idx, cch) MAX_POWER_INDEX
#define phy_get_txpwr_lmt_abs(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max)
#define phy_get_txpwr_lmt(adapter, regd_name, band, bw, rfpath, rs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max)
#define PHY_GetTxPowerLimit(adapter, regd_name, band, bw, rfpath, rate, ntx_idx, cch) (GET_HAL_SPEC(adapter)->txgi_max)
#endif /* CONFIG_TXPWR_LIMIT */
s8
@@ -297,5 +295,5 @@ int PHY_ConfigRFWithPowerLimitTableParaFile(IN PADAPTER Adapter, IN const char *
void phy_free_filebuf_mask(_adapter *padapter, u8 mask);
void phy_free_filebuf(_adapter *padapter);
#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */
u8 phy_check_under_survey_ch(_adapter *adapter);
#endif /* __HAL_COMMON_H__ */

64
include/hal_com_reg.h
View File

@@ -257,7 +257,7 @@
#define REG_LIFETIME_CTRL 0x0426
#define REG_MULTI_BCNQ_OFFSET 0x0427
#define REG_SPEC_SIFS 0x0428
#define REG_RL 0x042A
#define REG_RETRY_LIMIT 0x042A
#define REG_DARFRC 0x0430
#define REG_RARFRC 0x0438
#define REG_RRSR 0x0440
@@ -369,7 +369,7 @@
#define REG_BCN_CTRL_1 0x0551
#define REG_MBID_NUM 0x0552
#define REG_DUAL_TSF_RST 0x0553
#define REG_BCN_INTERVAL 0x0554 /* The same as REG_MBSSID_BCN_SPACE */
#define REG_MBSSID_BCN_SPACE 0x0554
#define REG_DRVERLYINT 0x0558
#define REG_BCNDMATIM 0x0559
#define REG_ATIMWND 0x055A
@@ -429,6 +429,8 @@
#define REG_CTS2TO 0x0641
#define REG_EIFS 0x0642
/*REG_TCR*/
#define BIT_PWRBIT_OW_EN BIT(7)
/* RXERR_RPT */
#define RXERR_TYPE_OFDM_PPDU 0
@@ -490,9 +492,20 @@
#define REG_BCN_PSR_RPT 0x06A8
#define REG_BT_COEX_TABLE 0x06C0
#define BIT_WKFCAM_WE BIT(16)
#define BIT_WKFCAM_POLLING_V1 BIT(31)
#define BIT_WKFCAM_CLR_V1 BIT(30)
#define BIT_SHIFT_WKFCAM_ADDR_V2 8
#define BIT_MASK_WKFCAM_ADDR_V2 0xff
#define BIT_WKFCAM_ADDR_V2(x) (((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2)
/* Hardware Port 1 */
#define REG_MACID1 0x0700
#define REG_BSSID1 0x0708
/* Enable/Disable Port 0 and Port 1 for Specific ICs (ex. 8192F)*/
#define REG_WLAN_ACT_MASK_CTRL_1 0x076C
/* Hardware Port 2 */
#define REG_MACID2 0x1620
#define REG_BSSID2 0x1628
@@ -1379,7 +1392,8 @@ Current IOREG MAP
#define QUEUE_LOW 1
#define QUEUE_NORMAL 2
#define QUEUE_HIGH 3
#define QUEUE_EXTRA_1 4
#define QUEUE_EXTRA_2 5
/* 2 TRXFF_BNDY */
@@ -1481,8 +1495,13 @@ Current IOREG MAP
#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
/* 2 RL */
#define RETRY_LIMIT_SHORT_SHIFT 8
#define RETRY_LIMIT_LONG_SHIFT 0
#define BIT_SHIFT_SRL 8
#define BIT_MASK_SRL 0x3f
#define BIT_SRL(x) (((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL)
#define BIT_SHIFT_LRL 0
#define BIT_MASK_LRL 0x3f
#define BIT_LRL(x) (((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL)
#define RL_VAL_AP 7
#ifdef CONFIG_RTW_CUSTOMIZE_RLSTA
@@ -1502,11 +1521,6 @@ Current IOREG MAP
#define AC_PARAM_ECW_MIN_OFFSET 8
#define AC_PARAM_AIFS_OFFSET 0
#define _LRL(x) ((x) & 0x3F)
#define _SRL(x) (((x) & 0x3F) << 8)
/* 2 BCN_CTRL */
#define EN_TXBCN_RPT BIT(2)
#define EN_BCN_FUNCTION BIT(3)
@@ -1517,11 +1531,6 @@ Current IOREG MAP
#define DIS_BCNQ_SUB BIT(1)
#define DIS_TSF_UDT BIT(4)
/* The same function but different bit field. */
#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)
#define DIS_TSF_UDT0_TEST_CHIP BIT(5)
/* 2 ACMHWCTRL */
#define AcmHw_HwEn BIT(0)
#define AcmHw_VoqEn BIT(1)
@@ -1610,6 +1619,13 @@ Current IOREG MAP
#define BIT_LSIC_TXOP_EN BIT(17)
#define BIT_CTS_EN BIT(16)
/*REG_RXFLTMAP1 (Offset 0x6A2)*/
#define BIT_CTRLFLT10EN BIT(10) /*PS-POLL*/
/*REG_WLAN_ACT_MASK_CTRL_1 (Offset 0x76C)*/
#define EN_PORT_0_FUNCTION BIT(12)
#define EN_PORT_1_FUNCTION BIT(13)
/* -----------------------------------------------------
*
* SDIO Bus Specification
@@ -1651,6 +1667,7 @@ Current IOREG MAP
#define SDIO_MAX_RX_QUEUE 1
#define SDIO_REG_TX_CTRL 0x0000 /* SDIO Tx Control */
#define SDIO_REG_TIMEOUT 0x0002/*SDIO status timeout*/
#define SDIO_REG_HIMR 0x0014 /* SDIO Host Interrupt Mask */
#define SDIO_REG_HISR 0x0018 /* SDIO Host Interrupt Service Routine */
#define SDIO_REG_HCPWM 0x0019 /* HCI Current Power Mode */
@@ -1745,6 +1762,19 @@ Current IOREG MAP
#define SDIO_TX_FREE_PG_QUEUE 4 /* The number of Tx FIFO free page */
#define SDIO_TX_FIFO_PAGE_SZ 128
/* indirect access */
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
#define SDIO_REG_INDIRECT_REG_CFG 0x40
#define SDIO_REG_INDIRECT_REG_DATA 0x44
#define SET_INDIRECT_REG_ADDR(_cmd, _addr) SET_BITS_TO_LE_2BYTE(((u8 *)(_cmd)) + 0, 0, 16, (_addr))
#define SET_INDIRECT_REG_SIZE_1BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 0)
#define SET_INDIRECT_REG_SIZE_2BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 1)
#define SET_INDIRECT_REG_SIZE_4BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 2)
#define SET_INDIRECT_REG_WRITE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 2, 1, 1)
#define SET_INDIRECT_REG_READ(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 3, 1, 1)
#define GET_INDIRECT_REG_RDY(_cmd) LE_BITS_TO_1BYTE(((u8 *)(_cmd)) + 2, 4, 1)
#endif/*CONFIG_SDIO_INDIRECT_ACCESS*/
#ifdef CONFIG_SDIO_HCI
#define MAX_TX_AGG_PACKET_NUMBER 0x8
#else
@@ -1822,8 +1852,10 @@ Current IOREG MAP
#define LAST_ENTRY_OF_TX_PKT_BUFFER_8703B 255
#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127
#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188F 255
#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188GTV 255
#define LAST_ENTRY_OF_TX_PKT_BUFFER_8723D 255
#define LAST_ENTRY_OF_TX_PKT_BUFFER_8710B 255
#define LAST_ENTRY_OF_TX_PKT_BUFFER_8192F 255
#define POLLING_LLT_THRESHOLD 20
#if defined(CONFIG_RTL8723B) && defined(CONFIG_PCI_HCI)
#define POLLING_READY_TIMEOUT_COUNT 6000

41
include/hal_data.h
View File

@@ -21,6 +21,7 @@
#ifdef CONFIG_BT_COEXIST
#include <hal_btcoex.h>
#endif
#include <hal_btcoex_wifionly.h>
#ifdef CONFIG_SDIO_HCI
#include <hal_sdio.h>
@@ -133,10 +134,19 @@ typedef enum _RX_AGG_MODE {
#ifdef CONFIG_RTL8188F
#define EFUSE_MAP_SIZE 512
#endif
#ifdef CONFIG_RTL8188GTV
#define EFUSE_MAP_SIZE 512
#endif
#ifdef CONFIG_RTL8710B
#define EFUSE_MAP_SIZE 512
#endif
#ifdef CONFIG_RTL8192F
#define EFUSE_MAP_SIZE 512
#endif
#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
#define EFUSE_MAX_SIZE 1024
#elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8703B)
#elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8710B)
#define EFUSE_MAX_SIZE 256
#else
#define EFUSE_MAX_SIZE 512
@@ -217,6 +227,8 @@ struct hal_spec_t {
u8 rfpath_num_2g:4; /* used for tx power index path */
u8 rfpath_num_5g:4; /* used for tx power index path */
u8 txgi_max; /* maximum tx power gain index */
u8 txgi_pdbm; /* tx power gain index per dBm */
u8 max_tx_cnt;
u8 tx_nss_num:4;
@@ -227,7 +239,10 @@ struct hal_spec_t {
u8 proto_cap; /* value of PROTO_CAP_XXX */
u8 wl_func; /* value of WL_FUNC_XXX */
u8 rx_tsf_filter:1;
u8 pg_txpwr_saddr; /* starting address of PG tx power info */
u8 pg_txgi_diff_factor; /* PG tx power gain index diff to tx power gain index */
u8 hci_type; /* value of HCI Type */
};
@@ -265,7 +280,7 @@ typedef struct hal_p2p_ps_para {
u8 noa_sel:1;
u8 all_sta_sleep:1;
u8 discovery:1;
u8 rsvd2:1;
u8 disable_close_rf:1;
u8 p2p_port_id;
u8 p2p_group;
u8 p2p_macid;
@@ -382,8 +397,9 @@ typedef struct hal_com_data {
u16 ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */
u8 bDumpRxPkt;
u8 bDumpTxPkt;
u8 dis_turboedca;
u8 dis_turboedca; /* 1: disable turboedca,
2: disable turboedca and setting EDCA parameter based on the input parameter*/
u32 edca_param_mode;
/****** EEPROM setting.******/
u8 bautoload_fail_flag;
@@ -429,7 +445,9 @@ typedef struct hal_com_data {
#endif /*CONFIG_RF_POWER_TRIM*/
#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \
defined(CONFIG_RTL8723D)
defined(CONFIG_RTL8723D) || \
defined(CONFIG_RTL8192F)
u8 adjuseVoltageVal;
u8 need_restore;
#endif
@@ -524,6 +542,7 @@ typedef struct hal_com_data {
u64 bk_rf_ability;
u8 bIQKInitialized;
u8 bNeedIQK;
u8 neediqk_24g;
u8 IQK_MP_Switch;
u8 bScanInProcess;
/******** PHY DM & DM Section **********/
@@ -537,7 +556,11 @@ typedef struct hal_com_data {
u32 interfaceIndex;
#ifdef CONFIG_P2P
#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
u16 p2p_ps_offload;
#else
u8 p2p_ps_offload;
#endif
#endif
/* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
u8 bMacPwrCtrlOn;
@@ -579,7 +602,11 @@ typedef struct hal_com_data {
/* SDIO Tx FIFO related. */
/* */
/* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */
#ifdef CONFIG_RTL8192F
u16 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
#else
u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
#endif/*CONFIG_RTL8192F*/
_lock SdioTxFIFOFreePageLock;
u8 SdioTxOQTMaxFreeSpace;
u8 SdioTxOQTFreeSpace;
@@ -683,7 +710,7 @@ typedef struct hal_com_data {
#endif /* CONFIG_BT_COEXIST */
#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) \
|| defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8723D)
|| defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D)|| defined(CONFIG_RTL8192F)
#ifndef CONFIG_PCI_HCI /* mutual exclusive with PCI -- so they're SDIO and GSPI */
/* Interrupt relatd register information. */
u32 SysIntrStatus;
@@ -735,7 +762,7 @@ typedef struct hal_com_data {
struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM];
#ifdef RTW_HALMAC
u8 drv_rsvd_page_number;
u16 drv_rsvd_page_number;
#endif
#ifdef CONFIG_BEAMFORMING

85
include/hal_ic_cfg.h
View File

@@ -21,6 +21,7 @@
#define RTL8723B_SUPPORT 0
#define RTL8723D_SUPPORT 0
#define RTL8192E_SUPPORT 0
#define RTL8192F_SUPPORT 0
#define RTL8814A_SUPPORT 0
#define RTL8195A_SUPPORT 0
#define RTL8197F_SUPPORT 0
@@ -32,9 +33,13 @@
#define RTL8710B_SUPPORT 0
#define RTL8814B_SUPPORT 0
#define RTL8824B_SUPPORT 0
#define RTL8192F_SUPPORT 0
#define RTL8198F_SUPPORT 0
#define RTL8195B_SUPPORT 0
#define RTL8822C_SUPPORT 0
#define RTL8812F_SUPPORT 0
#define RTL8197G_SUPPORT 0
#define RTL8721D_SUPPORT 0
/*#if (RTL8188E_SUPPORT==1)*/
#define RATE_ADAPTIVE_SUPPORT 0
#define POWER_TRAINING_ACTIVE 0
@@ -58,6 +63,7 @@
#ifndef CONFIG_FW_C2H_PKT
#define CONFIG_FW_C2H_PKT
#endif
#define CONFIG_RTS_FULL_BW
#endif
#ifdef CONFIG_RTL8821A
@@ -66,6 +72,7 @@
#ifndef CONFIG_FW_C2H_PKT
#define CONFIG_FW_C2H_PKT
#endif
#define CONFIG_RTS_FULL_BW
#endif
#ifdef CONFIG_RTL8192E
@@ -74,6 +81,24 @@
#ifndef CONFIG_FW_C2H_PKT
#define CONFIG_FW_C2H_PKT
#endif
#define CONFIG_RTS_FULL_BW
#endif
#ifdef CONFIG_RTL8192F
#undef RTL8192F_SUPPORT
#define RTL8192F_SUPPORT 1
#ifndef CONFIG_FW_C2H_PKT
#define CONFIG_FW_C2H_PKT
#endif
#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
#define CONFIG_RTW_MAC_HIDDEN_RPT
#endif
/*#define CONFIG_AMPDU_PRETX_CD*/
/*#define DBG_LA_MODE*/
#ifdef CONFIG_P2P_PS
#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
#endif
#define CONFIG_RTS_FULL_BW
#endif
#ifdef CONFIG_RTL8723B
@@ -82,6 +107,7 @@
#ifndef CONFIG_FW_C2H_PKT
#define CONFIG_FW_C2H_PKT
#endif
#define CONFIG_RTS_FULL_BW
#endif
#ifdef CONFIG_RTL8723D
@@ -96,6 +122,7 @@
#ifndef CONFIG_RTW_CUSTOMER_STR
#define CONFIG_RTW_CUSTOMER_STR
#endif
#define CONFIG_RTS_FULL_BW
#endif
#ifdef CONFIG_RTL8814A
@@ -104,6 +131,8 @@
#ifndef CONFIG_FW_C2H_PKT
#define CONFIG_FW_C2H_PKT
#endif
#define CONFIG_FW_CORRECT_BCN
#define CONFIG_RTS_FULL_BW
#endif
#ifdef CONFIG_RTL8703B
@@ -115,6 +144,7 @@
#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
#define CONFIG_RTW_MAC_HIDDEN_RPT
#endif
#define CONFIG_RTS_FULL_BW
#endif
#ifdef CONFIG_RTL8188F
@@ -129,6 +159,22 @@
#ifndef CONFIG_RTW_CUSTOMER_STR
#define CONFIG_RTW_CUSTOMER_STR
#endif
#define CONFIG_RTS_FULL_BW
#endif
#ifdef CONFIG_RTL8188GTV
#undef RTL8188F_SUPPORT
#define RTL8188F_SUPPORT 1
#ifndef CONFIG_FW_C2H_PKT
#define CONFIG_FW_C2H_PKT
#endif
#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
#define CONFIG_RTW_MAC_HIDDEN_RPT
#endif
#ifndef CONFIG_RTW_CUSTOMER_STR
#define CONFIG_RTW_CUSTOMER_STR
#endif
#define CONFIG_RTS_FULL_BW
#endif
#ifdef CONFIG_RTL8822B
@@ -139,6 +185,7 @@
#endif /* CONFIG_FW_C2H_PKT */
#define RTW_TX_PA_BIAS /* Adjust TX PA Bias from eFuse */
#define CONFIG_DFS /* Enable 5G band 2&3 channel */
#define RTW_AMPDU_AGG_RETRY_AND_NEW
#ifdef CONFIG_WOWLAN
#define CONFIG_GTK_OL
@@ -177,6 +224,11 @@
#ifndef RTW_IQK_FW_OFFLOAD
#define RTW_IQK_FW_OFFLOAD
#endif /* RTW_IQK_FW_OFFLOAD */
/* Checksum offload feature */
/*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/ /* not ready */
#define CONFIG_TCP_CSUM_OFFLOAD_RX
#define CONFIG_ADVANCE_OTA
#ifdef CONFIG_MCC_MODE
@@ -197,10 +249,13 @@
/* Supported since fw v22.1 */
#define RTW_PER_CMD_SUPPORT_FW
#endif /* RTW_PER_CMD_SUPPORT_FW */
#ifndef CONFIG_DYNAMIC_SOML
#define CONFIG_DYNAMIC_SOML
#endif /* CONFIG_DYNAMIC_SOML */
#define CONFIG_SUPPORT_FIFO_DUMP
#define CONFIG_HW_P0_TSF_SYNC
#define CONFIG_BCN_RECV_TIME
#ifdef CONFIG_P2P_PS
#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
#endif
#define CONFIG_RTS_FULL_BW
#endif /* CONFIG_RTL8822B */
#ifdef CONFIG_RTL8821C
@@ -230,15 +285,29 @@
#endif /* RTW_IQK_FW_OFFLOAD */
/*#define CONFIG_AMPDU_PRETX_CD*/
/*#define DBG_PRE_TX_HANG*/
/*
* Beamforming related definition
*/
/* Beamforming related definition */
/* Beamforming mechanism is on driver not phydm, always disable it */
#define BEAMFORMING_SUPPORT 0
/* Only support new beamforming mechanism */
#ifdef CONFIG_BEAMFORMING
#define RTW_BEAMFORMING_VERSION_2
#endif /* CONFIG_BEAMFORMING */
#define CONFIG_HW_P0_TSF_SYNC
#define CONFIG_BCN_RECV_TIME
#ifdef CONFIG_P2P_PS
#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
#endif
#define CONFIG_RTS_FULL_BW
#endif /*CONFIG_RTL8821C*/
#ifdef CONFIG_RTL8710B
#undef RTL8710B_SUPPORT
#define RTL8710B_SUPPORT 1
#ifndef CONFIG_FW_C2H_PKT
#define CONFIG_FW_C2H_PKT
#endif
#define CONFIG_RTS_FULL_BW
#endif
#endif /*__HAL_IC_CFG_H__*/

71
include/hal_intf.h
View File

@@ -34,9 +34,12 @@ enum _CHIP_TYPE {
RTL8814A,
RTL8703B,
RTL8188F,
RTL8188GTV,
RTL8822B,
RTL8723D,
RTL8821C,
RTL8710B,
RTL8192F,
MAX_CHIP_TYPE
};
@@ -67,6 +70,7 @@ typedef enum _HW_VARIABLES {
HW_VAR_BASIC_RATE,
HW_VAR_TXPAUSE,
HW_VAR_BCN_FUNC,
HW_VAR_BCN_CTRL_ADDR,
HW_VAR_CORRECT_TSF,
HW_VAR_RCR,
HW_VAR_MLME_DISCONNECT,
@@ -82,7 +86,6 @@ typedef enum _HW_VARIABLES {
HW_VAR_SEC_DK_CFG,
HW_VAR_BCN_VALID,
HW_VAR_RF_TYPE,
HW_VAR_TSF,
HW_VAR_FREECNT,
/* PHYDM odm->SupportAbility */
@@ -97,11 +100,14 @@ typedef enum _HW_VARIABLES {
HW_VAR_UAPSD_TID,
#endif /* CONFIG_WMMPS_STA */
HW_VAR_AMPDU_MIN_SPACE,
#ifdef CONFIG_80211N_HT
HW_VAR_AMPDU_FACTOR,
#endif /* CONFIG_80211N_HT */
HW_VAR_RXDMA_AGG_PG_TH,
HW_VAR_SET_RPWM,
HW_VAR_CPWM,
HW_VAR_H2C_FW_PWRMODE,
HW_VAR_H2C_INACTIVE_IPS,
HW_VAR_H2C_PS_TUNE_PARAM,
HW_VAR_H2C_FW_JOINBSSRPT,
HW_VAR_FWLPS_RF_ON,
@@ -195,9 +201,19 @@ typedef enum _HW_VARIABLES {
#endif
HW_VAR_DUMP_MAC_TXFIFO,
HW_VAR_PWR_CMD,
#ifdef CONFIG_FW_HANDLE_TXBCN
HW_VAR_BCN_HEAD_SEL,
#endif
HW_VAR_SET_SOML_PARAM,
HW_VAR_ENABLE_RX_BAR,
HW_VAR_TSF_AUTO_SYNC,
HW_VAR_LPS_STATE_CHK,
#ifdef CONFIG_RTS_FULL_BW
HW_VAR_SET_RTS_BW,
#endif
#if defined(CONFIG_PCI_HCI)
HW_VAR_ENSWBCN,
#endif
} HW_VARIABLES;
typedef enum _HAL_DEF_VARIABLE {
@@ -305,6 +321,7 @@ struct hal_ops {
u8(*check_ips_status)(_adapter *padapter);
#if defined(CONFIG_PCI_HCI)
s32(*interrupt_handler)(_adapter *padapter);
void (*unmap_beacon_icf)(_adapter *padapter);
#endif
#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
@@ -351,7 +368,10 @@ struct hal_ops {
void (*write_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
u32 (*read_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask);
void (*write_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
#ifdef CONFIG_SYSON_INDIRECT_ACCESS
u32 (*read_syson_reg)(_adapter *padapter, u32 RegAddr, u32 BitMask);
void (*write_syson_reg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
#endif
void (*read_wmmedca_reg)(_adapter *padapter, u16 *vo_params, u16 *vi_params, u16 *be_params, u16 *bk_params);
#ifdef CONFIG_HOSTAPD_MLME
@@ -367,6 +387,9 @@ struct hal_ops {
int (*Efuse_PgPacketWrite)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
u8(*Efuse_WordEnableDataWrite)(_adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
BOOLEAN(*Efuse_PgPacketWrite_BT)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
#if defined(CONFIG_RTL8710B)
BOOLEAN(*efuse_indirect_read4)(_adapter *padapter, u16 regaddr, u8 *value);
#endif
#ifdef DBG_CONFIG_ERROR_DETECT
void (*sreset_init_value)(_adapter *padapter);
@@ -406,7 +429,9 @@ struct hal_ops {
int (*hal_gpio_func_check)(_adapter *padapter, u8 gpio_num);
void (*hal_gpio_multi_func_reset)(_adapter *padapter, u8 gpio_num);
#endif
#ifdef CONFIG_FW_CORRECT_BCN
void (*fw_correct_bcn)(PADAPTER padapter);
#endif
#ifdef RTW_HALMAC
u8(*init_mac_register)(PADAPTER);
@@ -469,12 +494,18 @@ typedef enum _HARDWARE_TYPE {
HARDWARE_TYPE_RTL8188FE,
HARDWARE_TYPE_RTL8188FU,
HARDWARE_TYPE_RTL8188FS,
HARDWARE_TYPE_RTL8188GTVU,
HARDWARE_TYPE_RTL8188GTVS,
HARDWARE_TYPE_RTL8723DE,
HARDWARE_TYPE_RTL8723DU,
HARDWARE_TYPE_RTL8723DS,
HARDWARE_TYPE_RTL8821CE,
HARDWARE_TYPE_RTL8821CU,
HARDWARE_TYPE_RTL8821CS,
HARDWARE_TYPE_RTL8710BU,
HARDWARE_TYPE_RTL8192FS,
HARDWARE_TYPE_RTL8192FU,
HARDWARE_TYPE_RTL8192FE,
HARDWARE_TYPE_MAX,
} HARDWARE_TYPE;
@@ -548,6 +579,18 @@ typedef enum _HARDWARE_TYPE {
IS_HARDWARE_TYPE_8723DU(_Adapter) || \
IS_HARDWARE_TYPE_8723DS(_Adapter))
/* RTL8192F Series */
#define IS_HARDWARE_TYPE_8192FS(_Adapter)\
(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FS)
#define IS_HARDWARE_TYPE_8192FU(_Adapter)\
(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FU)
#define IS_HARDWARE_TYPE_8192FE(_Adapter)\
(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FE)
#define IS_HARDWARE_TYPE_8192F(_Adapter)\
(IS_HARDWARE_TYPE_8192FS(_Adapter) ||\
IS_HARDWARE_TYPE_8192FU(_Adapter) ||\
IS_HARDWARE_TYPE_8192FE(_Adapter))
/* RTL8188F Series */
#define IS_HARDWARE_TYPE_8188FE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FE)
#define IS_HARDWARE_TYPE_8188FS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FS)
@@ -555,6 +598,15 @@ typedef enum _HARDWARE_TYPE {
#define IS_HARDWARE_TYPE_8188F(_Adapter) \
(IS_HARDWARE_TYPE_8188FE(_Adapter) || IS_HARDWARE_TYPE_8188FU(_Adapter) || IS_HARDWARE_TYPE_8188FS(_Adapter))
#define IS_HARDWARE_TYPE_8188GTVU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188GTVU)
#define IS_HARDWARE_TYPE_8188GTVS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188GTVS)
#define IS_HARDWARE_TYPE_8188GTV(_Adapter) \
(IS_HARDWARE_TYPE_8188GTVU(_Adapter) || IS_HARDWARE_TYPE_8188GTVS(_Adapter))
/* RTL8710B Series */
#define IS_HARDWARE_TYPE_8710BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8710BU)
#define IS_HARDWARE_TYPE_8710B(_Adapter) (IS_HARDWARE_TYPE_8710BU(_Adapter))
#define IS_HARDWARE_TYPE_8821BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BE)
#define IS_HARDWARE_TYPE_8821BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BU)
#define IS_HARDWARE_TYPE_8821BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BS)
@@ -613,6 +665,9 @@ u32 rtw_hal_power_on(_adapter *padapter);
void rtw_hal_power_off(_adapter *padapter);
uint rtw_hal_init(_adapter *padapter);
#ifdef CONFIG_NEW_NETDEV_HDL
uint rtw_hal_iface_init(_adapter *adapter);
#endif
uint rtw_hal_deinit(_adapter *padapter);
void rtw_hal_stop(_adapter *padapter);
u8 rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val);
@@ -678,12 +733,19 @@ void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr,
#define phy_query_rf_reg(Adapter, eRFPath, RegAddr, BitMask) rtw_hal_read_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask))
#define phy_set_rf_reg(Adapter, eRFPath, RegAddr, BitMask, Data) rtw_hal_write_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
#ifdef CONFIG_SYSON_INDIRECT_ACCESS
u32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask);
void rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
#define hal_query_syson_reg(Adapter, RegAddr, BitMask) rtw_hal_read_syson_reg((Adapter), (RegAddr), (BitMask))
#define hal_set_syson_reg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_syson_reg((Adapter), (RegAddr), (BitMask), (Data))
#endif
#define phy_set_mac_reg phy_set_bb_reg
#define phy_query_mac_reg phy_query_bb_reg
#if defined(CONFIG_PCI_HCI)
s32 rtw_hal_interrupt_handler(_adapter *padapter);
void rtw_hal_unmap_beacon_icf(_adapter *padapter);
#endif
#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf);
@@ -757,8 +819,9 @@ void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag);
int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num);
void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num);
#endif
#ifdef CONFIG_FW_CORRECT_BCN
void rtw_hal_fw_correct_bcn(_adapter *padapter);
#endif
s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan);
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)

124
include/hal_pg.h
View File

@@ -320,6 +320,50 @@
#define EEPROM_MAC_ADDR_8188FS 0x11A
#define EEPROM_Voltage_ADDR_8188F 0x8
/* ====================================================
EEPROM/Efuse PG Offset for 8188GTV/8188GTVS
====================================================
*/
#define GET_PG_KFREE_ON_8188GTV(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
#define GET_PG_KFREE_THERMAL_K_ON_8188GTV(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
#define PPG_BB_GAIN_2G_TXA_OFFSET_8188GTV 0xEE
#define PPG_THERMAL_OFFSET_8188GTV 0xEF
#define EEPROM_ChannelPlan_8188GTV 0xB8
#define EEPROM_XTAL_8188GTV 0xB9
#define EEPROM_THERMAL_METER_8188GTV 0xBA
#define EEPROM_IQK_LCK_8188GTV 0xBB
#define EEPROM_2G_5G_PA_TYPE_8188GTV 0xBC
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8188GTV 0xBD
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8188GTV 0xBF
#define EEPROM_RF_BOARD_OPTION_8188GTV 0xC1
#define EEPROM_FEATURE_OPTION_8188GTV 0xC2
#define EEPROM_RF_BT_SETTING_8188GTV 0xC3
#define EEPROM_VERSION_8188GTV 0xC4
#define EEPROM_CustomID_8188GTV 0xC5
#define EEPROM_TX_BBSWING_2G_8188GTV 0xC6
#define EEPROM_TX_PWR_CALIBRATE_RATE_8188GTV 0xC8
#define EEPROM_RF_ANTENNA_OPT_8188GTV 0xC9
#define EEPROM_RFE_OPTION_8188GTV 0xCA
#define EEPROM_COUNTRY_CODE_8188GTV 0xCB
#define EEPROM_CUSTOMER_ID_8188GTV 0x7F
#define EEPROM_SUBCUSTOMER_ID_8188GTV 0x59
/* RTL8188GTVU */
#define EEPROM_MAC_ADDR_8188GTVU 0xD7
#define EEPROM_VID_8188GTVU 0xD0
#define EEPROM_PID_8188GTVU 0xD2
#define EEPROM_PA_TYPE_8188GTVU 0xBC
#define EEPROM_LNA_TYPE_2G_8188GTVU 0xBD
#define EEPROM_USB_OPTIONAL_FUNCTION0_8188GTVU 0xD4
/* RTL8188GTVS */
#define EEPROM_MAC_ADDR_8188GTVS 0x11A
#define EEPROM_Voltage_ADDR_8188GTV 0x8
/* ****************************************************
* EEPROM/Efuse PG Offset for 8723BE/8723BU/8723BS
* *****************************************************/
@@ -537,10 +581,82 @@
#define EEPROM_MAC_ADDR_8723DS 0x11A
#define EEPROM_Voltage_ADDR_8723D 0x8
/* ****************************************************
* EEPROM/Efuse PG Offset for 8192F
* **************************************************** */
#define EEPROM_ChannelPlan_8192F 0xB8
#define EEPROM_XTAL_8192F 0xB9
#define EEPROM_THERMAL_METER_8192F 0xBA
#define EEPROM_IQK_LCK_8192F 0xBB
#define EEPROM_2G_5G_PA_TYPE_8192F 0xBC
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8192F 0xBD
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8192F 0xBF
#define EEPROM_RF_BOARD_OPTION_8192F 0xC1
#define EEPROM_FEATURE_OPTION_8192F 0xC2
#define EEPROM_RF_BT_SETTING_8192F 0xC3
#define EEPROM_VERSION_8192F 0xC4
#define EEPROM_CustomID_8192F 0xC5
#define EEPROM_TX_BBSWING_2G_8192F 0xC6
#define EEPROM_TX_BBSWING_5G_8192F 0xC7
#define EEPROM_TX_PWR_CALIBRATE_RATE_8192F 0xC8
#define EEPROM_RF_ANTENNA_OPT_8192F 0xC9
#define EEPROM_RFE_OPTION_8192F 0xCA
#define EEPROM_COUNTRY_CODE_8192F 0xCB
/*RTL8192FS*/
#define EEPROM_MAC_ADDR_8192FS 0x11A
#define EEPROM_Voltage_ADDR_8192F 0x8
/* RTL8192FU */
#define EEPROM_MAC_ADDR_8192FU 0x107
#define EEPROM_VID_8192FU 0x100
#define EEPROM_PID_8192FU 0x102
#define EEPROM_USB_OPTIONAL_FUNCTION0_8192FU 0x104
/* RTL8192FE */
#define EEPROM_MAC_ADDR_8192FE 0xD0
#define EEPROM_VID_8192FE 0xD6
#define EEPROM_DID_8192FE 0xD8
#define EEPROM_SVID_8192FE 0xDA
#define EEPROM_SMID_8192FE 0xDC
/* ****************************************************
* EEPROM/Efuse PG Offset for 8710B
* **************************************************** */
#define RTL_EEPROM_ID_8710B 0x8195
#define EEPROM_Default_ThermalMeter_8710B 0x1A
#define EEPROM_CHANNEL_PLAN_8710B 0xC8
#define EEPROM_XTAL_8710B 0xC9
#define EEPROM_THERMAL_METER_8710B 0xCA
#define EEPROM_IQK_LCK_8710B 0xCB
#define EEPROM_2G_5G_PA_TYPE_8710B 0xCC
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8710B 0xCD
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8710B 0xCF
#define EEPROM_TX_KFREE_8710B 0xEE //Physical Efuse Address
#define EEPROM_THERMAL_8710B 0xEF //Physical Efuse Address
#define EEPROM_PACKAGE_TYPE_8710B 0xF8 //Physical Efuse Address
#define EEPROM_RF_BOARD_OPTION_8710B 0x131
#define EEPROM_RF_FEATURE_OPTION_8710B 0x132
#define EEPROM_RF_BT_SETTING_8710B 0x133
#define EEPROM_VERSION_8710B 0x134
#define EEPROM_CUSTOM_ID_8710B 0x135
#define EEPROM_TX_BBSWING_2G_8710B 0x136
#define EEPROM_TX_BBSWING_5G_8710B 0x137
#define EEPROM_TX_PWR_CALIBRATE_RATE_8710B 0x138
#define EEPROM_RF_ANTENNA_OPT_8710B 0x139
#define EEPROM_RFE_OPTION_8710B 0x13A
#define EEPROM_COUNTRY_CODE_8710B 0x13B
#define EEPROM_COUNTRY_CODE_2_8710B 0x13C
#define EEPROM_MAC_ADDR_8710B 0x11A
#define EEPROM_VID_8710BU 0x1C0
#define EEPROM_PID_8710BU 0x1C2
/* ****************************************************
* EEPROM/Efuse Value Type
* **************************************************** */
#define EETYPE_TX_PWR 0x0
#define EETYPE_MAX_RFE_8192F 0x31
/* ****************************************************
* EEPROM/Efuse Default Value
* **************************************************** */
@@ -588,8 +704,9 @@
#define EEPROM_Default_ThermalMeter_8703B 0x18
#define EEPROM_Default_ThermalMeter_8723D 0x18
#define EEPROM_Default_ThermalMeter_8188F 0x18
#define EEPROM_Default_ThermalMeter_8188GTV 0x18
#define EEPROM_Default_ThermalMeter_8814A 0x18
#define EEPROM_Default_ThermalMeter_8192F 0x1A
#define EEPROM_Default_CrystalCap 0x0
#define EEPROM_Default_CrystalCap_8723A 0x20
@@ -601,6 +718,8 @@
#define EEPROM_Default_CrystalCap_8703B 0x20
#define EEPROM_Default_CrystalCap_8723D 0x20
#define EEPROM_Default_CrystalCap_8188F 0x20
#define EEPROM_Default_CrystalCap_8188GTV 0x20
#define EEPROM_Default_CrystalCap_8192F 0x20
#define EEPROM_Default_CrystalFreq 0x0
#define EEPROM_Default_TxPowerLevel_92C 0x22
#define EEPROM_Default_TxPowerLevel_2G 0x2C
@@ -748,7 +867,8 @@ typedef enum _BT_CoType {
BT_RTL8703B = 12,
BT_RTL8822B = 13,
BT_RTL8723D = 14,
BT_RTL8821C = 15
BT_RTL8821C = 15,
BT_RTL8192F = 16,
} BT_CoType, *PBT_CoType;
typedef enum _BT_RadioShared {

27
include/hal_sdio.h
View File

@@ -20,7 +20,7 @@
u8 rtw_hal_sdio_max_txoqt_free_space(_adapter *padapter);
u8 rtw_hal_sdio_query_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
void rtw_hal_sdio_update_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
void rtw_hal_set_sdio_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ);
void rtw_hal_set_sdio_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ, u8 div_num);
u32 rtw_hal_get_sdio_tx_max_length(PADAPTER padapter, u8 queue_idx);
bool sdio_power_on_check(PADAPTER padapter);
@@ -28,4 +28,29 @@ bool sdio_power_on_check(PADAPTER padapter);
void sd_c2h_hisr_hdl(_adapter *adapter);
#endif
#if defined(CONFIG_RTL8188F) || defined (CONFIG_RTL8188GTV) || defined (CONFIG_RTL8192F)
#define SDIO_LOCAL_CMD_ADDR(addr) ((SDIO_LOCAL_DEVICE_ID << 13) | ((addr) & SDIO_LOCAL_MSK))
#endif
#ifdef CONFIG_SDIO_CHK_HCI_RESUME
bool sdio_chk_hci_resume(struct intf_hdl *pintfhdl);
void sdio_chk_hci_suspend(struct intf_hdl *pintfhdl);
#else
#define sdio_chk_hci_resume(pintfhdl) _FALSE
#define sdio_chk_hci_suspend(pintfhdl) do {} while (0)
#endif /* CONFIG_SDIO_CHK_HCI_RESUME */
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
/* program indirect access register in sdio local to read/write page0 registers */
s32 sdio_iread(PADAPTER padapter, u32 addr, u8 size, u8 *v);
s32 sdio_iwrite(PADAPTER padapter, u32 addr, u8 size, u8 *v);
u8 sdio_iread8(struct intf_hdl *pintfhdl, u32 addr);
u16 sdio_iread16(struct intf_hdl *pintfhdl, u32 addr);
u32 sdio_iread32(struct intf_hdl *pintfhdl, u32 addr);
s32 sdio_iwrite8(struct intf_hdl *pintfhdl, u32 addr, u8 val);
s32 sdio_iwrite16(struct intf_hdl *pintfhdl, u32 addr, u16 val);
s32 sdio_iwrite32(struct intf_hdl *pintfhdl, u32 addr, u32 val);
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
u32 cmd53_4byte_alignment(struct intf_hdl *pintfhdl, u32 addr);
#endif /* __HAL_SDIO_H_ */

55
include/ieee80211.h
View File

@@ -151,6 +151,58 @@ extern u8 RSN_CIPHER_SUITE_WRAP[];
extern u8 RSN_CIPHER_SUITE_CCMP[];
extern u8 RSN_CIPHER_SUITE_WEP104[];
/* IEEE 802.11i */
#define PMKID_LEN 16
#define PMK_LEN 32
#define PMK_LEN_SUITE_B_192 48
#define PMK_LEN_MAX 48
#define WPA_REPLAY_COUNTER_LEN 8
#define WPA_NONCE_LEN 32
#define WPA_KEY_RSC_LEN 8
#define WPA_GMK_LEN 32
#define WPA_GTK_MAX_LEN 32
/* IEEE 802.11, 8.5.2 EAPOL-Key frames */
#define WPA_KEY_INFO_TYPE_MASK ((u16) (BIT(0) | BIT(1) | BIT(2)))
#define WPA_KEY_INFO_TYPE_AKM_DEFINED 0
#define WPA_KEY_INFO_TYPE_HMAC_MD5_RC4 BIT(0)
#define WPA_KEY_INFO_TYPE_HMAC_SHA1_AES BIT(1)
#define WPA_KEY_INFO_TYPE_AES_128_CMAC 3
#define WPA_KEY_INFO_KEY_TYPE BIT(3) /* 1 = Pairwise, 0 = Group key */
/* bit4..5 is used in WPA, but is reserved in IEEE 802.11i/RSN */
#define WPA_KEY_INFO_KEY_INDEX_MASK (BIT(4) | BIT(5))
#define WPA_KEY_INFO_KEY_INDEX_SHIFT 4
#define WPA_KEY_INFO_INSTALL BIT(6) /* pairwise */
#define WPA_KEY_INFO_TXRX BIT(6) /* group */
#define WPA_KEY_INFO_ACK BIT(7)
#define WPA_KEY_INFO_MIC BIT(8)
#define WPA_KEY_INFO_SECURE BIT(9)
#define WPA_KEY_INFO_ERROR BIT(10)
#define WPA_KEY_INFO_REQUEST BIT(11)
#define WPA_KEY_INFO_ENCR_KEY_DATA BIT(12) /* IEEE 802.11i/RSN only */
#define WPA_KEY_INFO_SMK_MESSAGE BIT(13)
struct ieee802_1x_hdr {
u8 version;
u8 type;
u16 length;
/* followed by length octets of data */
};
struct wpa_eapol_key {
u8 type;
/* Note: key_info, key_length, and key_data_length are unaligned */
u8 key_info[2]; /* big endian */
u8 key_length[2]; /* big endian */
u8 replay_counter[WPA_REPLAY_COUNTER_LEN];
u8 key_nonce[WPA_NONCE_LEN];
u8 key_iv[16];
u8 key_rsc[WPA_KEY_RSC_LEN];
u8 key_id[8]; /* Reserved in IEEE 802.11i/RSN */
u8 key_mic[16];
u8 key_data_length[2]; /* big endian */
/* followed by key_data_length bytes of key_data */
};
typedef enum _RATEID_IDX_ {
RATEID_IDX_BGN_40M_2SS = 0,
@@ -1985,6 +2037,7 @@ u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset
u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, u8 flags, u16 reason, u16 precedence);
u8 *rtw_get_ie(const u8 *pbuf, sint index, sint *len, sint limit);
int rtw_remove_ie_g_rate(u8 *ie, uint *ie_len, uint offset, u8 eid);
u8 *rtw_get_ie_ex(const u8 *in_ie, uint in_len, u8 eid, const u8 *oui, u8 oui_len, u8 *ie, uint *ielen);
int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len);
@@ -2091,7 +2144,7 @@ int rtw_get_bit_value_from_ieee_value(u8 val);
uint rtw_is_cckrates_included(u8 *rate);
uint rtw_is_cckratesonly_included(u8 *rate);
uint rtw_get_cckrate_size(u8 *rate,u32 rate_length);
int rtw_check_network_type(unsigned char *rate, int ratelen, int channel);
void rtw_get_bcn_info(struct wlan_network *pnetwork);

2
include/osdep_service.h
View File

@@ -578,6 +578,7 @@ static inline int largest_bit(u32 bitmask)
return i;
}
#define rtw_abs(a) (a < 0 ? -a : a)
#define rtw_min(a, b) ((a > b) ? b : a)
#define rtw_is_range_a_in_b(hi_a, lo_a, hi_b, lo_b) (((hi_a) <= (hi_b)) && ((lo_a) >= (lo_b)))
#define rtw_is_range_overlap(hi_a, lo_a, hi_b, lo_b) (((hi_a) > (lo_b)) && ((lo_a) < (hi_b)))
@@ -589,6 +590,7 @@ static inline int largest_bit(u32 bitmask)
#define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5]
#endif
bool rtw_macaddr_is_larger(const u8 *a, const u8 *b);
extern void rtw_suspend_lock_init(void);
extern void rtw_suspend_lock_uninit(void);

1408
include/osdep_service_bsd.h
View File

File diff suppressed because it is too large Load Diff

306
include/osdep_service_ce.h
View File

@@ -12,113 +12,113 @@
* more details.
*
*****************************************************************************/
#ifndef __OSDEP_CE_SERVICE_H_
#define __OSDEP_CE_SERVICE_H_
#include <ndis.h>
#include <ntddndis.h>
#ifdef CONFIG_SDIO_HCI
#include "SDCardDDK.h"
#endif
#ifdef CONFIG_USB_HCI
#include <usbdi.h>
#endif
typedef HANDLE _sema;
typedef LIST_ENTRY _list;
typedef NDIS_STATUS _OS_STATUS;
typedef NDIS_SPIN_LOCK _lock;
typedef HANDLE _rwlock; //Mutex
typedef u32 _irqL;
typedef NDIS_HANDLE _nic_hdl;
#ifndef __OSDEP_CE_SERVICE_H_
#define __OSDEP_CE_SERVICE_H_
#include <ndis.h>
#include <ntddndis.h>
#ifdef CONFIG_SDIO_HCI
#include "SDCardDDK.h"
#endif
#ifdef CONFIG_USB_HCI
#include <usbdi.h>
#endif
typedef HANDLE _sema;
typedef LIST_ENTRY _list;
typedef NDIS_STATUS _OS_STATUS;
typedef NDIS_SPIN_LOCK _lock;
typedef HANDLE _rwlock; //Mutex
typedef u32 _irqL;
typedef NDIS_HANDLE _nic_hdl;
struct rtw_timer_list {
NDIS_MINIPORT_TIMER ndis_timer;
void (*function)(void *);
void *arg;
};
struct __queue {
LIST_ENTRY queue;
_lock lock;
};
typedef NDIS_PACKET _pkt;
typedef NDIS_BUFFER _buffer;
typedef struct __queue _queue;
typedef HANDLE _thread_hdl_;
typedef DWORD thread_return;
typedef void* thread_context;
typedef NDIS_WORK_ITEM _workitem;
struct __queue {
LIST_ENTRY queue;
_lock lock;
};
typedef NDIS_PACKET _pkt;
typedef NDIS_BUFFER _buffer;
typedef struct __queue _queue;
typedef HANDLE _thread_hdl_;
typedef DWORD thread_return;
typedef void* thread_context;
typedef NDIS_WORK_ITEM _workitem;
#define SEMA_UPBND (0x7FFFFFFF) //8192
__inline static _list *get_prev(_list *list)
{
return list->Blink;
}
__inline static _list *get_next(_list *list)
{
return list->Flink;
}
__inline static _list *get_list_head(_queue *queue)
{
return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
{
NdisAcquireSpinLock(plock);
}
__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
{
NdisReleaseSpinLock(plock);
}
__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprAcquireSpinLock(plock);
}
__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprReleaseSpinLock(plock);
}
__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
{
WaitForSingleObject(*prwlock, INFINITE );
}
__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
{
ReleaseMutex(*prwlock);
}
__inline static void rtw_list_delete(_list *plist)
{
RemoveEntryList(plist);
InitializeListHead(plist);
}
#define SEMA_UPBND (0x7FFFFFFF) //8192
__inline static _list *get_prev(_list *list)
{
return list->Blink;
}
__inline static _list *get_next(_list *list)
{
return list->Flink;
}
__inline static _list *get_list_head(_queue *queue)
{
return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
{
NdisAcquireSpinLock(plock);
}
__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
{
NdisReleaseSpinLock(plock);
}
__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprAcquireSpinLock(plock);
}
__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprReleaseSpinLock(plock);
}
__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
{
WaitForSingleObject(*prwlock, INFINITE );
}
__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
{
ReleaseMutex(*prwlock);
}
__inline static void rtw_list_delete(_list *plist)
{
RemoveEntryList(plist);
InitializeListHead(plist);
}
static inline void timer_hdl(
IN PVOID SystemSpecific1,
IN PVOID FunctionContext,
@@ -146,55 +146,55 @@ static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled)
{
NdisMCancelTimer(ptimer, bcancelled);
}
__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
{
NdisInitializeWorkItem(pwork, pfunc, cntx);
}
__inline static void _set_workitem(_workitem *pwork)
{
NdisScheduleWorkItem(pwork);
}
#define ATOMIC_INIT(i) { (i) }
//
// Global Mutex: can only be used at PASSIVE level.
//
#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
{ \
while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
NdisMSleep(10000); \
} \
}
#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
}
// limitation of path length
#define PATH_LENGTH_MAX MAX_PATH
//Atomic integer operations
#define ATOMIC_T LONG
#define NDEV_FMT "%s"
#define NDEV_ARG(ndev) ""
#define ADPT_FMT "%s"
#define ADPT_ARG(adapter) ""
#define FUNC_NDEV_FMT "%s"
#define FUNC_NDEV_ARG(ndev) __func__
#define FUNC_ADPT_FMT "%s"
#define FUNC_ADPT_ARG(adapter) __func__
#define STRUCT_PACKED
#endif
__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
{
NdisInitializeWorkItem(pwork, pfunc, cntx);
}
__inline static void _set_workitem(_workitem *pwork)
{
NdisScheduleWorkItem(pwork);
}
#define ATOMIC_INIT(i) { (i) }
//
// Global Mutex: can only be used at PASSIVE level.
//
#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
{ \
while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
NdisMSleep(10000); \
} \
}
#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
}
// limitation of path length
#define PATH_LENGTH_MAX MAX_PATH
//Atomic integer operations
#define ATOMIC_T LONG
#define NDEV_FMT "%s"
#define NDEV_ARG(ndev) ""
#define ADPT_FMT "%s"
#define ADPT_ARG(adapter) ""
#define FUNC_NDEV_FMT "%s"
#define FUNC_NDEV_ARG(ndev) __func__
#define FUNC_ADPT_FMT "%s"
#define FUNC_ADPT_ARG(adapter) __func__
#define STRUCT_PACKED
#endif

4
include/osdep_service_linux.h
View File

@@ -93,10 +93,6 @@
#include <net/cfg80211.h>
#endif /* CONFIG_IOCTL_CFG80211 */
#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
#include <linux/in.h>
#include <linux/udp.h>
#endif
#ifdef CONFIG_HAS_EARLYSUSPEND
#include <linux/earlysuspend.h>

328
include/osdep_service_xp.h
View File

@@ -12,122 +12,122 @@
* more details.
*
*****************************************************************************/
#ifndef __OSDEP_LINUX_SERVICE_H_
#define __OSDEP_LINUX_SERVICE_H_
#include <ndis.h>
#include <ntddk.h>
#include <ntddndis.h>
#include <ntdef.h>
#ifdef CONFIG_USB_HCI
#include <usb.h>
#include <usbioctl.h>
#include <usbdlib.h>
#endif
typedef KSEMAPHORE _sema;
typedef LIST_ENTRY _list;
typedef NDIS_STATUS _OS_STATUS;
typedef NDIS_SPIN_LOCK _lock;
typedef KMUTEX _mutex;
typedef KIRQL _irqL;
// USB_PIPE for WINCE , but handle can be use just integer under windows
typedef NDIS_HANDLE _nic_hdl;
#ifndef __OSDEP_LINUX_SERVICE_H_
#define __OSDEP_LINUX_SERVICE_H_
#include <ndis.h>
#include <ntddk.h>
#include <ntddndis.h>
#include <ntdef.h>
#ifdef CONFIG_USB_HCI
#include <usb.h>
#include <usbioctl.h>
#include <usbdlib.h>
#endif
typedef KSEMAPHORE _sema;
typedef LIST_ENTRY _list;
typedef NDIS_STATUS _OS_STATUS;
typedef NDIS_SPIN_LOCK _lock;
typedef KMUTEX _mutex;
typedef KIRQL _irqL;
// USB_PIPE for WINCE , but handle can be use just integer under windows
typedef NDIS_HANDLE _nic_hdl;
struct rtw_timer_list {
NDIS_MINIPORT_TIMER ndis_timer;
void (*function)(void *);
void *arg;
};
struct __queue {
LIST_ENTRY queue;
_lock lock;
};
typedef NDIS_PACKET _pkt;
typedef NDIS_BUFFER _buffer;
typedef struct __queue _queue;
typedef PKTHREAD _thread_hdl_;
typedef void thread_return;
typedef void* thread_context;
typedef NDIS_WORK_ITEM _workitem;
#define HZ 10000000
#define SEMA_UPBND (0x7FFFFFFF) //8192
__inline static _list *get_next(_list *list)
{
return list->Flink;
}
__inline static _list *get_list_head(_queue *queue)
{
return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
__inline static _enter_critical(_lock *plock, _irqL *pirqL)
{
NdisAcquireSpinLock(plock);
}
__inline static _exit_critical(_lock *plock, _irqL *pirqL)
{
NdisReleaseSpinLock(plock);
}
__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprAcquireSpinLock(plock);
}
__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprReleaseSpinLock(plock);
}
__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
{
NdisDprAcquireSpinLock(plock);
}
__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
{
NdisDprReleaseSpinLock(plock);
}
__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
{
KeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL);
}
__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
{
KeReleaseMutex(pmutex, FALSE);
}
__inline static void rtw_list_delete(_list *plist)
{
RemoveEntryList(plist);
InitializeListHead(plist);
}
struct __queue {
LIST_ENTRY queue;
_lock lock;
};
typedef NDIS_PACKET _pkt;
typedef NDIS_BUFFER _buffer;
typedef struct __queue _queue;
typedef PKTHREAD _thread_hdl_;
typedef void thread_return;
typedef void* thread_context;
typedef NDIS_WORK_ITEM _workitem;
#define HZ 10000000
#define SEMA_UPBND (0x7FFFFFFF) //8192
__inline static _list *get_next(_list *list)
{
return list->Flink;
}
__inline static _list *get_list_head(_queue *queue)
{
return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
__inline static _enter_critical(_lock *plock, _irqL *pirqL)
{
NdisAcquireSpinLock(plock);
}
__inline static _exit_critical(_lock *plock, _irqL *pirqL)
{
NdisReleaseSpinLock(plock);
}
__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprAcquireSpinLock(plock);
}
__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprReleaseSpinLock(plock);
}
__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
{
NdisDprAcquireSpinLock(plock);
}
__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
{
NdisDprReleaseSpinLock(plock);
}
__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
{
KeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL);
}
__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
{
KeReleaseMutex(pmutex, FALSE);
}
__inline static void rtw_list_delete(_list *plist)
{
RemoveEntryList(plist);
InitializeListHead(plist);
}
static inline void timer_hdl(
IN PVOID SystemSpecific1,
IN PVOID FunctionContext,
@@ -155,56 +155,56 @@ static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled)
{
NdisMCancelTimer(ptimer, bcancelled);
}
__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
{
NdisInitializeWorkItem(pwork, pfunc, cntx);
}
__inline static void _set_workitem(_workitem *pwork)
{
NdisScheduleWorkItem(pwork);
}
#define ATOMIC_INIT(i) { (i) }
//
// Global Mutex: can only be used at PASSIVE level.
//
#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
{ \
while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
NdisMSleep(10000); \
} \
}
#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
}
// limitation of path length
#define PATH_LENGTH_MAX MAX_PATH
//Atomic integer operations
#define ATOMIC_T LONG
#define NDEV_FMT "%s"
#define NDEV_ARG(ndev) ""
#define ADPT_FMT "%s"
#define ADPT_ARG(adapter) ""
#define FUNC_NDEV_FMT "%s"
#define FUNC_NDEV_ARG(ndev) __func__
#define FUNC_ADPT_FMT "%s"
#define FUNC_ADPT_ARG(adapter) __func__
#define STRUCT_PACKED
#endif
__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
{
NdisInitializeWorkItem(pwork, pfunc, cntx);
}
__inline static void _set_workitem(_workitem *pwork)
{
NdisScheduleWorkItem(pwork);
}
#define ATOMIC_INIT(i) { (i) }
//
// Global Mutex: can only be used at PASSIVE level.
//
#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
{ \
while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
NdisMSleep(10000); \
} \
}
#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
}
// limitation of path length
#define PATH_LENGTH_MAX MAX_PATH
//Atomic integer operations
#define ATOMIC_T LONG
#define NDEV_FMT "%s"
#define NDEV_ARG(ndev) ""
#define ADPT_FMT "%s"
#define ADPT_ARG(adapter) ""
#define FUNC_NDEV_FMT "%s"
#define FUNC_NDEV_ARG(ndev) __func__
#define FUNC_ADPT_FMT "%s"
#define FUNC_ADPT_ARG(adapter) __func__
#define STRUCT_PACKED
#endif

4
include/pci_hal.h
View File

@@ -27,6 +27,10 @@
void rtl8192ee_set_hal_ops(_adapter *padapter);
#endif
#if defined(CONFIG_RTL8192F)
void rtl8192fe_set_hal_ops(_adapter *padapter);
#endif
#ifdef CONFIG_RTL8723B
void rtl8723be_set_hal_ops(_adapter *padapter);
#endif

18
include/pci_ops.h
View File

@@ -25,6 +25,7 @@
void rtl8188ee_recv_tasklet(void *priv);
void rtl8188ee_prepare_bcn_tasklet(void *priv);
void rtl8188ee_set_intf_ops(struct _io_ops *pops);
void rtw8188ee_unmap_beacon_icf(_adapter *padapter);
#endif
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
@@ -36,6 +37,7 @@
void rtl8812ae_recv_tasklet(void *priv);
void rtl8812ae_prepare_bcn_tasklet(void *priv);
void rtl8812ae_set_intf_ops(struct _io_ops *pops);
void rtw8812ae_unmap_beacon_icf(_adapter *padapter);
#endif
#ifdef CONFIG_RTL8192E
@@ -46,6 +48,19 @@
void rtl8192ee_prepare_bcn_tasklet(void *priv);
int rtl8192ee_interrupt(PADAPTER Adapter);
void rtl8192ee_set_intf_ops(struct _io_ops *pops);
void rtw8192ee_unmap_beacon_icf(_adapter *padapter);
#endif
#ifdef CONFIG_RTL8192F
u32 rtl8192fe_init_desc_ring(_adapter *padapter);
u32 rtl8192fe_free_desc_ring(_adapter *padapter);
void rtl8192fe_reset_desc_ring(_adapter *padapter);
int rtl8192fe_interrupt(PADAPTER Adapter);
void rtl8192fe_recv_tasklet(void *priv);
void rtl8192fe_prepare_bcn_tasklet(void *priv);
void rtl8192fe_set_intf_ops(struct _io_ops *pops);
u8 check_tx_desc_resource(_adapter *padapter, int prio);
void rtl8192fe_unmap_beacon_icf(PADAPTER Adapter);
#endif
#ifdef CONFIG_RTL8723B
@@ -56,6 +71,7 @@
void rtl8723be_recv_tasklet(void *priv);
void rtl8723be_prepare_bcn_tasklet(void *priv);
void rtl8723be_set_intf_ops(struct _io_ops *pops);
void rtl8723be_unmap_beacon_icf(PADAPTER Adapter);
#endif
#ifdef CONFIG_RTL8723D
@@ -67,6 +83,7 @@
void rtl8723de_prepare_bcn_tasklet(void *priv);
void rtl8723de_set_intf_ops(struct _io_ops *pops);
u8 check_tx_desc_resource(_adapter *padapter, int prio);
void rtl8723de_unmap_beacon_icf(PADAPTER Adapter);
#endif
#ifdef CONFIG_RTL8814A
@@ -78,6 +95,7 @@
void rtl8814ae_recv_tasklet(void *priv);
void rtl8814ae_prepare_bcn_tasklet(void *priv);
void rtl8814ae_set_intf_ops(struct _io_ops *pops);
void rtl8814ae_unmap_beacon_icf(PADAPTER Adapter);
#endif
#ifdef CONFIG_RTL8822B

1
include/rtl8188e_cmd.h
View File

@@ -135,7 +135,6 @@ typedef struct _RSVDPAGE_LOC_88E {
/* host message to firmware cmd */
void rtl8188e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
void rtl8188e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
u8 rtl8188e_set_rssi_cmd(PADAPTER padapter, u8 *param);
s32 FillH2CCmd_88E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
/* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */
u8 GetTxBufferRsvdPageNum8188E(_adapter *padapter, bool wowlan);

14
include/rtl8188e_hal.h
View File

@@ -128,16 +128,18 @@ typedef struct _RT_8188E_FIRMWARE_HDR {
#define MAX_TX_REPORT_BUFFER_SIZE 0x0400 /* 1k */
#define PAGE_SIZE_TX_88E PAGE_SIZE_128
/* Note: We will divide number of page equally for each queue other than public queue!
* 22k = 22528 bytes = 176 pages (@page = 128 bytes)
* must reserved about 7 pages for LPS => 176-7 = 169 (0xA9)
* 2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS null-data */
* BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_88E
* 1 ps-poll / 1 null-data /1 prob_rsp /1 QOS null-data = 4 pages */
#define BCNQ_PAGE_NUM_88E 0x09
#define BCNQ_PAGE_NUM_88E (MAX_BEACON_LEN / PAGE_SIZE_TX_88E + 4) /*0x09*/
/* For WoWLan , more reserved page */
#ifdef CONFIG_WOWLAN
#define WOWLAN_PAGE_NUM_88E 0x00
/* 1 ArpRsp + 2 NbrAdv + 2 NDPInfo + 1 RCI + 1 AOAC = 7 pages */
#define WOWLAN_PAGE_NUM_88E 0x07
#else
#define WOWLAN_PAGE_NUM_88E 0x00
#endif
@@ -283,7 +285,6 @@ BOOLEAN HalDetectPwrDownMode88E(PADAPTER Adapter);
void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
#endif /*CONFIG_RF_POWER_TRIM*/
void rtl8188e_init_default_value(_adapter *adapter);
void InitBeaconParameters_8188e(_adapter *adapter);
void SetBeaconRelatedRegisters8188E(PADAPTER padapter);
@@ -291,9 +292,6 @@ void SetBeaconRelatedRegisters8188E(PADAPTER padapter);
void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc);
void init_hal_spec_8188e(_adapter *adapter);
/* register */
void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits);
void rtl8188e_start_thread(_adapter *padapter);
void rtl8188e_stop_thread(_adapter *padapter);

2
include/rtl8188f_cmd.h
View File

@@ -113,7 +113,6 @@ enum h2c_cmd_8188F {
#define SET_8188F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8188F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
#define SET_8188F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8188F_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
#define GET_8188F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
@@ -178,7 +177,6 @@ enum h2c_cmd_8188F {
/* host message to firmware cmd */
void rtl8188f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
void rtl8188f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
void rtl8188f_set_rssi_cmd(PADAPTER padapter, u8 *param);
void rtl8188f_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
/* s32 rtl8188f_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
void rtl8188f_set_FwPsTuneParam_cmd(PADAPTER padapter);

16
include/rtl8188f_hal.h
View File

@@ -104,18 +104,10 @@ typedef struct _RT_8188F_FIRMWARE_HDR {
/* Note: We will divide number of page equally for each queue other than public queue! */
/* For General Reserved Page Number(Beacon Queue is reserved page)
* Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1 */
#define BCNQ_PAGE_NUM_8188F 0x08
#ifdef CONFIG_CONCURRENT_MODE
#define BCNQ1_PAGE_NUM_8188F 0x08 /* 0x04 */
#else
#define BCNQ1_PAGE_NUM_8188F 0x00
#endif
* BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_8188F,
* PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1, CTS-2-SELF / LTE QoS Null */
#ifdef CONFIG_PNO_SUPPORT
#undef BCNQ1_PAGE_NUM_8188F
#define BCNQ1_PAGE_NUM_8188F 0x00 /* 0x04 */
#endif
#define BCNQ_PAGE_NUM_8188F (MAX_BEACON_LEN / PAGE_SIZE_TX_8188F + 6) /*0x08*/
/* For WoWLan , more reserved page
* ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt:1 ,PNO: 6
@@ -136,7 +128,7 @@ typedef struct _RT_8188F_FIRMWARE_HDR {
#define AP_WOWLAN_PAGE_NUM_8188F 0x02
#endif
#define TX_TOTAL_PAGE_NUMBER_8188F (0xFF - BCNQ_PAGE_NUM_8188F - BCNQ1_PAGE_NUM_8188F - WOWLAN_PAGE_NUM_8188F)
#define TX_TOTAL_PAGE_NUMBER_8188F (0xFF - BCNQ_PAGE_NUM_8188F - WOWLAN_PAGE_NUM_8188F)
#define TX_PAGE_BOUNDARY_8188F (TX_TOTAL_PAGE_NUMBER_8188F + 1)
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8188F TX_TOTAL_PAGE_NUMBER_8188F

12
include/rtl8188f_spec.h
View File

@@ -150,18 +150,6 @@
#define SDIO_REG_HCPWM1_8188F 0x0038
/* indirect access */
#define SDIO_REG_INDIRECT_REG_CFG_8188F 0x40
#define SET_INDIRECT_REG_ADDR(_cmd, _addr) SET_BITS_TO_LE_2BYTE(((u8 *)(_cmd)) + 0, 0, 16, (_addr))
#define SET_INDIRECT_REG_SIZE_1BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 0)
#define SET_INDIRECT_REG_SIZE_2BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 1)
#define SET_INDIRECT_REG_SIZE_4BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 2)
#define SET_INDIRECT_REG_WRITE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 2, 1, 1)
#define SET_INDIRECT_REG_READ(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 3, 1, 1)
#define GET_INDIRECT_REG_RDY(_cmd) LE_BITS_TO_1BYTE(((u8 *)(_cmd)) + 2, 4, 1)
#define SDIO_REG_INDIRECT_REG_DATA_8188F 0x44
/* ****************************************************************************
* 8188 Regsiter Bit and Content definition
* **************************************************************************** */

8
include/rtl8188f_xmit.h
View File

@@ -184,13 +184,15 @@
#define SET_TX_DESC_ANTSEL_D_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
/* Dword 7 */
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
#ifdef CONFIG_PCI_HCI
#define SET_TX_DESC_TX_BUFFER_SIZE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#else
#endif
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
#define SET_TX_DESC_TX_DESC_CHECKSUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#endif
#define SET_TX_DESC_USB_TXAGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
#if (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
#ifdef CONFIG_SDIO_HCI
#define SET_TX_DESC_SDIO_TXSEQ_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
#endif

2
include/rtl8192e_cmd.h
View File

@@ -101,7 +101,6 @@ typedef struct _RSVDPAGE_LOC_92E {
#define SET_8192E_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8192E_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
#define SET_8192E_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8192E_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
#define GET_8192E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
/* _P2P_PS_OFFLOAD */
@@ -116,7 +115,6 @@ typedef struct _RSVDPAGE_LOC_92E {
/* host message to firmware cmd */
void rtl8192e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
void rtl8192e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
u8 rtl8192e_set_rssi_cmd(PADAPTER padapter, u8 *param);
s32 FillH2CCmd_8192E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
u8 GetTxBufferRsvdPageNum8192E(_adapter *padapter, bool wowlan);
/* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */

12
include/rtl8192e_hal.h
View File

@@ -121,10 +121,15 @@ typedef struct _RT_FIRMWARE_8192E {
#endif
#define MAX_RX_DMA_BUFFER_SIZE_8192E (RX_DMA_SIZE_8192E-RX_DMA_RESERVED_SIZE_8192E) /*RX 16K*/
#define PAGE_SIZE_TX_92E PAGE_SIZE_256
/* For General Reserved Page Number(Beacon Queue is reserved page)
* if (CONFIG_2BCN_EN) Beacon:4, PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1
* Beacon:2, PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1 */
#define RSVD_PAGE_NUM_8192E 0x08
* Beacon: MAX_BEACON_LEN / PAGE_SIZE_TX_92E
* PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1,CTS-2-SELF / LTE QoS Null*/
#define RSVD_PAGE_NUM_8192E (MAX_BEACON_LEN / PAGE_SIZE_TX_92E + 6) /*0x08*/
/* For WoWLan , more reserved page
* ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6
* NS offload: 2 NDP info: 1
@@ -154,7 +159,6 @@ Total page numbers : 256(0x100)
#define TX_PAGE_BOUNDARY_8192E (TX_TOTAL_PAGE_NUMBER_8192E) /* beacon header start address */
#define PAGE_SIZE_TX_92E PAGE_SIZE_256
#define RSVD_PKT_LEN_92E (TOTAL_RSVD_PAGE_NUMBER_8192E * PAGE_SIZE_TX_92E)
#define TX_PAGE_LOAD_FW_BOUNDARY_8192E 0x47 /* 0xA5 */
@@ -304,8 +308,6 @@ GetHalDefVar8192E(
void rtl8192e_set_hal_ops(struct hal_ops *pHalFunc);
void init_hal_spec_8192e(_adapter *adapter);
void rtl8192e_init_default_value(_adapter *padapter);
/* register */
void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits);
void rtl8192e_start_thread(_adapter *padapter);
void rtl8192e_stop_thread(_adapter *padapter);

6
include/rtl8192e_xmit.h
View File

@@ -317,9 +317,11 @@ typedef struct txdescriptor_8192e {
#define SET_TX_DESC_ANTSEL_D_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
/* Dword 7 */
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
#ifdef CONFIG_PCI_HCI
#define SET_TX_DESC_TX_BUFFER_SIZE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#else
#endif
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
#define SET_TX_DESC_TX_DESC_CHECKSUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#endif
#define SET_TX_DESC_USB_TXAGG_NUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)

194
include/rtl8192f_cmd.h Normal file
View File

@@ -0,0 +1,194 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8192F_CMD_H__
#define __RTL8192F_CMD_H__
/* ---------------------------------------------------------------------------------------------------------
* ---------------------------------- H2C CMD DEFINITION ------------------------------------------------
* --------------------------------------------------------------------------------------------------------- */
enum h2c_cmd_8192F {
/* Common Class: 000 */
H2C_8192F_RSVD_PAGE = 0x00,
H2C_8192F_MEDIA_STATUS_RPT = 0x01,
H2C_8192F_SCAN_ENABLE = 0x02,
H2C_8192F_KEEP_ALIVE = 0x03,
H2C_8192F_DISCON_DECISION = 0x04,
H2C_8192F_PSD_OFFLOAD = 0x05,
H2C_8192F_AP_OFFLOAD = 0x08,
H2C_8192F_BCN_RSVDPAGE = 0x09,
H2C_8192F_PROBERSP_RSVDPAGE = 0x0A,
H2C_8192F_FCS_RSVDPAGE = 0x10,
H2C_8192F_FCS_INFO = 0x11,
H2C_8192F_AP_WOW_GPIO_CTRL = 0x13,
/* PoweSave Class: 001 */
H2C_8192F_SET_PWR_MODE = 0x20,
H2C_8192F_PS_TUNING_PARA = 0x21,
H2C_8192F_PS_TUNING_PARA2 = 0x22,
H2C_8192F_P2P_LPS_PARAM = 0x23,
H2C_8192F_P2P_PS_OFFLOAD = 0x24,
H2C_8192F_PS_SCAN_ENABLE = 0x25,
H2C_8192F_SAP_PS_ = 0x26,
H2C_8192F_INACTIVE_PS_ = 0x27,/* Inactive_PS */
H2C_8192F_FWLPS_IN_IPS_ = 0x28,
/* Dynamic Mechanism Class: 010 */
H2C_8192F_MACID_CFG = 0x40,
H2C_8192F_TXBF = 0x41,
H2C_8192F_RSSI_SETTING = 0x42,
H2C_8192F_AP_REQ_TXRPT = 0x43,
H2C_8192F_INIT_RATE_COLLECT = 0x44,
H2C_8192F_RA_PARA_ADJUST = 0x46,
/* BT Class: 011 */
H2C_8192F_B_TYPE_TDMA = 0x60,
H2C_8192F_BT_INFO = 0x61,
H2C_8192F_FORCE_BT_TXPWR = 0x62,
H2C_8192F_BT_IGNORE_WLANACT = 0x63,
H2C_8192F_DAC_SWING_VALUE = 0x64,
H2C_8192F_ANT_SEL_RSV = 0x65,
H2C_8192F_WL_OPMODE = 0x66,
H2C_8192F_BT_MP_OPER = 0x67,
H2C_8192F_BT_CONTROL = 0x68,
H2C_8192F_BT_WIFI_CTRL = 0x69,
H2C_8192F_BT_FW_PATCH = 0x6A,
H2C_8192F_BT_WLAN_CALIBRATION = 0x6D,
/* WOWLAN Class: 100 */
H2C_8192F_WOWLAN = 0x80,
H2C_8192F_REMOTE_WAKE_CTRL = 0x81,
H2C_8192F_AOAC_GLOBAL_INFO = 0x82,
H2C_8192F_AOAC_RSVD_PAGE = 0x83,
H2C_8192F_AOAC_RSVD_PAGE2 = 0x84,
H2C_8192F_D0_SCAN_OFFLOAD_CTRL = 0x85,
H2C_8192F_D0_SCAN_OFFLOAD_INFO = 0x86,
H2C_8192F_CHNL_SWITCH_OFFLOAD = 0x87,
H2C_8192F_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
H2C_8192F_P2P_OFFLOAD = 0x8B,
H2C_8192F_RESET_TSF = 0xC0,
H2C_8192F_MAXID,
};
/* ---------------------------------------------------------------------------------------------------------
* ---------------------------------- H2C CMD CONTENT --------------------------------------------------
* ---------------------------------------------------------------------------------------------------------
* _RSVDPAGE_LOC_CMD_0x00 */
#define SET_8192F_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8192F_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_8192F_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8192F_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8192F_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
/*_MEDIA_STATUS_RPT_PARM_CMD_0x01*/
#define SET_8192F_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
/* _PWR_MOD_CMD_0x20 */
#define SET_8192F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8192F_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
#define SET_8192F_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
#define SET_8192F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8192F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8192F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
#define SET_8192F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define GET_8192F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
/* _PS_TUNE_PARAM_CMD_0x21 */
#define SET_8192F_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8192F_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_8192F_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
#define SET_8192F_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
#define SET_8192F_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
/* _MACID_CFG_CMD_0x40 */
#define SET_8192F_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8192F_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
#define SET_8192F_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
#define SET_8192F_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
#define SET_8192F_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
#define SET_8192F_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
#define SET_8192F_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
#define SET_8192F_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
/* _RSSI_SETTING_CMD_0x42 */
#define SET_8192F_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8192F_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
#define SET_8192F_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
/* _AP_REQ_TXRPT_CMD_0x43 */
#define SET_8192F_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8192F_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
/* _FORCE_BT_TXPWR_CMD_0x62 */
#define SET_8192F_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
/* _FORCE_BT_MP_OPER_CMD_0x67 */
#define SET_8192F_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
#define SET_8192F_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
#define SET_8192F_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_8192F_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
#define SET_8192F_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
#define SET_8192F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
/* _BT_FW_PATCH_0x6A */
#define SET_8192F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
/* ---------------------------------------------------------------------------------------------------------
* ------------------------------------------- Structure --------------------------------------------------
* --------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------
* ---------------------------------- Function Statement --------------------------------------------------
* --------------------------------------------------------------------------------------------------------- */
/* host message to firmware cmd */
void rtl8192f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
void rtl8192f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
/* s32 rtl8192f__set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
void rtl8192f_set_FwPsTuneParam_cmd(PADAPTER padapter);
void rtl8192f_download_rsvd_page(PADAPTER padapter, u8 mstatus);
#ifdef CONFIG_BT_COEXIST
void rtl8192f__download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
#endif /* CONFIG_BT_COEXIST */
#ifdef CONFIG_P2P
void rtl8192f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
#endif /* CONFIG_P2P */
#ifdef CONFIG_TDLS
#ifdef CONFIG_TDLS_CH_SW
void rtl8192f_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
#endif
#endif
#ifdef CONFIG_P2P_WOWLAN
void rtl8192f_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
#endif
s32 FillH2CCmd8192F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
u8 GetTxBufferRsvdPageNum8192F(_adapter *padapter, bool wowlan);
#endif

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/******************************************************************************
*
* Copyright(c) 2012 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8192F_DM_H__
#define __RTL8192F_DM_H__
void rtl8192f_init_dm_priv(IN PADAPTER Adapter);
void rtl8192f_deinit_dm_priv(IN PADAPTER Adapter);
void rtl8192f_InitHalDm(IN PADAPTER Adapter);
void rtl8192f_HalDmWatchDog(IN PADAPTER Adapter);
/* VOID rtl8192c_dm_CheckTXPowerTracking(IN PADAPTER Adapter); */
/* void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal); */
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8192F_HAL_H__
#define __RTL8192F_HAL_H__
#include "hal_data.h"
#include "rtl8192f_spec.h"
#include "rtl8192f_rf.h"
#include "rtl8192f_dm.h"
#include "rtl8192f_recv.h"
#include "rtl8192f_xmit.h"
#include "rtl8192f_cmd.h"
#include "rtl8192f_led.h"
#include "Hal8192FPwrSeq.h"
#include "Hal8192FPhyReg.h"
#include "Hal8192FPhyCfg.h"
#ifdef DBG_CONFIG_ERROR_DETECT
#include "rtl8192f_sreset.h"
#endif
#ifdef CONFIG_LPS_POFF
#include "rtl8192f_lps_poff.h"
#endif
#define FW_8192F_SIZE 0x8000
#define FW_8192F_START_ADDRESS 0x4000
#define FW_8192F_END_ADDRESS 0x5000 /* brian_zhang@realsil.com.cn */
#define IS_FW_HEADER_EXIST_8192F(_pFwHdr)\
((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x92F0)
typedef struct _RT_FIRMWARE {
FIRMWARE_SOURCE eFWSource;
#ifdef CONFIG_EMBEDDED_FWIMG
u8 *szFwBuffer;
#else
u8 szFwBuffer[FW_8192F_SIZE];
#endif
u32 ulFwLength;
} RT_FIRMWARE_8192F, *PRT_FIRMWARE_8192F;
/*
* This structure must be cared byte-ordering
*
* Added by tynli. 2009.12.04. */
typedef struct _RT_8192F_FIRMWARE_HDR {
/* 8-byte alinment required */
/* --- LONG WORD 0 ---- */
u16 Signature; /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
u8 Category; /* AP/NIC and USB/PCI */
u8 Function; /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
u16 Version; /* FW Version */
u16 Subversion; /* FW Subversion, default 0x00 */
/* --- LONG WORD 1 ---- */
u8 Month; /* Release time Month field */
u8 Date; /* Release time Date field */
u8 Hour; /* Release time Hour field */
u8 Minute; /* Release time Minute field */
u16 RamCodeSize; /* The size of RAM code */
u16 Rsvd2;
/* --- LONG WORD 2 ---- */
u32 SvnIdx; /* The SVN entry index */
u32 Rsvd3;
/* --- LONG WORD 3 ---- */
u32 Rsvd4;
u32 Rsvd5;
} RT_8192F_FIRMWARE_HDR, *PRT_8192F_FIRMWARE_HDR;
#define DRIVER_EARLY_INT_TIME_8192F 0x05
#define BCN_DMA_ATIME_INT_TIME_8192F 0x02
/* for 8192F
* TX 64K, RX 16K, Page size 256B for TX*/
#define PAGE_SIZE_TX_8192F 256
#define PAGE_SIZE_RX_8192F 8
#define TX_DMA_SIZE_8192F 0x10000/* 64K(TX) */
#define RX_DMA_SIZE_8192F 0x4000/* 16K(RX) */
#ifdef CONFIG_WOWLAN
#define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
#else
#define RESV_FMWF 0
#endif
#ifdef CONFIG_FW_C2H_DEBUG
#define RX_DMA_RESERVED_SIZE_8192F 0x100 /* 256B, reserved for c2h debug message */
#else
#define RX_DMA_RESERVED_SIZE_8192F 0xc0 /* 192B, reserved for tx report 24*8=192*/
#endif
#define RX_DMA_BOUNDARY_8192F\
(RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F - 1)
/* Note: We will divide number of page equally for each queue other than public queue! */
/* For General Reserved Page Number(Beacon Queue is reserved page)
* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8192F
* PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
#define BCNQ_PAGE_NUM_8192F (MAX_BEACON_LEN/PAGE_SIZE_TX_8192F + 6) /*0x08*/
/* For WoWLan , more reserved page
* ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6
* NS offload: 2 NDP info: 1
*/
#ifdef CONFIG_WOWLAN
#define WOWLAN_PAGE_NUM_8192F 0x07
#else
#define WOWLAN_PAGE_NUM_8192F 0x00
#endif
#ifdef CONFIG_PNO_SUPPORT
#undef WOWLAN_PAGE_NUM_8192F
#define WOWLAN_PAGE_NUM_8192F 0x15
#endif
#ifdef CONFIG_AP_WOWLAN
#define AP_WOWLAN_PAGE_NUM_8192F 0x02
#endif
#ifdef DBG_LA_MODE
#define LA_MODE_PAGE_NUM 0xE0
#endif
#define MAX_RX_DMA_BUFFER_SIZE_8192F (RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F)
#ifdef DBG_LA_MODE
#define TX_TOTAL_PAGE_NUMBER_8192F (0xFF - LA_MODE_PAGE_NUM)
#else
#define TX_TOTAL_PAGE_NUMBER_8192F (0xFF - BCNQ_PAGE_NUM_8192F - WOWLAN_PAGE_NUM_8192F)
#endif
#define TX_PAGE_BOUNDARY_8192F (TX_TOTAL_PAGE_NUMBER_8192F + 1)
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8192F \
TX_TOTAL_PAGE_NUMBER_8192F
#define WMM_NORMAL_TX_PAGE_BOUNDARY_8192F \
(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8192F + 1)
/* For Normal Chip Setting
* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8192F */
#define NORMAL_PAGE_NUM_HPQ_8192F 0x8
#define NORMAL_PAGE_NUM_LPQ_8192F 0x8
#define NORMAL_PAGE_NUM_NPQ_8192F 0x8
#define NORMAL_PAGE_NUM_EPQ_8192F 0x00
/* Note: For Normal Chip Setting, modify later */
#define WMM_NORMAL_PAGE_NUM_HPQ_8192F 0x30
#define WMM_NORMAL_PAGE_NUM_LPQ_8192F 0x20
#define WMM_NORMAL_PAGE_NUM_NPQ_8192F 0x20
#define WMM_NORMAL_PAGE_NUM_EPQ_8192F 0x00
#include "HalVerDef.h"
#include "hal_com.h"
#define EFUSE_OOB_PROTECT_BYTES 56 /*0x1C8~0x1FF*/
#define HAL_EFUSE_MEMORY
#define HWSET_MAX_SIZE_8192F 512
#define EFUSE_REAL_CONTENT_LEN_8192F 512
#define EFUSE_MAP_LEN_8192F 512
#define EFUSE_MAX_SECTION_8192F 64
/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/
#define EFUSE_IC_ID_OFFSET 506
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8192F)
#define EFUSE_ACCESS_ON 0x69
#define EFUSE_ACCESS_OFF 0x00
/* ********************************************************
* EFUSE for BT definition
* ******************************************************** */
#define BANK_NUM 1
#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512
#define EFUSE_BT_REAL_CONTENT_LEN 1536/*512 * 3 */
/* (EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)*/
#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */
#define EFUSE_BT_MAX_SECTION 128 /* 1024/8 */
#define EFUSE_PROTECT_BYTES_BANK 16
typedef enum tag_Package_Definition {
PACKAGE_DEFAULT,
PACKAGE_QFN32,
PACKAGE_QFN40,
PACKAGE_QFN46
} PACKAGE_TYPE_E;
#define INCLUDE_MULTI_FUNC_BT(_Adapter) \
(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \
(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
#ifdef CONFIG_FILE_FWIMG
extern char *rtw_fw_file_path;
extern char *rtw_fw_wow_file_path;
#ifdef CONFIG_MP_INCLUDED
extern char *rtw_fw_mp_bt_file_path;
#endif /* CONFIG_MP_INCLUDED */
#endif /* CONFIG_FILE_FWIMG */
/* rtl8192f_hal_init.c */
s32 rtl8192f_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw);
void rtl8192f_FirmwareSelfReset(PADAPTER padapter);
void rtl8192f_InitializeFirmwareVars(PADAPTER padapter);
void rtl8192f_InitAntenna_Selection(PADAPTER padapter);
void rtl8192f_DeinitAntenna_Selection(PADAPTER padapter);
void rtl8192f_CheckAntenna_Selection(PADAPTER padapter);
void rtl8192f_init_default_value(PADAPTER padapter);
s32 rtl8192f_InitLLTTable(PADAPTER padapter);
s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
s32 CardDisableWithoutHWSM(PADAPTER padapter);
/* EFuse */
u8 GetEEPROMSize8192F(PADAPTER padapter);
void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
void Hal_EfuseParseTxPowerInfo_8192F(PADAPTER padapter,
u8 *PROMContent, BOOLEAN AutoLoadFail);
/*
void Hal_EfuseParseBTCoexistInfo_8192F(PADAPTER padapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
*/
void Hal_EfuseParseEEPROMVer_8192F(PADAPTER padapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseChnlPlan_8192F(PADAPTER padapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseCustomerID_8192F(PADAPTER padapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseAntennaDiversity_8192F(PADAPTER padapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseXtal_8192F(PADAPTER pAdapter,
u8 *hwinfo, u8 AutoLoadFail);
void Hal_EfuseParseThermalMeter_8192F(PADAPTER padapter,
u8 *hwinfo, u8 AutoLoadFail);
VOID Hal_EfuseParseVoltage_8192F(PADAPTER pAdapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
VOID Hal_EfuseParseBoardType_8192F(PADAPTER Adapter,
u8 *PROMContent, BOOLEAN AutoloadFail);
u8 Hal_ReadRFEType_8192F(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
void rtl8192f_set_hal_ops(struct hal_ops *pHalFunc);
void init_hal_spec_8192f(_adapter *adapter);
u8 SetHwReg8192F(PADAPTER padapter, u8 variable, u8 *val);
void GetHwReg8192F(PADAPTER padapter, u8 variable, u8 *val);
u8 SetHalDefVar8192F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
u8 GetHalDefVar8192F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
/* register */
void rtl8192f_InitBeaconParameters(PADAPTER padapter);
void rtl8192f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
void _InitMacAPLLSetting_8192F(PADAPTER Adapter);
void _8051Reset8192F(PADAPTER padapter);
#ifdef CONFIG_WOWLAN
void Hal_DetectWoWMode(PADAPTER pAdapter);
#endif /* CONFIG_WOWLAN */
void rtl8192f_start_thread(_adapter *padapter);
void rtl8192f_stop_thread(_adapter *padapter);
#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
void rtl8192fs_init_checkbthang_workqueue(_adapter *adapter);
void rtl8192fs_free_checkbthang_workqueue(_adapter *adapter);
void rtl8192fs_cancle_checkbthang_workqueue(_adapter *adapter);
void rtl8192fs_hal_check_bt_hang(_adapter *adapter);
#endif
#ifdef CONFIG_GPIO_WAKEUP
void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
#endif
#ifdef CONFIG_MP_INCLUDED
int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
#endif
void CCX_FwC2HTxRpt_8192f(PADAPTER padapter, u8 *pdata, u8 len);
u8 MRateToHwRate8192F(u8 rate);
u8 HwRateToMRate8192F(u8 rate);
#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
void check_bt_status_work(void *data);
#endif
void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc);
#ifdef CONFIG_AMPDU_PRETX_CD
void rtl8192f_pretx_cd_config(_adapter *adapter);
#endif
#ifdef CONFIG_PCI_HCI
BOOLEAN InterruptRecognized8192FE(PADAPTER Adapter);
VOID UpdateInterruptMask8192FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
VOID InitMAC_TRXBD_8192FE(PADAPTER Adapter);
u16 get_txbd_rw_reg(u16 ff_hwaddr);
#endif
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8192F_LED_H__
#define __RTL8192F_LED_H__
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#ifdef CONFIG_RTW_SW_LED
/* ********************************************************************************
* Interface to manipulate LED objects.
* ******************************************************************************** */
#ifdef CONFIG_USB_HCI
void rtl8192fu_InitSwLeds(PADAPTER padapter);
void rtl8192fu_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_SDIO_HCI
void rtl8192fs_InitSwLeds(PADAPTER padapter);
void rtl8192fs_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8192fe_InitSwLeds(PADAPTER padapter);
void rtl8192fe_DeInitSwLeds(PADAPTER padapter);
#endif
#endif /*#ifdef CONFIG_RTW_SW_LED*/
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8192F_RECV_H__
#define __RTL8192F_RECV_H__
#define RECV_BLK_SZ 512
#define RECV_BLK_CNT 16
#define RECV_BLK_TH RECV_BLK_CNT
#if defined(CONFIG_USB_HCI)
#ifndef MAX_RECVBUF_SZ
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
#else
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) /* 8K */
#else
#define MAX_RECVBUF_SZ (32768) /* 32k */
#endif
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
#else
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#endif
#endif
#endif /* !MAX_RECVBUF_SZ */
#elif defined(CONFIG_PCI_HCI)
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8192F + 1)
#endif
/* Rx smooth factor */
#define Rx_Smooth_Factor (20)
#ifdef CONFIG_SDIO_HCI
#ifndef CONFIG_SDIO_RX_COPY
#undef MAX_RECVBUF_SZ
#define MAX_RECVBUF_SZ (RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F)
#endif /* !CONFIG_SDIO_RX_COPY */
#endif /* CONFIG_SDIO_HCI */
/*-----------------------------------------------------------------*/
/* RTL8192F RX BUFFER DESC */
/*-----------------------------------------------------------------*/
/*DWORD 0*/
#define SET_RX_BUFFER_DESC_DATA_LENGTH_8192F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
#define SET_RX_BUFFER_DESC_LS_8192F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
#define SET_RX_BUFFER_DESC_FS_8192F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)
#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8192F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)
#define GET_RX_BUFFER_DESC_OWN_8192F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
#define GET_RX_BUFFER_DESC_LS_8192F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
#define GET_RX_BUFFER_DESC_FS_8192F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)
#ifdef USING_RX_TAG
#define GET_RX_BUFFER_DESC_RX_TAG_8192F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13)
#else
#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8192F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
#endif
/*DWORD 1*/
#define SET_RX_BUFFER_PHYSICAL_LOW_8192F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
/*DWORD 2*/
#ifdef CONFIG_64BIT_DMA
#define SET_RX_BUFFER_PHYSICAL_HIGH_8192F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
#else
#define SET_RX_BUFFER_PHYSICAL_HIGH_8192F(__pRxStatusDesc, __Value)
#endif
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
s32 rtl8192fs_init_recv_priv(PADAPTER padapter);
void rtl8192fs_free_recv_priv(PADAPTER padapter);
s32 rtl8192fs_recv_hdl(_adapter *padapter);
#endif
#ifdef CONFIG_USB_HCI
int rtl8192fu_init_recv_priv(_adapter *padapter);
void rtl8192fu_free_recv_priv(_adapter *padapter);
void rtl8192fu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8192fe_init_recv_priv(_adapter *padapter);
void rtl8192fe_free_recv_priv(_adapter *padapter);
#endif
void rtl8192f_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
#endif /* __RTL8192F_RECV_H__ */

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/******************************************************************************
*
* Copyright(c) 2012 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8192F_RF_H__
#define __RTL8192F_RF_H__
int PHY_RF6052_Config8192F(IN PADAPTER pdapter);
void PHY_RF6052SetBandwidth8192F(IN PADAPTER Adapter, IN enum channel_width Bandwidth);
#endif/* __RTL8192F_RF_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8192F_SPEC_H__
#define __RTL8192F_SPEC_H__
#include <drv_conf.h>
#define HAL_NAV_UPPER_UNIT_8192F 128 /* micro-second */
/* -----------------------------------------------------
*
* 0x0000h ~ 0x00FFh System Configuration
*
* ----------------------------------------------------- */
#define REG_SYS_ISO_CTRL_8192F 0x0000 /* 2 Byte */
#define REG_SYS_FUNC_EN_8192F 0x0002 /* 2 Byte */
#define REG_APS_FSMCO_8192F 0x0004 /* 4 Byte */
#define REG_SYS_CLKR_8192F 0x0008 /* 2 Byte */
#define REG_9346CR_8192F 0x000A /* 2 Byte */
#define REG_EE_VPD_8192F 0x000C /* 2 Byte */
#define REG_AFE_MISC_8192F 0x0010 /* 1 Byte */
#define REG_SPS0_CTRL_8192F 0x0011 /* 7 Byte */
#define REG_SPS_OCP_CFG_8192F 0x0018 /* 4 Byte */
#define REG_RSV_CTRL_8192F 0x001C /* 3 Byte */
#define REG_RF_CTRL_8192F 0x001F /* 1 Byte */
#define REG_LPLDO_CTRL_8192F 0x0023 /* 1 Byte */
#define REG_AFE_XTAL_CTRL_8192F 0x0024 /* 4 Byte */
#define REG_AFE_PLL_CTRL_8192F 0x0028 /* 4 Byte */
#define REG_MAC_PLL_CTRL_EXT_8192F 0x002c /* 4 Byte */
#define REG_EFUSE_CTRL_8192F 0x0030
#define REG_EFUSE_TEST_8192F 0x0034
#define REG_PWR_DATA_8192F 0x0038
#define REG_CAL_TIMER_8192F 0x003C
#define REG_ACLK_MON_8192F 0x003E
#define REG_GPIO_MUXCFG_8192F 0x0040
#define REG_GPIO_IO_SEL_8192F 0x0042
#define REG_MAC_PINMUX_CFG_8192F 0x0043
#define REG_GPIO_PIN_CTRL_8192F 0x0044
#define REG_GPIO_INTM_8192F 0x0048
#define REG_LEDCFG0_8192F 0x004C
#define REG_LEDCFG1_8192F 0x004D
#define REG_LEDCFG2_8192F 0x004E
#define REG_LEDCFG3_8192F 0x004F
#define REG_FSIMR_8192F 0x0050
#define REG_FSISR_8192F 0x0054
#define REG_HSIMR_8192F 0x0058
#define REG_HSISR_8192F 0x005c
#define REG_GPIO_EXT_CTRL 0x0060
#define REG_PAD_CTRL1_8192F 0x0064
#define REG_MULTI_FUNC_CTRL_8192F 0x0068
#define REG_GPIO_STATUS_8192F 0x006C
#define REG_SDIO_CTRL_8192F 0x0070
#define REG_OPT_CTRL_8192F 0x0074
#define REG_AFE_CTRL_4_8192F 0x0078
#define REG_MCUFWDL_8192F 0x0080
#define REG_8051FW_CTRL_8192F 0x0080
#define REG_HMEBOX_DBG_0_8192F 0x0088
#define REG_HMEBOX_DBG_1_8192F 0x008A
#define REG_HMEBOX_DBG_2_8192F 0x008C
#define REG_HMEBOX_DBG_3_8192F 0x008E
#define REG_WLLPS_CTRL 0x0090
#define REG_HIMR0_8192F 0x00B0
#define REG_HISR0_8192F 0x00B4
#define REG_HIMR1_8192F 0x00B8
#define REG_HISR1_8192F 0x00BC
#define REG_PMC_DBG_CTRL2_8192F 0x00CC
#define REG_EFUSE_BURN_GNT_8192F 0x00CF
#define REG_HPON_FSM_8192F 0x00EC
#define REG_SYS_CFG1_8192F 0x00F0
#define REG_SYS_CFG2_8192F 0x00FC
#define REG_ROM_VERSION 0x00FD
/* -----------------------------------------------------
*
* 0x0100h ~ 0x01FFh MACTOP General Configuration
*
* ----------------------------------------------------- */
#define REG_CR_8192F 0x0100
#define REG_PBP_8192F 0x0104
#define REG_PKT_BUFF_ACCESS_CTRL_8192F 0x0106
#define REG_TRXDMA_CTRL_8192F 0x010C
#define REG_TRXFF_BNDY_8192F 0x0114
#define REG_TRXFF_STATUS_8192F 0x0118
#define REG_RXFF_PTR_8192F 0x011C
#define REG_CPWM_8192F 0x012C
#define REG_FWIMR_8192F 0x0130
#define REG_FWISR_8192F 0x0134
#define REG_FTIMR_8192F 0x0138
#define REG_PKTBUF_DBG_CTRL_8192F 0x0140
#define REG_RXPKTBUF_CTRL_8192F 0x0142
#define REG_PKTBUF_DBG_DATA_L_8192F 0x0144
#define REG_PKTBUF_DBG_DATA_H_8192F 0x0148
#define REG_TC0_CTRL_8192F 0x0150
#define REG_TC1_CTRL_8192F 0x0154
#define REG_TC2_CTRL_8192F 0x0158
#define REG_TC3_CTRL_8192F 0x015C
#define REG_TC4_CTRL_8192F 0x0160
#define REG_TCUNIT_BASE_8192F 0x0164
#define REG_RSVD3_8192F 0x0168
#define REG_C2HEVT_CMD_ID_8192F 0x01A0
#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1
#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2
#define REG_C2HEVT_CMD_LEN_8192F 0x01AE
#define REG_C2HEVT_CLEAR_8192F 0x01AF
#define REG_MCUTST_1_8192F 0x01C0
#define REG_WOWLAN_WAKE_REASON 0x01C7
#define REG_FMETHR_8192F 0x01C8
#define REG_HMETFR_8192F 0x01CC
#define REG_HMEBOX_0_8192F 0x01D0
#define REG_HMEBOX_1_8192F 0x01D4
#define REG_HMEBOX_2_8192F 0x01D8
#define REG_HMEBOX_3_8192F 0x01DC
#define REG_LLT_INIT_8192F 0x01E0
#define REG_HMEBOX_EXT0_8192F 0x01F0
#define REG_HMEBOX_EXT1_8192F 0x01F4
#define REG_HMEBOX_EXT2_8192F 0x01F8
#define REG_HMEBOX_EXT3_8192F 0x01FC
/* -----------------------------------------------------
*
* 0x0200h ~ 0x027Fh TXDMA Configuration
*
* ----------------------------------------------------- */
#define REG_RQPN_8192F 0x0200
#define REG_FIFOPAGE_8192F 0x0204
#define REG_DWBCN0_CTRL_8192F REG_TDECTRL
#define REG_TXDMA_OFFSET_CHK_8192F 0x020C
#define REG_TXDMA_STATUS_8192F 0x0210
#define REG_RQPN_NPQ_8192F 0x0214
#define REG_DWBCN1_CTRL_8192F 0x0228
#define REG_RQPN_EXQ1_EXQ2 0x0230
/* -----------------------------------------------------
*
* 0x0280h ~ 0x02FFh RXDMA Configuration
*
* ----------------------------------------------------- */
#define REG_RXDMA_AGG_PG_TH_8192F 0x0280
#define REG_FW_UPD_RDPTR_8192F 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
#define REG_RXDMA_CONTROL_8192F 0x0286 /* Control the RX DMA. */
#define REG_RXDMA_STATUS_8192F 0x0288
#define REG_RXDMA_MODE_CTRL_8192F 0x0290
#define REG_EARLY_MODE_CONTROL_8192F 0x02BC
#define REG_RSVD5_8192F 0x02F0
#define REG_RSVD6_8192F 0x02F4
/* -----------------------------------------------------
*
* 0x0300h ~ 0x03FFh PCIe
*
* ----------------------------------------------------- */
#define REG_PCIE_CTRL_REG_8192F 0x0300
#define REG_INT_MIG_8192F 0x0304 /* Interrupt Migration */
#define REG_BCNQ_TXBD_DESA_8192F 0x0308 /* TX Beacon Descriptor Address */
#define REG_MGQ_TXBD_DESA_8192F 0x0310 /* TX Manage Queue Descriptor Address */
#define REG_VOQ_TXBD_DESA_8192F 0x0318 /* TX VO Queue Descriptor Address */
#define REG_VIQ_TXBD_DESA_8192F 0x0320 /* TX VI Queue Descriptor Address */
#define REG_BEQ_TXBD_DESA_8192F 0x0328 /* TX BE Queue Descriptor Address */
#define REG_BKQ_TXBD_DESA_8192F 0x0330 /* TX BK Queue Descriptor Address */
#define REG_RXQ_RXBD_DESA_8192F 0x0338 /* RX Queue Descriptor Address */
#define REG_HI0Q_TXBD_DESA_8192F 0x0340
#define REG_HI1Q_TXBD_DESA_8192F 0x0348
#define REG_HI2Q_TXBD_DESA_8192F 0x0350
#define REG_HI3Q_TXBD_DESA_8192F 0x0358
#define REG_HI4Q_TXBD_DESA_8192F 0x0360
#define REG_HI5Q_TXBD_DESA_8192F 0x0368
#define REG_HI6Q_TXBD_DESA_8192F 0x0370
#define REG_HI7Q_TXBD_DESA_8192F 0x0378
#define REG_MGQ_TXBD_NUM_8192F 0x0380
#define REG_RX_RXBD_NUM_8192F 0x0382
#define REG_VOQ_TXBD_NUM_8192F 0x0384
#define REG_VIQ_TXBD_NUM_8192F 0x0386
#define REG_BEQ_TXBD_NUM_8192F 0x0388
#define REG_BKQ_TXBD_NUM_8192F 0x038A
#define REG_HI0Q_TXBD_NUM_8192F 0x038C
#define REG_HI1Q_TXBD_NUM_8192F 0x038E
#define REG_HI2Q_TXBD_NUM_8192F 0x0390
#define REG_HI3Q_TXBD_NUM_8192F 0x0392
#define REG_HI4Q_TXBD_NUM_8192F 0x0394
#define REG_HI5Q_TXBD_NUM_8192F 0x0396
#define REG_HI6Q_TXBD_NUM_8192F 0x0398
#define REG_HI7Q_TXBD_NUM_8192F 0x039A
#define REG_TSFTIMER_HCI_8192F 0x039C
#define REG_BD_RW_PTR_CLR_8192F 0x039C
/* Read Write Point */
#define REG_VOQ_TXBD_IDX_8192F 0x03A0
#define REG_VIQ_TXBD_IDX_8192F 0x03A4
#define REG_BEQ_TXBD_IDX_8192F 0x03A8
#define REG_BKQ_TXBD_IDX_8192F 0x03AC
#define REG_MGQ_TXBD_IDX_8192F 0x03B0
#define REG_RXQ_TXBD_IDX_8192F 0x03B4
#define REG_HI0Q_TXBD_IDX_8192F 0x03B8
#define REG_HI1Q_TXBD_IDX_8192F 0x03BC
#define REG_HI2Q_TXBD_IDX_8192F 0x03C0
#define REG_HI3Q_TXBD_IDX_8192F 0x03C4
#define REG_HI4Q_TXBD_IDX_8192F 0x03C8
#define REG_HI5Q_TXBD_IDX_8192F 0x03CC
#define REG_HI6Q_TXBD_IDX_8192F 0x03D0
#define REG_HI7Q_TXBD_IDX_8192F 0x03D4
#define REG_DBI_WDATA_V1_8192F 0x03E8
#define REG_DBI_RDATA_V1_8192F 0x03EC
#define REG_DBI_FLAG_V1_8192F 0x03F0
#define REG_MDIO_V1_8192F 0x03F4
#define REG_HCI_MIX_CFG_8192F 0x03FC
#define REG_PCIE_HCPWM_8192FE 0x03D8
#define REG_PCIE_HRPWM_8192FE 0x03DC
#define REG_PCIE_MIX_CFG_8192F 0x03F8
/* -----------------------------------------------------
*
* 0x0400h ~ 0x047Fh Protocol Configuration
*
* ----------------------------------------------------- */
#define REG_QUEUELIST_INFO0_8192F 0x0400
#define REG_QUEUELIST_INFO1_8192F 0x0404
#define REG_QUEUELIST_INFO2_8192F 0x0414
#define REG_TXPKT_EMPTY_8192F 0x0418
#define REG_FWHW_TXQ_CTRL_8192F 0x0420
#define REG_HWSEQ_CTRL_8192F 0x0423
#define REG_TXPKTBUF_BCNQ_BDNY_8192F 0x0424
#define REG_TXPKTBUF_MGQ_BDNY_8192F 0x0425
#define REG_LIFECTRL_CTRL_8192F 0x0426
#define REG_MULTI_BCNQ_OFFSET_8192F 0x0427
#define REG_SPEC_SIFS_8192F 0x0428
#define REG_RL_8192F 0x042A
#define REG_TXBF_CTRL_8192F 0x042C
#define REG_DARFRC_8192F 0x0430
#define REG_RARFRC_8192F 0x0438
#define REG_RRSR_8192F 0x0440
#define REG_ARFR0_8192F 0x0444
#define REG_ARFR1_8192F 0x044C
#define REG_CCK_CHECK_8192F 0x0454
#define REG_AMPDU_MAX_TIME_8192F 0x0456
#define REG_TXPKTBUF_BCNQ_BDNY1_8192F 0x0457
#define REG_AMPDU_MAX_LENGTH_8192F 0x0458
#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8192F 0x045D
#define REG_NDPA_OPT_CTRL_8192F 0x045F
#define REG_FAST_EDCA_CTRL_8192F 0x0460
#define REG_RD_RESP_PKT_TH_8192F 0x0463
#define REG_DATA_SC_8192F 0x0483
#define REG_TXRPT_START_OFFSET 0x04AC
#define REG_POWER_STAGE1_8192F 0x04B4
#define REG_POWER_STAGE2_8192F 0x04B8
#define REG_AMPDU_BURST_MODE_8192F 0x04BC
#define REG_PKT_VO_VI_LIFE_TIME_8192F 0x04C0
#define REG_PKT_BE_BK_LIFE_TIME_8192F 0x04C2
#define REG_STBC_SETTING_8192F 0x04C4
#define REG_HT_SINGLE_AMPDU_8192F 0x04C7
#define REG_PROT_MODE_CTRL_8192F 0x04C8
#define REG_MAX_AGGR_NUM_8192F 0x04CA
#define REG_RTS_MAX_AGGR_NUM_8192F 0x04CB
#define REG_BAR_MODE_CTRL_8192F 0x04CC
#define REG_RA_TRY_RATE_AGG_LMT_8192F 0x04CF
#define REG_MACID_PKT_DROP0_8192F 0x04D0
#define REG_MACID_PKT_SLEEP_8192F 0x04D4
#define REG_PRECNT_CTRL_8192F 0x04E5
/* -----------------------------------------------------
*
* 0x0500h ~ 0x05FFh EDCA Configuration
*
* ----------------------------------------------------- */
#define REG_EDCA_VO_PARAM_8192F 0x0500
#define REG_EDCA_VI_PARAM_8192F 0x0504
#define REG_EDCA_BE_PARAM_8192F 0x0508
#define REG_EDCA_BK_PARAM_8192F 0x050C
#define REG_BCNTCFG_8192F 0x0510
#define REG_PIFS_8192F 0x0512
#define REG_RDG_PIFS_8192F 0x0513
#define REG_SIFS_CTX_8192F 0x0514
#define REG_SIFS_TRX_8192F 0x0516
#define REG_AGGR_BREAK_TIME_8192F 0x051A
#define REG_SLOT_8192F 0x051B
#define REG_TX_PTCL_CTRL_8192F 0x0520
#define REG_TXPAUSE_8192F 0x0522
#define REG_DIS_TXREQ_CLR_8192F 0x0523
#define REG_RD_CTRL_8192F 0x0524
/*
* Format for offset 540h-542h:
* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
* [7:4]: Reserved.
* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
* [23:20]: Reserved
* Description:
* |
* |<--Setup--|--Hold------------>|
* --------------|----------------------
* |
* TBTT
* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
* Described by Designer Tim and Bruce, 2011-01-14.
* */
#define REG_TBTT_PROHIBIT_8192F 0x0540
#define REG_RD_NAV_NXT_8192F 0x0544
#define REG_NAV_PROT_LEN_8192F 0x0546
#define REG_BCN_CTRL_8192F 0x0550
#define REG_BCN_CTRL_1_8192F 0x0551
#define REG_MBID_NUM_8192F 0x0552
#define REG_DUAL_TSF_RST_8192F 0x0553
#define REG_BCN_INTERVAL_8192F 0x0554
#define REG_DRVERLYINT_8192F 0x0558
#define REG_BCNDMATIM_8192F 0x0559
#define REG_ATIMWND_8192F 0x055A
#define REG_USTIME_TSF_8192F 0x055C
#define REG_BCN_MAX_ERR_8192F 0x055D
#define REG_RXTSF_OFFSET_CCK_8192F 0x055E
#define REG_RXTSF_OFFSET_OFDM_8192F 0x055F
#define REG_TSFTR_8192F 0x0560
#define REG_CTWND_8192F 0x0572
#define REG_SECONDARY_CCA_CTRL_8192F 0x0577
#define REG_PSTIMER_8192F 0x0580
#define REG_TIMER0_8192F 0x0584
#define REG_TIMER1_8192F 0x0588
#define REG_ACMHWCTRL_8192F 0x05C0
#define REG_SCH_TXCMD_8192F 0x05F8
/* -----------------------------------------------------
*
* 0x0600h ~ 0x07FFh WMAC Configuration
*
* ----------------------------------------------------- */
#define REG_MAC_CR_8192F 0x0600
#define REG_TCR_8192F 0x0604
#define REG_RCR_8192F 0x0608
#define REG_RX_PKT_LIMIT_8192F 0x060C
#define REG_RX_DLK_TIME_8192F 0x060D
#define REG_RX_DRVINFO_SZ_8192F 0x060F
#define REG_MACID_8192F 0x0610
#define REG_BSSID_8192F 0x0618
#define REG_MAR_8192F 0x0620
#define REG_MBIDCAMCFG_8192F 0x0628
#define REG_USTIME_EDCA_8192F 0x0638
#define REG_MAC_SPEC_SIFS_8192F 0x063A
#define REG_RESP_SIFP_CCK_8192F 0x063C
#define REG_RESP_SIFS_OFDM_8192F 0x063E
#define REG_ACKTO_8192F 0x0640
#define REG_CTS2TO_8192F 0x0641
#define REG_EIFS_8192F 0x0642
#define REG_NAV_UPPER_8192F 0x0652 /* unit of 128*/
#define REG_TRXPTCL_CTL_8192F 0x0668
/* Security*/
#define REG_CAMCMD_8192F 0x0670
#define REG_CAMWRITE_8192F 0x0674
#define REG_CAMREAD_8192F 0x0678
#define REG_CAMDBG_8192F 0x067C
#define REG_SECCFG_8192F 0x0680
/* Power */
#define REG_WOW_CTRL_8192F 0x0690
#define REG_PS_RX_INFO_8192F 0x0692
#define REG_UAPSD_TID_8192F 0x0693
#define REG_WKFMCAM_CMD_8192F 0x0698
#define REG_WKFMCAM_NUM_8192F 0x0698
#define REG_WKFMCAM_RWD_8192F 0x069C
#define REG_RXFLTMAP0_8192F 0x06A0
#define REG_RXFLTMAP1_8192F 0x06A2
#define REG_RXFLTMAP2_8192F 0x06A4
#define REG_BCN_PSR_RPT_8192F 0x06A8
#define REG_BT_COEX_TABLE_8192F 0x06C0
#define REG_BFMER0_INFO_8192F 0x06E4
#define REG_BFMER1_INFO_8192F 0x06EC
#define REG_CSI_RPT_PARAM_BW20_8192F 0x06F4
#define REG_CSI_RPT_PARAM_BW40_8192F 0x06F8
#define REG_CSI_RPT_PARAM_BW80_8192F 0x06FC
/* Hardware Port 2 */
#define REG_MACID1_8192F 0x0700
#define REG_BSSID1_8192F 0x0708
#define REG_BFMEE_SEL_8192F 0x0714
#define REG_SND_PTCL_CTRL_8192F 0x0718
/* LTR */
#define REG_LTR_CTRL_BASIC_8192F 0x07A4
#define REG_LTR_IDLE_LATENCY_V1_8192F 0x0798
#define REG_LTR_ACTIVE_LATENCY_V1_8192F 0x079C
/* ************************************************************
* SDIO Bus Specification
* ************************************************************ */
/* -----------------------------------------------------
* SDIO CMD Address Mapping
* ----------------------------------------------------- */
/* -----------------------------------------------------
* I/O bus domain (Host)
* ----------------------------------------------------- */
/*SDIO Host Interrupt Mask Register */
#define SDIO_HIMR_CRCERR_MSK BIT(31)
/* SDIO Host Interrupt Service Routine */
#define SDIO_HISR_HEISR_IND_INT BIT(28)
#define SDIO_HISR_HSISR2_IND_INT BIT(29)
#define SDIO_HISR_HSISR3_IND_INT BIT(30)
#define SDIO_HISR_SDIO_CRCERR BIT(31)
/* -----------------------------------------------------
* SDIO register
* ----------------------------------------------------- */
#define SDIO_REG_HCPWM1_8192F 0x038/* HCI Current Power Mode 1 */
#define SDIO_REG_FREE_TXPG1_8192F 0x0020 /* Free Tx Buffer Page1*/
#define SDIO_REG_FREE_TXPG2_8192F 0x0024 /* Free Tx Buffer Page1*/
#define SDIO_REG_FREE_TXPG3_8192F 0x0028
#define SDIO_REG_AC_OQT_FREEPG_8192F 0x002A
#define SDIO_REG_NOAC_OQT_FREEPG_8192F 0x002B
/* ****************************************************************************
* 8192F Regsiter Bit and Content definition
* **************************************************************************** */
#define BIT_USB_RXDMA_AGG_EN BIT(31)
#define RXDMA_AGG_MODE_EN BIT(1)
#ifdef CONFIG_WOWLAN
#define RXPKT_RELEASE_POLL BIT(16)
#define RXDMA_IDLE BIT(17)
#define RW_RELEASE_EN BIT(18)
#endif
#ifdef CONFIG_AMPDU_PRETX_CD
/*#define BIT_ERRORHDL_INT BIT(2)*/
/*#define BIT_MACTX_ERR_3 BIT(4)*/
#define BIT_PRE_TX_CMD_8192F BIT(6)
#define BIT_EN_PRECNT_8192F BIT(11)
#endif
/* SDIO Host Interrupt Service Routine */
#define SDIO_HISR_HEISR_IND_INT BIT(28)
#define SDIO_HISR_HSISR2_IND_INT BIT(29)
#define SDIO_HISR_HSISR3_IND_INT BIT(30)
#define SDIO_HISR_SDIO_CRCERR BIT(31)
/* PCIE Host Interrupt Mask Register (HIMR) */
#ifdef CONFIG_PCI_HCI
/* ----------------------------------------------------------------------------
* * 8192F IMR/ISR bits (offset 0xB0, 8bits)
* * ---------------------------------------------------------------------------- */
#define IMR_DISABLED_8192F 0
/* IMR DW0(0x00B0-00B3) Bit 0-31 */
#define IMR_TIMER2_8192F BIT(31) /* Timeout interrupt 2 */
#define IMR_TIMER1_8192F BIT(30) /* Timeout interrupt 1 */
#define IMR_PSTIMEOUT_8192F BIT(29) /* Power Save Time Out Interrupt */
#define IMR_GTINT4_8192F BIT(28) /* When GTIMER4 expires, this bit is set to 1 */
#define IMR_GTINT3_8192F BIT(27) /* When GTIMER3 expires, this bit is set to 1 */
#define IMR_TXBCN0ERR_8192F BIT(26) /* Transmit Beacon0 Error */
#define IMR_TXBCN0OK_8192F BIT(25) /* Transmit Beacon0 OK */
#define IMR_TSF_BIT32_TOGGLE_8192F BIT(24) /* TSF Timer BIT32 toggle indication interrupt */
#define IMR_BCNDMAINT0_8192F BIT(20) /* Beacon DMA Interrupt 0 */
#define IMR_BCNDERR0_8192F BIT(16) /* Beacon Queue DMA OK0 */
#define IMR_HSISR_IND_ON_INT_8192F BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
#define IMR_BCNDMAINT_E_8192F BIT(14) /* Beacon DMA Interrupt Extension for Win7 */
#define IMR_ATIMEND_8192F BIT(12) /* CTWidnow End or ATIM Window End */
#define IMR_C2HCMD_8192F BIT(10) /* CPU to Host Command INT status, Write 1 clear */
#define IMR_CPWM2_8192F BIT(9) /* CPU power mode exchange INT status, Write 1 clear */
#define IMR_CPWM_8192F BIT(8) /* CPU power mode exchange INT status, Write 1 clear */
#define IMR_HIGHDOK_8192F BIT(7) /* High Queue DMA OK */
#define IMR_MGNTDOK_8192F BIT(6) /* Management Queue DMA OK */
#define IMR_BKDOK_8192F BIT(5) /* AC_BK DMA OK */
#define IMR_BEDOK_8192F BIT(4) /* AC_BE DMA OK */
#define IMR_VIDOK_8192F BIT(3) /* AC_VI DMA OK */
#define IMR_VODOK_8192F BIT(2) /* AC_VO DMA OK */
#define IMR_RDU_8192F BIT(1) /* Rx Descriptor Unavailable */
#define IMR_ROK_8192F BIT(0) /* Receive DMA OK */
/* IMR DW1(0x00B4-00B7) Bit 0-31 */
#define IMR_MCUERR_8192F BIT(28)
#define IMR_BCNDMAINT7_8192F BIT(27) /* Beacon DMA Interrupt 7 */
#define IMR_BCNDMAINT6_8192F BIT(26) /* Beacon DMA Interrupt 6 */
#define IMR_BCNDMAINT5_8192F BIT(25) /* Beacon DMA Interrupt 5 */
#define IMR_BCNDMAINT4_8192F BIT(24) /* Beacon DMA Interrupt 4 */
#define IMR_BCNDMAINT3_8192F BIT(23) /* Beacon DMA Interrupt 3 */
#define IMR_BCNDMAINT2_8192F BIT(22) /* Beacon DMA Interrupt 2 */
#define IMR_BCNDMAINT1_8192F BIT(21) /* Beacon DMA Interrupt 1 */
#define IMR_BCNDOK7_8192F BIT(20) /* Beacon Queue DMA OK Interrup 7 */
#define IMR_BCNDOK6_8192F BIT(19) /* Beacon Queue DMA OK Interrup 6 */
#define IMR_BCNDOK5_8192F BIT(18) /* Beacon Queue DMA OK Interrup 5 */
#define IMR_BCNDOK4_8192F BIT(17) /* Beacon Queue DMA OK Interrup 4 */
#define IMR_BCNDOK3_8192F BIT(16) /* Beacon Queue DMA OK Interrup 3 */
#define IMR_BCNDOK2_8192F BIT(15) /* Beacon Queue DMA OK Interrup 2 */
#define IMR_BCNDOK1_8192F BIT(14) /* Beacon Queue DMA OK Interrup 1 */
#define IMR_ATIMEND_E_8192F BIT(13) /* ATIM Window End Extension for Win7 */
#define IMR_TXERR_8192F BIT(11) /* Tx Error Flag Interrupt status, write 1 clear. */
#define IMR_RXERR_8192F BIT(10) /* Rx Error Flag INT status, Write 1 clear */
#define IMR_TXFOVW_8192F BIT(9) /* Transmit FIFO Overflow */
#define IMR_RXFOVW_8192F BIT(8) /* Receive FIFO Overflow */
/* #define IMR_RX_MASK (IMR_ROK_8192F|IMR_RDU_8192F|IMR_RXFOVW_8192F) */
#define IMR_TX_MASK (IMR_VODOK_8192F | IMR_VIDOK_8192F | IMR_BEDOK_8192F | IMR_BKDOK_8192F | IMR_MGNTDOK_8192F | IMR_HIGHDOK_8192F)
#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8192F | IMR_TXBCN0OK_8192F | IMR_TXBCN0ERR_8192F | IMR_BCNDERR0_8192F)
#define RT_AC_INT_MASKS (IMR_VIDOK_8192F | IMR_VODOK_8192F | IMR_BEDOK_8192F | IMR_BKDOK_8192F)
#endif /* CONFIG_PCI_HCI */
/* 2 HSISR
* interrupt mask which needs to clear */
#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\
HSISR_SPS_OCP_INT |\
HSISR_RON_INT |\
HSISR_PDNINT |\
HSISR_GPIO9_INT)
#define _TXDMA_HIQ_MAP_8192F(x) (((x) & 0x7) << 19)
#define _TXDMA_MGQ_MAP_8192F(x) (((x) & 0x7) << 16)
#define _TXDMA_BKQ_MAP_8192F(x) (((x) & 0x7) << 13)
#define _TXDMA_BEQ_MAP_8192F(x) (((x) & 0x7) << 10)
#define _TXDMA_VIQ_MAP_8192F(x) (((x) & 0x7) << 7)
#define _TXDMA_VOQ_MAP_8192F(x) (((x) & 0x7) << 4)
/*mac queue info*/
#define QUEUE_TOTAL_NUM 20/*reg414h : 0~f ac queue 0x10~0x13MGQ HIQ BCNQ CMDQ*/
#define QUEUE_ACQ_NUM 16
#define QUEUE_INDEX_MGQ 0x10
#define QUEUE_INDEX_HIQ 0x11
#define QUEUE_INDEX_BCNQ 0x12
#define QUEUE_INDEX_CMDQ 0x13
#endif /* __RTL8192F_SPEC_H__ */

24
include/rtl8192f_sreset.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _RTL8192F_SRESET_H_
#define _RTL8192F_SRESET_H_
#include <rtw_sreset.h>
#ifdef DBG_CONFIG_ERROR_DETECT
extern void rtl8192f_sreset_xmit_status_check(_adapter *padapter);
extern void rtl8192f_sreset_linked_status_check(_adapter *padapter);
#endif /* DBG_CONFIG_ERROR_DETECT */
#endif /* _RTL8192F_SRESET_H_ */

531
include/rtl8192f_xmit.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8192F_XMIT_H__
#define __RTL8192F_XMIT_H__
#define MAX_TID (15)
#ifndef __INC_HAL8192FDESC_H
#define __INC_HAL8192FDESC_H
#define RX_STATUS_DESC_SIZE_8192F 24
#define RX_DRV_INFO_SIZE_UNIT_8192F 8
/* DWORD 0 */
#define SET_RX_STATUS_DESC_PKT_LEN_8192F(__pRxStatusDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
#define SET_RX_STATUS_DESC_EOR_8192F(__pRxStatusDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
#define SET_RX_STATUS_DESC_OWN_8192F(__pRxStatusDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
#define GET_RX_STATUS_DESC_PKT_LEN_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
#define GET_RX_STATUS_DESC_CRC32_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
#define GET_RX_STATUS_DESC_ICV_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
#define GET_RX_STATUS_DESC_SECURITY_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
#define GET_RX_STATUS_DESC_QOS_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
#define GET_RX_STATUS_DESC_SHIFT_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
#define GET_RX_STATUS_DESC_PHY_STATUS_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
#define GET_RX_STATUS_DESC_SWDEC_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
#define GET_RX_STATUS_DESC_EOR_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
#define GET_RX_STATUS_DESC_OWN_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
/* DWORD 1 */
#define GET_RX_STATUS_DESC_MACID_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
#define GET_RX_STATUS_DESC_TID_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
#define GET_RX_STATUS_DESC_AMSDU_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
#define GET_RX_STATUS_DESC_RXID_MATCH_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
#define GET_RX_STATUS_DESC_PAGGR_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
#define GET_RX_STATUS_DESC_A1_FIT_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
#define GET_RX_STATUS_DESC_CHKERR_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
#define GET_RX_STATUS_DESC_IPVER_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
#define GET_RX_STATUS_DESC_IS_TCPUDP__8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
#define GET_RX_STATUS_DESC_CHK_VLD_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
#define GET_RX_STATUS_DESC_PAM_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
#define GET_RX_STATUS_DESC_PWR_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
#define GET_RX_STATUS_DESC_MORE_DATA_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
#define GET_RX_STATUS_DESC_MORE_FRAG_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
#define GET_RX_STATUS_DESC_TYPE_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
#define GET_RX_STATUS_DESC_MC_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
#define GET_RX_STATUS_DESC_BC_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
/* DWORD 2 */
#define GET_RX_STATUS_DESC_SEQ_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
#define GET_RX_STATUS_DESC_FRAG_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
#define GET_RX_STATUS_DESC_RX_IS_QOS_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
#define GET_RX_STATUS_DESC_RPT_SEL_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
#define GET_RX_STATUS_DESC_FCS_OK_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
/* DWORD 3 */
#define GET_RX_STATUS_DESC_RX_RATE_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
#define GET_RX_STATUS_DESC_HTC_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
#define GET_RX_STATUS_DESC_EOSP_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
#define GET_RX_STATUS_DESC_BSSID_FIT_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
#ifdef CONFIG_USB_RX_AGGREGATION
#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
#endif
#define GET_RX_STATUS_DESC_PATTERN_MATCH_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
#define GET_RX_STATUS_DESC_UNICAST_MATCH_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
#define GET_RX_STATUS_DESC_MAGIC_MATCH_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
/* DWORD 6 */
#define GET_RX_STATUS_DESC_MATCH_ID_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7)
/* DWORD 5 */
#define GET_RX_STATUS_DESC_TSFL_8192F(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
#define GET_RX_STATUS_DESC_BUFF_ADDR64_8192F(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
/* Dword 0, rsvd: bit26, bit28 */
#define GET_TX_DESC_OWN_8192F(__pTxDesc)\
LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
#define SET_TX_DESC_PKT_SIZE_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
#define SET_TX_DESC_OFFSET_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
#define SET_TX_DESC_BMC_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
#define SET_TX_DESC_HTC_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
#define SET_TX_DESC_AMSDU_PAD_EN_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
#define SET_TX_DESC_NO_ACM_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
#define SET_TX_DESC_GF_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
/* Dword 1 */
#define SET_TX_DESC_MACID_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
#define SET_TX_DESC_QUEUE_SEL_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
#define SET_TX_DESC_RDG_NAV_EXT_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
#define SET_TX_DESC_LSIG_TXOP_EN_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
#define SET_TX_DESC_PIFS_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
#define SET_TX_DESC_RATE_ID_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
#define SET_TX_DESC_EN_DESC_ID_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
#define SET_TX_DESC_SEC_TYPE_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
#define SET_TX_DESC_PKT_OFFSET_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
#define SET_TX_DESC_MORE_DATA_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
/* Dword 2 ADD HW_DIG*/
#define SET_TX_DESC_PAID_92F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value)
#define SET_TX_DESC_CCA_RTS_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
#define SET_TX_DESC_AGG_ENABLE_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
#define SET_TX_DESC_RDG_ENABLE_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
#define SET_TX_DESC_NULL0_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
#define SET_TX_DESC_NULL1_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
#define SET_TX_DESC_BK_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
#define SET_TX_DESC_MORE_FRAG_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
#define SET_TX_DESC_RAW_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
#define SET_TX_DESC_CCX_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
#define SET_TX_DESC_AMPDU_DENSITY_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
#define SET_TX_DESC_BT_INT_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
#define SET_TX_DESC_HW_DIG_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 7, __Value)
/* Dword 3 */
#define SET_TX_DESC_HWSEQ_SEL_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
#define SET_TX_DESC_USE_RATE_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
#define SET_TX_DESC_DISABLE_RTS_FB_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
#define SET_TX_DESC_DISABLE_FB_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
#define SET_TX_DESC_CTS2SELF_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
#define SET_TX_DESC_RTS_ENABLE_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
#define SET_TX_DESC_HW_RTS_ENABLE_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
#define SET_TX_DESC_CHK_EN_92F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value)
#define SET_TX_DESC_NAV_USE_HDR_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
#define SET_TX_DESC_USE_MAX_LEN_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
#define SET_TX_DESC_MAX_AGG_NUM_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
#define SET_TX_DESC_NDPA_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
#define SET_TX_DESC_AMPDU_MAX_TIME_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
/* Dword 4 */
#define SET_TX_DESC_TX_RATE_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
#define SET_TX_DESC_TX_TRY_RATE_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
#define SET_TX_DESC_DATA_RETRY_LIMIT_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
#define SET_TX_DESC_RTS_RATE_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
#define SET_TX_DESC_PCTS_EN_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
#define SET_TX_DESC_PCTS_MASK_IDX_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
/* Dword 5 */
#define SET_TX_DESC_DATA_SC_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
#define SET_TX_DESC_DATA_SHORT_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
#define SET_TX_DESC_DATA_BW_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
#define SET_TX_DESC_DATA_LDPC_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
#define SET_TX_DESC_DATA_STBC_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
#define SET_TX_DESC_RTS_STBC_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
#define SET_TX_DESC_RTS_SHORT_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
#define SET_TX_DESC_RTS_SC_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
#define SET_TX_DESC_PORT_ID_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 21, 1, __Value)
#define SET_TX_DESC_DROP_ID_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 22, 2, __Value)
#define SET_TX_DESC_PATH_A_EN_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value)
#define SET_TX_DESC_PATH_B_EN_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 25, 1, __Value)
#define SET_TX_DESC_TXPWR_OF_SET_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
/* Dword 6 */
#define SET_TX_DESC_SW_DEFINE_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
#define SET_TX_DESC_MBSSID_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
#define SET_TX_DESC_RF_SEL_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
/* Dword 7 */
#ifdef CONFIG_PCI_HCI
#define SET_TX_DESC_TX_BUFFER_SIZE_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#endif
#ifdef CONFIG_USB_HCI
#define SET_TX_DESC_TX_DESC_CHECKSUM_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#endif
#ifdef CONFIG_SDIO_HCI
#define SET_TX_DESC_TX_TIMESTAMP_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value)
#endif
#define SET_TX_DESC_USB_TXAGG_NUM_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
/* Dword 8 */
#define SET_TX_DESC_RTS_RC_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
#define SET_TX_DESC_BAR_RC_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
#define SET_TX_DESC_DATA_RC_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
#define SET_TX_DESC_HWSEQ_EN_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
#define SET_TX_DESC_NEXTHEADPAGE_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
#define SET_TX_DESC_TAILPAGE_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
/* Dword 9 */
#define SET_TX_DESC_PADDING_LEN_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
#define SET_TX_DESC_SEQ_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
#define SET_TX_DESC_FINAL_DATA_RATE_8192F(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)
#define SET_EARLYMODE_PKTNUM_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
#define SET_EARLYMODE_LEN0_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
#define SET_EARLYMODE_LEN1_1_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
#define SET_EARLYMODE_LEN1_2_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
#define SET_EARLYMODE_LEN2_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value)
#define SET_EARLYMODE_LEN3_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
/*-----------------------------------------------------------------*/
/* RTL8192F TX BUFFER DESC */
/*-----------------------------------------------------------------*/
#ifdef CONFIG_64BIT_DMA
#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)
#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)
#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)
#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)
#else
#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) /* 64 BIT mode only */
#endif
/* ********************************************************* */
/* 64 bits -- 32 bits */
/* ======= ======= */
/* Dword 0 0 */
#define SET_TX_BUFF_DESC_LEN_0_8192F(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)
#define SET_TX_BUFF_DESC_PSB_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
#define SET_TX_BUFF_DESC_OWN_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
/* Dword 1 1 */
#define SET_TX_BUFF_DESC_ADDR_LOW_0_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
#define GET_TX_BUFF_DESC_ADDR_LOW_0_8192F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
/* Dword 2 NA */
#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value)
#ifdef CONFIG_64BIT_DMA
#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)
#else
#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc) 0
#endif
/* Dword 3 NA */
/* RESERVED 0 */
/* Dword 4 2 */
#define SET_TX_BUFF_DESC_LEN_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value)
#define SET_TX_BUFF_DESC_AMSDU_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value)
/* Dword 5 3 */
#define SET_TX_BUFF_DESC_ADDR_LOW_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value)
/* Dword 6 NA */
#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value)
/* Dword 7 NA */
/*RESERVED 0 */
/* Dword 8 4 */
#define SET_TX_BUFF_DESC_LEN_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value)
#define SET_TX_BUFF_DESC_AMSDU_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value)
/* Dword 9 5 */
#define SET_TX_BUFF_DESC_ADDR_LOW_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value)
/* Dword 10 NA */
#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value)
/* Dword 11 NA */
/*RESERVED 0 */
/* Dword 12 6 */
#define SET_TX_BUFF_DESC_LEN_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value)
#define SET_TX_BUFF_DESC_AMSDU_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value)
/* Dword 13 7 */
#define SET_TX_BUFF_DESC_ADDR_LOW_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value)
/* Dword 14 NA */
#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value)
/* Dword 15 NA */
/*RESERVED 0 */
#endif
/* -----------------------------------------------------------
*
* Rate
*
* -----------------------------------------------------------
* CCK Rates, TxHT = 0 */
#define DESC8192F_RATE1M 0x00
#define DESC8192F_RATE2M 0x01
#define DESC8192F_RATE5_5M 0x02
#define DESC8192F_RATE11M 0x03
/* OFDM Rates, TxHT = 0 */
#define DESC8192F_RATE6M 0x04
#define DESC8192F_RATE9M 0x05
#define DESC8192F_RATE12M 0x06
#define DESC8192F_RATE18M 0x07
#define DESC8192F_RATE24M 0x08
#define DESC8192F_RATE36M 0x09
#define DESC8192F_RATE48M 0x0a
#define DESC8192F_RATE54M 0x0b
/* MCS Rates, TxHT = 1 */
#define DESC8192F_RATEMCS0 0x0c
#define DESC8192F_RATEMCS1 0x0d
#define DESC8192F_RATEMCS2 0x0e
#define DESC8192F_RATEMCS3 0x0f
#define DESC8192F_RATEMCS4 0x10
#define DESC8192F_RATEMCS5 0x11
#define DESC8192F_RATEMCS6 0x12
#define DESC8192F_RATEMCS7 0x13
#define DESC8192F_RATEMCS8 0x14
#define DESC8192F_RATEMCS9 0x15
#define DESC8192F_RATEMCS10 0x16
#define DESC8192F_RATEMCS11 0x17
#define DESC8192F_RATEMCS12 0x18
#define DESC8192F_RATEMCS13 0x19
#define DESC8192F_RATEMCS14 0x1a
#define DESC8192F_RATEMCS15 0x1b
#define DESC8192F_RATEVHTSS1MCS0 0x2c
#define DESC8192F_RATEVHTSS1MCS1 0x2d
#define DESC8192F_RATEVHTSS1MCS2 0x2e
#define DESC8192F_RATEVHTSS1MCS3 0x2f
#define DESC8192F_RATEVHTSS1MCS4 0x30
#define DESC8192F_RATEVHTSS1MCS5 0x31
#define DESC8192F_RATEVHTSS1MCS6 0x32
#define DESC8192F_RATEVHTSS1MCS7 0x33
#define DESC8192F_RATEVHTSS1MCS8 0x34
#define DESC8192F_RATEVHTSS1MCS9 0x35
#define DESC8192F_RATEVHTSS2MCS0 0x36
#define DESC8192F_RATEVHTSS2MCS1 0x37
#define DESC8192F_RATEVHTSS2MCS2 0x38
#define DESC8192F_RATEVHTSS2MCS3 0x39
#define DESC8192F_RATEVHTSS2MCS4 0x3a
#define DESC8192F_RATEVHTSS2MCS5 0x3b
#define DESC8192F_RATEVHTSS2MCS6 0x3c
#define DESC8192F_RATEVHTSS2MCS7 0x3d
#define DESC8192F_RATEVHTSS2MCS8 0x3e
#define DESC8192F_RATEVHTSS2MCS9 0x3f
#define RX_HAL_IS_CCK_RATE_8192F(pDesc)\
(GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE1M || \
GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE2M || \
GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE5_5M || \
GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE11M)
#ifdef CONFIG_TRX_BD_ARCH
struct tx_desc;
#endif
void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc);
void rtl8192f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
void rtl8192f_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
void rtl8192f_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
void rtl8192f_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
void rtl8192f_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
#if defined(CONFIG_CONCURRENT_MODE)
void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
#endif
void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
s32 rtl8192fs_init_xmit_priv(PADAPTER padapter);
void rtl8192fs_free_xmit_priv(PADAPTER padapter);
s32 rtl8192fs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8192fs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
s32 rtl8192fs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8192fs_xmit_buf_handler(PADAPTER padapter);
thread_return rtl8192fs_xmit_thread(thread_context context);
#define hal_xmit_handler rtl8192fs_xmit_buf_handler
#endif
#ifdef CONFIG_USB_HCI
s32 rtl8192fu_init_xmit_priv(PADAPTER padapter);
void rtl8192fu_free_xmit_priv(PADAPTER padapter);
s32 rtl8192fu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8192fu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
s32 rtl8192fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8192fu_xmit_buf_handler(PADAPTER padapter);
#define hal_xmit_handler rtl8192fu_xmit_buf_handler
void rtl8192fu_xmit_tasklet(void *priv);
s32 rtl8192fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
void _dbg_dump_tx_info(_adapter *padapter,int frame_tag,struct tx_desc *ptxdesc);
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8192fe_init_xmit_priv(PADAPTER padapter);
void rtl8192fe_free_xmit_priv(PADAPTER padapter);
struct xmit_buf *rtl8192fe_dequeue_xmitbuf(struct rtw_tx_ring *ring);
void rtl8192fe_xmitframe_resume(_adapter *padapter);
s32 rtl8192fe_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8192fe_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
s32 rtl8192fe_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
void rtl8192fe_xmit_tasklet(void *priv);
#endif
u8 BWMapping_8192F(PADAPTER Adapter, struct pkt_attrib *pattrib);
u8 SCMapping_8192F(PADAPTER Adapter, struct pkt_attrib *pattrib);
#endif

2
include/rtl8703b_cmd.h
View File

@@ -113,7 +113,6 @@ enum h2c_cmd_8703B {
#define SET_8703B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8703B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
#define SET_8703B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8703B_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
#define GET_8703B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
@@ -177,7 +176,6 @@ enum h2c_cmd_8703B {
/* host message to firmware cmd */
void rtl8703b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
void rtl8703b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
void rtl8703b_set_rssi_cmd(PADAPTER padapter, u8 *param);
void rtl8703b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
/* s32 rtl8703b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
void rtl8703b_set_FwPsTuneParam_cmd(PADAPTER padapter);

16
include/rtl8703b_hal.h
View File

@@ -106,18 +106,10 @@ typedef struct _RT_8703B_FIRMWARE_HDR {
/* Note: We will divide number of page equally for each queue other than public queue! */
/* For General Reserved Page Number(Beacon Queue is reserved page)
* Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1 */
#define BCNQ_PAGE_NUM_8703B 0x08
#ifdef CONFIG_CONCURRENT_MODE
#define BCNQ1_PAGE_NUM_8703B 0x08 /* 0x04 */
#else
#define BCNQ1_PAGE_NUM_8703B 0x00
#endif
* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8703B
* PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
#ifdef CONFIG_PNO_SUPPORT
#undef BCNQ1_PAGE_NUM_8703B
#define BCNQ1_PAGE_NUM_8703B 0x00 /* 0x04 */
#endif
#define BCNQ_PAGE_NUM_8703B (MAX_BEACON_LEN/PAGE_SIZE_TX_8703B + 6) /*0x08*/
/* For WoWLan , more reserved page
* ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1 PNO: 6
@@ -138,7 +130,7 @@ typedef struct _RT_8703B_FIRMWARE_HDR {
#define AP_WOWLAN_PAGE_NUM_8703B 0x02
#endif
#define TX_TOTAL_PAGE_NUMBER_8703B (0xFF - BCNQ_PAGE_NUM_8703B - BCNQ1_PAGE_NUM_8703B - WOWLAN_PAGE_NUM_8703B)
#define TX_TOTAL_PAGE_NUMBER_8703B (0xFF - BCNQ_PAGE_NUM_8703B - WOWLAN_PAGE_NUM_8703B)
#define TX_PAGE_BOUNDARY_8703B (TX_TOTAL_PAGE_NUMBER_8703B + 1)
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8703B TX_TOTAL_PAGE_NUMBER_8703B

7
include/rtl8703b_xmit.h
View File

@@ -184,13 +184,14 @@
#define SET_TX_DESC_ANTSEL_D_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
/* Dword 7 */
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
#ifdef CONFIG_PCI_HCI
#define SET_TX_DESC_TX_BUFFER_SIZE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#else
#endif /*CONFIG_PCI_HCI*/
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
#define SET_TX_DESC_TX_DESC_CHECKSUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#endif
#define SET_TX_DESC_USB_TXAGG_NUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
#if (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
#ifdef CONFIG_SDIO_HCI
#define SET_TX_DESC_SDIO_TXSEQ_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
#endif

175
include/rtl8710b_cmd.h Normal file
View File

@@ -0,0 +1,175 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8710B_CMD_H__
#define __RTL8710B_CMD_H__
/* ---------------------------------------------------------------------------------------------------------
* ---------------------------------- H2C CMD DEFINITION ------------------------------------------------
* --------------------------------------------------------------------------------------------------------- */
enum h2c_cmd_8710B {
/* Common Class: 000 */
H2C_8710B_RSVD_PAGE = 0x00,
H2C_8710B_MEDIA_STATUS_RPT = 0x01,
H2C_8710B_SCAN_ENABLE = 0x02,
H2C_8710B_KEEP_ALIVE = 0x03,
H2C_8710B_DISCON_DECISION = 0x04,
H2C_8710B_PSD_OFFLOAD = 0x05,
H2C_8710B_AP_OFFLOAD = 0x08,
H2C_8710B_BCN_RSVDPAGE = 0x09,
H2C_8710B_PROBERSP_RSVDPAGE = 0x0A,
H2C_8710B_FCS_RSVDPAGE = 0x10,
H2C_8710B_FCS_INFO = 0x11,
H2C_8710B_AP_WOW_GPIO_CTRL = 0x13,
/* PoweSave Class: 001 */
H2C_8710B_SET_PWR_MODE = 0x20,
H2C_8710B_PS_TUNING_PARA = 0x21,
H2C_8710B_PS_TUNING_PARA2 = 0x22,
H2C_8710B_P2P_LPS_PARAM = 0x23,
H2C_8710B_P2P_PS_OFFLOAD = 0x24,
H2C_8710B_PS_SCAN_ENABLE = 0x25,
H2C_8710B_SAP_PS_ = 0x26,
H2C_8710B_INACTIVE_PS_ = 0x27, /* Inactive_PS */
H2C_8710B_FWLPS_IN_IPS_ = 0x28,
/* Dynamic Mechanism Class: 010 */
H2C_8710B_MACID_CFG = 0x40,
H2C_8710B_TXBF = 0x41,
H2C_8710B_RSSI_SETTING = 0x42,
H2C_8710B_AP_REQ_TXRPT = 0x43,
H2C_8710B_INIT_RATE_COLLECT = 0x44,
H2C_8710B_RA_PARA_ADJUST = 0x46,
/* WOWLAN Class: 100 */
H2C_8710B_WOWLAN = 0x80,
H2C_8710B_REMOTE_WAKE_CTRL = 0x81,
H2C_8710B_AOAC_GLOBAL_INFO = 0x82,
H2C_8710B_AOAC_RSVD_PAGE = 0x83,
H2C_8710B_AOAC_RSVD_PAGE2 = 0x84,
H2C_8710B_D0_SCAN_OFFLOAD_CTRL = 0x85,
H2C_8710B_D0_SCAN_OFFLOAD_INFO = 0x86,
H2C_8710B_CHNL_SWITCH_OFFLOAD = 0x87,
H2C_8710B_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
H2C_8710B_P2P_OFFLOAD = 0x8B,
H2C_8710B_RESET_TSF = 0xC0,
H2C_8710B_MAXID,
};
/* ---------------------------------------------------------------------------------------------------------
* ---------------------------------- H2C CMD CONTENT --------------------------------------------------
* ---------------------------------------------------------------------------------------------------------
* _RSVDPAGE_LOC_CMD_0x00 */
#define SET_8710B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8710B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_8710B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8710B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8710B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
/* _PWR_MOD_CMD_0x20 */
#define SET_8710B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8710B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
#define SET_8710B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
#define SET_8710B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8710B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8710B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
#define SET_8710B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define GET_8710B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
/* _PS_TUNE_PARAM_CMD_0x21 */
#define SET_8710B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8710B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_8710B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
#define SET_8710B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
#define SET_8710B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
/* _MACID_CFG_CMD_0x40 */
#define SET_8710B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8710B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
#define SET_8710B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
#define SET_8710B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
#define SET_8710B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
#define SET_8710B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
#define SET_8710B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
#define SET_8710B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
/* _RSSI_SETTING_CMD_0x42 */
#define SET_8710B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8710B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
#define SET_8710B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
/* _AP_REQ_TXRPT_CMD_0x43 */
#define SET_8710B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8710B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
/* _FORCE_BT_TXPWR_CMD_0x62 */
#define SET_8710B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
/* _FORCE_BT_MP_OPER_CMD_0x67 */
#define SET_8710B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
#define SET_8710B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
#define SET_8710B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_8710B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
#define SET_8710B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
#define SET_8710B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
/* _BT_FW_PATCH_0x6A */
#define SET_8710B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
/* ---------------------------------------------------------------------------------------------------------
* ------------------------------------------- Structure --------------------------------------------------
* --------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------
* ---------------------------------- Function Statement --------------------------------------------------
* --------------------------------------------------------------------------------------------------------- */
/* host message to firmware cmd */
void rtl8710b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
void rtl8710b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
/* s32 rtl8710b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
void rtl8710b_set_FwPsTuneParam_cmd(PADAPTER padapter);
void rtl8710b_download_rsvd_page(PADAPTER padapter, u8 mstatus);
#ifdef CONFIG_BT_COEXIST
void rtl8710b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
#endif /* CONFIG_BT_COEXIST */
#ifdef CONFIG_P2P
void rtl8710b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
#endif /* CONFIG_P2P */
#ifdef CONFIG_TDLS
#ifdef CONFIG_TDLS_CH_SW
void rtl8710b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable);
#endif
#endif
#ifdef CONFIG_P2P_WOWLAN
void rtl8710b_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
#endif
s32 FillH2CCmd8710B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
u8 GetTxBufferRsvdPageNum8710B(_adapter *padapter, bool wowlan);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8710B_DM_H__
#define __RTL8710B_DM_H__
/* ************************************************************
* Description:
*
* This file is for 8710B dynamic mechanism only
*
*
* ************************************************************ */
/* ************************************************************
* structure and define
* ************************************************************ */
/* ************************************************************
* function prototype
* ************************************************************ */
void rtl8710b_init_dm_priv(PADAPTER padapter);
void rtl8710b_deinit_dm_priv(PADAPTER padapter);
void rtl8710b_InitHalDm(PADAPTER padapter);
void rtl8710b_HalDmWatchDog(PADAPTER padapter);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8710B_HAL_H__
#define __RTL8710B_HAL_H__
#include "hal_data.h"
#include "rtl8710b_spec.h"
#include "rtl8710b_rf.h"
#include "rtl8710b_dm.h"
#include "rtl8710b_recv.h"
#include "rtl8710b_xmit.h"
#include "rtl8710b_cmd.h"
#include "rtl8710b_led.h"
#include "Hal8710BPwrSeq.h"
#include "Hal8710BPhyReg.h"
#include "Hal8710BPhyCfg.h"
#ifdef DBG_CONFIG_ERROR_DETECT
#include "rtl8710b_sreset.h"
#endif
#ifdef CONFIG_LPS_POFF
#include "rtl8710b_lps_poff.h"
#endif
#define FW_8710B_SIZE 0x8000
#define FW_8710B_START_ADDRESS 0x1000
#define FW_8710B_END_ADDRESS 0x1FFF /* 0x5FFF */
typedef struct _RT_FIRMWARE {
FIRMWARE_SOURCE eFWSource;
#ifdef CONFIG_EMBEDDED_FWIMG
u8 *szFwBuffer;
#else
u8 szFwBuffer[FW_8710B_SIZE];
#endif
u32 ulFwLength;
} RT_FIRMWARE_8710B, *PRT_FIRMWARE_8710B;
/*
* This structure must be cared byte-ordering
*
* Added by tynli. 2009.12.04. */
typedef struct _RT_8710B_FIRMWARE_HDR {
/* 8-byte alinment required */
/* --- LONG WORD 0 ---- */
u16 Signature; /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
u8 Category; /* AP/NIC and USB/PCI */
u8 Function; /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
u16 Version; /* FW Version */
u16 Subversion; /* FW Subversion, default 0x00 */
/* --- LONG WORD 1 ---- */
u8 Month; /* Release time Month field */
u8 Date; /* Release time Date field */
u8 Hour; /* Release time Hour field */
u8 Minute; /* Release time Minute field */
u16 RamCodeSize; /* The size of RAM code */
u16 Rsvd2;
/* --- LONG WORD 2 ---- */
u32 SvnIdx; /* The SVN entry index */
u32 Rsvd3;
/* --- LONG WORD 3 ---- */
u32 Rsvd4;
u32 Rsvd5;
} RT_8710B_FIRMWARE_HDR, *PRT_8710B_FIRMWARE_HDR;
#define DRIVER_EARLY_INT_TIME_8710B 0x05
#define BCN_DMA_ATIME_INT_TIME_8710B 0x02
/* for 8710B
* TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
#define PAGE_SIZE_TX_8710B 128
#define PAGE_SIZE_RX_8710B 8
#define TX_DMA_SIZE_8710B 0x8000 /* 32K(TX) */
#define RX_DMA_SIZE_8710B 0x4000 /* 16K(RX) */
#ifdef CONFIG_WOWLAN
#define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
#else
#define RESV_FMWF 0
#endif
#ifdef CONFIG_FW_C2H_DEBUG
#define RX_DMA_RESERVED_SIZE_8710B 0x100 /* 256B, reserved for c2h debug message */
#else
#define RX_DMA_RESERVED_SIZE_8710B 0x80 /* 128B, reserved for tx report */
#endif
#define RX_DMA_BOUNDARY_8710B\
(RX_DMA_SIZE_8710B - RX_DMA_RESERVED_SIZE_8710B - 1)
/* Note: We will divide number of page equally for each queue other than public queue! */
/* For General Reserved Page Number(Beacon Queue is reserved page)
* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8710B
* PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
#define BCNQ_PAGE_NUM_8710B (MAX_BEACON_LEN/PAGE_SIZE_TX_8710B + 6) /*0x08*/
/* For WoWLan , more reserved page
* ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6
* NS offload: 2 NDP info: 1
*/
#ifdef CONFIG_WOWLAN
#define WOWLAN_PAGE_NUM_8710B 0x0b
#else
#define WOWLAN_PAGE_NUM_8710B 0x00
#endif
#ifdef CONFIG_PNO_SUPPORT
#undef WOWLAN_PAGE_NUM_8710B
#define WOWLAN_PAGE_NUM_8710B 0x15
#endif
#ifdef CONFIG_AP_WOWLAN
#define AP_WOWLAN_PAGE_NUM_8710B 0x02
#endif
#define TX_TOTAL_PAGE_NUMBER_8710B\
(0xFF - BCNQ_PAGE_NUM_8710B -WOWLAN_PAGE_NUM_8710B)
#define TX_PAGE_BOUNDARY_8710B (TX_TOTAL_PAGE_NUMBER_8710B + 1)
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8710B TX_TOTAL_PAGE_NUMBER_8710B
#define WMM_NORMAL_TX_PAGE_BOUNDARY_8710B\
(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8710B + 1)
/* For Normal Chip Setting
* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8710B */
#define NORMAL_PAGE_NUM_HPQ_8710B 0x0C
#define NORMAL_PAGE_NUM_LPQ_8710B 0x02
#define NORMAL_PAGE_NUM_NPQ_8710B 0x02
#define NORMAL_PAGE_NUM_EPQ_8710B 0x04
/* Note: For Normal Chip Setting, modify later */
#define WMM_NORMAL_PAGE_NUM_HPQ_8710B 0x30
#define WMM_NORMAL_PAGE_NUM_LPQ_8710B 0x20
#define WMM_NORMAL_PAGE_NUM_NPQ_8710B 0x20
#define WMM_NORMAL_PAGE_NUM_EPQ_8710B 0x00
#include "HalVerDef.h"
#include "hal_com.h"
#define EFUSE_OOB_PROTECT_BYTES (96 + 1)
#define HAL_EFUSE_MEMORY
#define HWSET_MAX_SIZE_8710B 512
#define EFUSE_REAL_CONTENT_LEN_8710B 512
#define EFUSE_MAP_LEN_8710B 512
#define EFUSE_MAX_SECTION_8710B 64
/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/
#define EFUSE_IC_ID_OFFSET 506
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8710B)
#define EFUSE_ACCESS_ON 0x69
#define EFUSE_ACCESS_OFF 0x00
#define PACKAGE_QFN32_S 0
#define PACKAGE_QFN48M_S 1 //definiton 8188GU Dongle Package, Efuse Physical Address 0xF8 = 0xFE
#define PACKAGE_QFN48_S 2
#define PACKAGE_QFN64_S 3
#define PACKAGE_QFN32_U 4
#define PACKAGE_QFN48M_U 5 //definiton 8188GU Dongle Package, Efuse Physical Address 0xF8 = 0xEE
#define PACKAGE_QFN48_U 6
#define PACKAGE_QFN68_U 7
typedef enum _PACKAGE_TYPE_E
{
PACKAGE_DEFAULT,
PACKAGE_QFN68,
PACKAGE_TFBGA90,
PACKAGE_TFBGA80,
PACKAGE_TFBGA79
}PACKAGE_TYPE_E;
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \
(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
#ifdef CONFIG_FILE_FWIMG
extern char *rtw_fw_file_path;
extern char *rtw_fw_wow_file_path;
#ifdef CONFIG_MP_INCLUDED
extern char *rtw_fw_mp_bt_file_path;
#endif /* CONFIG_MP_INCLUDED */
#endif /* CONFIG_FILE_FWIMG */
/* rtl8710b_hal_init.c */
s32 rtl8710b_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw);
void rtl8710b_FirmwareSelfReset(PADAPTER padapter);
void rtl8710b_InitializeFirmwareVars(PADAPTER padapter);
void rtl8710b_InitAntenna_Selection(PADAPTER padapter);
void rtl8710b_DeinitAntenna_Selection(PADAPTER padapter);
void rtl8710b_CheckAntenna_Selection(PADAPTER padapter);
void rtl8710b_init_default_value(PADAPTER padapter);
u32 indirect_read32_8710b(PADAPTER padapter, u32 regaddr);
VOID indirect_write32_8710b(PADAPTER padapter, u32 regaddr, u32 data);
u32 hal_query_syson_reg_8710b(PADAPTER padapter, u32 regaddr, u32 bitmask);
VOID hal_set_syson_reg_8710b(PADAPTER padapter, u32 regaddr, u32 bitmask, u32 data);
#define HAL_SetSYSOnReg hal_set_syson_reg_8710b
/* EFuse */
u8 GetEEPROMSize8710B(PADAPTER padapter);
#if 0
void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
void Hal_EfuseParseTxPowerInfo_8710B(PADAPTER padapter,
u8 *PROMContent, BOOLEAN AutoLoadFail);
void Hal_EfuseParseEEPROMVer_8710B(PADAPTER padapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParsePackageType_8710B(PADAPTER pAdapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseChnlPlan_8710B(PADAPTER padapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseCustomerID_8710B(PADAPTER padapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseAntennaDiversity_8710B(PADAPTER padapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseXtal_8710B(PADAPTER pAdapter,
u8 *hwinfo, u8 AutoLoadFail);
void Hal_EfuseParseThermalMeter_8710B(PADAPTER padapter,
u8 *hwinfo, u8 AutoLoadFail);
VOID Hal_EfuseParseBoardType_8710B(PADAPTER Adapter,
u8 *PROMContent, BOOLEAN AutoloadFail);
#endif
void rtl8710b_set_hal_ops(struct hal_ops *pHalFunc);
void init_hal_spec_8710b(_adapter *adapter);
u8 SetHwReg8710B(PADAPTER padapter, u8 variable, u8 *val);
void GetHwReg8710B(PADAPTER padapter, u8 variable, u8 *val);
u8 SetHalDefVar8710B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
u8 GetHalDefVar8710B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
/* register */
void rtl8710b_InitBeaconParameters(PADAPTER padapter);
void rtl8710b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
void _8051Reset8710(PADAPTER padapter);
void rtl8710b_start_thread(_adapter *padapter);
void rtl8710b_stop_thread(_adapter *padapter);
#ifdef CONFIG_GPIO_WAKEUP
void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
#endif
void CCX_FwC2HTxRpt_8710b(PADAPTER padapter, u8 *pdata, u8 len);
u8 MRateToHwRate8710B(u8 rate);
u8 HwRateToMRate8710B(u8 rate);
#ifdef CONFIG_USB_HCI
void rtl8710b_cal_txdesc_chksum(struct tx_desc *ptxdesc);
#endif
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8710B_LED_H__
#define __RTL8710B_LED_H__
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#ifdef CONFIG_RTW_SW_LED
/* ********************************************************************************
* Interface to manipulate LED objects.
* ******************************************************************************** */
#ifdef CONFIG_USB_HCI
void rtl8710bu_InitSwLeds(PADAPTER padapter);
void rtl8710bu_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_SDIO_HCI
void rtl8710bs_InitSwLeds(PADAPTER padapter);
void rtl8710bs_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_GSPI_HCI
void rtl8710bs_InitSwLeds(PADAPTER padapter);
void rtl8710bs_DeInitSwLeds(PADAPTER padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8710be_InitSwLeds(PADAPTER padapter);
void rtl8710be_DeInitSwLeds(PADAPTER padapter);
#endif
#endif /*#ifdef CONFIG_RTW_SW_LED*/
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/******************************************** CONST ************************/
#define NUM_OF_REGISTER_BANK 13
#define NUM_OF_TOTAL_DWORD (NUM_OF_REGISTER_BANK * 64)
#define TOTAL_LEN_FOR_HIOE ((NUM_OF_TOTAL_DWORD + 1) * 8)
#define LPS_POFF_STATIC_FILE_LEN (TOTAL_LEN_FOR_HIOE + TXDESC_SIZE)
#define LPS_POFF_DYNAMIC_FILE_LEN (512 + TXDESC_SIZE)
/******************************************** CONST ************************/
/******************************************** MACRO ************************/
/* HOIE Entry Definition */
#define SET_HOIE_ENTRY_LOW_DATA(__pHOIE, __Value) \
SET_BITS_TO_LE_4BYTE((__pHOIE), 0, 16, __Value)
#define SET_HOIE_ENTRY_HIGH_DATA(__pHOIE, __Value) \
SET_BITS_TO_LE_4BYTE((__pHOIE), 16, 16, __Value)
#define SET_HOIE_ENTRY_MODE_SELECT(__pHOIE, __Value) \
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 0, 1, __Value)
#define SET_HOIE_ENTRY_ADDRESS(__pHOIE, __Value) \
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 1, 14, __Value)
#define SET_HOIE_ENTRY_BYTE_MASK(__pHOIE, __Value) \
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 15, 4, __Value)
#define SET_HOIE_ENTRY_IO_LOCK(__pHOIE, __Value) \
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 19, 1, __Value)
#define SET_HOIE_ENTRY_RD_EN(__pHOIE, __Value) \
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 20, 1, __Value)
#define SET_HOIE_ENTRY_WR_EN(__pHOIE, __Value) \
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 21, 1, __Value)
#define SET_HOIE_ENTRY_RAW_RW(__pHOIE, __Value) \
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 22, 1, __Value)
#define SET_HOIE_ENTRY_RAW(__pHOIE, __Value) \
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 23, 1, __Value)
#define SET_HOIE_ENTRY_IO_DELAY(__pHOIE, __Value) \
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 24, 8, __Value)
/*********************Function Definition*******************************************/
void rtl8710b_lps_poff_init(PADAPTER padapter);
void rtl8710b_lps_poff_deinit(PADAPTER padapter);
bool rtl8710b_lps_poff_get_txbndy_status(PADAPTER padapter);
void rtl8710b_lps_poff_h2c_ctrl(PADAPTER padapter, u8 enable);
void rtl8710b_lps_poff_set_ps_mode(PADAPTER padapter, bool bEnterLPS);
bool rtl8710b_lps_poff_get_status(PADAPTER padapter);
void rtl8710b_lps_poff_wow(PADAPTER padapter);

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8710B_RECV_H__
#define __RTL8710B_RECV_H__
#define RECV_BLK_SZ 512
#define RECV_BLK_CNT 16
#define RECV_BLK_TH RECV_BLK_CNT
#if defined(CONFIG_USB_HCI)
#ifndef MAX_RECVBUF_SZ
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */
#else
#ifdef CONFIG_MINIMAL_MEMORY_USAGE
#define MAX_RECVBUF_SZ (4000) /* about 4K */
#else
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) /* 8K */
#elif defined(CONFIG_PLATFORM_HISILICON)
#define MAX_RECVBUF_SZ (16384) /* 16k */
#else
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
#endif
#endif
#endif
#endif /* !MAX_RECVBUF_SZ */
#endif
/* Rx smooth factor */
#define Rx_Smooth_Factor (20)
/*-----------------------------------------------------------------*/
/* RTL8710B RX BUFFER DESC */
/*-----------------------------------------------------------------*/
/*DWORD 0*/
#define SET_RX_BUFFER_DESC_DATA_LENGTH_8710B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
#define SET_RX_BUFFER_DESC_LS_8710B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
#define SET_RX_BUFFER_DESC_FS_8710B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)
#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8710B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)
#define GET_RX_BUFFER_DESC_OWN_8710B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
#define GET_RX_BUFFER_DESC_LS_8710B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
#define GET_RX_BUFFER_DESC_FS_8710B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)
#ifdef USING_RX_TAG
#define GET_RX_BUFFER_DESC_RX_TAG_8710B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13)
#else
#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8710B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
#endif
/*DWORD 1*/
#define SET_RX_BUFFER_PHYSICAL_LOW_8710B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
/*DWORD 2*/
#ifdef CONFIG_64BIT_DMA
#define SET_RX_BUFFER_PHYSICAL_HIGH_8710B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
#else
#define SET_RX_BUFFER_PHYSICAL_HIGH_8710B(__pRxStatusDesc, __Value)
#endif
#ifdef CONFIG_USB_HCI
int rtl8710bu_init_recv_priv(_adapter *padapter);
void rtl8710bu_free_recv_priv(_adapter *padapter);
void rtl8710bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
#endif
void rtl8710b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
#endif /* __RTL8710B_RECV_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8710B_RF_H__
#define __RTL8710B_RF_H__
int PHY_RF6052_Config8710B(IN PADAPTER pdapter);
#endif

481
include/rtl8710b_spec.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8710B_SPEC_H__
#define __RTL8710B_SPEC_H__
#include <drv_conf.h>
#define HAL_NAV_UPPER_UNIT_8710B 128 /* micro-second */
/* -----------------------------------------------------
*
* 0x0000h ~ 0x00FFh System Configuration
*
* ----------------------------------------------------- */
#define REG_SYS_ISO_CTRL_8710B 0x0000 /* 2 Byte */
#define REG_APS_FSMCO_8710B 0x0004 /* 4 Byte */
#define REG_SYS_CLKR_8710B 0x0008 /* 2 Byte */
#define REG_9346CR_8710B 0x000A /* 2 Byte */
#define REG_EE_VPD_8710B 0x000C /* 2 Byte */
#define REG_AFE_MISC_8710B 0x0010 /* 1 Byte */
#define REG_SPS0_CTRL_8710B 0x0011 /* 7 Byte */
#define REG_SPS_OCP_CFG_8710B 0x0018 /* 4 Byte */
#define REG_RSV_CTRL_8710B 0x001C /* 3 Byte */
#define REG_RF_CTRL_8710B 0x001F /* 1 Byte */
#define REG_LPLDO_CTRL_8710B 0x0023 /* 1 Byte */
#define REG_AFE_XTAL_CTRL_8710B 0x0024 /* 4 Byte */
#define REG_AFE_PLL_CTRL_8710B 0x0028 /* 4 Byte */
#define REG_MAC_PLL_CTRL_EXT_8710B 0x002c /* 4 Byte */
#define REG_EFUSE_CTRL_8710B 0x0030
#define REG_EFUSE_TEST_8710B 0x0034
#define REG_PWR_DATA_8710B 0x0038
#define REG_CAL_TIMER_8710B 0x003C
#define REG_ACLK_MON_8710B 0x003E
#define REG_GPIO_MUXCFG_8710B 0x0040
#define REG_GPIO_IO_SEL_8710B 0x0042
#define REG_MAC_PINMUX_CFG_8710B 0x0043
#define REG_GPIO_PIN_CTRL_8710B 0x0044
#define REG_GPIO_INTM_8710B 0x0048
#define REG_LEDCFG0_8710B 0x004C
#define REG_LEDCFG1_8710B 0x004D
#define REG_LEDCFG2_8710B 0x004E
#define REG_LEDCFG3_8710B 0x004F
#define REG_FSIMR_8710B 0x0050
#define REG_FSISR_8710B 0x0054
#define REG_HSIMR_8710B 0x0058
#define REG_HSISR_8710B 0x005c
#define REG_GPIO_EXT_CTRL 0x0060
#define REG_PAD_CTRL1_8710B 0x0064
#define REG_MULTI_FUNC_CTRL_8710B 0x0068
#define REG_GPIO_STATUS_8710B 0x006C
#define REG_SDIO_CTRL_8710B 0x0070
#define REG_OPT_CTRL_8710B 0x0074
#define REG_AFE_CTRL_4_8710B 0x0078
#define REG_MCUFWDL_8710B 0x0080
#define REG_8051FW_CTRL_8710B 0x0080
#define REG_HMEBOX_DBG_0_8710B 0x0088
#define REG_HMEBOX_DBG_1_8710B 0x008A
#define REG_HMEBOX_DBG_2_8710B 0x008C
#define REG_HMEBOX_DBG_3_8710B 0x008E
#define REG_WLLPS_CTRL 0x0090
#define REG_PMC_DBG_CTRL2_8710B 0x00CC
#define REG_EFUSE_BURN_GNT_8710B 0x00CF
#define REG_HPON_FSM_8710B 0x00EC
#define REG_SYS_CFG1_8710B 0x00F0
#define REG_SYS_CFG_8710B 0x00FC
#define REG_ROM_VERSION 0x00FD
/* -----------------------------------------------------
*
* 0x0100h ~ 0x01FFh MACTOP General Configuration
*
* ----------------------------------------------------- */
#define REG_C2HEVT_CMD_ID_8710B 0x01A0
#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1
#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2
#define REG_C2HEVT_CMD_LEN_8710B 0x01AE
#define REG_C2HEVT_CLEAR_8710B 0x01AF
#define REG_MCUTST_1_8710B 0x01C0
#define REG_WOWLAN_WAKE_REASON 0x01C7
#define REG_FMETHR_8710B 0x01C8
#define REG_HMETFR_8710B 0x01CC
#define REG_HMEBOX_0_8710B 0x01D0
#define REG_HMEBOX_1_8710B 0x01D4
#define REG_HMEBOX_2_8710B 0x01D8
#define REG_HMEBOX_3_8710B 0x01DC
#define REG_LLT_INIT_8710B 0x01E0
#define REG_HMEBOX_EXT0_8710B 0x01F0
#define REG_HMEBOX_EXT1_8710B 0x01F4
#define REG_HMEBOX_EXT2_8710B 0x01F8
#define REG_HMEBOX_EXT3_8710B 0x01FC
/* -----------------------------------------------------
*
* 0x0200h ~ 0x027Fh TXDMA Configuration
*
* ----------------------------------------------------- */
#define REG_RQPN_8710B 0x0200
#define REG_FIFOPAGE_8710B 0x0204
#define REG_DWBCN0_CTRL_8710B REG_TDECTRL
#define REG_TXDMA_OFFSET_CHK_8710B 0x020C
#define REG_TXDMA_STATUS_8710B 0x0210
#define REG_RQPN_NPQ_8710B 0x0214
#define REG_DWBCN1_CTRL_8710B 0x0228
/* -----------------------------------------------------
*
* 0x0280h ~ 0x02FFh RXDMA Configuration
*
* ----------------------------------------------------- */
#define REG_RXDMA_AGG_PG_TH_8710B 0x0280
#define REG_FW_UPD_RDPTR_8710B 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
#define REG_RXDMA_CONTROL_8710B 0x0286 /* Control the RX DMA. */
#define REG_RXDMA_STATUS_8710B 0x0288
#define REG_RXDMA_MODE_CTRL_8710B 0x0290
#define REG_EARLY_MODE_CONTROL_8710B 0x02BC
#define REG_RSVD5_8710B 0x02F0
#define REG_RSVD6_8710B 0x02F4
/* -----------------------------------------------------
*
* 0x0300h ~ 0x03FFh PCIe
*
* ----------------------------------------------------- */
#define REG_PCIE_CTRL_REG_8710B 0x0300
#define REG_INT_MIG_8710B 0x0304 /* Interrupt Migration */
#define REG_BCNQ_TXBD_DESA_8710B 0x0308 /* TX Beacon Descriptor Address */
#define REG_MGQ_TXBD_DESA_8710B 0x0310 /* TX Manage Queue Descriptor Address */
#define REG_VOQ_TXBD_DESA_8710B 0x0318 /* TX VO Queue Descriptor Address */
#define REG_VIQ_TXBD_DESA_8710B 0x0320 /* TX VI Queue Descriptor Address */
#define REG_BEQ_TXBD_DESA_8710B 0x0328 /* TX BE Queue Descriptor Address */
#define REG_BKQ_TXBD_DESA_8710B 0x0330 /* TX BK Queue Descriptor Address */
#define REG_RXQ_RXBD_DESA_8710B 0x0338 /* RX Queue Descriptor Address */
#define REG_HI0Q_TXBD_DESA_8710B 0x0340
#define REG_HI1Q_TXBD_DESA_8710B 0x0348
#define REG_HI2Q_TXBD_DESA_8710B 0x0350
#define REG_HI3Q_TXBD_DESA_8710B 0x0358
#define REG_HI4Q_TXBD_DESA_8710B 0x0360
#define REG_HI5Q_TXBD_DESA_8710B 0x0368
#define REG_HI6Q_TXBD_DESA_8710B 0x0370
#define REG_HI7Q_TXBD_DESA_8710B 0x0378
#define REG_MGQ_TXBD_NUM_8710B 0x0380
#define REG_RX_RXBD_NUM_8710B 0x0382
#define REG_VOQ_TXBD_NUM_8710B 0x0384
#define REG_VIQ_TXBD_NUM_8710B 0x0386
#define REG_BEQ_TXBD_NUM_8710B 0x0388
#define REG_BKQ_TXBD_NUM_8710B 0x038A
#define REG_HI0Q_TXBD_NUM_8710B 0x038C
#define REG_HI1Q_TXBD_NUM_8710B 0x038E
#define REG_HI2Q_TXBD_NUM_8710B 0x0390
#define REG_HI3Q_TXBD_NUM_8710B 0x0392
#define REG_HI4Q_TXBD_NUM_8710B 0x0394
#define REG_HI5Q_TXBD_NUM_8710B 0x0396
#define REG_HI6Q_TXBD_NUM_8710B 0x0398
#define REG_HI7Q_TXBD_NUM_8710B 0x039A
#define REG_TSFTIMER_HCI_8710B 0x039C
#define REG_BD_RW_PTR_CLR_8710B 0x039C
/* Read Write Point */
#define REG_VOQ_TXBD_IDX_8710B 0x03A0
#define REG_VIQ_TXBD_IDX_8710B 0x03A4
#define REG_BEQ_TXBD_IDX_8710B 0x03A8
#define REG_BKQ_TXBD_IDX_8710B 0x03AC
#define REG_MGQ_TXBD_IDX_8710B 0x03B0
#define REG_RXQ_TXBD_IDX_8710B 0x03B4
#define REG_HI0Q_TXBD_IDX_8710B 0x03B8
#define REG_HI1Q_TXBD_IDX_8710B 0x03BC
#define REG_HI2Q_TXBD_IDX_8710B 0x03C0
#define REG_HI3Q_TXBD_IDX_8710B 0x03C4
#define REG_HI4Q_TXBD_IDX_8710B 0x03C8
#define REG_HI5Q_TXBD_IDX_8710B 0x03CC
#define REG_HI6Q_TXBD_IDX_8710B 0x03D0
#define REG_HI7Q_TXBD_IDX_8710B 0x03D4
#define REG_PCIE_HCPWM_8710BE 0x03D8 /* ?????? */
#define REG_PCIE_HRPWM_8710BE 0x03DC /* PCIe RPWM ?????? */
#define REG_DBI_WDATA_V1_8710B 0x03E8
#define REG_DBI_RDATA_V1_8710B 0x03EC
#define REG_DBI_FLAG_V1_8710B 0x03F0
#define REG_MDIO_V1_8710B 0x03F4
#define REG_PCIE_MIX_CFG_8710B 0x03F8
#define REG_HCI_MIX_CFG_8710B 0x03FC
/* -----------------------------------------------------
*
* 0x0400h ~ 0x047Fh Protocol Configuration
*
* ----------------------------------------------------- */
#define REG_VOQ_INFORMATION_8710B 0x0400
#define REG_VIQ_INFORMATION_8710B 0x0404
#define REG_BEQ_INFORMATION_8710B 0x0408
#define REG_BKQ_INFORMATION_8710B 0x040C
#define REG_MGQ_INFORMATION_8710B 0x0410
#define REG_HGQ_INFORMATION_8710B 0x0414
#define REG_BCNQ_INFORMATION_8710B 0x0418
#define REG_TXPKT_EMPTY_8710B 0x041A
#define REG_FWHW_TXQ_CTRL_8710B 0x0420
#define REG_HWSEQ_CTRL_8710B 0x0423
#define REG_TXPKTBUF_BCNQ_BDNY_8710B 0x0424
#define REG_TXPKTBUF_MGQ_BDNY_8710B 0x0425
#define REG_LIFECTRL_CTRL_8710B 0x0426
#define REG_MULTI_BCNQ_OFFSET_8710B 0x0427
#define REG_SPEC_SIFS_8710B 0x0428
#define REG_RL_8710B 0x042A
#define REG_TXBF_CTRL_8710B 0x042C
#define REG_DARFRC_8710B 0x0430
#define REG_RARFRC_8710B 0x0438
#define REG_RRSR_8710B 0x0440
#define REG_ARFR0_8710B 0x0444
#define REG_ARFR1_8710B 0x044C
#define REG_CCK_CHECK_8710B 0x0454
#define REG_AMPDU_MAX_TIME_8710B 0x0456
#define REG_TXPKTBUF_BCNQ_BDNY1_8710B 0x0457
#define REG_AMPDU_MAX_LENGTH_8710B 0x0458
#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8710B 0x045D
#define REG_NDPA_OPT_CTRL_8710B 0x045F
#define REG_FAST_EDCA_CTRL_8710B 0x0460
#define REG_RD_RESP_PKT_TH_8710B 0x0463
#define REG_DATA_SC_8710B 0x0483
#ifdef CONFIG_WOWLAN
#define REG_TXPKTBUF_IV_LOW 0x0484
#define REG_TXPKTBUF_IV_HIGH 0x0488
#endif
#define REG_TXRPT_START_OFFSET 0x04AC
#define REG_POWER_STAGE1_8710B 0x04B4
#define REG_POWER_STAGE2_8710B 0x04B8
#define REG_AMPDU_BURST_MODE_8710B 0x04BC
#define REG_PKT_VO_VI_LIFE_TIME_8710B 0x04C0
#define REG_PKT_BE_BK_LIFE_TIME_8710B 0x04C2
#define REG_STBC_SETTING_8710B 0x04C4
#define REG_HT_SINGLE_AMPDU_8710B 0x04C7
#define REG_PROT_MODE_CTRL_8710B 0x04C8
#define REG_MAX_AGGR_NUM_8710B 0x04CA
#define REG_RTS_MAX_AGGR_NUM_8710B 0x04CB
#define REG_BAR_MODE_CTRL_8710B 0x04CC
#define REG_RA_TRY_RATE_AGG_LMT_8710B 0x04CF
#define REG_MACID_PKT_DROP0_8710B 0x04D0
#define REG_MACID_PKT_SLEEP_8710B 0x04D4
/* -----------------------------------------------------
*
* 0x0500h ~ 0x05FFh EDCA Configuration
*
* ----------------------------------------------------- */
#define REG_EDCA_VO_PARAM_8710B 0x0500
#define REG_EDCA_VI_PARAM_8710B 0x0504
#define REG_EDCA_BE_PARAM_8710B 0x0508
#define REG_EDCA_BK_PARAM_8710B 0x050C
#define REG_BCNTCFG_8710B 0x0510
#define REG_PIFS_8710B 0x0512
#define REG_RDG_PIFS_8710B 0x0513
#define REG_SIFS_CTX_8710B 0x0514
#define REG_SIFS_TRX_8710B 0x0516
#define REG_AGGR_BREAK_TIME_8710B 0x051A
#define REG_SLOT_8710B 0x051B
#define REG_TX_PTCL_CTRL_8710B 0x0520
#define REG_TXPAUSE_8710B 0x0522
#define REG_DIS_TXREQ_CLR_8710B 0x0523
#define REG_RD_CTRL_8710B 0x0524
/*
* Format for offset 540h-542h:
* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
* [7:4]: Reserved.
* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
* [23:20]: Reserved
* Description:
* |
* |<--Setup--|--Hold------------>|
* --------------|----------------------
* |
* TBTT
* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
* Described by Designer Tim and Bruce, 2011-01-14.
* */
#define REG_TBTT_PROHIBIT_8710B 0x0540
#define REG_RD_NAV_NXT_8710B 0x0544
#define REG_NAV_PROT_LEN_8710B 0x0546
#define REG_BCN_CTRL_8710B 0x0550
#define REG_BCN_CTRL_1_8710B 0x0551
#define REG_MBID_NUM_8710B 0x0552
#define REG_DUAL_TSF_RST_8710B 0x0553
#define REG_BCN_INTERVAL_8710B 0x0554
#define REG_DRVERLYINT_8710B 0x0558
#define REG_BCNDMATIM_8710B 0x0559
#define REG_ATIMWND_8710B 0x055A
#define REG_USTIME_TSF_8710B 0x055C
#define REG_BCN_MAX_ERR_8710B 0x055D
#define REG_RXTSF_OFFSET_CCK_8710B 0x055E
#define REG_RXTSF_OFFSET_OFDM_8710B 0x055F
#define REG_TSFTR_8710B 0x0560
#define REG_CTWND_8710B 0x0572
#define REG_SECONDARY_CCA_CTRL_8710B 0x0577
#define REG_PSTIMER_8710B 0x0580
#define REG_TIMER0_8710B 0x0584
#define REG_TIMER1_8710B 0x0588
#define REG_ACMHWCTRL_8710B 0x05C0
#define REG_SCH_TXCMD_8710B 0x05F8
/* -----------------------------------------------------
*
* 0x0600h ~ 0x07FFh WMAC Configuration
*
* ----------------------------------------------------- */
#define REG_MAC_CR_8710B 0x0600
#define REG_TCR_8710B 0x0604
#define REG_RCR_8710B 0x0608
#define REG_RX_PKT_LIMIT_8710B 0x060C
#define REG_RX_DLK_TIME_8710B 0x060D
#define REG_RX_DRVINFO_SZ_8710B 0x060F
#define REG_MACID_8710B 0x0610
#define REG_BSSID_8710B 0x0618
#define REG_MAR_8710B 0x0620
#define REG_MBIDCAMCFG_8710B 0x0628
#define REG_WOWLAN_GTK_DBG1 0x630
#define REG_WOWLAN_GTK_DBG2 0x634
#define REG_USTIME_EDCA_8710B 0x0638
#define REG_MAC_SPEC_SIFS_8710B 0x063A
#define REG_RESP_SIFP_CCK_8710B 0x063C
#define REG_RESP_SIFS_OFDM_8710B 0x063E
#define REG_ACKTO_8710B 0x0640
#define REG_CTS2TO_8710B 0x0641
#define REG_EIFS_8710B 0x0642
#define REG_NAV_UPPER_8710B 0x0652 /* unit of 128 */
#define REG_TRXPTCL_CTL_8710B 0x0668
/* Security */
#define REG_CAMCMD_8710B 0x0670
#define REG_CAMWRITE_8710B 0x0674
#define REG_CAMREAD_8710B 0x0678
#define REG_CAMDBG_8710B 0x067C
#define REG_SECCFG_8710B 0x0680
/* Power */
#define REG_WOW_CTRL_8710B 0x0690
#define REG_PS_RX_INFO_8710B 0x0692
#define REG_UAPSD_TID_8710B 0x0693
#define REG_WKFMCAM_CMD_8710B 0x0698
#define REG_WKFMCAM_NUM_8710B 0x0698
#define REG_WKFMCAM_RWD_8710B 0x069C
#define REG_RXFLTMAP0_8710B 0x06A0
#define REG_RXFLTMAP1_8710B 0x06A2
#define REG_RXFLTMAP2_8710B 0x06A4
#define REG_BCN_PSR_RPT_8710B 0x06A8
#define REG_BT_COEX_TABLE_8710B 0x06C0
#define REG_BFMER0_INFO_8710B 0x06E4
#define REG_BFMER1_INFO_8710B 0x06EC
#define REG_CSI_RPT_PARAM_BW20_8710B 0x06F4
#define REG_CSI_RPT_PARAM_BW40_8710B 0x06F8
#define REG_CSI_RPT_PARAM_BW80_8710B 0x06FC
/* Hardware Port 2 */
#define REG_MACID1_8710B 0x0700
#define REG_BSSID1_8710B 0x0708
#define REG_BFMEE_SEL_8710B 0x0714
#define REG_SND_PTCL_CTRL_8710B 0x0718
/* LTR */
#define REG_LTR_CTRL_BASIC_8710B 0x07A4
#define REG_LTR_IDLE_LATENCY_V1_8710B 0x0798
#define REG_LTR_ACTIVE_LATENCY_V1_8710B 0x079C
/* LTE_COEX */
#define REG_LTECOEX_CTRL 0x07C0
#define REG_LTECOEX_WRITE_DATA 0x07C4
#define REG_LTECOEX_READ_DATA 0x07C8
#define REG_LTECOEX_PATH_CONTROL 0x70
/* Other */
#define REG_USB_ACCESS_TIMEOUT 0xFE4C
/* -----------------------------------------------------
* SYSON_REG_SPEC
* ----------------------------------------------------- */
#define SYSON_REG_BASE_ADDR_8710B 0x40000000
#define REG_SYS_XTAL_CTRL0 0x0060
#define REG_SYS_SYSTEM_CFG0 0x1F0
#define REG_SYS_SYSTEM_CFG1 0x1F4
#define REG_SYS_SYSTEM_CFG2 0x1F8
#define REG_SYS_EEPROM_CTRL0 0x0E0
/* -----------------------------------------------------
* Indirect_R/W_SPEC
* ----------------------------------------------------- */
#define NORMAL_REG_READ_OFFSET 0x83000000
#define NORMAL_REG_WRITE_OFFSET 0x84000000
#define EFUSE_READ_OFFSET 0x85000000
#define EFUSE_WRITE_OFFSET 0x86000000
/* -----------------------------------------------------
* PAGE0_WLANON_REG_SPEC
* ----------------------------------------------------- */
#define PAGE0_OFFSET 0x0 // WLANON_PAGE0_REG needs to add an offset.
/* ****************************************************************************
* 8723 Regsiter Bit and Content definition
* **************************************************************************** */
/* -----------------------------------------------------
* REG_SYS_SYSTEM_CFG0
* ----------------------------------------------------- */
#define BIT_RTL_ID_8710B BIT(16)
#define BIT_MASK_CHIP_VER_8710B 0xf
#define BIT_GET_CHIP_VER_8710B(x) ((x) & BIT_MASK_CHIP_VER_8710B)
#define BIT_SHIFT_VENDOR_ID_8710B 4
#define BIT_MASK_VENDOR_ID_8710B 0xf
#define BIT_GET_VENDOR_ID_8710B(x) (((x) >> BIT_SHIFT_VENDOR_ID_8710B) & BIT_MASK_VENDOR_ID_8710B)
/* -----------------------------------------------------
* REG_SYS_SYSTEM_CFG1
* ----------------------------------------------------- */
#define BIT_SPSLDO_SEL_8710B BIT(25)
/* -----------------------------------------------------
* REG_SYS_SYSTEM_CFG2
* ----------------------------------------------------- */
#define BIT_MASK_RF_RL_ID_8710B 0xf
#define BIT_GET_RF_RL_ID_8710B(x) ((x) & BIT_MASK_RF_RL_ID_8710B)
/* -----------------------------------------------------
* REG_SYS_SYSTEM_CFG2
* ----------------------------------------------------- */
#define BIT_EERPOMSEL_8710B BIT(4)
#define BIT_AUTOLOAD_SUS_8710B BIT(5)
/* -----------------------------------------------------
* Other
* ----------------------------------------------------- */
#define BIT_USB_RXDMA_AGG_EN BIT(31)
#define RXDMA_AGG_MODE_EN BIT(1)
#ifdef CONFIG_WOWLAN
#define RXPKT_RELEASE_POLL BIT(16)
#define RXDMA_IDLE BIT(17)
#define RW_RELEASE_EN BIT(18)
#endif
/* 2 HSISR
* interrupt mask which needs to clear */
#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\
HSISR_SPS_OCP_INT |\
HSISR_RON_INT |\
HSISR_PDNINT |\
HSISR_GPIO9_INT)
#ifdef CONFIG_RF_POWER_TRIM
#ifdef CONFIG_RTL8710B
#define EEPROM_RF_GAIN_OFFSET 0xC1
#endif
#define EEPROM_RF_GAIN_VAL 0x1F6
#endif /*CONFIG_RF_POWER_TRIM*/
#endif /* __RTL8710B_SPEC_H__ */

24
include/rtl8710b_sreset.h Normal file
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@@ -0,0 +1,24 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef _RTL8710B_SRESET_H_
#define _RTL8710B_SRESET_H_
#include <rtw_sreset.h>
#ifdef DBG_CONFIG_ERROR_DETECT
extern void rtl8710b_sreset_xmit_status_check(_adapter *padapter);
extern void rtl8710b_sreset_linked_status_check(_adapter *padapter);
#endif
#endif

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include/rtl8710b_xmit.h Normal file
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@@ -0,0 +1,522 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __RTL8710B_XMIT_H__
#define __RTL8710B_XMIT_H__
#define MAX_TID (15)
#ifndef __INC_HAL8710BDESC_H
#define __INC_HAL8710BDESC_H
#define RX_STATUS_DESC_SIZE_8710B 24
#define RX_DRV_INFO_SIZE_UNIT_8710B 8
/* DWORD 0 */
#define SET_RX_STATUS_DESC_PKT_LEN_8710B(__pRxStatusDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
#define SET_RX_STATUS_DESC_EOR_8710B(__pRxStatusDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
#define SET_RX_STATUS_DESC_OWN_8710B(__pRxStatusDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
#define GET_RX_STATUS_DESC_PKT_LEN_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
#define GET_RX_STATUS_DESC_CRC32_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
#define GET_RX_STATUS_DESC_ICV_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
#define GET_RX_STATUS_DESC_SECURITY_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
#define GET_RX_STATUS_DESC_QOS_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
#define GET_RX_STATUS_DESC_SHIFT_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
#define GET_RX_STATUS_DESC_PHY_STATUS_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
#define GET_RX_STATUS_DESC_SWDEC_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
#define GET_RX_STATUS_DESC_EOR_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
#define GET_RX_STATUS_DESC_OWN_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
/* DWORD 1 */
#define GET_RX_STATUS_DESC_MACID_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
#define GET_RX_STATUS_DESC_TID_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
#define GET_RX_STATUS_DESC_AMSDU_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
#define GET_RX_STATUS_DESC_RXID_MATCH_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
#define GET_RX_STATUS_DESC_PAGGR_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
#define GET_RX_STATUS_DESC_A1_FIT_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
#define GET_RX_STATUS_DESC_CHKERR_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
#define GET_RX_STATUS_DESC_IPVER_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
#define GET_RX_STATUS_DESC_IS_TCPUDP__8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
#define GET_RX_STATUS_DESC_CHK_VLD_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
#define GET_RX_STATUS_DESC_PAM_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
#define GET_RX_STATUS_DESC_PWR_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
#define GET_RX_STATUS_DESC_MORE_DATA_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
#define GET_RX_STATUS_DESC_MORE_FRAG_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
#define GET_RX_STATUS_DESC_TYPE_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
#define GET_RX_STATUS_DESC_MC_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
#define GET_RX_STATUS_DESC_BC_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
/* DWORD 2 */
#define GET_RX_STATUS_DESC_SEQ_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
#define GET_RX_STATUS_DESC_FRAG_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
#define GET_RX_STATUS_DESC_RX_IS_QOS_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
#define GET_RX_STATUS_DESC_RPT_SEL_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
#define GET_RX_STATUS_DESC_FCS_OK_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
/* DWORD 3 */
#define GET_RX_STATUS_DESC_RX_RATE_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
#define GET_RX_STATUS_DESC_HTC_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
#define GET_RX_STATUS_DESC_EOSP_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
#define GET_RX_STATUS_DESC_BSSID_FIT_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
#ifdef CONFIG_USB_RX_AGGREGATION
#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
#endif
#define GET_RX_STATUS_DESC_PATTERN_MATCH_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
#define GET_RX_STATUS_DESC_UNICAST_MATCH_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
#define GET_RX_STATUS_DESC_MAGIC_MATCH_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
/* DWORD 6 */
#define GET_RX_STATUS_DESC_MATCH_ID_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7)
/* DWORD 5 */
#define GET_RX_STATUS_DESC_TSFL_8710B(__pRxStatusDesc) \
LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
#define GET_RX_STATUS_DESC_BUFF_ADDR_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
#define GET_RX_STATUS_DESC_BUFF_ADDR64_8710B(__pRxDesc) \
LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
#define SET_RX_STATUS_DESC_BUFF_ADDR_8710B(__pRxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
/* Dword 0, rsvd: bit26, bit28 */
#define GET_TX_DESC_OWN_8710B(__pTxDesc)\
LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
#define SET_TX_DESC_PKT_SIZE_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
#define SET_TX_DESC_OFFSET_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
#define SET_TX_DESC_BMC_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
#define SET_TX_DESC_HTC_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
#define SET_TX_DESC_AMSDU_PAD_EN_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
#define SET_TX_DESC_NO_ACM_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
#define SET_TX_DESC_GF_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
/* Dword 1 */
#define SET_TX_DESC_MACID_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
#define SET_TX_DESC_QUEUE_SEL_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
#define SET_TX_DESC_RDG_NAV_EXT_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
#define SET_TX_DESC_LSIG_TXOP_EN_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
#define SET_TX_DESC_PIFS_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
#define SET_TX_DESC_RATE_ID_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
#define SET_TX_DESC_EN_DESC_ID_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
#define SET_TX_DESC_SEC_TYPE_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
#define SET_TX_DESC_PKT_OFFSET_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
#define SET_TX_DESC_MORE_DATA_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
/* Dword 2 remove P_AID, G_ID field*/
#define SET_TX_DESC_CCA_RTS_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
#define SET_TX_DESC_AGG_ENABLE_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
#define SET_TX_DESC_RDG_ENABLE_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
#define SET_TX_DESC_NULL0_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
#define SET_TX_DESC_NULL1_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
#define SET_TX_DESC_BK_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
#define SET_TX_DESC_MORE_FRAG_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
#define SET_TX_DESC_RAW_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
#define SET_TX_DESC_CCX_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
#define SET_TX_DESC_AMPDU_DENSITY_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
#define SET_TX_DESC_BT_INT_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
#define SET_TX_DESC_FTM_EN_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 30, 1, __Value)
/* Dword 3 */
#define SET_TX_DESC_NAV_USE_HDR_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
#define SET_TX_DESC_HWSEQ_SEL_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
#define SET_TX_DESC_USE_RATE_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
#define SET_TX_DESC_DISABLE_RTS_FB_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
#define SET_TX_DESC_DISABLE_FB_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
#define SET_TX_DESC_CTS2SELF_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
#define SET_TX_DESC_RTS_ENABLE_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
#define SET_TX_DESC_HW_RTS_ENABLE_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
#define SET_TX_DESC_PORT_ID_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 2, __Value)
#define SET_TX_DESC_USE_MAX_LEN_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
#define SET_TX_DESC_MAX_AGG_NUM_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
#define SET_TX_DESC_AMPDU_MAX_TIME_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
/* Dword 4 */
#define SET_TX_DESC_TX_RATE_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
#define SET_TX_DESC_TX_TRY_RATE_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
#define SET_TX_DESC_DATA_RETRY_LIMIT_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
#define SET_TX_DESC_RTS_RATE_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
#define SET_TX_DESC_PCTS_EN_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
#define SET_TX_DESC_PCTS_MASK_IDX_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
/* Dword 5 */
#define SET_TX_DESC_DATA_SC_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
#define SET_TX_DESC_DATA_SHORT_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
#define SET_TX_DESC_DATA_BW_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
#define SET_TX_DESC_DATA_STBC_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
#define SET_TX_DESC_RTS_STBC_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
#define SET_TX_DESC_RTS_SHORT_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
#define SET_TX_DESC_RTS_SC_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
#define SET_TX_DESC_PATH_A_EN_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value)
#define SET_TX_DESC_TXPWR_OF_SET_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
/* Dword 6 */
#define SET_TX_DESC_SW_DEFINE_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
#define SET_TX_DESC_MBSSID_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
#define SET_TX_DESC_RF_SEL_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
/* Dword 7 */
#ifdef CONFIG_PCI_HCI
#define SET_TX_DESC_TX_BUFFER_SIZE_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#endif
#ifdef CONFIG_USB_HCI
#define SET_TX_DESC_TX_DESC_CHECKSUM_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#endif
#ifdef CONFIG_SDIO_HCI
#define SET_TX_DESC_TX_TIMESTAMP_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value)
#endif
#define SET_TX_DESC_USB_TXAGG_NUM_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
/* Dword 8 */
#define SET_TX_DESC_RTS_RC_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
#define SET_TX_DESC_BAR_RC_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
#define SET_TX_DESC_DATA_RC_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
#define SET_TX_DESC_HWSEQ_EN_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
#define SET_TX_DESC_NEXTHEADPAGE_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
#define SET_TX_DESC_TAILPAGE_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
/* Dword 9 */
#define SET_TX_DESC_PADDING_LEN_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
#define SET_TX_DESC_SEQ_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
#define SET_TX_DESC_FINAL_DATA_RATE_8710B(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)
#define SET_EARLYMODE_PKTNUM_8710B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
#define SET_EARLYMODE_LEN0_8710B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
#define SET_EARLYMODE_LEN1_1_8710B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
#define SET_EARLYMODE_LEN1_2_8710B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
#define SET_EARLYMODE_LEN2_8710B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value)
#define SET_EARLYMODE_LEN3_8710B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
/*-----------------------------------------------------------------*/
/* RTL8710B TX BUFFER DESC */
/*-----------------------------------------------------------------*/
#ifdef CONFIG_64BIT_DMA
#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)
#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)
#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)
#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)
#else
#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) /* 64 BIT mode only */
#endif
/* ********************************************************* */
/* 64 bits -- 32 bits */
/* ======= ======= */
/* Dword 0 0 */
#define SET_TX_BUFF_DESC_LEN_0_8710B(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)
#define SET_TX_BUFF_DESC_PSB_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
#define SET_TX_BUFF_DESC_OWN_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
/* Dword 1 1 */
#define SET_TX_BUFF_DESC_ADDR_LOW_0_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
#define GET_TX_BUFF_DESC_ADDR_LOW_0_8710B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
/* Dword 2 NA */
#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value)
#ifdef CONFIG_64BIT_DMA
#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)
#else
#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc) 0
#endif
/* Dword 3 NA */
/* RESERVED 0 */
/* Dword 4 2 */
#define SET_TX_BUFF_DESC_LEN_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value)
#define SET_TX_BUFF_DESC_AMSDU_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value)
/* Dword 5 3 */
#define SET_TX_BUFF_DESC_ADDR_LOW_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value)
/* Dword 6 NA */
#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value)
/* Dword 7 NA */
/*RESERVED 0 */
/* Dword 8 4 */
#define SET_TX_BUFF_DESC_LEN_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value)
#define SET_TX_BUFF_DESC_AMSDU_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value)
/* Dword 9 5 */
#define SET_TX_BUFF_DESC_ADDR_LOW_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value)
/* Dword 10 NA */
#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value)
/* Dword 11 NA */
/*RESERVED 0 */
/* Dword 12 6 */
#define SET_TX_BUFF_DESC_LEN_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value)
#define SET_TX_BUFF_DESC_AMSDU_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value)
/* Dword 13 7 */
#define SET_TX_BUFF_DESC_ADDR_LOW_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value)
/* Dword 14 NA */
#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value)
/* Dword 15 NA */
/*RESERVED 0 */
#endif
/* -----------------------------------------------------------
*
* Rate
*
* -----------------------------------------------------------
* CCK Rates, TxHT = 0 */
#define DESC8710B_RATE1M 0x00
#define DESC8710B_RATE2M 0x01
#define DESC8710B_RATE5_5M 0x02
#define DESC8710B_RATE11M 0x03
/* OFDM Rates, TxHT = 0 */
#define DESC8710B_RATE6M 0x04
#define DESC8710B_RATE9M 0x05
#define DESC8710B_RATE12M 0x06
#define DESC8710B_RATE18M 0x07
#define DESC8710B_RATE24M 0x08
#define DESC8710B_RATE36M 0x09
#define DESC8710B_RATE48M 0x0a
#define DESC8710B_RATE54M 0x0b
/* MCS Rates, TxHT = 1 */
#define DESC8710B_RATEMCS0 0x0c
#define DESC8710B_RATEMCS1 0x0d
#define DESC8710B_RATEMCS2 0x0e
#define DESC8710B_RATEMCS3 0x0f
#define DESC8710B_RATEMCS4 0x10
#define DESC8710B_RATEMCS5 0x11
#define DESC8710B_RATEMCS6 0x12
#define DESC8710B_RATEMCS7 0x13
#define DESC8710B_RATEMCS8 0x14
#define DESC8710B_RATEMCS9 0x15
#define DESC8710B_RATEMCS10 0x16
#define DESC8710B_RATEMCS11 0x17
#define DESC8710B_RATEMCS12 0x18
#define DESC8710B_RATEMCS13 0x19
#define DESC8710B_RATEMCS14 0x1a
#define DESC8710B_RATEMCS15 0x1b
#define DESC8710B_RATEVHTSS1MCS0 0x2c
#define DESC8710B_RATEVHTSS1MCS1 0x2d
#define DESC8710B_RATEVHTSS1MCS2 0x2e
#define DESC8710B_RATEVHTSS1MCS3 0x2f
#define DESC8710B_RATEVHTSS1MCS4 0x30
#define DESC8710B_RATEVHTSS1MCS5 0x31
#define DESC8710B_RATEVHTSS1MCS6 0x32
#define DESC8710B_RATEVHTSS1MCS7 0x33
#define DESC8710B_RATEVHTSS1MCS8 0x34
#define DESC8710B_RATEVHTSS1MCS9 0x35
#define DESC8710B_RATEVHTSS2MCS0 0x36
#define DESC8710B_RATEVHTSS2MCS1 0x37
#define DESC8710B_RATEVHTSS2MCS2 0x38
#define DESC8710B_RATEVHTSS2MCS3 0x39
#define DESC8710B_RATEVHTSS2MCS4 0x3a
#define DESC8710B_RATEVHTSS2MCS5 0x3b
#define DESC8710B_RATEVHTSS2MCS6 0x3c
#define DESC8710B_RATEVHTSS2MCS7 0x3d
#define DESC8710B_RATEVHTSS2MCS8 0x3e
#define DESC8710B_RATEVHTSS2MCS9 0x3f
#define RX_HAL_IS_CCK_RATE_8710B(pDesc)\
(GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE1M || \
GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE2M || \
GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE5_5M || \
GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE11M)
#ifdef CONFIG_TRX_BD_ARCH
struct tx_desc;
#endif
void rtl8710b_cal_txdesc_chksum(struct tx_desc *ptxdesc);
void rtl8710b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
void rtl8710b_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
void rtl8710b_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
void rtl8710b_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
void rtl8710b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
#if defined(CONFIG_CONCURRENT_MODE)
void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
#endif
void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
s32 rtl8710bs_init_xmit_priv(PADAPTER padapter);
void rtl8710bs_free_xmit_priv(PADAPTER padapter);
s32 rtl8710bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8710bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
s32 rtl8710bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8710bs_xmit_buf_handler(PADAPTER padapter);
thread_return rtl8710bs_xmit_thread(thread_context context);
#define hal_xmit_handler rtl8710bs_xmit_buf_handler
#endif
#ifdef CONFIG_USB_HCI
s32 rtl8710bu_xmit_buf_handler(PADAPTER padapter);
#define hal_xmit_handler rtl8710bu_xmit_buf_handler
s32 rtl8710bu_init_xmit_priv(PADAPTER padapter);
void rtl8710bu_free_xmit_priv(PADAPTER padapter);
s32 rtl8710bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8710bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
s32 rtl8710bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
void rtl8710bu_xmit_tasklet(void *priv);
s32 rtl8710bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, struct tx_desc *ptxdesc);
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8710be_init_xmit_priv(PADAPTER padapter);
void rtl8710be_free_xmit_priv(PADAPTER padapter);
struct xmit_buf *rtl8710be_dequeue_xmitbuf(struct rtw_tx_ring *ring);
void rtl8710be_xmitframe_resume(_adapter *padapter);
s32 rtl8710be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
s32 rtl8710be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
s32 rtl8710be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
void rtl8710be_xmit_tasklet(void *priv);
#endif
u8 BWMapping_8710B(PADAPTER Adapter, struct pkt_attrib *pattrib);
u8 SCMapping_8710B(PADAPTER Adapter, struct pkt_attrib *pattrib);
#endif

2
include/rtl8723b_cmd.h
View File

@@ -113,7 +113,6 @@ enum h2c_cmd_8723B {
#define SET_8723B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
#define GET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
@@ -177,7 +176,6 @@ enum h2c_cmd_8723B {
/* host message to firmware cmd */
void rtl8723b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
void rtl8723b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
void rtl8723b_set_rssi_cmd(PADAPTER padapter, u8 *param);
void rtl8723b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
/* s32 rtl8723b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
void rtl8723b_set_FwPsTuneParam_cmd(PADAPTER padapter);

16
include/rtl8723b_hal.h
View File

@@ -106,18 +106,10 @@ typedef struct _RT_8723B_FIRMWARE_HDR {
/* Note: We will divide number of page equally for each queue other than public queue! */
/* For General Reserved Page Number(Beacon Queue is reserved page)
* Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1 */
#define BCNQ_PAGE_NUM_8723B 0x08
#ifdef CONFIG_CONCURRENT_MODE
#define BCNQ1_PAGE_NUM_8723B 0x08 /* 0x04 */
#else
#define BCNQ1_PAGE_NUM_8723B 0x00
#endif
* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8723B
* PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
#define BCNQ_PAGE_NUM_8723B (MAX_BEACON_LEN / PAGE_SIZE_TX_8723B + 6) /*0x08*/
#ifdef CONFIG_PNO_SUPPORT
#undef BCNQ1_PAGE_NUM_8723B
#define BCNQ1_PAGE_NUM_8723B 0x00 /* 0x04 */
#endif
/* For WoWLan , more reserved page
* ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6
@@ -138,7 +130,7 @@ typedef struct _RT_8723B_FIRMWARE_HDR {
#define AP_WOWLAN_PAGE_NUM_8723B 0x02
#endif
#define TX_TOTAL_PAGE_NUMBER_8723B (0xFF - BCNQ_PAGE_NUM_8723B - BCNQ1_PAGE_NUM_8723B - WOWLAN_PAGE_NUM_8723B)
#define TX_TOTAL_PAGE_NUMBER_8723B (0xFF - BCNQ_PAGE_NUM_8723B - WOWLAN_PAGE_NUM_8723B)
#define TX_PAGE_BOUNDARY_8723B (TX_TOTAL_PAGE_NUMBER_8723B + 1)
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723B TX_TOTAL_PAGE_NUMBER_8723B

7
include/rtl8723b_xmit.h
View File

@@ -184,13 +184,14 @@
#define SET_TX_DESC_ANTSEL_D_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
/* Dword 7 */
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
#ifdef CONFIG_PCI_HCI
#define SET_TX_DESC_TX_BUFFER_SIZE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#else
#endif
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
#define SET_TX_DESC_TX_DESC_CHECKSUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#endif
#define SET_TX_DESC_USB_TXAGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
#if (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
#ifdef CONFIG_SDIO_HCI
#define SET_TX_DESC_SDIO_TXSEQ_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
#endif

1
include/rtl8723d_cmd.h
View File

@@ -101,7 +101,6 @@ enum h2c_cmd_8723D {
#define SET_8723D_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8723D_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
#define SET_8723D_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8723D_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
#define GET_8723D_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)

18
include/rtl8723d_hal.h
View File

@@ -111,18 +111,10 @@ typedef struct _RT_8723D_FIRMWARE_HDR {
/* Note: We will divide number of page equally for each queue other than public queue! */
/* For General Reserved Page Number(Beacon Queue is reserved page)
* Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1 */
#define BCNQ_PAGE_NUM_8723D 0x08
#ifdef CONFIG_CONCURRENT_MODE
#define BCNQ1_PAGE_NUM_8723D 0x08 /* 0x04 */
#else
#define BCNQ1_PAGE_NUM_8723D 0x00
#endif
* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8723D
* PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
#ifdef CONFIG_PNO_SUPPORT
#undef BCNQ1_PAGE_NUM_8723D
#define BCNQ1_PAGE_NUM_8723D 0x00 /* 0x04 */
#endif
#define BCNQ_PAGE_NUM_8723D (MAX_BEACON_LEN/PAGE_SIZE_TX_8723D + 6) /*0x08*/
/* For WoWLan , more reserved page
* ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6
@@ -144,7 +136,7 @@ typedef struct _RT_8723D_FIRMWARE_HDR {
#endif
#define TX_TOTAL_PAGE_NUMBER_8723D\
(0xFF - BCNQ_PAGE_NUM_8723D - BCNQ1_PAGE_NUM_8723D - WOWLAN_PAGE_NUM_8723D)
(0xFF - BCNQ_PAGE_NUM_8723D - WOWLAN_PAGE_NUM_8723D)
#define TX_PAGE_BOUNDARY_8723D (TX_TOTAL_PAGE_NUMBER_8723D + 1)
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723D TX_TOTAL_PAGE_NUMBER_8723D
@@ -240,8 +232,6 @@ void Hal_EfuseParseBTCoexistInfo_8723D(PADAPTER padapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseEEPROMVer_8723D(PADAPTER padapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParsePackageType_8723D(PADAPTER pAdapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseChnlPlan_8723D(PADAPTER padapter,
u8 *hwinfo, BOOLEAN AutoLoadFail);
void Hal_EfuseParseCustomerID_8723D(PADAPTER padapter,

10
include/rtl8723d_xmit.h
View File

@@ -286,13 +286,17 @@
SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
/* Dword 7 */
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
#ifdef CONFIG_PCI_HCI
#define SET_TX_DESC_TX_BUFFER_SIZE_8723D(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#elif(DEV_BUS_TYPE == RT_USB_INTERFACE)
#endif
#ifdef CONFIG_USB_HCI
#define SET_TX_DESC_TX_DESC_CHECKSUM_8723D(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#else
#endif
#ifdef CONFIG_SDIO_HCI
#define SET_TX_DESC_TX_TIMESTAMP_8723D(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value)
#endif

1
include/rtl8812a_cmd.h
View File

@@ -84,7 +84,6 @@ struct H2C_SS_RFOFF_PARAM {
#define SET_8812_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8812_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
#define SET_8812_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8812_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
#define GET_8812_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)

22
include/rtl8812a_hal.h
View File

@@ -135,7 +135,11 @@ typedef struct _RT_FIRMWARE_8812 {
#endif
#define RX_DMA_BOUNDARY_8812 (MAX_RX_DMA_BUFFER_SIZE_8812 - RX_DMA_RESERVED_SIZE_8812 - 1)
#define BCNQ_PAGE_NUM_8812 0x07
#define PAGE_SIZE_TX_8812A PAGE_SIZE_512
/* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8812A
* PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
#define BCNQ_PAGE_NUM_8812 (MAX_BEACON_LEN / PAGE_SIZE_TX_8812A + 6) /*0x07*/
/* For WoWLan , more reserved page
* ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, AOAC rpt: 1,PNO: 6
@@ -193,12 +197,11 @@ typedef struct _RT_FIRMWARE_8812 {
#endif
#define RX_DMA_BOUNDARY_8821 (MAX_RX_DMA_BUFFER_SIZE_8821 - RX_DMA_RESERVED_SIZE_8821 - 1)
#define BCNQ_PAGE_NUM_8821 0x08
#ifdef CONFIG_CONCURRENT_MODE
#define BCNQ1_PAGE_NUM_8821 0x04
#else
#define BCNQ1_PAGE_NUM_8821 0x00
#endif
/* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8821A
* PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
#define BCNQ_PAGE_NUM_8821 (MAX_BEACON_LEN / PAGE_SIZE_TX_8821A + 6) /*0x08*/
/* For WoWLan , more reserved page
* ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, PNO: 6 */
@@ -208,7 +211,7 @@ typedef struct _RT_FIRMWARE_8812 {
#define WOWLAN_PAGE_NUM_8821 0x00
#endif
#define TX_TOTAL_PAGE_NUMBER_8821 (0xFF - BCNQ_PAGE_NUM_8821 - BCNQ1_PAGE_NUM_8821 - WOWLAN_PAGE_NUM_8821)
#define TX_TOTAL_PAGE_NUMBER_8821 (0xFF - BCNQ_PAGE_NUM_8821 - WOWLAN_PAGE_NUM_8821)
#define TX_PAGE_BOUNDARY_8821 (TX_TOTAL_PAGE_NUMBER_8821 + 1)
/* #define TX_PAGE_BOUNDARY_WOWLAN_8821 0xE0 */
@@ -344,9 +347,6 @@ void init_hal_spec_8821a(_adapter *adapter);
u32 upload_txpktbuf_8812au(_adapter *adapter, u8 *buf, u32 buflen);
/* register */
void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits);
void rtl8812_start_thread(PADAPTER padapter);
void rtl8812_stop_thread(PADAPTER padapter);

2
include/rtl8814a_cmd.h
View File

@@ -31,7 +31,6 @@
#define SET_8814A_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8814A_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
#define SET_8814A_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8814A_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
#define GET_8814A_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
@@ -140,7 +139,6 @@ void rtl8814_set_wowlan_cmd(_adapter *padapter, u8 enable);
void rtl8814_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
void rtl8814_set_FwPwrMode_cmd(PADAPTER padapter, u8 PSMode);
u8 GetTxBufferRsvdPageNum8814(_adapter *padapter, bool wowlan);
u8 rtl8814_set_rssi_cmd(_adapter *padapter, u8 *param);
void rtl8814_req_txrpt_cmd(PADAPTER padapter, u8 macid);
#ifdef CONFIG_TDLS

8
include/rtl8814a_hal.h
View File

@@ -51,7 +51,10 @@ typedef struct _RT_FIRMWARE_8814 {
} RT_FIRMWARE_8814, *PRT_FIRMWARE_8814;
#define PAGE_SIZE_TX_8814 PAGE_SIZE_128
#define BCNQ_PAGE_NUM_8814 0x08
/* BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_8814
* PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
#define BCNQ_PAGE_NUM_8814 (MAX_BEACON_LEN / PAGE_SIZE_TX_8814 + 6) /*0x08*/
#define Rtl8814A_NIC_PWR_ON_FLOW rtl8814A_power_on_flow
#define Rtl8814A_NIC_RF_OFF_FLOW rtl8814A_radio_off_flow
@@ -309,9 +312,6 @@ u8 GetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
void rtl8814_set_hal_ops(struct hal_ops *pHalFunc);
void init_hal_spec_8814a(_adapter *adapter);
/* register */
void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits);
void SetBcnCtrlReg(PADAPTER Adapter, u8 SetBits, u8 ClearBits);
void rtl8814_start_thread(PADAPTER padapter);
void rtl8814_stop_thread(PADAPTER padapter);

10
include/rtl8814a_xmit.h
View File

@@ -218,9 +218,10 @@ typedef struct txdescriptor_8814 {
/* Dword 7 */
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
#ifdef CONFIG_PCI_HCI
#define SET_TX_DESC_TX_BUFFER_SIZE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#else
#endif
#if defined(CONFIG_SDIO_HCI)|| defined(CONFIG_USB_HCI)
#define SET_TX_DESC_TX_DESC_CHECKSUM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#endif
#define SET_TX_DESC_NTX_MAP_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 20, 4, __Value)
@@ -233,9 +234,10 @@ typedef struct txdescriptor_8814 {
#define SET_TX_DESC_DATA_RC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
#define SET_TX_DESC_EN_HWEXSEQ_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 14, 1, __Value)
#define SET_TX_DESC_HWSEQ_EN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
#if (DEV_BUS_TYPE != RT_SDIO_INTERFACE)
#if defined(CONFIG_PCI_HCI)|| defined(CONFIG_USB_HCI)
#define SET_TX_DESC_NEXT_HEAD_PAGE_L_8814A(__pTxDesc, __Value)(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
#else
#endif
#ifdef CONFIG_SDIO_HCI
#define SET_TX_DESC_SDIO_SEQ_8814A(__pTxDesc, __Value)(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value) /* 20130415 KaiYuan add for 8814AS */
#endif
#define SET_TX_DESC_TAIL_PAGE_L_8814A(__pTxDesc, __Value)(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)

1
include/rtl8821c_hal.h
View File

@@ -75,6 +75,7 @@ void init_hal_spec_rtl8821c(PADAPTER);
void rtl8821c_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */
void rtl8821c_mp_config_rfpath(PADAPTER); /* hal_mp.c */
#endif
void rtl8821c_dl_rsvd_page(PADAPTER adapter, u8 mstatus);
#ifdef CONFIG_PCI_HCI
u16 get_txbd_rw_reg(u16 q_idx);

7
include/rtl8821c_spec.h
View File

@@ -29,7 +29,7 @@
#define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */
#define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */
#define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8821C/* hal_com.c */
#define REG_TSFTR1 REG_FREERUN_CNT_8821C /* hal_com.c */
#define REG_WOWLAN_WAKE_REASON 0x01C7
#define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8821C
@@ -187,8 +187,8 @@
struct hw_port_reg {
u32 net_type; /*reg_offset*/
u8 net_type_shift;
u32 macaddr; /*reg_offset*/
u32 bssid; /*reg_offset*/
u32 macaddr; /*reg_offset*/
u32 bssid; /*reg_offset*/
u32 bcn_ctl; /*reg_offset*/
u32 tsf_rst; /*reg_offset*/
u8 tsf_rst_bit;
@@ -196,6 +196,7 @@ struct hw_port_reg {
u8 bcn_space_shift;
u16 bcn_space_mask;
u32 ps_aid; /*reg_offset*/
u32 ta; /*reg_offset*/
};
#endif /* __RTL8192E_SPEC_H__ */

3
include/rtl8822b_hal.h
View File

@@ -38,7 +38,7 @@
#define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */
#define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */
#define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8822B /* hal_com.c */
#define REG_TSFTR1 REG_FREERUN_CNT_8822B /* hal_com.c */
#define REG_WOWLAN_WAKE_REASON 0x01C7 /* hal_com.c */
#define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8822B /* hal_com.c */
@@ -217,6 +217,7 @@ void rtl8822b_init_hal_spec(PADAPTER); /* hal/hal_com.c */
void rtl8822b_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */
void rtl8822b_mp_config_rfpath(PADAPTER); /* hal_mp.c */
#endif
void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus);
#ifdef CONFIG_USB_HCI
#include <rtl8822bu_hal.h>

5
include/rtw_android.h
View File

@@ -30,6 +30,7 @@ enum ANDROID_WIFI_CMD {
ANDROID_WIFI_CMD_BTCOEXSCAN_START,
ANDROID_WIFI_CMD_BTCOEXSCAN_STOP,
ANDROID_WIFI_CMD_BTCOEXMODE,
ANDROID_WIFI_CMD_SETSUSPENDMODE,
ANDROID_WIFI_CMD_SETSUSPENDOPT,
ANDROID_WIFI_CMD_P2P_DEV_ADDR,
ANDROID_WIFI_CMD_SETFWPATH,
@@ -93,11 +94,11 @@ int wifi_set_power(int on, unsigned long msec);
int wifi_get_mac_addr(unsigned char *buf);
void *wifi_get_country_code(char *ccode);
#else
static int rtw_android_wifictrl_func_add(void)
static inline int rtw_android_wifictrl_func_add(void)
{
return 0;
}
static void rtw_android_wifictrl_func_del(void) {}
static inline void rtw_android_wifictrl_func_del(void) {}
#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */
#ifdef CONFIG_GPIO_WAKEUP

12
include/rtw_ap.h
View File

@@ -70,7 +70,8 @@ void stop_ap_mode(_adapter *padapter);
#endif
void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, u8 offset);
bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offset, u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow);
u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp
, s16 req_ch, s8 req_bw, s8 req_offset, u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow);
#ifdef CONFIG_AUTO_AP_MODE
void rtw_auto_ap_rx_msg_dump(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_pos);
@@ -92,8 +93,15 @@ void rtw_update_bmc_sta_tx_rate(_adapter *adapter);
void rtw_process_ht_action_smps(_adapter *padapter, u8 *ta, u8 ctrl_field);
void rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_len);
#ifdef CONFIG_80211N_HT
int rtw_ht_operation_update(_adapter *padapter);
u8 rtw_ap_sta_linking_state_check(_adapter *adapter);
#endif /* CONFIG_80211N_HT */
u8 rtw_ap_sta_states_check(_adapter *adapter);
#ifdef CONFIG_FW_HANDLE_TXBCN
#define rtw_ap_get_nums(adapter) (adapter_to_dvobj(adapter)->nr_ap_if)
bool rtw_ap_nums_check(_adapter *adapter);
#endif
#ifdef CONFIG_SWTIMER_BASED_TXBCN
void tx_beacon_handlder(struct dvobj_priv *pdvobj);

2
include/rtw_beamforming.h
View File

@@ -327,7 +327,7 @@ struct beamforming_entry {
u16 mac_id; /* Used to Set Reg42C in IBSS mode. */
u16 p_aid; /* Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
u16 g_id;
u8 mac_addr[6];/* Used to fill Reg6E4 to fill Mac address of CSI report frame. */
u8 mac_addr[ETH_ALEN];/* Used to fill Reg6E4 to fill Mac address of CSI report frame. */
enum channel_width sound_bw; /* Sounding BandWidth */
u16 sound_period;
BEAMFORMING_CAP beamforming_entry_cap;

1
include/rtw_btcoex_wifionly.h
View File

@@ -17,6 +17,7 @@
void rtw_btcoex_wifionly_switchband_notify(PADAPTER padapter);
void rtw_btcoex_wifionly_scan_notify(PADAPTER padapter);
void rtw_btcoex_wifionly_connect_notify(PADAPTER padapter);
void rtw_btcoex_wifionly_hw_config(PADAPTER padapter);
void rtw_btcoex_wifionly_initialize(PADAPTER padapter);
void rtw_btcoex_wifionly_AntInfoSetting(PADAPTER padapter);

64
include/rtw_cmd.h
View File

@@ -150,6 +150,10 @@ struct P2P_PS_Offload_t {
u8 AllStaSleep:1; /* Only valid in Owner */
u8 discovery:1;
u8 rsvd:1;
#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
u8 p2p_macid:7;
u8 disable_close_rf:1; /*1: not close RF but just pause p2p_macid when NoA duration*/
#endif /* CONFIG_P2P_PS_NOA_USE_MACID_SLEEP */
};
struct P2P_PS_CTWPeriod_t {
@@ -246,9 +250,11 @@ enum rtw_drvextra_cmd_id {
BEAMFORMING_WK_CID,
LPS_CHANGE_DTIM_CID,
BTINFO_WK_CID,
DFS_MASTER_WK_CID,
DFS_RADAR_DETECT_WK_CID,
DFS_RADAR_DETECT_EN_DEC_WK_CID,
SESSION_TRACKER_WK_CID,
EN_HW_UPDATE_TSF_WK_CID,
PERIOD_TSF_UPDATE_END_WK_CID,
TEST_H2C_CID,
MP_CMD_WK_CID,
CUSTOMER_STR_WK_CID,
@@ -260,6 +266,10 @@ enum rtw_drvextra_cmd_id {
MCC_SET_DURATION_WK_CID,
#endif /* CONFIG_MCC_MODE */
REQ_PER_CMD_WK_CID,
SSMPS_WK_CID,
#ifdef CONFIG_CTRL_TXSS_BY_TP
TXSS_WK_CID,
#endif
MAX_WK_CID
};
@@ -344,7 +354,9 @@ Command Mode
struct createbss_parm {
bool adhoc;
/* used by AP mode now */
/* used by AP/Mesh mode now */
u8 ifbmp;
u8 excl_ifbmp;
s16 req_ch;
s8 req_bw;
s8 req_offset;
@@ -961,11 +973,6 @@ struct LedBlink_param {
PVOID pLed;
};
/*H2C Handler index: 61 */
struct SetChannelSwitch_param {
u8 new_ch_no;
};
/*H2C Handler index: 62 */
struct TDLSoption_param {
u8 addr[ETH_ALEN];
@@ -1016,9 +1023,11 @@ u8 rtw_startbss_cmd(_adapter *adapter, int flags);
#define REQ_CH_NONE -1
#define REQ_BW_NONE -1
#define REQ_BW_ORI -2
#define REQ_OFFSET_NONE -1
u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags, s16 req_ch, s8 req_bw, s8 req_offset);
u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags
, u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset);
extern u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch);
@@ -1049,7 +1058,7 @@ extern u8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr);
extern u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u16 start_seq);
/* add for CONFIG_IEEE80211W, none 11w also can use */
extern u8 rtw_reset_securitypriv_cmd(_adapter *padapter);
extern u8 rtw_free_assoc_resources_cmd(_adapter *padapter);
extern u8 rtw_free_assoc_resources_cmd(_adapter *padapter, u8 lock_scanned_queue, int flags);
extern u8 rtw_dynamic_chk_wk_cmd(_adapter *adapter);
u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 enqueue);
@@ -1068,14 +1077,17 @@ u8 rtw_dm_ra_mask_wk_cmd(_adapter *padapter, u8 *psta);
extern u8 rtw_ps_cmd(_adapter *padapter);
#ifdef CONFIG_DFS
void rtw_dfs_ch_switch_hdl(struct dvobj_priv *dvobj);
#endif
#ifdef CONFIG_AP_MODE
u8 rtw_chk_hi_queue_cmd(_adapter *padapter);
#ifdef CONFIG_DFS_MASTER
u8 rtw_dfs_master_cmd(_adapter *adapter, bool enqueue);
void rtw_dfs_master_timer_hdl(void *ctx);
void rtw_dfs_master_enable(_adapter *adapter, u8 ch, u8 bw, u8 offset);
void rtw_dfs_master_disable(_adapter *adapter, u8 ch, u8 bw, u8 offset, bool by_others);
void rtw_dfs_master_status_apply(_adapter *adapter, u8 self_action);
u8 rtw_dfs_rd_cmd(_adapter *adapter, bool enqueue);
void rtw_dfs_rd_timer_hdl(void *ctx);
void rtw_dfs_rd_en_decision(_adapter *adapter, u8 mlme_act, u8 excl_ifbmp);
u8 rtw_dfs_rd_en_decision_cmd(_adapter *adapter);
#endif /* CONFIG_DFS_MASTER */
#endif /* CONFIG_AP_MODE */
@@ -1086,6 +1098,7 @@ u8 rtw_btinfo_cmd(PADAPTER padapter, u8 *pbuf, u16 length);
u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len);
u8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter);
u8 rtw_periodic_tsf_update_end_cmd(_adapter *adapter);
u8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags);
@@ -1093,7 +1106,7 @@ u8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 swconfig);
u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, u8 swconfig);
extern u8 rtw_led_blink_cmd(_adapter *padapter, PVOID pLed);
extern u8 rtw_set_csa_cmd(_adapter *padapter, u8 new_ch_no);
extern u8 rtw_set_csa_cmd(_adapter *adapter);
extern u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option);
u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags);
@@ -1118,6 +1131,12 @@ u8 rtw_rson_scan_wk_cmd(_adapter *adapter, int op);
u8 rtw_run_in_thread_cmd(PADAPTER padapter, void (*func)(void *), void *context);
struct ssmps_cmd_parm {
struct sta_info *sta;
u8 smps;
};
u8 rtw_ssmps_wk_cmd(_adapter *adapter, struct sta_info *sta, u8 smps, u8 enqueue);
u8 session_tracker_chk_cmd(_adapter *adapter, struct sta_info *sta);
u8 session_tracker_add_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port);
u8 session_tracker_del_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port);
@@ -1126,6 +1145,21 @@ u8 session_tracker_del_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_na
u8 rtw_req_per_cmd(_adapter * adapter);
#endif
#ifdef CONFIG_CTRL_TXSS_BY_TP
struct txss_cmd_parm {
struct sta_info *sta;
u8 tx_1ss;
};
void rtw_ctrl_txss_update_mimo_type(_adapter *adapter, struct sta_info *sta);
u8 rtw_ctrl_txss(_adapter *adapter, struct sta_info *sta, u8 tx_1ss);
void rtw_ctrl_tx_ss_by_tp(_adapter *adapter, u8 from_timer);
#ifdef DBG_CTRL_TXSS
void dbg_ctrl_txss(_adapter *adapter, u8 tx_1ss);
#endif
#endif
u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf);
extern void rtw_survey_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd);

58
include/rtw_debug.h
View File

@@ -306,12 +306,6 @@ int proc_get_rf_info(struct seq_file *m, void *v);
int proc_get_scan_param(struct seq_file *m, void *v);
ssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
int proc_get_scan_abort(struct seq_file *m, void *v);
#ifdef CONFIG_SCAN_BACKOP
int proc_get_backop_flags_sta(struct seq_file *m, void *v);
ssize_t proc_set_backop_flags_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
int proc_get_backop_flags_ap(struct seq_file *m, void *v);
ssize_t proc_set_backop_flags_ap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
#endif /* CONFIG_SCAN_BACKOP */
#ifdef CONFIG_RTW_REPEATER_SON
int proc_get_rson_data(struct seq_file *m, void *v);
ssize_t proc_set_rson_data(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
@@ -319,6 +313,9 @@ ssize_t proc_set_rson_data(struct file *file, const char __user *buffer, size_t
int proc_get_survey_info(struct seq_file *m, void *v);
ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
int proc_get_ap_info(struct seq_file *m, void *v);
#ifdef ROKU_PRIVATE
int proc_get_infra_ap(struct seq_file *m, void *v);
#endif /* ROKU_PRIVATE */
ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
int proc_get_trx_info(struct seq_file *m, void *v);
ssize_t proc_set_tx_power_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
@@ -352,6 +349,11 @@ void rtw_sta_linking_test_set_start(void);
bool rtw_sta_linking_test_wait_done(void);
bool rtw_sta_linking_test_force_fail(void);
ssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
#ifdef CONFIG_AP_MODE
u16 rtw_ap_linking_test_force_auth_fail(void);
u16 rtw_ap_linking_test_force_asoc_fail(void);
ssize_t proc_set_ap_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
#endif
int proc_get_rx_stat(struct seq_file *m, void *v);
int proc_get_tx_stat(struct seq_file *m, void *v);
@@ -370,10 +372,15 @@ ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size
int proc_get_trx_info_debug(struct seq_file *m, void *v);
#ifdef CONFIG_HUAWEI_PROC
int proc_get_huawei_trx_info(struct seq_file *m, void *v);
#endif
int proc_get_rx_signal(struct seq_file *m, void *v);
ssize_t proc_set_rx_signal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
int proc_get_hw_status(struct seq_file *m, void *v);
ssize_t proc_set_hw_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
int proc_get_mac_rptbuf(struct seq_file *m, void *v);
#ifdef CONFIG_80211N_HT
int proc_get_ht_enable(struct seq_file *m, void *v);
@@ -385,8 +392,6 @@ ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t co
int proc_get_ampdu_enable(struct seq_file *m, void *v);
ssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
int proc_get_mac_rptbuf(struct seq_file *m, void *v);
void dump_regsty_rx_ampdu_size_limit(void *sel, _adapter *adapter);
int proc_get_rx_ampdu(struct seq_file *m, void *v);
ssize_t proc_set_rx_ampdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
@@ -462,6 +467,13 @@ int proc_get_int_logs(struct seq_file *m, void *v);
int proc_get_rx_ring(struct seq_file *m, void *v);
int proc_get_tx_ring(struct seq_file *m, void *v);
int proc_get_pci_aspm(struct seq_file *m, void *v);
int proc_get_pci_conf_space(struct seq_file *m, void *v);
ssize_t proc_set_pci_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
int proc_get_pci_bridge_conf_space(struct seq_file *m, void *v);
ssize_t proc_set_pci_bridge_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
#ifdef DBG_TXBD_DESC_DUMP
int proc_get_tx_ring_ext(struct seq_file *m, void *v);
ssize_t proc_set_tx_ring_ext(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
@@ -493,6 +505,7 @@ ssize_t proc_set_new_bcn_max(struct file *file, const char __user *buffer, size_
#ifdef CONFIG_POWER_SAVING
int proc_get_ps_info(struct seq_file *m, void *v);
ssize_t proc_set_ps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
#ifdef CONFIG_WMMPS_STA
int proc_get_wmmps_info(struct seq_file *m, void *v);
ssize_t proc_set_wmmps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
@@ -531,6 +544,11 @@ int proc_get_tx_auth(struct seq_file *m, void *v);
int proc_get_efuse_map(struct seq_file *m, void *v);
ssize_t proc_set_efuse_map(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
int proc_get_pathb_phase(struct seq_file *m, void *v);
ssize_t proc_set_pathb_phase(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
#endif
#ifdef CONFIG_MCC_MODE
int proc_get_mcc_info(struct seq_file *m, void *v);
ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
@@ -551,6 +569,11 @@ ssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_
int proc_get_fw_offload(struct seq_file *m, void *v);
ssize_t proc_set_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
#ifdef CONFIG_FW_HANDLE_TXBCN
ssize_t proc_set_fw_tbtt_rpt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
int proc_get_fw_tbtt_rpt(struct seq_file *m, void *v);
#endif
#ifdef CONFIG_DBG_RF_CAL
int proc_get_iqk_info(struct seq_file *m, void *v);
ssize_t proc_set_iqk(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
@@ -558,6 +581,25 @@ int proc_get_lck_info(struct seq_file *m, void *v);
ssize_t proc_set_lck(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
#endif /*CONFIG_DBG_RF_CAL*/
#ifdef CONFIG_CTRL_TXSS_BY_TP
ssize_t proc_set_txss_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
int proc_get_txss_tp(struct seq_file *m, void *v);
#ifdef DBG_CTRL_TXSS
ssize_t proc_set_txss_ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
int proc_get_txss_ctrl(struct seq_file *m, void *v);
#endif
#endif
#ifdef CONFIG_LPS_CHK_BY_TP
ssize_t proc_set_lps_chk_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
int proc_get_lps_chk_tp(struct seq_file *m, void *v);
#endif
#ifdef CONFIG_SUPPORT_STATIC_SMPS
ssize_t proc_set_smps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
int proc_get_smps(struct seq_file *m, void *v);
#endif
#define _drv_always_ 1
#define _drv_emerg_ 2
#define _drv_alert_ 3

12
include/rtw_efuse.h
View File

@@ -50,7 +50,7 @@ enum _EFUSE_DEF_TYPE {
#define EFUSE_MAX_SECTION_NUM 128
#define EFUSE_MAX_BANK_SIZE 512
/*RTL8822B 8821C BT EFUSE Define 1 BANK 128 size logical map 1024*/
/*RTL8822B 8821C BT EFUSE Define 1 BANK 128 size logical map 1024*/
#ifdef RTW_HALMAC
#define BANK_NUM 1
#define EFUSE_BT_REAL_BANK_CONTENT_LEN 128
@@ -179,13 +179,6 @@ extern u8 fakeBTEfuseModifiedMap[];
#define MAX_SEGMENT_NUM 200
#define MAX_BUF_SIZE (MAX_SEGMENT_SIZE*MAX_SEGMENT_NUM)
#define TMP_BUF_SIZE 100
static u8 dcmd_Return_Buffer[MAX_BUF_SIZE] = {0};
static u32 dcmd_Buf_Idx = 0;
static u32 dcmd_Finifh_Flag = 0;
static char dcmd_Buf[TMP_BUF_SIZE];
#define rtprintf dcmd_Store_Return_Buf
u8 efuse_bt_GetCurrentSize(PADAPTER padapter, u16 *size);
@@ -222,6 +215,9 @@ void EFUSE_ShadowMapUpdate(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest)
void EFUSE_ShadowRead(PADAPTER pAdapter, u8 Type, u16 Offset, u32 *Value);
#define efuse_logical_map_read(adapter, type, offset, value) EFUSE_ShadowRead((adapter), (type), (offset), (value))
BOOLEAN rtw_file_efuse_IsMasked(PADAPTER pAdapter, u16 Offset);
BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset);
VOID hal_ReadEFuse_BT_logic_map(
PADAPTER padapter,
u16 _offset,

32
include/rtw_ht.h
View File

@@ -51,6 +51,21 @@ struct ht_priv {
};
#ifdef ROKU_PRIVATE
struct ht_priv_infra_ap {
/*Infra mode, only store AP's info , not intersection of STA and AP*/
u8 channel_width_infra_ap;
u8 sgi_20m_infra_ap;
u8 sgi_40m_infra_ap;
u8 ldpc_cap_infra_ap;
u8 stbc_cap_infra_ap;
u8 MCS_set_infra_ap[16];
u8 Rx_ss_infra_ap;
u16 rx_highest_data_rate_infra_ap;
};
#endif /* ROKU_PRIVATE */
typedef enum AGGRE_SIZE {
HT_AGG_SIZE_8K = 0,
HT_AGG_SIZE_16K = 1,
@@ -62,23 +77,6 @@ typedef enum AGGRE_SIZE {
VHT_AGG_SIZE_1024K = 7,
} AGGRE_SIZE_E, *PAGGRE_SIZE_E;
typedef enum _RT_HT_INF0_CAP {
RT_HT_CAP_USE_TURBO_AGGR = 0x01,
RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
RT_HT_CAP_USE_AMPDU = 0x04,
RT_HT_CAP_USE_WOW = 0x8,
RT_HT_CAP_USE_SOFTAP = 0x10,
RT_HT_CAP_USE_92SE = 0x20,
RT_HT_CAP_USE_88C_92C = 0x40,
RT_HT_CAP_USE_AP_CLIENT_MODE = 0x80, /* AP team request to reserve this bit, by Emily */
} RT_HT_INF0_CAPBILITY, *PRT_HT_INF0_CAPBILITY;
typedef enum _RT_HT_INF1_CAP {
RT_HT_CAP_USE_VIDEO_CLIENT = 0x01,
RT_HT_CAP_USE_JAGUAR_BCUT = 0x02,
RT_HT_CAP_USE_JAGUAR_CCUT = 0x04,
} RT_HT_INF1_CAPBILITY, *PRT_HT_INF1_CAPBILITY;
#define LDPC_HT_ENABLE_RX BIT0
#define LDPC_HT_ENABLE_TX BIT1
#define LDPC_HT_TEST_TX_ENABLE BIT2

8
include/rtw_mcc.h
View File

@@ -100,7 +100,7 @@ enum mcc_status_rpt {
MCC_RPT_MAX,
};
enum MCC_ROLE {
enum mcc_role {
MCC_ROLE_STA = 0,
MCC_ROLE_AP = 1,
MCC_ROLE_GC = 2,
@@ -129,7 +129,7 @@ enum MCC_SCHED_MODE {
/* mcc data for adapter */
struct mcc_adapter_priv {
u8 order; /* FW document, softap/AP must be 0 */
u8 role; /* MCC role(AP,STA,GO,GC) */
enum mcc_role role; /* MCC role(AP,STA,GO,GC) */
u8 mcc_duration; /* channel stay period, UNIT:1TU */
/* flow control */
@@ -182,12 +182,14 @@ struct mcc_obj_priv {
u8 mcc_stop_threshold;
u8 current_order;
u8 last_tsfdiff;
u32 mcc_launch_time; /* mcc launch time, used for starting detect mcc switch channel success */
systime mcc_launch_time; /* mcc launch time, used for starting detect mcc switch channel success */
_mutex mcc_mutex;
_lock mcc_lock;
PADAPTER iface[MAX_MCC_NUM]; /* by order, use for mcc parameter cmd */
struct submit_ctx mcc_sctx;
struct submit_ctx mcc_tsf_req_sctx;
_mutex mcc_tsf_req_mutex;
u8 mcc_tsf_req_sctx_order; /* record current order for mcc_tsf_req_sctx */
#ifdef CONFIG_MCC_MODE_V2
u8 mcc_iqk_value_rsvd_page[3];
#endif /* CONFIG_MCC_MODE_V2 */

30
include/rtw_mi.h
View File

@@ -18,6 +18,8 @@
void rtw_mi_update_union_chan_inf(_adapter *adapter, u8 ch, u8 offset , u8 bw);
u8 rtw_mi_stayin_union_ch_chk(_adapter *adapter);
u8 rtw_mi_stayin_union_band_chk(_adapter *adapter);
int rtw_mi_get_ch_setting_union_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, u8 *ch, u8 *bw, u8 *offset);
int rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset);
int rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset);
@@ -48,7 +50,11 @@ struct mi_state {
#endif
u8 mgmt_tx_num;
#endif
#ifdef CONFIG_P2P
u8 p2p_device_num;
u8 p2p_gc;
u8 p2p_go;
#endif
u8 union_ch;
u8 union_bw;
u8 union_offset;
@@ -95,6 +101,16 @@ struct mi_state {
#define MSTATE_ROCH_NUM(_mstate) 0
#endif
#ifdef CONFIG_P2P
#define MSTATE_P2P_DV_NUM(_mstate) ((_mstate)->p2p_device_num)
#define MSTATE_P2P_GC_NUM(_mstate) ((_mstate)->p2p_gc)
#define MSTATE_P2P_GO_NUM(_mstate) ((_mstate)->p2p_go)
#else
#define MSTATE_P2P_DV_NUM(_mstate) 0
#define MSTATE_P2P_GC_NUM(_mstate) 0
#define MSTATE_P2P_GO_NUM(_mstate) 0
#endif
#if defined(CONFIG_IOCTL_CFG80211)
#define MSTATE_MGMT_TX_NUM(_mstate) ((_mstate)->mgmt_tx_num)
#else
@@ -112,8 +128,10 @@ struct mi_state {
#define rtw_mi_get_assoced_sta_num(adapter) DEV_STA_LD_NUM(adapter_to_dvobj(adapter))
#define rtw_mi_get_ap_num(adapter) DEV_AP_NUM(adapter_to_dvobj(adapter))
#define rtw_mi_get_mesh_num(adapter) DEV_MESH_NUM(adapter_to_dvobj(adapter))
u8 rtw_mi_get_assoc_if_num(_adapter *adapter);
/* For now, not return union_ch/bw/offset */
void rtw_mi_status_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, struct mi_state *mstate);
void rtw_mi_status(_adapter *adapter, struct mi_state *mstate);
void rtw_mi_status_no_self(_adapter *adapter, struct mi_state *mstate);
void rtw_mi_status_no_others(_adapter *adapter, struct mi_state *mstate);
@@ -157,6 +175,9 @@ void rtw_mi_buddy_intf_start(_adapter *adapter);
void rtw_mi_intf_stop(_adapter *adapter);
void rtw_mi_buddy_intf_stop(_adapter *adapter);
#ifdef CONFIG_NEW_NETDEV_HDL
u8 rtw_mi_hal_iface_init(_adapter *padapter);
#endif
void rtw_mi_suspend_free_assoc_resource(_adapter *adapter);
void rtw_mi_buddy_suspend_free_assoc_resource(_adapter *adapter);
@@ -236,9 +257,6 @@ void rtw_mi_buddy_adapter_reset(_adapter *padapter);
u8 rtw_mi_dynamic_check_timer_handlder(_adapter *padapter);
u8 rtw_mi_buddy_dynamic_check_timer_handlder(_adapter *padapter);
u8 rtw_mi_dev_unload(_adapter *padapter);
u8 rtw_mi_buddy_dev_unload(_adapter *padapter);
extern void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter);
u8 rtw_mi_dynamic_chk_wk_hdl(_adapter *padapter);
u8 rtw_mi_buddy_dynamic_chk_wk_hdl(_adapter *padapter);
@@ -268,7 +286,7 @@ u8 rtw_mi_buddy_stay_in_p2p_mode(_adapter *padapter);
#endif
_adapter *rtw_get_iface_by_id(_adapter *padapter, u8 iface_id);
_adapter *rtw_get_iface_by_macddr(_adapter *padapter, u8 *mac_addr);
_adapter *rtw_get_iface_by_macddr(_adapter *padapter, const u8 *mac_addr);
_adapter *rtw_get_iface_by_hwport(_adapter *padapter, u8 hw_port);
void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvframe, u8 *pphy_status);
@@ -278,6 +296,8 @@ void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvf
_adapter *rtw_mi_get_ap_adapter(_adapter *padapter);
#endif
u8 rtw_mi_get_ld_sta_ifbmp(_adapter *adapter);
u8 rtw_mi_get_ap_mesh_ifbmp(_adapter *adapter);
void rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b);
#endif /*__RTW_MI_H_*/

96
include/rtw_mlme.h
View File

@@ -56,7 +56,7 @@
#define WIFI_MP_CTX_CCK_CS 0x00200000 /* in continuous tx with carrier suppression */
#define WIFI_MP_LPBK_STATE 0x00400000
#define WIFI_OP_CH_SWITCHING 0x00800000
/*#define WIFI_UNDEFINED_STATE 0x01000000*/
#define WIFI_UNDER_KEY_HANDSHAKE 0x01000000
/*#define WIFI_UNDEFINED_STATE 0x02000000*/
/*#define WIFI_UNDEFINED_STATE 0x04000000*/
/*#define WIFI_UNDEFINED_STATE 0x08000000*/
@@ -158,6 +158,7 @@ enum {
MLME_ADHOC_STOPPED,
MLME_MESH_STARTED,
MLME_MESH_STOPPED,
MLME_OPCH_SWITCH,
};
#define _FW_UNDER_LINKING WIFI_UNDER_LINKING
@@ -749,20 +750,22 @@ struct mlme_priv {
_lock lock;
sint fw_state; /* shall we protect this variable? maybe not necessarily... */
u8 to_join; /* flag */
u16 join_status;
#ifdef CONFIG_LAYER2_ROAMING
u8 to_roam; /* roaming trying times */
struct wlan_network *roam_network; /* the target of active roam */
u8 roam_flags;
u8 roam_rssi_diff_th; /* rssi difference threshold for active scan candidate selection */
u32 roam_scan_int_ms; /* scan interval for active roam */
u32 roam_scan_int; /* scan interval for active roam (Unit:2 second)*/
u32 roam_scanr_exp_ms; /* scan result expire time in ms for roam */
u8 roam_tgt_addr[ETH_ALEN]; /* request to roam to speicific target without other consideration */
u8 roam_rssi_threshold;
systime last_roaming;
bool need_to_roam;
#endif
u8 *nic_hdl;
u32 max_bss_cnt; /* The size of scan queue */
_list *pscanned;
_queue free_bss_pool;
_queue scanned_queue;
@@ -777,14 +780,16 @@ struct mlme_priv {
/* bcn check info */
struct beacon_keys cur_beacon_keys; /* save current beacon keys */
#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
struct beacon_keys new_beacon_keys; /* save new beacon keys */
u8 new_beacon_cnts; /* if new_beacon_cnts >= threshold, ap beacon is changed */
#endif
#ifdef CONFIG_ARP_KEEP_ALIVE
/* for arp offload keep alive */
u8 bGetGateway;
u8 GetGatewayTryCnt;
u8 gw_mac_addr[6];
u8 gw_mac_addr[ETH_ALEN];
u8 gw_ip[4];
#endif
@@ -804,6 +809,7 @@ struct mlme_priv {
_timer set_scan_deny_timer;
ATOMIC_T set_scan_deny; /* 0: allowed, 1: deny */
#endif
u8 wpa_phase;/*wpa_phase after wps finished*/
struct qos_priv qospriv;
@@ -824,7 +830,16 @@ struct mlme_priv {
#ifdef CONFIG_80211AC_VHT
struct vht_priv vhtpriv;
#ifdef ROKU_PRIVATE
/*infra mode, used to store AP's info*/
struct vht_priv_infra_ap vhtpriv_infra_ap;
#endif /* ROKU_PRIVATE */
#endif
#ifdef ROKU_PRIVATE
struct ht_priv_infra_ap htpriv_infra_ap;
#endif /* ROKU_PRIVATE */
#ifdef CONFIG_BEAMFORMING
#ifndef RTW_BEAMFORMING_VERSION_2
#if (BEAMFORMING_SUPPORT == 0)/*for driver beamforming*/
@@ -833,13 +848,6 @@ struct mlme_priv {
#endif /* !RTW_BEAMFORMING_VERSION_2 */
#endif
#ifdef CONFIG_DFS
u8 handle_dfs;
#endif
#ifdef CONFIG_DFS_MASTER
/* TODO: move to rfctl */
_timer dfs_master_timer;
#endif
#ifdef CONFIG_RTW_80211R
struct ft_roam_info ft_roam;
#endif
@@ -1002,11 +1010,6 @@ struct mlme_priv {
u8 scanning_via_buddy_intf;
#endif
#if 0
u8 NumOfBcnInfoChkFail;
u32 timeBcnInfoChkStart;
#endif
#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
u32 vendor_ie_mask[WLAN_MAX_VENDOR_IE_NUM];
u8 vendor_ie[WLAN_MAX_VENDOR_IE_NUM][WLAN_MAX_VENDOR_IE_LEN];
@@ -1050,7 +1053,7 @@ extern void hostapd_mode_unload(_adapter *padapter);
#endif
extern void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf);
extern void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status);
extern void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf);
extern void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf);
extern void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf);
@@ -1188,7 +1191,7 @@ extern struct wlan_network *rtw_get_oldest_wlan_network(_queue *scanned_queue);
struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network);
struct wlan_network *rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network);
extern void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue);
extern void rtw_free_assoc_resources(_adapter *adapter, u8 lock_scanned_queue);
extern void rtw_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated);
extern void rtw_indicate_connect(_adapter *adapter);
void rtw_indicate_scan_done(_adapter *padapter, bool aborted);
@@ -1218,6 +1221,29 @@ extern void rtw_scan_timeout_handler(void *ctx);
extern void rtw_dynamic_check_timer_handlder(void *ctx);
extern void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter);
enum {
SS_DENY_MP_MODE,
SS_DENY_RSON_SCANING,
SS_DENY_BLOCK_SCAN,
SS_DENY_BY_DRV,
SS_DENY_SELF_AP_UNDER_WPS,
SS_DENY_SELF_AP_UNDER_LINKING,
SS_DENY_SELF_AP_UNDER_SURVEY,
/*SS_DENY_SELF_STA_UNDER_WPS,*/
SS_DENY_SELF_STA_UNDER_LINKING,
SS_DENY_SELF_STA_UNDER_SURVEY,
SS_DENY_BUDDY_UNDER_LINK_WPS,
SS_DENY_BUDDY_UNDER_SURVEY,
SS_DENY_BUSY_TRAFFIC,
SS_ALLOW,
#ifdef DBG_LA_MODE
SS_DENY_LA_MODE,
#endif
};
u8 _rtw_sitesurvey_condition_check(const char *caller, _adapter *adapter, bool check_sc_interval);
#define rtw_sitesurvey_condition_check(adapter, check_sc_interval) _rtw_sitesurvey_condition_check(__func__, adapter, check_sc_interval)
#ifdef CONFIG_SET_SCAN_DENY_TIMER
bool rtw_is_scan_deny(_adapter *adapter);
void rtw_clear_scan_deny(_adapter *adapter);
@@ -1332,6 +1358,40 @@ void rtw_proxim_disable(_adapter *padapter);
void rtw_proxim_send_packet(_adapter *padapter, u8 *pbuf, u16 len, u8 m_rate);
#endif /* CONFIG_INTEL_PROXIM */
#define GET_ARP_HTYPE(_arp) BE_BITS_TO_2BYTE(((u8 *)(_arp)) + 0, 0, 16)
#define GET_ARP_PTYPE(_arp) BE_BITS_TO_2BYTE(((u8 *)(_arp)) + 2, 0, 16)
#define GET_ARP_HLEN(_arp) BE_BITS_TO_1BYTE(((u8 *)(_arp)) + 4, 0, 8)
#define GET_ARP_PLEN(_arp) BE_BITS_TO_1BYTE(((u8 *)(_arp)) + 5, 0, 8)
#define GET_ARP_OPER(_arp) BE_BITS_TO_2BYTE(((u8 *)(_arp)) + 6, 0, 16)
#define SET_ARP_HTYPE(_arp, _val) SET_BITS_TO_BE_2BYTE(((u8 *)(_arp)) + 0, 0, 16, _val)
#define SET_ARP_PTYPE(_arp, _val) SET_BITS_TO_BE_2BYTE(((u8 *)(_arp)) + 2, 0, 16, _val)
#define SET_ARP_HLEN(_arp, _val) SET_BITS_TO_BE_1BYTE(((u8 *)(_arp)) + 4, 0, 8, _val)
#define SET_ARP_PLEN(_arp, _val) SET_BITS_TO_BE_1BYTE(((u8 *)(_arp)) + 5, 0, 8, _val)
#define SET_ARP_OPER(_arp, _val) SET_BITS_TO_BE_2BYTE(((u8 *)(_arp)) + 6, 0, 16, _val)
#define ARP_SHA(_arp, _hlen, _plen) (((u8 *)(_arp)) + 8)
#define ARP_SPA(_arp, _hlen, _plen) (((u8 *)(_arp)) + 8 + (_hlen))
#define ARP_THA(_arp, _hlen, _plen) (((u8 *)(_arp)) + 8 + (_hlen) + (_plen))
#define ARP_TPA(_arp, _hlen, _plen) (((u8 *)(_arp)) + 8 + 2 * (_hlen) + (_plen))
#define ARP_SENDER_MAC_ADDR(_arp) ARP_SHA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)
#define ARP_SENDER_IP_ADDR(_arp) ARP_SPA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)
#define ARP_TARGET_MAC_ADDR(_arp) ARP_THA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)
#define ARP_TARGET_IP_ADDR(_arp) ARP_TPA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)
#define GET_ARP_SENDER_MAC_ADDR(_arp, _val) _rtw_memcpy(_val, ARP_SENDER_MAC_ADDR(_arp), ETH_ALEN)
#define GET_ARP_SENDER_IP_ADDR(_arp, _val) _rtw_memcpy(_val, ARP_SENDER_IP_ADDR(_arp), RTW_IP_ADDR_LEN)
#define GET_ARP_TARGET_MAC_ADDR(_arp, _val) _rtw_memcpy(_val, ARP_TARGET_MAC_ADDR(_arp), ETH_ALEN)
#define GET_ARP_TARGET_IP_ADDR(_arp, _val) _rtw_memcpy(_val, ARP_TARGET_IP_ADDR(_arp), RTW_IP_ADDR_LEN)
#define SET_ARP_SENDER_MAC_ADDR(_arp, _val) _rtw_memcpy(ARP_SENDER_MAC_ADDR(_arp), _val, ETH_ALEN)
#define SET_ARP_SENDER_IP_ADDR(_arp, _val) _rtw_memcpy(ARP_SENDER_IP_ADDR(_arp), _val, RTW_IP_ADDR_LEN)
#define SET_ARP_TARGET_MAC_ADDR(_arp, _val) _rtw_memcpy(ARP_TARGET_MAC_ADDR(_arp), _val, ETH_ALEN)
#define SET_ARP_TARGET_IP_ADDR(_arp, _val) _rtw_memcpy(ARP_TARGET_IP_ADDR(_arp), _val, RTW_IP_ADDR_LEN)
void dump_arp_pkt(void *sel, u8 *da, u8 *sa, u8 *arp, bool tx);
#define IPV4_SRC(_iphdr) (((u8 *)(_iphdr)) + 12)
#define IPV4_DST(_iphdr) (((u8 *)(_iphdr)) + 16)
#define GET_IPV4_IHL(_iphdr) BE_BITS_TO_1BYTE(((u8 *)(_iphdr)) + 0, 0, 4)

308
include/rtw_mlme_ext.h
View File

@@ -88,146 +88,11 @@ extern unsigned char P2P_OUI[];
extern unsigned char WMM_INFO_OUI[];
extern unsigned char WMM_PARA_OUI[];
typedef enum _RT_CHANNEL_DOMAIN {
/* ===== 0x00 ~ 0x1F, legacy channel plan ===== */
RTW_CHPLAN_FCC = 0x00,
RTW_CHPLAN_IC = 0x01,
RTW_CHPLAN_ETSI = 0x02,
RTW_CHPLAN_SPAIN = 0x03,
RTW_CHPLAN_FRANCE = 0x04,
RTW_CHPLAN_MKK = 0x05,
RTW_CHPLAN_MKK1 = 0x06,
RTW_CHPLAN_ISRAEL = 0x07,
RTW_CHPLAN_TELEC = 0x08,
RTW_CHPLAN_GLOBAL_DOAMIN = 0x09,
RTW_CHPLAN_WORLD_WIDE_13 = 0x0A,
RTW_CHPLAN_TAIWAN = 0x0B,
RTW_CHPLAN_CHINA = 0x0C,
RTW_CHPLAN_SINGAPORE_INDIA_MEXICO = 0x0D,
RTW_CHPLAN_KOREA = 0x0E,
RTW_CHPLAN_TURKEY = 0x0F,
RTW_CHPLAN_JAPAN = 0x10,
RTW_CHPLAN_FCC_NO_DFS = 0x11,
RTW_CHPLAN_JAPAN_NO_DFS = 0x12,
RTW_CHPLAN_WORLD_WIDE_5G = 0x13,
RTW_CHPLAN_TAIWAN_NO_DFS = 0x14,
/* ===== 0x20 ~ 0x7F, new channel plan ===== */
RTW_CHPLAN_WORLD_NULL = 0x20,
RTW_CHPLAN_ETSI1_NULL = 0x21,
RTW_CHPLAN_FCC1_NULL = 0x22,
RTW_CHPLAN_MKK1_NULL = 0x23,
RTW_CHPLAN_ETSI2_NULL = 0x24,
RTW_CHPLAN_FCC1_FCC1 = 0x25,
RTW_CHPLAN_WORLD_ETSI1 = 0x26,
RTW_CHPLAN_MKK1_MKK1 = 0x27,
RTW_CHPLAN_WORLD_KCC1 = 0x28,
RTW_CHPLAN_WORLD_FCC2 = 0x29,
RTW_CHPLAN_FCC2_NULL = 0x2A,
RTW_CHPLAN_IC1_IC2 = 0x2B,
RTW_CHPLAN_MKK2_NULL = 0x2C,
RTW_CHPLAN_WORLD_CHILE1= 0x2D,
RTW_CHPLAN_WORLD1_WORLD1 = 0x2E,
RTW_CHPLAN_WORLD_CHILE2 = 0x2F,
RTW_CHPLAN_WORLD_FCC3 = 0x30,
RTW_CHPLAN_WORLD_FCC4 = 0x31,
RTW_CHPLAN_WORLD_FCC5 = 0x32,
RTW_CHPLAN_WORLD_FCC6 = 0x33,
RTW_CHPLAN_FCC1_FCC7 = 0x34,
RTW_CHPLAN_WORLD_ETSI2 = 0x35,
RTW_CHPLAN_WORLD_ETSI3 = 0x36,
RTW_CHPLAN_MKK1_MKK2 = 0x37,
RTW_CHPLAN_MKK1_MKK3 = 0x38,
RTW_CHPLAN_FCC1_NCC1 = 0x39,
RTW_CHPLAN_ETSI1_ETSI1 = 0x3A,
RTW_CHPLAN_ETSI1_ACMA1 = 0x3B,
RTW_CHPLAN_ETSI1_ETSI6 = 0x3C,
RTW_CHPLAN_ETSI1_ETSI12 = 0x3D,
RTW_CHPLAN_FCC1_NCC2 = 0x40,
RTW_CHPLAN_GLOBAL_NULL = 0x41,
RTW_CHPLAN_ETSI1_ETSI4 = 0x42,
RTW_CHPLAN_FCC1_FCC2 = 0x43,
RTW_CHPLAN_FCC1_NCC3 = 0x44,
RTW_CHPLAN_WORLD_ACMA1 = 0x45,
RTW_CHPLAN_FCC1_FCC8 = 0x46,
RTW_CHPLAN_WORLD_ETSI6 = 0x47,
RTW_CHPLAN_WORLD_ETSI7 = 0x48,
RTW_CHPLAN_WORLD_ETSI8 = 0x49,
RTW_CHPLAN_WORLD_ETSI9 = 0x50,
RTW_CHPLAN_WORLD_ETSI10 = 0x51,
RTW_CHPLAN_WORLD_ETSI11 = 0x52,
RTW_CHPLAN_FCC1_NCC4 = 0x53,
RTW_CHPLAN_WORLD_ETSI12 = 0x54,
RTW_CHPLAN_FCC1_FCC9 = 0x55,
RTW_CHPLAN_WORLD_ETSI13 = 0x56,
RTW_CHPLAN_FCC1_FCC10 = 0x57,
RTW_CHPLAN_MKK2_MKK4 = 0x58,
RTW_CHPLAN_WORLD_ETSI14 = 0x59,
RTW_CHPLAN_FCC1_FCC5 = 0x60,
RTW_CHPLAN_FCC2_FCC7 = 0x61,
RTW_CHPLAN_FCC2_FCC1 = 0x62,
RTW_CHPLAN_WORLD_ETSI15 = 0x63,
RTW_CHPLAN_MKK2_MKK5 = 0x64,
RTW_CHPLAN_ETSI1_ETSI16 = 0x65,
RTW_CHPLAN_FCC1_FCC14 = 0x66,
RTW_CHPLAN_FCC1_FCC12 = 0x67,
RTW_CHPLAN_FCC2_FCC14 = 0x68,
RTW_CHPLAN_FCC2_FCC12 = 0x69,
RTW_CHPLAN_ETSI1_ETSI17 = 0x6A,
RTW_CHPLAN_WORLD_FCC16 = 0x6B,
RTW_CHPLAN_WORLD_FCC13 = 0x6C,
RTW_CHPLAN_FCC2_FCC15 = 0x6D,
RTW_CHPLAN_WORLD_FCC12 = 0x6E,
RTW_CHPLAN_NULL_ETSI8 = 0x6F,
RTW_CHPLAN_NULL_ETSI18 = 0x70,
RTW_CHPLAN_NULL_ETSI17 = 0x71,
RTW_CHPLAN_NULL_ETSI19 = 0x72,
RTW_CHPLAN_WORLD_FCC7 = 0x73,
RTW_CHPLAN_FCC2_FCC17 = 0x74,
RTW_CHPLAN_WORLD_ETSI20 = 0x75,
RTW_CHPLAN_FCC2_FCC11 = 0x76,
RTW_CHPLAN_WORLD_ETSI21 = 0x77,
RTW_CHPLAN_FCC1_FCC18 = 0x78,
RTW_CHPLAN_MKK2_MKK1 = 0x79,
RTW_CHPLAN_MAX,
RTW_CHPLAN_REALTEK_DEFINE = 0x7F,
RTW_CHPLAN_UNSPECIFIED = 0xFF,
} RT_CHANNEL_DOMAIN, *PRT_CHANNEL_DOMAIN;
bool rtw_chplan_is_empty(u8 id);
#define rtw_is_channel_plan_valid(chplan) (((chplan) < RTW_CHPLAN_MAX || (chplan) == RTW_CHPLAN_REALTEK_DEFINE) && !rtw_chplan_is_empty(chplan))
#define rtw_is_legacy_channel_plan(chplan) ((chplan) < 0x20)
typedef struct _RT_CHANNEL_PLAN {
unsigned char Channel[MAX_CHANNEL_NUM];
unsigned char Len;
} RT_CHANNEL_PLAN, *PRT_CHANNEL_PLAN;
struct ch_list_t {
u8 *len_ch;
};
#define CH_LIST_ENT(_len, arg...) \
{.len_ch = (u8[_len + 1]) {_len, ##arg}, }
#define CH_LIST_LEN(_ch_list) (_ch_list.len_ch[0])
#define CH_LIST_CH(_ch_list, _i) (_ch_list.len_ch[_i + 1])
typedef struct _RT_CHANNEL_PLAN_MAP {
u8 Index2G;
#ifdef CONFIG_IEEE80211_BAND_5GHZ
u8 Index5G;
#endif
u8 regd; /* value of REGULATION_TXPWR_LMT */
} RT_CHANNEL_PLAN_MAP, *PRT_CHANNEL_PLAN_MAP;
#ifdef CONFIG_IEEE80211_BAND_5GHZ
#define CHPLAN_ENT(i2g, i5g, regd) {i2g, i5g, regd}
#else
#define CHPLAN_ENT(i2g, i5g, regd) {i2g, regd}
#endif
enum Associated_AP {
atherosAP = 0,
broadcomAP = 1,
@@ -262,6 +127,24 @@ typedef enum _HT_IOT_PEER {
HT_IOT_PEER_MAX = 18
} HT_IOT_PEER_E, *PHTIOT_PEER_E;
typedef enum _RT_HT_INF0_CAP {
RT_HT_CAP_USE_TURBO_AGGR = 0x01,
RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
RT_HT_CAP_USE_AMPDU = 0x04,
RT_HT_CAP_USE_WOW = 0x8,
RT_HT_CAP_USE_SOFTAP = 0x10,
RT_HT_CAP_USE_92SE = 0x20,
RT_HT_CAP_USE_88C_92C = 0x40,
RT_HT_CAP_USE_AP_CLIENT_MODE = 0x80, /* AP team request to reserve this bit, by Emily */
} RT_HT_INF0_CAPBILITY, *PRT_HT_INF0_CAPBILITY;
typedef enum _RT_HT_INF1_CAP {
RT_HT_CAP_USE_VIDEO_CLIENT = 0x01,
RT_HT_CAP_USE_JAGUAR_BCUT = 0x02,
RT_HT_CAP_USE_JAGUAR_CCUT = 0x04,
} RT_HT_INF1_CAPBILITY, *PRT_HT_INF1_CAPBILITY;
struct mlme_handler {
unsigned int num;
char *str;
@@ -325,7 +208,12 @@ struct ss_res {
u8 igi_before_scan; /* used for restoring IGI value without enable DIG & FA_CNT */
#ifdef CONFIG_SCAN_BACKOP
u8 backop_flags_sta; /* policy for station mode*/
#ifdef CONFIG_AP_MODE
u8 backop_flags_ap; /* policy for ap mode */
#endif
#ifdef CONFIG_RTW_MESH
u8 backop_flags_mesh; /* policy for mesh mode */
#endif
u8 backop_flags; /* per backop runtime decision */
u8 scan_cnt;
u8 scan_cnt_max;
@@ -427,6 +315,7 @@ struct mlme_ext_info {
u32 link_count;
u32 auth_seq;
u32 auth_algo; /* 802.11 auth, could be open, shared, auto */
u16 auth_status;
u32 authModeToggle;
u32 enc_algo;/* encrypt algorithm; */
u32 key_index; /* this is only valid for legendary wep, 0~3 for key id. */
@@ -466,6 +355,11 @@ struct mlme_ext_info {
struct HT_caps_element HT_caps;
struct HT_info_element HT_info;
WLAN_BSSID_EX network;/* join network or bss_network, if in ap mode, it is the same to cur_network.network */
#ifdef ROKU_PRIVATE
/*infra mode, store supported rates from AssocRsp*/
NDIS_802_11_RATES_EX SupportedRates_infra_ap;
u8 ht_vht_received;/*ht_vht_received used to show debug msg BIT(0):HT BIT(1):VHT */
#endif /* ROKU_PRIVATE */
};
/* The channel information about this channel including joining, scanning, and power constraints. */
@@ -484,15 +378,8 @@ typedef struct _RT_CHANNEL_INFO {
#endif
u8 hidden_bss_cnt; /* per scan count */
#endif
#ifdef CONFIG_RTW_MESH
#if CONFIG_RTW_MESH_OFFCH_CAND
u8 mesh_candidate_cnt; /* update at scan done for specific mesh iface */
#endif
#endif /* CONFIG_RTW_MESH */
} RT_CHANNEL_INFO, *PRT_CHANNEL_INFO;
#define DFS_MASTER_TIMER_MS 100
#define CAC_TIME_MS (60*1000)
#define CAC_TIME_CE_MS (10*60*1000)
#define NON_OCP_TIME_MS (30*60*1000)
@@ -506,19 +393,21 @@ void rtw_rfctl_deinit(_adapter *adapter);
#ifdef CONFIG_DFS_MASTER
struct rf_ctl_t;
#define CH_IS_NON_OCP(rt_ch_info) (rtw_time_after((rt_ch_info)->non_ocp_end_time, rtw_get_current_time()))
bool rtw_is_cac_reset_needed(_adapter *adapter, u8 ch, u8 bw, u8 offset);
bool rtw_is_cac_reset_needed(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset);
bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset);
bool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl);
bool rtw_rfctl_is_tx_blocked_by_ch_waiting(struct rf_ctl_t *rfctl);
bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset);
bool rtw_chset_is_chbw_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset);
bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch);
void rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset);
void rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms);
u32 rtw_get_ch_waiting_ms(_adapter *adapter, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms);
void rtw_reset_cac(_adapter *adapter, u8 ch, u8 bw, u8 offset);
u32 rtw_force_stop_cac(_adapter *adapter, u32 timeout_ms);
u32 rtw_get_ch_waiting_ms(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms);
void rtw_reset_cac(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset);
u32 rtw_force_stop_cac(struct rf_ctl_t *rfctl, u32 timeout_ms);
#else
#define CH_IS_NON_OCP(rt_ch_info) 0
#define rtw_chset_is_ch_non_ocp(ch_set, ch, bw, offset) _FALSE
#define rtw_chset_is_chbw_non_ocp(ch_set, ch, bw, offset) _FALSE
#define rtw_chset_is_ch_non_ocp(ch_set, ch) _FALSE
#define rtw_rfctl_is_tx_blocked_by_ch_waiting(rfctl) _FALSE
#endif
@@ -532,16 +421,12 @@ enum {
RTW_CHF_NON_OCP = BIT6,
};
bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 sel_ch, u8 max_bw
bool rtw_choose_shortest_waiting_ch(struct rf_ctl_t *rfctl, u8 sel_ch, u8 max_bw
, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset
, u8 d_flags, u8 cur_ch, u8 same_band_prefer);
, u8 d_flags, u8 cur_ch, u8 same_band_prefer, u8 mesh_only);
void dump_country_chplan(void *sel, const struct country_chplan *ent);
void dump_country_chplan_map(void *sel);
void dump_chplan_id_list(void *sel);
void dump_chplan_test(void *sel);
void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set);
void dump_cur_chset(void *sel, _adapter *adapter);
void dump_cur_chset(void *sel, struct rf_ctl_t *rfctl);
int rtw_chset_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch);
u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset);
@@ -637,15 +522,16 @@ struct mlme_ext_priv {
u32 retry; /* retry for issue probereq */
u64 TSFValue;
/* for LPS-32K to adaptive bcn early and timeout */
u8 adaptive_tsf_done;
u32 bcn_delay_cnt[9];
u32 bcn_delay_ratio[9];
u32 bcn_cnt;
u8 DrvBcnEarly;
u8 DrvBcnTimeOut;
u32 last_bcn_cnt;
u8 cur_bcn_cnt;/*2s*/
u8 dtim;/*DTIM Period*/
#ifdef DBG_RX_BCN
u8 tim[4];
#endif
#ifdef CONFIG_BCN_RECV_TIME
u16 bcn_rx_time;
#endif
#ifdef CONFIG_AP_MODE
unsigned char bstart_bss;
#endif
@@ -663,8 +549,34 @@ struct mlme_ext_priv {
#ifdef DBG_FIXED_CHAN
u8 fixed_chan;
#endif
/* set hw sync bcn tsf register or not */
u8 en_hw_update_tsf;
u8 tsf_update_required:1;
u8 en_hw_update_tsf:1; /* set hw sync bcn tsf register or not */
systime tsf_update_pause_stime;
u8 tsf_update_pause_factor; /* num of bcn intervals to stay TSF update pause status */
u8 tsf_update_restore_factor; /* num of bcn interval to stay TSF update restore status */
#ifdef CONFIG_SUPPORT_STATIC_SMPS
u8 ssmps_en;
u16 ssmps_tx_tp_th;/*Mbps*/
u16 ssmps_rx_tp_th;/*Mbps*/
#ifdef DBG_STATIC_SMPS
u8 ssmps_test;
u8 ssmps_test_en;
#endif
#endif
#ifdef CONFIG_CTRL_TXSS_BY_TP
u8 txss_ctrl_en;
u16 txss_tp_th;/*Mbps*/
u8 txss_tp_chk_cnt;/*unit 2s*/
u8 txss_1ss;
u8 txss_momi_type_bk;
#endif
};
struct support_rate_handler {
u8 rate;
bool basic;
bool existence;
};
static inline u8 check_mlmeinfo_state(struct mlme_ext_priv *plmeext, sint state)
@@ -712,13 +624,6 @@ void sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state);
do { \
((mlmeext)->sitesurvey_res.backop_flags_sta = (flags)); \
} while (0)
#define mlmeext_scan_backop_flags_ap(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_ap)
#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_ap & (flags))
#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) \
do { \
((mlmeext)->sitesurvey_res.backop_flags_ap = (flags)); \
} while (0)
#else
#define mlmeext_scan_backop_flags(mlmeext) (0)
#define mlmeext_chk_scan_backop_flags(mlmeext, flags) (0)
@@ -727,11 +632,34 @@ void sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state);
#define mlmeext_scan_backop_flags_sta(mlmeext) (0)
#define mlmeext_chk_scan_backop_flags_sta(mlmeext, flags) (0)
#define mlmeext_assign_scan_backop_flags_sta(mlmeext, flags) do {} while (0)
#endif /* CONFIG_SCAN_BACKOP */
#if defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE)
#define mlmeext_scan_backop_flags_ap(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_ap)
#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_ap & (flags))
#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) \
do { \
((mlmeext)->sitesurvey_res.backop_flags_ap = (flags)); \
} while (0)
#else
#define mlmeext_scan_backop_flags_ap(mlmeext) (0)
#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) (0)
#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) do {} while (0)
#endif
#endif /* defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE) */
#if defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_RTW_MESH)
#define mlmeext_scan_backop_flags_mesh(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_mesh)
#define mlmeext_chk_scan_backop_flags_mesh(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_mesh & (flags))
#define mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags) \
do { \
((mlmeext)->sitesurvey_res.backop_flags_mesh = (flags)); \
} while (0)
#else
#define mlmeext_scan_backop_flags_mesh(mlmeext) (0)
#define mlmeext_chk_scan_backop_flags_mesh(mlmeext, flags) (0)
#define mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags) do {} while (0)
#endif /* defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_RTW_MESH) */
u32 rtw_scan_timeout_decision(_adapter *padapter);
void init_mlme_default_rate_set(_adapter *padapter);
@@ -800,6 +728,13 @@ int is_client_associated_to_ibss(_adapter *padapter);
int is_IBSS_empty(_adapter *padapter);
unsigned char check_assoc_AP(u8 *pframe, uint len);
void get_assoc_AP_Vendor(char *vendor, u8 assoc_AP_vendor);
#ifdef CONFIG_RTS_FULL_BW
void rtw_parse_sta_vendor_ie_8812(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len);
#endif/*CONFIG_RTS_FULL_BW*/
#ifdef CONFIG_80211AC_VHT
unsigned char get_vht_mu_bfer_cap(u8 *pframe, uint len);
#endif
int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
#ifdef CONFIG_WFD
@@ -809,13 +744,24 @@ void rtw_process_wfd_ies(_adapter *adapter, u8 *ies, u8 ies_len, const char *tag
void WMMOnAssocRsp(_adapter *padapter);
void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
#ifdef ROKU_PRIVATE
void HT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
#endif
void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
void HTOnAssocRsp(_adapter *padapter);
#ifdef ROKU_PRIVATE
void Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
void Extended_Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
#endif
void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
void VCS_update(_adapter *padapter, struct sta_info *psta);
void update_ldpc_stbc_cap(struct sta_info *psta);
bool rtw_validate_value(u16 EID, u8 *p, u16 len);
bool hidden_ssid_ap(WLAN_BSSID_EX *snetwork);
void rtw_absorb_ssid_ifneed(_adapter *padapter, WLAN_BSSID_EX *bssid, u8 *pframe);
int rtw_get_bcn_keys(ADAPTER *Adapter, u8 *pframe, u32 packet_len,
struct beacon_keys *recv_beacon);
int validate_beacon_len(u8 *pframe, uint len);
@@ -849,6 +795,8 @@ unsigned int is_ap_in_tkip(_adapter *padapter);
unsigned int is_ap_in_wep(_adapter *padapter);
unsigned int should_forbid_n_rate(_adapter *padapter);
void parsing_eapol_packet(_adapter *padapter, u8 *key_payload, struct sta_info *psta, u8 trx_type);
bool _rtw_camctl_chk_cap(_adapter *adapter, u8 cap);
void _rtw_camctl_set_flags(_adapter *adapter, u32 flags);
void rtw_camctl_set_flags(_adapter *adapter, u32 flags);
@@ -906,7 +854,7 @@ bool rtw_tim_map_anyone_be_set(_adapter *padapter, const u8 *map);
bool rtw_tim_map_anyone_be_set_exclude_aid0(_adapter *padapter, const u8 *map);
#endif /* CONFIG_AP_MODE */
u32 report_join_res(_adapter *padapter, int res);
u32 report_join_res(_adapter *padapter, int aid_res, u16 status);
void report_survey_event(_adapter *padapter, union recv_frame *precv_frame);
void report_surveydone_event(_adapter *padapter);
u32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, bool enqueue, u8 locally_generated);
@@ -1059,6 +1007,10 @@ void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta);
void linked_status_chk(_adapter *padapter, u8 from_timer);
#define rtw_get_bcn_cnt(adapter) (adapter->mlmeextpriv.cur_bcn_cnt)
#define rtw_get_bcn_dtim_period(adapter) (adapter->mlmeextpriv.dtim)
void rtw_collect_bcn_info(_adapter *adapter);
void _linked_info_dump(_adapter *padapter);
void survey_timer_hdl(void *ctx);
@@ -1097,8 +1049,10 @@ extern int cckratesonly_included(unsigned char *rate, int ratelen);
extern void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr);
extern void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len);
extern void correct_TSF(_adapter *padapter, struct mlme_ext_priv *pmlmeext);
extern void adaptive_early_32k(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len);
extern void correct_TSF(_adapter *padapter, u8 mlme_state);
#ifdef CONFIG_BCN_RECV_TIME
void rtw_rx_bcn_time_update(_adapter *adapter, uint bcn_len, u8 data_rate);
#endif
extern u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer);
void rtw_process_bar_frame(_adapter *padapter, union recv_frame *precv_frame);
@@ -1226,7 +1180,7 @@ struct cmd_hdl wlancmds[] = {
GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelPlan_param), set_chplan_hdl) /*59*/
GEN_MLME_EXT_HANDLER(sizeof(struct LedBlink_param), led_blink_hdl) /*60*/
GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelSwitch_param), set_csa_hdl) /*61*/
GEN_MLME_EXT_HANDLER(0, set_csa_hdl) /*61*/
GEN_MLME_EXT_HANDLER(sizeof(struct TDLSoption_param), tdls_hdl) /*62*/
GEN_MLME_EXT_HANDLER(0, chk_bmc_sleepq_hdl) /*63*/
GEN_MLME_EXT_HANDLER(sizeof(struct RunInThread_param), run_in_thread_hdl) /*64*/

2
include/rtw_mp.h
View File

@@ -352,6 +352,7 @@ struct mp_priv {
u32 rx_pktloss;
BOOLEAN rx_bindicatePkt;
struct recv_stat rxstat;
BOOLEAN brx_filter_beacon;
/* RF/BB relative */
u8 channel;
@@ -422,6 +423,7 @@ struct mp_priv {
u8 *TXradomBuffer;
u8 CureFuseBTCoex;
};
typedef struct _IOCMD_STRUCT_ {

7
include/rtw_odm.h
View File

@@ -77,18 +77,19 @@ void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter);
bool rtw_odm_adaptivity_needed(_adapter *adapter);
void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter);
void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff, s8 th_l2h_ini_mode2, s8 th_edcca_hl_diff_mode2, u8 edcca_enable);
void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff);
void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter);
void rtw_odm_acquirespinlock(_adapter *adapter, enum rt_spinlock_type type);
void rtw_odm_releasespinlock(_adapter *adapter, enum rt_spinlock_type type);
u8 rtw_odm_get_dfs_domain(_adapter *adapter);
u8 rtw_odm_dfs_domain_unknown(_adapter *adapter);
u8 rtw_odm_get_dfs_domain(struct dvobj_priv *dvobj);
u8 rtw_odm_dfs_domain_unknown(struct dvobj_priv *dvobj);
#ifdef CONFIG_DFS_MASTER
VOID rtw_odm_radar_detect_reset(_adapter *adapter);
VOID rtw_odm_radar_detect_disable(_adapter *adapter);
VOID rtw_odm_radar_detect_enable(_adapter *adapter);
BOOLEAN rtw_odm_radar_detect(_adapter *adapter);
u8 rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv *dvobj);
#endif /* CONFIG_DFS_MASTER */
void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys);

7
include/rtw_p2p.h
View File

@@ -102,11 +102,8 @@ static inline void _rtw_p2p_restore_state(struct wifidirect_info *wdinfo)
}
}
#endif
static inline void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role)
{
if (wdinfo->role != role)
wdinfo->role = role;
}
void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role);
static inline int _rtw_p2p_state(struct wifidirect_info *wdinfo)
{
return wdinfo->p2p_state;

29
include/rtw_pwrctrl.h
View File

@@ -305,7 +305,9 @@ struct aoac_report {
u8 security_type;
u8 wow_pattern_idx;
u8 version_info;
u8 reserved[4];
u8 rekey_ok:1;
u8 dummy:7;
u8 reserved[3];
u8 rxptk_iv[8];
u8 rxgtk_iv[4][8];
};
@@ -317,11 +319,23 @@ struct pwrctrl_priv {
volatile u8 cpwm; /* fw current power state. updated when 1. read from HCPWM 2. driver lowers power level */
volatile u8 tog; /* toggling */
volatile u8 cpwm_tog; /* toggling */
u8 rpwm_retry;
u8 pwr_mode;
u8 smart_ps;
u8 bcn_ant_mode;
u8 dtim;
#ifdef CONFIG_LPS_CHK_BY_TP
u8 lps_chk_by_tp;
u16 lps_tx_tp_th;/*Mbps*/
u16 lps_rx_tp_th;/*Mbps*/
u16 lps_bi_tp_th;/*Mbps*//*TRX TP*/
int lps_chk_cnt_th;
int lps_chk_cnt;
u32 lps_tx_pkts;
u32 lps_rx_pkts;
#endif
#ifdef CONFIG_WMMPS_STA
u8 wmm_smart_ps;
@@ -397,6 +411,7 @@ struct pwrctrl_priv {
#ifdef CONFIG_GPIO_WAKEUP
u8 is_high_active;
#endif /* CONFIG_GPIO_WAKEUP */
u8 hst2dev_high_active;
#ifdef CONFIG_WOWLAN
bool default_patterns_en;
#ifdef CONFIG_IPV6
@@ -529,16 +544,22 @@ rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter);
#endif
#ifdef DBG_CHECK_FW_PS_STATE
int rtw_fw_ps_state(PADAPTER padapter);
#endif
#ifdef CONFIG_LPS
s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms);
void LPS_Enter(PADAPTER padapter, const char *msg);
void LPS_Leave(PADAPTER padapter, const char *msg);
#ifdef CONFIG_CHECK_LEAVE_LPS
#ifdef CONFIG_LPS_CHK_BY_TP
void traffic_check_for_leave_lps_by_tp(PADAPTER padapter, u8 tx, struct sta_info *sta);
#endif
void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets);
#endif /*CONFIG_CHECK_LEAVE_LPS*/
void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg);
void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable);
void rtw_set_rpwm(_adapter *padapter, u8 val8);
u8 rtw_set_rpwm(_adapter *padapter, u8 val8);
void rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en);
#endif
@@ -583,4 +604,6 @@ void rtw_wow_pattern_sw_reset(_adapter *adapter);
u8 rtw_set_default_pattern(_adapter *adapter);
void rtw_wow_pattern_sw_dump(_adapter *adapter);
#endif /* CONFIG_WOWLAN */
void rtw_ssmps_enter(_adapter *adapter, struct sta_info *sta);
void rtw_ssmps_leave(_adapter *adapter, struct sta_info *sta);
#endif /* __RTL871X_PWRCTRL_H_ */

33
include/rtw_recv.h
View File

@@ -84,20 +84,10 @@
#define RX_CMD_QUEUE 1
#define RX_MAX_QUEUE 2
static u8 SNAP_ETH_TYPE_IPX[2] = {0x81, 0x37};
static u8 SNAP_ETH_TYPE_APPLETALK_AARP[2] = {0x80, 0xf3};
static u8 SNAP_ETH_TYPE_APPLETALK_DDP[2] = {0x80, 0x9b};
static u8 SNAP_ETH_TYPE_TDLS[2] = {0x89, 0x0d};
static u8 SNAP_HDR_APPLETALK_DDP[3] = {0x08, 0x00, 0x07}; /* Datagram Delivery Protocol */
static u8 oui_8021h[] = {0x00, 0x00, 0xf8};
static u8 oui_rfc1042[] = {0x00, 0x00, 0x00};
#define MAX_SUBFRAME_COUNT 64
static u8 rtw_rfc1042_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 };
/* Bridge-Tunnel header (for EtherTypes ETH_P_AARP and ETH_P_IPX) */
static u8 rtw_bridge_tunnel_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 };
extern u8 rtw_bridge_tunnel_header[];
extern u8 rtw_rfc1042_header[];
/* for Rx reordering buffer control */
struct recv_reorder_ctrl {
@@ -221,6 +211,12 @@ struct rx_pkt_attrib {
u8 ppdu_cnt;
u32 free_cnt; /* free run counter */
struct phydm_phyinfo_struct phy_info;
#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
/* checksum offload realted varaiables */
u8 csum_valid; /* Checksum valid, 0: not check, 1: checked */
u8 csum_err; /* Checksum Error occurs */
#endif /* CONFIG_TCP_CSUM_OFFLOAD_RX */
};
#ifdef CONFIG_RTW_MESH
@@ -236,7 +232,11 @@ struct rx_pkt_attrib {
/* #define REORDER_ENTRY_NUM 128 */
#define REORDER_WAIT_TIME (50) /* (ms) */
#define RECVBUFF_ALIGN_SZ 8
#if defined(CONFIG_PLATFORM_RTK390X) && defined(CONFIG_USB_HCI)
#define RECVBUFF_ALIGN_SZ 32
#else
#define RECVBUFF_ALIGN_SZ 8
#endif
#ifdef CONFIG_TRX_BD_ARCH
#define RX_WIFI_INFO_SIZE 24
@@ -864,15 +864,8 @@ __inline static s32 translate_percentage_to_dbm(u32 SignalStrengthIndex)
{
s32 SignalPower; /* in dBm. */
#ifdef CONFIG_SIGNAL_SCALE_MAPPING
/* Translate to dBm (x=0.5y-95). */
SignalPower = (s32)((SignalStrengthIndex + 1) >> 1);
SignalPower -= 95;
#else
/* Translate to dBm (x=y-100) */
SignalPower = SignalStrengthIndex - 100;
#endif
return SignalPower;
}

43
include/rtw_rf.h
View File

@@ -16,7 +16,9 @@
#define __RTW_RF_H_
#define NumRates (13)
#define B_MODE_RATE_NUM (4)
#define G_MODE_RATE_NUM (8)
#define G_MODE_BASIC_RATE_NUM (3)
/* slot time for 11g */
#define SHORT_SLOT_TIME 9
#define NON_SHORT_SLOT_TIME 20
@@ -149,45 +151,6 @@ int rtw_ch2freq(int chan);
int rtw_freq2ch(int freq);
bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo);
#define RTW_MODULE_RTL8821AE_HMC_M2 BIT0 /* RTL8821AE(HMC + M.2) */
#define RTW_MODULE_RTL8821AU BIT1 /* RTL8821AU */
#define RTW_MODULE_RTL8812AENF_NGFF BIT2 /* RTL8812AENF(8812AE+8761)_NGFF */
#define RTW_MODULE_RTL8812AEBT_HMC BIT3 /* RTL8812AEBT(8812AE+8761)_HMC */
#define RTW_MODULE_RTL8188EE_HMC_M2 BIT4 /* RTL8188EE(HMC + M.2) */
#define RTW_MODULE_RTL8723BE_HMC_M2 BIT5 /* RTL8723BE(HMC + M.2) */
#define RTW_MODULE_RTL8723BS_NGFF1216 BIT6 /* RTL8723BS(NGFF1216) */
#define RTW_MODULE_RTL8192EEBT_HMC_M2 BIT7 /* RTL8192EEBT(8192EE+8761AU)_(HMC + M.2) */
#define RTW_MODULE_RTL8723DE_NGFF1630 BIT8 /* RTL8723DE(NGFF1630) */
#define RTW_MODULE_RTL8822BE BIT9 /* RTL8822BE */
#define RTW_MODULE_RTL8821CE BIT10 /* RTL8821CE */
#define IS_ALPHA2_NO_SPECIFIED(_alpha2) ((*((u16 *)(_alpha2))) == 0xFFFF)
struct country_chplan {
char alpha2[2];
u8 chplan;
#ifdef CONFIG_80211AC_VHT
u8 en_11ac;
#endif
#if RTW_DEF_MODULE_REGULATORY_CERT
u16 def_module_flags; /* RTW_MODULE_RTLXXX */
#endif
};
#ifdef CONFIG_80211AC_VHT
#define COUNTRY_CHPLAN_EN_11AC(_ent) ((_ent)->en_11ac)
#else
#define COUNTRY_CHPLAN_EN_11AC(_ent) 0
#endif
#if RTW_DEF_MODULE_REGULATORY_CERT
#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) ((_ent)->def_module_flags)
#else
#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) 0
#endif
const struct country_chplan *rtw_get_chplan_from_country(const char *country_code);
struct rf_ctl_t;
typedef enum _REGULATION_TXPWR_LMT {

4
include/rtw_version.h
View File

@@ -1,2 +1,2 @@
#define DRIVERVERSION "v5.3.1_27678.20180430_COEX20180427-5959"
#define BTCOEXVERSION "COEX20180427-5959"
#define DRIVERVERSION "v5.6.1_30362.20181109_COEX20180928-6a6a"
#define BTCOEXVERSION "COEX20180928-6a6a"

18
include/rtw_vht.h
View File

@@ -121,6 +121,7 @@ struct vht_priv {
u8 ldpc_cap;
u8 stbc_cap;
u16 beamform_cap;
u8 ap_is_mu_bfer;
u8 sgi_80m;/* short GI */
u8 ampdu_len;
@@ -136,6 +137,20 @@ struct vht_priv {
u8 vht_op_mode_notify;
};
#ifdef ROKU_PRIVATE
struct vht_priv_infra_ap {
/* Infra mode, only store for AP's info, not intersection of STA and AP*/
u8 ldpc_cap_infra_ap;
u8 stbc_cap_infra_ap;
u16 beamform_cap_infra_ap;
u8 vht_mcs_map_infra_ap[2];
u8 vht_mcs_map_tx_infra_ap[2];
u8 channel_width_infra_ap;
u8 number_of_streams_infra_ap;
};
#endif /* ROKU_PRIVATE */
u8 rtw_get_vht_highest_rate(u8 *pvht_mcs_map);
u16 rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate);
u64 rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss);
@@ -146,6 +161,9 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf);
void update_sta_vht_info_apmode(_adapter *padapter, PVOID psta);
void update_hw_vht_param(_adapter *padapter);
void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
#ifdef ROKU_PRIVATE
void VHT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
#endif /* ROKU_PRIVATE */
void VHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta);
u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len);

4
include/rtw_wifi_regd.h
View File

@@ -28,7 +28,7 @@ enum country_code_type_t {
COUNTRY_CODE_MAX
};
int rtw_regd_init(_adapter *padapter);
void rtw_reg_notify_by_driver(_adapter *adapter);
void rtw_regd_apply_flags(struct wiphy *wiphy);
int rtw_regd_init(struct wiphy *wiphy);
#endif /* __RTW_WIFI_REGD_H__ */

45
include/rtw_xmit.h
View File

@@ -27,6 +27,7 @@
#if defined CONFIG_SDIO_HCI
#define NR_XMITBUFF (16)
#define SDIO_TX_DIV_NUM (2)
#endif
#if defined(CONFIG_GSPI_HCI)
#define NR_XMITBUFF (128)
@@ -91,6 +92,8 @@
#define MAX_CMDBUF_SZ (5120) /* (4096) */
#endif
#define MAX_BEACON_LEN 512
#define MAX_NUMBLKS (1)
#define XMIT_VO_QUEUE (0)
@@ -182,7 +185,8 @@
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) ||\
defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8192E) ||\
defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8703B) ||\
defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8723D)
defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D) ||\
defined(CONFIG_RTL8710B) || defined(CONFIG_RTL8192F)
#define TXDESC_SIZE 40
#elif defined(CONFIG_RTL8822B)
#define TXDESC_SIZE 48 /* HALMAC_TX_DESC_SIZE_8822B */
@@ -236,7 +240,8 @@ enum TXDESC_SC {
#define TXDESC_64_BYTES
#endif
#elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8723B) \
|| defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8723D)
|| defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D) \
|| defined(CONFIG_RTL8192F)
#define TXDESC_40_BYTES
#endif
@@ -390,9 +395,6 @@ struct pkt_attrib {
u16 seqnum;
struct sta_info *psta;
#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
u8 hw_tcp_csum;
#endif
};
#else
/* reduce size */
@@ -435,6 +437,9 @@ struct pkt_attrib {
#endif
u8 mfwd_ttl;
u32 mseq;
#endif
#ifdef CONFIG_TX_CSUM_OFFLOAD
u8 hw_csum;
#endif
u8 key_idx;
u8 qos_en;
@@ -464,9 +469,6 @@ struct pkt_attrib {
#endif /* CONFIG_WMMPS_STA */
struct sta_info *psta;
#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
u8 hw_tcp_csum;
#endif
u8 rtsen;
u8 cts2self;
@@ -905,6 +907,30 @@ extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8822be(struct xmit_priv *pxmi
extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8821ce(struct xmit_priv *pxmitpriv,
enum cmdbuf_type buf_type);
#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8821ce(p, CMDBUF_BEACON)
#elif defined(CONFIG_RTL8192F) && defined(CONFIG_PCI_HCI)
extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8192fe(struct xmit_priv *pxmitpriv,
enum cmdbuf_type buf_type);
#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8192fe(p, CMDBUF_BEACON)
#elif defined(CONFIG_RTL8812A) && defined(CONFIG_PCI_HCI)
extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8812ae(struct xmit_priv *pxmitpriv,
enum cmdbuf_type buf_type);
#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8812ae(p, CMDBUF_BEACON)
#elif defined(CONFIG_RTL8723D) && defined(CONFIG_PCI_HCI)
extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8723de(struct xmit_priv *pxmitpriv,
enum cmdbuf_type buf_type);
#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8723de(p, CMDBUF_BEACON)
#elif defined(CONFIG_RTL8723B) && defined(CONFIG_PCI_HCI)
extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8723be(struct xmit_priv *pxmitpriv,
enum cmdbuf_type buf_type);
#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8723be(p, CMDBUF_BEACON)
#elif defined(CONFIG_RTL8814A) && defined(CONFIG_PCI_HCI)
extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8814ae(struct xmit_priv *pxmitpriv,
enum cmdbuf_type buf_type);
#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8814ae(p, CMDBUF_BEACON)
#elif defined(CONFIG_RTL8188E) && defined(CONFIG_PCI_HCI)
extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8188ee(struct xmit_priv *pxmitpriv,
enum cmdbuf_type buf_type);
#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8188ee(p, CMDBUF_BEACON)
#else
#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_BEACON)
#endif
@@ -917,8 +943,6 @@ extern s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitb
void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz);
extern void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len);
static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta);
static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta);
#ifdef CONFIG_WMMPS_STA
static void update_attrib_trigger_frame_info(_adapter *padapter, struct pkt_attrib *pattrib);
@@ -1022,7 +1046,6 @@ void rtw_tx_desc_backup_reset(void);
u8 rtw_get_tx_desc_backup(_adapter *padapter, u8 hwq, struct rtw_tx_desc_backup **pbak);
#endif
static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib);
u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe);
#ifdef CONFIG_XMIT_ACK

8
include/sdio_hal.h
View File

@@ -46,4 +46,12 @@ void rtl8723ds_set_hal_ops(PADAPTER padapter);
void rtl8188fs_set_hal_ops(PADAPTER padapter);
#endif
#ifdef CONFIG_RTL8188GTV
void rtl8188gtvs_set_hal_ops(PADAPTER padapter);
#endif
#ifdef CONFIG_RTL8192F
void rtl8192fs_set_hal_ops(PADAPTER padapter);
#endif
#endif /* __SDIO_HAL_H__ */

27
include/sdio_ops.h
View File

@@ -146,6 +146,20 @@ extern void ClearInterrupt8723DSdio(PADAPTER padapter);
#endif /* CONFIG_WOWLAN */
#endif
#ifdef CONFIG_RTL8192F
extern void InitInterrupt8192FSdio(PADAPTER padapter);
extern void InitSysInterrupt8192FSdio(PADAPTER padapter);
extern void EnableInterrupt8192FSdio(PADAPTER padapter);
extern void DisableInterrupt8192FSdio(PADAPTER padapter);
extern void UpdateInterruptMask8192FSdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);
extern u8 HalQueryTxBufferStatus8192FSdio(PADAPTER padapter);
extern u8 HalQueryTxOQTBufferStatus8192FSdio(PADAPTER padapter);
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
extern void DisableInterruptButCpwm2192fSdio(PADAPTER padapter);
extern void ClearInterrupt8192FSdio(PADAPTER padapter);
#endif /* CONFIG_WOWLAN */
#endif
#ifdef CONFIG_RTL8188F
extern void InitInterrupt8188FSdio(PADAPTER padapter);
extern void InitSysInterrupt8188FSdio(PADAPTER padapter);
@@ -159,6 +173,19 @@ extern void ClearInterrupt8188FSdio(PADAPTER padapter);
#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */
#endif
#ifdef CONFIG_RTL8188GTV
extern void InitInterrupt8188GTVSdio(PADAPTER padapter);
extern void InitSysInterrupt8188GTVSdio(PADAPTER padapter);
extern void EnableInterrupt8188GTVSdio(PADAPTER padapter);
extern void DisableInterrupt8188GTVSdio(PADAPTER padapter);
extern u8 HalQueryTxBufferStatus8188GTVSdio(PADAPTER padapter);
extern u8 HalQueryTxOQTBufferStatus8188GTVSdio(PADAPTER padapter);
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
extern void DisableInterruptButCpwm28188GTVSdio(PADAPTER padapter);
extern void ClearInterrupt8188GTVSdio(PADAPTER padapter);
#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */
#endif
/**
* rtw_sdio_get_block_size() - Get block size of SDIO transfer
* @d struct dvobj_priv*

64
include/sta_info.h
View File

@@ -99,27 +99,27 @@ struct stainfo_stats {
systime last_rx_time;
u64 rx_mgnt_pkts;
u64 rx_beacon_pkts;
u64 rx_probereq_pkts;
u64 rx_probersp_pkts; /* unicast to self */
u64 rx_probersp_bm_pkts;
u64 rx_probersp_uo_pkts; /* unicast to others */
u64 rx_beacon_pkts;
u64 rx_probereq_pkts;
u64 rx_probersp_pkts; /* unicast to self */
u64 rx_probersp_bm_pkts;
u64 rx_probersp_uo_pkts; /* unicast to others */
u64 rx_ctrl_pkts;
u64 rx_data_pkts;
u64 rx_data_bc_pkts;
u64 rx_data_mc_pkts;
u64 rx_data_bc_pkts;
u64 rx_data_mc_pkts;
u64 rx_data_qos_pkts[TID_NUM]; /* unicast only */
u64 last_rx_mgnt_pkts;
u64 last_rx_beacon_pkts;
u64 last_rx_probereq_pkts;
u64 last_rx_probersp_pkts; /* unicast to self */
u64 last_rx_probersp_bm_pkts;
u64 last_rx_probersp_uo_pkts; /* unicast to others */
u64 last_rx_beacon_pkts;
u64 last_rx_probereq_pkts;
u64 last_rx_probersp_pkts; /* unicast to self */
u64 last_rx_probersp_bm_pkts;
u64 last_rx_probersp_uo_pkts; /* unicast to others */
u64 last_rx_ctrl_pkts;
u64 last_rx_data_pkts;
u64 last_rx_data_bc_pkts;
u64 last_rx_data_mc_pkts;
u64 last_rx_data_bc_pkts;
u64 last_rx_data_mc_pkts;
u64 last_rx_data_qos_pkts[TID_NUM]; /* unicast only */
#ifdef CONFIG_TDLS
@@ -128,13 +128,14 @@ struct stainfo_stats {
#endif
u64 rx_bytes;
u64 rx_bc_bytes;
u64 rx_mc_bytes;
u64 rx_bc_bytes;
u64 rx_mc_bytes;
u64 last_rx_bytes;
u64 last_rx_bc_bytes;
u64 last_rx_mc_bytes;
u64 last_rx_bc_bytes;
u64 last_rx_mc_bytes;
u64 rx_drops; /* TBD */
u16 rx_tp_mbytes;
u32 rx_tp_kbits;
u32 smooth_rx_tp_kbits;
u64 tx_pkts;
u64 last_tx_pkts;
@@ -142,7 +143,13 @@ struct stainfo_stats {
u64 tx_bytes;
u64 last_tx_bytes;
u64 tx_drops; /* TBD */
u16 tx_tp_mbytes;
u32 tx_tp_kbits;
u32 smooth_tx_tp_kbits;
#ifdef CONFIG_LPS_CHK_BY_TP
u64 acc_tx_bytes;
u64 acc_rx_bytes;
#endif
/* unicast only */
u64 last_rx_data_uc_pkts; /* For Read & Clear requirement in proc_get_rx_stat() */
@@ -151,6 +158,10 @@ struct stainfo_stats {
u32 tx_ok_cnt; /* Read & Clear, in proc_get_tx_stat() */
u32 tx_fail_cnt; /* Read & Clear, in proc_get_tx_stat() */
u32 tx_retry_cnt; /* Read & Clear, in proc_get_tx_stat() */
#ifdef CONFIG_RTW_MESH
u32 rx_hwmp_pkts;
u32 last_rx_hwmp_pkts;
#endif
};
#ifndef DBG_SESSION_TRACKER
@@ -483,6 +494,9 @@ struct sta_info {
u8 max_agg_num_minimal_record; /*keep minimal tx desc max_agg_num setting*/
u8 curr_rx_rate;
u8 curr_rx_rate_bmc;
#ifdef CONFIG_RTS_FULL_BW
bool vendor_8812;
#endif
};
#ifdef CONFIG_RTW_MESH
@@ -555,6 +569,15 @@ struct sta_info {
#define sta_last_rx_probersp_uo_pkts(sta) \
(sta->sta_stats.last_rx_probersp_uo_pkts)
#ifdef CONFIG_RTW_MESH
#define update_last_rx_hwmp_pkts(sta) \
do { \
sta->sta_stats.last_rx_hwmp_pkts = sta->sta_stats.rx_hwmp_pkts; \
} while(0)
#else
#define update_last_rx_hwmp_pkts(sta) do {} while(0)
#endif
#define sta_update_last_rx_pkts(sta) \
do { \
int __i; \
@@ -566,6 +589,7 @@ struct sta_info {
sta->sta_stats.last_rx_probersp_bm_pkts = sta->sta_stats.rx_probersp_bm_pkts; \
sta->sta_stats.last_rx_probersp_uo_pkts = sta->sta_stats.rx_probersp_uo_pkts; \
sta->sta_stats.last_rx_ctrl_pkts = sta->sta_stats.rx_ctrl_pkts; \
update_last_rx_hwmp_pkts(sta); \
\
sta->sta_stats.last_rx_data_pkts = sta->sta_stats.rx_data_pkts; \
sta->sta_stats.last_rx_data_bc_pkts = sta->sta_stats.rx_data_bc_pkts; \

12
include/usb_hal.h
View File

@@ -48,6 +48,10 @@ void rtl8814au_set_hal_ops(_adapter *padapter);
void rtl8188fu_set_hal_ops(_adapter *padapter);
#endif
#ifdef CONFIG_RTL8188GTV
void rtl8188gtvu_set_hal_ops(_adapter *padapter);
#endif
#ifdef CONFIG_RTL8703B
void rtl8703bu_set_hal_ops(_adapter *padapter);
#endif
@@ -56,6 +60,14 @@ void rtl8703bu_set_hal_ops(_adapter *padapter);
void rtl8723du_set_hal_ops(_adapter *padapter);
#endif
#ifdef CONFIG_RTL8710B
void rtl8710bu_set_hal_ops(_adapter *padapter);
#endif
#ifdef CONFIG_RTL8192F
void rtl8192fu_set_hal_ops(_adapter *padapter);
#endif /* CONFIG_RTL8192F */
#ifdef CONFIG_INTEL_PROXIM
extern _adapter *rtw_usb_get_sw_pointer(void);
#endif /* CONFIG_INTEL_PROXIM */

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