RinCat/RTL88x2BU-Linux-Driver
1
0
Fork 0
mirror of https://github.com/RinCat/RTL88x2BU-Linux-Driver.git synced 2026-01-19 10:26:35 +00:00
Code Issues Packages Projects Releases Wiki Activity

Update to 5.6.1

Browse Source
This commit is contained in:
Rin Cat
2019-09-21 05:30:30 -04:00
parent 953142179e
commit 0644d0b316
413 changed files with 179115 additions and 110562 deletions
Download Patch File Download Diff File Expand all files Collapse all files

386
hal/phydm/txbf/halcomtxbf.c
View File

@@ -12,195 +12,175 @@
* more details.
*
*****************************************************************************/
/* ************************************************************
/*@************************************************************
* Description:
*
* This file is for TXBF mechanism
*
* ************************************************************ */
************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (BEAMFORMING_SUPPORT == 1)
/*Beamforming halcomtxbf API create by YuChen 2015/05*/
#ifdef PHYDM_BEAMFORMING_SUPPORT
/*@Beamforming halcomtxbf API create by YuChen 2015/05*/
void
hal_com_txbf_beamform_init(
void *dm_void
)
void hal_com_txbf_beamform_init(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
boolean is_iqgen_setting_ok = false;
struct dm_struct *dm = (struct dm_struct *)dm_void;
boolean is_iqgen_setting_ok = false;
if (dm->support_ic_type & ODM_RTL8814A) {
is_iqgen_setting_ok = phydm_beamforming_set_iqgen_8814A(dm);
PHYDM_DBG(dm, DBG_TXBF, "[%s] is_iqgen_setting_ok = %d\n", __func__, is_iqgen_setting_ok);
PHYDM_DBG(dm, DBG_TXBF, "[%s] is_iqgen_setting_ok = %d\n",
__func__, is_iqgen_setting_ok);
}
}
/*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/
void
hal_com_txbf_config_gtab(
void *dm_void
)
/*Only used for MU BFer Entry when get GID management frame (self as MU STA)*/
void hal_com_txbf_config_gtab(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_RTL8822B)
hal_txbf_8822b_config_gtab(dm);
}
void
phydm_beamform_set_sounding_enter(
void *dm_void
)
void phydm_beamform_set_sounding_enter(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_enter_work_item)) == false)
odm_schedule_work_item(&(p_txbf_info->txbf_enter_work_item));
if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_enter_work_item))
odm_schedule_work_item(&p_txbf_info->txbf_enter_work_item);
#else
hal_com_txbf_enter_work_item_callback(dm);
#endif
}
void
phydm_beamform_set_sounding_leave(
void *dm_void
)
void phydm_beamform_set_sounding_leave(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_leave_work_item)) == false)
odm_schedule_work_item(&(p_txbf_info->txbf_leave_work_item));
if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_leave_work_item))
odm_schedule_work_item(&p_txbf_info->txbf_leave_work_item);
#else
hal_com_txbf_leave_work_item_callback(dm);
#endif
}
void
phydm_beamform_set_sounding_rate(
void *dm_void
)
void phydm_beamform_set_sounding_rate(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_rate_work_item)) == false)
odm_schedule_work_item(&(p_txbf_info->txbf_rate_work_item));
if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_rate_work_item))
odm_schedule_work_item(&p_txbf_info->txbf_rate_work_item);
#else
hal_com_txbf_rate_work_item_callback(dm);
#endif
}
void
phydm_beamform_set_sounding_status(
void *dm_void
)
void phydm_beamform_set_sounding_status(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_status_work_item)) == false)
odm_schedule_work_item(&(p_txbf_info->txbf_status_work_item));
if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_status_work_item))
odm_schedule_work_item(&p_txbf_info->txbf_status_work_item);
#else
hal_com_txbf_status_work_item_callback(dm);
#endif
}
void
phydm_beamform_set_sounding_fw_ndpa(
void *dm_void
)
void phydm_beamform_set_sounding_fw_ndpa(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
if (*dm->is_fw_dw_rsvd_page_in_progress)
odm_set_timer(dm, &(p_txbf_info->txbf_fw_ndpa_timer), 5);
odm_set_timer(dm, &p_txbf_info->txbf_fw_ndpa_timer, 5);
else
odm_schedule_work_item(&(p_txbf_info->txbf_fw_ndpa_work_item));
odm_schedule_work_item(&p_txbf_info->txbf_fw_ndpa_work_item);
#else
hal_com_txbf_fw_ndpa_work_item_callback(dm);
#endif
}
void
phydm_beamform_set_sounding_clk(
void *dm_void
)
void phydm_beamform_set_sounding_clk(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_clk_work_item)) == false)
odm_schedule_work_item(&(p_txbf_info->txbf_clk_work_item));
if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_clk_work_item))
odm_schedule_work_item(&p_txbf_info->txbf_clk_work_item);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
void *padapter = dm->adapter;
rtw_run_in_thread_cmd(padapter, hal_com_txbf_clk_work_item_callback, dm);
phydm_run_in_thread_cmd(dm, hal_com_txbf_clk_work_item_callback, dm);
#else
hal_com_txbf_clk_work_item_callback(dm);
#endif
}
void
phydm_beamform_set_reset_tx_path(
void *dm_void
)
void phydm_beamform_set_reset_tx_path(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
struct _RT_WORK_ITEM *pwi = &p_txbf_info->txbf_reset_tx_path_work_item;
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_reset_tx_path_work_item)) == false)
odm_schedule_work_item(&(p_txbf_info->txbf_reset_tx_path_work_item));
if (!odm_is_work_item_scheduled(pwi))
odm_schedule_work_item(pwi);
#else
hal_com_txbf_reset_tx_path_work_item_callback(dm);
#endif
}
void
phydm_beamform_set_get_tx_rate(
void *dm_void
)
void phydm_beamform_set_get_tx_rate(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
struct _RT_WORK_ITEM *pwi = &p_txbf_info->txbf_get_tx_rate_work_item;
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_get_tx_rate_work_item)) == false)
odm_schedule_work_item(&(p_txbf_info->txbf_get_tx_rate_work_item));
if (!odm_is_work_item_scheduled(pwi))
odm_schedule_work_item(pwi);
#else
hal_com_txbf_get_tx_rate_work_item_callback(dm);
#endif
}
void
hal_com_txbf_enter_work_item_callback(
void hal_com_txbf_enter_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
void *adapter
#else
void *dm_void
void *dm_void
#endif
)
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
#else
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#endif
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
u8 idx = p_txbf_info->txbf_idx;
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
u8 idx = p_txbf_info->txbf_idx;
PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
@@ -214,24 +194,23 @@ hal_com_txbf_enter_work_item_callback(
hal_txbf_8822b_enter(dm, idx);
}
void
hal_com_txbf_leave_work_item_callback(
void hal_com_txbf_leave_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
void *adapter
#else
void *dm_void
void *dm_void
#endif
)
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
#else
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#endif
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
u8 idx = p_txbf_info->txbf_idx;
u8 idx = p_txbf_info->txbf_idx;
PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
@@ -245,24 +224,22 @@ hal_com_txbf_leave_work_item_callback(
hal_txbf_8822b_leave(dm, idx);
}
void
hal_com_txbf_fw_ndpa_work_item_callback(
void hal_com_txbf_fw_ndpa_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
void *adapter
#else
void *dm_void
void *dm_void
#endif
)
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
#else
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#endif
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
u8 idx = p_txbf_info->ndpa_idx;
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
u8 idx = p_txbf_info->ndpa_idx;
PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
@@ -276,20 +253,19 @@ hal_com_txbf_fw_ndpa_work_item_callback(
hal_txbf_8822b_fw_txbf(dm, idx);
}
void
hal_com_txbf_clk_work_item_callback(
void hal_com_txbf_clk_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
void *adapter
#else
void *dm_void
void *dm_void
#endif
)
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
#else
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#endif
PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
@@ -298,26 +274,23 @@ hal_com_txbf_clk_work_item_callback(
hal_txbf_jaguar_clk_8812a(dm);
}
void
hal_com_txbf_rate_work_item_callback(
void hal_com_txbf_rate_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
void *adapter
#else
void *dm_void
void *dm_void
#endif
)
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
#else
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#endif
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
u8 BW = p_txbf_info->BW;
u8 rate = p_txbf_info->rate;
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
u8 BW = p_txbf_info->BW;
u8 rate = p_txbf_info->rate;
PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
@@ -327,23 +300,17 @@ hal_com_txbf_rate_work_item_callback(
hal_txbf_8192e_set_ndpa_rate(dm, BW, rate);
else if (dm->support_ic_type & ODM_RTL8814A)
hal_txbf_8814a_set_ndpa_rate(dm, BW, rate);
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void
hal_com_txbf_fw_ndpa_timer_callback(
struct phydm_timer_list *timer
)
void hal_com_txbf_fw_ndpa_timer_callback(
struct phydm_timer_list *timer)
{
void *adapter = (void *)timer->Adapter;
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
void *adapter = (void *)timer->Adapter;
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
@@ -354,25 +321,23 @@ hal_com_txbf_fw_ndpa_timer_callback(
}
#endif
void
hal_com_txbf_status_work_item_callback(
void hal_com_txbf_status_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
void *adapter
#else
void *dm_void
void *dm_void
#endif
)
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
#else
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#endif
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
u8 idx = p_txbf_info->txbf_idx;
u8 idx = p_txbf_info->txbf_idx;
PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
@@ -386,61 +351,56 @@ hal_com_txbf_status_work_item_callback(
hal_txbf_8822b_status(dm, idx);
}
void
hal_com_txbf_reset_tx_path_work_item_callback(
void hal_com_txbf_reset_tx_path_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
void *adapter
#else
void *dm_void
void *dm_void
#endif
)
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
#else
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#endif
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
u8 idx = p_txbf_info->txbf_idx;
u8 idx = p_txbf_info->txbf_idx;
if (dm->support_ic_type & ODM_RTL8814A)
hal_txbf_8814a_reset_tx_path(dm, idx);
}
void
hal_com_txbf_get_tx_rate_work_item_callback(
void hal_com_txbf_get_tx_rate_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
void *adapter
#else
void *dm_void
void *dm_void
#endif
)
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
#else
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#endif
if (dm->support_ic_type & ODM_RTL8814A)
hal_txbf_8814a_get_tx_rate(dm);
}
boolean
hal_com_txbf_set(
void *dm_void,
u8 set_type,
void *p_in_buf
)
void *dm_void,
u8 set_type,
void *p_in_buf)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 *p_u1_tmp = (u8 *)p_in_buf;
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 *p_u1_tmp = (u8 *)p_in_buf;
struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
PHYDM_DBG(dm, DBG_TXBF, "[%s] set_type = 0x%X\n", __func__, set_type);
@@ -483,7 +443,6 @@ hal_com_txbf_set(
case TXBF_SET_GET_TX_RATE:
phydm_beamform_set_get_tx_rate(dm);
break;
}
return true;
@@ -492,52 +451,62 @@ hal_com_txbf_set(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
boolean
hal_com_txbf_get(
void *adapter,
u8 get_type,
void *p_out_buf
)
void *adapter,
u8 get_type,
void *p_out_buf)
{
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
boolean *p_boolean = (boolean *)p_out_buf;
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
boolean *p_boolean = (boolean *)p_out_buf;
PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
if (get_type == TXBF_GET_EXPLICIT_BEAMFORMEE) {
if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter))
*p_boolean = false;
else if (/*IS_HARDWARE_TYPE_8822B(adapter) ||*/
IS_HARDWARE_TYPE_8821B(adapter) ||
IS_HARDWARE_TYPE_8192E(adapter) ||
IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
else if (/*@IS_HARDWARE_TYPE_8822B(adapter) ||*/
IS_HARDWARE_TYPE_8821B(adapter) ||
IS_HARDWARE_TYPE_8192E(adapter) ||
IS_HARDWARE_TYPE_8192F(adapter) ||
IS_HARDWARE_TYPE_JAGUAR(adapter) ||
IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter) ||
IS_HARDWARE_TYPE_JAGUAR3(adapter))
*p_boolean = true;
else
*p_boolean = false;
} else if (get_type == TXBF_GET_EXPLICIT_BEAMFORMER) {
if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter))
*p_boolean = false;
else if (/*IS_HARDWARE_TYPE_8822B(adapter) ||*/
IS_HARDWARE_TYPE_8821B(adapter) ||
IS_HARDWARE_TYPE_8192E(adapter) ||
IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) {
if (hal_data->RF_Type == RF_2T2R || hal_data->RF_Type == RF_3T3R)
else if (/*@IS_HARDWARE_TYPE_8822B(adapter) ||*/
IS_HARDWARE_TYPE_8821B(adapter) ||
IS_HARDWARE_TYPE_8192E(adapter) ||
IS_HARDWARE_TYPE_8192F(adapter) ||
IS_HARDWARE_TYPE_JAGUAR(adapter) ||
IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter) ||
IS_HARDWARE_TYPE_JAGUAR3(adapter)) {
if (hal_data->RF_Type == RF_2T2R ||
hal_data->RF_Type == RF_3T3R ||
hal_data->RF_Type == RF_4T4R)
*p_boolean = true;
else
*p_boolean = false;
} else
*p_boolean = false;
} else if (get_type == TXBF_GET_MU_MIMO_STA) {
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1))
if (IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8821C(adapter))
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) ||\
(RTL8822C_SUPPORT == 1))
if (IS_HARDWARE_TYPE_8822B(adapter) ||
IS_HARDWARE_TYPE_8821C(adapter) ||
IS_HARDWARE_TYPE_JAGUAR3(adapter))
*p_boolean = true;
else
#endif
*p_boolean = false;
} else if (get_type == TXBF_GET_MU_MIMO_AP) {
#if (RTL8822B_SUPPORT == 1)
if (IS_HARDWARE_TYPE_8822B(adapter))
#if ((RTL8822B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
if (IS_HARDWARE_TYPE_8822B(adapter) ||
IS_HARDWARE_TYPE_JAGUAR3(adapter))
*p_boolean = true;
else
#endif
@@ -548,5 +517,4 @@ hal_com_txbf_get(
}
#endif
#endif

162
hal/phydm/txbf/halcomtxbf.h
View File

@@ -25,7 +25,7 @@
#ifndef __HAL_COM_TXBF_H__
#define __HAL_COM_TXBF_H__
/*
#if 0
typedef bool
(*TXBF_GET)(
void* adapter,
@@ -39,7 +39,7 @@ typedef bool
u8 set_type,
void* p_in_buf
);
*/
#endif
enum txbf_set_type {
TXBF_SET_SOUNDING_ENTER,
@@ -52,7 +52,6 @@ enum txbf_set_type {
TXBF_SET_GET_TX_RATE
};
enum txbf_get_type {
TXBF_GET_EXPLICIT_BEAMFORMEE,
TXBF_GET_EXPLICIT_BEAMFORMER,
@@ -60,144 +59,125 @@ enum txbf_get_type {
TXBF_GET_MU_MIMO_AP
};
/* 2 HAL TXBF related */
/* @2 HAL TXBF related */
struct _HAL_TXBF_INFO {
u8 txbf_idx;
u8 ndpa_idx;
u8 BW;
u8 rate;
u8 txbf_idx;
u8 ndpa_idx;
u8 BW;
u8 rate;
struct phydm_timer_list txbf_fw_ndpa_timer;
struct phydm_timer_list txbf_fw_ndpa_timer;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
RT_WORK_ITEM txbf_enter_work_item;
RT_WORK_ITEM txbf_leave_work_item;
RT_WORK_ITEM txbf_fw_ndpa_work_item;
RT_WORK_ITEM txbf_clk_work_item;
RT_WORK_ITEM txbf_status_work_item;
RT_WORK_ITEM txbf_rate_work_item;
RT_WORK_ITEM txbf_reset_tx_path_work_item;
RT_WORK_ITEM txbf_get_tx_rate_work_item;
RT_WORK_ITEM txbf_enter_work_item;
RT_WORK_ITEM txbf_leave_work_item;
RT_WORK_ITEM txbf_fw_ndpa_work_item;
RT_WORK_ITEM txbf_clk_work_item;
RT_WORK_ITEM txbf_status_work_item;
RT_WORK_ITEM txbf_rate_work_item;
RT_WORK_ITEM txbf_reset_tx_path_work_item;
RT_WORK_ITEM txbf_get_tx_rate_work_item;
#endif
};
#if (BEAMFORMING_SUPPORT == 1)
#ifdef PHYDM_BEAMFORMING_SUPPORT
void
hal_com_txbf_beamform_init(
void *dm_void
);
void hal_com_txbf_beamform_init(
void *dm_void);
void
hal_com_txbf_config_gtab(
void *dm_void
);
void hal_com_txbf_config_gtab(
void *dm_void);
void
hal_com_txbf_enter_work_item_callback(
void hal_com_txbf_enter_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
void *adapter
#else
void *dm_void
void *dm_void
#endif
);
);
void
hal_com_txbf_leave_work_item_callback(
void hal_com_txbf_leave_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
void *adapter
#else
void *dm_void
void *dm_void
#endif
);
);
void
hal_com_txbf_fw_ndpa_work_item_callback(
void hal_com_txbf_fw_ndpa_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
void *adapter
#else
void *dm_void
void *dm_void
#endif
);
);
void
hal_com_txbf_clk_work_item_callback(
void hal_com_txbf_clk_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
void *adapter
#else
void *dm_void
void *dm_void
#endif
);
);
void
hal_com_txbf_reset_tx_path_work_item_callback(
void hal_com_txbf_reset_tx_path_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
void *adapter
#else
void *dm_void
void *dm_void
#endif
);
);
void
hal_com_txbf_get_tx_rate_work_item_callback(
void hal_com_txbf_get_tx_rate_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
void *adapter
#else
void *dm_void
void *dm_void
#endif
);
);
void
hal_com_txbf_rate_work_item_callback(
void hal_com_txbf_rate_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
void *adapter
#else
void *dm_void
void *dm_void
#endif
);
);
void
hal_com_txbf_fw_ndpa_timer_callback(
struct phydm_timer_list *timer
);
void hal_com_txbf_fw_ndpa_timer_callback(
struct phydm_timer_list *timer);
void
hal_com_txbf_status_work_item_callback(
void hal_com_txbf_status_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
void *adapter
#else
void *dm_void
void *dm_void
#endif
);
);
boolean
hal_com_txbf_set(
void *dm_void,
u8 set_type,
void *p_in_buf
);
void *dm_void,
u8 set_type,
void *p_in_buf);
boolean
hal_com_txbf_get(
void *adapter,
u8 get_type,
void *p_out_buf
);
void *adapter,
u8 get_type,
void *p_out_buf);
#else
#define hal_com_txbf_beamform_init(dm_void) NULL
#define hal_com_txbf_config_gtab(dm_void) NULL
#define hal_com_txbf_enter_work_item_callback(_adapter) NULL
#define hal_com_txbf_leave_work_item_callback(_adapter) NULL
#define hal_com_txbf_fw_ndpa_work_item_callback(_adapter) NULL
#define hal_com_txbf_clk_work_item_callback(_adapter) NULL
#define hal_com_txbf_rate_work_item_callback(_adapter) NULL
#define hal_com_txbf_fw_ndpa_timer_callback(_adapter) NULL
#define hal_com_txbf_status_work_item_callback(_adapter) NULL
#define hal_com_txbf_beamform_init(dm_void) NULL
#define hal_com_txbf_config_gtab(dm_void) NULL
#define hal_com_txbf_enter_work_item_callback(_adapter) NULL
#define hal_com_txbf_leave_work_item_callback(_adapter) NULL
#define hal_com_txbf_fw_ndpa_work_item_callback(_adapter) NULL
#define hal_com_txbf_clk_work_item_callback(_adapter) NULL
#define hal_com_txbf_rate_work_item_callback(_adapter) NULL
#define hal_com_txbf_fw_ndpa_timer_callback(_adapter) NULL
#define hal_com_txbf_status_work_item_callback(_adapter) NULL
#define hal_com_txbf_get(_adapter, _get_type, _pout_buf)
#endif
#endif /* #ifndef __HAL_COM_TXBF_H__ */
#endif /* @#ifndef __HAL_COM_TXBF_H__ */

305
hal/phydm/txbf/haltxbf8192e.c
View File

@@ -12,38 +12,33 @@
* more details.
*
*****************************************************************************/
/* ************************************************************
/*************************************************************
* Description:
*
* This file is for 8192E TXBF mechanism
*
* ************************************************************ */
************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (BEAMFORMING_SUPPORT == 1)
#ifdef PHYDM_BEAMFORMING_SUPPORT
#if (RTL8192E_SUPPORT == 1)
void
hal_txbf_8192e_set_ndpa_rate(
void *dm_void,
u8 BW,
u8 rate
)
void hal_txbf_8192e_set_ndpa_rate(
void *dm_void,
u8 BW,
u8 rate)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8192E, (rate << 2 | BW));
}
void
hal_txbf_8192e_rf_mode(
void *dm_void,
struct _RT_BEAMFORMING_INFO *beam_info
)
void hal_txbf_8192e_rf_mode(
void *dm_void,
struct _RT_BEAMFORMING_INFO *beam_info)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
@@ -55,46 +50,42 @@ hal_txbf_8192e_rf_mode(
if (beam_info->beamformee_su_cnt > 0) {
/*Path_A*/
odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/
odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x0000f); /*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x77fc2); /*@Enable TXIQGEN in RX mode*/
/*Path_B*/
odm_set_rf_reg(dm, RF_PATH_B, 0x30, 0xfffff, 0x18000); /*Select RX mode*/
odm_set_rf_reg(dm, RF_PATH_B, 0x31, 0xfffff, 0x0000f); /*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_B, 0x32, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x77fc2); /*@Enable TXIQGEN in RX mode*/
} else {
/*Path_A*/
odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*Select RX mode*/
odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x0000f); /*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x77f82); /*@Disable TXIQGEN in RX mode*/
/*Path_B*/
odm_set_rf_reg(dm, RF_PATH_B, 0x30, 0xfffff, 0x18000); /*Select RX mode*/
odm_set_rf_reg(dm, RF_PATH_B, 0x31, 0xfffff, 0x0000f); /*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_B, 0x32, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x77f82); /*@Disable TXIQGEN in RX mode*/
}
odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
odm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
odm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
if (beam_info->beamformee_su_cnt > 0) {
odm_set_bb_reg(dm, 0x90c, MASKDWORD, 0x83321333);
odm_set_bb_reg(dm, 0xa04, MASKBYTE3, 0xc1);
odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x83321333);
odm_set_bb_reg(dm, R_0xa04, MASKBYTE3, 0xc1);
} else
odm_set_bb_reg(dm, 0x90c, MASKDWORD, 0x81121313);
odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x81121313);
}
void
hal_txbf_8192e_fw_txbf_cmd(
void *dm_void
)
void hal_txbf_8192e_fw_txbf_cmd(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 idx, period0 = 0, period1 = 0;
u8 PageNum0 = 0xFF, PageNum1 = 0xFF;
u8 u1_tx_bf_parm[3] = {0};
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 idx, period0 = 0, period1 = 0;
u8 PageNum0 = 0xFF, PageNum1 = 0xFF;
u8 u1_tx_bf_parm[3] = {0};
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
if (beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
@@ -120,24 +111,22 @@ hal_txbf_8192e_fw_txbf_cmd(
odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
PHYDM_DBG(dm, DBG_TXBF,
"[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n", __func__, PageNum0, period0, PageNum1, period1);
"[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n",
__func__, PageNum0, period0, PageNum1, period1);
}
void
hal_txbf_8192e_download_ndpa(
void *dm_void,
u8 idx
)
void hal_txbf_8192e_download_ndpa(
void *dm_void,
u8 idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 u1b_tmp = 0, tmp_reg422 = 0, head_page;
u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
boolean is_send_beacon = false;
u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812;
/*default reseved 1 page for the IC type which is undefined.*/
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 u1b_tmp = 0, tmp_reg422 = 0, head_page;
u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
boolean is_send_beacon = false;
u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812;
/*@default reseved 1 page for the IC type which is undefined.*/
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
@@ -151,69 +140,74 @@ hal_txbf_8192e_download_ndpa(
phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy);
/*Set REG_CR bit 8. DMA beacon by SW.*/
u1b_tmp = odm_read_1byte(dm, REG_CR_8192E+1);
odm_write_1byte(dm, REG_CR_8192E+1, (u1b_tmp | BIT(0)));
u1b_tmp = odm_read_1byte(dm, REG_CR_8192E + 1);
odm_write_1byte(dm, REG_CR_8192E + 1, (u1b_tmp | BIT(0)));
/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8192E+2);
odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E+2, tmp_reg422 & (~BIT(6)));
tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2);
odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2, tmp_reg422 & (~BIT(6)));
if (tmp_reg422 & BIT(6)) {
PHYDM_DBG(dm, DBG_TXBF, "%s There is an adapter is sending beacon.\n", __func__);
PHYDM_DBG(dm, DBG_TXBF,
"%s There is an adapter is sending beacon.\n",
__func__);
is_send_beacon = true;
}
/*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD NDPA Head for TXDMA*/
odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E+1, head_page);
odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 1, head_page);
do {
/*Clear beacon valid check bit.*/
bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E+2);
odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E+2, (bcn_valid_reg | BIT(0)));
/*@Clear beacon valid check bit.*/
bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);
odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 2, (bcn_valid_reg | BIT(0)));
/* download NDPA rsvd page. */
/* @download NDPA rsvd page. */
beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E+3);
count = 0;
while ((count < 20) && (u1b_tmp & BIT(4))) {
count++;
ODM_delay_us(10);
u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E+3);
if (dm->support_interface == ODM_ITRF_PCIE) {
u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3);
count = 0;
while ((count < 20) && (u1b_tmp & BIT(4))) {
count++;
ODM_delay_us(10);
u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3);
}
odm_write_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3, u1b_tmp | BIT(4));
}
odm_write_1byte(dm, REG_MGQ_TXBD_NUM_8192E+3, u1b_tmp | BIT(4));
#endif
/*check rsvd page download OK.*/
bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E+2);
/*@check rsvd page download OK.*/
bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);
count = 0;
while (!(bcn_valid_reg & BIT(0)) && count < 20) {
count++;
ODM_delay_us(10);
bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E+2);
bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);
}
dl_bcn_count++;
} while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5);
if (!(bcn_valid_reg & BIT(0)))
PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n", __func__);
PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n",
__func__);
/*TDECTRL[15:8] 0x209[7:0] = 0xF9 Beacon Head for TXDMA*/
odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E+1, tx_page_bndy);
odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 1, tx_page_bndy);
/*To make sure that if there exists an adapter which would like to send beacon.*/
/*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
/*the beacon cannot be sent by HW.*/
/*2010.06.23. Added by tynli.*/
/*@2010.06.23. Added by tynli.*/
if (is_send_beacon)
odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E+2, tmp_reg422);
odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2, tmp_reg422);
/*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
/*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
u1b_tmp = odm_read_1byte(dm, REG_CR_8192E+1);
odm_write_1byte(dm, REG_CR_8192E+1, (u1b_tmp & (~BIT(0))));
/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
u1b_tmp = odm_read_1byte(dm, REG_CR_8192E + 1);
odm_write_1byte(dm, REG_CR_8192E + 1, (u1b_tmp & (~BIT(0))));
p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
@@ -221,46 +215,43 @@ hal_txbf_8192e_download_ndpa(
#endif
}
void
hal_txbf_8192e_enter(
void *dm_void,
u8 bfer_bfee_idx
)
void hal_txbf_8192e_enter(
void *dm_void,
u8 bfer_bfee_idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i = 0;
u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
u8 bfee_idx = (bfer_bfee_idx & 0xF);
u32 csi_param;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
struct _RT_BEAMFORMER_ENTRY beamformer_entry;
u16 sta_id = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i = 0;
u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
u8 bfee_idx = (bfer_bfee_idx & 0xF);
u32 csi_param;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
struct _RT_BEAMFORMER_ENTRY beamformer_entry;
u16 sta_id = 0;
PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
hal_txbf_8192e_rf_mode(dm, beamforming_info);
if (dm->rf_type == RF_2T2R)
odm_write_4byte(dm, 0xd80, 0x00000000); /*nc =2*/
odm_write_4byte(dm, 0xd80, 0x00000000); /*nc =2*/
if ((beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) {
if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
beamformer_entry = beamforming_info->beamformer_entry[bfer_idx];
/*Sounding protocol control*/
odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xCB);
/*MAC address/Partial AID of Beamformer*/
/*@MAC address/Partial AID of Beamformer*/
if (bfer_idx == 0) {
for (i = 0; i < 6 ; i++)
odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8192E+i), beamformer_entry.mac_addr[i]);
for (i = 0; i < 6; i++)
odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8192E + i), beamformer_entry.mac_addr[i]);
} else {
for (i = 0; i < 6 ; i++)
odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8192E+i), beamformer_entry.mac_addr[i]);
for (i = 0; i < 6; i++)
odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8192E + i), beamformer_entry.mac_addr[i]);
}
/*CSI report parameters of Beamformer Default use nc = 2*/
/*@CSI report parameters of Beamformer Default use nc = 2*/
csi_param = 0x03090309;
odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW20_8192E, csi_param);
@@ -268,11 +259,10 @@ hal_txbf_8192e_enter(
odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW80_8192E, csi_param);
/*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/
odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E+3, 0x50);
odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E + 3, 0x50);
}
if ((beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) {
if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
beamformee_entry = beamforming_info->beamformee_entry[bfee_idx];
if (phydm_acting_determine(dm, phydm_acting_as_ibss))
@@ -280,44 +270,41 @@ hal_txbf_8192e_enter(
else
sta_id = beamformee_entry.p_aid;
PHYDM_DBG(dm, DBG_TXBF, "[%s], sta_id=0x%X\n", __func__, sta_id);
PHYDM_DBG(dm, DBG_TXBF, "[%s], sta_id=0x%X\n", __func__,
sta_id);
/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
if (bfee_idx == 0) {
odm_write_2byte(dm, REG_TXBF_CTRL_8192E, sta_id);
odm_write_1byte(dm, REG_TXBF_CTRL_8192E+3, odm_read_1byte(dm, REG_TXBF_CTRL_8192E+3) | BIT(4) | BIT(6) | BIT(7));
odm_write_1byte(dm, REG_TXBF_CTRL_8192E + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8192E + 3) | BIT(4) | BIT(6) | BIT(7));
} else
odm_write_2byte(dm, REG_TXBF_CTRL_8192E+2, sta_id | BIT(12) | BIT(14) | BIT(15));
odm_write_2byte(dm, REG_TXBF_CTRL_8192E + 2, sta_id | BIT(12) | BIT(14) | BIT(15));
/*CSI report parameters of Beamformee*/
/*@CSI report parameters of Beamformee*/
if (bfee_idx == 0) {
/*Get BIT24 & BIT25*/
u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E+3) & 0x3;
/*@Get BIT24 & BIT25*/
u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 3) & 0x3;
odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E+3, tmp | 0x60);
odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 3, tmp | 0x60);
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, sta_id | BIT(9));
} else {
/*Set BIT25*/
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, sta_id | 0xE200);
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2, sta_id | 0xE200);
}
phydm_beamforming_notify(dm);
}
}
void
hal_txbf_8192e_leave(
void *dm_void,
u8 idx
)
void hal_txbf_8192e_leave(
void *dm_void,
u8 idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
hal_txbf_8192e_rf_mode(dm, beam_info);
/* Clear P_AID of Beamformee
/* @Clear P_AID of Beamformee
* Clear MAC addresss of Beamformer
* Clear Associated Bfmee Sel
*/
@@ -327,30 +314,27 @@ hal_txbf_8192e_leave(
if (idx == 0) {
odm_write_2byte(dm, REG_TXBF_CTRL_8192E, 0);
odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0);
odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E+4, 0);
odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E + 4, 0);
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0);
} else {
odm_write_2byte(dm, REG_TXBF_CTRL_8192E+2, odm_read_1byte(dm, REG_TXBF_CTRL_8192E+2) & 0xF000);
odm_write_2byte(dm, REG_TXBF_CTRL_8192E + 2, odm_read_1byte(dm, REG_TXBF_CTRL_8192E + 2) & 0xF000);
odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0);
odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E+4, 0);
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E+2) & 0x60);
odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E + 4, 0);
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2) & 0x60);
}
PHYDM_DBG(dm, DBG_TXBF, "[%s] idx %d\n", __func__, idx);
}
void
hal_txbf_8192e_status(
void *dm_void,
u8 idx
)
void hal_txbf_8192e_status(
void *dm_void,
u8 idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u16 beam_ctrl_val;
u32 beam_ctrl_reg;
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx];
struct dm_struct *dm = (struct dm_struct *)dm_void;
u16 beam_ctrl_val;
u32 beam_ctrl_reg;
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx];
if (phydm_acting_determine(dm, phydm_acting_as_ibss))
beam_ctrl_val = beamform_entry.mac_id;
@@ -360,11 +344,11 @@ hal_txbf_8192e_status(
if (idx == 0)
beam_ctrl_reg = REG_TXBF_CTRL_8192E;
else {
beam_ctrl_reg = REG_TXBF_CTRL_8192E+2;
beam_ctrl_reg = REG_TXBF_CTRL_8192E + 2;
beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
}
if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (beam_info->apply_v_matrix == true)) {
if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beam_info->apply_v_matrix == true) {
if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
beam_ctrl_val |= BIT(9);
else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
@@ -374,19 +358,18 @@ hal_txbf_8192e_status(
odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
PHYDM_DBG(dm, DBG_TXBF, "[%s] idx %d beam_ctrl_reg %x beam_ctrl_val %x\n", __func__, idx, beam_ctrl_reg, beam_ctrl_val);
PHYDM_DBG(dm, DBG_TXBF,
"[%s] idx %d beam_ctrl_reg %x beam_ctrl_val %x\n", __func__,
idx, beam_ctrl_reg, beam_ctrl_val);
}
void
hal_txbf_8192e_fw_tx_bf(
void *dm_void,
u8 idx
)
void hal_txbf_8192e_fw_tx_bf(
void *dm_void,
u8 idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
@@ -396,6 +379,6 @@ hal_txbf_8192e_fw_tx_bf(
hal_txbf_8192e_fw_txbf_cmd(dm);
}
#endif /* #if (RTL8192E_SUPPORT == 1)*/
#endif /* @#if (RTL8192E_SUPPORT == 1)*/
#endif

47
hal/phydm/txbf/haltxbf8192e.h
View File

@@ -26,41 +26,28 @@
#define __HAL_TXBF_8192E_H__
#if (RTL8192E_SUPPORT == 1)
#if (BEAMFORMING_SUPPORT == 1)
#ifdef PHYDM_BEAMFORMING_SUPPORT
void
hal_txbf_8192e_set_ndpa_rate(
void *dm_void,
u8 BW,
u8 rate
);
void hal_txbf_8192e_set_ndpa_rate(
void *dm_void,
u8 BW,
u8 rate);
void
hal_txbf_8192e_enter(
void *dm_void,
u8 idx
);
void hal_txbf_8192e_enter(
void *dm_void,
u8 idx);
void hal_txbf_8192e_leave(
void *dm_void,
u8 idx);
void
hal_txbf_8192e_leave(
void *dm_void,
u8 idx
);
void hal_txbf_8192e_status(
void *dm_void,
u8 idx);
void
hal_txbf_8192e_status(
void *dm_void,
u8 idx
);
void
hal_txbf_8192e_fw_tx_bf(
void *dm_void,
u8 idx
);
void hal_txbf_8192e_fw_tx_bf(
void *dm_void,
u8 idx);
#else
#define hal_txbf_8192e_set_ndpa_rate(dm_void, BW, rate)

341
hal/phydm/txbf/haltxbf8814a.c
View File

@@ -22,33 +22,31 @@
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (BEAMFORMING_SUPPORT == 1)
#ifdef PHYDM_BEAMFORMING_SUPPORT
#if (RTL8814A_SUPPORT == 1)
boolean
phydm_beamforming_set_iqgen_8814A(
void *dm_void
)
phydm_beamforming_set_iqgen_8814A(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i = 0;
u16 counter = 0;
u32 rf_mode[4];
for (i = RF_PATH_A ; i < MAX_RF_PATH ; i++)
odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
while (1) {
counter++;
for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
odm_set_rf_reg(dm, i, RF_RCK_OS, 0xfffff, 0x18000); /*Select Rx mode*/
odm_set_rf_reg(dm, i, RF_RCK_OS, 0xfffff, 0x18000); /*Select Rx mode*/
ODM_delay_us(2);
for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
rf_mode[i] = odm_get_rf_reg(dm, i, RF_RCK_OS, 0xfffff);
if ((rf_mode[0] == 0x18000) && (rf_mode[1] == 0x18000) && (rf_mode[2] == 0x18000) && (rf_mode[3] == 0x18000))
if (rf_mode[0] == 0x18000 && rf_mode[1] == 0x18000 && rf_mode[2] == 0x18000 && rf_mode[3] == 0x18000)
break;
else if (counter == 100) {
PHYDM_DBG(dm, DBG_TXBF, "iqgen setting fail:8814A\n");
@@ -56,37 +54,28 @@ phydm_beamforming_set_iqgen_8814A(
}
}
for (i = RF_PATH_A ; i < MAX_RF_PATH ; i++) {
for (i = RF_PATH_A; i < MAX_RF_PATH; i++) {
odm_set_rf_reg(dm, i, RF_TXPA_G1, 0xfffff, 0xBE77F); /*Set Table data*/
odm_set_rf_reg(dm, i, RF_TXPA_G2, 0xfffff, 0x226BF); /*Enable TXIQGEN in Rx mode*/
odm_set_rf_reg(dm, i, RF_TXPA_G2, 0xfffff, 0x226BF); /*@Enable TXIQGEN in Rx mode*/
}
odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, 0xfffff, 0xE26BF); /*Enable TXIQGEN in Rx mode*/
odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in Rx mode*/
for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
return true;
}
void
hal_txbf_8814a_set_ndpa_rate(
void *dm_void,
u8 BW,
u8 rate
)
void hal_txbf_8814a_set_ndpa_rate(void *dm_void, u8 BW, u8 rate)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8814A, BW);
odm_write_1byte(dm, REG_NDPA_RATE_8814A, (u8) rate);
odm_write_1byte(dm, REG_NDPA_RATE_8814A, (u8)rate);
}
#if 0
#define PHYDM_MEMORY_MAP_BUF_READ 0x8000
#define PHYDM_CTRL_INFO_PAGE 0x660
#define PHYDM_MEMORY_MAP_BUF_READ 0x8000
#define PHYDM_CTRL_INFO_PAGE 0x660
void
phydm_data_rate_8814a(
@@ -100,65 +89,59 @@ phydm_data_rate_8814a(
u16 x_read_data_addr = 0;
odm_write_2byte(dm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE);
x_read_data_addr = PHYDM_MEMORY_MAP_BUF_READ + mac_id * 32; /*Ctrl Info: 32Bytes for each macid(n)*/
x_read_data_addr = PHYDM_MEMORY_MAP_BUF_READ + mac_id * 32; /*@Ctrl Info: 32Bytes for each macid(n)*/
if ((x_read_data_addr < PHYDM_MEMORY_MAP_BUF_READ) || (x_read_data_addr > 0x8FFF)) {
PHYDM_DBG(dm, DBG_TXBF, "x_read_data_addr(0x%x) is not correct!\n", x_read_data_addr);
if (x_read_data_addr < PHYDM_MEMORY_MAP_BUF_READ || x_read_data_addr > 0x8FFF) {
PHYDM_DBG(dm, DBG_TXBF,
"x_read_data_addr(0x%x) is not correct!\n",
x_read_data_addr);
return;
}
/* Read data */
for (i = 0; i < data_len; i++)
*(data + i) = odm_read_2byte(dm, x_read_data_addr + i);
}
#endif
void
hal_txbf_8814a_get_tx_rate(
void *dm_void
)
void hal_txbf_8814a_get_tx_rate(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY *entry;
struct ra_table *ra_tab = &dm->dm_ra_table;
struct cmn_sta_info *sta = NULL;
u8 data_rate = 0xFF;
u8 macid = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY *entry;
struct ra_table *ra_tab = &dm->dm_ra_table;
struct cmn_sta_info *sta = NULL;
u8 data_rate = 0xFF;
u8 macid = 0;
entry = &(beam_info->beamformee_entry[beam_info->beamformee_cur_idx]);
macid = (u8)entry->mac_id;
sta = dm->phydm_sta_info[macid];
if (is_sta_active(sta)) {
data_rate = (sta->ra_info.curr_tx_rate) & 0x7f; /*Bit7 indicates SGI*/
data_rate = (sta->ra_info.curr_tx_rate) & 0x7f; /*@Bit7 indicates SGI*/
beam_info->tx_bf_data_rate = data_rate;
}
PHYDM_DBG(dm, DBG_TXBF, "[%s] dm->tx_bf_data_rate = 0x%x\n", __func__, beam_info->tx_bf_data_rate);
PHYDM_DBG(dm, DBG_TXBF, "[%s] dm->tx_bf_data_rate = 0x%x\n", __func__,
beam_info->tx_bf_data_rate);
}
void
hal_txbf_8814a_reset_tx_path(
void *dm_void,
u8 idx
)
void hal_txbf_8814a_reset_tx_path(void *dm_void, u8 idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if DEV_BUS_TYPE == RT_USB_INTERFACE
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
u8 nr_index = 0, tx_ss = 0;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
u8 nr_index = 0, tx_ss = 0;
if (idx < BEAMFORMEE_ENTRY_NUM)
beamformee_entry = beamforming_info->beamformee_entry[idx];
else
return;
if ((beamforming_info->last_usb_hub) != (*dm->hub_usb_mode)) {
if (beamforming_info->last_usb_hub != (*dm->hub_usb_mode)) {
nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer);
if (*dm->hub_usb_mode == 2) {
@@ -168,7 +151,7 @@ hal_txbf_8814a_reset_tx_path(
tx_ss = 0xe;
else
tx_ss = 0x6;
} else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/
} else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/
tx_ss = 0x6;
else
tx_ss = 0x6;
@@ -189,33 +172,33 @@ hal_txbf_8814a_reset_tx_path(
case 0:
break;
case 1: /*Nsts = 2 BC*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
case 1: /*Nsts = 2 BC*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
break;
case 2: /*Nsts = 3 BCD*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
case 2: /*Nsts = 3 BCD*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
break;
default: /*nr>3, same as Case 3*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
default: /*nr>3, same as Case 3*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
break;
}
} else {
} else {
switch (nr_index) {
case 0:
break;
case 1: /*Nsts = 2 BC*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
case 1: /*Nsts = 2 BC*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
break;
case 2: /*Nsts = 3 BCD*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
case 2: /*Nsts = 3 BCD*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
break;
default: /*nr>3, same as Case 3*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
default: /*nr>3, same as Case 3*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
break;
}
}
@@ -226,14 +209,10 @@ hal_txbf_8814a_reset_tx_path(
#endif
}
u8
hal_txbf_8814a_get_ntx(
void *dm_void
)
u8 hal_txbf_8814a_get_ntx(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 ntx = 0, tx_ss = 3;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 ntx = 0, tx_ss = 3;
#if DEV_BUS_TYPE == RT_USB_INTERFACE
tx_ss = *dm->hub_usb_mode;
@@ -245,7 +224,7 @@ hal_txbf_8814a_get_ntx(
ntx = 2;
else
ntx = 1;
} else if (tx_ss == 1) /*USB 2.0 always 2Tx*/
} else if (tx_ss == 1) /*USB 2.0 always 2Tx*/
ntx = 1;
else
ntx = 1;
@@ -254,13 +233,10 @@ hal_txbf_8814a_get_ntx(
return ntx;
}
u8
hal_txbf_8814a_get_nrx(
void *dm_void
)
u8 hal_txbf_8814a_get_nrx(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 nrx = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 nrx = 0;
if (dm->rf_type == RF_4T4R)
nrx = 3;
@@ -283,17 +259,14 @@ hal_txbf_8814a_get_nrx(
return nrx;
}
void
hal_txbf_8814a_rf_mode(
void *dm_void,
struct _RT_BEAMFORMING_INFO *beamforming_info,
u8 idx
)
void hal_txbf_8814a_rf_mode(void *dm_void,
struct _RT_BEAMFORMING_INFO *beamforming_info,
u8 idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 nr_index = 0;
u8 tx_ss = 3; /*default use 3 Tx*/
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 nr_index = 0;
u8 tx_ss = 3; /*@default use 3 Tx*/
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
if (idx < BEAMFORMEE_ENTRY_NUM)
beamformee_entry = beamforming_info->beamformee_entry[idx];
@@ -317,7 +290,7 @@ hal_txbf_8814a_rf_mode(
tx_ss = 0xe;
else
tx_ss = 0x6;
} else if (tx_ss == 1) /*USB 2.0 always 2Tx*/
} else if (tx_ss == 1) /*USB 2.0 always 2Tx*/
tx_ss = 0x6;
else
tx_ss = 0x6;
@@ -333,25 +306,25 @@ hal_txbf_8814a_rf_mode(
odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360);
}
/*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(28) | BIT29, 0x2); /*enable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT30, 0x1); /*if Nsts > Nc don't apply V matrix*/
/*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT30, 0x1); /*@if Nsts > Nc don't apply V matrix*/
if (idx == 0) {
switch (nr_index) {
case 0:
break;
case 1: /*Nsts = 2 BC*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
case 1: /*Nsts = 2 BC*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
break;
case 2: /*Nsts = 3 BCD*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
case 2: /*Nsts = 3 BCD*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
break;
default: /*nr>3, same as Case 3*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
default: /*nr>3, same as Case 3*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
break;
}
@@ -360,23 +333,23 @@ hal_txbf_8814a_rf_mode(
case 0:
break;
case 1: /*Nsts = 2 BC*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
case 1: /*Nsts = 2 BC*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
break;
case 2: /*Nsts = 3 BCD*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
case 2: /*Nsts = 3 BCD*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
break;
default: /*nr>3, same as Case 3*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
default: /*nr>3, same as Case 3*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
break;
}
}
}
if ((beamforming_info->beamformee_su_cnt == 0) && (beamforming_info->beamformer_su_cnt == 0)) {
odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x932); /*set tx_path selection for 8814a BFer bug refine*/
if (beamforming_info->beamformee_su_cnt == 0 && beamforming_info->beamformer_su_cnt == 0) {
odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x932); /*set tx_path selection for 8814a BFer bug refine*/
odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e9360);
}
}
@@ -392,7 +365,7 @@ hal_txbf_8814a_download_ndpa(
u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
u16 head_page = 0x7FE;
boolean is_send_beacon = false;
u16 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/
u16 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*@default reseved 1 page for the IC type which is undefined.*/
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
void *adapter = dm->adapter;
@@ -414,25 +387,27 @@ hal_txbf_8814a_download_ndpa(
odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422 & (~BIT(6)));
if (tmp_reg422 & BIT(6)) {
PHYDM_DBG(dm, DBG_TXBF, "%s: There is an adapter is sending beacon.\n", __func__);
PHYDM_DBG(dm, DBG_TXBF,
"%s: There is an adapter is sending beacon.\n",
__func__);
is_send_beacon = true;
}
/*0x204[11:0] Beacon Head for TXDMA*/
/*@0x204[11:0] Beacon Head for TXDMA*/
odm_write_2byte(dm, REG_FIFOPAGE_CTRL_2_8814A, head_page);
do {
/*Clear beacon valid check bit.*/
/*@Clear beacon valid check bit.*/
bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1);
odm_write_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7)));
/*download NDPA rsvd page.*/
/*@download NDPA rsvd page.*/
if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE);
else
beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
/*check rsvd page download OK.*/
/*@check rsvd page download OK.*/
bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1);
count = 0;
while (!(bcn_valid_reg & BIT(7)) && count < 20) {
@@ -444,21 +419,22 @@ hal_txbf_8814a_download_ndpa(
} while (!(bcn_valid_reg & BIT(7)) && dl_bcn_count < 5);
if (!(bcn_valid_reg & BIT(7)))
PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n", __func__);
PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n",
__func__);
/*0x204[11:0] Beacon Head for TXDMA*/
/*@0x204[11:0] Beacon Head for TXDMA*/
odm_write_2byte(dm, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy);
/*To make sure that if there exists an adapter which would like to send beacon.*/
/*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
/*the beacon cannot be sent by HW.*/
/*2010.06.23. Added by tynli.*/
/*@2010.06.23. Added by tynli.*/
if (is_send_beacon)
odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422);
/*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
/*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
u1b_tmp = odm_read_1byte(dm, REG_CR_8814A + 1);
odm_write_1byte(dm, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0))));
@@ -499,49 +475,47 @@ hal_txbf_8814a_fw_txbf_cmd(
odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
PHYDM_DBG(dm, DBG_TXBF,
"[%s] PageNum0 = %d, PageNum1 = %d period = %d\n", __func__, PageNum0, PageNum1, period);
"[%s] PageNum0 = %d, PageNum1 = %d period = %d\n", __func__,
PageNum0, PageNum1, period);
}
#endif
void
hal_txbf_8814a_enter(
void *dm_void,
u8 bfer_bfee_idx
)
void hal_txbf_8814a_enter(void *dm_void, u8 bfer_bfee_idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i = 0;
u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
u8 bfee_idx = (bfer_bfee_idx & 0xF);
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
struct _RT_BEAMFORMER_ENTRY beamformer_entry;
u16 sta_id = 0, csi_param = 0;
u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i = 0;
u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
u8 bfee_idx = (bfer_bfee_idx & 0xF);
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
struct _RT_BEAMFORMER_ENTRY beamformer_entry;
u16 sta_id = 0, csi_param = 0;
u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;
PHYDM_DBG(dm, DBG_TXBF, "[%s] bfer_idx=%d, bfee_idx=%d\n", __func__, bfer_idx, bfee_idx);
PHYDM_DBG(dm, DBG_TXBF, "[%s] bfer_idx=%d, bfee_idx=%d\n", __func__,
bfer_idx, bfee_idx);
odm_set_mac_reg(dm, REG_SND_PTCL_CTRL_8814A, MASKBYTE1 | MASKBYTE2, 0x0202);
if ((beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) {
if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
beamformer_entry = beamforming_info->beamformer_entry[bfer_idx];
/*Sounding protocol control*/
odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xDB);
/*MAC address/Partial AID of Beamformer*/
/*@MAC address/Partial AID of Beamformer*/
if (bfer_idx == 0) {
for (i = 0; i < 6 ; i++)
for (i = 0; i < 6; i++)
odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), beamformer_entry.mac_addr[i]);
} else {
for (i = 0; i < 6 ; i++)
for (i = 0; i < 6; i++)
odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), beamformer_entry.mac_addr[i]);
}
/*CSI report parameters of Beamformer*/
nc_index = hal_txbf_8814a_get_nrx(dm); /*for 8814A nrx = 3(4 ant), min=0(1 ant)*/
nr_index = beamformer_entry.num_of_sounding_dim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
/*@CSI report parameters of Beamformer*/
nc_index = hal_txbf_8814a_get_nrx(dm); /*@for 8814A nrx = 3(4 ant), min=0(1 ant)*/
nr_index = beamformer_entry.num_of_sounding_dim; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
grouping = 0;
/*for ac = 1, for n = 3*/
/*@for ac = 1, for n = 3*/
if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)
codebookinfo = 1;
else if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT)
@@ -557,10 +531,9 @@ hal_txbf_8814a_enter(
odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, csi_param);
/*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/
odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A + 3, 0x40);
}
if ((beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) {
if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
beamformee_entry = beamforming_info->beamformee_entry[bfee_idx];
hal_txbf_8814a_rf_mode(dm, beamforming_info, bfee_idx);
@@ -577,32 +550,26 @@ hal_txbf_8814a_enter(
} else
odm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, sta_id | BIT(14) | BIT(15) | BIT(12));
/*CSI report parameters of Beamformee*/
/*@CSI report parameters of Beamformee*/
if (bfee_idx == 0) {
/*Get BIT24 & BIT25*/
u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3;
/*@Get BIT24 & BIT25*/
u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3;
odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60);
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, sta_id | BIT(9));
} else
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, sta_id | 0xE200); /*Set BIT25*/
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, sta_id | 0xE200); /*Set BIT25*/
phydm_beamforming_notify(dm);
}
}
void
hal_txbf_8814a_leave(
void *dm_void,
u8 idx
)
void hal_txbf_8814a_leave(void *dm_void, u8 idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMER_ENTRY beamformer_entry;
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMER_ENTRY beamformer_entry;
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
if (idx < BEAMFORMER_ENTRY_NUM) {
beamformer_entry = beamforming_info->beamformer_entry[idx];
@@ -610,9 +577,9 @@ hal_txbf_8814a_leave(
} else
return;
/*Clear P_AID of Beamformee*/
/*Clear MAC address of Beamformer*/
/*Clear Associated Bfmee Sel*/
/*@Clear P_AID of Beamformee*/
/*@Clear MAC address of Beamformer*/
/*@Clear Associated Bfmee Sel*/
if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xD8);
@@ -641,17 +608,13 @@ hal_txbf_8814a_leave(
}
}
void
hal_txbf_8814a_status(
void *dm_void,
u8 idx
)
void hal_txbf_8814a_status(void *dm_void, u8 idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u16 beam_ctrl_val, tmp_val;
u32 beam_ctrl_reg;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY beamform_entry;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u16 beam_ctrl_val, tmp_val;
u32 beam_ctrl_reg;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY beamform_entry;
if (idx < BEAMFORMEE_ENTRY_NUM)
beamform_entry = beamforming_info->beamformee_entry[idx];
@@ -663,7 +626,8 @@ hal_txbf_8814a_status(
else
beam_ctrl_val = beamform_entry.p_aid;
PHYDM_DBG(dm, DBG_TXBF, "@%s, beamform_entry.beamform_entry_state = %d", __func__, beamform_entry.beamform_entry_state);
PHYDM_DBG(dm, DBG_TXBF, "@%s, beamform_entry.beamform_entry_state = %d",
__func__, beamform_entry.beamform_entry_state);
if (idx == 0)
beam_ctrl_reg = REG_TXBF_CTRL_8814A;
@@ -672,7 +636,7 @@ hal_txbf_8814a_status(
beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
}
if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (beamforming_info->apply_v_matrix == true)) {
if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beamforming_info->apply_v_matrix == true) {
if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
beam_ctrl_val |= BIT(9);
else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
@@ -680,26 +644,17 @@ hal_txbf_8814a_status(
else if (beamform_entry.sound_bw == CHANNEL_WIDTH_80)
beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));
} else {
PHYDM_DBG(dm, DBG_TXBF, "@%s, Don't apply Vmatrix", __func__);
PHYDM_DBG(dm, DBG_TXBF, "@%s, Don't apply Vmatrix", __func__);
beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
}
odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
/*disable NDP packet use beamforming */
/*@disable NDP packet use beamforming */
tmp_val = odm_read_2byte(dm, REG_TXBF_CTRL_8814A);
odm_write_2byte(dm, REG_TXBF_CTRL_8814A, tmp_val | BIT(15));
}
void
hal_txbf_8814a_fw_txbf(
void *dm_void,
u8 idx
)
void hal_txbf_8814a_fw_txbf(void *dm_void, u8 idx)
{
#if 0
struct dm_struct *dm = (struct dm_struct *)dm_void;
@@ -715,6 +670,6 @@ hal_txbf_8814a_fw_txbf(
#endif
}
#endif /* (RTL8814A_SUPPORT == 1)*/
#endif /* @(RTL8814A_SUPPORT == 1)*/
#endif

72
hal/phydm/txbf/haltxbf8814a.h
View File

@@ -26,88 +26,52 @@
#define __HAL_TXBF_8814A_H__
#if (RTL8814A_SUPPORT == 1)
#if (BEAMFORMING_SUPPORT == 1)
#ifdef PHYDM_BEAMFORMING_SUPPORT
boolean
phydm_beamforming_set_iqgen_8814A(
void *dm_void
);
phydm_beamforming_set_iqgen_8814A(void *dm_void);
void
hal_txbf_8814a_set_ndpa_rate(
void *dm_void,
u8 BW,
u8 rate
);
void hal_txbf_8814a_set_ndpa_rate(void *dm_void, u8 BW, u8 rate);
u8
hal_txbf_8814a_get_ntx(
void *dm_void
);
u8 hal_txbf_8814a_get_ntx(void *dm_void);
void
hal_txbf_8814a_enter(
void *dm_void,
u8 idx
);
void hal_txbf_8814a_enter(void *dm_void, u8 idx);
void hal_txbf_8814a_leave(void *dm_void, u8 idx);
void
hal_txbf_8814a_leave(
void *dm_void,
u8 idx
);
void hal_txbf_8814a_status(void *dm_void, u8 idx);
void hal_txbf_8814a_reset_tx_path(void *dm_void, u8 idx);
void
hal_txbf_8814a_status(
void *dm_void,
u8 idx
);
void hal_txbf_8814a_get_tx_rate(void *dm_void);
void
hal_txbf_8814a_reset_tx_path(
void *dm_void,
u8 idx
);
void
hal_txbf_8814a_get_tx_rate(
void *dm_void
);
void
hal_txbf_8814a_fw_txbf(
void *dm_void,
u8 idx
);
void hal_txbf_8814a_fw_txbf(void *dm_void, u8 idx);
#else
#define hal_txbf_8814a_set_ndpa_rate(dm_void, BW, rate)
#define hal_txbf_8814a_set_ndpa_rate(dm_void, BW, rate)
#define hal_txbf_8814a_get_ntx(dm_void) 0
#define hal_txbf_8814a_enter(dm_void, idx)
#define hal_txbf_8814a_leave(dm_void, idx)
#define hal_txbf_8814a_status(dm_void, idx)
#define hal_txbf_8814a_reset_tx_path(dm_void, idx)
#define hal_txbf_8814a_reset_tx_path(dm_void, idx)
#define hal_txbf_8814a_get_tx_rate(dm_void)
#define hal_txbf_8814a_fw_txbf(dm_void, idx)
#define phydm_beamforming_set_iqgen_8814A(dm_void) 0
#define hal_txbf_8814a_fw_txbf(dm_void, idx)
#define phydm_beamforming_set_iqgen_8814A(dm_void) 0
#endif
#else
#define hal_txbf_8814a_set_ndpa_rate(dm_void, BW, rate)
#define hal_txbf_8814a_set_ndpa_rate(dm_void, BW, rate)
#define hal_txbf_8814a_get_ntx(dm_void) 0
#define hal_txbf_8814a_enter(dm_void, idx)
#define hal_txbf_8814a_leave(dm_void, idx)
#define hal_txbf_8814a_status(dm_void, idx)
#define hal_txbf_8814a_reset_tx_path(dm_void, idx)
#define hal_txbf_8814a_reset_tx_path(dm_void, idx)
#define hal_txbf_8814a_get_tx_rate(dm_void)
#define hal_txbf_8814a_fw_txbf(dm_void, idx)
#define phydm_beamforming_set_iqgen_8814A(dm_void) 0
#define hal_txbf_8814a_fw_txbf(dm_void, idx)
#define phydm_beamforming_set_iqgen_8814A(dm_void) 0
#endif
#endif

517
hal/phydm/txbf/haltxbf8822b.c
View File

@@ -12,37 +12,35 @@
* more details.
*
*****************************************************************************/
/*============================================================*/
/* Description: */
/* */
/*@============================================================*/
/* @Description: */
/* @*/
/* This file is for 8814A TXBF mechanism */
/* */
/*============================================================*/
/* @*/
/*@============================================================*/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#if (RTL8822B_SUPPORT == 1)
#if (BEAMFORMING_SUPPORT == 1)
#ifdef PHYDM_BEAMFORMING_SUPPORT
u8
hal_txbf_8822b_get_ntx(
void *dm_void
)
u8 hal_txbf_8822b_get_ntx(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 ntx = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 ntx = 0;
#if DEV_BUS_TYPE == RT_USB_INTERFACE
if (dm->support_interface == ODM_ITRF_USB) {
if (*dm->hub_usb_mode == 2) {/*USB3.0*/
if (*dm->hub_usb_mode == 2) { /*USB3.0*/
if (dm->rf_type == RF_4T4R)
ntx = 3;
else if (dm->rf_type == RF_3T3R)
ntx = 2;
else
ntx = 1;
} else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/
} else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/
ntx = 1;
else
ntx = 1;
@@ -58,16 +56,13 @@ hal_txbf_8822b_get_ntx(
}
return ntx;
}
u8
hal_txbf_8822b_get_nrx(
void *dm_void
)
u8 hal_txbf_8822b_get_nrx(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 nrx = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 nrx = 0;
if (dm->rf_type == RF_4T4R)
nrx = 3;
@@ -87,16 +82,13 @@ hal_txbf_8822b_get_nrx(
nrx = 0;
return nrx;
}
/***************SU & MU BFee Entry********************/
void
hal_txbf_8822b_rf_mode(
void *dm_void,
struct _RT_BEAMFORMING_INFO *beamforming_info,
u8 idx
)
void hal_txbf_8822b_rf_mode(
void *dm_void,
struct _RT_BEAMFORMING_INFO *beamforming_info,
u8 idx)
{
#if 0
struct dm_struct *dm = (struct dm_struct *)dm_void;
@@ -118,17 +110,17 @@ hal_txbf_8822b_rf_mode(
/*RF mode table write enable*/
}
if ((beamforming_info->beamformee_su_cnt > 0) || (beamforming_info->beamformee_mu_cnt > 0)) {
if (beamforming_info->beamformee_su_cnt > 0 || beamforming_info->beamformee_mu_cnt > 0) {
for (i = RF_PATH_A; i < RF_PATH_B; i++) {
odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_addr, 0xfffff, 0x18000);
/*Select RX mode*/
odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_data0, 0xfffff, 0xBE77F);
/*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_data1, 0xfffff, 0x226BF);
/*Enable TXIQGEN in RX mode*/
/*@Enable TXIQGEN in RX mode*/
}
odm_set_rf_reg(dm, RF_PATH_A, rf_mode_table_data1, 0xfffff, 0xE26BF);
/*Enable TXIQGEN in RX mode*/
/*@Enable TXIQGEN in RX mode*/
}
for (i = RF_PATH_A; i < RF_PATH_B; i++) {
@@ -137,9 +129,8 @@ hal_txbf_8822b_rf_mode(
}
if (beamforming_info->beamformee_su_cnt > 0) {
/*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*enable BB TxBF ant mapping register*/
/*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/
if (idx == 0) {
/*Nsts = 2 AB*/
@@ -147,18 +138,18 @@ hal_txbf_8822b_rf_mode(
odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
/*odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430);*/
} else {/*IDX =1*/
} else {/*@IDX =1*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433);
odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
/*odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430;*/
}
} else {
odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*1SS by path-A*/
odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*2SS by path-A,B*/
odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*@1SS by path-A*/
odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*@2SS by path-A,B*/
}
if (beamforming_info->beamformee_mu_cnt > 0) {
/*MU STAs share the common setting*/
/*@MU STAs share the common setting*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1);
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433);
odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
@@ -177,7 +168,7 @@ hal_txbf_8822b_download_ndpa(
u16 head_page = 0x7FE;
boolean is_send_beacon = false;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
u16 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/
u16 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*@default reseved 1 page for the IC type which is undefined.*/
struct _RT_BEAMFORMING_INFO *beam_info = GET_BEAMFORM_INFO(adapter);
struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
@@ -198,21 +189,21 @@ hal_txbf_8822b_download_ndpa(
is_send_beacon = true;
}
/*0x204[11:0] Beacon Head for TXDMA*/
/*@0x204[11:0] Beacon Head for TXDMA*/
platform_efio_write_2byte(adapter, REG_FIFOPAGE_CTRL_2_8814A, head_page);
do {
/*Clear beacon valid check bit.*/
/*@Clear beacon valid check bit.*/
bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1);
platform_efio_write_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7)));
/*download NDPA rsvd page.*/
/*@download NDPA rsvd page.*/
if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE);
else
beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
/*check rsvd page download OK.*/
/*@check rsvd page download OK.*/
bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1);
count = 0;
while (!(bcn_valid_reg & BIT(7)) && count < 20) {
@@ -226,19 +217,19 @@ hal_txbf_8822b_download_ndpa(
if (!(bcn_valid_reg & BIT(0)))
RT_DISP(FBEAM, FBEAM_ERROR, ("%s Download RSVD page failed!\n", __func__));
/*0x204[11:0] Beacon Head for TXDMA*/
/*@0x204[11:0] Beacon Head for TXDMA*/
platform_efio_write_2byte(adapter, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy);
/*To make sure that if there exists an adapter which would like to send beacon.*/
/*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
/*the beacon cannot be sent by HW.*/
/*2010.06.23. Added by tynli.*/
/*@2010.06.23. Added by tynli.*/
if (is_send_beacon)
platform_efio_write_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422);
/*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
/*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
u1b_tmp = platform_efio_read_1byte(adapter, REG_CR_8814A + 1);
platform_efio_write_1byte(adapter, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0))));
@@ -292,73 +283,72 @@ hal_txbf_8822b_init(
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
void *adapter = dm->adapter;
odm_set_bb_reg(dm, 0x14c0, BIT(16), 1); /*Enable P1 aggr new packet according to P0 transfer time*/
odm_set_bb_reg(dm, 0x14c0, BIT(15) | BIT14 | BIT13 | BIT12, 10); /*MU Retry Limit*/
odm_set_bb_reg(dm, 0x14c0, BIT(7), 0); /*Disable Tx MU-MIMO until sounding done*/
odm_set_bb_reg(dm, 0x14c0, 0x3F, 0); /* Clear validity of MU STAs */
odm_write_1byte(dm, 0x167c, 0x70); /*MU-MIMO Option as default value*/
odm_write_2byte(dm, 0x1680, 0); /*MU-MIMO Control as default value*/
odm_set_bb_reg(dm, R_0x14c0, BIT(16), 1); /*@Enable P1 aggr new packet according to P0 transfer time*/
odm_set_bb_reg(dm, R_0x14c0, BIT(15) | BIT14 | BIT13 | BIT12, 10); /*@MU Retry Limit*/
odm_set_bb_reg(dm, R_0x14c0, BIT(7), 0); /*@Disable Tx MU-MIMO until sounding done*/
odm_set_bb_reg(dm, R_0x14c0, 0x3F, 0); /* @Clear validity of MU STAs */
odm_write_1byte(dm, 0x167c, 0x70); /*@MU-MIMO Option as default value*/
odm_write_2byte(dm, 0x1680, 0); /*@MU-MIMO Control as default value*/
/* Set MU NDPA rate & BW source */
/* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */
/* @0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */
u1b_tmp = odm_read_1byte(dm, 0x42C);
odm_write_1byte(dm, REG_TXBF_CTRL_8822B, (u1b_tmp | BIT(6)));
/* 0x45F[7:0] = 0x10 (rate=OFDM_6M, BW20) */
/* @0x45F[7:0] = 0x10 (rate=OFDM_6M, BW20) */
odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8822B, 0x10);
/*Temp Settings*/
odm_set_bb_reg(dm, 0x6DC, 0x3F000000, 4); /*STA2's CSI rate is fixed at 6M*/
odm_set_bb_reg(dm, 0x1C94, MASKDWORD, 0xAFFFAFFF); /*Grouping bitmap parameters*/
odm_set_bb_reg(dm, R_0x6dc, 0x3F000000, 4); /*STA2's CSI rate is fixed at 6M*/
odm_set_bb_reg(dm, R_0x1c94, MASKDWORD, 0xAFFFAFFF); /*@Grouping bitmap parameters*/
/* Init HW variable */
/* @Init HW variable */
beamforming_info->reg_mu_tx_ctrl = odm_read_4byte(dm, 0x14c0);
if (dm->rf_type == RF_2T2R) { /*2T2R*/
if (dm->rf_type == RF_2T2R) { /*@2T2R*/
PHYDM_DBG(dm, DBG_TXBF, "%s: rf_type is 2T2R\n", __func__);
config_phydm_trx_mode_8822b(dm, (enum bb_path)3, (enum bb_path)3, true);/*Tx2path*/
}
#if (OMNIPEEK_SNIFFER_ENABLED == 1)
/* Config HW to receive packet on the user position from registry for sniffer mode. */
/* odm_set_bb_reg(dm, 0xB00, BIT(9), 1);*/ /* For A-cut only. RegB00[9] = 1 (enable PMAC Rx) */
odm_set_bb_reg(dm, 0xB54, BIT(30), 1); /* RegB54[30] = 1 (force user position) */
odm_set_bb_reg(dm, 0xB54, (BIT(29) | BIT28), adapter->MgntInfo.sniff_user_position); /* RegB54[29:28] = user position (0~3) */
PHYDM_DBG(dm, DBG_TXBF, "Set adapter->MgntInfo.sniff_user_position=%#X\n", adapter->MgntInfo.sniff_user_position);
/* @Config HW to receive packet on the user position from registry for sniffer mode. */
/* odm_set_bb_reg(dm, R_0xb00, BIT(9), 1);*/ /* For A-cut only. RegB00[9] = 1 (enable PMAC Rx) */
odm_set_bb_reg(dm, R_0xb54, BIT(30), 1); /* RegB54[30] = 1 (force user position) */
odm_set_bb_reg(dm, R_0xb54, (BIT(29) | BIT28), adapter->MgntInfo.sniff_user_position); /* RegB54[29:28] = user position (0~3) */
PHYDM_DBG(dm, DBG_TXBF,
"Set adapter->MgntInfo.sniff_user_position=%#X\n",
adapter->MgntInfo.sniff_user_position);
#endif
}
#endif
void
hal_txbf_8822b_enter(
void *dm_void,
u8 bfer_bfee_idx
)
void hal_txbf_8822b_enter(
void *dm_void,
u8 bfer_bfee_idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i = 0;
u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
u8 bfee_idx = (bfer_bfee_idx & 0xF);
u16 csi_param = 0;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry;
struct _RT_BEAMFORMER_ENTRY *beamformer_entry;
u16 value16, sta_id = 0;
u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;
u32 gid_valid, user_position_l, user_position_h;
u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e};
u8 u1b_tmp;
u32 u4b_tmp;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i = 0;
u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
u8 bfee_idx = (bfer_bfee_idx & 0xF);
u16 csi_param = 0;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry;
struct _RT_BEAMFORMER_ENTRY *beamformer_entry;
u16 value16, sta_id = 0;
u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;
u32 gid_valid, user_position_l, user_position_h;
u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e};
u8 u1b_tmp;
u32 u4b_tmp;
RT_DISP(FBEAM, FBEAM_FUN, ("%s: bfer_bfee_idx=%d, bfer_idx=%d, bfee_idx=%d\n", __func__, bfer_bfee_idx, bfer_idx, bfee_idx));
/*************SU BFer Entry Init*************/
if ((beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) {
if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
beamformer_entry = &beamforming_info->beamformer_entry[bfer_idx];
beamformer_entry->is_mu_ap = false;
/*Sounding protocol control*/
odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB);
for (i = 0; i < MAX_BEAMFORMER_SU; i++) {
if ((beamforming_info->beamformer_su_reg_maping & BIT(i)) == 0) {
beamforming_info->beamformer_su_reg_maping |= BIT(i);
@@ -367,22 +357,22 @@ hal_txbf_8822b_enter(
}
}
/*MAC address/Partial AID of Beamformer*/
/*@MAC address/Partial AID of Beamformer*/
if (beamformer_entry->su_reg_index == 0) {
for (i = 0; i < 6 ; i++)
for (i = 0; i < 6; i++)
odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), beamformer_entry->mac_addr[i]);
} else {
for (i = 0; i < 6 ; i++)
for (i = 0; i < 6; i++)
odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8822B + i), beamformer_entry->mac_addr[i]);
}
/*CSI report parameters of Beamformer*/
nc_index = hal_txbf_8822b_get_nrx(dm); /*for 8814A nrx = 3(4 ant), min=0(1 ant)*/
nr_index = beamformer_entry->num_of_sounding_dim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
/*@CSI report parameters of Beamformer*/
nc_index = hal_txbf_8822b_get_nrx(dm); /*@for 8814A nrx = 3(4 ant), min=0(1 ant)*/
nr_index = beamformer_entry->num_of_sounding_dim; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
grouping = 0;
/*for ac = 1, for n = 3*/
/*@for ac = 1, for n = 3*/
if (beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)
codebookinfo = 1;
else if (beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT)
@@ -398,11 +388,10 @@ hal_txbf_8822b_enter(
odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, csi_param);
/*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/
odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B + 3, 0x70);
}
/*************SU BFee Entry Init*************/
if ((beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) {
if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
p_beamformee_entry = &beamforming_info->beamformee_entry[bfee_idx];
p_beamformee_entry->is_mu_sta = false;
hal_txbf_8822b_rf_mode(dm, beamforming_info, bfee_idx);
@@ -427,21 +416,21 @@ hal_txbf_8822b_enter(
} else
odm_write_2byte(dm, REG_TXBF_CTRL_8822B + 2, sta_id | BIT(14) | BIT(15) | BIT(12));
/*CSI report parameters of Beamformee*/
/*@CSI report parameters of Beamformee*/
if (p_beamformee_entry->su_reg_index == 0) {
/*Get BIT24 & BIT25*/
u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3) & 0x3;
/*@Get BIT24 & BIT25*/
u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3) & 0x3;
odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3, tmp | 0x60);
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B, sta_id | BIT(9));
} else
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2, sta_id | 0xE200); /*Set BIT25*/
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2, sta_id | 0xE200); /*Set BIT25*/
phydm_beamforming_notify(dm);
}
/*************MU BFer Entry Init*************/
if ((beamforming_info->beamformer_mu_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) {
if (beamforming_info->beamformer_mu_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
beamformer_entry = &beamforming_info->beamformer_entry[bfer_idx];
beamforming_info->mu_ap_index = bfer_idx;
beamformer_entry->is_mu_ap = true;
@@ -453,14 +442,14 @@ hal_txbf_8822b_enter(
/*Sounding protocol control*/
odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB);
/* MAC address */
for (i = 0; i < 6 ; i++)
/* @MAC address */
for (i = 0; i < 6; i++)
odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), beamformer_entry->mac_addr[i]);
/* Set partial AID */
odm_write_2byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + 6), beamformer_entry->p_aid);
/* Fill our AID to 0x1680[11:0] and [13:12] = 2b'00, BF report segment select to 3895 bytes*/
/* @Fill our AID to 0x1680[11:0] and [13:12] = 2b'00, BF report segment select to 3895 bytes*/
u1b_tmp = odm_read_1byte(dm, 0x1680);
u1b_tmp = (beamformer_entry->p_aid) & 0xFFF;
odm_write_1byte(dm, 0x1680, u1b_tmp);
@@ -477,23 +466,22 @@ hal_txbf_8822b_enter(
u1b_tmp |= 0x30;
odm_write_1byte(dm, REG_RXFLTMAP1_8822B, u1b_tmp);
/*CSI report parameters of Beamformer*/
nc_index = hal_txbf_8822b_get_nrx(dm); /* Depend on RF type */
nr_index = 1; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
/*@CSI report parameters of Beamformer*/
nc_index = hal_txbf_8822b_get_nrx(dm); /* @Depend on RF type */
nr_index = 1; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
grouping = 0; /*no grouping*/
codebookinfo = 1; /*7 bit for psi, 9 bit for phi*/
codebookinfo = 1; /*@7 bit for psi, 9 bit for phi*/
coefficientsize = 0; /*This is nothing really matter*/
csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index));
odm_write_2byte(dm, 0x6F4, csi_param);
/*for B-cut*/
odm_set_bb_reg(dm, 0x6A0, BIT(20), 0);
odm_set_bb_reg(dm, 0x688, BIT(20), 0);
/*@for B-cut*/
odm_set_bb_reg(dm, R_0x6a0, BIT(20), 0);
odm_set_bb_reg(dm, R_0x688, BIT(20), 0);
}
/*************MU BFee Entry Init*************/
if ((beamforming_info->beamformee_mu_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) {
if (beamforming_info->beamformee_mu_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
p_beamformee_entry = &beamforming_info->beamformee_entry[bfee_idx];
p_beamformee_entry->is_mu_sta = true;
for (i = 0; i < MAX_BEAMFORMEE_MU; i++) {
@@ -568,25 +556,27 @@ hal_txbf_8822b_enter(
beamforming_info->reg_mu_tx_ctrl |= (p_beamformee_entry->mu_reg_index << 8) & (BIT(8) | BIT(9) | BIT(10));
odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
odm_set_bb_reg(dm, 0x14c4, MASKDWORD, 0); /*Reset gid_valid table*/
odm_set_bb_reg(dm, 0x14c8, MASKDWORD, user_position_l);
odm_set_bb_reg(dm, 0x14cc, MASKDWORD, user_position_h);
odm_set_bb_reg(dm, R_0x14c4, MASKDWORD, 0); /*Reset gid_valid table*/
odm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l);
odm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h);
/*set validity of MU STAs*/
beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0;
beamforming_info->reg_mu_tx_ctrl |= beamforming_info->beamformee_mu_reg_maping & 0x3F;
odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
PHYDM_DBG(dm, DBG_TXBF, "@%s, reg_mu_tx_ctrl = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n",
__func__, beamforming_info->reg_mu_tx_ctrl, user_position_l, user_position_h);
PHYDM_DBG(dm, DBG_TXBF,
"@%s, reg_mu_tx_ctrl = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n",
__func__, beamforming_info->reg_mu_tx_ctrl,
user_position_l, user_position_h);
value16 = odm_read_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index]);
value16 &= 0xFE00; /*Clear PAID*/
value16 |= BIT(9); /*Enable MU BFee*/
value16 &= 0xFE00; /*@Clear PAID*/
value16 |= BIT(9); /*@Enable MU BFee*/
value16 |= p_beamformee_entry->p_aid;
odm_write_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index], value16);
/* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */
/* @0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */
u1b_tmp = odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3);
u1b_tmp |= 0xD0; /* Set bit 28, 30, 31 to 3b'111*/
odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, u1b_tmp);
@@ -594,7 +584,7 @@ hal_txbf_8822b_enter(
odm_write_1byte(dm, REG_NDPA_RATE_8822B, 0x4);
u1b_tmp = odm_read_1byte(dm, REG_NDPA_OPT_CTRL_8822B);
u1b_tmp &= 0xFC; /* Clear bit 0, 1*/
u1b_tmp &= 0xFC; /* @Clear bit 0, 1*/
odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8822B, u1b_tmp);
u4b_tmp = odm_read_4byte(dm, REG_SND_PTCL_CTRL_8822B);
@@ -605,7 +595,7 @@ hal_txbf_8822b_enter(
u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP0_8822B + 1);
u1b_tmp |= 0x40;
odm_write_1byte(dm, REG_RXFLTMAP0_8822B + 1, u1b_tmp);
/* End of MAC registers setting */
/* @End of MAC registers setting */
hal_txbf_8822b_rf_mode(dm, beamforming_info, bfee_idx);
#if (SUPPORT_MU_BF == 1)
@@ -628,26 +618,25 @@ hal_txbf_8822b_enter(
odm_write_4byte(dm, ctrl_info_offset, (p_beamformee_entry->mu_reg_index + 1) << 16);
odm_write_1byte(dm, 0x81, 0x80); /*RPTBUF ready*/
PHYDM_DBG(dm, DBG_TXBF, "@%s, mac_id = %d, ctrl_info_offset = 0x%x, mu_reg_index = %x\n",
__func__, p_beamformee_entry->mac_id, ctrl_info_offset, p_beamformee_entry->mu_reg_index);
PHYDM_DBG(dm, DBG_TXBF,
"@%s, mac_id = %d, ctrl_info_offset = 0x%x, mu_reg_index = %x\n",
__func__, p_beamformee_entry->mac_id,
ctrl_info_offset,
p_beamformee_entry->mu_reg_index);
}
#endif
}
}
void
hal_txbf_8822b_leave(
void *dm_void,
u8 idx
)
void hal_txbf_8822b_leave(
void *dm_void,
u8 idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMER_ENTRY *beamformer_entry;
struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry;
u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e};
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMER_ENTRY *beamformer_entry;
struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry;
u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e};
if (idx < BEAMFORMER_ENTRY_NUM) {
beamformer_entry = &beamforming_info->beamformer_entry[idx];
@@ -655,9 +644,9 @@ hal_txbf_8822b_leave(
} else
return;
/*Clear P_AID of Beamformee*/
/*Clear MAC address of Beamformer*/
/*Clear Associated Bfmee Sel*/
/*@Clear P_AID of Beamformee*/
/*@Clear MAC address of Beamformer*/
/*@Clear Associated Bfmee Sel*/
if (beamformer_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) {
odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xD8);
@@ -673,7 +662,7 @@ hal_txbf_8822b_leave(
}
beamforming_info->beamformer_su_reg_maping &= ~(BIT(beamformer_entry->su_reg_index));
beamformer_entry->su_reg_index = 0xFF;
} else { /*MU BFer */
} else { /*@MU BFer */
/*set validity of MU STA0 and MU STA1*/
beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0;
odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
@@ -695,18 +684,17 @@ hal_txbf_8822b_leave(
odm_write_2byte(dm, REG_TXBF_CTRL_8822B + 2, 0x0 | BIT(14) | BIT(15) | BIT(12));
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2,
odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2) & 0x60);
odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2) & 0x60);
}
beamforming_info->beamformee_su_reg_maping &= ~(BIT(p_beamformee_entry->su_reg_index));
p_beamformee_entry->su_reg_index = 0xFF;
} else { /*MU BFee */
/*Disable sending NDPA & BF-rpt-poll to this BFee*/
} else { /*@MU BFee */
/*@Disable sending NDPA & BF-rpt-poll to this BFee*/
odm_write_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index], 0);
/*set validity of MU STA*/
beamforming_info->reg_mu_tx_ctrl &= ~(BIT(p_beamformee_entry->mu_reg_index));
odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
p_beamformee_entry->is_mu_sta = false;
beamforming_info->beamformee_mu_reg_maping &= ~(BIT(p_beamformee_entry->mu_reg_index));
p_beamformee_entry->mu_reg_index = 0xFF;
@@ -714,20 +702,17 @@ hal_txbf_8822b_leave(
}
}
/***********SU & MU BFee Entry Only when souding done****************/
void
hal_txbf_8822b_status(
void *dm_void,
u8 beamform_idx
)
void hal_txbf_8822b_status(
void *dm_void,
u8 beamform_idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u16 beam_ctrl_val, tmp_val;
u32 beam_ctrl_reg;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY *beamform_entry;
boolean is_mu_sounding = beamforming_info->is_mu_sounding, is_bitmap_ready = false;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u16 beam_ctrl_val, tmp_val;
u32 beam_ctrl_reg;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY *beamform_entry;
boolean is_mu_sounding = beamforming_info->is_mu_sounding, is_bitmap_ready = false;
u16 bitmap;
u8 idx, gid, i;
u8 id1, id0;
@@ -742,13 +727,14 @@ hal_txbf_8822b_status(
/*SU sounding done */
if (is_mu_sounding == false) {
if (phydm_acting_determine(dm, phydm_acting_as_ibss))
beam_ctrl_val = beamform_entry->mac_id;
else
beam_ctrl_val = beamform_entry->p_aid;
PHYDM_DBG(dm, DBG_TXBF, "@%s, beamform_entry.beamform_entry_state = %d", __func__, beamform_entry->beamform_entry_state);
PHYDM_DBG(dm, DBG_TXBF,
"@%s, beamform_entry.beamform_entry_state = %d",
__func__, beamform_entry->beamform_entry_state);
if (beamform_entry->su_reg_index == 0)
beam_ctrl_reg = REG_TXBF_CTRL_8822B;
@@ -765,53 +751,62 @@ hal_txbf_8822b_status(
else if (beamform_entry->sound_bw == CHANNEL_WIDTH_80)
beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));
} else {
PHYDM_DBG(dm, DBG_TXBF, "@%s, Don't apply Vmatrix", __func__);
PHYDM_DBG(dm, DBG_TXBF, "@%s, Don't apply Vmatrix",
__func__);
beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
}
odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
/*disable NDP packet use beamforming */
/*@disable NDP packet use beamforming */
tmp_val = odm_read_2byte(dm, REG_TXBF_CTRL_8822B);
odm_write_2byte(dm, REG_TXBF_CTRL_8822B, tmp_val | BIT(15));
} else {
PHYDM_DBG(dm, DBG_TXBF, "@%s, MU Sounding Done\n", __func__);
/*MU sounding done */
if (1) { /* (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { */
PHYDM_DBG(dm, DBG_TXBF, "@%s, BEAMFORMING_ENTRY_STATE_PROGRESSED\n", __func__);
PHYDM_DBG(dm, DBG_TXBF, "@%s, MU Sounding Done\n", __func__);
/*@MU sounding done */
if (1) { /* @(beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { */
PHYDM_DBG(dm, DBG_TXBF,
"@%s, BEAMFORMING_ENTRY_STATE_PROGRESSED\n",
__func__);
value32 = odm_get_bb_reg(dm, 0x1684, MASKDWORD);
value32 = odm_get_bb_reg(dm, R_0x1684, MASKDWORD);
is_sounding_success[0] = (value32 & BIT(10)) ? 1 : 0;
is_sounding_success[1] = (value32 & BIT(26)) ? 1 : 0;
value32 = odm_get_bb_reg(dm, 0x1688, MASKDWORD);
value32 = odm_get_bb_reg(dm, R_0x1688, MASKDWORD);
is_sounding_success[2] = (value32 & BIT(10)) ? 1 : 0;
is_sounding_success[3] = (value32 & BIT(26)) ? 1 : 0;
value32 = odm_get_bb_reg(dm, 0x168C, MASKDWORD);
value32 = odm_get_bb_reg(dm, R_0x168c, MASKDWORD);
is_sounding_success[4] = (value32 & BIT(10)) ? 1 : 0;
is_sounding_success[5] = (value32 & BIT(26)) ? 1 : 0;
PHYDM_DBG(dm, DBG_TXBF, "@%s, is_sounding_success STA1:%d, STA2:%d, STA3:%d, STA4:%d, STA5:%d, STA6:%d\n",
__func__, is_sounding_success[0], is_sounding_success[1], is_sounding_success[2], is_sounding_success[3], is_sounding_success[4], is_sounding_success[5]);
PHYDM_DBG(dm, DBG_TXBF,
"@%s, is_sounding_success STA1:%d, STA2:%d, STA3:%d, STA4:%d, STA5:%d, STA6:%d\n",
__func__, is_sounding_success[0],
is_sounding_success[1],
is_sounding_success[2],
is_sounding_success[3],
is_sounding_success[4],
is_sounding_success[5]);
value32 = odm_get_bb_reg(dm, 0xF4C, 0xFFFF0000);
/* odm_set_bb_reg(dm, 0x19E0, MASKHWORD, 0xFFFF);Let MAC ignore bitmap */
value32 = odm_get_bb_reg(dm, R_0xf4c, 0xFFFF0000);
/* odm_set_bb_reg(dm, R_0x19e0, MASKHWORD, 0xFFFF);Let MAC ignore bitmap */
is_bitmap_ready = (boolean)((value32 & BIT(15)) >> 15);
bitmap = (u16)(value32 & 0x3FFF);
for (idx = 0; idx < 15; idx++) {
if (idx < 5) {/*bit0~4*/
if (idx < 5) { /*@bit0~4*/
id0 = 0;
id1 = (u8)(idx + 1);
} else if (idx < 9) { /*bit5~8*/
} else if (idx < 9) { /*@bit5~8*/
id0 = 1;
id1 = (u8)(idx - 3);
} else if (idx < 12) { /*bit9~11*/
} else if (idx < 12) { /*@bit9~11*/
id0 = 2;
id1 = (u8)(idx - 6);
} else if (idx < 14) { /*bit12~13*/
} else if (idx < 14) { /*@bit12~13*/
id0 = 3;
id1 = (u8)(idx - 8);
} else { /*bit14*/
} else { /*@bit14*/
id0 = 4;
id1 = (u8)(idx - 9);
}
@@ -838,7 +833,7 @@ hal_txbf_8822b_status(
for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
beamform_entry = &beamforming_info->beamformee_entry[i];
if ((beamform_entry->is_mu_sta) && (beamform_entry->mu_reg_index < 6)) {
if (beamform_entry->is_mu_sta && beamform_entry->mu_reg_index < 6) {
value32 = gid_valid[beamform_entry->mu_reg_index];
for (idx = 0; idx < 4; idx++) {
beamform_entry->gid_valid[idx] = (u8)(value32 & 0xFF);
@@ -851,10 +846,10 @@ hal_txbf_8822b_status(
beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));
beamforming_info->reg_mu_tx_ctrl |= ((idx << 8) & (BIT(8) | BIT(9) | BIT(10)));
odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
odm_set_mac_reg(dm, 0x14C4, MASKDWORD, gid_valid[idx]); /*set MU STA gid valid table*/
odm_set_mac_reg(dm, R_0x14c4, MASKDWORD, gid_valid[idx]); /*set MU STA gid valid table*/
}
/*Enable TxMU PPDU*/
/*@Enable TxMU PPDU*/
if (beamforming_info->dbg_disable_mu_tx == false)
beamforming_info->reg_mu_tx_ctrl |= BIT(7);
else
@@ -865,15 +860,13 @@ hal_txbf_8822b_status(
}
/*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/
void
hal_txbf_8822b_config_gtab(
void *dm_void
)
void hal_txbf_8822b_config_gtab(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL;
u32 gid_valid = 0, user_position_l = 0, user_position_h = 0, i;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL;
u32 gid_valid = 0, user_position_l = 0, user_position_h = 0, i;
if (beamforming_info->mu_ap_index < BEAMFORMER_ENTRY_NUM)
beamformer_entry = &beamforming_info->beamformer_entry[beamforming_info->mu_ap_index];
@@ -882,7 +875,7 @@ hal_txbf_8822b_config_gtab(
PHYDM_DBG(dm, DBG_TXBF, "%s==>\n", __func__);
/*For GID 0~31*/
/*@For GID 0~31*/
for (i = 0; i < 4; i++)
gid_valid |= (beamformer_entry->gid_valid[i] << (i << 3));
for (i = 0; i < 8; i++) {
@@ -894,18 +887,19 @@ hal_txbf_8822b_config_gtab(
/*select MU STA0 table*/
beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));
odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
odm_set_bb_reg(dm, 0x14c4, MASKDWORD, gid_valid);
odm_set_bb_reg(dm, 0x14c8, MASKDWORD, user_position_l);
odm_set_bb_reg(dm, 0x14cc, MASKDWORD, user_position_h);
odm_set_bb_reg(dm, R_0x14c4, MASKDWORD, gid_valid);
odm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l);
odm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h);
PHYDM_DBG(dm, DBG_TXBF, "%s: STA0: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n",
__func__, gid_valid, user_position_l, user_position_h);
PHYDM_DBG(dm, DBG_TXBF,
"%s: STA0: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n",
__func__, gid_valid, user_position_l, user_position_h);
gid_valid = 0;
user_position_l = 0;
user_position_h = 0;
/*For GID 32~64*/
/*@For GID 32~64*/
for (i = 4; i < 8; i++)
gid_valid |= (beamformer_entry->gid_valid[i] << ((i - 4) << 3));
for (i = 8; i < 16; i++) {
@@ -918,22 +912,20 @@ hal_txbf_8822b_config_gtab(
beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));
beamforming_info->reg_mu_tx_ctrl |= BIT(8);
odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
odm_set_bb_reg(dm, 0x14c4, MASKDWORD, gid_valid);
odm_set_bb_reg(dm, 0x14c8, MASKDWORD, user_position_l);
odm_set_bb_reg(dm, 0x14cc, MASKDWORD, user_position_h);
odm_set_bb_reg(dm, R_0x14c4, MASKDWORD, gid_valid);
odm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l);
odm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h);
PHYDM_DBG(dm, DBG_TXBF, "%s: STA1: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n",
__func__, gid_valid, user_position_l, user_position_h);
PHYDM_DBG(dm, DBG_TXBF,
"%s: STA1: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n",
__func__, gid_valid, user_position_l, user_position_h);
/* Set validity of MU STA0 and MU STA1*/
beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0;
beamforming_info->reg_mu_tx_ctrl |= 0x3; /* STA0, STA1*/
odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
}
#if 0
/*This function translate the bitmap to GTAB*/
void
@@ -948,19 +940,19 @@ haltxbf8822b_gtab_translation(
u32 user_position_msb[6] = {0};
for (idx = 0; idx < 15; idx++) {
if (idx < 5) {/*bit0~4*/
if (idx < 5) {/*@bit0~4*/
id0 = 0;
id1 = (u8)(idx + 1);
} else if (idx < 9) { /*bit5~8*/
} else if (idx < 9) { /*@bit5~8*/
id0 = 1;
id1 = (u8)(idx - 3);
} else if (idx < 12) { /*bit9~11*/
} else if (idx < 12) { /*@bit9~11*/
id0 = 2;
id1 = (u8)(idx - 6);
} else if (idx < 14) { /*bit12~13*/
} else if (idx < 14) { /*@bit12~13*/
id0 = 3;
id1 = (u8)(idx - 8);
} else { /*bit14*/
} else { /*@bit14*/
id0 = 4;
id1 = (u8)(idx - 9);
}
@@ -988,22 +980,19 @@ haltxbf8822b_gtab_translation(
user_position_msb[id0] |= (1 << ((gid - 16) << 1));
/*user_position_msb[id1] |= (0 << ((gid - 16) << 1));*/
}
}
for (idx = 0; idx < 6; idx++) {
/*dbg_print("gid_valid[%d] = 0x%x\n", idx, gid_valid[idx]);
/*@dbg_print("gid_valid[%d] = 0x%x\n", idx, gid_valid[idx]);
dbg_print("user_position[%d] = 0x%x %x\n", idx, user_position_msb[idx], user_position_lsb[idx]);*/
}
}
#endif
void
hal_txbf_8822b_fw_txbf(
void *dm_void,
u8 idx
)
void hal_txbf_8822b_fw_txbf(
void *dm_void,
u8 idx)
{
#if 0
struct _RT_BEAMFORMING_INFO *beam_info = GET_BEAMFORM_INFO(adapter);
@@ -1020,93 +1009,79 @@ hal_txbf_8822b_fw_txbf(
#if (defined(CONFIG_BB_TXBF_API))
/*this function is only used for BFer*/
void
phydm_8822btxbf_rfmode(
void *dm_void,
u8 su_bfee_cnt,
u8 mu_bfee_cnt
)
void phydm_8822btxbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i;
if (dm->rf_type == RF_1T1R)
return;
if ((su_bfee_cnt > 0) || (mu_bfee_cnt > 0)) {
if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
for (i = RF_PATH_A; i <= RF_PATH_B; i++) {
odm_set_rf_reg(dm, (enum rf_path)i, 0xEF, BIT(19), 0x1); /*RF mode table write enable*/
odm_set_rf_reg(dm, (enum rf_path)i, 0x33, 0xF, 3); /*Select RX mode*/
odm_set_rf_reg(dm, (enum rf_path)i, 0x3E, 0xfffff, 0x00036); /*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, 0x3F, 0xfffff, 0x5AFCE); /*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, 0xEF, BIT(19), 0x0); /*RF mode table write disable*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19), 0x1); /*RF mode table write enable*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3); /*Select RX mode*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff, 0x00036); /*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff, 0x5AFCE); /*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19), 0x0); /*RF mode table write disable*/
}
}
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(30), 1); /*if Nsts > Nc, don't apply V matrix*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(30), 1); /*@if Nsts > Nc, don't apply V matrix*/
if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
/*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*enable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); /*ignore user since 8822B only 2Tx*/
/*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); /*@ignore user since 8822B only 2Tx*/
/*Nsts = 2 AB*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433);
odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
} else {
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x0); /*enable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 0); /*ignore user since 8822B only 2Tx*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x0); /*@enable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 0); /*@ignore user since 8822B only 2Tx*/
odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*1SS by path-A*/
odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*2SS by path-A,B*/
odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*@1SS by path-A*/
odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*@2SS by path-A,B*/
}
}
/*this function is for BFer bug workaround*/
void
phydm_8822b_sutxbfer_workaroud(
void *dm_void,
boolean enable_su_bfer,
u8 nc,
u8 nr,
u8 ng,
u8 CB,
u8 BW,
boolean is_vht
)
void phydm_8822b_sutxbfer_workaroud(void *dm_void, boolean enable_su_bfer,
u8 nc, u8 nr, u8 ng, u8 CB, u8 BW,
boolean is_vht)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (enable_su_bfer) {
odm_set_bb_reg(dm, 0x19f8, BIT(22) | BIT(21) | BIT(20), 0x1);
odm_set_bb_reg(dm, 0x19f8, BIT(25) | BIT(24) | BIT(23), 0x0);
odm_set_bb_reg(dm, 0x19f8, BIT(16), 0x1);
odm_set_bb_reg(dm, R_0x19f8, BIT(22) | BIT(21) | BIT(20), 0x1);
odm_set_bb_reg(dm, R_0x19f8, BIT(25) | BIT(24) | BIT(23), 0x0);
odm_set_bb_reg(dm, R_0x19f8, BIT(16), 0x1);
if (is_vht)
odm_set_bb_reg(dm, 0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x1f);
odm_set_bb_reg(dm, R_0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x1f);
else
odm_set_bb_reg(dm, 0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x22);
odm_set_bb_reg(dm, R_0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x22);
odm_set_bb_reg(dm, 0x19f0, BIT(7) | BIT(6), nc);
odm_set_bb_reg(dm, 0x19f0, BIT(9) | BIT(8), nr);
odm_set_bb_reg(dm, 0x19f0, BIT(11) | BIT(10), ng);
odm_set_bb_reg(dm, 0x19f0, BIT(13) | BIT(12), CB);
odm_set_bb_reg(dm, 0xb58, BIT(3) | BIT(2), BW);
odm_set_bb_reg(dm, 0xb58, BIT(7) | BIT(6) | BIT(5) | BIT(4), 0x0);
odm_set_bb_reg(dm, 0xb58, BIT(9) | BIT(8), BW);
odm_set_bb_reg(dm, 0xb58, BIT(13) | BIT(12) | BIT(11) | BIT(10), 0x0);
} else
odm_set_bb_reg(dm, 0x19f8, BIT(16), 0x0);
PHYDM_DBG(dm, DBG_TXBF, "[%s] enable_su_bfer = %d, is_vht = %d\n", __func__, enable_su_bfer, is_vht);
PHYDM_DBG(dm, DBG_TXBF, "[%s] nc = %d, nr = %d, ng = %d, CB = %d, BW = %d\n", __func__, nc, nr, ng, CB, BW);
odm_set_bb_reg(dm, R_0x19f0, BIT(7) | BIT(6), nc);
odm_set_bb_reg(dm, R_0x19f0, BIT(9) | BIT(8), nr);
odm_set_bb_reg(dm, R_0x19f0, BIT(11) | BIT(10), ng);
odm_set_bb_reg(dm, R_0x19f0, BIT(13) | BIT(12), CB);
odm_set_bb_reg(dm, R_0xb58, BIT(3) | BIT(2), BW);
odm_set_bb_reg(dm, R_0xb58, BIT(7) | BIT(6) | BIT(5) | BIT(4), 0x0);
odm_set_bb_reg(dm, R_0xb58, BIT(9) | BIT(8), BW);
odm_set_bb_reg(dm, R_0xb58, BIT(13) | BIT(12) | BIT(11) | BIT(10), 0x0);
} else {
odm_set_bb_reg(dm, R_0x19f8, BIT(16), 0x0);
}
PHYDM_DBG(dm, DBG_TXBF, "[%s] enable_su_bfer = %d, is_vht = %d\n",
__func__, enable_su_bfer, is_vht);
PHYDM_DBG(dm, DBG_TXBF,
"[%s] nc = %d, nr = %d, ng = %d, CB = %d, BW = %d\n",
__func__, nc, nr, ng, CB, BW);
}
#endif
#endif /* (RTL8822B_SUPPORT == 1)*/
#endif /* @(RTL8822B_SUPPORT == 1)*/

63
hal/phydm/txbf/haltxbf8822b.h
View File

@@ -26,38 +26,26 @@
#define __HAL_TXBF_8822B_H__
#if (RTL8822B_SUPPORT == 1)
#if (BEAMFORMING_SUPPORT == 1)
#ifdef PHYDM_BEAMFORMING_SUPPORT
void
hal_txbf_8822b_enter(
void *dm_void,
u8 idx
);
void hal_txbf_8822b_enter(
void *dm_void,
u8 idx);
void hal_txbf_8822b_leave(
void *dm_void,
u8 idx);
void
hal_txbf_8822b_leave(
void *dm_void,
u8 idx
);
void hal_txbf_8822b_status(
void *dm_void,
u8 beamform_idx);
void hal_txbf_8822b_config_gtab(
void *dm_void);
void
hal_txbf_8822b_status(
void *dm_void,
u8 beamform_idx
);
void
hal_txbf_8822b_config_gtab(
void *dm_void
);
void
hal_txbf_8822b_fw_txbf(
void *dm_void,
u8 idx
);
void hal_txbf_8822b_fw_txbf(
void *dm_void,
u8 idx);
#else
#define hal_txbf_8822b_enter(dm_void, idx)
#define hal_txbf_8822b_leave(dm_void, idx)
@@ -68,24 +56,11 @@ hal_txbf_8822b_fw_txbf(
#endif
#if (defined(CONFIG_BB_TXBF_API))
void
phydm_8822btxbf_rfmode(
void *dm_void,
u8 su_bfee_cnt,
u8 mu_bfee_cnt
);
void phydm_8822btxbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt);
void
phydm_8822b_sutxbfer_workaroud(
void *dm_void,
boolean enable_su_bfer,
u8 nc,
u8 nr,
u8 ng,
u8 CB,
u8 BW,
boolean is_vht
);
void phydm_8822b_sutxbfer_workaroud(void *dm_void, boolean enable_su_bfer,
u8 nc, u8 nr, u8 ng, u8 CB, u8 BW,
boolean is_vht);
#else
#define phydm_8822btxbf_rfmode(dm_void, su_bfee_cnt, mu_bfee_cnt)

922
hal/phydm/txbf/haltxbfinterface.c
View File

File diff suppressed because it is too large Load Diff

148
hal/phydm/txbf/haltxbfinterface.h
View File

@@ -25,87 +25,74 @@
#ifndef __HAL_TXBF_INTERFACE_H__
#define __HAL_TXBF_INTERFACE_H__
#if (BEAMFORMING_SUPPORT == 1)
#ifdef PHYDM_BEAMFORMING_SUPPORT
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define a_SifsTime ((IS_WIRELESS_MODE_5G(adapter)|| IS_WIRELESS_MODE_N_24G(adapter))? 16 : 10)
#define a_SifsTime ((IS_WIRELESS_MODE_5G(adapter) || IS_WIRELESS_MODE_N_24G(adapter)) ? 16 : 10)
void
beamforming_gid_paid(
void *adapter,
PRT_TCB tcb
);
void beamforming_gid_paid(
void *adapter,
PRT_TCB tcb);
enum rt_status
beamforming_get_report_frame(
void *adapter,
PRT_RFD rfd,
POCTET_STRING p_pdu_os
);
void *adapter,
PRT_RFD rfd,
POCTET_STRING p_pdu_os);
void
beamforming_get_ndpa_frame(
void *dm_void,
OCTET_STRING pdu_os
);
void beamforming_get_ndpa_frame(
void *dm_void,
OCTET_STRING pdu_os);
boolean
send_fw_ht_ndpa_packet(
void *dm_void,
u8 *RA,
enum channel_width BW
);
void *dm_void,
u8 *RA,
enum channel_width BW);
boolean
send_fw_vht_ndpa_packet(
void *dm_void,
u8 *RA,
u16 AID,
enum channel_width BW
);
void *dm_void,
u8 *RA,
u16 AID,
enum channel_width BW);
boolean
send_sw_vht_ndpa_packet(
void *dm_void,
u8 *RA,
u16 AID,
enum channel_width BW
);
void *dm_void,
u8 *RA,
u16 AID,
enum channel_width BW);
boolean
send_sw_ht_ndpa_packet(
void *dm_void,
u8 *RA,
enum channel_width BW
);
void *dm_void,
u8 *RA,
enum channel_width BW);
#if (SUPPORT_MU_BF == 1)
enum rt_status
beamforming_get_vht_gid_mgnt_frame(
void *adapter,
PRT_RFD rfd,
POCTET_STRING p_pdu_os
);
void *adapter,
PRT_RFD rfd,
POCTET_STRING p_pdu_os);
boolean
send_sw_vht_gid_mgnt_frame(
void *dm_void,
u8 *RA,
u8 idx
);
void *dm_void,
u8 *RA,
u8 idx);
boolean
send_sw_vht_bf_report_poll(
void *dm_void,
u8 *RA,
boolean is_final_poll
);
void *dm_void,
u8 *RA,
boolean is_final_poll);
boolean
send_sw_vht_mu_ndpa_packet(
void *dm_void,
enum channel_width BW
);
void *dm_void,
enum channel_width BW);
#else
#define beamforming_get_vht_gid_mgnt_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE
#define send_sw_vht_gid_mgnt_frame(dm_void, RA)
@@ -113,74 +100,65 @@ send_sw_vht_mu_ndpa_packet(
#define send_sw_vht_mu_ndpa_packet(dm_void, BW)
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
u32
beamforming_get_report_frame(
void *dm_void,
union recv_frame *precv_frame
);
u32 beamforming_get_report_frame(
void *dm_void,
union recv_frame *precv_frame);
boolean
send_fw_ht_ndpa_packet(
void *dm_void,
u8 *RA,
enum channel_width BW
);
void *dm_void,
u8 *RA,
enum channel_width BW);
boolean
send_sw_ht_ndpa_packet(
void *dm_void,
u8 *RA,
enum channel_width BW
);
void *dm_void,
u8 *RA,
enum channel_width BW);
boolean
send_fw_vht_ndpa_packet(
void *dm_void,
u8 *RA,
u16 AID,
enum channel_width BW
);
void *dm_void,
u8 *RA,
u16 AID,
enum channel_width BW);
boolean
send_sw_vht_ndpa_packet(
void *dm_void,
u8 *RA,
u16 AID,
enum channel_width BW
);
void *dm_void,
u8 *RA,
u16 AID,
enum channel_width BW);
#endif
void
beamforming_get_ndpa_frame(
void *dm_void,
void beamforming_get_ndpa_frame(
void *dm_void,
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
OCTET_STRING pdu_os
OCTET_STRING pdu_os
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
union recv_frame *precv_frame
#endif
);
);
boolean
dbg_send_sw_vht_mundpa_packet(
void *dm_void,
enum channel_width BW
);
void *dm_void,
enum channel_width BW);
#else
#define beamforming_get_ndpa_frame(dm, _pdu_os)
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define beamforming_get_report_frame(adapter, precv_frame) RT_STATUS_FAILURE
#define beamforming_get_report_frame(adapter, precv_frame) RT_STATUS_FAILURE
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define beamforming_get_report_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE
#define beamforming_get_vht_gid_mgnt_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE
#define beamforming_get_report_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE
#define beamforming_get_vht_gid_mgnt_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE
#endif
#define send_fw_ht_ndpa_packet(dm_void, RA, BW)
#define send_sw_ht_ndpa_packet(dm_void, RA, BW)
#define send_fw_vht_ndpa_packet(dm_void, RA, AID, BW)
#define send_sw_vht_ndpa_packet(dm_void, RA, AID, BW)
#define send_sw_vht_ndpa_packet(dm_void, RA, AID, BW)
#define send_sw_vht_gid_mgnt_frame(dm_void, RA, idx)
#define send_sw_vht_bf_report_poll(dm_void, RA, is_final_poll)
#define send_sw_vht_mu_ndpa_packet(dm_void, BW)

310
hal/phydm/txbf/haltxbfjaguar.c
View File

@@ -12,90 +12,82 @@
* more details.
*
*****************************************************************************/
/* ************************************************************
/*************************************************************
* Description:
*
* This file is for 8812/8821/8811 TXBF mechanism
*
* ************************************************************ */
************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (BEAMFORMING_SUPPORT == 1)
#ifdef PHYDM_BEAMFORMING_SUPPORT
#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
void
hal_txbf_8812a_set_ndpa_rate(
void *dm_void,
u8 BW,
u8 rate
)
void hal_txbf_8812a_set_ndpa_rate(
void *dm_void,
u8 BW,
u8 rate)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8812A, (rate << 2 | BW));
}
void
hal_txbf_jaguar_rf_mode(
void *dm_void,
struct _RT_BEAMFORMING_INFO *beam_info
)
void hal_txbf_jaguar_rf_mode(
void *dm_void,
struct _RT_BEAMFORMING_INFO *beam_info)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->rf_type == RF_1T1R)
return;
PHYDM_DBG(dm, DBG_TXBF, "[%s] set TxIQGen\n", __func__);
odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1); /*RF mode table write enable*/
odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x1); /*RF mode table write enable*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1); /*RF mode table write enable*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1); /*RF mode table write enable*/
if (beam_info->beamformee_su_cnt > 0) {
/* Paath_A */
odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0x78000, 0x3); /*Select RX mode*/
odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in RX mode*/
/* Path_B */
odm_set_rf_reg(dm, RF_PATH_B, 0x30, 0x78000, 0x3); /*Select RX mode*/
odm_set_rf_reg(dm, RF_PATH_B, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_B, 0x32, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in RX mode*/
} else {
/* Paath_A */
odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0x78000, 0x3); /*Select RX mode*/
odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0xC26BF); /*@Disable TXIQGEN in RX mode*/
/* Path_B */
odm_set_rf_reg(dm, RF_PATH_B, 0x30, 0x78000, 0x3); /*Select RX mode*/
odm_set_rf_reg(dm, RF_PATH_B, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_B, 0x32, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0xC26BF); /*@Disable TXIQGEN in RX mode*/
}
odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0); /*RF mode table write disable*/
odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x0); /*RF mode table write disable*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0); /*RF mode table write disable*/
odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0); /*RF mode table write disable*/
if (beam_info->beamformee_su_cnt > 0)
odm_set_bb_reg(dm, 0x80c, MASKBYTE1, 0x33);
odm_set_bb_reg(dm, R_0x80c, MASKBYTE1, 0x33);
else
odm_set_bb_reg(dm, 0x80c, MASKBYTE1, 0x11);
odm_set_bb_reg(dm, R_0x80c, MASKBYTE1, 0x11);
}
void
hal_txbf_jaguar_download_ndpa(
void *dm_void,
u8 idx
)
void hal_txbf_jaguar_download_ndpa(
void *dm_void,
u8 idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 u1b_tmp = 0, tmp_reg422 = 0, head_page;
u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
boolean is_send_beacon = false;
u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*default reseved 1 page for the IC type which is undefined.*/
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
void *adapter = dm->adapter;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 u1b_tmp = 0, tmp_reg422 = 0, head_page;
u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
boolean is_send_beacon = false;
u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*@default reseved 1 page for the IC type which is undefined.*/
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
void *adapter = dm->adapter;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
*dm->is_fw_dw_rsvd_page_in_progress = true;
#endif
@@ -110,15 +102,15 @@ hal_txbf_jaguar_download_ndpa(
/*Set REG_CR bit 8. DMA beacon by SW.*/
u1b_tmp = odm_read_1byte(dm, REG_CR_8812A + 1);
odm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp | BIT(0)));
odm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp | BIT(0)));
/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2);
odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422 & (~BIT(6)));
odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422 & (~BIT(6)));
if (tmp_reg422 & BIT(6)) {
PHYDM_DBG(dm, DBG_TXBF, "SetBeamformDownloadNDPA_8812(): There is an adapter is sending beacon.\n");
PHYDM_DBG(dm, DBG_TXBF,
"SetBeamformDownloadNDPA_8812(): There is an adapter is sending beacon.\n");
is_send_beacon = true;
}
@@ -126,17 +118,17 @@ hal_txbf_jaguar_download_ndpa(
odm_write_1byte(dm, REG_TDECTRL_8812A + 1, head_page);
do {
/*Clear beacon valid check bit.*/
/*@Clear beacon valid check bit.*/
bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2);
odm_write_1byte(dm, REG_TDECTRL_8812A + 2, (bcn_valid_reg | BIT(0)));
/*download NDPA rsvd page.*/
/*@download NDPA rsvd page.*/
if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->aid, p_beam_entry->sound_bw, BEACON_QUEUE);
else
beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
/*check rsvd page download OK.*/
/*@check rsvd page download OK.*/
bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2);
count = 0;
while (!(bcn_valid_reg & BIT(0)) && count < 20) {
@@ -148,21 +140,22 @@ hal_txbf_jaguar_download_ndpa(
} while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5);
if (!(bcn_valid_reg & BIT(0)))
PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n", __func__);
PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n",
__func__);
/*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/
odm_write_1byte(dm, REG_TDECTRL_8812A + 1, tx_page_bndy);
/*To make sure that if there exists an adapter which would like to send beacon.*/
/*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
/*the beacon cannot be sent by HW.*/
/*2010.06.23. Added by tynli.*/
/*@2010.06.23. Added by tynli.*/
if (is_send_beacon)
odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422);
/*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
/*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
u1b_tmp = odm_read_1byte(dm, REG_CR_8812A + 1);
odm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp & (~BIT(0))));
@@ -172,20 +165,17 @@ hal_txbf_jaguar_download_ndpa(
#endif
}
void
hal_txbf_jaguar_fw_txbf_cmd(
void *dm_void
)
void hal_txbf_jaguar_fw_txbf_cmd(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 idx, period0 = 0, period1 = 0;
u8 PageNum0 = 0xFF, PageNum1 = 0xFF;
u8 u1_tx_bf_parm[3] = {0};
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 idx, period0 = 0, period1 = 0;
u8 PageNum0 = 0xFF, PageNum1 = 0xFF;
u8 u1_tx_bf_parm[3] = {0};
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
/*Modified by David*/
/*@Modified by David*/
if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
if (idx == 0) {
if (beam_info->beamformee_entry[idx].is_sound)
@@ -209,55 +199,53 @@ hal_txbf_jaguar_fw_txbf_cmd(
odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
PHYDM_DBG(dm, DBG_TXBF,
"[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n", __func__, PageNum0, period0, PageNum1, period1);
"[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n",
__func__, PageNum0, period0, PageNum1, period1);
}
void
hal_txbf_jaguar_enter(
void *dm_void,
u8 bfer_bfee_idx
)
void hal_txbf_jaguar_enter(
void *dm_void,
u8 bfer_bfee_idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i = 0;
u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
u8 bfee_idx = (bfer_bfee_idx & 0xF);
u32 csi_param;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
struct _RT_BEAMFORMER_ENTRY beamformer_entry;
u16 sta_id = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i = 0;
u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
u8 bfee_idx = (bfer_bfee_idx & 0xF);
u32 csi_param;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
struct _RT_BEAMFORMER_ENTRY beamformer_entry;
u16 sta_id = 0;
PHYDM_DBG(dm, DBG_TXBF, "[%s]Start!\n", __func__);
hal_txbf_jaguar_rf_mode(dm, beamforming_info);
if (dm->rf_type == RF_2T2R)
odm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x00000000); /*nc =2*/
odm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x00000000); /*nc =2*/
else
odm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x01081008); /*nc =1*/
odm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x01081008); /*nc =1*/
if ((beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) {
if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
beamformer_entry = beamforming_info->beamformer_entry[bfer_idx];
/*Sounding protocol control*/
odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xCB);
/*MAC address/Partial AID of Beamformer*/
/*@MAC address/Partial AID of Beamformer*/
if (bfer_idx == 0) {
for (i = 0; i < 6 ; i++)
for (i = 0; i < 6; i++)
odm_write_1byte(dm, (REG_BFMER0_INFO_8812A + i), beamformer_entry.mac_addr[i]);
/*CSI report use legacy ofdm so don't need to fill P_AID. */
/*@CSI report use legacy ofdm so don't need to fill P_AID. */
/*platform_efio_write_2byte(adapter, REG_BFMER0_INFO_8812A+6, beamform_entry.P_AID); */
} else {
for (i = 0; i < 6 ; i++)
for (i = 0; i < 6; i++)
odm_write_1byte(dm, (REG_BFMER1_INFO_8812A + i), beamformer_entry.mac_addr[i]);
/*CSI report use legacy ofdm so don't need to fill P_AID.*/
/*@CSI report use legacy ofdm so don't need to fill P_AID.*/
/*platform_efio_write_2byte(adapter, REG_BFMER1_INFO_8812A+6, beamform_entry.P_AID);*/
}
/*CSI report parameters of Beamformee*/
/*@CSI report parameters of Beamformee*/
if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) {
if (dm->rf_type == RF_2T2R)
csi_param = 0x01090109;
@@ -278,8 +266,7 @@ hal_txbf_jaguar_enter(
odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A + 3, 0x50);
}
if ((beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) {
if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
beamformee_entry = beamforming_info->beamformee_entry[bfee_idx];
if (phydm_acting_determine(dm, phydm_acting_as_ibss))
@@ -294,10 +281,10 @@ hal_txbf_jaguar_enter(
} else
odm_write_2byte(dm, REG_TXBF_CTRL_8812A + 2, sta_id | BIT(12) | BIT(14) | BIT(15));
/*CSI report parameters of Beamformee*/
/*@CSI report parameters of Beamformee*/
if (bfee_idx == 0) {
/*Get BIT24 & BIT25*/
u8 tmp = odm_read_1byte(dm, REG_BFMEE_SEL_8812A + 3) & 0x3;
/*@Get BIT24 & BIT25*/
u8 tmp = odm_read_1byte(dm, REG_BFMEE_SEL_8812A + 3) & 0x3;
odm_write_1byte(dm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60);
odm_write_2byte(dm, REG_BFMEE_SEL_8812A, sta_id | BIT(9));
@@ -309,17 +296,14 @@ hal_txbf_jaguar_enter(
}
}
void
hal_txbf_jaguar_leave(
void *dm_void,
u8 idx
)
void hal_txbf_jaguar_leave(
void *dm_void,
u8 idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMER_ENTRY beamformer_entry;
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
struct _RT_BEAMFORMER_ENTRY beamformer_entry;
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
if (idx < BEAMFORMER_ENTRY_NUM) {
beamformer_entry = beamforming_info->beamformer_entry[idx];
@@ -329,9 +313,9 @@ hal_txbf_jaguar_leave(
PHYDM_DBG(dm, DBG_TXBF, "[%s]Start!, IDx = %d\n", __func__, idx);
/*Clear P_AID of Beamformee*/
/*Clear MAC address of Beamformer*/
/*Clear Associated Bfmee Sel*/
/*@Clear P_AID of Beamformee*/
/*@Clear MAC address of Beamformer*/
/*@Clear Associated Bfmee Sel*/
if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xC8);
@@ -360,21 +344,17 @@ hal_txbf_jaguar_leave(
odm_write_2byte(dm, REG_BFMEE_SEL_8812A + 2, odm_read_2byte(dm, REG_BFMEE_SEL_8812A + 2) & 0x60);
}
}
}
void
hal_txbf_jaguar_status(
void *dm_void,
u8 idx
)
void hal_txbf_jaguar_status(
void *dm_void,
u8 idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u16 beam_ctrl_val;
u32 beam_ctrl_reg;
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx];
struct dm_struct *dm = (struct dm_struct *)dm_void;
u16 beam_ctrl_val;
u32 beam_ctrl_reg;
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx];
if (phydm_acting_determine(dm, phydm_acting_as_ibss))
beam_ctrl_val = beamform_entry.mac_id;
@@ -388,7 +368,7 @@ hal_txbf_jaguar_status(
beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
}
if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (beam_info->apply_v_matrix == true)) {
if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beam_info->apply_v_matrix == true) {
if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
beam_ctrl_val |= BIT(9);
else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
@@ -398,22 +378,19 @@ hal_txbf_jaguar_status(
} else
beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
PHYDM_DBG(dm, DBG_TXBF, "[%s] beam_ctrl_val = 0x%x!\n", __func__, beam_ctrl_val);
PHYDM_DBG(dm, DBG_TXBF, "[%s] beam_ctrl_val = 0x%x!\n", __func__,
beam_ctrl_val);
odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
}
void
hal_txbf_jaguar_fw_txbf(
void *dm_void,
u8 idx
)
void hal_txbf_jaguar_fw_txbf(
void *dm_void,
u8 idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
@@ -423,15 +400,12 @@ hal_txbf_jaguar_fw_txbf(
hal_txbf_jaguar_fw_txbf_cmd(dm);
}
void
hal_txbf_jaguar_patch(
void *dm_void,
u8 operation
)
void hal_txbf_jaguar_patch(
void *dm_void,
u8 operation)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
@@ -445,31 +419,30 @@ hal_txbf_jaguar_patch(
#endif
}
void
hal_txbf_jaguar_clk_8812a(
void *dm_void
)
void hal_txbf_jaguar_clk_8812a(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u16 u2btmp;
u8 count = 0, u1btmp;
void *adapter = dm->adapter;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u16 u2btmp;
u8 count = 0, u1btmp;
void *adapter = dm->adapter;
PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
if (*(dm->is_scan_in_process)) {
if (*dm->is_scan_in_process) {
PHYDM_DBG(dm, DBG_TXBF, "[%s] return by Scan\n", __func__);
return;
}
#if DEV_BUS_TYPE == RT_PCI_INTERFACE
/*Stop PCIe TxDMA*/
odm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE);
if (dm->support_interface == ODM_ITRF_PCIE)
odm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE);
#endif
/*Stop Usb TxDMA*/
/*Stop Usb TxDMA*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
RT_DISABLE_FUNC((PADAPTER)adapter, DF_TX_BIT);
PlatformReturnAllPendingTxPackets((PADAPTER)adapter);
PlatformReturnAllPendingTxPackets(adapter);
#else
rtw_write_port_cancel(adapter);
#endif
@@ -496,7 +469,6 @@ hal_txbf_jaguar_clk_8812a(
break;
}
/*Stop RX DMA path*/
u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A);
odm_write_1byte(dm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT(2));
@@ -509,25 +481,25 @@ hal_txbf_jaguar_clk_8812a(
ODM_delay_ms(10);
}
/*Disable clock*/
/*@Disable clock*/
odm_write_1byte(dm, REG_SYS_CLKR_8812A + 1, 0xf0);
/*Disable 320M*/
/*@Disable 320M*/
odm_write_1byte(dm, REG_AFE_PLL_CTRL_8812A + 3, 0x8);
/*Enable 320M*/
/*@Enable 320M*/
odm_write_1byte(dm, REG_AFE_PLL_CTRL_8812A + 3, 0xa);
/*Enable clock*/
/*@Enable clock*/
odm_write_1byte(dm, REG_SYS_CLKR_8812A + 1, 0xfc);
/*Release Tx pause*/
odm_write_1byte(dm, REG_TXPAUSE_8812A, 0);
/*Enable RX DMA path*/
/*@Enable RX DMA path*/
u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A);
odm_write_1byte(dm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT(2)));
#if DEV_BUS_TYPE == RT_PCI_INTERFACE
/*Enable PCIe TxDMA*/
odm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0);
/*@Enable PCIe TxDMA*/
if (dm->support_interface == ODM_ITRF_PCIE)
odm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0);
#endif
/*Start Usb TxDMA*/
RT_ENABLE_FUNC((PADAPTER)adapter, DF_TX_BIT);
@@ -535,6 +507,4 @@ hal_txbf_jaguar_clk_8812a(
#endif
#endif

74
hal/phydm/txbf/haltxbfjaguar.h
View File

@@ -25,74 +25,54 @@
#ifndef __HAL_TXBF_JAGUAR_H__
#define __HAL_TXBF_JAGUAR_H__
#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
#if (BEAMFORMING_SUPPORT == 1)
#ifdef PHYDM_BEAMFORMING_SUPPORT
void
hal_txbf_8812a_set_ndpa_rate(
void *dm_void,
u8 BW,
u8 rate
);
void hal_txbf_8812a_set_ndpa_rate(
void *dm_void,
u8 BW,
u8 rate);
void hal_txbf_jaguar_enter(
void *dm_void,
u8 idx);
void
hal_txbf_jaguar_enter(
void *dm_void,
u8 idx
);
void hal_txbf_jaguar_leave(
void *dm_void,
u8 idx);
void hal_txbf_jaguar_status(
void *dm_void,
u8 idx);
void
hal_txbf_jaguar_leave(
void *dm_void,
u8 idx
);
void hal_txbf_jaguar_fw_txbf(
void *dm_void,
u8 idx);
void hal_txbf_jaguar_patch(
void *dm_void,
u8 operation);
void
hal_txbf_jaguar_status(
void *dm_void,
u8 idx
);
void
hal_txbf_jaguar_fw_txbf(
void *dm_void,
u8 idx
);
void
hal_txbf_jaguar_patch(
void *dm_void,
u8 operation
);
void
hal_txbf_jaguar_clk_8812a(
void *dm_void
);
void hal_txbf_jaguar_clk_8812a(
void *dm_void);
#else
#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate)
#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate)
#define hal_txbf_jaguar_enter(dm_void, idx)
#define hal_txbf_jaguar_leave(dm_void, idx)
#define hal_txbf_jaguar_status(dm_void, idx)
#define hal_txbf_jaguar_fw_txbf(dm_void, idx)
#define hal_txbf_jaguar_fw_txbf(dm_void, idx)
#define hal_txbf_jaguar_patch(dm_void, operation)
#define hal_txbf_jaguar_clk_8812a(dm_void)
#endif
#else
#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate)
#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate)
#define hal_txbf_jaguar_enter(dm_void, idx)
#define hal_txbf_jaguar_leave(dm_void, idx)
#define hal_txbf_jaguar_status(dm_void, idx)
#define hal_txbf_jaguar_fw_txbf(dm_void, idx)
#define hal_txbf_jaguar_fw_txbf(dm_void, idx)
#define hal_txbf_jaguar_patch(dm_void, operation)
#define hal_txbf_jaguar_clk_8812a(dm_void)
#endif
#endif /* #ifndef __HAL_TXBF_JAGUAR_H__ */
#endif /* @#ifndef __HAL_TXBF_JAGUAR_H__ */

347
hal/phydm/txbf/phydm_hal_txbf_api.c
View File

@@ -17,19 +17,17 @@
#include "phydm_precomp.h"
#if (defined(CONFIG_BB_TXBF_API))
#if (RTL8822B_SUPPORT == 1)
/*Add by YuChen for 8822B MU-MIMO API*/
#if (RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1 ||\
RTL8822C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
/*@Add by YuChen for 8822B MU-MIMO API*/
/*this function is only used for BFer*/
u8
phydm_get_ndpa_rate(
void *dm_void
)
u8 phydm_get_ndpa_rate(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 ndpa_rate = ODM_RATE6M;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 ndpa_rate = ODM_RATE6M;
if (dm->rssi_min >= 30) /*link RSSI > 30%*/
if (dm->rssi_min >= 30) /*@link RSSI > 30%*/
ndpa_rate = ODM_RATE24M;
else if (dm->rssi_min <= 25)
ndpa_rate = ODM_RATE6M;
@@ -37,55 +35,49 @@ phydm_get_ndpa_rate(
PHYDM_DBG(dm, DBG_TXBF, "[%s] ndpa_rate = 0x%x\n", __func__, ndpa_rate);
return ndpa_rate;
}
/*this function is only used for BFer*/
u8
phydm_get_beamforming_sounding_info(
void *dm_void,
u16 *troughput,
u8 total_bfee_num,
u8 *tx_rate
)
u8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *throughput,
u8 total_bfee_num, u8 *tx_rate)
{
u8 idx = 0;
u8 soundingdecision = 0xff;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 idx = 0;
u8 snddecision = 0xff;
struct dm_struct *dm = (struct dm_struct *)dm_void;
for (idx = 0; idx < total_bfee_num; idx++) {
if (dm->support_ic_type & (ODM_RTL8814A)) {
if (((tx_rate[idx] >= ODM_RATEVHTSS3MCS7) && (tx_rate[idx] <= ODM_RATEVHTSS3MCS9)))
soundingdecision = soundingdecision & ~(1 << idx);
} else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8822C | ODM_RTL8812)) {
if (((tx_rate[idx] >= ODM_RATEVHTSS2MCS7) && (tx_rate[idx] <= ODM_RATEVHTSS2MCS9)))
soundingdecision = soundingdecision & ~(1 << idx);
if ((tx_rate[idx] >= ODM_RATEVHTSS3MCS7 &&
tx_rate[idx] <= ODM_RATEVHTSS3MCS9))
snddecision = snddecision & ~(1 << idx);
} else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8822C |
ODM_RTL8812 | ODM_RTL8192F)) {
if ((tx_rate[idx] >= ODM_RATEVHTSS2MCS7 &&
tx_rate[idx] <= ODM_RATEVHTSS2MCS9))
snddecision = snddecision & ~(1 << idx);
} else if (dm->support_ic_type & (ODM_RTL8814B)) {
if (((tx_rate[idx] >= ODM_RATEVHTSS4MCS7) && (tx_rate[idx] <= ODM_RATEVHTSS4MCS9)))
soundingdecision = soundingdecision & ~(1 << idx);
if ((tx_rate[idx] >= ODM_RATEVHTSS4MCS7 &&
tx_rate[idx] <= ODM_RATEVHTSS4MCS9))
snddecision = snddecision & ~(1 << idx);
}
}
for (idx = 0; idx < total_bfee_num; idx++) {
if (troughput[idx] <= 10)
soundingdecision = soundingdecision & ~(1 << idx);
if (throughput[idx] <= 10)
snddecision = snddecision & ~(1 << idx);
}
PHYDM_DBG(dm, DBG_TXBF, "[%s] soundingdecision = 0x%x\n", __func__, soundingdecision);
return soundingdecision;
PHYDM_DBG(dm, DBG_TXBF, "[%s] soundingdecision = 0x%x\n", __func__,
snddecision);
return snddecision;
}
/*this function is only used for BFer*/
u8
phydm_get_mu_bfee_snding_decision(
void *dm_void,
u16 throughput
)
u8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput)
{
u8 snding_score = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 snding_score = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
/*throughput unit is Mbps*/
if (throughput >= 500)
@@ -111,31 +103,26 @@ phydm_get_mu_bfee_snding_decision(
else
snding_score = 0;
PHYDM_DBG(dm, DBG_TXBF, "[%s] snding_score = 0x%x\n", __func__, snding_score);
PHYDM_DBG(dm, DBG_TXBF, "[%s] snding_score = 0x%x\n", __func__,
snding_score);
return snding_score;
}
#endif
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
u8
beamforming_get_htndp_tx_rate(
void *dm_void,
u8 comp_steering_num_of_bfer
)
u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 nr_index = 0;
u8 ndp_tx_rate;
/*Find nr*/
/*@Find nr*/
#if (RTL8814A_SUPPORT == 1)
if (dm->support_ic_type & ODM_RTL8814A)
nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), comp_steering_num_of_bfer);
nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num);
else
#endif
nr_index = tx_bf_nr(1, comp_steering_num_of_bfer);
nr_index = tx_bf_nr(1, bfer_str_num);
switch (nr_index) {
case 1:
@@ -156,25 +143,20 @@ beamforming_get_htndp_tx_rate(
}
return ndp_tx_rate;
}
u8
beamforming_get_vht_ndp_tx_rate(
void *dm_void,
u8 comp_steering_num_of_bfer
)
u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 nr_index = 0;
u8 ndp_tx_rate;
/*Find nr*/
/*@Find nr*/
#if (RTL8814A_SUPPORT == 1)
if (dm->support_ic_type & ODM_RTL8814A)
nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), comp_steering_num_of_bfer);
nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num);
else
#endif
nr_index = tx_bf_nr(1, comp_steering_num_of_bfer);
nr_index = tx_bf_nr(1, bfer_str_num);
switch (nr_index) {
case 1:
@@ -195,8 +177,249 @@ beamforming_get_vht_ndp_tx_rate(
}
return ndp_tx_rate;
}
#endif
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
/*this function is only used for BFer*/
void phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i;
if (dm->rf_type == RF_1T1R)
return;
#if (RTL8822C_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8822C) {
if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
for (i = RF_PATH_A; i <= RF_PATH_B; i++) {
/*RF mode table write enable*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
BIT(19), 0x1);
/*Select RX mode*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33,
0xF, 3);
/*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e,
0x3, 0x2);
/*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f,
0xfffff, 0x61AFF);
/*RF mode table write disable*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
BIT(19), 0x0);
}
}
/*@if Nsts > Nc, don't apply V matrix*/
odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
/*@enable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
/* logic mapping */
/* TX BF logic map and TX path en for Nsts = 1~2 */
odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0x33);
odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0x404);
} else {
/*@Disable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
/*@1SS~2ss A, AB*/
odm_set_bb_reg(dm, R_0x820, 0xff, 0x31);
odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x400);
}
}
#endif
#if (RTL8814B_SUPPORT)
if (dm->support_ic_type == ODM_RTL8814B) {
if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
for (i = RF_PATH_A; i <= RF_PATH_D; i++) {
/*RF mode table write enable*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
BIT(19), 0x1);
/*Select RX mode*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33,
0xF, 2);
/*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e,
0xfffff, 0x3fc);
/*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f,
0xfffff, 0x280f7);
/*Select RX mode*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33,
0xF, 3);
/*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e,
0xfffff, 0x365);
/*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f,
0xfffff, 0xafcf7);
/*RF mode table write disable*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
BIT(19), 0x0);
}
}
/*@if Nsts > Nc, don't apply V matrix*/
odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
/*@enable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
/* logic mapping */
/* TX BF logic map and TX path en for Nsts = 1~4 */
odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0xff55);
/*verification path-AC*/
odm_set_bb_reg(dm, R_0x1e30, 0xffffffff, 0xe4e41010);
} else {
/*@Disable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
/*@1SS~4ss A, AB, ABC, ABCD*/
odm_set_bb_reg(dm, R_0x820, 0xffff, 0xf731);
odm_set_bb_reg(dm, R_0x1e2c, 0xffffffff, 0xe4240400);
}
}
#endif
#if (RTL8198F_SUPPORT)
if (dm->support_ic_type == ODM_RTL8198F) {
if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
for (i = RF_PATH_A; i <= RF_PATH_D; i++) {
/*RF mode table write enable*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
BIT(19), 0x1);
/*Select RX mode*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x30,
0xfffff, 0x18000);
/*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x31,
0xfffff, 0x4f);
/*Select RX mode*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x32,
0xfffff, 0x71fc0);
/*RF mode table write disable*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
BIT(19), 0x0);
}
}
/*@if Nsts > Nc, don't apply V matrix*/
odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
/*@enable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
/* logic mapping */
/* TX BF logic map and TX path en for Nsts = 1~4 */
odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0xffff);
odm_set_bb_reg(dm, R_0x1e30, 0xffffffff, 0xe4e4e4e4);
} else {
/*@Disable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
/*@1SS~4ss A, AB, ABC, ABCD*/
odm_set_bb_reg(dm, R_0x820, 0xffff, 0xf731);
odm_set_bb_reg(dm, R_0x1e2c, 0xffffffff, 0xe4240400);
}
}
#endif
}
void phydm_txbf_avoid_hang(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
/* avoid CCK CCA hang when the BF mode */
odm_set_bb_reg(dm, R_0x1e6c, 0x100000, 0x1);
}
#if (RTL8814B_SUPPORT == 1)
void phydm_txbf_80p80_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i;
if (dm->rf_type == RF_1T1R)
return;
if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
for (i = RF_PATH_A; i <= RF_PATH_D; i += 3) {
/*RF mode table write enable*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),
0x1);
/*Select RX mode*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 2);
/*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff,
0x3fc);
/*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
0x280f7);
/*Select RX mode*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3);
/*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff,
0x365);
/*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
0xafcf7);
/*RF mode table write disable*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),
0x0);
}
for (i = RF_PATH_B; i <= RF_PATH_C; i++) {
/*RF mode table write enable*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),
0x1);
/*Select RX mode*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 2);
/*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
0x280c7);
/*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
0x280c7);
/*Select RX mode*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3);
/*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff,
0x365);
/*Set Table data*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
0xafcc7);
/*RF mode table write disable*/
odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),
0x0);
}
}
/*@if Nsts > Nc, don't apply V matrix*/
odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
/*@enable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
/* logic mapping */
/* TX BF logic map and TX path en for Nsts = 1~2 */
odm_set_bb_reg(dm, R_0x820, 0xff0000, 0x33); /*seg0*/
odm_set_bb_reg(dm, R_0x824, 0xff00, 0xcc); /*seg1*/
odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0xe4e4);
} else {
/*@Disable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
/*@1SS~2ss A, AB*/
odm_set_bb_reg(dm, R_0x820, 0xff, 0x31); /*seg0*/
odm_set_bb_reg(dm, R_0x824, 0xff, 0xc8); /*seg1*/
odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0xe420);
}
}
#endif
#endif /*PHYSTS_3RD_TYPE_IC*/
#endif /*CONFIG_BB_TXBF_API*/

61
hal/phydm/txbf/phydm_hal_txbf_api.h
View File

@@ -22,54 +22,53 @@
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_HAL_TXBF_API_H__
#ifndef __PHYDM_HAL_TXBF_API_H__
#define __PHYDM_HAL_TXBF_API_H__
#if (defined(CONFIG_BB_TXBF_API))
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#if defined(DM_ODM_CE_MAC80211)
#define tx_bf_nr(a, b) ({ \
u8 __tx_bf_nr_a = (a); \
u8 __tx_bf_nr_b = (b); \
((__tx_bf_nr_a > __tx_bf_nr_b) ? (__tx_bf_nr_b) : (__tx_bf_nr_a)); })
#else
#define tx_bf_nr(a, b) ((a > b) ? (b) : (a))
#endif
u8
beamforming_get_htndp_tx_rate(
void *dm_void,
u8 comp_steering_num_of_bfer
);
u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num);
u8
beamforming_get_vht_ndp_tx_rate(
void *dm_void,
u8 comp_steering_num_of_bfer
);
u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num);
#endif
#if (RTL8822B_SUPPORT == 1)
u8
phydm_get_beamforming_sounding_info(
void *dm_void,
u16 *troughput,
u8 total_bfee_num,
u8 *tx_rate
);
#if (RTL8822B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8192F_SUPPORT == 1 ||\
RTL8814B_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
u8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *throughput,
u8 total_bfee_num, u8 *tx_rate);
u8
phydm_get_ndpa_rate(
void *dm_void
);
u8 phydm_get_ndpa_rate(void *dm_void);
u8
phydm_get_mu_bfee_snding_decision(
void *dm_void,
u16 throughput
);
u8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput);
#else
#define phydm_get_beamforming_sounding_info(dm_void, troughput, total_bfee_num, tx_rate) 0
#define phydm_get_ndpa_rate(dm_void)
#define phydm_get_mu_bfee_snding_decision(dm_void, troughput)
#define phydm_get_beamforming_sounding_info(dm, tp, bfee_num, rate) 0
#define phydm_get_ndpa_rate(dm)
#define phydm_get_mu_bfee_snding_decision(dm, tp)
#endif
#ifdef PHYSTS_3RD_TYPE_IC
/*this function is only used for BFer*/
void phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt);
void phydm_txbf_avoid_hang(void *dm_void);
#if (RTL8814B_SUPPORT == 1)
void phydm_txbf_80p80_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt);
#endif
#endif /*PHYSTS_3RD_TYPE_IC*/
#endif
#endif