mirror of
https://github.com/RinCat/RTL88x2BU-Linux-Driver.git
synced 2026-01-19 10:26:35 +00:00
Update to 5.6.1
This commit is contained in:
Rin Cat
@@ -25,111 +25,185 @@
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#include "mp_precomp.h"
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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#if RT_PLATFORM==PLATFORM_MACOSX
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#include "phydm_precomp.h"
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#else
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#include "../phydm_precomp.h"
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#endif
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#if RT_PLATFORM == PLATFORM_MACOSX
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#include "phydm_precomp.h"
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#else
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#include "../phydm_precomp.h"
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#endif
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#else
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#include "../../phydm_precomp.h"
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#endif
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#if (RTL8822B_SUPPORT == 1)
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void
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halrf_rf_lna_setting_8822b(
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struct dm_struct *dm_void,
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enum phydm_lna_set type
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)
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void halrf_rf_lna_setting_8822b(struct dm_struct *dm_void,
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enum halrf_lna_set type)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 path = 0x0;
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for (path = 0x0; path < 2; path++)
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if (type == phydm_lna_disable) {
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if (type == HALRF_LNA_DISABLE) {
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/*S0*/
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odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x1);
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odm_set_rf_reg(dm, (enum rf_path)path, 0x33, RFREGOFFSETMASK, 0x00003);
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odm_set_rf_reg(dm, (enum rf_path)path, 0x3e, RFREGOFFSETMASK, 0x00064);
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odm_set_rf_reg(dm, (enum rf_path)path, 0x3f, RFREGOFFSETMASK, 0x0afce);
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odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x0);
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} else if (type == phydm_lna_enable) {
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odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19),
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0x1);
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odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33,
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RFREGOFFSETMASK, 0x00003);
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odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e,
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RFREGOFFSETMASK, 0x00064);
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odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f,
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RFREGOFFSETMASK, 0x0afce);
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odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19),
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0x0);
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} else if (type == HALRF_LNA_ENABLE) {
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/*S0*/
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odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x1);
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odm_set_rf_reg(dm, (enum rf_path)path, 0x33, RFREGOFFSETMASK, 0x00003);
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odm_set_rf_reg(dm, (enum rf_path)path, 0x3e, RFREGOFFSETMASK, 0x00064);
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odm_set_rf_reg(dm, (enum rf_path)path, 0x3f, RFREGOFFSETMASK, 0x1afce);
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odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x0);
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odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19),
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0x1);
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odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33,
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RFREGOFFSETMASK, 0x00003);
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odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e,
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RFREGOFFSETMASK, 0x00064);
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odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f,
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RFREGOFFSETMASK, 0x1afce);
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odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19),
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0x0);
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}
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}
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boolean
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get_mix_mode_tx_agc_bb_swing_offset_8822b(
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void *dm_void,
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enum pwrtrack_method method,
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u8 rf_path,
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u8 tx_power_index_offest
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)
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boolean get_mix_mode_tx_agc_bb_swing_offset_8822b(void *dm_void,
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enum pwrtrack_method method,
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u8 rf_path,
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u8 tx_power_index_offset)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
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u8 bb_swing_upper_bound = cali_info->default_ofdm_index + 10;
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u8 bb_swing_lower_bound = 0;
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u8 bb_swing_upper_bound = cali_info->default_ofdm_index + 10;
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u8 bb_swing_lower_bound = 0;
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s8 tx_agc_index = 0;
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u8 tx_bb_swing_index = cali_info->default_ofdm_index;
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s8 tx_agc_index = 0;
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u8 tx_bb_swing_index = cali_info->default_ofdm_index;
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PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"Path_%d cali_info->absolute_ofdm_swing_idx[rf_path]=%d, tx_power_index_offest=%d\n",
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rf_path, cali_info->absolute_ofdm_swing_idx[rf_path], tx_power_index_offest);
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
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"Path_%d absolute_ofdm_swing[%d]=%d tx_power_idx_offset=%d\n",
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rf_path, rf_path, cali_info->absolute_ofdm_swing_idx[rf_path],
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tx_power_index_offset);
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if (tx_power_index_offest > 0XF)
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tx_power_index_offest = 0XF;
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if (tx_power_index_offset > 0XF)
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tx_power_index_offset = 0XF;
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if (cali_info->absolute_ofdm_swing_idx[rf_path] >= 0 && cali_info->absolute_ofdm_swing_idx[rf_path] <= tx_power_index_offest) {
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if (cali_info->absolute_ofdm_swing_idx[rf_path] >= 0 &&
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cali_info->absolute_ofdm_swing_idx[rf_path] <=
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tx_power_index_offset) {
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tx_agc_index = cali_info->absolute_ofdm_swing_idx[rf_path];
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tx_bb_swing_index = cali_info->default_ofdm_index;
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} else if (cali_info->absolute_ofdm_swing_idx[rf_path] > tx_power_index_offest) {
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tx_agc_index = tx_power_index_offest;
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cali_info->remnant_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path] - tx_power_index_offest;
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tx_bb_swing_index = cali_info->default_ofdm_index + cali_info->remnant_ofdm_swing_idx[rf_path];
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} else if (cali_info->absolute_ofdm_swing_idx[rf_path] >
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tx_power_index_offset) {
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tx_agc_index = tx_power_index_offset;
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cali_info->remnant_ofdm_swing_idx[rf_path] =
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cali_info->absolute_ofdm_swing_idx[rf_path] -
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tx_power_index_offset;
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tx_bb_swing_index = cali_info->default_ofdm_index +
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cali_info->remnant_ofdm_swing_idx[rf_path];
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if (tx_bb_swing_index > bb_swing_upper_bound)
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tx_bb_swing_index = bb_swing_upper_bound;
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} else {
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tx_agc_index = 0;
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if (cali_info->default_ofdm_index > (cali_info->absolute_ofdm_swing_idx[rf_path] * (-1)))
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tx_bb_swing_index = cali_info->default_ofdm_index + cali_info->absolute_ofdm_swing_idx[rf_path];
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if (cali_info->default_ofdm_index >
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(cali_info->absolute_ofdm_swing_idx[rf_path] * (-1)))
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tx_bb_swing_index =
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cali_info->default_ofdm_index +
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cali_info->absolute_ofdm_swing_idx[rf_path];
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else
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tx_bb_swing_index = bb_swing_lower_bound;
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if (tx_bb_swing_index < bb_swing_lower_bound)
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if (tx_bb_swing_index < bb_swing_lower_bound)
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tx_bb_swing_index = bb_swing_lower_bound;
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}
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cali_info->absolute_ofdm_swing_idx[rf_path] = tx_agc_index;
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cali_info->bb_swing_idx_ofdm[rf_path] = tx_bb_swing_index;
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PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"MixMode Offset Path_%d cali_info->absolute_ofdm_swing_idx[rf_path]=%d cali_info->bb_swing_idx_ofdm[rf_path]=%d tx_power_index_offest=%d\n",
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rf_path, cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->bb_swing_idx_ofdm[rf_path], tx_power_index_offest);
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
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"absolute_ofdm[%d]=%d bb_swing_ofdm[%d]=%d tx_pwr_offset=%d\n",
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rf_path, cali_info->absolute_ofdm_swing_idx[rf_path],
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rf_path, cali_info->bb_swing_idx_ofdm[rf_path],
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tx_power_index_offset);
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return true;
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}
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void odm_pwrtrack_method_set_pwr8822b(void *dm_void,
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enum pwrtrack_method method,
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u8 rf_path, u8 tx_pwr_idx_offset)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
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u32 tmp_reg1, tmp_reg2, tmp_reg3;
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u8 bb_swing_idx_ofdm = cali_info->bb_swing_idx_ofdm[rf_path];
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void
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odm_tx_pwr_track_set_pwr8822b(
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void *dm_void,
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enum pwrtrack_method method,
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u8 rf_path,
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u8 channel_mapped_index
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)
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/*use for mp driver clean power tracking status*/
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if (method == BBSWING) {
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if (rf_path == RF_PATH_A) {
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tmp_reg1 = R_0xc94;
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tmp_reg2 = REG_A_TX_SCALE_JAGUAR;
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} else if (rf_path == RF_PATH_B) {
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tmp_reg1 = R_0xe94;
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tmp_reg2 = REG_B_TX_SCALE_JAGUAR;
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} else {
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return;
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}
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odm_set_bb_reg(dm, tmp_reg1,
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BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25),
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cali_info->absolute_ofdm_swing_idx[rf_path]);
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odm_set_bb_reg(dm, tmp_reg2, 0xFFE00000,
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tx_scaling_table_jaguar[bb_swing_idx_ofdm]);
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} else if (method == MIX_MODE) {
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if (rf_path == RF_PATH_A) {
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tmp_reg1 = R_0xc94;
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tmp_reg2 = REG_A_TX_SCALE_JAGUAR;
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tmp_reg3 = 0xc1c;
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} else if (rf_path == RF_PATH_B) {
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tmp_reg1 = R_0xe94;
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tmp_reg2 = REG_B_TX_SCALE_JAGUAR;
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tmp_reg3 = 0xe1c;
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} else {
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return;
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}
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get_mix_mode_tx_agc_bb_swing_offset_8822b(dm,
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method,
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rf_path,
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tx_pwr_idx_offset);
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bb_swing_idx_ofdm = cali_info->bb_swing_idx_ofdm[rf_path];
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odm_set_bb_reg(dm, tmp_reg1,
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BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25),
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cali_info->absolute_ofdm_swing_idx[rf_path]);
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odm_set_bb_reg(dm, tmp_reg2, 0xFFE00000,
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tx_scaling_table_jaguar[bb_swing_idx_ofdm]);
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
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"TXAGC(%x)=0x%x BBSw(%x)=0x%x BBSwIdx=%d rf_path=%d\n",
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tmp_reg1,
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odm_get_bb_reg(dm, tmp_reg1,
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BIT(29) | BIT(28) | BIT(27) |
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BIT(26) | BIT(25)),
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tmp_reg3, odm_get_bb_reg(dm, tmp_reg3, 0xFFE00000),
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cali_info->bb_swing_idx_ofdm[rf_path], rf_path);
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}
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}
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void odm_tx_pwr_track_set_pwr8822b(void *dm_void, enum pwrtrack_method method,
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u8 rf_path, u8 channel_mapped_index)
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{
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#if 0
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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void *adapter = dm->adapter;
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HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
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struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
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struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
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u8 channel = *dm->channel;
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u8 band_width = hal_data->current_channel_bw;
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u8 tx_power_index = 0;
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@@ -138,7 +212,7 @@ odm_tx_pwr_track_set_pwr8822b(
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PHALMAC_PWR_TRACKING_OPTION p_pwr_tracking_opt = &(cali_info->HALMAC_PWR_TRACKING_INFO);
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if (*(dm->mp_mode) == true) {
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if (*dm->mp_mode == true) {
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
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#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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#if (MP_DRIVER == 1)
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@@ -166,12 +240,16 @@ odm_tx_pwr_track_set_pwr8822b(
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tx_rate = (u8) rate;
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}
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PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__, tx_rate);
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__,
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tx_rate);
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tx_power_index = phy_get_tx_power_index(adapter, (enum rf_path) rf_path, tx_rate, band_width, channel);
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PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
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"type=%d tx_power_index=%d cali_info->absolute_ofdm_swing_idx=%d cali_info->default_ofdm_index=%d rf_path=%d\n", method, tx_power_index, cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->default_ofdm_index, rf_path);
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
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"type=%d tx_power_index=%d cali_info->absolute_ofdm_swing_idx=%d cali_info->default_ofdm_index=%d rf_path=%d\n",
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method, tx_power_index,
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cali_info->absolute_ofdm_swing_idx[rf_path],
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cali_info->default_ofdm_index, rf_path);
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p_pwr_tracking_opt->type = method;
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p_pwr_tracking_opt->bbswing_index = cali_info->default_ofdm_index;
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@@ -185,44 +263,39 @@ odm_tx_pwr_track_set_pwr8822b(
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status = hal_mac_send_power_tracking_info(&GET_HAL_MAC_INFO(adapter), p_pwr_tracking_opt);
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if (status == RT_STATUS_SUCCESS) {
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PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
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"path A 0xC94=0x%X 0xC1C=0x%X\n",
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odm_get_bb_reg(dm, 0xC94, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)),
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odm_get_bb_reg(dm, 0xC1C, 0xFFE00000)
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);
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PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
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"path B 0xE94=0x%X 0xE1C=0x%X\n",
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odm_get_bb_reg(dm, 0xE94, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)),
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odm_get_bb_reg(dm, 0xE1C, 0xFFE00000)
|
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);
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
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"path A 0xC94=0x%X 0xC1C=0x%X\n",
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odm_get_bb_reg(dm, R_0xc94,
|
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BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)),
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odm_get_bb_reg(dm, R_0xc1c, 0xFFE00000));
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
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"path B 0xE94=0x%X 0xE1C=0x%X\n",
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odm_get_bb_reg(dm, R_0xe94,
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BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)),
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odm_get_bb_reg(dm, R_0xe1c, 0xFFE00000));
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} else {
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PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
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"Power Tracking to FW Fail ret code = %d\n", status);
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RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
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"Power Tracking to FW Fail ret code = %d\n",
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status);
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}
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}
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#endif
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
|
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struct _hal_rf_ *rf = &dm->rf_table;
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u8 tx_power_index_offest = 0;
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u8 tx_power_index = 0;
|
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|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
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#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
|
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struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
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struct rtl_phy *rtlphy = &rtlpriv->phy;
|
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u8 channel = rtlphy->current_channel;
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u8 band_width = rtlphy->current_chan_bw;
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#else
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struct _ADAPTER *adapter = (PADAPTER)dm->adapter;
|
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u8 channel = *dm->channel;
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||||
u8 band_width = *dm->band_width;
|
||||
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = dm->adapter;
|
||||
#endif
|
||||
u8 tx_rate = 0xFF;
|
||||
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
|
||||
struct _hal_rf_ *rf = &dm->rf_table;
|
||||
u8 tx_pwr_idx_offset = 0;
|
||||
u8 tx_pwr_idx = 0;
|
||||
u8 mpt_rate_index = 0;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
u8 channel = *dm->channel;
|
||||
u8 band_width = *dm->band_width;
|
||||
u8 tx_rate = 0xFF;
|
||||
|
||||
if (*dm->mp_mode == true) {
|
||||
if (*dm->mp_mode == 1) {
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#if (MP_DRIVER == 1)
|
||||
@@ -232,17 +305,20 @@ odm_tx_pwr_track_set_pwr8822b(
|
||||
#endif
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
#ifdef CONFIG_MP_INCLUDED
|
||||
PMPT_CONTEXT p_mpt_ctx = &adapter->mppriv.mpt_ctx;
|
||||
if (rf->mp_rate_index)
|
||||
mpt_rate_index = *rf->mp_rate_index;
|
||||
|
||||
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
|
||||
tx_rate = mpt_to_mgnt_rate(mpt_rate_index);
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
} else {
|
||||
u16 rate = *dm->forced_data_rate;
|
||||
u16 rate = *dm->forced_data_rate;
|
||||
|
||||
if (!rate) { /*auto rate*/
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = dm->adapter;
|
||||
|
||||
tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
|
||||
tx_rate = dm->tx_rate;
|
||||
@@ -252,164 +328,136 @@ odm_tx_pwr_track_set_pwr8822b(
|
||||
else
|
||||
tx_rate = rf->p_rate_index;
|
||||
#endif
|
||||
} else /*force rate*/
|
||||
tx_rate = (u8) rate;
|
||||
} else { /*force rate*/
|
||||
tx_rate = (u8)rate;
|
||||
}
|
||||
}
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__, tx_rate);
|
||||
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__,
|
||||
tx_rate);
|
||||
#endif
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"pRF->default_ofdm_index=%d pRF->default_cck_index=%d\n", cali_info->default_ofdm_index, cali_info->default_cck_index);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"pRF->default_ofdm_index=%d pRF->default_cck_index=%d\n",
|
||||
cali_info->default_ofdm_index, cali_info->default_cck_index);
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"pRF->absolute_ofdm_swing_idx=%d pRF->remnant_ofdm_swing_idx=%d pRF->absolute_cck_swing_idx=%d pRF->remnant_cck_swing_idx=%d rf_path=%d\n",
|
||||
cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->remnant_ofdm_swing_idx[rf_path], cali_info->absolute_cck_swing_idx[rf_path], cali_info->remnant_cck_swing_idx, rf_path);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"absolute_ofdm_swing_idx=%d remnant_ofdm_swing_idx=%d path=%d\n",
|
||||
cali_info->absolute_ofdm_swing_idx[rf_path],
|
||||
cali_info->remnant_ofdm_swing_idx[rf_path], rf_path);
|
||||
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"absolute_cck_swing_idx=%d remnant_cck_swing_idx=%d path=%d\n",
|
||||
cali_info->absolute_cck_swing_idx[rf_path],
|
||||
cali_info->remnant_cck_swing_idx, rf_path);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
tx_power_index = odm_get_tx_power_index(dm, (enum rf_path) rf_path, tx_rate, (enum channel_width)band_width, channel);
|
||||
tx_pwr_idx = odm_get_tx_power_index(dm, (enum rf_path)rf_path, tx_rate, (enum channel_width)band_width, channel);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
tx_power_index = odm_get_tx_power_index(dm, (enum rf_path) rf_path, tx_rate, band_width, channel);
|
||||
tx_pwr_idx = odm_get_tx_power_index(dm, (enum rf_path)rf_path,
|
||||
tx_rate, band_width, channel);
|
||||
#else
|
||||
tx_power_index = config_phydm_read_txagc_8822b(dm, rf_path, 0x04); /*0x04(TX_AGC_OFDM_6M)*/
|
||||
/*0x04(TX_AGC_OFDM_6M)*/
|
||||
tx_pwr_idx = config_phydm_read_txagc_8822b(dm, rf_path, 0x04);
|
||||
#endif
|
||||
|
||||
if (tx_power_index >= 63)
|
||||
tx_power_index = 63;
|
||||
if (tx_pwr_idx >= 63)
|
||||
tx_pwr_idx = 63;
|
||||
|
||||
tx_power_index_offest = 63 - tx_power_index;
|
||||
tx_pwr_idx_offset = 63 - tx_pwr_idx;
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"tx_power_index=%d tx_power_index_offest=%d rf_path=%d\n", tx_power_index, tx_power_index_offest, rf_path);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"tx_power_index=%d tx_power_index_offset=%d rf_path=%d\n",
|
||||
tx_pwr_idx, tx_pwr_idx_offset, rf_path);
|
||||
|
||||
if (method == BBSWING) { /*use for mp driver clean power tracking status*/
|
||||
switch (rf_path) {
|
||||
case RF_PATH_A:
|
||||
odm_set_bb_reg(dm, 0xC94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), cali_info->absolute_ofdm_swing_idx[rf_path]);
|
||||
odm_set_bb_reg(dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);
|
||||
break;
|
||||
case RF_PATH_B:
|
||||
odm_set_bb_reg(dm, 0xE94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), cali_info->absolute_ofdm_swing_idx[rf_path]);
|
||||
odm_set_bb_reg(dm, REG_B_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else if (method == MIX_MODE) {
|
||||
switch (rf_path) {
|
||||
case RF_PATH_A:
|
||||
get_mix_mode_tx_agc_bb_swing_offset_8822b(dm, method, rf_path, tx_power_index_offest);
|
||||
odm_set_bb_reg(dm, 0xC94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), cali_info->absolute_ofdm_swing_idx[rf_path]);
|
||||
odm_set_bb_reg(dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"TXAGC(0xC94)=0x%x BBSwing(0xc1c)=0x%x BBSwingIndex=%d rf_path=%d\n",
|
||||
odm_get_bb_reg(dm, 0xC94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25))),
|
||||
odm_get_bb_reg(dm, 0xc1c, 0xFFE00000),
|
||||
cali_info->bb_swing_idx_ofdm[rf_path], rf_path);
|
||||
break;
|
||||
|
||||
case RF_PATH_B:
|
||||
get_mix_mode_tx_agc_bb_swing_offset_8822b(dm, method, rf_path, tx_power_index_offest);
|
||||
odm_set_bb_reg(dm, 0xE94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), cali_info->absolute_ofdm_swing_idx[rf_path]);
|
||||
odm_set_bb_reg(dm, REG_B_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"TXAGC(0xE94)=0x%x BBSwing(0xe1c)=0x%x BBSwingIndex=%d rf_path=%d\n",
|
||||
odm_get_bb_reg(dm, 0xE94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25))),
|
||||
odm_get_bb_reg(dm, 0xe1c, 0xFFE00000),
|
||||
cali_info->bb_swing_idx_ofdm[rf_path], rf_path);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
odm_pwrtrack_method_set_pwr8822b(dm, method, rf_path,
|
||||
tx_pwr_idx_offset);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
get_delta_swing_table_8822b(
|
||||
void *dm_void,
|
||||
void get_delta_swing_table_8822b(void *dm_void,
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
u8 **temperature_up_a,
|
||||
u8 **temperature_down_a,
|
||||
u8 **temperature_up_b,
|
||||
u8 **temperature_down_b,
|
||||
u8 **temperature_up_cck_a,
|
||||
u8 **temperature_down_cck_a,
|
||||
u8 **temperature_up_cck_b,
|
||||
u8 **temperature_down_cck_b
|
||||
u8 **temperature_up_a, u8 **temperature_down_a,
|
||||
u8 **temperature_up_b, u8 **temperature_down_b,
|
||||
u8 **temperature_up_cck_a,
|
||||
u8 **temperature_down_cck_a,
|
||||
u8 **temperature_up_cck_b,
|
||||
u8 **temperature_down_cck_b)
|
||||
#else
|
||||
u8 **temperature_up_a,
|
||||
u8 **temperature_down_a,
|
||||
u8 **temperature_up_b,
|
||||
u8 **temperature_down_b
|
||||
u8 **temperature_up_a,
|
||||
u8 **temperature_down_a,
|
||||
u8 **temperature_up_b,
|
||||
u8 **temperature_down_b)
|
||||
#endif
|
||||
)
|
||||
{
|
||||
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
||||
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
|
||||
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
||||
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
|
||||
u8 channel = *dm->channel;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
u8 channel = *(dm->channel);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
|
||||
struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
|
||||
struct rtl_phy *rtlphy = &(rtlpriv->phy);
|
||||
u8 channel = rtlphy->current_channel;
|
||||
#else
|
||||
void *adapter = dm->adapter;
|
||||
u8 channel = *dm->channel;
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
*temperature_up_cck_a = cali_info->delta_swing_table_idx_2g_cck_a_p;
|
||||
*temperature_up_cck_a = cali_info->delta_swing_table_idx_2g_cck_a_p;
|
||||
*temperature_down_cck_a = cali_info->delta_swing_table_idx_2g_cck_a_n;
|
||||
*temperature_up_cck_b = cali_info->delta_swing_table_idx_2g_cck_b_p;
|
||||
*temperature_up_cck_b = cali_info->delta_swing_table_idx_2g_cck_b_p;
|
||||
*temperature_down_cck_b = cali_info->delta_swing_table_idx_2g_cck_b_n;
|
||||
#endif
|
||||
|
||||
*temperature_up_a = cali_info->delta_swing_table_idx_2ga_p;
|
||||
*temperature_up_a = cali_info->delta_swing_table_idx_2ga_p;
|
||||
*temperature_down_a = cali_info->delta_swing_table_idx_2ga_n;
|
||||
*temperature_up_b = cali_info->delta_swing_table_idx_2gb_p;
|
||||
*temperature_up_b = cali_info->delta_swing_table_idx_2gb_p;
|
||||
*temperature_down_b = cali_info->delta_swing_table_idx_2gb_n;
|
||||
|
||||
if (36 <= channel && channel <= 64) {
|
||||
*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[0];
|
||||
if (channel >= 36 && channel <= 64) {
|
||||
*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[0];
|
||||
*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[0];
|
||||
*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[0];
|
||||
*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[0];
|
||||
*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[0];
|
||||
} else if (100 <= channel && channel <= 144) {
|
||||
*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[1];
|
||||
} else if (channel >= 100 && channel <= 144) {
|
||||
*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[1];
|
||||
*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[1];
|
||||
*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[1];
|
||||
*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[1];
|
||||
*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[1];
|
||||
} else if (149 <= channel && channel <= 177) {
|
||||
*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[2];
|
||||
} else if (channel >= 149 && channel <= 177) {
|
||||
*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[2];
|
||||
*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[2];
|
||||
*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[2];
|
||||
*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[2];
|
||||
*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[2];
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
_phy_lc_calibrate_8822b(
|
||||
struct dm_struct *dm
|
||||
)
|
||||
void aac_check_8822b(struct dm_struct *dm)
|
||||
{
|
||||
u32 lc_cal = 0, cnt = 0,tmp0xc00, tmp0xe00;
|
||||
u32 temp;
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[LCK]LCK start!!!!!!!\n");
|
||||
static boolean firstrun = true;
|
||||
|
||||
if (firstrun) {
|
||||
RF_DBG(dm, DBG_RF_LCK, "[LCK]AAC check for 8822b\n");
|
||||
temp = odm_get_rf_reg(dm, RF_PATH_A, 0xc9, 0xf8);
|
||||
if (temp < 4 || temp > 7) {
|
||||
odm_set_rf_reg(dm, RF_PATH_A, 0xca, BIT(19), 0x0);
|
||||
odm_set_rf_reg(dm, RF_PATH_A, 0xb2, 0x7c000, 0x6);
|
||||
}
|
||||
firstrun = false;
|
||||
}
|
||||
}
|
||||
|
||||
void _phy_lc_calibrate_8822b(struct dm_struct *dm)
|
||||
{
|
||||
u32 lc_cal = 0, cnt = 0, tmp0xc00, tmp0xe00;
|
||||
|
||||
aac_check_8822b(dm);
|
||||
RF_DBG(dm, DBG_RF_IQK, "[LCK]LCK start!!!!!!!\n");
|
||||
tmp0xc00 = odm_read_4byte(dm, 0xc00);
|
||||
tmp0xe00 = odm_read_4byte(dm, 0xe00);
|
||||
odm_write_4byte(dm, 0xc00, 0x4);
|
||||
odm_write_4byte(dm, 0xe00, 0x4);
|
||||
odm_set_rf_reg(dm, RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x10000);
|
||||
odm_set_rf_reg(dm, RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x10000);
|
||||
odm_set_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK, 0x10000);
|
||||
odm_set_rf_reg(dm, RF_PATH_B, RF_0x0, RFREGOFFSETMASK, 0x10000);
|
||||
/*backup RF0x18*/
|
||||
lc_cal = odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK);
|
||||
/*disable RTK*/
|
||||
odm_set_rf_reg(dm, RF_PATH_A, 0xc4, RFREGOFFSETMASK, 0x01402);
|
||||
odm_set_rf_reg(dm, RF_PATH_A, RF_0xc4, RFREGOFFSETMASK, 0x01402);
|
||||
/*Start LCK*/
|
||||
odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal | 0x08000);
|
||||
odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK,
|
||||
lc_cal | 0x08000);
|
||||
ODM_delay_ms(100);
|
||||
for (cnt = 0; cnt < 100; cnt++) {
|
||||
if (odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
|
||||
@@ -419,31 +467,24 @@ _phy_lc_calibrate_8822b(
|
||||
/*Recover channel number*/
|
||||
odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal);
|
||||
/*enable RTK*/
|
||||
odm_set_rf_reg(dm, RF_PATH_A, 0xc4, RFREGOFFSETMASK, 0x81402);
|
||||
odm_set_rf_reg(dm, RF_PATH_A, RF_0xc4, RFREGOFFSETMASK, 0x81402);
|
||||
/**restore*/
|
||||
odm_write_4byte(dm, 0xc00, tmp0xc00);
|
||||
odm_write_4byte(dm, 0xe00, tmp0xe00);
|
||||
odm_set_rf_reg(dm, RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x3ffff);
|
||||
odm_set_rf_reg(dm, RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x3ffff);
|
||||
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[LCK]LCK end!!!!!!!\n");
|
||||
odm_set_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK, 0x3ffff);
|
||||
odm_set_rf_reg(dm, RF_PATH_B, RF_0x0, RFREGOFFSETMASK, 0x3ffff);
|
||||
RF_DBG(dm, DBG_RF_IQK, "[LCK]LCK end!!!!!!!\n");
|
||||
}
|
||||
|
||||
/*LCK VERSION:0x1*/
|
||||
void
|
||||
phy_lc_calibrate_8822b(
|
||||
void *dm_void
|
||||
)
|
||||
/*LCK VERSION:0x2*/
|
||||
void phy_lc_calibrate_8822b(void *dm_void)
|
||||
{
|
||||
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
||||
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
||||
|
||||
_phy_lc_calibrate_8822b(dm);
|
||||
}
|
||||
|
||||
|
||||
|
||||
void configure_txpower_track_8822b(
|
||||
struct txpwrtrack_cfg *config
|
||||
)
|
||||
void configure_txpower_track_8822b(struct txpwrtrack_cfg *config)
|
||||
{
|
||||
config->swing_table_size_cck = TXSCALE_TABLE_SIZE;
|
||||
config->swing_table_size_ofdm = TXSCALE_TABLE_SIZE;
|
||||
@@ -464,84 +505,79 @@ void configure_txpower_track_8822b(
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void phy_set_rf_path_switch_8822b(
|
||||
#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
|
||||
struct dm_struct *dm,
|
||||
void phy_set_rf_path_switch_8822b(struct dm_struct *dm, boolean is_main)
|
||||
#else
|
||||
void *adapter,
|
||||
void phy_set_rf_path_switch_8822b(void *adapter, boolean is_main)
|
||||
#endif
|
||||
boolean is_main
|
||||
)
|
||||
{
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
|
||||
struct dm_struct *dm = &hal_data->DM_OutSrc;
|
||||
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
|
||||
struct dm_struct *dm = &hal_data->DM_OutSrc;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*BY SY Request */
|
||||
odm_set_bb_reg(dm, 0x4C, (BIT(24) | BIT(23)), 0x2);
|
||||
odm_set_bb_reg(dm, R_0x4c, (BIT(24) | BIT(23)), 0x2);
|
||||
|
||||
odm_set_bb_reg(dm, 0x974, 0xff, 0xff);
|
||||
odm_set_bb_reg(dm, R_0x974, 0xff, 0xff);
|
||||
|
||||
/*odm_set_bb_reg(dm, 0x1991, 0x3, 0x0);*/
|
||||
odm_set_bb_reg(dm, 0x1990, (BIT(9) | BIT(8)), 0x0);
|
||||
#if 0
|
||||
/*odm_set_bb_reg(dm, R_0x1991, 0x3, 0x0);*/
|
||||
#endif
|
||||
odm_set_bb_reg(dm, R_0x1990, (BIT(9) | BIT(8)), 0x0);
|
||||
|
||||
/*odm_set_bb_reg(dm, 0xCBE, 0x8, 0x0);*/
|
||||
odm_set_bb_reg(dm, 0xCBC, BIT(19), 0x0);
|
||||
#if 0
|
||||
/*odm_set_bb_reg(dm, R_0xcbe, 0x8, 0x0);*/
|
||||
#endif
|
||||
odm_set_bb_reg(dm, R_0xcbc, BIT(19), 0x0);
|
||||
|
||||
odm_set_bb_reg(dm, 0xCB4, 0xff, 0x77);
|
||||
odm_set_bb_reg(dm, R_0xcb4, 0xff, 0x77);
|
||||
|
||||
odm_set_bb_reg(dm, 0x70, MASKBYTE3, 0x0e);
|
||||
odm_set_bb_reg(dm, 0x1704, MASKDWORD, 0x0000ff00);
|
||||
odm_set_bb_reg(dm, 0x1700, MASKDWORD, 0xc00f0038);
|
||||
odm_set_bb_reg(dm, R_0x70, MASKBYTE3, 0x0e);
|
||||
odm_set_bb_reg(dm, R_0x1704, MASKDWORD, 0x0000ff00);
|
||||
odm_set_bb_reg(dm, R_0x1700, MASKDWORD, 0xc00f0038);
|
||||
|
||||
if (is_main) {
|
||||
/*odm_set_bb_reg(dm, 0xCBD, 0x3, 0x2); WiFi */
|
||||
odm_set_bb_reg(dm, 0xCBC, (BIT(9) | BIT(8)), 0x2); /*WiFi */
|
||||
#if 0
|
||||
/*odm_set_bb_reg(dm, R_0xcbd, 0x3, 0x2); WiFi*/
|
||||
#endif
|
||||
odm_set_bb_reg(dm, R_0xcbc, (BIT(9) | BIT(8)), 0x2); /*WiFi*/
|
||||
} else {
|
||||
/*odm_set_bb_reg(dm, 0xCBD, 0x3, 0x1); BT*/
|
||||
odm_set_bb_reg(dm, 0xCBC, (BIT(9) | BIT(8)), 0x1); /*BT*/
|
||||
#if 0
|
||||
/*odm_set_bb_reg(dm, R_0xcbd, 0x3, 0x1); BT*/
|
||||
#endif
|
||||
odm_set_bb_reg(dm, R_0xcbc, (BIT(9) | BIT(8)), 0x1); /*BT*/
|
||||
}
|
||||
}
|
||||
|
||||
boolean
|
||||
_phy_query_rf_path_switch_8822b(
|
||||
#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
|
||||
struct dm_struct *dm
|
||||
boolean _phy_query_rf_path_switch_8822b(struct dm_struct *dm)
|
||||
#else
|
||||
void *adapter
|
||||
boolean _phy_query_rf_path_switch_8822b(void *adapter)
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
|
||||
struct dm_struct *dm = &hal_data->DM_OutSrc;
|
||||
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
|
||||
struct dm_struct *dm = &hal_data->DM_OutSrc;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if (odm_get_bb_reg(dm, 0xCBC, (BIT(9) | BIT(8))) == 0x2) /*WiFi */
|
||||
if (odm_get_bb_reg(dm, R_0xcbc, (BIT(9) | BIT(8))) == 0x2) /*WiFi*/
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
boolean phy_query_rf_path_switch_8822b(
|
||||
#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
|
||||
struct dm_struct *dm
|
||||
boolean phy_query_rf_path_switch_8822b(struct dm_struct *dm)
|
||||
#else
|
||||
void *adapter
|
||||
boolean phy_query_rf_path_switch_8822b(void *adapter)
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if DISABLE_BB_RF
|
||||
return true;
|
||||
#endif
|
||||
|
||||
#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
|
||||
return _phy_query_rf_path_switch_8822b(dm);
|
||||
#else
|
||||
@@ -549,5 +585,4 @@ boolean phy_query_rf_path_switch_8822b(
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#endif /* (RTL8822B_SUPPORT == 0)*/
|
||||
#endif /*(RTL8822B_SUPPORT == 0)*/
|
||||
|
||||
@@ -23,63 +23,43 @@
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __HAL_PHY_RF_8822B_H__
|
||||
#define __HAL_PHY_RF_8822B_H__
|
||||
#ifndef __HALRF_8822B_H__
|
||||
#define __HALRF_8822B_H__
|
||||
|
||||
#define AVG_THERMAL_NUM_8822B 4
|
||||
#define RF_T_METER_8822B 0x42
|
||||
#define AVG_THERMAL_NUM_8822B 4
|
||||
#define RF_T_METER_8822B 0x42
|
||||
|
||||
void configure_txpower_track_8822b(
|
||||
struct txpwrtrack_cfg *config
|
||||
);
|
||||
void configure_txpower_track_8822b(struct txpwrtrack_cfg *config);
|
||||
|
||||
void
|
||||
odm_tx_pwr_track_set_pwr8822b(
|
||||
void *dm_void,
|
||||
enum pwrtrack_method method,
|
||||
u8 rf_path,
|
||||
u8 channel_mapped_index
|
||||
);
|
||||
void odm_tx_pwr_track_set_pwr8822b(void *dm_void, enum pwrtrack_method method,
|
||||
u8 rf_path, u8 channel_mapped_index);
|
||||
|
||||
void
|
||||
get_delta_swing_table_8822b(
|
||||
void *dm_void,
|
||||
void get_delta_swing_table_8822b(void *dm_void,
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
u8 **temperature_up_a,
|
||||
u8 **temperature_down_a,
|
||||
u8 **temperature_up_b,
|
||||
u8 **temperature_down_b,
|
||||
u8 **temperature_up_cck_a,
|
||||
u8 **temperature_down_cck_a,
|
||||
u8 **temperature_up_cck_b,
|
||||
u8 **temperature_down_cck_b
|
||||
u8 **temperature_up_a, u8 **temperature_down_a,
|
||||
u8 **temperature_up_b, u8 **temperature_down_b,
|
||||
u8 **temperature_up_cck_a,
|
||||
u8 **temperature_down_cck_a,
|
||||
u8 **temperature_up_cck_b,
|
||||
u8 **temperature_down_cck_b
|
||||
#else
|
||||
u8 **temperature_up_a,
|
||||
u8 **temperature_down_a,
|
||||
u8 **temperature_up_b,
|
||||
u8 **temperature_down_b
|
||||
u8 **temperature_up_a, u8 **temperature_down_a,
|
||||
u8 **temperature_up_b,
|
||||
u8 **temperature_down_b
|
||||
#endif
|
||||
);
|
||||
);
|
||||
|
||||
void
|
||||
phy_lc_calibrate_8822b(
|
||||
void *dm_void
|
||||
);
|
||||
void aac_check_8822b(struct dm_struct *dm);
|
||||
|
||||
void
|
||||
halrf_rf_lna_setting_8822b(
|
||||
struct dm_struct *dm,
|
||||
enum phydm_lna_set type
|
||||
);
|
||||
void phy_lc_calibrate_8822b(void *dm_void);
|
||||
|
||||
void halrf_rf_lna_setting_8822b(struct dm_struct *dm, enum halrf_lna_set type);
|
||||
|
||||
void phy_set_rf_path_switch_8822b(
|
||||
#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
|
||||
struct dm_struct *dm,
|
||||
void phy_set_rf_path_switch_8822b(struct dm_struct *dm,
|
||||
#else
|
||||
void *adapter,
|
||||
void phy_set_rf_path_switch_8822b(void *adapter,
|
||||
#endif
|
||||
boolean is_main
|
||||
);
|
||||
boolean is_main);
|
||||
|
||||
#endif /* #ifndef __HAL_PHY_RF_8822B_H__ */
|
||||
#endif /*__HALRF_8822B_H__*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -23,56 +23,38 @@
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __PHYDM_IQK_8822B_H__
|
||||
#define __PHYDM_IQK_8822B_H__
|
||||
#ifndef __HALRF_IQK_8822B_H__
|
||||
#define __HALRF_IQK_8822B_H__
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define MAC_REG_NUM_8822B 2
|
||||
/*@--------------------------Define Parameters-------------------------------*/
|
||||
#define MAC_REG_NUM_8822B 2
|
||||
#define BB_REG_NUM_8822B 15
|
||||
#define RF_REG_NUM_8822B 5
|
||||
#define LOK_delay_8822B 2
|
||||
#define GS_delay_8822B 2
|
||||
#define WBIQK_delay_8822B 2
|
||||
#define RF_REG_NUM_8822B 5
|
||||
#define LOK_delay_8822B 2
|
||||
#define GS_delay_8822B 2
|
||||
#define WBIQK_delay_8822B 2
|
||||
|
||||
#define TXIQK 0
|
||||
#define RXIQK 1
|
||||
#define SS_8822B 2
|
||||
/*---------------------------End Define Parameters-------------------------------*/
|
||||
/*@-------------------------End Define Parameters-------------------------*/
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
void
|
||||
do_iqk_8822b(
|
||||
void *dm_void,
|
||||
u8 delta_thermal_index,
|
||||
u8 thermal_value,
|
||||
u8 threshold
|
||||
);
|
||||
void do_iqk_8822b(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
|
||||
u8 threshold);
|
||||
#else
|
||||
void
|
||||
do_iqk_8822b(
|
||||
void *dm_void,
|
||||
u8 delta_thermal_index,
|
||||
u8 thermal_value,
|
||||
u8 threshold
|
||||
);
|
||||
void do_iqk_8822b(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
|
||||
u8 threshold);
|
||||
#endif
|
||||
|
||||
void
|
||||
phy_iq_calibrate_8822b(
|
||||
void *dm_void,
|
||||
boolean clear,
|
||||
boolean segment_iqk
|
||||
);
|
||||
void phy_iq_calibrate_8822b(void *dm_void, boolean clear, boolean segment_iqk);
|
||||
|
||||
void
|
||||
do_imr_test_8822b(
|
||||
void *dm_void
|
||||
);
|
||||
void do_imr_test_8822b(void *dm_void);
|
||||
|
||||
#else /* (RTL8822B_SUPPORT == 0)*/
|
||||
#else /* (RTL8822B_SUPPORT == 0)*/
|
||||
|
||||
#define phy_iq_calibrate_8822b(_pdm_void, clear, segment_iqk)
|
||||
|
||||
#endif /* RTL8822B_SUPPORT */
|
||||
#endif /* RTL8822B_SUPPORT */
|
||||
|
||||
#endif /* #ifndef __PHYDM_IQK_8822B_H__*/
|
||||
#endif /*__HALRF_IQK_8822B_H__*/
|
||||
|
||||
1057
hal/phydm/halrf/rtl8822b/halrf_rfk_init_8822b.c
Normal file
1057
hal/phydm/halrf/rtl8822b/halrf_rfk_init_8822b.c
Normal file
File diff suppressed because it is too large
Load Diff
29
hal/phydm/halrf/rtl8822b/halrf_rfk_init_8822b.h
Normal file
29
hal/phydm/halrf/rtl8822b/halrf_rfk_init_8822b.h
Normal file
@@ -0,0 +1,29 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HALRF_RFK_INIT_8822B_H__
|
||||
#define __HALRF_RFK_INIT_8822B_H__
|
||||
|
||||
void odm_read_and_config_mp_8822b_cal_init(void *dm_void);
|
||||
#endif
|
||||
Reference in New Issue
Block a user