RinCat/RTL88x2BU-Linux-Driver
1
0
Fork 0
mirror of https://github.com/RinCat/RTL88x2BU-Linux-Driver.git synced 2026-03-07 01:19:38 +00:00
Code Issues Packages Projects Releases Wiki Activity

Update to 5.6.1

Browse Source
This commit is contained in:
Rin Cat
2019-09-21 05:30:30 -04:00
parent 953142179e
commit 0644d0b316
413 changed files with 179115 additions and 110562 deletions
Download Patch File Download Diff File Expand all files Collapse all files

306
hal/phydm/ap_makefile.mk
View File

@@ -1,118 +1,188 @@
_PHYDM_FILES :=\
phydm/phydm.o \
phydm/phydm_dig.o\
phydm/phydm_antdiv.o\
phydm/phydm_soml.o\
phydm/phydm_smt_ant.o\
phydm/phydm_pathdiv.o\
phydm/phydm_rainfo.o\
phydm/phydm_dynamictxpower.o\
phydm/phydm_adaptivity.o\
phydm/phydm_debug.o\
phydm/phydm_interface.o\
phydm/phydm_phystatus.o\
phydm/phydm_hwconfig.o\
phydm/phydm_dfs.o\
phydm/phydm_cfotracking.o\
phydm/phydm_adc_sampling.o\
phydm/phydm_ccx.o\
phydm/phydm_primary_cca.o\
phydm/phydm_cck_pd.o\
phydm/phydm_rssi_monitor.o\
phydm/phydm_auto_dbg.o\
phydm/phydm_math_lib.o\
phydm/phydm_noisemonitor.o\
phydm/phydm_api.o\
phydm/phydm_pow_train.o\
phydm/txbf/phydm_hal_txbf_api.o\
EdcaTurboCheck.o\
phydm/halrf/halrf.o\
phydm/halrf/halphyrf_ap.o\
phydm/halrf/halrf_powertracking_ap.o\
phydm/halrf/halrf_powertracking.o\
phydm/halrf/halrf_kfree.o
ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8188e/halhwimg8188e_bb.o\
phydm/rtl8188e/halhwimg8188e_mac.o\
phydm/rtl8188e/halhwimg8188e_rf.o\
phydm/rtl8188e/phydm_regconfig8188e.o\
phydm/rtl8188e/hal8188erateadaptive.o\
phydm/rtl8188e/phydm_rtl8188e.o\
phydm/halrf/rtl8188e/halrf_8188e_ap.o
endif
endif
ifeq ($(CONFIG_RTL_8812_SUPPORT),y)
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += ./phydm/halrf/rtl8812a/halrf_8812a_ap.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8881A),y)
_PHYDM_FILES += phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.o
endif
ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
_PHYDM_FILES += \
phydm/halrf/rtl8192e/halrf_8192e_ap.o\
phydm/rtl8192e/phydm_rtl8192e.o
endif
ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_8814a_ap.o
rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_iqk_8814a.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
rtl8192cd-objs += \
phydm/rtl8814a/halhwimg8814a_bb.o\
phydm/rtl8814a/halhwimg8814a_mac.o\
phydm/rtl8814a/halhwimg8814a_rf.o\
phydm/rtl8814a/phydm_regconfig8814a.o\
phydm/rtl8814a/phydm_rtl8814a.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8822BE),y)
_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_8822b.o
_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_iqk_8822b.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8822b/halhwimg8822b_bb.o\
phydm/rtl8822b/halhwimg8822b_mac.o\
phydm/rtl8822b/halhwimg8822b_rf.o\
phydm/rtl8822b/phydm_regconfig8822b.o\
phydm/rtl8822b/phydm_hal_api8822b.o\
phydm/rtl8822b/phydm_rtl8822b.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8821CE),y)
_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_8821c.o
_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_iqk_8821c.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8821c/halhwimg8821c_bb.o\
phydm/rtl8821c/halhwimg8821c_mac.o\
phydm/rtl8821c/halhwimg8821c_rf.o\
phydm/rtl8821c/phydm_regconfig8821c.o\
phydm/rtl8821c/phydm_hal_api8821c.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8197F),y)
_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_8197f.o
_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_iqk_8197f.o
_PHYDM_FILES += efuse_97f/efuse.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8197f/halhwimg8197f_bb.o\
phydm/rtl8197f/halhwimg8197f_mac.o\
phydm/rtl8197f/halhwimg8197f_rf.o\
phydm/rtl8197f/phydm_hal_api8197f.o\
phydm/rtl8197f/phydm_regconfig8197f.o\
phydm/rtl8197f/phydm_rtl8197f.o
endif
endif
_PHYDM_FILES :=\
phydm/phydm.o \
phydm/phydm_dig.o\
phydm/phydm_antdiv.o\
phydm/phydm_soml.o\
phydm/phydm_smt_ant.o\
phydm/phydm_pathdiv.o\
phydm/phydm_rainfo.o\
phydm/phydm_dynamictxpower.o\
phydm/phydm_adaptivity.o\
phydm/phydm_debug.o\
phydm/phydm_interface.o\
phydm/phydm_phystatus.o\
phydm/phydm_hwconfig.o\
phydm/phydm_dfs.o\
phydm/phydm_cfotracking.o\
phydm/phydm_adc_sampling.o\
phydm/phydm_ccx.o\
phydm/phydm_primary_cca.o\
phydm/phydm_cck_pd.o\
phydm/phydm_rssi_monitor.o\
phydm/phydm_auto_dbg.o\
phydm/phydm_math_lib.o\
phydm/phydm_noisemonitor.o\
phydm/phydm_api.o\
phydm/phydm_pow_train.o\
phydm/phydm_lna_sat.o\
phydm/phydm_pmac_tx_setting.o\
phydm/phydm_mp.o\
phydm/txbf/phydm_hal_txbf_api.o\
EdcaTurboCheck.o\
phydm/halrf/halrf.o\
phydm/halrf/halrf_debug.o\
phydm/halrf/halphyrf_ap.o\
phydm/halrf/halrf_powertracking_ap.o\
phydm/halrf/halrf_powertracking.o\
phydm/halrf/halrf_kfree.o
ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8188e/halhwimg8188e_bb.o\
phydm/rtl8188e/halhwimg8188e_mac.o\
phydm/rtl8188e/halhwimg8188e_rf.o\
phydm/rtl8188e/phydm_regconfig8188e.o\
phydm/rtl8188e/hal8188erateadaptive.o\
phydm/rtl8188e/phydm_rtl8188e.o\
phydm/halrf/rtl8188e/halrf_8188e_ap.o
endif
endif
ifeq ($(CONFIG_RTL_8812_SUPPORT),y)
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += ./phydm/halrf/rtl8812a/halrf_8812a_ap.o
endif
_PHYDM_FILES += phydm/rtl8812a/phydm_rtl8812a.o
endif
ifeq ($(CONFIG_WLAN_HAL_8881A),y)
_PHYDM_FILES += phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.o
endif
ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
_PHYDM_FILES += \
phydm/halrf/rtl8192e/halrf_8192e_ap.o\
phydm/rtl8192e/phydm_rtl8192e.o
endif
ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_8814a_ap.o
rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_iqk_8814a.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
rtl8192cd-objs += \
phydm/rtl8814a/halhwimg8814a_bb.o\
phydm/rtl8814a/halhwimg8814a_mac.o\
phydm/rtl8814a/halhwimg8814a_rf.o\
phydm/rtl8814a/phydm_regconfig8814a.o\
phydm/rtl8814a/phydm_rtl8814a.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8822BE),y)
_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_8822b.o
_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_iqk_8822b.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8822b/halhwimg8822b_bb.o\
phydm/rtl8822b/halhwimg8822b_mac.o\
phydm/rtl8822b/halhwimg8822b_rf.o\
phydm/rtl8822b/phydm_regconfig8822b.o\
phydm/rtl8822b/phydm_hal_api8822b.o\
phydm/rtl8822b/phydm_rtl8822b.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8822CE),y)
_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_8822c.o
_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_iqk_8822c.o
_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_dpk_8822c.o
_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_rfk_init_8822c.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8822c/halhwimg8822c_bb.o\
phydm/rtl8822c/halhwimg8822c_mac.o\
phydm/rtl8822c/halhwimg8822c_rf.o\
phydm/rtl8822c/phydm_regconfig8822c.o\
phydm/rtl8822c/phydm_hal_api8822c.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8821CE),y)
_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_8821c.o
_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_iqk_8821c.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8821c/halhwimg8821c_bb.o\
phydm/rtl8821c/halhwimg8821c_mac.o\
phydm/rtl8821c/halhwimg8821c_rf.o\
phydm/rtl8821c/phydm_regconfig8821c.o\
phydm/rtl8821c/phydm_hal_api8821c.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8197F),y)
_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_8197f.o
_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_iqk_8197f.o
_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_dpk_8197f.o
_PHYDM_FILES += efuse_97f/efuse.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8197f/halhwimg8197f_bb.o\
phydm/rtl8197f/halhwimg8197f_mac.o\
phydm/rtl8197f/halhwimg8197f_rf.o\
phydm/rtl8197f/phydm_hal_api8197f.o\
phydm/rtl8197f/phydm_regconfig8197f.o\
phydm/rtl8197f/phydm_rtl8197f.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8192FE),y)
_PHYDM_FILES += phydm/halrf/rtl8192f/halrf_8192f.o
_PHYDM_FILES += phydm/halrf/rtl8192f/halrf_dpk_8192f.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8192f/halhwimg8192f_bb.o\
phydm/rtl8192f/halhwimg8192f_mac.o\
phydm/rtl8192f/halhwimg8192f_rf.o\
phydm/rtl8192f/phydm_hal_api8192f.o\
phydm/rtl8192f/phydm_regconfig8192f.o\
phydm/rtl8192f/phydm_rtl8192f.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8198F),y)
_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_8198f.o
_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_iqk_8198f.o
_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_dpk_8198f.o
_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_rfk_init_8198f.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8198f/phydm_hal_api8198f.o\
phydm/rtl8198f/halhwimg8198f_bb.o\
phydm/rtl8198f/halhwimg8198f_mac.o\
phydm/rtl8198f/halhwimg8198f_rf.o\
phydm/rtl8198f/phydm_regconfig8198f.o \
phydm/halrf/rtl8198f/halrf_8198f.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8814BE),y)
_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_8814b.o
_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_iqk_8814b.o
_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_rfk_init_8814b.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8814b/phydm_hal_api8814b.o\
phydm/rtl8814b/halhwimg8814b_bb.o\
phydm/rtl8814b/halhwimg8814b_mac.o\
phydm/rtl8814b/halhwimg8814b_rf.o\
phydm/rtl8814b/phydm_regconfig8814b.o \
phydm/halrf/rtl8814b/halrf_8814b.o
endif
endif

46
hal/phydm/halhwimg.h
View File

@@ -16,76 +16,76 @@
#ifndef __INC_HW_IMG_H
#define __INC_HW_IMG_H
/*
/*@
* 2011/03/15 MH Add for different IC HW image file selection. code size consideration.
* */
#if RT_PLATFORM == PLATFORM_LINUX
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
/* For 92C */
/* @For 92C */
#define RTL8192CE_HWIMG_SUPPORT 1
#define RTL8192CE_TEST_HWIMG_SUPPORT 0
#define RTL8192CU_HWIMG_SUPPORT 0
#define RTL8192CU_TEST_HWIMG_SUPPORT 0
/* For 92D */
/* @For 92D */
#define RTL8192DE_HWIMG_SUPPORT 1
#define RTL8192DE_TEST_HWIMG_SUPPORT 0
#define RTL8192DU_HWIMG_SUPPORT 0
#define RTL8192DU_TEST_HWIMG_SUPPORT 0
/* For 8723 */
/* @For 8723 */
#define RTL8723E_HWIMG_SUPPORT 1
#define RTL8723U_HWIMG_SUPPORT 0
#define RTL8723S_HWIMG_SUPPORT 0
/* For 88E */
/* @For 88E */
#define RTL8188EE_HWIMG_SUPPORT 0
#define RTL8188EU_HWIMG_SUPPORT 0
#define RTL8188ES_HWIMG_SUPPORT 0
#elif (DEV_BUS_TYPE == RT_USB_INTERFACE)
/* For 92C */
/* @For 92C */
#define RTL8192CE_HWIMG_SUPPORT 0
#define RTL8192CE_TEST_HWIMG_SUPPORT 0
#define RTL8192CU_HWIMG_SUPPORT 1
#define RTL8192CU_TEST_HWIMG_SUPPORT 0
/* For 92D */
/* @For 92D */
#define RTL8192DE_HWIMG_SUPPORT 0
#define RTL8192DE_TEST_HWIMG_SUPPORT 0
#define RTL8192DU_HWIMG_SUPPORT 1
#define RTL8192DU_TEST_HWIMG_SUPPORT 0
/* For 8723 */
/* @For 8723 */
#define RTL8723E_HWIMG_SUPPORT 0
#define RTL8723U_HWIMG_SUPPORT 1
#define RTL8723S_HWIMG_SUPPORT 0
/* For 88E */
/* @For 88E */
#define RTL8188EE_HWIMG_SUPPORT 0
#define RTL8188EU_HWIMG_SUPPORT 0
#define RTL8188ES_HWIMG_SUPPORT 0
#elif (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
/* For 92C */
/* @For 92C */
#define RTL8192CE_HWIMG_SUPPORT 0
#define RTL8192CE_TEST_HWIMG_SUPPORT 0
#define RTL8192CU_HWIMG_SUPPORT 1
#define RTL8192CU_TEST_HWIMG_SUPPORT 0
/* For 92D */
/* @For 92D */
#define RTL8192DE_HWIMG_SUPPORT 0
#define RTL8192DE_TEST_HWIMG_SUPPORT 0
#define RTL8192DU_HWIMG_SUPPORT 1
#define RTL8192DU_TEST_HWIMG_SUPPORT 0
/* For 8723 */
/* @For 8723 */
#define RTL8723E_HWIMG_SUPPORT 0
#define RTL8723U_HWIMG_SUPPORT 0
#define RTL8723S_HWIMG_SUPPORT 1
/* For 88E */
/* @For 88E */
#define RTL8188EE_HWIMG_SUPPORT 0
#define RTL8188EU_HWIMG_SUPPORT 0
#define RTL8188ES_HWIMG_SUPPORT 0
@@ -93,40 +93,40 @@
#else /* PLATFORM_WINDOWS & MacOSX */
/* For 92C */
/* @For 92C */
#define RTL8192CE_HWIMG_SUPPORT 1
#define RTL8192CE_TEST_HWIMG_SUPPORT 1
#define RTL8192CU_HWIMG_SUPPORT 1
#define RTL8192CU_TEST_HWIMG_SUPPORT 1
/* For 92D */
/* @For 92D */
#define RTL8192DE_HWIMG_SUPPORT 1
#define RTL8192DE_TEST_HWIMG_SUPPORT 1
#define RTL8192DU_HWIMG_SUPPORT 1
#define RTL8192DU_TEST_HWIMG_SUPPORT 1
#if defined(UNDER_CE)
/* For 8723 */
/* @For 8723 */
#define RTL8723E_HWIMG_SUPPORT 0
#define RTL8723U_HWIMG_SUPPORT 0
#define RTL8723S_HWIMG_SUPPORT 1
/* For 88E */
/* @For 88E */
#define RTL8188EE_HWIMG_SUPPORT 0
#define RTL8188EU_HWIMG_SUPPORT 0
#define RTL8188ES_HWIMG_SUPPORT 0
#else
/* For 8723 */
/* @For 8723 */
#define RTL8723E_HWIMG_SUPPORT 1
/* #define RTL_8723E_TEST_HWIMG_SUPPORT 1 */
/* @#define RTL_8723E_TEST_HWIMG_SUPPORT 1 */
#define RTL8723U_HWIMG_SUPPORT 1
/* #define RTL_8723U_TEST_HWIMG_SUPPORT 1 */
/* @#define RTL_8723U_TEST_HWIMG_SUPPORT 1 */
#define RTL8723S_HWIMG_SUPPORT 1
/* #define RTL_8723S_TEST_HWIMG_SUPPORT 1 */
/* @#define RTL_8723S_TEST_HWIMG_SUPPORT 1 */
/* For 88E */
/* @For 88E */
#define RTL8188EE_HWIMG_SUPPORT 1
#define RTL8188EU_HWIMG_SUPPORT 1
#define RTL8188ES_HWIMG_SUPPORT 1
@@ -134,4 +134,4 @@
#endif
#endif /* __INC_HW_IMG_H */
#endif /* @__INC_HW_IMG_H */

370
hal/phydm/halrf/halphyrf_ap.c
View File

@@ -74,6 +74,15 @@ void configure_txpower_track(
configure_txpower_track_8822b(config);
#endif
#if RTL8192F_SUPPORT
if (dm->support_ic_type == ODM_RTL8192F)
configure_txpower_track_8192f(config);
#endif
#if RTL8198F_SUPPORT
if (dm->support_ic_type == ODM_RTL8198F)
configure_txpower_track_8198f(config);
#endif
}
@@ -95,7 +104,7 @@ odm_txpowertracking_callback_thermal_meter_92e(
struct rtl8192cd_priv *priv = dm->priv;
rf_mimo_mode = dm->rf_type;
/* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK,"%s:%d rf_mimo_mode:%d\n", __FUNCTION__, __LINE__, rf_mimo_mode); */
/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK,"%s:%d rf_mimo_mode:%d\n", __FUNCTION__, __LINE__, rf_mimo_mode); */
#ifdef MP_TEST
if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
@@ -109,7 +118,7 @@ odm_txpowertracking_callback_thermal_meter_92e(
}
thermal_value = (unsigned char)odm_get_rf_reg(dm, RF_PATH_A, ODM_RF_T_METER_92E, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
switch (rf_mimo_mode) {
@@ -129,7 +138,7 @@ odm_txpowertracking_callback_thermal_meter_92e(
for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) {
if (ele_D == (ofdm_swing_table_92e[i] >> 22)) {
OFDM_index[0] = (unsigned char)i;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0]);
break;
}
}
@@ -140,7 +149,7 @@ odm_txpowertracking_callback_thermal_meter_92e(
for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) {
if (ele_D == (ofdm_swing_table_92e[i] >> 22)) {
OFDM_index[1] = (unsigned char)i;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1]);
break;
}
}
@@ -162,7 +171,7 @@ odm_txpowertracking_callback_thermal_meter_92e(
if (thermal_value_avg_count) {
thermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value);
}
}
@@ -174,8 +183,8 @@ odm_txpowertracking_callback_thermal_meter_92e(
}
if (thermal_value != priv->pshare->thermal_value) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n");
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
delta_IQK = RTL_ABS(thermal_value, priv->pshare->thermal_value_iqk);
@@ -184,32 +193,32 @@ odm_txpowertracking_callback_thermal_meter_92e(
#ifdef _TRACKING_TABLE_FILE
if (priv->pshare->rf_ft_var.pwr_track_file) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
if (is_decrease) {
for (i = 0; i < rf; i++) {
OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0);
OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_92E- 1)) ? (OFDM_TABLE_SIZE_92E - 1) : OFDM_index[i]);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
CCK_index = priv->pshare->CCK_index0 + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1);
CCK_index = ((CCK_index > (CCK_TABLE_SIZE_92E - 1)) ? (CCK_TABLE_SIZE_92E - 1) : CCK_index);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1));
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1));
}
} else {
for (i = 0; i < rf; i++) {
OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0);
OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ? OFDM_min_index : OFDM_index[i]);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
CCK_index = priv->pshare->CCK_index0 - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1);
CCK_index = ((CCK_index < 0) ? 0 : CCK_index);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1));
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1));
}
}
}
#endif /* CFG_TRACKING_TABLE_FILE */
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]);
/* Adujst OFDM Ant_A according to IQK result */
ele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] & 0xFFC00000) >> 22;
@@ -275,8 +284,8 @@ odm_txpowertracking_callback_thermal_meter_92e(
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0xc80 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD));
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0xc88 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD));
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xc80 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD));
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xc88 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD));
if ((delta_IQK > 3) && (!iqk_info->rfk_forbidden)) {
priv->pshare->thermal_value_iqk = thermal_value;
@@ -305,37 +314,40 @@ odm_txpowertracking_callback_thermal_meter_92e(
priv->pshare->OFDM_index[i] = OFDM_index[i];
priv->pshare->CCK_index = CCK_index;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
}
#endif
#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
#if (RTL8197F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\
RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
void
odm_txpowertracking_callback_thermal_meter_jaguar_series3(
void *dm_void
)
{
#if 1
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase;
u8 thermal_value_avg_count = 0, p = 0, i = 0;
u32 thermal_value_avg = 0;
struct rtl8192cd_priv *priv = dm->priv;
struct txpwrtrack_cfg c;
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
struct dm_iqk_info *iqk_info = &dm->IQK_info;
/*4 1. The following TWO tables decide the final index of OFDM/CCK swing table.*/
u8 *delta_swing_table_idx_tup_a = NULL, *delta_swing_table_idx_tdown_a = NULL;
u8 *delta_swing_table_idx_tup_b = NULL, *delta_swing_table_idx_tdown_b = NULL;
u8 *delta_swing_table_idx_tup_cck_a = NULL, *delta_swing_table_idx_tdown_cck_a = NULL;
u8 *delta_swing_table_idx_tup_cck_b = NULL, *delta_swing_table_idx_tdown_cck_b = NULL;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase;
u8 thermal_value_avg_count = 0, p = 0, i = 0;
u32 thermal_value_avg = 0;
struct rtl8192cd_priv *priv = dm->priv;
struct txpwrtrack_cfg c;
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
struct dm_iqk_info *iqk_info = &dm->IQK_info;
struct _hal_rf_ *rf = &dm->rf_table;
/*The following tables decide the final index of OFDM/CCK swing table.*/
u8 *pwrtrk_tab_up_a = NULL, *pwrtrk_tab_down_a = NULL;
u8 *pwrtrk_tab_up_b = NULL, *pwrtrk_tab_down_b = NULL;
u8 *pwrtrk_tab_up_cck_a = NULL, *pwrtrk_tab_down_cck_a = NULL;
u8 *pwrtrk_tab_up_cck_b = NULL, *pwrtrk_tab_down_cck_b = NULL;
/*for 8814 add by Yu Chen*/
u8 *delta_swing_table_idx_tup_c = NULL, *delta_swing_table_idx_tdown_c = NULL;
u8 *delta_swing_table_idx_tup_d = NULL, *delta_swing_table_idx_tdown_d = NULL;
u8 *delta_swing_table_idx_tup_cck_c = NULL, *delta_swing_table_idx_tdown_cck_c = NULL;
u8 *delta_swing_table_idx_tup_cck_d = NULL, *delta_swing_table_idx_tdown_cck_d = NULL;
u8 *pwrtrk_tab_up_c = NULL, *pwrtrk_tab_down_c = NULL;
u8 *pwrtrk_tab_up_d = NULL, *pwrtrk_tab_down_d = NULL;
u8 *pwrtrk_tab_up_cck_c = NULL, *pwrtrk_tab_down_cck_c = NULL;
u8 *pwrtrk_tab_up_cck_d = NULL, *pwrtrk_tab_down_cck_d = NULL;
s8 thermal_value_temp = 0;
#ifdef MP_TEST
if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
@@ -350,22 +362,47 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series3(
configure_txpower_track(dm, &c);
(*c.get_delta_all_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b,
(u8 **)&delta_swing_table_idx_tup_cck_a, (u8 **)&delta_swing_table_idx_tdown_cck_a,
(u8 **)&delta_swing_table_idx_tup_cck_b, (u8 **)&delta_swing_table_idx_tdown_cck_b);
(*c.get_delta_all_swing_table)(dm,
(u8 **)&pwrtrk_tab_up_a, (u8 **)&pwrtrk_tab_down_a,
(u8 **)&pwrtrk_tab_up_b, (u8 **)&pwrtrk_tab_down_b,
(u8 **)&pwrtrk_tab_up_cck_a, (u8 **)&pwrtrk_tab_down_cck_a,
(u8 **)&pwrtrk_tab_up_cck_b, (u8 **)&pwrtrk_tab_down_cck_b);
thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /*0x42: RF Reg[15:10] 88E*/
if (GET_CHIP_VER(priv) == VERSION_8198F) {
(*c.get_delta_all_swing_table_ex)(dm,
(u8 **)&pwrtrk_tab_up_c, (u8 **)&pwrtrk_tab_down_c,
(u8 **)&pwrtrk_tab_up_d, (u8 **)&pwrtrk_tab_down_d,
(u8 **)&pwrtrk_tab_up_cck_c, (u8 **)&pwrtrk_tab_down_cck_c,
(u8 **)&pwrtrk_tab_up_cck_d, (u8 **)&pwrtrk_tab_down_cck_d);
}
/*0x42: RF Reg[15:10] 88E*/
thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);
#ifdef THER_TRIM
if (GET_CHIP_VER(priv) == VERSION_8197F) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"orig thermal_value=%d, ther_trim_val=%d\n", thermal_value, priv->pshare->rf_ft_var.ther_trim_val);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"orig thermal_value=%d, ther_trim_val=%d\n", thermal_value, priv->pshare->rf_ft_var.ther_trim_val);
thermal_value += priv->pshare->rf_ft_var.ther_trim_val;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"after thermal trim, thermal_value=%d\n", thermal_value);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"after thermal trim, thermal_value=%d\n", thermal_value);
}
if (GET_CHIP_VER(priv) == VERSION_8198F) {
thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"thermal_value_temp(%d) = ther_value(%d) + ther_trim_ther(%d)\n",
thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));
if (thermal_value_temp > 63)
thermal_value = 63;
else if (thermal_value_temp < 0)
thermal_value = 0;
else
thermal_value = thermal_value_temp;
}
#endif
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"Readback Thermal Meter = 0x%x(%d) EEPROMthermalmeter 0x%x(%d)\n"
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\n\n\nCurrent Thermal = 0x%x(%d) EEPROMthermalmeter 0x%x(%d)\n"
, thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther);
/* Initialize */
@@ -393,12 +430,12 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series3(
}
if (thermal_value_avg_count) {/*Calculate Average thermal_value after average enough times*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"thermal_value_avg=0x%x(%d) thermal_value_avg_count = %d\n"
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"thermal_value_avg=0x%x(%d) thermal_value_avg_count = %d\n"
, thermal_value_avg, thermal_value_avg, thermal_value_avg_count);
thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X(%d), EEPROMthermalmeter = 0x%X(%d)\n", thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X(%d), EEPROMthermalmeter = 0x%X(%d)\n", thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther);
}
/*4 Calculate delta, delta_LCK, delta_IQK.*/
@@ -408,136 +445,153 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series3(
is_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1);
if (delta > 29) { /* power track table index(thermal diff.) upper bound*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta(%d) > 29, set delta to 29\n", delta);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta(%d) > 29, set delta to 29\n", delta);
delta = 29;
}
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
/*4 if necessary, do LCK.*/
if ((delta_LCK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
if ((delta_LCK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
dm->rf_calibrate_info.thermal_value_lck = thermal_value;
#if (RTL8822B_SUPPORT != 1)
if (!(dm->support_ic_type & ODM_RTL8822B)) {
if (c.phy_lc_calibrate)
(*c.phy_lc_calibrate)(dm);
}
if (c.phy_lc_calibrate)
(*c.phy_lc_calibrate)(dm);
}
#endif
}
if ((delta_IQK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
if (c.do_iqk)
(*c.do_iqk)(dm, true, 0, 0);
}
if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/
if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/
return;
/*4 Do Power Tracking*/
if (thermal_value != dm->rf_calibrate_info.thermal_value) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"\n\n******** START POWER TRACKING ********\n");
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n",
thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******** START POWER TRACKING ********\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n",
thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
#ifdef _TRACKING_TABLE_FILE
if (priv->pshare->rf_ft_var.pwr_track_file) {
if (is_increase) { /*thermal is higher than base*/
if (is_increase) { /*thermal is higher than base*/
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
switch (p) {
case RF_PATH_B:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_b[%d] = %d delta_swing_table_idx_tup_cck_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta], delta, delta_swing_table_idx_tup_cck_b[delta]);
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta];
cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_b[delta];
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_b[%d] = %d pwrtrk_tab_up_cck_b[%d] = %d\n", delta, pwrtrk_tab_up_b[delta], delta, pwrtrk_tab_up_cck_b[delta]);
cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_b[delta];
cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_b[delta];
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
break;
case RF_PATH_C:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_c[%d] = %d delta_swing_table_idx_tup_cck_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta], delta, delta_swing_table_idx_tup_cck_c[delta]);
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta];
cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_c[delta];
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_c[%d] = %d pwrtrk_tab_up_cck_c[%d] = %d\n", delta, pwrtrk_tab_up_c[delta], delta, pwrtrk_tab_up_cck_c[delta]);
cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_c[delta];
cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_c[delta];
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
break;
case RF_PATH_D:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_d[%d] = %d delta_swing_table_idx_tup_cck_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta], delta, delta_swing_table_idx_tup_cck_d[delta]);
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta];
cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_d[delta];
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_d[%d] = %d pwrtrk_tab_up_cck_d[%d] = %d\n", delta, pwrtrk_tab_up_d[delta], delta, pwrtrk_tab_up_cck_d[delta]);
cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_d[delta];
cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_d[delta];
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
break;
default:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_a[%d] = %d delta_swing_table_idx_tup_cck_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta], delta, delta_swing_table_idx_tup_cck_a[delta]);
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta];
cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_a[delta];
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_a[%d] = %d pwrtrk_tab_up_cck_a[%d] = %d\n", delta, pwrtrk_tab_up_a[delta], delta, pwrtrk_tab_up_cck_a[delta]);
cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_a[delta];
cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_a[delta];
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
break;
}
}
} else { /* thermal is lower than base*/
} else { /* thermal is lower than base*/
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
switch (p) {
case RF_PATH_B:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_b[%d] = %d delta_swing_table_idx_tdown_cck_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta], delta, delta_swing_table_idx_tdown_cck_b[delta]);
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta];
cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_b[delta];
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_b[%d] = %d pwrtrk_tab_down_cck_b[%d] = %d\n", delta, pwrtrk_tab_down_b[delta], delta, pwrtrk_tab_down_cck_b[delta]);
cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_b[delta];
cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_b[delta];
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
break;
case RF_PATH_C:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_c[%d] = %d delta_swing_table_idx_tdown_cck_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta], delta, delta_swing_table_idx_tdown_cck_c[delta]);
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta];
cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_c[delta];
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_c[%d] = %d pwrtrk_tab_down_cck_c[%d] = %d\n", delta, pwrtrk_tab_down_c[delta], delta, pwrtrk_tab_down_cck_c[delta]);
cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_c[delta];
cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_c[delta];
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
break;
case RF_PATH_D:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_d[%d] = %d delta_swing_table_idx_tdown_cck_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta], delta, delta_swing_table_idx_tdown_cck_d[delta]);
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta];
cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_d[delta];
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_d[%d] = %d pwrtrk_tab_down_cck_d[%d] = %d\n", delta, pwrtrk_tab_down_d[delta], delta, pwrtrk_tab_down_cck_d[delta]);
cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_d[delta];
cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_d[delta];
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
break;
default:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_a[%d] = %d delta_swing_table_idx_tdown_cck_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta], delta, delta_swing_table_idx_tdown_cck_a[delta]);
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta];
cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_a[delta];
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_a[%d] = %d pwrtrk_tab_down_cck_a[%d] = %d\n", delta, pwrtrk_tab_down_a[delta], delta, pwrtrk_tab_down_cck_a[delta]);
cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_a[delta];
cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_a[delta];
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
break;
}
}
}
if (is_increase) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> increse power --->\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> increse power --->\n");
if (GET_CHIP_VER(priv) == VERSION_8197F) {
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
//} else if (GET_CHIP_VER(priv) == VERSION_8192F) {
// for (p = RF_PATH_A; p < c.rf_path_count; p++)
// (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
} else if (GET_CHIP_VER(priv) == VERSION_8822B) {
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
} else if (GET_CHIP_VER(priv) == VERSION_8821C) {
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
} else if (GET_CHIP_VER(priv) == VERSION_8198F) {
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
}
} else {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> decrese power --->\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power --->\n");
if (GET_CHIP_VER(priv) == VERSION_8197F) {
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
//} else if (GET_CHIP_VER(priv) == VERSION_8192F) {
// for (p = RF_PATH_A; p < c.rf_path_count; p++)
// (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
} else if (GET_CHIP_VER(priv) == VERSION_8822B) {
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
} else if (GET_CHIP_VER(priv) == VERSION_8821C) {
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
} else if (GET_CHIP_VER(priv) == VERSION_8198F) {
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
}
}
}
#endif
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** END:%s() ********\n\n", __func__);
if (GET_CHIP_VER(priv) != VERSION_8198F) {
if ((delta_IQK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
if (!(dm->support_ic_type & ODM_RTL8197F)) {
if (c.do_iqk)
(*c.do_iqk)(dm, false, thermal_value, 0);
}
}
}
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n\n", __func__);
/*update thermal meter value*/
dm->rf_calibrate_info.thermal_value = thermal_value;
@@ -597,7 +651,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2(
(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
/* Initialize */
if (!dm->rf_calibrate_info.thermal_value)
@@ -614,16 +668,16 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2(
/* 4 Query OFDM BB swing default setting Bit[31:21] */
for (p = RF_PATH_A ; p < c.rf_path_count ; p++) {
ele_D = odm_get_bb_reg(dm, bb_swing_reg[p], 0xffe00000);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[p], odm_get_bb_reg(dm, bb_swing_reg[p], MASKDWORD), ele_D);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[p], odm_get_bb_reg(dm, bb_swing_reg[p], MASKDWORD), ele_D);
for (bb_swing_idx = 0; bb_swing_idx < TXSCALE_TABLE_SIZE; bb_swing_idx++) {/* 4 */
if (ele_D == tx_scaling_table_jaguar[bb_swing_idx]) {
dm->rf_calibrate_info.OFDM_index[p] = (u8)bb_swing_idx;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"OFDM_index[%d]=%d\n", p, dm->rf_calibrate_info.OFDM_index[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"OFDM_index[%d]=%d\n", p, dm->rf_calibrate_info.OFDM_index[p]);
break;
}
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "kfree_offset[%d]=%d\n", p, cali_info->kfree_offset[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "kfree_offset[%d]=%d\n", p, cali_info->kfree_offset[p]);
}
@@ -642,7 +696,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2(
if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */
thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\n", thermal_value, priv->pmib->dot11RFEntry.ther);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\n", thermal_value, priv->pmib->dot11RFEntry.ther);
}
/* 4 Calculate delta, delta_LCK, delta_IQK. */
@@ -654,7 +708,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2(
/* 4 if necessary, do LCK. */
if (!(dm->support_ic_type & ODM_RTL8821)) {
if ((delta_LCK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
dm->rf_calibrate_info.thermal_value_lck = thermal_value;
/*Use RTLCK, so close power tracking driver LCK*/
@@ -669,7 +723,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2(
if ((delta_IQK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
panic_printk("%s(%d)\n", __FUNCTION__, __LINE__);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
if (c.do_iqk)
(*c.do_iqk)(dm, true, 0, 0);
@@ -681,12 +735,12 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2(
/* 4 Do Power Tracking */
if (is_tssi_enable == true) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter PURE TSSI MODE**********\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter PURE TSSI MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0);
} else if (thermal_value != dm->rf_calibrate_info.thermal_value) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"\n******** START POWER TRACKING ********\n");
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\n******** START POWER TRACKING ********\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
#ifdef _TRACKING_TABLE_FILE
if (priv->pshare->rf_ft_var.pwr_track_file) {
@@ -694,27 +748,27 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2(
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
switch (p) {
case RF_PATH_B:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /* Record delta swing for mix mode power tracking */
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
case RF_PATH_C:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]);
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /* Record delta swing for mix mode power tracking */
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
case RF_PATH_D:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]);
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /* Record delta swing for mix mode power tracking */
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
default:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /* Record delta swing for mix mode power tracking */
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
}
}
@@ -722,45 +776,45 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2(
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
switch (p) {
case RF_PATH_B:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /* Record delta swing for mix mode power tracking */
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
case RF_PATH_C:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]);
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /* Record delta swing for mix mode power tracking */
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
case RF_PATH_D:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]);
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /* Record delta swing for mix mode power tracking */
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
default:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /* Record delta swing for mix mode power tracking */
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
}
}
}
if (is_increase) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> increse power --->\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> increse power --->\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
} else {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> decrese power --->\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power --->\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
}
}
#endif
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
/* update thermal meter value */
dm->rf_calibrate_info.thermal_value = thermal_value;
@@ -811,17 +865,17 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series(
thermal_value = (unsigned char)phy_query_rf_reg(priv, RF_PATH_A, 0x42, 0xfc00, 1); /* 0x42: RF Reg[15:10] 88E */
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
/* 4 Query OFDM BB swing default setting Bit[31:21] */
for (rf_path = 0 ; rf_path < max_rf_path ; rf_path++) {
ele_D = phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], MASKDWORD), ele_D);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], MASKDWORD), ele_D);
for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */
if (ele_D == ofdm_swing_table_8812[i]) {
OFDM_index[rf_path] = (unsigned char)i;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "OFDM_index[%d]=%d\n", rf_path, OFDM_index[rf_path]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "OFDM_index[%d]=%d\n", rf_path, OFDM_index[rf_path]);
break;
}
}
@@ -829,22 +883,22 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series(
#if 0
/* Query OFDM path A default setting Bit[31:21] */
ele_D = phy_query_bb_reg(priv, 0xc1c, 0xffe00000);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0xc1c:0x%x ([31:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xc1c, MASKDWORD), ele_D);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xc1c:0x%x ([31:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xc1c, MASKDWORD), ele_D);
for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */
if (ele_D == ofdm_swing_table_8812[i]) {
OFDM_index[0] = (unsigned char)i;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "OFDM_index[0]=%d\n", OFDM_index[0]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "OFDM_index[0]=%d\n", OFDM_index[0]);
break;
}
}
/* Query OFDM path B default setting */
if (rf == 2) {
ele_D = phy_query_bb_reg(priv, 0xe1c, 0xffe00000);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0xe1c:0x%x ([32:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xe1c, MASKDWORD), ele_D);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xe1c:0x%x ([32:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xe1c, MASKDWORD), ele_D);
for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {
if (ele_D == ofdm_swing_table_8812[i]) {
OFDM_index[1] = (unsigned char)i;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "OFDM_index[1]=%d\n", OFDM_index[1]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "OFDM_index[1]=%d\n", OFDM_index[1]);
break;
}
}
@@ -883,8 +937,8 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series(
return;
if (thermal_value != priv->pshare->thermal_value) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n");
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
delta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck);
is_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0);
@@ -893,11 +947,11 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series(
#ifdef _TRACKING_TABLE_FILE
if (priv->pshare->rf_ft_var.pwr_track_file) {
for (rf_path = 0; rf_path < max_rf_path; rf_path++) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
if (is_decrease) {
OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] + get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0);
OFDM_index[rf_path] = ((OFDM_index[rf_path] > (OFDM_TABLE_SIZE_8812 - 1)) ? (OFDM_TABLE_SIZE_8812 - 1) : OFDM_index[rf_path]);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
#if 0/* RTL8881A_SUPPORT */
if (dm->support_ic_type == ODM_RTL8881A) {
if (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) {
@@ -932,7 +986,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series(
#else
OFDM_index[rf_path] = ((OFDM_index[rf_path] < OFDM_min_index) ? OFDM_min_index : OFDM_index[rf_path]);
#endif
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
}
}
}
@@ -940,7 +994,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series(
/* 4 Set new BB swing index */
for (rf_path = 0; rf_path < max_rf_path; rf_path++) {
phy_set_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000, ofdm_swing_table_8812[(unsigned int)OFDM_index[rf_path]]);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000), OFDM_index[rf_path]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000), OFDM_index[rf_path]);
}
}
@@ -959,7 +1013,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series(
RTL_W8(0x522, 0x0);
priv->pshare->thermal_value_lck = thermal_value;
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
/* update thermal meter value */
priv->pshare->thermal_value = thermal_value;
@@ -980,9 +1034,9 @@ odm_txpowertracking_callback_thermal_meter(
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
struct dm_iqk_info *iqk_info = &dm->IQK_info;
#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8197F || dm->support_ic_type == ODM_RTL8822B
|| dm->support_ic_type == ODM_RTL8821C) {
#if (RTL8197F_SUPPORT == 1 ||RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
if (dm->support_ic_type == ODM_RTL8197F || dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8822B
|| dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8198F) {
odm_txpowertracking_callback_thermal_meter_jaguar_series3(dm);
return;
}
@@ -1064,7 +1118,7 @@ odm_txpowertracking_callback_thermal_meter(
return;
}
#endif
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "===>odm_txpowertracking_callback_thermal_meter_8188e, dm->bb_swing_idx_cck_base: %d, dm->bb_swing_idx_ofdm_base: %d\n", cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "===>odm_txpowertracking_callback_thermal_meter_8188e, dm->bb_swing_idx_cck_base: %d, dm->bb_swing_idx_ofdm_base: %d\n", cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base);
/*
if (!dm->rf_calibrate_info.tm_trigger) {
odm_set_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, BIT(17) | BIT(16), 0x3);
@@ -1088,7 +1142,7 @@ odm_txpowertracking_callback_thermal_meter(
}
if (dm->rf_calibrate_info.is_reloadtxpowerindex)
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "reload ofdm index for band switch\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "reload ofdm index for band switch\n");
/* 4 4. Calculate average thermal meter */
@@ -1110,7 +1164,7 @@ odm_txpowertracking_callback_thermal_meter(
thermal_value = (u8)(thermal_value_avg / (thermal_value_avg_count + 4));
cali_info->thermal_value_delta = thermal_value - priv->pmib->dot11RFEntry.ther;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value);
}
/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
@@ -1161,8 +1215,8 @@ odm_txpowertracking_callback_thermal_meter(
cali_info->bb_swing_idx_cck = dm->rf_calibrate_info.CCK_index;
cali_info->bb_swing_idx_ofdm[RF_PATH_A] = dm->rf_calibrate_info.OFDM_index[RF_PATH_A];
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, dm->rf_calibrate_info.power_index_offset);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "The 'OFDM' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base, dm->rf_calibrate_info.power_index_offset);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, dm->rf_calibrate_info.power_index_offset);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "The 'OFDM' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base, dm->rf_calibrate_info.power_index_offset);
/* 4 7.1 Handle boundary conditions of index. */
@@ -1179,12 +1233,12 @@ odm_txpowertracking_callback_thermal_meter(
else if (dm->rf_calibrate_info.CCK_index < 0)
dm->rf_calibrate_info.CCK_index = 0;
} else {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"The thermal meter is unchanged or TxPowerTracking OFF: thermal_value: %d, dm->rf_calibrate_info.thermal_value: %d)\n", thermal_value, dm->rf_calibrate_info.thermal_value);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"The thermal meter is unchanged or TxPowerTracking OFF: thermal_value: %d, dm->rf_calibrate_info.thermal_value: %d)\n", thermal_value, dm->rf_calibrate_info.thermal_value);
dm->rf_calibrate_info.power_index_offset = 0;
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.CCK_index, cali_info->bb_swing_idx_cck_base);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.CCK_index, cali_info->bb_swing_idx_cck_base);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.OFDM_index[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.OFDM_index[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base);
if (dm->rf_calibrate_info.power_index_offset != 0 && dm->rf_calibrate_info.txpowertrack_control) {
/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
@@ -1196,20 +1250,20 @@ odm_txpowertracking_callback_thermal_meter(
/* */
/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
if (thermal_value > dm->rf_calibrate_info.thermal_value) {
/* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK, */
/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK, */
/* "Temperature Increasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */
/* dm->rf_calibrate_info.power_index_offset, delta, thermal_value, hal_data->eeprom_thermal_meter, dm->rf_calibrate_info.thermal_value); */
} else if (thermal_value < dm->rf_calibrate_info.thermal_value) { /* Low temperature */
/* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK, */
/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK, */
/* "Temperature Decreasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */
/* dm->rf_calibrate_info.power_index_offset, delta, thermal_value, hal_data->eeprom_thermal_meter, dm->rf_calibrate_info.thermal_value); */
}
if (thermal_value > dm->priv->pmib->dot11RFEntry.ther)
{
/* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK,"Temperature(%d) hugher than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */
/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK,"Temperature(%d) hugher than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */
(*c.odm_tx_pwr_track_set_pwr)(dm, TXAGC, 0, 0);
} else {
/* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK,"Temperature(%d) lower than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */
/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK,"Temperature(%d) lower than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, RF_PATH_A, indexforchannel);
if (is2T)
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, RF_PATH_B, indexforchannel);
@@ -1221,7 +1275,7 @@ odm_txpowertracking_callback_thermal_meter(
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n");
dm->rf_calibrate_info.tx_powercount = 0;
}

27
hal/phydm/halrf/halphyrf_ap.h
View File

@@ -13,8 +13,8 @@
*
*****************************************************************************/
#ifndef __HAL_PHY_RF_H__
#define __HAL_PHY_RF_H__
#ifndef __HALPHYRF_H__
#define __HALPHYRF_H__
#include "halrf/halrf_powertracking_ap.h"
#include "halrf/halrf_kfree.h"
@@ -31,6 +31,22 @@
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
#endif
#if (RTL8195B_SUPPORT == 1)
// #include "halrf/rtl8195b/halrf.h"
#include "halrf/rtl8195b/halrf_iqk_8195b.h"
#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
#include "halrf/rtl8195b/halrf_dpk_8195b.h"
#endif
#if (RTL8198F_SUPPORT == 1)
#include "halrf/rtl8198f/halrf_iqk_8198f.h"
#include "halrf/rtl8198f/halrf_dpk_8198f.h"
#endif
#if (RTL8814B_SUPPORT == 1)
#include "halrf/rtl8814b/halrf_iqk_8814b.h"
#endif
enum pwrtrack_method {
BBSWING,
TXAGC,
@@ -45,7 +61,7 @@ typedef void (*func_lck)(void *);
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_all_swing_ex)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
struct txpwrtrack_cfg {
u8 swing_table_size_cck;
@@ -60,7 +76,8 @@ struct txpwrtrack_cfg {
func_lck phy_lc_calibrate;
func_swing get_delta_swing_table;
func_swing8814only get_delta_swing_table8814only;
func_all_swing get_delta_all_swing_table;
func_all_swing get_delta_all_swing_table;
func_all_swing_ex get_delta_all_swing_table_ex;
};
void
@@ -119,4 +136,4 @@ odm_get_right_chnl_place_for_iqk(
void phydm_rf_init(void *dm_void);
void phydm_rf_watchdog(void *dm_void);
#endif /* #ifndef __HAL_PHY_RF_H__ */
#endif /*#ifndef __HALPHYRF_H__*/

1125
hal/phydm/halrf/halphyrf_ce.c
View File

File diff suppressed because it is too large Load Diff

106
hal/phydm/halrf/halphyrf_ce.h
View File

@@ -23,25 +23,35 @@
*
*****************************************************************************/
#ifndef __HAL_PHY_RF_H__
#define __HAL_PHY_RF_H__
#ifndef __HALPHYRF_H__
#define __HALPHYRF_H__
#include "halrf/halrf_kfree.h"
#if (RTL8814A_SUPPORT == 1)
#include "halrf/rtl8814a/halrf_iqk_8814a.h"
#include "halrf/rtl8814a/halrf_iqk_8814a.h"
#endif
#if (RTL8822B_SUPPORT == 1)
#include "halrf/rtl8822b/halrf_iqk_8822b.h"
#include "halrf/rtl8822b/halrf_iqk_8822b.h"
#endif
#if (RTL8821C_SUPPORT == 1)
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
#endif
#if (RTL8195B_SUPPORT == 1)
/* #include "halrf/rtl8195b/halrf.h" */
#include "halrf/rtl8195b/halrf_iqk_8195b.h"
#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
#include "halrf/rtl8195b/halrf_dpk_8195b.h"
#endif
#if (RTL8814B_SUPPORT == 1)
#include "halrf/rtl8814b/halrf_iqk_8814b.h"
#endif
#include "halrf/halrf_powertracking_ce.h"
enum spur_cal_method {
PLL_RESET,
AFE_PHASE_SEL
@@ -56,69 +66,49 @@ enum pwrtrack_method {
MIX_5G_TSSI_2G_MODE
};
typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
typedef void(*func_iqk)(void *, u8, u8, u8);
typedef void (*func_lck)(void *);
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void(*func_swing_xtal)(void *, s8 **, s8 **);
typedef void(*func_set_xtal)(void *);
typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
typedef void (*func_iqk)(void *, u8, u8, u8);
typedef void (*func_lck)(void *);
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
typedef void (*func_set_xtal)(void *);
struct txpwrtrack_cfg {
u8 swing_table_size_cck;
u8 swing_table_size_ofdm;
u8 threshold_iqk;
u8 threshold_dpk;
u8 average_thermal_num;
u8 rf_path_count;
u32 thermal_reg_addr;
func_set_pwr odm_tx_pwr_track_set_pwr;
func_iqk do_iqk;
func_lck phy_lc_calibrate;
func_swing get_delta_swing_table;
func_swing8814only get_delta_swing_table8814only;
func_swing_xtal get_delta_swing_xtal_table;
func_set_xtal odm_txxtaltrack_set_xtal;
u8 swing_table_size_cck;
u8 swing_table_size_ofdm;
u8 threshold_iqk;
u8 threshold_dpk;
u8 average_thermal_num;
u8 rf_path_count;
u32 thermal_reg_addr;
func_set_pwr odm_tx_pwr_track_set_pwr;
func_iqk do_iqk;
func_lck phy_lc_calibrate;
func_swing get_delta_swing_table;
func_swing8814only get_delta_swing_table8814only;
func_swing_xtal get_delta_swing_xtal_table;
func_set_xtal odm_txxtaltrack_set_xtal;
};
void
configure_txpower_track(
void *dm_void,
struct txpwrtrack_cfg *config
);
void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config);
void odm_clear_txpowertracking_state(void *dm_void);
void
odm_clear_txpowertracking_state(
void *dm_void
);
void
odm_txpowertracking_callback_thermal_meter(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
void *dm_void
void odm_txpowertracking_callback_thermal_meter(void *dm_void);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
void *dm
void odm_txpowertracking_callback_thermal_meter(void *dm);
#else
void *adapter
void odm_txpowertracking_callback_thermal_meter(void *adapter);
#endif
);
#define ODM_TARGET_CHNL_NUM_2G_5G 59
void odm_reset_iqk_result(void *dm_void);
u8 odm_get_right_chnl_place_for_iqk(u8 chnl);
#define ODM_TARGET_CHNL_NUM_2G_5G 59
void phydm_rf_init(void *dm_void);
void phydm_rf_watchdog(void *dm_void);
void
odm_reset_iqk_result(
void *dm_void
);
u8
odm_get_right_chnl_place_for_iqk(
u8 chnl
);
void phydm_rf_init(void *dm_void);
void phydm_rf_watchdog(void *dm_void);
#endif /* #ifndef __HAL_PHY_RF_H__ */
#endif /*__HALPHYRF_H__*/

528
hal/phydm/halrf/halphyrf_iot.c Normal file
View File

@@ -0,0 +1,528 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
do {\
for (_offset = 0; _offset < _size; _offset++) { \
if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
if (_offset != 0)\
_offset--;\
break;\
} \
} \
if (_offset >= _size)\
_offset = _size-1;\
} while (0)
void configure_txpower_track(
void *dm_void,
struct txpwrtrack_cfg *config
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if RTL8195B_SUPPORT
if (dm->support_ic_type == ODM_RTL8195B)
configure_txpower_track_8195b(config);
#endif
#if RTL8721D_SUPPORT
if (dm->support_ic_type == ODM_RTL8721D)
configure_txpower_track_8721d(config);
#endif
}
/* **********************************************************************
* <20121113, Kordan> This function should be called when tx_agc changed.
* Otherwise the previous compensation is gone, because we record the
* delta of temperature between two TxPowerTracking watch dogs.
*
* NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
* need to call this function.
* ********************************************************************** */
void
odm_clear_txpowertracking_state(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _hal_rf_ *rf = &dm->rf_table;
u8 p = 0;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
dm->rf_calibrate_info.CCK_index = 0;
for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
cali_info->power_index_offset[p] = 0;
cali_info->delta_power_index[p] = 0;
cali_info->delta_power_index_last[p] = 0;
cali_info->absolute_ofdm_swing_idx[p] = 0;
cali_info->remnant_ofdm_swing_idx[p] = 0;
cali_info->kfree_offset[p] = 0;
}
cali_info->modify_tx_agc_flag_path_a = false;
cali_info->modify_tx_agc_flag_path_b = false;
cali_info->modify_tx_agc_flag_path_c = false;
cali_info->modify_tx_agc_flag_path_d = false;
cali_info->remnant_cck_swing_idx = 0;
cali_info->thermal_value = rf->eeprom_thermal;
cali_info->modify_tx_agc_value_cck = 0;
cali_info->modify_tx_agc_value_ofdm = 0;
}
void
odm_txpowertracking_callback_thermal_meter(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _hal_rf_ *rf = &dm->rf_table;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
struct dm_iqk_info *iqk_info = &dm->IQK_info;
u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
u8 thermal_value_avg_count = 0;
u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */
u8 power_tracking_type = rf->pwt_type;
u8 xtal_offset_eanble = 0;
s8 thermal_value_temp = 0;
struct txpwrtrack_cfg c = {0};
/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
u8 *delta_swing_table_idx_tup_a = NULL;
u8 *delta_swing_table_idx_tdown_a = NULL;
u8 *delta_swing_table_idx_tup_b = NULL;
u8 *delta_swing_table_idx_tdown_b = NULL;
/*for Xtal Offset by James.Tung*/
s8 *delta_swing_table_xtal_up = NULL;
s8 *delta_swing_table_xtal_down = NULL;
/* 4 2. Initialization ( 7 steps in total ) */
configure_txpower_track(dm, &c);
(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
/*for Xtal Offset*/
if (dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8721D))
(*c.get_delta_swing_xtal_table)(dm,
(s8 **)&delta_swing_table_xtal_up,
(s8 **)&delta_swing_table_xtal_down);
cali_info->txpowertracking_callback_cnt++; /*cosa add for debug*/
cali_info->is_txpowertracking_init = true;
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
cali_info->bb_swing_idx_cck_base,
cali_info->bb_swing_idx_ofdm_base[RF_PATH_A],
cali_info->default_ofdm_index);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"cali_info->txpowertrack_control = %d, hal_data->eeprom_thermal_meter %d\n",
cali_info->txpowertrack_control, rf->eeprom_thermal);
if (dm->support_ic_type == ODM_RTL8721D)
thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A,
c.thermal_reg_addr, 0x7e0);
/* 0x42: RF Reg[10:5] 8721D */
else
thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A,
c.thermal_reg_addr, 0xfc00);
/* 0x42: RF Reg[15:10] 88E */
thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"thermal_value_temp(%d) = thermal_value(%d) + power_trim_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));
if (thermal_value_temp > 63)
thermal_value = 63;
else if (thermal_value_temp < 0)
thermal_value = 0;
else
thermal_value = thermal_value_temp;
if (!cali_info->txpowertrack_control)
return;
if (rf->eeprom_thermal == 0xff) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", rf->eeprom_thermal);
return;
}
#if 0
/*4 3. Initialize ThermalValues of rf_calibrate_info*/
//if (cali_info->is_reloadtxpowerindex)
// RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "reload ofdm index for band switch\n");
#endif
/*4 4. Calculate average thermal meter*/
cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] = thermal_value;
cali_info->thermal_value_avg_index++;
if (cali_info->thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/
cali_info->thermal_value_avg_index = 0;
for (i = 0; i < c.average_thermal_num; i++) {
if (cali_info->thermal_value_avg[i]) {
thermal_value_avg += cali_info->thermal_value_avg[i];
thermal_value_avg_count++;
}
}
if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */
thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
cali_info->thermal_value_delta = thermal_value - rf->eeprom_thermal;
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, rf->eeprom_thermal);
}
/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
/* "delta" here is used to determine whether thermal value changes or not. */
delta = (thermal_value > cali_info->thermal_value) ? (thermal_value - cali_info->thermal_value) : (cali_info->thermal_value - thermal_value);
delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
/*4 6. If necessary, do LCK.*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
/* Wait sacn to do LCK by RF Jenyu*/
if ((!*dm->is_scan_in_process) && !iqk_info->rfk_forbidden &&
(!*dm->is_tdma)) {
/* Delta temperature is equal to or larger than 20 centigrade.*/
if (delta_LCK >= c.threshold_iqk) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
cali_info->thermal_value_lck = thermal_value;
/*Use RTLCK, so close power tracking driver LCK*/
(*c.phy_lc_calibrate)(dm);
}
}
/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
if (delta > 0 && cali_info->txpowertrack_control) {
/* "delta" here is used to record the absolute value of difference. */
delta = thermal_value > rf->eeprom_thermal ? (thermal_value - rf->eeprom_thermal) : (rf->eeprom_thermal - thermal_value);
if (delta >= TXPWR_TRACK_TABLE_SIZE)
delta = TXPWR_TRACK_TABLE_SIZE - 1;
/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
if (thermal_value > rf->eeprom_thermal) {
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
switch (p) {
case RF_PATH_B:
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
cali_info->delta_power_index[p] =
delta_swing_table_idx_tup_b
[delta];
cali_info->absolute_ofdm_swing_idx[p] =
delta_swing_table_idx_tup_b
[delta];
/*Record delta swing for mix mode*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
default:
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
cali_info->absolute_ofdm_swing_idx[p] =
delta_swing_table_idx_tup_a[delta];
/*Record delta swing*/
/*for mix mode power tracking*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
}
}
/* JJ ADD 20161014 */
if (dm->support_ic_type &
(ODM_RTL8195B | ODM_RTL8721D)) {
/*Save xtal_offset from Xtal table*/
cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]);
cali_info->xtal_offset = delta_swing_table_xtal_up[delta];
xtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset);
}
} else {
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
switch (p) {
case RF_PATH_B:
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
default:
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
}
}
/* JJ ADD 20161014 */
if (dm->support_ic_type &
(ODM_RTL8195B | ODM_RTL8721D)) {
/*Save xtal_offset from Xtal table*/
cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]);
cali_info->xtal_offset = delta_swing_table_xtal_down[delta];
xtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset);
}
}
#if 0
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p);
if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/
cali_info->power_index_offset[p] = 0;
else
cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]);
cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];
cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p];
cali_info->bb_swing_idx_cck = cali_info->CCK_index;
cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p];
/*************Print BB Swing base and index Offset*************/
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]);
/*4 7.1 Handle boundary conditions of index.*/
if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
else if (cali_info->OFDM_index[p] <= OFDM_min_index)
cali_info->OFDM_index[p] = OFDM_min_index;
}
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"\n\n========================================================================================================\n");
if (cali_info->CCK_index > c.swing_table_size_cck - 1)
cali_info->CCK_index = c.swing_table_size_cck - 1;
else if (cali_info->CCK_index <= 0)
cali_info->CCK_index = 0;
#endif
} else {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n",
cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value);
for (p = RF_PATH_A; p < c.rf_path_count; p++)
cali_info->power_index_offset[p] = 0;
}
#if 0
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
cali_info->CCK_index, cali_info->bb_swing_idx_cck_base); /*Print Swing base & current*/
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]);
}
#endif
if (thermal_value > rf->eeprom_thermal) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"Temperature(%d) higher than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
if (dm->support_ic_type == ODM_RTL8188E ||
dm->support_ic_type == ODM_RTL8192E ||
dm->support_ic_type == ODM_RTL8821 ||
dm->support_ic_type == ODM_RTL8812 ||
dm->support_ic_type == ODM_RTL8723B ||
dm->support_ic_type == ODM_RTL8814A ||
dm->support_ic_type == ODM_RTL8703B ||
dm->support_ic_type == ODM_RTL8188F ||
dm->support_ic_type == ODM_RTL8822B ||
dm->support_ic_type == ODM_RTL8723D ||
dm->support_ic_type == ODM_RTL8821C ||
dm->support_ic_type == ODM_RTL8710B ||
dm->support_ic_type == ODM_RTL8192F ||
dm->support_ic_type == ODM_RTL8195B ||
dm->support_ic_type == ODM_RTL8721D){
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
} else {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
}
} else {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"Temperature(%d) lower than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
if (dm->support_ic_type == ODM_RTL8188E ||
dm->support_ic_type == ODM_RTL8192E ||
dm->support_ic_type == ODM_RTL8821 ||
dm->support_ic_type == ODM_RTL8812 ||
dm->support_ic_type == ODM_RTL8723B ||
dm->support_ic_type == ODM_RTL8814A ||
dm->support_ic_type == ODM_RTL8703B ||
dm->support_ic_type == ODM_RTL8188F ||
dm->support_ic_type == ODM_RTL8822B ||
dm->support_ic_type == ODM_RTL8723D ||
dm->support_ic_type == ODM_RTL8821C ||
dm->support_ic_type == ODM_RTL8710B ||
dm->support_ic_type == ODM_RTL8192F ||
dm->support_ic_type == ODM_RTL8195B ||
dm->support_ic_type == ODM_RTL8721D) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel);
} else {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
}
cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/
for (p = RF_PATH_A; p < c.rf_path_count; p++)
cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"cali_info->thermal_value = %d thermal_value= %d\n", cali_info->thermal_value, thermal_value);
cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
}
/* JJ ADD 20161014 */
if (dm->support_ic_type == (ODM_RTL8195B | ODM_RTL8721D)) {
if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (rf->eeprom_thermal != 0xff)) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
if (thermal_value > rf->eeprom_thermal) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"Temperature(%d) higher than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
(*c.odm_txxtaltrack_set_xtal)(dm);
} else {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"Temperature(%d) lower than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
(*c.odm_txxtaltrack_set_xtal)(dm);
}
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
}
}
/* Wait sacn to do IQK by RF Jenyu*/
if ((!*dm->is_scan_in_process) && (!iqk_info->rfk_forbidden)) {
/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
if (delta_IQK >= c.threshold_iqk) {
cali_info->thermal_value_iqk = thermal_value;
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
if (!cali_info->is_iqk_in_progress)
(*c.do_iqk)(dm, delta_IQK, thermal_value, 8);
}
}
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n");
cali_info->tx_powercount = 0;
}
/* 3============================================================
* 3 IQ Calibration
* 3============================================================
*/
void
odm_reset_iqk_result(
void *dm_void
)
{
return;
}
u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
{
}
void
odm_iq_calibrate(
struct dm_struct *dm
)
{
}
void phydm_rf_init(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
odm_txpowertracking_init(dm);
odm_clear_txpowertracking_state(dm);
}
void phydm_rf_watchdog(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
odm_txpowertracking_check(dm);
}

124
hal/phydm/halrf/halphyrf_iot.h Normal file
View File

@@ -0,0 +1,124 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALPHYRF_H__
#define __HALPHYRF_H__
#include "halrf/halrf_kfree.h"
#if (RTL8821C_SUPPORT == 1)
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
#endif
#if (RTL8195B_SUPPORT == 1)
// #include "halrf/rtl8195b/halrf.h"
#include "halrf/rtl8195b/halrf_iqk_8195b.h"
#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
#include "halrf/rtl8195b/halrf_dpk_8195b.h"
#endif
#include "halrf/halrf_powertracking_iot.h"
enum spur_cal_method {
PLL_RESET,
AFE_PHASE_SEL
};
enum pwrtrack_method {
BBSWING,
TXAGC,
MIX_MODE,
TSSI_MODE,
MIX_2G_TSSI_5G_MODE,
MIX_5G_TSSI_2G_MODE
};
typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
typedef void(*func_iqk)(void *, u8, u8, u8);
typedef void (*func_lck)(void *);
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void(*func_swing_xtal)(void *, s8 **, s8 **);
typedef void(*func_set_xtal)(void *);
struct txpwrtrack_cfg {
u8 swing_table_size_cck;
u8 swing_table_size_ofdm;
u8 threshold_iqk;
u8 threshold_dpk;
u8 average_thermal_num;
u8 rf_path_count;
u32 thermal_reg_addr;
func_set_pwr odm_tx_pwr_track_set_pwr;
func_iqk do_iqk;
func_lck phy_lc_calibrate;
func_swing get_delta_swing_table;
func_swing8814only get_delta_swing_table8814only;
func_swing_xtal get_delta_swing_xtal_table;
func_set_xtal odm_txxtaltrack_set_xtal;
};
void
configure_txpower_track(
void *dm_void,
struct txpwrtrack_cfg *config
);
void
odm_clear_txpowertracking_state(
void *dm_void
);
void
odm_txpowertracking_callback_thermal_meter(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
void *dm_void
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
void *dm
#else
void *adapter
#endif
);
#define ODM_TARGET_CHNL_NUM_2G_5G 59
void
odm_reset_iqk_result(
void *dm_void
);
u8
odm_get_right_chnl_place_for_iqk(
u8 chnl
);
void phydm_rf_init(void *dm_void);
void phydm_rf_watchdog(void *dm_void);
#endif /*#ifndef __HALPHYRF_H__*/

220
hal/phydm/halrf/halphyrf_win.c
View File

@@ -94,6 +94,16 @@ void configure_txpower_track(
configure_txpower_track_8821c(config);
#endif
#if RTL8192F_SUPPORT
if (dm->support_ic_type == ODM_RTL8192F)
configure_txpower_track_8192f(config);
#endif
#if RTL8822C_SUPPORT
if (dm->support_ic_type == ODM_RTL8822C)
configure_txpower_track_8822c(config);
#endif
}
/* **********************************************************************
@@ -166,7 +176,7 @@ odm_txpowertracking_callback_thermal_meter(
u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
s8 diff_DPK[4] = {0};
u8 thermal_value_avg_count = 0;
u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4, regc88, rege14, reg848,reg838, reg86c;
u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */
@@ -201,7 +211,7 @@ odm_txpowertracking_callback_thermal_meter(
(*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
/* JJ ADD 20161014 */
if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) /*for Xtal Offset*/
if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F)) /*for Xtal Offset*/
(*c.get_delta_swing_xtal_table)(dm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down);
@@ -220,17 +230,17 @@ odm_txpowertracking_callback_thermal_meter(
cali_info->rega24 = 0x090e1317;
#endif
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"cali_info->txpowertrack_control=%d, hal_data->eeprom_thermal_meter %d\n", cali_info->txpowertrack_control, hal_data->eeprom_thermal_meter);
thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"thermal_value_temp(%d) = thermal_value(%d) + power_time_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));
if (thermal_value_temp > 63)
@@ -242,34 +252,46 @@ odm_txpowertracking_callback_thermal_meter(
/*add log by zhao he, check c80/c94/c14/ca0 value*/
if (dm->support_ic_type == ODM_RTL8723D) {
regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD);
regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD);
regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD);
regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
regcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD);
regcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD);
regab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF);
RF_DBG(dm, DBG_RF_IQK, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
}
/* JJ ADD 20161014 */
if (dm->support_ic_type == ODM_RTL8710B) {
regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD);
regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD);
regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD);
regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
regcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD);
regcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD);
regab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF);
RF_DBG(dm, DBG_RF_IQK, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
}
/* Winnita add 20171205 */
if (dm->support_ic_type == ODM_RTL8192F) {
regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
regc88 = odm_get_bb_reg(dm, R_0xc88, MASKDWORD);
regab4 = odm_get_bb_reg(dm, R_0xab4, MASKDWORD);
rege14 = odm_get_bb_reg(dm, R_0xe14, MASKDWORD);
reg848 = odm_get_bb_reg(dm, R_0x848, MASKDWORD);
reg838 = odm_get_bb_reg(dm, R_0x838, MASKDWORD);
reg86c = odm_get_bb_reg(dm, R_0x86c, MASKDWORD);
RF_DBG(dm, DBG_RF_IQK, "0xc80 = 0x%x 0xc88 = 0x%x 0xab4 = 0x%x 0xe14 = 0x%x\n", regc80, regc88, regab4, rege14);
RF_DBG(dm, DBG_RF_IQK, "0x848 = 0x%x 0x838 = 0x%x 0x86c = 0x%x\n", reg848, reg838, reg86c);
}
if (!cali_info->txpowertrack_control)
return;
if (hal_data->eeprom_thermal_meter == 0xff) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", hal_data->eeprom_thermal_meter);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", hal_data->eeprom_thermal_meter);
return;
}
/*4 3. Initialize ThermalValues of rf_calibrate_info*/
if (cali_info->is_reloadtxpowerindex)
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "reload ofdm index for band switch\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "reload ofdm index for band switch\n");
/*4 4. Calculate average thermal meter*/
@@ -288,7 +310,7 @@ odm_txpowertracking_callback_thermal_meter(
if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */
thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
cali_info->thermal_value_delta = thermal_value - hal_data->eeprom_thermal_meter;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, hal_data->eeprom_thermal_meter);
}
@@ -302,7 +324,7 @@ odm_txpowertracking_callback_thermal_meter(
if (cali_info->thermal_value_iqk == 0xff) { /*no PG, use thermal value for IQK*/
cali_info->thermal_value_iqk = thermal_value;
delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no PG, use thermal_value for IQK\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no PG, use thermal_value for IQK\n");
}
for (p = RF_PATH_A; p < c.rf_path_count; p++)
@@ -312,7 +334,7 @@ odm_txpowertracking_callback_thermal_meter(
if (!(dm->support_ic_type & ODM_RTL8821)) { /*no PG, do LCK at initial status*/
if (cali_info->thermal_value_lck == 0xff) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no PG, do LCK\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no PG, do LCK\n");
cali_info->thermal_value_lck = thermal_value;
/*Use RTLCK, so close power tracking driver LCK*/
@@ -324,13 +346,13 @@ odm_txpowertracking_callback_thermal_meter(
delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
/* Wait sacn to do LCK by RF Jenyu*/
if( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
/* Delta temperature is equal to or larger than 20 centigrade.*/
if (delta_LCK >= c.threshold_iqk) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
cali_info->thermal_value_lck = thermal_value;
/*Use RTLCK, so close power tracking driver LCK*/
@@ -366,51 +388,51 @@ odm_txpowertracking_callback_thermal_meter(
cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
switch (p) {
case RF_PATH_B:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta];
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
case RF_PATH_C:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]);
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta];
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
case RF_PATH_D:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]);
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta];
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
default:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
}
}
/* JJ ADD 20161014 */
if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F)) {
/*Save xtal_offset from Xtal table*/
cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]);
cali_info->xtal_offset = delta_swing_table_xtal_up[delta];
@@ -426,47 +448,47 @@ odm_txpowertracking_callback_thermal_meter(
switch (p) {
case RF_PATH_B:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
case RF_PATH_C:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]);
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta];
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
case RF_PATH_D:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]);
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta];
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
default:
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
break;
}
}
/* JJ ADD 20161014 */
if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F)) {
/*Save xtal_offset from Xtal table*/
cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]);
cali_info->xtal_offset = delta_swing_table_xtal_down[delta];
@@ -479,7 +501,7 @@ odm_txpowertracking_callback_thermal_meter(
}
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p);
if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/
@@ -487,7 +509,7 @@ odm_txpowertracking_callback_thermal_meter(
else
cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]);
cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];
@@ -498,9 +520,9 @@ odm_txpowertracking_callback_thermal_meter(
/*************Print BB Swing base and index Offset*************/
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]);
/*4 7.1 Handle boundary conditions of index.*/
@@ -511,7 +533,7 @@ odm_txpowertracking_callback_thermal_meter(
cali_info->OFDM_index[p] = OFDM_min_index;
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"\n\n========================================================================================================\n");
if (cali_info->CCK_index > c.swing_table_size_cck - 1)
@@ -519,7 +541,7 @@ odm_txpowertracking_callback_thermal_meter(
else if (cali_info->CCK_index <= 0)
cali_info->CCK_index = 0;
} else {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n",
cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value);
@@ -527,33 +549,33 @@ odm_txpowertracking_callback_thermal_meter(
cali_info->power_index_offset[p] = 0;
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
cali_info->CCK_index, cali_info->bb_swing_idx_cck_base); /*Print Swing base & current*/
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]);
}
if ((dm->support_ic_type & ODM_RTL8814A)) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "power_tracking_type=%d\n", power_tracking_type);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "power_tracking_type=%d\n", power_tracking_type);
if (power_tracking_type == 0) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
} else if (power_tracking_type == 1) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_2G_TSSI_5G_MODE, p, 0);
} else if (power_tracking_type == 2) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_5G_TSSI_2G_MODE, p, 0);
} else if (power_tracking_type == 3) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI MODE**********\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0);
}
@@ -574,13 +596,13 @@ odm_txpowertracking_callback_thermal_meter(
/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
if (thermal_value > cali_info->thermal_value) {
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);
}
} else if (thermal_value < cali_info->thermal_value) { /*Low temperature*/
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);
}
@@ -592,36 +614,37 @@ odm_txpowertracking_callback_thermal_meter(
if (thermal_value > dm->priv->pmib->dot11RFEntry.ther)
#endif
{
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B ||
dm->support_ic_type == ODM_RTL8192F) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
} else {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
}
} else {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B ||
dm->support_ic_type == ODM_RTL8192F) {
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel);
} else {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
for (p = RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
}
@@ -632,7 +655,7 @@ odm_txpowertracking_callback_thermal_meter(
for (p = RF_PATH_A; p < c.rf_path_count; p++)
cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"cali_info->thermal_value = %d thermal_value= %d\n", cali_info->thermal_value, thermal_value);
cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
@@ -640,27 +663,28 @@ odm_txpowertracking_callback_thermal_meter(
}
if (dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
if (dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D ||
dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
if (thermal_value > hal_data->eeprom_thermal_meter) {
#else
if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
#endif
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
(*c.odm_txxtaltrack_set_xtal)(dm);
} else {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
(*c.odm_txxtaltrack_set_xtal)(dm);
}
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
@@ -671,7 +695,7 @@ odm_txpowertracking_callback_thermal_meter(
/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
if (delta_IQK >= c.threshold_iqk) {
cali_info->thermal_value_iqk = thermal_value;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
if (!cali_info->is_iqk_in_progress)
(*c.do_iqk)(dm, delta_IQK, thermal_value, 8);
}
@@ -679,42 +703,42 @@ odm_txpowertracking_callback_thermal_meter(
}
if (cali_info->dpk_thermal[RF_PATH_A] != 0) {
if (diff_DPK[RF_PATH_A] >= c.threshold_dpk) {
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk));
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk));
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
} else if ((diff_DPK[RF_PATH_A] <= -1 * c.threshold_dpk)) {
s32 value = 0x20 + (diff_DPK[RF_PATH_A] / c.threshold_dpk);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
} else {
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
}
}
if (cali_info->dpk_thermal[RF_PATH_B] != 0) {
if (diff_DPK[RF_PATH_B] >= c.threshold_dpk) {
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk));
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk));
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
} else if ((diff_DPK[RF_PATH_B] <= -1 * c.threshold_dpk)) {
s32 value = 0x20 + (diff_DPK[RF_PATH_B] / c.threshold_dpk);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
} else {
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
}
}
#endif
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n");
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n");
cali_info->tx_powercount = 0;
}
@@ -760,7 +784,7 @@ odm_iq_calibrate(
void *adapter = dm->adapter;
struct dm_iqk_info *iqk_info = &dm->IQK_info;
RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("=>%s\n" , __FUNCTION__));
RF_DBG(dm, DBG_RF_IQK, "=>%s\n",__FUNCTION__);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
if (*dm->is_fcs_mode_enable)
@@ -768,8 +792,8 @@ odm_iq_calibrate(
#endif
if ((dm->is_linked) && (!iqk_info->rfk_forbidden)) {
RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("interval=%d ch=%d prech=%d scan=%s\n", dm->linked_interval,
*dm->channel, dm->pre_channel, *dm->is_scan_in_process == TRUE ? "TRUE":"FALSE"));
RF_DBG(dm, DBG_RF_IQK, "interval=%d ch=%d prech=%d scan=%s\n", dm->linked_interval,
*dm->channel, dm->pre_channel, *dm->is_scan_in_process == TRUE ? "TRUE":"FALSE");
if (*dm->channel != dm->pre_channel) {
dm->pre_channel = *dm->channel;
@@ -780,12 +804,12 @@ odm_iq_calibrate(
dm->linked_interval++;
if (dm->linked_interval == 2)
PHY_IQCalibrate((PADAPTER)adapter, false);
PHY_IQCalibrate(adapter, false);
} else
dm->linked_interval = 0;
RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("<=%s interval=%d ch=%d prech=%d scan=%s\n", __FUNCTION__, dm->linked_interval,
*dm->channel, dm->pre_channel, *dm->is_scan_in_process == TRUE?"TRUE":"FALSE"));
RF_DBG(dm, DBG_RF_IQK, "<=%s interval=%d ch=%d prech=%d scan=%s\n", __FUNCTION__, dm->linked_interval,
*dm->channel, dm->pre_channel, *dm->is_scan_in_process == TRUE?"TRUE":"FALSE");
}
void phydm_rf_init(struct dm_struct *dm)

52
hal/phydm/halrf/halphyrf_win.h
View File

@@ -13,43 +13,33 @@
*
*****************************************************************************/
#ifndef __HAL_PHY_RF_H__
#define __HAL_PHY_RF_H__
#ifndef __HALPHYRF_H__
#define __HALPHYRF_H__
#if (RTL8814A_SUPPORT == 1)
#if RT_PLATFORM == PLATFORM_MACOSX
#include "rtl8814a/halrf_iqk_8814a.h"
#else
#include "halrf/rtl8814a/halrf_iqk_8814a.h"
#endif
#include "halrf/rtl8814a/halrf_iqk_8814a.h"
#endif
#if (RTL8822B_SUPPORT == 1)
#if RT_PLATFORM == PLATFORM_MACOSX
#include "rtl8822b/halrf_iqk_8822b.h"
#include "../../MAC/Halmac_type.h"
#else
#include "halrf/rtl8822b/halrf_iqk_8822b.h"
#include "../mac/Halmac_type.h"
#endif
#include "halrf/rtl8822b/halrf_iqk_8822b.h"
#include "../mac/Halmac_type.h"
#endif
#if RT_PLATFORM == PLATFORM_MACOSX
#include "halrf_powertracking_win.h"
#include "halrf_kfree.h"
#include "halrf_txgapcal.h"
#else
#include "halrf/halrf_powertracking_win.h"
#include "halrf/halrf_kfree.h"
#include "halrf/halrf_txgapcal.h"
#endif
#include "halrf/halrf_powertracking_win.h"
#include "halrf/halrf_kfree.h"
#include "halrf/halrf_txgapcal.h"
#if (RTL8821C_SUPPORT == 1)
#if RT_PLATFORM == PLATFORM_MACOSX
#include "rtl8821c/halrf_iqk_8821c.h"
#else
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
#endif
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
#endif
#if (RTL8195B_SUPPORT == 1)
// #include "halrf/rtl8195b/halrf.h"
#include "halrf/rtl8195b/halrf_iqk_8195b.h"
#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
#include "halrf/rtl8195b/halrf_dpk_8195b.h"
#endif
#if (RTL8814B_SUPPORT == 1)
#include "halrf/rtl8814b/halrf_iqk_8814b.h"
#endif
enum spur_cal_method {
@@ -132,4 +122,4 @@ void odm_iq_calibrate(struct dm_struct *dm);
void phydm_rf_init(struct dm_struct *dm);
void phydm_rf_watchdog(struct dm_struct *dm);
#endif /* #ifndef __HAL_PHY_RF_H__ */
#endif /*#ifndef __HALPHYRF_H__*/

2380
hal/phydm/halrf/halrf.c
View File

File diff suppressed because it is too large Load Diff

783
hal/phydm/halrf/halrf.h
View File

@@ -23,242 +23,385 @@
*
*****************************************************************************/
#ifndef __HALRF_H__
#define __HALRF_H__
#ifndef _HALRF_H__
#define _HALRF_H__
/*============================================================*/
/*include files*/
/*============================================================*/
/*@============================================================*/
/*@include files*/
/*@============================================================*/
#include "halrf/halrf_psd.h"
#if (RTL8822B_SUPPORT == 1)
#include "halrf/rtl8822b/halrf_rfk_init_8822b.h"
#endif
#if (RTL8822C_SUPPORT == 1)
#include "halrf/rtl8822c/halrf_rfk_init_8822c.h"
#include "halrf/rtl8822c/halrf_iqk_8822c.h"
#include "halrf/rtl8822c/halrf_tssi_8822c.h"
#include "halrf/rtl8822c/halrf_dpk_8822c.h"
#endif
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
#if (RTL8198F_SUPPORT == 1)
#include "halrf/rtl8198f/halrf_rfk_init_8198f.h"
#endif
#endif
/*============================================================*/
/*Definition */
/*============================================================*/
#if (RTL8814B_SUPPORT == 1)
#include "halrf/rtl8814b/halrf_rfk_init_8814b.h"
#include "halrf/rtl8814b/halrf_iqk_8814b.h"
#endif
/*@============================================================*/
/*@Definition */
/*@============================================================*/
/*IQK version*/
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
#define IQK_VERSION_8188E "0x14"
#define IQK_VERSION_8192E "0x01"
#define IQK_VERSION_8723B "0x1e"
#define IQK_VERSION_8812A "0x01"
#define IQK_VERSION_8821A "0x01"
#define IQK_VER_8188E "0x14"
#define IQK_VER_8192E "0x01"
#define IQK_VER_8192F "0x01"
#define IQK_VER_8723B "0x1e"
#define IQK_VER_8812A "0x02"
#define IQK_VER_8821A "0x01"
#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
#define IQK_VERSION_8188E "0x01"
#define IQK_VERSION_8192E "0x01"
#define IQK_VERSION_8723B "0x1e"
#define IQK_VERSION_8812A "0x01"
#define IQK_VERSION_8821A "0x01"
#define IQK_VER_8188E "0x01"
#define IQK_VER_8192E "0x01"
#define IQK_VER_8192F "0x01"
#define IQK_VER_8723B "0x1e"
#define IQK_VER_8812A "0x01"
#define IQK_VER_8821A "0x01"
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
#define IQK_VERSION_8188E "0x01"
#define IQK_VERSION_8192E "0x01"
#define IQK_VERSION_8723B "0x1e"
#define IQK_VERSION_8812A "0x01"
#define IQK_VERSION_8821A "0x01"
#define IQK_VER_8188E "0x01"
#define IQK_VER_8192E "0x01"
#define IQK_VER_8192F "0x01"
#define IQK_VER_8723B "0x1e"
#define IQK_VER_8812A "0x01"
#define IQK_VER_8821A "0x01"
#elif (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
#define IQK_VER_8188E "0x01"
#define IQK_VER_8192E "0x01"
#define IQK_VER_8192F "0x01"
#define IQK_VER_8723B "0x1e"
#define IQK_VER_8812A "0x01"
#define IQK_VER_8821A "0x01"
#endif
#define IQK_VERSION_8814A "0x0f"
#define IQK_VERSION_8188F "0x01"
#define IQK_VERSION_8197F "0x01"
#define IQK_VERSION_8703B "0x05"
#define IQK_VERSION_8710B "0x01"
#define IQK_VERSION_8723D "0x02"
#define IQK_VERSION_8822B "0x2f"
#define IQK_VERSION_8821C "0x23"
#define IQK_VER_8814A "0x0f"
#define IQK_VER_8188F "0x01"
#define IQK_VER_8197F "0x1d"
#define IQK_VER_8703B "0x05"
#define IQK_VER_8710B "0x01"
#define IQK_VER_8723D "0x02"
#define IQK_VER_8822B "0x2f"
#define IQK_VER_8822C "0x03"
#define IQK_VER_8821C "0x23"
#define IQK_VER_8198F "0x09"
#define IQK_VER_8814B "0x06"
/*LCK version*/
#define LCK_VERSION_8188E "0x01"
#define LCK_VERSION_8192E "0x01"
#define LCK_VERSION_8723B "0x01"
#define LCK_VERSION_8812A "0x01"
#define LCK_VERSION_8821A "0x01"
#define LCK_VERSION_8814A "0x01"
#define LCK_VERSION_8188F "0x01"
#define LCK_VERSION_8197F "0x01"
#define LCK_VERSION_8703B "0x01"
#define LCK_VERSION_8710B "0x01"
#define LCK_VERSION_8723D "0x01"
#define LCK_VERSION_8822B "0x01"
#define LCK_VERSION_8821C "0x01"
#define LCK_VER_8188E "0x01"
#define LCK_VER_8192E "0x01"
#define LCK_VER_8192F "0x01"
#define LCK_VER_8723B "0x01"
#define LCK_VER_8812A "0x01"
#define LCK_VER_8821A "0x01"
#define LCK_VER_8814A "0x01"
#define LCK_VER_8188F "0x01"
#define LCK_VER_8197F "0x01"
#define LCK_VER_8703B "0x01"
#define LCK_VER_8710B "0x01"
#define LCK_VER_8723D "0x01"
#define LCK_VER_8822B "0x02"
#define LCK_VER_8822C "0x00"
#define LCK_VER_8821C "0x02"
#define LCK_VER_8814B "0x00"
#define LCK_VER_8195B "0x02"
/*power tracking version*/
#define POWERTRACKING_VERSION_8188E "0x01"
#define POWERTRACKING_VERSION_8192E "0x01"
#define POWERTRACKING_VERSION_8723B "0x01"
#define POWERTRACKING_VERSION_8812A "0x01"
#define POWERTRACKING_VERSION_8821A "0x01"
#define POWERTRACKING_VERSION_8814A "0x01"
#define POWERTRACKING_VERSION_8188F "0x01"
#define POWERTRACKING_VERSION_8197F "0x01"
#define POWERTRACKING_VERSION_8703B "0x01"
#define POWERTRACKING_VERSION_8710B "0x01"
#define POWERTRACKING_VERSION_8723D "0x01"
#define POWERTRACKING_VERSION_8822B "0x01"
#define POWERTRACKING_VERSION_8821C "0x01"
#define PWRTRK_VER_8188E "0x01"
#define PWRTRK_VER_8192E "0x01"
#define PWRTRK_VER_8192F "0x01"
#define PWRTRK_VER_8723B "0x01"
#define PWRTRK_VER_8812A "0x01"
#define PWRTRK_VER_8821A "0x01"
#define PWRTRK_VER_8814A "0x01"
#define PWRTRK_VER_8188F "0x01"
#define PWRTRK_VER_8197F "0x01"
#define PWRTRK_VER_8703B "0x01"
#define PWRTRK_VER_8710B "0x01"
#define PWRTRK_VER_8723D "0x01"
#define PWRTRK_VER_8822B "0x01"
#define PWRTRK_VER_8822C "0x00"
#define PWRTRK_VER_8821C "0x01"
#define PWRTRK_VER_8814B "0x00"
/*DPK tracking version*/
#define DPK_VERSION_8188E "NONE"
#define DPK_VERSION_8192E "NONE"
#define DPK_VERSION_8723B "NONE"
#define DPK_VERSION_8812A "NONE"
#define DPK_VERSION_8821A "NONE"
#define DPK_VERSION_8814A "NONE"
#define DPK_VERSION_8188F "NONE"
#define DPK_VERSION_8197F "NONE"
#define DPK_VERSION_8703B "NONE"
#define DPK_VERSION_8710B "NONE"
#define DPK_VERSION_8723D "NONE"
#define DPK_VERSION_8822B "NONE"
#define DPK_VERSION_8821C "NONE"
/*DPK version*/
#define DPK_VER_8188E "NONE"
#define DPK_VER_8192E "NONE"
#define DPK_VER_8723B "NONE"
#define DPK_VER_8812A "NONE"
#define DPK_VER_8821A "NONE"
#define DPK_VER_8814A "NONE"
#define DPK_VER_8188F "NONE"
#define DPK_VER_8197F "0x08"
#define DPK_VER_8703B "NONE"
#define DPK_VER_8710B "NONE"
#define DPK_VER_8723D "NONE"
#define DPK_VER_8822B "NONE"
#define DPK_VER_8822C "0x04"
#define DPK_VER_8821C "NONE"
#define DPK_VER_8192F "0x0c"
#define DPK_VER_8198F "0x0a"
#define DPK_VER_8814B "0x00"
#define DPK_VER_8195B "0x06"
/*RFK_INIT version*/
#define RFK_INIT_VER_8822B "0x8"
#define RFK_INIT_VER_8822C "0x3"
#define RFK_INIT_VER_8195B "0x1"
#define RFK_INIT_VER_8198F "0x5"
#define RFK_INIT_VER_8814B "0x5"
/*DACK version*/
#define DACK_VER_8822C "0x3"
/*Kfree tracking version*/
#define KFREE_VERSION_8188E (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8192E (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8723B (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8812A (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8821A (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8814A (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8188F (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8197F (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8703B (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8710B (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8723D (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8822B (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VERSION_8821C (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
#define KFREE_VER_8188E \
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
#define KFREE_VER_8192E \
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
#define KFREE_VER_8192F \
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
#define KFREE_VER_8723B \
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
#define KFREE_VER_8812A \
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
#define KFREE_VER_8821A \
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
#define KFREE_VER_8814A \
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
#define KFREE_VER_8188F \
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
#define KFREE_VER_8197F \
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
#define KFREE_VER_8703B \
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
#define KFREE_VER_8710B \
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
#define KFREE_VER_8723D \
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
#define KFREE_VER_8822B \
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
#define KFREE_VER_8822C \
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
#define KFREE_VER_8821C \
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
#define KFREE_VER_8814B \
(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
/*PA Bias Calibration version*/
#define PABIASK_VERSION_8188E (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8192E (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8723B (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8812A (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8821A (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8814A (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8188F (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8197F (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8703B (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8710B (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8723D (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8822B (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VERSION_8821C (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
#define PABIASK_VER_8188E \
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define PABIASK_VER_8192E \
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define PABIASK_VER_8192F \
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define PABIASK_VER_8723B \
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define PABIASK_VER_8812A \
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define PABIASK_VER_8821A \
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define PABIASK_VER_8814A \
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define PABIASK_VER_8188F \
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define PABIASK_VER_8197F \
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define PABIASK_VER_8703B \
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define PABIASK_VER_8710B \
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define PABIASK_VER_8723D \
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define PABIASK_VER_8822B \
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define PABIASK_VER_8822C \
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define PABIASK_VER_8821C \
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define PABIASK_VER_8814B \
(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
#define HALRF_IQK_VER \
(dm->support_ic_type == ODM_RTL8188E) ? IQK_VER_8188E : \
(dm->support_ic_type == ODM_RTL8192E) ? IQK_VER_8192E : \
(dm->support_ic_type == ODM_RTL8192F) ? IQK_VER_8192F : \
(dm->support_ic_type == ODM_RTL8723B) ? IQK_VER_8723B : \
(dm->support_ic_type == ODM_RTL8812) ? IQK_VER_8812A : \
(dm->support_ic_type == ODM_RTL8821) ? IQK_VER_8821A : \
(dm->support_ic_type == ODM_RTL8814A) ? IQK_VER_8814A : \
(dm->support_ic_type == ODM_RTL8188F) ? IQK_VER_8188F : \
(dm->support_ic_type == ODM_RTL8197F) ? IQK_VER_8197F : \
(dm->support_ic_type == ODM_RTL8703B) ? IQK_VER_8703B : \
(dm->support_ic_type == ODM_RTL8710B) ? IQK_VER_8710B : \
(dm->support_ic_type == ODM_RTL8723D) ? IQK_VER_8723D : \
(dm->support_ic_type == ODM_RTL8822B) ? IQK_VER_8822B : \
(dm->support_ic_type == ODM_RTL8822C) ? IQK_VER_8822C : \
(dm->support_ic_type == ODM_RTL8821C) ? IQK_VER_8821C : \
(dm->support_ic_type == ODM_RTL8814B) ? IQK_VER_8814B : "unknown"
#define HALRF_LCK_VER \
(dm->support_ic_type == ODM_RTL8188E) ? LCK_VER_8188E : \
(dm->support_ic_type == ODM_RTL8192E) ? LCK_VER_8192E : \
(dm->support_ic_type == ODM_RTL8192F) ? LCK_VER_8192F : \
(dm->support_ic_type == ODM_RTL8723B) ? LCK_VER_8723B : \
(dm->support_ic_type == ODM_RTL8812) ? LCK_VER_8812A : \
(dm->support_ic_type == ODM_RTL8821) ? LCK_VER_8821A : \
(dm->support_ic_type == ODM_RTL8814A) ? LCK_VER_8814A : \
(dm->support_ic_type == ODM_RTL8188F) ? LCK_VER_8188F : \
(dm->support_ic_type == ODM_RTL8197F) ? LCK_VER_8197F : \
(dm->support_ic_type == ODM_RTL8703B) ? LCK_VER_8703B : \
(dm->support_ic_type == ODM_RTL8710B) ? LCK_VER_8710B : \
(dm->support_ic_type == ODM_RTL8723D) ? LCK_VER_8723D : \
(dm->support_ic_type == ODM_RTL8822B) ? LCK_VER_8822B : \
(dm->support_ic_type == ODM_RTL8822C) ? LCK_VER_8822C : \
(dm->support_ic_type == ODM_RTL8821C) ? LCK_VER_8821C : \
(dm->support_ic_type == ODM_RTL8814B) ? LCK_VER_8814B : "unknown"
#define HALRF_IQK_VER (dm->support_ic_type == ODM_RTL8188E)? IQK_VERSION_8188E :\
(dm->support_ic_type == ODM_RTL8192E)? IQK_VERSION_8192E :\
(dm->support_ic_type == ODM_RTL8723B)? IQK_VERSION_8723B :\
(dm->support_ic_type == ODM_RTL8812)? IQK_VERSION_8812A :\
(dm->support_ic_type == ODM_RTL8821)? IQK_VERSION_8821A :\
(dm->support_ic_type == ODM_RTL8814A)? IQK_VERSION_8814A :\
(dm->support_ic_type == ODM_RTL8188F)? IQK_VERSION_8188F :\
(dm->support_ic_type == ODM_RTL8197F)? IQK_VERSION_8197F :\
(dm->support_ic_type == ODM_RTL8703B)? IQK_VERSION_8703B :\
(dm->support_ic_type == ODM_RTL8710B)? IQK_VERSION_8710B :\
(dm->support_ic_type == ODM_RTL8723D)? IQK_VERSION_8723D :\
(dm->support_ic_type == ODM_RTL8822B)? IQK_VERSION_8822B :\
(dm->support_ic_type == ODM_RTL8821C)? IQK_VERSION_8821C :"unknown"
#define HALRF_POWRTRACKING_VER \
(dm->support_ic_type == ODM_RTL8188E) ? PWRTRK_VER_8188E : \
(dm->support_ic_type == ODM_RTL8192E) ? PWRTRK_VER_8192E : \
(dm->support_ic_type == ODM_RTL8192F) ? PWRTRK_VER_8192F : \
(dm->support_ic_type == ODM_RTL8723B) ? PWRTRK_VER_8723B : \
(dm->support_ic_type == ODM_RTL8812) ? PWRTRK_VER_8812A : \
(dm->support_ic_type == ODM_RTL8821) ? PWRTRK_VER_8821A : \
(dm->support_ic_type == ODM_RTL8814A) ? PWRTRK_VER_8814A : \
(dm->support_ic_type == ODM_RTL8188F) ? PWRTRK_VER_8188F : \
(dm->support_ic_type == ODM_RTL8197F) ? PWRTRK_VER_8197F : \
(dm->support_ic_type == ODM_RTL8703B) ? PWRTRK_VER_8703B : \
(dm->support_ic_type == ODM_RTL8710B) ? PWRTRK_VER_8710B : \
(dm->support_ic_type == ODM_RTL8723D) ? PWRTRK_VER_8723D : \
(dm->support_ic_type == ODM_RTL8822B) ? PWRTRK_VER_8822B : \
(dm->support_ic_type == ODM_RTL8822C) ? PWRTRK_VER_8822C : \
(dm->support_ic_type == ODM_RTL8821C) ? PWRTRK_VER_8821C : \
(dm->support_ic_type == ODM_RTL8814B) ? PWRTRK_VER_8814B : "unknown"
#define HALRF_DPK_VER \
(dm->support_ic_type == ODM_RTL8188E) ? DPK_VER_8188E : \
(dm->support_ic_type == ODM_RTL8192E) ? DPK_VER_8192E : \
(dm->support_ic_type == ODM_RTL8192F) ? DPK_VER_8192F : \
(dm->support_ic_type == ODM_RTL8723B) ? DPK_VER_8723B : \
(dm->support_ic_type == ODM_RTL8812) ? DPK_VER_8812A : \
(dm->support_ic_type == ODM_RTL8821) ? DPK_VER_8821A : \
(dm->support_ic_type == ODM_RTL8814A) ? DPK_VER_8814A : \
(dm->support_ic_type == ODM_RTL8188F) ? DPK_VER_8188F : \
(dm->support_ic_type == ODM_RTL8197F) ? DPK_VER_8197F : \
(dm->support_ic_type == ODM_RTL8198F) ? DPK_VER_8198F : \
(dm->support_ic_type == ODM_RTL8703B) ? DPK_VER_8703B : \
(dm->support_ic_type == ODM_RTL8710B) ? DPK_VER_8710B : \
(dm->support_ic_type == ODM_RTL8723D) ? DPK_VER_8723D : \
(dm->support_ic_type == ODM_RTL8822B) ? DPK_VER_8822B : \
(dm->support_ic_type == ODM_RTL8822C) ? DPK_VER_8822C : \
(dm->support_ic_type == ODM_RTL8821C) ? DPK_VER_8821C : \
(dm->support_ic_type == ODM_RTL8814B) ? DPK_VER_8814B : "unknown"
#define HALRF_LCK_VER (dm->support_ic_type == ODM_RTL8188E)? LCK_VERSION_8188E :\
(dm->support_ic_type == ODM_RTL8192E)? LCK_VERSION_8192E :\
(dm->support_ic_type == ODM_RTL8723B)? LCK_VERSION_8723B :\
(dm->support_ic_type == ODM_RTL8812)? LCK_VERSION_8812A :\
(dm->support_ic_type == ODM_RTL8821)? LCK_VERSION_8821A :\
(dm->support_ic_type == ODM_RTL8814A)? LCK_VERSION_8814A :\
(dm->support_ic_type == ODM_RTL8188F)? LCK_VERSION_8188F :\
(dm->support_ic_type == ODM_RTL8197F)? LCK_VERSION_8197F :\
(dm->support_ic_type == ODM_RTL8703B)? LCK_VERSION_8703B :\
(dm->support_ic_type == ODM_RTL8710B)? LCK_VERSION_8710B :\
(dm->support_ic_type == ODM_RTL8723D)? LCK_VERSION_8723D :\
(dm->support_ic_type == ODM_RTL8822B)? LCK_VERSION_8822B :\
(dm->support_ic_type == ODM_RTL8821C)? LCK_VERSION_8821C :"unknown"
#define HALRF_KFREE_VER \
(dm->support_ic_type == ODM_RTL8188E) ? KFREE_VER_8188E : \
(dm->support_ic_type == ODM_RTL8192E) ? KFREE_VER_8192E : \
(dm->support_ic_type == ODM_RTL8192F) ? KFREE_VER_8192F : \
(dm->support_ic_type == ODM_RTL8723B) ? KFREE_VER_8723B : \
(dm->support_ic_type == ODM_RTL8812) ? KFREE_VER_8812A : \
(dm->support_ic_type == ODM_RTL8821) ? KFREE_VER_8821A : \
(dm->support_ic_type == ODM_RTL8814A) ? KFREE_VER_8814A : \
(dm->support_ic_type == ODM_RTL8188F) ? KFREE_VER_8188F : \
(dm->support_ic_type == ODM_RTL8197F) ? KFREE_VER_8197F : \
(dm->support_ic_type == ODM_RTL8703B) ? KFREE_VER_8703B : \
(dm->support_ic_type == ODM_RTL8710B) ? KFREE_VER_8710B : \
(dm->support_ic_type == ODM_RTL8723D) ? KFREE_VER_8723D : \
(dm->support_ic_type == ODM_RTL8822B) ? KFREE_VER_8822B : \
(dm->support_ic_type == ODM_RTL8822C) ? KFREE_VER_8822C : \
(dm->support_ic_type == ODM_RTL8821C) ? KFREE_VER_8821C : \
(dm->support_ic_type == ODM_RTL8814B) ? KFREE_VER_8814B : "unknown"
#define HALRF_PABIASK_VER \
(dm->support_ic_type == ODM_RTL8188E) ? PABIASK_VER_8188E : \
(dm->support_ic_type == ODM_RTL8192E) ? PABIASK_VER_8192E : \
(dm->support_ic_type == ODM_RTL8192F) ? PABIASK_VER_8192F : \
(dm->support_ic_type == ODM_RTL8723B) ? PABIASK_VER_8723B : \
(dm->support_ic_type == ODM_RTL8812) ? PABIASK_VER_8812A : \
(dm->support_ic_type == ODM_RTL8821) ? PABIASK_VER_8821A : \
(dm->support_ic_type == ODM_RTL8814A) ? PABIASK_VER_8814A : \
(dm->support_ic_type == ODM_RTL8188F) ? PABIASK_VER_8188F : \
(dm->support_ic_type == ODM_RTL8197F) ? PABIASK_VER_8197F : \
(dm->support_ic_type == ODM_RTL8703B) ? PABIASK_VER_8703B : \
(dm->support_ic_type == ODM_RTL8710B) ? PABIASK_VER_8710B : \
(dm->support_ic_type == ODM_RTL8723D) ? PABIASK_VER_8723D : \
(dm->support_ic_type == ODM_RTL8822B) ? PABIASK_VER_8822B : \
(dm->support_ic_type == ODM_RTL8822C) ? PABIASK_VER_8822C : \
(dm->support_ic_type == ODM_RTL8821C) ? PABIASK_VER_8821C : \
(dm->support_ic_type == ODM_RTL8814B) ? PABIASK_VER_8814B : "unknown"
#define HALRF_POWRTRACKING_VER (dm->support_ic_type == ODM_RTL8188E)? POWERTRACKING_VERSION_8188E :\
(dm->support_ic_type == ODM_RTL8192E)? POWERTRACKING_VERSION_8192E :\
(dm->support_ic_type == ODM_RTL8723B)? POWERTRACKING_VERSION_8723B :\
(dm->support_ic_type == ODM_RTL8812)? POWERTRACKING_VERSION_8812A :\
(dm->support_ic_type == ODM_RTL8821)? POWERTRACKING_VERSION_8821A :\
(dm->support_ic_type == ODM_RTL8814A)? POWERTRACKING_VERSION_8814A :\
(dm->support_ic_type == ODM_RTL8188F)? POWERTRACKING_VERSION_8188F :\
(dm->support_ic_type == ODM_RTL8197F)? POWERTRACKING_VERSION_8197F :\
(dm->support_ic_type == ODM_RTL8703B)? POWERTRACKING_VERSION_8703B :\
(dm->support_ic_type == ODM_RTL8710B)? POWERTRACKING_VERSION_8710B :\
(dm->support_ic_type == ODM_RTL8723D)? POWERTRACKING_VERSION_8723D :\
(dm->support_ic_type == ODM_RTL8822B)? POWERTRACKING_VERSION_8822B :\
(dm->support_ic_type == ODM_RTL8821C)? POWERTRACKING_VERSION_8821C :"unknown"
#define HALRF_RFK_INIT_VER \
(dm->support_ic_type == ODM_RTL8822B) ? RFK_INIT_VER_8822B : \
(dm->support_ic_type == ODM_RTL8822C) ? RFK_INIT_VER_8822C : \
(dm->support_ic_type == ODM_RTL8198F) ? RFK_INIT_VER_8198F : \
(dm->support_ic_type == ODM_RTL8814B) ? RFK_INIT_VER_8814B : "unknown"
#define HALRF_DPK_VER (dm->support_ic_type == ODM_RTL8188E)? DPK_VERSION_8188E :\
(dm->support_ic_type == ODM_RTL8192E)? DPK_VERSION_8192E :\
(dm->support_ic_type == ODM_RTL8723B)? DPK_VERSION_8723B :\
(dm->support_ic_type == ODM_RTL8812)? DPK_VERSION_8812A :\
(dm->support_ic_type == ODM_RTL8821)? DPK_VERSION_8821A :\
(dm->support_ic_type == ODM_RTL8814A)? DPK_VERSION_8814A :\
(dm->support_ic_type == ODM_RTL8188F)? DPK_VERSION_8188F :\
(dm->support_ic_type == ODM_RTL8197F)? DPK_VERSION_8197F :\
(dm->support_ic_type == ODM_RTL8703B)? DPK_VERSION_8703B :\
(dm->support_ic_type == ODM_RTL8710B)? DPK_VERSION_8710B :\
(dm->support_ic_type == ODM_RTL8723D)? DPK_VERSION_8723D :\
(dm->support_ic_type == ODM_RTL8822B)? DPK_VERSION_8822B :\
(dm->support_ic_type == ODM_RTL8821C)? DPK_VERSION_8821C :"unknown"
#define HALRF_DACK_VER \
(dm->support_ic_type == ODM_RTL8822C) ? DACK_VER_8822C : "unknown"
#define HALRF_KFREE_VER (dm->support_ic_type == ODM_RTL8188E)? KFREE_VERSION_8188E :\
(dm->support_ic_type == ODM_RTL8192E)? KFREE_VERSION_8192E :\
(dm->support_ic_type == ODM_RTL8723B)? KFREE_VERSION_8723B :\
(dm->support_ic_type == ODM_RTL8812)? KFREE_VERSION_8812A :\
(dm->support_ic_type == ODM_RTL8821)? KFREE_VERSION_8821A :\
(dm->support_ic_type == ODM_RTL8814A)? KFREE_VERSION_8814A :\
(dm->support_ic_type == ODM_RTL8188F)? KFREE_VERSION_8188F :\
(dm->support_ic_type == ODM_RTL8197F)? KFREE_VERSION_8197F :\
(dm->support_ic_type == ODM_RTL8703B)? KFREE_VERSION_8703B :\
(dm->support_ic_type == ODM_RTL8710B)? KFREE_VERSION_8710B :\
(dm->support_ic_type == ODM_RTL8723D)? KFREE_VERSION_8723D :\
(dm->support_ic_type == ODM_RTL8822B)? KFREE_VERSION_8822B :\
(dm->support_ic_type == ODM_RTL8821C)? KFREE_VERSION_8821C :"unknown"
#define HALRF_PABIASK_VER (dm->support_ic_type == ODM_RTL8188E)? PABIASK_VERSION_8188E :\
(dm->support_ic_type == ODM_RTL8192E)? PABIASK_VERSION_8192E :\
(dm->support_ic_type == ODM_RTL8723B)? PABIASK_VERSION_8723B :\
(dm->support_ic_type == ODM_RTL8812)? PABIASK_VERSION_8812A :\
(dm->support_ic_type == ODM_RTL8821)? PABIASK_VERSION_8821A :\
(dm->support_ic_type == ODM_RTL8814A)? PABIASK_VERSION_8814A :\
(dm->support_ic_type == ODM_RTL8188F)? PABIASK_VERSION_8188F :\
(dm->support_ic_type == ODM_RTL8197F)? PABIASK_VERSION_8197F :\
(dm->support_ic_type == ODM_RTL8703B)? PABIASK_VERSION_8703B :\
(dm->support_ic_type == ODM_RTL8710B)? PABIASK_VERSION_8710B :\
(dm->support_ic_type == ODM_RTL8723D)? PABIASK_VERSION_8723D :\
(dm->support_ic_type == ODM_RTL8822B)? PABIASK_VERSION_8822B :\
(dm->support_ic_type == ODM_RTL8821C)? PABIASK_VERSION_8821C :"unknown"
#define IQK_THRESHOLD 8
#define DPK_THRESHOLD 4
/*===========================================================*/
#define IQK_THRESHOLD 8
#define DPK_THRESHOLD 4
#define HALRF_ABS(a,b) ((a>b) ? (a-b) : (b-a))
#define SN 100
/*@===========================================================*/
/*AGC RX High Power mode*/
/*===========================================================*/
#define lna_low_gain_1 0x64
#define lna_low_gain_2 0x5A
#define lna_low_gain_3 0x58
/*@===========================================================*/
#define lna_low_gain_1 0x64
#define lna_low_gain_2 0x5A
#define lna_low_gain_3 0x58
/*@============================================================*/
/*@ enumeration */
/*@============================================================*/
enum halrf_func_idx { /*F_XXX = PHYDM XXX function*/
RF00_PWR_TRK = 0,
RF01_IQK = 1,
RF02_LCK = 2,
RF03_DPK = 3,
RF04_TXGAPK = 4,
RF05_DACK = 5,
};
/*============================================================*/
/* enumeration */
/*============================================================*/
enum halrf_ability {
HAL_RF_TX_PWR_TRACK = BIT(0),
HAL_RF_IQK = BIT(1),
HAL_RF_LCK = BIT(2),
HAL_RF_DPK = BIT(3),
HAL_RF_TXGAPK = BIT(4)
HAL_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK),
HAL_RF_IQK = BIT(RF01_IQK),
HAL_RF_LCK = BIT(RF02_LCK),
HAL_RF_DPK = BIT(RF03_DPK),
HAL_RF_TXGAPK = BIT(RF04_TXGAPK),
HAL_RF_DACK = BIT(RF05_DACK)
};
enum halrf_dbg_comp {
DBG_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK),
DBG_RF_IQK = BIT(RF01_IQK),
DBG_RF_LCK = BIT(RF02_LCK),
DBG_RF_DPK = BIT(RF03_DPK),
DBG_RF_TXGAPK = BIT(RF04_TXGAPK),
DBG_RF_DACK = BIT(RF05_DACK),
DBG_RF_MP = BIT(29),
DBG_RF_TMP = BIT(30),
DBG_RF_INIT = BIT(31)
};
enum halrf_cmninfo_init {
HALRF_CMNINFO_ABILITY = 0,
HALRF_CMNINFO_DPK_EN = 1,
HALRF_CMNINFO_EEPROM_THERMAL_VALUE,
HALRF_CMNINFO_FW_VER,
HALRF_CMNINFO_RFK_FORBIDDEN,
HALRF_CMNINFO_IQK_SEGMENT,
HALRF_CMNINFO_RATE_INDEX,
HALRF_CMNINFO_PWT_TYPE,
HALRF_CMNINFO_MP_PSD_POINT,
HALRF_CMNINFO_MP_PSD_START_POINT,
HALRF_CMNINFO_MP_PSD_STOP_POINT,
@@ -268,188 +411,152 @@ enum halrf_cmninfo_init {
enum halrf_cmninfo_hook {
HALRF_CMNINFO_CON_TX,
HALRF_CMNINFO_SINGLE_TONE,
HALRF_CMNINFO_CARRIER_SUPPRESSION,
HALRF_CMNINFO_CARRIER_SUPPRESSION,
HALRF_CMNINFO_MP_RATE_INDEX
};
enum phydm_lna_set {
phydm_lna_disable = 0,
phydm_lna_enable = 1,
enum halrf_lna_set {
HALRF_LNA_DISABLE = 0,
HALRF_LNA_ENABLE = 1,
};
/*============================================================*/
/* structure */
/*============================================================*/
/*@============================================================*/
/*@ structure */
/*@============================================================*/
struct _hal_rf_ {
/*hook*/
u8 *test1;
u8 *test1;
/*update*/
u32 rf_supportability;
u32 rf_supportability;
u8 eeprom_thermal;
u8 dpk_en; /*Enable Function DPK OFF/ON = 0/1*/
boolean dpk_done;
u32 fw_ver;
u8 eeprom_thermal;
u8 dpk_en; /*Enable Function DPK OFF/ON = 0/1*/
boolean dpk_done;
u64 dpk_progressing_time;
u32 fw_ver;
boolean *is_con_tx;
boolean *is_single_tone;
boolean *is_carrier_suppresion;
boolean *is_con_tx;
boolean *is_single_tone;
boolean *is_carrier_suppresion;
boolean is_dpk_in_progress;
u8 *mp_rate_index;
u32 p_rate_index;
u8 *mp_rate_index;
u32 p_rate_index;
u8 pwt_type;
u32 rf_dbg_comp;
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
struct _halrf_psd_data halrf_psd_data;
struct _halrf_psd_data halrf_psd_data;
#endif
};
/*============================================================*/
/* function prototype */
/*============================================================*/
/*@============================================================*/
/*@ function prototype */
/*@============================================================*/
void halrf_basic_profile(
void *dm_void,
u32 *_used,
char *output,
u32 *_out_len
);
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
void halrf_iqk_info_dump(
void *dm_void,
u32 *_used,
char *output,
u32 *_out_len
);
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
void halrf_iqk_info_dump(void *dm_void, u32 *_used, char *output,
u32 *_out_len);
void
halrf_iqk_hwtx_check(
void *dm_void,
boolean is_check
);
void halrf_iqk_hwtx_check(void *dm_void, boolean is_check);
#endif
u8
halrf_match_iqk_version(
void *dm_void
);
u8 halrf_match_iqk_version(void *dm_void);
void
halrf_support_ability_debug(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len
);
void halrf_support_ability_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void
halrf_cmn_info_init(
void *dm_void,
enum halrf_cmninfo_init cmn_info,
u32 value
);
void halrf_cmn_info_init(void *dm_void, enum halrf_cmninfo_init cmn_info,
u32 value);
void
halrf_cmn_info_hook(
void *dm_void,
u32 cmn_info,
void *value
);
void halrf_cmn_info_hook(void *dm_void, enum halrf_cmninfo_hook cmn_info,
void *value);
void
halrf_cmn_info_set(
void *dm_void,
u32 cmn_info,
u64 value
);
void halrf_cmn_info_set(void *dm_void, u32 cmn_info, u64 value);
u64
halrf_cmn_info_get(
void *dm_void,
u32 cmn_info
);
u64 halrf_cmn_info_get(void *dm_void, u32 cmn_info);
void
halrf_watchdog(
void *dm_void
);
void halrf_watchdog(void *dm_void);
void
halrf_supportability_init(
void *dm_void
);
void halrf_supportability_init(void *dm_void);
void
halrf_init(
void *dm_void
);
void halrf_init(void *dm_void);
void
halrf_iqk_trigger(
void *dm_void,
boolean is_recovery
);
void halrf_iqk_trigger(void *dm_void, boolean is_recovery);
void
halrf_segment_iqk_trigger(
void *dm_void,
boolean clear,
boolean segment_iqk
);
void halrf_segment_iqk_trigger(void *dm_void, boolean clear,
boolean segment_iqk);
void
halrf_lck_trigger(
void *dm_void
);
void halrf_lck_trigger(void *dm_void);
void
halrf_iqk_debug(
void *dm_void,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
);
void halrf_iqk_debug(void *dm_void, u32 *const dm_value, u32 *_used,
char *output, u32 *_out_len);
void
phydm_get_iqk_cfir(
void *dm_void,
u8 idx,
u8 path,
boolean debug
);
void phydm_get_iqk_cfir(void *dm_void, u8 idx, u8 path, boolean debug);
void
halrf_iqk_xym_read(
void *dm_void,
u8 path,
u8 xym_type
);
void halrf_iqk_xym_read(void *dm_void, u8 path, u8 xym_type);
void
halrf_rf_lna_setting(
void *dm_void,
enum phydm_lna_set type
);
void halrf_rf_lna_setting(void *dm_void, enum halrf_lna_set type);
void halrf_do_imr_test(void *dm_void, u8 data);
void
halrf_do_imr_test(
void *dm_void,
u8 data
);
u32 halrf_psd_log2base(u32 val);
u32
halrf_psd_log2base(
u32 val
);
void halrf_dpk_trigger(void *dm_void);
u8 halrf_dpk_result_check(void *dm_void);
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
void halrf_iqk_dbg(void *dm_void);
#endif
void halrf_dpk_sram_read(void *dm_void);
void halrf_dpk_enable_disable(void *dm_void);
void halrf_dpk_track(void *dm_void);
void halrf_dpk_reload(void *dm_void);
/*Global function*/
void halrf_reload_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num);
void halrf_reload_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num,
u8 ss);
void halrf_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num);
void halrf_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num, u8 ss);
void halrf_mode(void *dm_void, u32 *i_value, u32 *q_value);
boolean halrf_compare(void *dm_void, u32 value);
u32 halrf_delta(void *dm_void, u32 v1, u32 v2);
void halrf_minmax_compare(void *dm_void, u32 value, u32 *min, u32 *max);
void halrf_b_sort(void *dm_void, u32 *iv, u32 *qv);
void halrf_bubble(void *dm_void, u32 *v1, u32 *v2);
void halrf_swap(void *dm_void, u32 *v1, u32 *v2);
enum hal_status
halrf_config_rfk_with_header_file(void *dm_void, u32 config_type);
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
void halrf_iqk_dbg(void *dm_void);
#endif
void halrf_tssi_init(void *dm_void);
void halrf_do_tssi(void *dm_void);
void halrf_set_tssi_value(void *dm_void, u32 tssi_value);
u32 halrf_query_tssi_value(void *dm_void);
#endif /*__HALRF_H__*/

261
hal/phydm/halrf/halrf_debug.c Normal file
View File

@@ -0,0 +1,261 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*@************************************************************
* include files
* ************************************************************
*/
#include "mp_precomp.h"
#include "phydm_precomp.h"
void halrf_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len)
{
#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
/* HAL RF version List */
PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n",
"% HAL RF version %");
PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
"Power Tracking", HALRF_POWRTRACKING_VER);
PDM_SNPF(out_len, used, output + used, out_len - used,
" %-35s: %s %s\n", "IQK",
(dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW" :
HALRF_IQK_VER,
(halrf_match_iqk_version(dm_void)) ? "(match)" : "(mismatch)");
PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
"LCK", HALRF_LCK_VER);
PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
"DPK", HALRF_DPK_VER);
PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
"KFREE", HALRF_KFREE_VER);
PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
"TX 2G Current Calibration", HALRF_PABIASK_VER);
PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
"RFK Init. Parameter", HALRF_RFK_INIT_VER);
*_used = used;
*_out_len = out_len;
#endif
}
void halrf_debug_trace(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _hal_rf_ *rf = &dm->rf_table;
u32 one = 1;
u32 used = *_used;
u32 out_len = *_out_len;
u32 rf_var[10] = {0};
u8 i;
for (i = 0; i < 5; i++)
if (input[i + 1])
PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &rf_var[i]);
if (rf_var[0] == 100) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"\n[DBG MSG] RF Selection\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"00. (( %s ))TX_PWR_TRACK\n",
((rf->rf_dbg_comp & DBG_RF_TX_PWR_TRACK) ? ("V") :
(".")));
PDM_SNPF(out_len, used, output + used, out_len - used,
"01. (( %s ))IQK\n",
((rf->rf_dbg_comp & DBG_RF_IQK) ? ("V") : (".")));
PDM_SNPF(out_len, used, output + used, out_len - used,
"02. (( %s ))LCK\n",
((rf->rf_dbg_comp & DBG_RF_LCK) ? ("V") : (".")));
PDM_SNPF(out_len, used, output + used, out_len - used,
"03. (( %s ))DPK\n",
((rf->rf_dbg_comp & DBG_RF_DPK) ? ("V") : (".")));
PDM_SNPF(out_len, used, output + used, out_len - used,
"04. (( %s ))TXGAPK\n",
((rf->rf_dbg_comp & DBG_RF_TXGAPK) ? ("V") : (".")));
PDM_SNPF(out_len, used, output + used, out_len - used,
"29. (( %s ))MP\n",
((rf->rf_dbg_comp & DBG_RF_MP) ? ("V") : (".")));
PDM_SNPF(out_len, used, output + used, out_len - used,
"30. (( %s ))TMP\n",
((rf->rf_dbg_comp & DBG_RF_TMP) ? ("V") : (".")));
PDM_SNPF(out_len, used, output + used, out_len - used,
"31. (( %s ))INIT\n",
((rf->rf_dbg_comp & DBG_RF_INIT) ? ("V") : (".")));
} else if (rf_var[0] == 101) {
rf->rf_dbg_comp = 0;
PDM_SNPF(out_len, used, output + used, out_len - used,
"Disable all DBG COMP\n");
} else {
if (rf_var[1] == 1) /*enable*/
rf->rf_dbg_comp |= (one << rf_var[0]);
else if (rf_var[1] == 2) /*disable*/
rf->rf_dbg_comp &= ~(one << rf_var[0]);
}
PDM_SNPF(out_len, used, output + used, out_len - used,
"\nCurr-RF_Dbg_Comp = 0x%x\n", rf->rf_dbg_comp);
*_used = used;
*_out_len = out_len;
}
struct halrf_command {
char name[16];
u8 id;
};
enum halrf_CMD_ID {
HALRF_HELP,
HALRF_SUPPORTABILITY,
HALRF_DBG_COMP,
HALRF_PROFILE,
HALRF_IQK_INFO,
HALRF_IQK,
HALRF_IQK_DEBUG,
};
struct halrf_command halrf_cmd_ary[] = {
{"-h", HALRF_HELP},
{"ability", HALRF_SUPPORTABILITY},
{"dbg", HALRF_DBG_COMP},
{"profile", HALRF_PROFILE},
{"iqk_info", HALRF_IQK_INFO},
{"iqk", HALRF_IQK},
{"iqk_dbg", HALRF_IQK_DEBUG},
};
void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len, u32 input_num)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
u8 id = 0;
u32 rf_var[10] = {0};
u32 i, input_idx = 0;
u32 halrf_ary_size =
sizeof(halrf_cmd_ary) / sizeof(struct halrf_command);
u32 used = *_used;
u32 out_len = *_out_len;
/* Parsing Cmd ID */
for (i = 0; i < halrf_ary_size; i++) {
if (strcmp(halrf_cmd_ary[i].name, input[1]) == 0) {
id = halrf_cmd_ary[i].id;
break;
}
}
if (i == halrf_ary_size) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"RF Cmd not found\n");
return;
}
switch (id) {
case HALRF_HELP:
PDM_SNPF(out_len, used, output + used, out_len - used,
"RF cmd ==>\n");
for (i = 0; i < halrf_ary_size - 1; i++) {
PDM_SNPF(out_len, used, output + used, out_len - used,
" %-5d: %s\n", i, halrf_cmd_ary[i + 1].name);
}
break;
case HALRF_SUPPORTABILITY:
halrf_support_ability_debug(dm, &input[0], &used, output,
&out_len);
break;
case HALRF_DBG_COMP:
halrf_debug_trace(dm, &input[0], &used, output, &out_len);
break;
case HALRF_PROFILE:
halrf_basic_profile(dm, &used, output, &out_len);
break;
case HALRF_IQK_INFO:
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
halrf_iqk_info_dump(dm, &used, output, &out_len);
#endif
break;
case HALRF_IQK:
PDM_SNPF(out_len, used, output + used, out_len - used,
"TRX IQK Trigger\n");
halrf_iqk_trigger(dm, false);
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
halrf_iqk_info_dump(dm, &used, output, &out_len);
#endif
break;
case HALRF_IQK_DEBUG:
for (i = 0; i < 5; i++) {
if (input[i + 1]) {
PHYDM_SSCANF(input[i + 2], DCMD_HEX,
&rf_var[i]);
input_idx++;
}
}
if (input_idx >= 1) {
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C))
halrf_iqk_debug(dm, (u32 *)rf_var, &used,
output, &out_len);
#endif
}
break;
default:
break;
}
*_used = used;
*_out_len = out_len;
#endif
}
void halrf_init_debug_setting(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _hal_rf_ *rf = &dm->rf_table;
rf->rf_dbg_comp =
#if DBG
#if 0
/*DBG_RF_TX_PWR_TRACK |*/
/*DBG_RF_IQK | */
/*DBG_RF_LCK | */
/*DBG_RF_DPK | */
/*DBG_RF_DACK | */
/*DBG_RF_TXGAPK | */
/*DBG_RF_MP | */
/*DBG_RF_TMP | */
/*DBG_RF_INIT | */
#endif
#endif
0;
}

123
hal/phydm/halrf/halrf_debug.h Normal file
View File

@@ -0,0 +1,123 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_DEBUG_H__
#define __HALRF_DEBUG_H__
/*@============================================================*/
/*@include files*/
/*@============================================================*/
/*@============================================================*/
/*@Definition */
/*@============================================================*/
#if DBG
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define RF_DBG(dm, comp, fmt, args...) \
do { \
if ((comp) & dm->rf_table.rf_dbg_comp) { \
pr_debug("[RF] "); \
RT_PRINTK(fmt, ##args); \
} \
} while (0)
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
static __inline void RF_DBG(PDM_ODM_T dm, int comp, char *fmt, ...)
{
RT_STATUS rt_status;
va_list args;
char buf[PRINT_MAX_SIZE] = {0};
if ((comp & dm->rf_table.rf_dbg_comp) == 0)
return;
if (fmt == NULL)
return;
va_start(args, fmt);
rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
va_end(args);
if (rt_status != RT_STATUS_SUCCESS) {
DbgPrint("Failed (%d) to print message to buffer\n", rt_status);
return;
}
DbgPrint("[RF] %s", buf);
}
#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
#define RF_DBG(dm, comp, fmt, args...) \
do { \
if ((comp) & dm->rf_table.rf_dbg_comp) { \
RT_DEBUG(COMP_PHYDM, DBG_DMESG, "[RF] " fmt, ##args); \
} \
} while (0)
#else
#define RF_DBG(dm, comp, fmt, args...) \
do { \
struct dm_struct *__dm = dm; \
if ((comp) & __dm->rf_table.rf_dbg_comp) { \
RT_TRACE(((struct rtl_priv *)__dm->adapter), \
COMP_PHYDM, DBG_DMESG, "[RF] " fmt, ##args); \
} \
} while (0)
#endif
#else /*#if DBG*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
static __inline void RF_DBG(struct dm_struct *dm, int comp, char *fmt, ...)
{
}
#else
#define RF_DBG(dm, comp, fmt, args...)
#endif
#endif /*#if DBG*/
/*@============================================================*/
/*@ enumeration */
/*@============================================================*/
/*@============================================================*/
/*@ structure */
/*@============================================================*/
/*@============================================================*/
/*@ function prototype */
/*@============================================================*/
void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len, u32 input_num);
void halrf_init_debug_setting(void *dm_void);
#endif /*__HALRF_H__*/

86
hal/phydm/halrf/halrf_dpk.h Normal file
View File

@@ -0,0 +1,86 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_DPK_H__
#define __HALRF_DPK_H__
/*@--------------------------Define Parameters-------------------------------*/
#define GAIN_LOSS 1
#define DO_DPK 2
#define DPK_ON 3
#define DPK_LOK 4
#define DPK_TXK 5
#define DAGC 4
#define LOSS_CHK 0
#define GAIN_CHK 1
#define PAS_READ 2
#define AVG_THERMAL_NUM 8
#define AVG_THERMAL_NUM_DPK 8
#define THERMAL_DPK_AVG_NUM 4
/*@---------------------------End Define Parameters---------------------------*/
struct dm_dpk_info {
boolean is_dpk_enable;
boolean is_dpk_pwr_on;
boolean is_dpk_by_channel;
u16 dpk_path_ok;
/*@BIT(15)~BIT(12) : 5G reserved, BIT(11)~BIT(8) 5G_S3~5G_S0*/
/*@BIT(7)~BIT(4) : 2G reserved, BIT(3)~BIT(0) 2G_S3~2G_S0*/
u8 thermal_dpk;
u8 thermal_dpk_avg[AVG_THERMAL_NUM_DPK];
u8 thermal_dpk_avg_index;
#if (RTL8822C_SUPPORT == 1)
u8 result[2][1]; /*path/group*/
u8 tx_agc[2][1]; /*path/group*/
u32 coef[2][1][20]; /*path/group/MDPD coefficient*/
#endif
#if (RTL8198F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
/*2G DPK data*/
u8 dpk_result[4][3]; /*path/group*/
u8 pwsf_2g[4][3]; /*path/group*/
u32 lut_2g_even[4][3][64]; /*path/group/LUT data*/
u32 lut_2g_odd[4][3][64]; /*path/group/LUT data*/
#endif
#if (RTL8195B_SUPPORT == 1)
/*2G DPK data*/
u8 dpk_2g_result[1][3]; /*path/group*/
u8 pwsf_2g[1][3]; /*path/group*/
u32 lut_2g_even[1][3][16]; /*path/group/LUT data*/
u32 lut_2g_odd[1][3][16]; /*path/group/LUT data*/
/*5G DPK data*/
u8 dpk_5g_result[1][6]; /*path/group*/
u8 pwsf_5g[1][6]; /*path/group*/
u32 lut_5g_even[1][6][16]; /*path/group/LUT data*/
u32 lut_5g_odd[1][6][16]; /*path/group/LUT data*/
#endif
};
#endif /*__HALRF_DPK_H__*/

12
hal/phydm/halrf/halrf_features.h
View File

@@ -23,21 +23,21 @@
*
*****************************************************************************/
#ifndef __HALRF_FEATURES_H__
#define __HALRF_FEATURES
#ifndef __HALRF_FEATURES_H__
#define __HALRF_FEATURES_H__
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define CONFIG_HALRF_POWERTRACKING 1
#define CONFIG_HALRF_POWERTRACKING 1
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define CONFIG_HALRF_POWERTRACKING 1
#define CONFIG_HALRF_POWERTRACKING 1
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define CONFIG_HALRF_POWERTRACKING 1
#define CONFIG_HALRF_POWERTRACKING 1
#endif
#endif
#endif /*#ifndef __HALRF_FEATURES_H__*/

110
hal/phydm/halrf/halrf_iqk.h
View File

@@ -23,63 +23,81 @@
*
*****************************************************************************/
#ifndef __PHYDMIQK_H__
#define __PHYDMIQK_H__
#ifndef __HALRF_IQK_H__
#define __HALRF_IQK_H__
/*--------------------------Define Parameters-------------------------------*/
#define LOK_delay 1
#define WBIQK_delay 10
#define TX_IQK 0
#define RX_IQK 1
#define TXIQK 0
#define RXIQK1 1
#define RXIQK2 2
/*@--------------------------Define Parameters-------------------------------*/
#define LOK_delay 1
#define WBIQK_delay 10
#define TX_IQK 0
#define RX_IQK 1
#define TXIQK 0
#define RXIQK1 1
#define RXIQK2 2
#define kcount_limit_80m 2
#define kcount_limit_others 4
#define rxiqk_gs_limit 10
#define TXWBIQK_EN 1
#define RXWBIQK_EN 1
#define NUM 4
/*@-----------------------End Define Parameters-----------------------*/
#define NUM 4
/*---------------------------End Define Parameters-------------------------------*/
struct dm_dack_info {
u32 ic_a;
u32 qc_a;
u32 ic_b;
u32 qc_b;
};
struct dm_iqk_info {
boolean lok_fail[NUM];
boolean iqk_fail[2][NUM];
u32 iqc_matrix[2][NUM];
u8 iqk_times;
u32 rf_reg18;
u32 lna_idx;
u8 rxiqk_step;
u8 tmp1bcc;
u8 kcount;
u8 rfk_ing; /*bit0:IQKing, bit1:LCKing, bit2:DPKing*/
boolean rfk_forbidden;
#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
u32 iqk_channel[2];
boolean iqk_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */
u32 iqk_cfir_real[3][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/ /*channel index = 2 is just for debug*/
u32 iqk_cfir_imag[3][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/ /*channel index = 2 is just for debug*/
u8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */
u8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */
u8 rxiqk_fail_code[2][4]; /* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */
u32 lok_idac[2][4]; /*channel / path*/
u16 rxiqk_agc[2][4]; /*channel / path*/
u32 bypass_iqk[2][4]; /*channel / 0xc94/0xe94*/
u32 txgap_result[8]; /*txagpK result */
u32 tmp_gntwl;
boolean is_btg;
boolean isbnd;
boolean lok_fail[NUM];
boolean iqk_fail[2][NUM];
u32 iqc_matrix[2][NUM];
u8 iqk_times;
u32 rf_reg18;
u32 rf_reg08;
u32 lna_idx;
u8 iqk_step;
u8 rxiqk_step;
u8 tmp1bcc;
u8 txgain;
u8 kcount;
u8 rfk_ing; /*bit0:IQKing, bit1:LCKing, bit2:DPKing*/
boolean rfk_forbidden;
u8 rxbb;
#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
u32 iqk_channel[2];
boolean iqk_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */
/*channel / path / TRX(TX:0, RX:1) / CFIR_real*/
/*channel index = 2 is just for debug*/
u32 iqk_cfir_real[3][4][2][8];
/*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
/*channel index = 2 is just for debug*/
u32 iqk_cfir_imag[3][4][2][8];
u8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */
u8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */
/* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */
u8 rxiqk_fail_code[2][4];
u32 lok_idac[2][4]; /*channel / path*/
u16 rxiqk_agc[2][4]; /*channel / path*/
u32 bypass_iqk[2][4]; /*channel / 0xc94/0xe94*/
u32 txgap_result[8]; /*txagpK result */
u32 tmp_gntwl;
boolean is_btg;
boolean isbnd;
boolean is_reload;
boolean segment_iqk;
boolean is_hwtx;
boolean xym_read;
boolean xym_read;
boolean trximr_enable;
u32 rx_xym[2][10];
u32 tx_xym[2][10];
u32 gs1_xym[2][6];
u32 gs2_xym[2][6];
u32 rxk1_xym[2][6];
u32 rx_xym[2][10];
u32 tx_xym[2][10];
u32 gs1_xym[2][6];
u32 gs2_xym[2][6];
u32 rxk1_xym[2][6];
#endif
};
#endif
#endif /*__HALRF_IQK_H__*/

1380
hal/phydm/halrf/halrf_kfree.c
View File

File diff suppressed because it is too large Load Diff

137
hal/phydm/halrf/halrf_kfree.h
View File

@@ -23,66 +23,70 @@
*
*****************************************************************************/
#ifndef __HALRF_KFREE_H__
#define __HALRF_KFREE_H__
#ifndef __PHYDMKFREE_H__
#define __PHYDKFREE_H__
#define KFREE_VERSION "1.0"
#define KFREE_VERSION "1.0"
#define KFREE_BAND_NUM 6
#define KFREE_BAND_NUM 6
#define KFREE_CH_NUM 3
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
#define BB_GAIN_NUM 6
#define BB_GAIN_NUM 6
#endif
#define KFREE_FLAG_ON BIT(0)
#define KFREE_FLAG_THERMAL_K_ON BIT(1)
#define KFREE_FLAG_ON BIT(0)
#define KFREE_FLAG_THERMAL_K_ON BIT(1)
#define KFREE_FLAG_ON_2G BIT(2)
#define KFREE_FLAG_ON_5G BIT(3)
#define KFREE_FLAG_ON_2G BIT(2)
#define KFREE_FLAG_ON_5G BIT(3)
#define PA_BIAS_FLAG_ON BIT(4)
#define PA_BIAS_FLAG_ON BIT(4)
#define PPG_THERMAL_OFFSET_8821C 0x1EF
#define PPG_BB_GAIN_2G_TXAB_OFFSET_8821C 0x1EE
#define PPG_BB_GAIN_5GL1_TXA_OFFSET_8821C 0x1EC
#define PPG_BB_GAIN_5GL2_TXA_OFFSET_8821C 0x1E8
#define PPG_BB_GAIN_5GM1_TXA_OFFSET_8821C 0x1E4
#define PPG_BB_GAIN_5GM2_TXA_OFFSET_8821C 0x1E0
#define PPG_BB_GAIN_5GH1_TXA_OFFSET_8821C 0x1DC
#define PPG_THERMAL_OFFSET_98F 0x50
#define PPG_2GM_TXAB_98F 0x51
#define PPG_2GM_TXCD_98F 0x52
#define PPG_2GL_TXAB_98F 0x53
#define PPG_2GL_TXCD_98F 0x54
#define PPG_5GH_TXAB_98F 0x55
#define PPG_5GH_TXCD_98F 0x56
#define PPG_THERMAL_OFFSET_21C 0x1EF
#define PPG_2G_TXAB_21C 0x1EE
#define PPG_5GL1_TXA_21C 0x1EC
#define PPG_5GL2_TXA_21C 0x1E8
#define PPG_5GM1_TXA_21C 0x1E4
#define PPG_5GM2_TXA_21C 0x1E0
#define PPG_5GH1_TXA_21C 0x1DC
#define PPG_THERMAL_OFFSET_22B 0x3EF
#define PPG_2G_TXAB_22B 0x3EE
#define PPG_2G_TXCD_22B 0x3ED
#define PPG_5GL1_TXA_22B 0x3EC
#define PPG_5GL1_TXB_22B 0x3EB
#define PPG_5GL1_TXC_22B 0x3EA
#define PPG_5GL1_TXD_22B 0x3E9
#define PPG_5GL2_TXA_22B 0x3E8
#define PPG_5GL2_TXB_22B 0x3E7
#define PPG_5GL2_TXC_22B 0x3E6
#define PPG_5GL2_TXD_22B 0x3E5
#define PPG_5GM1_TXA_22B 0x3E4
#define PPG_5GM1_TXB_22B 0x3E3
#define PPG_5GM1_TXC_22B 0x3E2
#define PPG_5GM1_TXD_22B 0x3E1
#define PPG_5GM2_TXA_22B 0x3E0
#define PPG_5GM2_TXB_22B 0x3DF
#define PPG_5GM2_TXC_22B 0x3DE
#define PPG_5GM2_TXD_22B 0x3DD
#define PPG_5GH1_TXA_22B 0x3DC
#define PPG_5GH1_TXB_22B 0x3DB
#define PPG_5GH1_TXC_22B 0x3DA
#define PPG_5GH1_TXD_22B 0x3D9
#define PPG_THERMAL_OFFSET 0x3EF
#define PPG_BB_GAIN_2G_TXAB_OFFSET 0x3EE
#define PPG_BB_GAIN_2G_TXCD_OFFSET 0x3ED
#define PPG_BB_GAIN_5GL1_TXA_OFFSET 0x3EC
#define PPG_BB_GAIN_5GL1_TXB_OFFSET 0x3EB
#define PPG_BB_GAIN_5GL1_TXC_OFFSET 0x3EA
#define PPG_BB_GAIN_5GL1_TXD_OFFSET 0x3E9
#define PPG_BB_GAIN_5GL2_TXA_OFFSET 0x3E8
#define PPG_BB_GAIN_5GL2_TXB_OFFSET 0x3E7
#define PPG_BB_GAIN_5GL2_TXC_OFFSET 0x3E6
#define PPG_BB_GAIN_5GL2_TXD_OFFSET 0x3E5
#define PPG_BB_GAIN_5GM1_TXA_OFFSET 0x3E4
#define PPG_BB_GAIN_5GM1_TXB_OFFSET 0x3E3
#define PPG_BB_GAIN_5GM1_TXC_OFFSET 0x3E2
#define PPG_BB_GAIN_5GM1_TXD_OFFSET 0x3E1
#define PPG_BB_GAIN_5GM2_TXA_OFFSET 0x3E0
#define PPG_BB_GAIN_5GM2_TXB_OFFSET 0x3DF
#define PPG_BB_GAIN_5GM2_TXC_OFFSET 0x3DE
#define PPG_BB_GAIN_5GM2_TXD_OFFSET 0x3DD
#define PPG_BB_GAIN_5GH1_TXA_OFFSET 0x3DC
#define PPG_BB_GAIN_5GH1_TXB_OFFSET 0x3DB
#define PPG_BB_GAIN_5GH1_TXC_OFFSET 0x3DA
#define PPG_BB_GAIN_5GH1_TXD_OFFSET 0x3D9
#define PPG_PA_BIAS_2G_TXA_OFFSET 0x3D5
#define PPG_PA_BIAS_2G_TXB_OFFSET 0x3D6
#define PPG_PABIAS_2GA_22B 0x3D5
#define PPG_PABIAS_2GB_22B 0x3D6
struct odm_power_trim_data {
u8 flag;
@@ -91,8 +95,6 @@ struct odm_power_trim_data {
s8 thermal;
};
enum phydm_kfree_channeltosw {
PHYDM_2G = 0,
PHYDM_5GLB1 = 1,
@@ -102,41 +104,16 @@ enum phydm_kfree_channeltosw {
PHYDM_5GHB = 5,
};
void phydm_get_thermal_trim_offset(void *dm_void);
void phydm_get_power_trim_offset(void *dm_void);
void
phydm_get_thermal_trim_offset(
void *dm_void
);
void phydm_get_pa_bias_offset(void *dm_void);
void
phydm_get_power_trim_offset(
void *dm_void
);
s8 phydm_get_thermal_offset(void *dm_void);
void
phydm_get_pa_bias_offset(
void *dm_void
);
void phydm_clear_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data);
s8
phydm_get_thermal_offset(
void *dm_void
);
void phydm_config_kfree(void *dm_void, u8 channel_to_sw);
void
phydm_clear_kfree_to_rf(
void *dm_void,
u8 e_rf_path,
u8 data
);
void
phydm_config_kfree(
void *dm_void,
u8 channel_to_sw
);
#endif
#endif /*__HALRF_KFREE_H__*/

101
hal/phydm/halrf/halrf_powertracking.c
View File

@@ -23,58 +23,55 @@
*
*****************************************************************************/
/* ************************************************************
/*@************************************************************
* include files
* ************************************************************ */
* ************************************************************
*/
#include "mp_precomp.h"
#include "phydm_precomp.h"
boolean
odm_check_power_status(
void *dm_void
)
odm_check_power_status(void *dm_void)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct dm_struct *dm = (struct dm_struct *)dm_void;
PADAPTER adapter = (PADAPTER)dm->adapter;
struct dm_struct *dm = (struct dm_struct *)dm_void;
PADAPTER *adapter = dm->adapter;
RT_RF_POWER_STATE rt_state;
MGNT_INFO *mgnt_info = &adapter->MgntInfo;
RT_RF_POWER_STATE rt_state;
MGNT_INFO *mgnt_info = &((PADAPTER)adapter)->MgntInfo;
/* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */
if (mgnt_info->init_adpt_in_progress == true) {
PHYDM_DBG(dm, ODM_COMP_INIT, "check_pow_status Return true, due to initadapter\n");
return true;
RF_DBG(dm, DBG_RF_INIT,
"check_pow_status Return true, due to initadapter\n");
return true;
}
/* */
/* 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. */
/* */
adapter->HalFunc.GetHwRegHandler(adapter, HW_VAR_RF_STATE, (u8 *)(&rt_state));
if (adapter->bDriverStopped || adapter->bDriverIsGoingToPnpSetPowerSleep || rt_state == eRfOff) {
PHYDM_DBG(dm, ODM_COMP_INIT, "check_pow_status Return false, due to %d/%d/%d\n",
adapter->bDriverStopped, adapter->bDriverIsGoingToPnpSetPowerSleep, rt_state);
return false;
/*
* 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.
*/
((PADAPTER)adapter)->HalFunc.GetHwRegHandler((PADAPTER)adapter, HW_VAR_RF_STATE, (u8 *)(&rt_state));
if (((PADAPTER)adapter)->bDriverStopped || ((PADAPTER)adapter)->bDriverIsGoingToPnpSetPowerSleep || rt_state == eRfOff) {
RF_DBG(dm, DBG_RF_INIT,
"check_pow_status Return false, due to %d/%d/%d\n",
((PADAPTER)adapter)->bDriverStopped,
((PADAPTER)adapter)->bDriverIsGoingToPnpSetPowerSleep,
rt_state);
return false;
}
#endif
return true;
return true;
}
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
void
halrf_update_pwr_track(
void *dm_void,
u8 rate
)
void halrf_update_pwr_track(void *dm_void, u8 rate)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
u8 path_idx = 0;
u8 path_idx = 0;
#endif
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "Pwr Track Get rate=0x%x\n", rate);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Pwr Track Get rate=0x%x\n", rate);
dm->tx_rate = rate;
@@ -113,47 +110,43 @@ halrf_update_pwr_track(
odm_schedule_work_item(&dm->ra_rpt_workitem);
#endif
#endif
}
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void
halrf_update_init_rate_work_item_callback(
void *context
)
void halrf_update_init_rate_work_item_callback(
void *context)
{
void *adapter = (void *)context;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
u8 p = 0;
void *adapter = (void *)context;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
u8 p = 0;
if (dm->support_ic_type == ODM_RTL8821) {
#if (RTL8821A_SUPPORT == 1)
odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);
/**/
#endif
} else if (dm->support_ic_type == ODM_RTL8812) {
for (p = RF_PATH_A; p < MAX_PATH_NUM_8812A; p++) { /*DOn't know how to include &c*/
#if (RTL8812A_SUPPORT == 1)
/*Don't know how to include &c*/
for (p = RF_PATH_A; p < MAX_PATH_NUM_8812A; p++)
odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, p, 0);
/**/
}
#endif
} else if (dm->support_ic_type == ODM_RTL8723B) {
#if (RTL8723B_SUPPORT == 1)
odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);
/**/
#endif
} else if (dm->support_ic_type == ODM_RTL8192E) {
for (p = RF_PATH_A; p < MAX_PATH_NUM_8192E; p++) { /*DOn't know how to include &c*/
#if (RTL8192E_SUPPORT == 1)
/*Don't know how to include &c*/
for (p = RF_PATH_A; p < MAX_PATH_NUM_8192E; p++)
odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, p, 0);
/**/
}
#endif
} else if (dm->support_ic_type == ODM_RTL8188E) {
#if (RTL8188E_SUPPORT == 1)
odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);
/**/
#endif
}
}
#endif

23
hal/phydm/halrf/halrf_powertracking.h
View File

@@ -23,28 +23,19 @@
*
*****************************************************************************/
#ifndef __HALRF_POWER_TRACKING_H__
#define __HALRF_POWER_TRACKING_H__
#ifndef __HALRF_POWER_TRACKING_H__
#define __HALRF_POWER_TRACKING_H__
boolean
odm_check_power_status(
void *dm_void
);
odm_check_power_status(void *dm_void);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
void
halrf_update_pwr_track(
void *dm_void,
u8 rate
);
void halrf_update_pwr_track(void *dm_void, u8 rate);
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void
halrf_update_init_rate_work_item_callback(
void *context
);
void halrf_update_init_rate_work_item_callback(
void *context);
#endif
#endif
#endif /*#ifndef __HALRF_POWERTRACKING_H__*/

78
hal/phydm/halrf/halrf_powertracking_ap.c
View File

@@ -338,6 +338,50 @@ u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
};
/* Winnita ADD 20171113 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/
u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {
0x0CD, /*0 , -20dB*/
0x0D9,
0x0E6,
0x0F3,
0x102,
0x111,
0x121,
0x132,
0x144,
0x158,
0x16C,
0x182,
0x198,
0x1B1,
0x1CA,
0x1E5,
0x202,
0x221,
0x241,
0x263, /*19*/
0x287, /*20*/
0x2AE, /*21*/
0x2D6, /*22*/
0x301, /*23*/
0x32F, /*24*/
0x35F, /*25*/
0x392, /*26*/
0x3C9, /*27*/
0x402, /*28*/
0x43F, /*29*/
0x47F, /*30*/
0x4C3, /*31*/
0x50C, /*32*/
0x558, /*33*/
0x5A9, /*34*/
0x5FF, /*35*/
0x65A, /*36*/
0x6BA,
0x720,
0x78C,
0x7FF,
};
#if 0
@@ -692,7 +736,9 @@ u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8] = {
};
#endif
#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\
RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
RTL8814B_SUPPORT == 1)
u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
0x081, /* 0, -12.0dB */
0x088, /* 1, -11.5dB */
@@ -910,6 +956,15 @@ get_swing_index(
}
#endif
#if (RTL8192F_SUPPORT == 1)
if (GET_CHIP_VER(priv) == VERSION_8192F) {
bb_swing = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D);
swing_table = ofdm_swing_table_new;
swing_table_size = OFDM_TABLE_SIZE_92D;
bb_swing_mask = 22;
}
#endif
#if (RTL8822B_SUPPORT == 1)
if (GET_CHIP_VER(priv) == VERSION_8822B) {
bb_swing = phy_query_bb_reg(priv, REG_A_TX_SCALE_JAGUAR, 0xFFE00000);
@@ -926,7 +981,7 @@ get_swing_index(
break;
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "bb_swing=0x%x bbswing_index=%d\n", bb_swing, i);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "bb_swing=0x%x bbswing_index=%d\n", bb_swing, i);
return i;
@@ -943,8 +998,8 @@ odm_txpowertracking_thermal_meter_init(
struct rtl8192cd_priv *priv = dm->priv;
u8 p;
u8 default_swing_index;
#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
if ((GET_CHIP_VER(priv) == VERSION_8197F) || (GET_CHIP_VER(priv) == VERSION_8822B))
#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1)
if ((GET_CHIP_VER(priv) == VERSION_8197F) || (GET_CHIP_VER(priv) == VERSION_8822B) ||(GET_CHIP_VER(priv) == VERSION_8192F))
default_swing_index = get_swing_index(dm);
#endif
@@ -959,7 +1014,7 @@ odm_txpowertracking_thermal_meter_init(
if (*(dm->mp_mode) == false)
hal_data->txpowertrack_control = true;
PHYDM_DBG(dm, COMP_POWER_TRACKING, "mgnt_info->is_txpowertracking = %d\n", mgnt_info->is_txpowertracking);
RF_DBG(dm, COMP_POWER_TRACKING, "mgnt_info->is_txpowertracking = %d\n", mgnt_info->is_txpowertracking);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#ifdef CONFIG_RTL8188E
{
@@ -1016,6 +1071,13 @@ odm_txpowertracking_thermal_meter_init(
}
#endif
#if (RTL8192F_SUPPORT == 1)
if (GET_CHIP_VER(priv) == VERSION_8192F) {
cali_info->default_ofdm_index = 30;
cali_info->default_cck_index = 28;
}
#endif
#if (RTL8822B_SUPPORT == 1)
if (GET_CHIP_VER(priv) == VERSION_8822B) {
cali_info->default_ofdm_index = (default_swing_index >= (TXSCALE_TABLE_SIZE - 1)) ? 24 : default_swing_index;
@@ -1040,7 +1102,7 @@ odm_txpowertracking_thermal_meter_init(
}
cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "cali_info->default_ofdm_index=%d cali_info->default_cck_index=%d\n", cali_info->default_ofdm_index, cali_info->default_cck_index);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "cali_info->default_ofdm_index=%d cali_info->default_cck_index=%d\n", cali_info->default_ofdm_index, cali_info->default_cck_index);
cali_info->tm_trigger = 0;
}
@@ -1146,8 +1208,8 @@ odm_txpowertracking_check_ap(
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
struct rtl8192cd_priv *priv = dm->priv;
#if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8821C))
#if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1) || (RTL8198F_SUPPORT == 1))
if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8192F | ODM_RTL8198F))
odm_txpowertracking_callback_thermal_meter(dm);
else
#endif

65
hal/phydm/halrf/halrf_powertracking_ap.h
View File

@@ -13,8 +13,8 @@
*
*****************************************************************************/
#ifndef __PHYDMPOWERTRACKING_H__
#define __PHYDMPOWERTRACKING_H__
#ifndef __HALRF_POWERTRACKING_H__
#define __HALRF_POWERTRACKING_H__
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#ifdef RTK_AC_SUPPORT
@@ -44,6 +44,9 @@
#define IQK_BB_REG_NUM 9
#define AVG_THERMAL_NUM 8
#define AVG_THERMAL_NUM_DPK 8
#define THERMAL_DPK_AVG_NUM 4
#define iqk_matrix_reg_num 8
/* #define IQK_MATRIX_SETTINGS_NUM 1+24+21 */
#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
@@ -53,6 +56,7 @@
#define OFDM_TABLE_SIZE 37
#define CCK_TABLE_SIZE 33
#define CCK_TABLE_SIZE_88F 21
#define CCK_TABLE_SIZE_8192F 41
@@ -69,6 +73,7 @@
extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
#endif
@@ -96,7 +101,9 @@ static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4
#define OFDM_TABLE_SIZE_8812 43
#define AVG_THERMAL_NUM_8812 4
#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\
RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
RTL8814B_SUPPORT == 1)
extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
#elif(ODM_IC_11AC_SERIES_SUPPORT)
extern unsigned int ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812];
@@ -135,7 +142,7 @@ struct dm_rf_calibration_struct {
u8 thermal_value_lck;
u8 thermal_value_iqk;
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
u8 thermal_value_dpk;
u8 thermal_value_avg[AVG_THERMAL_NUM];
u8 thermal_value_avg_index;
u8 thermal_value_rx_gain;
@@ -143,7 +150,7 @@ struct dm_rf_calibration_struct {
u8 thermal_value_dpk_store;
u8 thermal_value_dpk_track;
boolean txpowertracking_in_progress;
boolean is_dpk_enable;
boolean is_reloadtxpowerindex;
u8 is_rf_pi_enable;
@@ -195,6 +202,8 @@ struct dm_rf_calibration_struct {
u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
@@ -223,6 +232,7 @@ struct dm_rf_calibration_struct {
boolean modify_tx_agc_flag_path_c;
boolean modify_tx_agc_flag_path_d;
boolean modify_tx_agc_flag_path_a_cck;
boolean modify_tx_agc_flag_path_b_cck;
s8 kfree_offset[MAX_RF_PATH];
@@ -269,8 +279,51 @@ struct dm_rf_calibration_struct {
u8 is_ap_kdone;
u8 is_apk_thermal_meter_ignore;
u8 is_dp_done;
#if 0 /*move below members to halrf_dpk.h*/
u8 is_dp_path_aok;
u8 is_dp_path_bok;
u8 is_dp_path_cok;
u8 is_dp_path_dok;
u8 dp_path_a_result[3];
u8 dp_path_b_result[3];
u8 dp_path_c_result[3];
u8 dp_path_d_result[3];
boolean is_dpk_enable;
u32 txrate[11];
u8 pwsf_2g_a[3];
u8 pwsf_2g_b[3];
u8 pwsf_2g_c[3];
u8 pwsf_2g_d[3];
u32 lut_2g_even_a[3][64];
u32 lut_2g_odd_a[3][64];
u32 lut_2g_even_b[3][64];
u32 lut_2g_odd_b[3][64];
u32 lut_2g_even_c[3][64];
u32 lut_2g_odd_c[3][64];
u32 lut_2g_even_d[3][64];
u32 lut_2g_odd_d[3][64];
u1Byte is_5g_pdk_a_ok;
u1Byte is_5g_pdk_b_ok;
u1Byte is_5g_pdk_c_ok;
u1Byte is_5g_pdk_d_ok;
u1Byte pwsf_5g_a[9];
u1Byte pwsf_5g_b[9];
u1Byte pwsf_5g_c[9];
u1Byte pwsf_5g_d[9];
u4Byte lut_5g_even_a[9][16];
u4Byte lut_5g_odd_a[9][16];
u4Byte lut_5g_even_b[9][16];
u4Byte lut_5g_odd_b[9][16];
u4Byte lut_5g_even_c[9][16];
u4Byte lut_5g_odd_c[9][16];
u4Byte lut_5g_even_d[9][16];
u4Byte lut_5g_odd_d[9][16];
u8 thermal_value_dpk;
u8 thermal_value_dpk_avg[AVG_THERMAL_NUM_DPK];
u8 thermal_value_dpk_avg_index;
#endif
s8 modify_tx_agc_value_ofdm;
s8 modify_tx_agc_value_cck;
/*Add by Yuchen for Kfree Phydm*/
u8 reg_rf_kfree_enable; /*for registry*/
@@ -342,4 +395,4 @@ odm_txpowertracking_thermal_meter_check(
#endif
#endif /*#ifndef __HALRF_POWER_TRACKING_H__*/

1116
hal/phydm/halrf/halrf_powertracking_ce.c
View File

File diff suppressed because it is too large Load Diff

473
hal/phydm/halrf/halrf_powertracking_ce.h
View File

@@ -23,326 +23,305 @@
*
*****************************************************************************/
#ifndef __PHYDMPOWERTRACKING_H__
#define __PHYDMPOWERTRACKING_H__
#ifndef __HALRF_POWERTRACKING_H__
#define __HALRF_POWERTRACKING_H__
#define DPK_DELTA_MAPPING_NUM 13
#define index_mapping_HP_NUM 15
#define OFDM_TABLE_SIZE 43
#define CCK_TABLE_SIZE 33
#define CCK_TABLE_SIZE_88F 21
#define TXSCALE_TABLE_SIZE 37
#define CCK_TABLE_SIZE_8723D 41
/* JJ ADD 20161014 */
#define CCK_TABLE_SIZE_8710B 41
#define DPK_DELTA_MAPPING_NUM 13
#define index_mapping_HP_NUM 15
#define OFDM_TABLE_SIZE 43
#define CCK_TABLE_SIZE 33
#define CCK_TABLE_SIZE_88F 21
#define TXSCALE_TABLE_SIZE 37
#define CCK_TABLE_SIZE_8723D 41
/*@JJ ADD 20161014 */
#define CCK_TABLE_SIZE_8710B 41
#define CCK_TABLE_SIZE_8192F 41
#define TXPWR_TRACK_TABLE_SIZE 30
#define DELTA_SWINGIDX_SIZE 30
#define DELTA_SWINTSSI_SIZE 61
#define BAND_NUM 4
#define TXPWR_TRACK_TABLE_SIZE 30
#define DELTA_SWINGIDX_SIZE 30
#define DELTA_SWINTSSI_SIZE 61
#define BAND_NUM 4
#define AVG_THERMAL_NUM 8
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM_MAX 10
#define AVG_THERMAL_NUM 8
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM_MAX 10
#define IQK_BB_REG_NUM 9
#define IQK_BB_REG_NUM 9
#define iqk_matrix_reg_num 8
#define iqk_matrix_reg_num 8
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
#else
#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
/* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
#define IQK_MATRIX_SETTINGS_NUM (14 + 24 + 21)
#endif
extern u32 ofdm_swing_table[OFDM_TABLE_SIZE];
extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
extern u32 ofdm_swing_table[OFDM_TABLE_SIZE];
extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
/* JJ ADD 20161014 */
extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
/*@JJ ADD 20161014 */
extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
extern u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
/*@<20121018, Kordan> In case fail to read TxPowerTrack.txt */
/* we use the table of 88E as the default table. */
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
#else
static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
extern u8 delta_swing_table_idx_2ga_p_8188e[];
extern u8 delta_swing_table_idx_2ga_n_8188e[];
#endif
#define dm_check_txpowertracking odm_txpowertracking_check
#define dm_check_txpowertracking odm_txpowertracking_check
struct iqk_matrix_regs_setting {
boolean is_iqk_done;
s32 value[3][iqk_matrix_reg_num];
boolean is_bw_iqk_result_saved[3];
boolean is_iqk_done;
s32 value[3][iqk_matrix_reg_num];
boolean is_bw_iqk_result_saved[3];
};
struct dm_rf_calibration_struct {
/* for tx power tracking */
u32 rega24; /* for TempCCK */
s32 rege94;
s32 rege9c;
s32 regeb4;
s32 regebc;
u32 rega24; /* for TempCCK */
s32 rege94;
s32 rege9c;
s32 regeb4;
s32 regebc;
u8 tx_powercount;
u8 tx_powercount;
boolean is_txpowertracking_init;
boolean is_txpowertracking;
u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
u8 tm_trigger;
u8 internal_pa_5g[2]; /* pathA / pathB */
/* for mp mode, turn off txpwrtracking as default */
u8 txpowertrack_control;
u8 tm_trigger;
u8 internal_pa_5g[2]; /* pathA / pathB */
u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
u8 thermal_value;
u8 thermal_value_lck;
u8 thermal_value_iqk;
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
u8 thermal_value_dpk;
u8 thermal_value_avg[AVG_THERMAL_NUM];
u8 thermal_value_avg_index;
u8 thermal_value_rx_gain;
u8 thermal_value_crystal;
u8 thermal_value_dpk_store;
u8 thermal_value_dpk_track;
boolean txpowertracking_in_progress;
/* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
u8 thermal_meter[2];
u8 thermal_value;
u8 thermal_value_lck;
u8 thermal_value_iqk;
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
u8 thermal_value_dpk;
u8 thermal_value_avg[AVG_THERMAL_NUM];
u8 thermal_value_avg_index;
u8 thermal_value_rx_gain;
u8 thermal_value_crystal;
u8 thermal_value_dpk_store;
u8 thermal_value_dpk_track;
boolean txpowertracking_in_progress;
boolean is_reloadtxpowerindex;
u8 is_rf_pi_enable;
u32 txpowertracking_callback_cnt; /* cosa add for debug */
boolean is_reloadtxpowerindex;
u8 is_rf_pi_enable;
u32 txpowertracking_callback_cnt; /* cosa add for debug */
/* ------------------------- Tx power Tracking ------------------------- */
u8 is_cck_in_ch14;
u8 CCK_index;
u8 OFDM_index[MAX_RF_PATH];
s8 power_index_offset[MAX_RF_PATH];
s8 delta_power_index[MAX_RF_PATH];
s8 delta_power_index_last[MAX_RF_PATH];
/*@---------------------- Tx power Tracking ---------------------- */
u8 is_cck_in_ch14;
u8 CCK_index;
u8 OFDM_index[MAX_RF_PATH];
s8 power_index_offset[MAX_RF_PATH];
s8 delta_power_index[MAX_RF_PATH];
s8 delta_power_index_last[MAX_RF_PATH];
boolean is_tx_power_changed;
s8 xtal_offset;
s8 xtal_offset_last;
s8 xtal_offset;
s8 xtal_offset_last;
u8 xtal_offset_eanble;
struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
u8 delta_lck;
s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
struct iqk_matrix_regs_setting
iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
u8 delta_lck;
s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
u8 bb_swing_idx_ofdm[MAX_RF_PATH];
u8 bb_swing_idx_ofdm_current;
u8 bb_swing_idx_ofdm[MAX_RF_PATH];
u8 bb_swing_idx_ofdm_current;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
#else
u8 bb_swing_idx_ofdm_base;
u8 bb_swing_idx_ofdm_base;
#endif
boolean default_bb_swing_index_flag;
boolean bb_swing_flag_ofdm;
u8 bb_swing_idx_cck;
u8 bb_swing_idx_cck_current;
u8 bb_swing_idx_cck_base;
u8 default_ofdm_index;
u8 default_cck_index;
boolean bb_swing_flag_cck;
boolean default_bb_swing_index_flag;
boolean bb_swing_flag_ofdm;
u8 bb_swing_idx_cck;
u8 bb_swing_idx_cck_current;
u8 bb_swing_idx_cck_base;
u8 default_ofdm_index;
u8 default_cck_index;
boolean bb_swing_flag_cck;
s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
s8 absolute_cck_swing_idx[MAX_RF_PATH];
s8 remnant_cck_swing_idx;
s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
boolean modify_tx_agc_flag_path_a;
boolean modify_tx_agc_flag_path_b;
boolean modify_tx_agc_flag_path_c;
boolean modify_tx_agc_flag_path_d;
boolean modify_tx_agc_flag_path_a_cck;
s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
s8 absolute_cck_swing_idx[MAX_RF_PATH];
s8 remnant_cck_swing_idx;
s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
boolean modify_tx_agc_flag_path_a;
boolean modify_tx_agc_flag_path_b;
boolean modify_tx_agc_flag_path_c;
boolean modify_tx_agc_flag_path_d;
boolean modify_tx_agc_flag_path_a_cck;
boolean modify_tx_agc_flag_path_b_cck;
s8 kfree_offset[MAX_RF_PATH];
s8 kfree_offset[MAX_RF_PATH];
/* -------------------------------------------------------------------- */
/*@----------------------------------------------------------------- */
/* for IQK */
u32 regc04;
u32 reg874;
u32 regc08;
u32 regb68;
u32 regb6c;
u32 reg870;
u32 reg860;
u32 reg864;
u32 regc04;
u32 reg874;
u32 regc08;
u32 regb68;
u32 regb6c;
u32 reg870;
u32 reg860;
u32 reg864;
boolean is_iqk_initialized;
boolean is_iqk_initialized;
boolean is_lck_in_progress;
boolean is_antenna_detected;
boolean is_need_iqk;
boolean is_iqk_in_progress;
boolean is_antenna_detected;
boolean is_need_iqk;
boolean is_iqk_in_progress;
boolean is_iqk_pa_off;
u8 delta_iqk;
u32 ADDA_backup[IQK_ADDA_REG_NUM];
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
u32 IQK_BB_backup_recover[9];
u32 IQK_BB_backup[IQK_BB_REG_NUM];
u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
u32 tx_iqc_8723d[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8723d[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
u8 delta_iqk;
u32 ADDA_backup[IQK_ADDA_REG_NUM];
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
u32 IQK_BB_backup_recover[9];
u32 IQK_BB_backup[IQK_BB_REG_NUM];
/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
u32 tx_iqc_8723b[2][3][2];
/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
u32 rx_iqc_8723b[2][2][2];
/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
u32 tx_iqc_8703b[3][2];
/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
u32 rx_iqc_8703b[2][2];
/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
u32 tx_iqc_8723d[2][3][2];
/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
u32 rx_iqc_8723d[2][2][2];
/* JJ ADD 20161014 */
u32 tx_iqc_8710b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8710b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
u32 tx_iqc_8710b[2][3][2];
/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
u32 rx_iqc_8710b[2][2][2];
u8 iqk_step;
u8 kcount;
u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
boolean is_mp_mode;
u8 iqk_step;
u8 kcount;
u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
boolean is_mp_mode;
/* <James> IQK time measurement */
u64 iqk_start_time;
u64 iqk_progressing_time;
u64 iqk_total_progressing_time;
/*@<James> IQK time measurement */
u64 iqk_start_time;
u64 iqk_progressing_time;
u64 iqk_total_progressing_time;
u64 lck_progressing_time;
u32 lok_result;
u32 lok_result;
/* for APK */
u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
u8 is_ap_kdone;
u8 is_apk_thermal_meter_ignore;
u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
u8 is_ap_kdone;
u8 is_apk_thermal_meter_ignore;
/* DPK */
boolean is_dpk_fail;
u8 is_dp_done;
u8 is_dp_path_aok;
u8 is_dp_path_bok;
u8 is_dp_done;
u8 is_dp_path_aok;
u8 is_dp_path_bok;
u32 tx_lok[2];
u32 dpk_tx_agc;
s32 dpk_gain;
u32 dpk_thermal[4];
u32 tx_lok[2];
u32 dpk_tx_agc;
s32 dpk_gain;
u32 dpk_thermal[4];
s8 modify_tx_agc_value_ofdm;
s8 modify_tx_agc_value_cck;
/*Add by Yuchen for Kfree Phydm*/
u8 reg_rf_kfree_enable; /*for registry*/
u8 rf_kfree_enable; /*for efuse enable check*/
/*@Add by Yuchen for Kfree Phydm*/
u8 reg_rf_kfree_enable; /*for registry*/
u8 rf_kfree_enable; /*for efuse enable check*/
};
void odm_txpowertracking_check(void *dm_void);
void
odm_txpowertracking_check(
void *dm_void
);
void odm_txpowertracking_init(void *dm_void);
void odm_txpowertracking_check_ap(void *dm_void);
void
odm_txpowertracking_init(
void *dm_void
);
void odm_txpowertracking_thermal_meter_init(void *dm_void);
void
odm_txpowertracking_check_ap(
void *dm_void
);
void odm_txpowertracking_init(void *dm_void);
void
odm_txpowertracking_thermal_meter_init(
void *dm_void
);
void odm_txpowertracking_check_mp(void *dm_void);
void
odm_txpowertracking_init(
void *dm_void
);
void odm_txpowertracking_check_ce(void *dm_void);
void
odm_txpowertracking_check_mp(
void *dm_void
);
void
odm_txpowertracking_check_ce(
void *dm_void
);
void odm_txpowertracking_direct_ce(void *dm_void);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
void
odm_txpowertracking_callback_thermal_meter92c(
void *adapter
);
void odm_txpowertracking_callback_thermal_meter92c(
void *adapter);
void
odm_txpowertracking_callback_rx_gain_thermal_meter92d(
void *adapter
);
void odm_txpowertracking_callback_rx_gain_thermal_meter92d(
void *adapter);
void
odm_txpowertracking_callback_thermal_meter92d(
void *adapter
);
void odm_txpowertracking_callback_thermal_meter92d(
void *adapter);
void
odm_txpowertracking_direct_call92c(
void *adapter
);
void odm_txpowertracking_direct_call92c(
void *adapter);
void
odm_txpowertracking_thermal_meter_check(
void *adapter
);
void odm_txpowertracking_thermal_meter_check(
void *adapter);
#endif
#endif
#endif /*__HALRF_POWER_TRACKING_H__*/

741
hal/phydm/halrf/halrf_powertracking_iot.c Normal file
View File

@@ -0,0 +1,741 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*============================================================ */
/* include files */
/*============================================================ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
/* ************************************************************
* Global var
* ************************************************************
*/
u32 ofdm_swing_table[OFDM_TABLE_SIZE] = {
0x7f8001fe, /* 0, +6.0dB */
0x788001e2, /* 1, +5.5dB */
0x71c001c7, /* 2, +5.0dB*/
0x6b8001ae, /* 3, +4.5dB*/
0x65400195, /* 4, +4.0dB*/
0x5fc0017f, /* 5, +3.5dB*/
0x5a400169, /* 6, +3.0dB*/
0x55400155, /* 7, +2.5dB*/
0x50800142, /* 8, +2.0dB*/
0x4c000130, /* 9, +1.5dB*/
0x47c0011f, /* 10, +1.0dB*/
0x43c0010f, /* 11, +0.5dB*/
0x40000100, /* 12, +0dB*/
0x3c8000f2, /* 13, -0.5dB*/
0x390000e4, /* 14, -1.0dB*/
0x35c000d7, /* 15, -1.5dB*/
0x32c000cb, /* 16, -2.0dB*/
0x300000c0, /* 17, -2.5dB*/
0x2d4000b5, /* 18, -3.0dB*/
0x2ac000ab, /* 19, -3.5dB*/
0x288000a2, /* 20, -4.0dB*/
0x26000098, /* 21, -4.5dB*/
0x24000090, /* 22, -5.0dB*/
0x22000088, /* 23, -5.5dB*/
0x20000080, /* 24, -6.0dB*/
0x1e400079, /* 25, -6.5dB*/
0x1c800072, /* 26, -7.0dB*/
0x1b00006c, /* 27. -7.5dB*/
0x19800066, /* 28, -8.0dB*/
0x18000060, /* 29, -8.5dB*/
0x16c0005b, /* 30, -9.0dB*/
0x15800056, /* 31, -9.5dB*/
0x14400051, /* 32, -10.0dB*/
0x1300004c, /* 33, -10.5dB*/
0x12000048, /* 34, -11.0dB*/
0x11000044, /* 35, -11.5dB*/
0x10000040, /* 36, -12.0dB*/
};
u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB*/
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB*/
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB*/
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB*/
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB*/
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB*/
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB*/
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB <== default */
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB*/
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB*/
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB*/
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB*/
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB*/
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB*/
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB*/
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB*/
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB*/
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB*/
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB*/
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB*/
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB*/
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB*/
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB*/
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB*/
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB*/
};
u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB*/
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB*/
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB*/
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB*/
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB <== default*/
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB*/
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB*/
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB*/
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB*/
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB*/
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB*/
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB*/
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB*/
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB*/
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB*/
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB*/
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB*/
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB*/
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB*/
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB*/
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB*/
};
u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
0x0b40002d, /* 0, -15.0dB */
0x0c000030, /* 1, -14.5dB*/
0x0cc00033, /* 2, -14.0dB*/
0x0d800036, /* 3, -13.5dB*/
0x0e400039, /* 4, -13.0dB */
0x0f00003c, /* 5, -12.5dB*/
0x10000040, /* 6, -12.0dB*/
0x11000044, /* 7, -11.5dB*/
0x12000048, /* 8, -11.0dB*/
0x1300004c, /* 9, -10.5dB*/
0x14400051, /* 10, -10.0dB*/
0x15800056, /* 11, -9.5dB*/
0x16c0005b, /* 12, -9.0dB*/
0x18000060, /* 13, -8.5dB*/
0x19800066, /* 14, -8.0dB*/
0x1b00006c, /* 15, -7.5dB*/
0x1c800072, /* 16, -7.0dB*/
0x1e400079, /* 17, -6.5dB*/
0x20000080, /* 18, -6.0dB*/
0x22000088, /* 19, -5.5dB*/
0x24000090, /* 20, -5.0dB*/
0x26000098, /* 21, -4.5dB*/
0x288000a2, /* 22, -4.0dB*/
0x2ac000ab, /* 23, -3.5dB*/
0x2d4000b5, /* 24, -3.0dB*/
0x300000c0, /* 25, -2.5dB*/
0x32c000cb, /* 26, -2.0dB*/
0x35c000d7, /* 27, -1.5dB*/
0x390000e4, /* 28, -1.0dB*/
0x3c8000f2, /* 29, -0.5dB*/
0x40000100, /* 30, +0dB*/
0x43c0010f, /* 31, +0.5dB*/
0x47c0011f, /* 32, +1.0dB*/
0x4c000130, /* 33, +1.5dB*/
0x50800142, /* 34, +2.0dB*/
0x55400155, /* 35, +2.5dB*/
0x5a400169, /* 36, +3.0dB*/
0x5fc0017f, /* 37, +3.5dB*/
0x65400195, /* 38, +4.0dB*/
0x6b8001ae, /* 39, +4.5dB*/
0x71c001c7, /* 40, +5.0dB*/
0x788001e2, /* 41, +5.5dB*/
0x7f8001fe /* 42, +6.0dB*/
};
u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
};
u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
};
u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
};
u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB*/
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB*/
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB*/
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB*/
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB*/
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB*/
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB*/
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB*/
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB*/
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB*/
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB*/
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB*/
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB*/
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB*/
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB*/
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB*/
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB*/
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*20, -6.0dB */
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB*/
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB*/
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB*/
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB*/
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB*/
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB*/
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB*/
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB*/
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB*/
};
u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB*/
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB*/
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB*/
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB*/
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB*/
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*5, -13.5dB*/
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB*/
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB*/
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB*/
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB*/
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB*/
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*11, -10.5dB*/
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB*/
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB*/
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*14, -9.0dB */
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB*/
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB*/
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB*/
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*23, -4.5dB*/
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*27, -2.5dB*/
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*29, -1.5dB*/
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */
};
u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
0x0CD, /*0 , -20dB*/
0x0D9,
0x0E6,
0x0F3,
0x102,
0x111,
0x121,
0x132,
0x144,
0x158,
0x16C,
0x182,
0x198,
0x1B1,
0x1CA,
0x1E5,
0x202,
0x221,
0x241,
0x263,
0x287,
0x2AE,
0x2D6,
0x301,
0x32F,
0x35F,
0x392,
0x3C9,
0x402,
0x43F,
0x47F,
0x4C3,
0x50C,
0x558,
0x5A9,
0x5FF,
0x65A,
0x6BA,
0x720,
0x78C,
0x7FF,
};
/* JJ ADD 20161014 */
u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
0x0CD, /*0 , -20dB*/
0x0D9,
0x0E6,
0x0F3,
0x102,
0x111,
0x121,
0x132,
0x144,
0x158,
0x16C,
0x182,
0x198,
0x1B1,
0x1CA,
0x1E5,
0x202,
0x221,
0x241,
0x263,
0x287,
0x2AE,
0x2D6,
0x301,
0x32F,
0x35F,
0x392,
0x3C9,
0x402,
0x43F,
0x47F,
0x4C3,
0x50C,
0x558,
0x5A9,
0x5FF,
0x65A,
0x6BA,
0x720,
0x78C,
0x7FF,
};
/* Winnita ADD 20171116 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/
u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {
0x0CD, /*0 , -20dB*/
0x0D9,
0x0E6,
0x0F3,
0x102,
0x111,
0x121,
0x132,
0x144,
0x158,
0x16C,
0x182,
0x198,
0x1B1,
0x1CA,
0x1E5,
0x202,
0x221,
0x241,
0x263, /*19*/
0x287, /*20*/
0x2AE, /*21*/
0x2D6, /*22*/
0x301, /*23*/
0x32F, /*24*/
0x35F, /*25*/
0x392, /*26*/
0x3C9, /*27*/
0x402, /*28*/
0x43F, /*29*/
0x47F, /*30*/
0x4C3, /*31*/
0x50C, /*32*/
0x558, /*33*/
0x5A9, /*34*/
0x5FF, /*35*/
0x65A, /*36*/
0x6BA,
0x720,
0x78C,
0x7FF,
};
/* Winnita ADD 201805 PathA 0xAB4[10:0]*/
u32 cck_swing_table_ch1_ch14_8721d[CCK_TABLE_SIZE_8721D] = {
0x0CD, /*0 , -20dB*/
0x0D9,
0x0E6,
0x0F3,
0x102,
0x111,
0x121,
0x132,
0x144,
0x158,
0x16C,
0x182,
0x198,
0x1B1,
0x1CA,
0x1E5,
0x202,
0x221,
0x241,
0x263, /*19*/
0x287, /*20*/
0x2AE, /*21*/
0x2D6, /*22*/
0x301, /*23*/
0x32F, /*24*/
0x35F, /*25*/
0x392, /*26*/
0x3C9, /*27*/
0x402, /*28*/
0x43F, /*29*/
0x47F, /*30*/
0x4C3, /*31*/
0x50C, /*32*/
0x558, /*33*/
0x5A9, /*34*/
0x5FF, /*35*/
0x65A, /*36*/
0x6BA,
0x720,
0x78C,
0x7FF,
};
u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
0x081, /* 0, -12.0dB*/
0x088, /* 1, -11.5dB*/
0x090, /* 2, -11.0dB*/
0x099, /* 3, -10.5dB*/
0x0A2, /* 4, -10.0dB*/
0x0AC, /* 5, -9.5dB*/
0x0B6, /* 6, -9.0dB*/
0x0C0, /*7, -8.5dB*/
0x0CC, /* 8, -8.0dB*/
0x0D8, /* 9, -7.5dB*/
0x0E5, /* 10, -7.0dB*/
0x0F2, /* 11, -6.5dB*/
0x101, /* 12, -6.0dB*/
0x110, /* 13, -5.5dB*/
0x120, /* 14, -5.0dB*/
0x131, /* 15, -4.5dB*/
0x143, /* 16, -4.0dB*/
0x156, /* 17, -3.5dB*/
0x16A, /* 18, -3.0dB*/
0x180, /* 19, -2.5dB*/
0x197, /* 20, -2.0dB*/
0x1AF, /* 21, -1.5dB*/
0x1C8, /* 22, -1.0dB*/
0x1E3, /* 23, -0.5dB*/
0x200, /* 24, +0 dB*/
0x21E, /* 25, +0.5dB*/
0x23E, /* 26, +1.0dB*/
0x261, /* 27, +1.5dB*/
0x285,/* 28, +2.0dB*/
0x2AB, /* 29, +2.5dB*/
0x2D3, /*30, +3.0dB*/
0x2FE, /* 31, +3.5dB*/
0x32B, /* 32, +4.0dB*/
0x35C, /* 33, +4.5dB*/
0x38E, /* 34, +5.0dB*/
0x3C4, /* 35, +5.5dB*/
0x3FE /* 36, +6.0dB */
};
void
odm_txpowertracking_init(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
odm_txpowertracking_thermal_meter_init(dm);
}
u8
get_swing_index(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i = 0;
u32 bb_swing;
u32 swing_table_size;
u32 *swing_table;
if (dm->support_ic_type == ODM_RTL8195B) {
bb_swing = odm_get_bb_reg(dm, R_0xc1c, 0xFFE00000);
swing_table = tx_scaling_table_jaguar;
swing_table_size = TXSCALE_TABLE_SIZE;
}
for (i = 0; i < swing_table_size; i++) {
u32 table_value = swing_table[i];
table_value = table_value;
if (bb_swing == table_value)
break;
}
return i;
}
u8
get_cck_swing_index(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i = 0;
u32 bb_cck_swing;
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
dm->support_ic_type == ODM_RTL8192E) {
bb_cck_swing = odm_read_1byte(dm, 0xa22);
for (i = 0; i < CCK_TABLE_SIZE; i++) {
if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
break;
}
} else if (dm->support_ic_type == ODM_RTL8703B) {
bb_cck_swing = odm_read_1byte(dm, 0xa22);
for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
break;
}
}
return i;
}
void
odm_txpowertracking_thermal_meter_init(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 default_swing_index = get_swing_index(dm);
u8 p = 0;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
struct _hal_rf_ *rf = &dm->rf_table;
if (!(*dm->mp_mode))
cali_info->txpowertrack_control = true;
else
cali_info->txpowertrack_control = false;
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "dm txpowertrack_control = %d\n", cali_info->txpowertrack_control);
/* dm->rf_calibrate_info.txpowertrack_control = true; */
cali_info->thermal_value = rf->eeprom_thermal;
cali_info->thermal_value_iqk = rf->eeprom_thermal;
cali_info->thermal_value_lck = rf->eeprom_thermal;
if (!cali_info->default_bb_swing_index_flag) {
if (dm->support_ic_type == ODM_RTL8195B) {
cali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
cali_info->default_cck_index = 24;
} else if (dm->support_ic_type == ODM_RTL8721D) {
cali_info->default_ofdm_index = 30; /*OFDM: 0dB*/
cali_info->default_cck_index = 28; /*CCK: -6dB*/
}
cali_info->default_bb_swing_index_flag = true;
}
cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
cali_info->CCK_index = cali_info->default_cck_index;
for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
cali_info->delta_power_index[p] = 0;
cali_info->delta_power_index_last[p] = 0;
cali_info->power_index_offset[p] = 0;
}
cali_info->modify_tx_agc_value_ofdm = 0;
cali_info->modify_tx_agc_value_cck = 0;
cali_info->tm_trigger = 0;
}
void
odm_txpowertracking_check(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
odm_txpowertracking_check_iot(dm);
}
void
odm_txpowertracking_check_iot(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _hal_rf_ *rf = &dm->rf_table;
if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
return;
if (!dm->rf_calibrate_info.tm_trigger) {
if (dm->support_ic_type == ODM_RTL8195B)
odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03);
else if (dm->support_ic_type == ODM_RTL8721D)
odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW,
(BIT(12) | BIT(11)), 0x03);
dm->rf_calibrate_info.tm_trigger = 1;
return;
}
odm_txpowertracking_callback_thermal_meter(dm);
dm->rf_calibrate_info.tm_trigger = 0;
}
void
odm_txpowertracking_check_mp(
void *dm_void
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct dm_struct *dm = (struct dm_struct *)dm_void;
void *adapter = dm->adapter;
if (odm_check_power_status(adapter) == false) {
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("check_pow_status, return false\n"));
return;
}
odm_txpowertracking_thermal_meter_check(adapter);
#endif
}
void
odm_txpowertracking_check_ap(
void *dm_void
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct rtl8192cd_priv *priv = dm->priv;
return;
#endif
}

349
hal/phydm/halrf/halrf_powertracking_iot.h Normal file
View File

@@ -0,0 +1,349 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_POWERTRACKING_H__
#define __HALRF_POWERTRACKING_H__
#define DPK_DELTA_MAPPING_NUM 13
#define index_mapping_HP_NUM 15
#define OFDM_TABLE_SIZE 43
#define CCK_TABLE_SIZE 33
#define CCK_TABLE_SIZE_88F 21
#define TXSCALE_TABLE_SIZE 37
#define CCK_TABLE_SIZE_8723D 41
/* JJ ADD 20161014 */
#define CCK_TABLE_SIZE_8710B 41
#define CCK_TABLE_SIZE_8192F 41
#define CCK_TABLE_SIZE_8721D 41
#define TXPWR_TRACK_TABLE_SIZE 30
#define DELTA_SWINGIDX_SIZE 30
#define DELTA_SWINTSSI_SIZE 61
#define BAND_NUM 4
#define AVG_THERMAL_NUM 8
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM_MAX 10
#define IQK_BB_REG_NUM 9
#define iqk_matrix_reg_num 8
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
#else
#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
#endif
extern u32 ofdm_swing_table[OFDM_TABLE_SIZE];
extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
/* JJ ADD 20161014 */
extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
extern u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
extern u32 cck_swing_table_ch1_ch14_8721d[CCK_TABLE_SIZE_8721D];
extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
#else
static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
#endif
void
odm_txpowertracking_init(
void *dm_void
);
#define dm_check_txpowertracking odm_txpowertracking_check
struct iqk_matrix_regs_setting {
boolean is_iqk_done;
s32 value[3][iqk_matrix_reg_num];
boolean is_bw_iqk_result_saved[3];
};
struct dm_rf_calibration_struct {
/* for tx power tracking */
u32 rega24; /* for TempCCK */
s32 rege94;
s32 rege9c;
s32 regeb4;
s32 regebc;
u8 tx_powercount;
boolean is_txpowertracking_init;
boolean is_txpowertracking;
u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
u8 tm_trigger;
u8 internal_pa_5g[2]; /* pathA / pathB */
u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
u8 thermal_value;
u8 thermal_value_lck;
u8 thermal_value_iqk;
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
u8 thermal_value_dpk;
u8 thermal_value_avg[AVG_THERMAL_NUM];
u8 thermal_value_avg_index;
u8 thermal_value_rx_gain;
u8 thermal_value_crystal;
u8 thermal_value_dpk_store;
u8 thermal_value_dpk_track;
boolean txpowertracking_in_progress;
boolean is_reloadtxpowerindex;
u8 is_rf_pi_enable;
u32 txpowertracking_callback_cnt; /* cosa add for debug */
/* ------------------------- Tx power Tracking ------------------------- */
u8 is_cck_in_ch14;
u8 CCK_index;
u8 OFDM_index[MAX_RF_PATH];
s8 power_index_offset[MAX_RF_PATH];
s8 delta_power_index[MAX_RF_PATH];
s8 delta_power_index_last[MAX_RF_PATH];
boolean is_tx_power_changed;
s8 xtal_offset;
s8 xtal_offset_last;
struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
u8 delta_lck;
s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
u8 bb_swing_idx_ofdm[MAX_RF_PATH];
u8 bb_swing_idx_ofdm_current;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
#else
u8 bb_swing_idx_ofdm_base;
#endif
boolean default_bb_swing_index_flag;
boolean bb_swing_flag_ofdm;
u8 bb_swing_idx_cck;
u8 bb_swing_idx_cck_current;
u8 bb_swing_idx_cck_base;
u8 default_ofdm_index;
u8 default_cck_index;
boolean bb_swing_flag_cck;
s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
s8 absolute_cck_swing_idx[MAX_RF_PATH];
s8 remnant_cck_swing_idx;
s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
boolean modify_tx_agc_flag_path_a;
boolean modify_tx_agc_flag_path_b;
boolean modify_tx_agc_flag_path_c;
boolean modify_tx_agc_flag_path_d;
boolean modify_tx_agc_flag_path_a_cck;
boolean modify_tx_agc_flag_path_b_cck;
s8 kfree_offset[MAX_RF_PATH];
/* -------------------------------------------------------------------- */
/* for IQK */
u32 regc04;
u32 reg874;
u32 regc08;
u32 regb68;
u32 regb6c;
u32 reg870;
u32 reg860;
u32 reg864;
boolean is_iqk_initialized;
boolean is_lck_in_progress;
boolean is_antenna_detected;
boolean is_need_iqk;
boolean is_iqk_in_progress;
boolean is_iqk_pa_off;
u8 delta_iqk;
u32 ADDA_backup[IQK_ADDA_REG_NUM];
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
u32 IQK_BB_backup_recover[9];
u32 IQK_BB_backup[IQK_BB_REG_NUM];
u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
u32 tx_iqc_8723d[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8723d[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
/* JJ ADD 20161014 */
u32 tx_iqc_8710b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
u32 rx_iqc_8710b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
u8 iqk_step;
u8 kcount;
u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
boolean is_mp_mode;
/* <James> IQK time measurement */
u32 iqk_start_time;
u32 iqk_progressing_time;
u32 iqk_total_progressing_time;
u32 lck_progressing_time;
u32 lok_result;
/* for APK */
u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
u8 is_ap_kdone;
u8 is_apk_thermal_meter_ignore;
/* DPK */
boolean is_dpk_fail;
u8 is_dp_done;
u8 is_dp_path_aok;
u8 is_dp_path_bok;
u32 tx_lok[2];
u32 dpk_tx_agc;
s32 dpk_gain;
u32 dpk_thermal[4];
s8 modify_tx_agc_value_ofdm;
s8 modify_tx_agc_value_cck;
/*Add by Yuchen for Kfree Phydm*/
u8 reg_rf_kfree_enable; /*for registry*/
u8 rf_kfree_enable; /*for efuse enable check*/
};
void
odm_txpowertracking_check(
void *dm_void
);
void
odm_txpowertracking_check_ap(
void *dm_void
);
void
odm_txpowertracking_thermal_meter_init(
void *dm_void
);
void
odm_txpowertracking_check_mp(
void *dm_void
);
void
odm_txpowertracking_check_iot(
void *dm_void
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
void
odm_txpowertracking_callback_thermal_meter92c(
void *adapter
);
void
odm_txpowertracking_callback_rx_gain_thermal_meter92d(
void *adapter
);
void
odm_txpowertracking_callback_thermal_meter92d(
void *adapter
);
void
odm_txpowertracking_direct_call92c(
void *adapter
);
void
odm_txpowertracking_thermal_meter_check(
void *adapter
);
#endif
#endif /*#ifndef __HALRF_POWER_TRACKING_H__*/

101
hal/phydm/halrf/halrf_powertracking_win.c
View File

@@ -419,6 +419,50 @@ u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
0x7FF,
};
/* Winnita ADD 20170828 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/
u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {
0x0CD, /*0 , -20dB*/
0x0D9,
0x0E6,
0x0F3,
0x102,
0x111,
0x121,
0x132,
0x144,
0x158,
0x16C,
0x182,
0x198,
0x1B1,
0x1CA,
0x1E5,
0x202,
0x221,
0x241,
0x263, /*19*/
0x287, /*20*/
0x2AE, /*21*/
0x2D6, /*22*/
0x301, /*23*/
0x32F, /*24*/
0x35F, /*25*/
0x392, /*26*/
0x3C9, /*27*/
0x402, /*28*/
0x43F, /*29*/
0x47F, /*30*/
0x4C3, /*31*/
0x50C, /*32*/
0x558, /*33*/
0x5A9, /*34*/
0x5FF, /*35*/
0x65A, /*36*/
0x6BA,
0x720,
0x78C,
0x7FF,
};
u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
0x081, /* 0, -12.0dB */
@@ -483,30 +527,34 @@ get_swing_index(
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
u8 i = 0;
u32 bb_swing;
u32 swing_table_size;
u32 *swing_table;
u32 bb_swing, table_value;
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710B) {
dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8188F ||
dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D ||
dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8710B ||
dm->support_ic_type == ODM_RTL8821) {
bb_swing = odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000);
swing_table = ofdm_swing_table_new;
swing_table_size = OFDM_TABLE_SIZE;
for (i = 0; i < OFDM_TABLE_SIZE; i++) {
table_value = ofdm_swing_table_new[i];
if (table_value >= 0x100000)
table_value >>= 22;
if (bb_swing == table_value)
break;
}
} else {
bb_swing = PHY_GetTxBBSwing_8812A((PADAPTER)adapter, hal_data->CurrentBandType, RF_PATH_A);
swing_table = tx_scaling_table_jaguar;
swing_table_size = TXSCALE_TABLE_SIZE;
bb_swing = PHY_GetTxBBSwing_8812A(adapter, hal_data->CurrentBandType, RF_PATH_A);
for (i = 0; i < TXSCALE_TABLE_SIZE; i++) {
table_value = tx_scaling_table_jaguar[i];
if (bb_swing == table_value)
break;
}
}
for (i = 0; i < swing_table_size; ++i) {
u32 table_value = swing_table[i];
if (table_value >= 0x100000)
table_value >>= 22;
if (bb_swing == table_value)
break;
}
return i;
}
@@ -615,7 +663,8 @@ odm_txpowertracking_thermal_meter_init(
if (cali_info->default_bb_swing_index_flag != true) {
/*The index of "0 dB" in SwingTable.*/
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8703B) {
dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8703B ||
dm->support_ic_type == ODM_RTL8821) {
cali_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index;
cali_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index;
} else if (dm->support_ic_type == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/
@@ -628,6 +677,10 @@ odm_txpowertracking_thermal_meter_init(
} else if (dm->support_ic_type == ODM_RTL8710B) {
cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
cali_info->default_cck_index = 28; /*CCK: -6dB*/
/*Winnita add 20170828*/
} else if (dm->support_ic_type == ODM_RTL8192F) {
cali_info->default_ofdm_index = 30; /*OFDM: 0dB*/
cali_info->default_cck_index = 28; /*CCK: -6dB*/
} else {
cali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
cali_info->default_cck_index = 24;
@@ -785,18 +838,20 @@ odm_txpowertracking_thermal_meter_check(
}
if (!tm_trigger) {
if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8192E(adapter) ||
IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8814A(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8703B(adapter)
if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8192E(adapter) || IS_HARDWARE_TYPE_8192F(adapter)
||IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8814A(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8703B(adapter)
|| IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8821C(adapter) || IS_HARDWARE_TYPE_8710B(adapter))/* JJ ADD 20161014 */
PHY_SetRFReg((PADAPTER)adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
PHY_SetRFReg(adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
else
PHY_SetRFReg((PADAPTER)adapter, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
PHY_SetRFReg(adapter, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Trigger Thermal Meter!!\n"));
tm_trigger = 1;
return;
} else {
} else if (IS_HARDWARE_TYPE_8822C(adapter) || IS_HARDWARE_TYPE_8814B(adapter))
return;
else {
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Schedule TxPowerTracking direct call!!\n"));
odm_txpowertracking_direct_call(adapter);
tm_trigger = 0;

9
hal/phydm/halrf/halrf_powertracking_win.h
View File

@@ -13,8 +13,8 @@
*
*****************************************************************************/
#ifndef __PHYDMPOWERTRACKING_H__
#define __PHYDMPOWERTRACKING_H__
#ifndef __HALRF_POWERTRACKING_H__
#define __HALRF_POWERTRACKING_H__
#define DPK_DELTA_MAPPING_NUM 13
#define index_mapping_HP_NUM 15
@@ -30,6 +30,7 @@
#define CCK_TABLE_SIZE_88F 21
/* JJ ADD 20161014 */
#define CCK_TABLE_SIZE_8710B 41
#define CCK_TABLE_SIZE_8192F 41
#define dm_check_txpowertracking odm_txpowertracking_check
@@ -56,6 +57,7 @@ extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
/* JJ ADD 20161014 */
extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
extern u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
@@ -223,6 +225,7 @@ struct dm_rf_calibration_struct {
boolean modify_tx_agc_flag_path_c;
boolean modify_tx_agc_flag_path_d;
boolean modify_tx_agc_flag_path_a_cck;
boolean modify_tx_agc_flag_path_b_cck;
s8 kfree_offset[MAX_RF_PATH];
@@ -296,4 +299,4 @@ struct dm_rf_calibration_struct {
#endif
#endif /*#ifndef __HALRF_POWER_TRACKING_H__*/

749
hal/phydm/halrf/halrf_psd.c
View File

@@ -1,321 +1,428 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
//============================================================
// include files
//============================================================
#include "mp_precomp.h"
#include "phydm_precomp.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if 0
u32 _sqrt(u64 n)
{
u64 ans = 0, q = 0;
s64 i;
/*for (i = sizeof(n) * 8 - 2; i > -1; i = i - 2) {*/
for (i = 8 * 8 - 2; i > -1; i = i - 2) {
q = (q << 2) | ((n & (3 << i)) >> i);
if (q >= ((ans << 2) | 1))
{
q = q - ((ans << 2) | 1);
ans = (ans << 1) | 1;
}
else
ans = ans << 1;
}
DbgPrint("ans=0x%x\n", ans);
return (u32)ans;
}
#endif
u64 _sqrt(u64 x)
{
u64 i = 0;
u64 j = x / 2 + 1;
while (i <= j) {
u64 mid = (i + j) / 2;
u64 sq = mid * mid;
if (sq == x)
return mid;
else if (sq < x)
i = mid + 1;
else
j = mid - 1;
}
return j;
}
u32
halrf_get_psd_data(
struct dm_struct *dm,
u32 point
)
{
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
u32 psd_val = 0, psd_reg, psd_report, psd_point, psd_start, i, delay_time;
#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
if (psd->average == 0)
delay_time = 100;
else
delay_time = 0;
#else
if (psd->average == 0)
delay_time = 1000;
else
delay_time = 100;
#endif
if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
psd_reg = 0x910;
psd_report = 0xf44;
} else {
psd_reg = 0x808;
psd_report = 0x8b4;
}
if (dm->support_ic_type & ODM_RTL8710B) {
psd_point = 0xeffffc00;
psd_start = 0x10000000;
} else {
psd_point = 0xffbffc00;
psd_start = 0x00400000;
}
psd_val = odm_get_bb_reg(dm, psd_reg, MASKDWORD);
psd_val &= psd_point;
psd_val |= point;
odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val);
psd_val |= psd_start;
odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val);
for (i = 0; i < delay_time; i++)
ODM_delay_us(1);
psd_val = odm_get_bb_reg(dm, psd_report, MASKDWORD);
if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8710B)) {
psd_val &= MASKL3BYTES;
psd_val = psd_val / 32;
} else
psd_val &= MASKLWORD;
return psd_val;
}
void
halrf_psd(
struct dm_struct *dm,
u32 point,
u32 start_point,
u32 stop_point,
u32 average
)
{
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
u32 i = 0, j = 0, k = 0;
u32 psd_reg, avg_org, point_temp, average_tmp;
u64 data_tatal = 0, data_temp[64] = {0};
psd->buf_size = 256;
if (average == 0)
average_tmp = 1;
else
average_tmp = average;
if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
psd_reg = 0x910;
else
psd_reg = 0x808;
#if 0
dbg_print("[PSD]point=%d, start_point=%d, stop_point=%d, average=%d, average_tmp=%d, buf_size=%d\n",
point, start_point, stop_point, average, average_tmp, psd->buf_size);
#endif
for (i = 0; i < psd->buf_size; i++)
psd->psd_data[i] = 0;
if (dm->support_ic_type & ODM_RTL8710B)
avg_org = odm_get_bb_reg(dm, psd_reg, 0x30000);
else
avg_org = odm_get_bb_reg(dm, psd_reg, 0x3000);
if (average != 0)
{
if (dm->support_ic_type & ODM_RTL8710B)
odm_set_bb_reg(dm, psd_reg, 0x30000, 0x1);
else
odm_set_bb_reg(dm, psd_reg, 0x3000, 0x1);
}
#if 0
if (avg_temp == 0)
avg = 1;
else if (avg_temp == 1)
avg = 8;
else if (avg_temp == 2)
avg = 16;
else if (avg_temp == 3)
avg = 32;
#endif
i = start_point;
while (i < stop_point) {
data_tatal = 0;
if (i >= point)
point_temp = i - point;
else
point_temp = i;
for (k = 0; k < average_tmp; k++) {
data_temp[k] = halrf_get_psd_data(dm, point_temp);
data_tatal = data_tatal + (data_temp[k] * data_temp[k]);
#if 0
if ((k % 20) == 0)
dbg_print("\n ");
dbg_print("0x%x ", data_temp[k]);
#endif
}
/*dbg_print("\n");*/
data_tatal = ((data_tatal * 100) / average_tmp);
psd->psd_data[j] = (u32)_sqrt(data_tatal);
i++;
j++;
}
#if 0
for (i = 0; i < psd->buf_size; i++) {
if ((i % 20) == 0)
dbg_print("\n ");
dbg_print("0x%x ", psd->psd_data[i]);
}
dbg_print("\n\n");
#endif
if (dm->support_ic_type & ODM_RTL8710B)
odm_set_bb_reg(dm, psd_reg, 0x30000, avg_org);
else
odm_set_bb_reg(dm, psd_reg, 0x3000, avg_org);
}
enum rt_status
halrf_psd_init(
struct dm_struct *dm
)
{
enum rt_status ret_status = RT_STATUS_SUCCESS;
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
if (psd->psd_progress)
ret_status = RT_STATUS_PENDING;
else {
psd->psd_progress = 1;
halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
psd->psd_progress = 0;
}
return ret_status;
}
enum rt_status
halrf_psd_query(
struct dm_struct *dm,
u32 *outbuf,
u32 buf_size
)
{
enum rt_status ret_status = RT_STATUS_SUCCESS;
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
if (psd->psd_progress)
ret_status = RT_STATUS_PENDING;
else
PlatformMoveMemory(outbuf, psd->psd_data, 0x400);
return ret_status;
}
enum rt_status
halrf_psd_init_query(
struct dm_struct *dm,
u32 *outbuf,
u32 point,
u32 start_point,
u32 stop_point,
u32 average,
u32 buf_size
)
{
enum rt_status ret_status = RT_STATUS_SUCCESS;
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
psd->point = point;
psd->start_point = start_point;
psd->stop_point = stop_point;
psd->average = average;
if (psd->psd_progress)
ret_status = RT_STATUS_PENDING;
else {
psd->psd_progress = 1;
halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
PlatformMoveMemory(outbuf, psd->psd_data, 0x400);
psd->psd_progress = 0;
}
return ret_status;
}
#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*@===========================================================
* include files
*============================================================
*/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
u64 _sqrt(u64 x)
{
u64 i = 0;
u64 j = x / 2 + 1;
while (i <= j) {
u64 mid = (i + j) / 2;
u64 sq = mid * mid;
if (sq == x)
return mid;
else if (sq < x)
i = mid + 1;
else
j = mid - 1;
}
return j;
}
u32 halrf_get_psd_data(
struct dm_struct *dm,
u32 point)
{
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
u32 psd_val = 0, psd_reg, psd_report, psd_point, psd_start, i, delay_time;
#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) {
if (psd->average == 0)
delay_time = 100;
else
delay_time = 0;
}
#endif
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
if (dm->support_interface == ODM_ITRF_PCIE) {
if (psd->average == 0)
delay_time = 1000;
else
delay_time = 100;
}
#endif
if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
psd_reg = R_0x910;
psd_report = R_0xf44;
} else {
psd_reg = R_0x808;
psd_report = R_0x8b4;
}
if (dm->support_ic_type & ODM_RTL8710B) {
psd_point = 0xeffffc00;
psd_start = 0x10000000;
} else {
psd_point = 0xffbffc00;
psd_start = 0x00400000;
}
psd_val = odm_get_bb_reg(dm, psd_reg, MASKDWORD);
psd_val &= psd_point;
psd_val |= point;
odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val);
psd_val |= psd_start;
odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val);
for (i = 0; i < delay_time; i++)
ODM_delay_us(1);
psd_val = odm_get_bb_reg(dm, psd_report, MASKDWORD);
if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8710B)) {
psd_val &= MASKL3BYTES;
psd_val = psd_val / 32;
} else {
psd_val &= MASKLWORD;
}
return psd_val;
}
void halrf_psd(
struct dm_struct *dm,
u32 point,
u32 start_point,
u32 stop_point,
u32 average)
{
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
u32 i = 0, j = 0, k = 0;
u32 psd_reg, avg_org, point_temp, average_tmp, mode;
u64 data_tatal = 0, data_temp[64] = {0};
psd->buf_size = 256;
mode = average >> 16;
if (mode == 1)
average_tmp = average & 0xffff;
else if (mode == 2)
average_tmp = 1;
if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
psd_reg = R_0x910;
else
psd_reg = R_0x808;
#if 0
dbg_print("[PSD]point=%d, start_point=%d, stop_point=%d, average=%d, average_tmp=%d, buf_size=%d\n",
point, start_point, stop_point, average, average_tmp, psd->buf_size);
#endif
for (i = 0; i < psd->buf_size; i++)
psd->psd_data[i] = 0;
if (dm->support_ic_type & ODM_RTL8710B)
avg_org = odm_get_bb_reg(dm, psd_reg, 0x30000);
else
avg_org = odm_get_bb_reg(dm, psd_reg, 0x3000);
if (mode == 1) {
if (dm->support_ic_type & ODM_RTL8710B)
odm_set_bb_reg(dm, psd_reg, 0x30000, 0x1);
else
odm_set_bb_reg(dm, psd_reg, 0x3000, 0x1);
}
#if 0
if (avg_temp == 0)
avg = 1;
else if (avg_temp == 1)
avg = 8;
else if (avg_temp == 2)
avg = 16;
else if (avg_temp == 3)
avg = 32;
#endif
i = start_point;
while (i < stop_point) {
data_tatal = 0;
if (i >= point)
point_temp = i - point;
else
point_temp = i;
for (k = 0; k < average_tmp; k++) {
data_temp[k] = halrf_get_psd_data(dm, point_temp);
data_tatal = data_tatal + (data_temp[k] * data_temp[k]);
#if 0
if ((k % 20) == 0)
dbg_print("\n ");
dbg_print("0x%x ", data_temp[k]);
#endif
}
#if 0
/*dbg_print("\n");*/
#endif
data_tatal = ((data_tatal * 100) / average_tmp);
psd->psd_data[j] = (u32)_sqrt(data_tatal);
i++;
j++;
}
#if 0
for (i = 0; i < psd->buf_size; i++) {
if ((i % 20) == 0)
dbg_print("\n ");
dbg_print("0x%x ", psd->psd_data[i]);
}
dbg_print("\n\n");
#endif
if (dm->support_ic_type & ODM_RTL8710B)
odm_set_bb_reg(dm, psd_reg, 0x30000, avg_org);
else
odm_set_bb_reg(dm, psd_reg, 0x3000, avg_org);
}
u32 halrf_get_iqk_psd_data(
struct dm_struct *dm,
u32 point)
{
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
u32 psd_val, psd_val1, psd_val2, psd_point, i, delay_time;
#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) {
delay_time = 0;
}
#endif
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
if (dm->support_interface == ODM_ITRF_PCIE) {
delay_time = 150;
}
#endif
psd_point = odm_get_bb_reg(dm, R_0x1b2c, MASKDWORD);
psd_point &= 0xF000FFFF;
point &= 0xFFF;
psd_point = psd_point | (point << 16);
odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, psd_point);
odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x1);
odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x0);
for (i = 0; i < delay_time; i++)
ODM_delay_us(1);
odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00250001);
psd_val1 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
psd_val1 = (psd_val1 & 0x07FF0000) >> 16;
odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x002e0001);
psd_val2 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
psd_val = (psd_val1 << 21) + (psd_val2 >> 11);
return psd_val;
}
void halrf_iqk_psd(
struct dm_struct *dm,
u32 point,
u32 start_point,
u32 stop_point,
u32 average)
{
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
u32 i = 0, j = 0, k = 0;
u32 psd_reg, avg_org, point_temp, average_tmp, mode;
u64 data_tatal = 0, data_temp[64] = {0};
s32 point_8814B;
psd->buf_size = 256;
mode = average >> 16;
if (mode == 1)
average_tmp = average & 0xffff;
else if (mode == 2) {
if (dm->support_ic_type & ODM_RTL8814B)
average_tmp = average & 0xffff;
else
average_tmp = 1;
}
#if 0
DbgPrint("[PSD]point=%d, start_point=%d, stop_point=%d, average=0x%x, average_tmp=%d, buf_size=%d, mode=%d\n",
point, start_point, stop_point, average, average_tmp, psd->buf_size, mode);
#endif
for (i = 0; i < psd->buf_size; i++)
psd->psd_data[i] = 0;
i = start_point;
while (i < stop_point) {
data_tatal = 0;
if (i >= point)
point_temp = i - point;
else
{
if (dm->support_ic_type & ODM_RTL8814B)
{
point_8814B = i -point -1;
point_temp = point_8814B & 0xfff;
}
else
point_temp = i;
}
for (k = 0; k < average_tmp; k++) {
data_temp[k] = halrf_get_iqk_psd_data(dm, point_temp);
/*data_tatal = data_tatal + (data_temp[k] * data_temp[k]);*/
data_tatal = data_tatal + data_temp[k];
#if 0
if ((k % 20) == 0)
DbgPrint("\n ");
DbgPrint("0x%x ", data_temp[k]);
#endif
}
/*data_tatal = ((data_tatal * 100) / average_tmp);*/
/*psd->psd_data[j] = (u32)_sqrt(data_tatal);*/
psd->psd_data[j] = (u32)((data_tatal * 10) / average_tmp);
i++;
j++;
}
#if 0
DbgPrint("\n [iqk psd]psd result:\n");
for (i = 0; i < psd->buf_size; i++) {
if ((i % 20) == 0)
DbgPrint("\n ");
DbgPrint("0x%x ", psd->psd_data[i]);
}
DbgPrint("\n\n");
#endif
}
enum rt_status
halrf_psd_init(
struct dm_struct *dm)
{
enum rt_status ret_status = RT_STATUS_SUCCESS;
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
if (psd->psd_progress) {
ret_status = RT_STATUS_PENDING;
} else {
psd->psd_progress = 1;
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B))
halrf_iqk_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
else
halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
psd->psd_progress = 0;
}
return ret_status;
}
enum rt_status
halrf_psd_query(
struct dm_struct *dm,
u32 *outbuf,
u32 buf_size)
{
enum rt_status ret_status = RT_STATUS_SUCCESS;
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
if (psd->psd_progress)
ret_status = RT_STATUS_PENDING;
else
PlatformMoveMemory(outbuf, psd->psd_data, 0x400);
return ret_status;
}
enum rt_status
halrf_psd_init_query(
struct dm_struct *dm,
u32 *outbuf,
u32 point,
u32 start_point,
u32 stop_point,
u32 average,
u32 buf_size)
{
enum rt_status ret_status = RT_STATUS_SUCCESS;
struct _hal_rf_ *rf = &(dm->rf_table);
struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
psd->point = point;
psd->start_point = start_point;
psd->stop_point = stop_point;
psd->average = average;
if (psd->psd_progress) {
ret_status = RT_STATUS_PENDING;
} else {
psd->psd_progress = 1;
halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
PlatformMoveMemory(outbuf, psd->psd_data, 0x400);
psd->psd_progress = 0;
}
return ret_status;
}
#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/

112
hal/phydm/halrf/halrf_psd.h
View File

@@ -1,60 +1,52 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HALRF_PSD_H__
#define __HALRF_PSD_H__
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
struct _halrf_psd_data {
u32 point;
u32 start_point;
u32 stop_point;
u32 average;
u32 buf_size;
u32 psd_data[256];
u32 psd_progress;
};
enum rt_status
halrf_psd_init (
struct dm_struct *dm
);
enum rt_status
halrf_psd_query (
struct dm_struct *dm,
u32 *outbuf,
u32 buf_size
);
enum rt_status
halrf_psd_init_query(
struct dm_struct *dm,
u32 *outbuf,
u32 point,
u32 start_point,
u32 stop_point,
u32 average,
u32 buf_size
);
#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/
#endif /*#ifndef __HALRF_PSD_H__*/
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HALRF_PSD_H__
#define __HALRF_PSD_H__
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
struct _halrf_psd_data {
u32 point;
u32 start_point;
u32 stop_point;
u32 average;
u32 buf_size;
u32 psd_data[256];
u32 psd_progress;
};
enum rt_status
halrf_psd_init(
struct dm_struct *dm);
enum rt_status
halrf_psd_query(
struct dm_struct *dm,
u32 *outbuf,
u32 buf_size);
enum rt_status
halrf_psd_init_query(
struct dm_struct *dm,
u32 *outbuf,
u32 point,
u32 start_point,
u32 stop_point,
u32 average,
u32 buf_size);
#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/
#endif /*#__HALRF_PSD_H__*/

555
hal/phydm/halrf/halrf_txgapcal.c
View File

@@ -22,282 +22,279 @@
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
void odm_bub_sort(pu4Byte data, u4Byte n)
{
int i, j, temp, sp;
for (i = n - 1;i >= 0;i--) {
sp = 1;
for (j = 0;j < i;j++) {
if (data[j] < data[j + 1]) {
temp = data[j];
data[j] = data[j + 1];
data[j + 1] = temp;
sp = 0;
}
}
if (sp == 1)
break;
}
}
#if (RTL8197F_SUPPORT == 1)
u4Byte
odm_tx_gain_gap_psd_8197f(
void *dm_void,
u1Byte rf_path,
u4Byte rf56
)
{
PDM_ODM_T dm = (PDM_ODM_T)dm_void;
u1Byte i, j;
u4Byte psd_vaule[5], psd_avg_time = 5, psd_vaule_temp;
u4Byte iqk_ctl_addr[2][6] = {{0xe30, 0xe34, 0xe50, 0xe54, 0xe38, 0xe3c},
{0xe50, 0xe54, 0xe30, 0xe34, 0xe58, 0xe5c}};
u4Byte psd_finish_bit[2] = {0x04000000, 0x20000000};
u4Byte psd_fail_bit[2] = {0x08000000, 0x40000000};
u4Byte psd_cntl_value[2][2] = {{0x38008c1c, 0x10008c1c},
{0x38008c2c, 0x10008c2c}};
u4Byte psd_report_addr[2] = {0xea0, 0xec0};
odm_set_rf_reg(dm, rf_path, 0xdf, bRFRegOffsetMask, 0x00e02);
ODM_delay_us(100);
odm_set_bb_reg(dm, 0xe28, 0xffffffff, 0x0);
odm_set_rf_reg(dm, rf_path, 0x56, 0xfff, rf56);
while(rf56 != (odm_get_rf_reg(dm, rf_path, 0x56, 0xfff)))
odm_set_rf_reg(dm, rf_path, 0x56, 0xfff, rf56);
odm_set_bb_reg(dm, 0xd94, 0xffffffff, 0x44FFBB44);
odm_set_bb_reg(dm, 0xe70, 0xffffffff, 0x00400040);
odm_set_bb_reg(dm, 0xc04, 0xffffffff, 0x6f005403);
odm_set_bb_reg(dm, 0xc08, 0xffffffff, 0x000804e4);
odm_set_bb_reg(dm, 0x874, 0xffffffff, 0x04203400);
odm_set_bb_reg(dm, 0xe28, 0xffffffff, 0x80800000);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][0], 0xffffffff, psd_cntl_value[rf_path][0]);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][1], 0xffffffff, psd_cntl_value[rf_path][1]);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][2], 0xffffffff, psd_cntl_value[rf_path][0]);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][3], 0xffffffff, psd_cntl_value[rf_path][0]);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][4], 0xffffffff, 0x8215001F);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][5], 0xffffffff, 0x2805001F);
odm_set_bb_reg(dm, 0xe40, 0xffffffff, 0x81007C00);
odm_set_bb_reg(dm, 0xe44, 0xffffffff, 0x81004800);
odm_set_bb_reg(dm, 0xe4c, 0xffffffff, 0x0046a8d0);
for (i = 0; i < psd_avg_time; i++) {
for(j = 0; j < 1000 ; j++) {
odm_set_bb_reg(dm, 0xe48, 0xffffffff, 0xfa005800);
odm_set_bb_reg(dm, 0xe48, 0xffffffff, 0xf8005800);
while(!odm_get_bb_reg(dm, 0xeac, psd_finish_bit[rf_path])); /*wait finish bit*/
if (!odm_get_bb_reg(dm, 0xeac, psd_fail_bit[rf_path])) { /*check fail bit*/
psd_vaule[i] = odm_get_bb_reg(dm, psd_report_addr[rf_path], 0xffffffff);
if (psd_vaule[i] > 0xffff)
break;
}
}
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x time=%d psd_vaule=0x%x\n",
odm_get_rf_reg(dm, rf_path, 0x0, 0xff),
rf56, odm_get_rf_reg(dm, rf_path, 0x56, 0xfff), j, psd_vaule[i]);
}
odm_bub_sort(psd_vaule, psd_avg_time);
psd_vaule_temp = psd_vaule[(UINT)(psd_avg_time / 2)];
odm_set_bb_reg(dm, 0xd94, 0xffffffff, 0x44BBBB44);
odm_set_bb_reg(dm, 0xe70, 0xffffffff, 0x80408040);
odm_set_bb_reg(dm, 0xc04, 0xffffffff, 0x6f005433);
odm_set_bb_reg(dm, 0xc08, 0xffffffff, 0x000004e4);
odm_set_bb_reg(dm, 0x874, 0xffffffff, 0x04003400);
odm_set_bb_reg(dm, 0xe28, 0xffffffff, 0x00000000);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x psd_vaule_temp=0x%x\n",
odm_get_rf_reg(dm, rf_path, 0x0, 0xff),
rf56, odm_get_rf_reg(dm, rf_path, 0x56, 0xfff), psd_vaule_temp);
odm_set_rf_reg(dm, rf_path, 0xdf, bRFRegOffsetMask, 0x00602);
return psd_vaule_temp;
}
void
odm_tx_gain_gap_calibration_8197f(
void *dm_void
)
{
PDM_ODM_T dm = (PDM_ODM_T)dm_void;
u1Byte rf_path, rf0_idx, rf0_idx_current, rf0_idx_next, i, delta_gain_retry = 3;
s1Byte delta_gain_gap_pre, delta_gain_gap[2][11];
u4Byte rf56_current, rf56_next, psd_value_current, psd_value_next;
u4Byte psd_gap, rf56_current_temp[2][11];
s4Byte rf33[2][11];
memset(rf33, 0x0, sizeof(rf33));
for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {
if (rf_path == RF_PATH_A)
odm_set_bb_reg(dm, 0x88c, (BIT(21) | BIT(20)), 0x3); /*disable 3-wire*/
else if (rf_path == RF_PATH_B)
odm_set_bb_reg(dm, 0x88c, (BIT(23) | BIT(22)), 0x3); /*disable 3-wire*/
ODM_delay_us(100);
for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {
rf0_idx_current = 3 * (rf0_idx - 1) + 1;
odm_set_rf_reg(dm, rf_path, 0x0, 0xff, rf0_idx_current);
ODM_delay_us(100);
rf56_current_temp[rf_path][rf0_idx] = odm_get_rf_reg(dm, rf_path, 0x56, 0xfff);
rf56_current = rf56_current_temp[rf_path][rf0_idx];
rf0_idx_next = 3 * rf0_idx + 1;
odm_set_rf_reg(dm, rf_path, 0x0, 0xff, rf0_idx_next);
ODM_delay_us(100);
rf56_next= odm_get_rf_reg(dm, rf_path, 0x56, 0xfff);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf56_current[%d][%d]=0x%x rf56_next[%d][%d]=0x%x\n",
rf_path, rf0_idx, rf56_current, rf_path, rf0_idx, rf56_next);
if ((rf56_current >> 5) == (rf56_next >> 5)) {
delta_gain_gap[rf_path][rf0_idx] = 0;
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf56_current[11:5] == rf56_next[%d][%d][11:5]=0x%x delta_gain_gap[%d][%d]=%d\n",
rf_path, rf0_idx, (rf56_next >> 5), rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx]);
continue;
}
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf56_current[%d][%d][11:5]=0x%x != rf56_next[%d][%d][11:5]=0x%x\n",
rf_path, rf0_idx, (rf56_current >> 5), rf_path, rf0_idx, (rf56_next >> 5));
for (i = 0; i < delta_gain_retry; i++) {
psd_value_current = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_current);
psd_value_next = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_next - 2);
psd_gap = psd_value_next / (psd_value_current / 1000);
#if 0
if (psd_gap > 1413)
delta_gain_gap[rf_path][rf0_idx] = 1;
else if (psd_gap > 1122)
delta_gain_gap[rf_path][rf0_idx] = 0;
else
delta_gain_gap[rf_path][rf0_idx] = -1;
#endif
if (psd_gap > 1445)
delta_gain_gap[rf_path][rf0_idx] = 1;
else if (psd_gap > 1096)
delta_gain_gap[rf_path][rf0_idx] = 0;
else
delta_gain_gap[rf_path][rf0_idx] = -1;
if (i == 0)
delta_gain_gap_pre = delta_gain_gap[rf_path][rf0_idx];
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] psd_value_current=0x%x psd_value_next=0x%x psd_value_next/psd_value_current=%d delta_gain_gap[%d][%d]=%d\n",
psd_value_current, psd_value_next, psd_gap, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx]);
if ((i == 0) && (delta_gain_gap[rf_path][rf0_idx] == 0))
break;
if (delta_gain_gap_pre != delta_gain_gap[rf_path][rf0_idx]) {
delta_gain_gap[rf_path][rf0_idx] = 0;
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] delta_gain_gap_pre(%d) != delta_gain_gap[%d][%d](%d) time=%d\n",
delta_gain_gap_pre, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx], i);
break;
} else {
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] delta_gain_gap_pre(%d) == delta_gain_gap[%d][%d](%d) time=%d\n",
delta_gain_gap_pre, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx], i);
}
}
}
if (rf_path == RF_PATH_A)
odm_set_bb_reg(dm, 0x88c, (BIT(21) | BIT(20)), 0x0); /*enable 3-wire*/
else if (rf_path == RF_PATH_B)
odm_set_bb_reg(dm, 0x88c, (BIT(23) | BIT(22)), 0x0); /*enable 3-wire*/
ODM_delay_us(100);
}
/*odm_set_bb_reg(dm, 0x88c, (BIT(23) | BIT(22) | BIT(21) | BIT(20)), 0x0);*/ /*enable 3-wire*/
for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {
odm_set_rf_reg(dm, rf_path, 0xef, bRFRegOffsetMask, 0x00100);
for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {
rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + (rf56_current_temp[rf_path][rf0_idx] & 0x1f);
for (i = rf0_idx; i <= 10; i++)
rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + delta_gain_gap[rf_path][i];
if (rf33[rf_path][rf0_idx] >= 0x1d)
rf33[rf_path][rf0_idx] = 0x1d;
else if (rf33[rf_path][rf0_idx] <= 0x2)
rf33[rf_path][rf0_idx] = 0x2;
rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + ((rf0_idx - 1) * 0x4000) + (rf56_current_temp[rf_path][rf0_idx] & 0xfffe0);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf56[%d][%d]=0x%05x rf33[%d][%d]=0x%05x\n", rf_path, rf0_idx, rf56_current_temp[rf_path][rf0_idx], rf_path, rf0_idx, rf33[rf_path][rf0_idx]);
odm_set_rf_reg(dm, rf_path, 0x33, bRFRegOffsetMask, rf33[rf_path][rf0_idx]);
}
odm_set_rf_reg(dm, rf_path, 0xef, bRFRegOffsetMask, 0x00000);
}
}
#endif
void
odm_tx_gain_gap_calibration(
void *dm_void
)
{
PDM_ODM_T dm = (PDM_ODM_T)dm_void;
#if (RTL8197F_SUPPORT == 1)
if (dm->SupportICType & ODM_RTL8197F)
odm_tx_gain_gap_calibration_8197f(dm_void);
#endif
}
#include "mp_precomp.h"
#include "phydm_precomp.h"
void odm_bub_sort(u32 *data, u32 n)
{
int i, j, temp, sp;
for (i = n - 1; i >= 0; i--) {
sp = 1;
for (j = 0; j < i; j++) {
if (data[j] < data[j + 1]) {
temp = data[j];
data[j] = data[j + 1];
data[j + 1] = temp;
sp = 0;
}
}
if (sp == 1)
break;
}
}
#if (RTL8197F_SUPPORT == 1)
u4Byte
odm_tx_gain_gap_psd_8197f(
void *dm_void,
u1Byte rf_path,
u4Byte rf56)
{
PDM_ODM_T dm = (PDM_ODM_T)dm_void;
u1Byte i, j;
u4Byte psd_vaule[5], psd_avg_time = 5, psd_vaule_temp;
u4Byte iqk_ctl_addr[2][6] = {{0xe30, 0xe34, 0xe50, 0xe54, 0xe38, 0xe3c},
{0xe50, 0xe54, 0xe30, 0xe34, 0xe58, 0xe5c}};
u4Byte psd_finish_bit[2] = {0x04000000, 0x20000000};
u4Byte psd_fail_bit[2] = {0x08000000, 0x40000000};
u4Byte psd_cntl_value[2][2] = {{0x38008c1c, 0x10008c1c},
{0x38008c2c, 0x10008c2c}};
u4Byte psd_report_addr[2] = {0xea0, 0xec0};
odm_set_rf_reg(dm, rf_path, RF_0xdf, bRFRegOffsetMask, 0x00e02);
ODM_delay_us(100);
odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x0);
odm_set_rf_reg(dm, rf_path, RF_0x56, 0xfff, rf56);
while (rf56 != (odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff)))
odm_set_rf_reg(dm, rf_path, RF_0x56, 0xfff, rf56);
odm_set_bb_reg(dm, R_0xd94, 0xffffffff, 0x44FFBB44);
odm_set_bb_reg(dm, R_0xe70, 0xffffffff, 0x00400040);
odm_set_bb_reg(dm, R_0xc04, 0xffffffff, 0x6f005403);
odm_set_bb_reg(dm, R_0xc08, 0xffffffff, 0x000804e4);
odm_set_bb_reg(dm, R_0x874, 0xffffffff, 0x04203400);
odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x80800000);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][0], 0xffffffff, psd_cntl_value[rf_path][0]);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][1], 0xffffffff, psd_cntl_value[rf_path][1]);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][2], 0xffffffff, psd_cntl_value[rf_path][0]);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][3], 0xffffffff, psd_cntl_value[rf_path][0]);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][4], 0xffffffff, 0x8215001F);
odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][5], 0xffffffff, 0x2805001F);
odm_set_bb_reg(dm, R_0xe40, 0xffffffff, 0x81007C00);
odm_set_bb_reg(dm, R_0xe44, 0xffffffff, 0x81004800);
odm_set_bb_reg(dm, R_0xe4c, 0xffffffff, 0x0046a8d0);
for (i = 0; i < psd_avg_time; i++) {
for (j = 0; j < 1000; j++) {
odm_set_bb_reg(dm, R_0xe48, 0xffffffff, 0xfa005800);
odm_set_bb_reg(dm, R_0xe48, 0xffffffff, 0xf8005800);
while (!odm_get_bb_reg(dm, R_0xeac, psd_finish_bit[rf_path]))
; /*wait finish bit*/
if (!odm_get_bb_reg(dm, R_0xeac, psd_fail_bit[rf_path])) { /*check fail bit*/
psd_vaule[i] = odm_get_bb_reg(dm, psd_report_addr[rf_path], 0xffffffff);
if (psd_vaule[i] > 0xffff)
break;
}
}
RF_DBG(dm, DBG_RF_IQK,
"[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x time=%d psd_vaule=0x%x\n",
odm_get_rf_reg(dm, rf_path, RF_0x0, 0xff), rf56,
odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff), j,
psd_vaule[i]);
}
odm_bub_sort(psd_vaule, psd_avg_time);
psd_vaule_temp = psd_vaule[(UINT)(psd_avg_time / 2)];
odm_set_bb_reg(dm, R_0xd94, 0xffffffff, 0x44BBBB44);
odm_set_bb_reg(dm, R_0xe70, 0xffffffff, 0x80408040);
odm_set_bb_reg(dm, R_0xc04, 0xffffffff, 0x6f005433);
odm_set_bb_reg(dm, R_0xc08, 0xffffffff, 0x000004e4);
odm_set_bb_reg(dm, R_0x874, 0xffffffff, 0x04003400);
odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x00000000);
RF_DBG(dm, DBG_RF_IQK,
"[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x psd_vaule_temp=0x%x\n",
odm_get_rf_reg(dm, rf_path, RF_0x0, 0xff), rf56,
odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff), psd_vaule_temp);
odm_set_rf_reg(dm, rf_path, RF_0xdf, bRFRegOffsetMask, 0x00602);
return psd_vaule_temp;
}
void odm_tx_gain_gap_calibration_8197f(
void *dm_void)
{
PDM_ODM_T dm = (PDM_ODM_T)dm_void;
u1Byte rf_path, rf0_idx, rf0_idx_current, rf0_idx_next, i, delta_gain_retry = 3;
s1Byte delta_gain_gap_pre, delta_gain_gap[2][11];
u4Byte rf56_current, rf56_next, psd_value_current, psd_value_next;
u4Byte psd_gap, rf56_current_temp[2][11];
s4Byte rf33[2][11];
memset(rf33, 0x0, sizeof(rf33));
for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {
if (rf_path == RF_PATH_A)
odm_set_bb_reg(dm, R_0x88c, (BIT(21) | BIT(20)), 0x3); /*disable 3-wire*/
else if (rf_path == RF_PATH_B)
odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22)), 0x3); /*disable 3-wire*/
ODM_delay_us(100);
for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {
rf0_idx_current = 3 * (rf0_idx - 1) + 1;
odm_set_rf_reg(dm, rf_path, RF_0x0, 0xff, rf0_idx_current);
ODM_delay_us(100);
rf56_current_temp[rf_path][rf0_idx] = odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff);
rf56_current = rf56_current_temp[rf_path][rf0_idx];
rf0_idx_next = 3 * rf0_idx + 1;
odm_set_rf_reg(dm, rf_path, RF_0x0, 0xff, rf0_idx_next);
ODM_delay_us(100);
rf56_next = odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff);
RF_DBG(dm, DBG_RF_IQK,
"[TGGC] rf56_current[%d][%d]=0x%x rf56_next[%d][%d]=0x%x\n",
rf_path, rf0_idx, rf56_current, rf_path, rf0_idx,
rf56_next);
if ((rf56_current >> 5) == (rf56_next >> 5)) {
delta_gain_gap[rf_path][rf0_idx] = 0;
RF_DBG(dm, DBG_RF_IQK,
"[TGGC] rf56_current[11:5] == rf56_next[%d][%d][11:5]=0x%x delta_gain_gap[%d][%d]=%d\n",
rf_path, rf0_idx, (rf56_next >> 5),
rf_path, rf0_idx,
delta_gain_gap[rf_path][rf0_idx]);
continue;
}
RF_DBG(dm, DBG_RF_IQK,
"[TGGC] rf56_current[%d][%d][11:5]=0x%x != rf56_next[%d][%d][11:5]=0x%x\n",
rf_path, rf0_idx, (rf56_current >> 5), rf_path,
rf0_idx, (rf56_next >> 5));
for (i = 0; i < delta_gain_retry; i++) {
psd_value_current = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_current);
psd_value_next = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_next - 2);
psd_gap = psd_value_next / (psd_value_current / 1000);
#if 0
if (psd_gap > 1413)
delta_gain_gap[rf_path][rf0_idx] = 1;
else if (psd_gap > 1122)
delta_gain_gap[rf_path][rf0_idx] = 0;
else
delta_gain_gap[rf_path][rf0_idx] = -1;
#endif
if (psd_gap > 1445)
delta_gain_gap[rf_path][rf0_idx] = 1;
else if (psd_gap > 1096)
delta_gain_gap[rf_path][rf0_idx] = 0;
else
delta_gain_gap[rf_path][rf0_idx] = -1;
if (i == 0)
delta_gain_gap_pre = delta_gain_gap[rf_path][rf0_idx];
RF_DBG(dm, DBG_RF_IQK,
"[TGGC] psd_value_current=0x%x psd_value_next=0x%x psd_value_next/psd_value_current=%d delta_gain_gap[%d][%d]=%d\n",
psd_value_current, psd_value_next,
psd_gap, rf_path, rf0_idx,
delta_gain_gap[rf_path][rf0_idx]);
if (i == 0 && delta_gain_gap[rf_path][rf0_idx] == 0)
break;
if (delta_gain_gap_pre != delta_gain_gap[rf_path][rf0_idx]) {
delta_gain_gap[rf_path][rf0_idx] = 0;
RF_DBG(dm, DBG_RF_IQK, "[TGGC] delta_gain_gap_pre(%d) != delta_gain_gap[%d][%d](%d) time=%d\n",
delta_gain_gap_pre, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx], i);
break;
}
RF_DBG(dm, DBG_RF_IQK,
"[TGGC] delta_gain_gap_pre(%d) == delta_gain_gap[%d][%d](%d) time=%d\n",
delta_gain_gap_pre, rf_path, rf0_idx,
delta_gain_gap[rf_path][rf0_idx], i);
}
}
if (rf_path == RF_PATH_A)
odm_set_bb_reg(dm, R_0x88c, (BIT(21) | BIT(20)), 0x0); /*enable 3-wire*/
else if (rf_path == RF_PATH_B)
odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22)), 0x0); /*enable 3-wire*/
ODM_delay_us(100);
}
#if 0
/*odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22) | BIT(21) | BIT(20)), 0x0);*/ /*enable 3-wire*/
#endif
for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {
odm_set_rf_reg(dm, rf_path, RF_0xef, bRFRegOffsetMask, 0x00100);
for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {
rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + (rf56_current_temp[rf_path][rf0_idx] & 0x1f);
for (i = rf0_idx; i <= 10; i++)
rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + delta_gain_gap[rf_path][i];
if (rf33[rf_path][rf0_idx] >= 0x1d)
rf33[rf_path][rf0_idx] = 0x1d;
else if (rf33[rf_path][rf0_idx] <= 0x2)
rf33[rf_path][rf0_idx] = 0x2;
rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + ((rf0_idx - 1) * 0x4000) + (rf56_current_temp[rf_path][rf0_idx] & 0xfffe0);
RF_DBG(dm, DBG_RF_IQK,
"[TGGC] rf56[%d][%d]=0x%05x rf33[%d][%d]=0x%05x\n",
rf_path, rf0_idx,
rf56_current_temp[rf_path][rf0_idx], rf_path,
rf0_idx, rf33[rf_path][rf0_idx]);
odm_set_rf_reg(dm, rf_path, RF_0x33, bRFRegOffsetMask, rf33[rf_path][rf0_idx]);
}
odm_set_rf_reg(dm, rf_path, RF_0xef, bRFRegOffsetMask, 0x00000);
}
}
#endif
void odm_tx_gain_gap_calibration(void *dm_void)
{
PDM_ODM_T dm = (PDM_ODM_T)dm_void;
#if (RTL8197F_SUPPORT == 1)
if (dm->SupportICType & ODM_RTL8197F)
odm_tx_gain_gap_calibration_8197f(dm_void);
#endif
}

12
hal/phydm/halrf/halrf_txgapcal.h
View File

@@ -22,8 +22,10 @@
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
void
odm_tx_gain_gap_calibration(
void *dm_void
);
#ifndef __HALRF_TXGAPCAL_H__
#define __HALRF_TXGAPCAL_H__
void odm_tx_gain_gap_calibration(void *dm_void);
#endif /*__HALRF_TXGAPCAL_H__*/

559
hal/phydm/halrf/rtl8822b/halrf_8822b.c
View File

@@ -25,111 +25,185 @@
#include "mp_precomp.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if RT_PLATFORM==PLATFORM_MACOSX
#include "phydm_precomp.h"
#else
#include "../phydm_precomp.h"
#endif
#if RT_PLATFORM == PLATFORM_MACOSX
#include "phydm_precomp.h"
#else
#include "../phydm_precomp.h"
#endif
#else
#include "../../phydm_precomp.h"
#endif
#if (RTL8822B_SUPPORT == 1)
void
halrf_rf_lna_setting_8822b(
struct dm_struct *dm_void,
enum phydm_lna_set type
)
void halrf_rf_lna_setting_8822b(struct dm_struct *dm_void,
enum halrf_lna_set type)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 path = 0x0;
for (path = 0x0; path < 2; path++)
if (type == phydm_lna_disable) {
if (type == HALRF_LNA_DISABLE) {
/*S0*/
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x1);
odm_set_rf_reg(dm, (enum rf_path)path, 0x33, RFREGOFFSETMASK, 0x00003);
odm_set_rf_reg(dm, (enum rf_path)path, 0x3e, RFREGOFFSETMASK, 0x00064);
odm_set_rf_reg(dm, (enum rf_path)path, 0x3f, RFREGOFFSETMASK, 0x0afce);
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x0);
} else if (type == phydm_lna_enable) {
odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19),
0x1);
odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33,
RFREGOFFSETMASK, 0x00003);
odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e,
RFREGOFFSETMASK, 0x00064);
odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f,
RFREGOFFSETMASK, 0x0afce);
odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19),
0x0);
} else if (type == HALRF_LNA_ENABLE) {
/*S0*/
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x1);
odm_set_rf_reg(dm, (enum rf_path)path, 0x33, RFREGOFFSETMASK, 0x00003);
odm_set_rf_reg(dm, (enum rf_path)path, 0x3e, RFREGOFFSETMASK, 0x00064);
odm_set_rf_reg(dm, (enum rf_path)path, 0x3f, RFREGOFFSETMASK, 0x1afce);
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x0);
odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19),
0x1);
odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33,
RFREGOFFSETMASK, 0x00003);
odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e,
RFREGOFFSETMASK, 0x00064);
odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f,
RFREGOFFSETMASK, 0x1afce);
odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19),
0x0);
}
}
boolean
get_mix_mode_tx_agc_bb_swing_offset_8822b(
void *dm_void,
enum pwrtrack_method method,
u8 rf_path,
u8 tx_power_index_offest
)
boolean get_mix_mode_tx_agc_bb_swing_offset_8822b(void *dm_void,
enum pwrtrack_method method,
u8 rf_path,
u8 tx_power_index_offset)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
u8 bb_swing_upper_bound = cali_info->default_ofdm_index + 10;
u8 bb_swing_lower_bound = 0;
u8 bb_swing_upper_bound = cali_info->default_ofdm_index + 10;
u8 bb_swing_lower_bound = 0;
s8 tx_agc_index = 0;
u8 tx_bb_swing_index = cali_info->default_ofdm_index;
s8 tx_agc_index = 0;
u8 tx_bb_swing_index = cali_info->default_ofdm_index;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"Path_%d cali_info->absolute_ofdm_swing_idx[rf_path]=%d, tx_power_index_offest=%d\n",
rf_path, cali_info->absolute_ofdm_swing_idx[rf_path], tx_power_index_offest);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"Path_%d absolute_ofdm_swing[%d]=%d tx_power_idx_offset=%d\n",
rf_path, rf_path, cali_info->absolute_ofdm_swing_idx[rf_path],
tx_power_index_offset);
if (tx_power_index_offest > 0XF)
tx_power_index_offest = 0XF;
if (tx_power_index_offset > 0XF)
tx_power_index_offset = 0XF;
if (cali_info->absolute_ofdm_swing_idx[rf_path] >= 0 && cali_info->absolute_ofdm_swing_idx[rf_path] <= tx_power_index_offest) {
if (cali_info->absolute_ofdm_swing_idx[rf_path] >= 0 &&
cali_info->absolute_ofdm_swing_idx[rf_path] <=
tx_power_index_offset) {
tx_agc_index = cali_info->absolute_ofdm_swing_idx[rf_path];
tx_bb_swing_index = cali_info->default_ofdm_index;
} else if (cali_info->absolute_ofdm_swing_idx[rf_path] > tx_power_index_offest) {
tx_agc_index = tx_power_index_offest;
cali_info->remnant_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path] - tx_power_index_offest;
tx_bb_swing_index = cali_info->default_ofdm_index + cali_info->remnant_ofdm_swing_idx[rf_path];
} else if (cali_info->absolute_ofdm_swing_idx[rf_path] >
tx_power_index_offset) {
tx_agc_index = tx_power_index_offset;
cali_info->remnant_ofdm_swing_idx[rf_path] =
cali_info->absolute_ofdm_swing_idx[rf_path] -
tx_power_index_offset;
tx_bb_swing_index = cali_info->default_ofdm_index +
cali_info->remnant_ofdm_swing_idx[rf_path];
if (tx_bb_swing_index > bb_swing_upper_bound)
tx_bb_swing_index = bb_swing_upper_bound;
} else {
tx_agc_index = 0;
if (cali_info->default_ofdm_index > (cali_info->absolute_ofdm_swing_idx[rf_path] * (-1)))
tx_bb_swing_index = cali_info->default_ofdm_index + cali_info->absolute_ofdm_swing_idx[rf_path];
if (cali_info->default_ofdm_index >
(cali_info->absolute_ofdm_swing_idx[rf_path] * (-1)))
tx_bb_swing_index =
cali_info->default_ofdm_index +
cali_info->absolute_ofdm_swing_idx[rf_path];
else
tx_bb_swing_index = bb_swing_lower_bound;
if (tx_bb_swing_index < bb_swing_lower_bound)
if (tx_bb_swing_index < bb_swing_lower_bound)
tx_bb_swing_index = bb_swing_lower_bound;
}
cali_info->absolute_ofdm_swing_idx[rf_path] = tx_agc_index;
cali_info->bb_swing_idx_ofdm[rf_path] = tx_bb_swing_index;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"MixMode Offset Path_%d cali_info->absolute_ofdm_swing_idx[rf_path]=%d cali_info->bb_swing_idx_ofdm[rf_path]=%d tx_power_index_offest=%d\n",
rf_path, cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->bb_swing_idx_ofdm[rf_path], tx_power_index_offest);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"absolute_ofdm[%d]=%d bb_swing_ofdm[%d]=%d tx_pwr_offset=%d\n",
rf_path, cali_info->absolute_ofdm_swing_idx[rf_path],
rf_path, cali_info->bb_swing_idx_ofdm[rf_path],
tx_power_index_offset);
return true;
}
void odm_pwrtrack_method_set_pwr8822b(void *dm_void,
enum pwrtrack_method method,
u8 rf_path, u8 tx_pwr_idx_offset)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
u32 tmp_reg1, tmp_reg2, tmp_reg3;
u8 bb_swing_idx_ofdm = cali_info->bb_swing_idx_ofdm[rf_path];
void
odm_tx_pwr_track_set_pwr8822b(
void *dm_void,
enum pwrtrack_method method,
u8 rf_path,
u8 channel_mapped_index
)
/*use for mp driver clean power tracking status*/
if (method == BBSWING) {
if (rf_path == RF_PATH_A) {
tmp_reg1 = R_0xc94;
tmp_reg2 = REG_A_TX_SCALE_JAGUAR;
} else if (rf_path == RF_PATH_B) {
tmp_reg1 = R_0xe94;
tmp_reg2 = REG_B_TX_SCALE_JAGUAR;
} else {
return;
}
odm_set_bb_reg(dm, tmp_reg1,
BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25),
cali_info->absolute_ofdm_swing_idx[rf_path]);
odm_set_bb_reg(dm, tmp_reg2, 0xFFE00000,
tx_scaling_table_jaguar[bb_swing_idx_ofdm]);
} else if (method == MIX_MODE) {
if (rf_path == RF_PATH_A) {
tmp_reg1 = R_0xc94;
tmp_reg2 = REG_A_TX_SCALE_JAGUAR;
tmp_reg3 = 0xc1c;
} else if (rf_path == RF_PATH_B) {
tmp_reg1 = R_0xe94;
tmp_reg2 = REG_B_TX_SCALE_JAGUAR;
tmp_reg3 = 0xe1c;
} else {
return;
}
get_mix_mode_tx_agc_bb_swing_offset_8822b(dm,
method,
rf_path,
tx_pwr_idx_offset);
bb_swing_idx_ofdm = cali_info->bb_swing_idx_ofdm[rf_path];
odm_set_bb_reg(dm, tmp_reg1,
BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25),
cali_info->absolute_ofdm_swing_idx[rf_path]);
odm_set_bb_reg(dm, tmp_reg2, 0xFFE00000,
tx_scaling_table_jaguar[bb_swing_idx_ofdm]);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"TXAGC(%x)=0x%x BBSw(%x)=0x%x BBSwIdx=%d rf_path=%d\n",
tmp_reg1,
odm_get_bb_reg(dm, tmp_reg1,
BIT(29) | BIT(28) | BIT(27) |
BIT(26) | BIT(25)),
tmp_reg3, odm_get_bb_reg(dm, tmp_reg3, 0xFFE00000),
cali_info->bb_swing_idx_ofdm[rf_path], rf_path);
}
}
void odm_tx_pwr_track_set_pwr8822b(void *dm_void, enum pwrtrack_method method,
u8 rf_path, u8 channel_mapped_index)
{
#if 0
struct dm_struct *dm = (struct dm_struct *)dm_void;
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
u8 channel = *dm->channel;
u8 band_width = hal_data->current_channel_bw;
u8 tx_power_index = 0;
@@ -138,7 +212,7 @@ odm_tx_pwr_track_set_pwr8822b(
PHALMAC_PWR_TRACKING_OPTION p_pwr_tracking_opt = &(cali_info->HALMAC_PWR_TRACKING_INFO);
if (*(dm->mp_mode) == true) {
if (*dm->mp_mode == true) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
@@ -166,12 +240,16 @@ odm_tx_pwr_track_set_pwr8822b(
tx_rate = (u8) rate;
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__, tx_rate);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__,
tx_rate);
tx_power_index = phy_get_tx_power_index(adapter, (enum rf_path) rf_path, tx_rate, band_width, channel);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"type=%d tx_power_index=%d cali_info->absolute_ofdm_swing_idx=%d cali_info->default_ofdm_index=%d rf_path=%d\n", method, tx_power_index, cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->default_ofdm_index, rf_path);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"type=%d tx_power_index=%d cali_info->absolute_ofdm_swing_idx=%d cali_info->default_ofdm_index=%d rf_path=%d\n",
method, tx_power_index,
cali_info->absolute_ofdm_swing_idx[rf_path],
cali_info->default_ofdm_index, rf_path);
p_pwr_tracking_opt->type = method;
p_pwr_tracking_opt->bbswing_index = cali_info->default_ofdm_index;
@@ -185,44 +263,39 @@ odm_tx_pwr_track_set_pwr8822b(
status = hal_mac_send_power_tracking_info(&GET_HAL_MAC_INFO(adapter), p_pwr_tracking_opt);
if (status == RT_STATUS_SUCCESS) {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"path A 0xC94=0x%X 0xC1C=0x%X\n",
odm_get_bb_reg(dm, 0xC94, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)),
odm_get_bb_reg(dm, 0xC1C, 0xFFE00000)
);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"path B 0xE94=0x%X 0xE1C=0x%X\n",
odm_get_bb_reg(dm, 0xE94, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)),
odm_get_bb_reg(dm, 0xE1C, 0xFFE00000)
);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"path A 0xC94=0x%X 0xC1C=0x%X\n",
odm_get_bb_reg(dm, R_0xc94,
BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)),
odm_get_bb_reg(dm, R_0xc1c, 0xFFE00000));
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"path B 0xE94=0x%X 0xE1C=0x%X\n",
odm_get_bb_reg(dm, R_0xe94,
BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)),
odm_get_bb_reg(dm, R_0xe1c, 0xFFE00000));
} else {
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
"Power Tracking to FW Fail ret code = %d\n", status);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"Power Tracking to FW Fail ret code = %d\n",
status);
}
}
#endif
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
struct _hal_rf_ *rf = &dm->rf_table;
u8 tx_power_index_offest = 0;
u8 tx_power_index = 0;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
struct rtl_phy *rtlphy = &rtlpriv->phy;
u8 channel = rtlphy->current_channel;
u8 band_width = rtlphy->current_chan_bw;
#else
struct _ADAPTER *adapter = (PADAPTER)dm->adapter;
u8 channel = *dm->channel;
u8 band_width = *dm->band_width;
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
struct _ADAPTER *adapter = dm->adapter;
#endif
u8 tx_rate = 0xFF;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
struct _hal_rf_ *rf = &dm->rf_table;
u8 tx_pwr_idx_offset = 0;
u8 tx_pwr_idx = 0;
u8 mpt_rate_index = 0;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
u8 channel = *dm->channel;
u8 band_width = *dm->band_width;
u8 tx_rate = 0xFF;
if (*dm->mp_mode == true) {
if (*dm->mp_mode == 1) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
@@ -232,17 +305,20 @@ odm_tx_pwr_track_set_pwr8822b(
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
#ifdef CONFIG_MP_INCLUDED
PMPT_CONTEXT p_mpt_ctx = &adapter->mppriv.mpt_ctx;
if (rf->mp_rate_index)
mpt_rate_index = *rf->mp_rate_index;
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
tx_rate = mpt_to_mgnt_rate(mpt_rate_index);
#endif
#endif
#endif
} else {
u16 rate = *dm->forced_data_rate;
u16 rate = *dm->forced_data_rate;
if (!rate) { /*auto rate*/
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
struct _ADAPTER *adapter = dm->adapter;
tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
tx_rate = dm->tx_rate;
@@ -252,164 +328,136 @@ odm_tx_pwr_track_set_pwr8822b(
else
tx_rate = rf->p_rate_index;
#endif
} else /*force rate*/
tx_rate = (u8) rate;
} else { /*force rate*/
tx_rate = (u8)rate;
}
}
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__, tx_rate);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__,
tx_rate);
#endif
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"pRF->default_ofdm_index=%d pRF->default_cck_index=%d\n", cali_info->default_ofdm_index, cali_info->default_cck_index);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"pRF->default_ofdm_index=%d pRF->default_cck_index=%d\n",
cali_info->default_ofdm_index, cali_info->default_cck_index);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"pRF->absolute_ofdm_swing_idx=%d pRF->remnant_ofdm_swing_idx=%d pRF->absolute_cck_swing_idx=%d pRF->remnant_cck_swing_idx=%d rf_path=%d\n",
cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->remnant_ofdm_swing_idx[rf_path], cali_info->absolute_cck_swing_idx[rf_path], cali_info->remnant_cck_swing_idx, rf_path);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"absolute_ofdm_swing_idx=%d remnant_ofdm_swing_idx=%d path=%d\n",
cali_info->absolute_ofdm_swing_idx[rf_path],
cali_info->remnant_ofdm_swing_idx[rf_path], rf_path);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"absolute_cck_swing_idx=%d remnant_cck_swing_idx=%d path=%d\n",
cali_info->absolute_cck_swing_idx[rf_path],
cali_info->remnant_cck_swing_idx, rf_path);
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
tx_power_index = odm_get_tx_power_index(dm, (enum rf_path) rf_path, tx_rate, (enum channel_width)band_width, channel);
tx_pwr_idx = odm_get_tx_power_index(dm, (enum rf_path)rf_path, tx_rate, (enum channel_width)band_width, channel);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
tx_power_index = odm_get_tx_power_index(dm, (enum rf_path) rf_path, tx_rate, band_width, channel);
tx_pwr_idx = odm_get_tx_power_index(dm, (enum rf_path)rf_path,
tx_rate, band_width, channel);
#else
tx_power_index = config_phydm_read_txagc_8822b(dm, rf_path, 0x04); /*0x04(TX_AGC_OFDM_6M)*/
/*0x04(TX_AGC_OFDM_6M)*/
tx_pwr_idx = config_phydm_read_txagc_8822b(dm, rf_path, 0x04);
#endif
if (tx_power_index >= 63)
tx_power_index = 63;
if (tx_pwr_idx >= 63)
tx_pwr_idx = 63;
tx_power_index_offest = 63 - tx_power_index;
tx_pwr_idx_offset = 63 - tx_pwr_idx;
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"tx_power_index=%d tx_power_index_offest=%d rf_path=%d\n", tx_power_index, tx_power_index_offest, rf_path);
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
"tx_power_index=%d tx_power_index_offset=%d rf_path=%d\n",
tx_pwr_idx, tx_pwr_idx_offset, rf_path);
if (method == BBSWING) { /*use for mp driver clean power tracking status*/
switch (rf_path) {
case RF_PATH_A:
odm_set_bb_reg(dm, 0xC94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), cali_info->absolute_ofdm_swing_idx[rf_path]);
odm_set_bb_reg(dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);
break;
case RF_PATH_B:
odm_set_bb_reg(dm, 0xE94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), cali_info->absolute_ofdm_swing_idx[rf_path]);
odm_set_bb_reg(dm, REG_B_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);
break;
default:
break;
}
} else if (method == MIX_MODE) {
switch (rf_path) {
case RF_PATH_A:
get_mix_mode_tx_agc_bb_swing_offset_8822b(dm, method, rf_path, tx_power_index_offest);
odm_set_bb_reg(dm, 0xC94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), cali_info->absolute_ofdm_swing_idx[rf_path]);
odm_set_bb_reg(dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"TXAGC(0xC94)=0x%x BBSwing(0xc1c)=0x%x BBSwingIndex=%d rf_path=%d\n",
odm_get_bb_reg(dm, 0xC94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25))),
odm_get_bb_reg(dm, 0xc1c, 0xFFE00000),
cali_info->bb_swing_idx_ofdm[rf_path], rf_path);
break;
case RF_PATH_B:
get_mix_mode_tx_agc_bb_swing_offset_8822b(dm, method, rf_path, tx_power_index_offest);
odm_set_bb_reg(dm, 0xE94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), cali_info->absolute_ofdm_swing_idx[rf_path]);
odm_set_bb_reg(dm, REG_B_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"TXAGC(0xE94)=0x%x BBSwing(0xe1c)=0x%x BBSwingIndex=%d rf_path=%d\n",
odm_get_bb_reg(dm, 0xE94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25))),
odm_get_bb_reg(dm, 0xe1c, 0xFFE00000),
cali_info->bb_swing_idx_ofdm[rf_path], rf_path);
break;
default:
break;
}
}
odm_pwrtrack_method_set_pwr8822b(dm, method, rf_path,
tx_pwr_idx_offset);
}
void
get_delta_swing_table_8822b(
void *dm_void,
void get_delta_swing_table_8822b(void *dm_void,
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
u8 **temperature_up_a,
u8 **temperature_down_a,
u8 **temperature_up_b,
u8 **temperature_down_b,
u8 **temperature_up_cck_a,
u8 **temperature_down_cck_a,
u8 **temperature_up_cck_b,
u8 **temperature_down_cck_b
u8 **temperature_up_a, u8 **temperature_down_a,
u8 **temperature_up_b, u8 **temperature_down_b,
u8 **temperature_up_cck_a,
u8 **temperature_down_cck_a,
u8 **temperature_up_cck_b,
u8 **temperature_down_cck_b)
#else
u8 **temperature_up_a,
u8 **temperature_down_a,
u8 **temperature_up_b,
u8 **temperature_down_b
u8 **temperature_up_a,
u8 **temperature_down_a,
u8 **temperature_up_b,
u8 **temperature_down_b)
#endif
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
u8 channel = *dm->channel;
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
u8 channel = *(dm->channel);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
struct rtl_phy *rtlphy = &(rtlpriv->phy);
u8 channel = rtlphy->current_channel;
#else
void *adapter = dm->adapter;
u8 channel = *dm->channel;
#endif
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
*temperature_up_cck_a = cali_info->delta_swing_table_idx_2g_cck_a_p;
*temperature_up_cck_a = cali_info->delta_swing_table_idx_2g_cck_a_p;
*temperature_down_cck_a = cali_info->delta_swing_table_idx_2g_cck_a_n;
*temperature_up_cck_b = cali_info->delta_swing_table_idx_2g_cck_b_p;
*temperature_up_cck_b = cali_info->delta_swing_table_idx_2g_cck_b_p;
*temperature_down_cck_b = cali_info->delta_swing_table_idx_2g_cck_b_n;
#endif
*temperature_up_a = cali_info->delta_swing_table_idx_2ga_p;
*temperature_up_a = cali_info->delta_swing_table_idx_2ga_p;
*temperature_down_a = cali_info->delta_swing_table_idx_2ga_n;
*temperature_up_b = cali_info->delta_swing_table_idx_2gb_p;
*temperature_up_b = cali_info->delta_swing_table_idx_2gb_p;
*temperature_down_b = cali_info->delta_swing_table_idx_2gb_n;
if (36 <= channel && channel <= 64) {
*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[0];
if (channel >= 36 && channel <= 64) {
*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[0];
*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[0];
*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[0];
*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[0];
*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[0];
} else if (100 <= channel && channel <= 144) {
*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[1];
} else if (channel >= 100 && channel <= 144) {
*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[1];
*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[1];
*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[1];
*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[1];
*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[1];
} else if (149 <= channel && channel <= 177) {
*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[2];
} else if (channel >= 149 && channel <= 177) {
*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[2];
*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[2];
*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[2];
*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[2];
*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[2];
}
}
void
_phy_lc_calibrate_8822b(
struct dm_struct *dm
)
void aac_check_8822b(struct dm_struct *dm)
{
u32 lc_cal = 0, cnt = 0,tmp0xc00, tmp0xe00;
u32 temp;
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[LCK]LCK start!!!!!!!\n");
static boolean firstrun = true;
if (firstrun) {
RF_DBG(dm, DBG_RF_LCK, "[LCK]AAC check for 8822b\n");
temp = odm_get_rf_reg(dm, RF_PATH_A, 0xc9, 0xf8);
if (temp < 4 || temp > 7) {
odm_set_rf_reg(dm, RF_PATH_A, 0xca, BIT(19), 0x0);
odm_set_rf_reg(dm, RF_PATH_A, 0xb2, 0x7c000, 0x6);
}
firstrun = false;
}
}
void _phy_lc_calibrate_8822b(struct dm_struct *dm)
{
u32 lc_cal = 0, cnt = 0, tmp0xc00, tmp0xe00;
aac_check_8822b(dm);
RF_DBG(dm, DBG_RF_IQK, "[LCK]LCK start!!!!!!!\n");
tmp0xc00 = odm_read_4byte(dm, 0xc00);
tmp0xe00 = odm_read_4byte(dm, 0xe00);
odm_write_4byte(dm, 0xc00, 0x4);
odm_write_4byte(dm, 0xe00, 0x4);
odm_set_rf_reg(dm, RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x10000);
odm_set_rf_reg(dm, RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x10000);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK, 0x10000);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x0, RFREGOFFSETMASK, 0x10000);
/*backup RF0x18*/
lc_cal = odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK);
/*disable RTK*/
odm_set_rf_reg(dm, RF_PATH_A, 0xc4, RFREGOFFSETMASK, 0x01402);
odm_set_rf_reg(dm, RF_PATH_A, RF_0xc4, RFREGOFFSETMASK, 0x01402);
/*Start LCK*/
odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal | 0x08000);
odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK,
lc_cal | 0x08000);
ODM_delay_ms(100);
for (cnt = 0; cnt < 100; cnt++) {
if (odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
@@ -419,31 +467,24 @@ _phy_lc_calibrate_8822b(
/*Recover channel number*/
odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal);
/*enable RTK*/
odm_set_rf_reg(dm, RF_PATH_A, 0xc4, RFREGOFFSETMASK, 0x81402);
odm_set_rf_reg(dm, RF_PATH_A, RF_0xc4, RFREGOFFSETMASK, 0x81402);
/**restore*/
odm_write_4byte(dm, 0xc00, tmp0xc00);
odm_write_4byte(dm, 0xe00, tmp0xe00);
odm_set_rf_reg(dm, RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x3ffff);
odm_set_rf_reg(dm, RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x3ffff);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[LCK]LCK end!!!!!!!\n");
odm_set_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK, 0x3ffff);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x0, RFREGOFFSETMASK, 0x3ffff);
RF_DBG(dm, DBG_RF_IQK, "[LCK]LCK end!!!!!!!\n");
}
/*LCK VERSION:0x1*/
void
phy_lc_calibrate_8822b(
void *dm_void
)
/*LCK VERSION:0x2*/
void phy_lc_calibrate_8822b(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
_phy_lc_calibrate_8822b(dm);
}
void configure_txpower_track_8822b(
struct txpwrtrack_cfg *config
)
void configure_txpower_track_8822b(struct txpwrtrack_cfg *config)
{
config->swing_table_size_cck = TXSCALE_TABLE_SIZE;
config->swing_table_size_ofdm = TXSCALE_TABLE_SIZE;
@@ -464,84 +505,79 @@ void configure_txpower_track_8822b(
#endif
}
void phy_set_rf_path_switch_8822b(
#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
struct dm_struct *dm,
void phy_set_rf_path_switch_8822b(struct dm_struct *dm, boolean is_main)
#else
void *adapter,
void phy_set_rf_path_switch_8822b(void *adapter, boolean is_main)
#endif
boolean is_main
)
{
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
#endif
#endif
/*BY SY Request */
odm_set_bb_reg(dm, 0x4C, (BIT(24) | BIT(23)), 0x2);
odm_set_bb_reg(dm, R_0x4c, (BIT(24) | BIT(23)), 0x2);
odm_set_bb_reg(dm, 0x974, 0xff, 0xff);
odm_set_bb_reg(dm, R_0x974, 0xff, 0xff);
/*odm_set_bb_reg(dm, 0x1991, 0x3, 0x0);*/
odm_set_bb_reg(dm, 0x1990, (BIT(9) | BIT(8)), 0x0);
#if 0
/*odm_set_bb_reg(dm, R_0x1991, 0x3, 0x0);*/
#endif
odm_set_bb_reg(dm, R_0x1990, (BIT(9) | BIT(8)), 0x0);
/*odm_set_bb_reg(dm, 0xCBE, 0x8, 0x0);*/
odm_set_bb_reg(dm, 0xCBC, BIT(19), 0x0);
#if 0
/*odm_set_bb_reg(dm, R_0xcbe, 0x8, 0x0);*/
#endif
odm_set_bb_reg(dm, R_0xcbc, BIT(19), 0x0);
odm_set_bb_reg(dm, 0xCB4, 0xff, 0x77);
odm_set_bb_reg(dm, R_0xcb4, 0xff, 0x77);
odm_set_bb_reg(dm, 0x70, MASKBYTE3, 0x0e);
odm_set_bb_reg(dm, 0x1704, MASKDWORD, 0x0000ff00);
odm_set_bb_reg(dm, 0x1700, MASKDWORD, 0xc00f0038);
odm_set_bb_reg(dm, R_0x70, MASKBYTE3, 0x0e);
odm_set_bb_reg(dm, R_0x1704, MASKDWORD, 0x0000ff00);
odm_set_bb_reg(dm, R_0x1700, MASKDWORD, 0xc00f0038);
if (is_main) {
/*odm_set_bb_reg(dm, 0xCBD, 0x3, 0x2); WiFi */
odm_set_bb_reg(dm, 0xCBC, (BIT(9) | BIT(8)), 0x2); /*WiFi */
#if 0
/*odm_set_bb_reg(dm, R_0xcbd, 0x3, 0x2); WiFi*/
#endif
odm_set_bb_reg(dm, R_0xcbc, (BIT(9) | BIT(8)), 0x2); /*WiFi*/
} else {
/*odm_set_bb_reg(dm, 0xCBD, 0x3, 0x1); BT*/
odm_set_bb_reg(dm, 0xCBC, (BIT(9) | BIT(8)), 0x1); /*BT*/
#if 0
/*odm_set_bb_reg(dm, R_0xcbd, 0x3, 0x1); BT*/
#endif
odm_set_bb_reg(dm, R_0xcbc, (BIT(9) | BIT(8)), 0x1); /*BT*/
}
}
boolean
_phy_query_rf_path_switch_8822b(
#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
struct dm_struct *dm
boolean _phy_query_rf_path_switch_8822b(struct dm_struct *dm)
#else
void *adapter
boolean _phy_query_rf_path_switch_8822b(void *adapter)
#endif
)
{
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &hal_data->DM_OutSrc;
#endif
#endif
if (odm_get_bb_reg(dm, 0xCBC, (BIT(9) | BIT(8))) == 0x2) /*WiFi */
if (odm_get_bb_reg(dm, R_0xcbc, (BIT(9) | BIT(8))) == 0x2) /*WiFi*/
return true;
else
return false;
}
boolean phy_query_rf_path_switch_8822b(
#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
struct dm_struct *dm
boolean phy_query_rf_path_switch_8822b(struct dm_struct *dm)
#else
void *adapter
boolean phy_query_rf_path_switch_8822b(void *adapter)
#endif
)
{
#if DISABLE_BB_RF
return true;
#endif
#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
return _phy_query_rf_path_switch_8822b(dm);
#else
@@ -549,5 +585,4 @@ boolean phy_query_rf_path_switch_8822b(
#endif
}
#endif /* (RTL8822B_SUPPORT == 0)*/
#endif /*(RTL8822B_SUPPORT == 0)*/

70
hal/phydm/halrf/rtl8822b/halrf_8822b.h
View File

@@ -23,63 +23,43 @@
*
*****************************************************************************/
#ifndef __HAL_PHY_RF_8822B_H__
#define __HAL_PHY_RF_8822B_H__
#ifndef __HALRF_8822B_H__
#define __HALRF_8822B_H__
#define AVG_THERMAL_NUM_8822B 4
#define RF_T_METER_8822B 0x42
#define AVG_THERMAL_NUM_8822B 4
#define RF_T_METER_8822B 0x42
void configure_txpower_track_8822b(
struct txpwrtrack_cfg *config
);
void configure_txpower_track_8822b(struct txpwrtrack_cfg *config);
void
odm_tx_pwr_track_set_pwr8822b(
void *dm_void,
enum pwrtrack_method method,
u8 rf_path,
u8 channel_mapped_index
);
void odm_tx_pwr_track_set_pwr8822b(void *dm_void, enum pwrtrack_method method,
u8 rf_path, u8 channel_mapped_index);
void
get_delta_swing_table_8822b(
void *dm_void,
void get_delta_swing_table_8822b(void *dm_void,
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
u8 **temperature_up_a,
u8 **temperature_down_a,
u8 **temperature_up_b,
u8 **temperature_down_b,
u8 **temperature_up_cck_a,
u8 **temperature_down_cck_a,
u8 **temperature_up_cck_b,
u8 **temperature_down_cck_b
u8 **temperature_up_a, u8 **temperature_down_a,
u8 **temperature_up_b, u8 **temperature_down_b,
u8 **temperature_up_cck_a,
u8 **temperature_down_cck_a,
u8 **temperature_up_cck_b,
u8 **temperature_down_cck_b
#else
u8 **temperature_up_a,
u8 **temperature_down_a,
u8 **temperature_up_b,
u8 **temperature_down_b
u8 **temperature_up_a, u8 **temperature_down_a,
u8 **temperature_up_b,
u8 **temperature_down_b
#endif
);
);
void
phy_lc_calibrate_8822b(
void *dm_void
);
void aac_check_8822b(struct dm_struct *dm);
void
halrf_rf_lna_setting_8822b(
struct dm_struct *dm,
enum phydm_lna_set type
);
void phy_lc_calibrate_8822b(void *dm_void);
void halrf_rf_lna_setting_8822b(struct dm_struct *dm, enum halrf_lna_set type);
void phy_set_rf_path_switch_8822b(
#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
struct dm_struct *dm,
void phy_set_rf_path_switch_8822b(struct dm_struct *dm,
#else
void *adapter,
void phy_set_rf_path_switch_8822b(void *adapter,
#endif
boolean is_main
);
boolean is_main);
#endif /* #ifndef __HAL_PHY_RF_8822B_H__ */
#endif /*__HALRF_8822B_H__*/

1858
hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c
View File

File diff suppressed because it is too large Load Diff

54
hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.h
View File

@@ -23,56 +23,38 @@
*
*****************************************************************************/
#ifndef __PHYDM_IQK_8822B_H__
#define __PHYDM_IQK_8822B_H__
#ifndef __HALRF_IQK_8822B_H__
#define __HALRF_IQK_8822B_H__
#if (RTL8822B_SUPPORT == 1)
/*--------------------------Define Parameters-------------------------------*/
#define MAC_REG_NUM_8822B 2
/*@--------------------------Define Parameters-------------------------------*/
#define MAC_REG_NUM_8822B 2
#define BB_REG_NUM_8822B 15
#define RF_REG_NUM_8822B 5
#define LOK_delay_8822B 2
#define GS_delay_8822B 2
#define WBIQK_delay_8822B 2
#define RF_REG_NUM_8822B 5
#define LOK_delay_8822B 2
#define GS_delay_8822B 2
#define WBIQK_delay_8822B 2
#define TXIQK 0
#define RXIQK 1
#define SS_8822B 2
/*---------------------------End Define Parameters-------------------------------*/
/*@-------------------------End Define Parameters-------------------------*/
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
void
do_iqk_8822b(
void *dm_void,
u8 delta_thermal_index,
u8 thermal_value,
u8 threshold
);
void do_iqk_8822b(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
u8 threshold);
#else
void
do_iqk_8822b(
void *dm_void,
u8 delta_thermal_index,
u8 thermal_value,
u8 threshold
);
void do_iqk_8822b(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
u8 threshold);
#endif
void
phy_iq_calibrate_8822b(
void *dm_void,
boolean clear,
boolean segment_iqk
);
void phy_iq_calibrate_8822b(void *dm_void, boolean clear, boolean segment_iqk);
void
do_imr_test_8822b(
void *dm_void
);
void do_imr_test_8822b(void *dm_void);
#else /* (RTL8822B_SUPPORT == 0)*/
#else /* (RTL8822B_SUPPORT == 0)*/
#define phy_iq_calibrate_8822b(_pdm_void, clear, segment_iqk)
#endif /* RTL8822B_SUPPORT */
#endif /* RTL8822B_SUPPORT */
#endif /* #ifndef __PHYDM_IQK_8822B_H__*/
#endif /*__HALRF_IQK_8822B_H__*/

1057
hal/phydm/halrf/rtl8822b/halrf_rfk_init_8822b.c Normal file
View File

File diff suppressed because it is too large Load Diff

29
hal/phydm/halrf/rtl8822b/halrf_rfk_init_8822b.h Normal file
View File

@@ -0,0 +1,29 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALRF_RFK_INIT_8822B_H__
#define __HALRF_RFK_INIT_8822B_H__
void odm_read_and_config_mp_8822b_cal_init(void *dm_void);
#endif

3163
hal/phydm/phydm.c
View File

File diff suppressed because it is too large Load Diff

1192
hal/phydm/phydm.h
View File

File diff suppressed because it is too large Load Diff

60
hal/phydm/phydm.mk
View File

@@ -31,7 +31,11 @@ _PHYDM_FILES := hal/phydm/phydm_debug.o \
hal/phydm/phydm_math_lib.o\
hal/phydm/phydm_api.o\
hal/phydm/phydm_pow_train.o\
hal/phydm/phydm_lna_sat.o\
hal/phydm/phydm_pmac_tx_setting.o\
hal/phydm/phydm_mp.o\
hal/phydm/halrf/halrf.o\
hal/phydm/halrf/halrf_debug.o\
hal/phydm/halrf/halphyrf_ce.o\
hal/phydm/halrf/halrf_powertracking_ce.o\
hal/phydm/halrf/halrf_powertracking.o\
@@ -115,6 +119,7 @@ _PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\
hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\
hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\
hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\
hal/phydm/$(RTL871X)/phydm_rtl8703b.o\
hal/phydm/halrf/$(RTL871X)/halrf_8703b.o
endif
@@ -129,6 +134,17 @@ _PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\
endif
ifeq ($(CONFIG_RTL8710B), y)
RTL871X = rtl8710b
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8710b_bb.o\
hal/phydm/$(RTL871X)/halhwimg8710b_mac.o\
hal/phydm/$(RTL871X)/halhwimg8710b_rf.o\
hal/phydm/$(RTL871X)/phydm_regconfig8710b.o\
hal/phydm/$(RTL871X)/phydm_rtl8710b.o\
hal/phydm/halrf/$(RTL871X)/halrf_8710b.o
endif
ifeq ($(CONFIG_RTL8188F), y)
RTL871X = rtl8188f
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\
@@ -147,6 +163,7 @@ _PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \
hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \
hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \
hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822b.o \
hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \
hal/phydm/$(RTL871X)/phydm_rtl8822b.o
@@ -163,4 +180,47 @@ _PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \
hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\
hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o
endif
ifeq ($(CONFIG_RTL8192F), y)
RTL871X = rtl8192f
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192f_bb.o\
hal/phydm/$(RTL871X)/halhwimg8192f_mac.o\
hal/phydm/$(RTL871X)/halhwimg8192f_rf.o\
hal/phydm/$(RTL871X)/phydm_hal_api8192f.o\
hal/phydm/$(RTL871X)/phydm_regconfig8192f.o\
hal/phydm/$(RTL871X)/phydm_rtl8192f.o\
hal/phydm/halrf/$(RTL871X)/halrf_8192f.o
endif
ifeq ($(CONFIG_RTL8198F), y)
RTL871X = rtl8198f
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8198f_bb.o\
hal/phydm/$(RTL871X)/halhwimg8198f_mac.o\
hal/phydm/$(RTL871X)/halhwimg8198f_rf.o\
hal/phydm/$(RTL871X)/phydm_hal_api8198f.o\
hal/phydm/$(RTL871X)/phydm_regconfig8198f.o
endif
ifeq ($(CONFIG_RTL8822C), y)
RTL871X = rtl8822c
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822c_bb.o\
hal/phydm/$(RTL871X)/halhwimg8822c_mac.o\
hal/phydm/$(RTL871X)/halhwimg8822c_rf.o\
hal/phydm/$(RTL871X)/phydm_hal_api8822c.o\
hal/phydm/$(RTL871X)/phydm_regconfig8822c.o\
hal/phydm/halrf/$(RTL871X)/halrf_8822c.o\
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822c.o\
hal/phydm/halrf/$(RTL871X)/halrf_tssi_8822c.o\
hal/phydm/halrf/$(RTL871X)/halrf_dpk_8822c.o\
hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822c.o
endif
ifeq ($(CONFIG_RTL8814B), y)
RTL871X = rtl8814b
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814b_bb.o\
hal/phydm/$(RTL871X)/phydm_hal_api8814b.o\
hal/phydm/$(RTL871X)/phydm_regconfig8814b.o\
hal/phydm/halrf/$(RTL871X)/halrf_8814b.o \
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814b.o \
hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8814b.o
endif

1152
hal/phydm/phydm_acs.c
View File

File diff suppressed because it is too large Load Diff

115
hal/phydm/phydm_acs.h
View File

@@ -1,115 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMACS_H__
#define __PHYDMACS_H__
#define ACS_VERSION "1.1" /*20150729 by YuChen*/
#define CLM_VERSION "1.0"
#define ODM_MAX_CHANNEL_2G 14
#define ODM_MAX_CHANNEL_5G 24
/* For phydm_auto_channel_select_setting_ap() */
#define STORE_DEFAULT_NHM_SETTING 0
#define RESTORE_DEFAULT_NHM_SETTING 1
#define ACS_NHM_SETTING 2
struct acs_info {
boolean is_force_acs_result;
u8 clean_channel_2g;
u8 clean_channel_5g;
u16 channel_info_2g[2][ODM_MAX_CHANNEL_2G]; /* Channel_Info[1]: channel score, Channel_Info[2]:Channel_Scan_Times */
u16 channel_info_5g[2][ODM_MAX_CHANNEL_5G];
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
u8 acs_step;
/* NHM count 0-11 */
u8 nhm_cnt[14][11];
/* AC-Series, for storing previous setting */
u32 reg0x990;
u32 reg0x994;
u32 reg0x998;
u32 reg0x99c;
u8 reg0x9a0; /* u8 */
/* N-Series, for storing previous setting */
u32 reg0x890;
u32 reg0x894;
u32 reg0x898;
u32 reg0x89c;
u8 reg0xe28; /* u8 */
#endif
};
void
odm_auto_channel_select_init(
void *dm_void
);
void
odm_auto_channel_select_reset(
void *dm_void
);
void
odm_auto_channel_select(
void *dm_void,
u8 channel
);
u8
odm_get_auto_channel_select_result(
void *dm_void,
u8 band
);
boolean
phydm_acs_check(
void *dm_void
);
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
void
phydm_auto_channel_select_setting_ap(
void *dm_void,
u32 setting, /* 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING */
u32 acs_step
);
void
phydm_get_nhm_statistics_ap(
void *dm_void,
u32 idx, /* @ 2G, Real channel number = idx+1 */
u32 acs_step
);
#endif /* #if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) */
#endif /* #ifndef __PHYDMACS_H__ */

1421
hal/phydm/phydm_adaptivity.c
View File

File diff suppressed because it is too large Load Diff

185
hal/phydm/phydm_adaptivity.h
View File

@@ -23,15 +23,26 @@
*
*****************************************************************************/
#ifndef __PHYDMADAPTIVITY_H__
#define __PHYDMADAPTIVITY_H__
#ifndef __PHYDMADAPTIVITY_H__
#define __PHYDMADAPTIVITY_H__
#define ADAPTIVITY_VERSION "9.6.01" /*@20180814 changed by Kevin,
*add phydm_edcca_abort func.
*/
#define ADAPTIVITY_VERSION "9.5.7" /*20170627 changed by Kevin, move adapt_igi_up from phydm.h to phydm_adaptivity.h*/
#define pwdb_upper_bound 7
#define dfir_loss 7
#define PWDB_UPPER_BOUND 7
#define DFIR_LOSS 7
#define ADC_BACKOFF 12
#define ODM_IC_PWDB_EDCCA (ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |\
ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8812)
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
#define ADAPT_DC_BACKOFF 2
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#define ADAPT_DC_BACKOFF 4
#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
#define ADAPT_DC_BACKOFF 0
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
enum phydm_regulation_type {
REGULATION_FCC = 0,
@@ -44,174 +55,68 @@ enum phydm_regulation_type {
enum phydm_adapinfo {
PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,
PHYDM_ADAPINFO_DCBACKOFF,
PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY,
PHYDM_ADAPINFO_TH_L2H_INI,
PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,
PHYDM_ADAPINFO_AP_NUM_TH
};
enum phydm_set_lna {
phydm_disable_lna = 0,
phydm_enable_lna = 1,
};
enum phydm_trx_mux_type {
phydm_shutdown = 0,
phydm_standby_mode = 1,
phydm_tx_mode = 2,
phydm_rx_mode = 3
PHYDM_ADAPINFO_AP_NUM_TH,
PHYDM_ADAPINFO_DOMAIN_CODE_2G,
PHYDM_ADAPINFO_DOMAIN_CODE_5G
};
enum phydm_mac_edcca_type {
phydm_ignore_edcca = 0,
phydm_dont_ignore_edcca = 1
PHYDM_IGNORE_EDCCA = 0,
PHYDM_DONT_IGNORE_EDCCA = 1
};
enum phydm_adaptivity_mode {
PHYDM_ADAPT_MSG = 0,
PHYDM_ADAPT_DEBUG = 1,
PHYDM_ADAPT_RESUME = 2,
PHYDM_EDCCA_TH_PAUSE = 3,
PHYDM_EDCCA_RESUME = 4
PHYDM_EDCCA_TH_PAUSE = 3,
PHYDM_EDCCA_TH_RESUME = 4
};
struct phydm_adaptivity_struct {
s8 th_l2h_ini_backup;
s8 th_edcca_hl_diff_backup;
s8 igi_base;
u8 igi_target;
s8 h2l_lb;
s8 l2h_lb;
boolean is_check;
boolean dynamic_link_adaptivity;
u8 ap_num_th;
u8 adajust_igi_level;
s8 backup_l2h;
s8 backup_h2l;
boolean is_stop_edcca;
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
RT_WORK_ITEM phydm_pause_edcca_work_item;
RT_WORK_ITEM phydm_resume_edcca_work_item;
#endif
u32 adaptivity_dbg_port; /*N:0x208, AC:0x209*/
u8 debug_mode;
s8 th_l2h_ini_debug;
u16 igi_up_bound_lmt_cnt; /*When igi_up_bound_lmt_cnt !=0, limit IGI upper bound to "adapt_igi_up"*/
u16 igi_up_bound_lmt_val; /*max value of igi_up_bound_lmt_cnt*/
boolean igi_lmt_en;
u16 igi_up_bound_lmt_cnt; /*@When igi_up_bound_lmt_cnt !=0, limit IGI upper bound to "adapt_igi_up"*/
u16 igi_up_bound_lmt_val; /*@max value of igi_up_bound_lmt_cnt*/
boolean igi_lmt_en;
u8 adapt_igi_up;
s8 rvrt_val[2];
u32 rvrt_val[2];
s8 th_l2h;
s8 th_h2l;
u8 regulation_2g;
u8 regulation_5g;
boolean is_adapt_en;
boolean edcca_en;
s8 th_l2h_ini_mode2;
s8 th_edcca_hl_diff_mode2;
};
void
phydm_pause_edcca(
void *dm_void,
boolean is_pasue_edcca
);
#ifdef PHYDM_SUPPORT_ADAPTIVITY
void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void
phydm_check_environment(
void *dm_void
);
void
phydm_mac_edcca_state(
void *dm_void,
enum phydm_mac_edcca_type state
);
void
phydm_set_edcca_threshold(
void *dm_void,
s8 H2L,
s8 L2H
);
void
phydm_set_trx_mux(
void *dm_void,
enum phydm_trx_mux_type tx_mode,
enum phydm_trx_mux_type rx_mode
);
void
phydm_search_pwdb_lower_bound(
void *dm_void
);
void
phydm_adaptivity_info_init(
void *dm_void,
enum phydm_adapinfo cmn_info,
u32 value
);
void
phydm_adaptivity_init(
void *dm_void
);
void
phydm_adaptivity(
void *dm_void
);
void
phydm_set_edcca_threshold_api(
void *dm_void,
u8 IGI
);
void
phydm_pause_edcca_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
#else
void *dm_void
void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len);
#endif
);
void
phydm_resume_edcca_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter
#else
void *dm_void
#endif
);
void phydm_set_edcca_threshold_api(void *dm_void, u8 IGI);
void
phydm_adaptivity_debug(
void *dm_void,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
);
void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
u32 value);
void
phydm_set_l2h_th_ini(
void *dm_void
);
void phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info,
u32 value);
void
phydm_set_forgetting_factor(
void *dm_void
);
void phydm_adaptivity_init(void *dm_void);
void
phydm_set_pwdb_mode(
void *dm_void
);
void
phydm_set_edcca_val(
void *dm_void,
u32 *val_buf,
u8 val_len
);
void phydm_adaptivity(void *dm_void);
#endif

1499
hal/phydm/phydm_adc_sampling.c
View File

File diff suppressed because it is too large Load Diff

155
hal/phydm/phydm_adc_sampling.h
View File

@@ -26,18 +26,21 @@
#ifndef __INC_ADCSMP_H
#define __INC_ADCSMP_H
#define DYNAMIC_LA_MODE "2.0" /*2017.02.06 Dino */
#if (PHYDM_LA_MODE_SUPPORT)
#if (PHYDM_LA_MODE_SUPPORT == 1)
#define DYNAMIC_LA_MODE "3.0"
#define FULL_BUFF_MODE_SUPPORT (ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8822C |\
ODM_RTL8812F | ODM_RTL8814B)
struct rt_adcsmp_string {
u32 *octet;
u32 length;
u32 buffer_size;
u32 start_pos;
u32 end_pos; /*@buf addr*/
};
enum rt_adcsmp_trig_sel {
PHYDM_ADC_BB_TRIG = 0,
PHYDM_ADC_MAC_TRIG = 1,
@@ -46,7 +49,6 @@ enum rt_adcsmp_trig_sel {
PHYDM_MAC_TRIG = 4
};
enum rt_adcsmp_trig_sig_sel {
ADCSMP_TRIG_CRCOK = 0,
ADCSMP_TRIG_CRCFAIL = 1,
@@ -54,28 +56,49 @@ enum rt_adcsmp_trig_sig_sel {
ADCSMP_TRIG_REG = 3
};
enum rt_adcsmp_state {
ADCSMP_STATE_IDLE = 0,
ADCSMP_STATE_SET = 1,
ADCSMP_STATE_QUERY = 2
ADCSMP_STATE_IDLE = 0,
ADCSMP_STATE_SET = 1,
ADCSMP_STATE_QUERY = 2
};
enum la_buff_mode {
ADCSMP_BUFF_HALF = 0,
ADCSMP_BUFF_ALL = 1 /*Only use in MP Driver*/
};
struct rt_adcsmp {
struct rt_adcsmp_string adc_smp_buf;
enum rt_adcsmp_state adc_smp_state;
u8 la_trig_mode;
u32 la_trig_sig_sel;
u8 la_dma_type;
u32 la_trigger_time;
u32 la_mac_mask_or_hdr_sel; /*1.BB mode: for debug port header sel; 2.MAC mode: for reference mask*/
u32 la_dbg_port;
u8 la_trigger_edge;
u8 la_smp_rate;
u32 la_count;
u8 is_bb_trigger;
u8 la_work_item_index;
struct rt_adcsmp_string adc_smp_buf;
enum rt_adcsmp_state adc_smp_state;
enum la_buff_mode la_buff_mode;
u8 la_trig_mode;
u32 la_trig_sig_sel;
u8 la_dma_type;
u32 la_trigger_time;
/*
* @1.BB mode: for debug port header sel;
* 2.MAC mode: for reference mask
*/
u32 la_mac_mask_or_hdr_sel;
u32 la_dbg_port;
u8 la_trigger_edge;
u8 la_smp_rate;
u32 la_count;
u8 is_bb_trigger;
u8 la_work_item_index;
boolean la_en_new_bbtrigger;
boolean la_ori_bb_dis;
u8 la_and1_sel;
u8 la_and1_val;
u8 la_and2_sel;
u8 la_and2_val;
u8 la_and3_sel;
u8 la_and3_val;
u32 la_and4_en;
u32 la_and4_val;
boolean is_fake_trig;
boolean is_la_print;
boolean en_fake_trig;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
RT_WORK_ITEM adc_smp_work_item;
@@ -84,89 +107,45 @@ struct rt_adcsmp {
};
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
void
adc_smp_work_item_callback(
void *context
);
void adc_smp_work_item_callback(
void *context);
#endif
void
adc_smp_set(
void *dm_void,
u8 trig_mode,
u32 trig_sig_sel,
u8 dma_data_sig_sel,
u32 trigger_time,
u16 polling_time
);
void adc_smp_set(void *dm_void, u8 trig_mode, u32 trig_sig_sel,
u8 dma_data_sig_sel, u32 trig_time, u16 polling_time);
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
enum rt_status
adc_smp_query(
void *dm_void,
ULONG information_buffer_length,
void *information_buffer,
PULONG bytes_written
);
adc_smp_query(void *dm_void, ULONG info_buf_length, void *info_buf,
PULONG bytes_written);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
void
adc_smp_query(
void *dm_void,
void *output,
u32 out_len,
u32 *pused
);
void adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused);
s32
adc_smp_get_sample_counts(
void *dm_void
);
s32 adc_smp_get_sample_counts(void *dm_void);
s32
adc_smp_query_single_data(
void *dm_void,
void *output,
u32 out_len,
u32 index
);
s32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len,
u32 idx);
#endif
void
adc_smp_stop(
void *dm_void
);
void adc_smp_stop(void *dm_void);
void
adc_smp_init(
void *dm_void
);
void phydm_la_bb_adv_reset_jgr3(void *dm_void);
void adc_smp_init(void *dm_void);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
void
adc_smp_de_init(
void *dm_void
);
void adc_smp_de_init(void *dm_void);
#endif
void
phydm_la_mode_bb_setting(
void *dm_void
);
void phydm_la_set_buff_mode(void *dm_void, enum la_buff_mode mode);
void
phydm_la_mode_set_trigger_time(
void *dm_void,
u32 trigger_time_mu_sec
);
void phydm_la_mode_bb_setting(void *dm_void, boolean en_fake_trig);
void phydm_la_mode_set_trigger_time(void *dm_void, u32 trigger_time_mu_sec);
void phydm_lamode_trigger_cmd(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void phydm_la_pre_run(void *dm_void);
void
phydm_lamode_trigger_setting(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
#endif
#endif

500
hal/phydm/phydm_antdect.c
View File

@@ -30,29 +30,38 @@
#include "mp_precomp.h"
#include "phydm_precomp.h"
/* #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */
#if (defined(CONFIG_ANT_DETECTION))
#ifdef CONFIG_ANT_DETECTION
/* IS_ANT_DETECT_SUPPORT_SINGLE_TONE(adapter)
/* @IS_ANT_DETECT_SUPPORT_SINGLE_TONE(adapter)
* IS_ANT_DETECT_SUPPORT_RSSI(adapter)
* IS_ANT_DETECT_SUPPORT_PSD(adapter) */
/* 1 [1. Single Tone method] =================================================== */
/* @1 [1. Single Tone method] =================================================== */
/*
/*@
* Description:
* Set Single/Dual Antenna default setting for products that do not do detection in advance.
*
* Added by Joseph, 2012.03.22
* */
void
odm_single_dual_antenna_default_setting(
void *dm_void
)
void odm_sw_ant_div_construct_scan_chnl(
void *adapter,
u8 scan_chnl)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
void *adapter = dm->adapter;
}
u8 odm_sw_ant_div_select_scan_chnl(
void *adapter)
{
return 0;
}
void odm_single_dual_antenna_default_setting(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
void *adapter = dm->adapter;
u8 bt_ant_num = BT_GetPgAntNum(adapter);
/* Set default antenna A and B status */
@@ -69,8 +78,7 @@ odm_single_dual_antenna_default_setting(
RT_ASSERT(false, ("Incorrect antenna number!!\n"));
}
/* 2 8723A ANT DETECT
/* @2 8723A ANT DETECT
*
* Description:
* Implement IQK single tone for RF DPK loopback and BB PSD scanning.
@@ -80,23 +88,21 @@ odm_single_dual_antenna_default_setting(
* */
boolean
odm_single_dual_antenna_detection(
void *dm_void,
u8 mode
)
void *dm_void,
u8 mode)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
void *adapter = dm->adapter;
struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
u32 current_channel, rf_loop_reg;
u8 n;
u32 reg88c, regc08, reg874, regc50, reg948, regb2c, reg92c, reg930, reg064, afe_rrx_wait_cca;
u8 initial_gain = 0x5a;
u32 PSD_report_tmp;
u32 ant_a_report = 0x0, ant_b_report = 0x0, ant_0_report = 0x0;
boolean is_result = true;
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection()============>\n");
struct dm_struct *dm = (struct dm_struct *)dm_void;
void *adapter = dm->adapter;
struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
u32 current_channel, rf_loop_reg;
u8 n;
u32 reg88c, regc08, reg874, regc50, reg948, regb2c, reg92c, reg930, reg064, afe_rrx_wait_cca;
u8 initial_gain = 0x5a;
u32 PSD_report_tmp;
u32 ant_a_report = 0x0, ant_b_report = 0x0, ant_0_report = 0x0;
boolean is_result = true;
PHYDM_DBG(dm, DBG_ANT_DIV, "%s============>\n", __func__);
if (!(dm->support_ic_type & ODM_RTL8723B))
return is_result;
@@ -105,10 +111,10 @@ odm_single_dual_antenna_detection(
if (!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(((PADAPTER)adapter)))
return is_result;
/* 1 Backup Current RF/BB Settings */
/* @1 Backup Current RF/BB Settings */
current_channel = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
rf_loop_reg = odm_get_rf_reg(dm, RF_PATH_A, 0x00, RFREGOFFSETMASK);
rf_loop_reg = odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK);
if (dm->support_ic_type & ODM_RTL8723B) {
reg92c = odm_get_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD);
reg930 = odm_get_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD);
@@ -117,8 +123,8 @@ odm_single_dual_antenna_detection(
reg064 = odm_get_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29));
odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x1);
odm_set_bb_reg(dm, rfe_ctrl_anta_src, 0xff, 0x77);
odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), 0x1); /* dbg 7 */
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0x3c0, 0x0);/* dbg 8 */
odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), 0x1); /* @dbg 7 */
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0x3c0, 0x0); /* @dbg 8 */
odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x0);
}
@@ -135,23 +141,23 @@ odm_single_dual_antenna_detection(
afe_rrx_wait_cca = odm_get_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD);
/* Set PSD 128 pts */
odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pts */
odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* @128 pts */
/* To SET CH1 to do */
odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK, 0x7401); /* channel 1 */
odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK, 0x7401); /* @channel 1 */
/* AFE all on step */
/* @AFE all on step */
if (dm->support_ic_type & ODM_RTL8723B)
odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, 0x01c00016);
/* 3 wire Disable */
/* @3 wire Disable */
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, 0xCCF000C0);
/* BB IQK setting */
/* @BB IQK setting */
odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800E4);
odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x22208000);
/* IQK setting tone@ 4.34Mhz */
/* @IQK setting tone@ 4.34Mhz */
odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008C1C);
odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00);
@@ -167,7 +173,7 @@ odm_single_dual_antenna_detection(
odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x001028d0);
odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7f, initial_gain);
/* IQK Single tone start */
/* @IQK Single tone start */
odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
@@ -182,9 +188,11 @@ odm_single_dual_antenna_detection(
ant_a_report = PSD_report_tmp;
}
/* change to Antenna B */
/* @change to Antenna B */
if (dm->support_ic_type & ODM_RTL8723B) {
#if 0
/* odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x2); */
#endif
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
}
@@ -199,15 +207,15 @@ odm_single_dual_antenna_detection(
ant_b_report = PSD_report_tmp;
}
/* Close IQK Single Tone function */
/* @Close IQK Single Tone function */
odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
/* 1 Return to antanna A */
/* @1 Return to antanna A */
if (dm->support_ic_type & ODM_RTL8723B) {
/* external DPDT */
/* @external DPDT */
odm_set_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD, reg92c);
/* internal S0/S1 */
/* @internal S0/S1 */
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
odm_set_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD, reg930);
@@ -220,34 +228,40 @@ odm_single_dual_antenna_detection(
odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7F, 0x40);
odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD, regc50);
odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, current_channel);
odm_set_rf_reg(dm, RF_PATH_A, 0x00, RFREGOFFSETMASK, rf_loop_reg);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_loop_reg);
/* Reload AFE Registers */
if (dm->support_ic_type & ODM_RTL8723B)
odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, afe_rrx_wait_cca);
if (dm->support_ic_type & ODM_RTL8723B) {
PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_A[%d]= %d\n", 2416, ant_a_report);
PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_B[%d]= %d\n", 2416, ant_b_report);
PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_A[%d]= %d\n", 2416,
ant_a_report);
PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_B[%d]= %d\n", 2416,
ant_b_report);
/* 2 Test ant B based on ant A is ON */
if ((ant_a_report >= 100) && (ant_b_report >= 100) && (ant_a_report <= 135) && (ant_b_report <= 135)) {
/* @2 Test ant B based on ant A is ON */
if (ant_a_report >= 100 && ant_b_report >= 100 && ant_a_report <= 135 && ant_b_report <= 135) {
u8 TH1 = 2, TH2 = 6;
if ((ant_a_report - ant_b_report < TH1) || (ant_b_report - ant_a_report < TH1)) {
dm_swat_table->ANTA_ON = true;
dm_swat_table->ANTB_ON = true;
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection(): Dual Antenna\n");
PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Dual Antenna\n",
__func__);
} else if (((ant_a_report - ant_b_report >= TH1) && (ant_a_report - ant_b_report <= TH2)) ||
((ant_b_report - ant_a_report >= TH1) && (ant_b_report - ant_a_report <= TH2))) {
((ant_b_report - ant_a_report >= TH1) && (ant_b_report - ant_a_report <= TH2))) {
dm_swat_table->ANTA_ON = false;
dm_swat_table->ANTB_ON = false;
is_result = false;
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection(): Need to check again\n");
PHYDM_DBG(dm, DBG_ANT_DIV,
"%s: Need to check again\n",
__func__);
} else {
dm_swat_table->ANTA_ON = true;
dm_swat_table->ANTB_ON = false;
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection(): Single Antenna\n");
PHYDM_DBG(dm, DBG_ANT_DIV,
"%s: Single Antenna\n", __func__);
}
dm->ant_detected_info.is_ant_detected = true;
dm->ant_detected_info.db_for_ant_a = ant_a_report;
@@ -260,44 +274,39 @@ odm_single_dual_antenna_detection(
}
}
return is_result;
}
/* 1 [2. Scan AP RSSI method] ================================================== */
/* @1 [2. Scan AP RSSI method] ================================================== */
boolean
odm_sw_ant_div_check_before_link(
void *dm_void
)
void *dm_void)
{
#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
struct dm_struct *dm = (struct dm_struct *)dm_void;
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = (struct dm_struct *)dm_void;
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
//PMGNT_INFO mgnt_info = &adapter->MgntInfo;
PMGNT_INFO mgnt_info = &(((PADAPTER)(adapter))->MgntInfo);
struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
s8 score = 0;
PRT_WLAN_BSS p_tmp_bss_desc, p_test_bss_desc;
u8 power_target_L = 9, power_target_H = 16;
u8 tmp_power_diff = 0, power_diff = 0, avg_power_diff = 0, max_power_diff = 0, min_power_diff = 0xff;
u16 index, counter = 0;
static u8 scan_channel;
u32 tmp_swas_no_link_bk_reg948;
PMGNT_INFO mgnt_info = &(((PADAPTER)(adapter))->MgntInfo);
struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
s8 score = 0;
PRT_WLAN_BSS p_tmp_bss_desc, p_test_bss_desc;
u8 power_target_L = 9, power_target_H = 16;
u8 tmp_power_diff = 0, power_diff = 0, avg_power_diff = 0, max_power_diff = 0, min_power_diff = 0xff;
u16 index, counter = 0;
static u8 scan_channel;
u32 tmp_swas_no_link_bk_reg948;
PHYDM_DBG(dm, DBG_ANT_DIV, "ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n", dm->dm_swat_table.ANTA_ON, dm->dm_swat_table.ANTB_ON);
PHYDM_DBG(dm, DBG_ANT_DIV, "ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n",
dm->dm_swat_table.ANTA_ON, dm->dm_swat_table.ANTB_ON);
/* if(HP id) */
/* @if(HP id) */
{
if (dm->dm_swat_table.rssi_ant_dect_result == true && dm->support_ic_type == ODM_RTL8723B) {
PHYDM_DBG(dm, DBG_ANT_DIV, "8723B RSSI-based Antenna Detection is done\n");
PHYDM_DBG(dm, DBG_ANT_DIV,
"8723B RSSI-based Antenna Detection is done\n");
return false;
}
@@ -307,7 +316,7 @@ odm_sw_ant_div_check_before_link(
}
}
if (dm->adapter == NULL) { /* For BSOD when plug/unplug fast. //By YJ,120413 */
if (dm->adapter == NULL) { /* @For BSOD when plug/unplug fast. //By YJ,120413 */
/* The ODM structure is not initialized. */
return false;
}
@@ -324,33 +333,35 @@ odm_sw_ant_div_check_before_link(
odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK);
PHYDM_DBG(dm, DBG_ANT_DIV,
"odm_sw_ant_div_check_before_link(): rf_change_in_progress(%x), e_rf_power_state(%x)\n",
mgnt_info->RFChangeInProgress, hal_data->eRFPowerState);
"%s: rf_change_in_progress(%x), e_rf_power_state(%x)\n",
__func__, mgnt_info->RFChangeInProgress,
hal_data->eRFPowerState);
dm_swat_table->swas_no_link_state = 0;
return false;
} else
odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK);
PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->swas_no_link_state = %d\n", dm_swat_table->swas_no_link_state);
/* 1 Run AntDiv mechanism "Before Link" part. */
PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->swas_no_link_state = %d\n",
dm_swat_table->swas_no_link_state);
/* @1 Run AntDiv mechanism "Before Link" part. */
if (dm_swat_table->swas_no_link_state == 0) {
/* 1 Prepare to do Scan again to check current antenna state. */
/* @1 Prepare to do Scan again to check current antenna state. */
/* Set check state to next step. */
dm_swat_table->swas_no_link_state = 1;
/* Copy Current Scan list. */
/* @Copy Current Scan list. */
mgnt_info->tmpNumBssDesc = mgnt_info->NumBssDesc;
PlatformMoveMemory((void *)mgnt_info->tmpbssDesc, (void *)mgnt_info->bssDesc, sizeof(RT_WLAN_BSS) * MAX_BSS_DESC);
/* Go back to scan function again. */
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link: Scan one more time\n");
/* @Go back to scan function again. */
PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Scan one more time\n",
__func__);
mgnt_info->ScanStep = 0;
mgnt_info->bScanAntDetect = true;
scan_channel = odm_sw_ant_div_select_scan_chnl(adapter);
if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
if (fat_tab->rx_idle_ant == MAIN_ANT)
odm_update_rx_idle_ant(dm, AUX_ANT);
@@ -358,7 +369,10 @@ odm_sw_ant_div_check_before_link(
odm_update_rx_idle_ant(dm, MAIN_ANT);
if (scan_channel == 0) {
PHYDM_DBG(dm, DBG_ANT_DIV,
"odm_sw_ant_div_check_before_link(): No AP List Avaiable, Using ant(%s)\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "AUX_ANT" : "MAIN_ANT");
"%s: No AP List Avaiable, Using ant(%s)\n",
__func__,
(fat_tab->rx_idle_ant == MAIN_ANT) ?
"AUX_ANT" : "MAIN_ANT");
if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) {
dm_swat_table->ant_5g = fat_tab->rx_idle_ant;
@@ -371,56 +385,67 @@ odm_sw_ant_div_check_before_link(
}
PHYDM_DBG(dm, DBG_ANT_DIV,
"odm_sw_ant_div_check_before_link: Change to %s for testing.\n", ((fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
"%s: Change to %s for testing.\n", __func__,
((fat_tab->rx_idle_ant == MAIN_ANT) ?
"MAIN_ANT" : "AUX_ANT"));
} else if (dm->support_ic_type & (ODM_RTL8723B)) {
/*Switch Antenna to another one.*/
tmp_swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH);
if ((dm_swat_table->cur_antenna == MAIN_ANT) && (tmp_swas_no_link_bk_reg948 == 0x200)) {
if (dm_swat_table->cur_antenna == MAIN_ANT && tmp_swas_no_link_bk_reg948 == 0x200) {
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
dm_swat_table->cur_antenna = AUX_ANT;
} else {
PHYDM_DBG(dm, DBG_ANT_DIV, "Reg[948]= (( %x )) was in wrong state\n", tmp_swas_no_link_bk_reg948);
PHYDM_DBG(dm, DBG_ANT_DIV,
"Reg[948]= (( %x )) was in wrong state\n",
tmp_swas_no_link_bk_reg948);
return false;
}
ODM_delay_us(10);
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link: Change to (( %s-ant)) for testing.\n", (dm_swat_table->cur_antenna == MAIN_ANT) ? "MAIN" : "AUX");
PHYDM_DBG(dm, DBG_ANT_DIV,
"%s: Change to (( %s-ant)) for testing.\n",
__func__,
(dm_swat_table->cur_antenna == MAIN_ANT) ?
"MAIN" : "AUX");
}
odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
return true;
} else { /* dm_swat_table->swas_no_link_state == 1 */
/* 1 ScanComple() is called after antenna swiched. */
/* 1 Check scan result and determine which antenna is going */
/* 1 to be used. */
} else { /* @dm_swat_table->swas_no_link_state == 1 */
/* @1 ScanComple() is called after antenna swiched. */
/* @1 Check scan result and determine which antenna is going */
/* @1 to be used. */
PHYDM_DBG(dm, DBG_ANT_DIV, " tmp_num_bss_desc= (( %d ))\n", mgnt_info->tmpNumBssDesc); /* debug for Dino */
PHYDM_DBG(dm, DBG_ANT_DIV, " tmp_num_bss_desc= (( %d ))\n",
mgnt_info->tmpNumBssDesc); /* @debug for Dino */
for (index = 0; index < mgnt_info->tmpNumBssDesc; index++) {
p_tmp_bss_desc = &mgnt_info->tmpbssDesc[index]; /* Antenna 1 */
p_test_bss_desc = &mgnt_info->bssDesc[index]; /* Antenna 2 */
p_tmp_bss_desc = &mgnt_info->tmpbssDesc[index]; /* @Antenna 1 */
p_test_bss_desc = &mgnt_info->bssDesc[index]; /* @Antenna 2 */
if (PlatformCompareMemory(p_test_bss_desc->bdBssIdBuf, p_tmp_bss_desc->bdBssIdBuf, 6) != 0) {
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): ERROR!! This shall not happen.\n");
PHYDM_DBG(dm, DBG_ANT_DIV,
"%s: ERROR!! This shall not happen.\n",
__func__);
continue;
}
if (dm->support_ic_type != ODM_RTL8723B) {
if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) {
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link: Compare scan entry: score++\n");
PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Compare scan entry: score++\n", __func__);
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
score++;
PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
} else if (p_tmp_bss_desc->RecvSignalPower < p_test_bss_desc->RecvSignalPower) {
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link: Compare scan entry: score--\n");
PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Compare scan entry: score--\n", __func__);
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
score--;
@@ -432,7 +457,7 @@ odm_sw_ant_div_check_before_link(
}
}
}
} else { /* 8723B */
} else { /* @8723B */
if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
PHYDM_DBG(dm, DBG_ANT_DIV, "channel_number == scan_channel->(( %d ))\n", p_tmp_bss_desc->ChannelNumber);
@@ -445,12 +470,16 @@ odm_sw_ant_div_check_before_link(
PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
#if 0
/* PHYDM_DBG(dm,DBG_ANT_DIV, "tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d))\n", tmp_power_diff,max_power_diff,min_power_diff); */
#endif
if (tmp_power_diff > max_power_diff)
max_power_diff = tmp_power_diff;
if (tmp_power_diff < min_power_diff)
min_power_diff = tmp_power_diff;
#if 0
/* PHYDM_DBG(dm,DBG_ANT_DIV, "max_power_diff: (( %d)),min_power_diff: (( %d))\n",max_power_diff,min_power_diff); */
#endif
PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
} else if (p_test_bss_desc->RecvSignalPower > p_tmp_bss_desc->RecvSignalPower) { /* Pow(Ant1) < Pow(Ant2) */
@@ -484,10 +513,14 @@ odm_sw_ant_div_check_before_link(
if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
if (mgnt_info->NumBssDesc != 0 && score < 0) {
PHYDM_DBG(dm, DBG_ANT_DIV,
"odm_sw_ant_div_check_before_link(): Using ant(%s)\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
"%s: Using ant(%s)\n", __func__,
(fat_tab->rx_idle_ant == MAIN_ANT) ?
"MAIN_ANT" : "AUX_ANT");
} else {
PHYDM_DBG(dm, DBG_ANT_DIV,
"odm_sw_ant_div_check_before_link(): Remain ant(%s)\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "AUX_ANT" : "MAIN_ANT");
"%s: Remain ant(%s)\n", __func__,
(fat_tab->rx_idle_ant == MAIN_ANT) ?
"AUX_ANT" : "MAIN_ANT");
if (fat_tab->rx_idle_ant == MAIN_ANT)
odm_update_rx_idle_ant(dm, AUX_ANT);
@@ -497,10 +530,16 @@ odm_sw_ant_div_check_before_link(
if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) {
dm_swat_table->ant_5g = fat_tab->rx_idle_ant;
PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_5g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
PHYDM_DBG(dm, DBG_ANT_DIV,
"dm_swat_table->ant_5g=%s\n",
(fat_tab->rx_idle_ant == MAIN_ANT) ?
"MAIN_ANT" : "AUX_ANT");
} else {
dm_swat_table->ant_2g = fat_tab->rx_idle_ant;
PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_2g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
PHYDM_DBG(dm, DBG_ANT_DIV,
"dm_swat_table->ant_2g=%s\n",
(fat_tab->rx_idle_ant == MAIN_ANT) ?
"MAIN_ANT" : "AUX_ANT");
}
} else if (dm->support_ic_type == ODM_RTL8723B) {
if (counter == 0) {
@@ -509,16 +548,16 @@ odm_sw_ant_div_check_before_link(
dm->dm_swat_table.rssi_ant_dect_result = false;
PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again\n");
/* 3 [ Scan again ] */
/* @3 [ Scan again ] */
odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
return true;
} else { /* pre_aux_fail_detec == true */
/* 2 [ Single Antenna ] */
/* @2 [ Single Antenna ] */
dm->dm_swat_table.pre_aux_fail_detec = false;
dm->dm_swat_table.rssi_ant_dect_result = true;
PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Still cannot find any AP ]]\n");
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Single antenna\n");
PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__);
}
dm->dm_swat_table.aux_fail_detec_counter++;
} else {
@@ -533,74 +572,82 @@ odm_sw_ant_div_check_before_link(
PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff);
PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff);
} else { /* counter==1,2 */
} else { /* @counter==1,2 */
avg_power_diff = power_diff / counter;
PHYDM_DBG(dm, DBG_ANT_DIV, "avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d ))\n", avg_power_diff, counter, power_diff);
}
/* 2 [ Retry ] */
if ((avg_power_diff >= power_target_L) && (avg_power_diff <= power_target_H)) {
/* @2 [ Retry ] */
if (avg_power_diff >= power_target_L && avg_power_diff <= power_target_H) {
dm->dm_swat_table.retry_counter++;
if (dm->dm_swat_table.retry_counter <= 3) {
dm->dm_swat_table.rssi_ant_dect_result = false;
PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]]\n", avg_power_diff);
/* 3 [ Scan again ] */
/* @3 [ Scan again ] */
odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
return true;
} else {
dm->dm_swat_table.rssi_ant_dect_result = true;
PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Still Low confidence result ]] (( retry_counter > 3 ))\n");
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Single antenna\n");
PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__);
}
}
/* 2 [ Dual Antenna ] */
/* @2 [ Dual Antenna ] */
else if ((mgnt_info->NumBssDesc != 0) && (avg_power_diff < power_target_L)) {
dm->dm_swat_table.rssi_ant_dect_result = true;
if (dm->dm_swat_table.ANTB_ON == false) {
dm->dm_swat_table.ANTA_ON = true;
dm->dm_swat_table.ANTB_ON = true;
}
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Dual antenna\n");
PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Dual antenna\n", __func__);
dm->dm_swat_table.dual_ant_counter++;
/* set bt coexDM from 1ant coexDM to 2ant coexDM */
BT_SetBtCoexAntNum(adapter, BT_COEX_ANT_TYPE_DETECTED, 2);
/* 3 [ Init antenna diversity ] */
/* @3 [ Init antenna diversity ] */
dm->support_ability |= ODM_BB_ANT_DIV;
odm_ant_div_init(dm);
}
/* 2 [ Single Antenna ] */
/* @2 [ Single Antenna ] */
else if (avg_power_diff > power_target_H) {
dm->dm_swat_table.rssi_ant_dect_result = true;
if (dm->dm_swat_table.ANTB_ON == true) {
dm->dm_swat_table.ANTA_ON = true;
dm->dm_swat_table.ANTB_ON = false;
/* bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 1); */
#if 0
/* @bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 1); */
#endif
}
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Single antenna\n");
PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__);
dm->dm_swat_table.single_ant_counter++;
}
}
#if 0
/* PHYDM_DBG(dm,DBG_ANT_DIV, "is_result=(( %d ))\n",dm->dm_swat_table.rssi_ant_dect_result); */
PHYDM_DBG(dm, DBG_ANT_DIV, "dual_ant_counter = (( %d )), single_ant_counter = (( %d )) , retry_counter = (( %d )) , aux_fail_detec_counter = (( %d ))\n\n\n",
dm->dm_swat_table.dual_ant_counter, dm->dm_swat_table.single_ant_counter, dm->dm_swat_table.retry_counter, dm->dm_swat_table.aux_fail_detec_counter);
#endif
PHYDM_DBG(dm, DBG_ANT_DIV,
"dual_ant_counter = (( %d )), single_ant_counter = (( %d )) , retry_counter = (( %d )) , aux_fail_detec_counter = (( %d ))\n\n\n",
dm->dm_swat_table.dual_ant_counter,
dm->dm_swat_table.single_ant_counter,
dm->dm_swat_table.retry_counter,
dm->dm_swat_table.aux_fail_detec_counter);
/* 2 recover the antenna setting */
/* @2 recover the antenna setting */
if (dm->dm_swat_table.ANTB_ON == false)
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, (dm_swat_table->swas_no_link_bk_reg948));
PHYDM_DBG(dm, DBG_ANT_DIV, "is_result=(( %d )), Recover Reg[948]= (( %x ))\n\n", dm->dm_swat_table.rssi_ant_dect_result, dm_swat_table->swas_no_link_bk_reg948);
PHYDM_DBG(dm, DBG_ANT_DIV,
"is_result=(( %d )), Recover Reg[948]= (( %x ))\n\n",
dm->dm_swat_table.rssi_ant_dect_result,
dm_swat_table->swas_no_link_bk_reg948);
}
/* Check state reset to default and wait for next time. */
/* @Check state reset to default and wait for next time. */
dm_swat_table->swas_no_link_state = 0;
mgnt_info->bScanAntDetect = false;
@@ -608,236 +655,237 @@ odm_sw_ant_div_check_before_link(
}
#else
return false;
return false;
#endif
return false;
}
/* 1 [3. PSD method] ========================================================== */
void
odm_single_dual_antenna_detection_psd(
void *dm_void
)
/* @1 [3. PSD method] ========================================================== */
void odm_single_dual_antenna_detection_psd(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 channel_ori;
u8 initial_gain = 0x36;
u8 tone_idx;
u8 tone_lenth_1 = 7, tone_lenth_2 = 4;
u16 tone_idx_1[7] = {88, 104, 120, 8, 24, 40, 56};
u16 tone_idx_2[4] = {8, 24, 40, 56};
u32 psd_report_main[11] = {0}, psd_report_aux[11] = {0};
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 channel_ori;
u8 initial_gain = 0x36;
u8 tone_idx;
u8 tone_lenth_1 = 7, tone_lenth_2 = 4;
u16 tone_idx_1[7] = {88, 104, 120, 8, 24, 40, 56};
u16 tone_idx_2[4] = {8, 24, 40, 56};
u32 psd_report_main[11] = {0}, psd_report_aux[11] = {0};
/* u8 tone_lenth_1=4, tone_lenth_2=2; */
/* u16 tone_idx_1[4]={88, 120, 24, 56}; */
/* u16 tone_idx_2[2]={ 24, 56}; */
/* u32 psd_report_main[6]={0}, psd_report_aux[6]={0}; */
u32 PSD_report_temp, max_psd_report_main = 0, max_psd_report_aux = 0;
u32 PSD_power_threshold;
u32 main_psd_result = 0, aux_psd_result = 0;
u32 regc50, reg948, regb2c, regc14, reg908;
u32 i = 0, test_num = 8;
u32 PSD_report_temp, max_psd_report_main = 0, max_psd_report_aux = 0;
u32 PSD_power_threshold;
u32 main_psd_result = 0, aux_psd_result = 0;
u32 regc50, reg948, regb2c, regc14, reg908;
u32 i = 0, test_num = 8;
if (dm->support_ic_type != ODM_RTL8723B)
return;
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection_psd()============>\n");
PHYDM_DBG(dm, DBG_ANT_DIV, "%s============>\n", __func__);
/* 2 [ Backup Current RF/BB Settings ] */
/* @2 [ Backup Current RF/BB Settings ] */
channel_ori = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD);
regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD);
regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
regc14 = odm_get_bb_reg(dm, 0xc14, MASKDWORD);
reg908 = odm_get_bb_reg(dm, 0x908, MASKDWORD);
regc14 = odm_get_bb_reg(dm, R_0xc14, MASKDWORD);
reg908 = odm_get_bb_reg(dm, R_0x908, MASKDWORD);
/* 2 [ setting for doing PSD function (CH4)] */
odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 0); /* disable whole CCK block */
/* @2 [ setting for doing PSD function (CH4)] */
odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 0); /* @disable whole CCK block */
odm_write_1byte(dm, REG_TXPAUSE, 0xFF); /* Turn off TX -> Pause TX Queue */
odm_set_bb_reg(dm, 0xC14, MASKDWORD, 0x0); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */
odm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0); /* @[ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */
/* PHYTXON while loop */
odm_set_bb_reg(dm, 0x908, MASKDWORD, 0x803);
while (odm_get_bb_reg(dm, 0xdf4, BIT(6))) {
odm_set_bb_reg(dm, R_0x908, MASKDWORD, 0x803);
while (odm_get_bb_reg(dm, R_0xdf4, BIT(6))) {
i++;
if (i > 1000000) {
PHYDM_DBG(dm, DBG_ANT_DIV, "Wait in %s() more than %d times!\n", __FUNCTION__, i);
PHYDM_DBG(dm, DBG_ANT_DIV,
"Wait in %s() more than %d times!\n",
__FUNCTION__, i);
break;
}
}
odm_set_bb_reg(dm, 0xc50, 0x7f, initial_gain);
odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH4 & 40M */
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */
odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pt */ /* Set PSD 128 ptss */
odm_set_bb_reg(dm, R_0xc50, 0x7f, initial_gain);
odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH4 & 40M */
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* @3 wire Disable 88c[23:20]=0xf */
odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pt */ /* Set PSD 128 ptss */
ODM_delay_us(3000);
/* @2 [ Doing PSD Function in (CH4)] */
/* 2 [ Doing PSD Function in (CH4)] */
/* Antenna A */
/* @Antenna A */
PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant (CH4)\n");
odm_set_bb_reg(dm, 0x948, 0xfff, 0x200);
odm_set_bb_reg(dm, R_0x948, 0xfff, 0x200);
ODM_delay_us(10);
PHYDM_DBG(dm, DBG_ANT_DIV, "dbg\n");
for (i = 0; i < test_num; i++) {
for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain);
/* if( PSD_report_temp>psd_report_main[tone_idx] ) */
/* @if( PSD_report_temp>psd_report_main[tone_idx] ) */
psd_report_main[tone_idx] += PSD_report_temp;
}
}
/* Antenna B */
/* @Antenna B */
PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant (CH4)\n");
odm_set_bb_reg(dm, 0x948, 0xfff, 0x280);
odm_set_bb_reg(dm, R_0x948, 0xfff, 0x280);
ODM_delay_us(10);
for (i = 0; i < test_num; i++) {
for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain);
/* if( PSD_report_temp>psd_report_aux[tone_idx] ) */
/* @if( PSD_report_temp>psd_report_aux[tone_idx] ) */
psd_report_aux[tone_idx] += PSD_report_temp;
}
}
/* 2 [ Doing PSD Function in (CH8)] */
/* @2 [ Doing PSD Function in (CH8)] */
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* @3 wire enable 88c[23:20]=0x0 */
ODM_delay_us(3000);
odm_set_bb_reg(dm, 0xc50, 0x7f, initial_gain);
odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH8 & 40M */
odm_set_bb_reg(dm, R_0xc50, 0x7f, initial_gain);
odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH8 & 40M */
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* @3 wire Disable 88c[23:20]=0xf */
ODM_delay_us(3000);
/* Antenna A */
/* @Antenna A */
PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant (CH8)\n");
odm_set_bb_reg(dm, 0x948, 0xfff, 0x200);
odm_set_bb_reg(dm, R_0x948, 0xfff, 0x200);
ODM_delay_us(10);
for (i = 0; i < test_num; i++) {
for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain);
/* if( PSD_report_temp>psd_report_main[tone_idx] ) */
/* @if( PSD_report_temp>psd_report_main[tone_idx] ) */
psd_report_main[tone_lenth_1 + tone_idx] += PSD_report_temp;
}
}
/* Antenna B */
/* @Antenna B */
PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant (CH8)\n");
odm_set_bb_reg(dm, 0x948, 0xfff, 0x280);
odm_set_bb_reg(dm, R_0x948, 0xfff, 0x280);
ODM_delay_us(10);
for (i = 0; i < test_num; i++) {
for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain);
/* if( PSD_report_temp>psd_report_aux[tone_idx] ) */
/* @if( PSD_report_temp>psd_report_aux[tone_idx] ) */
psd_report_aux[tone_lenth_1 + tone_idx] += PSD_report_temp;
}
}
/* 2 [ Calculate Result ] */
/* @2 [ Calculate Result ] */
PHYDM_DBG(dm, DBG_ANT_DIV, "\nMain PSD Result: (ALL)\n");
for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1), psd_report_main[tone_idx]);
PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1),
psd_report_main[tone_idx]);
main_psd_result += psd_report_main[tone_idx];
if (psd_report_main[tone_idx] > max_psd_report_main)
max_psd_report_main = psd_report_main[tone_idx];
}
PHYDM_DBG(dm, DBG_ANT_DIV, "--------------------------- \nTotal_Main= (( %d ))\n", main_psd_result);
PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Main = (( %d ))\n", max_psd_report_main);
PHYDM_DBG(dm, DBG_ANT_DIV,
"--------------------------- \nTotal_Main= (( %d ))\n",
main_psd_result);
PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Main = (( %d ))\n",
max_psd_report_main);
PHYDM_DBG(dm, DBG_ANT_DIV, "\nAux PSD Result: (ALL)\n");
for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1), psd_report_aux[tone_idx]);
PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1),
psd_report_aux[tone_idx]);
aux_psd_result += psd_report_aux[tone_idx];
if (psd_report_aux[tone_idx] > max_psd_report_aux)
max_psd_report_aux = psd_report_aux[tone_idx];
}
PHYDM_DBG(dm, DBG_ANT_DIV, "--------------------------- \nTotal_Aux= (( %d ))\n", aux_psd_result);
PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Aux = (( %d ))\n\n", max_psd_report_aux);
PHYDM_DBG(dm, DBG_ANT_DIV,
"--------------------------- \nTotal_Aux= (( %d ))\n",
aux_psd_result);
PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Aux = (( %d ))\n\n",
max_psd_report_aux);
/* main_psd_result=main_psd_result-max_psd_report_main; */
/* aux_psd_result=aux_psd_result-max_psd_report_aux; */
/* @main_psd_result=main_psd_result-max_psd_report_main; */
/* @aux_psd_result=aux_psd_result-max_psd_report_aux; */
PSD_power_threshold = (main_psd_result * 7) >> 3;
PHYDM_DBG(dm, DBG_ANT_DIV, "[ Main_result, Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", main_psd_result, aux_psd_result, PSD_power_threshold);
PHYDM_DBG(dm, DBG_ANT_DIV,
"[ Main_result, Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n",
main_psd_result, aux_psd_result, PSD_power_threshold);
/* 3 [ Dual Antenna ] */
/* @3 [ Dual Antenna ] */
if (aux_psd_result >= PSD_power_threshold) {
if (dm->dm_swat_table.ANTB_ON == false) {
dm->dm_swat_table.ANTA_ON = true;
dm->dm_swat_table.ANTB_ON = true;
}
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Dual antenna\n");
PHYDM_DBG(dm, DBG_ANT_DIV,
"odm_sw_ant_div_check_before_link(): Dual antenna\n");
#if 0
/* set bt coexDM from 1ant coexDM to 2ant coexDM */
/* bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 2); */
/* @bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 2); */
#endif
/* Init antenna diversity */
/* @Init antenna diversity */
dm->support_ability |= ODM_BB_ANT_DIV;
odm_ant_div_init(dm);
}
/* 3 [ Single Antenna ] */
/* @3 [ Single Antenna ] */
else {
if (dm->dm_swat_table.ANTB_ON == true) {
dm->dm_swat_table.ANTA_ON = true;
dm->dm_swat_table.ANTB_ON = false;
}
PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Single antenna\n");
PHYDM_DBG(dm, DBG_ANT_DIV,
"odm_sw_ant_div_check_before_link(): Single antenna\n");
}
/* 2 [ Recover all parameters ] */
/* @2 [ Recover all parameters ] */
odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, channel_ori);
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */
odm_set_bb_reg(dm, 0xc50, 0x7f, regc50);
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* @3 wire enable 88c[23:20]=0x0 */
odm_set_bb_reg(dm, R_0xc50, 0x7f, regc50);
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 1); /* enable whole CCK block */
odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 1); /* @enable whole CCK block */
odm_write_1byte(dm, REG_TXPAUSE, 0x0); /* Turn on TX */ /* Resume TX Queue */
odm_set_bb_reg(dm, 0xC14, MASKDWORD, regc14); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] */
odm_set_bb_reg(dm, 0x908, MASKDWORD, reg908);
odm_set_bb_reg(dm, R_0xc14, MASKDWORD, regc14); /* @[ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] */
odm_set_bb_reg(dm, R_0x908, MASKDWORD, reg908);
return;
}
#endif
void
odm_sw_ant_detect_init(
void *dm_void
)
void odm_sw_ant_detect_init(void *dm_void)
{
#if (defined(CONFIG_ANT_DETECTION))
#if (RTL8723B_SUPPORT == 1)
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
if (dm->support_ic_type != ODM_RTL8723B)
return;
/* dm_swat_table->pre_antenna = MAIN_ANT; */
/* dm_swat_table->cur_antenna = MAIN_ANT; */
/* @dm_swat_table->pre_antenna = MAIN_ANT; */
/* @dm_swat_table->cur_antenna = MAIN_ANT; */
dm_swat_table->swas_no_link_state = 0;
dm_swat_table->pre_aux_fail_detec = false;
dm_swat_table->swas_no_link_bk_reg948 = 0xff;
#ifdef CONFIG_PSD_TOOL
#ifdef CONFIG_PSD_TOOL
phydm_psd_init(dm);
#endif
#endif
#endif
}
#endif

72
hal/phydm/phydm_antdect.h
View File

@@ -23,78 +23,56 @@
*
*****************************************************************************/
#ifndef __PHYDMANTDECT_H__
#define __PHYDMANTDECT_H__
#ifndef __PHYDMANTDECT_H__
#define __PHYDMANTDECT_H__
#define ANTDECT_VERSION "2.1" /*2015.07.29 by YuChen*/
#define ANTDECT_VERSION "2.1"
#if (defined(CONFIG_ANT_DETECTION))
/* #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */
/* ANT Test */
#define ANTTESTALL 0x00 /*ant A or B will be Testing*/
#define ANTTESTA 0x01 /*ant A will be Testing*/
#define ANTTESTB 0x02 /*ant B will be testing*/
#define MAX_ANTENNA_DETECTION_CNT 10
/* @#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */
/* @ANT Test */
#define ANTTESTALL 0x00 /*@ant A or B will be Testing*/
#define ANTTESTA 0x01 /*@ant A will be Testing*/
#define ANTTESTB 0x02 /*@ant B will be testing*/
#define MAX_ANTENNA_DETECTION_CNT 10
struct _ANT_DETECTED_INFO {
boolean is_ant_detected;
u32 db_for_ant_a;
u32 db_for_ant_b;
u32 db_for_ant_o;
boolean is_ant_detected;
u32 db_for_ant_a;
u32 db_for_ant_b;
u32 db_for_ant_o;
};
enum dm_swas {
antenna_a = 1,
antenna_b = 2,
antenna_max = 3,
};
/* @1 [1. Single Tone method] =================================================== */
/* 1 [1. Single Tone method] =================================================== */
void
odm_single_dual_antenna_default_setting(
void *dm_void
);
void odm_single_dual_antenna_default_setting(
void *dm_void);
boolean
odm_single_dual_antenna_detection(
void *dm_void,
u8 mode
);
void *dm_void,
u8 mode);
/* 1 [2. Scan AP RSSI method] ================================================== */
/* @1 [2. Scan AP RSSI method] ================================================== */
#define sw_ant_div_check_before_link odm_sw_ant_div_check_before_link
#define sw_ant_div_check_before_link odm_sw_ant_div_check_before_link
boolean
odm_sw_ant_div_check_before_link(
void *dm_void
);
void *dm_void);
/* @1 [3. PSD method] ========================================================== */
void odm_single_dual_antenna_detection_psd(
void *dm_void);
/* 1 [3. PSD method] ========================================================== */
void
odm_single_dual_antenna_detection_psd(
void *dm_void
);
void odm_sw_ant_detect_init(void *dm_void);
#endif
void
odm_sw_ant_detect_init(
void *dm_void
);
#endif

5799
hal/phydm/phydm_antdiv.c
View File

File diff suppressed because it is too large Load Diff

500
hal/phydm/phydm_antdiv.h
View File

@@ -23,35 +23,49 @@
*
*****************************************************************************/
#ifndef __PHYDMANTDIV_H__
#define __PHYDMANTDIV_H__
#ifndef __PHYDMANTDIV_H__
#define __PHYDMANTDIV_H__
/*#define ANTDIV_VERSION "2.0" //2014.11.04*/
/*#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/
/*#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/
/*#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen, remove 92c 92d 8723a*/
/*#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B*/
/*#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not need to check the antenna is control by BT,
because antenna diversity only works when BT is disable or radio off*/
/*#define ANTDIV_VERSION "3.4" 2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna Diversity*/
/*#define ANTDIV_VERSION "3.5" 2015.10.07 Stanley Always check antenna detection result from BT-coex. for 8723B, not from PHYDM*/
/*#define ANTDIV_VERSION "3.6"*/ /*2015.11.16 Stanley */
/*#define ANTDIV_VERSION "3.7"*/ /*2015.11.20 Dino Add SmartAnt FAT Patch */
/*#define ANTDIV_VERSION "3.8" 2015.12.21 Dino, Add SmartAnt dynamic training packet num */
/*#define ANTDIV_VERSION "3.9" 2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and add cmd for adjust truth table */
#define ANTDIV_VERSION "4.0" /*2017.05.25 Mark, Add SW antenna diversity for 8821c because HW transient issue */
/*@#define ANTDIV_VERSION "2.0" //2014.11.04*/
/*@#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/
/*@#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/
/*@#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen,remove 92c 92d 8723a*/
/*@#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna*/
/*@diversity when BT is enable for 8723B*/
/*@#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not*/
/*@need to check the antenna is control by BT,*/
/*@because antenna diversity only works when */
/*@BT is disable or radio off*/
/*@#define ANTDIV_VERSION "3.4" 2015.08.28 Dino 1.Add 8821A Smart */
/*@Antenna 2. Add 8188F SW S0S1 Antenna*/
/*@Diversity*/
/*@#define ANTDIV_VERSION "3.5" 2015.10.07 Stanley Always check antenna*/
/*@detection result from BT-coex. for 8723B,*/
/*@not from PHYDM*/
/*@#define ANTDIV_VERSION "3.6"*/ /*@2015.11.16 Stanley */
/*@#define ANTDIV_VERSION "3.7" 2015.11.20 Dino Add SmartAnt FAT Patch */
/*@#define ANTDIV_VERSION "3.8" 2015.12.21 Dino, Add SmartAnt dynamic*/
/*@training packet num */
/*@#define ANTDIV_VERSION "3.9" 2016.01.05 Dino, Add SmartAnt cmd for*/
/*@converting single & two smtant, and add cmd*/
/*@for adjust truth table */
#define ANTDIV_VERSION "4.0" /*@2017.05.25 Mark, Add SW antenna diversity*/
/*@for 8821c because HW transient issue */
/* 1 ============================================================
/* @1 ============================================================
* 1 Definition
* 1 ============================================================ */
* 1 ============================================================
*/
#define ANTDIV_INIT 0xff
#define MAIN_ANT 1 /*ant A or ant Main or S1*/
#define AUX_ANT 2 /*AntB or ant Aux or S0*/
#define MAX_ANT 3 /* 3 for AP using*/
#define MAIN_ANT 1 /*@ant A or ant Main or S1*/
#define AUX_ANT 2 /*@AntB or ant Aux or S0*/
#define MAX_ANT 3 /* @3 for AP using*/
#define ANT1_2G 0 /* = ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */
#define ANT2_2G 1 /* = ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */
#define ANT1_2G 0
/* @= ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */
#define ANT2_2G 1
/* @= ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */
/*smart antenna*/
#define SUPPORT_RF_PATH_NUM 4
#define SUPPORT_BEAM_PATTERN_NUM 4
@@ -63,21 +77,27 @@
#define FIX_TX_AT_MAIN 1
#define FIX_AUX_AT_MAIN 2
/* Antenna Diversty Control type */
/* @Antenna Diversty Control type */
#define ODM_AUTO_ANT 0
#define ODM_FIX_MAIN_ANT 1
#define ODM_FIX_AUX_ANT 2
#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A)
#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B)
#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT)
#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B |\
ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A |\
ODM_RTL8197F | ODM_RTL8721D)
#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 |\
ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B)
#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT)
#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B)
#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D)
#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C)
#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B |\
ODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D |\
ODM_RTL8197F)
#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 |\
ODM_RTL8821C | ODM_RTL8822B)
#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E)
#define ODM_EVM_ANTDIV_IC (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8822B)
#define ODM_ANTDIV_2G BIT(0)
#define ODM_ANTDIV_5G BIT(1)
@@ -85,6 +105,10 @@
#define ANTDIV_ON 1
#define ANTDIV_OFF 0
#define ANT_PATH_A 0
#define ANT_PATH_B 1
#define ANT_PATH_AB 2
#define FAT_ON 1
#define FAT_OFF 0
@@ -138,25 +162,34 @@
#define RSSI_CHECK_RESET_PERIOD 10
#define RSSI_CHECK_THRESHOLD 50
/*Hong Lin Smart antenna*/
/*@Hong Lin Smart antenna*/
#define HL_SMTANT_2WIRE_DATA_LEN 24
/* 1 ============================================================
#if (RTL8723D_SUPPORT == 1)
#ifndef CONFIG_ANTDIV_PERIOD
#define CONFIG_ANTDIV_PERIOD 1
#endif
#endif
/* @1 ============================================================
* 1 structure
* 1 ============================================================ */
* 1 ============================================================
*/
struct sw_antenna_switch {
u8 double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than check this antenna again*/
u8 double_chk_flag;
/*@If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than*/
/*@check this antenna again*/
u8 try_flag;
s32 pre_rssi;
u8 cur_antenna;
u8 pre_antenna;
u8 pre_ant;
u8 rssi_trying;
u8 reset_idx;
u8 train_time;
u8 train_time_flag; /*base on RSSI difference between two antennas*/
struct phydm_timer_list phydm_sw_antenna_switch_timer;
u8 train_time_flag;
/*@base on RSSI difference between two antennas*/
struct phydm_timer_list sw_antdiv_timer;
u32 pkt_cnt_sw_ant_div_by_ctrl_frame;
boolean is_sw_ant_div_by_ctrl_frame;
@@ -166,7 +199,7 @@ struct sw_antenna_switch {
#endif
#endif
/* AntDect (Before link Antenna Switch check) need to be moved*/
/* @AntDect (Before link Antenna Switch check) need to be moved*/
u16 single_ant_counter;
u16 dual_ant_counter;
u16 aux_fail_detec_counter;
@@ -174,25 +207,22 @@ struct sw_antenna_switch {
u8 swas_no_link_state;
u32 swas_no_link_bk_reg948;
boolean ANTA_ON; /*To indicate ant A is or not*/
boolean ANTB_ON; /*To indicate ant B is on or not*/
boolean ANTB_ON; /*@To indicate ant B is on or not*/
boolean pre_aux_fail_detec;
boolean rssi_ant_dect_result;
u8 ant_5g;
u8 ant_2g;
};
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
struct _BF_DIV_COEX_ {
boolean w_bfer_client[ODM_ASSOCIATE_ENTRY_NUM];
boolean w_bfee_client[ODM_ASSOCIATE_ENTRY_NUM];
u32 MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM];
u32 MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM];
u32 MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM];
u32 MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM];
u8 bd_ccoex_type_wbfer;
u8 bd_ccoex_type_wbfer;
u8 num_txbfee_client;
u8 num_txbfer_client;
u8 bdc_try_counter;
@@ -215,7 +245,6 @@ struct _BF_DIV_COEX_ {
#endif
#endif
struct phydm_fat_struct {
u8 bssid[6];
u8 antsel_rx_keep_0;
@@ -231,17 +260,19 @@ struct phydm_fat_struct {
u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_sum[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_sum[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
u8 rx_idle_ant;
u8 rx_idle_ant2;
u8 rvrt_val;
u8 ant_div_on_off;
u8 div_path_type;
boolean is_become_linked;
u32 min_max_rssi;
u8 idx_ant_div_counter_2g;
@@ -249,17 +280,17 @@ struct phydm_fat_struct {
u8 ant_div_2g_5g;
#ifdef ODM_EVM_ENHANCE_ANTDIV
/*For 1SS RX phy rate*/
u32 main_ant_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];
u32 aux_ant_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];
u32 main_ant_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u32 aux_ant_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];
/*@For 1SS RX phy rate*/
u32 main_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];
u32 aux_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];
u32 main_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u32 aux_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];
/*For 2SS RX phy rate*/
u32 main_ant_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2]; /*2SS with A1+B*/
u32 aux_ant_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2]; /*2SS with A2+B*/
u32 main_ant_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u32 aux_ant_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM];
/*@For 2SS RX phy rate*/
u32 main_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2];/*@2SS with A1+B*/
u32 aux_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2];/*@2SS with A2+B*/
u32 main_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u32 aux_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM];
boolean evm_method_enable;
u8 target_ant_evm;
@@ -277,10 +308,10 @@ struct phydm_fat_struct {
u32 main_crc32_fail_cnt;
u32 aux_crc32_fail_cnt;
u32 antdiv_tp_main;
u32 antdiv_tp_aux;
u32 antdiv_tp_main_cnt;
u32 antdiv_tp_aux_cnt;
u32 main_tp;
u32 aux_tp;
u32 main_tp_cnt;
u32 aux_tp_cnt;
u8 pre_antdiv_rssi;
u8 pre_antdiv_tp;
@@ -290,31 +321,32 @@ struct phydm_fat_struct {
u32 cck_ctrl_frame_cnt_aux;
u32 ofdm_ctrl_frame_cnt_main;
u32 ofdm_ctrl_frame_cnt_aux;
u32 main_ant_ctrl_frame_sum;
u32 aux_ant_ctrl_frame_sum;
u32 main_ant_ctrl_frame_cnt;
u32 aux_ant_ctrl_frame_cnt;
u32 main_ctrl_sum;
u32 aux_ctrl_sum;
u32 main_ctrl_cnt;
u32 aux_ctrl_cnt;
#endif
u8 b_fix_tx_ant;
boolean fix_ant_bfee;
boolean enable_ctrl_frame_antdiv;
boolean use_ctrl_frame_antdiv;
boolean *is_no_csi_feedback;
boolean force_antdiv_type;
u8 antdiv_type_dbg;
u8 hw_antsw_occur;
u8 *p_force_tx_ant_by_desc;
u8 force_tx_ant_by_desc; /*A temp value, will hook to driver team's outer parameter later*/
u8 *p_default_s0_s1;
u8 default_s0_s1;
u8 *p_force_tx_by_desc;
u8 force_tx_by_desc;
/*@A temp value, will hook to driver team's outer parameter later*/
u8 *p_default_s0_s1;
u8 default_s0_s1;
};
/* 1 ============================================================
/* @1 ============================================================
* 1 enumeration
* 1 ============================================================ */
* 1 ============================================================
*/
enum fat_state /*Fast antenna training*/
enum fat_state /*@Fast antenna training*/
{
FAT_BEFORE_LINK_STATE = 0,
FAT_PREPARE_STATE = 1,
@@ -329,289 +361,159 @@ enum ant_div_type {
FIXED_HW_ANTDIV = 0x03,
CG_TRX_SMART_ANTDIV = 0x04,
CGCS_RX_SW_ANTDIV = 0x05,
S0S1_SW_ANTDIV = 0x06, /*8723B intrnal switch S0 S1*/
S0S1_TRX_HW_ANTDIV = 0x07, /*TRX S0S1 diversity for 8723D*/
HL_SW_SMART_ANT_TYPE1 = 0x10, /*Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys, and each ant. is equipped with 4 antenna patterns*/
HL_SW_SMART_ANT_TYPE2 = 0x11 /*Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/
S0S1_SW_ANTDIV = 0x06, /*@8723B intrnal switch S0 S1*/
S0S1_TRX_HW_ANTDIV = 0x07, /*TRX S0S1 diversity for 8723D*/
HL_SW_SMART_ANT_TYPE1 = 0x10,
/*@Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys,*/
/*@and each ant. is equipped with 4 antenna patterns*/
HL_SW_SMART_ANT_TYPE2 = 0x11
/*@Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/
};
/* 1 ============================================================
/* @1 ============================================================
* 1 function prototype
* 1 ============================================================ */
* 1 ============================================================
*/
void odm_stop_antenna_switch_dm(void *dm_void);
void
odm_stop_antenna_switch_dm(
void *dm_void
);
void phydm_enable_antenna_diversity(void *dm_void);
void
phydm_enable_antenna_diversity(
void *dm_void
);
void odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C,....*/
);
void
odm_set_ant_config(
void *dm_void,
u8 ant_setting /* 0=A, 1=B, 2=C, .... */
);
#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link
void odm_sw_ant_div_rest_after_link(void *dm_void);
#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link
void odm_ant_div_on_off(void *dm_void, u8 swch, u8 path);
void odm_sw_ant_div_rest_after_link(
void *dm_void
);
void
odm_ant_div_on_off(
void *dm_void,
u8 swch
);
void
odm_tx_by_tx_desc_or_reg(
void *dm_void,
u8 swch
);
void odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch);
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
void
phydm_antdiv_reset_statistic(
void *dm_void,
u32 macid
);
void phydm_antdiv_reset_statistic(void *dm_void, u32 macid);
void
odm_update_rx_idle_ant(
void *dm_void,
u8 ant
);
void odm_update_rx_idle_ant(void *dm_void, u8 ant);
void
phydm_set_antdiv_val(
void *dm_void,
u32 *val_buf,
u8 val_len
);
void phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant);
void phydm_set_antdiv_val(void *dm_void, u32 *val_buf, u8 val_len);
#if (RTL8723B_SUPPORT == 1)
void
odm_update_rx_idle_ant_8723b(
void *dm_void,
u8 ant,
u32 default_ant,
u32 optional_ant
);
void odm_update_rx_idle_ant_8723b(void *dm_void, u8 ant, u32 default_ant,
u32 optional_ant);
#endif
#if (RTL8188F_SUPPORT == 1)
void
phydm_update_rx_idle_antenna_8188F(
void *dm_void,
u32 default_ant
);
void phydm_update_rx_idle_antenna_8188F(void *dm_void, u32 default_ant);
#endif
#if (RTL8723D_SUPPORT == 1)
void
phydm_set_tx_ant_pwr_8723d(
void *dm_void,
u8 ant
);
void phydm_set_tx_ant_pwr_8723d(void *dm_void, u8 ant);
void
odm_update_rx_idle_ant_8723d(
void *dm_void,
u8 ant,
u32 default_ant,
u32 optional_ant
);
void odm_update_rx_idle_ant_8723d(void *dm_void, u8 ant, u32 default_ant,
u32 optional_ant);
#endif
#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void
odm_sw_antdiv_callback(
struct phydm_timer_list *timer
);
void
odm_sw_antdiv_workitem_callback(
void *context
);
void odm_sw_antdiv_callback(struct phydm_timer_list *timer);
void odm_sw_antdiv_workitem_callback(void *context);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
void
odm_sw_antdiv_workitem_callback(
void *context
);
void odm_sw_antdiv_workitem_callback(void *context);
void
odm_sw_antdiv_callback(
void *function_context
);
void odm_sw_antdiv_callback(void *function_context);
#endif
void
odm_s0s1_sw_ant_div_by_ctrl_frame(
void *dm_void,
u8 step
);
void odm_s0s1_sw_ant_div_by_ctrl_frame(void *dm_void, u8 step);
void
odm_antsel_statistics_of_ctrl_frame(
void *dm_void,
u8 antsel_tr_mux,
u32 rx_pwdb_all
);
void odm_antsel_statistics_ctrl(void *dm_void, u8 antsel_tr_mux,
u32 rx_pwdb_all);
void
odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(
void *dm_void,
void *phy_info_void,
void *pkt_info_void
);
void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(void *dm_void,
void *phy_info_void,
void *pkt_info_void);
#endif
#ifdef ODM_EVM_ENHANCE_ANTDIV
void
phydm_evm_sw_antdiv_init(
void *dm_void
);
void phydm_evm_sw_antdiv_init(void *dm_void);
void
odm_evm_fast_ant_training_callback(
void *dm_void
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void phydm_evm_antdiv_callback(struct phydm_timer_list *timer);
void phydm_evm_antdiv_workitem_callback(void *context);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
void phydm_evm_antdiv_callback(void *dm_void);
void phydm_evm_antdiv_workitem_callback(void *context);
#else
void phydm_evm_antdiv_callback(void *dm_void);
#endif
void
odm_hw_ant_div(
void *dm_void
);
#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
void
odm_fast_ant_training(
void *dm_void
);
void
odm_fast_ant_training_callback(
void *dm_void
);
void
odm_fast_ant_training_work_item_callback(
void *dm_void
);
#endif
void
odm_ant_div_init(
void *dm_void
);
void odm_hw_ant_div(void *dm_void);
void
odm_ant_div(
void *dm_void
);
#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
void odm_fast_ant_training(
void *dm_void);
void
odm_antsel_statistics(
void *dm_void,
void *phy_info_void,
u8 antsel_tr_mux,
u32 mac_id,
u32 utility,
u8 method,
u8 is_cck_rate
);
void odm_fast_ant_training_callback(void *dm_void);
void
odm_process_rssi_for_ant_div(
void *dm_void,
void *phy_info_void,
void *pkt_info_void
);
void odm_fast_ant_training_work_item_callback(void *dm_void);
#endif
void odm_ant_div_init(void *dm_void);
void odm_ant_div(void *dm_void);
void odm_antsel_statistics(void *dm_void, void *phy_info_void,
u8 antsel_tr_mux, u32 mac_id, u32 utility, u8 method,
u8 is_cck_rate);
void odm_process_rssi_for_ant_div(void *dm_void, void *phy_info_void,
void *pkt_info_void);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
void
odm_set_tx_ant_by_tx_info(
void *dm_void,
u8 *desc,
u8 mac_id
);
void odm_set_tx_ant_by_tx_info(void *dm_void, u8 *desc, u8 mac_id);
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
struct tx_desc; /*declared tx_desc here or compile error happened when enabled 8822B*/
struct tx_desc;
/*@declared tx_desc here or compile error happened when enabled 8822B*/
void
odm_set_tx_ant_by_tx_info(
struct rtl8192cd_priv *priv,
struct tx_desc *pdesc,
unsigned short aid
);
void odm_set_tx_ant_by_tx_info(struct rtl8192cd_priv *priv,
struct tx_desc *pdesc, unsigned short aid);
#if 1/*def def CONFIG_WLAN_HAL*/
void
odm_set_tx_ant_by_tx_info_hal(
struct rtl8192cd_priv *priv,
void *pdesc_data,
u16 aid
);
#endif /*#ifdef CONFIG_WLAN_HAL*/
#if 1 /*@def def CONFIG_WLAN_HAL*/
void odm_set_tx_ant_by_tx_info_hal(struct rtl8192cd_priv *priv,
void *pdesc_data, u16 aid);
#endif /*@#ifdef CONFIG_WLAN_HAL*/
#endif
void odm_ant_div_config(void *dm_void);
void
odm_ant_div_config(
void *dm_void
);
void odm_ant_div_timers(void *dm_void, u8 state);
void
odm_ant_div_timers(
void *dm_void,
u8 state
);
void phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void
phydm_antdiv_debug(
void *dm_void,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
);
void odm_ant_div_reset(void *dm_void);
#endif /*#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))*/
void odm_antenna_diversity_init(void *dm_void);
void
odm_ant_div_reset(
void *dm_void
);
void
odm_antenna_diversity_init(
void *dm_void
);
void
odm_antenna_diversity(
void *dm_void
);
#endif /*#ifndef __ODMANTDIV_H__*/
void odm_antenna_diversity(void *dm_void);
#endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/
#endif /*@#ifndef __ODMANTDIV_H__*/

3215
hal/phydm/phydm_api.c
View File

File diff suppressed because it is too large Load Diff

290
hal/phydm/phydm_api.h
View File

@@ -23,227 +23,163 @@
*
*****************************************************************************/
#ifndef __PHYDM_API_H__
#define __PHYDM_API_H__
#ifndef __PHYDM_API_H__
#define __PHYDM_API_H__
#define PHYDM_API_VERSION "1.0" /* @2017.07.10 Dino, Add phydm_api.h*/
#define PHYDM_API_VERSION "1.0" /* 2017.07.10 Dino, Add phydm_api.h*/
/* 1 ============================================================
/* @1 ============================================================
* 1 Definition
* 1 ============================================================ */
* 1 ============================================================
*/
#define CN_CNT_MAX 10 /*@max condition number threshold*/
#define FUNC_ENABLE 1
#define FUNC_DISABLE 2
#define FUNC_ENABLE 1
#define FUNC_DISABLE 2
/*@NBI API------------------------------------*/
#define NBI_128TONE 27 /*register table size*/
#define NBI_256TONE 59 /*register table size*/
/*NBI API------------------------------------*/
#define NBI_TABLE_SIZE_128 27
#define NBI_TABLE_SIZE_256 59
#define NUM_START_CH_80M 7
#define NUM_START_CH_40M 14
#define NUM_START_CH_80M 7
#define NUM_START_CH_40M 14
#define CH_OFFSET_40M 2
#define CH_OFFSET_80M 6
#define CH_OFFSET_40M 2
#define CH_OFFSET_80M 6
#define FFT_128_TYPE 1
#define FFT_256_TYPE 2
#define FFT_128_TYPE 1
#define FFT_256_TYPE 2
#define FREQ_POSITIVE 1
#define FREQ_NEGATIVE 2
/*------------------------------------------------*/
/* 1 ============================================================
* 1 structure
* 1 ============================================================ */
struct phydm_api_stuc {
u32 rx_iqc_reg_1; /*N-mode: for pathA REG0xc14*/
u32 rx_iqc_reg_2; /*N-mode: for pathB REG0xc1c*/
u8 tx_queue_bitmap;/*REG0x520[23:16]*/
#define FREQ_POSITIVE 1
#define FREQ_NEGATIVE 2
/*@------------------------------------------------*/
enum phystat_rpt {
PHY_PWDB = 0,
PHY_EVM = 1,
PHY_CFO = 2,
PHY_RXSNR = 3,
PHY_LGAIN = 4,
PHY_HT_AAGC_GAIN = 5,
};
/* 1 ============================================================
#ifndef PHYDM_COMMON_API_SUPPORT
#define INVALID_RF_DATA 0xffffffff
#define INVALID_TXAGC_DATA 0xff
#endif
/* @1 ============================================================
* 1 structure
* 1 ============================================================
*/
struct phydm_api_stuc {
u32 rxiqc_reg1; /*N-mode: for pathA REG0xc14*/
u32 rxiqc_reg2; /*N-mode: for pathB REG0xc1c*/
u8 tx_queue_bitmap; /*REG0x520[23:16]*/
u8 ccktx_path;
};
/* @1 ============================================================
* 1 enumeration
* 1 ============================================================ */
* 1 ============================================================
*/
/* 1 ============================================================
/* @1 ============================================================
* 1 function prototype
* 1 ============================================================ */
* 1 ============================================================
*/
void phydm_reset_bb_hw_cnt(void *dm_void);
void
phydm_dynamic_ant_weighting(
void *dm_void
);
void phydm_dynamic_ant_weighting(void *dm_void);
#ifdef DYN_ANT_WEIGHTING_SUPPORT
void
phydm_dyn_ant_weight_dbg(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
void
phydm_pathb_q_matrix_rotate_en(
void *dm_void
);
void phydm_pathb_q_matrix_rotate_en(void *dm_void);
void
phydm_pathb_q_matrix_rotate(
void *dm_void,
u16 phase_idx
);
void phydm_pathb_q_matrix_rotate(void *dm_void, u16 phase_idx);
void
phydm_init_trx_antenna_setting(
void *dm_void
);
void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path);
void
phydm_config_ofdm_rx_path(
void *dm_void,
u32 path
);
void phydm_config_ofdm_rx_path(void *dm_void, u32 path);
void
phydm_config_cck_rx_path(
void *dm_void,
enum bb_path path
);
void phydm_config_cck_rx_path(void *dm_void, enum bb_path path);
void
phydm_config_cck_rx_antenna_init(
void *dm_void
);
void phydm_config_cck_rx_antenna_init(void *dm_void);
void
phydm_config_trx_path(
void *dm_void,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
);
void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void
phydm_tx_2path(
void *dm_void
);
void phydm_tx_2path(void *dm_void);
void
phydm_stop_3_wire(
void *dm_void,
u8 set_type
);
void phydm_stop_3_wire(void *dm_void, u8 set_type);
u8
phydm_stop_ic_trx(
void *dm_void,
u8 set_type
);
u8 phydm_stop_ic_trx(void *dm_void, u8 set_type);
void
phydm_set_ext_switch(
void *dm_void,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
);
void phydm_dis_cck_trx(void *dm_void, u8 set_type);
void
phydm_nbi_enable(
void *dm_void,
u32 enable
);
void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch);
u8
phydm_csi_mask_setting(
void *dm_void,
u32 enable,
u32 channel,
u32 bw,
u32 f_interference,
u32 Second_ch
);
void phydm_nbi_enable(void *dm_void, u32 enable);
u8
phydm_nbi_setting(
void *dm_void,
u32 enable,
u32 channel,
u32 bw,
u32 f_interference,
u32 second_ch
);
u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
u32 sec_ch);
u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
u32 sec_ch);
void
phydm_api_debug(
void *dm_void,
u32 function_map,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
);
void phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void
phydm_stop_ck320(
void *dm_void,
u8 enable
);
void phydm_csi_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void phydm_stop_ck320(void *dm_void, u8 enable);
boolean
phydm_set_bb_txagc_offset(
void *dm_void,
s8 power_offset,
u8 add_half_db
);
phydm_set_bb_txagc_offset(void *dm_void, s8 power_offset, u8 add_half_db);
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw,
u32 f_intf, u32 sec_ch, u8 wgt);
void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
u8 wgt);
u8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
u32 sec_ch, u8 path);
void phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
u8 path);
void phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path);
u8 phydm_phystat_rpt_jgr3(void *dm_void, enum phystat_rpt info,
enum rf_path ant_path);
void phydm_user_position_for_sniffer(void *dm_void, u8 user_position);
void phydm_txagc_power_limit(void *dm_void, boolean is_bf, u8 ss, u8 pwr);
#endif
#ifdef PHYDM_COMMON_API_SUPPORT
boolean
phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path,
boolean is_positive);
boolean
phydm_api_set_txagc(void *dm_void, u32 power_index, enum rf_path path,
u8 hw_rate, boolean is_single_rate);
u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate);
boolean
phydm_api_set_txagc(
void *dm_void,
u32 power_index,
enum rf_path path,
u8 hw_rate,
boolean is_single_rate
);
u8
phydm_api_get_txagc(
void *dm_void,
enum rf_path path,
u8 hw_rate
);
phydm_api_switch_bw_channel(void *dm_void, u8 central_ch, u8 primary_ch_idx,
enum channel_width bandwidth);
boolean
phydm_api_switch_bw_channel(
void *dm_void,
u8 central_ch,
u8 primary_ch_idx,
enum channel_width bandwidth
);
boolean
phydm_api_trx_mode(
void *dm_void,
enum bb_path tx_path,
enum bb_path rx_path,
boolean is_tx2_path
);
phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path,
boolean is_tx2_path);
#endif

611
hal/phydm/phydm_auto_dbg.c
View File

@@ -23,22 +23,20 @@
*
*****************************************************************************/
/* ************************************************************
/*************************************************************
* include files
* ************************************************************ */
************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef PHYDM_AUTO_DEGBUG
void
phydm_check_hang_reset(
void *dm_void
)
void phydm_check_hang_reset(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struc *atd_t = &dm->auto_dbg_table;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
atd_t->dbg_step = 0;
atd_t->auto_dbg_type = AUTO_DBG_STOP;
@@ -46,32 +44,40 @@ phydm_check_hang_reset(
dm->debug_components &= (~ODM_COMP_API);
}
#if (ODM_IC_11N_SERIES_SUPPORT == 1)
void
phydm_auto_check_hang_engine_n(
void *dm_void
)
void phydm_check_hang_init(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struc *atd_t = &dm->auto_dbg_table;
struct n_dbgport_803 dbgport_803 = {0};
u32 value32_tmp = 0, value32_tmp_2 = 0;
u8 i;
u32 curr_dbg_port_val[DBGPORT_CHK_NUM];
u16 curr_ofdm_t_cnt;
u16 curr_ofdm_r_cnt;
u16 curr_cck_t_cnt;
u16 curr_cck_r_cnt;
u16 curr_ofdm_crc_error_cnt;
u16 curr_cck_crc_error_cnt;
u16 diff_ofdm_t_cnt;
u16 diff_ofdm_r_cnt;
u16 diff_cck_t_cnt;
u16 diff_cck_r_cnt;
u16 diff_ofdm_crc_error_cnt;
u16 diff_cck_crc_error_cnt;
u8 rf_mode;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
atd_t->dbg_step = 0;
atd_t->auto_dbg_type = AUTO_DBG_STOP;
phydm_pause_dm_watchdog(dm, PHYDM_RESUME);
}
#if (ODM_IC_11N_SERIES_SUPPORT == 1)
void phydm_auto_check_hang_engine_n(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
struct n_dbgport_803 dbgport_803 = {0};
u32 value32_tmp = 0, value32_tmp_2 = 0;
u8 i;
u32 curr_dbg_port_val[DBGPORT_CHK_NUM];
u16 curr_ofdm_t_cnt;
u16 curr_ofdm_r_cnt;
u16 curr_cck_t_cnt;
u16 curr_cck_r_cnt;
u16 curr_ofdm_crc_error_cnt;
u16 curr_cck_crc_error_cnt;
u16 diff_ofdm_t_cnt;
u16 diff_ofdm_r_cnt;
u16 diff_cck_t_cnt;
u16 diff_cck_r_cnt;
u16 diff_ofdm_crc_error_cnt;
u16 diff_cck_crc_error_cnt;
u8 rf_mode;
if (atd_t->auto_dbg_type == AUTO_DBG_STOP)
return;
@@ -83,246 +89,228 @@ phydm_auto_check_hang_engine_n(
if (atd_t->dbg_step == 0) {
pr_debug("dbg_step=0\n\n");
/*Reset all packet counter*/
odm_set_bb_reg(dm, 0xf14, BIT(16), 1);
odm_set_bb_reg(dm, 0xf14, BIT(16), 0);
odm_set_bb_reg(dm, R_0xf14, BIT(16), 1);
odm_set_bb_reg(dm, R_0xf14, BIT(16), 0);
} else if (atd_t->dbg_step == 1) {
} else if (atd_t->dbg_step == 1) {
pr_debug("dbg_step=1\n\n");
/*Check packet counter Register*/
atd_t->ofdm_t_cnt = (u16)odm_get_bb_reg(dm, 0x9cc, MASKHWORD);
atd_t->ofdm_r_cnt = (u16)odm_get_bb_reg(dm, 0xf94, MASKLWORD);
atd_t->ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, 0xf94, MASKHWORD);
atd_t->cck_t_cnt = (u16)odm_get_bb_reg(dm, 0x9d0, MASKHWORD);;
atd_t->cck_r_cnt = (u16)odm_get_bb_reg(dm, 0xfa0, MASKHWORD);
atd_t->cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, 0xf84, 0x3fff);
atd_t->ofdm_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9cc, MASKHWORD);
atd_t->ofdm_r_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, MASKLWORD);
atd_t->ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf94,
MASKHWORD);
atd_t->cck_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9d0, MASKHWORD);
atd_t->cck_r_cnt = (u16)odm_get_bb_reg(dm, R_0xfa0, MASKHWORD);
atd_t->cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf84,
0x3fff);
/*Check Debug Port*/
for (i = 0; i < DBGPORT_CHK_NUM; i++) {
if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_3, (u32)atd_t->dbg_port_table[i])) {
atd_t->dbg_port_val[i] = phydm_get_bb_dbg_port_value(dm);
if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3,
(u32)atd_t->dbg_port_table[i])
) {
atd_t->dbg_port_val[i] =
phydm_get_bb_dbg_port_val(dm);
phydm_release_bb_dbg_port(dm);
}
}
} else if (atd_t->dbg_step == 2) {
} else if (atd_t->dbg_step == 2) {
pr_debug("dbg_step=2\n\n");
/*Check packet counter Register*/
curr_ofdm_t_cnt = (u16)odm_get_bb_reg(dm, 0x9cc, MASKHWORD);
curr_ofdm_r_cnt = (u16)odm_get_bb_reg(dm, 0xf94, MASKLWORD);
curr_ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, 0xf94, MASKHWORD);
curr_cck_t_cnt = (u16)odm_get_bb_reg(dm, 0x9d0, MASKHWORD);;
curr_cck_r_cnt = (u16)odm_get_bb_reg(dm, 0xfa0, MASKHWORD);
curr_cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, 0xf84, 0x3fff);
curr_ofdm_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9cc, MASKHWORD);
curr_ofdm_r_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, MASKLWORD);
curr_ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf94,
MASKHWORD);
curr_cck_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9d0, MASKHWORD);
curr_cck_r_cnt = (u16)odm_get_bb_reg(dm, R_0xfa0, MASKHWORD);
curr_cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf84,
0x3fff);
/*Check Debug Port*/
for (i = 0; i < DBGPORT_CHK_NUM; i++) {
if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_3, (u32)atd_t->dbg_port_table[i])) {
curr_dbg_port_val[i] = phydm_get_bb_dbg_port_value(dm);
if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3,
(u32)atd_t->dbg_port_table[i])
) {
curr_dbg_port_val[i] =
phydm_get_bb_dbg_port_val(dm);
phydm_release_bb_dbg_port(dm);
}
}
/*=== Make check hang decision ================================*/
/*=== Make check hang decision ===============================*/
pr_debug("Check Hang Decision\n\n");
/* ----- Check RF Register -----------------------------------*/
for (i = 0; i < dm->num_rf_path; i++) {
rf_mode = (u8)odm_get_rf_reg(dm, i, 0x0, 0xf0000);
rf_mode = (u8)odm_get_rf_reg(dm, i, RF_0x0, 0xf0000);
pr_debug("RF0x0[%d] = 0x%x\n", i, rf_mode);
if (rf_mode > 3) {
pr_debug("Incorrect RF mode\n");
pr_debug("ReasonCode:RHN-1\n");
}
}
value32_tmp = odm_get_rf_reg(dm, 0, 0xb0, 0xf0000);
value32_tmp = odm_get_rf_reg(dm, 0, RF_0xb0, 0xf0000);
if (dm->support_ic_type == ODM_RTL8188E) {
if (value32_tmp != 0xff8c8) {
pr_debug("ReasonCode:RHN-3\n");
}
}
/* ----- Check BB Register -----------------------------------*/
/* ----- Check BB Register ----------------------------------*/
/*BB mode table*/
value32_tmp = odm_get_bb_reg(dm, 0x824, 0xe);
value32_tmp_2 = odm_get_bb_reg(dm, 0x82c, 0xe);
pr_debug("BB TX mode table {A, B}= {%d, %d}\n", value32_tmp, value32_tmp_2);
value32_tmp = odm_get_bb_reg(dm, R_0x824, 0xe);
value32_tmp_2 = odm_get_bb_reg(dm, R_0x82c, 0xe);
pr_debug("BB TX mode table {A, B}= {%d, %d}\n",
value32_tmp, value32_tmp_2);
if ((value32_tmp > 3) || (value32_tmp_2 > 3)) {
if (value32_tmp > 3 || value32_tmp_2 > 3) {
pr_debug("ReasonCode:RHN-2\n");
}
value32_tmp = odm_get_bb_reg(dm, 0x824, 0x700000);
value32_tmp_2 = odm_get_bb_reg(dm, 0x82c, 0x700000);
pr_debug("BB RX mode table {A, B}= {%d, %d}\n", value32_tmp, value32_tmp_2);
value32_tmp = odm_get_bb_reg(dm, R_0x824, 0x700000);
value32_tmp_2 = odm_get_bb_reg(dm, R_0x82c, 0x700000);
pr_debug("BB RX mode table {A, B}= {%d, %d}\n", value32_tmp,
value32_tmp_2);
if ((value32_tmp > 3) || (value32_tmp_2 > 3)) {
if (value32_tmp > 3 || value32_tmp_2 > 3) {
pr_debug("ReasonCode:RHN-2\n");
}
/*BB HW Block*/
value32_tmp = odm_get_bb_reg(dm, 0x800, MASKDWORD);
value32_tmp = odm_get_bb_reg(dm, R_0x800, MASKDWORD);
if (!(value32_tmp & BIT(24))) {
pr_debug("Reg0x800[24] = 0, CCK BLK is disabled\n");
pr_debug("ReasonCode: THN-3\n");
}
if (!(value32_tmp & BIT(25))) {
pr_debug("Reg0x800[24] = 0, OFDM BLK is disabled\n");
pr_debug("ReasonCode:THN-3\n");
}
/*BB Continue TX*/
value32_tmp = odm_get_bb_reg(dm, 0xd00, 0x70000000);
value32_tmp = odm_get_bb_reg(dm, R_0xd00, 0x70000000);
pr_debug("Continue TX=%d\n", value32_tmp);
if (value32_tmp != 0) {
pr_debug("ReasonCode: THN-4\n");
}
/* ----- Check Packet Counter --------------------------------*/
diff_ofdm_t_cnt = curr_ofdm_t_cnt - atd_t->ofdm_t_cnt;
diff_ofdm_r_cnt = curr_ofdm_r_cnt - atd_t->ofdm_r_cnt;
diff_ofdm_crc_error_cnt = curr_ofdm_crc_error_cnt - atd_t->ofdm_crc_error_cnt;
diff_ofdm_crc_error_cnt = curr_ofdm_crc_error_cnt -
atd_t->ofdm_crc_error_cnt;
diff_cck_t_cnt = curr_cck_t_cnt - atd_t->cck_t_cnt;
diff_cck_r_cnt = curr_cck_r_cnt - atd_t->cck_r_cnt;
diff_cck_crc_error_cnt = curr_cck_crc_error_cnt - atd_t->cck_crc_error_cnt;
diff_cck_crc_error_cnt = curr_cck_crc_error_cnt -
atd_t->cck_crc_error_cnt;
pr_debug("OFDM[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n",
atd_t->ofdm_t_cnt, atd_t->ofdm_r_cnt, atd_t->ofdm_crc_error_cnt);
pr_debug("OFDM[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n",
curr_ofdm_t_cnt, curr_ofdm_r_cnt, curr_ofdm_crc_error_cnt);
pr_debug("OFDM_diff {TX, RX, CRC_error} = {%d, %d, %d}\n",
diff_ofdm_t_cnt, diff_ofdm_r_cnt, diff_ofdm_crc_error_cnt);
pr_debug("OFDM[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n",
atd_t->ofdm_t_cnt, atd_t->ofdm_r_cnt,
atd_t->ofdm_crc_error_cnt);
pr_debug("OFDM[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n",
curr_ofdm_t_cnt, curr_ofdm_r_cnt,
curr_ofdm_crc_error_cnt);
pr_debug("OFDM_diff {TX, RX, CRC_error} = {%d, %d, %d}\n",
diff_ofdm_t_cnt, diff_ofdm_r_cnt,
diff_ofdm_crc_error_cnt);
pr_debug("CCK[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n",
atd_t->cck_t_cnt, atd_t->cck_r_cnt, atd_t->cck_crc_error_cnt);
pr_debug("CCK[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n",
curr_cck_t_cnt, curr_cck_r_cnt, curr_cck_crc_error_cnt);
pr_debug("CCK_diff {TX, RX, CRC_error} = {%d, %d, %d}\n",
diff_cck_t_cnt, diff_cck_r_cnt, diff_cck_crc_error_cnt);
pr_debug("CCK[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n",
atd_t->cck_t_cnt, atd_t->cck_r_cnt,
atd_t->cck_crc_error_cnt);
pr_debug("CCK[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n",
curr_cck_t_cnt, curr_cck_r_cnt,
curr_cck_crc_error_cnt);
pr_debug("CCK_diff {TX, RX, CRC_error} = {%d, %d, %d}\n",
diff_cck_t_cnt, diff_cck_r_cnt,
diff_cck_crc_error_cnt);
/* ----- Check Dbg Port --------------------------------*/
for (i = 0; i < DBGPORT_CHK_NUM; i++) {
pr_debug("Dbg_port=((0x%x))\n", atd_t->dbg_port_table[i]);
pr_debug("Val{pre, curr}={0x%x, 0x%x}\n", atd_t->dbg_port_val[i], curr_dbg_port_val[i]);
pr_debug("Dbg_port=((0x%x))\n",
atd_t->dbg_port_table[i]);
pr_debug("Val{pre, curr}={0x%x, 0x%x}\n",
atd_t->dbg_port_val[i], curr_dbg_port_val[i]);
if ((atd_t->dbg_port_table[i]) == 0) {
if (atd_t->dbg_port_val[i] == curr_dbg_port_val[i]) {
if (atd_t->dbg_port_table[i] == 0) {
if (atd_t->dbg_port_val[i] ==
curr_dbg_port_val[i]) {
pr_debug("BB state hang\n");
pr_debug("ReasonCode:\n");
}
} else if (atd_t->dbg_port_table[i] == 0x803) {
if (atd_t->dbg_port_val[i] == curr_dbg_port_val[i]) {
//dbgport_803 = (struct n_dbgport_803 )(atd_t->dbg_port_val[i]);
if (atd_t->dbg_port_val[i] ==
curr_dbg_port_val[i]) {
/* dbgport_803 = */
/* (struct n_dbgport_803 ) */
/* (atd_t->dbg_port_val[i]); */
odm_move_memory(dm, &dbgport_803,
&atd_t->dbg_port_val[i],
&atd_t->dbg_port_val[i],
sizeof(struct n_dbgport_803));
pr_debug("RSTB{BB, GLB, OFDM}={%d, %d, %d}\n", dbgport_803.bb_rst_b, dbgport_803.glb_rst_b, dbgport_803.ofdm_rst_b);
pr_debug("{ofdm_tx_en, cck_tx_en, phy_tx_on}={%d, %d, %d}\n", dbgport_803.ofdm_tx_en, dbgport_803.cck_tx_en, dbgport_803.phy_tx_on);
pr_debug("CCA_PP{OFDM, CCK}={%d, %d}\n", dbgport_803.ofdm_cca_pp, dbgport_803.cck_cca_pp);
pr_debug("RSTB{BB, GLB, OFDM}={%d, %d,%d}\n",
dbgport_803.bb_rst_b,
dbgport_803.glb_rst_b,
dbgport_803.ofdm_rst_b);
pr_debug("{ofdm_tx_en, cck_tx_en, phy_tx_on}={%d, %d, %d}\n",
dbgport_803.ofdm_tx_en,
dbgport_803.cck_tx_en,
dbgport_803.phy_tx_on);
pr_debug("CCA_PP{OFDM, CCK}={%d, %d}\n",
dbgport_803.ofdm_cca_pp,
dbgport_803.cck_cca_pp);
if (dbgport_803.phy_tx_on)
pr_debug("Maybe TX Hang\n");
else if (dbgport_803.ofdm_cca_pp || dbgport_803.cck_cca_pp)
pr_debug("Maybe RX Hang\n");
else if (dbgport_803.ofdm_cca_pp ||
dbgport_803.cck_cca_pp)
pr_debug("Maybe RX Hang\n");
}
} else if (atd_t->dbg_port_table[i] == 0x208) {
if ((atd_t->dbg_port_val[i] & BIT(30)) && (curr_dbg_port_val[i] & BIT(30))) {
if ((atd_t->dbg_port_val[i] & BIT(30)) &&
(curr_dbg_port_val[i] & BIT(30))) {
pr_debug("EDCCA Pause TX\n");
pr_debug("ReasonCode: THN-2\n");
}
} else if (atd_t->dbg_port_table[i] == 0xab0) {
if (((atd_t->dbg_port_val[i] & 0xffffff) == 0) ||
((curr_dbg_port_val[i] & 0xffffff) == 0)) {
/* atd_t->dbg_port_val[i] & 0xffffff == 0 */
/* curr_dbg_port_val[i] & 0xffffff == 0 */
if (((atd_t->dbg_port_val[i] &
MASK24BITS) == 0) ||
((curr_dbg_port_val[i] &
MASK24BITS) == 0)) {
pr_debug("Wrong L-SIG formate\n");
pr_debug("ReasonCode: THN-1\n");
}
}
}
phydm_check_hang_reset(dm);
}
atd_t->dbg_step++;
}
void
phydm_bb_auto_check_hang_start_n(
void *dm_void,
u32 *_used,
char *output,
u32 *_out_len
)
void phydm_bb_auto_check_hang_start_n(
void *dm_void,
u32 *_used,
char *output,
u32 *_out_len)
{
u32 value32 = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struc *atd_t = &dm->auto_dbg_table;
u32 used = *_used;
u32 out_len = *_out_len;
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
return;
PDM_SNPF(out_len, used, output + used, out_len - used,
"PHYDM auto check hang (N-series) is started, Please check the system log\n");
dm->debug_components |= ODM_COMP_API;
atd_t->auto_dbg_type = AUTO_DBG_CHECK_HANG;
atd_t->dbg_step = 0;
phydm_pause_dm_watchdog(dm, PHYDM_PAUSE);
*_used = used;
*_out_len = out_len;
}
void
phydm_bb_rx_hang_info_n(
void *dm_void,
u32 *_used,
char *output,
u32 *_out_len
)
{
u32 value32 = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 value32 = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
u32 used = *_used;
u32 out_len = *_out_len;
@@ -330,50 +318,67 @@ phydm_bb_rx_hang_info_n(
return;
PDM_SNPF(out_len, used, output + used, out_len - used,
"not support now\n");
"PHYDM auto check hang (N-series) is started, Please check the system log\n");
dm->debug_components |= ODM_COMP_API;
atd_t->auto_dbg_type = AUTO_DBG_CHECK_HANG;
atd_t->dbg_step = 0;
phydm_pause_dm_watchdog(dm, PHYDM_PAUSE);
*_used = used;
*_out_len = out_len;
}
#endif
void phydm_dbg_port_dump_n(void *dm_void, u32 *_used, char *output,
u32 *_out_len)
{
u32 value32 = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
return;
PDM_SNPF(out_len, used, output + used, out_len - used,
"not support now\n");
*_used = used;
*_out_len = out_len;
}
#endif
#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
void
phydm_bb_rx_hang_info_ac(
void *dm_void,
u32 *_used,
char *output,
u32 *_out_len
)
void phydm_dbg_port_dump_ac(void *dm_void, u32 *_used, char *output,
u32 *_out_len)
{
u32 value32 = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 value32 = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
if (dm->support_ic_type & ODM_IC_11N_SERIES)
return;
value32 = odm_get_bb_reg(dm, 0xF80, MASKDWORD);
value32 = odm_get_bb_reg(dm, R_0xf80, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "rptreg of sc/bw/ht/...",
value32);
"\r\n %-35s = 0x%x", "rptreg of sc/bw/ht/...", value32);
if (dm->support_ic_type & ODM_RTL8822B)
odm_set_bb_reg(dm, 0x198c, BIT(2) | BIT(1) | BIT(0), 7);
odm_set_bb_reg(dm, R_0x198c, BIT(2) | BIT(1) | BIT(0), 7);
/* dbg_port = basic state machine */
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x000);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "basic state machine",
value32);
"\r\n %-35s = 0x%x", "basic state machine", value32);
}
/* dbg_port = state machine */
@@ -381,11 +386,11 @@ phydm_bb_rx_hang_info_ac(
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x007);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "state machine", value32);
"\r\n %-35s = 0x%x", "state machine", value32);
}
/* dbg_port = CCA-related*/
@@ -393,24 +398,23 @@ phydm_bb_rx_hang_info_ac(
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x204);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "CCA-related", value32);
"\r\n %-35s = 0x%x", "CCA-related", value32);
}
/* dbg_port = edcca/rxd*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x278);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "edcca/rxd", value32);
"\r\n %-35s = 0x%x", "edcca/rxd", value32);
}
/* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/
@@ -418,12 +422,12 @@ phydm_bb_rx_hang_info_ac(
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x290);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x",
"rx_state/mux_state/ADC_MASK_OFDM", value32);
"\r\n %-35s = 0x%x",
"rx_state/mux_state/ADC_MASK_OFDM", value32);
}
/* dbg_port = bf-related*/
@@ -431,11 +435,11 @@ phydm_bb_rx_hang_info_ac(
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B2);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "bf-related", value32);
"\r\n %-35s = 0x%x", "bf-related", value32);
}
/* dbg_port = bf-related*/
@@ -443,11 +447,11 @@ phydm_bb_rx_hang_info_ac(
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B8);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "bf-related", value32);
"\r\n %-35s = 0x%x", "bf-related", value32);
}
/* dbg_port = txon/rxd*/
@@ -455,11 +459,11 @@ phydm_bb_rx_hang_info_ac(
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA03);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "txon/rxd", value32);
"\r\n %-35s = 0x%x", "txon/rxd", value32);
}
/* dbg_port = l_rate/l_length*/
@@ -467,12 +471,11 @@ phydm_bb_rx_hang_info_ac(
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0B);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "l_rate/l_length",
value32);
"\r\n %-35s = 0x%x", "l_rate/l_length", value32);
}
/* dbg_port = rxd/rxd_hit*/
@@ -480,11 +483,11 @@ phydm_bb_rx_hang_info_ac(
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0D);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "rxd/rxd_hit", value32);
"\r\n %-35s = 0x%x", "rxd/rxd_hit", value32);
}
/* dbg_port = dis_cca*/
@@ -492,24 +495,23 @@ phydm_bb_rx_hang_info_ac(
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAA0);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "dis_cca", value32);
"\r\n %-35s = 0x%x", "dis_cca", value32);
}
/* dbg_port = tx*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAB0);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "tx", value32);
"\r\n %-35s = 0x%x", "tx", value32);
}
/* dbg_port = rx plcp*/
@@ -517,130 +519,167 @@ phydm_bb_rx_hang_info_ac(
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD0);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "rx plcp", value32);
"\r\n %-35s = 0x%x", "rx plcp", value32);
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD1);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "rx plcp", value32);
"\r\n %-35s = 0x%x", "rx plcp", value32);
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD2);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "rx plcp", value32);
"\r\n %-35s = 0x%x", "rx plcp", value32);
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD3);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "rx plcp", value32);
"\r\n %-35s = 0x%x", "rx plcp", value32);
}
*_used = used;
*_out_len = out_len;
}
#endif
void
phydm_auto_dbg_console(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
)
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
void phydm_dbg_port_dump_jgr3(void *dm_void, u32 *_used, char *output,
u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
char help[] = "-h";
u32 var1[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
u32 dbg_port_idx_all[3] = {0x000, 0x001, 0x002};
u32 val = 0;
u32 dbg_port_idx = 0;
u32 i = 0;
if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
return;
PDM_SNPF(out_len, used, output + used, out_len - used,
"%-16s = %s\n", "DbgPort index", "Value");
/*0x000/0x001/0x002*/
for (i = 0; i < 3; i++) {
dbg_port_idx = dbg_port_idx_all[i];
if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port_idx)) {
val = phydm_get_bb_dbg_port_val(dm);
PDM_SNPF(out_len, used, output + used, out_len - used,
"0x%-15x = 0x%x\n", dbg_port_idx, val);
phydm_release_bb_dbg_port(dm);
}
}
/*0x3a0/0x3a1/.../0x3ab/0x3ac*/
for (dbg_port_idx = 0x3a0; dbg_port_idx <= 0x3ac; dbg_port_idx++) {
if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port_idx)) {
val = phydm_get_bb_dbg_port_val(dm);
PDM_SNPF(out_len, used, output + used, out_len - used,
"0x%-15x = 0x%x\n", dbg_port_idx, val);
phydm_release_bb_dbg_port(dm);
}
}
*_used = used;
*_out_len = out_len;
}
#endif
void phydm_auto_dbg_console(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
char help[] = "-h";
u32 var1[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
if ((strcmp(input[1], help) == 0)) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"Show dbg port: {1} {1}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"Auto check hang: {1} {2}\n");
"hang: {1} {1:Show DbgPort, 2:Auto check hang}\n");
return;
} else if (var1[0] == 1) {
PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
if (var1[1] == 1) {
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
phydm_bb_rx_hang_info_ac(dm, &used, output, &out_len);
#else
PDM_SNPF(out_len, used, output + used,
out_len - used,
"Not support\n");
#endif
} else {
#if (ODM_IC_11N_SERIES_SUPPORT == 1)
phydm_bb_rx_hang_info_n(dm, &used, output, &out_len);
#else
PDM_SNPF(out_len, used, output + used,
out_len - used,
"Not support\n");
#endif
switch (dm->ic_ip_series) {
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
case PHYDM_IC_JGR3:
phydm_dbg_port_dump_jgr3(dm, &used, output,
&out_len);
break;
#endif
#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
case PHYDM_IC_AC:
phydm_dbg_port_dump_ac(dm, &used, output,
&out_len);
break;
#endif
#if (ODM_IC_11N_SERIES_SUPPORT == 1)
case PHYDM_IC_N:
phydm_dbg_port_dump_n(dm, &used, output,
&out_len);
break;
#endif
default:
break;
}
} else if (var1[1] == 2) {
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
PDM_SNPF(out_len, used, output + used,
out_len - used,
"Not support\n");
out_len - used, "Not support\n");
} else {
#if (ODM_IC_11N_SERIES_SUPPORT == 1)
phydm_bb_auto_check_hang_start_n(dm, &used, output, &out_len);
phydm_bb_auto_check_hang_start_n(dm, &used,
output,
&out_len);
#else
PDM_SNPF(out_len, used, output + used,
out_len - used,
"Not support\n");
out_len - used, "Not support\n");
#endif
}
}
}
}
*_used = used;
*_out_len = out_len;
}
#endif
void
phydm_auto_dbg_engine(
void *dm_void
)
void phydm_auto_dbg_engine(void *dm_void)
{
#ifdef PHYDM_AUTO_DEGBUG
u32 value32 = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struc *atd_t = &dm->auto_dbg_table;
u32 value32 = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
if (atd_t->auto_dbg_type == AUTO_DBG_STOP)
return;
pr_debug("%s ======>\n", __func__);
if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_HANG) {
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
pr_debug("Not Support\n");
@@ -653,30 +692,22 @@ phydm_auto_dbg_engine(
}
} else if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_RA) {
pr_debug("Not Support\n");
}
#endif
}
void
phydm_auto_dbg_engine_init(
void *dm_void
)
void phydm_auto_dbg_engine_init(void *dm_void)
{
#ifdef PHYDM_AUTO_DEGBUG
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struc *atd_t = &dm->auto_dbg_table;
u16 dbg_port_table[DBGPORT_CHK_NUM] = {0x0, 0x803, 0x208, 0xab0, 0xab1, 0xab2};
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
u16 dbg_port_table[DBGPORT_CHK_NUM] = {0x0, 0x803, 0x208, 0xab0,
0xab1, 0xab2};
PHYDM_DBG(dm, ODM_COMP_API, "%s ======>n", __func__);
odm_move_memory(dm, &atd_t->dbg_port_table[0],
&dbg_port_table[0], (DBGPORT_CHK_NUM * 2));
&dbg_port_table[0], (DBGPORT_CHK_NUM * 2));
phydm_check_hang_reset(dm);
#endif
phydm_check_hang_init(dm);
}
#endif

141
hal/phydm/phydm_auto_dbg.h
View File

@@ -23,102 +23,91 @@
*
*****************************************************************************/
#ifndef __PHYDM_AUTO_DBG_H__
#define __PHYDM_AUTO_DBG_H__
#ifndef __PHYDM_AUTO_DBG_H__
#define __PHYDM_AUTO_DBG_H__
#define AUTO_DBG_VERSION "1.0" /* @2017.05.015 Dino, Add phydm_auto_dbg.h*/
#define AUTO_DBG_VERSION "1.0" /* 2017.05.015 Dino, Add phydm_auto_dbg.h*/
/* 1 ============================================================
/* @1 ============================================================
* 1 Definition
* 1 ============================================================ */
* 1 ============================================================
*/
#define AUTO_CHK_HANG_STEP_MAX 3
#define DBGPORT_CHK_NUM 6
#define AUTO_CHK_HANG_STEP_MAX 3
#define DBGPORT_CHK_NUM 6
#ifdef PHYDM_AUTO_DEGBUG
/* 1 ============================================================
/* @1 ============================================================
* 1 enumeration
* 1 ============================================================ */
* 1 ============================================================
*/
enum auto_dbg_type_e{
AUTO_DBG_STOP = 0,
AUTO_DBG_CHECK_HANG = 1,
enum auto_dbg_type_e {
AUTO_DBG_STOP = 0,
AUTO_DBG_CHECK_HANG = 1,
AUTO_DBG_CHECK_RA = 2,
AUTO_DBG_CHECK_DIG = 3
AUTO_DBG_CHECK_DIG = 3
};
/* 1 ============================================================
/* @1 ============================================================
* 1 structure
* 1 ============================================================ */
* 1 ============================================================
*/
struct n_dbgport_803 {
/*BYTE 3*/
u8 bb_rst_b: 1;
u8 glb_rst_b: 1;
u8 zero_1bit_1:1;
u8 ofdm_rst_b: 1;
u8 cck_txpe: 1;
u8 ofdm_txpe: 1;
u8 phy_tx_on: 1;
u8 tdrdy: 1;
/*BYTE 2*/
u8 txd:8;
/*BYTE 1*/
u8 cck_cca_pp: 1;
u8 ofdm_cca_pp: 1;
u8 rx_rst: 1;
u8 rdrdy: 1;
u8 rxd_7_4: 4;
/*BYTE 0*/
u8 rxd_3_0: 4;
u8 ofdm_tx_en: 1;
u8 cck_tx_en: 1;
u8 zero_1bit_2:1;
u8 clk_80m: 1;
/*@BYTE 3*/
u8 bb_rst_b : 1;
u8 glb_rst_b : 1;
u8 zero_1bit_1 : 1;
u8 ofdm_rst_b : 1;
u8 cck_txpe : 1;
u8 ofdm_txpe : 1;
u8 phy_tx_on : 1;
u8 tdrdy : 1;
/*@BYTE 2*/
u8 txd : 8;
/*@BYTE 1*/
u8 cck_cca_pp : 1;
u8 ofdm_cca_pp : 1;
u8 rx_rst : 1;
u8 rdrdy : 1;
u8 rxd_7_4 : 4;
/*@BYTE 0*/
u8 rxd_3_0 : 4;
u8 ofdm_tx_en : 1;
u8 cck_tx_en : 1;
u8 zero_1bit_2 : 1;
u8 clk_80m : 1;
};
struct phydm_auto_dbg_struc {
enum auto_dbg_type_e auto_dbg_type;
u8 dbg_step;
u16 dbg_port_table[DBGPORT_CHK_NUM];
u32 dbg_port_val[DBGPORT_CHK_NUM];
u16 ofdm_t_cnt;
u16 ofdm_r_cnt;
u16 cck_t_cnt;
u16 cck_r_cnt;
u16 ofdm_crc_error_cnt;
u16 cck_crc_error_cnt;
struct phydm_auto_dbg_struct {
enum auto_dbg_type_e auto_dbg_type;
u8 dbg_step;
u16 dbg_port_table[DBGPORT_CHK_NUM];
u32 dbg_port_val[DBGPORT_CHK_NUM];
u16 ofdm_t_cnt;
u16 ofdm_r_cnt;
u16 cck_t_cnt;
u16 cck_r_cnt;
u16 ofdm_crc_error_cnt;
u16 cck_crc_error_cnt;
};
/* 1 ============================================================
/* @1 ============================================================
* 1 function prototype
* 1 ============================================================ */
* 1 ============================================================
*/
void phydm_auto_dbg_console(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len);
void
phydm_auto_dbg_console(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
void phydm_auto_dbg_engine(void *dm_void);
void phydm_auto_dbg_engine_init(void *dm_void);
#endif
#endif
void
phydm_auto_dbg_engine(
void *dm_void
);
void
phydm_auto_dbg_engine_init(
void *dm_void
);
#endif

1373
hal/phydm/phydm_beamforming.c
View File

File diff suppressed because it is too large Load Diff

418
hal/phydm/phydm_beamforming.h
View File

@@ -26,11 +26,7 @@
#ifndef __INC_PHYDM_BEAMFORMING_H
#define __INC_PHYDM_BEAMFORMING_H
#ifndef BEAMFORMING_SUPPORT
#define BEAMFORMING_SUPPORT 0
#endif
/*Beamforming Related*/
/*@Beamforming Related*/
#include "txbf/halcomtxbf.h"
#include "txbf/haltxbfjaguar.h"
#include "txbf/haltxbf8192e.h"
@@ -38,34 +34,34 @@
#include "txbf/haltxbf8822b.h"
#include "txbf/haltxbfinterface.h"
#if (BEAMFORMING_SUPPORT == 1)
#ifdef PHYDM_BEAMFORMING_SUPPORT
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define eq_mac_addr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
#define cp_mac_addr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5])
#define eq_mac_addr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0)
#define cp_mac_addr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5])
#endif
#define MAX_BEAMFORMEE_SU 2
#define MAX_BEAMFORMER_SU 2
#define MAX_BEAMFORMEE_SU 2
#define MAX_BEAMFORMER_SU 2
#if (RTL8822B_SUPPORT == 1)
#define MAX_BEAMFORMEE_MU 6
#define MAX_BEAMFORMER_MU 1
#define MAX_BEAMFORMEE_MU 6
#define MAX_BEAMFORMER_MU 1
#else
#define MAX_BEAMFORMEE_MU 0
#define MAX_BEAMFORMER_MU 0
#define MAX_BEAMFORMEE_MU 0
#define MAX_BEAMFORMER_MU 0
#endif
#define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU)
#define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU)
#define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU)
#define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU)
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
/*for different naming between WIN and CE*/
#define BEACON_QUEUE BCN_QUEUE_INX
#define NORMAL_QUEUE MGT_QUEUE_INX
#define RT_DISABLE_FUNC RTW_DISABLE_FUNC
#define RT_ENABLE_FUNC RTW_ENABLE_FUNC
/*@for different naming between WIN and CE*/
#define BEACON_QUEUE BCN_QUEUE_INX
#define NORMAL_QUEUE MGT_QUEUE_INX
#define RT_DISABLE_FUNC RTW_DISABLE_FUNC
#define RT_ENABLE_FUNC RTW_ENABLE_FUNC
#endif
enum beamforming_entry_state {
@@ -76,7 +72,6 @@ enum beamforming_entry_state {
BEAMFORMING_ENTRY_STATE_PROGRESSED
};
enum beamforming_notify_state {
BEAMFORMING_NOTIFY_NONE,
BEAMFORMING_NOTIFY_ADD,
@@ -92,15 +87,14 @@ enum beamforming_cap {
BEAMFORMING_CAP_NONE = 0x0,
BEAMFORMER_CAP_HT_EXPLICIT = BIT(1),
BEAMFORMEE_CAP_HT_EXPLICIT = BIT(2),
BEAMFORMER_CAP_VHT_SU = BIT(5), /* Self has er Cap, because Reg er & peer ee */
BEAMFORMEE_CAP_VHT_SU = BIT(6), /* Self has ee Cap, because Reg ee & peer er */
BEAMFORMER_CAP_VHT_MU = BIT(7), /* Self has er Cap, because Reg er & peer ee */
BEAMFORMEE_CAP_VHT_MU = BIT(8), /* Self has ee Cap, because Reg ee & peer er */
BEAMFORMER_CAP_VHT_SU = BIT(5), /* @Self has er Cap, because Reg er & peer ee */
BEAMFORMEE_CAP_VHT_SU = BIT(6), /* @Self has ee Cap, because Reg ee & peer er */
BEAMFORMER_CAP_VHT_MU = BIT(7), /* @Self has er Cap, because Reg er & peer ee */
BEAMFORMEE_CAP_VHT_MU = BIT(8), /* @Self has ee Cap, because Reg ee & peer er */
BEAMFORMER_CAP = BIT(9),
BEAMFORMEE_CAP = BIT(10),
};
enum sounding_mode {
SOUNDING_SW_VHT_TIMER = 0x0,
SOUNDING_SW_HT_TIMER = 0x1,
@@ -115,138 +109,131 @@ enum sounding_mode {
};
struct _RT_BEAMFORM_STAINFO {
u8 *ra;
u16 aid;
u16 mac_id;
u8 my_mac_addr[6];
u8 *ra;
u16 aid;
u16 mac_id;
u8 my_mac_addr[6];
/*WIRELESS_MODE wireless_mode;*/
enum channel_width bw;
enum beamforming_cap beamform_cap;
u8 ht_beamform_cap;
u16 vht_beamform_cap;
u8 cur_beamform;
u16 cur_beamform_vht;
enum channel_width bw;
enum beamforming_cap beamform_cap;
u8 ht_beamform_cap;
u16 vht_beamform_cap;
u8 cur_beamform;
u16 cur_beamform_vht;
};
struct _RT_BEAMFORMEE_ENTRY {
boolean is_used;
boolean is_txbf;
boolean is_txbf;
boolean is_sound;
u16 aid; /*Used to construct AID field of NDPA packet.*/
u16 mac_id; /*Used to Set Reg42C in IBSS mode. */
u16 p_aid; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
u8 g_id; /*Used to fill Tx DESC*/
u8 my_mac_addr[6];
u8 mac_addr[6]; /*Used to fill Reg6E4 to fill Mac address of CSI report frame.*/
enum channel_width sound_bw; /*Sounding band_width*/
u16 sound_period;
enum beamforming_cap beamform_entry_cap;
enum beamforming_entry_state beamform_entry_state;
boolean is_beamforming_in_progress;
/*u8 log_seq; // Move to _RT_BEAMFORMER_ENTRY*/
/*u16 log_retry_cnt:3; // 0~4 // Move to _RT_BEAMFORMER_ENTRY*/
/*u16 LogSuccessCnt:2; // 0~2 // Move to _RT_BEAMFORMER_ENTRY*/
u16 log_status_fail_cnt:5; /* 0~21 */
u16 default_csi_cnt:5; /* 0~21 */
u8 csi_matrix[327];
u16 csi_matrix_len;
u8 num_of_sounding_dim;
u8 comp_steering_num_of_bfer;
u8 su_reg_index;
/*For MU-MIMO*/
boolean is_mu_sta;
u8 mu_reg_index;
u8 gid_valid[8];
u8 user_position[16];
u16 aid; /*Used to construct AID field of NDPA packet.*/
u16 mac_id; /*Used to Set Reg42C in IBSS mode. */
u16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
u8 g_id; /*Used to fill Tx DESC*/
u8 my_mac_addr[6];
u8 mac_addr[6]; /*@Used to fill Reg6E4 to fill Mac address of CSI report frame.*/
enum channel_width sound_bw; /*Sounding band_width*/
u16 sound_period;
enum beamforming_cap beamform_entry_cap;
enum beamforming_entry_state beamform_entry_state;
boolean is_beamforming_in_progress;
/*@u8 log_seq; // Move to _RT_BEAMFORMER_ENTRY*/
/*@u16 log_retry_cnt:3; // 0~4 // Move to _RT_BEAMFORMER_ENTRY*/
/*@u16 LogSuccessCnt:2; // 0~2 // Move to _RT_BEAMFORMER_ENTRY*/
u16 log_status_fail_cnt : 5; /* @0~21 */
u16 default_csi_cnt : 5; /* @0~21 */
u8 csi_matrix[327];
u16 csi_matrix_len;
u8 num_of_sounding_dim;
u8 comp_steering_num_of_bfer;
u8 su_reg_index;
/*@For MU-MIMO*/
boolean is_mu_sta;
u8 mu_reg_index;
u8 gid_valid[8];
u8 user_position[16];
};
struct _RT_BEAMFORMER_ENTRY {
boolean is_used;
boolean is_used;
/*P_AID of BFer entry is probably not used*/
u16 p_aid; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
u8 g_id;
u8 my_mac_addr[6];
u8 mac_addr[6];
enum beamforming_cap beamform_entry_cap;
u8 num_of_sounding_dim;
u8 clock_reset_times; /*Modified by Jeffery @2015-04-10*/
u8 pre_log_seq; /*Modified by Jeffery @2015-03-30*/
u8 log_seq; /*Modified by Jeffery @2014-10-29*/
u16 log_retry_cnt:3; /*Modified by Jeffery @2014-10-29*/
u16 log_success:2; /*Modified by Jeffery @2014-10-29*/
u8 su_reg_index;
/*For MU-MIMO*/
boolean is_mu_ap;
u8 gid_valid[8];
u8 user_position[16];
u16 aid;
u16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
u8 g_id;
u8 my_mac_addr[6];
u8 mac_addr[6];
enum beamforming_cap beamform_entry_cap;
u8 num_of_sounding_dim;
u8 clock_reset_times; /*@Modified by Jeffery @2015-04-10*/
u8 pre_log_seq; /*@Modified by Jeffery @2015-03-30*/
u8 log_seq; /*@Modified by Jeffery @2014-10-29*/
u16 log_retry_cnt : 3; /*@Modified by Jeffery @2014-10-29*/
u16 log_success : 2; /*@Modified by Jeffery @2014-10-29*/
u8 su_reg_index;
/*@For MU-MIMO*/
boolean is_mu_ap;
u8 gid_valid[8];
u8 user_position[16];
u16 aid;
};
struct _RT_SOUNDING_INFO {
u8 sound_idx;
enum channel_width sound_bw;
enum sounding_mode sound_mode;
u16 sound_period;
u8 sound_idx;
enum channel_width sound_bw;
enum sounding_mode sound_mode;
u16 sound_period;
};
struct _RT_BEAMFORMING_OID_INFO {
u8 sound_oid_idx;
enum channel_width sound_oid_bw;
enum sounding_mode sound_oid_mode;
u16 sound_oid_period;
u8 sound_oid_idx;
enum channel_width sound_oid_bw;
enum sounding_mode sound_oid_mode;
u16 sound_oid_period;
};
struct _RT_BEAMFORMING_INFO {
enum beamforming_cap beamform_cap;
struct _RT_BEAMFORMEE_ENTRY beamformee_entry[BEAMFORMEE_ENTRY_NUM];
struct _RT_BEAMFORMER_ENTRY beamformer_entry[BEAMFORMER_ENTRY_NUM];
struct _RT_BEAMFORM_STAINFO beamform_sta_info;
u8 beamformee_cur_idx;
struct phydm_timer_list beamforming_timer;
struct phydm_timer_list mu_timer;
struct _RT_SOUNDING_INFO sounding_info;
struct _RT_BEAMFORMING_OID_INFO beamforming_oid_info;
struct _HAL_TXBF_INFO txbf_info;
u8 sounding_sequence;
u8 beamformee_su_cnt;
u8 beamformer_su_cnt;
u32 beamformee_su_reg_maping;
u32 beamformer_su_reg_maping;
/*For MU-MINO*/
u8 beamformee_mu_cnt;
u8 beamformer_mu_cnt;
u32 beamformee_mu_reg_maping;
u8 mu_ap_index;
boolean is_mu_sounding;
u8 first_mu_bfee_index;
boolean is_mu_sounding_in_progress;
boolean dbg_disable_mu_tx;
boolean apply_v_matrix;
boolean snding3ss;
enum beamforming_cap beamform_cap;
struct _RT_BEAMFORMEE_ENTRY beamformee_entry[BEAMFORMEE_ENTRY_NUM];
struct _RT_BEAMFORMER_ENTRY beamformer_entry[BEAMFORMER_ENTRY_NUM];
struct _RT_BEAMFORM_STAINFO beamform_sta_info;
u8 beamformee_cur_idx;
struct phydm_timer_list beamforming_timer;
struct phydm_timer_list mu_timer;
struct _RT_SOUNDING_INFO sounding_info;
struct _RT_BEAMFORMING_OID_INFO beamforming_oid_info;
struct _HAL_TXBF_INFO txbf_info;
u8 sounding_sequence;
u8 beamformee_su_cnt;
u8 beamformer_su_cnt;
u32 beamformee_su_reg_maping;
u32 beamformer_su_reg_maping;
/*@For MU-MINO*/
u8 beamformee_mu_cnt;
u8 beamformer_mu_cnt;
u32 beamformee_mu_reg_maping;
u8 mu_ap_index;
boolean is_mu_sounding;
u8 first_mu_bfee_index;
boolean is_mu_sounding_in_progress;
boolean dbg_disable_mu_tx;
boolean apply_v_matrix;
boolean snding3ss;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *source_adapter;
void *source_adapter;
#endif
/* Control register */
u32 reg_mu_tx_ctrl; /* For USB/SDIO interfaces aync I/O */
u8 tx_bf_data_rate;
u8 last_usb_hub;
/* @Control register */
u32 reg_mu_tx_ctrl; /* @For USB/SDIO interfaces aync I/O */
u8 tx_bf_data_rate;
u8 last_usb_hub;
};
void
phydm_get_txbf_device_num(
void *dm_void,
u8 macid
);
void phydm_get_txbf_device_num(
void *dm_void,
u8 macid);
struct _RT_NDPA_STA_INFO {
u16 aid:12;
u16 feedback_type:1;
u16 nc_index:3;
u16 aid : 12;
u16 feedback_type : 1;
u16 nc_index : 3;
};
enum phydm_acting_type {
@@ -254,158 +241,123 @@ enum phydm_acting_type {
phydm_acting_as_ap = 1
};
enum beamforming_cap
phydm_beamforming_get_entry_beam_cap_by_mac_id(
void *dm_void,
u8 mac_id
);
void *dm_void,
u8 mac_id);
struct _RT_BEAMFORMEE_ENTRY *
phydm_beamforming_get_bfee_entry_by_addr(
void *dm_void,
u8 *RA,
u8 *idx
);
void *dm_void,
u8 *RA,
u8 *idx);
struct _RT_BEAMFORMER_ENTRY *
phydm_beamforming_get_bfer_entry_by_addr(
void *dm_void,
u8 *TA,
u8 *idx
);
void *dm_void,
u8 *TA,
u8 *idx);
void
phydm_beamforming_notify(
void *dm_void
);
void phydm_beamforming_notify(
void *dm_void);
boolean
phydm_acting_determine(
void *dm_void,
enum phydm_acting_type type
);
void *dm_void,
enum phydm_acting_type type);
void
beamforming_enter(
void *dm_void,
u16 sta_idx
);
void beamforming_enter(void *dm_void, u16 sta_idx, u8 *my_mac_addr);
void
beamforming_leave(
void *dm_void,
u8 *RA
);
void beamforming_leave(
void *dm_void,
u8 *RA);
boolean
beamforming_start_fw(
void *dm_void,
u8 idx
);
void *dm_void,
u8 idx);
void
beamforming_check_sounding_success(
void *dm_void,
boolean status
);
void beamforming_check_sounding_success(
void *dm_void,
boolean status);
void
phydm_beamforming_end_sw(
void *dm_void,
boolean status
);
void
beamforming_timer_callback(
void *dm_void
);
void
phydm_beamforming_init(
void *dm_void
);
void phydm_beamforming_end_sw(
void *dm_void,
boolean status);
void beamforming_timer_callback(
void *dm_void);
void phydm_beamforming_init(
void *dm_void);
enum beamforming_cap
phydm_beamforming_get_beam_cap(
void *dm_void,
struct _RT_BEAMFORMING_INFO *beam_info
);
void *dm_void,
struct _RT_BEAMFORMING_INFO *beam_info);
enum beamforming_cap
phydm_get_beamform_cap(
void *dm_void
);
void *dm_void);
boolean
beamforming_control_v1(
void *dm_void,
u8 *RA,
u8 AID,
u8 mode,
enum channel_width BW,
u8 rate
);
void *dm_void,
u8 *RA,
u8 AID,
u8 mode,
enum channel_width BW,
u8 rate);
boolean
phydm_beamforming_control_v2(
void *dm_void,
u8 idx,
u8 mode,
enum channel_width BW,
u16 period
);
void *dm_void,
u8 idx,
u8 mode,
enum channel_width BW,
u16 period);
void
phydm_beamforming_watchdog(
void *dm_void
);
void phydm_beamforming_watchdog(
void *dm_void);
void
beamforming_sw_timer_callback(
void beamforming_sw_timer_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct phydm_timer_list *timer
struct phydm_timer_list *timer
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
void *function_context
#endif
);
);
boolean
beamforming_send_ht_ndpa_packet(
void *dm_void,
u8 *RA,
enum channel_width BW,
u8 q_idx
);
void *dm_void,
u8 *RA,
enum channel_width BW,
u8 q_idx);
boolean
beamforming_send_vht_ndpa_packet(
void *dm_void,
u8 *RA,
u16 AID,
enum channel_width BW,
u8 q_idx
);
void *dm_void,
u8 *RA,
u16 AID,
enum channel_width BW,
u8 q_idx);
#else
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
#define beamforming_gid_paid(adapter, tcb)
#define phydm_acting_determine(dm, type) false
#define beamforming_enter(dm, sta_idx)
#define phydm_acting_determine(dm, type) false
#define beamforming_enter(dm, sta_idx, my_mac_addr)
#define beamforming_leave(dm, RA)
#define beamforming_end_fw(dm)
#define beamforming_control_v1(dm, RA, AID, mode, BW, rate) true
#define beamforming_control_v2(dm, idx, mode, BW, period) true
#define beamforming_control_v1(dm, RA, AID, mode, BW, rate) true
#define beamforming_control_v2(dm, idx, mode, BW, period) true
#define phydm_beamforming_end_sw(dm, _status)
#define beamforming_timer_callback(dm)
#define phydm_beamforming_init(dm)
#define phydm_beamforming_control_v2(dm, _idx, _mode, _BW, _period) false
#define phydm_beamforming_control_v2(dm, _idx, _mode, _BW, _period) false
#define beamforming_watchdog(dm)
#define phydm_beamforming_watchdog(dm)
#endif
#endif /*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/
#endif /*@#ifdef PHYDM_BEAMFORMING_SUPPORT*/
#endif

1329
hal/phydm/phydm_cck_pd.c
View File

File diff suppressed because it is too large Load Diff

159
hal/phydm/phydm_cck_pd.h
View File

@@ -23,72 +23,133 @@
*
*****************************************************************************/
#ifndef __PHYDM_CCK_PD_H__
#define __PHYDM_CCK_PD_H__
#ifndef __PHYDM_CCK_PD_H__
#define __PHYDM_CCK_PD_H__
#define CCK_PD_VERSION "3.1"
#define CCK_PD_VERSION "1.0" /* 2017.05.09 Dino, Add phydm_cck_pd.h*/
/* 1 ============================================================
/*@
* 1 ============================================================
* 1 Definition
* 1 ============================================================ */
* 1 ============================================================
*/
#define CCK_FA_MA_RESET 0xffffffff
/*@Run time flag of CCK_PD HW type*/
#define CCK_PD_IC_TYPE1 (ODM_RTL8188E | ODM_RTL8812 | ODM_RTL8821 |\
ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8814A |\
ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8703B |\
ODM_RTL8195A | ODM_RTL8188F)
#define AAA_BASE 4
#define AAA_STEP 2
#define CCK_PD_IC_TYPE2 (ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8723D |\
ODM_RTL8710B | ODM_RTL8195B) /*extend 0xaaa*/
#define CCK_FA_MA_RESET 0xffffffff
#define CCK_PD_IC_TYPE3 (ODM_RTL8192F | ODM_RTL8721D)
/*@extend for different bw & path*/
#define EXTEND_CCK_CCATH_AAA_IC (ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8723D |ODM_RTL8710B)
/* 1 ============================================================
#define CCK_PD_IC_TYPE4 ODM_IC_JGR3_SERIES /*@extend for different bw & path*/
/*@Compile time flag of CCK_PD HW type*/
#if (RTL8188E_SUPPORT || RTL8812A_SUPPORT || RTL8821A_SUPPORT ||\
RTL8192E_SUPPORT || RTL8723B_SUPPORT || RTL8814A_SUPPORT ||\
RTL8881A_SUPPORT || RTL8822B_SUPPORT || RTL8703B_SUPPORT ||\
RTL8195A_SUPPORT || RTL8188F_SUPPORT)
#define PHYDM_COMPILE_CCKPD_TYPE1 /*@only 0xa0a*/
#endif
#if (RTL8197F_SUPPORT || RTL8821C_SUPPORT || RTL8723D_SUPPORT ||\
RTL8710B_SUPPORT || RTL8195B_SUPPORT)
#define PHYDM_COMPILE_CCKPD_TYPE2 /*@extend 0xaaa*/
#endif
#if (RTL8192F_SUPPORT || RTL8721D_SUPPORT)
#define PHYDM_COMPILE_CCKPD_TYPE3 /*@extend for different & path*/
#endif
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
#define PHYDM_COMPILE_CCKPD_TYPE4 /*@extend for different bw & path*/
#endif
/*@
* 1 ============================================================
* 1 enumeration
* 1 ============================================================
*/
enum cckpd_lv {
CCK_PD_LV_INIT = 0xff,
CCK_PD_LV_0 = 0,
CCK_PD_LV_1 = 1,
CCK_PD_LV_2 = 2,
CCK_PD_LV_3 = 3,
CCK_PD_LV_4 = 4,
CCK_PD_LV_MAX = 5
};
enum cckpd_mode {
CCK_BW20_1R = 0,
CCK_BW20_2R = 1,
CCK_BW20_3R = 2,
CCK_BW20_4R = 3,
CCK_BW40_1R = 4,
CCK_BW40_2R = 5,
CCK_BW40_3R = 6,
CCK_BW40_4R = 7
};
/*@
* 1 ============================================================
* 1 structure
* 1 ============================================================ */
* 1 ============================================================
*/
#ifdef PHYDM_SUPPORT_CCKPD
struct phydm_cckpd_struct {
u8 cur_cck_cca_thres; /*0xA0A*/
u8 cck_cca_th_aaa; /*0xAAA*/
u8 cckpd_hw_type;
u8 cur_cck_cca_thres; /*@current cck_pd value 0xa0a*/
u32 cck_fa_ma;
u8 cckpd_bkp;
u32 rvrt_val[2];
u8 pause_bitmap;/*will be removed*/
u8 rvrt_val;
u8 pause_lv;
u8 pause_cckpd_value[PHYDM_PAUSE_MAX_NUM]; /*will be removed*/
u8 cck_n_rx;
enum channel_width cck_bw;
enum cckpd_lv cck_pd_lv;
#ifdef PHYDM_COMPILE_CCKPD_TYPE2
u8 cck_cca_th_aaa; /*@current cs_ratio value 0xaaa*/
u8 aaa_default; /*@Init cs_ratio value - 0xaaa*/
#endif
#ifdef PHYDM_COMPILE_CCKPD_TYPE3
/*Default value*/
u8 cck_pd_20m_1r;
u8 cck_pd_20m_2r;
u8 cck_pd_40m_1r;
u8 cck_pd_40m_2r;
u8 cck_cs_ratio_20m_1r;
u8 cck_cs_ratio_20m_2r;
u8 cck_cs_ratio_40m_1r;
u8 cck_cs_ratio_40m_2r;
/*Current value*/
u8 cur_cck_pd_20m_1r;
u8 cur_cck_pd_20m_2r;
u8 cur_cck_pd_40m_1r;
u8 cur_cck_pd_40m_2r;
u8 cur_cck_cs_ratio_20m_1r;
u8 cur_cck_cs_ratio_20m_2r;
u8 cur_cck_cs_ratio_40m_1r;
u8 cur_cck_cs_ratio_40m_2r;
#endif
#ifdef PHYDM_COMPILE_CCKPD_TYPE4
/*@[bw][nrx][0:PD/1:CS][lv]*/
u8 cck_pd_table_jgr3[2][4][2][CCK_PD_LV_MAX];
#endif
};
#endif
/* 1 ============================================================
* 1 enumeration
* 1 ============================================================ */
/* 1 ============================================================
/*@
* 1 ============================================================
* 1 function prototype
* 1 ============================================================ */
* 1 ============================================================
*/
void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len);
void
phydm_set_cckpd_val(
void *dm_void,
u32 *val_buf,
u8 val_len
);
void
phydm_cck_pd_th(
void *dm_void
);
void
odm_pause_cck_packet_detection(
void *dm_void,
enum phydm_pause_type pause_type,
enum phydm_pause_level pause_level,
u8 cck_pd_threshold
);
void
phydm_cck_pd_init(
void *dm_void
);
void phydm_cck_pd_th(void *dm_void);
void phydm_cck_pd_init(void *dm_void);
#endif

2241
hal/phydm/phydm_ccx.c
View File

File diff suppressed because it is too large Load Diff

280
hal/phydm/phydm_ccx.h
View File

@@ -23,12 +23,16 @@
*
*****************************************************************************/
#ifndef __PHYDMCCX_H__
#define __PHYDMCCX_H__
#ifndef __PHYDMCCX_H__
#define __PHYDMCCX_H__
/* 1 ============================================================
/* @1 ============================================================
* 1 Definition
* 1 ============================================================ */
* 1 ============================================================
*/
#define ENV_MNTR_DBG 0 /*@debug for the HW processing time from NHM/CLM trigger and get result*/
#define ENV_MNTR_DBG_1 0 /*@debug 8812A & 8821A P2P Fail to get result*/
#define ENV_MNTR_DBG_2 0 /*@debug for read reister*/
#define CCX_EN 1
@@ -46,7 +50,7 @@
#define IGI_2_NHM_TH(igi) ((igi) << 1)/*NHM_threshold = IGI * 2*/
#define NTH_TH_2_RSSI(th) ((th >> 1) - 10)
/*FAHM*/
/*@FAHM*/
#define FAHM_INCLD_FA BIT(0)
#define FAHM_INCLD_CRC_OK BIT(1)
#define FAHM_INCLD_CRC_ER BIT(2)
@@ -56,25 +60,26 @@
#define FAHM_SUCCESS BIT(2)
#define ENV_MNTR_FAIL 0xff
/* 1 ============================================================
/* @1 ============================================================
* 1 enumrate
* 1 ============================================================ */
* 1 ============================================================
*/
enum phydm_clm_level {
CLM_RELEASE = 0,
CLM_LV_1 = 1, /* Low Priority function */
CLM_LV_2 = 2, /* Middle Priority function */
CLM_LV_3 = 3, /* High priority function (ex: Check hang function) */
CLM_LV_4 = 4, /* Debug function (the highest priority) */
CLM_MAX_NUM = 5
CLM_RELEASE = 0,
CLM_LV_1 = 1, /* @Low Priority function */
CLM_LV_2 = 2, /* @Middle Priority function */
CLM_LV_3 = 3, /* @High priority function (ex: Check hang function) */
CLM_LV_4 = 4, /* @Debug function (the highest priority) */
CLM_MAX_NUM = 5
};
enum phydm_nhm_level {
NHM_RELEASE = 0,
NHM_LV_1 = 1, /* Low Priority function */
NHM_LV_2 = 2, /* Middle Priority function */
NHM_LV_3 = 3, /* High priority function (ex: Check hang function) */
NHM_LV_4 = 4, /* Debug function (the highest priority) */
NHM_MAX_NUM = 5
NHM_RELEASE = 0,
NHM_LV_1 = 1, /* @Low Priority function */
NHM_LV_2 = 2, /* @Middle Priority function */
NHM_LV_3 = 3, /* @High priority function (ex: Check hang function) */
NHM_LV_4 = 4, /* @Debug function (the highest priority) */
NHM_MAX_NUM = 5
};
enum nhm_divider_opt_all {
@@ -89,29 +94,29 @@ enum nhm_setting {
RESTORE_NHM_SETTING
};
enum nhm_inexclude_cca_all {
enum nhm_option_cca_all {
NHM_EXCLUDE_CCA = 0,
NHM_INCLUDE_CCA = 1,
NHM_CCA_INIT
};
enum nhm_inexclude_txon_all {
enum nhm_option_txon_all {
NHM_EXCLUDE_TXON = 0,
NHM_INCLUDE_TXON = 1,
NHM_TXON_INIT
};
enum nhm_application {
NHM_BACKGROUND = 0,/*default*/
NHM_BACKGROUND = 0,/*@default*/
NHM_ACS = 1,
IEEE_11K_HIGH = 2,
IEEE_11K_LOW = 3,
INTEL_XBOX = 4,
NHM_DBG = 5, /*manual trigger*/
NHM_DBG = 5, /*@manual trigger*/
};
enum clm_application {
CLM_BACKGROUND = 0,/*default*/
CLM_BACKGROUND = 0,/*@default*/
CLM_ACS = 1,
};
@@ -120,9 +125,10 @@ enum clm_monitor_mode {
CLM_FW_MNTR = 2
};
/* 1 ============================================================
/* @1 ============================================================
* 1 structure
* 1 ============================================================ */
* 1 ============================================================
*/
struct env_trig_rpt {
u8 nhm_rpt_stamp;
u8 clm_rpt_stamp;
@@ -138,38 +144,39 @@ struct env_mntr_rpt {
};
struct nhm_para_info {
enum nhm_inexclude_txon_all incld_txon; /*Include TX on*/
enum nhm_inexclude_cca_all incld_cca; /*Include CCA*/
enum nhm_divider_opt_all div_opt; /*divider option*/
enum nhm_option_txon_all incld_txon; /*@Include TX on*/
enum nhm_option_cca_all incld_cca; /*@Include CCA*/
enum nhm_divider_opt_all div_opt; /*@divider option*/
enum nhm_application nhm_app;
enum phydm_nhm_level nhm_lv;
u16 mntr_time; /*0~262 unit ms*/
enum phydm_nhm_level nhm_lv;
u16 mntr_time; /*@0~262 unit ms*/
};
struct clm_para_info {
enum clm_application clm_app;
enum phydm_clm_level clm_lv;
u16 mntr_time; /*0~262 unit ms*/
enum phydm_clm_level clm_lv;
u16 mntr_time; /*@0~262 unit ms*/
};
struct ccx_info {
u32 nhm_trigger_time;
u32 clm_trigger_time;
u64 start_time; /*@monitor for the test duration*/
#ifdef NHM_SUPPORT
enum nhm_application nhm_app;
enum nhm_inexclude_txon_all nhm_include_txon;
enum nhm_inexclude_cca_all nhm_include_cca;
enum nhm_option_txon_all nhm_include_txon;
enum nhm_option_cca_all nhm_include_cca;
enum nhm_divider_opt_all nhm_divider_opt;
/*Report*/
u8 nhm_th[NHM_TH_NUM];
u8 nhm_result[NHM_RPT_NUM];
u16 nhm_period; /* 4us per unit */
u16 nhm_period; /* @4us per unit */
u8 nhm_igi;
u8 nhm_manual_ctrl;
u8 nhm_ratio; /*1% per nuit, it means the interference igi can't overcome.*/
u8 nhm_ratio; /*@1% per nuit, it means the interference igi can't overcome.*/
u8 nhm_rpt_sum;
u16 nhm_duration; /*Real time of NHM_VALID */
u16 nhm_duration; /*@Real time of NHM_VALID */
u8 nhm_set_lv;
boolean nhm_ongoing;
u8 nhm_rpt_stamp;
@@ -179,7 +186,7 @@ struct ccx_info {
u8 clm_manual_ctrl;
u8 clm_set_lv;
boolean clm_ongoing;
u16 clm_period; /* 4us per unit */
u16 clm_period; /* @4us per unit */
u16 clm_result;
u8 clm_ratio;
u32 clm_fw_result_acc;
@@ -190,195 +197,72 @@ struct ccx_info {
#ifdef FAHM_SUPPORT
boolean fahm_ongoing;
u8 env_mntr_igi;
u8 fahm_nume_sel; /*fahm_numerator_sel: select {FA, CRCOK, CRC_fail} */
u8 fahm_denum_sel; /*fahm_denumerator_sel: select {FA, CRCOK, CRC_fail} */
u8 fahm_nume_sel; /*@fahm_numerator_sel: select {FA, CRCOK, CRC_fail} */
u8 fahm_denom_sel; /*@fahm_denominator_sel: select {FA, CRCOK, CRC_fail} */
u16 fahm_period; /*unit: 4us*/
#endif
#if 1 /*Will remove*/
/*Previous Settings*/
enum nhm_inexclude_txon_all nhm_inexclude_txon_restore;
enum nhm_inexclude_cca_all nhm_inexclude_cca_restore;
u8 nhm_th_restore[NHM_TH_NUM];
u16 nhm_period_restore;/* 4us per unit */
u8 echo_igi; /* nhm_result comes from this igi */
#endif
};
/* 1 ============================================================
* 1 structure
* 1 ============================================================ */
void
phydm_get_nhm_result(
void *dm_void
);
void
phydm_set_nhm_th_by_igi(
void *dm_void,
u8 igi
);
void
phydm_nhm_setting(
void *dm_void,
u8 nhm_setting
);
void
phydm_ccx_monitor_trigger(
void *dm_void,
u16 monitor_time
);
void
phydm_ccx_monitor_result(
void *dm_void
);
/* @1 ============================================================
* 1 Function Prototype
* 1 ============================================================
*/
#ifdef FAHM_SUPPORT
void
phydm_fahm_init(
void *dm_void
);
void phydm_fahm_init(void *dm_void);
void
phydm_fahm_dbg(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
void phydm_fahm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len);
#endif
/*NHM*/
/*@NHM*/
#ifdef NHM_SUPPORT
void
phydm_nhm_trigger(
void *dm_void
);
void phydm_nhm_trigger(void *dm_void);
void
phydm_nhm_init(
void *dm_void
);
void phydm_nhm_init(void *dm_void);
void
phydm_nhm_dbg(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len);
u8 phydm_get_igi(void *dm_void, enum bb_path path);
#endif
/*CLM*/
/*@CLM*/
#ifdef CLM_SUPPORT
void
phydm_clm_c2h_report_handler(
void *dm_void,
u8 *cmd_buf,
u8 cmd_len
);
void phydm_clm_c2h_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
void
phydm_clm_h2c(
void *dm_void,
u16 obs_time,
u8 fw_clm_en
);
void phydm_clm_h2c(void *dm_void, u16 obs_time, u8 fw_clm_en);
void phydm_clm_setting(void *dm_void, u16 clm_period);
void
phydm_clm_setting(
void *dm_void,
u16 clm_period
);
void phydm_clm_trigger(void *dm_void);
void
phydm_clm_trigger(
void *dm_void
);
boolean phydm_clm_check_rdy(void *dm_void);
boolean
phydm_clm_check_rdy(
void *dm_void
);
void phydm_clm_get_utility(void *dm_void);
void
phydm_clm_get_utility(
void *dm_void
);
boolean phydm_clm_get_result(void *dm_void);
boolean
phydm_clm_get_result(
void *dm_void
);
u8 phydm_clm_mntr_set(void *dm_void, struct clm_para_info *clm_para);
u8
phydm_clm_mntr_set(
void *dm_void,
struct clm_para_info *clm_para
);
void phydm_set_clm_mntr_mode(void *dm_void, enum clm_monitor_mode mode);
void
phydm_set_clm_mntr_mode(
void *dm_void,
enum clm_monitor_mode mode
);
void
phydm_clm_dbg(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
void phydm_clm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len);
#endif
u8
phydm_env_mntr_trigger(
void *dm_void,
struct nhm_para_info *nhm_para,
struct clm_para_info *clm_para,
struct env_trig_rpt *rpt
);
u8 phydm_env_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para,
struct clm_para_info *clm_para,
struct env_trig_rpt *rpt);
u8
phydm_env_mntr_result(
void *dm_void,
struct env_mntr_rpt *rpt
);
u8 phydm_env_mntr_result(void *dm_void, struct env_mntr_rpt *rpt);
void
phydm_env_mntr_watchdog(
void *dm_void
);
void phydm_env_mntr_watchdog(void *dm_void);
void phydm_env_monitor_init(void *dm_void);
void
phydm_env_monitor_init(
void *dm_void
);
void
phydm_env_mntr_dbg(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
void phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif

619
hal/phydm/phydm_cfotracking.c
View File

@@ -25,212 +25,368 @@
#include "mp_precomp.h"
#include "phydm_precomp.h"
void
phydm_set_crystal_cap(
void *dm_void,
u8 crystal_cap
)
s32 phydm_get_cfo_hz(void *dm_void, u32 val, u8 bit_num, u8 frac_num)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK);
s32 val_s = 0;
if (cfo_track->crystal_cap == crystal_cap)
return;
val_s = phydm_cnvrt_2_sign(val, bit_num);
crystal_cap = crystal_cap & 0x3F;
cfo_track->crystal_cap = crystal_cap;
if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) {
#if (RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1)
/* write 0x24[22:17] = 0x24[16:11] = crystal_cap */
odm_set_bb_reg(dm, REG_AFE_XTAL_CTRL, 0x007ff800, (crystal_cap | (crystal_cap << 6)));
#endif
}
#if (RTL8812A_SUPPORT == 1)
else if (dm->support_ic_type & ODM_RTL8812) {
/* write 0x2C[30:25] = 0x2C[24:19] = crystal_cap */
odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x7FF80000, (crystal_cap | (crystal_cap << 6)));
}
#endif
#if (RTL8703B_SUPPORT == 1) || (RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8723D_SUPPORT == 1)
else if ((dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8192E | ODM_RTL8821 | ODM_RTL8723D))) {
/* 0x2C[23:18] = 0x2C[17:12] = crystal_cap */
odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x00FFF000, (crystal_cap | (crystal_cap << 6)));
}
#endif
#if (RTL8814A_SUPPORT == 1)
else if (dm->support_ic_type & ODM_RTL8814A) {
/* write 0x2C[26:21] = 0x2C[20:15] = crystal_cap */
odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x07FF8000, (crystal_cap | (crystal_cap << 6)));
}
#endif
#if (RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)
else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8197F)) {
/* write 0x24[30:25] = 0x28[6:1] = crystal_cap */
odm_set_bb_reg(dm, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap);
odm_set_bb_reg(dm, REG_AFE_PLL_CTRL, 0x7e, crystal_cap);
}
#endif
#if (RTL8710B_SUPPORT == 1)
else if (dm->support_ic_type & (ODM_RTL8710B)) {
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
/* write 0x60[29:24] = 0x60[23:18] = crystal_cap */
HAL_SetSYSOnReg((PADAPTER)dm->adapter, REG_SYS_XTAL_CTRL0, 0x3FFC0000, (crystal_cap | (crystal_cap << 6)));
#endif
}
#endif
PHYDM_DBG(dm, DBG_CFO_TRK, "Set rystal_cap = 0x%x\n", cfo_track->crystal_cap);
if (frac_num == 10) /*@ (X*312500)/1024 ~= X*305*/
val_s *= 305;
else if (frac_num == 11) /*@ (X*312500)/2048 ~= X*152*/
val_s *= 152;
else if (frac_num == 12) /*@ (X*312500)/4096 ~= X*76*/
val_s *= 76;
return val_s;
}
u8
phydm_get_default_crytaltal_cap(
void *dm_void
)
#if (ODM_IC_11AC_SERIES_SUPPORT)
void phydm_get_cfo_info_ac(void *dm_void, struct phydm_cfo_rpt *cfo)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 crystal_cap = 0x20;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i = 0;
u32 val[4] = {0};
u32 val_1[4] = {0};
u32 val_2[4] = {0};
u32 val_tmp = 0;
#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
val[0] = odm_read_4byte(dm, R_0xd0c);
val_1[0] = odm_read_4byte(dm, R_0xd10);
val_2[0] = odm_get_bb_reg(dm, R_0xd14, 0x1fff0000);
crystal_cap = rtlefuse->crystalcap;
#elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
#if (defined(PHYDM_COMPILE_ABOVE_2SS))
val[1] = odm_read_4byte(dm, R_0xd4c);
val_1[1] = odm_read_4byte(dm, R_0xd50);
val_2[1] = odm_get_bb_reg(dm, R_0xd54, 0x1fff0000);
#endif
crystal_cap = hal_data->crystal_cap;
#else
struct rtl8192cd_priv *priv = dm->priv;
#if (defined(PHYDM_COMPILE_ABOVE_3SS))
val[2] = odm_read_4byte(dm, R_0xd8c);
val_1[2] = odm_read_4byte(dm, R_0xd90);
val_2[2] = odm_get_bb_reg(dm, R_0xd94, 0x1fff0000);
#endif
if (priv->pmib->dot11RFEntry.xcap > 0)
crystal_cap = priv->pmib->dot11RFEntry.xcap;
#if (defined(PHYDM_COMPILE_ABOVE_4SS))
val[3] = odm_read_4byte(dm, R_0xdcc);
val_1[3] = odm_read_4byte(dm, R_0xdd0);
val_2[3] = odm_get_bb_reg(dm, R_0xdd4, 0x1fff0000);
#endif
for (i = 0; i < dm->num_rf_path; i++) {
val_tmp = val[i] & 0xfff; /*@ Short CFO, S(12,11)*/
cfo->cfo_rpt_s[i] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
val_tmp = val[i] >> 16; /*@ Long CFO, S(13,12)*/
cfo->cfo_rpt_l[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
val_tmp = val_1[i] & 0x7ff; /*@ SCFO, S(11,10)*/
cfo->cfo_rpt_sec[i] = phydm_get_cfo_hz(dm, val_tmp, 11, 10);
val_tmp = val_1[i] >> 16; /*@ Acq CFO, S(13,12)*/
cfo->cfo_rpt_acq[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
val_tmp = val_2[i]; /*@ End CFO, S(13,12)*/
cfo->cfo_rpt_end[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
}
}
#endif
crystal_cap = crystal_cap & 0x3f;
#if (ODM_IC_11N_SERIES_SUPPORT)
void phydm_get_cfo_info_n(void *dm_void, struct phydm_cfo_rpt *cfo)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 val[5] = {0};
u32 val_tmp = 0;
return crystal_cap;
odm_set_bb_reg(dm, R_0xd00, BIT(26), 1);
val[0] = odm_read_4byte(dm, R_0xdac); /*@ Short CFO*/
val[1] = odm_read_4byte(dm, R_0xdb0); /*@ Long CFO*/
val[2] = odm_read_4byte(dm, R_0xdb8); /*@ Sec CFO*/
val[3] = odm_read_4byte(dm, R_0xde0); /*@ Acq CFO*/
val[4] = odm_read_4byte(dm, R_0xdbc); /*@ End CFO*/
/*@[path-A]*/
if (dm->support_ic_type == ODM_RTL8721D) {
val_tmp = (val[0] & 0x0fff0000) >> 16; /*@ Short CFO, S(12,11)*/
cfo->cfo_rpt_s[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
val_tmp = (val[1] & 0x0fff0000) >> 16; /*@ Long CFO, S(12,11)*/
cfo->cfo_rpt_l[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
val_tmp = (val[2] & 0x0fff0000) >> 16; /*@ Sec CFO, S(12,11)*/
cfo->cfo_rpt_sec[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
val_tmp = (val[3] & 0x0fff0000) >> 16; /*@ Acq CFO, S(12,11)*/
cfo->cfo_rpt_acq[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
val_tmp = (val[4] & 0x0fff0000) >> 16; /*@ Acq CFO, S(12,11)*/
cfo->cfo_rpt_end[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
} else {
val_tmp = (val[0] & 0x0fff0000) >> 16; /*@ Short CFO, S(12,11)*/
cfo->cfo_rpt_s[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
val_tmp = (val[1] & 0x1fff0000) >> 16; /*@ Long CFO, S(13,12)*/
cfo->cfo_rpt_l[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
val_tmp = (val[2] & 0x7ff0000) >> 16; /*@ Sec CFO, S(11,10)*/
cfo->cfo_rpt_sec[0] = phydm_get_cfo_hz(dm, val_tmp, 11, 10);
val_tmp = (val[3] & 0x1fff0000) >> 16; /*@ Acq CFO, S(13,12)*/
cfo->cfo_rpt_acq[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
val_tmp = (val[4] & 0x1fff0000) >> 16; /*@ Acq CFO, S(13,12)*/
cfo->cfo_rpt_end[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
}
#if (defined(PHYDM_COMPILE_ABOVE_2SS))
/*@[path-B]*/
val_tmp = val[0] & 0xfff; /*@ Short CFO, S(12,11)*/
cfo->cfo_rpt_s[1] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
val_tmp = val[1] & 0x1fff; /*@ Long CFO, S(13,12)*/
cfo->cfo_rpt_l[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
val_tmp = val[2] & 0x7ff; /*@ Sec CFO, S(11,10)*/
cfo->cfo_rpt_sec[1] = phydm_get_cfo_hz(dm, val_tmp, 11, 10);
val_tmp = val[3] & 0x1fff; /*@ Acq CFO, S(13,12)*/
cfo->cfo_rpt_acq[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
val_tmp = val[4] & 0x1fff; /*@ Acq CFO, S(13,12)*/
cfo->cfo_rpt_end[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
#endif
}
void
phydm_set_atc_status(
void *dm_void,
boolean atc_status
)
void phydm_set_atc_status(void *dm_void, boolean atc_status)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK);
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
u32 reg_tmp = 0;
u32 mask_tmp = 0;
PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]ATC_en=%d\n", __func__, atc_status);
if (cfo_track->is_atc_status == atc_status)
return;
odm_set_bb_reg(dm, ODM_REG(BB_ATC, dm), ODM_BIT(BB_ATC, dm), atc_status);
reg_tmp = ODM_REG(BB_ATC, dm);
mask_tmp = ODM_BIT(BB_ATC, dm);
odm_set_bb_reg(dm, reg_tmp, mask_tmp, atc_status);
cfo_track->is_atc_status = atc_status;
}
boolean
phydm_get_atc_status(
void *dm_void
)
phydm_get_atc_status(void *dm_void)
{
boolean atc_status;
struct dm_struct *dm = (struct dm_struct *)dm_void;
boolean atc_status = false;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 reg_tmp = 0;
u32 mask_tmp = 0;
atc_status = (boolean)odm_get_bb_reg(dm, ODM_REG(BB_ATC, dm), ODM_BIT(BB_ATC, dm));
reg_tmp = ODM_REG(BB_ATC, dm);
mask_tmp = ODM_BIT(BB_ATC, dm);
atc_status = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]atc_status=%d\n", __func__, atc_status);
return atc_status;
}
#endif
void
phydm_cfo_tracking_reset(
void *dm_void
)
void phydm_get_cfo_info(void *dm_void, struct phydm_cfo_rpt *cfo)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK);
struct dm_struct *dm = (struct dm_struct *)dm_void;
switch (dm->ic_ip_series) {
#if (ODM_IC_11N_SERIES_SUPPORT)
case PHYDM_IC_N:
phydm_get_cfo_info_n(dm, cfo);
break;
#endif
#if (ODM_IC_11AC_SERIES_SUPPORT)
case PHYDM_IC_AC:
phydm_get_cfo_info_ac(dm, cfo);
break;
#endif
default:
break;
}
}
void phydm_set_crystal_cap(void *dm_void, u8 crystal_cap)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
if (cfo_track->crystal_cap == crystal_cap)
return;
if (phydm_set_crystal_cap_reg(dm, crystal_cap))
PHYDM_DBG(dm, DBG_CFO_TRK, "Set crystal_cap = 0x%x\n",
cfo_track->crystal_cap);
else
PHYDM_DBG(dm, DBG_CFO_TRK, "Set fail\n");
}
boolean
phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
u32 reg_val = 0;
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |
ODM_RTL8195B | ODM_RTL8812F | ODM_RTL8721D)) {
crystal_cap &= 0x7F;
reg_val = crystal_cap | (crystal_cap << 7);
} else {
crystal_cap &= 0x3F;
reg_val = crystal_cap | (crystal_cap << 6);
}
cfo_track->crystal_cap = crystal_cap;
if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) {
#if (RTL8188E_SUPPORT || RTL8188F_SUPPORT)
/* write 0x24[22:17] = 0x24[16:11] = crystal_cap */
odm_set_mac_reg(dm, R_0x24, 0x7ff800, reg_val);
#endif
}
#if (RTL8812A_SUPPORT)
else if (dm->support_ic_type & ODM_RTL8812) {
/* write 0x2C[30:25] = 0x2C[24:19] = crystal_cap */
odm_set_mac_reg(dm, R_0x2c, 0x7FF80000, reg_val);
}
#endif
#if (RTL8703B_SUPPORT || RTL8723B_SUPPORT || RTL8192E_SUPPORT ||\
RTL8821A_SUPPORT || RTL8723D_SUPPORT)
else if ((dm->support_ic_type &
(ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8192E | ODM_RTL8821 |
ODM_RTL8723D))) {
/* @0x2C[23:18] = 0x2C[17:12] = crystal_cap */
odm_set_mac_reg(dm, R_0x2c, 0x00FFF000, reg_val);
}
#endif
#if (RTL8814A_SUPPORT)
else if (dm->support_ic_type & ODM_RTL8814A) {
/* write 0x2C[26:21] = 0x2C[20:15] = crystal_cap */
odm_set_mac_reg(dm, R_0x2c, 0x07FF8000, reg_val);
}
#endif
#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8197F_SUPPORT ||\
RTL8192F_SUPPORT)
else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C |
ODM_RTL8197F | ODM_RTL8192F)) {
/* write 0x24[30:25] = 0x28[6:1] = crystal_cap */
odm_set_mac_reg(dm, R_0x24, 0x7e000000, crystal_cap);
odm_set_mac_reg(dm, R_0x28, 0x7e, crystal_cap);
}
#endif
#if (RTL8710B_SUPPORT)
else if (dm->support_ic_type & (ODM_RTL8710B)) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
/* write 0x60[29:24] = 0x60[23:18] = crystal_cap */
HAL_SetSYSOnReg(dm->adapter, R_0x60, 0x3FFC0000, reg_val);
#endif
}
#endif
#if (RTL8195B_SUPPORT)
else if (dm->support_ic_type & ODM_RTL8195B) {
phydm_set_crystalcap(dm, (u8)(reg_val & 0x7f));
}
#endif
#if (RTL8721D_SUPPORT)
else if (dm->support_ic_type & (ODM_RTL8721D)) {
/* write 0x4800_0228[30:24] crystal_cap */
/*HAL_SetSYSOnReg(dm->adapter, */
/*REG_SYS_XTAL_8721d, 0x7F000000, crystal_cap);*/
u32 temp_val = HAL_READ32(SYSTEM_CTRL_BASE_LP,
REG_SYS_EFUSE_SYSCFG2);
temp_val = ((crystal_cap << 24) & 0x7F000000)
| (temp_val & (~0x7F000000));
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_SYS_EFUSE_SYSCFG2,
temp_val);
}
#endif
#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)
else if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |
ODM_RTL8812F)) {
/* write 0x1040[23:17] = 0x1040[16:10] = crystal_cap */
odm_set_mac_reg(dm, R_0x1040, 0x00FFFC00, reg_val);
} else {
return false;
}
#endif
return true;
}
void phydm_cfo_tracking_reset(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__);
cfo_track->def_x_cap = phydm_get_default_crytaltal_cap(dm);
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8195B |
ODM_RTL8812F))
cfo_track->def_x_cap = cfo_track->crystal_cap_default & 0x7f;
else
cfo_track->def_x_cap = cfo_track->crystal_cap_default & 0x3f;
cfo_track->is_adjust = true;
if (cfo_track->crystal_cap > cfo_track->def_x_cap) {
phydm_set_crystal_cap(dm, cfo_track->crystal_cap - 1);
PHYDM_DBG(dm, DBG_CFO_TRK, "approch to Init-val (0x%x)\n", cfo_track->crystal_cap);
PHYDM_DBG(dm, DBG_CFO_TRK, "approch to Init-val (0x%x)\n",
cfo_track->crystal_cap);
} else if (cfo_track->crystal_cap < cfo_track->def_x_cap) {
phydm_set_crystal_cap(dm, cfo_track->crystal_cap + 1);
PHYDM_DBG(dm, DBG_CFO_TRK, "approch to init-val 0x%x\n", cfo_track->crystal_cap);
PHYDM_DBG(dm, DBG_CFO_TRK, "approch to init-val 0x%x\n",
cfo_track->crystal_cap);
}
#if ODM_IC_11N_SERIES_SUPPORT
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
phydm_set_atc_status(dm, true);
if (dm->support_ic_type & ODM_IC_11N_SERIES)
phydm_set_atc_status(dm, true);
#endif
#endif
}
void
phydm_cfo_tracking_init(
void *dm_void
)
void phydm_cfo_tracking_init(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK);
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
cfo_track->def_x_cap = cfo_track->crystal_cap = phydm_get_default_crytaltal_cap(dm);
cfo_track->is_atc_status = phydm_get_atc_status(dm);
PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]=========>\n", __func__);
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8195B |
ODM_RTL8812F))
cfo_track->crystal_cap = cfo_track->crystal_cap_default & 0x7f;
else
cfo_track->crystal_cap = cfo_track->crystal_cap_default & 0x3f;
cfo_track->def_x_cap = cfo_track->crystal_cap;
cfo_track->is_adjust = true;
PHYDM_DBG(dm, DBG_CFO_TRK, "ODM_CfoTracking_init()=========>\n");
PHYDM_DBG(dm, DBG_CFO_TRK, "ODM_CfoTracking_init(): is_atc_status = %d, crystal_cap = 0x%x\n", cfo_track->is_atc_status, cfo_track->def_x_cap);
PHYDM_DBG(dm, DBG_CFO_TRK, "crystal_cap=0x%x\n", cfo_track->def_x_cap);
#if RTL8822B_SUPPORT
/* Crystal cap. control by WiFi */
if (dm->support_ic_type & ODM_RTL8822B)
odm_set_bb_reg(dm, 0x10, 0x40, 0x1);
#endif
#if RTL8821C_SUPPORT
/* Crystal cap. control by WiFi */
if (dm->support_ic_type & ODM_RTL8821C)
odm_set_bb_reg(dm, 0x10, 0x40, 0x1);
#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
/* @Crystal cap. control by WiFi */
if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C))
odm_set_mac_reg(dm, R_0x10, 0x40, 0x1);
#endif
}
void
phydm_cfo_tracking(
void *dm_void
)
void phydm_cfo_tracking(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK);
s32 cfo_avg = 0, cfo_path_sum = 0; /*avg among each path*/
u32 cfo_rpt_sum, cfo_khz_avg[4] = {0};
s8 crystal_cap = cfo_track->crystal_cap;
u8 i, valid_path_cnt = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
s32 cfo_avg = 0, cfo_path_sum = 0, cfo_abs = 0;
u32 cfo_rpt_sum = 0, cfo_khz_avg[4] = {0};
s8 crystal_cap = cfo_track->crystal_cap;
u8 i = 0, valid_path_cnt = 0;
if (!(dm->support_ability & ODM_BB_CFO_TRACKING)) {
if (!(dm->support_ability & ODM_BB_CFO_TRACKING))
return;
}
PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__);
if (!dm->is_linked || !dm->is_one_entry_only) {
phydm_cfo_tracking_reset(dm);
PHYDM_DBG(dm, DBG_CFO_TRK, "is_linked = %d, one_entry_only = %d\n",
dm->is_linked, dm->is_one_entry_only);
PHYDM_DBG(dm, DBG_CFO_TRK, "is_linked=%d, one_entry_only=%d\n",
dm->is_linked, dm->is_one_entry_only);
} else {
/* No new packet */
if (cfo_track->packet_count == cfo_track->packet_count_pre) {
PHYDM_DBG(dm, DBG_CFO_TRK, "Pkt cnt doesn't change\n");
@@ -238,23 +394,30 @@ phydm_cfo_tracking(
}
cfo_track->packet_count_pre = cfo_track->packet_count;
/*Calculate CFO */
/*@Calculate CFO */
for (i = 0; i < dm->num_rf_path; i++) {
if (cfo_track->CFO_cnt[i] == 0)
if (!(dm->rx_ant_status & BIT(i)))
continue;
valid_path_cnt++;
cfo_rpt_sum = (u32)CFO_HW_RPT_2_KHZ(((cfo_track->CFO_tail[i] < 0) ? (0 - cfo_track->CFO_tail[i]) : cfo_track->CFO_tail[i]));
if (cfo_track->CFO_tail[i] < 0)
cfo_abs = 0 - cfo_track->CFO_tail[i];
else
cfo_abs = cfo_track->CFO_tail[i];
cfo_rpt_sum = (u32)CFO_HW_RPT_2_KHZ(cfo_abs);
cfo_khz_avg[i] = cfo_rpt_sum / cfo_track->CFO_cnt[i];
PHYDM_DBG(dm, DBG_CFO_TRK, "[Path-%d] CFO_sum = (( %d )), cnt = (( %d )) , CFO_avg= (( %s%d )) kHz\n",
i, cfo_rpt_sum, cfo_track->CFO_cnt[i], ((cfo_track->CFO_tail[i] < 0) ? "-" : " "), cfo_khz_avg[i]);
}
PHYDM_DBG(dm, DBG_CFO_TRK,
"[Path-%d] CFO_sum=((%d)), cnt=((%d)), CFO_avg=((%s%d))kHz\n",
i, cfo_rpt_sum, cfo_track->CFO_cnt[i],
((cfo_track->CFO_tail[i] < 0) ? "-" : " "),
cfo_khz_avg[i]);
for (i = 0; i < valid_path_cnt; i++) {
if (cfo_track->CFO_tail[i] < 0) {
if (cfo_track->CFO_tail[i] < 0)
cfo_path_sum += (0 - (s32)cfo_khz_avg[i]);
} else
else
cfo_path_sum += (s32)cfo_khz_avg[i];
}
@@ -265,7 +428,8 @@ phydm_cfo_tracking(
cfo_track->CFO_ave_pre = cfo_avg;
PHYDM_DBG(dm, DBG_CFO_TRK, "path_cnt = ((%d)), CFO_avg_path=((%d kHz))\n", valid_path_cnt, cfo_avg);
PHYDM_DBG(dm, DBG_CFO_TRK, "path_cnt=%d, CFO_avg_path=%d kHz\n",
valid_path_cnt, cfo_avg);
/*reset counter*/
for (i = 0; i < dm->num_rf_path; i++) {
@@ -274,98 +438,157 @@ phydm_cfo_tracking(
}
/* To adjust crystal cap or not */
if (cfo_track->is_adjust == false) {
if (cfo_avg > CFO_TRK_ENABLE_TH || cfo_avg < (-CFO_TRK_ENABLE_TH))
if (!cfo_track->is_adjust) {
if (cfo_avg > CFO_TRK_ENABLE_TH ||
cfo_avg < (-CFO_TRK_ENABLE_TH))
cfo_track->is_adjust = true;
} else {
if (cfo_avg < CFO_TRK_STOP_TH && cfo_avg > (-CFO_TRK_STOP_TH))
if (cfo_avg < CFO_TRK_STOP_TH &&
cfo_avg > (-CFO_TRK_STOP_TH))
cfo_track->is_adjust = false;
}
#ifdef ODM_CONFIG_BT_COEXIST
/*BT case: Disable CFO tracking */
/*@BT case: Disable CFO tracking */
if (dm->bt_info_table.is_bt_enabled) {
cfo_track->is_adjust = false;
phydm_set_crystal_cap(dm, cfo_track->def_x_cap);
PHYDM_DBG(dm, DBG_CFO_TRK, "Disable CFO tracking for BT\n");
PHYDM_DBG(dm, DBG_CFO_TRK, "[BT]Disable CFO_track\n");
}
#endif
/*Adjust Crystal Cap. */
/*@Adjust Crystal Cap. */
if (cfo_track->is_adjust) {
if (cfo_avg > CFO_TRK_STOP_TH)
crystal_cap += 1;
else if (cfo_avg < (-CFO_TRK_STOP_TH))
crystal_cap -=1;
crystal_cap -= 1;
if (crystal_cap > 0x3f)
crystal_cap = 0x3f;
else if (crystal_cap < 0)
if (dm->support_ic_type & (ODM_RTL8822C |
ODM_RTL8814B | ODM_RTL8195B | ODM_RTL8812F)) {
if (crystal_cap > 0x7F)
crystal_cap = 0x7F;
} else {
if (crystal_cap > 0x3F)
crystal_cap = 0x3F;
}
if (crystal_cap < 0)
crystal_cap = 0;
phydm_set_crystal_cap(dm, (u8)crystal_cap);
}
PHYDM_DBG(dm, DBG_CFO_TRK, "Crystal cap{Current, Default}={0x%x, 0x%x}\n\n",
cfo_track->crystal_cap, cfo_track->def_x_cap);
/* Dynamic ATC switch */
PHYDM_DBG(dm, DBG_CFO_TRK, "X_cap{Curr,Default}={0x%x,0x%x}\n",
cfo_track->crystal_cap, cfo_track->def_x_cap);
/* @Dynamic ATC switch */
#if ODM_IC_11N_SERIES_SUPPORT
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
if (dm->support_ic_type & ODM_IC_11N_SERIES) {
if (cfo_avg < CFO_TH_ATC && cfo_avg > -CFO_TH_ATC) {
if (cfo_avg < CFO_TH_ATC && cfo_avg > -CFO_TH_ATC)
phydm_set_atc_status(dm, false);
PHYDM_DBG(dm, DBG_CFO_TRK, "Disable ATC\n");
} else {
else
phydm_set_atc_status(dm, true);
PHYDM_DBG(dm, DBG_CFO_TRK, "Enable ATC\n");
}
}
#endif
#endif
}
}
void
phydm_parsing_cfo(
void *dm_void,
void *pktinfo_void,
s8 *pcfotail,
u8 num_ss
)
void phydm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail,
u8 num_ss)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pktinfo_void;
struct phydm_cfo_track_struct *cfo_track = (struct phydm_cfo_track_struct *)phydm_get_structure(dm, PHYDM_CFOTRACK);
u8 i;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_perpkt_info_struct *pktinfo = NULL;
struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
boolean valid_info = false;
u8 i = 0;
if (!(dm->support_ability & ODM_BB_CFO_TRACKING))
return;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
pktinfo = (struct phydm_perpkt_info_struct *)pktinfo_void;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
if (pktinfo->is_packet_match_bssid)
valid_info = true;
#else
if (pktinfo->station_id != 0)
if (dm->number_active_client == 1)
valid_info = true;
#endif
{
if (num_ss > dm->num_rf_path) /*For fool proof*/
if (valid_info) {
if (num_ss > dm->num_rf_path) /*@For fool proof*/
num_ss = dm->num_rf_path;
#if 0
PHYDM_DBG(dm, DBG_CFO_TRK, "num_ss=%d, num_rf_path=%d\n",
num_ss, dm->num_rf_path);
#endif
/*PHYDM_DBG(dm, DBG_CFO_TRK, "num_ss = ((%d)), dm->num_rf_path = ((%d))\n", num_ss, dm->num_rf_path);*/
/* 3 Update CFO report for path-A & path-B */
/* @ Update CFO report for path-A & path-B */
/* Only paht-A and path-B have CFO tail and short CFO */
for (i = 0; i < num_ss; i++) {
for (i = 0; i < dm->num_rf_path; i++) {
if (!(dm->rx_ant_status & BIT(i)))
continue;
cfo_track->CFO_tail[i] += pcfotail[i];
cfo_track->CFO_cnt[i]++;
/*PHYDM_DBG(dm, DBG_CFO_TRK, "[ID %d][path %d][rate 0x%x] CFO_tail = ((%d)), CFO_tail_sum = ((%d)), CFO_cnt = ((%d))\n",
pktinfo->station_id, i, pktinfo->data_rate, pcfotail[i], cfo_track->CFO_tail[i], cfo_track->CFO_cnt[i]);
*/
#if 0
PHYDM_DBG(dm, DBG_CFO_TRK,
"[ID %d][path %d][rate 0x%x] CFO_tail = ((%d)), CFO_tail_sum = ((%d)), CFO_cnt = ((%d))\n",
pktinfo->station_id, i, pktinfo->data_rate,
pcfotail[i], cfo_track->CFO_tail[i],
cfo_track->CFO_cnt[i]);
#endif
}
/* 3 Update packet counter */
/* @ Update packet counter */
if (cfo_track->packet_count == 0xffffffff)
cfo_track->packet_count = 0;
else
cfo_track->packet_count++;
}
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void phy_Init_crystal_capacity(void *dm_void, u8 crystal_cap)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (!phydm_set_crystal_cap_reg(dm, crystal_cap))
RT_TRACE_F(COMP_INIT, DBG_SERIOUS,
("Crystal is not initialized!\n"));
}
#endif
void phydm_cfo_tracking_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
char help[] = "-h";
u32 var1[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
if ((strcmp(input[1], help) == 0)) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"set Xcap: {1}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"show Xcap: {100}\n");
} else {
PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
if (var1[0] == 1) {
PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);
phydm_set_crystal_cap(dm, (u8)var1[1]);
PDM_SNPF(out_len, used, output + used, out_len - used,
"Set X_cap=0x%x\n", cfo_track->crystal_cap);
} else if (var1[0] == 100) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"X_cap=0x%x\n", cfo_track->crystal_cap);
}
}
*_used = used;
*_out_len = out_len;
}

70
hal/phydm/phydm_cfotracking.h
View File

@@ -23,49 +23,51 @@
*
*****************************************************************************/
#ifndef __PHYDMCFOTRACK_H__
#define __PHYDMCFOTRACK_H__
#ifndef __PHYDMCFOTRACK_H__
#define __PHYDMCFOTRACK_H__
#define CFO_TRACKING_VERSION "1.4" /*2015.10.01 Stanley, Modify for 8822B*/
#define CFO_TRACKING_VERSION "2.0"
#define CFO_TRK_ENABLE_TH 20 /* (kHz) enable CFO Tracking threshold*/
#define CFO_TRK_STOP_TH 10 /* (kHz) disable CFO Tracking threshold*/
#define CFO_TH_ATC 80 /* kHz */
#define CFO_TRK_ENABLE_TH 20 /* @kHz enable CFO_Track threshold*/
#define CFO_TRK_STOP_TH 10 /* @kHz disable CFO_Track threshold*/
#define CFO_TH_ATC 80 /* @kHz */
struct phydm_cfo_track_struct {
boolean is_atc_status;
boolean is_adjust; /*already modify crystal cap*/
u8 crystal_cap;
u8 def_x_cap;
s32 CFO_tail[4];
u32 CFO_cnt[4];
s32 CFO_ave_pre;
u32 packet_count;
u32 packet_count_pre;
boolean is_adjust; /*@already modify crystal cap*/
u8 crystal_cap;
u8 crystal_cap_default;
u8 def_x_cap;
s32 CFO_tail[4];
u32 CFO_cnt[4];
s32 CFO_ave_pre;
u32 packet_count;
u32 packet_count_pre;
};
void
phydm_set_crystal_cap(
void *dm_void,
u8 crystal_cap
);
struct phydm_cfo_rpt {
s32 cfo_rpt_s[PHYDM_MAX_RF_PATH];
s32 cfo_rpt_l[PHYDM_MAX_RF_PATH];
s32 cfo_rpt_acq[PHYDM_MAX_RF_PATH];
s32 cfo_rpt_sec[PHYDM_MAX_RF_PATH];
s32 cfo_rpt_end[PHYDM_MAX_RF_PATH];
};
void
phydm_cfo_tracking_init(
void *dm_void
);
void phydm_get_cfo_info(void *dm_void, struct phydm_cfo_rpt *cfo);
void
phydm_cfo_tracking(
void *dm_void
);
void phydm_set_crystal_cap(void *dm_void, u8 crystal_cap);
void
phydm_parsing_cfo(
void *dm_void,
void *pktinfo_void,
s8 *pcfotail,
u8 num_ss
);
boolean phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap);
void phydm_cfo_tracking_init(void *dm_void);
void phydm_cfo_tracking(void *dm_void);
void phydm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail,
u8 num_ss);
void phydm_cfo_tracking_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void phy_Init_crystal_capacity(void *dm_void, u8 crystal_cap);
#endif
#endif

5857
hal/phydm/phydm_debug.c
View File

File diff suppressed because it is too large Load Diff

374
hal/phydm/phydm_debug.h
View File

@@ -23,101 +23,86 @@
*
*****************************************************************************/
#ifndef __ODM_DBG_H__
#ifndef __ODM_DBG_H__
#define __ODM_DBG_H__
/*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/
/*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/
/*#define DEBUG_VERSION "1.3"*/ /*2016.04.28 YuChen*/
#define DEBUG_VERSION "1.4" /*2017.03.13 Dino*/
/*@#define DEBUG_VERSION "1.1"*/ /*@2015.07.29 YuChen*/
/*@#define DEBUG_VERSION "1.2"*/ /*@2015.08.28 Dino*/
/*@#define DEBUG_VERSION "1.3"*/ /*@2016.04.28 YuChen*/
/*@#define DEBUG_VERSION "1.4"*/ /*@2017.03.13 Dino*/
#define DEBUG_VERSION "2.0" /*@2018.01.10 Dino*/
/* -----------------------------------------------------------------------------
* Define the debug levels
*
* 1. DBG_TRACE and DBG_LOUD are used for normal cases.
* So that, they can help SW engineer to develope or trace states changed
* and also help HW enginner to trace every operation to and from HW,
* e.g IO, Tx, Rx.
*
* 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
* which help us to debug SW or HW.
*
* -----------------------------------------------------------------------------
*
* Never used in a call to ODM_RT_TRACE()!
* */
#define ODM_DBG_OFF 1
/*@
* ============================================================
* Definition
* ============================================================
*/
/*
* Fatal bug.
* For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
* resource allocation failed, unexpected HW behavior, HW BUG and so on.
* */
#define ODM_DBG_SERIOUS 2
/*
* Abnormal, rare, or unexpeted cases.
* For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
* */
#define ODM_DBG_WARNING 3
/*
* Normal case with useful information about current SW or HW state.
* For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
* SW protocol state change, dynamic mechanism state change and so on.
* */
#define ODM_DBG_LOUD 4
/*
* Normal case with detail execution flow or information.
* */
#define ODM_DBG_TRACE 5
/*FW DBG MSG*/
#define RATE_DECISION 1
#define INIT_RA_TABLE 2
#define RATE_UP 4
/*@FW DBG MSG*/
#define RATE_DECISION 1
#define INIT_RA_TABLE 2
#define RATE_UP 4
#define RATE_DOWN 8
#define TRY_DONE 16
#define RA_H2C 32
#define F_RATE_AP_RPT 64
#define DBC_FW_CLM 9
#define F_RATE_AP_RPT 64
#define DBC_FW_CLM 9
/* -----------------------------------------------------------------------------
#define PHYDM_SNPRINT_SIZE 64
/* @----------------------------------------------------------------------------
* Define the tracing components
*
* -----------------------------------------------------------------------------
*BB FW Functions*/
#define PHYDM_FW_COMP_RA BIT(0)
#define PHYDM_FW_COMP_MU BIT(1)
#define PHYDM_FW_COMP_PATH_DIV BIT(2)
#define PHYDM_FW_COMP_PT BIT(3)
* BB FW Functions
*/
#define PHYDM_FW_COMP_RA BIT(0)
#define PHYDM_FW_COMP_MU BIT(1)
#define PHYDM_FW_COMP_PATH_DIV BIT(2)
#define PHYDM_FW_COMP_PT BIT(3)
/*------------------------Export Marco Definition---------------------------*/
/*@------------------------Export Marco Definition---------------------------*/
#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA)
#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
extern VOID DCMD_Printf(const char *pMsg);
#if (DBG_CMD_SUPPORT == 1)
extern VOID DCMD_Printf(const char *pMsg);
#else
#define DCMD_Printf(_pMsg)
#endif
#define pr_debug DbgPrint
#define dcmd_printf DCMD_Printf
#define dcmd_scanf DCMD_Scanf
#define RT_PRINTK pr_debug
#if OS_WIN_FROM_WIN10(OS_VERSION)
#define pr_debug(fmt, ...) DbgPrintEx(DPFLTR_IHVNETWORK_ID, DPFLTR_ERROR_LEVEL, fmt, ##__VA_ARGS__)
#else
#define pr_debug DbgPrint
#endif
#define dcmd_printf DCMD_Printf
#define dcmd_scanf DCMD_Scanf
#define RT_PRINTK pr_debug
#define PRINT_MAX_SIZE 512
#define PHYDM_SNPRINTF RT_SPRINTF
#define PHYDM_TRACE(_MSG_) EXhalPHYDMoutsrc_Print(_MSG_)
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
#define PHYDM_SNPRINTF snprintf
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#undef pr_debug
#define pr_debug printk
#undef pr_debug
#define pr_debug printk
#define RT_PRINTK(fmt, args...) pr_debug(fmt, ## args)
#define RT_DISP(dbgtype, dbgflag, printstr)
#define RT_TRACE(adapter, comp, drv_level, fmt, args...) \
RTW_INFO(fmt, ## args)
#define PHYDM_SNPRINTF snprintf
#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
#define pr_debug(fmt, args...) RTW_PRINT_MSG(fmt, ## args)
#define RT_DEBUG(comp, drv_level, fmt, args...) \
RTW_PRINT_MSG(fmt, ## args)
#define PHYDM_SNPRINTF snprintf
#else
#define pr_debug panic_printk
/*#define RT_PRINTK(fmt, args...) pr_debug("%s(): " fmt, __FUNCTION__, ## args);*/
/*@#define RT_PRINTK(fmt, args...) pr_debug("%s(): " fmt, __FUNCTION__, ## args);*/
#define RT_PRINTK(fmt, args...) pr_debug(fmt, ## args)
#define PHYDM_SNPRINTF snprintf
#endif
#ifndef ASSERT
@@ -128,16 +113,16 @@
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define PHYDM_DBG(dm, comp, fmt, args...) \
do { \
if ((comp) & (dm->debug_components)) { \
if ((comp) & dm->debug_components) { \
pr_debug("[PHYDM] "); \
RT_PRINTK(fmt, ## args); \
RT_PRINTK(fmt, ## args); \
} \
} while (0)
#define PHYDM_DBG_F(dm, comp, fmt, args...) \
do { \
if ((comp) & dm->debug_components) { \
RT_PRINTK(fmt, ## args); \
RT_PRINTK(fmt, ## args); \
} \
} while (0)
@@ -158,7 +143,6 @@
static __inline void PHYDM_DBG(PDM_ODM_T dm, int comp, char *fmt, ...)
{
RT_STATUS rt_status;
va_list args;
char buf[PRINT_MAX_SIZE] = {0};
@@ -178,12 +162,15 @@ static __inline void PHYDM_DBG(PDM_ODM_T dm, int comp, char *fmt, ...)
return;
}
DbgPrint("[PHYDM] %s", buf);
#if OS_WIN_FROM_WIN10(OS_VERSION)
DbgPrintEx(DPFLTR_IHVNETWORK_ID, DPFLTR_ERROR_LEVEL, "%s", buf);
#else
DbgPrint("%s", buf);
#endif
}
static __inline void PHYDM_DBG_F(PDM_ODM_T dm, int comp, char *fmt, ...)
{
RT_STATUS rt_status;
va_list args;
char buf[PRINT_MAX_SIZE] = {0};
@@ -199,79 +186,141 @@ static __inline void PHYDM_DBG_F(PDM_ODM_T dm, int comp, char *fmt, ...)
va_end(args);
if (rt_status != RT_STATUS_SUCCESS) {
/*DbgPrint("DM Print Fail\n");*/
/*@DbgPrint("DM Print Fail\n");*/
return;
}
#if OS_WIN_FROM_WIN10(OS_VERSION)
DbgPrintEx(DPFLTR_IHVNETWORK_ID, DPFLTR_ERROR_LEVEL, "%s", buf);
#else
DbgPrint("%s", buf);
#endif
}
#define PHYDM_PRINT_ADDR(p_dm, comp, title_str, ptr) do {\
if ((comp) & p_dm->debug_components) { \
\
int __i; \
u8 *__ptr = (u8 *)ptr; \
pr_debug("[PHYDM] "); \
pr_debug(title_str); \
pr_debug(" "); \
for (__i = 0; __i < 6; __i++) \
pr_debug("%02X%s", __ptr[__i], (__i == 5) ? "" : "-"); \
pr_debug("\n"); \
#define PHYDM_PRINT_ADDR(p_dm, comp, title_str, ptr) \
do { \
if ((comp) & p_dm->debug_components) { \
\
int __i; \
u8 *__ptr = (u8 *)ptr; \
pr_debug("[PHYDM] "); \
pr_debug(title_str); \
pr_debug(" "); \
for (__i = 0; __i < 6; __i++) \
pr_debug("%02X%s", __ptr[__i], (__i == 5) ? "" : "-"); \
pr_debug("\n"); \
} \
} while (0)
#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
#define PHYDM_DBG(dm, comp, fmt, args...) \
do { \
if ((comp) & dm->debug_components) { \
RT_DEBUG(COMP_PHYDM, \
DBG_DMESG, "[PHYDM] " fmt, ##args); \
} \
} while (0)
#define PHYDM_DBG_F(dm, comp, fmt, args...) \
do { \
if ((comp) & dm->debug_components) { \
RT_DEBUG(COMP_PHYDM, \
DBG_DMESG, fmt, ##args); \
} \
} while (0)
#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr) \
do { \
if ((comp) & dm->debug_components) { \
RT_DEBUG(COMP_PHYDM, \
DBG_DMESG, "[PHYDM] " title_str "%pM\n", \
addr); \
} \
} while (0)
#elif defined(DM_ODM_CE_MAC80211_V2)
#define PHYDM_DBG(dm, comp, fmt, args...)
#define PHYDM_DBG_F(dm, comp, fmt, args...)
#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr)
#else
#define PHYDM_DBG(dm, comp, fmt, args...) \
do { \
if ((comp) & (dm->debug_components)) { \
RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \
DBG_DMESG, "[PHYDM] " fmt, ##args); \
} \
#define PHYDM_DBG(dm, comp, fmt, args...) \
do { \
struct dm_struct *__dm = (dm); \
if ((comp) & __dm->debug_components) { \
RT_TRACE(((struct rtl_priv *)__dm->adapter),\
COMP_PHYDM, DBG_DMESG, \
"[PHYDM] " fmt, ##args); \
} \
} while (0)
#define PHYDM_DBG_F(dm, comp, fmt, args...) \
do { \
if ((comp) & dm->debug_components) { \
RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \
DBG_DMESG, fmt, ##args); \
#define PHYDM_DBG_F(dm, comp, fmt, args...) \
do { \
struct dm_struct *__dm = (dm); \
if ((comp) & __dm->debug_components) { \
RT_TRACE(((struct rtl_priv *)__dm->adapter),\
COMP_PHYDM, DBG_DMESG, fmt, ##args); \
} \
} while (0)
#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr) \
do { \
if ((comp) & dm->debug_components) { \
RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \
DBG_DMESG, "[PHYDM] " title_str "%pM\n", \
addr); \
} \
#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr) \
do { \
struct dm_struct *__dm = (dm); \
if ((comp) & __dm->debug_components) { \
RT_TRACE(((struct rtl_priv *)__dm->adapter),\
COMP_PHYDM, DBG_DMESG, \
"[PHYDM] " title_str "%pM\n", addr);\
} \
} while (0)
#endif
#define ODM_RT_TRACE(dm, comp, level, fmt)
#else
#else /*@#if DBG*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
static __inline void PHYDM_DBG(struct dm_struct *dm, int comp, char *fmt, ...)
{}
static __inline void PHYDM_DBG_F(struct dm_struct *dm, int comp, char *fmt, ...)
{}
static __inline void PHYDM_DBG(struct dm_struct *dm, int comp, char *fmt, ...)
{
RT_STATUS rt_status;
va_list args;
char buf[PRINT_MAX_SIZE] = {0};
if ((comp & dm->debug_components) == 0)
return;
if (fmt == NULL)
return;
va_start(args, fmt);
rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
va_end(args);
if (rt_status != RT_STATUS_SUCCESS) {
DbgPrint("Failed (%d) to print message to buffer\n", rt_status);
return;
}
PHYDM_TRACE(buf);
}
static __inline void PHYDM_DBG_F(struct dm_struct *dm, int comp, char *fmt, ...)
{
}
#else
#define PHYDM_DBG(dm, comp, fmt)
#define PHYDM_DBG_F(dm, comp, fmt)
#define PHYDM_DBG(dm, comp, fmt, args...)
#define PHYDM_DBG_F(dm, comp, fmt, args...)
#endif
#define PHYDM_PRINT_ADDR(dm, comp, title_str, ptr)
#define ODM_RT_TRACE(dm, comp, level, fmt)
#endif
#define BB_DBGPORT_PRIORITY_3 3 /*Debug function (the highest priority)*/
#define BB_DBGPORT_PRIORITY_2 2 /*Check hang function & Strong function*/
#define BB_DBGPORT_PRIORITY_1 1 /*Watch dog function*/
#define BB_DBGPORT_RELEASE 0 /*Init value (the lowest priority)*/
#define DBGPORT_PRI_3 3 /*@Debug function (the highest priority)*/
#define DBGPORT_PRI_2 2 /*@Check hang function & Strong function*/
#define DBGPORT_PRI_1 1 /*Watch dog function*/
#define DBGPORT_RELEASE 0 /*@Init value (the lowest priority)*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define PHYDM_DBGPRINT 0
#define PHYDM_SSCANF(x, y, z) dcmd_scanf(x, y, z)
#define PHYDM_VAST_INFO_SNPRINTF PDM_SNPF
#define PDM_VAST_SNPF PDM_SNPF
#if (PHYDM_DBGPRINT == 1)
#define PDM_SNPF(msg) \
do {\
@@ -280,7 +329,8 @@ static __inline void PHYDM_DBG_F(struct dm_struct *dm, int comp, char *fmt, ...)
} while (0)
#else
static __inline void PDM_SNPF(u32 out_len, u32 used, char * buff, int len, char *fmt, ...)
static __inline void PDM_SNPF(u32 out_len, u32 used, char *buff, int len,
char *fmt, ...)
{
RT_STATUS rt_status;
va_list args;
@@ -294,33 +344,45 @@ static __inline void PDM_SNPF(u32 out_len, u32 used, char * buff, int len, char
va_end(args);
if (rt_status != RT_STATUS_SUCCESS) {
/*DbgPrint("DM Print Fail\n");*/
/*@DbgPrint("DM Print Fail\n");*/
return;
}
DCMD_Printf(buf);
}
#endif /*#if (PHYDM_DBGPRINT == 1)*/
#else /*(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/
#endif /*@#if (PHYDM_DBGPRINT == 1)*/
#else /*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) || defined(__OSK__)
#define PHYDM_DBGPRINT 0
#define PHYDM_DBGPRINT 0
#else
#define PHYDM_DBGPRINT 1
#define PHYDM_DBGPRINT 1
#endif
#define MAX_ARGC 20
#define MAX_ARGV 16
#define DCMD_DECIMAL "%d"
#define DCMD_CHAR "%c"
#define DCMD_HEX "%x"
#define MAX_ARGC 20
#define MAX_ARGV 16
#define DCMD_DECIMAL "%d"
#define DCMD_CHAR "%c"
#define DCMD_HEX "%x"
#define PHYDM_SSCANF(x, y, z) sscanf(x, y, z)
#define PHYDM_VAST_INFO_SNPRINTF(out_len, used, buff, len, fmt, args...) \
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...) RT_PRINTK(fmt, ## args)
#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...) \
do { \
RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \
DBG_DMESG, fmt, ##args); \
RT_DEBUG(COMP_PHYDM, DBG_DMESG, fmt, ##args); \
} while (0)
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...)
#else
#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...) \
RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \
DBG_DMESG, fmt, ##args)
#endif
#if (PHYDM_DBGPRINT == 1)
#define PDM_SNPF(out_len, used, buff, len, fmt, args...) \
@@ -331,11 +393,32 @@ static __inline void PDM_SNPF(u32 out_len, u32 used, char * buff, int len, char
#else
#define PDM_SNPF(out_len, used, buff, len, fmt, args...) \
do { \
if (out_len > used) \
used += snprintf(buff, len, fmt, ##args); \
u32 *__pdm_snpf_u = &(used); \
if (out_len > *__pdm_snpf_u) \
*__pdm_snpf_u += snprintf(buff, len, fmt, ##args);\
} while (0)
#endif
#endif
/* @1 ============================================================
* 1 enumeration
* 1 ============================================================
*/
enum auto_detection_state { /*@Fast antenna training*/
AD_LEGACY_MODE = 0,
AD_HT_MODE = 1,
AD_VHT_MODE = 2
};
/*@
* ============================================================
* 1 structure
* ============================================================
*/
#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
u8 phydm_get_l_sig_rate(void *dm_void, u8 rate_idx_l_sig);
#endif
void phydm_init_debug_setting(struct dm_struct *dm);
@@ -345,16 +428,20 @@ u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port);
void phydm_release_bb_dbg_port(void *dm_void);
u32 phydm_get_bb_dbg_port_value(void *dm_void);
u32 phydm_get_bb_dbg_port_val(void *dm_void);
void phydm_reset_rx_rate_distribution(struct dm_struct *dm);
void phydm_rx_rate_distribution(void *dm_void);
void phydm_show_phy_hitogram(void *dm_void);
void phydm_get_avg_phystatus_val(void *dm_void);
void phydm_get_phy_statistic(void *dm_void);
void phydm_dm_summary(void *dm_void, u8 macid);
void phydm_basic_dbg_message(void *dm_void);
void phydm_basic_profile(void *dm_void, u32 *_used, char *output,
@@ -367,17 +454,16 @@ void phydm_cmd_parser(struct dm_struct *dm, char input[][16], u32 input_num,
u8 flag, char *output, u32 out_len);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void phydm_basic_dbg_msg_cli_win(void *dm_void, char *buf);
void phydm_sbd_check(
struct dm_struct *dm
);
struct dm_struct *dm);
void phydm_sbd_callback(
struct phydm_timer_list *timer
);
struct phydm_timer_list *timer);
void phydm_sbd_workitem_callback(
void *context
);
void *context);
#endif
void phydm_fw_trace_en_h2c(void *dm_void, boolean enable,
@@ -389,4 +475,4 @@ void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len);
void phydm_fw_trace_handler_8051(void *dm_void, u8 *cmd_buf, u8 cmd_len);
#endif /* __ODM_DBG_H__ */
#endif /* @__ODM_DBG_H__ */

2208
hal/phydm/phydm_dfs.c
View File

File diff suppressed because it is too large Load Diff

196
hal/phydm/phydm_dfs.h
View File

@@ -26,93 +26,165 @@
#ifndef __PHYDM_DFS_H__
#define __PHYDM_DFS_H__
#define DFS_VERSION "1.1"
#define DFS_VERSION "1.1"
/* ============================================================
Definition
============================================================
*/
/*@
* ============================================================
* Definition
* ============================================================
*/
/*
============================================================
1 structure
============================================================
*/
/*@
* ============================================================
* 1 structure
* ============================================================
*/
struct _DFS_STATISTICS {
u8 mask_idx;
u8 igi_cur;
u8 igi_pre;
u8 st_l2h_cur;
u16 fa_count_pre;
u16 fa_inc_hist[5];
u16 vht_crc_ok_cnt_pre;
u16 ht_crc_ok_cnt_pre;
u16 leg_crc_ok_cnt_pre;
u16 short_pulse_cnt_pre;
u16 long_pulse_cnt_pre;
u8 pwdb_th;
u8 pwdb_th_cur;
u8 pwdb_scalar_factor;
u8 peak_th;
u8 short_pulse_cnt_th;
u8 long_pulse_cnt_th;
u8 peak_window;
u8 nb2wb_th;
u8 fa_mask_th;
u8 det_flag_offset;
u8 st_l2h_max;
u8 st_l2h_min;
u8 mask_hist_checked;
u8 mask_idx;
u8 igi_cur;
u8 igi_pre;
u8 st_l2h_cur;
u16 fa_count_pre;
u16 fa_inc_hist[5];
u16 vht_crc_ok_cnt_pre;
u16 ht_crc_ok_cnt_pre;
u16 leg_crc_ok_cnt_pre;
u16 short_pulse_cnt_pre;
u16 long_pulse_cnt_pre;
u8 pwdb_th;
u8 pwdb_th_cur;
u8 pwdb_scalar_factor;
u8 peak_th;
u8 short_pulse_cnt_th;
u8 long_pulse_cnt_th;
u8 peak_window;
u8 three_peak_opt;
u8 three_peak_th2;
u8 fa_mask_th;
u8 det_flag_offset;
u8 st_l2h_max;
u8 st_l2h_min;
u8 mask_hist_checked;
boolean pulse_flag_hist[5];
boolean pulse_type_hist[5];
boolean radar_det_mask_hist[5];
boolean idle_mode;
boolean force_TP_mode;
boolean dbg_mode;
boolean sw_trigger_mode;
boolean det_print;
boolean det_print2;
boolean radar_type;
/*@dfs histogram*/
boolean print_hist_rpt;
boolean hist_cond_on;
boolean pri_cond1;
boolean pri_cond2;
boolean pri_cond3;
boolean pri_cond4;
boolean pri_cond5;
boolean pw_cond1;
boolean pw_cond2;
boolean pw_cond3;
boolean pri_type3_4_cond1; /*@for ETSI*/
boolean pri_type3_4_cond2; /*@for ETSI*/
boolean pw_long_cond1; /*@for long radar*/
boolean pw_long_cond2; /*@for long radar*/
boolean pri_long_cond1; /*@for long radar*/
boolean pw_flag;
boolean pri_flag;
boolean pri_type3_4_flag; /*@for ETSI*/
boolean long_radar_flag;
u16 pri_hold_sum[6];
u16 pw_hold_sum[6];
u16 pri_long_hold_sum[6];
u16 pw_long_hold_sum[6];
u8 hist_idx;
u8 hist_long_idx;
u8 pw_hold[4][6];
u8 pri_hold[4][6];
u8 pw_long_hold[300][6];
u8 pri_long_hold[300][6];
u16 pw_std; /*@The std(var) of reasonable num of pw group*/
u16 pri_std;/*@The std(var) of reasonable num of pri group*/
/*@dfs histogram threshold*/
u8 pri_hist_th;
u8 pri_sum_g1_th;
u8 pri_sum_g5_th;
u8 pri_sum_g1_fcc_th;
u8 pri_sum_g3_fcc_th;
u8 pri_sum_safe_fcc_th;
u8 pri_sum_type4_th;
u8 pri_sum_type6_th;
u8 pri_sum_safe_th;
u8 pri_sum_g5_under_g1_th;
u8 pri_pw_diff_th;
u8 pri_pw_diff_fcc_th;
u8 pri_pw_diff_fcc_idle_th;
u8 pri_pw_diff_w53_th;
u8 pri_type1_low_fcc_th;
u8 pri_type1_upp_fcc_th;
u8 pri_type1_cen_fcc_th;
u8 pw_g0_th;
u8 pw_long_lower_20m_th;
u8 pw_long_lower_th;
u8 pri_long_upper_th;
u8 pw_long_sum_upper_th;
u8 pw_std_th;
u8 pw_std_idle_th;
u8 pri_std_th;
u8 pri_std_idle_th;
u8 type4_pw_max_cnt;
u8 type4_safe_pri_sum_th;
};
/* ============================================================
enumeration
============================================================
*/
/*@
* ============================================================
* enumeration
* ============================================================
*/
enum phydm_dfs_region_domain {
PHYDM_DFS_DOMAIN_UNKNOWN = 0,
PHYDM_DFS_DOMAIN_FCC = 1,
PHYDM_DFS_DOMAIN_MKK = 2,
PHYDM_DFS_DOMAIN_ETSI = 3,
PHYDM_DFS_DOMAIN_UNKNOWN = 0,
PHYDM_DFS_DOMAIN_FCC = 1,
PHYDM_DFS_DOMAIN_MKK = 2,
PHYDM_DFS_DOMAIN_ETSI = 3,
};
/*
============================================================
function prototype
============================================================
*/
/*@
* ============================================================
* function prototype
* ============================================================
*/
#if defined(CONFIG_PHYDM_DFS_MASTER)
void phydm_radar_detect_reset(void *dm_void);
void phydm_radar_detect_disable(void *dm_void);
void phydm_radar_detect_enable(void *dm_void);
boolean phydm_radar_detect(void *dm_void);
void phydm_dfs_histogram_radar_distinguish(void *dm_void);
boolean phydm_dfs_hist_log(void *dm_void, u8 index);
void phydm_dfs_parameter_init(void *dm_void);
void phydm_dfs_debug(void *dm_void, u32 *const argv, u32 *_used, char *output, u32 *_out_len);
#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */
boolean
phydm_dfs_is_meteorology_channel(
void *dm_void
);
void phydm_dfs_hist_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
u8 phydm_dfs_polling_time(void *dm_void);
#endif /* @defined(CONFIG_PHYDM_DFS_MASTER) */
boolean
phydm_is_dfs_band(
void *dm_void
);
phydm_dfs_is_meteorology_channel(void *dm_void);
boolean
phydm_dfs_master_enabled(
void *dm_void
);
phydm_is_dfs_band(void *dm_void);
#endif /*#ifndef __PHYDM_DFS_H__ */
boolean
phydm_dfs_master_enabled(void *dm_void);
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
void phydm_dfs_ap_reset_radar_detect_counter_and_flag(void *dm_void);
#endif
#endif
#endif /*@#ifndef __PHYDM_DFS_H__ */

3437
hal/phydm/phydm_dig.c
View File

File diff suppressed because it is too large Load Diff

339
hal/phydm/phydm_dig.h
View File

@@ -23,64 +23,64 @@
*
*****************************************************************************/
#ifndef __PHYDMDIG_H__
#define __PHYDMDIG_H__
#ifndef __PHYDMDIG_H__
#define __PHYDMDIG_H__
/*#define DIG_VERSION "1.4"*/ /* 2017.04.18 YuChen. refine DIG code structure*/
/*#define DIG_VERSION "2.0"*/ /* 2017.05.09 Dino. Move CCKPD to new files*/
/*#define DIG_VERSION "2.1"*/ /* 2017.06.01 YuChen. Refine DFS condition*/
#define DIG_VERSION "2.2" /* 2017.06.13 YuChen. Remove MP dig*/
#define DIG_VERSION "2.3"
#define DIG_HW 0
#define DIG_HW 0
#define DIG_LIMIT_PERIOD 60 /*@60 sec*/
/*--------------------Define ---------------------------------------*/
/*@--------------------Define ---------------------------------------*/
/*=== [DIG Boundary] ========================================*/
/*DIG coverage mode*/
#define DIG_MAX_COVERAGR 0x26
#define DIG_MIN_COVERAGE 0x1c
#define DIG_MAX_OF_MIN_COVERAGE 0x22
/*DIG performance mode*/
/*@=== [DIG Boundary] ========================================*/
/*@DIG coverage mode*/
#define DIG_MAX_COVERAGR 0x26
#define DIG_MIN_COVERAGE 0x1c
#define DIG_MAX_OF_MIN_COVERAGE 0x22
/*@[DIG Balance mode]*/
#if (DIG_HW == 1)
#define DIG_MAX_BALANCE_MODE 0x32
#define DIG_MAX_BALANCE_MODE 0x32
#else
#define DIG_MAX_BALANCE_MODE 0x3e
#define DIG_MAX_BALANCE_MODE 0x3e
#endif
#define DIG_MAX_OF_MIN_BALANCE_MODE 0x2a
#define DIG_MAX_OF_MIN_BALANCE_MODE 0x2a
#define DIG_MAX_PERFORMANCE_MODE 0x5a
#define DIG_MAX_OF_MIN_PERFORMANCE_MODE 0x40 /*from 3E -> 2A, refine by YuChen 2017/04/18*/
/*@[DIG Performance mode]*/
#define DIG_MAX_PERFORMANCE_MODE 0x5a
#define DIG_MAX_OF_MIN_PERFORMANCE_MODE 0x40 /*@[WLANBB-871]*/
#define DIG_MIN_PERFORMANCE 0x20
#define DIG_MIN_PERFORMANCE 0x20
/*@DIG DFS function*/
#define DIG_MAX_DFS 0x28
#define DIG_MIN_DFS 0x20
/*DIG DFS function*/
#define DIG_MAX_DFS 0x28
#define DIG_MIN_DFS 0x20
/*@DIG LPS function*/
#define DIG_MAX_LPS 0x3e
#define DIG_MIN_LPS 0x20
/*DIG LPS function*/
#define DIG_MAX_LPS 0x3e
#define DIG_MIN_LPS 0x20
#ifdef PHYDM_TDMA_DIG_SUPPORT
#define DIG_NUM_OF_TDMA_STATES 2 /*@L, H state*/
#define DIG_TIMER_MS 250
#define ONE_SEC_MS 1000
#endif
/*=== [DIG FA Threshold] ======================================*/
/*@=== [DIG FA Threshold] ======================================*/
/*Normal*/
#define DM_DIG_FA_TH0 500
#define DM_DIG_FA_TH1 750
#define DM_DIG_FA_TH0 500
#define DM_DIG_FA_TH1 750
/*LPS*/
#define DM_DIG_FA_TH0_LPS 4 /* -> 4 lps */
#define DM_DIG_FA_TH1_LPS 15 /* -> 15 lps */
#define DM_DIG_FA_TH2_LPS 30 /* -> 30 lps */
/*@LPS*/
#define DM_DIG_FA_TH0_LPS 4 /* @-> 4 lps */
#define DM_DIG_FA_TH1_LPS 15 /* @-> 15 lps */
#define DM_DIG_FA_TH2_LPS 30 /* @-> 30 lps */
#define RSSI_OFFSET_DIG_LPS 5
#define RSSI_OFFSET_DIG_LPS 5
#define DIG_RECORD_NUM 4
/*LNA saturation check*/
#define OFDM_AGC_TAB_0 0
#define OFDM_AGC_TAB_2 2
#define DIFF_RSSI_TO_IGI 10
#define ONE_SEC_MS 1000
/*--------------------Enum-----------------------------------*/
/*@--------------------Enum-----------------------------------*/
enum dig_goupcheck_level {
DIG_GOUPCHECK_LEVEL_0,
DIG_GOUPCHECK_LEVEL_1,
@@ -89,38 +89,63 @@ enum dig_goupcheck_level {
enum phydm_dig_mode {
PHYDM_DIG_PERFORAMNCE_MODE = 0,
PHYDM_DIG_COVERAGE_MODE = 1,
PHYDM_DIG_COVERAGE_MODE = 1,
};
enum lna_sat_timer_state {
INIT_LNA_SAT_CHK_TIMMER,
CANCEL_LNA_SAT_CHK_TIMMER,
RELEASE_LNA_SAT_CHK_TIMMER
#ifdef IS_USE_NEW_TDMA
enum tdma_dig_timer {
INIT_TDMA_DIG_TIMMER,
CANCEL_TDMA_DIG_TIMMER,
RELEASE_TDMA_DIG_TIMMER
};
enum tdma_dig_state {
TDMA_DIG_LOW_STATE = 0,
TDMA_DIG_HIGH_STATE = 1,
NORMAL_DIG = 2
};
#endif
/*@--------------------Define Struct-----------------------------------*/
#ifdef CFG_DIG_DAMPING_CHK
struct phydm_dig_recorder_strcut {
u8 igi_bitmap; /*@Don't add any new parameter before this*/
u8 igi_history[DIG_RECORD_NUM];
u32 fa_history[DIG_RECORD_NUM];
u8 damping_limit_en;
u8 damping_limit_val; /*@Limit IGI_dyn_min*/
u32 limit_time;
u8 limit_rssi;
};
#endif
struct phydm_mcc_dig {
u8 mcc_rssi_A;
u8 mcc_rssi_B;
};
/*--------------------Define Struct-----------------------------------*/
struct phydm_dig_struct {
boolean is_ignore_dig; /*for old pause function*/
boolean is_dbg_fa_th;
u8 dig_mode_decision;
#ifdef CFG_DIG_DAMPING_CHK
struct phydm_dig_recorder_strcut dig_recorder_t;
u8 dig_dl_en; /*@damping limit function enable*/
#endif
boolean is_dbg_fa_th;
u8 cur_ig_value;
u8 rvrt_val;
u8 igi_backup;
u8 rx_gain_range_max; /*dig_dynamic_max*/
u8 rx_gain_range_min; /*dig_dynamic_min*/
u8 dm_dig_max; /*Absolutly upper bound*/
u8 dm_dig_min; /*Absolutly lower bound*/
u8 dig_max_of_min; /*Absolutly max of min*/
boolean is_media_connect;
u8 rx_gain_range_max; /*@dig_dynamic_max*/
u8 rx_gain_range_min; /*@dig_dynamic_min*/
u8 dm_dig_max; /*@Absolutly upper bound*/
u8 dm_dig_min; /*@Absolutly lower bound*/
u8 dig_max_of_min; /*@Absolutly max of min*/
boolean is_media_connect;
u32 ant_div_rssi_max;
u8 *is_p2p_in_process;
u8 pause_lv_bitmap; /*bit-map of pause level*/
u8 pause_dig_value[PHYDM_PAUSE_MAX_NUM];
enum dig_goupcheck_level dig_go_up_check_level;
u8 aaa_default;
u8 a0a_default;
enum dig_goupcheck_level go_up_chk_lv;
u16 fa_th[3];
#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\
RTL8198F_SUPPORT || RTL8192F_SUPPORT || RTL8195B_SUPPORT ||\
RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8721D_SUPPORT)
u8 rf_gain_idx;
u8 agc_table_idx;
u8 big_jump_lmt[16];
@@ -129,14 +154,14 @@ struct phydm_dig_struct {
u8 big_jump_step2:2;
u8 big_jump_step3:2;
#endif
u8 dig_upcheck_initial_value;
u8 dig_level0_ratio_reciprocal;
u8 dig_level1_ratio_reciprocal;
u8 upcheck_init_val;
u8 lv0_ratio_reciprocal;
u8 lv1_ratio_reciprocal;
#ifdef PHYDM_TDMA_DIG_SUPPORT
u8 cur_ig_value_tdma;
u8 low_ig_value;
u8 tdma_dig_state; /*To distinguish which state is now.(L-sate or H-state)*/
u8 tdma_dig_cnt; /*for phydm_tdma_dig_timer_check use*/
u8 tdma_dig_state; /*@To distinguish which state is now.(L-sate or H-state)*/
u8 tdma_dig_cnt; /*@for phydm_tdma_dig_timer_check use*/
u8 pre_tdma_dig_cnt;
u8 sec_factor;
u32 cur_timestamp;
@@ -144,7 +169,15 @@ struct phydm_dig_struct {
u32 fa_start_timestamp;
u32 fa_end_timestamp;
u32 fa_acc_1sec_timestamp;
#endif
#ifdef IS_USE_NEW_TDMA
u8 tdma_dig_block_cnt;/*@for 1 second dump indicator use*/
/*@dynamic upper bound for L/H state*/
u8 tdma_rx_gain_max[DIG_NUM_OF_TDMA_STATES];
/*@dynamic lower bound for L/H state*/
u8 tdma_rx_gain_min[DIG_NUM_OF_TDMA_STATES];
/*To distinguish current state(L-sate or H-state)*/
#endif
#endif
};
struct phydm_fa_struct {
@@ -155,9 +188,10 @@ struct phydm_fa_struct {
u32 cnt_mcs_fail;
u32 cnt_mcs_fail_vht;
u32 cnt_ofdm_fail;
u32 cnt_ofdm_fail_pre; /* For RTL8881A */
u32 cnt_ofdm_fail_pre; /* @For RTL8881A */
u32 cnt_cck_fail;
u32 cnt_all;
u32 cnt_all_accumulated;
u32 cnt_all_pre;
u32 cnt_fast_fsync;
u32 cnt_sb_search_fail;
@@ -179,10 +213,10 @@ struct phydm_fa_struct {
u32 cnt_crc32_error_all;
u32 cnt_crc32_ok_all;
u32 time_fa_all;
boolean cck_block_enable;
boolean ofdm_block_enable;
boolean cck_block_enable;
boolean ofdm_block_enable;
u32 dbg_port0;
boolean edcca_flag;
boolean edcca_flag;
};
#ifdef PHYDM_TDMA_DIG_SUPPORT
@@ -192,7 +226,7 @@ struct phydm_fa_acc_struct {
u32 cnt_crc8_fail;
u32 cnt_mcs_fail;
u32 cnt_ofdm_fail;
u32 cnt_ofdm_fail_pre; /*For RTL8881A*/
u32 cnt_ofdm_fail_pre; /*@For RTL8881A*/
u32 cnt_cck_fail;
u32 cnt_all;
u32 cnt_all_pre;
@@ -216,148 +250,73 @@ struct phydm_fa_acc_struct {
u32 cnt_cck_fail_1sec;
};
#endif /*#ifdef PHYDM_TDMA_DIG_SUPPORT*/
#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
struct phydm_lna_sat_info_struct {
u32 sat_cnt_acc_patha;
u32 sat_cnt_acc_pathb;
u32 check_time;
boolean pre_sat_status;
boolean cur_sat_status;
struct phydm_timer_list phydm_lna_sat_chk_timer;
u32 cur_timer_check_cnt;
u32 pre_timer_check_cnt;
};
/*@--------------------Function declaration-----------------------------*/
void phydm_write_dig_reg(void *dm_void, u8 igi);
/*--------------------Function declaration-----------------------------*/
void
odm_write_dig(
void *dm_void,
u8 current_igi
);
void odm_write_dig(void *dm_void, u8 current_igi);
void
phydm_set_dig_val(
void *dm_void,
u32 *val_buf,
u8 val_len
);
u8 phydm_get_igi(void *dm_void, enum bb_path path);
void
odm_pause_dig(
void *dm_void,
enum phydm_pause_type pause_type,
enum phydm_pause_level pause_level,
u8 igi_value
);
void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len);
void
phydm_dig_init(
void *dm_void
);
void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type,
enum phydm_pause_level pause_level, u8 igi_value);
void
phydm_dig(
void *dm_void
);
void phydm_dig_init(void *dm_void);
void
phydm_dig_lps_32k(
void *dm_void
);
void phydm_dig(void *dm_void);
void
phydm_dig_by_rssi_lps(
void *dm_void
);
void phydm_dig_lps_32k(void *dm_void);
void
odm_false_alarm_counter_statistics(
void *dm_void
);
void phydm_dig_by_rssi_lps(void *dm_void);
void phydm_false_alarm_counter_statistics(void *dm_void);
#ifdef PHYDM_TDMA_DIG_SUPPORT
void
phydm_set_tdma_dig_timer(
void *dm_void
);
void phydm_set_tdma_dig_timer(void *dm_void);
void
phydm_tdma_dig_timer_check(
void *dm_void
);
void phydm_tdma_dig_timer_check(void *dm_void);
void
phydm_tdma_dig(
void *dm_void
);
void phydm_tdma_dig(void *dm_void);
void
phydm_tdma_false_alarm_counter_check(
void *dm_void
);
void phydm_tdma_false_alarm_counter_check(void *dm_void);
void
phydm_tdma_dig_add_interrupt_mask_handler(
void *dm_void
);
void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void);
void
phydm_false_alarm_counter_reset(
void *dm_void
);
void phydm_false_alarm_counter_reset(void *dm_void);
void
phydm_false_alarm_counter_acc(
void *dm_void,
boolean rssi_dump_en
);
void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en);
void
phydm_false_alarm_counter_acc_reset(
void *dm_void
);
void phydm_false_alarm_counter_acc_reset(void *dm_void);
#endif /*#ifdef PHYDM_TDMA_DIG_SUPPORT*/
#ifdef IS_USE_NEW_TDMA
void phydm_tdma_dig_timers(void *dm_void, u8 state);
void
phydm_set_ofdm_agc_tab(
void *dm_void,
u8 tab_sel
);
void phydm_tdma_dig_cbk(void *dm_void);
#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
u8
phydm_get_ofdm_agc_tab(
void *dm_void
);
void phydm_tdma_dig_workitem_callback(void *dm_void);
void
phydm_lna_sat_chk(
void *dm_void
);
void phydm_tdma_fa_cnt_chk(void *dm_void);
void
phydm_lna_sat_chk_timers(
void *dm_void,
u8 state
);
void phydm_tdma_low_dig(void *dm_void);
void
phydm_lna_sat_chk_watchdog(
void *dm_void
);
void phydm_tdma_high_dig(void *dm_void);
#endif /*#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/
void phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en,
u8 cur_tdma_dig_state);
#endif /*@#ifdef IS_USE_NEW_TDMA*/
#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
void phydm_set_ofdm_agc_tab(void *dm_void, u8 tab_sel);
void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len);
#ifdef CONFIG_MCC_DM
void phydm_mcc_igi_cal(void *dm_void);
#endif
void
phydm_dig_debug(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
#endif

352
hal/phydm/phydm_dynamic_rx_path.c
View File

@@ -1,352 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef CONFIG_DYNAMIC_RX_PATH
void
phydm_process_phy_status_for_dynamic_rx_path(
void *dm_void,
void *phy_info_void,
void *pkt_info_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table);
}
void
phydm_drp_get_statistic(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table);
struct phydm_fa_struct *false_alm_cnt = (struct phydm_fa_struct *)phydm_get_structure(dm, PHYDM_FALSEALMCNT);
odm_false_alarm_counter_statistics(dm);
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all);
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all);
}
void
phydm_dynamic_rx_path(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table);
u8 training_set_timmer_en;
u8 curr_drp_state;
u32 rx_ok_cal;
u32 RSSI = 0;
struct phydm_fa_struct *false_alm_cnt = (struct phydm_fa_struct *)phydm_get_structure(dm, PHYDM_FALSEALMCNT);
if (!(dm->support_ability & ODM_BB_DYNAMIC_RX_PATH)) {
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[Return Init] Not Support Dynamic RX PAth\n");
return;
}
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "Current drp_state = ((%d))\n", p_dm_drp_table->drp_state);
curr_drp_state = p_dm_drp_table->drp_state;
if (p_dm_drp_table->drp_state == DRP_INIT_STATE) {
phydm_drp_get_statistic(dm);
if (false_alm_cnt->cnt_crc32_ok_all > 20) { /*Signal + Interference*/
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[Stop DRP Training] cnt_crc32_ok_all = ((%d))\n", false_alm_cnt->cnt_crc32_ok_all);
p_dm_drp_table->drp_state = DRP_INIT_STATE;
training_set_timmer_en = false;
} else {/*Interference only*/
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[Start DRP Training] cnt_crc32_ok_all = ((%d))\n", false_alm_cnt->cnt_crc32_ok_all);
p_dm_drp_table->drp_state = DRP_TRAINING_STATE_0;
p_dm_drp_table->curr_rx_path = BB_PATH_AB;
training_set_timmer_en = true;
}
} else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_0) {
phydm_drp_get_statistic(dm);
p_dm_drp_table->curr_cca_all_cnt_0 = false_alm_cnt->cnt_cca_all;
p_dm_drp_table->curr_fa_all_cnt_0 = false_alm_cnt->cnt_all;
p_dm_drp_table->drp_state = DRP_TRAINING_STATE_1;
p_dm_drp_table->curr_rx_path = BB_PATH_B;
training_set_timmer_en = true;
} else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_1) {
phydm_drp_get_statistic(dm);
p_dm_drp_table->curr_cca_all_cnt_1 = false_alm_cnt->cnt_cca_all;
p_dm_drp_table->curr_fa_all_cnt_1 = false_alm_cnt->cnt_all;
#if 1
p_dm_drp_table->drp_state = DRP_DECISION_STATE;
#else
if (*(dm->mp_mode)) {
rx_ok_cal = dm->phy_dbg_info.num_qry_phy_status_cck + dm->phy_dbg_info.num_qry_phy_status_ofdm;
RSSI = (rx_ok_cal != 0) ? dm->rx_pwdb_ave / rx_ok_cal : 0;
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "MP RSSI = ((%d))\n", RSSI);
}
if (RSSI > p_dm_drp_table->rssi_threshold)
p_dm_drp_table->drp_state = DRP_DECISION_STATE;
else {
p_dm_drp_table->drp_state = DRP_TRAINING_STATE_2;
p_dm_drp_table->curr_rx_path = BB_PATH_A;
training_set_timmer_en = true;
}
#endif
} else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_2) {
phydm_drp_get_statistic(dm);
p_dm_drp_table->curr_cca_all_cnt_2 = false_alm_cnt->cnt_cca_all;
p_dm_drp_table->curr_fa_all_cnt_2 = false_alm_cnt->cnt_all;
p_dm_drp_table->drp_state = DRP_DECISION_STATE;
}
if (p_dm_drp_table->drp_state == DRP_DECISION_STATE) {
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "Current drp_state = ((%d))\n", p_dm_drp_table->drp_state);
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[0] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_0, p_dm_drp_table->curr_fa_all_cnt_0);
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[1] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_1, p_dm_drp_table->curr_fa_all_cnt_1);
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[2] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_2, p_dm_drp_table->curr_fa_all_cnt_2);
if (p_dm_drp_table->curr_fa_all_cnt_1 < p_dm_drp_table->curr_fa_all_cnt_0) {
if ((p_dm_drp_table->curr_fa_all_cnt_0 - p_dm_drp_table->curr_fa_all_cnt_1) > p_dm_drp_table->fa_diff_threshold)
p_dm_drp_table->curr_rx_path = BB_PATH_B;
else
p_dm_drp_table->curr_rx_path = BB_PATH_AB;
} else
p_dm_drp_table->curr_rx_path = BB_PATH_AB;
phydm_config_ofdm_rx_path(dm, p_dm_drp_table->curr_rx_path);
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[Training Result] curr_rx_path = ((%s%s)),\n",
((p_dm_drp_table->curr_rx_path & BB_PATH_A) ? "A" : " "), ((p_dm_drp_table->curr_rx_path & BB_PATH_B) ? "B" : " "));
p_dm_drp_table->drp_state = DRP_INIT_STATE;
training_set_timmer_en = false;
}
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "DRP_state: ((%d)) -> ((%d))\n", curr_drp_state, p_dm_drp_table->drp_state);
if (training_set_timmer_en) {
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[Training en] curr_rx_path = ((%s%s)), training_time = ((%d ms))\n",
((p_dm_drp_table->curr_rx_path & BB_PATH_A) ? "A" : " "), ((p_dm_drp_table->curr_rx_path & BB_PATH_B) ? "B" : " "), p_dm_drp_table->training_time);
phydm_config_ofdm_rx_path(dm, p_dm_drp_table->curr_rx_path);
odm_set_timer(dm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer), p_dm_drp_table->training_time); /*ms*/
} else
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "DRP period end\n\n", curr_drp_state, p_dm_drp_table->drp_state);
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void
phydm_dynamic_rx_path_callback(
struct phydm_timer_list *timer
)
{
void *adapter = (void *)timer->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &(hal_data->DM_OutSrc);
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table);
#if DEV_BUS_TYPE == RT_PCI_INTERFACE
#if USE_WORKITEM
odm_schedule_work_item(&(p_dm_drp_table->phydm_dynamic_rx_path_workitem));
#else
{
/* dbg_print("phydm_dynamic_rx_path\n"); */
phydm_dynamic_rx_path(dm);
}
#endif
#else
odm_schedule_work_item(&(p_dm_drp_table->phydm_dynamic_rx_path_workitem));
#endif
}
void
phydm_dynamic_rx_path_workitem_callback(
void *context
)
{
void *adapter = (void *)context;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
struct dm_struct *dm = &(hal_data->DM_OutSrc);
/* dbg_print("phydm_dynamic_rx_path\n"); */
phydm_dynamic_rx_path(dm);
}
#else if (DM_ODM_SUPPORT_TYPE == ODM_CE)
void
phydm_dynamic_rx_path_callback(
void *function_context
)
{
struct dm_struct *dm = (struct dm_struct *)function_context;
void *padapter = dm->adapter;
if (*(dm->is_net_closed) == true)
return;
#if 0 /* Can't do I/O in timer callback*/
odm_s0s1_sw_ant_div(dm, SWAW_STEP_DETERMINE);
#else
/*rtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback, padapter);*/
#endif
}
#endif
void
phydm_dynamic_rx_path_timers(
void *dm_void,
u8 state
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table);
if (state == INIT_DRP_TIMMER) {
odm_initialize_timer(dm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer),
(void *)phydm_dynamic_rx_path_callback, NULL, "phydm_sw_antenna_switch_timer");
} else if (state == CANCEL_DRP_TIMMER)
odm_cancel_timer(dm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer));
else if (state == RELEASE_DRP_TIMMER)
odm_release_timer(dm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer));
}
void
phydm_dynamic_rx_path_init(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table);
boolean ret_value;
if (!(dm->support_ability & ODM_BB_DYNAMIC_RX_PATH)) {
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "[Return] Not Support Dynamic RX PAth\n");
return;
}
PHYDM_DBG(dm, DBG_DYN_RX_PATH, "phydm_dynamic_rx_path_init\n");
p_dm_drp_table->drp_state = DRP_INIT_STATE;
p_dm_drp_table->rssi_threshold = DRP_RSSI_TH;
p_dm_drp_table->fa_count_thresold = 50;
p_dm_drp_table->fa_diff_threshold = 50;
p_dm_drp_table->training_time = 100; /*ms*/
p_dm_drp_table->drp_skip_counter = 0;
p_dm_drp_table->drp_period = 0;
p_dm_drp_table->drp_init_finished = true;
ret_value = phydm_api_trx_mode(dm, (enum bb_path)BB_PATH_AB, (enum bb_path)BB_PATH_AB, true);
}
void
phydm_drp_debug(
void *dm_void,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table);
switch (dm_value[0]) {
case DRP_TRAINING_TIME:
p_dm_drp_table->training_time = (u16)dm_value[1];
break;
case DRP_TRAINING_PERIOD:
p_dm_drp_table->drp_period = (u8)dm_value[1];
break;
case DRP_RSSI_THRESHOLD:
p_dm_drp_table->rssi_threshold = (u8)dm_value[1];
break;
case DRP_FA_THRESHOLD:
p_dm_drp_table->fa_count_thresold = dm_value[1];
break;
case DRP_FA_DIFF_THRESHOLD:
p_dm_drp_table->fa_diff_threshold = dm_value[1];
break;
default:
PDM_SNPF(out_len, used, output + used, out_len - used,
"[DRP] unknown command\n");
break;
}
*_used = used;
*_out_len = out_len;
}
void
phydm_dynamic_rx_path_caller(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(dm->dm_drp_table);
if (p_dm_drp_table->drp_skip_counter < p_dm_drp_table->drp_period)
p_dm_drp_table->drp_skip_counter++;
else
p_dm_drp_table->drp_skip_counter = 0;
if (p_dm_drp_table->drp_skip_counter != 0)
return;
if (p_dm_drp_table->drp_init_finished != true)
return;
phydm_dynamic_rx_path(dm);
}
#endif

151
hal/phydm/phydm_dynamic_rx_path.h
View File

@@ -1,151 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMDYMICRXPATH_H__
#define __PHYDMDYMICRXPATH_H__
#define DYNAMIC_RX_PATH_VERSION "1.0" /*2016.07.15 Dino */
#define DRP_RSSI_TH 35
#define INIT_DRP_TIMMER 0
#define CANCEL_DRP_TIMMER 1
#define RELEASE_DRP_TIMMER 2
#if (RTL8822B_SUPPORT == 1)
struct drp_rtl8822b_struct {
enum bb_path path_judge;
u16 path_a_cck_fa;
u16 path_b_cck_fa;
};
#endif
#ifdef CONFIG_DYNAMIC_RX_PATH
enum drp_state {
DRP_INIT_STATE = 0,
DRP_TRAINING_STATE_0 = 1,
DRP_TRAINING_STATE_1 = 2,
DRP_TRAINING_STATE_2 = 3,
DRP_DECISION_STATE = 4
};
enum adjustable_value {
DRP_TRAINING_TIME = 0,
DRP_TRAINING_PERIOD = 1,
DRP_RSSI_THRESHOLD = 2,
DRP_FA_THRESHOLD = 3,
DRP_FA_DIFF_THRESHOLD = 4
};
struct _DYNAMIC_RX_PATH_ {
u8 curr_rx_path;
u8 drp_state;
u16 training_time;
u8 rssi_threshold;
u32 fa_count_thresold;
u32 fa_diff_threshold;
u32 curr_cca_all_cnt_0;
u32 curr_fa_all_cnt_0;
u32 curr_cca_all_cnt_1;
u32 curr_fa_all_cnt_1;
u32 curr_cca_all_cnt_2;
u32 curr_fa_all_cnt_2;
u8 drp_skip_counter;
u8 drp_period;
u8 drp_init_finished;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if USE_WORKITEM
RT_WORK_ITEM phydm_dynamic_rx_path_workitem;
#endif
#endif
struct phydm_timer_list phydm_dynamic_rx_path_timer;
};
void
phydm_process_phy_status_for_dynamic_rx_path(
void *dm_void,
void *phy_info_void,
void *pkt_info_void
);
void
phydm_dynamic_rx_path(
void *dm_void
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void
phydm_dynamic_rx_path_callback(
struct phydm_timer_list *timer
);
void
phydm_dynamic_rx_path_workitem_callback(
void *context
);
#else if (DM_ODM_SUPPORT_TYPE == ODM_CE)
void
phydm_dynamic_rx_path_callback(
void *function_context
);
#endif
void
phydm_dynamic_rx_path_timers(
void *dm_void,
u8 state
);
void
phydm_dynamic_rx_path_init(
void *dm_void
);
void
phydm_drp_debug(
void *dm_void,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
);
void
phydm_dynamic_rx_path_caller(
void *dm_void
);
#endif
#endif

923
hal/phydm/phydm_dynamictxpower.c
View File

File diff suppressed because it is too large Load Diff

135
hal/phydm/phydm_dynamictxpower.h
View File

@@ -23,112 +23,81 @@
*
*****************************************************************************/
#ifndef __PHYDMDYNAMICTXPOWER_H__
#define __PHYDMDYNAMICTXPOWER_H__
#ifndef __PHYDMDYNAMICTXPOWER_H__
#define __PHYDMDYNAMICTXPOWER_H__
/*#define DYNAMIC_TXPWR_VERSION "1.0"*/
/*#define DYNAMIC_TXPWR_VERSION "1.3" */ /*2015.08.26, Add 8814 Dynamic TX power*/
#define DYNAMIC_TXPWR_VERSION "1.4" /*2015.11.06, Add CE 8821A Dynamic TX power*/
#ifdef CONFIG_DYNAMIC_TX_TWR
/* @============================================================
* Definition
* ============================================================
*/
/*@#define DYNAMIC_TXPWR_VERSION "1.0"*/
/*@#define DYNAMIC_TXPWR_VERSION "1.3" */ /*@2015.08.26, Add 8814 Dynamic TX power*/
#define DYNAMIC_TXPWR_VERSION "1.4" /*@2015.11.06, Add CE 8821A Dynamic TX power*/
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
#endif
#define tx_high_pwr_level_normal 0
#define tx_high_pwr_level_level1 1
#define tx_high_pwr_level_level2 2
#define tx_high_pwr_level_bt1 3
#define tx_high_pwr_level_bt2 4
#define tx_high_pwr_level_15 5
#define tx_high_pwr_level_35 6
#define tx_high_pwr_level_50 7
#define tx_high_pwr_level_70 8
#define tx_high_pwr_level_100 9
#define tx_high_pwr_level_normal 0
#define tx_high_pwr_level_level1 1
#define tx_high_pwr_level_level2 2
#define tx_high_pwr_level_level3 3
#define tx_high_pwr_level_unchange 4
/* @============================================================
* enumrate
* ============================================================
*/
enum phydm_dtp_power_offset {
PHYDM_OFFSET_ZERO = 0,
PHYDM_OFFSET_MINUS_3DB = 1,
PHYDM_OFFSET_MINUS_3DB = 1,
PHYDM_OFFSET_MINUS_7DB = 2,
PHYDM_OFFSET_MINUS_11DB = 3,
PHYDM_OFFSET_ADD_3DB = 4,
PHYDM_OFFSET_ADD_6DB = 5
};
void
phydm_pow_train_init(
void *dm_void
);
enum phydm_dtp_power_offset_2ndtype {
PHYDM_2ND_OFFSET_ZERO = 0,
PHYDM_2ND_OFFSET_MINUS_3DB = 2,
PHYDM_2ND_OFFSET_MINUS_7DB = 3,
PHYDM_2ND_OFFSET_MINUS_11DB = 1
};
void
phydm_dynamic_tx_power(
void *dm_void
);
void
odm_dynamic_tx_power_restore_power_index(
void *dm_void
);
/* @============================================================
* structure
* ============================================================
*/
void
odm_dynamic_tx_power_nic(
void *dm_void
);
/* @============================================================
* Function Prototype
* ============================================================
*/
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
void
odm_dynamic_tx_power_save_power_index(
void *dm_void
);
extern void
odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 mac_id);
void
odm_dynamic_tx_power_write_power_index(
void *dm_void,
u8 value);
void phydm_dynamic_tx_power(void *dm_void);
void phydm_dynamic_tx_power_init(void *dm_void);
void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len);
void
odm_dynamic_tx_power_8821(
void *dm_void,
u8 *desc,
u8 mac_id
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void
odm_dynamic_tx_power_8814a(
void *dm_void
);
void
odm_set_tx_power_level8814(
void *adapter,
u8 channel,
u8 pwr_lvl
);
#endif
void odm_dynamic_tx_power_win(void *dm_void);
#endif
void
odm_dynamic_tx_power(
void *dm_void
);
void
phydm_dynamic_tx_power(
void *dm_void
);
void
phydm_dynamic_tx_power_init(
void *dm_void
);
#endif
#endif

42
hal/phydm/phydm_features.h
View File

@@ -23,30 +23,50 @@
*
*****************************************************************************/
#ifndef __PHYDM_FEATURES_H__
#ifndef __PHYDM_FEATURES_H__
#define __PHYDM_FEATURES_H__
#define ODM_DC_CANCELLATION_SUPPORT (ODM_RTL8188F | ODM_RTL8710B)
#define CONFIG_RUN_IN_DRV
#define ODM_DC_CANCELLATION_SUPPORT (ODM_RTL8188F | \
ODM_RTL8710B | \
ODM_RTL8192F | \
ODM_RTL8821C | \
ODM_RTL8721D)
#define ODM_RECEIVER_BLOCKING_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
#if ((RTL8814A_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
#define PHYDM_LA_MODE_SUPPORT 1
#else
#define PHYDM_LA_MODE_SUPPORT 0
#endif
/*20170103 YuChen add for FW API*/
#define PHYDM_FW_API_ENABLE_8822B 1
/*@20170103 YuChen add for FW API*/
#define PHYDM_FW_API_ENABLE_8822B 1
#define PHYDM_FW_API_FUNC_ENABLE_8822B 1
#define PHYDM_FW_API_ENABLE_8821C 1
#define PHYDM_FW_API_ENABLE_8821C 1
#define PHYDM_FW_API_FUNC_ENABLE_8821C 1
#define PHYDM_FW_API_ENABLE_8195B 1
#define PHYDM_FW_API_FUNC_ENABLE_8195B 1
#define PHYDM_FW_API_ENABLE_8198F 1
#define PHYDM_FW_API_FUNC_ENABLE_8198F 1
#define PHYDM_FW_API_ENABLE_8822C 1
#define PHYDM_FW_API_FUNC_ENABLE_8822C 1
#define PHYDM_FW_API_ENABLE_8814B 1
#define PHYDM_FW_API_FUNC_ENABLE_8814B 1
#define PHYDM_FW_API_ENABLE_8812F 1
#define PHYDM_FW_API_FUNC_ENABLE_8812F 1
#define CONFIG_POWERSAVING 0
#ifdef BEAMFORMING_SUPPORT
#if (BEAMFORMING_SUPPORT)
#define PHYDM_BEAMFORMING_SUPPORT
#endif
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "phydm_features_win.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "phydm_features_ce.h"
/*@#include "phydm_features_ce2_kernel.h"*/
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "phydm_features_ap.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
#include "phydm_features_iot.h"
#endif
#endif

115
hal/phydm/phydm_features_ap.h
View File

@@ -16,81 +16,138 @@
#ifndef __PHYDM_FEATURES_AP_H__
#define __PHYDM_FEATURES_AP_H__
#if (RTL8822B_SUPPORT == 1 || RTL8812A_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT)
#define PHYDM_LA_MODE_SUPPORT 1
#else
#define PHYDM_LA_MODE_SUPPORT 0
#endif
#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
RTL8192F_SUPPORT)
#define DYN_ANT_WEIGHTING_SUPPORT
#endif
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
#define FAHM_SUPPORT
#endif
#define NHM_SUPPORT
#define CLM_SUPPORT
#if (RTL8822B_SUPPORT == 1)
#if (RTL8822B_SUPPORT)
/*#define PHYDM_PHYSTAUS_SMP_MODE*/
#endif
#if (RTL8197F_SUPPORT == 1)
#if (RTL8197F_SUPPORT)
/*#define PHYDM_TDMA_DIG_SUPPORT*/
#endif
#if (RTL8197F_SUPPORT == 1)
#define PHYDM_LNA_SAT_CHK_SUPPORT
#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)
#define PHYDM_TDMA_DIG_SUPPORT 1
#ifdef PHYDM_TDMA_DIG_SUPPORT
#define IS_USE_NEW_TDMA /*new tdma dig test*/
#endif
#endif
#if (RTL8822B_SUPPORT == 1)
#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT ||\
RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)
#define PHYDM_LNA_SAT_CHK_SUPPORT
#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
#if (RTL8197F_SUPPORT)
/*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
#endif
#if (RTL8822B_SUPPORT)
/*#define PHYDM_LNA_SAT_CHK_TYPE2*/
#endif
#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)
#define PHYDM_LNA_SAT_CHK_TYPE1
#endif
#endif
#endif
#if (RTL8822B_SUPPORT)
/*#define PHYDM_POWER_TRAINING_SUPPORT*/
#endif
#if (RTL8822B_SUPPORT == 1)
#if (RTL8814B_SUPPORT)
/* #define PHYDM_PMAC_TX_SETTING_SUPPORT */
#endif
#if (RTL8814B_SUPPORT)
/* #define PHYDM_MP_SUPPORT */
#endif
#if (RTL8822B_SUPPORT)
#define PHYDM_TXA_CALIBRATION
#endif
#if (RTL8188E_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)
#if (RTL8188E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
#define PHYDM_PRIMARY_CCA
#endif
#if (RTL8188F_SUPPORT == 1 || RTL8710B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8192F_SUPPORT)
#define PHYDM_DC_CANCELLATION
#endif
#if (RTL8822B_SUPPORT == 1)
/*#define CONFIG_DYNAMIC_RX_PATH*/
#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
#define CONFIG_ADAPTIVE_SOML
#endif
#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
/*#define CONFIG_ADAPTIVE_SOML*/
#endif
#if (RTL8812A_SUPPORT == 1 || RTL8821A_SUPPORT == 1 || RTL8881A_SUPPORT == 1 || RTL8192E_SUPPORT == 1 || RTL8723B_SUPPORT == 1)
#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
RTL8192E_SUPPORT || RTL8723B_SUPPORT)
/*#define CONFIG_RA_FW_DBG_CODE*/
#endif
/* #define CONFIG_DYNAMIC_TX_TWR */
#define PHYDM_DIG_MODE_DECISION_SUPPORT
#if (RTL8192F_SUPPORT == 1)
/*#define CONFIG_8912F_SPUR_CALIBRATION*/
#endif
#if (RTL8822B_SUPPORT == 1)
/* #define CONFIG_8822B_SPUR_CALIBRATION */
#endif
#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
#define CONFIG_DYNAMIC_TX_TWR
#endif
/*#define CONFIG_PSD_TOOL*/
#define PHYDM_SUPPORT_CCKPD
#define RA_MASK_PHYDMLIZE_AP
/* #define CONFIG_RA_DBG_CMD*/
#define PHYDM_SUPPORT_ADAPTIVITY
/*#define CONFIG_PATH_DIVERSITY*/
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
#define CONFIG_RA_DYNAMIC_RATE_ID
/*#define CONFIG_RA_DYNAMIC_RATE_ID*/
#define CONFIG_BB_TXBF_API
/*#define ODM_CONFIG_BT_COEXIST*/
/*#define PHYDM_3RD_REFORM_RA_MASK*/
#define PHYDM_3RD_REFORM_RSSI_MONOTOR
#define PHYDM_SUPPORT_RSSI_MONITOR
#if !defined(CONFIG_DISABLE_PHYDM_DEBUG_FUNCTION)
#define CONFIG_PHYDM_DEBUG_FUNCTION
#endif
/* [ Configure Antenna Diversity ] */
#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH)
#if (RTL8188F_SUPPORT)
#ifdef CONFIG_ANTENNA_DIVERSITY
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
#endif
#endif
#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) || defined(CONFIG_RTL_8197F_ANT_SWITCH)
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
#define ODM_EVM_ENHANCE_ANTDIV
#define SKIP_EVM_ANTDIV_TRAINING_PATCH
/*----------*/
#ifdef CONFIG_NO_2G_DIVERSITY_8197F
#define CONFIG_NO_2G_DIVERSITY
#elif defined(CONFIG_2G_CGCS_RX_DIVERSITY_8197F)
#define CONFIG_2G_CGCS_RX_DIVERSITY
#elif defined(CONFIG_2G_CG_TRX_DIVERSITY_8197F)
#define CONFIG_2G_CG_TRX_DIVERSITY
#endif
#if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
#define CONFIG_NO_2G_DIVERSITY
@@ -126,6 +183,14 @@
#ifdef CONFIG_SMART_ANTENNA
/*#define CONFIG_CUMITEK_SMART_ANTENNA*/
#endif
#define CFG_DIG_DAMPING_CHK
/* --------------------------------------------------*/
#ifdef PHYDM_BEAMFORMING_SUPPORT
#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8814B_SUPPORT || RTL8812F_SUPPORT)
#define DRIVER_BEAMFORMING_VERSION2
#endif
#endif
#endif

165
hal/phydm/phydm_features_ce.h
View File

@@ -23,110 +23,191 @@
*
*****************************************************************************/
#ifndef __PHYDM_FEATURES_CE_H__
#ifndef __PHYDM_FEATURES_CE_H__
#define __PHYDM_FEATURES_CE_H__
#if (RTL8822B_SUPPORT == 1 || RTL8812A_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8822C_SUPPORT)
#define PHYDM_LA_MODE_SUPPORT 1
#else
#define PHYDM_LA_MODE_SUPPORT 0
#endif
#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
RTL8192F_SUPPORT)
#define DYN_ANT_WEIGHTING_SUPPORT
#endif
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
#define FAHM_SUPPORT
#endif
#define NHM_SUPPORT
#define CLM_SUPPORT
#if (RTL8822B_SUPPORT == 1)
/*#define PHYDM_PHYSTAUS_SMP_MODE*/
#if (RTL8822B_SUPPORT)
/*@#define PHYDM_PHYSTAUS_SMP_MODE*/
#endif
/*#define PHYDM_TDMA_DIG_SUPPORT*/
/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/
/*@#define PHYDM_TDMA_DIG_SUPPORT*/
#if (RTL8822B_SUPPORT == 1)
#if (RTL8822B_SUPPORT)
/*#define IS_USE_NEW_TDMA*/
#define PHYDM_TDMA_DIG_SUPPORT
#ifdef PHYDM_TDMA_DIG_SUPPORT
#define IS_USE_NEW_TDMA /*new tdma dig test*/
#endif
#endif
#if (RTL8814B_SUPPORT)
/*@#define PHYDM_TDMA_DIG_SUPPORT*/
#ifdef PHYDM_TDMA_DIG_SUPPORT
/*@#define IS_USE_NEW_TDMA*/ /*new tdma dig test*/
#endif
#endif
#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8814B_SUPPORT)
/*@#define PHYDM_LNA_SAT_CHK_SUPPORT*/
#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
#if (RTL8197F_SUPPORT)
/*@#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
#endif
#if (RTL8822B_SUPPORT)
/*@#define PHYDM_LNA_SAT_CHK_TYPE2*/
#endif
#if (RTL8814B_SUPPORT)
/*@#define PHYDM_LNA_SAT_CHK_TYPE1*/
#endif
#endif
#endif
#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT)
#define PHYDM_POWER_TRAINING_SUPPORT
#endif
#if (RTL8822B_SUPPORT == 1)
#if (RTL8822C_SUPPORT)
#define PHYDM_PMAC_TX_SETTING_SUPPORT
#endif
#if (RTL8822C_SUPPORT)
#define PHYDM_MP_SUPPORT
#endif
#if (RTL8822B_SUPPORT)
#define PHYDM_TXA_CALIBRATION
#endif
#if (RTL8188E_SUPPORT == 1)
#if (RTL8188E_SUPPORT)
#define PHYDM_PRIMARY_CCA
#endif
#if (RTL8188F_SUPPORT == 1 || RTL8710B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8192F_SUPPORT)
#define PHYDM_DC_CANCELLATION
#endif
#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
#define CONFIG_ADAPTIVE_SOML
#endif
#if (RTL8822B_SUPPORT == 1)
/*#define CONFIG_DYNAMIC_RX_PATH*/
#endif
#if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
#define CONFIG_RECEIVER_BLOCKING
#endif
/* #define CONFIG_DYNAMIC_TX_TWR */
#define PHYDM_SUPPORT_CCKPD
#define RA_MASK_PHYDMLIZE_CE
#if (RTL8192F_SUPPORT == 1)
/*#define CONFIG_8912F_SPUR_CALIBRATION*/
#endif
/*Antenna Diversity*/
#if (RTL8822B_SUPPORT == 1)
#define CONFIG_8822B_SPUR_CALIBRATION
#endif
#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
#define CONFIG_DYNAMIC_TX_TWR
#endif
#define PHYDM_SUPPORT_CCKPD
#define PHYDM_SUPPORT_ADAPTIVITY
/*@Antenna Diversity*/
#ifdef CONFIG_ANTENNA_DIVERSITY
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)
#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT ||\
RTL8188F_SUPPORT || RTL8821C_SUPPORT ||\
RTL8723D_SUPPORT)
#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
#endif
#if (RTL8821A_SUPPORT == 1)
/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
#if (RTL8821A_SUPPORT)
/*@#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
#endif
#if (RTL8822B_SUPPORT == 1)
/*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/
#if (RTL8822B_SUPPORT)
/*@#define CONFIG_HL_SMART_ANTENNA_TYPE2*/
#endif
#endif
#endif
/*[SmartAntenna]*/
/*#define CONFIG_SMART_ANTENNA*/
/*@[SmartAntenna]*/
/*@#define CONFIG_SMART_ANTENNA*/
#ifdef CONFIG_SMART_ANTENNA
/*#define CONFIG_CUMITEK_SMART_ANTENNA*/
/*@#define CONFIG_CUMITEK_SMART_ANTENNA*/
#endif
/* --------------------------------------------------*/
/* @--------------------------------------------------*/
#ifdef CONFIG_DFS_MASTER
#define CONFIG_PHYDM_DFS_MASTER
#endif
#if (RTL8812A_SUPPORT == 1 || RTL8821A_SUPPORT == 1 || RTL8881A_SUPPORT == 1 || RTL8192E_SUPPORT == 1 || RTL8723B_SUPPORT == 1)
/*#define CONFIG_RA_FW_DBG_CODE*/
#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
RTL8192E_SUPPORT || RTL8723B_SUPPORT)
/*@#define CONFIG_RA_FW_DBG_CODE*/
#endif
/*#define PHYDM_DIG_MODE_DECISION_SUPPORT*/
#define CONFIG_PSD_TOOL
/*#define CONFIG_RA_DBG_CMD*/
/*#define CONFIG_ANT_DETECTION*/
/*#define CONFIG_PATH_DIVERSITY*/
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
/*@#define CONFIG_ANT_DETECTION*/
/*@#define CONFIG_PATH_DIVERSITY*/
/*@#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
#define CONFIG_BB_TXBF_API
#define CONFIG_PHYDM_DEBUG_FUNCTION
#ifdef CONFIG_BT_COEXIST
#define ODM_CONFIG_BT_COEXIST
#endif
#define PHYDM_3RD_REFORM_RA_MASK
#define PHYDM_3RD_REFORM_RSSI_MONOTOR
#define PHYDM_SUPPORT_RSSI_MONITOR
/*#define PHYDM_AUTO_DEGBUG*/
/*@#define PHYDM_AUTO_DEGBUG*/
#define CFG_DIG_DAMPING_CHK
#ifdef PHYDM_BEAMFORMING_SUPPORT
#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8192E_SUPPORT ||\
RTL8814A_SUPPORT || RTL8881A_SUPPORT)
#define PHYDM_BEAMFORMING_VERSION1
#endif
#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8822C_SUPPORT || RTL8814B_SUPPORT)
#define DRIVER_BEAMFORMING_VERSION2
#endif
#endif
#if (RTL8822B_SUPPORT)
#ifdef CONFIG_MCC_MODE
#define CONFIG_MCC_DM
#endif
#endif
#if (RTL8822B_SUPPORT)
#ifdef CONFIG_DYNAMIC_BYPASS_MODE
#define CONFIG_DYNAMIC_BYPASS
#endif
#endif
#endif

84
hal/phydm/phydm_features_ce2_kernel.h Normal file
View File

@@ -0,0 +1,84 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_FEATURES_CE_H__
#define __PHYDM_FEATURES_CE_H__
#define PHYDM_LA_MODE_SUPPORT 0
#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
RTL8192F_SUPPORT)
#define DYN_ANT_WEIGHTING_SUPPORT
#endif
#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
#define FAHM_SUPPORT
#endif
#define NHM_SUPPORT
#define CLM_SUPPORT
#if (RTL8822B_SUPPORT)
#define PHYDM_TXA_CALIBRATION
#endif
#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8192F_SUPPORT)
#define PHYDM_DC_CANCELLATION
#endif
#if (RTL8192F_SUPPORT == 1)
/*#define CONFIG_8912F_SPUR_CALIBRATION*/
#endif
#if (RTL8822B_SUPPORT == 1)
/* #define CONFIG_8822B_SPUR_CALIBRATION */
#endif
#define PHYDM_SUPPORT_CCKPD
#define PHYDM_SUPPORT_ADAPTIVITY
#ifdef CONFIG_DFS_MASTER
#define CONFIG_PHYDM_DFS_MASTER
#endif
#define CONFIG_BB_TXBF_API
#define CONFIG_PHYDM_DEBUG_FUNCTION
#ifdef CONFIG_BT_COEXIST
#define ODM_CONFIG_BT_COEXIST
#endif
#define PHYDM_SUPPORT_RSSI_MONITOR
#define CFG_DIG_DAMPING_CHK
#ifdef PHYDM_BEAMFORMING_SUPPORT
#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8822C_SUPPORT || RTL8814B_SUPPORT)
#define DRIVER_BEAMFORMING_VERSION2
#endif
#endif
#endif

174
hal/phydm/phydm_features_iot.h Normal file
View File

@@ -0,0 +1,174 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_FEATURES_IOT_H__
#define __PHYDM_FEATURES_IOT_H__
#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8822C_SUPPORT || RTL8195B_SUPPORT)
#define PHYDM_LA_MODE_SUPPORT 1
#else
#define PHYDM_LA_MODE_SUPPORT 0
#endif
#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
RTL8192F_SUPPORT)
#define DYN_ANT_WEIGHTING_SUPPORT
#endif
#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
#define FAHM_SUPPORT
#endif
#define NHM_SUPPORT
#define CLM_SUPPORT
#if (RTL8822B_SUPPORT)
/*#define PHYDM_PHYSTAUS_SMP_MODE*/
#endif
/*#define PHYDM_TDMA_DIG_SUPPORT*/
#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT)
/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/
#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
#if (RTL8197F_SUPPORT)
/*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
#endif
#if (RTL8822B_SUPPORT)
/*#define PHYDM_LNA_SAT_CHK_TYPE2*/
#endif
#endif
#endif
#if (RTL8822B_SUPPORT)
#define PHYDM_POWER_TRAINING_SUPPORT
#endif
#if (RTL8822C_SUPPORT)
/* #define PHYDM_PMAC_TX_SETTING_SUPPORT */
#endif
#if (RTL8822C_SUPPORT)
/* #define PHYDM_MP_SUPPORT */
#endif
#if (RTL8822B_SUPPORT)
#define PHYDM_TXA_CALIBRATION
#endif
#if (RTL8188E_SUPPORT)
#define PHYDM_PRIMARY_CCA
#endif
#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8721D_SUPPORT)
#define PHYDM_DC_CANCELLATION
#endif
#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
#define CONFIG_ADAPTIVE_SOML
#endif
#if (RTL8822B_SUPPORT)
/*#define CONFIG_DYNAMIC_RX_PATH*/
#endif
#if (RTL8822B_SUPPORT == 1)
/* #define CONFIG_8822B_SPUR_CALIBRATION */
#endif
#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
#define CONFIG_RECEIVER_BLOCKING
#endif
#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
#define CONFIG_DYNAMIC_TX_TWR
#endif
#define PHYDM_SUPPORT_CCKPD
#define PHYDM_SUPPORT_ADAPTIVITY
/*Antenna Diversity*/
#ifdef CONFIG_ANTENNA_DIVERSITY
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT ||\
RTL8188F_SUPPORT || RTL8821C_SUPPORT)
#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
#endif
#if (RTL8821A_SUPPORT)
/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
#endif
#if (RTL8822B_SUPPORT)
/*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/
#endif
#endif
#endif
/*[SmartAntenna]*/
/*#define CONFIG_SMART_ANTENNA*/
#ifdef CONFIG_SMART_ANTENNA
/*#define CONFIG_CUMITEK_SMART_ANTENNA*/
#endif
/* --------------------------------------------------*/
#ifdef CONFIG_DFS_MASTER
#define CONFIG_PHYDM_DFS_MASTER
#endif
#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
RTL8192E_SUPPORT || RTL8723B_SUPPORT)
/*#define CONFIG_RA_FW_DBG_CODE*/
#endif
#define CONFIG_PSD_TOOL
/*#define CONFIG_RA_DBG_CMD*/
/*#define CONFIG_ANT_DETECTION*/
/*#define CONFIG_PATH_DIVERSITY*/
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
#define CONFIG_BB_TXBF_API
#define CONFIG_PHYDM_DEBUG_FUNCTION
#ifdef CONFIG_BT_COEXIST
#define ODM_CONFIG_BT_COEXIST
#endif
#define PHYDM_SUPPORT_RSSI_MONITOR
/*#define PHYDM_AUTO_DEGBUG*/
#define CFG_DIG_DAMPING_CHK
#ifdef PHYDM_BEAMFORMING_SUPPORT
#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8822C_SUPPORT || RTL8814B_SUPPORT)
#define DRIVER_BEAMFORMING_VERSION2
#endif
#endif
#endif

117
hal/phydm/phydm_features_win.h
View File

@@ -16,59 +16,112 @@
#ifndef __PHYDM_FEATURES_WIN_H__
#define __PHYDM_FEATURES_WIN_H__
#if (RTL8822B_SUPPORT == 1 || RTL8812A_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8822C_SUPPORT || RTL8814B_SUPPORT)
#define PHYDM_LA_MODE_SUPPORT 1
#else
#define PHYDM_LA_MODE_SUPPORT 0
#endif
#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
RTL8192F_SUPPORT)
#define DYN_ANT_WEIGHTING_SUPPORT
#endif
#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
#define FAHM_SUPPORT
#endif
#define NHM_SUPPORT
#define CLM_SUPPORT
#if (RTL8822B_SUPPORT == 1)
#if (RTL8822B_SUPPORT)
/*#define PHYDM_PHYSTAUS_SMP_MODE*/
#endif
/*#define PHYDM_TDMA_DIG_SUPPORT*/
/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/
#if (RTL8822B_SUPPORT == 1)
#if (RTL8814B_SUPPORT)
/*#define PHYDM_TDMA_DIG_SUPPORT*/
#ifdef PHYDM_TDMA_DIG_SUPPORT
/*#define IS_USE_NEW_TDMA*/ /*new tdma dig test*/
#endif
#endif
#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8814B_SUPPORT)
/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/
#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
#if (RTL8197F_SUPPORT)
/*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
#endif
#if (RTL8822B_SUPPORT)
/*#define PHYDM_LNA_SAT_CHK_TYPE2*/
#endif
#if (RTL8814B_SUPPORT)
/*#define PHYDM_LNA_SAT_CHK_TYPE1*/
#endif
#endif
#endif
#if (RTL8822B_SUPPORT || RTL8710B_SUPPORT || RTL8723D_SUPPORT ||\
RTL8192F_SUPPORT)
#define PHYDM_POWER_TRAINING_SUPPORT
#endif
#if (RTL8822B_SUPPORT == 1)
#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT)
#define PHYDM_PMAC_TX_SETTING_SUPPORT
#endif
#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT)
#define PHYDM_MP_SUPPORT
#endif
#if (RTL8822B_SUPPORT)
#define PHYDM_TXA_CALIBRATION
#endif
#if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
#define PHYDM_PRIMARY_CCA
#endif
#if (RTL8188F_SUPPORT == 1 || RTL8710B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8192F_SUPPORT)
#define PHYDM_DC_CANCELLATION
#endif
#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
/*#define CONFIG_ADAPTIVE_SOML*/
#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
#define CONFIG_ADAPTIVE_SOML
#endif
#if (RTL8192F_SUPPORT == 1)
#define CONFIG_8912F_SPUR_CALIBRATION
#endif
/*Antenna Diversity*/
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)
#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT || RTL8188F_SUPPORT ||\
RTL8821C_SUPPORT)
#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
#endif
#if (RTL8822B_SUPPORT)
/*#define ODM_EVM_ENHANCE_ANTDIV*/
/*#define CONFIG_2T3R_ANTENNA*/
/*#define CONFIG_2T4R_ANTENNA*/
#endif
/* --[SmtAnt]-----------------------------------------*/
#if (RTL8821A_SUPPORT == 1)
#if (RTL8821A_SUPPORT)
/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
#define CONFIG_FAT_PATCH
#endif
#if (RTL8822B_SUPPORT == 1)
#if (RTL8822B_SUPPORT)
/*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/
#endif
@@ -80,41 +133,53 @@
#endif
#if (RTL8822C_SUPPORT)
#define CONFIG_PATH_DIVERSITY
#endif
/*[SmartAntenna]*/
#define CONFIG_SMART_ANTENNA
#ifdef CONFIG_SMART_ANTENNA
/*#define CONFIG_CUMITEK_SMART_ANTENNA*/
/*#define CONFIG_CUMITEK_SMART_ANTENNA*/
#endif
/* --------------------------------------------------*/
#if (RTL8822B_SUPPORT == 1)
/*#define CONFIG_DYNAMIC_RX_PATH*/
#endif
#if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
#define CONFIG_RECEIVER_BLOCKING
#endif
#if (RTL8812A_SUPPORT == 1 || RTL8821A_SUPPORT == 1 || RTL8881A_SUPPORT == 1 || RTL8192E_SUPPORT == 1 || RTL8723B_SUPPORT == 1)
#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
RTL8192E_SUPPORT || RTL8723B_SUPPORT)
#define CONFIG_RA_FW_DBG_CODE
#endif
/* #define CONFIG_DYNAMIC_TX_TWR */
/*#define PHYDM_DIG_MODE_DECISION_SUPPORT */
/* #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR */
#define CONFIG_DYNAMIC_TX_TWR
/* #endif */
#define CONFIG_PSD_TOOL
#define PHYDM_SUPPORT_ADAPTIVITY
#define PHYDM_SUPPORT_CCKPD
#define RA_MASK_PHYDMLIZE_WIN
/*#define CONFIG_PATH_DIVERSITY*/
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
#define CONFIG_ANT_DETECTION
/*#define CONFIG_RA_DBG_CMD*/
#define CONFIG_BB_TXBF_API
#define ODM_CONFIG_BT_COEXIST
#define PHYDM_3RD_REFORM_RA_MASK
#define PHYDM_3RD_REFORM_RSSI_MONOTOR
#define CONFIG_PHYDM_DFS_MASTER
#define PHYDM_SUPPORT_RSSI_MONITOR
#define PHYDM_AUTO_DEGBUG
#define CONFIG_PHYDM_DEBUG_FUNCTION
#define CFG_DIG_DAMPING_CHK
#ifdef PHYDM_BEAMFORMING_SUPPORT
#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8192E_SUPPORT ||\
RTL8814A_SUPPORT || RTL8881A_SUPPORT)
#define PHYDM_BEAMFORMING_VERSION1
#endif
#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8822C_SUPPORT || RTL8814B_SUPPORT)
#define DRIVER_BEAMFORMING_VERSION2
#endif
#endif
#endif

818
hal/phydm/phydm_hwconfig.c
View File

File diff suppressed because it is too large Load Diff

94
hal/phydm/phydm_hwconfig.h
View File

@@ -23,81 +23,57 @@
*
*****************************************************************************/
#ifndef __HALHWOUTSRC_H__
#ifndef __HALHWOUTSRC_H__
#define __HALHWOUTSRC_H__
/*--------------------------Define -------------------------------------------*/
#define AGC_DIFF_CONFIG_MP(ic, band) (odm_read_and_config_mp_##ic##_agc_tab_diff(dm, array_mp_##ic##_agc_tab_diff_##band, \
sizeof(array_mp_##ic##_agc_tab_diff_##band)/sizeof(u32)))
#define AGC_DIFF_CONFIG_TC(ic, band) (odm_read_and_config_tc_##ic##_agc_tab_diff(dm, array_tc_##ic##_agc_tab_diff_##band, \
sizeof(array_tc_##ic##_agc_tab_diff_##band)/sizeof(u32)))
#define AGC_DIFF_CONFIG(ic, band) do {\
if (dm->is_mp_chip)\
AGC_DIFF_CONFIG_MP(ic, band);\
else\
AGC_DIFF_CONFIG_TC(ic, band);\
/*@--------------------------Define -------------------------------------------*/
#define AGC_DIFF_CONFIG_MP(ic, band) \
(odm_read_and_config_mp_##ic##_agc_tab_diff(dm, \
array_mp_##ic##_agc_tab_diff_##band, \
sizeof(array_mp_##ic##_agc_tab_diff_##band) / sizeof(u32)))
#define AGC_DIFF_CONFIG_TC(ic, band) \
(odm_read_and_config_tc_##ic##_agc_tab_diff(dm, \
array_tc_##ic##_agc_tab_diff_##band, \
sizeof(array_tc_##ic##_agc_tab_diff_##band) / sizeof(u32)))
#if defined(DM_ODM_CE_MAC80211)
#else
#define AGC_DIFF_CONFIG(ic, band) \
do { \
if (dm->is_mp_chip) \
AGC_DIFF_CONFIG_MP(ic, band); \
else \
AGC_DIFF_CONFIG_TC(ic, band); \
} while (0)
/* ************************************************************
#endif
/*@************************************************************
* structure and define
* ************************************************************ */
************************************************************/
enum hal_status
odm_config_rf_with_tx_pwr_track_header_file(
struct dm_struct *dm
);
odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm);
enum hal_status
odm_config_rf_with_header_file(
struct dm_struct *dm,
enum odm_rf_config_type config_type,
u8 e_rf_path
);
odm_config_rf_with_header_file(struct dm_struct *dm,
enum odm_rf_config_type config_type,
u8 e_rf_path);
enum hal_status
odm_config_bb_with_header_file(
struct dm_struct *dm,
enum odm_bb_config_type config_type
);
odm_config_bb_with_header_file(struct dm_struct *dm,
enum odm_bb_config_type config_type);
enum hal_status
odm_config_mac_with_header_file(
struct dm_struct *dm
);
odm_config_mac_with_header_file(struct dm_struct *dm);
u32
odm_get_hw_img_version(
struct dm_struct *dm
);
u32 odm_get_hw_img_version(struct dm_struct *dm);
u32 query_phydm_trx_capability(struct dm_struct *dm);
u32
query_phydm_trx_capability(
struct dm_struct *dm
);
u32 query_phydm_stbc_capability(struct dm_struct *dm);
u32
query_phydm_stbc_capability(
struct dm_struct *dm
);
u32 query_phydm_ldpc_capability(struct dm_struct *dm);
u32
query_phydm_ldpc_capability(
struct dm_struct *dm
);
u32 query_phydm_txbf_parameters(struct dm_struct *dm);
u32
query_phydm_txbf_parameters(
struct dm_struct *dm
);
u32 query_phydm_txbf_capability(struct dm_struct *dm);
u32
query_phydm_txbf_capability(
struct dm_struct *dm
);
#endif /*#ifndef __HALHWOUTSRC_H__*/
#endif /*@#ifndef __HALHWOUTSRC_H__*/

1076
hal/phydm/phydm_interface.c
View File

File diff suppressed because it is too large Load Diff

527
hal/phydm/phydm_interface.h
View File

@@ -23,46 +23,48 @@
*
*****************************************************************************/
#ifndef __ODM_INTERFACE_H__
#ifndef __ODM_INTERFACE_H__
#define __ODM_INTERFACE_H__
#define INTERFACE_VERSION "1.2" /*2017.05.03 YuChen add phy param offload HAL MAC API*/
#define INTERFACE_VERSION "1.2"
#define pdm_set_reg odm_set_bb_reg
#define pdm_set_reg odm_set_bb_reg
/*=========== Constant/Structure/Enum/... Define*/
/*@=========== Constant/Structure/Enum/... Define*/
enum phydm_h2c_cmd {
PHYDM_H2C_RA_MASK = 0x40,
PHYDM_H2C_TXBF = 0x41,
ODM_H2C_RSSI_REPORT = 0x42,
ODM_H2C_IQ_CALIBRATION = 0x45,
PHYDM_RA_MASK_ABOVE_3SS = 0x46,
ODM_H2C_RA_PARA_ADJUST = 0x47,
PHYDM_H2C_DYNAMIC_TX_PATH = 0x48,
PHYDM_H2C_FW_TRACE_EN = 0x49,
ODM_H2C_IQ_CALIBRATION = 0x45,
PHYDM_RA_MASK_ABOVE_3SS = 0x46,
ODM_H2C_RA_PARA_ADJUST = 0x47,
PHYDM_H2C_DYNAMIC_TX_PATH = 0x48,
PHYDM_H2C_FW_TRACE_EN = 0x49,
ODM_H2C_WIFI_CALIBRATION = 0x6d,
PHYDM_H2C_MU = 0x4a,
PHYDM_H2C_FW_GENERAL_INIT = 0x4c,
PHYDM_H2C_FW_CLM_MNTR = 0x4d,
PHYDM_H2C_MU = 0x4a,
PHYDM_H2C_FW_GENERAL_INIT = 0x4c,
PHYDM_H2C_FW_CLM_MNTR = 0x4d,
PHYDM_H2C_MCC = 0x4f,
PHYDM_H2C_RESP_TX_PATH_CTRL = 0x50,
PHYDM_H2C_RESP_TX_ANT_CTRL = 0x51,
ODM_MAX_H2CCMD
};
enum phydm_c2h_evt {
PHYDM_C2H_DBG = 0,
PHYDM_C2H_LB = 1,
PHYDM_C2H_XBF = 2,
PHYDM_C2H_TX_REPORT = 3,
PHYDM_C2H_INFO = 9,
PHYDM_C2H_BT_MP = 11,
PHYDM_C2H_RA_RPT = 12,
PHYDM_C2H_DBG = 0,
PHYDM_C2H_LB = 1,
PHYDM_C2H_XBF = 2,
PHYDM_C2H_TX_REPORT = 3,
PHYDM_C2H_INFO = 9,
PHYDM_C2H_BT_MP = 11,
PHYDM_C2H_RA_RPT = 12,
PHYDM_C2H_RA_PARA_RPT = 14,
PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15,
PHYDM_C2H_IQK_FINISH = 17, /*0x11*/
PHYDM_C2H_CLM_MONITOR = 0x2a,
PHYDM_C2H_DBG_CODE = 0xFE,
PHYDM_C2H_EXTEND = 0xFF,
PHYDM_C2H_IQK_FINISH = 17, /*@0x11*/
PHYDM_C2H_CLM_MONITOR = 0x2a,
PHYDM_C2H_DBG_CODE = 0xFE,
PHYDM_C2H_EXTEND = 0xFF,
};
enum phydm_extend_c2h_evt {
@@ -83,430 +85,243 @@ enum phydm_halmac_param {
PHYDM_HALMAC_CMD_END = 0XFF,
};
/*=========== Macro Define*/
/*@=========== Macro Define*/
#define _reg_all(_name) ODM_##_name
#define _reg_ic(_name, _ic) ODM_##_name##_ic
#define _bit_all(_name) BIT_##_name
#define _bit_ic(_name, _ic) BIT_##_name##_ic
/* _cat: implemented by Token-Pasting Operator. */
/* @_cat: implemented by Token-Pasting Operator. */
#if 0
#define _cat(_name, _ic_type, _func) \
(\
_func##_all(_name) \
)
#define _cat(_name, _ic_type, _func) \
( \
_func##_all(_name))
#endif
/*===================================
#if 0
#define ODM_REG_DIG_11N 0xC50
#define ODM_REG_DIG_11AC 0xDDD
ODM_REG(DIG,_pdm_odm)
=====================================*/
#endif
#if defined(DM_ODM_CE_MAC80211)
#define ODM_BIT(name, dm) \
((dm->support_ic_type & ODM_IC_11N_SERIES) ? \
ODM_BIT_##name##_11N : ODM_BIT_##name##_11AC)
#define ODM_REG(name, dm) \
((dm->support_ic_type & ODM_IC_11N_SERIES) ? \
ODM_REG_##name##_11N : ODM_REG_##name##_11AC)
#else
#define _reg_11N(_name) ODM_REG_##_name##_11N
#define _reg_11AC(_name) ODM_REG_##_name##_11AC
#define _bit_11N(_name) ODM_BIT_##_name##_11N
#define _bit_11AC(_name) ODM_BIT_##_name##_11AC
#ifdef __ECOS
#define _rtk_cat(_name, _ic_type, _func) \
(\
((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
_func##_11AC(_name) \
)
#define _rtk_cat(_name, _ic_type, _func) \
( \
((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
_func##_11AC(_name))
#else
#define _cat(_name, _ic_type, _func) \
(\
((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
_func##_11AC(_name) \
)
#define _cat(_name, _ic_type, _func) \
( \
((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
_func##_11AC(_name))
#endif
/*
/*@
* only sample code
*#define _cat(_name, _ic_type, _func) \
* ( \
* ((_ic_type) & ODM_RTL8188E) ? _func##_ic(_name, _8188E) : \
* _func##_ic(_name, _8195) \
*#define _cat(_name, _ic_type, _func) \
* ( \
* ((_ic_type) & ODM_RTL8188E) ? _func##_ic(_name, _8188E) :\
* _func##_ic(_name, _8195) \
* )
*/
/* _name: name of register or bit.
/* @_name: name of register or bit.
* Example: "ODM_REG(R_A_AGC_CORE1, dm)"
* gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on support_ic_type. */
* gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C",
* depends on support_ic_type.
*/
#ifdef __ECOS
#define ODM_REG(_name, _pdm_odm) _rtk_cat(_name, _pdm_odm->support_ic_type, _reg)
#define ODM_BIT(_name, _pdm_odm) _rtk_cat(_name, _pdm_odm->support_ic_type, _bit)
#define ODM_REG(_name, _pdm_odm) \
_rtk_cat(_name, _pdm_odm->support_ic_type, _reg)
#define ODM_BIT(_name, _pdm_odm) \
_rtk_cat(_name, _pdm_odm->support_ic_type, _bit)
#else
#define ODM_REG(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _reg)
#define ODM_BIT(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _bit)
#define ODM_REG(_name, _pdm_odm) \
_cat(_name, _pdm_odm->support_ic_type, _reg)
#define ODM_BIT(_name, _pdm_odm) \
_cat(_name, _pdm_odm->support_ic_type, _bit)
#endif
/*
#endif
/*@
* =========== Extern Variable ??? It should be forbidden.
* */
*/
/*
/*@
* =========== EXtern Function Prototype
* */
*/
u8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr);
u8
odm_read_1byte(
struct dm_struct *dm,
u32 reg_addr
);
u16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr);
u16
odm_read_2byte(
struct dm_struct *dm,
u32 reg_addr
);
u32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr);
u32
odm_read_4byte(
struct dm_struct *dm,
u32 reg_addr
);
void odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data);
void
odm_write_1byte(
struct dm_struct *dm,
u32 reg_addr,
u8 data
);
void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data);
void
odm_write_2byte(
struct dm_struct *dm,
u32 reg_addr,
u16 data
);
void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data);
void
odm_write_4byte(
struct dm_struct *dm,
u32 reg_addr,
u32 data
);
void odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask,
u32 data);
void
odm_set_mac_reg(
struct dm_struct *dm,
u32 reg_addr,
u32 bit_mask,
u32 data
);
u32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask);
u32
odm_get_mac_reg(
struct dm_struct *dm,
u32 reg_addr,
u32 bit_mask
);
void odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data);
void
odm_set_bb_reg(
struct dm_struct *dm,
u32 reg_addr,
u32 bit_mask,
u32 data
);
u32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask);
u32
odm_get_bb_reg(
struct dm_struct *dm,
u32 reg_addr,
u32 bit_mask
);
void odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
u32 bit_mask, u32 data);
void
odm_set_rf_reg(
struct dm_struct *dm,
u8 e_rf_path,
u32 reg_addr,
u32 bit_mask,
u32 data
);
u32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
u32 bit_mask);
u32
odm_get_rf_reg(
struct dm_struct *dm,
u8 e_rf_path,
u32 reg_addr,
u32 bit_mask
);
/*
/*@
* Memory Relative Function.
* */
void
odm_allocate_memory(
struct dm_struct *dm,
void **ptr,
u32 length
);
void
odm_free_memory(
struct dm_struct *dm,
void *ptr,
u32 length
);
*/
void odm_allocate_memory(struct dm_struct *dm, void **ptr, u32 length);
void odm_free_memory(struct dm_struct *dm, void *ptr, u32 length);
void
odm_move_memory(
struct dm_struct *dm,
void *dest,
void *src,
u32 length
);
void odm_move_memory(struct dm_struct *dm, void *dest, void *src, u32 length);
s32 odm_compare_memory(
struct dm_struct *dm,
void *buf1,
void *buf2,
u32 length
);
s32 odm_compare_memory(struct dm_struct *dm, void *buf1, void *buf2,
u32 length);
void odm_memory_set(
struct dm_struct *dm,
void *pbuf,
s8 value,
u32 length
);
void odm_memory_set(struct dm_struct *dm, void *pbuf, s8 value, u32 length);
/*
/*@
* ODM MISC-spin lock relative API.
* */
void
odm_acquire_spin_lock(
struct dm_struct *dm,
enum rt_spinlock_type type
);
*/
void odm_acquire_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type);
void
odm_release_spin_lock(
struct dm_struct *dm,
enum rt_spinlock_type type
);
void odm_release_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
/*
/*@
* ODM MISC-workitem relative API.
* */
void
odm_initialize_work_item(
struct dm_struct *dm,
PRT_WORK_ITEM p_rt_work_item,
RT_WORKITEM_CALL_BACK rt_work_item_callback,
void *context,
const char *sz_id
);
*/
void odm_initialize_work_item(
struct dm_struct *dm,
PRT_WORK_ITEM p_rt_work_item,
RT_WORKITEM_CALL_BACK rt_work_item_callback,
void *context,
const char *sz_id);
void
odm_start_work_item(
PRT_WORK_ITEM p_rt_work_item
);
void odm_start_work_item(
PRT_WORK_ITEM p_rt_work_item);
void
odm_stop_work_item(
PRT_WORK_ITEM p_rt_work_item
);
void odm_stop_work_item(
PRT_WORK_ITEM p_rt_work_item);
void
odm_free_work_item(
PRT_WORK_ITEM p_rt_work_item
);
void odm_free_work_item(
PRT_WORK_ITEM p_rt_work_item);
void
odm_schedule_work_item(
PRT_WORK_ITEM p_rt_work_item
);
void odm_schedule_work_item(
PRT_WORK_ITEM p_rt_work_item);
boolean
odm_is_work_item_scheduled(
PRT_WORK_ITEM p_rt_work_item
);
PRT_WORK_ITEM p_rt_work_item);
#endif
/*
/*@
* ODM Timer relative API.
* */
void
ODM_delay_ms(u32 ms);
*/
void ODM_delay_ms(u32 ms);
void
ODM_delay_us(u32 us);
void ODM_delay_us(u32 us);
void
ODM_sleep_ms(u32 ms);
void ODM_sleep_ms(u32 ms);
void
ODM_sleep_us(u32 us);
void ODM_sleep_us(u32 us);
void
odm_set_timer(
struct dm_struct *dm,
struct phydm_timer_list *timer,
u32 ms_delay
);
void odm_set_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
u32 ms_delay);
void
odm_initialize_timer(
struct dm_struct *dm,
struct phydm_timer_list *timer,
void *call_back_func,
void *context,
const char *sz_id
);
void odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
void *call_back_func, void *context,
const char *sz_id);
void
odm_cancel_timer(
struct dm_struct *dm,
struct phydm_timer_list *timer
);
void odm_cancel_timer(struct dm_struct *dm, struct phydm_timer_list *timer);
void
odm_release_timer(
struct dm_struct *dm,
struct phydm_timer_list *timer
);
void odm_release_timer(struct dm_struct *dm, struct phydm_timer_list *timer);
/*ODM FW relative API.*/
enum hal_status
phydm_set_reg_by_fw(
struct dm_struct *dm,
enum phydm_halmac_param config_type,
u32 offset,
u32 data,
u32 mask,
enum rf_path e_rf_path,
u32 delay_time
);
phydm_set_reg_by_fw(struct dm_struct *dm, enum phydm_halmac_param config_type,
u32 offset, u32 data, u32 mask, enum rf_path e_rf_path,
u32 delay_time);
void
odm_fill_h2c_cmd(
struct dm_struct *dm,
u8 element_id,
u32 cmd_len,
u8 *cmd_buffer
);
void odm_fill_h2c_cmd(struct dm_struct *dm, u8 element_id, u32 cmd_len,
u8 *cmd_buffer);
u8
phydm_c2H_content_parsing(
void *dm_void,
u8 c2h_cmd_id,
u8 c2h_cmd_len,
u8 *tmp_buf
);
u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len,
u8 *tmp_buf);
u64
odm_get_current_time(
struct dm_struct *dm
);
u64
odm_get_progressing_time(
struct dm_struct *dm,
u64 start_time
);
u64 odm_get_current_time(struct dm_struct *dm);
u64 odm_get_progressing_time(struct dm_struct *dm, u64 start_time);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) && !defined(DM_ODM_CE_MAC80211)
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) && \
(!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))
void
phydm_set_hw_reg_handler_interface (
struct dm_struct *dm,
u8 reg_Name,
u8 *val
);
void phydm_set_hw_reg_handler_interface(struct dm_struct *dm, u8 reg_Name,
u8 *val);
void
phydm_get_hal_def_var_handler_interface (
struct dm_struct *dm,
enum _HAL_DEF_VARIABLE e_variable,
void *value
);
void phydm_get_hal_def_var_handler_interface(struct dm_struct *dm,
enum _HAL_DEF_VARIABLE e_variable,
void *value);
#endif
void
odm_set_tx_power_index_by_rate_section (
struct dm_struct *dm,
enum rf_path path,
u8 channel,
u8 rate_section
);
void odm_set_tx_power_index_by_rate_section(struct dm_struct *dm,
enum rf_path path, u8 channel,
u8 rate_section);
u8
odm_get_tx_power_index (
struct dm_struct *dm,
enum rf_path path,
u8 tx_rate,
u8 band_width,
u8 channel
);
u8 odm_get_tx_power_index(struct dm_struct *dm, enum rf_path path, u8 tx_rate,
u8 band_width, u8 channel);
u8
odm_efuse_one_byte_read(
struct dm_struct *dm,
u16 addr,
u8 *data,
boolean b_pseu_do_test
);
u8 odm_efuse_one_byte_read(struct dm_struct *dm, u16 addr, u8 *data,
boolean b_pseu_do_test);
void
odm_efuse_logical_map_read(
struct dm_struct *dm,
u8 type,
u16 offset,
u32 *data
);
void odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset,
u32 *data);
enum hal_status
odm_iq_calibrate_by_fw(
struct dm_struct *dm,
u8 clear,
u8 segment
);
odm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment);
void
odm_cmn_info_ptr_array_hook(
struct dm_struct *dm,
enum odm_cmninfo cmn_info,
u16 index,
void *value
);
void odm_cmn_info_ptr_array_hook(struct dm_struct *dm,
enum odm_cmninfo cmn_info, u16 index,
void *value);
void
phydm_cmn_sta_info_hook(
struct dm_struct *dm,
u8 index,
struct cmn_sta_info *pcmn_sta_info
);
void phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 index,
struct cmn_sta_info *pcmn_sta_info);
void
phydm_macid2sta_idx_table(
struct dm_struct *dm,
u8 entry_idx,
struct cmn_sta_info *pcmn_sta_info
);
void phydm_macid2sta_idx_table(struct dm_struct *dm, u8 entry_idx,
struct cmn_sta_info *pcmn_sta_info);
void
phydm_add_interrupt_mask_handler(
struct dm_struct *dm,
u8 interrupt_type
);
void phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type);
void
phydm_enable_rx_related_interrupt_handler(
struct dm_struct *dm
);
void phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm);
#if 0
boolean
@@ -517,10 +332,12 @@ phydm_get_txbf_en(
);
#endif
void
phydm_iqk_wait(
struct dm_struct *dm,
u32 timeout
);
#endif /* __ODM_INTERFACE_H__ */
void phydm_iqk_wait(struct dm_struct *dm, u32 timeout);
u8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate);
void phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap);
void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *),
void *context);
u32 phydm_get_tx_rate(struct dm_struct *dm);
#endif /* @__ODM_INTERFACE_H__ */

1343
hal/phydm/phydm_lna_sat.c Normal file
View File

File diff suppressed because it is too large Load Diff

173
hal/phydm/phydm_lna_sat.h Normal file
View File

@@ -0,0 +1,173 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_LNA_SAT_H__
#define __PHYDM_LNA_SAT_H__
#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
/* @1 ============================================================
* 1 Definition
* 1 ============================================================
*/
#define LNA_SAT_VERSION "1.0"
/*@LNA saturation check*/
#define OFDM_AGC_TAB_0 0
#define OFDM_AGC_TAB_2 2
#define DIFF_RSSI_TO_IGI 10
#define ONE_SEC_MS 1000
#define LNA_CHK_PERIOD 100 /*@ms*/
#define LNA_CHK_CNT 10 /*@checks per callback*/
#define LNA_CHK_DUTY_CYCLE 5 /*@percentage*/
#define DELTA_STD 2
#define DELTA_MEAN 2
#define SNR_STATISTIC_SHIFT 8
#define SNR_RPT_MAX 256
/* @1 ============================================================
* 1 enumrate
* 1 ============================================================
*/
enum lna_sat_timer_state {
INIT_LNA_SAT_CHK_TIMMER,
CANCEL_LNA_SAT_CHK_TIMMER,
RELEASE_LNA_SAT_CHK_TIMMER
};
#ifdef PHYDM_LNA_SAT_CHK_TYPE2
enum lna_sat_chk_type2_status {
ORI_TABLE_MONITOR,
ORI_TABLE_TRAINING,
SAT_TABLE_MONITOR,
SAT_TABLE_TRAINING,
SAT_TABLE_TRY_FAIL,
ORI_TABLE_TRY_FAIL
};
#endif
enum lna_sat_type {
LNA_SAT_WITH_PEAK_DET = 1, /*type1*/
LNA_SAT_WITH_TRAIN = 2, /*type2*/
};
/* @1 ============================================================
* 1 structure
* 1 ============================================================
*/
struct phydm_lna_sat_t {
#ifdef PHYDM_LNA_SAT_CHK_TYPE1
u8 chk_cnt;
u8 chk_duty_cycle;
u32 chk_period;/*@ms*/
boolean is_disable_lna_sat_chk;
boolean dis_agc_table_swh;
#endif
#ifdef PHYDM_LNA_SAT_CHK_TYPE2
u8 force_traget_macid;
u32 snr_var_thd;
u32 delta_snr_mean;
u16 ori_table_try_fail_times;
u16 cnt_lower_snr_statistic;
u16 sat_table_monitor_times;
u16 force_change_period;
u8 is_snr_detail_en;
u8 is_force_lna_sat_table;
u8 lwr_snr_ratio_bit_shift;
u8 cnt_snr_statistic;
u16 snr_statistic_sqr[SNR_RPT_MAX];
u8 snr_statistic[SNR_RPT_MAX];
u8 is_sm_done;
u8 is_snr_done;
u32 cur_snr_var;
u8 total_bit_shift;
u8 total_cnt_snr;
u32 cur_snr_mean;
u8 cur_snr_var0;
u32 cur_lower_snr_mean;
u32 pre_snr_mean;
u32 pre_snr_var;
u32 pre_lower_snr_mean;
u8 nxt_state;
u8 pre_state;
#endif
enum lna_sat_type lna_sat_type;
u32 sat_cnt_acc_patha;
u32 sat_cnt_acc_pathb;
#ifdef PHYDM_IC_ABOVE_3SS
u32 sat_cnt_acc_pathc;
#endif
#ifdef PHYDM_IC_ABOVE_4SS
u32 sat_cnt_acc_pathd;
#endif
u32 check_time;
boolean pre_sat_status;
boolean cur_sat_status;
struct phydm_timer_list phydm_lna_sat_chk_timer;
u32 cur_timer_check_cnt;
u32 pre_timer_check_cnt;
};
/* @1 ============================================================
* 1 function prototype
* 1 ============================================================
*/
void phydm_lna_sat_chk_init(void *dm_void);
u8 phydm_get_ofdm_agc_tab(void *dm_void);
void phydm_lna_sat_chk(void *dm_void);
void phydm_lna_sat_chk_timers(void *dm_void, u8 state);
#ifdef PHYDM_LNA_SAT_CHK_TYPE1
#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
void phydm_lna_sat_chk_bb_init(void *dm_void);
void phydm_set_ofdm_agc_tab_path(void *dm_void,
u8 tab_sel, enum rf_path path);
u8 phydm_get_ofdm_agc_tab_path(void *dm_void, enum rf_path path);
#endif /*@#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)*/
#endif
#ifdef PHYDM_LNA_SAT_CHK_TYPE2
void phydm_parsing_snr(void *dm_void, void *pktinfo_void, s8 *rx_snr);
#endif
void phydm_lna_sat_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void phydm_lna_sat_chk_watchdog(void *dm_void);
void phydm_lna_sat_check_init(void *dm_void);
#endif /*@#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/
#endif

222
hal/phydm/phydm_math_lib.c
View File

@@ -22,88 +22,98 @@
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
const u16 db_invert_table[12][8] = {
{ 1, 1, 1, 2, 2, 2, 2, 3},
{ 3, 3, 4, 4, 4, 5, 6, 6},
{ 7, 8, 9, 10, 11, 13, 14, 16},
{ 18, 20, 22, 25, 28, 32, 35, 40},
{ 45, 50, 56, 63, 71, 79, 89, 100},
{ 112, 126, 141, 158, 178, 200, 224, 251},
{ 282, 316, 355, 398, 447, 501, 562, 631},
{ 708, 794, 891, 1000, 1122, 1259, 1413, 1585},
{ 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
{ 4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000},
{ 11220, 12589, 14125, 15849, 17783, 19953, 22387, 25119},
{ 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}
};
/*@************************************************************
* include files
************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
const u32 db_invert_table[12][8] = {
{10, 13, 16, 20, 25, 32, 40, 50}, /* @U(32,3) */
{64, 80, 101, 128, 160, 201, 256, 318}, /* @U(32,3) */
{401, 505, 635, 800, 1007, 1268, 1596, 2010}, /* @U(32,3) */
{316, 398, 501, 631, 794, 1000, 1259, 1585}, /* @U(32,0) */
{1995, 2512, 3162, 3981, 5012, 6310, 7943, 10000}, /* @U(32,0) */
{12589, 15849, 19953, 25119, 31623, 39811, 50119, 63098}, /* @U(32,0) */
{79433, 100000, 125893, 158489, 199526, 251189, 316228,
398107}, /* @U(32,0) */
{501187, 630957, 794328, 1000000, 1258925, 1584893, 1995262,
2511886}, /* @U(32,0) */
{3162278, 3981072, 5011872, 6309573, 7943282, 1000000, 12589254,
15848932}, /* @U(32,0) */
{19952623, 25118864, 31622777, 39810717, 50118723, 63095734,
79432823, 100000000}, /* @U(32,0) */
{125892541, 158489319, 199526232, 251188643, 316227766, 398107171,
501187234, 630957345}, /* @U(32,0) */
{794328235, 1000000000, 1258925412, 1584893192, 1995262315,
2511886432U, 3162277660U, 3981071706U} }; /* @U(32,0) */
/*Y = 10*log(X)*/
s32
odm_pwdb_conversion(
s32 X,
u32 total_bit,
u32 decimal_bit
)
s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit)
{
s32 Y, integer = 0, decimal = 0;
u32 i;
if (X == 0)
X = 1; /* log2(x), x can't be 0 */
X = 1; /* @log2(x), x can't be 0 */
for (i = (total_bit - 1); i > 0; i--) {
if (X & BIT(i)) {
integer = i;
if (i > 0)
decimal = (X & BIT(i - 1)) ? 2 : 0; /* decimal is 0.5dB*3=1.5dB~=2dB */
if (i > 0) {
/*decimal is 0.5dB*3=1.5dB~=2dB */
decimal = (X & BIT(i - 1)) ? 2 : 0;
}
break;
}
}
Y = 3 * (integer - decimal_bit) + decimal; /* 10*log(x)=3*log2(x), */
Y = 3 * (integer - decimal_bit) + decimal; /* @10*log(x)=3*log2(x), */
return Y;
}
s32
odm_sign_conversion(
s32 value,
u32 total_bit
)
s32 odm_sign_conversion(s32 value, u32 total_bit)
{
if (value & BIT(total_bit - 1))
value -= BIT(total_bit);
value -= BIT(total_bit);
return value;
}
void
phydm_seq_sorting(
void *dm_void,
u32 *value,
u32 *rank_idx,
u32 *idx_out,
u8 seq_length
)
/*threshold must form low to high*/
u16 phydm_find_intrvl(void *dm_void, u16 val, u16 *threshold, u16 th_len)
{
u8 i = 0, j = 0;
u32 tmp_a, tmp_b;
u32 tmp_idx_a, tmp_idx_b;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u16 i = 0;
u16 ret_val = 0;
u16 max_th = threshold[th_len - 1];
for (i = 0; i < seq_length; i++) {
rank_idx[i] = i;
/**/
for (i = 0; i < th_len; i++) {
if (val < threshold[i]) {
ret_val = i;
break;
} else if (val >= max_th) {
ret_val = th_len;
break;
}
}
return ret_val;
}
void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,
u8 seq_length)
{
u8 i = 0, j = 0;
u32 tmp_a, tmp_b;
u32 tmp_idx_a, tmp_idx_b;
for (i = 0; i < seq_length; i++)
rank_idx[i] = i;
for (i = 0; i < (seq_length - 1); i++) {
for (j = 0; j < (seq_length - 1 - i); j++) {
tmp_a = value[j];
@@ -122,50 +132,72 @@ phydm_seq_sorting(
}
}
for (i = 0; i < seq_length; i++) {
for (i = 0; i < seq_length; i++)
idx_out[rank_idx[i]] = i + 1;
/**/
}
}
u32
odm_convert_to_db(
u32 value)
u32 odm_convert_to_db(u64 value)
{
u8 i;
u8 j;
u32 dB;
value = value & 0xFFFF;
for (i = 0; i < 12; i++) {
if (value <= db_invert_table[i][7])
break;
if (value >= db_invert_table[11][7]) {
pr_debug("[%s] ====>\n", __func__);
return 96; /* @maximum 96 dB */
}
if (i >= 12) {
return 96; /* maximum 96 dB */
for (i = 0; i < 12; i++) {
if (i <= 2 && (value << FRAC_BITS) <= db_invert_table[i][7])
break;
else if (i > 2 && value <= db_invert_table[i][7])
break;
}
for (j = 0; j < 8; j++) {
if (value <= db_invert_table[i][j])
if (i <= 2 && (value << FRAC_BITS) <= db_invert_table[i][j])
break;
else if (i > 2 && i < 12 && value <= db_invert_table[i][j])
break;
}
if (j == 0 && i == 0)
goto end;
if (j == 0) {
if (i != 3) {
if (db_invert_table[i][0] - value >
value - db_invert_table[i - 1][7]) {
i = i - 1;
j = 7;
}
} else {
if (db_invert_table[3][0] - value >
value - db_invert_table[2][7]) {
i = 2;
j = 7;
}
}
} else {
if (db_invert_table[i][j] - value >
value - db_invert_table[i][j - 1]) {
i = i;
j = j - 1;
}
}
end:
dB = (i << 3) + j + 1;
return dB;
}
u32
odm_convert_to_linear(
u32 value)
u64 phydm_db_2_linear(u32 value)
{
u8 i;
u8 j;
u32 linear;
u64 linear;
/* 1dB~96dB */
/* @1dB~96dB */
value = value & 0xFF;
@@ -174,6 +206,44 @@ odm_convert_to_linear(
linear = db_invert_table[i][j];
if (i > 2)
linear = linear << FRAC_BITS;
return linear;
}
}
u16 phydm_show_fraction_num(u32 frac_val, u8 bit_num)
{
u8 i = 0;
u16 val = 0;
u16 base = 5000;
for (i = bit_num; i > 0; i--) {
if (frac_val & BIT(i - 1))
val += (base >> (bit_num - i));
}
return val;
}
u32 phydm_gen_bitmask(u8 mask_num)
{
u8 i = 0;
u32 bitmask = 0;
if (mask_num > 32)
return 1;
for (i = 0; i < mask_num; i++)
bitmask = (bitmask << 1) | BIT(0);
return bitmask;
}
s32 phydm_cnvrt_2_sign(u32 val, u8 bit_num)
{
if (val & BIT(bit_num - 1)) /*Sign BIT*/
val -= (1 << bit_num); /*@2's*/
return val;
}

141
hal/phydm/phydm_math_lib.h
View File

@@ -23,65 +23,92 @@
*
*****************************************************************************/
#ifndef __PHYDM_MATH_LIB_H__
#define __PHYDM_MATH_LIB_H__
#ifndef __PHYDM_MATH_LIB_H__
#define __PHYDM_MATH_LIB_H__
#define AUTO_MATH_LIB_VERSION "1.0" /* @2017.06.06*/
#define AUTO_MATH_LIB_VERSION "1.0" /* 2017.06.06*/
/* 1 ============================================================
/*@
* 1 ============================================================
* 1 Definition
* 1 ============================================================ */
/* 1 ============================================================
* 1 enumeration
* 1 ============================================================ */
/* 1 ============================================================
* 1 structure
* 1 ============================================================ */
/* 1 ============================================================
* 1 function prototype
* 1 ============================================================ */
s32
odm_pwdb_conversion(
s32 X,
u32 total_bit,
u32 decimal_bit
);
s32
odm_sign_conversion(
s32 value,
u32 total_bit
);
void
phydm_seq_sorting(
void *dm_void,
u32 *value,
u32 *rank_idx,
u32 *idx_out,
u8 seq_length
);
u32
odm_convert_to_db(
u32 value
);
u32
odm_convert_to_linear(
u32 value
);
* 1 ============================================================
*/
#define DIVIDED_2(X) ((X) >> 1)
/*@1/3 ~ 11/32*/
#if defined(DM_ODM_CE_MAC80211)
#define DIVIDED_3(X) ({ \
u32 div_3_tmp = (X); \
(((div_3_tmp) + ((div_3_tmp) << 1) + ((div_3_tmp) << 3)) >> 5); })
#else
#define DIVIDED_3(X) (((X) + ((X) << 1) + ((X) << 3)) >> 5)
#endif
#define DIVIDED_4(X) ((X) >> 2)
/*Store Ori Value*/
#if defined(DM_ODM_CE_MAC80211)
#define WEIGHTING_AVG(v1, w1, v2, w2) \
__WEIGHTING_AVG(v1, w1, v2, w2, typeof(v1), typeof(w1), typeof(v2), \
typeof(w2))
#define __WEIGHTING_AVG(v1, w1, v2, w2, t1, t2, t3, t4) ({ \
t1 __w_a_v1 = (v1); \
t2 __w_a_w1 = (w1); \
t3 __w_a_v2 = (v2); \
t4 __w_a_w2 = (w2); \
((__w_a_v1) * (__w_a_w1) + (__w_a_v2) * (__w_a_w2)) \
/ ((__w_a_w2) + (__w_a_w1)); })
#else
#define WEIGHTING_AVG(v1, w1, v2, w2) \
(((v1) * (w1) + (v2) * (w2)) / ((w2) + (w1)))
#endif
/*Store 2^ma x Value*/
#if defined(DM_ODM_CE_MAC80211)
#define MA_ACC(old, new_val, ma) ({ \
s16 __ma_acc_o = (old); \
(__ma_acc_o) - ((__ma_acc_o) >> (ma)) + (new_val); })
#define GET_MA_VAL(val, ma) ({ \
s16 __get_ma_tmp = (ma);\
((val) + (1 << ((__get_ma_tmp) - 1))) >> (__get_ma_tmp); })
#else
#define MA_ACC(old, new_val, ma) ((old) - ((old) >> (ma)) + (new_val))
#define GET_MA_VAL(val, ma) (((val) + (1 << ((ma) - 1))) >> (ma))
#endif
#define FRAC_BITS 3
/*@
* 1 ============================================================
* 1 enumeration
* 1 ============================================================
*/
/*@
* 1 ============================================================
* 1 structure
* 1 ============================================================
*/
/*@
* 1 ============================================================
* 1 function prototype
* 1 ============================================================
*/
s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit);
s32 odm_sign_conversion(s32 value, u32 total_bit);
u16 phydm_find_intrvl(void *dm_void, u16 val, u16 *threshold, u16 th_len);
void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,
u8 seq_length);
u32 odm_convert_to_db(u64 value);
u64 phydm_db_2_linear(u32 value);
u16 phydm_show_fraction_num(u32 frac_val, u8 bit_num);
u32 phydm_gen_bitmask(u8 mask_num);
s32 phydm_cnvrt_2_sign(u32 val, u8 bit_num);
#endif

348
hal/phydm/phydm_mp.c Normal file
View File

@@ -0,0 +1,348 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*@************************************************************
* include files
************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef PHYDM_MP_SUPPORT
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
u8 path)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_mp *mp = &dm->dm_mp_table;
u8 start = RF_PATH_A, end = RF_PATH_A;
switch (path) {
case RF_PATH_A:
case RF_PATH_B:
case RF_PATH_C:
case RF_PATH_D:
start = path;
end = path;
break;
case RF_PATH_AB:
start = RF_PATH_A;
end = RF_PATH_B;
break;
#if (RTL8814B_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
case RF_PATH_AC:
start = RF_PATH_A;
end = RF_PATH_C;
break;
case RF_PATH_AD:
start = RF_PATH_A;
end = RF_PATH_D;
break;
case RF_PATH_BC:
start = RF_PATH_B;
end = RF_PATH_C;
break;
case RF_PATH_BD:
start = RF_PATH_B;
end = RF_PATH_D;
break;
case RF_PATH_CD:
start = RF_PATH_C;
end = RF_PATH_D;
break;
case RF_PATH_ABC:
start = RF_PATH_A;
end = RF_PATH_C;
break;
case RF_PATH_ABD:
start = RF_PATH_A;
end = RF_PATH_D;
break;
case RF_PATH_ACD:
start = RF_PATH_A;
end = RF_PATH_D;
break;
case RF_PATH_BCD:
start = RF_PATH_B;
end = RF_PATH_D;
break;
case RF_PATH_ABCD:
start = RF_PATH_A;
end = RF_PATH_D;
break;
#endif
}
if (is_single_tone) {
mp->rf_reg0 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, 0xfffff);
#if 0
mp->rfe_sel_a_0 = odm_get_bb_reg(dm, R_0x1840, MASKDWORD);
mp->rfe_sel_b_0 = odm_get_bb_reg(dm, R_0x4140, MASKDWORD);
mp->rfe_sel_c_0 = odm_get_bb_reg(dm, R_0x5240, MASKDWORD);
mp->rfe_sel_d_0 = odm_get_bb_reg(dm, R_0x5340, MASKDWORD);
mp->rfe_sel_a_1 = odm_get_bb_reg(dm, R_0x1844, MASKDWORD);
mp->rfe_sel_b_1 = odm_get_bb_reg(dm, R_0x4144, MASKDWORD);
mp->rfe_sel_c_1 = odm_get_bb_reg(dm, R_0x5244, MASKDWORD);
mp->rfe_sel_d_1 = odm_get_bb_reg(dm, R_0x5344, MASKDWORD);
#endif
/* Disable CCK and OFDM */
odm_set_bb_reg(dm, R_0x1c3c, 0x3, 0x0);
for (start; start <= end; start++) {
/* @Tx mode: RF0x00[19:16]=4'b0010 */
odm_set_rf_reg(dm, start, RF_0x0, 0xF0000, 0x2);
/* @Lowest RF gain index: RF_0x0[4:0] = 0*/
odm_set_rf_reg(dm, start, RF_0x0, 0x1F, 0x0);
/* @RF LO enabled */
odm_set_rf_reg(dm, start, RF_0x58, BIT(1), 0x1);
}
#if (RTL8814B_SUPPORT == 1)
if (dm->support_ic_type & ODM_RTL8814B) {
/* @Tx mode: RF0x00[19:16]=4'b0010 */
config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
0xF0000, 0x2);
/* @Lowest RF gain index: RF_0x0[4:0] = 0*/
config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
0x1F, 0x0);
/* @RF LO enabled */
config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
BIT(1), 0x1);
}
#endif
} else {
/* Eable CCK and OFDM */
odm_set_bb_reg(dm, R_0x1c3c, 0x3, 0x3);
if (!(dm->support_ic_type & ODM_RTL8814B)) {
for (start; start <= end; start++) {
odm_set_rf_reg(dm, start, RF_0x00, 0xfffff,
mp->rf_reg0);
/* RF LO disabled */
odm_set_rf_reg(dm, start, RF_0x58, BIT(1),
0x0);
}
}
#if 0
odm_set_bb_reg(dm, R_0x1840, MASKDWORD, mp->rfe_sel_a_0);
odm_set_bb_reg(dm, R_0x4140, MASKDWORD, mp->rfe_sel_b_0);
odm_set_bb_reg(dm, R_0x5240, MASKDWORD, mp->rfe_sel_c_0);
odm_set_bb_reg(dm, R_0x5340, MASKDWORD, mp->rfe_sel_d_0);
odm_set_bb_reg(dm, R_0x1844, MASKDWORD, mp->rfe_sel_a_1);
odm_set_bb_reg(dm, R_0x4144, MASKDWORD, mp->rfe_sel_b_1);
odm_set_bb_reg(dm, R_0x5244, MASKDWORD, mp->rfe_sel_c_1);
odm_set_bb_reg(dm, R_0x5344, MASKDWORD, mp->rfe_sel_d_1);
#endif
}
}
void phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp,
u32 rate_index)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_mp *mp = &dm->dm_mp_table;
if (is_carrier_supp) {
if (phydm_is_cck_rate(dm, (u8)rate_index)) {
/* @if CCK block on? */
if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1);
/* @Turn Off All Test mode */
odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
/* @transmit mode */
odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2);
/* @turn off scramble setting */
odm_set_bb_reg(dm, R_0x1a00, 0x8, 0x0);
/* @Set CCK Tx Test Rate, set FTxRate to 1Mbps */
odm_set_bb_reg(dm, R_0x1a00, 0x3000, 0x0);
}
} else { /* @Stop Carrier Suppression. */
if (phydm_is_cck_rate(dm, (u8)rate_index)) {
/* @normal mode */
odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);
/* @turn on scramble setting */
odm_set_bb_reg(dm, R_0x1a00, 0x8, 0x1);
/* @BB Reset */
odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0);
odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1);
}
}
}
#endif
void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
phydm_set_crystal_cap(dm, crystal_cap);
}
void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_mp_set_single_tone_jgr3(dm, is_single_tone, path);
}
void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,
u32 rate_index)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_mp_set_carrier_supp_jgr3(dm, is_carrier_supp, rate_index);
}
void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_mp *mp = &dm->dm_mp_table;
if (is_single_carrier) {
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
/* @1. if OFDM block on? */
if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1);
/* @2. set CCK test mode off, set to CCK normal mode */
odm_set_bb_reg(dm, R_0x1a00, 0x3, 0);
/* @3. turn on scramble setting */
odm_set_bb_reg(dm, R_0x1a00, 0x8, 1);
/* @4. Turn On single carrier. */
odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
} else {
/* @1. if OFDM block on? */
if (!odm_get_bb_reg(dm, R_0x800, 0x2000000))
odm_set_bb_reg(dm, R_0x800, 0x2000000, 1);
/* @2. set CCK test mode off, set to CCK normal mode */
odm_set_bb_reg(dm, R_0xa00, 0x3, 0);
/* @3. turn on scramble setting */
odm_set_bb_reg(dm, R_0xa00, 0x8, 1);
/* @4. Turn On single carrier. */
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
odm_set_bb_reg(dm, R_0x914, 0x70000,
OFDM_SINGLE_CARRIER);
else if (dm->support_ic_type & ODM_IC_11N_SERIES)
odm_set_bb_reg(dm, R_0xd00, 0x70000000,
OFDM_SINGLE_CARRIER);
}
} else { /* @Stop Single Carrier. */
/* @Turn off all test modes. */
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_OFF);
else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
odm_set_bb_reg(dm, R_0x914, 0x70000, OFDM_OFF);
else if (dm->support_ic_type & ODM_IC_11N_SERIES)
odm_set_bb_reg(dm, R_0xd00, 0x70000000, OFDM_OFF);
/* @Delay 10 ms */
ODM_delay_ms(10);
/* @BB Reset */
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0);
odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1);
} else {
odm_set_bb_reg(dm, R_0x100, 0x100, 0x0);
odm_set_bb_reg(dm, R_0x100, 0x100, 0x1);
}
}
}
void phydm_mp_reset_rx_counters_phy(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
phydm_reset_bb_hw_cnt(dm);
}
void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_mp *mp = &dm->dm_mp_table;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
if (phydm_is_cck_rate(dm, (u8)rate_index))
mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de4,
0xffff);
else
mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de0,
0xffff);
} else {
if (phydm_is_cck_rate(dm, (u8)rate_index))
mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0xf50,
0xffff);
else
mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0xf50,
0xffff0000);
}
}
void phydm_mp_get_rx_ok(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_mp *mp = &dm->dm_mp_table;
u32 cck_ok = 0, ofdm_ok = 0, ht_ok = 0, vht_ok = 0;
u32 cck_err = 0, ofdm_err = 0, ht_err = 0, vht_err = 0;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
cck_ok = odm_get_bb_reg(dm, R_0x2c04, 0xffff);
ofdm_ok = odm_get_bb_reg(dm, R_0x2c14, 0xffff);
ht_ok = odm_get_bb_reg(dm, R_0x2c10, 0xffff);
vht_ok = odm_get_bb_reg(dm, R_0x2c0c, 0xffff);
cck_err = odm_get_bb_reg(dm, R_0x2c04, 0xffff0000);
ofdm_err = odm_get_bb_reg(dm, R_0x2c14, 0xffff0000);
ht_err = odm_get_bb_reg(dm, R_0x2c10, 0xffff0000);
vht_err = odm_get_bb_reg(dm, R_0x2c0c, 0xffff0000);
} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
cck_ok = odm_get_bb_reg(dm, R_0xf04, 0x3FFF);
ofdm_ok = odm_get_bb_reg(dm, R_0xf14, 0x3FFF);
ht_ok = odm_get_bb_reg(dm, R_0xf10, 0x3FFF);
vht_ok = odm_get_bb_reg(dm, R_0xf0c, 0x3FFF);
cck_err = odm_get_bb_reg(dm, R_0xf04, 0x3FFF0000);
ofdm_err = odm_get_bb_reg(dm, R_0xf14, 0x3FFF0000);
ht_err = odm_get_bb_reg(dm, R_0xf10, 0x3FFF0000);
vht_err = odm_get_bb_reg(dm, R_0xf0c, 0x3FFF0000);
} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
cck_ok = odm_get_bb_reg(dm, R_0xf88, MASKDWORD);
ofdm_ok = odm_get_bb_reg(dm, R_0xf94, 0xffff);
ht_ok = odm_get_bb_reg(dm, R_0xf90, 0xffff);
cck_err = odm_get_bb_reg(dm, R_0xf84, MASKDWORD);
ofdm_err = odm_get_bb_reg(dm, R_0xf94, 0xffff0000);
ht_err = odm_get_bb_reg(dm, R_0xf90, 0xffff0000);
}
mp->rx_phy_ok_cnt = cck_ok + ofdm_ok + ht_ok + vht_ok;
mp->rx_phy_crc_err_cnt = cck_err + ofdm_err + ht_err + vht_err;
mp->io_value = (u32)mp->rx_phy_ok_cnt;
}
#endif

94
hal/phydm/phydm_mp.h Normal file
View File

@@ -0,0 +1,94 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_MP_H__
#define __PHYDM_MP_H__
#define MP_VERSION "1.0"
/* @1 ============================================================
* 1 Definition
* 1 ============================================================
*/
/* @1 ============================================================
* 1 structure
* 1 ============================================================
*/
struct phydm_mp {
/* @Rx OK count, statistics used in Mass Production Test.*/
u64 tx_phy_ok_cnt;
u64 rx_phy_ok_cnt;
/* @Rx CRC32 error count, statistics used in Mass Production Test.*/
u64 rx_phy_crc_err_cnt;
/* @The Value of IO operation is depend of MptActType.*/
u32 io_value;
u32 rf_reg0;
/* @u32 rfe_sel_a_0;*/
/* @u32 rfe_sel_b_0;*/
/* @u32 rfe_sel_c_0;*/
/* @u32 rfe_sel_d_0;*/
/* @u32 rfe_sel_a_1;*/
/* @u32 rfe_sel_b_1;*/
/* @u32 rfe_sel_c_1;*/
/* @u32 rfe_sel_d_1;*/
};
/* @1 ============================================================
* 1 enumeration
* 1 ============================================================
*/
enum TX_MODE_OFDM {
OFDM_OFF = 0,
OFDM_CONT_TX = 1,
OFDM_SINGLE_CARRIER = 2,
OFDM_SINGLE_TONE = 4,
};
/* @1 ============================================================
* 1 function prototype
* 1 ============================================================
*/
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
u8 path);
void phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp,
u32 rate_index);
#endif
void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap);
void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path);
void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,
u32 rate_index);
void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier);
void phydm_mp_reset_rx_counters_phy(void *dm_void);
void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index);
void phydm_mp_get_rx_ok(void *dm_void);
#endif

358
hal/phydm/phydm_noisemonitor.c
View File

@@ -23,13 +23,13 @@
*
*****************************************************************************/
/* ************************************************************
/*************************************************************
* include files
* ************************************************************ */
************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
/* *************************************************
/**************************************************
* This function is for inband noise test utility only
* To obtain the inband noise level(dbm), do the following.
* 1. disable DIG and Power Saving
@@ -37,45 +37,47 @@
* 3. Stop updating idle time pwer report (for driver read)
* - 0x80c[25]
*
* ************************************************* */
#define VALID_CNT 5
*************************************************/
void phydm_set_noise_data_sum(struct noise_level *noise_data, u8 max_rf_path)
{
u8 rf_path;
u8 i = 0;
for (rf_path = RF_PATH_A; rf_path < max_rf_path; rf_path++) {
if (noise_data->valid_cnt[rf_path])
noise_data->sum[rf_path] /= noise_data->valid_cnt[rf_path];
for (i = RF_PATH_A; i < max_rf_path; i++) {
if (noise_data->valid_cnt[i])
noise_data->sum[i] /= noise_data->valid_cnt[i];
else
noise_data->sum[rf_path] = 0;
noise_data->sum[i] = 0;
}
}
s16 odm_inband_noise_monitor_n_series(struct dm_struct *dm, u8 is_pause_dig, u8 igi_value, u32 max_time)
#if (ODM_IC_11N_SERIES_SUPPORT)
s16 odm_inband_noise_monitor_n(struct dm_struct *dm, u8 is_pause_dig, u8 igi,
u32 max_time)
{
u32 tmp4b;
u8 max_rf_path = 0, rf_path;
u8 reg_c50, reg_c58, valid_done = 0;
struct noise_level noise_data;
u64 start = 0, func_start = 0, func_end = 0;
u32 tmp4b;
u8 max_rf_path = 0, i = 0;
u8 reg_c50, reg_c58, valid_done = 0;
struct noise_level noise_data;
u64 start = 0, func_start = 0, func_end = 0;
s8 val_s8 = 0;
func_start = odm_get_current_time(dm);
dm->noise_level.noise_all = 0;
if ((dm->rf_type == RF_1T2R) || (dm->rf_type == RF_2T2R))
if (dm->rf_type == RF_1T2R || dm->rf_type == RF_2T2R)
max_rf_path = 2;
else
max_rf_path = 1;
PHYDM_DBG(dm, DBG_ENV_MNTR, "odm_DebugControlInbandNoise_Nseries() ==>\n");
PHYDM_DBG(dm, DBG_ENV_MNTR,
"odm_DebugControlInbandNoise_Nseries() ==>\n");
odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));
/* step 1. Disable DIG && Set initial gain. */
if (is_pause_dig)
odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value);
odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);
/* step 3. Get noise power level */
start = odm_get_current_time(dm);
@@ -84,7 +86,7 @@ s16 odm_inband_noise_monitor_n_series(struct dm_struct *dm, u8 is_pause_dig, u8
odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1);
/* Read Noise Floor Report */
tmp4b = odm_get_bb_reg(dm, 0x8f8, MASKDWORD);
tmp4b = odm_get_bb_reg(dm, R_0x8f8, MASKDWORD);
/* update idle time pwer report per 5us */
odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0);
@@ -92,172 +94,179 @@ s16 odm_inband_noise_monitor_n_series(struct dm_struct *dm, u8 is_pause_dig, u8
ODM_delay_us(5);
noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff);
noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
for (rf_path = RF_PATH_A; rf_path < max_rf_path; rf_path++) {
noise_data.sval[rf_path] = (s8)noise_data.value[rf_path];
noise_data.sval[rf_path] /= 2;
for (i = RF_PATH_A; i < max_rf_path; i++) {
noise_data.sval[i] = (s8)noise_data.value[i];
noise_data.sval[i] /= 2;
}
for (rf_path = RF_PATH_A; rf_path < max_rf_path; rf_path++) {
if (noise_data.valid_cnt[rf_path] >= VALID_CNT)
for (i = RF_PATH_A; i < max_rf_path; i++) {
if (noise_data.valid_cnt[i] >= VALID_CNT)
continue;
noise_data.valid_cnt[rf_path]++;
noise_data.sum[rf_path] += noise_data.sval[rf_path];
PHYDM_DBG(dm, DBG_ENV_MNTR, "rf_path:%d Valid sval = %d\n", rf_path, noise_data.sval[rf_path]);
PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n", noise_data.sum[rf_path]);
if (noise_data.valid_cnt[rf_path] == VALID_CNT)
noise_data.valid_cnt[i]++;
noise_data.sum[i] += noise_data.sval[i];
PHYDM_DBG(dm, DBG_ENV_MNTR,
"rf_path:%d Valid sval=%d\n", i,
noise_data.sval[i]);
PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n",
noise_data.sum[i]);
if (noise_data.valid_cnt[i] == VALID_CNT)
valid_done++;
}
if ((valid_done == max_rf_path) || (odm_get_progressing_time(dm, start) > max_time)) {
if (valid_done == max_rf_path ||
(odm_get_progressing_time(dm, start) > max_time)) {
phydm_set_noise_data_sum(&noise_data, max_rf_path);
break;
}
}
reg_c50 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0);
reg_c50 &= ~BIT(7);
dm->noise_level.noise[RF_PATH_A] = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]);
val_s8 = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]);
dm->noise_level.noise[RF_PATH_A] = val_s8;
dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A];
if (max_rf_path == 2) {
reg_c58 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XB_AGC_CORE1, MASKBYTE0);
reg_c58 = (u8)odm_get_bb_reg(dm, R_0xc58, MASKBYTE0);
reg_c58 &= ~BIT(7);
dm->noise_level.noise[RF_PATH_B] = (s8)(-110 + reg_c58 + noise_data.sum[RF_PATH_B]);
val_s8 = (s8)(-110 + reg_c58 + noise_data.sum[RF_PATH_B]);
dm->noise_level.noise[RF_PATH_B] = val_s8;
dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B];
}
dm->noise_level.noise_all /= max_rf_path;
PHYDM_DBG(dm, DBG_ENV_MNTR, "noise_a = %d, noise_b = %d, noise_all = %d\n",
dm->noise_level.noise[RF_PATH_A], dm->noise_level.noise[RF_PATH_B],
dm->noise_level.noise_all);
PHYDM_DBG(dm, DBG_ENV_MNTR,
"noise_a = %d, noise_b = %d, noise_all = %d\n",
dm->noise_level.noise[RF_PATH_A],
dm->noise_level.noise[RF_PATH_B], dm->noise_level.noise_all);
/* step 4. Recover the Dig */
if (is_pause_dig)
odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value);
odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);
func_end = odm_get_progressing_time(dm, func_start);
PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n");
return dm->noise_level.noise_all;
}
#endif
s16
phydm_idle_noise_measurement_ac(
struct dm_struct *dm,
u8 is_pause_dig,
u8 igi_value,
u32 max_time
)
#if (ODM_IC_11AC_SERIES_SUPPORT)
s16 phydm_idle_noise_measure_ac(struct dm_struct *dm, u8 pause_dig,
u8 igi, u32 max_time)
{
u32 tmp4b;
u8 max_rf_path = 0, rf_path;
u8 reg_c50, reg_e50, valid_done = 0;
u64 start = 0, func_start = 0, func_end = 0;
struct noise_level noise_data;
u32 tmp4b;
u8 max_rf_path = 0, i = 0;
u8 reg_c50, reg_e50, valid_done = 0;
u64 start = 0, func_start = 0, func_end = 0;
struct noise_level noise_data;
s8 val_s8 = 0;
func_start = odm_get_current_time(dm);
dm->noise_level.noise_all = 0;
if ((dm->rf_type == RF_1T2R) || (dm->rf_type == RF_2T2R))
if (dm->rf_type == RF_1T2R || dm->rf_type == RF_2T2R)
max_rf_path = 2;
else
max_rf_path = 1;
PHYDM_DBG(dm, DBG_ENV_MNTR, "phydm_idle_noise_measurement_ac==>\n");
PHYDM_DBG(dm, DBG_ENV_MNTR, "%s==>\n", __func__);
odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));
/*Step 1. Disable DIG && Set initial gain.*/
if (is_pause_dig)
odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value);
if (pause_dig)
odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);
/*Step 2. Get noise power level*/
start = odm_get_current_time(dm);
while (1) {
/*Stop updating idle time pwer report (for driver read)*/
odm_set_bb_reg(dm, 0x9e4, BIT(30), 0x1);
odm_set_bb_reg(dm, R_0x9e4, BIT(30), 0x1);
/*Read Noise Floor Report*/
tmp4b = odm_get_bb_reg(dm, 0xff0, MASKDWORD);
tmp4b = odm_get_bb_reg(dm, R_0xff0, MASKDWORD);
/*update idle time pwer report per 5us*/
odm_set_bb_reg(dm, 0x9e4, BIT(30), 0x0);
odm_set_bb_reg(dm, R_0x9e4, BIT(30), 0x0);
ODM_delay_us(5);
noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff);
noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
for (rf_path = RF_PATH_A; rf_path < max_rf_path; rf_path++) {
noise_data.sval[rf_path] = (s8)noise_data.value[rf_path];
noise_data.sval[rf_path] = noise_data.sval[rf_path] >> 1;
for (i = RF_PATH_A; i < max_rf_path; i++) {
noise_data.sval[i] = (s8)noise_data.value[i];
noise_data.sval[i] = noise_data.sval[i] >> 1;
}
for (rf_path = RF_PATH_A; rf_path < max_rf_path; rf_path++) {
if (noise_data.valid_cnt[rf_path] >= VALID_CNT)
for (i = RF_PATH_A; i < max_rf_path; i++) {
if (noise_data.valid_cnt[i] >= VALID_CNT)
continue;
noise_data.valid_cnt[rf_path]++;
noise_data.sum[rf_path] += noise_data.sval[rf_path];
PHYDM_DBG(dm, DBG_ENV_MNTR, "Path:%d Valid sval = %d\n", rf_path, noise_data.sval[rf_path]);
PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d\n", noise_data.sum[rf_path]);
if (noise_data.valid_cnt[rf_path] == VALID_CNT)
noise_data.valid_cnt[i]++;
noise_data.sum[i] += noise_data.sval[i];
PHYDM_DBG(dm, DBG_ENV_MNTR, "Path:%d Valid sval = %d\n",
i, noise_data.sval[i]);
PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d\n",
noise_data.sum[i]);
if (noise_data.valid_cnt[i] == VALID_CNT)
valid_done++;
}
if ((valid_done == max_rf_path) || (odm_get_progressing_time(dm, start) > max_time)) {
if (valid_done == max_rf_path ||
(odm_get_progressing_time(dm, start) > max_time)) {
phydm_set_noise_data_sum(&noise_data, max_rf_path);
break;
}
}
reg_c50 = (u8)odm_get_bb_reg(dm, 0xc50, MASKBYTE0);
reg_c50 = (u8)odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
reg_c50 &= ~BIT(7);
dm->noise_level.noise[RF_PATH_A] = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]);
val_s8 = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]);
dm->noise_level.noise[RF_PATH_A] = val_s8;
dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A];
if (max_rf_path == 2) {
reg_e50 = (u8)odm_get_bb_reg(dm, 0xe50, MASKBYTE0);
reg_e50 = (u8)odm_get_bb_reg(dm, R_0xe50, MASKBYTE0);
reg_e50 &= ~BIT(7);
dm->noise_level.noise[RF_PATH_B] = (s8)(-110 + reg_e50 + noise_data.sum[RF_PATH_B]);
val_s8 = (s8)(-110 + reg_e50 + noise_data.sum[RF_PATH_B]);
dm->noise_level.noise[RF_PATH_B] = val_s8;
dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B];
}
dm->noise_level.noise_all /= max_rf_path;
PHYDM_DBG(dm, DBG_ENV_MNTR, "noise_a = %d, noise_b = %d, noise_all = %d\n",
dm->noise_level.noise[RF_PATH_A], dm->noise_level.noise[RF_PATH_B],
dm->noise_level.noise_all);
PHYDM_DBG(dm, DBG_ENV_MNTR,
"noise_a = %d, noise_b = %d, noise_all = %d\n",
dm->noise_level.noise[RF_PATH_A],
dm->noise_level.noise[RF_PATH_B], dm->noise_level.noise_all);
/*Step 3. Recover the Dig*/
if (is_pause_dig)
odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value);
if (pause_dig)
odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);
func_end = odm_get_progressing_time(dm, func_start);
PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n");
return dm->noise_level.noise_all;
}
s16
odm_inband_noise_monitor_ac_series(
struct dm_struct *dm,
u8 is_pause_dig,
u8 igi_value,
u32 max_time
)
s16 odm_inband_noise_monitor_ac(struct dm_struct *dm, u8 pause_dig, u8 igi,
u32 max_time)
{
s32 rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/
s32 value32, pwdb_A = 0, sval, noise, sum = 0;
boolean pd_flag;
u8 valid_cnt = 0;
u64 start = 0, func_start = 0, func_end = 0;
s32 rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/
s32 value32, pwdb_A = 0, sval, noise, sum = 0;
boolean pd_flag;
u8 valid_cnt = 0;
u64 start = 0, func_start = 0, func_end = 0;
s32 val_s32 = 0;
s16 rpt = 0;
u8 val_u8 = 0;
if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C))
return phydm_idle_noise_measurement_ac(dm, is_pause_dig, igi_value, max_time);
if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
rpt = phydm_idle_noise_measure_ac(dm, pause_dig, igi, max_time);
return rpt;
}
if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A)))
return 0;
@@ -265,11 +274,11 @@ odm_inband_noise_monitor_ac_series(
func_start = odm_get_current_time(dm);
dm->noise_level.noise_all = 0;
PHYDM_DBG(dm, DBG_ENV_MNTR, "odm_inband_noise_monitor_ac_series() ==>\n");
PHYDM_DBG(dm, DBG_ENV_MNTR, "%s ==>\n", __func__);
/* step 1. Disable DIG && Set initial gain. */
if (is_pause_dig)
odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value);
if (pause_dig)
odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);
/* step 3. Get noise power level */
start = odm_get_current_time(dm);
@@ -279,56 +288,72 @@ odm_inband_noise_monitor_ac_series(
/*Set IGI=0x1C */
odm_write_dig(dm, 0x1C);
/*stop CK320&CK88 */
odm_set_bb_reg(dm, 0x8B4, BIT(6), 1);
odm_set_bb_reg(dm, R_0x8b4, BIT(6), 1);
/*Read path-A */
odm_set_bb_reg(dm, 0x8FC, MASKDWORD, 0x200); /*set debug port*/
value32 = odm_get_bb_reg(dm, 0xFA0, MASKDWORD); /*read debug port*/
rxi_buf_anta = (value32 & 0xFFC00) >> 10; /*rxi_buf_anta=RegFA0[19:10]*/
/*set debug port*/
odm_set_bb_reg(dm, R_0x8fc, MASKDWORD, 0x200);
/*read debug port*/
value32 = odm_get_bb_reg(dm, R_0xfa0, MASKDWORD);
/*rxi_buf_anta=RegFA0[19:10]*/
rxi_buf_anta = (value32 & 0xFFC00) >> 10;
rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/
pd_flag = (boolean)((value32 & BIT(31)) >> 31);
/*Not in packet detection period or Tx state */
if ((!pd_flag) || (rxi_buf_anta != 0x200)) {
if (!pd_flag || rxi_buf_anta != 0x200) {
/*sign conversion*/
rxi_buf_anta = odm_sign_conversion(rxi_buf_anta, 10);
rxq_buf_anta = odm_sign_conversion(rxq_buf_anta, 10);
pwdb_A = odm_pwdb_conversion(rxi_buf_anta * rxi_buf_anta + rxq_buf_anta * rxq_buf_anta, 20, 18); /*S(10,9)*S(10,9)=S(20,18)*/
val_s32 = rxi_buf_anta * rxi_buf_anta +
rxq_buf_anta * rxq_buf_anta;
/*S(10,9)*S(10,9)=S(20,18)*/
pwdb_A = odm_pwdb_conversion(val_s32, 20, 18);
PHYDM_DBG(dm, DBG_ENV_MNTR, "pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n", pwdb_A, rxi_buf_anta & 0x3FF, rxq_buf_anta & 0x3FF);
PHYDM_DBG(dm, DBG_ENV_MNTR,
"pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n",
pwdb_A, rxi_buf_anta & 0x3FF,
rxq_buf_anta & 0x3FF);
}
/*Start CK320&CK88*/
odm_set_bb_reg(dm, 0x8B4, BIT(6), 0);
/*BB Reset*/
odm_write_1byte(dm, 0x02, odm_read_1byte(dm, 0x02) & (~BIT(0)));
odm_write_1byte(dm, 0x02, odm_read_1byte(dm, 0x02) | BIT(0));
odm_set_bb_reg(dm, R_0x8b4, BIT(6), 0);
/*@BB Reset*/
val_u8 = odm_read_1byte(dm, 0x02) & (~BIT(0));
odm_write_1byte(dm, 0x02, val_u8);
val_u8 = odm_read_1byte(dm, 0x02) | BIT(0);
odm_write_1byte(dm, 0x02, val_u8);
/*PMAC Reset*/
odm_write_1byte(dm, 0xB03, odm_read_1byte(dm, 0xB03) & (~BIT(0)));
odm_write_1byte(dm, 0xB03, odm_read_1byte(dm, 0xB03) | BIT(0));
/*CCK Reset*/
val_u8 = odm_read_1byte(dm, 0xB03) & (~BIT(0));
odm_write_1byte(dm, 0xB03, val_u8);
val_u8 = odm_read_1byte(dm, 0xB03) | BIT(0);
odm_write_1byte(dm, 0xB03, val_u8);
/*@CCK Reset*/
if (odm_read_1byte(dm, 0x80B) & BIT(4)) {
odm_write_1byte(dm, 0x80B, odm_read_1byte(dm, 0x80B) & (~BIT(4)));
odm_write_1byte(dm, 0x80B, odm_read_1byte(dm, 0x80B) | BIT(4));
val_u8 = odm_read_1byte(dm, 0x80B) & (~BIT(4));
odm_write_1byte(dm, 0x80B, val_u8);
val_u8 = odm_read_1byte(dm, 0x80B) | BIT(4);
odm_write_1byte(dm, 0x80B, val_u8);
}
sval = pwdb_A;
if ((sval < 0 && sval >= -27) && (valid_cnt < VALID_CNT)){
if ((sval < 0 && sval >= -27) && valid_cnt < VALID_CNT) {
valid_cnt++;
sum += sval;
PHYDM_DBG(dm, DBG_ENV_MNTR, "Valid sval = %d\n", sval);
PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n", sum);
if ((valid_cnt >= VALID_CNT) || (odm_get_progressing_time(dm, start) > max_time)) {
if (valid_cnt >= VALID_CNT ||
(odm_get_progressing_time(dm, start) > max_time)) {
sum /= VALID_CNT;
PHYDM_DBG(dm, DBG_ENV_MNTR, "After divided, sum = %d\n", sum);
PHYDM_DBG(dm, DBG_ENV_MNTR,
"After divided, sum = %d\n", sum);
break;
}
}
}
/*ADC backoff is 12dB,*/
/*@ADC backoff is 12dB,*/
/*Ptarget=0x1C-110=-82dBm*/
noise = sum + 12 + 0x1C - 110;
@@ -338,70 +363,72 @@ odm_inband_noise_monitor_ac_series(
dm->noise_level.noise_all = (s16)noise;
/* step 4. Recover the Dig*/
if (is_pause_dig)
odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value);
if (pause_dig)
odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);
func_end = odm_get_progressing_time(dm, func_start);
PHYDM_DBG(dm, DBG_ENV_MNTR, "odm_inband_noise_monitor_ac_series() <==\n");
PHYDM_DBG(dm, DBG_ENV_MNTR, "%s <==\n", __func__);
return dm->noise_level.noise_all;
}
#endif
s16
odm_inband_noise_monitor(
void *dm_void,
u8 is_pause_dig,
u8 igi_value,
u32 max_time
)
s16 odm_inband_noise_monitor(void *dm_void, u8 pause_dig, u8 igi,
u32 max_time)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct dm_struct *dm = (struct dm_struct *)dm_void;
s16 val = 0;
igi_value = 0x32; /*since HW ability is about +15~-35, we fix IGI = -60 for maximum coverage*/
igi = 0x32;
/* since HW ability is about +15~-35,
* we fix IGI = -60 for maximum coverage
*/
#if (ODM_IC_11AC_SERIES_SUPPORT)
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
return odm_inband_noise_monitor_ac_series(dm, is_pause_dig, igi_value, max_time);
else
return odm_inband_noise_monitor_n_series(dm, is_pause_dig, igi_value, max_time);
val = odm_inband_noise_monitor_ac(dm, pause_dig, igi, max_time);
#endif
#if (ODM_IC_11N_SERIES_SUPPORT)
if (dm->support_ic_type & ODM_IC_11N_SERIES)
val = odm_inband_noise_monitor_n(dm, pause_dig, igi, max_time);
#endif
return val;
}
void
phydm_noisy_detection(
void *dm_void
)
void phydm_noisy_detection(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 total_fa_cnt, total_cca_cnt;
u32 score = 0, i, score_smooth;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 total_fa_cnt, total_cca_cnt;
u32 score = 0, i, score_smooth;
total_cca_cnt = dm->false_alm_cnt.cnt_cca_all;
total_fa_cnt = dm->false_alm_cnt.cnt_all;
total_fa_cnt = dm->false_alm_cnt.cnt_all;
#if 0
if (total_fa_cnt * 16 >= total_cca_cnt * 14) /* 87.5 */
if (total_fa_cnt * 16 >= total_cca_cnt * 14) /* @87.5 */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 12) /* 75 */
else if (total_fa_cnt * 16 >= total_cca_cnt * 12) /* @75 */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 10) /* 56.25 */
else if (total_fa_cnt * 16 >= total_cca_cnt * 10) /* @56.25 */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 8) /* 50 */
else if (total_fa_cnt * 16 >= total_cca_cnt * 8) /* @50 */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 7) /* 43.75 */
else if (total_fa_cnt * 16 >= total_cca_cnt * 7) /* @43.75 */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 6) /* 37.5 */
else if (total_fa_cnt * 16 >= total_cca_cnt * 6) /* @37.5 */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 5) /* 31.25% */
else if (total_fa_cnt * 16 >= total_cca_cnt * 5) /* @31.25% */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 4) /* 25% */
else if (total_fa_cnt * 16 >= total_cca_cnt * 4) /* @25% */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 3) /* 18.75% */
else if (total_fa_cnt * 16 >= total_cca_cnt * 3) /* @18.75% */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 2) /* 12.5% */
else if (total_fa_cnt * 16 >= total_cca_cnt * 2) /* @12.5% */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 1) /* 6.25% */
else if (total_fa_cnt * 16 >= total_cca_cnt * 1) /* @6.25% */
;
#endif
for (i = 0; i <= 16; i++) {
@@ -412,16 +439,19 @@ phydm_noisy_detection(
}
/* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */
dm->noisy_decision_smooth = (dm->noisy_decision_smooth >> 1) + (score << 2);
dm->noisy_decision_smooth = (dm->noisy_decision_smooth >> 1) +
(score << 2);
/* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */
score_smooth = (total_cca_cnt >= 300) ? ((dm->noisy_decision_smooth + 3) >> 3) : 0;
if (total_cca_cnt >= 300)
score_smooth = (dm->noisy_decision_smooth + 3) >> 3;
else
score_smooth = 0;
dm->noisy_decision = (score_smooth >= 3) ? 1 : 0;
PHYDM_DBG(dm, DBG_ENV_MNTR,
"[NoisyDetection] CCA_cnt=%d,FA_cnt=%d, noisy_dec_smooth=%d, score=%d, score_smooth=%d, noisy_dec=%d\n",
total_cca_cnt, total_fa_cnt, dm->noisy_decision_smooth, score, score_smooth, dm->noisy_decision);
"[NoisyDetection] CCA_cnt=%d,FA_cnt=%d, noisy_dec_smooth=%d, score=%d, score_smooth=%d, noisy_dec=%d\n",
total_cca_cnt, total_fa_cnt, dm->noisy_decision_smooth, score,
score_smooth, dm->noisy_decision);
}

35
hal/phydm/phydm_noisemonitor.h
View File

@@ -22,34 +22,27 @@
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __ODMNOISEMONITOR_H__
#ifndef __ODMNOISEMONITOR_H__
#define __ODMNOISEMONITOR_H__
#define ODM_MAX_CHANNEL_NUM 38/* 14+24 */
struct noise_level {
u8 value[PHYDM_MAX_RF_PATH];
s8 sval[PHYDM_MAX_RF_PATH];
s32 sum[PHYDM_MAX_RF_PATH];
u8 valid[PHYDM_MAX_RF_PATH];
u8 valid_cnt[PHYDM_MAX_RF_PATH];
};
#define VALID_CNT 5
struct noise_level {
u8 value[PHYDM_MAX_RF_PATH];
s8 sval[PHYDM_MAX_RF_PATH];
s32 sum[PHYDM_MAX_RF_PATH];
u8 valid[PHYDM_MAX_RF_PATH];
u8 valid_cnt[PHYDM_MAX_RF_PATH];
};
struct odm_noise_monitor {
s8 noise[PHYDM_MAX_RF_PATH];
s16 noise_all;
s8 noise[PHYDM_MAX_RF_PATH];
s16 noise_all;
};
s16 odm_inband_noise_monitor(
void *dm_void,
u8 is_pause_dig,
u8 igi_value,
u32 max_time
);
s16 odm_inband_noise_monitor(void *dm_void, u8 is_pause_dig, u8 igi_value,
u32 max_time);
void
phydm_noisy_detection(
void *dm_void
);
void phydm_noisy_detection(void *dm_void);
#endif

1177
hal/phydm/phydm_pathdiv.c
View File

File diff suppressed because it is too large Load Diff

237
hal/phydm/phydm_pathdiv.h
View File

@@ -23,24 +23,24 @@
*
*****************************************************************************/
#ifndef __PHYDMPATHDIV_H__
#define __PHYDMPATHDIV_H__
/*#define PATHDIV_VERSION "2.0" //2014.11.04*/
#define PATHDIV_VERSION "3.1" /*2015.07.29 by YuChen*/
#ifndef __PHYDMPATHDIV_H__
#define __PHYDMPATHDIV_H__
#if (defined(CONFIG_PATH_DIVERSITY))
#define USE_PATH_A_AS_DEFAULT_ANT /* for 8814 dynamic TX path selection */
#ifdef CONFIG_PATH_DIVERSITY
#define PATHDIV_VERSION "4.0"
#define NUM_RESET_DTP_PERIOD 5
#define ANT_DECT_RSSI_TH 3
#define USE_PATH_A_AS_DEFAULT_ANT /* @for 8814 dynamic TX path selection */
#define NUM_RESET_DTP_PERIOD 5
#define ANT_DECT_RSSI_TH 3
#define PATH_A 1
#define PATH_B 2
#define PATH_C 3
#define PATH_D 4
#define PHYDM_AUTO_PATH 0
#define PHYDM_FIX_PATH 1
#define PHYDM_AUTO_PATH 0
#define PHYDM_FIX_PATH 1
#define NUM_CHOOSE2_FROM4 6
#define NUM_CHOOSE3_FROM4 4
@@ -48,7 +48,6 @@
enum phydm_dtp_state {
PHYDM_DTP_INIT = 1,
PHYDM_DTP_RUNNING_1
};
enum phydm_path_div_type {
@@ -56,16 +55,14 @@ enum phydm_path_div_type {
PHYDM_4R_PATH_DIV = 2
};
void
phydm_process_rssi_for_path_div(
void *dm_void,
void *phy_info_void,
void *pkt_info_void
);
enum phydm_path_ctrl {
TX_PATH_BY_REG = 0,
TX_PATH_BY_DESC = 1
};
struct _ODM_PATH_DIVERSITY_ {
u8 resp_tx_path;
u8 path_sel[ODM_ASSOCIATE_ENTRY_NUM];
enum bb_path default_tx_path;
enum bb_path path_sel[ODM_ASSOCIATE_ENTRY_NUM];
u32 path_a_sum[ODM_ASSOCIATE_ENTRY_NUM];
u32 path_b_sum[ODM_ASSOCIATE_ENTRY_NUM];
u16 path_a_cnt[ODM_ASSOCIATE_ENTRY_NUM];
@@ -100,205 +97,27 @@ struct _ODM_PATH_DIVERSITY_ {
u8 pre_tx_path;
u8 use_path_a_as_default_ant;
boolean is_path_a_exist;
boolean is_path_a_exist;
#endif
};
void phydm_set_tx_path_by_bb_reg(void *dm_void, u8 path);
#endif /* #if(defined(CONFIG_PATH_DIVERSITY)) */
u8 phydm_get_tx_path_txdesc(void *dm_void, u8 macid);
void
phydm_c2h_dtp_handler(
void *dm_void,
u8 *cmd_buf,
u8 cmd_len
);
void phydm_c2h_dtp_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
void
phydm_path_diversity_init(
void *dm_void
);
void phydm_tx_path_diversity_init(void *dm_void);
void
odm_path_diversity(
void *dm_void
);
void phydm_tx_path_diversity(void *dm_void);
void
odm_pathdiv_debug(
void *dm_void,
u32 *const dm_value,
u32 *_used,
char *output,
u32 *_out_len
);
void phydm_process_rssi_for_path_div(void *dm_void, void *phy_info_void,
void *pkt_info_void);
void phydm_pathdiv_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif /* @#ifdef CONFIG_PATH_DIVERSITY */
#endif /* @#ifndef __PHYDMPATHDIV_H__ */
/* 1 [OLD IC]-------------------------------------------------------------------------------- */
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
/* #define PATHDIV_ENABLE 1 */
#define dm_path_div_rssi_check odm_path_div_chk_per_pkt_rssi
#define path_div_check_before_link8192c odm_path_diversity_before_link92c
struct _path_div_parameter_define_ {
u32 org_5g_rege30;
u32 org_5g_regc14;
u32 org_5g_regca0;
u32 swt_5g_rege30;
u32 swt_5g_regc14;
u32 swt_5g_regca0;
/* for 2G IQK information */
u32 org_2g_regc80;
u32 org_2g_regc4c;
u32 org_2g_regc94;
u32 org_2g_regc14;
u32 org_2g_regca0;
u32 swt_2g_regc80;
u32 swt_2g_regc4c;
u32 swt_2g_regc94;
u32 swt_2g_regc14;
u32 swt_2g_regca0;
};
void
odm_path_diversity_init_92c(
void *adapter
);
void
odm_2t_path_diversity_init_92c(
void *adapter
);
void
odm_1t_path_diversity_init_92c(
void *adapter
);
boolean
odm_is_connected_92c(
void *adapter
);
boolean
odm_path_diversity_before_link92c(
/* struct void* adapter */
struct dm_struct *dm
);
void
odm_path_diversity_after_link_92c(
void *adapter
);
void
odm_set_resp_path_92c(
void *adapter,
u8 default_resp_path
);
void
odm_ofdm_tx_path_diversity_92c(
void *adapter
);
void
odm_cck_tx_path_diversity_92c(
void *adapter
);
void
odm_reset_path_diversity_92c(
void *adapter
);
void
odm_cck_tx_path_diversity_callback(
struct phydm_timer_list *timer
);
void
odm_cck_tx_path_diversity_work_item_callback(
void *context
);
void
odm_path_div_chk_ant_switch_callback(
struct phydm_timer_list *timer
);
void
odm_path_div_chk_ant_switch_workitem_callback(
void *context
);
void
odm_path_div_chk_ant_switch(
struct dm_struct *dm
);
void
odm_cck_path_diversity_chk_per_pkt_rssi(
void *adapter,
boolean is_def_port,
boolean is_match_bssid,
struct _WLAN_STA *entry,
PRT_RFD rfd,
u8 *desc
);
void
odm_path_div_chk_per_pkt_rssi(
void *adapter,
boolean is_def_port,
boolean is_match_bssid,
struct _WLAN_STA *entry,
PRT_RFD rfd
);
void
odm_path_div_rest_after_link(
struct dm_struct *dm
);
void
odm_fill_tx_path_in_txdesc(
void *adapter,
PRT_TCB tcb,
u8 *desc
);
void
odm_path_div_init_92d(
struct dm_struct *dm
);
u8
odm_sw_ant_div_select_scan_chnl(
void *adapter
);
void
odm_sw_ant_div_construct_scan_chnl(
void *adapter,
u8 scan_chnl
);
#endif /* #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) */
#endif /* #ifndef __ODMPATHDIV_H__ */

4020
hal/phydm/phydm_phystatus.c
View File

File diff suppressed because it is too large Load Diff

1582
hal/phydm/phydm_phystatus.h
View File

File diff suppressed because it is too large Load Diff

543
hal/phydm/phydm_pmac_tx_setting.c Normal file
View File

@@ -0,0 +1,543 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*@************************************************************
* include files
************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
void phydm_start_cck_cont_tx_jgr3(void *dm_void,
struct phydm_pmac_info *tx_info)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
u8 rate = tx_info->tx_rate; /* @HW rate */
/* @if CCK block on? */
if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1);
/* @Turn Off All Test mode */
odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
odm_set_bb_reg(dm, R_0x1a00, 0x3000, rate);
odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2); /* @transmit mode */
odm_set_bb_reg(dm, R_0x1a00, 0x8, 0x1); /* @turn on scramble setting */
/* @Fix rate selection issue */
odm_set_bb_reg(dm, R_0x1a70, 0x4000, 0x1);
/* @set RX weighting for path I & Q to 0 */
odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
/* @set loopback mode */
odm_set_bb_reg(dm, R_0x1c3c, 0x10, 0x1);
pmac_tx->cck_cont_tx = true;
pmac_tx->ofdm_cont_tx = false;
}
void phydm_stop_cck_cont_tx_jgr3(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
pmac_tx->cck_cont_tx = false;
pmac_tx->ofdm_cont_tx = false;
odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0); /* @normal mode */
odm_set_bb_reg(dm, R_0x1a00, 0x8, 0x1); /* @turn on scramble setting */
/* @back to default */
odm_set_bb_reg(dm, R_0x1a70, 0x4000, 0x0);
odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
odm_set_bb_reg(dm, R_0x1c3c, 0x10, 0x0);
/* @BB Reset */
odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0);
odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1);
}
void phydm_start_ofdm_cont_tx_jgr3(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
/* @1. if OFDM block on */
if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1);
/* @2. set CCK test mode off, set to CCK normal mode */
odm_set_bb_reg(dm, R_0x1a00, 0x3, 0);
/* @3. turn on scramble setting */
odm_set_bb_reg(dm, R_0x1a00, 0x8, 1);
/* @4. Turn On Continue Tx and turn off the other test modes. */
odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x1);
pmac_tx->cck_cont_tx = false;
pmac_tx->ofdm_cont_tx = true;
}
void phydm_stop_ofdm_cont_tx_jgr3(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
pmac_tx->cck_cont_tx = false;
pmac_tx->ofdm_cont_tx = false;
/* @Turn Off All Test mode */
odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
/* @Delay 10 ms */
ODM_delay_ms(10);
/* @BB Reset */
odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0);
odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1);
}
void phydm_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
boolean en_pmac_tx, u8 path)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
u8 start = RF_PATH_A, end = RF_PATH_A;
switch (path) {
case RF_PATH_A:
case RF_PATH_B:
case RF_PATH_C:
case RF_PATH_D:
start = path;
end = path;
break;
case RF_PATH_AB:
start = RF_PATH_A;
end = RF_PATH_B;
break;
#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT)
case RF_PATH_AC:
start = RF_PATH_A;
end = RF_PATH_C;
break;
case RF_PATH_AD:
start = RF_PATH_A;
end = RF_PATH_D;
break;
case RF_PATH_BC:
start = RF_PATH_B;
end = RF_PATH_C;
break;
case RF_PATH_BD:
start = RF_PATH_B;
end = RF_PATH_D;
break;
case RF_PATH_CD:
start = RF_PATH_C;
end = RF_PATH_D;
break;
case RF_PATH_ABC:
start = RF_PATH_A;
end = RF_PATH_C;
break;
case RF_PATH_ABD:
start = RF_PATH_A;
end = RF_PATH_D;
break;
case RF_PATH_ACD:
start = RF_PATH_A;
end = RF_PATH_D;
break;
case RF_PATH_BCD:
start = RF_PATH_B;
end = RF_PATH_D;
break;
case RF_PATH_ABCD:
start = RF_PATH_A;
end = RF_PATH_D;
break;
#endif
}
if (is_single_tone) {
pmac_tx->tx_scailing = odm_get_bb_reg(dm, R_0x81c, MASKDWORD);
if (!en_pmac_tx) {
phydm_start_ofdm_cont_tx_jgr3(dm);
/*SendPSPoll(pAdapter);*/
}
odm_set_bb_reg(dm, R_0x1c68, BIT(24), 0x1); /* @Disable CCA */
for (start; start <= end; start++) {
/* @Tx mode: RF0x00[19:16]=4'b0010 */
/* odm_set_rf_reg(dm, start, RF_0x0, 0xF0000, 0x2); */
/* @Lowest RF gain index: RF_0x0[4:0] = 0*/
odm_set_rf_reg(dm, start, RF_0x0, 0x1F, 0x0);
/* @RF LO enabled */
odm_set_rf_reg(dm, start, RF_0x58, BIT(1), 0x1);
}
#if (RTL8814B_SUPPORT == 1)
if (dm->support_ic_type & ODM_RTL8814B) {
/* @Tx mode: RF0x00[19:16]=4'b0010 */
/* config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
* 0xF0000, 0x2);
*/
/* @Lowest RF gain index: RF_0x0[4:0] = 0*/
config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
0x1F, 0x0);
/* @RF LO enabled */
config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
BIT(1), 0x1);
}
#endif
odm_set_bb_reg(dm, R_0x81c, 0x001FC000, 0);
} else {
for (start; start <= end; start++) {
/* @RF LO disabled */
odm_set_rf_reg(dm, start, RF_0x58, BIT(1), 0x0);
}
odm_set_bb_reg(dm, R_0x1c68, BIT(24), 0x0); /* @Enable CCA */
if (!en_pmac_tx)
phydm_stop_ofdm_cont_tx_jgr3(dm);
odm_set_bb_reg(dm, R_0x81c, MASKDWORD, pmac_tx->tx_scailing);
}
}
void phydm_stop_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
u32 tmp = 0;
if (tx_info->mode == CONT_TX) {
odm_set_bb_reg(dm, R_0x1e70, 0xf, 2); /* TX Stop */
if (pmac_tx->is_cck_rate)
phydm_stop_cck_cont_tx_jgr3(dm);
else
phydm_stop_ofdm_cont_tx_jgr3(dm);
} else {
if (pmac_tx->is_cck_rate) {
tmp = odm_get_bb_reg(dm, R_0x2de4, MASKLWORD);
odm_set_bb_reg(dm, R_0x1e64, MASKLWORD, tmp + 50);
}
odm_set_bb_reg(dm, R_0x1e70, 0xf, 2); /* TX Stop */
}
if (tx_info->mode == OFDM_SINGLE_TONE_TX) {
/* Stop HW TX -> Stop Continuous TX -> Stop RF Setting */
if (pmac_tx->is_cck_rate)
phydm_stop_cck_cont_tx_jgr3(dm);
else
phydm_stop_ofdm_cont_tx_jgr3(dm);
phydm_set_single_tone_jgr3(dm, false, true, pmac_tx->path);
}
}
void phydm_set_mac_phy_txinfo_jgr3(void *dm_void,
struct phydm_pmac_info *tx_info)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
u32 tmp = 0;
odm_set_bb_reg(dm, R_0xa58, 0x003F8000, tx_info->tx_rate);
/* @0x900[1] ndp_sound */
odm_set_bb_reg(dm, R_0x900, 0x2, tx_info->ndp_sound);
/* @0x900[27:24] txsc [29:28] bw [31:30] m_stbc */
tmp = (tx_info->tx_sc) | ((tx_info->bw) << 4) |
((tx_info->m_stbc - 1) << 6);
odm_set_bb_reg(dm, R_0x900, 0xFF000000, tmp);
if (pmac_tx->is_ofdm_rate) {
odm_set_bb_reg(dm, R_0x900, 0x1, 0);
odm_set_bb_reg(dm, R_0x900, 0x4, 0);
} else if (pmac_tx->is_ht_rate) {
odm_set_bb_reg(dm, R_0x900, 0x1, 1);
odm_set_bb_reg(dm, R_0x900, 0x4, 0);
} else if (pmac_tx->is_vht_rate) {
odm_set_bb_reg(dm, R_0x900, 0x1, 0);
odm_set_bb_reg(dm, R_0x900, 0x4, 1);
}
tmp = tx_info->packet_period; /* @for TX interval */
odm_set_bb_reg(dm, R_0x9b8, 0xffff0000, tmp);
}
void phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
u32 tmp = 0;
if (pmac_tx->is_cck_rate)
return;
/* @L-SIG */
odm_set_bb_reg(dm, R_0x1eb4, 0xfffff, tx_info->packet_count);
tmp = BYTE_2_DWORD(0, tx_info->lsig[2], tx_info->lsig[1],
tx_info->lsig[0]);
odm_set_bb_reg(dm, R_0x908, 0xffffff, tmp);
#if 0
/* @0x924[7:0] = Data init octet */
tmp = tx_info->packet_pattern;
odm_set_bb_reg(dm, R_0x924, 0xff, tmp);
if (tx_info->packet_pattern == RANDOM_BY_PN32)
tmp = 0x3;
else
tmp = 0x0;
odm_set_bb_reg(dm, R_0x914, 0x60000000, tmp);
#endif
if (pmac_tx->is_ht_rate) {
/* @HT SIG */
tmp = BYTE_2_DWORD(0, tx_info->ht_sig[2], tx_info->ht_sig[1],
tx_info->ht_sig[0]);
odm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp);
tmp = BYTE_2_DWORD(0, tx_info->ht_sig[5], tx_info->ht_sig[4],
tx_info->ht_sig[3]);
odm_set_bb_reg(dm, R_0x910, 0xffffff, tmp);
} else if (pmac_tx->is_vht_rate) {
/* @VHT SIG A/B/serv_field/delimiter */
tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[2],
tx_info->vht_sig_a[1],
tx_info->vht_sig_a[0]);
odm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp);
tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[5],
tx_info->vht_sig_a[4],
tx_info->vht_sig_a[3]);
odm_set_bb_reg(dm, R_0x910, 0xffffff, tmp);
tmp = BYTE_2_DWORD(tx_info->vht_sig_b[3], tx_info->vht_sig_b[2],
tx_info->vht_sig_b[1],
tx_info->vht_sig_b[0]);
odm_set_bb_reg(dm, R_0x914, 0x1FFFFFFF, tmp);
tmp = tx_info->vht_sig_b_crc;
odm_set_bb_reg(dm, R_0x938, 0xff00, tmp);
tmp = BYTE_2_DWORD(tx_info->vht_delimiter[3],
tx_info->vht_delimiter[2],
tx_info->vht_delimiter[1],
tx_info->vht_delimiter[0]);
odm_set_bb_reg(dm, R_0x940, MASKDWORD, tmp);
}
}
void phydm_set_cck_preamble_hdr_jgr3(void *dm_void,
struct phydm_pmac_info *tx_info)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
u32 tmp = 0;
if (!pmac_tx->is_cck_rate)
return;
tmp = tx_info->packet_count | (tx_info->sfd << 16);
odm_set_bb_reg(dm, R_0x1e64, MASKDWORD, tmp);
tmp = tx_info->signal_field | (tx_info->service_field << 8) |
(tx_info->length << 16);
odm_set_bb_reg(dm, R_0x1e68, MASKDWORD, tmp);
tmp = BYTE_2_DWORD(0, 0, tx_info->crc16[1], tx_info->crc16[0]);
odm_set_bb_reg(dm, R_0x1e6c, 0xffff, tmp);
if (tx_info->is_short_preamble)
odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0);
else
odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 1);
}
void phydm_set_mode_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
enum phydm_pmac_mode mode)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
if (mode == CONT_TX) {
tx_info->packet_count = 1;
if (pmac_tx->is_cck_rate)
phydm_start_cck_cont_tx_jgr3(dm, tx_info);
else
phydm_start_ofdm_cont_tx_jgr3(dm);
} else if (mode == OFDM_SINGLE_TONE_TX) {
/* Continuous TX -> HW TX -> RF Setting */
tx_info->packet_count = 1;
if (pmac_tx->is_cck_rate)
phydm_start_cck_cont_tx_jgr3(dm, tx_info);
else
phydm_start_ofdm_cont_tx_jgr3(dm);
} else if (mode == PKTS_TX) {
if (pmac_tx->is_cck_rate && tx_info->packet_count == 0)
tx_info->packet_count = 0xffff;
}
}
void phydm_set_pmac_txon_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
odm_set_bb_reg(dm, R_0x1d08, BIT(0), 1); /* Turn on PMAC */
/* mac scramble seed setting, only in 8198F */
#if (RTL8198F_SUPPORT == 1)
if (dm->support_ic_type & ODM_RTL8198F)
if ~(odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
odm_set_bb_reg(dm, R_0x1d10, BIT(16), 1);
#endif
if (pmac_tx->is_cck_rate) {
odm_set_bb_reg(dm, R_0x1e70, 0xf, 8); /* TX CCK ON */
odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0);
} else {
odm_set_bb_reg(dm, R_0x1e70, 0xf, 4); /* TX Ofdm ON */
}
if (tx_info->mode == OFDM_SINGLE_TONE_TX)
phydm_set_single_tone_jgr3(dm, true, true, pmac_tx->path);
}
void phydm_set_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
enum rf_path mpt_rf_path)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
pmac_tx->is_cck_rate = phydm_is_cck_rate(dm, tx_info->tx_rate);
pmac_tx->is_ofdm_rate = phydm_is_ofdm_rate(dm, tx_info->tx_rate);
pmac_tx->is_ht_rate = phydm_is_ht_rate(dm, tx_info->tx_rate);
pmac_tx->is_vht_rate = phydm_is_vht_rate(dm, tx_info->tx_rate);
pmac_tx->path = mpt_rf_path;
if (!tx_info->en_pmac_tx) {
phydm_stop_pmac_tx_jgr3(dm, tx_info);
return;
}
phydm_set_mode_jgr3(dm, tx_info, tx_info->mode);
if (pmac_tx->is_cck_rate)
phydm_set_cck_preamble_hdr_jgr3(dm, tx_info);
else
phydm_set_sig_jgr3(dm, tx_info);
phydm_set_mac_phy_txinfo_jgr3(dm, tx_info);
phydm_set_pmac_txon_jgr3(dm, tx_info);
}
void phydm_set_tmac_tx_jgr3(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
/* Turn on TMAC */
if (odm_get_bb_reg(dm, R_0x1d08, BIT(0)))
odm_set_bb_reg(dm, R_0x1d08, BIT(0), 0);
/* mac scramble seed setting, only in 8198F */
#if (RTL8198F_SUPPORT == 1)
if (dm->support_ic_type & ODM_RTL8198F)
if (odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
odm_set_bb_reg(dm, R_0x1d10, BIT(16), 0);
#endif
/* Turn on TMAC CCK */
if ((odm_get_bb_reg(dm, R_0x1a84, BIT(31))) == 0)
odm_set_bb_reg(dm, R_0x1a84, BIT(31), 1);
}
#endif
void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_start_cck_cont_tx_jgr3(dm, tx_info);
}
void phydm_stop_cck_cont_tx(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_stop_cck_cont_tx_jgr3(dm);
}
void phydm_start_ofdm_cont_tx(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_start_ofdm_cont_tx_jgr3(dm);
}
void phydm_stop_ofdm_cont_tx(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_stop_ofdm_cont_tx_jgr3(dm);
}
void phydm_set_single_tone(void *dm_void, boolean is_single_tone,
boolean en_pmac_tx, u8 path)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_set_single_tone_jgr3(dm, is_single_tone,
en_pmac_tx, path);
}
void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info,
enum rf_path mpt_rf_path)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_set_pmac_tx_jgr3(dm, tx_info, mpt_rf_path);
}
void phydm_set_tmac_tx(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_set_tmac_tx_jgr3(dm);
}
#endif

152
hal/phydm/phydm_pmac_tx_setting.h Normal file
View File

@@ -0,0 +1,152 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_PMAC_TX_SETTING_H__
#define __PHYDM_PMAC_TX_SETTING_H__
#define PMAC_TX_SETTING_VERSION "1.0"
/* @1 ============================================================
* 1 Definition
* 1 ============================================================
*/
#define RANDOM_BY_PN32 0x12
/* @1 ============================================================
* 1 structure
* 1 ============================================================
*/
struct phydm_pmac_info {
u8 en_pmac_tx:1; /*@ disable pmac 1: enable pmac */
u8 mode:3; /*@ 0: Packet TX 3:Continuous TX */
/* @u8 Ntx:4; */
u8 tx_rate; /* @should be HW rate*/
/* @u8 TX_RATE_HEX; */
u8 tx_sc;
/* @u8 bSGI:1; */
u8 is_short_preamble:1;
/* @u8 bSTBC:1; */
/* @u8 bLDPC:1; */
u8 ndp_sound:1;
u8 bw:3; /* @0:20 1:40 2:80Mhz */
u8 m_stbc; /* @bSTBC + 1 */
u16 packet_period;
u32 packet_count;
/* @u32 PacketLength; */
u8 packet_pattern;
u16 sfd;
u8 signal_field;
u8 service_field;
u16 length;
u8 crc16[2];
u8 lsig[3];
u8 ht_sig[6];
u8 vht_sig_a[6];
u8 vht_sig_b[4];
u8 vht_sig_b_crc;
u8 vht_delimiter[4];
/* @u8 mac_addr[6]; */
};
struct phydm_pmac_tx {
boolean is_cck_rate;
boolean is_ofdm_rate;
boolean is_ht_rate;
boolean is_vht_rate;
boolean cck_cont_tx;
boolean ofdm_cont_tx;
u8 path;
u32 tx_scailing;
};
/* @1 ============================================================
* 1 enumeration
* 1 ============================================================
*/
enum phydm_pmac_mode {
NONE_TEST,
PKTS_TX,
PKTS_RX,
CONT_TX,
OFDM_SINGLE_TONE_TX,
CCK_CARRIER_SIPPRESSION_TX
};
/* @1 ============================================================
* 1 function prototype
* 1 ============================================================
*/
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
void phydm_start_cck_cont_tx_jgr3(void *dm_void,
struct phydm_pmac_info *tx_info);
void phydm_stop_cck_cont_tx_jgr3(void *dm_void);
void phydm_start_ofdm_cont_tx_jgr3(void *dm_void);
void phydm_stop_ofdm_cont_tx_jgr3(void *dm_void);
void phydm_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
boolean en_pmac_tx, u8 path);
void phydm_stop_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info);
void phydm_set_mac_phy_txinfo_jgr3(void *dm_void,
struct phydm_pmac_info *tx_info);
void phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info);
void phydm_set_cck_preamble_hdr_jgr3(void *dm_void,
struct phydm_pmac_info *tx_info);
void phydm_set_mode_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
enum phydm_pmac_mode mode);
void phydm_set_pmac_txon_jgr3(void *dm_void, struct phydm_pmac_info *tx_info);
void phydm_set_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
enum rf_path mpt_rf_path);
void phydm_set_tmac_tx_jgr3(void *dm_void);
#endif
void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info);
void phydm_stop_cck_cont_tx(void *dm_void);
void phydm_start_ofdm_cont_tx(void *dm_void);
void phydm_stop_ofdm_cont_tx(void *dm_void);
void phydm_set_single_tone(void *dm_void, boolean is_single_tone,
boolean en_pmac_tx, u8 path);
void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info,
enum rf_path mpt_rf_path);
void phydm_set_tmac_tx(void *dm_void);
#endif

229
hal/phydm/phydm_pow_train.c
View File

@@ -23,206 +23,149 @@
*
*****************************************************************************/
/* ************************************************************
/*************************************************************
* include files
* ************************************************************ */
************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef PHYDM_POWER_TRAINING_SUPPORT
void
phydm_reset_pt_para(
void *dm_void
)
void phydm_reset_pt_para(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pow_train_stuc *pow_train_t = &dm->pow_train_table;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table;
pow_train_t->pow_train_score = 0;
dm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
dm->phy_dbg_info.num_qry_phy_status_cck = 0;
pt_t->pow_train_score = 0;
}
void
phydm_update_power_training_state(
void *dm_void
)
void phydm_update_power_training_state(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pow_train_stuc *pow_train_t = &dm->pow_train_table;
struct phydm_fa_struct *fa_cnt = &dm->false_alm_cnt;
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
u32 pt_score_tmp = 0;
u32 crc_ok_cnt;
u32 cca_all_cnt;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table;
struct phydm_fa_struct *fa_cnt = &dm->false_alm_cnt;
struct ccx_info *ccx = &dm->dm_ccx_info;
u32 pt_score_tmp = ENABLE_PT_SCORE;
u32 crc_ok_cnt = 0;
u32 cca_cnt = 0;
/*is_disable_power_training is the key to H2C to disable/enable power training*/
/*if is_disable_power_training == 1, it will use largest power*/
if (!(dm->support_ability & ODM_BB_PWR_TRAIN)) {
/*@is_disable_power_training is the key to H2C to disable/enable PT*/
/*@if is_disable_power_training == 1, it will use largest power*/
if (!(dm->support_ability & ODM_BB_PWR_TRAIN) || !dm->is_linked) {
dm->is_disable_power_training = true;
phydm_reset_pt_para(dm);
return;
}
PHYDM_DBG(dm, DBG_PWR_TRAIN, "%s ======>\n", __FUNCTION__);
PHYDM_DBG(dm, DBG_PWR_TRAIN, "%s ======>\n", __func__);
if (pow_train_t->force_power_training_state == DISABLE_POW_TRAIN) {
if (pt_t->pt_state == DISABLE_POW_TRAIN) {
dm->is_disable_power_training = true;
phydm_reset_pt_para(dm);
PHYDM_DBG(dm, DBG_PWR_TRAIN, "Disable PT\n");
return;
} else if (pow_train_t->force_power_training_state == ENABLE_POW_TRAIN) {
} else if (pt_t->pt_state == ENABLE_POW_TRAIN) {
dm->is_disable_power_training = false;
phydm_reset_pt_para(dm);
PHYDM_DBG(dm, DBG_PWR_TRAIN, "Enable PT\n");
return;
} else if (pow_train_t->force_power_training_state == DYNAMIC_POW_TRAIN) {
} else if (pt_t->pt_state == DYNAMIC_POW_TRAIN) {
PHYDM_DBG(dm, DBG_PWR_TRAIN, "Dynamic PT\n");
if (!dm->is_linked) {
/* @Compute score */
crc_ok_cnt = dm->phy_dbg_info.num_qry_phy_status_ofdm +
dm->phy_dbg_info.num_qry_phy_status_cck;
cca_cnt = fa_cnt->cnt_cca_all;
#if 0
if (crc_ok_cnt > cca_cnt) { /*invalid situation*/
pt_score_tmp = KEEP_PRE_PT_SCORE;
return;
} else if ((crc_ok_cnt + (crc_ok_cnt >> 1)) <= cca_cnt) {
/* @???crc_ok <= (2/3)*cca */
pt_score_tmp = DISABLE_PT_SCORE;
dm->is_disable_power_training = true;
pow_train_t->pow_train_score = 0;
dm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
dm->phy_dbg_info.num_qry_phy_status_cck = 0;
PHYDM_DBG(dm, DBG_PWR_TRAIN, "PT is disabled due to no link.\n");
return;
}
/* First connect */
if ((dm->is_linked) && (!dig_t->is_media_connect)) {
pow_train_t->pow_train_score = 0;
dm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
dm->phy_dbg_info.num_qry_phy_status_cck = 0;
PHYDM_DBG(dm, DBG_PWR_TRAIN, "(PT)First Connect\n");
return;
}
/* Compute score */
crc_ok_cnt = dm->phy_dbg_info.num_qry_phy_status_ofdm + dm->phy_dbg_info.num_qry_phy_status_cck;
cca_all_cnt = fa_cnt->cnt_cca_all;
if (crc_ok_cnt < cca_all_cnt) {
/* crc_ok <= (2/3)*cca */
if ((crc_ok_cnt + (crc_ok_cnt >> 1)) <= cca_all_cnt)
pt_score_tmp = DISABLE_PT_SCORE;
/* crc_ok <= (4/5)*cca */
else if ((crc_ok_cnt + (crc_ok_cnt >> 2)) <= cca_all_cnt)
pt_score_tmp = KEEP_PRE_PT_SCORE;
/* crc_ok > (4/5)*cca */
else
pt_score_tmp = ENABLE_PT_SCORE;
} else if ((crc_ok_cnt + (crc_ok_cnt >> 2)) <= cca_cnt) {
/* @???crc_ok <= (4/5)*cca */
pt_score_tmp = KEEP_PRE_PT_SCORE;
} else {
/* @???crc_ok > (4/5)*cca */
pt_score_tmp = ENABLE_PT_SCORE;
dm->is_disable_power_training = false;
}
#endif
if (ccx->nhm_ratio > 10) {
pt_score_tmp = DISABLE_PT_SCORE;
dm->is_disable_power_training = true;
} else if (ccx->nhm_ratio < 5) {
pt_score_tmp = ENABLE_PT_SCORE;
dm->is_disable_power_training = false;
} else {
pt_score_tmp = KEEP_PRE_PT_SCORE;
}
PHYDM_DBG(dm, DBG_PWR_TRAIN, "crc_ok_cnt = %d, cnt_cca_all = %d\n",
crc_ok_cnt, cca_all_cnt);
PHYDM_DBG(dm, DBG_PWR_TRAIN,
"pkt_cnt{ofdm,cck,all} = {%d, %d, %d}, cnt_cca_all=%d\n",
dm->phy_dbg_info.num_qry_phy_status_ofdm,
dm->phy_dbg_info.num_qry_phy_status_cck,
crc_ok_cnt, cca_cnt);
PHYDM_DBG(dm, DBG_PWR_TRAIN, "num_qry_phy_status_ofdm = %d, num_qry_phy_status_cck = %d\n",
dm->phy_dbg_info.num_qry_phy_status_ofdm, dm->phy_dbg_info.num_qry_phy_status_cck);
PHYDM_DBG(dm, DBG_PWR_TRAIN, "pt_score_tmp = %d\n", pt_score_tmp);
PHYDM_DBG(dm, DBG_PWR_TRAIN, "pt_score_tmp = 0(DISABLE), 1(KEEP), 2(ENABLE)\n");
PHYDM_DBG(dm, DBG_PWR_TRAIN, "pt_score_tmp=%d\n", pt_score_tmp);
/* smoothing */
pow_train_t->pow_train_score = (pt_score_tmp << 4) + (pow_train_t->pow_train_score >> 1) + (pow_train_t->pow_train_score >> 2);
pt_score_tmp = (pow_train_t->pow_train_score + 32) >> 6;
PHYDM_DBG(dm, DBG_PWR_TRAIN, "pow_train_score = %d, score after smoothing = %d\n",
pow_train_t->pow_train_score, pt_score_tmp);
pt_t->pow_train_score = (pt_score_tmp << 4) +
(pt_t->pow_train_score >> 1) +
(pt_t->pow_train_score >> 2);
/* mode decision */
if (pt_score_tmp == ENABLE_PT_SCORE) {
dm->is_disable_power_training = false;
PHYDM_DBG(dm, DBG_PWR_TRAIN, "Enable power training under dynamic.\n");
} else if (pt_score_tmp == DISABLE_PT_SCORE) {
dm->is_disable_power_training = true;
PHYDM_DBG(dm, DBG_PWR_TRAIN, "Disable PT due to noisy.\n");
}
pt_score_tmp = (pt_t->pow_train_score + 32) >> 6;
PHYDM_DBG(dm, DBG_PWR_TRAIN, "Final, score = %d, is_disable_power_training = %d\n",
pt_score_tmp, dm->is_disable_power_training);
dm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
dm->phy_dbg_info.num_qry_phy_status_cck = 0;
PHYDM_DBG(dm, DBG_PWR_TRAIN,
"pow_train_score = %d, score after smoothing = %d, is_disable_PT = %d\n",
pt_t->pow_train_score, pt_score_tmp,
dm->is_disable_power_training);
} else {
dm->is_disable_power_training = true;
phydm_reset_pt_para(dm);
PHYDM_DBG(dm, DBG_PWR_TRAIN, "PT is disabled due to unknown pt state.\n");
return;
PHYDM_DBG(dm, DBG_PWR_TRAIN, "[%s]warning\n", __func__);
}
}
void
phydm_pow_train_debug(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
)
void phydm_pow_train_debug(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pow_train_stuc *pow_train_t = &dm->pow_train_table;
char help[] = "-h";
u32 var1[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u32 i;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table;
char help[] = "-h";
u32 var1[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u32 i;
if ((strcmp(input[1], help) == 0)) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"0: Dynamic state\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"1: Enable PT\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"2: Disable PT\n");
"{0: Auto PT, 1:enable, 2: disable}\n");
} else {
for (i = 0; i < 10; i++) {
if (input[i + 1]) {
if (input[i + 1])
PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
}
}
if (var1[0] == 0) {
pow_train_t->force_power_training_state = DYNAMIC_POW_TRAIN;
PDM_SNPF(out_len, used, output + used,
out_len - used, "Dynamic state\n");
} else if (var1[0] == 1) {
pow_train_t->force_power_training_state = ENABLE_POW_TRAIN;
PDM_SNPF(out_len, used, output + used,
out_len - used, "Enable PT\n");
} else if (var1[0] == 2) {
pow_train_t->force_power_training_state = DISABLE_POW_TRAIN;
PDM_SNPF(out_len, used, output + used,
out_len - used, "Disable PT\n");
} else {
PDM_SNPF(out_len, used, output + used,
out_len - used, "Set Error\n");
}
if (var1[0] == 0)
pt_t->pt_state = DYNAMIC_POW_TRAIN;
else if (var1[0] == 1)
pt_t->pt_state = ENABLE_POW_TRAIN;
else if (var1[0] == 2)
pt_t->pt_state = DISABLE_POW_TRAIN;
PDM_SNPF(out_len, used, output + used, out_len - used,
"PT state = %d\n", pt_t->pt_state);
}
*_used = used;
*_out_len = out_len;
}
#endif

60
hal/phydm/phydm_pow_train.h
View File

@@ -23,33 +23,34 @@
*
*****************************************************************************/
#ifndef __PHYDM_POW_TRAIN_H__
#define __PHYDM_POW_TRAIN_H__
#ifndef __PHYDM_POW_TRAIN_H__
#define __PHYDM_POW_TRAIN_H__
#define POW_TRAIN_VERSION "1.0" /* @2017.07.0141 Dino, Add phydm_pow_train.h*/
#define POW_TRAIN_VERSION "1.0" /* 2017.07.0141 Dino, Add phydm_pow_train.h*/
/* 1 ============================================================
/****************************************************************
* 1 ============================================================
* 1 Definition
* 1 ============================================================ */
* 1 ============================================================
***************************************************************/
#ifdef PHYDM_POWER_TRAINING_SUPPORT
/* 1 ============================================================
/****************************************************************
* 1 ============================================================
* 1 structure
* 1 ============================================================ */
* 1 ============================================================
***************************************************************/
struct phydm_pow_train_stuc {
u8 force_power_training_state;
u32 pow_train_score;
u8 pt_state;
u32 pow_train_score;
};
/* 1 ============================================================
/****************************************************************
* 1 ============================================================
* 1 enumeration
* 1 ============================================================ */
* 1 ============================================================
***************************************************************/
enum pow_train_state {
DYNAMIC_POW_TRAIN = 0,
@@ -63,24 +64,21 @@ enum power_training_score {
ENABLE_PT_SCORE = 2
};
/* 1 ============================================================
/****************************************************************
* 1 ============================================================
* 1 function prototype
* 1 ============================================================ */
* 1 ============================================================
***************************************************************/
void
phydm_update_power_training_state(
void *dm_void
);
void phydm_update_power_training_state(
void *dm_void);
void
phydm_pow_train_debug(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len,
u32 input_num
);
void phydm_pow_train_debug(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len);
#endif
#endif

Some files were not shown because too many files have changed in this diff Show More