RinCat/RTL88x2BU-Linux-Driver
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Update to 5.6.1

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This commit is contained in:
Rin Cat
2019-09-21 05:30:30 -04:00
parent 953142179e
commit 0644d0b316
413 changed files with 179115 additions and 110562 deletions
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8
hal/halmac/halmac_2_platform.h
View File

@@ -28,13 +28,19 @@
#include <osdep_service.h> /* __BIG_ENDIAN, __LITTLE_ENDIAN, _sema, _mutex */
#endif
/*[Driver] provide the define of _TRUE, _FALSE, NULL, u8, u16, u32*/
/*[Driver] provide the define of NULL, u8, u16, u32*/
#ifndef NULL
#define NULL ((void *)0)
#endif
#define HALMAC_INLINE inline
/*
* Ignore following typedef because Linux already have these
* u8, u16, u32, s8, s16, s32
* __le16, __le32, __be16, __be32
*/
#define HALMAC_PLATFORM_LITTLE_ENDIAN 1
#define HALMAC_PLATFORM_BIG_ENDIAN 0

1
hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h
View File

@@ -55,6 +55,7 @@
#define EFUSE_SIZE_8822B 1024
#define EEPROM_SIZE_8822B 768
#define BT_EFUSE_SIZE_8822B 128
#define PRTCT_EFUSE_SIZE_8822B 96
#define SEC_CAM_NUM_8822B 64

23
hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.c
View File

@@ -37,7 +37,6 @@ cfg_drv_info_8822b(struct halmac_adapter *adapter,
u8 value8;
u32 value32;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
struct halmac_mac_rx_ignore_cfg cfg;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
PLTFM_MSG_TRACE("[TRACE]drv info = %d\n", drv_info);
@@ -48,28 +47,24 @@ cfg_drv_info_8822b(struct halmac_adapter *adapter,
phy_status_en = 0;
sniffer_en = 0;
plcp_hdr_en = 0;
cfg.hdr_chk_en = _FALSE;
break;
case HALMAC_DRV_INFO_PHY_STATUS:
drv_info_size = 4;
phy_status_en = 1;
sniffer_en = 0;
plcp_hdr_en = 0;
cfg.hdr_chk_en = _FALSE;
break;
case HALMAC_DRV_INFO_PHY_SNIFFER:
drv_info_size = 5; /* phy status 4byte, sniffer info 1byte */
phy_status_en = 1;
sniffer_en = 1;
plcp_hdr_en = 0;
cfg.hdr_chk_en = _FALSE;
break;
case HALMAC_DRV_INFO_PHY_PLCP:
drv_info_size = 6; /* phy status 4byte, plcp header 2byte */
phy_status_en = 1;
sniffer_en = 0;
plcp_hdr_en = 1;
cfg.hdr_chk_en = _FALSE;
break;
default:
return HALMAC_RET_SW_CASE_NOT_SUPPORT;
@@ -79,8 +74,6 @@ cfg_drv_info_8822b(struct halmac_adapter *adapter,
HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE)
drv_info_size = RX_DESC_DUMMY_SIZE_8822B >> 3;
api->halmac_set_hw_value(adapter, HALMAC_HW_RX_IGNORE, &cfg);
HALMAC_REG_W8(REG_RX_DRVINFO_SZ, drv_info_size);
value8 = HALMAC_REG_R8(REG_TRXFF_BNDY + 1);
@@ -127,22 +120,6 @@ void
cfg_rx_ignore_8822b(struct halmac_adapter *adapter,
struct halmac_mac_rx_ignore_cfg *cfg)
{
u8 value8;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
value8 = HALMAC_REG_R8(REG_BBPSF_CTRL);
/*mac header check enable*/
if (cfg->hdr_chk_en == _TRUE)
value8 |= BIT_BBPSF_MHCHKEN | BIT_BBPSF_MPDUCHKEN;
else
value8 &= ~(BIT_BBPSF_MHCHKEN) & (~(BIT_BBPSF_MPDUCHKEN));
HALMAC_REG_W8(REG_BBPSF_CTRL, value8);
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
}
enum halmac_ret_status

24
hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.c
View File

@@ -50,6 +50,10 @@ get_hw_value_8822b(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
case HALMAC_HW_FW_MAX_SIZE:
*(u32 *)value = WLAN_FW_MAX_SIZE_8822B;
break;
case HALMAC_HW_SDIO_INT_LAT:
break;
case HALMAC_HW_SDIO_CLK_CNT:
break;
default:
return HALMAC_RET_PARA_NOT_SUPPORT;
}
@@ -94,14 +98,16 @@ set_hw_value_8822b(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
case HALMAC_HW_RXGCK_FIFO:
break;
case HALMAC_HW_RX_IGNORE:
cfg_rx_ignore_8822b(adapter,
(struct halmac_mac_rx_ignore_cfg *)value);
break;
case HALMAC_HW_LDO25_EN:
cfg_ldo25_8822b(adapter, *(u8 *)value);
break;
case HALMAC_HW_PCIE_REF_AUTOK:
break;
case HALMAC_HW_SDIO_WT_EN:
break;
case HALMAC_HW_SDIO_CLK_MONITOR:
break;
default:
return HALMAC_RET_PARA_NOT_SUPPORT;
}
@@ -122,8 +128,8 @@ set_hw_value_8822b(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
enum halmac_ret_status
fill_txdesc_check_sum_8822b(struct halmac_adapter *adapter, u8 *txdesc)
{
u16 chksum = 0;
u16 *data = (u16 *)NULL;
__le16 chksum = 0;
__le16 *data;
u32 i;
if (!txdesc) {
@@ -131,12 +137,12 @@ fill_txdesc_check_sum_8822b(struct halmac_adapter *adapter, u8 *txdesc)
return HALMAC_RET_NULL_POINTER;
}
if (adapter->tx_desc_checksum != _TRUE)
if (adapter->tx_desc_checksum != 1)
PLTFM_MSG_TRACE("[TRACE]chksum disable");
SET_TX_DESC_TXDESC_CHECKSUM(txdesc, 0x0000);
data = (u16 *)(txdesc);
data = (__le16 *)(txdesc);
/* HW clculates only 32byte */
for (i = 0; i < 8; i++)
@@ -144,9 +150,7 @@ fill_txdesc_check_sum_8822b(struct halmac_adapter *adapter, u8 *txdesc)
/* *(data + 2 * i) & *(data + (2 * i + 1) have endain issue*/
/* Process eniadn issue after checksum calculation */
chksum = rtk_le16_to_cpu(chksum);
SET_TX_DESC_TXDESC_CHECKSUM(txdesc, chksum);
SET_TX_DESC_TXDESC_CHECKSUM(txdesc, rtk_le16_to_cpu(chksum));
return HALMAC_RET_SUCCESS;
}
@@ -159,7 +163,7 @@ cfg_ldo25_8822b(struct halmac_adapter *adapter, u8 enable)
value8 = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 3);
if (enable == _TRUE)
if (enable == 1)
HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 3, (u8)(value8 | BIT(7)));
else
HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 3, (u8)(value8 & ~BIT(7)));

126
hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.c
View File

@@ -314,7 +314,7 @@
{HALMAC_SW_IO, HALMAC_GPIO15, HALMAC_GPIO_IN_OUT, \
0x40, BIT(1) | BIT(0), 0}
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO0_8822B[] = {
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO0_8822B[] = {
GPIO0_BT_GPIO0_8822B,
GPIO0_BT_ACT_8822B,
GPIO0_WL_ACT_8822B,
@@ -324,7 +324,7 @@ const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO0_8822B[] = {
GPIO0_SW_IO_8822B
};
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO1_8822B[] = {
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO1_8822B[] = {
GPIO1_BT_GPIO1_8822B,
GPIO1_BT_3DD_SYNC_A_8822B,
GPIO1_WL_CK_8822B,
@@ -335,7 +335,7 @@ const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO1_8822B[] = {
GPIO1_SW_IO_8822B
};
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO2_8822B[] = {
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO2_8822B[] = {
GPIO2_BT_GPIO2_8822B,
GPIO2_WL_STATE_8822B,
GPIO2_BT_STATE_8822B,
@@ -346,7 +346,7 @@ const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO2_8822B[] = {
GPIO2_SW_IO_8822B
};
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO3_8822B[] = {
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO3_8822B[] = {
GPIO3_BT_GPIO3_8822B,
GPIO3_WL_PRI_8822B,
GPIO3_BT_PRI_8822B,
@@ -357,7 +357,7 @@ const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO3_8822B[] = {
GPIO3_SW_IO_8822B
};
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO4_8822B[] = {
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO4_8822B[] = {
GPIO4_BT_SPI_D0_8822B,
GPIO4_WL_SPI_D0_8822B,
GPIO4_SDIO_INT_8822B,
@@ -369,7 +369,7 @@ const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO4_8822B[] = {
GPIO4_SW_IO_8822B
};
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO5_8822B[] = {
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO5_8822B[] = {
GPIO5_BT_SPI_D1_8822B,
GPIO5_WL_SPI_D1_8822B,
GPIO5_JTAG_TDI_8822B,
@@ -380,7 +380,7 @@ const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO5_8822B[] = {
GPIO5_SW_IO_8822B
};
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO6_8822B[] = {
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO6_8822B[] = {
GPIO6_BT_SPI_D2_8822B,
GPIO6_WL_SPI_D2_8822B,
GPIO6_EEDO_8822B,
@@ -394,7 +394,7 @@ const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO6_8822B[] = {
GPIO6_SW_IO_8822B
};
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO7_8822B[] = {
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO7_8822B[] = {
GPIO7_BT_SPI_D3_8822B,
GPIO7_WL_SPI_D3_8822B,
GPIO7_EEDI_8822B,
@@ -407,45 +407,45 @@ const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO7_8822B[] = {
GPIO7_SW_IO_8822B
};
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO8_8822B[] = {
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO8_8822B[] = {
GPIO8_WL_EXT_WOL_8822B,
GPIO8_WL_LED_8822B,
GPIO8_SW_IO_8822B
};
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO9_8822B[] = {
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO9_8822B[] = {
GPIO9_DIS_WL_N_8822B,
GPIO9_WL_EXT_WOL_8822B,
GPIO9_USCTS0_8822B,
GPIO9_SW_IO_8822B
};
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO10_8822B[] = {
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO10_8822B[] = {
GPIO10_SW_IO_8822B
};
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO11_8822B[] = {
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO11_8822B[] = {
GPIO11_DIS_BT_N_8822B,
GPIO11_USOUT0_8822B,
GPIO11_SW_IO_8822B
};
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO12_8822B[] = {
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO12_8822B[] = {
GPIO12_USIN0_8822B,
GPIO12_SW_IO_8822B
};
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO13_8822B[] = {
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO13_8822B[] = {
GPIO13_BT_WAKE_8822B,
GPIO13_SW_IO_8822B
};
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO14_8822B[] = {
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO14_8822B[] = {
GPIO14_UART_WAKE_8822B,
GPIO14_SW_IO_8822B
};
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO15_8822B[] = {
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO15_8822B[] = {
GPIO15_EXT_XTAL_8822B,
GPIO15_SW_IO_8822B
};
@@ -498,6 +498,10 @@ pinmux_get_func_8822b(struct halmac_adapter *adapter,
case HALMAC_GPIO_FUNC_SDIO_INT:
*enable = (cur_func == HALMAC_SDIO_INT) ? 1 : 0;
break;
case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
*enable = (cur_func == HALMAC_GPIO13_14_WL_CTRL_EN) ? 1 : 0;
break;
case HALMAC_GPIO_FUNC_SW_IO_0:
case HALMAC_GPIO_FUNC_SW_IO_1:
case HALMAC_GPIO_FUNC_SW_IO_2:
@@ -630,9 +634,13 @@ pinmux_free_func_8822b(struct halmac_adapter *adapter,
info->sw_io_12 = 0;
break;
case HALMAC_GPIO_FUNC_SW_IO_13:
case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
info->bt_dev_wake = 0;
info->sw_io_13 = 0;
break;
case HALMAC_GPIO_FUNC_SW_IO_14:
case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
info->bt_host_wake = 0;
info->sw_io_14 = 0;
break;
case HALMAC_GPIO_FUNC_SW_IO_15:
@@ -656,85 +664,87 @@ get_pinmux_list_8822b(struct halmac_adapter *adapter,
{
switch (gpio_func) {
case HALMAC_GPIO_FUNC_SW_IO_0:
*list = PIMUX_LIST_GPIO0_8822B;
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO0_8822B);
*list = PINMUX_LIST_GPIO0_8822B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO0_8822B);
*gpio_id = HALMAC_GPIO0;
break;
case HALMAC_GPIO_FUNC_SW_IO_1:
*list = PIMUX_LIST_GPIO1_8822B;
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO1_8822B);
*list = PINMUX_LIST_GPIO1_8822B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO1_8822B);
*gpio_id = HALMAC_GPIO1;
break;
case HALMAC_GPIO_FUNC_SW_IO_2:
*list = PIMUX_LIST_GPIO2_8822B;
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO2_8822B);
*list = PINMUX_LIST_GPIO2_8822B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO2_8822B);
*gpio_id = HALMAC_GPIO2;
break;
case HALMAC_GPIO_FUNC_SW_IO_3:
*list = PIMUX_LIST_GPIO3_8822B;
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO3_8822B);
*list = PINMUX_LIST_GPIO3_8822B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO3_8822B);
*gpio_id = HALMAC_GPIO3;
break;
case HALMAC_GPIO_FUNC_SW_IO_4:
case HALMAC_GPIO_FUNC_SDIO_INT:
*list = PIMUX_LIST_GPIO4_8822B;
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO4_8822B);
*list = PINMUX_LIST_GPIO4_8822B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO4_8822B);
*gpio_id = HALMAC_GPIO4;
break;
case HALMAC_GPIO_FUNC_SW_IO_5:
*list = PIMUX_LIST_GPIO5_8822B;
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO5_8822B);
*list = PINMUX_LIST_GPIO5_8822B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO5_8822B);
*gpio_id = HALMAC_GPIO5;
break;
case HALMAC_GPIO_FUNC_SW_IO_6:
*list = PIMUX_LIST_GPIO6_8822B;
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO6_8822B);
*list = PINMUX_LIST_GPIO6_8822B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO6_8822B);
*gpio_id = HALMAC_GPIO6;
break;
case HALMAC_GPIO_FUNC_SW_IO_7:
*list = PIMUX_LIST_GPIO7_8822B;
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO7_8822B);
*list = PINMUX_LIST_GPIO7_8822B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO7_8822B);
*gpio_id = HALMAC_GPIO7;
break;
case HALMAC_GPIO_FUNC_SW_IO_8:
case HALMAC_GPIO_FUNC_WL_LED:
*list = PIMUX_LIST_GPIO8_8822B;
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO8_8822B);
*list = PINMUX_LIST_GPIO8_8822B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO8_8822B);
*gpio_id = HALMAC_GPIO8;
break;
case HALMAC_GPIO_FUNC_SW_IO_9:
*list = PIMUX_LIST_GPIO9_8822B;
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO9_8822B);
*list = PINMUX_LIST_GPIO9_8822B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO9_8822B);
*gpio_id = HALMAC_GPIO9;
break;
case HALMAC_GPIO_FUNC_SW_IO_10:
*list = PIMUX_LIST_GPIO10_8822B;
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO10_8822B);
*list = PINMUX_LIST_GPIO10_8822B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO10_8822B);
*gpio_id = HALMAC_GPIO10;
break;
case HALMAC_GPIO_FUNC_SW_IO_11:
*list = PIMUX_LIST_GPIO11_8822B;
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO11_8822B);
*list = PINMUX_LIST_GPIO11_8822B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO11_8822B);
*gpio_id = HALMAC_GPIO11;
break;
case HALMAC_GPIO_FUNC_SW_IO_12:
*list = PIMUX_LIST_GPIO12_8822B;
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO12_8822B);
*list = PINMUX_LIST_GPIO12_8822B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO12_8822B);
*gpio_id = HALMAC_GPIO12;
break;
case HALMAC_GPIO_FUNC_SW_IO_13:
*list = PIMUX_LIST_GPIO13_8822B;
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO13_8822B);
case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
*list = PINMUX_LIST_GPIO13_8822B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO13_8822B);
*gpio_id = HALMAC_GPIO13;
break;
case HALMAC_GPIO_FUNC_SW_IO_14:
*list = PIMUX_LIST_GPIO14_8822B;
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO14_8822B);
case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
*list = PINMUX_LIST_GPIO14_8822B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO14_8822B);
*gpio_id = HALMAC_GPIO14;
break;
case HALMAC_GPIO_FUNC_SW_IO_15:
*list = PIMUX_LIST_GPIO15_8822B;
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO15_8822B);
*list = PINMUX_LIST_GPIO15_8822B;
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO15_8822B);
*gpio_id = HALMAC_GPIO15;
break;
default:
@@ -786,10 +796,14 @@ chk_pinmux_valid_8822b(struct halmac_adapter *adapter,
status = HALMAC_RET_PINMUX_USED;
break;
case HALMAC_GPIO_FUNC_SW_IO_8:
case HALMAC_GPIO_FUNC_WL_LED:
if (info->sw_io_8 == 1 || info->wl_led == 1)
status = HALMAC_RET_PINMUX_USED;
break;
case HALMAC_GPIO_FUNC_WL_LED:
if (info->sw_io_8 == 1 || info->wl_led == 1 ||
info->bt_dev_wake == 1 || info->bt_host_wake == 1)
status = HALMAC_RET_PINMUX_USED;
break;
case HALMAC_GPIO_FUNC_SW_IO_9:
if (info->sw_io_9 == 1)
status = HALMAC_RET_PINMUX_USED;
@@ -807,11 +821,21 @@ chk_pinmux_valid_8822b(struct halmac_adapter *adapter,
status = HALMAC_RET_PINMUX_USED;
break;
case HALMAC_GPIO_FUNC_SW_IO_13:
if (info->sw_io_13 == 1)
if (info->sw_io_13 == 1 || info->bt_dev_wake == 1)
status = HALMAC_RET_PINMUX_USED;
break;
case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
if (info->sw_io_13 == 1 || info->bt_dev_wake == 1 ||
info->wl_led == 1)
status = HALMAC_RET_PINMUX_USED;
break;
case HALMAC_GPIO_FUNC_SW_IO_14:
if (info->sw_io_14 == 1)
if (info->sw_io_14 == 1 || info->bt_host_wake == 1)
status = HALMAC_RET_PINMUX_USED;
break;
case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
if (info->sw_io_14 == 1 || info->bt_host_wake == 1 ||
info->wl_led == 1)
status = HALMAC_RET_PINMUX_USED;
break;
case HALMAC_GPIO_FUNC_SW_IO_15:

305
hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.c
View File

@@ -15,9 +15,16 @@
#include "halmac_init_8822b.h"
#include "halmac_8822b_cfg.h"
#if HALMAC_PCIE_SUPPORT
#include "halmac_pcie_8822b.h"
#endif
#if HALMAC_SDIO_SUPPORT
#include "halmac_sdio_8822b.h"
#include "../halmac_sdio_88xx.h"
#endif
#if HALMAC_USB_SUPPORT
#include "halmac_usb_8822b.h"
#endif
#include "halmac_gpio_8822b.h"
#include "halmac_common_8822b.h"
#include "halmac_cfg_wmac_8822b.h"
@@ -26,6 +33,8 @@
#if HALMAC_8822B_SUPPORT
#define SYS_FUNC_EN 0xDC
#define RSVD_PG_DRV_NUM 16
#define RSVD_PG_H2C_EXTRAINFO_NUM 24
#define RSVD_PG_H2C_STATICINFO_NUM 8
@@ -33,7 +42,8 @@
#define RSVD_PG_CPU_INSTRUCTION_NUM 0
#define RSVD_PG_FW_TXBUF_NUM 4
#define RSVD_PG_CSIBUF_NUM 0
#define RSVD_PG_DLLB_NUM 32
#define RSVD_PG_DLLB_NUM (TX_FIFO_SIZE_8822B / 3 >> \
TX_PAGE_SIZE_SHIFT_88XX)
#define MAC_TRX_ENABLE (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \
BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \
@@ -41,6 +51,29 @@
#define BLK_DESC_NUM 0x3
#define WLAN_SLOT_TIME 0x09
#define WLAN_PIFS_TIME 0x19
#define WLAN_SIFS_CCK_CONT_TX 0xA
#define WLAN_SIFS_OFDM_CONT_TX 0xE
#define WLAN_SIFS_CCK_TRX 0x10
#define WLAN_SIFS_OFDM_TRX 0x10
#define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */
#define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */
#define WLAN_RDG_NAV 0x05
#define WLAN_TXOP_NAV 0x1B
#define WLAN_CCK_RX_TSF 0x30
#define WLAN_OFDM_RX_TSF 0x30
#define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
#define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
#define WLAN_DRV_EARLY_INT 0x04
#define WLAN_BCN_DMA_TIME 0x02
#define WLAN_RX_FILTER0 0x0FFFFFFF
#define WLAN_RX_FILTER2 0xFFFF
#define WLAN_RCR_CFG 0xE400220E
#define WLAN_RXPKT_MAX_SZ 12288
#define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9)
#define WLAN_AMPDU_MAX_TIME 0x70
#define WLAN_RTS_LEN_TH 0xFF
#define WLAN_RTS_TX_TIME_TH 0x08
@@ -53,9 +86,26 @@
#define WLAN_BAR_RETRY_LIMIT 0x01
#define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
#define WLAN_TX_FUNC_CFG1 0x30
#define WLAN_TX_FUNC_CFG2 0x30
#define WLAN_MAC_OPT_NORM_FUNC1 0x98
#define WLAN_MAC_OPT_LB_FUNC1 0x80
#define WLAN_MAC_OPT_FUNC2 0x30810041
#define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \
(WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
(WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
(WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
#define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
(WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
#define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
#define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
#if HALMAC_PLATFORM_WINDOWS
/*SDIO RQPN Mapping for Windows, extra queue is not implemented in Driver code*/
struct halmac_rqpn HALMAC_RQPN_SDIO_8822B[] = {
static struct halmac_rqpn HALMAC_RQPN_SDIO_8822B[] = {
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
{HALMAC_TRX_MODE_NORMAL,
HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
@@ -78,7 +128,7 @@ struct halmac_rqpn HALMAC_RQPN_SDIO_8822B[] = {
};
#else
/*SDIO RQPN Mapping*/
struct halmac_rqpn HALMAC_RQPN_SDIO_8822B[] = {
static struct halmac_rqpn HALMAC_RQPN_SDIO_8822B[] = {
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
{HALMAC_TRX_MODE_NORMAL,
HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
@@ -102,7 +152,7 @@ struct halmac_rqpn HALMAC_RQPN_SDIO_8822B[] = {
#endif
/*PCIE RQPN Mapping*/
struct halmac_rqpn HALMAC_RQPN_PCIE_8822B[] = {
static struct halmac_rqpn HALMAC_RQPN_PCIE_8822B[] = {
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
{HALMAC_TRX_MODE_NORMAL,
HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
@@ -125,7 +175,7 @@ struct halmac_rqpn HALMAC_RQPN_PCIE_8822B[] = {
};
/*USB 2 Bulkout RQPN Mapping*/
struct halmac_rqpn HALMAC_RQPN_2BULKOUT_8822B[] = {
static struct halmac_rqpn HALMAC_RQPN_2BULKOUT_8822B[] = {
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
{HALMAC_TRX_MODE_NORMAL,
HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ,
@@ -148,7 +198,7 @@ struct halmac_rqpn HALMAC_RQPN_2BULKOUT_8822B[] = {
};
/*USB 3 Bulkout RQPN Mapping*/
struct halmac_rqpn HALMAC_RQPN_3BULKOUT_8822B[] = {
static struct halmac_rqpn HALMAC_RQPN_3BULKOUT_8822B[] = {
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
{HALMAC_TRX_MODE_NORMAL,
HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
@@ -171,7 +221,7 @@ struct halmac_rqpn HALMAC_RQPN_3BULKOUT_8822B[] = {
};
/*USB 4 Bulkout RQPN Mapping*/
struct halmac_rqpn HALMAC_RQPN_4BULKOUT_8822B[] = {
static struct halmac_rqpn HALMAC_RQPN_4BULKOUT_8822B[] = {
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
{HALMAC_TRX_MODE_NORMAL,
HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
@@ -195,70 +245,70 @@ struct halmac_rqpn HALMAC_RQPN_4BULKOUT_8822B[] = {
#if HALMAC_PLATFORM_WINDOWS
/*SDIO Page Number*/
struct halmac_pg_num HALMAC_PG_NUM_SDIO_8822B[] = {
static struct halmac_pg_num HALMAC_PG_NUM_SDIO_8822B[] = {
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1},
{HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 0, 1},
{HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1},
{HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 640},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 640},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 1},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 1},
};
#else
/*SDIO Page Number*/
struct halmac_pg_num HALMAC_PG_NUM_SDIO_8822B[] = {
static struct halmac_pg_num HALMAC_PG_NUM_SDIO_8822B[] = {
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 32, 1},
{HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 1},
};
#endif
/*PCIE Page Number*/
struct halmac_pg_num HALMAC_PG_NUM_PCIE_8822B[] = {
static struct halmac_pg_num HALMAC_PG_NUM_PCIE_8822B[] = {
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 1},
};
/*USB 2 Bulkout Page Number*/
struct halmac_pg_num HALMAC_PG_NUM_2BULKOUT_8822B[] = {
static struct halmac_pg_num HALMAC_PG_NUM_2BULKOUT_8822B[] = {
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
{HALMAC_TRX_MODE_NORMAL, 64, 64, 0, 0, 1},
{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 0, 0, 1},
{HALMAC_TRX_MODE_WMM, 64, 64, 0, 0, 1},
{HALMAC_TRX_MODE_P2P, 64, 64, 0, 0, 1},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 0, 0, 1024},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 0, 0, 1024},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 0, 0, 1},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 0, 0, 1},
};
/*USB 3 Bulkout Page Number*/
struct halmac_pg_num HALMAC_PG_NUM_3BULKOUT_8822B[] = {
static struct halmac_pg_num HALMAC_PG_NUM_3BULKOUT_8822B[] = {
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1},
{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 0, 1},
{HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1},
{HALMAC_TRX_MODE_WMM, 256, 256, 256, 0, 1},
{HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 1024},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 1024},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 1},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 1},
};
/*USB 4 Bulkout Page Number*/
struct halmac_pg_num HALMAC_PG_NUM_4BULKOUT_8822B[] = {
static struct halmac_pg_num HALMAC_PG_NUM_4BULKOUT_8822B[] = {
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 1},
};
static enum halmac_ret_status
@@ -281,6 +331,7 @@ mount_api_8822b(struct halmac_adapter *adapter)
adapter->hw_cfg_info.efuse_size = EFUSE_SIZE_8822B;
adapter->hw_cfg_info.eeprom_size = EEPROM_SIZE_8822B;
adapter->hw_cfg_info.bt_efuse_size = BT_EFUSE_SIZE_8822B;
adapter->hw_cfg_info.prtct_efuse_size = PRTCT_EFUSE_SIZE_8822B;
adapter->hw_cfg_info.cam_entry_num = SEC_CAM_NUM_8822B;
adapter->hw_cfg_info.tx_fifo_size = TX_FIFO_SIZE_8822B;
adapter->hw_cfg_info.rx_fifo_size = RX_FIFO_SIZE_8822B;
@@ -290,6 +341,7 @@ mount_api_8822b(struct halmac_adapter *adapter)
adapter->txff_alloc.rsvd_drv_pg_num = RSVD_PG_DRV_NUM;
api->halmac_init_trx_cfg = init_trx_cfg_8822b;
api->halmac_init_system_cfg = init_system_cfg_8822b;
api->halmac_init_protocol_cfg = init_protocol_cfg_8822b;
api->halmac_init_h2c = init_h2c_8822b;
api->halmac_pinmux_get_func = pinmux_get_func_8822b;
@@ -300,8 +352,13 @@ mount_api_8822b(struct halmac_adapter *adapter)
api->halmac_cfg_drv_info = cfg_drv_info_8822b;
api->halmac_fill_txdesc_checksum = fill_txdesc_check_sum_8822b;
api->halmac_init_low_pwr = init_low_pwr_8822b;
api->halmac_pre_init_system_cfg = pre_init_system_cfg_8822b;
api->halmac_init_wmac_cfg = init_wmac_cfg_8822b;
api->halmac_init_edca_cfg = init_edca_cfg_8822b;
if (adapter->intf == HALMAC_INTERFACE_SDIO) {
#if HALMAC_SDIO_SUPPORT
api->halmac_mac_power_switch = mac_pwr_switch_sdio_8822b;
api->halmac_phy_cfg = phy_cfg_sdio_8822b;
api->halmac_pcie_switch = pcie_switch_sdio_8822b;
@@ -322,16 +379,22 @@ mount_api_8822b(struct halmac_adapter *adapter)
if (!adapter->sdio_fs.macid_map)
PLTFM_MSG_ERR("[ERR]allocate macid_map!!\n");
}
#endif
} else if (adapter->intf == HALMAC_INTERFACE_USB) {
#if HALMAC_USB_SUPPORT
api->halmac_mac_power_switch = mac_pwr_switch_usb_8822b;
api->halmac_phy_cfg = phy_cfg_usb_8822b;
api->halmac_pcie_switch = pcie_switch_usb_8822b;
api->halmac_interface_integration_tuning = intf_tun_usb_8822b;
#endif
} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
#if HALMAC_PCIE_SUPPORT
api->halmac_mac_power_switch = mac_pwr_switch_pcie_8822b;
api->halmac_phy_cfg = phy_cfg_pcie_8822b;
api->halmac_pcie_switch = pcie_switch_8822b;
api->halmac_interface_integration_tuning = intf_tun_pcie_8822b;
api->halmac_cfgspc_set_pcie = cfgspc_set_pcie_8822b;
#endif
} else {
PLTFM_MSG_ERR("[ERR]Undefined IC\n");
return HALMAC_RET_CHIP_NOT_SUPPORT;
@@ -625,6 +688,40 @@ set_trx_fifo_info_8822b(struct halmac_adapter *adapter,
return HALMAC_RET_SUCCESS;
}
/**
* init_system_cfg_8822b() - init system config
* @adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
init_system_cfg_8822b(struct halmac_adapter *adapter)
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
u32 tmp = 0;
u32 value32;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
value32 = HALMAC_REG_R32(REG_CPU_DMEM_CON) | BIT_WL_PLATFORM_RST;
HALMAC_REG_W32(REG_CPU_DMEM_CON, value32);
HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, SYS_FUNC_EN);
/*disable boot-from-flash for driver's DL FW*/
tmp = HALMAC_REG_R32(REG_MCUFW_CTRL);
if (tmp & BIT_BOOT_FSPI_EN) {
HALMAC_REG_W32(REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN));
value32 = HALMAC_REG_R32(REG_GPIO_MUXCFG) & (~BIT_FSPI_EN);
HALMAC_REG_W32(REG_GPIO_MUXCFG, value32);
}
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* init_protocol_cfg_8822b() - config protocol register
* @adapter : the adapter of halmac
@@ -643,7 +740,7 @@ init_protocol_cfg_8822b(struct halmac_adapter *adapter)
HALMAC_REG_W8_CLR(REG_SW_AMPDU_BURST_MODE_CTRL, BIT(6));
HALMAC_REG_W8(REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
HALMAC_REG_W8(REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
HALMAC_REG_W8_SET(REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
(WLAN_MAX_AGG_PKT_LIMIT << 16) |
@@ -721,4 +818,158 @@ init_h2c_8822b(struct halmac_adapter *adapter)
return HALMAC_RET_SUCCESS;
}
/**
* init_edca_cfg_8822b() - init EDCA config
* @adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
init_edca_cfg_8822b(struct halmac_adapter *adapter)
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
/* Init SYNC_CLI_SEL : reg 0x5B4[6:4] = 0 */
HALMAC_REG_W8_CLR(REG_TIMER0_SRC_SEL, BIT(4) | BIT(5) | BIT(6));
/* Clear TX pause */
HALMAC_REG_W16(REG_TXPAUSE, 0x0000);
HALMAC_REG_W8(REG_SLOT, WLAN_SLOT_TIME);
HALMAC_REG_W8(REG_PIFS, WLAN_PIFS_TIME);
HALMAC_REG_W32(REG_SIFS, WLAN_SIFS_CFG);
HALMAC_REG_W16(REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
HALMAC_REG_W16(REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
HALMAC_REG_W32(REG_RD_NAV_NXT, WLAN_NAV_CFG);
HALMAC_REG_W16(REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
/* Set beacon cotnrol - enable TSF and other related functions */
HALMAC_REG_W8(REG_BCN_CTRL, (u8)(HALMAC_REG_R8(REG_BCN_CTRL) |
BIT_EN_BCN_FUNCTION));
/* Set send beacon related registers */
HALMAC_REG_W32(REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
HALMAC_REG_W8(REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
HALMAC_REG_W8(REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
HALMAC_REG_W8_CLR(REG_TX_PTCL_CTRL + 1, BIT(4));
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* init_wmac_cfg_8822b() - init wmac config
* @adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
init_wmac_cfg_8822b(struct halmac_adapter *adapter)
{
u8 value8;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
HALMAC_REG_W32(REG_RXFLTMAP0, WLAN_RX_FILTER0);
HALMAC_REG_W16(REG_RXFLTMAP2, WLAN_RX_FILTER2);
HALMAC_REG_W32(REG_RCR, WLAN_RCR_CFG);
HALMAC_REG_W8(REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
HALMAC_REG_W8(REG_TCR + 2, WLAN_TX_FUNC_CFG2);
HALMAC_REG_W8(REG_TCR + 1, WLAN_TX_FUNC_CFG1);
HALMAC_REG_W32(REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
if (adapter->hw_cfg_info.trx_mode == HALMAC_TRNSFER_NORMAL)
value8 = WLAN_MAC_OPT_NORM_FUNC1;
else
value8 = WLAN_MAC_OPT_LB_FUNC1;
HALMAC_REG_W8(REG_WMAC_OPTION_FUNCTION + 4, value8);
status = api->halmac_init_low_pwr(adapter);
if (status != HALMAC_RET_SUCCESS)
return status;
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* pre_init_system_cfg_8822b() - pre-init system config
* @adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
pre_init_system_cfg_8822b(struct halmac_adapter *adapter)
{
u32 value32;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
u8 enable_bb;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
HALMAC_REG_W8(REG_RSV_CTRL, 0);
if (adapter->intf == HALMAC_INTERFACE_SDIO) {
#if HALMAC_SDIO_SUPPORT
if (leave_sdio_suspend_88xx(adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
#endif
} else if (adapter->intf == HALMAC_INTERFACE_USB) {
#if HALMAC_USB_SUPPORT
if (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20)
HALMAC_REG_W8(0xFE5B, HALMAC_REG_R8(0xFE5B) | BIT(4));
#endif
} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
#if HALMAC_PCIE_SUPPORT
/* For PCIE power on fail issue */
HALMAC_REG_W8(REG_HCI_OPT_CTRL + 1,
HALMAC_REG_R8(REG_HCI_OPT_CTRL + 1) | BIT(0));
#endif
}
/* Config PIN Mux */
value32 = HALMAC_REG_R32(REG_PAD_CTRL1);
value32 = value32 & (~(BIT(28) | BIT(29)));
value32 = value32 | BIT(28) | BIT(29);
HALMAC_REG_W32(REG_PAD_CTRL1, value32);
value32 = HALMAC_REG_R32(REG_LED_CFG);
value32 = value32 & (~(BIT(25) | BIT(26)));
HALMAC_REG_W32(REG_LED_CFG, value32);
value32 = HALMAC_REG_R32(REG_GPIO_MUXCFG);
value32 = value32 & (~(BIT(2)));
value32 = value32 | BIT(2);
HALMAC_REG_W32(REG_GPIO_MUXCFG, value32);
enable_bb = 0;
set_hw_value_88xx(adapter, HALMAC_HW_EN_BB_RF, &enable_bb);
if (HALMAC_REG_R8(REG_SYS_CFG1 + 2) & BIT(4)) {
PLTFM_MSG_ERR("[ERR]test mode!!\n");
return HALMAC_RET_WLAN_MODE_FAIL;
}
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
#endif /* HALMAC_8822B_SUPPORT */

12
hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.h
View File

@@ -26,12 +26,24 @@ mount_api_8822b(struct halmac_adapter *adapter);
enum halmac_ret_status
init_trx_cfg_8822b(struct halmac_adapter *adapter, enum halmac_trx_mode mode);
enum halmac_ret_status
init_system_cfg_8822b(struct halmac_adapter *adapter);
enum halmac_ret_status
init_protocol_cfg_8822b(struct halmac_adapter *adapter);
enum halmac_ret_status
init_h2c_8822b(struct halmac_adapter *adapter);
enum halmac_ret_status
init_edca_cfg_8822b(struct halmac_adapter *adapter);
enum halmac_ret_status
init_wmac_cfg_8822b(struct halmac_adapter *adapter);
enum halmac_ret_status
pre_init_system_cfg_8822b(struct halmac_adapter *adapter);
#endif /* HALMAC_8822B_SUPPORT */
#endif/* _HALMAC_INIT_8822B_H_ */

214
hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.c
View File

@@ -1,214 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "halmac_pcie_8822b.h"
#include "halmac_pwr_seq_8822b.h"
#include "../halmac_init_88xx.h"
#include "../halmac_common_88xx.h"
#include "../halmac_pcie_88xx.h"
#include "../halmac_88xx_cfg.h"
#if HALMAC_8822B_SUPPORT
/**
* mac_pwr_switch_pcie_8822b() - switch mac power
* @adapter : the adapter of halmac
* @pwr : power state
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
mac_pwr_switch_pcie_8822b(struct halmac_adapter *adapter,
enum halmac_mac_power pwr)
{
u8 value8;
u8 rpwm;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
enum halmac_ret_status status;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
PLTFM_MSG_TRACE("[TRACE]pwr = %x\n", pwr);
PLTFM_MSG_TRACE("[TRACE]8822B pwr seq ver = %s\n",
HALMAC_8822B_PWR_SEQ_VER);
adapter->rpwm = HALMAC_REG_R8(REG_PCIE_HRPWM1_V1);
/* Check FW still exist or not */
if (HALMAC_REG_R16(REG_MCUFW_CTRL) == 0xC078) {
/* Leave 32K */
rpwm = (u8)((adapter->rpwm ^ BIT(7)) & 0x80);
HALMAC_REG_W8(REG_PCIE_HRPWM1_V1, rpwm);
}
value8 = HALMAC_REG_R8(REG_CR);
if (value8 == 0xEA)
adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
else
adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
/* Check if power switch is needed */
if (pwr == HALMAC_MAC_POWER_ON &&
adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_ON) {
PLTFM_MSG_WARN("[WARN]power state unchange!!\n");
return HALMAC_RET_PWR_UNCHANGE;
}
if (pwr == HALMAC_MAC_POWER_OFF) {
status = trxdma_check_idle_88xx(adapter);
if (status != HALMAC_RET_SUCCESS)
return status;
if (pwr_seq_parser_88xx(adapter, card_dis_flow_8822b) !=
HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]Handle power off cmd error\n");
return HALMAC_RET_POWER_OFF_FAIL;
}
adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
init_adapter_dynamic_param_88xx(adapter);
} else {
if (pwr_seq_parser_88xx(adapter, card_en_flow_8822b) !=
HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]Handle power on cmd error\n");
return HALMAC_RET_POWER_ON_FAIL;
}
adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
}
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_pcie_switch_8822b() - pcie gen1/gen2 switch
* @adapter : the adapter of halmac
* @cfg : gen1/gen2 selection
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
pcie_switch_8822b(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg)
{
u8 value8;
u32 value32;
u8 speed = 0;
u32 cnt = 0;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (cfg == HALMAC_PCIE_GEN1) {
value8 = dbi_r8_88xx(adapter, LINK_CTRL2_REG_OFFSET) & 0xF0;
dbi_w8_88xx(adapter, LINK_CTRL2_REG_OFFSET, value8 | BIT(0));
value32 = dbi_r32_88xx(adapter, GEN2_CTRL_OFFSET);
dbi_w32_88xx(adapter, GEN2_CTRL_OFFSET, value32 | BIT(17));
speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET) & 0x0F;
cnt = 2000;
while ((speed != PCIE_GEN1_SPEED) && (cnt != 0)) {
PLTFM_DELAY_US(50);
speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET);
speed &= 0x0F;
cnt--;
}
if (speed != PCIE_GEN1_SPEED) {
PLTFM_MSG_ERR("[ERR]Speed change to GEN1 fail !\n");
return HALMAC_RET_FAIL;
}
} else if (cfg == HALMAC_PCIE_GEN2) {
value8 = dbi_r8_88xx(adapter, LINK_CTRL2_REG_OFFSET) & 0xF0;
dbi_w8_88xx(adapter, LINK_CTRL2_REG_OFFSET, value8 | BIT(1));
value32 = dbi_r32_88xx(adapter, GEN2_CTRL_OFFSET);
dbi_w32_88xx(adapter, GEN2_CTRL_OFFSET, value32 | BIT(17));
speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET) & 0x0F;
cnt = 2000;
while ((speed != PCIE_GEN2_SPEED) && (cnt != 0)) {
PLTFM_DELAY_US(50);
speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET);
speed &= 0x0F;
cnt--;
}
if (speed != PCIE_GEN2_SPEED) {
PLTFM_MSG_ERR("[ERR]Speed change to GEN1 fail !\n");
return HALMAC_RET_FAIL;
}
} else {
PLTFM_MSG_ERR("[ERR]Error Speed !\n");
return HALMAC_RET_FAIL;
}
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* phy_cfg_pcie_8822b() - phy config
* @adapter : the adapter of halmac
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
phy_cfg_pcie_8822b(struct halmac_adapter *adapter,
enum halmac_intf_phy_platform pltfm)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
status = parse_intf_phy_88xx(adapter, pcie_gen1_phy_param_8822b, pltfm,
HAL_INTF_PHY_PCIE_GEN1);
if (status != HALMAC_RET_SUCCESS)
return status;
status = parse_intf_phy_88xx(adapter, pcie_gen2_phy_param_8822b, pltfm,
HAL_INTF_PHY_PCIE_GEN2);
if (status != HALMAC_RET_SUCCESS)
return status;
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* intf_tun_pcie_8822b() - pcie interface fine tuning
* @adapter : the adapter of halmac
* Author : Rick Liu
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
intf_tun_pcie_8822b(struct halmac_adapter *adapter)
{
return HALMAC_RET_SUCCESS;
}
#endif /* HALMAC_8822B_SUPPORT*/

42
hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.h
View File

@@ -1,42 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _HALMAC_API_8822B_PCIE_H_
#define _HALMAC_API_8822B_PCIE_H_
#include "../../halmac_api.h"
#if HALMAC_8822B_SUPPORT
extern struct halmac_intf_phy_para pcie_gen1_phy_param_8822b[];
extern struct halmac_intf_phy_para pcie_gen2_phy_param_8822b[];
enum halmac_ret_status
mac_pwr_switch_pcie_8822b(struct halmac_adapter *adapter,
enum halmac_mac_power pwr);
enum halmac_ret_status
pcie_switch_8822b(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg);
enum halmac_ret_status
phy_cfg_pcie_8822b(struct halmac_adapter *adapter,
enum halmac_intf_phy_platform pltfm);
enum halmac_ret_status
intf_tun_pcie_8822b(struct halmac_adapter *adapter);
#endif /* HALMAC_8822B_SUPPORT*/
#endif/* _HALMAC_API_8822B_PCIE_H_ */

10
hal/halmac/halmac_88xx/halmac_8822b/halmac_phy_8822b.c
View File

@@ -14,6 +14,12 @@
******************************************************************************/
#include "../../halmac_type.h"
#if HALMAC_USB_SUPPORT
#include "halmac_usb_8822b.h"
#endif
#if HALMAC_PCIE_SUPPORT
#include "halmac_pcie_8822b.h"
#endif
/**
* ============ip sel item list============
@@ -39,7 +45,7 @@ struct halmac_intf_phy_para usb2_phy_param_8822b[] = {
HALMAC_INTF_PHY_PLATFORM_ALL},
};
struct halmac_intf_phy_para usb3_phy_8822b[] = {
struct halmac_intf_phy_para usb3_phy_param_8822b[] = {
/* {offset, value, ip sel, cut mask, platform mask} */
{0x0001, 0xA841,
HALMAC_IP_INTF_PHY,
@@ -147,4 +153,4 @@ struct halmac_intf_phy_para pcie_gen2_phy_param_8822b[] = {
HALMAC_INTF_PHY_PLATFORM_ALL},
};
#endif /* HALMAC_8822B_SUPPORT*/
#endif /* HALMAC_8822B_SUPPORT */

100
hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.c
View File

@@ -17,7 +17,7 @@
#if HALMAC_8822B_SUPPORT
struct halmac_wlan_pwr_cfg TRANS_CARDDIS_TO_CARDEMU_8822B[] = {
static struct halmac_wlan_pwr_cfg TRANS_CARDDIS_TO_CARDEMU_8822B[] = {
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
{0x0086,
HALMAC_PWR_CUT_ALL_MSK,
@@ -56,7 +56,7 @@ struct halmac_wlan_pwr_cfg TRANS_CARDDIS_TO_CARDEMU_8822B[] = {
HALMAC_PWR_CMD_END, 0, 0},
};
struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_ACT_8822B[] = {
static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_ACT_8822B[] = {
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
{0x0012,
HALMAC_PWR_CUT_ALL_MSK,
@@ -190,7 +190,7 @@ struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_ACT_8822B[] = {
HALMAC_PWR_CMD_END, 0, 0},
};
struct halmac_wlan_pwr_cfg TRANS_ACT_TO_CARDEMU_8822B[] = {
static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_CARDEMU_8822B[] = {
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
{0x0003,
HALMAC_PWR_CUT_ALL_MSK,
@@ -264,7 +264,7 @@ struct halmac_wlan_pwr_cfg TRANS_ACT_TO_CARDEMU_8822B[] = {
HALMAC_PWR_CMD_END, 0, 0},
};
struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_CARDDIS_8822B[] = {
static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_CARDDIS_8822B[] = {
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
{0x0005,
HALMAC_PWR_CUT_ALL_MSK,
@@ -281,11 +281,6 @@ struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_CARDDIS_8822B[] = {
HALMAC_PWR_INTF_ALL_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(5), 0},
{0x0005,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
{0x0005,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK,
@@ -340,7 +335,12 @@ struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_CARDDIS_8822B[] = {
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(7), 0},
HALMAC_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
{0x0005,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
{0x0086,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK,
@@ -399,7 +399,7 @@ struct halmac_wlan_pwr_cfg *card_dis_flow_8822b[] = {
#if HALMAC_PLATFORM_TESTPROGRAM
struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_SUS_8822B[] = {
static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_SUS_8822B[] = {
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
{0x0005,
HALMAC_PWR_CUT_ALL_MSK,
@@ -438,8 +438,18 @@ struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_SUS_8822B[] = {
HALMAC_PWR_CMD_END, 0, 0},
};
struct halmac_wlan_pwr_cfg TRANS_SUS_TO_CARDEMU_8822B[] = {
static struct halmac_wlan_pwr_cfg TRANS_SUS_TO_CARDEMU_8822B[] = {
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
{0xFF0A,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0},
{0xFF0B,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0},
{0x0005,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK,
@@ -467,7 +477,7 @@ struct halmac_wlan_pwr_cfg TRANS_SUS_TO_CARDEMU_8822B[] = {
HALMAC_PWR_CMD_END, 0, 0},
};
struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_PDN_8822B[] = {
static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_PDN_8822B[] = {
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
{0x0007,
HALMAC_PWR_CUT_ALL_MSK,
@@ -491,7 +501,7 @@ struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_PDN_8822B[] = {
HALMAC_PWR_CMD_END, 0, 0},
};
struct halmac_wlan_pwr_cfg TRANS_PDN_TO_CARDEMU_8822B[] = {
static struct halmac_wlan_pwr_cfg TRANS_PDN_TO_CARDEMU_8822B[] = {
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
{0x0005,
HALMAC_PWR_CUT_ALL_MSK,
@@ -505,7 +515,7 @@ struct halmac_wlan_pwr_cfg TRANS_PDN_TO_CARDEMU_8822B[] = {
HALMAC_PWR_CMD_END, 0, 0},
};
struct halmac_wlan_pwr_cfg TRANS_ACT_TO_LPS_8822B[] = {
static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_LPS_8822B[] = {
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
{0x0101,
HALMAC_PWR_CUT_ALL_MSK,
@@ -534,14 +544,34 @@ struct halmac_wlan_pwr_cfg TRANS_ACT_TO_LPS_8822B[] = {
HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0093,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0x42},
HALMAC_PWR_CMD_WRITE, 0xFF, 0xDE},
{0x0092,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
HALMAC_PWR_CMD_WRITE, 0xFF, 0x60},
{0x0093,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0x9B},
{0x0092,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0x60},
{0x0093,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0xA},
{0x0092,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0x60},
{0x0090,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK,
@@ -629,7 +659,7 @@ struct halmac_wlan_pwr_cfg TRANS_ACT_TO_LPS_8822B[] = {
HALMAC_PWR_CMD_END, 0, 0},
};
struct halmac_wlan_pwr_cfg TRANS_ACT_TO_DEEP_LPS_8822B[] = {
static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_DEEP_LPS_8822B[] = {
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
{0x0101,
HALMAC_PWR_CUT_ALL_MSK,
@@ -658,14 +688,34 @@ struct halmac_wlan_pwr_cfg TRANS_ACT_TO_DEEP_LPS_8822B[] = {
HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
{0x0093,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0x40},
HALMAC_PWR_CMD_WRITE, 0xFF, 0xDE},
{0x0092,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
HALMAC_PWR_CMD_WRITE, 0xFF, 0x60},
{0x0093,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0x9B},
{0x0092,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0x60},
{0x0093,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0xA},
{0x0092,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_ADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF, 0x60},
{0x0090,
HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK,
@@ -753,7 +803,7 @@ struct halmac_wlan_pwr_cfg TRANS_ACT_TO_DEEP_LPS_8822B[] = {
HALMAC_PWR_CMD_END, 0, 0},
};
struct halmac_wlan_pwr_cfg TRANS_LPS_TO_ACT_8822B[] = {
static struct halmac_wlan_pwr_cfg TRANS_LPS_TO_ACT_8822B[] = {
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
{0x0080,
HALMAC_PWR_CUT_ALL_MSK,

2
hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.h
View File

@@ -21,7 +21,7 @@
#if HALMAC_8822B_SUPPORT
#define HALMAC_8822B_PWR_SEQ_VER "V24"
#define HALMAC_8822B_PWR_SEQ_VER "V30"
extern struct halmac_wlan_pwr_cfg *card_en_flow_8822b[];
extern struct halmac_wlan_pwr_cfg *card_dis_flow_8822b[];

868
hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.c
View File

@@ -1,868 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "halmac_sdio_8822b.h"
#include "halmac_pwr_seq_8822b.h"
#include "../halmac_init_88xx.h"
#include "../halmac_common_88xx.h"
#include "../halmac_sdio_88xx.h"
#if HALMAC_8822B_SUPPORT
#define WLAN_ACQ_NUM_MAX 8
static enum halmac_ret_status
chk_oqt_8822b(struct halmac_adapter *adapter, u32 tx_agg_num, u8 *buf,
u8 macid_cnt);
static enum halmac_ret_status
update_oqt_free_space_8822b(struct halmac_adapter *adapter);
static enum halmac_ret_status
update_sdio_free_page_8822b(struct halmac_adapter *adapter);
static enum halmac_ret_status
chk_qsel_8822b(struct halmac_adapter *adapter, u8 qsel_first, u8 *pkt,
u8 *macid_cnt);
static enum halmac_ret_status
chk_dma_mapping_8822b(struct halmac_adapter *adapter, u16 **cur_fs,
u8 qsel_first);
static enum halmac_ret_status
chk_rqd_page_num_8822b(struct halmac_adapter *adapter, u8 *buf, u32 *rqd_pg_num,
u16 **cur_fs, u8 *macid_cnt, u32 tx_agg_num);
/**
* mac_pwr_switch_sdio_8822b() - switch mac power
* @adapter : the adapter of halmac
* @pwr : power state
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
mac_pwr_switch_sdio_8822b(struct halmac_adapter *adapter,
enum halmac_mac_power pwr)
{
u8 value8;
u8 rpwm;
u32 imr_backup;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
PLTFM_MSG_TRACE("[TRACE]8822B pwr seq ver = %s\n",
HALMAC_8822B_PWR_SEQ_VER);
adapter->rpwm = HALMAC_REG_R8(REG_SDIO_HRPWM1);
/* Check FW still exist or not */
if (HALMAC_REG_R16(REG_MCUFW_CTRL) == 0xC078) {
/* Leave 32K */
rpwm = (u8)((adapter->rpwm ^ BIT(7)) & 0x80);
HALMAC_REG_W8(REG_SDIO_HRPWM1, rpwm);
}
value8 = HALMAC_REG_R8(REG_CR);
if (value8 == 0xEA)
adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
else
adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
/*Check if power switch is needed*/
if (pwr == HALMAC_MAC_POWER_ON &&
adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_ON) {
PLTFM_MSG_WARN("[WARN]power state unchange!!\n");
return HALMAC_RET_PWR_UNCHANGE;
}
imr_backup = HALMAC_REG_R32(REG_SDIO_HIMR);
HALMAC_REG_W32(REG_SDIO_HIMR, 0);
if (pwr == HALMAC_MAC_POWER_OFF) {
adapter->pwr_off_flow_flag = 1;
if (pwr_seq_parser_88xx(adapter, card_dis_flow_8822b) !=
HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]Handle power off cmd error\n");
HALMAC_REG_W32(REG_SDIO_HIMR, imr_backup);
return HALMAC_RET_POWER_OFF_FAIL;
}
adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
adapter->pwr_off_flow_flag = 0;
init_adapter_dynamic_param_88xx(adapter);
} else {
if (pwr_seq_parser_88xx(adapter, card_en_flow_8822b) !=
HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]Handle power on cmd error\n");
HALMAC_REG_W32(REG_SDIO_HIMR, imr_backup);
return HALMAC_RET_POWER_ON_FAIL;
}
adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
}
HALMAC_REG_W32(REG_SDIO_HIMR, imr_backup);
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_tx_allowed_sdio_88xx() - check tx status
* @adapter : the adapter of halmac
* @buf : tx packet, include txdesc
* @size : tx packet size, include txdesc
* Author : Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
tx_allowed_sdio_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size)
{
u16 *cur_fs = NULL;
u32 cnt;
u32 tx_agg_num;
u32 rqd_pg_num = 0;
u8 macid_cnt = 0;
struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (!fs_info->macid_map) {
PLTFM_MSG_ERR("[ERR]halmac allocate Macid_map Fail!!\n");
return HALMAC_RET_MALLOC_FAIL;
}
PLTFM_MEMSET(fs_info->macid_map, 0x00, fs_info->macid_map_size);
tx_agg_num = GET_TX_DESC_DMA_TXAGG_NUM(buf);
tx_agg_num = (tx_agg_num == 0) ? 1 : tx_agg_num;
status = chk_rqd_page_num_8822b(adapter, buf, &rqd_pg_num, &cur_fs,
&macid_cnt, tx_agg_num);
if (status != HALMAC_RET_SUCCESS)
return status;
cnt = 10;
do {
if ((u32)(*cur_fs + fs_info->pubq_pg_num) > rqd_pg_num) {
status = chk_oqt_8822b(adapter, tx_agg_num, buf,
macid_cnt);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_WARN("[WARN]oqt buffer full!!\n");
return status;
}
if (*cur_fs >= rqd_pg_num) {
*cur_fs -= (u16)rqd_pg_num;
} else {
fs_info->pubq_pg_num -=
(u16)(rqd_pg_num - *cur_fs);
*cur_fs = 0;
}
break;
}
update_sdio_free_page_8822b(adapter);
cnt--;
if (cnt == 0)
return HALMAC_RET_FREE_SPACE_NOT_ENOUGH;
} while (1);
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_8_sdio_88xx() - read 1byte register
* @adapter : the adapter of halmac
* @offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u8
reg_r8_sdio_8822b(struct halmac_adapter *adapter, u32 offset)
{
u8 value8;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if ((offset & 0xFFFF0000) == 0) {
value8 = (u8)r_indir_sdio_88xx(adapter, offset, HALMAC_IO_BYTE);
} else {
status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]convert offset\n");
return status;
}
value8 = PLTFM_SDIO_CMD52_R(offset);
}
return value8;
}
/**
* halmac_reg_write_8_sdio_88xx() - write 1byte register
* @adapter : the adapter of halmac
* @offset : register offset
* @value : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
reg_w8_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u8 value)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if ((offset & 0xFFFF0000) == 0)
offset |= WLAN_IOREG_OFFSET;
status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]convert offset\n");
return status;
}
PLTFM_SDIO_CMD52_W(offset, value);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_16_sdio_88xx() - read 2byte register
* @adapter : the adapter of halmac
* @offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u16
reg_r16_sdio_8822b(struct halmac_adapter *adapter, u32 offset)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
union {
u16 word;
u8 byte[2];
} value16 = { 0x0000 };
if ((offset & 0xFFFF0000) == 0)
return (u16)r_indir_sdio_88xx(adapter, offset, HALMAC_IO_WORD);
status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]convert offset\n");
return status;
}
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF ||
((offset & (2 - 1)) != 0) ||
adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_RW ||
adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_R) {
value16.byte[0] = PLTFM_SDIO_CMD52_R(offset);
value16.byte[1] = PLTFM_SDIO_CMD52_R(offset + 1);
value16.word = rtk_le16_to_cpu(value16.word);
} else {
value16.word = PLTFM_SDIO_CMD53_R16(offset);
}
return value16.word;
}
/**
* halmac_reg_write_16_sdio_88xx() - write 2byte register
* @adapter : the adapter of halmac
* @offset : register offset
* @value : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
reg_w16_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u16 value)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF ||
((offset & (2 - 1)) != 0) ||
adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_RW ||
adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_W) {
if ((offset & 0xFFFF0000) == 0 && ((offset & (2 - 1)) == 0)) {
status = w_indir_sdio_88xx(adapter, offset, value,
HALMAC_IO_WORD);
} else {
if ((offset & 0xFFFF0000) == 0)
offset |= WLAN_IOREG_OFFSET;
status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]convert offset\n");
return status;
}
PLTFM_SDIO_CMD52_W(offset, (u8)(value & 0xFF));
PLTFM_SDIO_CMD52_W(offset + 1,
(u8)((value & 0xFF00) >> 8));
}
} else {
if ((offset & 0xFFFF0000) == 0)
offset |= WLAN_IOREG_OFFSET;
status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]convert offset\n");
return status;
}
PLTFM_SDIO_CMD53_W16(offset, value);
}
return status;
}
/**
* halmac_reg_read_32_sdio_88xx() - read 4byte register
* @adapter : the adapter of halmac
* @offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u32
reg_r32_sdio_8822b(struct halmac_adapter *adapter, u32 offset)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
union {
u32 dword;
u8 byte[4];
} value32 = { 0x00000000 };
if ((offset & 0xFFFF0000) == 0)
return r_indir_sdio_88xx(adapter, offset, HALMAC_IO_DWORD);
status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]convert offset\n");
return status;
}
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF ||
(offset & (4 - 1)) != 0) {
value32.byte[0] = PLTFM_SDIO_CMD52_R(offset);
value32.byte[1] = PLTFM_SDIO_CMD52_R(offset + 1);
value32.byte[2] = PLTFM_SDIO_CMD52_R(offset + 2);
value32.byte[3] = PLTFM_SDIO_CMD52_R(offset + 3);
value32.dword = rtk_le32_to_cpu(value32.dword);
} else {
value32.dword = PLTFM_SDIO_CMD53_R32(offset);
}
return value32.dword;
}
/**
* halmac_reg_write_32_sdio_88xx() - write 4byte register
* @adapter : the adapter of halmac
* @offset : register offset
* @value : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
reg_w32_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u32 value)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF ||
(offset & (4 - 1)) != 0) {
if ((offset & 0xFFFF0000) == 0 && ((offset & (4 - 1)) == 0)) {
status = w_indir_sdio_88xx(adapter, offset, value,
HALMAC_IO_DWORD);
} else {
if ((offset & 0xFFFF0000) == 0)
offset |= WLAN_IOREG_OFFSET;
status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]convert offset\n");
return status;
}
PLTFM_SDIO_CMD52_W(offset, (u8)(value & 0xFF));
PLTFM_SDIO_CMD52_W(offset + 1,
(u8)((value >> 8) & 0xFF));
PLTFM_SDIO_CMD52_W(offset + 2,
(u8)((value >> 16) & 0xFF));
PLTFM_SDIO_CMD52_W(offset + 3,
(u8)((value >> 24) & 0xFF));
}
} else {
if ((offset & 0xFFFF0000) == 0)
offset |= WLAN_IOREG_OFFSET;
status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]convert offset\n");
return status;
}
PLTFM_SDIO_CMD53_W32(offset, value);
}
return status;
}
static enum halmac_ret_status
chk_oqt_8822b(struct halmac_adapter *adapter, u32 tx_agg_num, u8 *buf,
u8 macid_cnt)
{
u32 cnt = 10;
struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
/*S0, S1 are not allowed to use, 0x4E4[0] should be 0. Soar 20160323*/
/*no need to check non_ac_oqt_number*/
/*HI and MGQ blocked will cause protocal issue before H_OQT being full*/
switch ((enum halmac_qsel)GET_TX_DESC_QSEL(buf)) {
case HALMAC_QSEL_VO:
case HALMAC_QSEL_VO_V2:
case HALMAC_QSEL_VI:
case HALMAC_QSEL_VI_V2:
case HALMAC_QSEL_BE:
case HALMAC_QSEL_BE_V2:
case HALMAC_QSEL_BK:
case HALMAC_QSEL_BK_V2:
if (macid_cnt > WLAN_ACQ_NUM_MAX &&
tx_agg_num > OQT_ENTRY_AC_8822B) {
PLTFM_MSG_WARN("[WARN]txagg num %d > oqt entry\n",
tx_agg_num);
PLTFM_MSG_WARN("[WARN]macid cnt %d > acq max\n",
macid_cnt);
}
cnt = 10;
do {
if (fs_info->ac_empty >= macid_cnt) {
fs_info->ac_empty -= macid_cnt;
break;
}
if (fs_info->ac_oqt_num >= tx_agg_num) {
fs_info->ac_empty = 0;
fs_info->ac_oqt_num -= (u8)tx_agg_num;
break;
}
update_oqt_free_space_8822b(adapter);
cnt--;
if (cnt == 0)
return HALMAC_RET_OQT_NOT_ENOUGH;
} while (1);
break;
case HALMAC_QSEL_MGNT:
case HALMAC_QSEL_HIGH:
if (tx_agg_num > OQT_ENTRY_NOAC_8822B)
PLTFM_MSG_WARN("[WARN]tx_agg_num %d > oqt entry\n",
tx_agg_num, OQT_ENTRY_NOAC_8822B);
cnt = 10;
do {
if (fs_info->non_ac_oqt_num >= tx_agg_num) {
fs_info->non_ac_oqt_num -= (u8)tx_agg_num;
break;
}
update_oqt_free_space_8822b(adapter);
cnt--;
if (cnt == 0)
return HALMAC_RET_OQT_NOT_ENOUGH;
} while (1);
break;
default:
break;
}
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
update_oqt_free_space_8822b(struct halmac_adapter *adapter)
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
u8 value;
u32 oqt_free_page;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
oqt_free_page = HALMAC_REG_R32(REG_SDIO_OQT_FREE_TXPG_V1);
fs_info->ac_oqt_num = (u8)BIT_GET_AC_OQT_FREEPG_V1(oqt_free_page);
fs_info->non_ac_oqt_num = (u8)BIT_GET_NOAC_OQT_FREEPG_V1(oqt_free_page);
fs_info->ac_empty = 0;
if (fs_info->ac_oqt_num == OQT_ENTRY_AC_8822B) {
value = HALMAC_REG_R8(REG_TXPKT_EMPTY);
while (value > 0) {
value = value & (value - 1);
fs_info->ac_empty++;
};
} else {
PLTFM_MSG_TRACE("[TRACE]free_space->ac_oqt_num %d != %d\n",
fs_info->ac_oqt_num, OQT_ENTRY_AC_8822B);
}
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
update_sdio_free_page_8822b(struct halmac_adapter *adapter)
{
u32 free_page = 0;
u32 free_page2 = 0;
u32 free_page3 = 0;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
u8 data[12] = {0};
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
HALMAC_REG_SDIO_RN(REG_SDIO_FREE_TXPG, 12, data);
free_page = rtk_le32_to_cpu(*(u32 *)(data + 0));
free_page2 = rtk_le32_to_cpu(*(u32 *)(data + 4));
free_page3 = rtk_le32_to_cpu(*(u32 *)(data + 8));
fs_info->hiq_pg_num = (u16)BIT_GET_HIQ_FREEPG_V1(free_page);
fs_info->miq_pg_num = (u16)BIT_GET_MID_FREEPG_V1(free_page);
fs_info->lowq_pg_num = (u16)BIT_GET_LOW_FREEPG_V1(free_page2);
fs_info->pubq_pg_num = (u16)BIT_GET_PUB_FREEPG_V1(free_page2);
fs_info->exq_pg_num = (u16)BIT_GET_EXQ_FREEPG_V1(free_page3);
fs_info->ac_oqt_num = (u8)BIT_GET_AC_OQT_FREEPG_V1(free_page3);
fs_info->non_ac_oqt_num = (u8)BIT_GET_NOAC_OQT_FREEPG_V1(free_page3);
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* phy_cfg_sdio_8822b() - phy config
* @adapter : the adapter of halmac
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
phy_cfg_sdio_8822b(struct halmac_adapter *adapter,
enum halmac_intf_phy_platform pltfm)
{
return HALMAC_RET_SUCCESS;
}
/**
* halmac_pcie_switch_8821c() - pcie gen1/gen2 switch
* @adapter : the adapter of halmac
* @cfg : gen1/gen2 selection
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
pcie_switch_sdio_8822b(struct halmac_adapter *adapter,
enum halmac_pcie_cfg cfg)
{
return HALMAC_RET_NOT_SUPPORT;
}
/**
* intf_tun_sdio_8822b() - sdio interface fine tuning
* @adapter : the adapter of halmac
* Author : Ivan
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
intf_tun_sdio_8822b(struct halmac_adapter *adapter)
{
return HALMAC_RET_SUCCESS;
}
/**
* halmac_get_sdio_tx_addr_sdio_88xx() - get CMD53 addr for the TX packet
* @adapter : the adapter of halmac
* @buf : tx packet, include txdesc
* @size : tx packet size
* @cmd53_addr : cmd53 addr value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
get_sdio_tx_addr_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size,
u32 *cmd53_addr)
{
u32 len_unit4;
enum halmac_qsel queue_sel;
enum halmac_dma_mapping dma_mapping;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (!buf) {
PLTFM_MSG_ERR("[ERR]buf is NULL!!\n");
return HALMAC_RET_DATA_BUF_NULL;
}
if (size == 0) {
PLTFM_MSG_ERR("[ERR]size is 0!!\n");
return HALMAC_RET_DATA_SIZE_INCORRECT;
}
queue_sel = (enum halmac_qsel)GET_TX_DESC_QSEL(buf);
switch (queue_sel) {
case HALMAC_QSEL_VO:
case HALMAC_QSEL_VO_V2:
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VO];
break;
case HALMAC_QSEL_VI:
case HALMAC_QSEL_VI_V2:
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VI];
break;
case HALMAC_QSEL_BE:
case HALMAC_QSEL_BE_V2:
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BE];
break;
case HALMAC_QSEL_BK:
case HALMAC_QSEL_BK_V2:
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BK];
break;
case HALMAC_QSEL_MGNT:
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_MG];
break;
case HALMAC_QSEL_HIGH:
case HALMAC_QSEL_BCN:
case HALMAC_QSEL_CMD:
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_HI];
break;
default:
PLTFM_MSG_ERR("[ERR]Qsel is out of range\n");
return HALMAC_RET_QSEL_INCORRECT;
}
len_unit4 = (size >> 2) + ((size & (4 - 1)) ? 1 : 0);
switch (dma_mapping) {
case HALMAC_DMA_MAPPING_HIGH:
*cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_HIGH;
break;
case HALMAC_DMA_MAPPING_NORMAL:
*cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL;
break;
case HALMAC_DMA_MAPPING_LOW:
*cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_LOW;
break;
case HALMAC_DMA_MAPPING_EXTRA:
*cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA;
break;
default:
PLTFM_MSG_ERR("[ERR]DmaMapping is out of range\n");
return HALMAC_RET_DMA_MAP_INCORRECT;
}
*cmd53_addr = (*cmd53_addr << 13) |
(len_unit4 & HALMAC_SDIO_4BYTE_LEN_MASK);
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
chk_qsel_8822b(struct halmac_adapter *adapter, u8 qsel_first, u8 *pkt,
u8 *macid_cnt)
{
u8 flag = 0;
u8 qsel_now;
u8 macid;
struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
macid = (u8)GET_TX_DESC_MACID(pkt);
qsel_now = (u8)GET_TX_DESC_QSEL(pkt);
if (qsel_first == qsel_now) {
if (*(fs_info->macid_map + macid) == 0) {
*(fs_info->macid_map + macid) = 1;
(*macid_cnt)++;
}
} else {
switch ((enum halmac_qsel)qsel_now) {
case HALMAC_QSEL_VO:
if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VO_V2)
flag = 1;
break;
case HALMAC_QSEL_VO_V2:
if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VO)
flag = 1;
break;
case HALMAC_QSEL_VI:
if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VI_V2)
flag = 1;
break;
case HALMAC_QSEL_VI_V2:
if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VI)
flag = 1;
break;
case HALMAC_QSEL_BE:
if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BE_V2)
flag = 1;
break;
case HALMAC_QSEL_BE_V2:
if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BE)
flag = 1;
break;
case HALMAC_QSEL_BK:
if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BK_V2)
flag = 1;
break;
case HALMAC_QSEL_BK_V2:
if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BK)
flag = 1;
break;
case HALMAC_QSEL_MGNT:
case HALMAC_QSEL_HIGH:
case HALMAC_QSEL_BCN:
case HALMAC_QSEL_CMD:
flag = 1;
break;
default:
PLTFM_MSG_ERR("[ERR]Qsel is out of range\n");
return HALMAC_RET_QSEL_INCORRECT;
}
if (flag == 1) {
PLTFM_MSG_ERR("[ERR]Multi-Qsel is not allowed\n");
PLTFM_MSG_ERR("[ERR]qsel = %d, %d\n",
qsel_first, qsel_now);
return HALMAC_RET_QSEL_INCORRECT;
}
if (*(fs_info->macid_map + macid + MACID_MAX_8822B) == 0) {
*(fs_info->macid_map + macid + MACID_MAX_8822B) = 1;
(*macid_cnt)++;
}
}
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
chk_dma_mapping_8822b(struct halmac_adapter *adapter, u16 **cur_fs,
u8 qsel_first)
{
enum halmac_dma_mapping dma_mapping;
switch ((enum halmac_qsel)qsel_first) {
case HALMAC_QSEL_VO:
case HALMAC_QSEL_VO_V2:
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VO];
break;
case HALMAC_QSEL_VI:
case HALMAC_QSEL_VI_V2:
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VI];
break;
case HALMAC_QSEL_BE:
case HALMAC_QSEL_BE_V2:
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BE];
break;
case HALMAC_QSEL_BK:
case HALMAC_QSEL_BK_V2:
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BK];
break;
case HALMAC_QSEL_MGNT:
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_MG];
break;
case HALMAC_QSEL_HIGH:
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_HI];
break;
case HALMAC_QSEL_BCN:
case HALMAC_QSEL_CMD:
return HALMAC_RET_SUCCESS;
default:
PLTFM_MSG_ERR("[ERR]Qsel is out of range: %d\n", qsel_first);
return HALMAC_RET_QSEL_INCORRECT;
}
switch (dma_mapping) {
case HALMAC_DMA_MAPPING_HIGH:
*cur_fs = &adapter->sdio_fs.hiq_pg_num;
break;
case HALMAC_DMA_MAPPING_NORMAL:
*cur_fs = &adapter->sdio_fs.miq_pg_num;
break;
case HALMAC_DMA_MAPPING_LOW:
*cur_fs = &adapter->sdio_fs.lowq_pg_num;
break;
case HALMAC_DMA_MAPPING_EXTRA:
*cur_fs = &adapter->sdio_fs.exq_pg_num;
break;
default:
PLTFM_MSG_ERR("[ERR]DmaMapping is out of range\n");
return HALMAC_RET_DMA_MAP_INCORRECT;
}
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
chk_rqd_page_num_8822b(struct halmac_adapter *adapter, u8 *buf, u32 *rqd_pg_num,
u16 **cur_fs, u8 *macid_cnt, u32 tx_agg_num)
{
u8 *pkt;
u8 qsel_first;
u32 i;
u32 pkt_size;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
pkt = buf;
qsel_first = (u8)GET_TX_DESC_QSEL(pkt);
status = chk_dma_mapping_8822b(adapter, cur_fs, qsel_first);
if (status != HALMAC_RET_SUCCESS)
return status;
for (i = 0; i < tx_agg_num; i++) {
/*QSEL parser*/
status = chk_qsel_8822b(adapter, qsel_first, pkt, macid_cnt);
if (status != HALMAC_RET_SUCCESS)
return status;
/*Page number parser*/
pkt_size = GET_TX_DESC_TXPKTSIZE(pkt) + GET_TX_DESC_OFFSET(pkt);
*rqd_pg_num += (pkt_size >> TX_PAGE_SIZE_SHIFT_88XX) +
((pkt_size & (TX_PAGE_SIZE_88XX - 1)) ? 1 : 0);
pkt += HALMAC_ALIGN(GET_TX_DESC_TXPKTSIZE(pkt) +
(GET_TX_DESC_PKT_OFFSET(pkt) << 3) +
TX_DESC_SIZE_88XX, 8);
}
return HALMAC_RET_SUCCESS;
}
#endif /* HALMAC_8822B_SUPPORT*/

66
hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.h
View File

@@ -1,66 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _HALMAC_API_8822B_SDIO_H_
#define _HALMAC_API_8822B_SDIO_H_
#include "../../halmac_api.h"
#include "halmac_8822b_cfg.h"
#if HALMAC_8822B_SUPPORT
enum halmac_ret_status
mac_pwr_switch_sdio_8822b(struct halmac_adapter *adapter,
enum halmac_mac_power pwr);
enum halmac_ret_status
tx_allowed_sdio_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size);
u8
reg_r8_sdio_8822b(struct halmac_adapter *adapter, u32 offset);
enum halmac_ret_status
reg_w8_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u8 value);
u16
reg_r16_sdio_8822b(struct halmac_adapter *adapter, u32 offset);
enum halmac_ret_status
reg_w16_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u16 value);
u32
reg_r32_sdio_8822b(struct halmac_adapter *adapter, u32 offset);
enum halmac_ret_status
reg_w32_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u32 value);
enum halmac_ret_status
phy_cfg_sdio_8822b(struct halmac_adapter *adapter,
enum halmac_intf_phy_platform pltfm);
enum halmac_ret_status
pcie_switch_sdio_8822b(struct halmac_adapter *adapter,
enum halmac_pcie_cfg cfg);
enum halmac_ret_status
intf_tun_sdio_8822b(struct halmac_adapter *adapter);
enum halmac_ret_status
get_sdio_tx_addr_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size,
u32 *cmd53_addr);
#endif /* HALMAC_8822B_SUPPORT*/
#endif/* _HALMAC_API_8822B_SDIO_H_ */

6
hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.c
View File

@@ -18,7 +18,7 @@
#include "../halmac_init_88xx.h"
#include "../halmac_common_88xx.h"
#if HALMAC_8822B_SUPPORT
#if (HALMAC_8822B_SUPPORT && HALMAC_USB_SUPPORT)
/**
* mac_pwr_switch_usb_8822b() - switch mac power
@@ -118,7 +118,7 @@ phy_cfg_usb_8822b(struct halmac_adapter *adapter,
if (status != HALMAC_RET_SUCCESS)
return status;
status = parse_intf_phy_88xx(adapter, usb3_phy_8822b, pltfm,
status = parse_intf_phy_88xx(adapter, usb3_phy_param_8822b, pltfm,
HAL_INTF_PHY_USB3);
if (status != HALMAC_RET_SUCCESS)
@@ -156,4 +156,4 @@ intf_tun_usb_8822b(struct halmac_adapter *adapter)
return HALMAC_RET_SUCCESS;
}
#endif /* HALMAC_8822B_SUPPORT*/
#endif /* HALMAC_8822B_SUPPORT */

4
hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.h
View File

@@ -18,10 +18,10 @@
#include "../../halmac_api.h"
#if HALMAC_8822B_SUPPORT
#if (HALMAC_8822B_SUPPORT && HALMAC_USB_SUPPORT)
extern struct halmac_intf_phy_para usb2_phy_param_8822b[];
extern struct halmac_intf_phy_para usb3_phy_8822b[];
extern struct halmac_intf_phy_para usb3_phy_param_8822b[];
enum halmac_ret_status
mac_pwr_switch_usb_8822b(struct halmac_adapter *adapter,

11
hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c
View File

@@ -56,7 +56,7 @@ start_iqk_88xx(struct halmac_adapter *adapter, struct halmac_iqk_para *param)
hdr_info.sub_cmd_id = SUB_CMD_ID_IQK;
hdr_info.content_size = 1;
hdr_info.ack = _TRUE;
hdr_info.ack = 1;
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
adapter->halmac_state.iqk_state.seq_num = seq_num;
@@ -116,16 +116,19 @@ ctrl_pwr_tracking_88xx(struct halmac_adapter *adapter,
PWR_TRK_SET_TSSI_VALUE_A(h2c_buf, param->tssi_value);
PWR_TRK_SET_OFFSET_VALUE_A(h2c_buf, param->pwr_tracking_offset_value);
param = &opt->pwr_tracking_para[HALMAC_RF_PATH_B];
PWR_TRK_SET_ENABLE_B(h2c_buf, param->enable);
PWR_TRK_SET_TX_PWR_INDEX_B(h2c_buf, param->tx_pwr_index);
PWR_TRK_SET_TSSI_VALUE_B(h2c_buf, param->tssi_value);
PWR_TRK_SET_OFFSET_VALUE_B(h2c_buf, param->pwr_tracking_offset_value);
param = &opt->pwr_tracking_para[HALMAC_RF_PATH_C];
PWR_TRK_SET_ENABLE_C(h2c_buf, param->enable);
PWR_TRK_SET_TX_PWR_INDEX_C(h2c_buf, param->tx_pwr_index);
PWR_TRK_SET_TSSI_VALUE_C(h2c_buf, param->tssi_value);
PWR_TRK_SET_OFFSET_VALUE_C(h2c_buf, param->pwr_tracking_offset_value);
param = &opt->pwr_tracking_para[HALMAC_RF_PATH_D];
PWR_TRK_SET_ENABLE_D(h2c_buf, param->enable);
PWR_TRK_SET_TX_PWR_INDEX_D(h2c_buf, param->tx_pwr_index);
PWR_TRK_SET_TSSI_VALUE_D(h2c_buf, param->tssi_value);
@@ -133,7 +136,7 @@ ctrl_pwr_tracking_88xx(struct halmac_adapter *adapter,
hdr_info.sub_cmd_id = SUB_CMD_ID_PWR_TRK;
hdr_info.content_size = 20;
hdr_info.ack = _TRUE;
hdr_info.ack = 1;
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
adapter->halmac_state.pwr_trk_state.seq_num = seq_num;
@@ -243,7 +246,7 @@ psd_88xx(struct halmac_adapter *adapter, u16 start_psd, u16 end_psd)
hdr_info.sub_cmd_id = SUB_CMD_ID_PSD;
hdr_info.content_size = 4;
hdr_info.ack = _TRUE;
hdr_info.ack = 1;
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
status = send_h2c_pkt_88xx(adapter, h2c_buf);
@@ -377,7 +380,7 @@ get_psd_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
PLTFM_MEMCPY(state->data + seg_id * state->seg_size,
buf + C2H_DATA_OFFSET_88XX, seg_size);
if (PSD_DATA_GET_END_SEGMENT(buf) == _FALSE)
if (PSD_DATA_GET_END_SEGMENT(buf) == 0)
return HALMAC_RET_SUCCESS;
proc_status = HALMAC_CMD_PROCESS_DONE;

278
hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c
View File

@@ -15,10 +15,12 @@
#include "halmac_cfg_wmac_88xx.h"
#include "halmac_88xx_cfg.h"
#include "halmac_efuse_88xx.h"
#if HALMAC_88XX_SUPPORT
#define MAC_CLK_SPEED 80 /* 80M */
#define EFUSE_PCB_INFO_OFFSET 0xCA
enum mac_clock_hw_def {
MAC_CLK_HW_DEF_80M = 0,
@@ -26,6 +28,9 @@ enum mac_clock_hw_def {
MAC_CLK_HW_DEF_20M = 2,
};
static enum halmac_ret_status
board_rf_fine_tune_88xx(struct halmac_adapter *adapter);
/**
* cfg_mac_addr_88xx() - config mac address
* @adapter : the adapter of halmac
@@ -39,8 +44,7 @@ enum halmac_ret_status
cfg_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,
union halmac_wlan_addr *addr)
{
u16 mac_addr_h;
u32 mac_addr_l;
u32 offset;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
@@ -50,37 +54,29 @@ cfg_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,
return HALMAC_RET_PORT_NOT_SUPPORT;
}
mac_addr_l = addr->addr_l_h.low;
mac_addr_h = addr->addr_l_h.high;
mac_addr_l = rtk_le32_to_cpu(mac_addr_l);
mac_addr_h = rtk_le16_to_cpu(mac_addr_h);
switch (port) {
case HALMAC_PORTID0:
HALMAC_REG_W32(REG_MACID, mac_addr_l);
HALMAC_REG_W16(REG_MACID + 4, mac_addr_h);
offset = REG_MACID;
break;
case HALMAC_PORTID1:
HALMAC_REG_W32(REG_MACID1, mac_addr_l);
HALMAC_REG_W16(REG_MACID1 + 4, mac_addr_h);
offset = REG_MACID1;
break;
case HALMAC_PORTID2:
HALMAC_REG_W32(REG_MACID2, mac_addr_l);
HALMAC_REG_W16(REG_MACID2 + 4, mac_addr_h);
offset = REG_MACID2;
break;
case HALMAC_PORTID3:
HALMAC_REG_W32(REG_MACID3, mac_addr_l);
HALMAC_REG_W16(REG_MACID3 + 4, mac_addr_h);
offset = REG_MACID3;
break;
case HALMAC_PORTID4:
HALMAC_REG_W32(REG_MACID4, mac_addr_l);
HALMAC_REG_W16(REG_MACID4 + 4, mac_addr_h);
offset = REG_MACID4;
break;
default:
break;
return HALMAC_RET_PORT_NOT_SUPPORT;
}
HALMAC_REG_W32(offset, rtk_le32_to_cpu(addr->addr_l_h.low));
HALMAC_REG_W16(offset + 4, rtk_le16_to_cpu(addr->addr_l_h.high));
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
@@ -99,8 +95,7 @@ enum halmac_ret_status
cfg_bssid_88xx(struct halmac_adapter *adapter, u8 port,
union halmac_wlan_addr *addr)
{
u16 bssid_addr_h;
u32 bssid_addr_l;
u32 offset;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
@@ -110,37 +105,29 @@ cfg_bssid_88xx(struct halmac_adapter *adapter, u8 port,
return HALMAC_RET_PORT_NOT_SUPPORT;
}
bssid_addr_l = addr->addr_l_h.low;
bssid_addr_h = addr->addr_l_h.high;
bssid_addr_l = rtk_le32_to_cpu(bssid_addr_l);
bssid_addr_h = rtk_le16_to_cpu(bssid_addr_h);
switch (port) {
case HALMAC_PORTID0:
HALMAC_REG_W32(REG_BSSID, bssid_addr_l);
HALMAC_REG_W16(REG_BSSID + 4, bssid_addr_h);
offset = REG_BSSID;
break;
case HALMAC_PORTID1:
HALMAC_REG_W32(REG_BSSID1, bssid_addr_l);
HALMAC_REG_W16(REG_BSSID1 + 4, bssid_addr_h);
offset = REG_BSSID1;
break;
case HALMAC_PORTID2:
HALMAC_REG_W32(REG_BSSID2, bssid_addr_l);
HALMAC_REG_W16(REG_BSSID2 + 4, bssid_addr_h);
offset = REG_BSSID2;
break;
case HALMAC_PORTID3:
HALMAC_REG_W32(REG_BSSID3, bssid_addr_l);
HALMAC_REG_W16(REG_BSSID3 + 4, bssid_addr_h);
offset = REG_BSSID3;
break;
case HALMAC_PORTID4:
HALMAC_REG_W32(REG_BSSID4, bssid_addr_l);
HALMAC_REG_W16(REG_BSSID4 + 4, bssid_addr_h);
offset = REG_BSSID4;
break;
default:
break;
return HALMAC_RET_PORT_NOT_SUPPORT;
}
HALMAC_REG_W32(offset, rtk_le32_to_cpu(addr->addr_l_h.low));
HALMAC_REG_W16(offset + 4, rtk_le16_to_cpu(addr->addr_l_h.high));
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
@@ -158,8 +145,7 @@ enum halmac_ret_status
cfg_transmitter_addr_88xx(struct halmac_adapter *adapter, u8 port,
union halmac_wlan_addr *addr)
{
u16 mac_addr_h;
u32 mac_addr_l;
u32 offset;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
@@ -169,37 +155,29 @@ cfg_transmitter_addr_88xx(struct halmac_adapter *adapter, u8 port,
return HALMAC_RET_PORT_NOT_SUPPORT;
}
mac_addr_l = addr->addr_l_h.low;
mac_addr_h = addr->addr_l_h.high;
mac_addr_l = rtk_le32_to_cpu(mac_addr_l);
mac_addr_h = rtk_le16_to_cpu(mac_addr_h);
switch (port) {
case HALMAC_PORTID0:
HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_0, mac_addr_l);
HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_0 + 4, mac_addr_h);
offset = REG_TRANSMIT_ADDRSS_0;
break;
case HALMAC_PORTID1:
HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_1, mac_addr_l);
HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_1 + 4, mac_addr_h);
offset = REG_TRANSMIT_ADDRSS_1;
break;
case HALMAC_PORTID2:
HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_2, mac_addr_l);
HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_2 + 4, mac_addr_h);
offset = REG_TRANSMIT_ADDRSS_2;
break;
case HALMAC_PORTID3:
HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_3, mac_addr_l);
HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_3 + 4, mac_addr_h);
offset = REG_TRANSMIT_ADDRSS_3;
break;
case HALMAC_PORTID4:
HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_4, mac_addr_l);
HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_4 + 4, mac_addr_h);
offset = REG_TRANSMIT_ADDRSS_4;
break;
default:
break;
return HALMAC_RET_PORT_NOT_SUPPORT;
}
HALMAC_REG_W32(offset, rtk_le32_to_cpu(addr->addr_l_h.low));
HALMAC_REG_W16(offset + 4, rtk_le16_to_cpu(addr->addr_l_h.high));
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
@@ -380,48 +358,43 @@ rw_bcn_ctrl_88xx(struct halmac_adapter *adapter, u8 port, u8 write_en,
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (write_en) {
if (ctrl->dis_rx_bssid_fit == _TRUE)
if (ctrl->dis_rx_bssid_fit == 1)
ctrl_value |= BIT_DIS_RX_BSSID_FIT;
if (ctrl->en_txbcn_rpt == _TRUE)
if (ctrl->en_txbcn_rpt == 1)
ctrl_value |= BIT_P0_EN_TXBCN_RPT;
if (ctrl->dis_tsf_udt == _TRUE)
if (ctrl->dis_tsf_udt == 1)
ctrl_value |= BIT_DIS_TSF_UDT;
if (ctrl->en_bcn == _TRUE)
if (ctrl->en_bcn == 1)
ctrl_value |= BIT_EN_BCN_FUNCTION;
if (ctrl->en_rxbcn_rpt == _TRUE)
if (ctrl->en_rxbcn_rpt == 1)
ctrl_value |= BIT_P0_EN_RXBCN_RPT;
if (ctrl->en_p2p_ctwin == _TRUE)
if (ctrl->en_p2p_ctwin == 1)
ctrl_value |= BIT_EN_P2P_CTWINDOW;
if (ctrl->en_p2p_bcn_area == _TRUE)
if (ctrl->en_p2p_bcn_area == 1)
ctrl_value |= BIT_EN_P2P_BCNQ_AREA;
switch (port) {
case HALMAC_PORTID0:
HALMAC_REG_W8(REG_BCN_CTRL, ctrl_value);
break;
case HALMAC_PORTID1:
HALMAC_REG_W8(REG_BCN_CTRL_CLINT0, ctrl_value);
break;
case HALMAC_PORTID2:
HALMAC_REG_W8(REG_BCN_CTRL_CLINT1, ctrl_value);
break;
case HALMAC_PORTID3:
HALMAC_REG_W8(REG_BCN_CTRL_CLINT2, ctrl_value);
break;
case HALMAC_PORTID4:
HALMAC_REG_W8(REG_BCN_CTRL_CLINT3, ctrl_value);
break;
default:
break;
}
@@ -431,61 +404,56 @@ rw_bcn_ctrl_88xx(struct halmac_adapter *adapter, u8 port, u8 write_en,
case HALMAC_PORTID0:
ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL);
break;
case HALMAC_PORTID1:
ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT0);
break;
case HALMAC_PORTID2:
ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT1);
break;
case HALMAC_PORTID3:
ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT2);
break;
case HALMAC_PORTID4:
ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT3);
break;
default:
break;
}
if (ctrl_value & BIT_EN_P2P_BCNQ_AREA)
ctrl->en_p2p_bcn_area = _TRUE;
ctrl->en_p2p_bcn_area = 1;
else
ctrl->en_p2p_bcn_area = _FALSE;
ctrl->en_p2p_bcn_area = 0;
if (ctrl_value & BIT_EN_P2P_CTWINDOW)
ctrl->en_p2p_ctwin = _TRUE;
ctrl->en_p2p_ctwin = 1;
else
ctrl->en_p2p_ctwin = _FALSE;
ctrl->en_p2p_ctwin = 0;
if (ctrl_value & BIT_P0_EN_RXBCN_RPT)
ctrl->en_rxbcn_rpt = _TRUE;
ctrl->en_rxbcn_rpt = 1;
else
ctrl->en_rxbcn_rpt = _FALSE;
ctrl->en_rxbcn_rpt = 0;
if (ctrl_value & BIT_EN_BCN_FUNCTION)
ctrl->en_bcn = _TRUE;
ctrl->en_bcn = 1;
else
ctrl->en_bcn = _FALSE;
ctrl->en_bcn = 0;
if (ctrl_value & BIT_DIS_TSF_UDT)
ctrl->dis_tsf_udt = _TRUE;
ctrl->dis_tsf_udt = 1;
else
ctrl->dis_tsf_udt = _FALSE;
ctrl->dis_tsf_udt = 0;
if (ctrl_value & BIT_P0_EN_TXBCN_RPT)
ctrl->en_txbcn_rpt = _TRUE;
ctrl->en_txbcn_rpt = 1;
else
ctrl->en_txbcn_rpt = _FALSE;
ctrl->en_txbcn_rpt = 0;
if (ctrl_value & BIT_DIS_RX_BSSID_FIT)
ctrl->dis_rx_bssid_fit = _TRUE;
ctrl->dis_rx_bssid_fit = 1;
else
ctrl->dis_rx_bssid_fit = _FALSE;
ctrl->dis_rx_bssid_fit = 0;
}
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
@@ -505,20 +473,12 @@ enum halmac_ret_status
cfg_multicast_addr_88xx(struct halmac_adapter *adapter,
union halmac_wlan_addr *addr)
{
u16 addr_h;
u32 addr_l;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
addr_l = addr->addr_l_h.low;
addr_h = addr->addr_l_h.high;
addr_l = rtk_le32_to_cpu(addr_l);
addr_h = rtk_le16_to_cpu(addr_h);
HALMAC_REG_W32(REG_MAR, addr_l);
HALMAC_REG_W16(REG_MAR + 4, addr_h);
HALMAC_REG_W32(REG_MAR, rtk_le32_to_cpu(addr->addr_l_h.low));
HALMAC_REG_W16(REG_MAR + 4, rtk_le16_to_cpu(addr->addr_l_h.high));
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
@@ -628,10 +588,10 @@ cfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw)
switch (bw) {
case HALMAC_BW_80:
value32 = value32 | BIT(7);
value32 |= BIT(8);
break;
case HALMAC_BW_40:
value32 = value32 | BIT(8);
value32 |= BIT(7);
break;
case HALMAC_BW_20:
case HALMAC_BW_10:
@@ -643,13 +603,7 @@ cfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw)
HALMAC_REG_W32(REG_WMAC_TRXPTCL_CTL, value32);
/* TODO:Move to change mac clk api later... */
value32 = HALMAC_REG_R32(REG_AFE_CTRL1) & ~(BIT(20) | BIT(21));
value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL);
HALMAC_REG_W32(REG_AFE_CTRL1, value32);
HALMAC_REG_W8(REG_USTIME_TSF, MAC_CLK_SPEED);
HALMAC_REG_W8(REG_USTIME_EDCA, MAC_CLK_SPEED);
cfg_mac_clk_88xx(adapter);
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
@@ -657,13 +611,38 @@ cfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw)
}
void
enable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable)
cfg_txfifo_lt_88xx(struct halmac_adapter *adapter,
struct halmac_txfifo_lifetime_cfg *cfg)
{
u8 value8;
u32 value32;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
if (cfg->enable == 1) {
value8 = HALMAC_REG_R8(REG_LIFETIME_EN);
value8 = value8 | BIT(0) | BIT(1) | BIT(2) | BIT(3);
HALMAC_REG_W8(REG_LIFETIME_EN, value8);
value32 = (cfg->lifetime) >> 8;
value32 = value32 + (value32 << 16);
HALMAC_REG_W32(REG_PKT_LIFE_TIME, value32);
} else {
value8 = HALMAC_REG_R8(REG_LIFETIME_EN);
value8 = value8 & (~(BIT(0) | BIT(1) | BIT(2) | BIT(3)));
HALMAC_REG_W8(REG_LIFETIME_EN, value8);
}
}
enum halmac_ret_status
enable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable)
{
u8 value8;
u32 value32;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (enable == 1) {
status = board_rf_fine_tune_88xx(adapter);
value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN);
value8 = value8 | BIT(0) | BIT(1);
HALMAC_REG_W8(REG_SYS_FUNC_EN, value8);
@@ -688,6 +667,59 @@ enable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable)
value32 = value32 & (~(BIT(24) | BIT(25) | BIT(26)));
HALMAC_REG_W32(REG_WLRF1, value32);
}
return status;
}
static enum halmac_ret_status
board_rf_fine_tune_88xx(struct halmac_adapter *adapter)
{
u8 *map = NULL;
u32 size = adapter->hw_cfg_info.eeprom_size;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
if (adapter->chip_id == HALMAC_CHIP_ID_8822B) {
if (!adapter->efuse_map_valid || !adapter->efuse_map) {
PLTFM_MSG_ERR("[ERR]efuse map invalid!!\n");
return HALMAC_RET_EFUSE_R_FAIL;
}
map = (u8 *)PLTFM_MALLOC(size);
if (!map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
return HALMAC_RET_MALLOC_FAIL;
}
PLTFM_MEMSET(map, 0xFF, size);
if (eeprom_parser_88xx(adapter, adapter->efuse_map, map) !=
HALMAC_RET_SUCCESS) {
PLTFM_FREE(map, size);
return HALMAC_RET_EEPROM_PARSING_FAIL;
}
/* Fine-tune XTAL voltage for 2L PCB board */
if (*(map + EFUSE_PCB_INFO_OFFSET) == 0x0C)
HALMAC_REG_W8_SET(REG_AFE_CTRL1 + 1, BIT(1));
PLTFM_FREE(map, size);
}
return HALMAC_RET_SUCCESS;
}
void
cfg_mac_clk_88xx(struct halmac_adapter *adapter)
{
u32 value32;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
value32 = HALMAC_REG_R32(REG_AFE_CTRL1) & ~(BIT(20) | BIT(21));
value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL);
HALMAC_REG_W32(REG_AFE_CTRL1, value32);
HALMAC_REG_W8(REG_USTIME_TSF, MAC_CLK_SPEED);
HALMAC_REG_W8(REG_USTIME_EDCA, MAC_CLK_SPEED);
}
/**
@@ -753,11 +785,10 @@ config_security_88xx(struct halmac_adapter *adapter,
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
HALMAC_REG_W16(REG_CR, (u16)(HALMAC_REG_R16(REG_CR) | BIT_MAC_SEC_EN));
HALMAC_REG_W16_SET(REG_CR, BIT_MAC_SEC_EN);
if (setting->compare_keyid == 1) {
sec_cfg = HALMAC_REG_R8(REG_SECCFG + 1) | BIT(0);
HALMAC_REG_W8(REG_SECCFG + 1, sec_cfg);
HALMAC_REG_W8_SET(REG_SECCFG + 1, BIT(0));
adapter->hw_cfg_info.chk_security_keyid = 1;
} else {
adapter->hw_cfg_info.chk_security_keyid = 0;
@@ -784,7 +815,7 @@ config_security_88xx(struct halmac_adapter *adapter,
if (setting->bip_enable == 1) {
if (adapter->chip_id == HALMAC_CHIP_ID_8822B)
return HALMAC_RET_BIP_NO_SUPPORT;
#if HALMAC_8821C_SUPPORT
#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
sec_cfg = HALMAC_REG_R8(REG_WSEC_OPTION + 2);
if (setting->tx_encryption == 1)
@@ -1054,7 +1085,7 @@ rx_clk_gate_88xx(struct halmac_adapter *adapter, u8 enable)
value8 = HALMAC_REG_R8(REG_RCR + 2);
if (enable == _TRUE)
if (enable == 1)
HALMAC_REG_W8(REG_RCR + 2, value8 & ~(BIT(3)));
else
HALMAC_REG_W8(REG_RCR + 2, value8 | BIT(3));
@@ -1154,15 +1185,26 @@ get_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,
return HALMAC_RET_PORT_NOT_SUPPORT;
}
mac_addr_l = rtk_le32_to_cpu(mac_addr_l);
mac_addr_h = rtk_le16_to_cpu(mac_addr_h);
addr->addr_l_h.low = mac_addr_l;
addr->addr_l_h.high = mac_addr_h;
addr->addr_l_h.low = rtk_cpu_to_le32(mac_addr_l);
addr->addr_l_h.high = rtk_cpu_to_le16(mac_addr_h);
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
void
rts_full_bw_88xx(struct halmac_adapter *adapter, u8 enable)
{
u8 value8;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
value8 = HALMAC_REG_R8(REG_INIRTS_RATE_SEL);
if (enable == 1)
HALMAC_REG_W8(REG_INIRTS_RATE_SEL, value8 | BIT(5));
else
HALMAC_REG_W8(REG_INIRTS_RATE_SEL, value8 & ~(BIT(5)));
}
#endif /* HALMAC_88XX_SUPPORT */

10
hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h
View File

@@ -68,6 +68,10 @@ enum halmac_ret_status
cfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw);
void
cfg_txfifo_lt_88xx(struct halmac_adapter *adapter,
struct halmac_txfifo_lifetime_cfg *cfg);
enum halmac_ret_status
enable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable);
enum halmac_ret_status
@@ -118,6 +122,12 @@ enum halmac_ret_status
get_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,
union halmac_wlan_addr *addr);
void
rts_full_bw_88xx(struct halmac_adapter *adapter, u8 enable);
void
cfg_mac_clk_88xx(struct halmac_adapter *adapter);
#endif/* HALMAC_88XX_SUPPORT */
#endif/* _HALMAC_CFG_WMAC_88XX_H_ */

212
hal/halmac/halmac_88xx/halmac_common_88xx.c
View File

@@ -19,9 +19,15 @@
#include "halmac_cfg_wmac_88xx.h"
#include "halmac_efuse_88xx.h"
#include "halmac_bb_rf_88xx.h"
#if HALMAC_USB_SUPPORT
#include "halmac_usb_88xx.h"
#endif
#if HALMAC_SDIO_SUPPORT
#include "halmac_sdio_88xx.h"
#endif
#if HALMAC_PCIE_SUPPORT
#include "halmac_pcie_88xx.h"
#endif
#include "halmac_mimo_88xx.h"
#if HALMAC_88XX_SUPPORT
@@ -202,6 +208,14 @@ wlhdr_data_valid_88xx(struct halmac_adapter *adapter,
static void
dump_reg_88xx(struct halmac_adapter *adapter);
static u8
packet_in_nlo_88xx(struct halmac_adapter *adapter,
enum halmac_packet_id pkt_id);
static enum halmac_packet_id
get_real_pkt_id_88xx(struct halmac_adapter *adapter,
enum halmac_packet_id pkt_id);
/**
* ofld_func_cfg_88xx() - config offload function
* @adapter : the adapter of halmac
@@ -301,7 +315,7 @@ dl_rsvd_page_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *buf,
value8 = (u8)(value8 & ~(BIT(6)));
HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8);
if (PLTFM_SEND_RSVD_PAGE(buf, size) == _FALSE) {
if (PLTFM_SEND_RSVD_PAGE(buf, size) == 0) {
PLTFM_MSG_ERR("[ERR]send rvsd pg(pltfm)!!\n");
status = HALMAC_RET_DL_RSVD_PAGE_FAIL;
goto DL_RSVD_PG_END;
@@ -455,8 +469,9 @@ enum halmac_ret_status
set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
void *value)
{
enum halmac_ret_status status;
struct halmac_tx_page_threshold_info *tx_th_info;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
struct halmac_tx_page_threshold_info *th_info = NULL;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
@@ -466,12 +481,14 @@ set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
}
switch (hw_id) {
#if HALMAC_USB_SUPPORT
case HALMAC_HW_USB_MODE:
status = set_usb_mode_88xx(adapter,
*(enum halmac_usb_mode *)value);
if (status != HALMAC_RET_SUCCESS)
return status;
break;
#endif
case HALMAC_HW_BANDWIDTH:
cfg_bw_88xx(adapter, *(enum halmac_bw *)value);
break;
@@ -482,12 +499,20 @@ set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
cfg_pri_ch_idx_88xx(adapter, *(enum halmac_pri_ch_idx *)value);
break;
case HALMAC_HW_EN_BB_RF:
enable_bb_rf_88xx(adapter, *(u8 *)value);
status = enable_bb_rf_88xx(adapter, *(u8 *)value);
if (status != HALMAC_RET_SUCCESS)
return status;
break;
#if HALMAC_SDIO_SUPPORT
case HALMAC_HW_SDIO_TX_PAGE_THRESHOLD:
tx_th_info = (struct halmac_tx_page_threshold_info *)value;
cfg_sdio_tx_page_threshold_88xx(adapter, tx_th_info);
if (adapter->intf == HALMAC_INTERFACE_SDIO) {
th_info = (struct halmac_tx_page_threshold_info *)value;
cfg_sdio_tx_page_threshold_88xx(adapter, th_info);
} else {
return HALMAC_RET_FAIL;
}
break;
#endif
case HALMAC_HW_RX_SHIFT:
rx_shift_88xx(adapter, *(u8 *)value);
break;
@@ -501,6 +526,15 @@ set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
fast_edca_cfg_88xx(adapter,
(struct halmac_fast_edca_cfg *)value);
break;
case HALMAC_HW_RTS_FULL_BW:
rts_full_bw_88xx(adapter, *(u8 *)value);
break;
case HALMAC_HW_FREE_CNT_EN:
HALMAC_REG_W8_SET(REG_MISC_CTRL, BIT_EN_FREECNT);
break;
case HALMAC_HW_TXFIFO_LIFETIME:
cfg_txfifo_lt_88xx(adapter,
(struct halmac_txfifo_lifetime_cfg *)value);
default:
return HALMAC_RET_PARA_NOT_SUPPORT;
}
@@ -531,8 +565,8 @@ set_h2c_pkt_hdr_88xx(struct halmac_adapter *adapter, u8 *hdr,
(adapter->h2c_info.seq_num)++;
PLTFM_MUTEX_UNLOCK(&adapter->h2c_seq_mutex);
if (info->ack == _TRUE)
FW_OFFLOAD_H2C_SET_ACK(hdr, _TRUE);
if (info->ack == 1)
FW_OFFLOAD_H2C_SET_ACK(hdr, 1);
return HALMAC_RET_SUCCESS;
}
@@ -554,7 +588,7 @@ send_h2c_pkt_88xx(struct halmac_adapter *adapter, u8 *pkt)
cnt = 100;
do {
if (PLTFM_SEND_H2C_PKT(pkt, H2C_PKT_SIZE_88XX) == _TRUE)
if (PLTFM_SEND_H2C_PKT(pkt, H2C_PKT_SIZE_88XX) == 1)
break;
cnt--;
if (cnt == 0) {
@@ -578,8 +612,8 @@ get_h2c_buf_free_space_88xx(struct halmac_adapter *adapter)
struct halmac_h2c_info *info = &adapter->h2c_info;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
hw_wptr = HALMAC_REG_R32(REG_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_WR_ADDR;
fw_rptr = HALMAC_REG_R32(REG_H2C_PKT_READADDR) & BIT_MASK_H2C_READ_ADDR;
hw_wptr = HALMAC_REG_R32(REG_H2C_PKT_WRITEADDR) & 0x3FFFF;
fw_rptr = HALMAC_REG_R32(REG_H2C_PKT_READADDR) & 0x3FFFF;
if (hw_wptr >= fw_rptr)
info->buf_fs = info->buf_size - (hw_wptr - fw_rptr);
@@ -594,6 +628,9 @@ get_h2c_buf_free_space_88xx(struct halmac_adapter *adapter)
* @adapter : the adapter of halmac
* @buf : RX Packet pointer
* @size : RX Packet size
*
* Note : Don't use any IO or DELAY in this API
*
* Author : KaiYuan Chang/Ivan Lin
*
* Used to process c2h packet info from RX path. After receiving the packet,
@@ -607,7 +644,7 @@ get_c2h_info_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (GET_RX_DESC_C2H(buf) == _TRUE) {
if (GET_RX_DESC_C2H(buf) == 1) {
PLTFM_MSG_TRACE("[TRACE]Parse c2h pkt\n");
status = parse_c2h_pkt_88xx(adapter, buf, size);
@@ -623,7 +660,8 @@ get_c2h_info_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
static enum halmac_ret_status
parse_c2h_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
{
u8 cmd_id, sub_cmd_id;
u8 cmd_id;
u8 sub_cmd_id;
u8 *c2h_pkt = buf + adapter->hw_cfg_info.rxdesc_size;
u32 c2h_size = size - adapter->hw_cfg_info.rxdesc_size;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
@@ -732,7 +770,8 @@ _ENDFOUND:
static enum halmac_ret_status
get_h2c_ack_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
{
u8 cmd_id, sub_cmd_id;
u8 cmd_id;
u8 sub_cmd_id;
u8 fw_rc;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
@@ -960,11 +999,10 @@ get_h2c_ack_ch_switch_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
}
/**
* mac_debug_88xx() - dump debug information
* @adapter : the adapter of halmac
* mac_debug_88xx_v1() - read some registers for debug
* @adapter
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
mac_debug_88xx(struct halmac_adapter *adapter)
@@ -1054,7 +1092,7 @@ dump_reg_88xx(struct halmac_adapter *adapter)
* @info : cmd id, content
* @full_fifo : parameter information
*
* If msk_en = _TRUE, the format of array is {reg_info, mask, value}.
* If msk_en = 1, the format of array is {reg_info, mask, value}.
* If msk_en =_FAUSE, the format of array is {reg_info, value}
* The format of reg_info is
* reg_info[31]=rf_reg, 0: MAC_BB reg, 1: RF reg
@@ -1062,7 +1100,7 @@ dump_reg_88xx(struct halmac_adapter *adapter)
* if rf_reg=0(MAC_BB reg), rf_path is meaningless.
* ref_info[15:0]=offset
*
* Example: msk_en = _FALSE
* Example: msk_en = 0
* {0x8100000a, 0x00001122}
* =>Set RF register, path_B, offset 0xA to 0x00001122
* {0x00000824, 0x11224433}
@@ -1124,7 +1162,7 @@ static enum halmac_ret_status
proc_cfg_param_88xx(struct halmac_adapter *adapter,
struct halmac_phy_parameter_info *param, u8 full_fifo)
{
u8 end_cmd = _FALSE;
u8 end_cmd = 0;
u32 rsvd_size;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
struct halmac_cfg_param_info *info = &adapter->cfg_param_info;
@@ -1137,8 +1175,12 @@ proc_cfg_param_88xx(struct halmac_adapter *adapter,
return status;
if (cnv_cfg_param_state_88xx(adapter, HALMAC_CMD_CNSTR_CNSTR) !=
HALMAC_RET_SUCCESS)
HALMAC_RET_SUCCESS) {
PLTFM_FREE(info->buf, info->buf_size);
info->buf = NULL;
info->buf_wptr = NULL;
return HALMAC_RET_ERROR_STATE;
}
add_param_buf_88xx(adapter, param, info->buf_wptr, &end_cmd);
if (param->cmd_id != HALMAC_PARAMETER_CMD_END) {
@@ -1148,7 +1190,7 @@ proc_cfg_param_88xx(struct halmac_adapter *adapter,
}
rsvd_size = info->avl_buf_size - adapter->hw_cfg_info.txdesc_size;
if (rsvd_size > CFG_PARAM_H2C_INFO_SIZE && end_cmd == _FALSE)
if (rsvd_size > CFG_PARAM_H2C_INFO_SIZE && end_cmd == 0)
return HALMAC_RET_SUCCESS;
if (info->num == 0) {
@@ -1166,10 +1208,16 @@ proc_cfg_param_88xx(struct halmac_adapter *adapter,
}
status = send_cfg_param_h2c_88xx(adapter);
if (status != HALMAC_RET_SUCCESS)
if (status != HALMAC_RET_SUCCESS) {
if (info->buf) {
PLTFM_FREE(info->buf, info->buf_size);
info->buf = NULL;
info->buf_wptr = NULL;
}
return status;
}
if (end_cmd == _FALSE) {
if (end_cmd == 0) {
PLTFM_MSG_TRACE("[TRACE]send h2c-buf full\n");
return HALMAC_RET_PARA_SENDING;
}
@@ -1197,7 +1245,7 @@ send_cfg_param_h2c_88xx(struct halmac_adapter *adapter)
*proc_status = HALMAC_CMD_PROCESS_SENDING;
if (info->full_fifo_mode == _TRUE)
if (info->full_fifo_mode == 1)
pg_addr = 0;
else
pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
@@ -1214,7 +1262,7 @@ send_cfg_param_h2c_88xx(struct halmac_adapter *adapter)
hdr_info.sub_cmd_id = SUB_CMD_ID_CFG_PARAM;
hdr_info.content_size = 4;
hdr_info.ack = _TRUE;
hdr_info.ack = 1;
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
adapter->halmac_state.cfg_param_state.seq_num = seq_num;
@@ -1276,7 +1324,7 @@ add_param_buf_88xx(struct halmac_adapter *adapter,
struct halmac_cfg_param_info *info = &adapter->cfg_param_info;
union halmac_parameter_content *content = &param->content;
*end_cmd = _FALSE;
*end_cmd = 0;
PARAM_INFO_SET_LEN(buf, CFG_PARAM_H2C_INFO_SIZE);
PARAM_INFO_SET_IO_CMD(buf, param->cmd_id);
@@ -1311,7 +1359,7 @@ add_param_buf_88xx(struct halmac_adapter *adapter,
PARAM_INFO_SET_DELAY_VAL(buf, content->DELAY_TIME.delay_time);
break;
case HALMAC_PARAMETER_CMD_END:
*end_cmd = _TRUE;
*end_cmd = 1;
break;
default:
PLTFM_MSG_ERR("[ERR]cmd id!!\n");
@@ -1330,7 +1378,7 @@ gen_cfg_param_h2c_88xx(struct halmac_adapter *adapter, u8 *buff)
CFG_PARAM_SET_NUM(buff, info->num);
if (info->full_fifo_mode == _TRUE) {
if (info->full_fifo_mode == 1) {
CFG_PARAM_SET_INIT_CASE(buff, 0x1);
CFG_PARAM_SET_LOC(buff, 0);
} else {
@@ -1350,7 +1398,7 @@ malloc_cfg_param_buf_88xx(struct halmac_adapter *adapter, u8 full_fifo)
if (info->buf)
return HALMAC_RET_SUCCESS;
if (full_fifo == _TRUE)
if (full_fifo == 1)
info->buf_size = pltfm_info->malloc_size;
else
info->buf_size = CFG_PARAM_RSVDPG_SIZE;
@@ -1420,6 +1468,11 @@ update_packet_88xx(struct halmac_adapter *adapter, enum halmac_packet_id pkt_id,
return status;
}
if (packet_in_nlo_88xx(adapter, pkt_id)) {
*proc_status = HALMAC_CMD_PROCESS_DONE;
adapter->nlo_flag = 1;
}
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
@@ -1435,6 +1488,7 @@ send_h2c_update_packet_88xx(struct halmac_adapter *adapter,
u16 pg_offset;
struct halmac_h2c_header_info hdr_info;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
enum halmac_packet_id real_pkt_id;
status = dl_rsvd_page_88xx(adapter, pg_addr, pkt, size);
if (status != HALMAC_RET_SUCCESS) {
@@ -1442,14 +1496,18 @@ send_h2c_update_packet_88xx(struct halmac_adapter *adapter,
return status;
}
real_pkt_id = get_real_pkt_id_88xx(adapter, pkt_id);
pg_offset = pg_addr - adapter->txff_alloc.rsvd_boundary;
UPDATE_PKT_SET_SIZE(h2c_buf, size + adapter->hw_cfg_info.txdesc_size);
UPDATE_PKT_SET_ID(h2c_buf, pkt_id);
UPDATE_PKT_SET_ID(h2c_buf, real_pkt_id);
UPDATE_PKT_SET_LOC(h2c_buf, pg_offset);
hdr_info.sub_cmd_id = SUB_CMD_ID_UPDATE_PKT;
hdr_info.content_size = 8;
hdr_info.ack = _TRUE;
if (packet_in_nlo_88xx(adapter, pkt_id))
hdr_info.ack = 0;
else
hdr_info.ack = 1;
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
adapter->halmac_state.update_pkt_state.seq_num = seq_num;
@@ -1583,7 +1641,7 @@ dump_fifo_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel,
return HALMAC_RET_NULL_POINTER;
tmp8 = HALMAC_REG_R8(REG_RCR + 2);
enable = _FALSE;
enable = 0;
status = api->halmac_set_hw_value(adapter, HALMAC_HW_RX_CLK_GATE,
&enable);
if (status != HALMAC_RET_SUCCESS)
@@ -1702,8 +1760,8 @@ set_h2c_header_88xx(struct halmac_adapter *adapter, u8 *hdr, u16 *seq, u8 ack)
(adapter->h2c_info.seq_num)++;
PLTFM_MUTEX_UNLOCK(&adapter->h2c_seq_mutex);
if (ack == _TRUE)
H2C_CMD_HEADER_SET_ACK(hdr, _TRUE);
if (ack == 1)
H2C_CMD_HEADER_SET_ACK(hdr, 1);
return HALMAC_RET_SUCCESS;
}
@@ -1898,7 +1956,7 @@ ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (opt->switch_en == _FALSE)
if (opt->switch_en == 0)
*proc_status = HALMAC_CMD_PROCESS_IDLE;
if ((*proc_status == HALMAC_CMD_PROCESS_SENDING) ||
@@ -1908,7 +1966,7 @@ ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
}
state = scan_cmd_cnstr_state_88xx(adapter);
if (opt->switch_en == _TRUE) {
if (opt->switch_en == 1) {
if (state != HALMAC_CMD_CNSTR_CNSTR) {
PLTFM_MSG_ERR("[ERR]state(en = 1)\n");
return HALMAC_RET_ERROR_STATE;
@@ -1946,6 +2004,9 @@ proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (opt->nlo_en == 1 && adapter->nlo_flag != 1)
PLTFM_MSG_WARN("[WARN]probe req is NOT nlo pkt!!\n");
if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) !=
HALMAC_RET_SUCCESS)
return HALMAC_RET_ERROR_STATE;
@@ -1981,7 +2042,10 @@ proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
hdr_info.sub_cmd_id = SUB_CMD_ID_CH_SWITCH;
hdr_info.content_size = 20;
hdr_info.ack = _TRUE;
if (opt->nlo_en == 1)
hdr_info.ack = 0;
else
hdr_info.ack = 1;
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
adapter->halmac_state.scan_state.seq_num = seq_num;
@@ -2004,6 +2068,8 @@ proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
HALMAC_RET_SUCCESS)
return HALMAC_RET_ERROR_STATE;
adapter->nlo_flag = 0;
return status;
}
@@ -2060,7 +2126,7 @@ chk_txdesc_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (GET_TX_DESC_BMC(buf) == _TRUE && GET_TX_DESC_AGG_EN(buf) == _TRUE)
if (GET_TX_DESC_BMC(buf) == 1 && GET_TX_DESC_AGG_EN(buf) == 1)
PLTFM_MSG_ERR("[ERR]txdesc - agg + bmc\n");
if (size < (GET_TX_DESC_TXPKTSIZE(buf) +
@@ -2121,15 +2187,15 @@ wlhdr_valid_88xx(struct halmac_adapter *adapter, u8 *buf)
switch (wlhdr->type) {
case WLHDR_TYPE_MGMT:
if (wlhdr_mgmt_valid_88xx(adapter, wlhdr) != _TRUE)
if (wlhdr_mgmt_valid_88xx(adapter, wlhdr) != 1)
status = HALMAC_RET_WLHDR_FAIL;
break;
case WLHDR_TYPE_CTRL:
if (wlhdr_ctrl_valid_88xx(adapter, wlhdr) != _TRUE)
if (wlhdr_ctrl_valid_88xx(adapter, wlhdr) != 1)
status = HALMAC_RET_WLHDR_FAIL;
break;
case WLHDR_TYPE_DATA:
if (wlhdr_data_valid_88xx(adapter, wlhdr) != _TRUE)
if (wlhdr_data_valid_88xx(adapter, wlhdr) != 1)
status = HALMAC_RET_WLHDR_FAIL;
break;
default:
@@ -2160,11 +2226,11 @@ wlhdr_mgmt_valid_88xx(struct halmac_adapter *adapter,
case WLHDR_SUB_TYPE_DEAUTH:
case WLHDR_SUB_TYPE_ACTION:
case WLHDR_SUB_TYPE_ACTION_NOACK:
state = _TRUE;
state = 1;
break;
default:
PLTFM_MSG_ERR("[ERR]mgmt invalid!!\n");
state = _FALSE;
state = 0;
break;
}
@@ -2180,11 +2246,11 @@ wlhdr_ctrl_valid_88xx(struct halmac_adapter *adapter,
switch (wlhdr->sub_type) {
case WLHDR_SUB_TYPE_BF_RPT_POLL:
case WLHDR_SUB_TYPE_NDPA:
state = _TRUE;
state = 1;
break;
default:
PLTFM_MSG_ERR("[ERR]ctrl invalid!!\n");
state = _FALSE;
state = 0;
break;
}
@@ -2202,11 +2268,11 @@ wlhdr_data_valid_88xx(struct halmac_adapter *adapter,
case WLHDR_SUB_TYPE_NULL:
case WLHDR_SUB_TYPE_QOS_DATA:
case WLHDR_SUB_TYPE_QOS_NULL:
state = _TRUE;
state = 1;
break;
default:
PLTFM_MSG_ERR("[ERR]data invalid!!\n");
state = _FALSE;
state = 0;
break;
}
@@ -2214,7 +2280,7 @@ wlhdr_data_valid_88xx(struct halmac_adapter *adapter,
}
/**
* halmac_get_version() - get HALMAC version
* get_version_88xx() - get HALMAC version
* @ver : return version of major, prototype and minor information
* Author : KaiYuan Chang / Ivan Lin
* Return : enum halmac_ret_status
@@ -2283,7 +2349,7 @@ proc_p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info)
hdr_info.sub_cmd_id = SUB_CMD_ID_P2PPS;
hdr_info.content_size = 24;
hdr_info.ack = _FALSE;
hdr_info.ack = 0;
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
status = send_h2c_pkt_88xx(adapter, h2c_buf);
@@ -2424,6 +2490,9 @@ cfg_drv_rsvd_pg_num_88xx(struct halmac_adapter *adapter,
case HALMAC_RSVD_PG_NUM128:
adapter->txff_alloc.rsvd_drv_pg_num = 128;
break;
case HALMAC_RSVD_PG_NUM256:
adapter->txff_alloc.rsvd_drv_pg_num = 256;
break;
}
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
@@ -2688,13 +2757,15 @@ parse_intf_phy_88xx(struct halmac_adapter *adapter,
HALMAC_REG_W8((u32)offset, (u8)value);
} else if (intf_phy == HAL_INTF_PHY_USB2 ||
intf_phy == HAL_INTF_PHY_USB3) {
#if HALMAC_USB_SUPPORT
result = usbphy_write_88xx(adapter, (u8)offset,
value, intf_phy);
if (result != HALMAC_RET_SUCCESS)
PLTFM_MSG_ERR("[ERR]usb phy!!\n");
#endif
} else if (intf_phy == HAL_INTF_PHY_PCIE_GEN1 ||
intf_phy == HAL_INTF_PHY_PCIE_GEN2) {
#if HALMAC_PCIE_SUPPORT
if (ip_sel == HALMAC_IP_INTF_PHY)
result = mdio_write_88xx(adapter,
(u8)offset,
@@ -2705,7 +2776,7 @@ parse_intf_phy_88xx(struct halmac_adapter *adapter,
(u8)value);
if (result != HALMAC_RET_SUCCESS)
PLTFM_MSG_ERR("[ERR]mdio/dbi!!\n");
#endif
} else {
PLTFM_MSG_ERR("[ERR]intf phy sel!!\n");
}
@@ -2855,4 +2926,41 @@ pwr_state_88xx(struct halmac_adapter *adapter, enum halmac_mac_power *state)
*state = HALMAC_MAC_POWER_ON;
}
static u8
packet_in_nlo_88xx(struct halmac_adapter *adapter,
enum halmac_packet_id pkt_id)
{
enum halmac_packet_id nlo_pkt = HALMAC_PACKET_PROBE_REQ_NLO;
if (pkt_id >= nlo_pkt)
return 1;
else
return 0;
}
static enum halmac_packet_id
get_real_pkt_id_88xx(struct halmac_adapter *adapter,
enum halmac_packet_id pkt_id)
{
enum halmac_packet_id real_pkt_id;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
switch (pkt_id) {
case HALMAC_PACKET_PROBE_REQ_NLO:
real_pkt_id = HALMAC_PACKET_PROBE_REQ;
break;
case HALMAC_PACKET_SYNC_BCN_NLO:
real_pkt_id = HALMAC_PACKET_SYNC_BCN;
break;
case HALMAC_PACKET_DISCOVERY_BCN_NLO:
real_pkt_id = HALMAC_PACKET_DISCOVERY_BCN;
break;
default:
real_pkt_id = pkt_id;
}
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return real_pkt_id;
}
#endif /* HALMAC_88XX_SUPPORT */

92
hal/halmac/halmac_88xx/halmac_efuse_88xx.c
View File

@@ -22,7 +22,6 @@
#define RSVD_EFUSE_SIZE 16
#define RSVD_CS_EFUSE_SIZE 24
#define PROTECT_EFUSE_SIZE 96
#define FEATURE_DUMP_PHY_EFUSE HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE
#define FEATURE_DUMP_LOG_EFUSE HALMAC_FEATURE_DUMP_LOGICAL_EFUSE
@@ -37,9 +36,6 @@ static enum halmac_ret_status
read_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
u8 *map);
static enum halmac_ret_status
eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map);
static enum halmac_ret_status
read_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map);
@@ -98,6 +94,7 @@ dump_efuse_map_88xx(struct halmac_adapter *adapter,
u8 *map = NULL;
u8 *efuse_map;
u32 efuse_size = adapter->hw_cfg_info.efuse_size;
u32 prtct_efuse_size = adapter->hw_cfg_info.prtct_efuse_size;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
enum halmac_cmd_process_status *proc_status;
@@ -138,7 +135,7 @@ dump_efuse_map_88xx(struct halmac_adapter *adapter,
return status;
}
if (adapter->efuse_map_valid == _TRUE) {
if (adapter->efuse_map_valid == 1) {
*proc_status = HALMAC_CMD_PROCESS_DONE;
efuse_map = adapter->efuse_map;
@@ -149,13 +146,17 @@ dump_efuse_map_88xx(struct halmac_adapter *adapter,
}
PLTFM_MEMSET(map, 0xFF, efuse_size);
PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
PLTFM_MEMCPY(map, efuse_map, efuse_size - PROTECT_EFUSE_SIZE);
PLTFM_MEMCPY(map + efuse_size - PROTECT_EFUSE_SIZE +
#if HALMAC_PLATFORM_WINDOWS
PLTFM_MEMCPY(map, efuse_map, efuse_size);
#else
PLTFM_MEMCPY(map, efuse_map, efuse_size - prtct_efuse_size);
PLTFM_MEMCPY(map + efuse_size - prtct_efuse_size +
RSVD_CS_EFUSE_SIZE,
efuse_map + efuse_size - PROTECT_EFUSE_SIZE +
efuse_map + efuse_size - prtct_efuse_size +
RSVD_CS_EFUSE_SIZE,
PROTECT_EFUSE_SIZE - RSVD_EFUSE_SIZE -
prtct_efuse_size - RSVD_EFUSE_SIZE -
RSVD_CS_EFUSE_SIZE);
#endif
PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
PLTFM_EVENT_SIG(HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE,
@@ -311,8 +312,9 @@ read_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value,
enum halmac_efuse_bank bank)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
enum halmac_cmd_process_status *proc_status =
&adapter->halmac_state.efuse_state.proc_status;
enum halmac_cmd_process_status *proc_status;
proc_status = &adapter->halmac_state.efuse_state.proc_status;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
@@ -397,8 +399,8 @@ get_efuse_available_size_88xx(struct halmac_adapter *adapter, u32 *size)
if (status != HALMAC_RET_SUCCESS)
return status;
*size = adapter->hw_cfg_info.efuse_size - PROTECT_EFUSE_SIZE -
adapter->efuse_end;
*size = adapter->hw_cfg_info.efuse_size -
adapter->hw_cfg_info.prtct_efuse_size - adapter->efuse_end;
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
@@ -460,8 +462,9 @@ dump_log_efuse_map_88xx(struct halmac_adapter *adapter,
u8 *map = NULL;
u32 size = adapter->hw_cfg_info.eeprom_size;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
enum halmac_cmd_process_status *proc_status =
&adapter->halmac_state.efuse_state.proc_status;
enum halmac_cmd_process_status *proc_status;
proc_status = &adapter->halmac_state.efuse_state.proc_status;
if (cfg == HALMAC_EFUSE_R_FW &&
halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
@@ -498,7 +501,7 @@ dump_log_efuse_map_88xx(struct halmac_adapter *adapter,
return status;
}
if (adapter->efuse_map_valid == _TRUE) {
if (adapter->efuse_map_valid == 1) {
*proc_status = HALMAC_CMD_PROCESS_DONE;
map = (u8 *)PLTFM_MALLOC(size);
@@ -889,7 +892,7 @@ read_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
/* Read efuse no need 2.5V LDO */
enable = _FALSE;
enable = 0;
status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]dis ldo25\n");
@@ -923,7 +926,8 @@ enum halmac_ret_status
write_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
{
const u8 unlock_code = 0x69;
u8 value_read = 0, enable;
u8 value_read = 0;
u8 enable;
u32 value32;
u32 tmp32;
u32 cnt;
@@ -931,13 +935,13 @@ write_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
adapter->efuse_map_valid = _FALSE;
adapter->efuse_map_valid = 0;
PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
HALMAC_REG_W8(REG_PMC_DBG_CTRL2 + 3, unlock_code);
/* Enable 2.5V LDO */
enable = _TRUE;
enable = 1;
status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]en ldo25\n");
@@ -964,7 +968,7 @@ write_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
HALMAC_REG_W8(REG_PMC_DBG_CTRL2 + 3, 0x00);
/* Disable 2.5V LDO */
enable = _FALSE;
enable = 0;
status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]dis ldo25\n");
@@ -984,7 +988,7 @@ write_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
enum halmac_ret_status
eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map)
{
u8 i;
@@ -996,6 +1000,7 @@ eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map)
u8 hdr2 = 0;
u32 eeprom_idx;
u32 efuse_idx = 0;
u32 prtct_efuse_size = adapter->hw_cfg_info.prtct_efuse_size;
struct halmac_hw_cfg_info *hw_info = &adapter->hw_cfg_info;
PLTFM_MEMSET(log_map, 0xFF, hw_info->eeprom_size);
@@ -1022,7 +1027,7 @@ eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map)
efuse_idx++;
if (efuse_idx >= hw_info->efuse_size - PROTECT_EFUSE_SIZE - 1)
if (efuse_idx >= hw_info->efuse_size - prtct_efuse_size - 1)
return HALMAC_RET_EEPROM_PARSING_FAIL;
for (i = 0; i < 4; i++) {
@@ -1050,7 +1055,7 @@ eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map)
efuse_idx++;
if (efuse_idx > hw_info->efuse_size -
PROTECT_EFUSE_SIZE - 1)
prtct_efuse_size - 1)
return HALMAC_RET_EEPROM_PARSING_FAIL;
value8 = *(phy_map + efuse_idx);
@@ -1059,7 +1064,7 @@ eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map)
efuse_idx++;
if (efuse_idx > hw_info->efuse_size -
PROTECT_EFUSE_SIZE)
prtct_efuse_size)
return HALMAC_RET_EEPROM_PARSING_FAIL;
}
}
@@ -1077,7 +1082,7 @@ read_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map)
u32 efuse_size;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (adapter->efuse_map_valid == _FALSE) {
if (adapter->efuse_map_valid == 0) {
efuse_size = adapter->hw_cfg_info.efuse_size;
local_map = (u8 *)PLTFM_MALLOC(efuse_size);
@@ -1104,7 +1109,7 @@ read_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map)
PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
PLTFM_MEMCPY(adapter->efuse_map, local_map, efuse_size);
adapter->efuse_map_valid = _TRUE;
adapter->efuse_map_valid = 1;
PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
PLTFM_FREE(local_map, efuse_size);
@@ -1175,7 +1180,7 @@ dump_efuse_drv_88xx(struct halmac_adapter *adapter)
}
}
if (adapter->efuse_map_valid == _FALSE) {
if (adapter->efuse_map_valid == 0) {
map = (u8 *)PLTFM_MALLOC(efuse_size);
if (!map) {
PLTFM_MSG_ERR("[ERR]malloc map\n");
@@ -1190,7 +1195,7 @@ dump_efuse_drv_88xx(struct halmac_adapter *adapter)
PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
PLTFM_MEMCPY(adapter->efuse_map, map, efuse_size);
adapter->efuse_map_valid = _TRUE;
adapter->efuse_map_valid = 1;
PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
PLTFM_FREE(map, efuse_size);
@@ -1210,7 +1215,7 @@ dump_efuse_fw_88xx(struct halmac_adapter *adapter)
hdr_info.sub_cmd_id = SUB_CMD_ID_DUMP_PHYSICAL_EFUSE;
hdr_info.content_size = 0;
hdr_info.ack = _TRUE;
hdr_info.ack = 1;
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
adapter->halmac_state.efuse_state.seq_num = seq_num;
@@ -1225,7 +1230,7 @@ dump_efuse_fw_88xx(struct halmac_adapter *adapter)
}
}
if (adapter->efuse_map_valid == _FALSE) {
if (adapter->efuse_map_valid == 0) {
status = send_h2c_pkt_88xx(adapter, h2c_buf);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]send h2c pkt\n");
@@ -1249,6 +1254,7 @@ proc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
u8 hdr2;
u8 *map = NULL;
u32 eeprom_size = adapter->hw_cfg_info.eeprom_size;
u32 prtct_efuse_size = adapter->hw_cfg_info.prtct_efuse_size;
u32 end;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
@@ -1289,7 +1295,7 @@ proc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
if (offset > 0x7f) {
if (adapter->hw_cfg_info.efuse_size <=
4 + PROTECT_EFUSE_SIZE + end) {
4 + prtct_efuse_size + end) {
PLTFM_FREE(map, eeprom_size);
return HALMAC_RET_EFUSE_NOT_ENOUGH;
}
@@ -1319,7 +1325,7 @@ proc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
}
} else {
if (adapter->hw_cfg_info.efuse_size <=
3 + PROTECT_EFUSE_SIZE + end) {
3 + prtct_efuse_size + end) {
PLTFM_FREE(map, eeprom_size);
return HALMAC_RET_EFUSE_NOT_ENOUGH;
}
@@ -1357,7 +1363,7 @@ read_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, u8 *map)
return HALMAC_RET_NULL_POINTER;
}
if (adapter->efuse_map_valid == _TRUE) {
if (adapter->efuse_map_valid == 1) {
PLTFM_MEMCPY(map, adapter->efuse_map + offset, size);
} else {
if (read_hw_efuse_88xx(adapter, offset, size, map) !=
@@ -1485,7 +1491,8 @@ check_efuse_enough_88xx(struct halmac_adapter *adapter,
}
if (adapter->hw_cfg_info.efuse_size <=
(pg_num + PROTECT_EFUSE_SIZE + adapter->efuse_end))
(pg_num + adapter->hw_cfg_info.prtct_efuse_size +
adapter->efuse_end))
return HALMAC_RET_EFUSE_NOT_ENOUGH;
return HALMAC_RET_SUCCESS;
@@ -1716,7 +1723,7 @@ get_efuse_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
buf + C2H_DATA_OFFSET_88XX, seg_size);
PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
if (EFUSE_DATA_GET_END_SEGMENT(buf) == _FALSE) {
if (EFUSE_DATA_GET_END_SEGMENT(buf) == 0) {
PLTFM_FREE(map, eeprom_size);
return HALMAC_RET_SUCCESS;
}
@@ -1728,7 +1735,7 @@ get_efuse_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
state->proc_status = proc_status;
PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
adapter->efuse_map_valid = _TRUE;
adapter->efuse_map_valid = 1;
PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
if (adapter->evnt.phy_efuse_map == 1) {
@@ -1777,6 +1784,7 @@ get_dump_phy_efuse_status_88xx(struct halmac_adapter *adapter,
{
u8 *map = NULL;
u32 efuse_size = adapter->hw_cfg_info.efuse_size;
u32 prtct_efuse_size = adapter->hw_cfg_info.prtct_efuse_size;
struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;
*proc_status = state->proc_status;
@@ -1803,12 +1811,12 @@ get_dump_phy_efuse_status_88xx(struct halmac_adapter *adapter,
PLTFM_MEMSET(map, 0xFF, efuse_size);
PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
PLTFM_MEMCPY(map, adapter->efuse_map,
efuse_size - PROTECT_EFUSE_SIZE);
PLTFM_MEMCPY(map + efuse_size - PROTECT_EFUSE_SIZE +
efuse_size - prtct_efuse_size);
PLTFM_MEMCPY(map + efuse_size - prtct_efuse_size +
RSVD_CS_EFUSE_SIZE,
adapter->efuse_map + efuse_size -
PROTECT_EFUSE_SIZE + RSVD_CS_EFUSE_SIZE,
PROTECT_EFUSE_SIZE - RSVD_EFUSE_SIZE -
prtct_efuse_size + RSVD_CS_EFUSE_SIZE,
prtct_efuse_size - RSVD_EFUSE_SIZE -
RSVD_CS_EFUSE_SIZE);
PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
@@ -1896,7 +1904,7 @@ get_h2c_ack_phy_efuse_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
u32
get_rsvd_efuse_size_88xx(struct halmac_adapter *adapter)
{
return PROTECT_EFUSE_SIZE;
return adapter->hw_cfg_info.prtct_efuse_size;
}
#endif /* HALMAC_88XX_SUPPORT */

3
hal/halmac/halmac_88xx/halmac_efuse_88xx.h
View File

@@ -24,6 +24,9 @@ enum halmac_ret_status
dump_efuse_map_88xx(struct halmac_adapter *adapter,
enum halmac_efuse_read_cfg cfg);
enum halmac_ret_status
eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map);
enum halmac_ret_status
dump_efuse_map_bt_88xx(struct halmac_adapter *adapter,
enum halmac_efuse_bank bank, u32 size, u8 *map);

12
hal/halmac/halmac_88xx/halmac_flash_88xx.c
View File

@@ -87,7 +87,7 @@ download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH;
hdr_info.content_size = 20;
hdr_info.ack = _TRUE;
hdr_info.ack = 1;
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
rc = send_h2c_pkt_88xx(adapter, h2c_buf);
@@ -131,7 +131,7 @@ download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
read_flash_88xx(struct halmac_adapter *adapter, u32 addr)
read_flash_88xx(struct halmac_adapter *adapter, u32 addr, u32 length)
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
enum halmac_ret_status status;
@@ -168,13 +168,13 @@ read_flash_88xx(struct halmac_adapter *adapter, u32 addr)
/* Construct H2C Content */
DOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, 0x03);
DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, h2c_info_addr - rsvd_pg_addr);
DOWNLOAD_FLASH_SET_SIZE(h2c_buf, 4096);
DOWNLOAD_FLASH_SET_SIZE(h2c_buf, length);
DOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, addr);
/* Fill in H2C Header */
hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH;
hdr_info.content_size = 16;
hdr_info.ack = _TRUE;
hdr_info.ack = 1;
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
/* Send H2C Cmd Packet */
@@ -231,7 +231,7 @@ erase_flash_88xx(struct halmac_adapter *adapter, u8 erase_cmd, u32 addr)
/* Fill in H2C Header */
hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH;
hdr_info.content_size = 16;
hdr_info.ack = _TRUE;
hdr_info.ack = 1;
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
/* Send H2C Cmd Packet */
@@ -286,7 +286,7 @@ check_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
else
pkt_size = size;
read_flash_88xx(adapter, addr);
read_flash_88xx(adapter, addr, 4096);
cnt = 0;
while (cnt < pkt_size) {

2
hal/halmac/halmac_88xx/halmac_flash_88xx.h
View File

@@ -25,7 +25,7 @@ download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
u32 rom_addr);
enum halmac_ret_status
read_flash_88xx(struct halmac_adapter *adapter, u32 addr);
read_flash_88xx(struct halmac_adapter *adapter, u32 addr, u32 length);
enum halmac_ret_status
erase_flash_88xx(struct halmac_adapter *adapter, u8 erase_cmd, u32 addr);

133
hal/halmac/halmac_88xx/halmac_fw_88xx.c
View File

@@ -243,14 +243,13 @@ start_dlfw_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
enum halmac_ret_status status;
dmem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_DMEM_SIZE));
imem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_IMEM_SIZE));
dmem_size =
rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_DMEM_SIZE)));
imem_size =
rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_IMEM_SIZE)));
if (0 != ((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4)))
emem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_EMEM_SIZE));
dmem_size = rtk_le32_to_cpu(dmem_size);
imem_size = rtk_le32_to_cpu(imem_size);
emem_size = rtk_le32_to_cpu(emem_size);
emem_size =
rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_EMEM_SIZE)));
dmem_size += WLAN_FW_HDR_CHKSUM_SIZE;
imem_size += WLAN_FW_HDR_CHKSUM_SIZE;
@@ -268,15 +267,15 @@ start_dlfw_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
HALMAC_REG_W16(REG_MCUFW_CTRL, value16);
cur_fw = fw_bin + WLAN_FW_HDR_SIZE;
addr = *((u32 *)(fw_bin + WLAN_FW_HDR_DMEM_ADDR));
addr = rtk_le32_to_cpu(addr) & ~BIT(31);
addr = rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_DMEM_ADDR)));
addr &= ~BIT(31);
status = dlfw_to_mem_88xx(adapter, cur_fw, 0, addr, dmem_size);
if (status != HALMAC_RET_SUCCESS)
return status;
cur_fw = fw_bin + WLAN_FW_HDR_SIZE + dmem_size;
addr = *((u32 *)(fw_bin + WLAN_FW_HDR_IMEM_ADDR));
addr = rtk_le32_to_cpu(addr) & ~BIT(31);
addr = rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_IMEM_ADDR)));
addr &= ~BIT(31);
status = dlfw_to_mem_88xx(adapter, cur_fw, 0, addr, imem_size);
if (status != HALMAC_RET_SUCCESS)
return status;
@@ -285,8 +284,9 @@ DLFW_EMEM:
if (emem_size) {
cur_fw = fw_bin + WLAN_FW_HDR_SIZE +
dmem_size + imem_size;
addr = *((u32 *)(fw_bin + WLAN_FW_HDR_EMEM_ADDR));
addr = rtk_le32_to_cpu(addr) & ~BIT(31);
addr = rtk_le32_to_cpu(*((__le32 *)(fw_bin +
WLAN_FW_HDR_EMEM_ADDR)));
addr &= ~BIT(31);
status = dlfw_to_mem_88xx(adapter, cur_fw, dl_addr << 7, addr,
emem_size);
if (status != HALMAC_RET_SUCCESS)
@@ -308,15 +308,12 @@ chk_h2c_ver_88xx(struct halmac_adapter *adapter, u8 *fw_bin)
u16 halmac_h2c_ver;
u16 fw_h2c_ver;
fw_h2c_ver = *((u16 *)(fw_bin + WLAN_FW_HDR_H2C_FMT_VER));
fw_h2c_ver = rtk_le16_to_cpu(fw_h2c_ver);
fw_h2c_ver = rtk_le16_to_cpu(*((__le16 *)(fw_bin +
WLAN_FW_HDR_H2C_FMT_VER)));
halmac_h2c_ver = H2C_FORMAT_VERSION;
PLTFM_MSG_TRACE("[TRACE]halmac h2c ver = %x, fw h2c ver = %x!!\n",
halmac_h2c_ver, fw_h2c_ver);
if (fw_h2c_ver != halmac_h2c_ver)
PLTFM_MSG_WARN("[WARN]H2C/C2H ver is compatible!!\n");
}
static enum halmac_ret_status
@@ -332,14 +329,13 @@ chk_fw_size_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size)
return HALMAC_RET_FW_SIZE_ERR;
}
dmem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_DMEM_SIZE));
imem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_IMEM_SIZE));
dmem_size =
rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_DMEM_SIZE)));
imem_size =
rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_IMEM_SIZE)));
if (0 != ((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4)))
emem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_EMEM_SIZE));
dmem_size = rtk_le32_to_cpu(dmem_size);
imem_size = rtk_le32_to_cpu(imem_size);
emem_size = rtk_le32_to_cpu(emem_size);
emem_size =
rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_EMEM_SIZE)));
dmem_size += WLAN_FW_HDR_CHKSUM_SIZE;
imem_size += WLAN_FW_HDR_CHKSUM_SIZE;
@@ -469,6 +465,28 @@ DL_FREE_FW_END:
return status;
}
/**
* reset_wifi_fw_88xx() - reset wifi fw
* @adapter : the adapter of halmac
* Author : LIN YONG-CHING
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
reset_wifi_fw_88xx(struct halmac_adapter *adapter)
{
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
wlan_cpu_en_88xx(adapter, 0);
pltfm_reset_88xx(adapter);
init_ofld_feature_state_machine_88xx(adapter);
wlan_cpu_en_88xx(adapter, 1);
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* get_fw_version_88xx() - get FW version
* @adapter : the adapter of halmac
@@ -507,18 +525,18 @@ update_fw_info_88xx(struct halmac_adapter *adapter, u8 *fw_bin)
{
struct halmac_fw_version *info = &adapter->fw_ver;
info->version = *((u16 *)(fw_bin + WLAN_FW_HDR_VERSION));
info->version = rtk_le16_to_cpu(info->version);
info->version =
rtk_le16_to_cpu(*((__le16 *)(fw_bin + WLAN_FW_HDR_VERSION)));
info->sub_version = *(fw_bin + WLAN_FW_HDR_SUBVERSION);
info->sub_index = *(fw_bin + WLAN_FW_HDR_SUBINDEX);
info->h2c_version = *((u16 *)(fw_bin + WLAN_FW_HDR_H2C_FMT_VER));
info->h2c_version = rtk_le16_to_cpu(info->h2c_version);
info->h2c_version = rtk_le16_to_cpu(*((__le16 *)(fw_bin +
WLAN_FW_HDR_H2C_FMT_VER)));
info->build_time.month = *(fw_bin + WLAN_FW_HDR_MONTH);
info->build_time.date = *(fw_bin + WLAN_FW_HDR_DATE);
info->build_time.hour = *(fw_bin + WLAN_FW_HDR_HOUR);
info->build_time.min = *(fw_bin + WLAN_FW_HDR_MIN);
info->build_time.year = *((u16 *)(fw_bin + WLAN_FW_HDR_YEAR));
info->build_time.year = rtk_le16_to_cpu(info->build_time.year);
info->build_time.year =
rtk_le16_to_cpu(*((__le16 *)(fw_bin + WLAN_FW_HDR_YEAR)));
PLTFM_MSG_TRACE("[TRACE]=== FW info ===\n");
PLTFM_MSG_TRACE("[TRACE]ver : %X\n", info->version);
@@ -560,7 +578,7 @@ dlfw_to_mem_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 src, u32 dest,
status = send_fwpkt_88xx(adapter, (u16)(src >> 7),
fw_bin + mem_offset, pkt_size);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]send fw pkt!!");
PLTFM_MSG_ERR("[ERR]send fw pkt!!\n");
return status;
}
@@ -570,7 +588,7 @@ dlfw_to_mem_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 src, u32 dest,
dest + mem_offset, pkt_size,
first_part);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]iddma dlfw!!");
PLTFM_MSG_ERR("[ERR]iddma dlfw!!\n");
return status;
}
@@ -581,7 +599,7 @@ dlfw_to_mem_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 src, u32 dest,
status = check_fw_chksum_88xx(adapter, dest);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]chk fw chksum!!");
PLTFM_MSG_ERR("[ERR]chk fw chksum!!\n");
return status;
}
@@ -691,8 +709,29 @@ static enum halmac_ret_status
send_fwpkt_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *fw_bin,
u32 size)
{
u8 *fw_add_dum = NULL;
enum halmac_ret_status status;
if (adapter->intf == HALMAC_INTERFACE_USB &&
!((size + TX_DESC_SIZE_88XX) & (512 - 1))) {
fw_add_dum = (u8 *)PLTFM_MALLOC(size + 1);
if (!fw_add_dum) {
PLTFM_MSG_ERR("[ERR]fw bin malloc!!\n");
return HALMAC_RET_MALLOC_FAIL;
}
PLTFM_MEMCPY(fw_add_dum, fw_bin, size);
status = dl_rsvd_page_88xx(adapter, pg_addr,
fw_add_dum, size + 1);
if (status != HALMAC_RET_SUCCESS)
PLTFM_MSG_ERR("[ERR]dl rsvd page - dum!!\n");
PLTFM_FREE(fw_add_dum, size + 1);
return status;
}
status = dl_rsvd_page_88xx(adapter, pg_addr, fw_bin, size);
if (status != HALMAC_RET_SUCCESS)
PLTFM_MSG_ERR("[ERR]dl rsvd page!!\n");
@@ -803,7 +842,7 @@ check_fw_status_88xx(struct halmac_adapter *adapter, u8 *fw_status)
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
*fw_status = _TRUE;
*fw_status = 1;
fw_dbg6 = HALMAC_REG_R32(REG_FW_DBG6);
@@ -818,7 +857,7 @@ check_fw_status_88xx(struct halmac_adapter *adapter, u8 *fw_status)
if ((fw_dbg6 & FW_STATUS_CHK_FATAL) != 0) {
PLTFM_MSG_ERR("[ERR]fw status(fatal):%X\n", fw_dbg6);
fw_fatal_status_debug_88xx(adapter);
*fw_status = _FALSE;
*fw_status = 0;
return status;
}
}
@@ -837,7 +876,7 @@ check_fw_status_88xx(struct halmac_adapter *adapter, u8 *fw_status)
cnt--;
if (cnt == 0) {
PLTFM_MSG_ERR("[ERR]fw pc\n");
*fw_status = _FALSE;
*fw_status = 0;
return status;
}
PLTFM_DELAY_US(50);
@@ -996,6 +1035,8 @@ enum halmac_ret_status
send_general_info_88xx(struct halmac_adapter *adapter,
struct halmac_general_info *info)
{
u8 h2cq_ele[4] = {0};
u32 h2cq_addr;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
@@ -1023,6 +1064,20 @@ send_general_info_88xx(struct halmac_adapter *adapter,
return status;
}
h2cq_addr = adapter->txff_alloc.rsvd_h2cq_addr;
h2cq_addr <<= TX_PAGE_SIZE_SHIFT_88XX;
status = dump_fifo_88xx(adapter, HAL_FIFO_SEL_TX,
h2cq_addr, 4, h2cq_ele);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]dump h2cq!!\n");
return status;
}
if ((h2cq_ele[0] & 0x7F) != 0x01 || h2cq_ele[1] != 0xFF) {
PLTFM_MSG_ERR("[ERR]h2cq compare!!\n");
return HALMAC_RET_SEND_H2C_FAIL;
}
if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_DONE)
adapter->halmac_state.dlfw_state = HALMAC_GEN_INFO_SENT;
@@ -1048,7 +1103,7 @@ proc_send_general_info_88xx(struct halmac_adapter *adapter,
hdr_info.sub_cmd_id = SUB_CMD_ID_GENERAL_INFO;
hdr_info.content_size = 4;
hdr_info.ack = _FALSE;
hdr_info.ack = 0;
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
status = send_h2c_pkt_88xx(adapter, h2c_buf);
@@ -1078,7 +1133,7 @@ proc_send_phydm_info_88xx(struct halmac_adapter *adapter,
hdr_info.sub_cmd_id = SUB_CMD_ID_PHYDM_INFO;
hdr_info.content_size = 8;
hdr_info.ack = _FALSE;
hdr_info.ack = 0;
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
status = send_h2c_pkt_88xx(adapter, h2c_buf);

7
hal/halmac/halmac_88xx/halmac_fw_88xx.h
View File

@@ -22,8 +22,6 @@
#define HALMC_DDMA_POLLING_COUNT 1000
#endif /* HALMAC_88XX_SUPPORT */
enum halmac_ret_status
download_firmware_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size);
@@ -31,6 +29,9 @@ enum halmac_ret_status
free_download_firmware_88xx(struct halmac_adapter *adapter,
enum halmac_dlfw_mem mem_sel, u8 *fw_bin, u32 size);
enum halmac_ret_status
reset_wifi_fw_88xx(struct halmac_adapter *adapter);
enum halmac_ret_status
get_fw_version_88xx(struct halmac_adapter *adapter,
struct halmac_fw_version *ver);
@@ -58,4 +59,6 @@ send_general_info_88xx(struct halmac_adapter *adapter,
enum halmac_ret_status
drv_fwctrl_88xx(struct halmac_adapter *adapter, u8 *payload, u32 size, u8 ack);
#endif /* HALMAC_88XX_SUPPORT */
#endif/* _HALMAC_FW_88XX_H_ */

10
hal/halmac/halmac_88xx/halmac_gpio_88xx.c
View File

@@ -273,6 +273,10 @@ pinmux_switch_88xx(struct halmac_adapter *adapter,
case HALMAC_GPIO_FUNC_SDIO_INT:
switch_func = HALMAC_SDIO_INT;
break;
case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
switch_func = HALMAC_GPIO13_14_WL_CTRL_EN;
break;
case HALMAC_GPIO_FUNC_SW_IO_0:
case HALMAC_GPIO_FUNC_SW_IO_1:
case HALMAC_GPIO_FUNC_SW_IO_2:
@@ -352,6 +356,12 @@ pinmux_record_88xx(struct halmac_adapter *adapter,
case HALMAC_GPIO_FUNC_SDIO_INT:
adapter->pinmux_info.sdio_int = val;
break;
case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
adapter->pinmux_info.bt_host_wake = val;
break;
case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
adapter->pinmux_info.bt_dev_wake = val;
break;
case HALMAC_GPIO_FUNC_SW_IO_0:
adapter->pinmux_info.sw_io_0 = val;
break;

325
hal/halmac/halmac_88xx/halmac_init_88xx.c
View File

@@ -21,9 +21,15 @@
#include "halmac_efuse_88xx.h"
#include "halmac_mimo_88xx.h"
#include "halmac_bb_rf_88xx.h"
#if HALMAC_SDIO_SUPPORT
#include "halmac_sdio_88xx.h"
#endif
#if HALMAC_USB_SUPPORT
#include "halmac_usb_88xx.h"
#endif
#if HALMAC_PCIE_SUPPORT
#include "halmac_pcie_88xx.h"
#endif
#include "halmac_gpio_88xx.h"
#include "halmac_flash_88xx.h"
@@ -39,6 +45,10 @@
#include "halmac_8822c/halmac_init_8822c.h"
#endif
#if HALMAC_8812F_SUPPORT
#include "halmac_8812f/halmac_init_8812f.h"
#endif
#if HALMAC_PLATFORM_TESTPROGRAM
#include "halmisc_api_88xx.h"
#endif
@@ -49,48 +59,6 @@
#define PLTFM_INFO_RSVD_PG_SIZE 16384
#define DLFW_PKT_MAX_SIZE 8192 /* need multiple of 2 */
#define SYS_FUNC_EN 0xDC
#define WLAN_SLOT_TIME 0x05
#define WLAN_PIFS_TIME 0x19
#define WLAN_SIFS_CCK_CONT_TX 0xA
#define WLAN_SIFS_OFDM_CONT_TX 0xA
#define WLAN_SIFS_CCK_TRX 0x10
#define WLAN_SIFS_OFDM_TRX 0x10
#define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */
#define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */
#define WLAN_RDG_NAV 0x05
#define WLAN_TXOP_NAV 0x1B
#define WLAN_CCK_RX_TSF 0x30
#define WLAN_OFDM_RX_TSF 0x30
#define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
#define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
#define WLAN_DRV_EARLY_INT 0x04
#define WLAN_BCN_DMA_TIME 0x02
#define WLAN_ACK_TO_CCK 0x40
#define WLAN_RX_FILTER0 0x0FFFFFFF
#define WLAN_RX_FILTER2 0xFFFF
#define WLAN_RCR_CFG 0xE400220E
#define WLAN_RXPKT_MAX_SZ 12288
#define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9)
#define WLAN_TX_FUNC_CFG1 0x30
#define WLAN_TX_FUNC_CFG2 0x30
#define WLAN_MAC_OPT_NORM_FUNC1 0x98
#define WLAN_MAC_OPT_LB_FUNC1 0x80
#define WLAN_MAC_OPT_FUNC2 0x30810041
#define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \
(WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
(WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
(WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
#define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
(WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
#define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
#define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
static void
init_state_machine_88xx(struct halmac_adapter *adapter);
@@ -109,7 +77,7 @@ init_adapter_param_88xx(struct halmac_adapter *adapter)
adapter->api_registry.sdio_cmd53_4byte_en = 1;
adapter->efuse_map = (u8 *)NULL;
adapter->efuse_map_valid = _FALSE;
adapter->efuse_map_valid = 0;
adapter->efuse_end = 0;
adapter->dlfw_pkt_size = DLFW_PKT_MAX_SIZE;
@@ -119,7 +87,7 @@ init_adapter_param_88xx(struct halmac_adapter *adapter)
adapter->cfg_param_info.buf = NULL;
adapter->cfg_param_info.buf_wptr = NULL;
adapter->cfg_param_info.num = 0;
adapter->cfg_param_info.full_fifo_mode = _FALSE;
adapter->cfg_param_info.full_fifo_mode = 0;
adapter->cfg_param_info.buf_size = 0;
adapter->cfg_param_info.avl_buf_size = 0;
adapter->cfg_param_info.offset_accum = 0;
@@ -134,7 +102,7 @@ init_adapter_param_88xx(struct halmac_adapter *adapter)
adapter->ch_sw_info.ch_num = 0;
adapter->drv_info_size = 0;
adapter->tx_desc_transfer = _FALSE;
adapter->tx_desc_transfer = 0;
adapter->txff_alloc.tx_fifo_pg_num = 0;
adapter->txff_alloc.acq_pg_num = 0;
@@ -193,6 +161,13 @@ init_adapter_param_88xx(struct halmac_adapter *adapter)
adapter->pcie_refautok_en = 1;
adapter->pwr_off_flow_flag = 0;
adapter->rx_ignore_info.hdr_chk_mask = 1;
adapter->rx_ignore_info.fcs_chk_mask = 1;
adapter->rx_ignore_info.hdr_chk_en = 0;
adapter->rx_ignore_info.fcs_chk_en = 0;
adapter->rx_ignore_info.cck_rst_en = 0;
adapter->rx_ignore_info.fcs_chk_thr = HALMAC_PSF_FCS_CHK_THR_28;
init_adapter_dynamic_param_88xx(adapter);
init_state_machine_88xx(adapter);
}
@@ -223,6 +198,7 @@ mount_api_88xx(struct halmac_adapter *adapter)
api->halmac_register_api = register_api_88xx;
api->halmac_download_firmware = download_firmware_88xx;
api->halmac_free_download_firmware = free_download_firmware_88xx;
api->halmac_reset_wifi_fw = reset_wifi_fw_88xx;
api->halmac_get_fw_version = get_fw_version_88xx;
api->halmac_cfg_mac_addr = cfg_mac_addr_88xx;
api->halmac_cfg_bssid = cfg_bssid_88xx;
@@ -232,13 +208,9 @@ mount_api_88xx(struct halmac_adapter *adapter)
api->halmac_cfg_bcn_space = cfg_bcn_space_88xx;
api->halmac_rw_bcn_ctrl = rw_bcn_ctrl_88xx;
api->halmac_cfg_multicast_addr = cfg_multicast_addr_88xx;
api->halmac_pre_init_system_cfg = pre_init_system_cfg_88xx;
api->halmac_init_system_cfg = init_system_cfg_88xx;
api->halmac_init_edca_cfg = init_edca_cfg_88xx;
api->halmac_cfg_operation_mode = cfg_operation_mode_88xx;
api->halmac_cfg_ch_bw = cfg_ch_bw_88xx;
api->halmac_cfg_bw = cfg_bw_88xx;
api->halmac_init_wmac_cfg = init_wmac_cfg_88xx;
api->halmac_init_mac_cfg = init_mac_cfg_88xx;
api->halmac_dump_efuse_map = dump_efuse_map_88xx;
api->halmac_dump_efuse_map_bt = dump_efuse_map_bt_88xx;
@@ -315,15 +287,6 @@ mount_api_88xx(struct halmac_adapter *adapter)
api->halmac_dl_drv_rsvd_page = dl_drv_rsvd_page_88xx;
api->halmac_cfg_csi_rate = cfg_csi_rate_88xx;
api->halmac_sdio_cmd53_4byte = sdio_cmd53_4byte_88xx;
api->halmac_sdio_hw_info = sdio_hw_info_88xx;
api->halmac_init_sdio_cfg = init_sdio_cfg_88xx;
api->halmac_init_usb_cfg = init_usb_cfg_88xx;
api->halmac_init_pcie_cfg = init_pcie_cfg_88xx;
api->halmac_deinit_sdio_cfg = deinit_sdio_cfg_88xx;
api->halmac_deinit_usb_cfg = deinit_usb_cfg_88xx;
api->halmac_deinit_pcie_cfg = deinit_pcie_cfg_88xx;
api->halmac_txfifo_is_empty = txfifo_is_empty_88xx;
api->halmac_download_flash = download_flash_88xx;
api->halmac_read_flash = read_flash_88xx;
@@ -344,9 +307,11 @@ mount_api_88xx(struct halmac_adapter *adapter)
api->halmac_enter_cpu_sleep_mode = enter_cpu_sleep_mode_88xx;
api->halmac_get_cpu_mode = get_cpu_mode_88xx;
api->halmac_drv_fwctrl = drv_fwctrl_88xx;
api->halmac_en_ref_autok_pcie = en_ref_autok_88xx;
if (adapter->intf == HALMAC_INTERFACE_SDIO) {
#if HALMAC_SDIO_SUPPORT
api->halmac_init_sdio_cfg = init_sdio_cfg_88xx;
api->halmac_deinit_sdio_cfg = deinit_sdio_cfg_88xx;
api->halmac_cfg_rx_aggregation = cfg_sdio_rx_agg_88xx;
api->halmac_init_interface_cfg = init_sdio_cfg_88xx;
api->halmac_deinit_interface_cfg = deinit_sdio_cfg_88xx;
@@ -355,7 +320,14 @@ mount_api_88xx(struct halmac_adapter *adapter)
api->halmac_get_usb_bulkout_id = get_sdio_bulkout_id_88xx;
api->halmac_reg_read_indirect_32 = sdio_indirect_reg_r32_88xx;
api->halmac_reg_sdio_cmd53_read_n = sdio_reg_rn_88xx;
api->halmac_sdio_cmd53_4byte = sdio_cmd53_4byte_88xx;
api->halmac_sdio_hw_info = sdio_hw_info_88xx;
#endif
} else if (adapter->intf == HALMAC_INTERFACE_USB) {
#if HALMAC_USB_SUPPORT
api->halmac_init_usb_cfg = init_usb_cfg_88xx;
api->halmac_deinit_usb_cfg = deinit_usb_cfg_88xx;
api->halmac_cfg_rx_aggregation = cfg_usb_rx_agg_88xx;
api->halmac_init_interface_cfg = init_usb_cfg_88xx;
api->halmac_deinit_interface_cfg = deinit_usb_cfg_88xx;
@@ -372,7 +344,11 @@ mount_api_88xx(struct halmac_adapter *adapter)
api->halmac_reg_write_32 = reg_w32_usb_88xx;
api->halmac_reg_read_indirect_32 = usb_indirect_reg_r32_88xx;
api->halmac_reg_sdio_cmd53_read_n = usb_reg_rn_88xx;
#endif
} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
#if HALMAC_PCIE_SUPPORT
api->halmac_init_pcie_cfg = init_pcie_cfg_88xx;
api->halmac_deinit_pcie_cfg = deinit_pcie_cfg_88xx;
api->halmac_cfg_rx_aggregation = cfg_pcie_rx_agg_88xx;
api->halmac_init_interface_cfg = init_pcie_cfg_88xx;
api->halmac_deinit_interface_cfg = deinit_pcie_cfg_88xx;
@@ -389,6 +365,8 @@ mount_api_88xx(struct halmac_adapter *adapter)
api->halmac_reg_write_32 = reg_w32_pcie_88xx;
api->halmac_reg_read_indirect_32 = pcie_indirect_reg_r32_88xx;
api->halmac_reg_sdio_cmd53_read_n = pcie_reg_rn_88xx;
api->halmac_en_ref_autok_pcie = en_ref_autok_88xx;
#endif
} else {
PLTFM_MSG_ERR("[ERR]Set halmac io function Error!!\n");
}
@@ -404,6 +382,10 @@ mount_api_88xx(struct halmac_adapter *adapter)
} else if (adapter->chip_id == HALMAC_CHIP_ID_8822C) {
#if HALMAC_8822C_SUPPORT
mount_api_8822c(adapter);
#endif
} else if (adapter->chip_id == HALMAC_CHIP_ID_8812F) {
#if HALMAC_8812F_SUPPORT
mount_api_8812f(adapter);
#endif
} else {
PLTFM_MSG_ERR("[ERR]Chip ID undefine!!\n");
@@ -498,206 +480,6 @@ register_api_88xx(struct halmac_adapter *adapter,
return HALMAC_RET_SUCCESS;
}
/**
* pre_init_system_cfg_88xx() - pre-init system config
* @adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
pre_init_system_cfg_88xx(struct halmac_adapter *adapter)
{
u32 value32;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
u8 enable_bb;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
HALMAC_REG_W8(REG_RSV_CTRL, 0);
if (adapter->intf == HALMAC_INTERFACE_SDIO) {
if (leave_sdio_suspend_88xx(adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
} else if (adapter->intf == HALMAC_INTERFACE_USB) {
if (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20)
HALMAC_REG_W8(0xFE5B, HALMAC_REG_R8(0xFE5B) | BIT(4));
} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
/* For PCIE power on fail issue */
HALMAC_REG_W8(REG_HCI_OPT_CTRL + 1,
HALMAC_REG_R8(REG_HCI_OPT_CTRL + 1) | BIT(0));
}
/* Config PIN Mux */
value32 = HALMAC_REG_R32(REG_PAD_CTRL1);
value32 = value32 & (~(BIT(28) | BIT(29)));
value32 = value32 | BIT(28) | BIT(29);
HALMAC_REG_W32(REG_PAD_CTRL1, value32);
value32 = HALMAC_REG_R32(REG_LED_CFG);
value32 = value32 & (~(BIT(25) | BIT(26)));
HALMAC_REG_W32(REG_LED_CFG, value32);
value32 = HALMAC_REG_R32(REG_GPIO_MUXCFG);
value32 = value32 & (~(BIT(2)));
value32 = value32 | BIT(2);
HALMAC_REG_W32(REG_GPIO_MUXCFG, value32);
enable_bb = _FALSE;
set_hw_value_88xx(adapter, HALMAC_HW_EN_BB_RF, &enable_bb);
if (HALMAC_REG_R8(REG_SYS_CFG1 + 2) & BIT(4)) {
PLTFM_MSG_ERR("[ERR]test mode!!\n");
return HALMAC_RET_WLAN_MODE_FAIL;
}
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* init_system_cfg_88xx() - init system config
* @adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
init_system_cfg_88xx(struct halmac_adapter *adapter)
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
u32 tmp = 0;
u32 value32;
enum halmac_ret_status status;
u8 hwval;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (adapter->intf == HALMAC_INTERFACE_PCIE) {
hwval = 1;
status = api->halmac_set_hw_value(adapter,
HALMAC_HW_PCIE_REF_AUTOK,
&hwval);
if (status != HALMAC_RET_SUCCESS)
return status;
}
HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, SYS_FUNC_EN);
value32 = HALMAC_REG_R32(REG_SYS_SDIO_CTRL) | BIT_LTE_MUX_CTRL_PATH;
HALMAC_REG_W32(REG_SYS_SDIO_CTRL, value32);
value32 = HALMAC_REG_R32(REG_CPU_DMEM_CON) | BIT_WL_PLATFORM_RST;
#if HALMAC_8822C_SUPPORT
if (adapter->chip_id != HALMAC_CHIP_ID_8822B &&
adapter->chip_id != HALMAC_CHIP_ID_8821C)
value32 |= BIT_DDMA_EN;
#endif
HALMAC_REG_W32(REG_CPU_DMEM_CON, value32);
/*disable boot-from-flash for driver's DL FW*/
tmp = HALMAC_REG_R32(REG_MCUFW_CTRL);
if (tmp & BIT_BOOT_FSPI_EN) {
HALMAC_REG_W32(REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN));
value32 = HALMAC_REG_R32(REG_GPIO_MUXCFG) & (~BIT_FSPI_EN);
HALMAC_REG_W32(REG_GPIO_MUXCFG, value32);
}
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* init_edca_cfg_88xx() - init EDCA config
* @adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
init_edca_cfg_88xx(struct halmac_adapter *adapter)
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
/* Clear TX pause */
HALMAC_REG_W16(REG_TXPAUSE, 0x0000);
HALMAC_REG_W8(REG_SLOT, WLAN_SLOT_TIME);
HALMAC_REG_W8(REG_PIFS, WLAN_PIFS_TIME);
HALMAC_REG_W32(REG_SIFS, WLAN_SIFS_CFG);
HALMAC_REG_W16(REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
HALMAC_REG_W16(REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
HALMAC_REG_W32(REG_RD_NAV_NXT, WLAN_NAV_CFG);
HALMAC_REG_W16(REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
/* Set beacon cotnrol - enable TSF and other related functions */
HALMAC_REG_W8(REG_BCN_CTRL, (u8)(HALMAC_REG_R8(REG_BCN_CTRL) |
BIT_EN_BCN_FUNCTION));
/* Set send beacon related registers */
HALMAC_REG_W32(REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
HALMAC_REG_W8(REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
HALMAC_REG_W8(REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* init_wmac_cfg_88xx() - init wmac config
* @adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
init_wmac_cfg_88xx(struct halmac_adapter *adapter)
{
u8 value8;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
HALMAC_REG_W32(REG_RXFLTMAP0, WLAN_RX_FILTER0);
HALMAC_REG_W16(REG_RXFLTMAP2, WLAN_RX_FILTER2);
HALMAC_REG_W32(REG_RCR, WLAN_RCR_CFG);
HALMAC_REG_W8(REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
HALMAC_REG_W8(REG_TCR + 2, WLAN_TX_FUNC_CFG2);
HALMAC_REG_W8(REG_TCR + 1, WLAN_TX_FUNC_CFG1);
#if HALMAC_8821C_SUPPORT
if (adapter->chip_id == HALMAC_CHIP_ID_8821C)
HALMAC_REG_W8(REG_ACKTO_CCK, WLAN_ACK_TO_CCK);
#endif
HALMAC_REG_W32(REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
if (adapter->hw_cfg_info.trx_mode == HALMAC_TRNSFER_NORMAL)
value8 = WLAN_MAC_OPT_NORM_FUNC1;
else
value8 = WLAN_MAC_OPT_LB_FUNC1;
HALMAC_REG_W8(REG_WMAC_OPTION_FUNCTION + 4, value8);
status = api->halmac_init_low_pwr(adapter);
if (status != HALMAC_RET_SUCCESS)
return status;
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* init_mac_cfg_88xx() - config page1~page7 register
* @adapter : the adapter of halmac
@@ -712,7 +494,7 @@ init_mac_cfg_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode)
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__, mode);
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
status = api->halmac_init_trx_cfg(adapter, mode);
if (status != HALMAC_RET_SUCCESS) {
@@ -726,13 +508,13 @@ init_mac_cfg_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode)
return status;
}
status = init_edca_cfg_88xx(adapter);
status = api->halmac_init_edca_cfg(adapter);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]init edca %x\n", status);
return status;
}
status = init_wmac_cfg_88xx(adapter);
status = api->halmac_init_wmac_cfg(adapter);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]init wmac %x\n", status);
return status;
@@ -854,7 +636,7 @@ tx_desc_chksum_88xx(struct halmac_adapter *adapter, u8 enable)
adapter->tx_desc_checksum = enable;
value16 = HALMAC_REG_R16(REG_TXDMA_OFFSET_CHK);
if (enable == _TRUE)
if (enable == 1)
HALMAC_REG_W16(REG_TXDMA_OFFSET_CHK, value16 | BIT(13));
else
HALMAC_REG_W16(REG_TXDMA_OFFSET_CHK, value16 & ~BIT(13));
@@ -875,9 +657,11 @@ verify_io_88xx(struct halmac_adapter *adapter)
offset = REG_PAGE5_DUMMY;
if (0 == (offset & 0xFFFF0000))
offset |= WLAN_IOREG_OFFSET;
#if HALMAC_SDIO_SUPPORT
ret_status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
#else
return HALMAC_RET_WRONG_INTF;
#endif
/* Verify CMD52 R/W */
wvalue8 = 0xab;
PLTFM_SDIO_CMD52_W(offset, wvalue8);
@@ -945,7 +729,8 @@ verify_send_rsvd_page_88xx(struct halmac_adapter *adapter)
u8 *rsvd_buf = NULL;
u8 *rsvd_page = NULL;
u32 i;
u32 pkt_size = 64, payload = 0xab;
u32 pkt_size = 64;
u32 payload = 0xab;
enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;
rsvd_buf = (u8 *)PLTFM_MALLOC(pkt_size);
@@ -1002,8 +787,12 @@ pg_num_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode,
struct halmac_pg_num *tbl)
{
u8 flag;
u16 hpq_num = 0, lpq_num = 0, npq_num = 0, gapq_num = 0;
u16 expq_num = 0, pubq_num = 0;
u16 hpq_num = 0;
u16 lpq_num = 0;
u16 npq_num = 0;
u16 gapq_num = 0;
u16 expq_num = 0;
u16 pubq_num = 0;
u32 i = 0;
flag = 0;

12
hal/halmac/halmac_88xx/halmac_init_88xx.h
View File

@@ -33,18 +33,6 @@ init_adapter_dynamic_param_88xx(struct halmac_adapter *adapter);
enum halmac_ret_status
mount_api_88xx(struct halmac_adapter *adapter);
enum halmac_ret_status
pre_init_system_cfg_88xx(struct halmac_adapter *adapter);
enum halmac_ret_status
init_system_cfg_88xx(struct halmac_adapter *adapter);
enum halmac_ret_status
init_edca_cfg_88xx(struct halmac_adapter *adapter);
enum halmac_ret_status
init_wmac_cfg_88xx(struct halmac_adapter *adapter);
enum halmac_ret_status
init_mac_cfg_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode);

27
hal/halmac/halmac_88xx/halmac_mimo_88xx.c
View File

@@ -22,6 +22,7 @@
#define TXBF_CTRL_CFG (BIT_R_ENABLE_NDPA | BIT_USE_NDPA_PARAMETER | \
BIT_R_EN_NDPA_INT | BIT_DIS_NDP_BFEN)
#define CSI_RATE_MAP 0x292911
static void
cfg_mu_bfee_88xx(struct halmac_adapter *adapter,
@@ -153,7 +154,7 @@ cfg_mu_bfer_88xx(struct halmac_adapter *adapter,
u32 gid_valid[6] = {0};
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
if (param->mu_tx_en == _FALSE) {
if (param->mu_tx_en == 0) {
HALMAC_REG_W8(REG_MU_TX_CTL,
HALMAC_REG_R8(REG_MU_TX_CTL) & ~(BIT(7)));
return;
@@ -211,7 +212,7 @@ cfg_mu_bfer_88xx(struct halmac_adapter *adapter,
/*To validate the sounding successful MU STA and enable MU TX*/
for (i = 0; i < 6; i++) {
if (param->sounding_sts[i] == _TRUE)
if (param->sounding_sts[i] == 1)
mu_tbl_valid |= BIT(i);
}
HALMAC_REG_W8(REG_MU_TX_CTL, mu_tbl_valid | BIT(7));
@@ -252,6 +253,16 @@ cfg_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role,
HALMAC_REG_W8(REG_SND_PTCL_CTRL + 3, 0x26);
HALMAC_REG_W8_CLR(REG_RXFLTMAP1, BIT(4));
HALMAC_REG_W8_CLR(REG_RXFLTMAP4, BIT(4));
#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
if (adapter->chip_id == HALMAC_CHIP_ID_8822C)
HALMAC_REG_W32(REG_CSI_RRSR,
BIT_CSI_RRSC_BITMAP(CSI_RATE_MAP) |
BIT_OFDM_LEN_TH(0));
else if (adapter->chip_id == HALMAC_CHIP_ID_8812F)
HALMAC_REG_W32(REG_CSI_RRSR,
BIT_CSI_RRSC_BITMAP(CSI_RATE_MAP) |
BIT_OFDM_LEN_TH(3));
#endif
break;
default:
return HALMAC_RET_INVALID_SOUNDING_SETTING;
@@ -740,7 +751,7 @@ fw_snding_88xx(struct halmac_adapter *adapter,
hdr_info.sub_cmd_id = SUB_CMD_ID_FW_SNDING;
hdr_info.content_size = 8;
hdr_info.ack = _TRUE;
hdr_info.ack = 1;
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
adapter->halmac_state.fw_snding_state.seq_num = seq_num;
@@ -767,7 +778,7 @@ snding_pkt_chk_88xx(struct halmac_adapter *adapter, u8 *pkt)
if (GET_TX_DESC_NDPA(pkt) == 0) {
PLTFM_MSG_ERR("[ERR]txdesc ndpa = 0\n");
return _FALSE;
return 0;
}
data_rate = (u8)GET_TX_DESC_DATARATE(pkt);
@@ -775,21 +786,21 @@ snding_pkt_chk_88xx(struct halmac_adapter *adapter, u8 *pkt)
data_rate <= HALMAC_VHT_NSS2_MCS9)) {
if (!(data_rate >= HALMAC_MCS8 && data_rate <= HALMAC_MCS15)) {
PLTFM_MSG_ERR("[ERR]txdesc rate\n");
return _FALSE;
return 0;
}
}
if (GET_TX_DESC_NAVUSEHDR(pkt) == 0) {
PLTFM_MSG_ERR("[ERR]txdesc navusehdr = 0\n");
return _FALSE;
return 0;
}
if (GET_TX_DESC_USE_RATE(pkt) == 0) {
PLTFM_MSG_ERR("[ERR]txdesc userate = 0\n");
return _FALSE;
return 0;
}
return _TRUE;
return 1;
}
static enum halmac_cmd_construct_state

543
hal/halmac/halmac_88xx/halmac_pcie_88xx.c
View File

@@ -1,543 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "halmac_pcie_88xx.h"
#if HALMAC_88XX_SUPPORT
/**
* init_pcie_cfg_88xx() - init PCIe
* @adapter : the adapter of halmac
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
init_pcie_cfg_88xx(struct halmac_adapter *adapter)
{
if (adapter->intf != HALMAC_INTERFACE_PCIE)
return HALMAC_RET_WRONG_INTF;
return HALMAC_RET_SUCCESS;
}
/**
* deinit_pcie_cfg_88xx() - deinit PCIE
* @adapter : the adapter of halmac
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
deinit_pcie_cfg_88xx(struct halmac_adapter *adapter)
{
if (adapter->intf != HALMAC_INTERFACE_PCIE)
return HALMAC_RET_WRONG_INTF;
return HALMAC_RET_SUCCESS;
}
/**
* cfg_pcie_rx_agg_88xx() - config rx aggregation
* @adapter : the adapter of halmac
* @halmac_rx_agg_mode
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
cfg_pcie_rx_agg_88xx(struct halmac_adapter *adapter,
struct halmac_rxagg_cfg *cfg)
{
return HALMAC_RET_SUCCESS;
}
/**
* reg_r8_pcie_88xx() - read 1byte register
* @adapter : the adapter of halmac
* @offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u8
reg_r8_pcie_88xx(struct halmac_adapter *adapter, u32 offset)
{
return PLTFM_REG_R8(offset);
}
/**
* reg_w8_pcie_88xx() - write 1byte register
* @adapter : the adapter of halmac
* @offset : register offset
* @value : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
reg_w8_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
{
PLTFM_REG_W8(offset, value);
return HALMAC_RET_SUCCESS;
}
/**
* reg_r16_pcie_88xx() - read 2byte register
* @adapter : the adapter of halmac
* @offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u16
reg_r16_pcie_88xx(struct halmac_adapter *adapter, u32 offset)
{
return PLTFM_REG_R16(offset);
}
/**
* reg_w16_pcie_88xx() - write 2byte register
* @adapter : the adapter of halmac
* @offset : register offset
* @value : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
reg_w16_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u16 value)
{
PLTFM_REG_W16(offset, value);
return HALMAC_RET_SUCCESS;
}
/**
* reg_r32_pcie_88xx() - read 4byte register
* @adapter : the adapter of halmac
* @offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u32
reg_r32_pcie_88xx(struct halmac_adapter *adapter, u32 offset)
{
return PLTFM_REG_R32(offset);
}
/**
* reg_w32_pcie_88xx() - write 4byte register
* @adapter : the adapter of halmac
* @offset : register offset
* @value : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
reg_w32_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u32 value)
{
PLTFM_REG_W32(offset, value);
return HALMAC_RET_SUCCESS;
}
/**
* cfg_txagg_pcie_align_88xx() -config sdio bus tx agg alignment
* @adapter : the adapter of halmac
* @enable : function enable(1)/disable(0)
* @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
* Author : Soar Tu
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
cfg_txagg_pcie_align_88xx(struct halmac_adapter *adapter, u8 enable,
u16 align_size)
{
return HALMAC_RET_NOT_SUPPORT;
}
/**
* tx_allowed_pcie_88xx() - check tx status
* @adapter : the adapter of halmac
* @buf : tx packet, include txdesc
* @size : tx packet size, include txdesc
* Author : Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
tx_allowed_pcie_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
{
return HALMAC_RET_NOT_SUPPORT;
}
/**
* pcie_indirect_reg_r32_88xx() - read MAC reg by SDIO reg
* @adapter : the adapter of halmac
* @offset : register offset
* Author : Soar
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u32
pcie_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset)
{
return 0xFFFFFFFF;
}
/**
* pcie_reg_rn_88xx() - read n byte register
* @adapter : the adapter of halmac
* @offset : register offset
* @size : register value size
* @value : register value
* Author : Soar
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
pcie_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
u8 *value)
{
return HALMAC_RET_NOT_SUPPORT;
}
/**
* set_pcie_bulkout_num_88xx() - inform bulk-out num
* @adapter : the adapter of halmac
* @num : usb bulk-out number
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
set_pcie_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num)
{
return HALMAC_RET_NOT_SUPPORT;
}
/**
* get_pcie_tx_addr_88xx() - get CMD53 addr for the TX packet
* @adapter : the adapter of halmac
* @buf : tx packet, include txdesc
* @size : tx packet size
* @cmd53_addr : cmd53 addr value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
get_pcie_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
u32 *cmd53_addr)
{
return HALMAC_RET_NOT_SUPPORT;
}
/**
* get_pcie_bulkout_id_88xx() - get bulk out id for the TX packet
* @adapter : the adapter of halmac
* @buf : tx packet, include txdesc
* @size : tx packet size
* @id : usb bulk-out id
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
get_pcie_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
u8 *id)
{
return HALMAC_RET_NOT_SUPPORT;
}
enum halmac_ret_status
mdio_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed)
{
u8 tmp_u1b = 0;
u32 cnt = 0;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
u8 real_addr = 0;
HALMAC_REG_W16(REG_MDIO_V1, data);
real_addr = (addr & 0x1F);
HALMAC_REG_W8(REG_PCIE_MIX_CFG, real_addr);
if (speed == HAL_INTF_PHY_PCIE_GEN1) {
if (addr < 0x20)
HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x00);
else
HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x01);
} else if (speed == HAL_INTF_PHY_PCIE_GEN2) {
if (addr < 0x20)
HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x02);
else
HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x03);
} else {
PLTFM_MSG_ERR("[ERR]Error Speed !\n");
}
HALMAC_REG_W8_SET(REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1);
tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1;
cnt = 20;
while (tmp_u1b && (cnt != 0)) {
PLTFM_DELAY_US(10);
tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1;
cnt--;
}
if (tmp_u1b) {
PLTFM_MSG_ERR("[ERR]MDIO write fail!\n");
return HALMAC_RET_FAIL;
}
return HALMAC_RET_SUCCESS;
}
u16
mdio_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed)
{
u16 ret = 0;
u8 tmp_u1b = 0;
u32 cnt = 0;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
u8 real_addr = 0;
real_addr = (addr & 0x1F);
HALMAC_REG_W8(REG_PCIE_MIX_CFG, real_addr);
if (speed == HAL_INTF_PHY_PCIE_GEN1) {
if (addr < 0x20)
HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x00);
else
HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x01);
} else if (speed == HAL_INTF_PHY_PCIE_GEN2) {
if (addr < 0x20)
HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x02);
else
HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x03);
} else {
PLTFM_MSG_ERR("[ERR]Error Speed !\n");
}
HALMAC_REG_W8_SET(REG_PCIE_MIX_CFG, BIT_MDIO_RFLAG_V1);
tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1;
cnt = 20;
while (tmp_u1b && (cnt != 0)) {
PLTFM_DELAY_US(10);
tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1;
cnt--;
}
if (tmp_u1b) {
ret = 0xFFFF;
PLTFM_MSG_ERR("[ERR]MDIO read fail!\n");
} else {
ret = HALMAC_REG_R16(REG_MDIO_V1 + 2);
PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret);
}
return ret;
}
enum halmac_ret_status
dbi_w32_88xx(struct halmac_adapter *adapter, u16 addr, u32 data)
{
u8 tmp_u1b = 0;
u32 cnt = 0;
u16 write_addr = 0;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
HALMAC_REG_W32(REG_DBI_WDATA_V1, data);
write_addr = ((addr & 0x0ffc) | (0x000F << 12));
HALMAC_REG_W16(REG_DBI_FLAG_V1, write_addr);
PLTFM_MSG_TRACE("[TRACE]Addr-W = %x\n", write_addr);
HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x01);
tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
cnt = 20;
while (tmp_u1b && (cnt != 0)) {
PLTFM_DELAY_US(10);
tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
cnt--;
}
if (tmp_u1b) {
PLTFM_MSG_ERR("[ERR]DBI write fail!\n");
return HALMAC_RET_FAIL;
}
return HALMAC_RET_SUCCESS;
}
u32
dbi_r32_88xx(struct halmac_adapter *adapter, u16 addr)
{
u16 read_addr = addr & 0x0ffc;
u8 tmp_u1b = 0;
u32 cnt = 0;
u32 ret = 0;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
HALMAC_REG_W16(REG_DBI_FLAG_V1, read_addr);
HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x2);
tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
cnt = 20;
while (tmp_u1b && (cnt != 0)) {
PLTFM_DELAY_US(10);
tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
cnt--;
}
if (tmp_u1b) {
ret = 0xFFFF;
PLTFM_MSG_ERR("[ERR]DBI read fail!\n");
} else {
ret = HALMAC_REG_R32(REG_DBI_RDATA_V1);
PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret);
}
return ret;
}
enum halmac_ret_status
dbi_w8_88xx(struct halmac_adapter *adapter, u16 addr, u8 data)
{
u8 tmp_u1b = 0;
u32 cnt = 0;
u16 write_addr = 0;
u16 remainder = addr & (4 - 1);
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
HALMAC_REG_W8(REG_DBI_WDATA_V1 + remainder, data);
write_addr = ((addr & 0x0ffc) | (BIT(0) << (remainder + 12)));
HALMAC_REG_W16(REG_DBI_FLAG_V1, write_addr);
PLTFM_MSG_TRACE("[TRACE]Addr-W = %x\n", write_addr);
HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x01);
tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
cnt = 20;
while (tmp_u1b && (cnt != 0)) {
PLTFM_DELAY_US(10);
tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
cnt--;
}
if (tmp_u1b) {
PLTFM_MSG_ERR("[ERR]DBI write fail!\n");
return HALMAC_RET_FAIL;
}
return HALMAC_RET_SUCCESS;
}
u8
dbi_r8_88xx(struct halmac_adapter *adapter, u16 addr)
{
u16 read_addr = addr & 0x0ffc;
u8 tmp_u1b = 0;
u32 cnt = 0;
u8 ret = 0;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
HALMAC_REG_W16(REG_DBI_FLAG_V1, read_addr);
HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x2);
tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
cnt = 20;
while (tmp_u1b && (cnt != 0)) {
PLTFM_DELAY_US(10);
tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
cnt--;
}
if (tmp_u1b) {
ret = 0xFF;
PLTFM_MSG_ERR("[ERR]DBI read fail!\n");
} else {
ret = HALMAC_REG_R8(REG_DBI_RDATA_V1 + (addr & (4 - 1)));
PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret);
}
return ret;
}
enum halmac_ret_status
trxdma_check_idle_88xx(struct halmac_adapter *adapter)
{
u32 cnt = 0;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
/* Stop Tx & Rx DMA */
HALMAC_REG_W32_SET(REG_RXPKT_NUM, BIT(18));
HALMAC_REG_W16_SET(REG_PCIE_CTRL, ~(BIT(15) | BIT(8)));
/* Stop FW */
HALMAC_REG_W16_CLR(REG_SYS_FUNC_EN, BIT(10));
/* Check Tx DMA is idle */
cnt = 20;
while ((HALMAC_REG_R8(REG_SYS_CFG5) & BIT(2)) == BIT(2)) {
PLTFM_DELAY_US(10);
cnt--;
if (cnt == 0) {
PLTFM_MSG_ERR("[ERR]Chk tx idle\n");
return HALMAC_RET_POWER_OFF_FAIL;
}
}
/* Check Rx DMA is idle */
cnt = 20;
while ((HALMAC_REG_R32(REG_RXPKT_NUM) & BIT(17)) != BIT(17)) {
PLTFM_DELAY_US(10);
cnt--;
if (cnt == 0) {
PLTFM_MSG_ERR("[ERR]Chk rx idle\n");
return HALMAC_RET_POWER_OFF_FAIL;
}
}
return HALMAC_RET_SUCCESS;
}
void
en_ref_autok_88xx(struct halmac_adapter *adapter, u8 en)
{
if (en == 1)
adapter->pcie_refautok_en = 1;
else
adapter->pcie_refautok_en = 0;
}
#endif /* HALMAC_88XX_SUPPORT */

102
hal/halmac/halmac_88xx/halmac_pcie_88xx.h
View File

@@ -1,102 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _HALMAC_PCIE_88XX_H_
#define _HALMAC_PCIE_88XX_H_
#include "../halmac_api.h"
#if HALMAC_88XX_SUPPORT
enum halmac_ret_status
init_pcie_cfg_88xx(struct halmac_adapter *adapter);
enum halmac_ret_status
deinit_pcie_cfg_88xx(struct halmac_adapter *adapter);
enum halmac_ret_status
cfg_pcie_rx_agg_88xx(struct halmac_adapter *adapter,
struct halmac_rxagg_cfg *cfg);
u8
reg_r8_pcie_88xx(struct halmac_adapter *adapter, u32 offset);
enum halmac_ret_status
reg_w8_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
u16
reg_r16_pcie_88xx(struct halmac_adapter *adapter, u32 offset);
enum halmac_ret_status
reg_w16_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u16 value);
u32
reg_r32_pcie_88xx(struct halmac_adapter *adapter, u32 offset);
enum halmac_ret_status
reg_w32_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u32 value);
enum halmac_ret_status
cfg_txagg_pcie_align_88xx(struct halmac_adapter *adapter, u8 enable,
u16 align_size);
enum halmac_ret_status
tx_allowed_pcie_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
u32
pcie_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset);
enum halmac_ret_status
pcie_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
u8 *value);
enum halmac_ret_status
set_pcie_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num);
enum halmac_ret_status
get_pcie_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
u32 *cmd53_addr);
enum halmac_ret_status
get_pcie_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
u8 *id);
enum halmac_ret_status
mdio_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed);
u16
mdio_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed);
enum halmac_ret_status
dbi_w32_88xx(struct halmac_adapter *adapter, u16 addr, u32 data);
u32
dbi_r32_88xx(struct halmac_adapter *adapter, u16 addr);
enum halmac_ret_status
dbi_w8_88xx(struct halmac_adapter *adapter, u16 addr, u8 data);
u8
dbi_r8_88xx(struct halmac_adapter *adapter, u16 addr);
enum halmac_ret_status
trxdma_check_idle_88xx(struct halmac_adapter *adapter);
void
en_ref_autok_88xx(struct halmac_adapter *dapter, u8 en);
#endif /* HALMAC_88XX_SUPPORT */
#endif/* _HALMAC_PCIE_88XX_H_ */

892
hal/halmac/halmac_88xx/halmac_sdio_88xx.c
View File

@@ -1,892 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#include "halmac_sdio_88xx.h"
#include "halmac_88xx_cfg.h"
#if HALMAC_88XX_SUPPORT
/* define the SDIO Bus CLK threshold */
/* for avoiding CMD53 fails that result from SDIO CLK sync to ana_clk fail */
#define SDIO_CLK_HIGH_SPEED_TH 50 /* 50MHz */
#define SDIO_CLK_SPEED_MAX 208 /* 208MHz */
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
static u8
r_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 offset);
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
static u32
r_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 offset);
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
static u32
r8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr);
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
static u32
r16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr);
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
static u32
r32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr);
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
static enum halmac_ret_status
w_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
enum halmac_io_size size);
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
static enum halmac_ret_status
w_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
enum halmac_io_size size);
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
static enum halmac_ret_status
w8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val);
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
static enum halmac_ret_status
w16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val);
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
static enum halmac_ret_status
w32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val);
/**
* init_sdio_cfg_88xx() - init SDIO
* @adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
init_sdio_cfg_88xx(struct halmac_adapter *adapter)
{
u32 value32;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
if (adapter->intf != HALMAC_INTERFACE_SDIO)
return HALMAC_RET_WRONG_INTF;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
HALMAC_REG_R32(REG_SDIO_FREE_TXPG);
value32 = HALMAC_REG_R32(REG_SDIO_TX_CTRL) & 0xFFFF;
value32 &= ~(BIT_CMD_ERR_STOP_INT_EN | BIT_EN_MASK_TIMER |
BIT_EN_RXDMA_MASK_INT);
HALMAC_REG_W32(REG_SDIO_TX_CTRL, value32);
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* deinit_sdio_cfg_88xx() - deinit SDIO
* @adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
deinit_sdio_cfg_88xx(struct halmac_adapter *adapter)
{
if (adapter->intf != HALMAC_INTERFACE_SDIO)
return HALMAC_RET_WRONG_INTF;
return HALMAC_RET_SUCCESS;
}
/**
* cfg_sdio_rx_agg_88xx() - config rx aggregation
* @adapter : the adapter of halmac
* @halmac_rx_agg_mode
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
cfg_sdio_rx_agg_88xx(struct halmac_adapter *adapter,
struct halmac_rxagg_cfg *cfg)
{
u8 value8;
u8 size;
u8 timeout;
u8 agg_enable;
u32 value32;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
agg_enable = HALMAC_REG_R8(REG_TXDMA_PQ_MAP);
switch (cfg->mode) {
case HALMAC_RX_AGG_MODE_NONE:
agg_enable &= ~(BIT_RXDMA_AGG_EN);
break;
case HALMAC_RX_AGG_MODE_DMA:
case HALMAC_RX_AGG_MODE_USB:
agg_enable |= BIT_RXDMA_AGG_EN;
break;
default:
PLTFM_MSG_ERR("[ERR]unsupported mode\n");
agg_enable &= ~BIT_RXDMA_AGG_EN;
break;
}
if (cfg->threshold.drv_define == _FALSE) {
size = 0xFF;
timeout = 0x01;
} else {
size = cfg->threshold.size;
timeout = cfg->threshold.timeout;
}
value32 = HALMAC_REG_R32(REG_RXDMA_AGG_PG_TH);
if (cfg->threshold.size_limit_en == _FALSE)
HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 & ~BIT_EN_PRE_CALC);
else
HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 | BIT_EN_PRE_CALC);
HALMAC_REG_W8(REG_TXDMA_PQ_MAP, agg_enable);
HALMAC_REG_W16(REG_RXDMA_AGG_PG_TH,
(u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO_V1)));
value8 = HALMAC_REG_R8(REG_RXDMA_MODE);
if (0 != (agg_enable & BIT_RXDMA_AGG_EN))
HALMAC_REG_W8(REG_RXDMA_MODE, value8 | BIT_DMA_MODE);
else
HALMAC_REG_W8(REG_RXDMA_MODE, value8 & ~(BIT_DMA_MODE));
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* sdio_reg_rn_88xx() - read n byte register
* @adapter : the adapter of halmac
* @offset : register offset
* @halmac_size : register value size
* @value : register value
* Author : Soar
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
sdio_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
u8 *value)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (0 == (offset & 0xFFFF0000)) {
PLTFM_MSG_ERR("[ERR]offset 0x%x\n", offset);
return HALMAC_RET_FAIL;
}
status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
if (status != HALMAC_RET_SUCCESS) {
PLTFM_MSG_ERR("[ERR]convert offset\n");
return status;
}
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
PLTFM_MSG_ERR("[ERR]power off\n");
return HALMAC_RET_FAIL;
}
PLTFM_SDIO_CMD53_RN(offset, size, value);
return HALMAC_RET_SUCCESS;
}
/**
* cfg_txagg_sdio_align_88xx() -config sdio bus tx agg alignment
* @adapter : the adapter of halmac
* @enable : function enable(1)/disable(0)
* @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
* Author : Soar Tu
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
cfg_txagg_sdio_align_88xx(struct halmac_adapter *adapter, u8 enable,
u16 align_size)
{
u8 i;
u8 flag = 0;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (adapter->chip_id == HALMAC_CHIP_ID_8822B)
return HALMAC_RET_NOT_SUPPORT;
if ((align_size & 0xF000) != 0) {
PLTFM_MSG_ERR("[ERR]out of range\n");
return HALMAC_RET_FAIL;
}
for (i = 3; i <= 11; i++) {
if (align_size == 1 << i) {
flag = 1;
break;
}
}
if (flag == 0) {
PLTFM_MSG_ERR("[ERR]not 2^3 ~ 2^11\n");
return HALMAC_RET_FAIL;
}
adapter->hw_cfg_info.tx_align_size = align_size;
if (enable)
HALMAC_REG_W16(REG_RQPN_CTRL_2, 0x8000 | align_size);
else
HALMAC_REG_W16(REG_RQPN_CTRL_2, align_size);
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* sdio_indirect_reg_r32_88xx() - read MAC reg by SDIO reg
* @adapter : the adapter of halmac
* @offset : register offset
* Author : Soar
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u32
sdio_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset)
{
return r_indir_sdio_88xx(adapter, offset, HALMAC_IO_DWORD);
}
/**
* set_sdio_bulkout_num_88xx() - inform bulk-out num
* @adapter : the adapter of halmac
* @bulkout_num : usb bulk-out number
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
set_sdio_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num)
{
return HALMAC_RET_NOT_SUPPORT;
}
/**
* get_sdio_bulkout_id_88xx() - get bulk out id for the TX packet
* @adapter : the adapter of halmac
* @halmac_buf : tx packet, include txdesc
* @halmac_size : tx packet size
* @bulkout_id : usb bulk-out id
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
get_sdio_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
u8 *id)
{
return HALMAC_RET_NOT_SUPPORT;
}
/**
* sdio_cmd53_4byte_88xx() - cmd53 only for 4byte len register IO
* @adapter : the adapter of halmac
* @enable : 1->CMD53 only use in 4byte reg, 0 : No limitation
* Author : Ivan Lin/KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
sdio_cmd53_4byte_88xx(struct halmac_adapter *adapter,
enum halmac_sdio_cmd53_4byte_mode mode)
{
if (adapter->intf != HALMAC_INTERFACE_SDIO)
return HALMAC_RET_WRONG_INTF;
if (adapter->api_registry.sdio_cmd53_4byte_en == 0)
return HALMAC_RET_NOT_SUPPORT;
adapter->sdio_cmd53_4byte = mode;
return HALMAC_RET_SUCCESS;
}
/**
* sdio_hw_info_88xx() - info sdio hw info
* @adapter : the adapter of halmac
* @HALMAC_SDIO_CMD53_4BYTE_MODE :
* clock_speed : sdio bus clock. Unit -> MHz
* spec_ver : sdio spec version
* Author : Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
sdio_hw_info_88xx(struct halmac_adapter *adapter,
struct halmac_sdio_hw_info *info)
{
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (adapter->intf != HALMAC_INTERFACE_SDIO)
return HALMAC_RET_WRONG_INTF;
PLTFM_MSG_TRACE("[TRACE]SDIO clock:%d, spec:%d\n",
info->clock_speed, info->spec_ver);
if (info->clock_speed > SDIO_CLK_SPEED_MAX)
return HALMAC_RET_SDIO_CLOCK_ERR;
if (info->clock_speed > SDIO_CLK_HIGH_SPEED_TH)
adapter->sdio_hw_info.io_hi_speed_flag = 1;
adapter->sdio_hw_info.io_indir_flag = info->io_indir_flag;
if (info->clock_speed > SDIO_CLK_HIGH_SPEED_TH &&
adapter->sdio_hw_info.io_indir_flag == 0)
PLTFM_MSG_WARN("[WARN]SDIO clock:%d, indir access is better\n",
info->clock_speed);
adapter->sdio_hw_info.clock_speed = info->clock_speed;
adapter->sdio_hw_info.spec_ver = info->spec_ver;
adapter->sdio_hw_info.block_size = info->block_size;
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return HALMAC_RET_SUCCESS;
}
void
cfg_sdio_tx_page_threshold_88xx(struct halmac_adapter *adapter,
struct halmac_tx_page_threshold_info *info)
{
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
u32 threshold = info->threshold;
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
if (info->enable == 1) {
threshold = BIT(31) | threshold;
PLTFM_MSG_TRACE("[TRACE]enable\n");
} else {
threshold = ~(BIT(31)) & threshold;
PLTFM_MSG_TRACE("[TRACE]disable\n");
}
switch (info->dma_queue_sel) {
case HALMAC_MAP2_HQ:
HALMAC_REG_W32(REG_TQPNT1, threshold);
break;
case HALMAC_MAP2_NQ:
HALMAC_REG_W32(REG_TQPNT2, threshold);
break;
case HALMAC_MAP2_LQ:
HALMAC_REG_W32(REG_TQPNT3, threshold);
break;
case HALMAC_MAP2_EXQ:
HALMAC_REG_W32(REG_TQPNT4, threshold);
break;
default:
break;
}
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
}
enum halmac_ret_status
cnv_to_sdio_bus_offset_88xx(struct halmac_adapter *adapter, u32 *offset)
{
switch ((*offset) & 0xFFFF0000) {
case WLAN_IOREG_OFFSET:
*offset &= HALMAC_WLAN_MAC_REG_MSK;
*offset |= HALMAC_SDIO_CMD_ADDR_MAC_REG << 13;
break;
case SDIO_LOCAL_OFFSET:
*offset &= HALMAC_SDIO_LOCAL_MSK;
*offset |= HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13;
break;
default:
*offset = 0xFFFFFFFF;
PLTFM_MSG_ERR("[ERR]base address!!\n");
return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL;
}
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status
leave_sdio_suspend_88xx(struct halmac_adapter *adapter)
{
u8 value8;
u32 cnt;
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
value8 = HALMAC_REG_R8(REG_SDIO_HSUS_CTRL);
HALMAC_REG_W8(REG_SDIO_HSUS_CTRL, value8 & ~(BIT(0)));
cnt = 10000;
while (!(HALMAC_REG_R8(REG_SDIO_HSUS_CTRL) & 0x02)) {
cnt--;
if (cnt == 0)
return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
}
value8 = HALMAC_REG_R8(REG_HCI_OPT_CTRL + 2);
if (adapter->sdio_hw_info.spec_ver == HALMAC_SDIO_SPEC_VER_3_00)
HALMAC_REG_W8(REG_HCI_OPT_CTRL + 2, value8 | BIT(2));
else
HALMAC_REG_W8(REG_HCI_OPT_CTRL + 2, value8 & ~(BIT(2)));
return HALMAC_RET_SUCCESS;
}
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
static u8
r_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 offset)
{
u8 value8, tmp, cnt = 50;
u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_cfg);
if (status != HALMAC_RET_SUCCESS)
return status;
status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_data);
if (status != HALMAC_RET_SUCCESS)
return status;
PLTFM_SDIO_CMD52_W(reg_cfg, (u8)offset);
PLTFM_SDIO_CMD52_W(reg_cfg + 1, (u8)(offset >> 8));
PLTFM_SDIO_CMD52_W(reg_cfg + 2, (u8)(BIT(3) | BIT(4)));
do {
tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
cnt--;
} while (((tmp & BIT(4)) == 0) && (cnt > 0));
if (((cnt & BIT(4)) == 0) && cnt == 0)
PLTFM_MSG_ERR("[ERR]sdio indirect CMD52 read\n");
value8 = PLTFM_SDIO_CMD52_R(reg_data);
return value8;
}
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
static u32
r_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 offset)
{
u8 tmp, cnt = 50;
u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
union {
u32 dword;
u8 byte[4];
} value32 = { 0x00000000 };
status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_cfg);
if (status != HALMAC_RET_SUCCESS)
return status;
status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_data);
if (status != HALMAC_RET_SUCCESS)
return status;
PLTFM_SDIO_CMD53_W32(reg_cfg, offset | BIT(19) | BIT(20));
do {
tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
cnt--;
} while (((tmp & BIT(4)) == 0) && (cnt > 0));
if (((cnt & BIT(4)) == 0) && cnt == 0)
PLTFM_MSG_ERR("[ERR]sdio indirect CMD53 read\n");
value32.dword = PLTFM_SDIO_CMD53_R32(reg_data);
return value32.dword;
}
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
static u32
r8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr)
{
union {
u32 dword;
u8 byte[4];
} val = { 0x00000000 };
if (adapter->pwr_off_flow_flag == 1 ||
adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
val.dword = rtk_le32_to_cpu(val.dword);
} else {
val.dword = r_indir_cmd53_88xx(adapter, adr);
}
return val.dword;
}
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
static u32
r16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr)
{
u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
union {
u32 dword;
u8 byte[4];
} val = { 0x00000000 };
status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_data);
if (status != HALMAC_RET_SUCCESS)
return status;
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
if (0 != (adr & (2 - 1))) {
val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
val.byte[1] = r_indir_cmd52_88xx(adapter, adr + 1);
} else {
val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
val.byte[1] = PLTFM_SDIO_CMD52_R(reg_data + 1);
}
val.dword = rtk_le32_to_cpu(val.dword);
} else {
if (0 != (adr & (2 - 1))) {
val.byte[0] = (u8)r_indir_cmd53_88xx(adapter, adr);
val.byte[1] = (u8)r_indir_cmd53_88xx(adapter, adr + 1);
val.dword = rtk_le32_to_cpu(val.dword);
} else {
val.dword = r_indir_cmd53_88xx(adapter, adr);
}
}
return val.dword;
}
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
static u32
r32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr)
{
u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
union {
u32 dword;
u8 byte[4];
} val = { 0x00000000 };
status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_data);
if (status != HALMAC_RET_SUCCESS)
return status;
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
if (0 != (adr & (4 - 1))) {
val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
val.byte[1] = r_indir_cmd52_88xx(adapter, adr + 1);
val.byte[2] = r_indir_cmd52_88xx(adapter, adr + 2);
val.byte[3] = r_indir_cmd52_88xx(adapter, adr + 3);
} else {
val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
val.byte[1] = PLTFM_SDIO_CMD52_R(reg_data + 1);
val.byte[2] = PLTFM_SDIO_CMD52_R(reg_data + 2);
val.byte[3] = PLTFM_SDIO_CMD52_R(reg_data + 3);
}
val.dword = rtk_le32_to_cpu(val.dword);
} else {
if (0 != (adr & (4 - 1))) {
val.byte[0] = (u8)r_indir_cmd53_88xx(adapter, adr);
val.byte[1] = (u8)r_indir_cmd53_88xx(adapter, adr + 1);
val.byte[2] = (u8)r_indir_cmd53_88xx(adapter, adr + 2);
val.byte[3] = (u8)r_indir_cmd53_88xx(adapter, adr + 3);
val.dword = rtk_le32_to_cpu(val.dword);
} else {
val.dword = r_indir_cmd53_88xx(adapter, adr);
}
}
return val.dword;
}
u32
r_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr,
enum halmac_io_size size)
{
u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
union {
u32 dword;
u8 byte[4];
} val = { 0x00000000 };
status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_data);
if (status != HALMAC_RET_SUCCESS)
return status;
PLTFM_MUTEX_LOCK(&adapter->sdio_indir_mutex);
switch (size) {
case HALMAC_IO_BYTE:
val.dword = r8_indir_sdio_88xx(adapter, adr);
break;
case HALMAC_IO_WORD:
val.dword = r16_indir_sdio_88xx(adapter, adr);
break;
case HALMAC_IO_DWORD:
val.dword = r32_indir_sdio_88xx(adapter, adr);
break;
default:
break;
}
PLTFM_MUTEX_UNLOCK(&adapter->sdio_indir_mutex);
return val.dword;
}
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
static enum halmac_ret_status
w_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
enum halmac_io_size size)
{
u8 tmp, cnt = 50;
u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_cfg);
if (status != HALMAC_RET_SUCCESS)
return status;
status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_data);
if (status != HALMAC_RET_SUCCESS)
return status;
PLTFM_SDIO_CMD52_W(reg_cfg, (u8)adr);
PLTFM_SDIO_CMD52_W(reg_cfg + 1, (u8)(adr >> 8));
switch (size) {
case HALMAC_IO_BYTE:
PLTFM_SDIO_CMD52_W(reg_data, (u8)val);
PLTFM_SDIO_CMD52_W(reg_cfg + 2, (u8)(BIT(2) | BIT(4)));
break;
case HALMAC_IO_WORD:
PLTFM_SDIO_CMD52_W(reg_data, (u8)val);
PLTFM_SDIO_CMD52_W(reg_data + 1, (u8)(val >> 8));
PLTFM_SDIO_CMD52_W(reg_cfg + 2,
(u8)(BIT(0) | BIT(2) | BIT(4)));
break;
case HALMAC_IO_DWORD:
PLTFM_SDIO_CMD52_W(reg_data, (u8)val);
PLTFM_SDIO_CMD52_W(reg_data + 1, (u8)(val >> 8));
PLTFM_SDIO_CMD52_W(reg_data + 2, (u8)(val >> 16));
PLTFM_SDIO_CMD52_W(reg_data + 3, (u8)(val >> 24));
PLTFM_SDIO_CMD52_W(reg_cfg + 2,
(u8)(BIT(1) | BIT(2) | BIT(4)));
break;
default:
break;
}
do {
tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
cnt--;
} while (((tmp & BIT(4)) == 0) && (cnt > 0));
if (((cnt & BIT(4)) == 0) && cnt == 0)
PLTFM_MSG_ERR("[ERR]sdio indirect CMD52 write\n");
return status;
}
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
static enum halmac_ret_status
w_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
enum halmac_io_size size)
{
u8 tmp, cnt = 50;
u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
u32 value32 = 0;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_cfg);
if (status != HALMAC_RET_SUCCESS)
return status;
status = cnv_to_sdio_bus_offset_88xx(adapter, &reg_data);
if (status != HALMAC_RET_SUCCESS)
return status;
switch (size) {
case HALMAC_IO_BYTE:
value32 = adr | BIT(18) | BIT(20);
break;
case HALMAC_IO_WORD:
value32 = adr | BIT(16) | BIT(18) | BIT(20);
break;
case HALMAC_IO_DWORD:
value32 = adr | BIT(17) | BIT(18) | BIT(20);
break;
default:
return HALMAC_RET_FAIL;
}
PLTFM_SDIO_CMD53_W32(reg_data, val);
PLTFM_SDIO_CMD53_W32(reg_cfg, value32);
do {
tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
cnt--;
} while (((tmp & BIT(4)) == 0) && (cnt > 0));
if (((cnt & BIT(4)) == 0) && cnt == 0)
PLTFM_MSG_ERR("[ERR]sdio indirect CMD53 read\n");
return status;
}
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
static enum halmac_ret_status
w8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (adapter->pwr_off_flow_flag == 1 ||
adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF)
status = w_indir_cmd52_88xx(adapter, adr, val, HALMAC_IO_BYTE);
else
status = w_indir_cmd53_88xx(adapter, adr, val, HALMAC_IO_BYTE);
return status;
}
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
static enum halmac_ret_status
w16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
if (0 != (adr & (2 - 1))) {
status = w_indir_cmd52_88xx(adapter, adr, val,
HALMAC_IO_BYTE);
if (status != HALMAC_RET_SUCCESS)
return status;
status = w_indir_cmd52_88xx(adapter, adr + 1, val >> 8,
HALMAC_IO_BYTE);
} else {
status = w_indir_cmd52_88xx(adapter, adr, val,
HALMAC_IO_WORD);
}
} else {
if (0 != (adr & (2 - 1))) {
status = w_indir_cmd53_88xx(adapter, adr, val,
HALMAC_IO_BYTE);
if (status != HALMAC_RET_SUCCESS)
return status;
status = w_indir_cmd53_88xx(adapter, adr + 1, val >> 8,
HALMAC_IO_BYTE);
} else {
status = w_indir_cmd53_88xx(adapter, adr, val,
HALMAC_IO_WORD);
}
}
return status;
}
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
static enum halmac_ret_status
w32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
if (0 != (adr & (4 - 1))) {
status = w_indir_cmd52_88xx(adapter, adr, val,
HALMAC_IO_BYTE);
if (status != HALMAC_RET_SUCCESS)
return status;
status = w_indir_cmd52_88xx(adapter, adr + 1, val >> 8,
HALMAC_IO_BYTE);
if (status != HALMAC_RET_SUCCESS)
return status;
status = w_indir_cmd52_88xx(adapter, adr + 2, val >> 16,
HALMAC_IO_BYTE);
if (status != HALMAC_RET_SUCCESS)
return status;
status = w_indir_cmd52_88xx(adapter, adr + 3, val >> 24,
HALMAC_IO_BYTE);
} else {
status = w_indir_cmd52_88xx(adapter, adr, val,
HALMAC_IO_DWORD);
}
} else {
if (0 != (adr & (4 - 1))) {
status = w_indir_cmd53_88xx(adapter, adr, val,
HALMAC_IO_BYTE);
if (status != HALMAC_RET_SUCCESS)
return status;
status = w_indir_cmd53_88xx(adapter, adr + 1, val >> 8,
HALMAC_IO_BYTE);
if (status != HALMAC_RET_SUCCESS)
return status;
status = w_indir_cmd53_88xx(adapter, adr + 2, val >> 16,
HALMAC_IO_BYTE);
if (status != HALMAC_RET_SUCCESS)
return status;
status = w_indir_cmd53_88xx(adapter, adr + 3, val >> 24,
HALMAC_IO_BYTE);
} else {
status = w_indir_cmd53_88xx(adapter, adr, val,
HALMAC_IO_DWORD);
}
}
return status;
}
enum halmac_ret_status
w_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
enum halmac_io_size size)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
PLTFM_MUTEX_LOCK(&adapter->sdio_indir_mutex);
switch (size) {
case HALMAC_IO_BYTE:
status = w8_indir_sdio_88xx(adapter, adr, val);
break;
case HALMAC_IO_WORD:
status = w16_indir_sdio_88xx(adapter, adr, val);
break;
case HALMAC_IO_DWORD:
status = w32_indir_sdio_88xx(adapter, adr, val);
break;
default:
break;
}
PLTFM_MUTEX_UNLOCK(&adapter->sdio_indir_mutex);
return status;
}
#endif /* HALMAC_88XX_SUPPORT */

79
hal/halmac/halmac_88xx/halmac_sdio_88xx.h
View File

@@ -1,79 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
******************************************************************************/
#ifndef _HALMAC_SDIO_88XX_H_
#define _HALMAC_SDIO_88XX_H_
#include "../halmac_api.h"
#if HALMAC_88XX_SUPPORT
enum halmac_ret_status
init_sdio_cfg_88xx(struct halmac_adapter *adapter);
enum halmac_ret_status
deinit_sdio_cfg_88xx(struct halmac_adapter *adapter);
enum halmac_ret_status
cfg_sdio_rx_agg_88xx(struct halmac_adapter *adapter,
struct halmac_rxagg_cfg *cfg);
enum halmac_ret_status
cfg_txagg_sdio_align_88xx(struct halmac_adapter *adapter, u8 enable,
u16 align_size);
u32
sdio_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset);
enum halmac_ret_status
sdio_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
u8 *value);
enum halmac_ret_status
set_sdio_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num);
enum halmac_ret_status
get_sdio_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
u8 *id);
enum halmac_ret_status
sdio_cmd53_4byte_88xx(struct halmac_adapter *adapter,
enum halmac_sdio_cmd53_4byte_mode mode);
enum halmac_ret_status
sdio_hw_info_88xx(struct halmac_adapter *adapter,
struct halmac_sdio_hw_info *info);
void
cfg_sdio_tx_page_threshold_88xx(struct halmac_adapter *adapter,
struct halmac_tx_page_threshold_info *info);
enum halmac_ret_status
cnv_to_sdio_bus_offset_88xx(struct halmac_adapter *adapter, u32 *offset);
enum halmac_ret_status
leave_sdio_suspend_88xx(struct halmac_adapter *adapter);
u32
r_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr,
enum halmac_io_size size);
enum halmac_ret_status
w_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
enum halmac_io_size size);
#endif /* HALMAC_88XX_SUPPORT */
#endif/* _HALMAC_SDIO_88XX_H_ */

33
hal/halmac/halmac_88xx/halmac_usb_88xx.c
View File

@@ -15,7 +15,7 @@
#include "halmac_usb_88xx.h"
#if HALMAC_88XX_SUPPORT
#if (HALMAC_88XX_SUPPORT && HALMAC_USB_SUPPORT)
enum usb_burst_size {
USB_BURST_SIZE_3_0 = 0x0,
@@ -53,8 +53,7 @@ init_usb_cfg_88xx(struct halmac_adapter *adapter)
}
HALMAC_REG_W8(REG_RXDMA_MODE, value8);
HALMAC_REG_W16(REG_TXDMA_OFFSET_CHK,
HALMAC_REG_R16(REG_TXDMA_OFFSET_CHK) | BIT_DROP_DATA_EN);
HALMAC_REG_W16_SET(REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN);
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
@@ -117,7 +116,7 @@ cfg_usb_rx_agg_88xx(struct halmac_adapter *adapter,
break;
}
if (cfg->threshold.drv_define == _FALSE) {
if (cfg->threshold.drv_define == 0) {
if (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20) {
/* usb3.0 */
size = 0x5;
@@ -133,7 +132,7 @@ cfg_usb_rx_agg_88xx(struct halmac_adapter *adapter,
}
value32 = HALMAC_REG_R32(REG_RXDMA_AGG_PG_TH);
if (cfg->threshold.size_limit_en == _FALSE)
if (cfg->threshold.size_limit_en == 0)
HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 & ~BIT_EN_PRE_CALC);
else
HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 | BIT_EN_PRE_CALC);
@@ -159,11 +158,7 @@ cfg_usb_rx_agg_88xx(struct halmac_adapter *adapter,
u8
reg_r8_usb_88xx(struct halmac_adapter *adapter, u32 offset)
{
u8 value8;
value8 = PLTFM_REG_R8(offset);
return value8;
return PLTFM_REG_R8(offset);
}
/**
@@ -194,11 +189,7 @@ reg_w8_usb_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
u16
reg_r16_usb_88xx(struct halmac_adapter *adapter, u32 offset)
{
u16 value16;
value16 = PLTFM_REG_R16(offset);
return value16;
return PLTFM_REG_R16(offset);
}
/**
@@ -229,11 +220,7 @@ reg_w16_usb_88xx(struct halmac_adapter *adapter, u32 offset, u16 value)
u32
reg_r32_usb_88xx(struct halmac_adapter *adapter, u32 offset)
{
u32 value32;
value32 = PLTFM_REG_R32(offset);
return value32;
return PLTFM_REG_R32(offset);
}
/**
@@ -442,9 +429,9 @@ set_usb_mode_88xx(struct halmac_adapter *adapter, enum halmac_usb_mode mode)
cur_mode = (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20) ?
HALMAC_USB_MODE_U3 : HALMAC_USB_MODE_U2;
/*check if HW supports usb2_usb3 switch*/
/* check if HW supports usb2_usb3 switch */
usb_tmp = HALMAC_REG_R32(REG_PAD_CTRL2);
if (_FALSE == (BIT_GET_USB23_SW_MODE_V1(usb_tmp) |
if (0 == (BIT_GET_USB23_SW_MODE_V1(usb_tmp) |
(usb_tmp & BIT_USB3_USB2_TRANSITION))) {
PLTFM_MSG_ERR("[ERR]u2/u3 switch\n");
return HALMAC_RET_USB2_3_SWITCH_UNSUPPORT;
@@ -512,7 +499,7 @@ usbphy_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed)
HALMAC_REG_W8(0xff0c, addr | BIT(6));
value = (u16)(HALMAC_REG_R32(0xff0c) >> 8);
} else if (speed == HAL_INTF_PHY_USB2) {
if (addr >= 0xE0 && addr <= 0xFF)
if (addr >= 0xE0)
addr -= 0x20;
if (addr >= 0xC0 && addr <= 0xDF) {
HALMAC_REG_W8(0xfe40, addr);

2
hal/halmac/halmac_88xx/halmac_usb_88xx.h
View File

@@ -18,7 +18,7 @@
#include "../halmac_api.h"
#if HALMAC_88XX_SUPPORT
#if (HALMAC_88XX_SUPPORT && HALMAC_USB_SUPPORT)
enum halmac_ret_status
init_usb_cfg_88xx(struct halmac_adapter *adapter);

28
hal/halmac/halmac_api.c
View File

@@ -41,10 +41,13 @@
#endif
#if HALMAC_88XX_V1_SUPPORT
#include "halmac_88xx_v1/halmac_init_88xx_v1.h"
#if defined(HALMAC_DATA_CPU_EN)
#include "halmac_88xxd_v1/halmac_init_88xxd_v1.h"
#endif
#endif
#endif
/* Remove halmac_*/
enum chip_id_hw_def {
CHIP_ID_HW_DEF_8723A = 0x01,
CHIP_ID_HW_DEF_8188E = 0x02,
@@ -63,6 +66,7 @@ enum chip_id_hw_def {
CHIP_ID_HW_DEF_8723D = 0x0F,
CHIP_ID_HW_DEF_8814B = 0x11,
CHIP_ID_HW_DEF_8822C = 0x13,
CHIP_ID_HW_DEF_8812F = 0x14,
CHIP_ID_HW_DEF_UNDEFINE = 0x7F,
CHIP_ID_HW_DEF_PS = 0xEA,
};
@@ -84,7 +88,7 @@ pltfm_reg_w8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
u32 offset, u8 data);
static u8
pltfm_reg_r_indir_sdio(VOID *drv_adapter, struct halmac_platform_api *pltfm_api,
pltfm_reg_r_indir_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
u32 offset);
static enum halmac_ret_status
@@ -170,7 +174,8 @@ halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api,
#if HALMAC_88XX_SUPPORT
if (adapter->chip_id == HALMAC_CHIP_ID_8822B ||
adapter->chip_id == HALMAC_CHIP_ID_8821C ||
adapter->chip_id == HALMAC_CHIP_ID_8822C) {
adapter->chip_id == HALMAC_CHIP_ID_8822C ||
adapter->chip_id == HALMAC_CHIP_ID_8812F) {
init_adapter_param_88xx(adapter);
status = mount_api_88xx(adapter);
}
@@ -181,6 +186,12 @@ halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api,
init_adapter_param_88xx_v1(adapter);
status = mount_api_88xx_v1(adapter);
}
#if defined(HALMAC_DATA_CPU_EN)
if (adapter->chip_id == HALMAC_CHIP_ID_8814B) {
init_adapter_param_88xxd_v1(adapter);
status = mount_api_88xxd_v1(adapter);
}
#endif
#endif
#else
@@ -213,6 +224,13 @@ halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api,
}
#endif
#if HALMAC_8812F_SUPPORT
if (adapter->chip_id == HALMAC_CHIP_ID_8812F) {
init_adapter_param_win8812f(adapter);
status = mount_api_win8812f(adapter);
}
#endif
#endif
*halmac_api = (struct halmac_api *)adapter->halmac_api;
@@ -496,6 +514,8 @@ get_chip_info(void *drv_adapter, struct halmac_platform_api *pltfm_api,
adapter->chip_id = HALMAC_CHIP_ID_8197F;
} else if (chip_id == CHIP_ID_HW_DEF_8822C) {
adapter->chip_id = HALMAC_CHIP_ID_8822C;
} else if (chip_id == CHIP_ID_HW_DEF_8812F) {
adapter->chip_id = HALMAC_CHIP_ID_8812F;
} else {
adapter->chip_id = HALMAC_CHIP_ID_UNDEFINE;
PLTFM_MSG_ERR("[ERR]Chip id is undefined\n");
@@ -544,7 +564,7 @@ pltfm_reg_w8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
}
static u8
pltfm_reg_r_indir_sdio(VOID *drv_adapter, struct halmac_platform_api *pltfm_api,
pltfm_reg_r_indir_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
u32 offset)
{
u8 value8, tmp, cnt = 50;

9
hal/halmac/halmac_api.h
View File

@@ -19,13 +19,14 @@
#define HALMAC_SVN_VER "11692M"
#define HALMAC_MAJOR_VER 0x0001
#define HALMAC_PROTOTYPE_VER 0x0004
#define HALMAC_MINOR_VER 0x0008
#define HALMAC_PATCH_VER 0x0003
#define HALMAC_PROTOTYPE_VER 0x0005
#define HALMAC_MINOR_VER 0x0014
#define HALMAC_PATCH_VER 0x0015
#define HALMAC_88XX_SUPPORT (HALMAC_8821C_SUPPORT || \
HALMAC_8822B_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define HALMAC_88XX_V1_SUPPORT HALMAC_8814B_SUPPORT

25505
hal/halmac/halmac_bit2.h
View File

File diff suppressed because it is too large Load Diff

97
hal/halmac/halmac_bit_8197f.h
View File

@@ -17026,17 +17026,19 @@
(BIT_CLEAR_R_WMAC_MASK_LA_MAC_8197F(x) | \
BIT_R_WMAC_MASK_LA_MAC_8197F(v))
#define BIT_SHIFT_DUMP_OK_ADDR_8197F 16
#define BIT_MASK_DUMP_OK_ADDR_8197F 0xffff
#define BIT_DUMP_OK_ADDR_8197F(x) \
(((x) & BIT_MASK_DUMP_OK_ADDR_8197F) << BIT_SHIFT_DUMP_OK_ADDR_8197F)
#define BITS_DUMP_OK_ADDR_8197F \
(BIT_MASK_DUMP_OK_ADDR_8197F << BIT_SHIFT_DUMP_OK_ADDR_8197F)
#define BIT_CLEAR_DUMP_OK_ADDR_8197F(x) ((x) & (~BITS_DUMP_OK_ADDR_8197F))
#define BIT_GET_DUMP_OK_ADDR_8197F(x) \
(((x) >> BIT_SHIFT_DUMP_OK_ADDR_8197F) & BIT_MASK_DUMP_OK_ADDR_8197F)
#define BIT_SET_DUMP_OK_ADDR_8197F(x, v) \
(BIT_CLEAR_DUMP_OK_ADDR_8197F(x) | BIT_DUMP_OK_ADDR_8197F(v))
#define BIT_SHIFT_DUMP_OK_ADDR_V1_8197F 15
#define BIT_MASK_DUMP_OK_ADDR_V1_8197F 0x1ffff
#define BIT_DUMP_OK_ADDR_V1_8197F(x) \
(((x) & BIT_MASK_DUMP_OK_ADDR_V1_8197F) \
<< BIT_SHIFT_DUMP_OK_ADDR_V1_8197F)
#define BITS_DUMP_OK_ADDR_V1_8197F \
(BIT_MASK_DUMP_OK_ADDR_V1_8197F << BIT_SHIFT_DUMP_OK_ADDR_V1_8197F)
#define BIT_CLEAR_DUMP_OK_ADDR_V1_8197F(x) ((x) & (~BITS_DUMP_OK_ADDR_V1_8197F))
#define BIT_GET_DUMP_OK_ADDR_V1_8197F(x) \
(((x) >> BIT_SHIFT_DUMP_OK_ADDR_V1_8197F) & \
BIT_MASK_DUMP_OK_ADDR_V1_8197F)
#define BIT_SET_DUMP_OK_ADDR_V1_8197F(x, v) \
(BIT_CLEAR_DUMP_OK_ADDR_V1_8197F(x) | BIT_DUMP_OK_ADDR_V1_8197F(v))
#define BIT_SHIFT_R_TRIG_TIME_SEL_8197F 8
#define BIT_MASK_R_TRIG_TIME_SEL_8197F 0x7f
@@ -17290,4 +17292,77 @@
/* 2 REG_RTS_ADDRESS_1_8197F */
/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8197F */
#define BIT_LTECOEX_ACCESS_START_V1_8197F BIT(31)
#define BIT_LTECOEX_WRITE_MODE_V1_8197F BIT(30)
#define BIT_LTECOEX_READY_BIT_V1_8197F BIT(29)
#define BIT_SHIFT_WRITE_BYTE_EN_V1_8197F 16
#define BIT_MASK_WRITE_BYTE_EN_V1_8197F 0xf
#define BIT_WRITE_BYTE_EN_V1_8197F(x) \
(((x) & BIT_MASK_WRITE_BYTE_EN_V1_8197F) \
<< BIT_SHIFT_WRITE_BYTE_EN_V1_8197F)
#define BITS_WRITE_BYTE_EN_V1_8197F \
(BIT_MASK_WRITE_BYTE_EN_V1_8197F << BIT_SHIFT_WRITE_BYTE_EN_V1_8197F)
#define BIT_CLEAR_WRITE_BYTE_EN_V1_8197F(x) \
((x) & (~BITS_WRITE_BYTE_EN_V1_8197F))
#define BIT_GET_WRITE_BYTE_EN_V1_8197F(x) \
(((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8197F) & \
BIT_MASK_WRITE_BYTE_EN_V1_8197F)
#define BIT_SET_WRITE_BYTE_EN_V1_8197F(x, v) \
(BIT_CLEAR_WRITE_BYTE_EN_V1_8197F(x) | BIT_WRITE_BYTE_EN_V1_8197F(v))
#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8197F 0
#define BIT_MASK_LTECOEX_REG_ADDR_V1_8197F 0xffff
#define BIT_LTECOEX_REG_ADDR_V1_8197F(x) \
(((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8197F) \
<< BIT_SHIFT_LTECOEX_REG_ADDR_V1_8197F)
#define BITS_LTECOEX_REG_ADDR_V1_8197F \
(BIT_MASK_LTECOEX_REG_ADDR_V1_8197F \
<< BIT_SHIFT_LTECOEX_REG_ADDR_V1_8197F)
#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8197F(x) \
((x) & (~BITS_LTECOEX_REG_ADDR_V1_8197F))
#define BIT_GET_LTECOEX_REG_ADDR_V1_8197F(x) \
(((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8197F) & \
BIT_MASK_LTECOEX_REG_ADDR_V1_8197F)
#define BIT_SET_LTECOEX_REG_ADDR_V1_8197F(x, v) \
(BIT_CLEAR_LTECOEX_REG_ADDR_V1_8197F(x) | \
BIT_LTECOEX_REG_ADDR_V1_8197F(v))
/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8197F */
#define BIT_SHIFT_LTECOEX_W_DATA_V1_8197F 0
#define BIT_MASK_LTECOEX_W_DATA_V1_8197F 0xffffffffL
#define BIT_LTECOEX_W_DATA_V1_8197F(x) \
(((x) & BIT_MASK_LTECOEX_W_DATA_V1_8197F) \
<< BIT_SHIFT_LTECOEX_W_DATA_V1_8197F)
#define BITS_LTECOEX_W_DATA_V1_8197F \
(BIT_MASK_LTECOEX_W_DATA_V1_8197F << BIT_SHIFT_LTECOEX_W_DATA_V1_8197F)
#define BIT_CLEAR_LTECOEX_W_DATA_V1_8197F(x) \
((x) & (~BITS_LTECOEX_W_DATA_V1_8197F))
#define BIT_GET_LTECOEX_W_DATA_V1_8197F(x) \
(((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8197F) & \
BIT_MASK_LTECOEX_W_DATA_V1_8197F)
#define BIT_SET_LTECOEX_W_DATA_V1_8197F(x, v) \
(BIT_CLEAR_LTECOEX_W_DATA_V1_8197F(x) | BIT_LTECOEX_W_DATA_V1_8197F(v))
/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8197F */
#define BIT_SHIFT_LTECOEX_R_DATA_V1_8197F 0
#define BIT_MASK_LTECOEX_R_DATA_V1_8197F 0xffffffffL
#define BIT_LTECOEX_R_DATA_V1_8197F(x) \
(((x) & BIT_MASK_LTECOEX_R_DATA_V1_8197F) \
<< BIT_SHIFT_LTECOEX_R_DATA_V1_8197F)
#define BITS_LTECOEX_R_DATA_V1_8197F \
(BIT_MASK_LTECOEX_R_DATA_V1_8197F << BIT_SHIFT_LTECOEX_R_DATA_V1_8197F)
#define BIT_CLEAR_LTECOEX_R_DATA_V1_8197F(x) \
((x) & (~BITS_LTECOEX_R_DATA_V1_8197F))
#define BIT_GET_LTECOEX_R_DATA_V1_8197F(x) \
(((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8197F) & \
BIT_MASK_LTECOEX_R_DATA_V1_8197F)
#define BIT_SET_LTECOEX_R_DATA_V1_8197F(x, v) \
(BIT_CLEAR_LTECOEX_R_DATA_V1_8197F(x) | BIT_LTECOEX_R_DATA_V1_8197F(v))
/* 2 REG_NOT_VALID_8197F */
#endif

45
hal/halmac/halmac_bit_8814b.h
View File

@@ -16159,8 +16159,6 @@
(BIT_CLEAR_MU_SCORETABLE_OFFSET_8814B(x) | \
BIT_MU_SCORETABLE_OFFSET_8814B(v))
/* 2 REG_USEREG_SETTING_8814B */
/* 2 REG_BF0_TIME_SETTING_8814B */
#define BIT_BF0_TIMER_SET_8814B BIT(31)
#define BIT_BF0_TIMER_CLR_8814B BIT(30)
@@ -19948,7 +19946,43 @@
/* 2 REG_RSVD_8814B */
/* 2 REG_RSVD_8814B */
/* 2 REG_SCHEDULER_COUNTER_8814B */
#define BIT_SHIFT__SCHEDULER_COUNTER_8814B 16
#define BIT_MASK__SCHEDULER_COUNTER_8814B 0xffff
#define BIT__SCHEDULER_COUNTER_8814B(x) \
(((x) & BIT_MASK__SCHEDULER_COUNTER_8814B) \
<< BIT_SHIFT__SCHEDULER_COUNTER_8814B)
#define BITS__SCHEDULER_COUNTER_8814B \
(BIT_MASK__SCHEDULER_COUNTER_8814B \
<< BIT_SHIFT__SCHEDULER_COUNTER_8814B)
#define BIT_CLEAR__SCHEDULER_COUNTER_8814B(x) \
((x) & (~BITS__SCHEDULER_COUNTER_8814B))
#define BIT_GET__SCHEDULER_COUNTER_8814B(x) \
(((x) >> BIT_SHIFT__SCHEDULER_COUNTER_8814B) & \
BIT_MASK__SCHEDULER_COUNTER_8814B)
#define BIT_SET__SCHEDULER_COUNTER_8814B(x, v) \
(BIT_CLEAR__SCHEDULER_COUNTER_8814B(x) | \
BIT__SCHEDULER_COUNTER_8814B(v))
#define BIT__SCHEDULER_COUNTER_RST_8814B BIT(8)
#define BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B 0
#define BIT_MASK_SCHEDULER_COUNTER_SEL_8814B 0xff
#define BIT_SCHEDULER_COUNTER_SEL_8814B(x) \
(((x) & BIT_MASK_SCHEDULER_COUNTER_SEL_8814B) \
<< BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B)
#define BITS_SCHEDULER_COUNTER_SEL_8814B \
(BIT_MASK_SCHEDULER_COUNTER_SEL_8814B \
<< BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B)
#define BIT_CLEAR_SCHEDULER_COUNTER_SEL_8814B(x) \
((x) & (~BITS_SCHEDULER_COUNTER_SEL_8814B))
#define BIT_GET_SCHEDULER_COUNTER_SEL_8814B(x) \
(((x) >> BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B) & \
BIT_MASK_SCHEDULER_COUNTER_SEL_8814B)
#define BIT_SET_SCHEDULER_COUNTER_SEL_8814B(x, v) \
(BIT_CLEAR_SCHEDULER_COUNTER_SEL_8814B(x) | \
BIT_SCHEDULER_COUNTER_SEL_8814B(v))
/* 2 REG_RSVD_8814B */
@@ -23204,6 +23238,11 @@
#define BIT_CLI0_PWR_ST_V1_8814B BIT(0)
/* 2 REG_GENERAL_OPTION_8814B */
#define BIT_FIX_MSDU_TAIL_WR_8814B BIT(12)
#define BIT_FIX_MSDU_SHIFT_8814B BIT(11)
#define BIT_RXFIFO_GNT_CUT_8814B BIT(8)
#define BIT_WMAC_FIX_FIRST_MPDU_WITH_PHYSTS_8814B BIT(5)
#define BIT_DUMMY_RXD_FCS_ERROR_MASK_EN_8814B BIT(4)
#define BIT_PATTERN_MATCH_FIX_EN_8814B BIT(3)
#define BIT_TXSERV_FIELD_SEL_8814B BIT(2)
#define BIT_RXVHT_LEN_SEL_8814B BIT(1)

92
hal/halmac/halmac_bit_8822c.h
View File

@@ -260,6 +260,18 @@
#define BIT_RF_EN_8822C BIT(0)
/* 2 REG_AFE_LDO_CTRL_8822C */
#define BIT_R_SYM_WLPON_EMEM1_EN_8822C BIT(31)
#define BIT_R_SYM_WLPON_EMEM0_EN_8822C BIT(30)
#define BIT_R_SYM_WLPOFF_P4EN_8822C BIT(28)
#define BIT_R_SYM_WLPOFF_P3EN_8822C BIT(27)
#define BIT_R_SYM_WLPOFF_P2EN_8822C BIT(26)
#define BIT_R_SYM_WLPOFF_P1EN_8822C BIT(25)
#define BIT_R_SYM_WLPOFF_EN_8822C BIT(24)
#define BIT_R_SYM_WLPON_P3EN_8822C BIT(21)
#define BIT_R_SYM_WLPON_P2EN_8822C BIT(20)
#define BIT_R_SYM_WLPON_P1EN_8822C BIT(19)
#define BIT_R_SYM_WLPON_EN_8822C BIT(18)
#define BIT_R_SYM_LDOV12D_STBY_8822C BIT(16)
#define BIT_R_SYM_WLBBOFF1_P4_EN_8822C BIT(9)
#define BIT_R_SYM_WLBBOFF1_P3_EN_8822C BIT(8)
#define BIT_R_SYM_WLBBOFF1_P2_EN_8822C BIT(7)
@@ -12144,34 +12156,8 @@
#define BIT_SET_BCNQ_PKT_INFO_8822C(x, v) \
(BIT_CLEAR_BCNQ_PKT_INFO_8822C(x) | BIT_BCNQ_PKT_INFO_8822C(v))
/* 2 REG_USEREG_SETTING_8822C */
#define BIT_NDPA_USEREG_8822C BIT(21)
#define BIT_SHIFT_RETRY_USEREG_8822C 19
#define BIT_MASK_RETRY_USEREG_8822C 0x3
#define BIT_RETRY_USEREG_8822C(x) \
(((x) & BIT_MASK_RETRY_USEREG_8822C) << BIT_SHIFT_RETRY_USEREG_8822C)
#define BITS_RETRY_USEREG_8822C \
(BIT_MASK_RETRY_USEREG_8822C << BIT_SHIFT_RETRY_USEREG_8822C)
#define BIT_CLEAR_RETRY_USEREG_8822C(x) ((x) & (~BITS_RETRY_USEREG_8822C))
#define BIT_GET_RETRY_USEREG_8822C(x) \
(((x) >> BIT_SHIFT_RETRY_USEREG_8822C) & BIT_MASK_RETRY_USEREG_8822C)
#define BIT_SET_RETRY_USEREG_8822C(x, v) \
(BIT_CLEAR_RETRY_USEREG_8822C(x) | BIT_RETRY_USEREG_8822C(v))
#define BIT_SHIFT_TRYPKT_USEREG_8822C 17
#define BIT_MASK_TRYPKT_USEREG_8822C 0x3
#define BIT_TRYPKT_USEREG_8822C(x) \
(((x) & BIT_MASK_TRYPKT_USEREG_8822C) << BIT_SHIFT_TRYPKT_USEREG_8822C)
#define BITS_TRYPKT_USEREG_8822C \
(BIT_MASK_TRYPKT_USEREG_8822C << BIT_SHIFT_TRYPKT_USEREG_8822C)
#define BIT_CLEAR_TRYPKT_USEREG_8822C(x) ((x) & (~BITS_TRYPKT_USEREG_8822C))
#define BIT_GET_TRYPKT_USEREG_8822C(x) \
(((x) >> BIT_SHIFT_TRYPKT_USEREG_8822C) & BIT_MASK_TRYPKT_USEREG_8822C)
#define BIT_SET_TRYPKT_USEREG_8822C(x, v) \
(BIT_CLEAR_TRYPKT_USEREG_8822C(x) | BIT_TRYPKT_USEREG_8822C(v))
#define BIT_CTLPKT_USEREG_8822C BIT(16)
/* 2 REG_LOOPBACK_OPTION_8822C */
#define BIT_LOOPACK_FAST_EDCA_EN_8822C BIT(24)
/* 2 REG_AESIV_SETTING_8822C */
@@ -13531,6 +13517,10 @@
/* 2 REG_NOT_VALID_8822C */
/* 2 REG_CCA_TXEN_CNT_8822C */
#define BIT_ENABLE_STOP_UPDATE_NAV_8822C BIT(21)
#define BIT_ENABLE_GEN_RANDON_SLOT_TX_8822C BIT(20)
#define BIT_ENABLE_RANDOM_SHIFT_TX_8822C BIT(19)
#define BIT_ENABLE_EDCA_REF_FUNCTION_8822C BIT(18)
#define BIT_CCA_TXEN_CNT_SWITCH_8822C BIT(17)
#define BIT_CCA_TXEN_CNT_EN_8822C BIT(16)
@@ -15814,7 +15804,43 @@
/* 2 REG_RSVD_8822C */
/* 2 REG_RSVD_8822C */
/* 2 REG_SCHEDULER_COUNTER_8822C */
#define BIT_SHIFT__SCHEDULER_COUNTER_8822C 16
#define BIT_MASK__SCHEDULER_COUNTER_8822C 0xffff
#define BIT__SCHEDULER_COUNTER_8822C(x) \
(((x) & BIT_MASK__SCHEDULER_COUNTER_8822C) \
<< BIT_SHIFT__SCHEDULER_COUNTER_8822C)
#define BITS__SCHEDULER_COUNTER_8822C \
(BIT_MASK__SCHEDULER_COUNTER_8822C \
<< BIT_SHIFT__SCHEDULER_COUNTER_8822C)
#define BIT_CLEAR__SCHEDULER_COUNTER_8822C(x) \
((x) & (~BITS__SCHEDULER_COUNTER_8822C))
#define BIT_GET__SCHEDULER_COUNTER_8822C(x) \
(((x) >> BIT_SHIFT__SCHEDULER_COUNTER_8822C) & \
BIT_MASK__SCHEDULER_COUNTER_8822C)
#define BIT_SET__SCHEDULER_COUNTER_8822C(x, v) \
(BIT_CLEAR__SCHEDULER_COUNTER_8822C(x) | \
BIT__SCHEDULER_COUNTER_8822C(v))
#define BIT__SCHEDULER_COUNTER_RST_8822C BIT(8)
#define BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C 0
#define BIT_MASK_SCHEDULER_COUNTER_SEL_8822C 0xff
#define BIT_SCHEDULER_COUNTER_SEL_8822C(x) \
(((x) & BIT_MASK_SCHEDULER_COUNTER_SEL_8822C) \
<< BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C)
#define BITS_SCHEDULER_COUNTER_SEL_8822C \
(BIT_MASK_SCHEDULER_COUNTER_SEL_8822C \
<< BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C)
#define BIT_CLEAR_SCHEDULER_COUNTER_SEL_8822C(x) \
((x) & (~BITS_SCHEDULER_COUNTER_SEL_8822C))
#define BIT_GET_SCHEDULER_COUNTER_SEL_8822C(x) \
(((x) >> BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C) & \
BIT_MASK_SCHEDULER_COUNTER_SEL_8822C)
#define BIT_SET_SCHEDULER_COUNTER_SEL_8822C(x, v) \
(BIT_CLEAR_SCHEDULER_COUNTER_SEL_8822C(x) | \
BIT_SCHEDULER_COUNTER_SEL_8822C(v))
/* 2 REG_RSVD_8822C */
@@ -18568,6 +18594,11 @@
#define BIT_CLI0_PWR_ST_V1_8822C BIT(0)
/* 2 REG_GENERAL_OPTION_8822C */
#define BIT_WMAC_RXRST_NDP_TIMEOUT_8822C BIT(11)
#define BIT_WMAC_NDP_STANDBY_WAIT_RXEND_8822C BIT(10)
#define BIT_DUMMY_FCS_READY_MASK_EN_8822C BIT(9)
#define BIT_RXFIFO_GNT_CUT_8822C BIT(8)
#define BIT_DUMMY_RXD_FCS_ERROR_MASK_EN_V1_8822C BIT(7)
#define BIT_WMAC_EXT_DBG_SEL_V1_8822C BIT(6)
#define BIT_WMAC_FIX_FIRST_MPDU_WITH_PHYSTS_8822C BIT(5)
#define BIT_RX_DMA_BYPASS_CHECK_DATABYPASS_CHECK_DATA_8822C BIT(4)
@@ -21264,6 +21295,9 @@
#define BIT_CMD11_SEQ_EN_8822C BIT(0)
/* 2 REG_SDIO_CTRL_8822C */
#define BIT_SIG_OUT_PH_8822C BIT(0)
/* 2 REG_SDIO_DRIVING_8822C */
#define BIT_SHIFT_SDIO_DRV_TYPE_D_8822C 12

5
hal/halmac/halmac_fw_info.h
View File

@@ -16,7 +16,7 @@
#ifndef _HALMAC_FW_INFO_H_
#define _HALMAC_FW_INFO_H_
#define H2C_FORMAT_VERSION 11
#define H2C_FORMAT_VERSION 12
/* FW bin information */
#define WLAN_FW_HDR_SIZE 64
@@ -69,6 +69,9 @@ enum halmac_packet_id {
HALMAC_PACKET_PROBE_REQ = 0x00,
HALMAC_PACKET_SYNC_BCN = 0x01,
HALMAC_PACKET_DISCOVERY_BCN = 0x02,
HALMAC_PACKET_PROBE_REQ_NLO = 0xF0,
HALMAC_PACKET_SYNC_BCN_NLO = 0xF1,
HALMAC_PACKET_DISCOVERY_BCN_NLO = 0xF2,
HALMAC_PACKET_UNDEFINE = 0x7FFFFFFF,
};

164
hal/halmac/halmac_fw_offload_c2h_ap.h
View File

@@ -20,15 +20,16 @@
#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03
#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01
#define C2H_SUB_CMD_ID_CFG_PARAM_ACK 0X01
#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01
#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01
#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01
#define C2H_SUB_CMD_ID_UPDATE_PKT_ACK 0X01
#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01
#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01
#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01
#define C2H_SUB_CMD_ID_IQK_ACK 0X01
#define C2H_SUB_CMD_ID_PWR_TRK_ACK 0X01
#define C2H_SUB_CMD_ID_PSD_ACK 0X01
#define C2H_SUB_CMD_ID_FW_MEM_DUMP_ACK 0X01
#define C2H_SUB_CMD_ID_PSD_DATA 0X04
#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
#define C2H_SUB_CMD_ID_IQK_DATA 0X06
@@ -50,16 +51,20 @@
#define C2H_SUB_CMD_ID_FW_FWCTRL_RPT 0X1F
#define C2H_SUB_CMD_ID_H2C_LOOPBACK_ACK 0X20
#define C2H_SUB_CMD_ID_FWCMD_LOOPBACK_ACK 0X21
#define C2H_SUB_CMD_ID_SCAN_CH_NOTIFY 0X22
#define C2H_SUB_CMD_ID_FW_TBTT_RPT 0X23
#define C2H_SUB_CMD_ID_BCN_OFFLOAD 0X24
#define H2C_SUB_CMD_ID_CFG_PARAM_ACK SUB_CMD_ID_CFG_PARAM
#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH
#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX
#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE
#define H2C_SUB_CMD_ID_UPDATE_PKT_ACK SUB_CMD_ID_UPDATE_PKT
#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK
#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK
#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH
#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK
#define H2C_SUB_CMD_ID_PWR_TRK_ACK SUB_CMD_ID_PWR_TRK
#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD
#define H2C_SUB_CMD_ID_FW_MEM_DUMP_ACK SUB_CMD_ID_FW_MEM_DUMP
#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT
#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG
#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING
@@ -67,15 +72,16 @@
#define H2C_SUB_CMD_ID_H2C_LOOPBACK_ACK SUB_CMD_ID_H2C_LOOPBACK
#define H2C_SUB_CMD_ID_FWCMD_LOOPBACK_ACK SUB_CMD_ID_FWCMD_LOOPBACK
#define H2C_CMD_ID_CFG_PARAM_ACK 0XFF
#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF
#define H2C_CMD_ID_BT_COEX_ACK 0XFF
#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF
#define H2C_CMD_ID_UPDATE_PKT_ACK 0XFF
#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF
#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF
#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF
#define H2C_CMD_ID_IQK_ACK 0XFF
#define H2C_CMD_ID_PWR_TRK_ACK 0XFF
#define H2C_CMD_ID_PSD_ACK 0XFF
#define H2C_CMD_ID_FW_MEM_DUMP_ACK 0XFF
#define H2C_CMD_ID_CCX_RPT 0XFF
#define H2C_CMD_ID_FW_DBG_MSG 0XFF
#define H2C_CMD_ID_FW_SNDING_ACK 0XFF
@@ -124,6 +130,46 @@
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
#define SCAN_STATUS_RPT_SET_H2C_SEQ_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
#define SCAN_STATUS_RPT_GET_TSF_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
#define SCAN_STATUS_RPT_SET_TSF_0(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
#define SCAN_STATUS_RPT_SET_TSF_0_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
#define SCAN_STATUS_RPT_GET_TSF_1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)
#define SCAN_STATUS_RPT_SET_TSF_1(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)
#define SCAN_STATUS_RPT_SET_TSF_1_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)
#define SCAN_STATUS_RPT_GET_TSF_2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)
#define SCAN_STATUS_RPT_SET_TSF_2(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)
#define SCAN_STATUS_RPT_SET_TSF_2_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)
#define SCAN_STATUS_RPT_GET_TSF_3(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 24, 8)
#define SCAN_STATUS_RPT_SET_TSF_3(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value)
#define SCAN_STATUS_RPT_SET_TSF_3_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value)
#define SCAN_STATUS_RPT_GET_TSF_4(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 0, 8)
#define SCAN_STATUS_RPT_SET_TSF_4(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 8, value)
#define SCAN_STATUS_RPT_SET_TSF_4_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 8, value)
#define SCAN_STATUS_RPT_GET_TSF_5(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 8, 8)
#define SCAN_STATUS_RPT_SET_TSF_5(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 8, 8, value)
#define SCAN_STATUS_RPT_SET_TSF_5_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 8, 8, value)
#define SCAN_STATUS_RPT_GET_TSF_6(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 16, 8)
#define SCAN_STATUS_RPT_SET_TSF_6(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 16, 8, value)
#define SCAN_STATUS_RPT_SET_TSF_6_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 16, 8, value)
#define SCAN_STATUS_RPT_GET_TSF_7(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 24, 8)
#define SCAN_STATUS_RPT_SET_TSF_7(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 24, 8, value)
#define SCAN_STATUS_RPT_SET_TSF_7_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 24, 8, value)
#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_pkt) \
GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(c2h_pkt, value) \
@@ -158,6 +204,46 @@
SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 0, 32, value)
#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 0, 32, value)
#define CH_SWITCH_ACK_GET_TSF_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8)
#define CH_SWITCH_ACK_SET_TSF_0(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value)
#define CH_SWITCH_ACK_SET_TSF_0_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value)
#define CH_SWITCH_ACK_GET_TSF_1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8)
#define CH_SWITCH_ACK_SET_TSF_1(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value)
#define CH_SWITCH_ACK_SET_TSF_1_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value)
#define CH_SWITCH_ACK_GET_TSF_2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
#define CH_SWITCH_ACK_SET_TSF_2(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
#define CH_SWITCH_ACK_SET_TSF_2_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
#define CH_SWITCH_ACK_GET_TSF_3(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
#define CH_SWITCH_ACK_SET_TSF_3(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
#define CH_SWITCH_ACK_SET_TSF_3_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
#define CH_SWITCH_ACK_GET_TSF_4(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X10, 0, 8)
#define CH_SWITCH_ACK_SET_TSF_4(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 0, 8, value)
#define CH_SWITCH_ACK_SET_TSF_4_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 0, 8, value)
#define CH_SWITCH_ACK_GET_TSF_5(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X10, 8, 8)
#define CH_SWITCH_ACK_SET_TSF_5(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 8, 8, value)
#define CH_SWITCH_ACK_SET_TSF_5_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 8, 8, value)
#define CH_SWITCH_ACK_GET_TSF_6(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X10, 16, 8)
#define CH_SWITCH_ACK_SET_TSF_6(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 16, 8, value)
#define CH_SWITCH_ACK_SET_TSF_6_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 16, 8, value)
#define CH_SWITCH_ACK_GET_TSF_7(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X10, 24, 8)
#define CH_SWITCH_ACK_SET_TSF_7(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 24, 8, value)
#define CH_SWITCH_ACK_SET_TSF_7_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 24, 8, value)
#define BT_COEX_ACK_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 0, 8)
#define BT_COEX_ACK_SET_DATA_START(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 8, value)
@@ -503,4 +589,76 @@
SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 8, value)
#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 8, value)
#define SCAN_CH_NOTIFY_GET_CH_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
#define SCAN_CH_NOTIFY_SET_CH_NUM(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
#define SCAN_CH_NOTIFY_SET_CH_NUM_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
#define SCAN_CH_NOTIFY_GET_NOTIFY_ID(c2h_pkt) \
GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
#define SCAN_CH_NOTIFY_SET_NOTIFY_ID(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
#define SCAN_CH_NOTIFY_SET_NOTIFY_ID_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
#define SCAN_CH_NOTIFY_GET_STATUS(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
#define SCAN_CH_NOTIFY_SET_STATUS(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
#define SCAN_CH_NOTIFY_SET_STATUS_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
#define SCAN_CH_NOTIFY_GET_TSF_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
#define SCAN_CH_NOTIFY_SET_TSF_0(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
#define SCAN_CH_NOTIFY_SET_TSF_0_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
#define SCAN_CH_NOTIFY_GET_TSF_1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)
#define SCAN_CH_NOTIFY_SET_TSF_1(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)
#define SCAN_CH_NOTIFY_SET_TSF_1_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)
#define SCAN_CH_NOTIFY_GET_TSF_2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)
#define SCAN_CH_NOTIFY_SET_TSF_2(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)
#define SCAN_CH_NOTIFY_SET_TSF_2_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)
#define SCAN_CH_NOTIFY_GET_TSF_3(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 24, 8)
#define SCAN_CH_NOTIFY_SET_TSF_3(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value)
#define SCAN_CH_NOTIFY_SET_TSF_3_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value)
#define SCAN_CH_NOTIFY_GET_TSF_4(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8)
#define SCAN_CH_NOTIFY_SET_TSF_4(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value)
#define SCAN_CH_NOTIFY_SET_TSF_4_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value)
#define SCAN_CH_NOTIFY_GET_TSF_5(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8)
#define SCAN_CH_NOTIFY_SET_TSF_5(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value)
#define SCAN_CH_NOTIFY_SET_TSF_5_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value)
#define SCAN_CH_NOTIFY_GET_TSF_6(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
#define SCAN_CH_NOTIFY_SET_TSF_6(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
#define SCAN_CH_NOTIFY_SET_TSF_6_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
#define SCAN_CH_NOTIFY_GET_TSF_7(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
#define SCAN_CH_NOTIFY_SET_TSF_7(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
#define SCAN_CH_NOTIFY_SET_TSF_7_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
#define FW_TBTT_RPT_GET_PORT_NUMBER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
#define FW_TBTT_RPT_SET_PORT_NUMBER(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
#define FW_TBTT_RPT_SET_PORT_NUMBER_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
#define BCN_OFFLOAD_GET_SUPPORT_VER(c2h_pkt) \
GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
#define BCN_OFFLOAD_SET_SUPPORT_VER(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
#define BCN_OFFLOAD_SET_SUPPORT_VER_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
#define BCN_OFFLOAD_GET_STATUS(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
#define BCN_OFFLOAD_SET_STATUS(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
#define BCN_OFFLOAD_SET_STATUS_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
#endif

117
hal/halmac/halmac_fw_offload_c2h_nic.h
View File

@@ -20,15 +20,16 @@
#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03
#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01
#define C2H_SUB_CMD_ID_CFG_PARAM_ACK 0X01
#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01
#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01
#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01
#define C2H_SUB_CMD_ID_UPDATE_PKT_ACK 0X01
#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01
#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01
#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01
#define C2H_SUB_CMD_ID_IQK_ACK 0X01
#define C2H_SUB_CMD_ID_PWR_TRK_ACK 0X01
#define C2H_SUB_CMD_ID_PSD_ACK 0X01
#define C2H_SUB_CMD_ID_FW_MEM_DUMP_ACK 0X01
#define C2H_SUB_CMD_ID_PSD_DATA 0X04
#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
#define C2H_SUB_CMD_ID_IQK_DATA 0X06
@@ -50,16 +51,20 @@
#define C2H_SUB_CMD_ID_FW_FWCTRL_RPT 0X1F
#define C2H_SUB_CMD_ID_H2C_LOOPBACK_ACK 0X20
#define C2H_SUB_CMD_ID_FWCMD_LOOPBACK_ACK 0X21
#define C2H_SUB_CMD_ID_SCAN_CH_NOTIFY 0X22
#define C2H_SUB_CMD_ID_FW_TBTT_RPT 0X23
#define C2H_SUB_CMD_ID_BCN_OFFLOAD 0X24
#define H2C_SUB_CMD_ID_CFG_PARAM_ACK SUB_CMD_ID_CFG_PARAM
#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH
#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX
#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE
#define H2C_SUB_CMD_ID_UPDATE_PKT_ACK SUB_CMD_ID_UPDATE_PKT
#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK
#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK
#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH
#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK
#define H2C_SUB_CMD_ID_PWR_TRK_ACK SUB_CMD_ID_PWR_TRK
#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD
#define H2C_SUB_CMD_ID_FW_MEM_DUMP_ACK SUB_CMD_ID_FW_MEM_DUMP
#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT
#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG
#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING
@@ -67,15 +72,16 @@
#define H2C_SUB_CMD_ID_H2C_LOOPBACK_ACK SUB_CMD_ID_H2C_LOOPBACK
#define H2C_SUB_CMD_ID_FWCMD_LOOPBACK_ACK SUB_CMD_ID_FWCMD_LOOPBACK
#define H2C_CMD_ID_CFG_PARAM_ACK 0XFF
#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF
#define H2C_CMD_ID_BT_COEX_ACK 0XFF
#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF
#define H2C_CMD_ID_UPDATE_PKT_ACK 0XFF
#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF
#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF
#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF
#define H2C_CMD_ID_IQK_ACK 0XFF
#define H2C_CMD_ID_PWR_TRK_ACK 0XFF
#define H2C_CMD_ID_PSD_ACK 0XFF
#define H2C_CMD_ID_FW_MEM_DUMP_ACK 0XFF
#define H2C_CMD_ID_CCX_RPT 0XFF
#define H2C_CMD_ID_FW_DBG_MSG 0XFF
#define H2C_CMD_ID_FW_SNDING_ACK 0XFF
@@ -110,6 +116,36 @@
LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
#define SCAN_STATUS_RPT_SET_H2C_SEQ(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
#define SCAN_STATUS_RPT_GET_TSF_0(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
#define SCAN_STATUS_RPT_SET_TSF_0(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
#define SCAN_STATUS_RPT_GET_TSF_1(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)
#define SCAN_STATUS_RPT_SET_TSF_1(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)
#define SCAN_STATUS_RPT_GET_TSF_2(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)
#define SCAN_STATUS_RPT_SET_TSF_2(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)
#define SCAN_STATUS_RPT_GET_TSF_3(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8)
#define SCAN_STATUS_RPT_SET_TSF_3(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value)
#define SCAN_STATUS_RPT_GET_TSF_4(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 8)
#define SCAN_STATUS_RPT_SET_TSF_4(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 8, value)
#define SCAN_STATUS_RPT_GET_TSF_5(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 8, 8)
#define SCAN_STATUS_RPT_SET_TSF_5(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 8, 8, value)
#define SCAN_STATUS_RPT_GET_TSF_6(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 16, 8)
#define SCAN_STATUS_RPT_SET_TSF_6(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 16, 8, value)
#define SCAN_STATUS_RPT_GET_TSF_7(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 24, 8)
#define SCAN_STATUS_RPT_SET_TSF_7(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 24, 8, value)
#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(c2h_pkt, value) \
@@ -133,6 +169,30 @@
LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 0, 32)
#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 0, 32, value)
#define CH_SWITCH_ACK_GET_TSF_0(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8)
#define CH_SWITCH_ACK_SET_TSF_0(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value)
#define CH_SWITCH_ACK_GET_TSF_1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8)
#define CH_SWITCH_ACK_SET_TSF_1(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value)
#define CH_SWITCH_ACK_GET_TSF_2(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
#define CH_SWITCH_ACK_SET_TSF_2(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
#define CH_SWITCH_ACK_GET_TSF_3(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
#define CH_SWITCH_ACK_SET_TSF_3(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
#define CH_SWITCH_ACK_GET_TSF_4(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 0, 8)
#define CH_SWITCH_ACK_SET_TSF_4(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 0, 8, value)
#define CH_SWITCH_ACK_GET_TSF_5(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 8, 8)
#define CH_SWITCH_ACK_SET_TSF_5(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 8, 8, value)
#define CH_SWITCH_ACK_GET_TSF_6(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 16, 8)
#define CH_SWITCH_ACK_SET_TSF_6(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 16, 8, value)
#define CH_SWITCH_ACK_GET_TSF_7(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 24, 8)
#define CH_SWITCH_ACK_SET_TSF_7(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 24, 8, value)
#define BT_COEX_ACK_GET_DATA_START(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 8)
#define BT_COEX_ACK_SET_DATA_START(c2h_pkt, value) \
@@ -368,4 +428,55 @@
LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 8)
#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 8, value)
#define SCAN_CH_NOTIFY_GET_CH_NUM(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
#define SCAN_CH_NOTIFY_SET_CH_NUM(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
#define SCAN_CH_NOTIFY_GET_NOTIFY_ID(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
#define SCAN_CH_NOTIFY_SET_NOTIFY_ID(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
#define SCAN_CH_NOTIFY_GET_STATUS(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
#define SCAN_CH_NOTIFY_SET_STATUS(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
#define SCAN_CH_NOTIFY_GET_TSF_0(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
#define SCAN_CH_NOTIFY_SET_TSF_0(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
#define SCAN_CH_NOTIFY_GET_TSF_1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)
#define SCAN_CH_NOTIFY_SET_TSF_1(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)
#define SCAN_CH_NOTIFY_GET_TSF_2(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)
#define SCAN_CH_NOTIFY_SET_TSF_2(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)
#define SCAN_CH_NOTIFY_GET_TSF_3(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8)
#define SCAN_CH_NOTIFY_SET_TSF_3(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value)
#define SCAN_CH_NOTIFY_GET_TSF_4(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8)
#define SCAN_CH_NOTIFY_SET_TSF_4(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value)
#define SCAN_CH_NOTIFY_GET_TSF_5(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8)
#define SCAN_CH_NOTIFY_SET_TSF_5(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value)
#define SCAN_CH_NOTIFY_GET_TSF_6(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
#define SCAN_CH_NOTIFY_SET_TSF_6(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
#define SCAN_CH_NOTIFY_GET_TSF_7(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
#define SCAN_CH_NOTIFY_SET_TSF_7(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
#define FW_TBTT_RPT_GET_PORT_NUMBER(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
#define FW_TBTT_RPT_SET_PORT_NUMBER(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
#define BCN_OFFLOAD_GET_SUPPORT_VER(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
#define BCN_OFFLOAD_SET_SUPPORT_VER(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
#define BCN_OFFLOAD_GET_STATUS(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
#define BCN_OFFLOAD_SET_STATUS(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
#endif

538
hal/halmac/halmac_fw_offload_h2c_ap.h
View File

@@ -16,6 +16,7 @@
#ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_
#define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_
#define CMD_ID_FW_OFFLOAD_H2C 0XFF
#define CMD_ID_FW_ACCESS_TEST 0XFF
#define CMD_ID_CH_SWITCH 0XFF
#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF
#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF
@@ -28,19 +29,21 @@
#define CMD_ID_IQK 0XFF
#define CMD_ID_PWR_TRK 0XFF
#define CMD_ID_PSD 0XFF
#define CMD_ID_PHYDM_INFO 0XFF
#define CMD_ID_FW_SNDING 0XFF
#define CMD_ID_FW_FWCTRL 0XFF
#define CMD_ID_H2C_LOOPBACK 0XFF
#define CMD_ID_FWCMD_LOOPBACK 0XFF
#define CMD_ID_UPDATE_SCAN_PKT 0XFF
#define CMD_ID_BCN_OFFLOAD 0XFF
#define CMD_ID_P2PPS 0XFF
#define CMD_ID_BT_COEX 0XFF
#define CMD_ID_NAN_CTRL 0XFF
#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF
#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF
#define CMD_ID_FW_ACCESS_TEST 0XFF
#define CMD_ID_PHYDM_INFO 0XFF
#define CMD_ID_FW_SNDING 0XFF
#define CMD_ID_H2C_LOOPBACK 0XFF
#define CMD_ID_FWCMD_LOOPBACK 0XFF
#define CMD_ID_FW_FWCTRL 0XFF
#define CATEGORY_H2C_CMD_HEADER 0X00
#define CATEGORY_FW_OFFLOAD_H2C 0X01
#define CATEGORY_FW_ACCESS_TEST 0X01
#define CATEGORY_CH_SWITCH 0X01
#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01
#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01
@@ -53,17 +56,19 @@
#define CATEGORY_IQK 0X01
#define CATEGORY_PWR_TRK 0X01
#define CATEGORY_PSD 0X01
#define CATEGORY_PHYDM_INFO 0X01
#define CATEGORY_FW_SNDING 0X01
#define CATEGORY_FW_FWCTRL 0X01
#define CATEGORY_H2C_LOOPBACK 0X01
#define CATEGORY_FWCMD_LOOPBACK 0X01
#define CATEGORY_UPDATE_SCAN_PKT 0X01
#define CATEGORY_BCN_OFFLOAD 0X01
#define CATEGORY_P2PPS 0X01
#define CATEGORY_BT_COEX 0X01
#define CATEGORY_NAN_CTRL 0X01
#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01
#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01
#define CATEGORY_FW_ACCESS_TEST 0X01
#define CATEGORY_PHYDM_INFO 0X01
#define CATEGORY_FW_SNDING 0X01
#define CATEGORY_H2C_LOOPBACK 0X01
#define CATEGORY_FWCMD_LOOPBACK 0X01
#define CATEGORY_FW_FWCTRL 0X01
#define SUB_CMD_ID_FW_ACCESS_TEST 0X00
#define SUB_CMD_ID_CH_SWITCH 0X02
#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05
@@ -76,17 +81,18 @@
#define SUB_CMD_ID_IQK 0X0E
#define SUB_CMD_ID_PWR_TRK 0X0F
#define SUB_CMD_ID_PSD 0X10
#define SUB_CMD_ID_PHYDM_INFO 0X11
#define SUB_CMD_ID_FW_SNDING 0X12
#define SUB_CMD_ID_FW_FWCTRL 0X13
#define SUB_CMD_ID_H2C_LOOPBACK 0X14
#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15
#define SUB_CMD_ID_UPDATE_SCAN_PKT 0X16
#define SUB_CMD_ID_BCN_OFFLOAD 0X17
#define SUB_CMD_ID_P2PPS 0X24
#define SUB_CMD_ID_BT_COEX 0X60
#define SUB_CMD_ID_NAN_CTRL 0XB2
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
#define SUB_CMD_ID_FW_ACCESS_TEST 0X00
#define SUB_CMD_ID_PHYDM_INFO 0X11
#define SUB_CMD_ID_FW_SNDING 0X12
#define SUB_CMD_ID_H2C_LOOPBACK 0X14
#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15
#define SUB_CMD_ID_FW_FWCTRL 0X13
#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 7)
#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 7, value)
@@ -142,6 +148,114 @@
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 16, value)
#define FW_OFFLOAD_H2C_SET_SEQ_NUM_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 16, value)
#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_TXFF_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_RXFF_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_FWFF_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_PHYFF_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 4, 1)
#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 5, 1)
#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_CAM_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 6, 1)
#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 6, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 6, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 7, 1)
#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 7, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 7, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1)
#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 9, 1)
#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 16, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE0_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 17, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 17, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE1_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 17, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 18, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 18, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE2_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 18, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 19, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 19, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE3_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 19, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 20, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 20, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE4_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 20, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 21, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 21, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE5_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 21, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 22, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 22, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE6_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 22, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 23, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 23, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE7_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 23, 1, value)
#define CH_SWITCH_GET_START(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
#define CH_SWITCH_SET_START(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
@@ -162,6 +276,11 @@
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 2, value)
#define CH_SWITCH_SET_PERIODIC_OPT_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 2, value)
#define CH_SWITCH_GET_SCAN_MODE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 5, 1)
#define CH_SWITCH_SET_SCAN_MODE(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value)
#define CH_SWITCH_SET_SCAN_MODE_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value)
#define CH_SWITCH_GET_INFO_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
#define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
@@ -480,6 +599,171 @@
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 16, value)
#define PSD_SET_END_PSD_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 16, value)
#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
#define PHYDM_INFO_SET_REF_TYPE_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
#define PHYDM_INFO_SET_RF_TYPE_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
#define PHYDM_INFO_SET_CUT_VER_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 24, 4)
#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 4, value)
#define PHYDM_INFO_SET_RX_ANT_STATUS_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 4, value)
#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 28, 4)
#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 28, 4, value)
#define PHYDM_INFO_SET_TX_ANT_STATUS_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 28, 4, value)
#define FW_SNDING_GET_SU0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
#define FW_SNDING_SET_SU0(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
#define FW_SNDING_SET_SU0_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
#define FW_SNDING_GET_SU1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
#define FW_SNDING_SET_SU1(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
#define FW_SNDING_SET_SU1_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
#define FW_SNDING_GET_MU(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
#define FW_SNDING_SET_MU(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
#define FW_SNDING_SET_MU_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
#define FW_SNDING_GET_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
#define FW_SNDING_SET_PERIOD(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
#define FW_SNDING_SET_PERIOD_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
#define FW_SNDING_SET_NDPA0_HEAD_PG_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
#define FW_SNDING_SET_NDPA1_HEAD_PG_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0XC, 0, 8)
#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 0, 8, value)
#define FW_SNDING_SET_MU_NDPA_HEAD_PG_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 0, 8, value)
#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 8, 8)
#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 8, 8, value)
#define FW_SNDING_SET_RPT0_HEAD_PG_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 8, 8, value)
#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 16, 8)
#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 16, 8, value)
#define FW_SNDING_SET_RPT1_HEAD_PG_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 16, 8, value)
#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 24, 8)
#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 24, 8, value)
#define FW_SNDING_SET_RPT2_HEAD_PG_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 24, 8, value)
#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
#define FW_FWCTRL_SET_SEQ_NUM_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1)
#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value)
#define FW_FWCTRL_SET_MORE_CONTENT_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value)
#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 9, 7)
#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 7, value)
#define FW_FWCTRL_SET_CONTENT_IDX_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 7, value)
#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
#define FW_FWCTRL_SET_CLASS_ID_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
#define FW_FWCTRL_GET_LENGTH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
#define FW_FWCTRL_SET_LENGTH_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
#define FW_FWCTRL_GET_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32)
#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value)
#define FW_FWCTRL_SET_CONTENT_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value)
#define UPDATE_SCAN_PKT_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)
#define UPDATE_SCAN_PKT_SET_SIZE(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)
#define UPDATE_SCAN_PKT_SET_SIZE_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)
#define UPDATE_SCAN_PKT_GET_INDEX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
#define UPDATE_SCAN_PKT_SET_INDEX(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
#define UPDATE_SCAN_PKT_SET_INDEX_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
#define UPDATE_SCAN_PKT_GET_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
#define UPDATE_SCAN_PKT_SET_LOC(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
#define UPDATE_SCAN_PKT_SET_LOC_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
#define BCN_OFFLOAD_GET_REQUEST_VERSION(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
#define BCN_OFFLOAD_SET_REQUEST_VERSION(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
#define BCN_OFFLOAD_SET_REQUEST_VERSION_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
#define BCN_OFFLOAD_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
#define BCN_OFFLOAD_SET_ENABLE(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
#define BCN_OFFLOAD_SET_ENABLE_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
#define BCN_OFFLOAD_GET_MORE_RULE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
#define BCN_OFFLOAD_SET_MORE_RULE(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
#define BCN_OFFLOAD_SET_MORE_RULE_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
#define BCN_OFFLOAD_GET_C2H_PERIODIC_REPORT(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)
#define BCN_OFFLOAD_SET_C2H_PERIODIC_REPORT(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)
#define BCN_OFFLOAD_SET_C2H_PERIODIC_REPORT_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)
#define BCN_OFFLOAD_GET_REPORT_PERIOD(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
#define BCN_OFFLOAD_SET_REPORT_PERIOD(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
#define BCN_OFFLOAD_SET_REPORT_PERIOD_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
#define BCN_OFFLOAD_GET_RULE_LENGTH(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
#define BCN_OFFLOAD_SET_RULE_LENGTH(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
#define BCN_OFFLOAD_SET_RULE_LENGTH_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
#define BCN_OFFLOAD_GET_RULE_CONTENT(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)
#define BCN_OFFLOAD_SET_RULE_CONTENT(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
#define BCN_OFFLOAD_SET_RULE_CONTENT_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
#define P2PPS_GET_OFFLOAD_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
#define P2PPS_SET_OFFLOAD_EN(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
@@ -768,222 +1052,4 @@
SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 16, 16, value)
#define NAN_CHANNEL_PLAN_1_SET_DURATION_5_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 16, 16, value)
#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_TXFF_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_RXFF_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_FWFF_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_PHYFF_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 4, 1)
#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 5, 1)
#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_CAM_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 6, 1)
#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 6, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 6, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 7, 1)
#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 7, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 7, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1)
#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 9, 1)
#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 16, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE0_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 17, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 17, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE1_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 17, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 18, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 18, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE2_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 18, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 19, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 19, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE3_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 19, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 20, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 20, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE4_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 20, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 21, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 21, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE5_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 21, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 22, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 22, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE6_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 22, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 23, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 23, 1, value)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE7_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 23, 1, value)
#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
#define PHYDM_INFO_SET_REF_TYPE_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
#define PHYDM_INFO_SET_RF_TYPE_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
#define PHYDM_INFO_SET_CUT_VER_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 24, 4)
#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 4, value)
#define PHYDM_INFO_SET_RX_ANT_STATUS_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 4, value)
#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 28, 4)
#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 28, 4, value)
#define PHYDM_INFO_SET_TX_ANT_STATUS_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 28, 4, value)
#define FW_SNDING_GET_SU0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
#define FW_SNDING_SET_SU0(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
#define FW_SNDING_SET_SU0_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
#define FW_SNDING_GET_SU1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
#define FW_SNDING_SET_SU1(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
#define FW_SNDING_SET_SU1_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
#define FW_SNDING_GET_MU(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
#define FW_SNDING_SET_MU(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
#define FW_SNDING_SET_MU_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
#define FW_SNDING_GET_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
#define FW_SNDING_SET_PERIOD(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
#define FW_SNDING_SET_PERIOD_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
#define FW_SNDING_SET_NDPA0_HEAD_PG_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
#define FW_SNDING_SET_NDPA1_HEAD_PG_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0XC, 0, 8)
#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 0, 8, value)
#define FW_SNDING_SET_MU_NDPA_HEAD_PG_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 0, 8, value)
#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 8, 8)
#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 8, 8, value)
#define FW_SNDING_SET_RPT0_HEAD_PG_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 8, 8, value)
#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 16, 8)
#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 16, 8, value)
#define FW_SNDING_SET_RPT1_HEAD_PG_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 16, 8, value)
#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 24, 8)
#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 24, 8, value)
#define FW_SNDING_SET_RPT2_HEAD_PG_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 24, 8, value)
#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
#define FW_FWCTRL_SET_SEQ_NUM_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1)
#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value)
#define FW_FWCTRL_SET_MORE_CONTENT_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value)
#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 9, 7)
#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 7, value)
#define FW_FWCTRL_SET_CONTENT_IDX_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 7, value)
#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
#define FW_FWCTRL_SET_CLASS_ID_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
#define FW_FWCTRL_GET_LENGTH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
#define FW_FWCTRL_SET_LENGTH_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
#define FW_FWCTRL_GET_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32)
#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value)
#define FW_FWCTRL_SET_CONTENT_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value)
#endif

373
hal/halmac/halmac_fw_offload_h2c_nic.h
View File

@@ -16,6 +16,7 @@
#ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_
#define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_
#define CMD_ID_FW_OFFLOAD_H2C 0XFF
#define CMD_ID_FW_ACCESS_TEST 0XFF
#define CMD_ID_CH_SWITCH 0XFF
#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF
#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF
@@ -28,19 +29,21 @@
#define CMD_ID_IQK 0XFF
#define CMD_ID_PWR_TRK 0XFF
#define CMD_ID_PSD 0XFF
#define CMD_ID_PHYDM_INFO 0XFF
#define CMD_ID_FW_SNDING 0XFF
#define CMD_ID_FW_FWCTRL 0XFF
#define CMD_ID_H2C_LOOPBACK 0XFF
#define CMD_ID_FWCMD_LOOPBACK 0XFF
#define CMD_ID_UPDATE_SCAN_PKT 0XFF
#define CMD_ID_BCN_OFFLOAD 0XFF
#define CMD_ID_P2PPS 0XFF
#define CMD_ID_BT_COEX 0XFF
#define CMD_ID_NAN_CTRL 0XFF
#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF
#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF
#define CMD_ID_FW_ACCESS_TEST 0XFF
#define CMD_ID_PHYDM_INFO 0XFF
#define CMD_ID_FW_SNDING 0XFF
#define CMD_ID_H2C_LOOPBACK 0XFF
#define CMD_ID_FWCMD_LOOPBACK 0XFF
#define CMD_ID_FW_FWCTRL 0XFF
#define CATEGORY_H2C_CMD_HEADER 0X00
#define CATEGORY_FW_OFFLOAD_H2C 0X01
#define CATEGORY_FW_ACCESS_TEST 0X01
#define CATEGORY_CH_SWITCH 0X01
#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01
#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01
@@ -53,17 +56,19 @@
#define CATEGORY_IQK 0X01
#define CATEGORY_PWR_TRK 0X01
#define CATEGORY_PSD 0X01
#define CATEGORY_PHYDM_INFO 0X01
#define CATEGORY_FW_SNDING 0X01
#define CATEGORY_FW_FWCTRL 0X01
#define CATEGORY_H2C_LOOPBACK 0X01
#define CATEGORY_FWCMD_LOOPBACK 0X01
#define CATEGORY_UPDATE_SCAN_PKT 0X01
#define CATEGORY_BCN_OFFLOAD 0X01
#define CATEGORY_P2PPS 0X01
#define CATEGORY_BT_COEX 0X01
#define CATEGORY_NAN_CTRL 0X01
#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01
#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01
#define CATEGORY_FW_ACCESS_TEST 0X01
#define CATEGORY_PHYDM_INFO 0X01
#define CATEGORY_FW_SNDING 0X01
#define CATEGORY_H2C_LOOPBACK 0X01
#define CATEGORY_FWCMD_LOOPBACK 0X01
#define CATEGORY_FW_FWCTRL 0X01
#define SUB_CMD_ID_FW_ACCESS_TEST 0X00
#define SUB_CMD_ID_CH_SWITCH 0X02
#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05
@@ -76,17 +81,18 @@
#define SUB_CMD_ID_IQK 0X0E
#define SUB_CMD_ID_PWR_TRK 0X0F
#define SUB_CMD_ID_PSD 0X10
#define SUB_CMD_ID_P2PPS 0X24
#define SUB_CMD_ID_BT_COEX 0X60
#define SUB_CMD_ID_NAN_CTRL 0XB2
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
#define SUB_CMD_ID_FW_ACCESS_TEST 0X00
#define SUB_CMD_ID_PHYDM_INFO 0X11
#define SUB_CMD_ID_FW_SNDING 0X12
#define SUB_CMD_ID_FW_FWCTRL 0X13
#define SUB_CMD_ID_H2C_LOOPBACK 0X14
#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15
#define SUB_CMD_ID_UPDATE_SCAN_PKT 0X16
#define SUB_CMD_ID_BCN_OFFLOAD 0X17
#define SUB_CMD_ID_P2PPS 0X24
#define SUB_CMD_ID_BT_COEX 0X60
#define SUB_CMD_ID_NAN_CTRL 0XB2
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 7)
#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value) \
@@ -125,6 +131,78 @@
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 16)
#define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 16, value)
#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 1)
#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1)
#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 6, 1)
#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 6, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 7, 1)
#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 7, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1)
#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 1)
#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 17, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 17, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 18, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 18, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 19, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 19, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 20, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 20, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 21, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 21, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 22, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 22, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 23, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 23, 1, value)
#define CH_SWITCH_GET_START(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
#define CH_SWITCH_SET_START(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
@@ -139,6 +217,9 @@
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 2)
#define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 2, value)
#define CH_SWITCH_GET_SCAN_MODE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1)
#define CH_SWITCH_SET_SCAN_MODE(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value)
#define CH_SWITCH_GET_INFO_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
#define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
@@ -356,6 +437,117 @@
#define PSD_GET_END_PSD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 16)
#define PSD_SET_END_PSD(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 16, value)
#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 4)
#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 4, value)
#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 28, 4)
#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 28, 4, value)
#define FW_SNDING_GET_SU0(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
#define FW_SNDING_SET_SU0(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
#define FW_SNDING_GET_SU1(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
#define FW_SNDING_SET_SU1(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
#define FW_SNDING_GET_MU(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
#define FW_SNDING_SET_MU(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
#define FW_SNDING_GET_PERIOD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
#define FW_SNDING_SET_PERIOD(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 0, 8)
#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 0, 8, value)
#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 8, 8)
#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 8, 8, value)
#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 16, 8)
#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 16, 8, value)
#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 24, 8)
#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 24, 8, value)
#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1)
#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value)
#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 7)
#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 7, value)
#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
#define FW_FWCTRL_GET_LENGTH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
#define FW_FWCTRL_GET_CONTENT(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32)
#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value)
#define UPDATE_SCAN_PKT_GET_SIZE(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)
#define UPDATE_SCAN_PKT_SET_SIZE(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)
#define UPDATE_SCAN_PKT_GET_INDEX(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
#define UPDATE_SCAN_PKT_SET_INDEX(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
#define UPDATE_SCAN_PKT_GET_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
#define UPDATE_SCAN_PKT_SET_LOC(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
#define BCN_OFFLOAD_GET_REQUEST_VERSION(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
#define BCN_OFFLOAD_SET_REQUEST_VERSION(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
#define BCN_OFFLOAD_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
#define BCN_OFFLOAD_SET_ENABLE(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
#define BCN_OFFLOAD_GET_MORE_RULE(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
#define BCN_OFFLOAD_SET_MORE_RULE(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
#define BCN_OFFLOAD_GET_C2H_PERIODIC_REPORT(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)
#define BCN_OFFLOAD_SET_C2H_PERIODIC_REPORT(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)
#define BCN_OFFLOAD_GET_REPORT_PERIOD(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
#define BCN_OFFLOAD_SET_REPORT_PERIOD(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
#define BCN_OFFLOAD_GET_RULE_LENGTH(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
#define BCN_OFFLOAD_SET_RULE_LENGTH(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
#define BCN_OFFLOAD_GET_RULE_CONTENT(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
#define BCN_OFFLOAD_SET_RULE_CONTENT(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
#define P2PPS_GET_OFFLOAD_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
#define P2PPS_SET_OFFLOAD_EN(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
@@ -546,149 +738,4 @@
LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 16, 16)
#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 16, 16, value)
#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 1)
#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1)
#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 6, 1)
#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 6, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 7, 1)
#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 7, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1)
#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 1)
#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 17, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 17, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 18, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 18, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 19, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 19, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 20, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 20, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 21, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 21, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 22, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 22, 1, value)
#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 23, 1)
#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 23, 1, value)
#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 4)
#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 4, value)
#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 28, 4)
#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 28, 4, value)
#define FW_SNDING_GET_SU0(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
#define FW_SNDING_SET_SU0(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
#define FW_SNDING_GET_SU1(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
#define FW_SNDING_SET_SU1(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
#define FW_SNDING_GET_MU(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
#define FW_SNDING_SET_MU(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
#define FW_SNDING_GET_PERIOD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
#define FW_SNDING_SET_PERIOD(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 0, 8)
#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 0, 8, value)
#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 8, 8)
#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 8, 8, value)
#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 16, 8)
#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 16, 8, value)
#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 24, 8)
#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 24, 8, value)
#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1)
#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value)
#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 7)
#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 7, value)
#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
#define FW_FWCTRL_GET_LENGTH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
#define FW_FWCTRL_GET_CONTENT(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32)
#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value)
#endif

17
hal/halmac/halmac_gpio_cmd.h
View File

@@ -71,6 +71,23 @@
#define HALMAC_WLPHY_RFE_CTRL2GPIO 25
#define HALMAC_EXT_XTAL 26
#define HALMAC_SW_IO 27
#define HALMAC_BT_SDIO_INT 28
#define HALMAC_BT_JTAG 29
#define HALMAC_WL_JTAG 30
#define HALMAC_BT_RF 31
#define HALMAC_WLPHY_RFE_CTRL2GPIO_2 32
#define HALMAC_MAILBOX_3W 33
#define HALMAC_MAILBOX_1W 34
#define HALMAC_SW_DPDT_SEL 35
#define HALMAC_BT_DPDT_SEL 36
#define HALMAC_WL_DPDT_SEL 37
#define HALMAC_BT_PAPE_SEL 38
#define HALMAC_SW_PAPE_SEL 39
#define HALMAC_WLBT_PAPE_SEL 40
#define HALMAC_SW_LNAON_SET 41
#define HALMAC_BT_LNAON_SEL 42
#define HALMAC_WLBT_LNAON_SEL 43
#define HALMAC_SWR_CTRL_EN 44
struct halmac_gpio_pimux_list {
u16 func;

38
hal/halmac/halmac_hw_cfg.h
View File

@@ -16,7 +16,7 @@
#ifndef __HALMAC__HW_CFG_H__
#define __HALMAC__HW_CFG_H__
#include <drv_conf.h> /* CONFIG_[IC] */
#include <drv_conf.h> /* CONFIG_[IC], CONFIG_[INTF]_HCI */
#ifdef CONFIG_RTL8723A
#define HALMAC_8723A_SUPPORT 1
@@ -138,6 +138,24 @@
#define HALMAC_8198F_SUPPORT 0
#endif
#ifdef CONFIG_RTL8192F
#define HALMAC_8192F_SUPPORT 1
#else
#define HALMAC_8192F_SUPPORT 0
#endif
#ifdef CONFIG_RTL8197G
#define HALMAC_8197G_SUPPORT 1
#else
#define HALMAC_8197G_SUPPORT 0
#endif
#ifdef CONFIG_RTL8812F
#define HALMAC_8812F_SUPPORT 1
#else
#define HALMAC_8812F_SUPPORT 0
#endif
/* Halmac support IC version */
@@ -165,6 +183,24 @@
#define HALMAC_8822C_SUPPORT 0
#endif
/* Interface support */
#ifdef CONFIG_SDIO_HCI
#define HALMAC_SDIO_SUPPORT 1
#else
#define HALMAC_SDIO_SUPPORT 0
#endif
#ifdef CONFIG_USB_HCI
#define HALMAC_USB_SUPPORT 1
#else
#define HALMAC_USB_SUPPORT 0
#endif
#ifdef CONFIG_PCI_HCI
#define HALMAC_PCIE_SUPPORT 1
#else
#define HALMAC_PCIE_SUPPORT 0
#endif
#endif /* __HALMAC__HW_CFG_H__ */

38
hal/halmac/halmac_original_c2h_ap.h
View File

@@ -27,6 +27,7 @@
#define CMD_ID_C2H_RA_PARA_RPT 0X0E
#define CMD_ID_C2H_CUR_CHANNEL 0X10
#define CMD_ID_C2H_GPIO_WAKEUP 0X14
#define CMD_ID_C2H_DROPID_RPT 0X2D
#define C2H_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
#define C2H_SET_CMD_ID(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
@@ -609,4 +610,41 @@
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
#define C2H_GPIO_WAKEUP_SET_TRIGGER_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
#define C2H_DROPID_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
#define C2H_DROPID_RPT_SET_CMD_ID(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
#define C2H_DROPID_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
#define C2H_DROPID_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
#define C2H_DROPID_RPT_SET_SEQ(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
#define C2H_DROPID_RPT_SET_SEQ_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
#define C2H_DROPID_RPT_GET_DROPIDBIT(c2h_pkt) \
GET_C2H_FIELD(c2h_pkt + 0X00, 16, 4)
#define C2H_DROPID_RPT_SET_DROPIDBIT(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 4, value)
#define C2H_DROPID_RPT_SET_DROPIDBIT_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 4, value)
#define C2H_DROPID_RPT_GET_CURDROPID(c2h_pkt) \
GET_C2H_FIELD(c2h_pkt + 0X00, 20, 2)
#define C2H_DROPID_RPT_SET_CURDROPID(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 20, 2, value)
#define C2H_DROPID_RPT_SET_CURDROPID_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 20, 2, value)
#define C2H_DROPID_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
#define C2H_DROPID_RPT_SET_MACID(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
#define C2H_DROPID_RPT_SET_MACID_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
#define C2H_DROPID_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
#define C2H_DROPID_RPT_SET_LEN(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
#define C2H_DROPID_RPT_SET_LEN_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
#define C2H_DROPID_RPT_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
#define C2H_DROPID_RPT_SET_TRIGGER(c2h_pkt, value) \
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
#define C2H_DROPID_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value) \
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
#endif

26
hal/halmac/halmac_original_c2h_nic.h
View File

@@ -27,6 +27,7 @@
#define CMD_ID_C2H_RA_PARA_RPT 0X0E
#define CMD_ID_C2H_CUR_CHANNEL 0X10
#define CMD_ID_C2H_GPIO_WAKEUP 0X14
#define CMD_ID_C2H_DROPID_RPT 0X2D
#define C2H_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
#define C2H_SET_CMD_ID(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
@@ -405,4 +406,29 @@
LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
#define C2H_GPIO_WAKEUP_SET_TRIGGER(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
#define C2H_DROPID_RPT_GET_CMD_ID(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
#define C2H_DROPID_RPT_SET_CMD_ID(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
#define C2H_DROPID_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
#define C2H_DROPID_RPT_SET_SEQ(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
#define C2H_DROPID_RPT_GET_DROPIDBIT(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 4)
#define C2H_DROPID_RPT_SET_DROPIDBIT(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 4, value)
#define C2H_DROPID_RPT_GET_CURDROPID(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 20, 2)
#define C2H_DROPID_RPT_SET_CURDROPID(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 20, 2, value)
#define C2H_DROPID_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
#define C2H_DROPID_RPT_SET_MACID(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
#define C2H_DROPID_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
#define C2H_DROPID_RPT_SET_LEN(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
#define C2H_DROPID_RPT_GET_TRIGGER(c2h_pkt) \
LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
#define C2H_DROPID_RPT_SET_TRIGGER(c2h_pkt, value) \
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
#endif

84
hal/halmac/halmac_original_h2c_ap.h
View File

@@ -675,66 +675,30 @@
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
#define SET_PWR_MODE_SET_PWR_STATE_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X04, 16, 1)
#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 1, value)
#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 1, value)
#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X04, 17, 1)
#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 17, 1, value)
#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 17, 1, value)
#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X04, 18, 1)
#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 18, 1, value)
#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 18, 1, value)
#define SET_PWR_MODE_GET_PROTECT_BCN(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X04, 19, 1)
#define SET_PWR_MODE_SET_PROTECT_BCN(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 19, 1, value)
#define SET_PWR_MODE_SET_PROTECT_BCN_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 19, 1, value)
#define SET_PWR_MODE_GET_SILENCE_PERIOD(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X04, 20, 1)
#define SET_PWR_MODE_SET_SILENCE_PERIOD(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 20, 1, value)
#define SET_PWR_MODE_SET_SILENCE_PERIOD_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 20, 1, value)
#define SET_PWR_MODE_GET_FAST_BT_CONNECT(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X04, 21, 1)
#define SET_PWR_MODE_SET_FAST_BT_CONNECT(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 21, 1, value)
#define SET_PWR_MODE_SET_FAST_BT_CONNECT_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 21, 1, value)
#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X04, 22, 1)
#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 22, 1, value)
#define SET_PWR_MODE_SET_TWO_ANTENNA_EN_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 22, 1, value)
#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X04, 24, 1)
#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 1, value)
#define SET_PWR_MODE_SET_ADOPT_USER_SETTING_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 1, value)
#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X04, 25, 3)
#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 25, 3, value)
#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 25, 3, value)
#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X04, 28, 4)
#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 28, 4, value)
#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 28, 4, value)
#define SET_PWR_MODE_GET_RSVD_NOUSED(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)
#define SET_PWR_MODE_SET_RSVD_NOUSED(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)
#define SET_PWR_MODE_SET_RSVD_NOUSED_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)
#define SET_PWR_MODE_GET_BCN_RECEIVING_TIME(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X04, 24, 5)
#define SET_PWR_MODE_SET_BCN_RECEIVING_TIME(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 5, value)
#define SET_PWR_MODE_SET_BCN_RECEIVING_TIME_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 5, value)
#define SET_PWR_MODE_GET_BCN_LISTEN_INTERVAL(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X04, 29, 2)
#define SET_PWR_MODE_SET_BCN_LISTEN_INTERVAL(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 29, 2, value)
#define SET_PWR_MODE_SET_BCN_LISTEN_INTERVAL_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 29, 2, value)
#define SET_PWR_MODE_GET_ADOPT_BCN_RECEIVING_TIME(h2c_pkt) \
GET_H2C_FIELD(h2c_pkt + 0X04, 31, 1)
#define SET_PWR_MODE_SET_ADOPT_BCN_RECEIVING_TIME(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 31, 1, value)
#define SET_PWR_MODE_SET_ADOPT_BCN_RECEIVING_TIME_NO_CLR(h2c_pkt, value) \
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 31, 1, value)
#define PS_TUNING_PARA_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
#define PS_TUNING_PARA_SET_CMD_ID(h2c_pkt, value) \
SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)

56
hal/halmac/halmac_original_h2c_nic.h
View File

@@ -485,46 +485,22 @@
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
#define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 1)
#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 1, value)
#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 17, 1)
#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 17, 1, value)
#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 18, 1)
#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 18, 1, value)
#define SET_PWR_MODE_GET_PROTECT_BCN(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 19, 1)
#define SET_PWR_MODE_SET_PROTECT_BCN(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 19, 1, value)
#define SET_PWR_MODE_GET_SILENCE_PERIOD(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 20, 1)
#define SET_PWR_MODE_SET_SILENCE_PERIOD(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 20, 1, value)
#define SET_PWR_MODE_GET_FAST_BT_CONNECT(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 21, 1)
#define SET_PWR_MODE_SET_FAST_BT_CONNECT(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 21, 1, value)
#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 22, 1)
#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 22, 1, value)
#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 1)
#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 1, value)
#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 25, 3)
#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 25, 3, value)
#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 28, 4)
#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 28, 4, value)
#define SET_PWR_MODE_GET_RSVD_NOUSED(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)
#define SET_PWR_MODE_SET_RSVD_NOUSED(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)
#define SET_PWR_MODE_GET_BCN_RECEIVING_TIME(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 5)
#define SET_PWR_MODE_SET_BCN_RECEIVING_TIME(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 5, value)
#define SET_PWR_MODE_GET_BCN_LISTEN_INTERVAL(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 29, 2)
#define SET_PWR_MODE_SET_BCN_LISTEN_INTERVAL(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 29, 2, value)
#define SET_PWR_MODE_GET_ADOPT_BCN_RECEIVING_TIME(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 31, 1)
#define SET_PWR_MODE_SET_ADOPT_BCN_RECEIVING_TIME(h2c_pkt, value) \
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 31, 1, value)
#define PS_TUNING_PARA_GET_CMD_ID(h2c_pkt) \
LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
#define PS_TUNING_PARA_SET_CMD_ID(h2c_pkt, value) \

32
hal/halmac/halmac_pcie_reg.h
View File

@@ -17,13 +17,37 @@
#define __HALMAC_PCIE_REG_H__
/* PCIE PHY register */
#define RAC_CTRL_PPR 0x00
#define RAC_SET_PPR 0x20
#define RAC_TRG_PPR 0x21
#define RAC_CTRL_PPR 0x00
#define RAC_SET_PPR 0x20
#define RAC_TRG_PPR 0x21
#define RAC_CTRL_PPR_V1 0x30
#define RAC_SET_PPR_V1 0x31
/* PCIE CFG register */
#define PCIE_L1_BACKDOOR 0x719
#define PCIE_L1SS_CTRL 0x718
#define PCIE_L1_CTRL 0x719
#define PCIE_ASPM_CTRL 0x70F
#define PCIE_CLK_CTRL 0x725
#define PCIE_L1SS_CAP 0x160
#define PCIE_L1SS_SUP 0x164
#define PCIE_L1SS_STS 0x168
/* PCIE CFG bit */
#define PCIE_BIT_WAKE BIT(2)
#define PCIE_BIT_L1 BIT(3)
#define PCIE_BIT_CLK BIT(4)
#define PCIE_BIT_L0S BIT(7)
#define PCIE_BIT_L1SS BIT(5)
#define PCIE_BIT_L1SSSUP BIT(4)
/* PCIE ASPM mask*/
#define SHFT_L1DLY 3
#define SHFT_L0SDLY 0
#define PCIE_ASPMDLY_MASK 0x07
#define PCIE_L1SS_MASK 0x0F
/* PCIE Capability */
#define PCIE_L1SS_ID 0x001E
/* PCIE MAC register */
#define LINK_CTRL2_REG_OFFSET 0xA0

31
hal/halmac/halmac_pwr_seq_cmd.h
View File

@@ -20,26 +20,21 @@
#define HALMAC_PWR_POLLING_CNT 20000
/*
* The value of cmd : 4 bits
*/
/* The value of cmd : 4 bits */
/*
* offset : the read register offset
/* offset : the read register offset
* msk : the mask of the read value
* value : N/A, left by 0
* Note : dirver shall implement this function by read & msk
*/
#define HALMAC_PWR_CMD_READ 0x00
/*
* offset: the read register offset
/* offset: the read register offset
* msk: the mask of the write bits
* value: write value
* Note: driver shall implement this cmd by read & msk after write
*/
#define HALMAC_PWR_CMD_WRITE 0x01
/*
* offset: the read register offset
/* offset: the read register offset
* msk: the mask of the polled value
* value: the value to be polled, masked by the msd field.
* Note: driver shall implement this cmd by
@@ -49,22 +44,18 @@
* } while(not timeout);
*/
#define HALMAC_PWR_CMD_POLLING 0x02
/*
* offset: the value to delay
/* offset: the value to delay
* msk: N/A
* value: the unit of delay, 0: us, 1: ms
*/
#define HALMAC_PWR_CMD_DELAY 0x03
/*
* offset: N/A
/* offset: N/A
* msk: N/A
* value: N/A
*/
#define HALMAC_PWR_CMD_END 0x04
/*
* The value of base : 4 bits
*/
/* The value of base : 4 bits */
/* define the base address of each block */
#define HALMAC_PWR_ADDR_MAC 0x00
@@ -72,17 +63,13 @@
#define HALMAC_PWR_ADDR_PCIE 0x02
#define HALMAC_PWR_ADDR_SDIO 0x03
/*
* The value of interface_msk : 4 bits
*/
/* The value of interface_msk : 4 bits */
#define HALMAC_PWR_INTF_SDIO_MSK BIT(0)
#define HALMAC_PWR_INTF_USB_MSK BIT(1)
#define HALMAC_PWR_INTF_PCI_MSK BIT(2)
#define HALMAC_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
/*
* The value of cut_msk : 8 bits
*/
/* The value of cut_msk : 8 bits */
#define HALMAC_PWR_CUT_TESTCHIP_MSK BIT(0)
#define HALMAC_PWR_CUT_A_MSK BIT(1)
#define HALMAC_PWR_CUT_B_MSK BIT(2)

3684
hal/halmac/halmac_reg2.h
View File

File diff suppressed because it is too large Load Diff

3
hal/halmac/halmac_reg_8197f.h
View File

@@ -696,5 +696,8 @@
#define REG_SEC_OPT_V2_8197F 0x07EC
#define REG_RTS_ADDRESS_0_8197F 0x07F0
#define REG_RTS_ADDRESS_1_8197F 0x07F8
#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8197F 0x1700
#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8197F 0x1704
#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8197F 0x1708
#endif

2
hal/halmac/halmac_reg_8814b.h
View File

@@ -628,7 +628,6 @@
#define REG_DUMMY_PAGE4_V1_8814B 0x04FC
#define REG_DUMMY_PAGE4_1_8814B 0x04FE
#define REG_MU_OFFSET_8814B 0x1400
#define REG_USEREG_SETTING_8814B 0x1420
#define REG_BF0_TIME_SETTING_8814B 0x1428
#define REG_BF1_TIME_SETTING_8814B 0x142C
#define REG_BF_TIMEOUT_EN_8814B 0x1430
@@ -796,6 +795,7 @@
#define REG_TIMER_COMPARE_8814B 0x15C0
#define REG_TIMER_COMPARE_VALUE_LOW_8814B 0x15C4
#define REG_TIMER_COMPARE_VALUE_HIGH_8814B 0x15C8
#define REG_SCHEDULER_COUNTER_8814B 0x15D0
#define REG_WMAC_CR_8814B 0x0600
#define REG_WMAC_FWPKT_CR_8814B 0x0601
#define REG_FW_STS_FILTER_8814B 0x0602

4
hal/halmac/halmac_reg_8822c.h
View File

@@ -440,7 +440,7 @@
#define REG_Q6_Q7_INFO_8822C 0x140C
#define REG_MGQ_HIQ_INFO_8822C 0x1410
#define REG_CMDQ_BCNQ_INFO_8822C 0x1414
#define REG_USEREG_SETTING_8822C 0x1420
#define REG_LOOPBACK_OPTION_8822C 0x1420
#define REG_AESIV_SETTING_8822C 0x1424
#define REG_BF0_TIME_SETTING_8822C 0x1428
#define REG_BF1_TIME_SETTING_8822C 0x142C
@@ -620,6 +620,7 @@
#define REG_P2PPS_HW_AUTO_PAUSE_CTRL_8822C 0x156C
#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8822C 0x1570
#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8822C 0x1574
#define REG_SCHEDULER_COUNTER_8822C 0x15D0
#define REG_WMAC_CR_8822C 0x0600
#define REG_WMAC_FWPKT_CR_8822C 0x0601
#define REG_FW_STS_FILTER_8822C 0x0602
@@ -837,6 +838,7 @@
#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822C 0x1708
#define REG_SDIO_TX_CTRL_8822C 0x10250000
#define REG_SDIO_CMD11_VOL_SWITCH_8822C 0x10250004
#define REG_SDIO_CTRL_8822C 0x10250005
#define REG_SDIO_DRIVING_8822C 0x10250006
#define REG_SDIO_MONITOR_8822C 0x10250008
#define REG_SDIO_MONITOR_2_8822C 0x1025000C

3
hal/halmac/halmac_rx_bd_nic.h
View File

@@ -16,7 +16,8 @@
#ifndef _HALMAC_RX_BD_NIC_H_
#define _HALMAC_RX_BD_NIC_H_
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||\
HALMAC_8812F_SUPPORT)
/*TXBD_DW0*/

129
hal/halmac/halmac_rx_desc_ap.h
View File

@@ -16,13 +16,21 @@
#ifndef _HALMAC_RX_DESC_AP_H_
#define _HALMAC_RX_DESC_AP_H_
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
/*RXDESC_WORD0*/
#define GET_RX_DESC_EOR(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \
30)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_PHYPKTIDC(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \
28)
@@ -39,7 +47,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_SWDEC(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \
@@ -81,7 +89,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_TY_PE(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x3, \
@@ -99,7 +108,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_MF(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
@@ -114,7 +123,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_PAM(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
@@ -131,7 +141,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_CHK_VLD(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
@@ -149,7 +160,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
@@ -161,7 +172,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_CHKERR(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
@@ -184,7 +196,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_PAGGR(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
@@ -201,7 +214,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RXID_MATCH(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
@@ -219,7 +233,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_AMSDU(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
@@ -228,7 +242,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_MACID_VLD(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
@@ -238,7 +253,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_TID(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0xf, 8)
@@ -246,7 +261,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_MACID(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x7f, \
@@ -269,7 +285,8 @@
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_PPDU_CNT(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x3, \
@@ -279,7 +296,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_C2H(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
@@ -287,7 +304,7 @@
#endif
#if (HALMAC_8198F_SUPPORT)
#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)
#define GET_RX_DESC_HWRSVD_V1(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x7, \
@@ -296,7 +313,7 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_HWRSVD(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0xf, \
@@ -304,7 +321,7 @@
#endif
#if (HALMAC_8198F_SUPPORT)
#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)
#define GET_RX_DESC_RXMAGPKT(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
@@ -314,7 +331,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_WLANHD_IV_LEN(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x3f, \
@@ -330,7 +347,7 @@
#endif
#if (HALMAC_8822C_SUPPORT)
#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RX_STATISTICS(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
@@ -339,7 +356,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RX_IS_QOS(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
@@ -357,7 +375,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_FRAG(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0xf, \
@@ -378,7 +396,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_PATTERN_MATCH(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \
@@ -395,7 +414,7 @@
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \
@@ -408,7 +427,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_DMA_AGG_NUM(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0xff, \
@@ -417,7 +436,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_BSSID_FIT_1_0(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x3, \
@@ -438,7 +458,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_HTC(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \
@@ -456,7 +476,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_BSSID_FIT_4_2(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x7, 7)
@@ -472,7 +493,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RX_RATE(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x7f, \
@@ -481,7 +502,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
HALMAC_8812F_SUPPORT)
/*RXDESC_WORD4*/
@@ -516,17 +538,33 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_MACID_RPT_BUFF(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \
17)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, \
16)
#endif
#if (HALMAC_8192F_SUPPORT)
#define GET_RX_DESC_SWPS_RPT_V1(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, \
16)
#endif
#if (HALMAC_8814B_SUPPORT)
#define GET_RX_DESC_MACID_V1(rxdesc) \
@@ -535,8 +573,20 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define GET_RX_DESC_FC_POWER_V1(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, \
15)
#define GET_RX_DESC_TXRPTMID_CTL_MASK_V1(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, \
14)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RX_SCRAMBLER(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \
@@ -546,6 +596,14 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define GET_RX_DESC_SNIF_INFO(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x3f, \
8)
#endif
#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
#define GET_RX_DESC_FC_POWER(rxdesc) \
@@ -568,7 +626,7 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_PATTERN_IDX(rxdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \
@@ -593,7 +651,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
/*RXDESC_WORD5*/

168
hal/halmac/halmac_rx_desc_chip.h
View File

@@ -608,4 +608,172 @@
#endif
#if (HALMAC_8192F_SUPPORT)
/*RXDESC_WORD0*/
#define GET_RX_DESC_EOR_8192F(rxdesc) GET_RX_DESC_EOR(rxdesc)
#define GET_RX_DESC_SWDEC_8192F(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
#define GET_RX_DESC_PHYST_8192F(rxdesc) GET_RX_DESC_PHYST(rxdesc)
#define GET_RX_DESC_SHIFT_8192F(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
#define GET_RX_DESC_QOS_8192F(rxdesc) GET_RX_DESC_QOS(rxdesc)
#define GET_RX_DESC_SECURITY_8192F(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
#define GET_RX_DESC_DRV_INFO_SIZE_8192F(rxdesc) \
GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
#define GET_RX_DESC_ICV_ERR_8192F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
#define GET_RX_DESC_CRC32_8192F(rxdesc) GET_RX_DESC_CRC32(rxdesc)
#define GET_RX_DESC_PKT_LEN_8192F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
/*RXDESC_WORD1*/
#define GET_RX_DESC_BC_8192F(rxdesc) GET_RX_DESC_BC(rxdesc)
#define GET_RX_DESC_MC_8192F(rxdesc) GET_RX_DESC_MC(rxdesc)
#define GET_RX_DESC_TY_PE_8192F(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
#define GET_RX_DESC_MF_8192F(rxdesc) GET_RX_DESC_MF(rxdesc)
#define GET_RX_DESC_MD_8192F(rxdesc) GET_RX_DESC_MD(rxdesc)
#define GET_RX_DESC_PWR_8192F(rxdesc) GET_RX_DESC_PWR(rxdesc)
#define GET_RX_DESC_PAM_8192F(rxdesc) GET_RX_DESC_PAM(rxdesc)
#define GET_RX_DESC_CHK_VLD_8192F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
#define GET_RX_DESC_RX_IS_TCP_UDP_8192F(rxdesc) \
GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
#define GET_RX_DESC_RX_IPV_8192F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
#define GET_RX_DESC_CHKERR_8192F(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
#define GET_RX_DESC_PAGGR_8192F(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
#define GET_RX_DESC_RXID_MATCH_8192F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
#define GET_RX_DESC_AMSDU_8192F(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
#define GET_RX_DESC_MACID_VLD_8192F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
#define GET_RX_DESC_TID_8192F(rxdesc) GET_RX_DESC_TID(rxdesc)
#define GET_RX_DESC_MACID_8192F(rxdesc) GET_RX_DESC_MACID(rxdesc)
/*RXDESC_WORD2*/
#define GET_RX_DESC_FCS_OK_8192F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
#define GET_RX_DESC_PPDU_CNT_8192F(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
#define GET_RX_DESC_C2H_8192F(rxdesc) GET_RX_DESC_C2H(rxdesc)
#define GET_RX_DESC_HWRSVD_8192F(rxdesc) GET_RX_DESC_HWRSVD_V1(rxdesc)
#define GET_RX_DESC_RXMAGPKT_8192F(rxdesc) GET_RX_DESC_RXMAGPKT(rxdesc)
#define GET_RX_DESC_WLANHD_IV_LEN_8192F(rxdesc) \
GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
#define GET_RX_DESC_RX_IS_QOS_8192F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
#define GET_RX_DESC_FRAG_8192F(rxdesc) GET_RX_DESC_FRAG(rxdesc)
#define GET_RX_DESC_SEQ_8192F(rxdesc) GET_RX_DESC_SEQ(rxdesc)
/*RXDESC_WORD3*/
#define GET_RX_DESC_MAGIC_WAKE_8192F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
#define GET_RX_DESC_UNICAST_WAKE_8192F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
#define GET_RX_DESC_PATTERN_MATCH_8192F(rxdesc) \
GET_RX_DESC_PATTERN_MATCH(rxdesc)
#define GET_RX_DESC_DMA_AGG_NUM_8192F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
#define GET_RX_DESC_BSSID_FIT_1_0_8192F(rxdesc) \
GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
#define GET_RX_DESC_EOSP_8192F(rxdesc) GET_RX_DESC_EOSP(rxdesc)
#define GET_RX_DESC_HTC_8192F(rxdesc) GET_RX_DESC_HTC(rxdesc)
#define GET_RX_DESC_RX_RATE_8192F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
/*RXDESC_WORD4*/
#define GET_RX_DESC_A1_FIT_8192F(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
#define GET_RX_DESC_MACID_RPT_BUFF_8192F(rxdesc) \
GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
#define GET_RX_DESC_SWPS_RPT_8192F(rxdesc) GET_RX_DESC_SWPS_RPT_V1(rxdesc)
#define GET_RX_DESC_FC_POWER_8192F(rxdesc) GET_RX_DESC_FC_POWER_V1(rxdesc)
#define GET_RX_DESC_TXRPTMID_CTL_MASK_8192F(rxdesc) \
GET_RX_DESC_TXRPTMID_CTL_MASK_V1(rxdesc)
#define GET_RX_DESC_SNIF_INFO_8192F(rxdesc) GET_RX_DESC_SNIF_INFO(rxdesc)
#define GET_RX_DESC_PATTERN_IDX_8192F(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)
/*RXDESC_WORD5*/
#define GET_RX_DESC_TSFL_8192F(rxdesc) GET_RX_DESC_TSFL(rxdesc)
#endif
#if (HALMAC_8812F_SUPPORT)
/*RXDESC_WORD0*/
#define GET_RX_DESC_EOR_8812F(rxdesc) GET_RX_DESC_EOR(rxdesc)
#define GET_RX_DESC_PHYPKTIDC_8812F(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
#define GET_RX_DESC_SWDEC_8812F(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
#define GET_RX_DESC_PHYST_8812F(rxdesc) GET_RX_DESC_PHYST(rxdesc)
#define GET_RX_DESC_SHIFT_8812F(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
#define GET_RX_DESC_QOS_8812F(rxdesc) GET_RX_DESC_QOS(rxdesc)
#define GET_RX_DESC_SECURITY_8812F(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
#define GET_RX_DESC_DRV_INFO_SIZE_8812F(rxdesc) \
GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
#define GET_RX_DESC_ICV_ERR_8812F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
#define GET_RX_DESC_CRC32_8812F(rxdesc) GET_RX_DESC_CRC32(rxdesc)
#define GET_RX_DESC_PKT_LEN_8812F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
/*RXDESC_WORD1*/
#define GET_RX_DESC_BC_8812F(rxdesc) GET_RX_DESC_BC(rxdesc)
#define GET_RX_DESC_MC_8812F(rxdesc) GET_RX_DESC_MC(rxdesc)
#define GET_RX_DESC_TY_PE_8812F(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
#define GET_RX_DESC_MF_8812F(rxdesc) GET_RX_DESC_MF(rxdesc)
#define GET_RX_DESC_MD_8812F(rxdesc) GET_RX_DESC_MD(rxdesc)
#define GET_RX_DESC_PWR_8812F(rxdesc) GET_RX_DESC_PWR(rxdesc)
#define GET_RX_DESC_PAM_8812F(rxdesc) GET_RX_DESC_PAM(rxdesc)
#define GET_RX_DESC_CHK_VLD_8812F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
#define GET_RX_DESC_RX_IS_TCP_UDP_8812F(rxdesc) \
GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
#define GET_RX_DESC_RX_IPV_8812F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
#define GET_RX_DESC_CHKERR_8812F(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
#define GET_RX_DESC_PAGGR_8812F(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
#define GET_RX_DESC_RXID_MATCH_8812F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
#define GET_RX_DESC_AMSDU_8812F(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
#define GET_RX_DESC_MACID_VLD_8812F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
#define GET_RX_DESC_TID_8812F(rxdesc) GET_RX_DESC_TID(rxdesc)
#define GET_RX_DESC_MACID_8812F(rxdesc) GET_RX_DESC_MACID(rxdesc)
/*RXDESC_WORD2*/
#define GET_RX_DESC_FCS_OK_8812F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
#define GET_RX_DESC_PPDU_CNT_8812F(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
#define GET_RX_DESC_C2H_8812F(rxdesc) GET_RX_DESC_C2H(rxdesc)
#define GET_RX_DESC_HWRSVD_8812F(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)
#define GET_RX_DESC_WLANHD_IV_LEN_8812F(rxdesc) \
GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
#define GET_RX_DESC_RX_STATISTICS_8812F(rxdesc) \
GET_RX_DESC_RX_STATISTICS(rxdesc)
#define GET_RX_DESC_RX_IS_QOS_8812F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
#define GET_RX_DESC_FRAG_8812F(rxdesc) GET_RX_DESC_FRAG(rxdesc)
#define GET_RX_DESC_SEQ_8812F(rxdesc) GET_RX_DESC_SEQ(rxdesc)
/*RXDESC_WORD3*/
#define GET_RX_DESC_MAGIC_WAKE_8812F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
#define GET_RX_DESC_UNICAST_WAKE_8812F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
#define GET_RX_DESC_PATTERN_MATCH_8812F(rxdesc) \
GET_RX_DESC_PATTERN_MATCH(rxdesc)
#define GET_RX_DESC_RXPAYLOAD_MATCH_8812F(rxdesc) \
GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)
#define GET_RX_DESC_RXPAYLOAD_ID_8812F(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)
#define GET_RX_DESC_DMA_AGG_NUM_8812F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
#define GET_RX_DESC_BSSID_FIT_1_0_8812F(rxdesc) \
GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
#define GET_RX_DESC_EOSP_8812F(rxdesc) GET_RX_DESC_EOSP(rxdesc)
#define GET_RX_DESC_HTC_8812F(rxdesc) GET_RX_DESC_HTC(rxdesc)
#define GET_RX_DESC_BSSID_FIT_4_2_8812F(rxdesc) \
GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
#define GET_RX_DESC_RX_RATE_8812F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
/*RXDESC_WORD4*/
#define GET_RX_DESC_A1_FIT_8812F(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
#define GET_RX_DESC_MACID_RPT_BUFF_8812F(rxdesc) \
GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
#define GET_RX_DESC_RX_PRE_NDP_VLD_8812F(rxdesc) \
GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
#define GET_RX_DESC_RX_SCRAMBLER_8812F(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
#define GET_RX_DESC_RX_EOF_8812F(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
#define GET_RX_DESC_PATTERN_IDX_8812F(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)
/*RXDESC_WORD5*/
#define GET_RX_DESC_TSFL_8812F(rxdesc) GET_RX_DESC_TSFL(rxdesc)
#endif
#endif

122
hal/halmac/halmac_rx_desc_nic.h
View File

@@ -16,11 +16,19 @@
#ifndef _HALMAC_RX_DESC_NIC_H_
#define _HALMAC_RX_DESC_NIC_H_
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
/*RXDESC_WORD0*/
#define GET_RX_DESC_EOR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 30, 1)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_PHYPKTIDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 28, 1)
#endif
@@ -33,7 +41,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_SWDEC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 27, 1)
#define GET_RX_DESC_PHYST(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 26, 1)
@@ -53,7 +61,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_TY_PE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 28, 2)
@@ -67,7 +76,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_MF(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 27, 1)
#define GET_RX_DESC_MD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 26, 1)
@@ -76,7 +85,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_PAM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 24, 1)
@@ -89,7 +99,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_CHK_VLD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 23, 1)
@@ -104,7 +115,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 22, 1)
#define GET_RX_DESC_RX_IPV(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 21, 1)
@@ -112,7 +123,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_CHKERR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 20, 1)
@@ -128,7 +140,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_PAGGR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 15, 1)
@@ -141,7 +154,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RXID_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 14, 1)
@@ -155,14 +169,15 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_AMSDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 13, 1)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_MACID_VLD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 12, 1)
@@ -170,14 +185,15 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_TID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 8, 4)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_MACID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 0, 7)
@@ -194,7 +210,8 @@
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_PPDU_CNT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 29, 2)
@@ -202,26 +219,26 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_C2H(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 28, 1)
#endif
#if (HALMAC_8198F_SUPPORT)
#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)
#define GET_RX_DESC_HWRSVD_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 25, 3)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_HWRSVD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 24, 4)
#endif
#if (HALMAC_8198F_SUPPORT)
#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)
#define GET_RX_DESC_RXMAGPKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 24, 1)
@@ -229,7 +246,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_WLANHD_IV_LEN(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 18, 6)
@@ -241,14 +258,15 @@
#endif
#if (HALMAC_8822C_SUPPORT)
#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RX_STATISTICS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 17, 1)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RX_IS_QOS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 16, 1)
@@ -262,7 +280,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_FRAG(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 12, 4)
#define GET_RX_DESC_SEQ(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 0, 12)
@@ -275,7 +293,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_PATTERN_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 29, 1)
@@ -288,7 +307,7 @@
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) \
LE_BITS_TO_4BYTE(rxdesc + 0x0C, 28, 1)
@@ -298,14 +317,15 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_DMA_AGG_NUM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 16, 8)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_BSSID_FIT_1_0(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 12, 2)
#define GET_RX_DESC_EOSP(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 11, 1)
@@ -320,7 +340,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_HTC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 10, 1)
@@ -335,7 +355,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_BSSID_FIT_4_2(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 7, 3)
@@ -349,14 +370,15 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RX_RATE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 0, 7)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
HALMAC_8812F_SUPPORT)
/*RXDESC_WORD4*/
@@ -383,29 +405,58 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_MACID_RPT_BUFF(rxdesc) \
LE_BITS_TO_4BYTE(rxdesc + 0x10, 17, 7)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) \
LE_BITS_TO_4BYTE(rxdesc + 0x10, 16, 1)
#endif
#if (HALMAC_8192F_SUPPORT)
#define GET_RX_DESC_SWPS_RPT_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 16, 1)
#endif
#if (HALMAC_8814B_SUPPORT)
#define GET_RX_DESC_MACID_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 15, 8)
#endif
#if (HALMAC_8192F_SUPPORT)
#define GET_RX_DESC_FC_POWER_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 15, 1)
#define GET_RX_DESC_TXRPTMID_CTL_MASK_V1(rxdesc) \
LE_BITS_TO_4BYTE(rxdesc + 0x10, 14, 1)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_RX_SCRAMBLER(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 9, 7)
#define GET_RX_DESC_RX_EOF(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 8, 1)
#endif
#if (HALMAC_8192F_SUPPORT)
#define GET_RX_DESC_SNIF_INFO(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 8, 6)
#endif
#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
#define GET_RX_DESC_FC_POWER(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 7, 1)
@@ -426,7 +477,7 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define GET_RX_DESC_PATTERN_IDX(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 8)
@@ -445,7 +496,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
/*RXDESC_WORD5*/

3
hal/halmac/halmac_tx_bd_nic.h
View File

@@ -16,7 +16,8 @@
#ifndef _HALMAC_TX_BD_NIC_H_
#define _HALMAC_TX_BD_NIC_H_
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||\
HALMAC_8812F_SUPPORT)
/*TXBD_DW0*/

484
hal/halmac/halmac_tx_desc_ap.h
View File

@@ -16,7 +16,8 @@
#ifndef _HALMAC_TX_DESC_AP_H_
#define _HALMAC_TX_DESC_AP_H_
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
/*TXDESC_WORD0*/
@@ -47,7 +48,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_GF(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
@@ -76,7 +78,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_NO_ACM(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
@@ -105,7 +108,7 @@
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
@@ -120,7 +123,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
@@ -131,6 +135,13 @@
#define GET_TX_DESC_AMSDU_PAD_EN(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \
27)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_LS(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
value, 0x1, 26)
@@ -140,6 +151,13 @@
#define GET_TX_DESC_LS(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \
26)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_HTC(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
value, 0x1, 25)
@@ -177,7 +195,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_OFFSET(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
@@ -244,8 +262,23 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_KEYID_SEL(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
value, 0x1, 30)
#define SET_TX_DESC_KEYID_SEL_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 30)
#define GET_TX_DESC_KEYID_SEL(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
30)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_MOREDATA(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
@@ -283,7 +316,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_PKT_OFFSET(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
@@ -312,7 +346,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_SEC_TYPE(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
@@ -359,7 +394,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_PIFS(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
@@ -407,7 +443,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_QSEL(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
@@ -435,7 +471,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_MACID(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
@@ -464,7 +501,7 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
/*TXDESC_WORD2*/
@@ -495,7 +532,7 @@
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_FTM_EN(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
@@ -538,7 +575,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_G_ID(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
@@ -581,7 +619,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_BT_NULL(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
@@ -655,7 +694,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_NULL_1(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
@@ -706,7 +746,8 @@
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_TRI_FRAME(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
@@ -720,7 +761,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_P_AID(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
@@ -749,7 +791,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
/*TXDESC_WORD3*/
@@ -807,7 +850,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_NAVUSEHDR(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
@@ -872,7 +916,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_DISDATAFB(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
@@ -932,7 +977,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_WHEADER_LEN(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
@@ -961,7 +1007,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
/*TXDESC_WORD4*/
@@ -1060,7 +1107,7 @@
#endif
#if (HALMAC_8822C_SUPPORT)
#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_ANTSEL_EN_V1(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
@@ -1089,7 +1136,7 @@
#endif
#if (HALMAC_8822C_SUPPORT)
#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
@@ -1103,8 +1150,23 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_TXPWR_OFSET_TYPE_V1(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
value, 0x7, 28)
#define SET_TX_DESC_TXPWR_OFSET_TYPE_V1_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword5, value, 0x7, 28)
#define GET_TX_DESC_TXPWR_OFSET_TYPE_V1(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x7, \
28)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_TX_ANT(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
@@ -1132,8 +1194,23 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_DROP_ID_V1(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
value, 0x3, 22)
#define SET_TX_DESC_DROP_ID_V1_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 22)
#define GET_TX_DESC_DROP_ID_V1(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, \
22)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_PORT_ID(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
@@ -1147,8 +1224,22 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_PORT_ID_V1(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
value, 0x1, 21)
#define SET_TX_DESC_PORT_ID_V1_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 21)
#define GET_TX_DESC_PORT_ID_V1(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \
21)
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_MULTIPLE_PORT(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
@@ -1163,7 +1254,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
@@ -1177,7 +1269,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_RTS_SC(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
@@ -1191,7 +1284,8 @@
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
@@ -1206,7 +1300,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_RTS_SHORT(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
@@ -1270,7 +1365,7 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
/*TXDESC_WORD6*/
@@ -1300,8 +1395,22 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_ANT_MAPC_V2(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
value, 0x3, 30)
#define SET_TX_DESC_ANT_MAPC_V2_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 30)
#define GET_TX_DESC_ANT_MAPC_V2(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
30)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_ANT_MAPD(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
@@ -1329,8 +1438,22 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_ANT_MAPB_V2(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
value, 0x3, 28)
#define SET_TX_DESC_ANT_MAPB_V2_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 28)
#define GET_TX_DESC_ANT_MAPB_V2(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
28)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_ANT_MAPC(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
@@ -1358,8 +1481,22 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_ANT_MAPA_V2(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
value, 0x3, 26)
#define SET_TX_DESC_ANT_MAPA_V2_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 26)
#define GET_TX_DESC_ANT_MAPA_V2(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
26)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_ANT_MAPB(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
@@ -1387,8 +1524,22 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_ANTSEL_D_V1(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
value, 0x3, 24)
#define SET_TX_DESC_ANTSEL_D_V1_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 24)
#define GET_TX_DESC_ANTSEL_D_V1(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
24)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_ANT_MAPA(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
@@ -1399,6 +1550,26 @@
#define GET_TX_DESC_ANT_MAPA(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
22)
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_ANTSEL_C_V2(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
value, 0x3, 22)
#define SET_TX_DESC_ANTSEL_C_V2_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 22)
#define GET_TX_DESC_ANTSEL_C_V2(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
22)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_ANTSEL_C(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
value, 0x3, 20)
@@ -1425,8 +1596,22 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_ANTSEL_B_V2(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
value, 0x7, 19)
#define SET_TX_DESC_ANTSEL_B_V2_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword6, value, 0x7, 19)
#define GET_TX_DESC_ANTSEL_B_V2(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x7, \
19)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_ANTSEL_B(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
@@ -1463,8 +1648,23 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_ANTSEL_A_V2(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
value, 0x7, 16)
#define SET_TX_DESC_ANTSEL_A_V2_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword6, value, 0x7, 16)
#define GET_TX_DESC_ANTSEL_A_V2(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x7, \
16)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_MBSSID(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
@@ -1479,7 +1679,7 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_SW_DEFINE(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
@@ -1493,7 +1693,7 @@
#endif
#if (HALMAC_8198F_SUPPORT)
#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_SWPS_SEQ(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
@@ -1508,7 +1708,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
/*TXDESC_WORD7*/
@@ -1521,6 +1722,13 @@
#define GET_TX_DESC_DMA_TXAGG_NUM(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xff, \
24)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
value, 0xff, 24)
@@ -1530,6 +1738,36 @@
#define GET_TX_DESC_FINAL_DATA_RATE(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xff, \
24)
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_ANT_MAPD_V2(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
value, 0x3, 22)
#define SET_TX_DESC_ANT_MAPD_V2_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword7, value, 0x3, 22)
#define GET_TX_DESC_ANT_MAPD_V2(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x3, \
22)
#define SET_TX_DESC_ANTSEL_EN_V2(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
value, 0x1, 21)
#define SET_TX_DESC_ANTSEL_EN_V2_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1, 21)
#define GET_TX_DESC_ANTSEL_EN_V2(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1, \
21)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_NTX_MAP(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
value, 0xf, 20)
@@ -1565,8 +1803,23 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_MBSSID_EX_V1(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
value, 0x1, 16)
#define SET_TX_DESC_MBSSID_EX_V1_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1, 16)
#define GET_TX_DESC_MBSSID_EX_V1(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1, \
16)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
@@ -1596,6 +1849,12 @@
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, \
0xffff, 0)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
/*TXDESC_WORD8*/
#define SET_TX_DESC_TXWIFI_CP(txdesc, value) \
@@ -1670,6 +1929,13 @@
#define GET_TX_DESC_SMH_EN(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \
24)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_TAILPAGE_L(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
value, 0xff, 24)
@@ -1697,6 +1963,13 @@
#define GET_TX_DESC_NEXTHEADPAGE_L(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xff, \
16)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_EN_HWSEQ(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
value, 0x1, 15)
@@ -1706,6 +1979,12 @@
#define GET_TX_DESC_EN_HWSEQ(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \
15)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
#define SET_TX_DESC_EN_HWEXSEQ(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
value, 0x1, 14)
@@ -1715,6 +1994,27 @@
#define GET_TX_DESC_EN_HWEXSEQ(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \
14)
#endif
#if (HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_EN_HWSEQ_MODE(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
value, 0x3, 14)
#define SET_TX_DESC_EN_HWSEQ_MODE_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 14)
#define GET_TX_DESC_EN_HWSEQ_MODE(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, \
14)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_DATA_RC(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
value, 0x3f, 8)
@@ -1742,6 +2042,12 @@
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3f, \
0)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
/*TXDESC_WORD9*/
#define SET_TX_DESC_TAILPAGE_H(txdesc, value) \
@@ -1762,6 +2068,27 @@
#define GET_TX_DESC_NEXTHEADPAGE_H(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xf, \
24)
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_FINAL_DATA_RATE_V1(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
value, 0xff, 24)
#define SET_TX_DESC_FINAL_DATA_RATE_V1_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword9, value, 0xff, 24)
#define GET_TX_DESC_FINAL_DATA_RATE_V1(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xff, \
24)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_SW_SEQ(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
value, 0xfff, 12)
@@ -1771,6 +2098,13 @@
#define GET_TX_DESC_SW_SEQ(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, \
0xfff, 12)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_TXBF_PATH(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
value, 0x1, 11)
@@ -1780,6 +2114,13 @@
#define GET_TX_DESC_TXBF_PATH(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, \
11)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_PADDING_LEN(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
value, 0x7ff, 0)
@@ -1801,10 +2142,34 @@
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
#if (HALMAC_8812F_SUPPORT)
/*WORD10*/
#define SET_TX_DESC_HT_DATA_SND(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
value, 0x1, 31)
#define SET_TX_DESC_HT_DATA_SND_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 31)
#define GET_TX_DESC_HT_DATA_SND(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
31)
#define SET_TX_DESC_SHCUT_CAM(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
value, 0x3f, 16)
#define SET_TX_DESC_SHCUT_CAM_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword10, value, 0x3f, 16)
#define GET_TX_DESC_SHCUT_CAM(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, \
0x3f, 16)
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_MU_DATARATE(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
value, 0xff, 8)
@@ -1823,6 +2188,35 @@
#define GET_TX_DESC_MU_RC(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0xf, \
4)
#endif
#if (HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_NDPA_RATE_SEL(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
value, 0x1, 3)
#define SET_TX_DESC_NDPA_RATE_SEL_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 3)
#define GET_TX_DESC_NDPA_RATE_SEL(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
3)
#define SET_TX_DESC_HW_NDPA_EN(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
value, 0x1, 2)
#define SET_TX_DESC_HW_NDPA_EN_NO_CLR(txdesc, value) \
HALMAC_SET_DESC_FIELD_NO_CLR( \
((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 2)
#define GET_TX_DESC_HW_NDPA_EN(txdesc) \
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
2)
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_SND_PKT_SEL(txdesc, value) \
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
value, 0x3, 0)

723
hal/halmac/halmac_tx_desc_chip.h
View File

@@ -2382,4 +2382,727 @@
#endif
#if (HALMAC_8192F_SUPPORT)
/*TXDESC_WORD0*/
#define SET_TX_DESC_GF_8192F(txdesc, value) SET_TX_DESC_GF(txdesc, value)
#define GET_TX_DESC_GF_8192F(txdesc) GET_TX_DESC_GF(txdesc)
#define SET_TX_DESC_NO_ACM_8192F(txdesc, value) \
SET_TX_DESC_NO_ACM(txdesc, value)
#define GET_TX_DESC_NO_ACM_8192F(txdesc) GET_TX_DESC_NO_ACM(txdesc)
#define SET_TX_DESC_AMSDU_PAD_EN_8192F(txdesc, value) \
SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)
#define GET_TX_DESC_AMSDU_PAD_EN_8192F(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)
#define SET_TX_DESC_HTC_8192F(txdesc, value) SET_TX_DESC_HTC(txdesc, value)
#define GET_TX_DESC_HTC_8192F(txdesc) GET_TX_DESC_HTC(txdesc)
#define SET_TX_DESC_BMC_8192F(txdesc, value) SET_TX_DESC_BMC(txdesc, value)
#define GET_TX_DESC_BMC_8192F(txdesc) GET_TX_DESC_BMC(txdesc)
#define SET_TX_DESC_OFFSET_8192F(txdesc, value) \
SET_TX_DESC_OFFSET(txdesc, value)
#define GET_TX_DESC_OFFSET_8192F(txdesc) GET_TX_DESC_OFFSET(txdesc)
#define SET_TX_DESC_TXPKTSIZE_8192F(txdesc, value) \
SET_TX_DESC_TXPKTSIZE(txdesc, value)
#define GET_TX_DESC_TXPKTSIZE_8192F(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
/*WORD1*/
#define SET_TX_DESC_KEYID_SEL_8192F(txdesc, value) \
SET_TX_DESC_KEYID_SEL(txdesc, value)
#define GET_TX_DESC_KEYID_SEL_8192F(txdesc) GET_TX_DESC_KEYID_SEL(txdesc)
#define SET_TX_DESC_MOREDATA_8192F(txdesc, value) \
SET_TX_DESC_MOREDATA(txdesc, value)
#define GET_TX_DESC_MOREDATA_8192F(txdesc) GET_TX_DESC_MOREDATA(txdesc)
#define SET_TX_DESC_PKT_OFFSET_8192F(txdesc, value) \
SET_TX_DESC_PKT_OFFSET(txdesc, value)
#define GET_TX_DESC_PKT_OFFSET_8192F(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)
#define SET_TX_DESC_SEC_TYPE_8192F(txdesc, value) \
SET_TX_DESC_SEC_TYPE(txdesc, value)
#define GET_TX_DESC_SEC_TYPE_8192F(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)
#define SET_TX_DESC_EN_DESC_ID_8192F(txdesc, value) \
SET_TX_DESC_EN_DESC_ID(txdesc, value)
#define GET_TX_DESC_EN_DESC_ID_8192F(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)
#define SET_TX_DESC_RATE_ID_8192F(txdesc, value) \
SET_TX_DESC_RATE_ID(txdesc, value)
#define GET_TX_DESC_RATE_ID_8192F(txdesc) GET_TX_DESC_RATE_ID(txdesc)
#define SET_TX_DESC_PIFS_8192F(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)
#define GET_TX_DESC_PIFS_8192F(txdesc) GET_TX_DESC_PIFS(txdesc)
#define SET_TX_DESC_LSIG_TXOP_EN_8192F(txdesc, value) \
SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)
#define GET_TX_DESC_LSIG_TXOP_EN_8192F(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)
#define SET_TX_DESC_RD_NAV_EXT_8192F(txdesc, value) \
SET_TX_DESC_RD_NAV_EXT(txdesc, value)
#define GET_TX_DESC_RD_NAV_EXT_8192F(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)
#define SET_TX_DESC_QSEL_8192F(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
#define GET_TX_DESC_QSEL_8192F(txdesc) GET_TX_DESC_QSEL(txdesc)
#define SET_TX_DESC_MACID_8192F(txdesc, value) SET_TX_DESC_MACID(txdesc, value)
#define GET_TX_DESC_MACID_8192F(txdesc) GET_TX_DESC_MACID(txdesc)
/*TXDESC_WORD2*/
#define SET_TX_DESC_FTM_EN_8192F(txdesc, value) \
SET_TX_DESC_FTM_EN(txdesc, value)
#define GET_TX_DESC_FTM_EN_8192F(txdesc) GET_TX_DESC_FTM_EN(txdesc)
#define SET_TX_DESC_G_ID_8192F(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)
#define GET_TX_DESC_G_ID_8192F(txdesc) GET_TX_DESC_G_ID(txdesc)
#define SET_TX_DESC_BT_NULL_8192F(txdesc, value) \
SET_TX_DESC_BT_NULL(txdesc, value)
#define GET_TX_DESC_BT_NULL_8192F(txdesc) GET_TX_DESC_BT_NULL(txdesc)
#define SET_TX_DESC_AMPDU_DENSITY_8192F(txdesc, value) \
SET_TX_DESC_AMPDU_DENSITY(txdesc, value)
#define GET_TX_DESC_AMPDU_DENSITY_8192F(txdesc) \
GET_TX_DESC_AMPDU_DENSITY(txdesc)
#define SET_TX_DESC_SPE_RPT_8192F(txdesc, value) \
SET_TX_DESC_SPE_RPT(txdesc, value)
#define GET_TX_DESC_SPE_RPT_8192F(txdesc) GET_TX_DESC_SPE_RPT(txdesc)
#define SET_TX_DESC_RAW_8192F(txdesc, value) SET_TX_DESC_RAW(txdesc, value)
#define GET_TX_DESC_RAW_8192F(txdesc) GET_TX_DESC_RAW(txdesc)
#define SET_TX_DESC_MOREFRAG_8192F(txdesc, value) \
SET_TX_DESC_MOREFRAG(txdesc, value)
#define GET_TX_DESC_MOREFRAG_8192F(txdesc) GET_TX_DESC_MOREFRAG(txdesc)
#define SET_TX_DESC_BK_8192F(txdesc, value) SET_TX_DESC_BK(txdesc, value)
#define GET_TX_DESC_BK_8192F(txdesc) GET_TX_DESC_BK(txdesc)
#define SET_TX_DESC_NULL_1_8192F(txdesc, value) \
SET_TX_DESC_NULL_1(txdesc, value)
#define GET_TX_DESC_NULL_1_8192F(txdesc) GET_TX_DESC_NULL_1(txdesc)
#define SET_TX_DESC_NULL_0_8192F(txdesc, value) \
SET_TX_DESC_NULL_0(txdesc, value)
#define GET_TX_DESC_NULL_0_8192F(txdesc) GET_TX_DESC_NULL_0(txdesc)
#define SET_TX_DESC_RDG_EN_8192F(txdesc, value) \
SET_TX_DESC_RDG_EN(txdesc, value)
#define GET_TX_DESC_RDG_EN_8192F(txdesc) GET_TX_DESC_RDG_EN(txdesc)
#define SET_TX_DESC_AGG_EN_8192F(txdesc, value) \
SET_TX_DESC_AGG_EN(txdesc, value)
#define GET_TX_DESC_AGG_EN_8192F(txdesc) GET_TX_DESC_AGG_EN(txdesc)
#define SET_TX_DESC_CCA_RTS_8192F(txdesc, value) \
SET_TX_DESC_CCA_RTS(txdesc, value)
#define GET_TX_DESC_CCA_RTS_8192F(txdesc) GET_TX_DESC_CCA_RTS(txdesc)
#define SET_TX_DESC_TRI_FRAME_8192F(txdesc, value) \
SET_TX_DESC_TRI_FRAME(txdesc, value)
#define GET_TX_DESC_TRI_FRAME_8192F(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)
#define SET_TX_DESC_P_AID_8192F(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)
#define GET_TX_DESC_P_AID_8192F(txdesc) GET_TX_DESC_P_AID(txdesc)
/*TXDESC_WORD3*/
#define SET_TX_DESC_AMPDU_MAX_TIME_8192F(txdesc, value) \
SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)
#define GET_TX_DESC_AMPDU_MAX_TIME_8192F(txdesc) \
GET_TX_DESC_AMPDU_MAX_TIME(txdesc)
#define SET_TX_DESC_NDPA_8192F(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)
#define GET_TX_DESC_NDPA_8192F(txdesc) GET_TX_DESC_NDPA(txdesc)
#define SET_TX_DESC_MAX_AGG_NUM_8192F(txdesc, value) \
SET_TX_DESC_MAX_AGG_NUM(txdesc, value)
#define GET_TX_DESC_MAX_AGG_NUM_8192F(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)
#define SET_TX_DESC_USE_MAX_TIME_EN_8192F(txdesc, value) \
SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)
#define GET_TX_DESC_USE_MAX_TIME_EN_8192F(txdesc) \
GET_TX_DESC_USE_MAX_TIME_EN(txdesc)
#define SET_TX_DESC_NAVUSEHDR_8192F(txdesc, value) \
SET_TX_DESC_NAVUSEHDR(txdesc, value)
#define GET_TX_DESC_NAVUSEHDR_8192F(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)
#define SET_TX_DESC_CHK_EN_8192F(txdesc, value) \
SET_TX_DESC_CHK_EN(txdesc, value)
#define GET_TX_DESC_CHK_EN_8192F(txdesc) GET_TX_DESC_CHK_EN(txdesc)
#define SET_TX_DESC_HW_RTS_EN_8192F(txdesc, value) \
SET_TX_DESC_HW_RTS_EN(txdesc, value)
#define GET_TX_DESC_HW_RTS_EN_8192F(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)
#define SET_TX_DESC_RTSEN_8192F(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)
#define GET_TX_DESC_RTSEN_8192F(txdesc) GET_TX_DESC_RTSEN(txdesc)
#define SET_TX_DESC_CTS2SELF_8192F(txdesc, value) \
SET_TX_DESC_CTS2SELF(txdesc, value)
#define GET_TX_DESC_CTS2SELF_8192F(txdesc) GET_TX_DESC_CTS2SELF(txdesc)
#define SET_TX_DESC_DISDATAFB_8192F(txdesc, value) \
SET_TX_DESC_DISDATAFB(txdesc, value)
#define GET_TX_DESC_DISDATAFB_8192F(txdesc) GET_TX_DESC_DISDATAFB(txdesc)
#define SET_TX_DESC_DISRTSFB_8192F(txdesc, value) \
SET_TX_DESC_DISRTSFB(txdesc, value)
#define GET_TX_DESC_DISRTSFB_8192F(txdesc) GET_TX_DESC_DISRTSFB(txdesc)
#define SET_TX_DESC_USE_RATE_8192F(txdesc, value) \
SET_TX_DESC_USE_RATE(txdesc, value)
#define GET_TX_DESC_USE_RATE_8192F(txdesc) GET_TX_DESC_USE_RATE(txdesc)
#define SET_TX_DESC_HW_SSN_SEL_8192F(txdesc, value) \
SET_TX_DESC_HW_SSN_SEL(txdesc, value)
#define GET_TX_DESC_HW_SSN_SEL_8192F(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)
#define SET_TX_DESC_WHEADER_LEN_8192F(txdesc, value) \
SET_TX_DESC_WHEADER_LEN(txdesc, value)
#define GET_TX_DESC_WHEADER_LEN_8192F(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)
/*TXDESC_WORD4*/
#define SET_TX_DESC_PCTS_MASK_IDX_8192F(txdesc, value) \
SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)
#define GET_TX_DESC_PCTS_MASK_IDX_8192F(txdesc) \
GET_TX_DESC_PCTS_MASK_IDX(txdesc)
#define SET_TX_DESC_PCTS_EN_8192F(txdesc, value) \
SET_TX_DESC_PCTS_EN(txdesc, value)
#define GET_TX_DESC_PCTS_EN_8192F(txdesc) GET_TX_DESC_PCTS_EN(txdesc)
#define SET_TX_DESC_RTSRATE_8192F(txdesc, value) \
SET_TX_DESC_RTSRATE(txdesc, value)
#define GET_TX_DESC_RTSRATE_8192F(txdesc) GET_TX_DESC_RTSRATE(txdesc)
#define SET_TX_DESC_RTS_DATA_RTY_LMT_8192F(txdesc, value) \
SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)
#define GET_TX_DESC_RTS_DATA_RTY_LMT_8192F(txdesc) \
GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)
#define SET_TX_DESC_RTY_LMT_EN_8192F(txdesc, value) \
SET_TX_DESC_RTY_LMT_EN(txdesc, value)
#define GET_TX_DESC_RTY_LMT_EN_8192F(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)
#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8192F(txdesc, value) \
SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)
#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8192F(txdesc) \
GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)
#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8192F(txdesc, value) \
SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)
#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8192F(txdesc) \
GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)
#define SET_TX_DESC_TRY_RATE_8192F(txdesc, value) \
SET_TX_DESC_TRY_RATE(txdesc, value)
#define GET_TX_DESC_TRY_RATE_8192F(txdesc) GET_TX_DESC_TRY_RATE(txdesc)
#define SET_TX_DESC_DATARATE_8192F(txdesc, value) \
SET_TX_DESC_DATARATE(txdesc, value)
#define GET_TX_DESC_DATARATE_8192F(txdesc) GET_TX_DESC_DATARATE(txdesc)
/*TXDESC_WORD5*/
#define SET_TX_DESC_POLLUTED_8192F(txdesc, value) \
SET_TX_DESC_POLLUTED(txdesc, value)
#define GET_TX_DESC_POLLUTED_8192F(txdesc) GET_TX_DESC_POLLUTED(txdesc)
#define SET_TX_DESC_TXPWR_OFSET_TYPE_8192F(txdesc, value) \
SET_TX_DESC_TXPWR_OFSET_TYPE_V1(txdesc, value)
#define GET_TX_DESC_TXPWR_OFSET_TYPE_8192F(txdesc) \
GET_TX_DESC_TXPWR_OFSET_TYPE_V1(txdesc)
#define SET_TX_DESC_TX_ANT_8192F(txdesc, value) \
SET_TX_DESC_TX_ANT(txdesc, value)
#define GET_TX_DESC_TX_ANT_8192F(txdesc) GET_TX_DESC_TX_ANT(txdesc)
#define SET_TX_DESC_DROP_ID_8192F(txdesc, value) \
SET_TX_DESC_DROP_ID_V1(txdesc, value)
#define GET_TX_DESC_DROP_ID_8192F(txdesc) GET_TX_DESC_DROP_ID_V1(txdesc)
#define SET_TX_DESC_PORT_ID_8192F(txdesc, value) \
SET_TX_DESC_PORT_ID_V1(txdesc, value)
#define GET_TX_DESC_PORT_ID_8192F(txdesc) GET_TX_DESC_PORT_ID_V1(txdesc)
#define SET_TX_DESC_RTS_SC_8192F(txdesc, value) \
SET_TX_DESC_RTS_SC(txdesc, value)
#define GET_TX_DESC_RTS_SC_8192F(txdesc) GET_TX_DESC_RTS_SC(txdesc)
#define SET_TX_DESC_RTS_SHORT_8192F(txdesc, value) \
SET_TX_DESC_RTS_SHORT(txdesc, value)
#define GET_TX_DESC_RTS_SHORT_8192F(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)
#define SET_TX_DESC_VCS_STBC_8192F(txdesc, value) \
SET_TX_DESC_VCS_STBC(txdesc, value)
#define GET_TX_DESC_VCS_STBC_8192F(txdesc) GET_TX_DESC_VCS_STBC(txdesc)
#define SET_TX_DESC_DATA_STBC_8192F(txdesc, value) \
SET_TX_DESC_DATA_STBC(txdesc, value)
#define GET_TX_DESC_DATA_STBC_8192F(txdesc) GET_TX_DESC_DATA_STBC(txdesc)
#define SET_TX_DESC_DATA_LDPC_8192F(txdesc, value) \
SET_TX_DESC_DATA_LDPC(txdesc, value)
#define GET_TX_DESC_DATA_LDPC_8192F(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)
#define SET_TX_DESC_DATA_BW_8192F(txdesc, value) \
SET_TX_DESC_DATA_BW(txdesc, value)
#define GET_TX_DESC_DATA_BW_8192F(txdesc) GET_TX_DESC_DATA_BW(txdesc)
#define SET_TX_DESC_DATA_SHORT_8192F(txdesc, value) \
SET_TX_DESC_DATA_SHORT(txdesc, value)
#define GET_TX_DESC_DATA_SHORT_8192F(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)
#define SET_TX_DESC_DATA_SC_8192F(txdesc, value) \
SET_TX_DESC_DATA_SC(txdesc, value)
#define GET_TX_DESC_DATA_SC_8192F(txdesc) GET_TX_DESC_DATA_SC(txdesc)
/*TXDESC_WORD6*/
#define SET_TX_DESC_ANT_MAPC_8192F(txdesc, value) \
SET_TX_DESC_ANT_MAPC_V2(txdesc, value)
#define GET_TX_DESC_ANT_MAPC_8192F(txdesc) GET_TX_DESC_ANT_MAPC_V2(txdesc)
#define SET_TX_DESC_ANT_MAPB_8192F(txdesc, value) \
SET_TX_DESC_ANT_MAPB_V2(txdesc, value)
#define GET_TX_DESC_ANT_MAPB_8192F(txdesc) GET_TX_DESC_ANT_MAPB_V2(txdesc)
#define SET_TX_DESC_ANT_MAPA_8192F(txdesc, value) \
SET_TX_DESC_ANT_MAPA_V2(txdesc, value)
#define GET_TX_DESC_ANT_MAPA_8192F(txdesc) GET_TX_DESC_ANT_MAPA_V2(txdesc)
#define SET_TX_DESC_ANTSEL_D_8192F(txdesc, value) \
SET_TX_DESC_ANTSEL_D_V1(txdesc, value)
#define GET_TX_DESC_ANTSEL_D_8192F(txdesc) GET_TX_DESC_ANTSEL_D_V1(txdesc)
#define SET_TX_DESC_ANTSEL_C_8192F(txdesc, value) \
SET_TX_DESC_ANTSEL_C_V2(txdesc, value)
#define GET_TX_DESC_ANTSEL_C_8192F(txdesc) GET_TX_DESC_ANTSEL_C_V2(txdesc)
#define SET_TX_DESC_ANTSEL_B_8192F(txdesc, value) \
SET_TX_DESC_ANTSEL_B_V2(txdesc, value)
#define GET_TX_DESC_ANTSEL_B_8192F(txdesc) GET_TX_DESC_ANTSEL_B_V2(txdesc)
#define SET_TX_DESC_ANTSEL_A_8192F(txdesc, value) \
SET_TX_DESC_ANTSEL_A_V2(txdesc, value)
#define GET_TX_DESC_ANTSEL_A_8192F(txdesc) GET_TX_DESC_ANTSEL_A_V2(txdesc)
#define SET_TX_DESC_MBSSID_8192F(txdesc, value) \
SET_TX_DESC_MBSSID(txdesc, value)
#define GET_TX_DESC_MBSSID_8192F(txdesc) GET_TX_DESC_MBSSID(txdesc)
#define SET_TX_DESC_SWPS_SEQ_8192F(txdesc, value) \
SET_TX_DESC_SWPS_SEQ(txdesc, value)
#define GET_TX_DESC_SWPS_SEQ_8192F(txdesc) GET_TX_DESC_SWPS_SEQ(txdesc)
/*TXDESC_WORD7*/
#define SET_TX_DESC_DMA_TXAGG_NUM_8192F(txdesc, value) \
SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)
#define GET_TX_DESC_DMA_TXAGG_NUM_8192F(txdesc) \
GET_TX_DESC_DMA_TXAGG_NUM(txdesc)
#define SET_TX_DESC_ANT_MAPD_8192F(txdesc, value) \
SET_TX_DESC_ANT_MAPD_V2(txdesc, value)
#define GET_TX_DESC_ANT_MAPD_8192F(txdesc) GET_TX_DESC_ANT_MAPD_V2(txdesc)
#define SET_TX_DESC_ANTSEL_EN_8192F(txdesc, value) \
SET_TX_DESC_ANTSEL_EN_V2(txdesc, value)
#define GET_TX_DESC_ANTSEL_EN_8192F(txdesc) GET_TX_DESC_ANTSEL_EN_V2(txdesc)
#define SET_TX_DESC_MBSSID_EX_8192F(txdesc, value) \
SET_TX_DESC_MBSSID_EX_V1(txdesc, value)
#define GET_TX_DESC_MBSSID_EX_8192F(txdesc) GET_TX_DESC_MBSSID_EX_V1(txdesc)
#define SET_TX_DESC_TX_BUFF_SIZE_8192F(txdesc, value) \
SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)
#define GET_TX_DESC_TX_BUFF_SIZE_8192F(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)
#define SET_TX_DESC_TXDESC_CHECKSUM_8192F(txdesc, value) \
SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)
#define GET_TX_DESC_TXDESC_CHECKSUM_8192F(txdesc) \
GET_TX_DESC_TXDESC_CHECKSUM(txdesc)
#define SET_TX_DESC_TIMESTAMP_8192F(txdesc, value) \
SET_TX_DESC_TIMESTAMP(txdesc, value)
#define GET_TX_DESC_TIMESTAMP_8192F(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)
/*TXDESC_WORD8*/
#define SET_TX_DESC_TAILPAGE_L_8192F(txdesc, value) \
SET_TX_DESC_TAILPAGE_L(txdesc, value)
#define GET_TX_DESC_TAILPAGE_L_8192F(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)
#define SET_TX_DESC_SDIO_DMASEQ_8192F(txdesc, value) \
SET_TX_DESC_SDIO_DMASEQ(txdesc, value)
#define GET_TX_DESC_SDIO_DMASEQ_8192F(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)
#define SET_TX_DESC_NEXTHEADPAGE_L_8192F(txdesc, value) \
SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)
#define GET_TX_DESC_NEXTHEADPAGE_L_8192F(txdesc) \
GET_TX_DESC_NEXTHEADPAGE_L(txdesc)
#define SET_TX_DESC_EN_HWSEQ_8192F(txdesc, value) \
SET_TX_DESC_EN_HWSEQ(txdesc, value)
#define GET_TX_DESC_EN_HWSEQ_8192F(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)
#define SET_TX_DESC_DATA_RC_8192F(txdesc, value) \
SET_TX_DESC_DATA_RC(txdesc, value)
#define GET_TX_DESC_DATA_RC_8192F(txdesc) GET_TX_DESC_DATA_RC(txdesc)
#define SET_TX_DESC_BAR_RTY_TH_8192F(txdesc, value) \
SET_TX_DESC_BAR_RTY_TH(txdesc, value)
#define GET_TX_DESC_BAR_RTY_TH_8192F(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)
#define SET_TX_DESC_RTS_RC_8192F(txdesc, value) \
SET_TX_DESC_RTS_RC(txdesc, value)
#define GET_TX_DESC_RTS_RC_8192F(txdesc) GET_TX_DESC_RTS_RC(txdesc)
/*TXDESC_WORD9*/
#define SET_TX_DESC_FINAL_DATA_RATE_8192F(txdesc, value) \
SET_TX_DESC_FINAL_DATA_RATE_V1(txdesc, value)
#define GET_TX_DESC_FINAL_DATA_RATE_8192F(txdesc) \
GET_TX_DESC_FINAL_DATA_RATE_V1(txdesc)
#define SET_TX_DESC_SW_SEQ_8192F(txdesc, value) \
SET_TX_DESC_SW_SEQ(txdesc, value)
#define GET_TX_DESC_SW_SEQ_8192F(txdesc) GET_TX_DESC_SW_SEQ(txdesc)
#define SET_TX_DESC_PADDING_LEN_8192F(txdesc, value) \
SET_TX_DESC_PADDING_LEN(txdesc, value)
#define GET_TX_DESC_PADDING_LEN_8192F(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)
#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8192F(txdesc, value) \
SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)
#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8192F(txdesc) \
GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)
/*WORD10*/
#endif
#if (HALMAC_8812F_SUPPORT)
/*TXDESC_WORD0*/
#define SET_TX_DESC_DISQSELSEQ_8812F(txdesc, value) \
SET_TX_DESC_DISQSELSEQ(txdesc, value)
#define GET_TX_DESC_DISQSELSEQ_8812F(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)
#define SET_TX_DESC_GF_8812F(txdesc, value) SET_TX_DESC_GF(txdesc, value)
#define GET_TX_DESC_GF_8812F(txdesc) GET_TX_DESC_GF(txdesc)
#define SET_TX_DESC_NO_ACM_8812F(txdesc, value) \
SET_TX_DESC_NO_ACM(txdesc, value)
#define GET_TX_DESC_NO_ACM_8812F(txdesc) GET_TX_DESC_NO_ACM(txdesc)
#define SET_TX_DESC_BCNPKT_TSF_CTRL_8812F(txdesc, value) \
SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)
#define GET_TX_DESC_BCNPKT_TSF_CTRL_8812F(txdesc) \
GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)
#define SET_TX_DESC_AMSDU_PAD_EN_8812F(txdesc, value) \
SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)
#define GET_TX_DESC_AMSDU_PAD_EN_8812F(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)
#define SET_TX_DESC_LS_8812F(txdesc, value) SET_TX_DESC_LS(txdesc, value)
#define GET_TX_DESC_LS_8812F(txdesc) GET_TX_DESC_LS(txdesc)
#define SET_TX_DESC_HTC_8812F(txdesc, value) SET_TX_DESC_HTC(txdesc, value)
#define GET_TX_DESC_HTC_8812F(txdesc) GET_TX_DESC_HTC(txdesc)
#define SET_TX_DESC_BMC_8812F(txdesc, value) SET_TX_DESC_BMC(txdesc, value)
#define GET_TX_DESC_BMC_8812F(txdesc) GET_TX_DESC_BMC(txdesc)
#define SET_TX_DESC_OFFSET_8812F(txdesc, value) \
SET_TX_DESC_OFFSET(txdesc, value)
#define GET_TX_DESC_OFFSET_8812F(txdesc) GET_TX_DESC_OFFSET(txdesc)
#define SET_TX_DESC_TXPKTSIZE_8812F(txdesc, value) \
SET_TX_DESC_TXPKTSIZE(txdesc, value)
#define GET_TX_DESC_TXPKTSIZE_8812F(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
/*WORD1*/
#define SET_TX_DESC_MOREDATA_8812F(txdesc, value) \
SET_TX_DESC_MOREDATA(txdesc, value)
#define GET_TX_DESC_MOREDATA_8812F(txdesc) GET_TX_DESC_MOREDATA(txdesc)
#define SET_TX_DESC_PKT_OFFSET_8812F(txdesc, value) \
SET_TX_DESC_PKT_OFFSET(txdesc, value)
#define GET_TX_DESC_PKT_OFFSET_8812F(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)
#define SET_TX_DESC_SEC_TYPE_8812F(txdesc, value) \
SET_TX_DESC_SEC_TYPE(txdesc, value)
#define GET_TX_DESC_SEC_TYPE_8812F(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)
#define SET_TX_DESC_EN_DESC_ID_8812F(txdesc, value) \
SET_TX_DESC_EN_DESC_ID(txdesc, value)
#define GET_TX_DESC_EN_DESC_ID_8812F(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)
#define SET_TX_DESC_RATE_ID_8812F(txdesc, value) \
SET_TX_DESC_RATE_ID(txdesc, value)
#define GET_TX_DESC_RATE_ID_8812F(txdesc) GET_TX_DESC_RATE_ID(txdesc)
#define SET_TX_DESC_PIFS_8812F(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)
#define GET_TX_DESC_PIFS_8812F(txdesc) GET_TX_DESC_PIFS(txdesc)
#define SET_TX_DESC_LSIG_TXOP_EN_8812F(txdesc, value) \
SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)
#define GET_TX_DESC_LSIG_TXOP_EN_8812F(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)
#define SET_TX_DESC_RD_NAV_EXT_8812F(txdesc, value) \
SET_TX_DESC_RD_NAV_EXT(txdesc, value)
#define GET_TX_DESC_RD_NAV_EXT_8812F(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)
#define SET_TX_DESC_QSEL_8812F(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
#define GET_TX_DESC_QSEL_8812F(txdesc) GET_TX_DESC_QSEL(txdesc)
#define SET_TX_DESC_MACID_8812F(txdesc, value) SET_TX_DESC_MACID(txdesc, value)
#define GET_TX_DESC_MACID_8812F(txdesc) GET_TX_DESC_MACID(txdesc)
/*TXDESC_WORD2*/
#define SET_TX_DESC_HW_AES_IV_8812F(txdesc, value) \
SET_TX_DESC_HW_AES_IV(txdesc, value)
#define GET_TX_DESC_HW_AES_IV_8812F(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)
#define SET_TX_DESC_FTM_EN_8812F(txdesc, value) \
SET_TX_DESC_FTM_EN(txdesc, value)
#define GET_TX_DESC_FTM_EN_8812F(txdesc) GET_TX_DESC_FTM_EN(txdesc)
#define SET_TX_DESC_G_ID_8812F(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)
#define GET_TX_DESC_G_ID_8812F(txdesc) GET_TX_DESC_G_ID(txdesc)
#define SET_TX_DESC_BT_NULL_8812F(txdesc, value) \
SET_TX_DESC_BT_NULL(txdesc, value)
#define GET_TX_DESC_BT_NULL_8812F(txdesc) GET_TX_DESC_BT_NULL(txdesc)
#define SET_TX_DESC_AMPDU_DENSITY_8812F(txdesc, value) \
SET_TX_DESC_AMPDU_DENSITY(txdesc, value)
#define GET_TX_DESC_AMPDU_DENSITY_8812F(txdesc) \
GET_TX_DESC_AMPDU_DENSITY(txdesc)
#define SET_TX_DESC_SPE_RPT_8812F(txdesc, value) \
SET_TX_DESC_SPE_RPT(txdesc, value)
#define GET_TX_DESC_SPE_RPT_8812F(txdesc) GET_TX_DESC_SPE_RPT(txdesc)
#define SET_TX_DESC_RAW_8812F(txdesc, value) SET_TX_DESC_RAW(txdesc, value)
#define GET_TX_DESC_RAW_8812F(txdesc) GET_TX_DESC_RAW(txdesc)
#define SET_TX_DESC_MOREFRAG_8812F(txdesc, value) \
SET_TX_DESC_MOREFRAG(txdesc, value)
#define GET_TX_DESC_MOREFRAG_8812F(txdesc) GET_TX_DESC_MOREFRAG(txdesc)
#define SET_TX_DESC_BK_8812F(txdesc, value) SET_TX_DESC_BK(txdesc, value)
#define GET_TX_DESC_BK_8812F(txdesc) GET_TX_DESC_BK(txdesc)
#define SET_TX_DESC_NULL_1_8812F(txdesc, value) \
SET_TX_DESC_NULL_1(txdesc, value)
#define GET_TX_DESC_NULL_1_8812F(txdesc) GET_TX_DESC_NULL_1(txdesc)
#define SET_TX_DESC_NULL_0_8812F(txdesc, value) \
SET_TX_DESC_NULL_0(txdesc, value)
#define GET_TX_DESC_NULL_0_8812F(txdesc) GET_TX_DESC_NULL_0(txdesc)
#define SET_TX_DESC_RDG_EN_8812F(txdesc, value) \
SET_TX_DESC_RDG_EN(txdesc, value)
#define GET_TX_DESC_RDG_EN_8812F(txdesc) GET_TX_DESC_RDG_EN(txdesc)
#define SET_TX_DESC_AGG_EN_8812F(txdesc, value) \
SET_TX_DESC_AGG_EN(txdesc, value)
#define GET_TX_DESC_AGG_EN_8812F(txdesc) GET_TX_DESC_AGG_EN(txdesc)
#define SET_TX_DESC_CCA_RTS_8812F(txdesc, value) \
SET_TX_DESC_CCA_RTS(txdesc, value)
#define GET_TX_DESC_CCA_RTS_8812F(txdesc) GET_TX_DESC_CCA_RTS(txdesc)
#define SET_TX_DESC_TRI_FRAME_8812F(txdesc, value) \
SET_TX_DESC_TRI_FRAME(txdesc, value)
#define GET_TX_DESC_TRI_FRAME_8812F(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)
#define SET_TX_DESC_P_AID_8812F(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)
#define GET_TX_DESC_P_AID_8812F(txdesc) GET_TX_DESC_P_AID(txdesc)
/*TXDESC_WORD3*/
#define SET_TX_DESC_AMPDU_MAX_TIME_8812F(txdesc, value) \
SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)
#define GET_TX_DESC_AMPDU_MAX_TIME_8812F(txdesc) \
GET_TX_DESC_AMPDU_MAX_TIME(txdesc)
#define SET_TX_DESC_NDPA_8812F(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)
#define GET_TX_DESC_NDPA_8812F(txdesc) GET_TX_DESC_NDPA(txdesc)
#define SET_TX_DESC_MAX_AGG_NUM_8812F(txdesc, value) \
SET_TX_DESC_MAX_AGG_NUM(txdesc, value)
#define GET_TX_DESC_MAX_AGG_NUM_8812F(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)
#define SET_TX_DESC_USE_MAX_TIME_EN_8812F(txdesc, value) \
SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)
#define GET_TX_DESC_USE_MAX_TIME_EN_8812F(txdesc) \
GET_TX_DESC_USE_MAX_TIME_EN(txdesc)
#define SET_TX_DESC_NAVUSEHDR_8812F(txdesc, value) \
SET_TX_DESC_NAVUSEHDR(txdesc, value)
#define GET_TX_DESC_NAVUSEHDR_8812F(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)
#define SET_TX_DESC_CHK_EN_8812F(txdesc, value) \
SET_TX_DESC_CHK_EN(txdesc, value)
#define GET_TX_DESC_CHK_EN_8812F(txdesc) GET_TX_DESC_CHK_EN(txdesc)
#define SET_TX_DESC_HW_RTS_EN_8812F(txdesc, value) \
SET_TX_DESC_HW_RTS_EN(txdesc, value)
#define GET_TX_DESC_HW_RTS_EN_8812F(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)
#define SET_TX_DESC_RTSEN_8812F(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)
#define GET_TX_DESC_RTSEN_8812F(txdesc) GET_TX_DESC_RTSEN(txdesc)
#define SET_TX_DESC_CTS2SELF_8812F(txdesc, value) \
SET_TX_DESC_CTS2SELF(txdesc, value)
#define GET_TX_DESC_CTS2SELF_8812F(txdesc) GET_TX_DESC_CTS2SELF(txdesc)
#define SET_TX_DESC_DISDATAFB_8812F(txdesc, value) \
SET_TX_DESC_DISDATAFB(txdesc, value)
#define GET_TX_DESC_DISDATAFB_8812F(txdesc) GET_TX_DESC_DISDATAFB(txdesc)
#define SET_TX_DESC_DISRTSFB_8812F(txdesc, value) \
SET_TX_DESC_DISRTSFB(txdesc, value)
#define GET_TX_DESC_DISRTSFB_8812F(txdesc) GET_TX_DESC_DISRTSFB(txdesc)
#define SET_TX_DESC_USE_RATE_8812F(txdesc, value) \
SET_TX_DESC_USE_RATE(txdesc, value)
#define GET_TX_DESC_USE_RATE_8812F(txdesc) GET_TX_DESC_USE_RATE(txdesc)
#define SET_TX_DESC_HW_SSN_SEL_8812F(txdesc, value) \
SET_TX_DESC_HW_SSN_SEL(txdesc, value)
#define GET_TX_DESC_HW_SSN_SEL_8812F(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)
#define SET_TX_DESC_WHEADER_LEN_8812F(txdesc, value) \
SET_TX_DESC_WHEADER_LEN(txdesc, value)
#define GET_TX_DESC_WHEADER_LEN_8812F(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)
/*TXDESC_WORD4*/
#define SET_TX_DESC_PCTS_MASK_IDX_8812F(txdesc, value) \
SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)
#define GET_TX_DESC_PCTS_MASK_IDX_8812F(txdesc) \
GET_TX_DESC_PCTS_MASK_IDX(txdesc)
#define SET_TX_DESC_PCTS_EN_8812F(txdesc, value) \
SET_TX_DESC_PCTS_EN(txdesc, value)
#define GET_TX_DESC_PCTS_EN_8812F(txdesc) GET_TX_DESC_PCTS_EN(txdesc)
#define SET_TX_DESC_RTSRATE_8812F(txdesc, value) \
SET_TX_DESC_RTSRATE(txdesc, value)
#define GET_TX_DESC_RTSRATE_8812F(txdesc) GET_TX_DESC_RTSRATE(txdesc)
#define SET_TX_DESC_RTS_DATA_RTY_LMT_8812F(txdesc, value) \
SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)
#define GET_TX_DESC_RTS_DATA_RTY_LMT_8812F(txdesc) \
GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)
#define SET_TX_DESC_RTY_LMT_EN_8812F(txdesc, value) \
SET_TX_DESC_RTY_LMT_EN(txdesc, value)
#define GET_TX_DESC_RTY_LMT_EN_8812F(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)
#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8812F(txdesc, value) \
SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)
#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8812F(txdesc) \
GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)
#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8812F(txdesc, value) \
SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)
#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8812F(txdesc) \
GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)
#define SET_TX_DESC_TRY_RATE_8812F(txdesc, value) \
SET_TX_DESC_TRY_RATE(txdesc, value)
#define GET_TX_DESC_TRY_RATE_8812F(txdesc) GET_TX_DESC_TRY_RATE(txdesc)
#define SET_TX_DESC_DATARATE_8812F(txdesc, value) \
SET_TX_DESC_DATARATE(txdesc, value)
#define GET_TX_DESC_DATARATE_8812F(txdesc) GET_TX_DESC_DATARATE(txdesc)
/*TXDESC_WORD5*/
#define SET_TX_DESC_POLLUTED_8812F(txdesc, value) \
SET_TX_DESC_POLLUTED(txdesc, value)
#define GET_TX_DESC_POLLUTED_8812F(txdesc) GET_TX_DESC_POLLUTED(txdesc)
#define SET_TX_DESC_ANTSEL_EN_8812F(txdesc, value) \
SET_TX_DESC_ANTSEL_EN_V1(txdesc, value)
#define GET_TX_DESC_ANTSEL_EN_8812F(txdesc) GET_TX_DESC_ANTSEL_EN_V1(txdesc)
#define SET_TX_DESC_TXPWR_OFSET_TYPE_8812F(txdesc, value) \
SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value)
#define GET_TX_DESC_TXPWR_OFSET_TYPE_8812F(txdesc) \
GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc)
#define SET_TX_DESC_TX_ANT_8812F(txdesc, value) \
SET_TX_DESC_TX_ANT(txdesc, value)
#define GET_TX_DESC_TX_ANT_8812F(txdesc) GET_TX_DESC_TX_ANT(txdesc)
#define SET_TX_DESC_PORT_ID_8812F(txdesc, value) \
SET_TX_DESC_PORT_ID(txdesc, value)
#define GET_TX_DESC_PORT_ID_8812F(txdesc) GET_TX_DESC_PORT_ID(txdesc)
#define SET_TX_DESC_MULTIPLE_PORT_8812F(txdesc, value) \
SET_TX_DESC_MULTIPLE_PORT(txdesc, value)
#define GET_TX_DESC_MULTIPLE_PORT_8812F(txdesc) \
GET_TX_DESC_MULTIPLE_PORT(txdesc)
#define SET_TX_DESC_SIGNALING_TAPKT_EN_8812F(txdesc, value) \
SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)
#define GET_TX_DESC_SIGNALING_TAPKT_EN_8812F(txdesc) \
GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)
#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8812F(txdesc, value) \
SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value)
#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8812F(txdesc) \
GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc)
#define SET_TX_DESC_RTS_SHORT_8812F(txdesc, value) \
SET_TX_DESC_RTS_SHORT(txdesc, value)
#define GET_TX_DESC_RTS_SHORT_8812F(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)
#define SET_TX_DESC_VCS_STBC_8812F(txdesc, value) \
SET_TX_DESC_VCS_STBC(txdesc, value)
#define GET_TX_DESC_VCS_STBC_8812F(txdesc) GET_TX_DESC_VCS_STBC(txdesc)
#define SET_TX_DESC_DATA_STBC_8812F(txdesc, value) \
SET_TX_DESC_DATA_STBC(txdesc, value)
#define GET_TX_DESC_DATA_STBC_8812F(txdesc) GET_TX_DESC_DATA_STBC(txdesc)
#define SET_TX_DESC_DATA_LDPC_8812F(txdesc, value) \
SET_TX_DESC_DATA_LDPC(txdesc, value)
#define GET_TX_DESC_DATA_LDPC_8812F(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)
#define SET_TX_DESC_DATA_BW_8812F(txdesc, value) \
SET_TX_DESC_DATA_BW(txdesc, value)
#define GET_TX_DESC_DATA_BW_8812F(txdesc) GET_TX_DESC_DATA_BW(txdesc)
#define SET_TX_DESC_DATA_SHORT_8812F(txdesc, value) \
SET_TX_DESC_DATA_SHORT(txdesc, value)
#define GET_TX_DESC_DATA_SHORT_8812F(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)
#define SET_TX_DESC_DATA_SC_8812F(txdesc, value) \
SET_TX_DESC_DATA_SC(txdesc, value)
#define GET_TX_DESC_DATA_SC_8812F(txdesc) GET_TX_DESC_DATA_SC(txdesc)
/*TXDESC_WORD6*/
#define SET_TX_DESC_ANTSEL_D_8812F(txdesc, value) \
SET_TX_DESC_ANTSEL_D(txdesc, value)
#define GET_TX_DESC_ANTSEL_D_8812F(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)
#define SET_TX_DESC_ANT_MAPD_8812F(txdesc, value) \
SET_TX_DESC_ANT_MAPD(txdesc, value)
#define GET_TX_DESC_ANT_MAPD_8812F(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)
#define SET_TX_DESC_ANT_MAPC_8812F(txdesc, value) \
SET_TX_DESC_ANT_MAPC(txdesc, value)
#define GET_TX_DESC_ANT_MAPC_8812F(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)
#define SET_TX_DESC_ANT_MAPB_8812F(txdesc, value) \
SET_TX_DESC_ANT_MAPB(txdesc, value)
#define GET_TX_DESC_ANT_MAPB_8812F(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)
#define SET_TX_DESC_ANT_MAPA_8812F(txdesc, value) \
SET_TX_DESC_ANT_MAPA(txdesc, value)
#define GET_TX_DESC_ANT_MAPA_8812F(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)
#define SET_TX_DESC_ANTSEL_C_8812F(txdesc, value) \
SET_TX_DESC_ANTSEL_C(txdesc, value)
#define GET_TX_DESC_ANTSEL_C_8812F(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)
#define SET_TX_DESC_ANTSEL_B_8812F(txdesc, value) \
SET_TX_DESC_ANTSEL_B(txdesc, value)
#define GET_TX_DESC_ANTSEL_B_8812F(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)
#define SET_TX_DESC_ANTSEL_A_8812F(txdesc, value) \
SET_TX_DESC_ANTSEL_A(txdesc, value)
#define GET_TX_DESC_ANTSEL_A_8812F(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)
#define SET_TX_DESC_MBSSID_8812F(txdesc, value) \
SET_TX_DESC_MBSSID(txdesc, value)
#define GET_TX_DESC_MBSSID_8812F(txdesc) GET_TX_DESC_MBSSID(txdesc)
#define SET_TX_DESC_SW_DEFINE_8812F(txdesc, value) \
SET_TX_DESC_SW_DEFINE(txdesc, value)
#define GET_TX_DESC_SW_DEFINE_8812F(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)
/*TXDESC_WORD7*/
#define SET_TX_DESC_DMA_TXAGG_NUM_8812F(txdesc, value) \
SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)
#define GET_TX_DESC_DMA_TXAGG_NUM_8812F(txdesc) \
GET_TX_DESC_DMA_TXAGG_NUM(txdesc)
#define SET_TX_DESC_FINAL_DATA_RATE_8812F(txdesc, value) \
SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)
#define GET_TX_DESC_FINAL_DATA_RATE_8812F(txdesc) \
GET_TX_DESC_FINAL_DATA_RATE(txdesc)
#define SET_TX_DESC_NTX_MAP_8812F(txdesc, value) \
SET_TX_DESC_NTX_MAP(txdesc, value)
#define GET_TX_DESC_NTX_MAP_8812F(txdesc) GET_TX_DESC_NTX_MAP(txdesc)
#define SET_TX_DESC_TX_BUFF_SIZE_8812F(txdesc, value) \
SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)
#define GET_TX_DESC_TX_BUFF_SIZE_8812F(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)
#define SET_TX_DESC_TXDESC_CHECKSUM_8812F(txdesc, value) \
SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)
#define GET_TX_DESC_TXDESC_CHECKSUM_8812F(txdesc) \
GET_TX_DESC_TXDESC_CHECKSUM(txdesc)
#define SET_TX_DESC_TIMESTAMP_8812F(txdesc, value) \
SET_TX_DESC_TIMESTAMP(txdesc, value)
#define GET_TX_DESC_TIMESTAMP_8812F(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)
/*TXDESC_WORD8*/
#define SET_TX_DESC_TXWIFI_CP_8812F(txdesc, value) \
SET_TX_DESC_TXWIFI_CP(txdesc, value)
#define GET_TX_DESC_TXWIFI_CP_8812F(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)
#define SET_TX_DESC_MAC_CP_8812F(txdesc, value) \
SET_TX_DESC_MAC_CP(txdesc, value)
#define GET_TX_DESC_MAC_CP_8812F(txdesc) GET_TX_DESC_MAC_CP(txdesc)
#define SET_TX_DESC_STW_PKTRE_DIS_8812F(txdesc, value) \
SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)
#define GET_TX_DESC_STW_PKTRE_DIS_8812F(txdesc) \
GET_TX_DESC_STW_PKTRE_DIS(txdesc)
#define SET_TX_DESC_STW_RB_DIS_8812F(txdesc, value) \
SET_TX_DESC_STW_RB_DIS(txdesc, value)
#define GET_TX_DESC_STW_RB_DIS_8812F(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)
#define SET_TX_DESC_STW_RATE_DIS_8812F(txdesc, value) \
SET_TX_DESC_STW_RATE_DIS(txdesc, value)
#define GET_TX_DESC_STW_RATE_DIS_8812F(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)
#define SET_TX_DESC_STW_ANT_DIS_8812F(txdesc, value) \
SET_TX_DESC_STW_ANT_DIS(txdesc, value)
#define GET_TX_DESC_STW_ANT_DIS_8812F(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)
#define SET_TX_DESC_STW_EN_8812F(txdesc, value) \
SET_TX_DESC_STW_EN(txdesc, value)
#define GET_TX_DESC_STW_EN_8812F(txdesc) GET_TX_DESC_STW_EN(txdesc)
#define SET_TX_DESC_SMH_EN_8812F(txdesc, value) \
SET_TX_DESC_SMH_EN(txdesc, value)
#define GET_TX_DESC_SMH_EN_8812F(txdesc) GET_TX_DESC_SMH_EN(txdesc)
#define SET_TX_DESC_TAILPAGE_L_8812F(txdesc, value) \
SET_TX_DESC_TAILPAGE_L(txdesc, value)
#define GET_TX_DESC_TAILPAGE_L_8812F(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)
#define SET_TX_DESC_SDIO_DMASEQ_8812F(txdesc, value) \
SET_TX_DESC_SDIO_DMASEQ(txdesc, value)
#define GET_TX_DESC_SDIO_DMASEQ_8812F(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)
#define SET_TX_DESC_NEXTHEADPAGE_L_8812F(txdesc, value) \
SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)
#define GET_TX_DESC_NEXTHEADPAGE_L_8812F(txdesc) \
GET_TX_DESC_NEXTHEADPAGE_L(txdesc)
#define SET_TX_DESC_EN_HWSEQ_MODE_8812F(txdesc, value) \
SET_TX_DESC_EN_HWSEQ_MODE(txdesc, value)
#define GET_TX_DESC_EN_HWSEQ_MODE_8812F(txdesc) \
GET_TX_DESC_EN_HWSEQ_MODE(txdesc)
#define SET_TX_DESC_DATA_RC_8812F(txdesc, value) \
SET_TX_DESC_DATA_RC(txdesc, value)
#define GET_TX_DESC_DATA_RC_8812F(txdesc) GET_TX_DESC_DATA_RC(txdesc)
#define SET_TX_DESC_BAR_RTY_TH_8812F(txdesc, value) \
SET_TX_DESC_BAR_RTY_TH(txdesc, value)
#define GET_TX_DESC_BAR_RTY_TH_8812F(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)
#define SET_TX_DESC_RTS_RC_8812F(txdesc, value) \
SET_TX_DESC_RTS_RC(txdesc, value)
#define GET_TX_DESC_RTS_RC_8812F(txdesc) GET_TX_DESC_RTS_RC(txdesc)
/*TXDESC_WORD9*/
#define SET_TX_DESC_TAILPAGE_H_8812F(txdesc, value) \
SET_TX_DESC_TAILPAGE_H(txdesc, value)
#define GET_TX_DESC_TAILPAGE_H_8812F(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)
#define SET_TX_DESC_NEXTHEADPAGE_H_8812F(txdesc, value) \
SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)
#define GET_TX_DESC_NEXTHEADPAGE_H_8812F(txdesc) \
GET_TX_DESC_NEXTHEADPAGE_H(txdesc)
#define SET_TX_DESC_SW_SEQ_8812F(txdesc, value) \
SET_TX_DESC_SW_SEQ(txdesc, value)
#define GET_TX_DESC_SW_SEQ_8812F(txdesc) GET_TX_DESC_SW_SEQ(txdesc)
#define SET_TX_DESC_TXBF_PATH_8812F(txdesc, value) \
SET_TX_DESC_TXBF_PATH(txdesc, value)
#define GET_TX_DESC_TXBF_PATH_8812F(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)
#define SET_TX_DESC_PADDING_LEN_8812F(txdesc, value) \
SET_TX_DESC_PADDING_LEN(txdesc, value)
#define GET_TX_DESC_PADDING_LEN_8812F(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)
#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8812F(txdesc, value) \
SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)
#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8812F(txdesc) \
GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)
/*WORD10*/
#define SET_TX_DESC_HT_DATA_SND_8812F(txdesc, value) \
SET_TX_DESC_HT_DATA_SND(txdesc, value)
#define GET_TX_DESC_HT_DATA_SND_8812F(txdesc) GET_TX_DESC_HT_DATA_SND(txdesc)
#define SET_TX_DESC_SHCUT_CAM_8812F(txdesc, value) \
SET_TX_DESC_SHCUT_CAM(txdesc, value)
#define GET_TX_DESC_SHCUT_CAM_8812F(txdesc) GET_TX_DESC_SHCUT_CAM(txdesc)
#define SET_TX_DESC_MU_DATARATE_8812F(txdesc, value) \
SET_TX_DESC_MU_DATARATE(txdesc, value)
#define GET_TX_DESC_MU_DATARATE_8812F(txdesc) GET_TX_DESC_MU_DATARATE(txdesc)
#define SET_TX_DESC_MU_RC_8812F(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value)
#define GET_TX_DESC_MU_RC_8812F(txdesc) GET_TX_DESC_MU_RC(txdesc)
#define SET_TX_DESC_NDPA_RATE_SEL_8812F(txdesc, value) \
SET_TX_DESC_NDPA_RATE_SEL(txdesc, value)
#define GET_TX_DESC_NDPA_RATE_SEL_8812F(txdesc) \
GET_TX_DESC_NDPA_RATE_SEL(txdesc)
#define SET_TX_DESC_HW_NDPA_EN_8812F(txdesc, value) \
SET_TX_DESC_HW_NDPA_EN(txdesc, value)
#define GET_TX_DESC_HW_NDPA_EN_8812F(txdesc) GET_TX_DESC_HW_NDPA_EN(txdesc)
#define SET_TX_DESC_SND_PKT_SEL_8812F(txdesc, value) \
SET_TX_DESC_SND_PKT_SEL(txdesc, value)
#define GET_TX_DESC_SND_PKT_SEL_8812F(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc)
#endif
#endif

366
hal/halmac/halmac_tx_desc_nic.h
View File

@@ -16,7 +16,8 @@
#ifndef _HALMAC_TX_DESC_NIC_H_
#define _HALMAC_TX_DESC_NIC_H_
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
/*TXDESC_WORD0*/
@@ -35,7 +36,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_GF(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value)
@@ -52,7 +54,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_NO_ACM(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value)
@@ -69,7 +72,7 @@
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 28, 1, value)
@@ -79,14 +82,29 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 27, 1, value)
#define GET_TX_DESC_AMSDU_PAD_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 27, 1)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_LS(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 26, 1, value)
#define GET_TX_DESC_LS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 26, 1)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_HTC(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 25, 1, value)
#define GET_TX_DESC_HTC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 25, 1)
@@ -106,7 +124,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_OFFSET(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 16, 8, value)
@@ -143,8 +161,17 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_KEYID_SEL(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value)
#define GET_TX_DESC_KEYID_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_MOREDATA(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value)
@@ -164,7 +191,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_PKT_OFFSET(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 24, 5, value)
@@ -181,7 +209,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_SEC_TYPE(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 22, 2, value)
@@ -204,7 +233,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_PIFS(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 15, 1, value)
@@ -228,7 +258,7 @@
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_QSEL(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 8, 5, value)
@@ -245,7 +275,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_MACID(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 7, value)
@@ -262,7 +293,7 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
/*TXDESC_WORD2*/
@@ -281,7 +312,7 @@
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
HALMAC_8822C_SUPPORT)
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_FTM_EN(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 30, 1, value)
@@ -306,7 +337,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_G_ID(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 6, value)
@@ -332,7 +364,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_BT_NULL(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 23, 1, value)
@@ -365,7 +398,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_NULL_1(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 15, 1, value)
@@ -386,7 +420,8 @@
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_TRI_FRAME(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 9, 1, value)
@@ -395,7 +430,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_P_AID(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 9, value)
@@ -413,7 +449,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
/*TXDESC_WORD3*/
@@ -443,7 +480,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_NAVUSEHDR(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 15, 1, value)
@@ -472,7 +510,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_DISDATAFB(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 10, 1, value)
@@ -501,7 +540,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_WHEADER_LEN(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value)
@@ -518,7 +558,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
/*TXDESC_WORD4*/
@@ -561,7 +602,7 @@
#endif
#if (HALMAC_8822C_SUPPORT)
#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_ANTSEL_EN_V1(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 30, 1, value)
@@ -578,7 +619,7 @@
#endif
#if (HALMAC_8822C_SUPPORT)
#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 2, value)
@@ -587,8 +628,18 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_TXPWR_OFSET_TYPE_V1(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 3, value)
#define GET_TX_DESC_TXPWR_OFSET_TYPE_V1(txdesc) \
LE_BITS_TO_4BYTE(txdesc + 0x14, 28, 3)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_TX_ANT(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 4, value)
@@ -604,8 +655,17 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_DROP_ID_V1(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 22, 2, value)
#define GET_TX_DESC_DROP_ID_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 22, 2)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_PORT_ID(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 21, 3, value)
@@ -613,8 +673,16 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_PORT_ID_V1(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 21, 1, value)
#define GET_TX_DESC_PORT_ID_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 21, 1)
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_MULTIPLE_PORT(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 18, 3, value)
@@ -623,7 +691,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 17, 1, value)
@@ -632,7 +701,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_RTS_SC(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 13, 4, value)
@@ -640,7 +710,8 @@
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 13, 4, value)
@@ -650,7 +721,8 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_RTS_SHORT(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 12, 1, value)
@@ -677,7 +749,7 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
/*TXDESC_WORD6*/
@@ -695,8 +767,16 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_ANT_MAPC_V2(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 30, 2, value)
#define GET_TX_DESC_ANT_MAPC_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 30, 2)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_ANT_MAPD(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 2, value)
@@ -712,8 +792,16 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_ANT_MAPB_V2(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 2, value)
#define GET_TX_DESC_ANT_MAPB_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 2)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_ANT_MAPC(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 2, value)
@@ -729,8 +817,16 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_ANT_MAPA_V2(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 2, value)
#define GET_TX_DESC_ANT_MAPA_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 2)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_ANT_MAPB(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 2, value)
@@ -746,12 +842,34 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_ANTSEL_D_V1(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 2, value)
#define GET_TX_DESC_ANTSEL_D_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 2)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_ANT_MAPA(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 22, 2, value)
#define GET_TX_DESC_ANT_MAPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 22, 2)
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_ANTSEL_C_V2(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 22, 2, value)
#define GET_TX_DESC_ANTSEL_C_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 22, 2)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_ANTSEL_C(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 20, 2, value)
#define GET_TX_DESC_ANTSEL_C(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 20, 2)
@@ -766,8 +884,16 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_ANTSEL_B_V2(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 19, 3, value)
#define GET_TX_DESC_ANTSEL_B_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 19, 3)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_ANTSEL_B(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 18, 2, value)
@@ -786,8 +912,17 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_ANTSEL_A_V2(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 3, value)
#define GET_TX_DESC_ANTSEL_A_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 3)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_MBSSID(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 12, 4, value)
@@ -796,7 +931,7 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_SW_DEFINE(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 12, value)
@@ -804,7 +939,7 @@
#endif
#if (HALMAC_8198F_SUPPORT)
#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_SWPS_SEQ(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 12, value)
@@ -813,17 +948,43 @@
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
/*TXDESC_WORD7*/
#define SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 24, 8, value)
#define GET_TX_DESC_DMA_TXAGG_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 24, 8)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 24, 8, value)
#define GET_TX_DESC_FINAL_DATA_RATE(txdesc) \
LE_BITS_TO_4BYTE(txdesc + 0x1C, 24, 8)
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_ANT_MAPD_V2(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 22, 2, value)
#define GET_TX_DESC_ANT_MAPD_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 22, 2)
#define SET_TX_DESC_ANTSEL_EN_V2(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 21, 1, value)
#define GET_TX_DESC_ANTSEL_EN_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 21, 1)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_NTX_MAP(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 20, 4, value)
#define GET_TX_DESC_NTX_MAP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 20, 4)
@@ -841,8 +1002,17 @@
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_MBSSID_EX_V1(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 16, 1, value)
#define GET_TX_DESC_MBSSID_EX_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 16, 1)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value)
@@ -855,6 +1025,12 @@
SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value)
#define GET_TX_DESC_TIMESTAMP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
/*TXDESC_WORD8*/
#define SET_TX_DESC_TXWIFI_CP(txdesc, value) \
@@ -881,6 +1057,13 @@
#define SET_TX_DESC_SMH_EN(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 1, value)
#define GET_TX_DESC_SMH_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 1)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_TAILPAGE_L(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 8, value)
#define GET_TX_DESC_TAILPAGE_L(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 8)
@@ -891,12 +1074,40 @@
SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 8, value)
#define GET_TX_DESC_NEXTHEADPAGE_L(txdesc) \
LE_BITS_TO_4BYTE(txdesc + 0x20, 16, 8)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_EN_HWSEQ(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 15, 1, value)
#define GET_TX_DESC_EN_HWSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 15, 1)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
#define SET_TX_DESC_EN_HWEXSEQ(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 14, 1, value)
#define GET_TX_DESC_EN_HWEXSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 14, 1)
#endif
#if (HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_EN_HWSEQ_MODE(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 14, 2, value)
#define GET_TX_DESC_EN_HWSEQ_MODE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 14, 2)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_DATA_RC(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 8, 6, value)
#define GET_TX_DESC_DATA_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 8, 6)
@@ -907,6 +1118,12 @@
SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 0, 6, value)
#define GET_TX_DESC_RTS_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 0, 6)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
/*TXDESC_WORD9*/
#define SET_TX_DESC_TAILPAGE_H(txdesc, value) \
@@ -916,12 +1133,42 @@
SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 24, 4, value)
#define GET_TX_DESC_NEXTHEADPAGE_H(txdesc) \
LE_BITS_TO_4BYTE(txdesc + 0x24, 24, 4)
#endif
#if (HALMAC_8192F_SUPPORT)
#define SET_TX_DESC_FINAL_DATA_RATE_V1(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 24, 8, value)
#define GET_TX_DESC_FINAL_DATA_RATE_V1(txdesc) \
LE_BITS_TO_4BYTE(txdesc + 0x24, 24, 8)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_SW_SEQ(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 12, 12, value)
#define GET_TX_DESC_SW_SEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 12, 12)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_TXBF_PATH(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 11, 1, value)
#define GET_TX_DESC_TXBF_PATH(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 11, 1)
#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_PADDING_LEN(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 11, value)
#define GET_TX_DESC_PADDING_LEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 0, 11)
@@ -932,16 +1179,45 @@
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
#if (HALMAC_8812F_SUPPORT)
/*WORD10*/
#define SET_TX_DESC_HT_DATA_SND(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 31, 1, value)
#define GET_TX_DESC_HT_DATA_SND(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 31, 1)
#define SET_TX_DESC_SHCUT_CAM(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 16, 6, value)
#define GET_TX_DESC_SHCUT_CAM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 16, 6)
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_MU_DATARATE(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 8, 8, value)
#define GET_TX_DESC_MU_DATARATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 8, 8)
#define SET_TX_DESC_MU_RC(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 4, 4, value)
#define GET_TX_DESC_MU_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 4, 4)
#endif
#if (HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_NDPA_RATE_SEL(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 3, 1, value)
#define GET_TX_DESC_NDPA_RATE_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 3, 1)
#define SET_TX_DESC_HW_NDPA_EN(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 2, 1, value)
#define GET_TX_DESC_HW_NDPA_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 2, 1)
#endif
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \
HALMAC_8812F_SUPPORT)
#define SET_TX_DESC_SND_PKT_SEL(txdesc, value) \
SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 0, 2, value)
#define GET_TX_DESC_SND_PKT_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 0, 2)

178
hal/halmac/halmac_type.h
View File

@@ -48,6 +48,18 @@
#define HALMAC_MSG_LEVEL_NO_LOG 0
#endif
#ifndef HALMAC_SDIO_SUPPORT
#define HALMAC_SDIO_SUPPORT 1
#endif
#ifndef HALMAC_USB_SUPPORT
#define HALMAC_USB_SUPPORT 1
#endif
#ifndef HALMAC_PCIE_SUPPORT
#define HALMAC_PCIE_SUPPORT 1
#endif
#ifndef HALMAC_MSG_LEVEL
#define HALMAC_MSG_LEVEL HALMAC_MSG_LEVEL_TRACE
#endif
@@ -176,18 +188,36 @@
api->halmac_reg_sdio_cmd53_read_n(adapter, offset, size, data)
#define HALMAC_REG_W8_CLR(offset, mask) \
HALMAC_REG_W8(offset, HALMAC_REG_R8(offset) & ~(mask))
do { \
u32 __offset = (u32)offset; \
HALMAC_REG_W8(__offset, HALMAC_REG_R8(__offset) & ~(mask)); \
} while (0)
#define HALMAC_REG_W16_CLR(offset, mask) \
HALMAC_REG_W16(offset, HALMAC_REG_R16(offset) & ~(mask))
do { \
u32 __offset = (u32)offset; \
HALMAC_REG_W16(__offset, HALMAC_REG_R16(__offset) & ~(mask)); \
} while (0)
#define HALMAC_REG_W32_CLR(offset, mask) \
HALMAC_REG_W32(offset, HALMAC_REG_R32(offset) & ~(mask))
do { \
u32 __offset = (u32)offset; \
HALMAC_REG_W32(__offset, HALMAC_REG_R32(__offset) & ~(mask)); \
} while (0)
#define HALMAC_REG_W8_SET(offset, mask) \
HALMAC_REG_W8(offset, HALMAC_REG_R8(offset) | (mask))
do { \
u32 __offset = (u32)offset; \
HALMAC_REG_W8(__offset, HALMAC_REG_R8(__offset) | mask); \
} while (0)
#define HALMAC_REG_W16_SET(offset, mask) \
HALMAC_REG_W16(offset, HALMAC_REG_R16(offset) | (mask))
do { \
u32 __offset = (u32)offset; \
HALMAC_REG_W16(__offset, HALMAC_REG_R16(__offset) | mask); \
} while (0)
#define HALMAC_REG_W32_SET(offset, mask) \
HALMAC_REG_W32(offset, HALMAC_REG_R32(offset) | (mask))
do { \
u32 __offset = (u32)offset; \
HALMAC_REG_W32(__offset, HALMAC_REG_R32(__offset) | mask); \
} while (0)
/* Swap Little-endian <-> Big-endia*/
#define SWAP32(x) \
@@ -479,6 +509,8 @@ enum halmac_ret_status {
HALMAC_RET_TXDESC_SET_FAIL = 0x73,
HALMAC_RET_WLHDR_FAIL = 0x74,
HALMAC_RET_WLAN_MODE_FAIL = 0x75,
HALMAC_RET_SDIO_SEQ_FAIL = 0x72,
HALMAC_RET_INIT_XTAL_AAC_FAIL = 0x76,
};
enum halmac_chip_id {
@@ -487,6 +519,7 @@ enum halmac_chip_id {
HALMAC_CHIP_ID_8814B = 2,
HALMAC_CHIP_ID_8197F = 3,
HALMAC_CHIP_ID_8822C = 4,
HALMAC_CHIP_ID_8812F = 5,
HALMAC_CHIP_ID_UNDEFINE = 0x7F,
};
@@ -858,6 +891,7 @@ struct halmac_hw_cfg_info {
u8 acq_num;
u8 trx_mode;
u8 usb_txagg_num;
u32 prtct_efuse_size;
};
struct halmac_sdio_free_space {
@@ -948,6 +982,7 @@ struct halmac_ch_switch_option {
u8 normal_cycle;
u8 phase_2_period;
u8 phase_2_period_sel;
u8 nlo_en;
};
struct halmac_p2pps {
@@ -1027,6 +1062,11 @@ struct halmac_fast_edca_cfg {
u8 queue_to; /* unit : 32us*/
};
struct halmac_txfifo_lifetime_cfg {
u8 enable;
u32 lifetime;
};
enum halmac_data_rate {
HALMAC_CCK1,
HALMAC_CCK2,
@@ -1199,6 +1239,7 @@ enum halmac_drv_rsvd_pg_num {
HALMAC_RSVD_PG_NUM32, /* 4K */
HALMAC_RSVD_PG_NUM64, /* 8K */
HALMAC_RSVD_PG_NUM128, /* 16K */
HALMAC_RSVD_PG_NUM256, /* 32K */
};
enum halmac_pcie_cfg {
@@ -1232,11 +1273,11 @@ union halmac_wlan_addr {
u8 addr[6];
struct {
union {
u32 low;
__le32 low;
u8 low_byte[4];
};
union {
u16 high;
__le16 high;
u8 high_byte[2];
};
} addr_l_h;
@@ -1268,9 +1309,6 @@ struct halmac_platform_api {
/* send pBuf to h2c queue, the tx_desc is not included in pBuf */
/* driver need to fill tx_desc with qsel = h2c */
u8 (*SEND_H2C_PKT)(void *drv_adapter, u8 *buf, u32 size);
/* send pBuf to fw cmd queue, the tx_desc is not included in pBuf */
/*driver need to fill tx_desc with qsel = h2c */
u8 (*SEND_FWCMD)(void *drv_adapter, u8 *buf, u32 size);
u8 (*RTL_FREE)(void *drv_adapter, void *buf, u32 size);
void* (*RTL_MALLOC)(void *drv_adapter, u32 size);
@@ -1518,6 +1556,8 @@ enum halmac_api_id {
HALMAC_API_GET_CPU_MODE = 0x9A,
HALMAC_API_DRV_FWCTRL = 0x9B,
HALMAC_API_EN_REF_AUTOK = 0x9C,
HALMAC_API_RESET_WIFI_FW = 0x9D,
HALMAC_API_CFGSPC_SET_PCIE = 0x9E,
HALMAC_API_MAX
};
@@ -1556,6 +1596,12 @@ enum halmac_sdio_tx_format {
HALMAC_SDIO_DUMMY_AUTO_MODE = 3,
};
enum halmac_sdio_clk_monitor {
HALMAC_MONITOR_5US = 1,
HALMAC_MONITOR_50US = 2,
HALMAC_MONITOR_9MS = 3,
};
enum halmac_hw_id {
/* Get HW value */
HALMAC_HW_RQPN_MAPPING = 0x00,
@@ -1584,13 +1630,13 @@ enum halmac_hw_id {
HALMAC_HW_TX_PAGE_SIZE = 0x17,
HALMAC_HW_USB_TXAGG_DESC_NUM = 0x18,
HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 0x19,
HALMAC_HW_HIOE_INST_START = 0x1A,
HALMAC_HW_HIOE_INST_END = 0x1B,
HALMAC_HW_AC_OQT_SIZE = 0x1C,
HALMAC_HW_NON_AC_OQT_SIZE = 0x1D,
HALMAC_HW_AC_QUEUE_NUM = 0x1E,
HALMAC_HW_RQPN_CH_MAPPING = 0x1F,
HALMAC_HW_PWR_STATE = 0x20,
HALMAC_HW_SDIO_INT_LAT = 0x21,
HALMAC_HW_SDIO_CLK_CNT = 0x22,
/* Set HW value */
HALMAC_HW_USB_MODE = 0x60,
HALMAC_HW_SEQ_EN = 0x61,
@@ -1609,6 +1655,11 @@ enum halmac_hw_id {
HALMAC_HW_FAST_EDCA = 0x6E,
HALMAC_HW_LDO25_EN = 0x6F,
HALMAC_HW_PCIE_REF_AUTOK = 0x70,
HALMAC_HW_RTS_FULL_BW = 0x71,
HALMAC_HW_FREE_CNT_EN = 0x72,
HALMAC_HW_SDIO_WT_EN = 0x73,
HALMAC_HW_SDIO_CLK_MONITOR = 0x74,
HALMAC_HW_TXFIFO_LIFETIME = 0x75,
HALMAC_HW_ID_UNDEFINE = 0x7F,
};
@@ -1646,6 +1697,8 @@ enum halmac_gpio_func {
HALMAC_GPIO_FUNC_SW_IO_13 = 15,
HALMAC_GPIO_FUNC_SW_IO_14 = 16,
HALMAC_GPIO_FUNC_SW_IO_15 = 17,
HALMAC_GPIO_FUNC_BT_HOST_WAKE1 = 18,
HALMAC_GPIO_FUNC_BT_DEV_WAKE1 = 19,
HALMAC_GPIO_FUNC_UNDEFINE = 0X7F,
};
@@ -1668,6 +1721,68 @@ enum halmac_psf_fcs_chk_thr {
HALMAC_PSF_FCS_CHK_THR_28 = 7,
};
enum halmac_func_ctrl {
HALMAC_DISABLE = 0,
HALMAC_ENABLE = 1,
HALMAC_DEFAULT = 0xFE,
HALMAC_IGNORE = 0xFF
};
enum halmac_pcie_clkdly {
HALMAC_CLKDLY_0 = 0,
HALMAC_CLKDLY_5US = 1,
HALMAC_CLKDLY_6US = 2,
HALMAC_CLKDLY_11US = 3,
HALMAC_CLKDLY_15US = 4,
HALMAC_CLKDLY_19US = 5,
HALMAC_CLKDLY_25US = 6,
HALMAC_CLKDLY_30US = 7,
HALMAC_CLKDLY_38US = 8,
HALMAC_CLKDLY_50US = 9,
HALMAC_CLKDLY_64US = 10,
HALMAC_CLKDLY_100US = 11,
HALMAC_CLKDLY_128US = 12,
HALMAC_CLKDLY_150US = 13,
HALMAC_CLKDLY_192US = 14,
HALMAC_CLKDLY_200US = 15,
HALMAC_CLKDLY_R_ERR = 0xFD,
HALMAC_CLKDLY_DEF = 0xFE,
HALMAC_CLKDLY_IGNORE = 0xFF
};
enum halmac_pcie_l1dly {
HALMAC_L1DLY_16US = 0,
HALMAC_L1DLY_32US = 1,
HALMAC_L1DLY_64US = 2,
HALMAC_L1DLY_INFI = 3,
HALMAC_L1DLY_R_ERR = 0xFD,
HALMAC_L1DLY_DEF = 0xFE,
HALMAC_L1DLY_IGNORE = 0xFF
};
enum halmac_pcie_l0sdly {
HALMAC_L0SDLY_1US = 0,
HALMAC_L0SDLY_3US = 1,
HALMAC_L0SDLY_5US = 2,
HALMAC_L0SDLY_7US = 3,
HALMAC_L0SDLY_R_ERR = 0xFD,
HALMAC_L0SDLY_DEF = 0xFE,
HALMAC_L0SDLY_IGNORE = 0xFF
};
struct halmac_pcie_cfgspc_param {
u8 write;
u8 read;
enum halmac_func_ctrl l0s_ctrl;
enum halmac_func_ctrl l1_ctrl;
enum halmac_func_ctrl l1ss_ctrl;
enum halmac_func_ctrl wake_ctrl;
enum halmac_func_ctrl crq_ctrl;
enum halmac_pcie_clkdly clkdly_ctrl;
enum halmac_pcie_l0sdly l0sdly_ctrl;
enum halmac_pcie_l1dly l1dly_ctrl;
};
struct halmac_txff_allocation {
u16 tx_fifo_pg_num;
u16 rsvd_pg_num;
@@ -1828,6 +1943,16 @@ struct halmac_edca_para {
struct halmac_mac_rx_ignore_cfg {
u8 hdr_chk_en;
u8 fcs_chk_en;
u8 cck_rst_en;
enum halmac_psf_fcs_chk_thr fcs_chk_thr;
};
struct halmac_rx_ignore_info {
u8 hdr_chk_mask;
u8 fcs_chk_mask;
u8 hdr_chk_en;
u8 fcs_chk_en;
u8 cck_rst_en;
enum halmac_psf_fcs_chk_thr fcs_chk_thr;
};
@@ -1835,7 +1960,9 @@ struct halmac_pinmux_info {
/* byte0 */
u8 wl_led:1;
u8 sdio_int:1;
u8 rsvd1:6;
u8 bt_host_wake:1;
u8 bt_dev_wake:1;
u8 rsvd1:4;
/* byte1 */
u8 sw_io_0:1;
u8 sw_io_1:1;
@@ -1885,9 +2012,9 @@ struct halmac_h2c_info {
struct halmac_adapter {
enum halmac_dma_mapping pq_map[HALMAC_PQ_MAP_NUM];
enum halmac_dma_ch ch_map[HALMAC_PQ_MAP_NUM];
HALMAC_MUTEX h2c_seq_mutex;
HALMAC_MUTEX efuse_mutex;
HALMAC_MUTEX sdio_indir_mutex; /*Protect sdio indirect access */
HALMAC_MUTEX h2c_seq_mutex; /* protect h2c seq num */
HALMAC_MUTEX efuse_mutex; /*protect adapter efuse map */
HALMAC_MUTEX sdio_indir_mutex; /*protect sdio indirect access */
struct halmac_cfg_param_info cfg_param_info;
struct halmac_ch_sw_info ch_sw_info;
struct halmac_event_trigger evnt;
@@ -1922,7 +2049,8 @@ struct halmac_adapter {
u8 efuse_auto_check_en;
u8 pcie_refautok_en;
u8 pwr_off_flow_flag;
u8 nlo_flag;
struct halmac_rx_ignore_info rx_ignore_info;
#if HALMAC_PLATFORM_TESTPROGRAM
struct halmisc_adapter *halmisc_adapter;
#endif
@@ -1943,6 +2071,8 @@ struct halmac_api {
enum halmac_dlfw_mem mem_sel,
u8 *fw_bin, u32 size);
enum halmac_ret_status
(*halmac_reset_wifi_fw)(struct halmac_adapter *adapter);
enum halmac_ret_status
(*halmac_get_fw_version)(struct halmac_adapter *adapter,
struct halmac_fw_version *ver);
enum halmac_ret_status
@@ -2238,12 +2368,14 @@ struct halmac_api {
enum halmac_ret_status
(*halmac_cfg_csi_rate)(struct halmac_adapter *adapter, u8 rssi,
u8 cur_rate, u8 fixrate_en, u8 *new_rate);
#if HALMAC_SDIO_SUPPORT
enum halmac_ret_status
(*halmac_sdio_cmd53_4byte)(struct halmac_adapter *adapter,
enum halmac_sdio_cmd53_4byte_mode mode);
enum halmac_ret_status
(*halmac_sdio_hw_info)(struct halmac_adapter *adapter,
struct halmac_sdio_hw_info *info);
#endif
enum halmac_ret_status
(*halmac_cfg_transmitter_addr)(struct halmac_adapter *adapter, u8 port,
union halmac_wlan_addr *addr);
@@ -2266,7 +2398,8 @@ struct halmac_api {
(*halmac_download_flash)(struct halmac_adapter *adapter, u8 *fw_bin,
u32 size, u32 rom_addr);
enum halmac_ret_status
(*halmac_read_flash)(struct halmac_adapter *adapter, u32 addr);
(*halmac_read_flash)(struct halmac_adapter *adapter, u32 addr,
u32 length);
enum halmac_ret_status
(*halmac_erase_flash)(struct halmac_adapter *adapter, u8 erase_cmd,
u32 addr);
@@ -2332,8 +2465,13 @@ struct halmac_api {
enum halmac_ret_status
(*halmac_write_efuse)(struct halmac_adapter *adapter, u32 offset,
u8 value);
VOID
#if HALMAC_PCIE_SUPPORT
enum halmac_ret_status
(*halmac_cfgspc_set_pcie)(struct halmac_adapter *adapter,
struct halmac_pcie_cfgspc_param *param);
void
(*halmac_en_ref_autok_pcie)(struct halmac_adapter *adapter, u8 en);
#endif
#if HALMAC_PLATFORM_TESTPROGRAM
struct halmisc_api *halmisc_api;
#endif