mirror of
https://github.com/RinCat/RTL88x2BU-Linux-Driver.git
synced 2026-01-19 10:26:35 +00:00
Update to 5.6.1
This commit is contained in:
Rin Cat
File diff suppressed because it is too large
Load Diff
@@ -19,517 +19,477 @@
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/* *******************************************
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* The following is for 8822B 1ANT BT Co-exist definition
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* ******************************************* */
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#define BT_8822B_1ANT_COEX_DBG 0
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#define BT_AUTO_REPORT_ONLY_8822B_1ANT 1
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#define BT_INFO_8822B_1ANT_B_FTP BIT(7)
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#define BT_INFO_8822B_1ANT_B_A2DP BIT(6)
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#define BT_INFO_8822B_1ANT_B_HID BIT(5)
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#define BT_INFO_8822B_1ANT_B_SCO_BUSY BIT(4)
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#define BT_INFO_8822B_1ANT_B_ACL_BUSY BIT(3)
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#define BT_INFO_8822B_1ANT_B_INQ_PAGE BIT(2)
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#define BT_INFO_8822B_1ANT_B_SCO_ESCO BIT(1)
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#define BT_INFO_8822B_1ANT_B_CONNECTION BIT(0)
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#define BT_INFO_8822B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
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(((_BT_INFO_EXT_&BIT(0))) ? true : false)
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#define BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT 2
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#define BT_8822B_1ANT_WIFI_NOISY_THRESH 150 /* max: 255 */
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#define BT_8822B_1ANT_DEFAULT_ISOLATION 15 /* unit: dB */
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/* for Antenna detection */
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#define BT_8822B_1ANT_ANTDET_PSDTHRES_BACKGROUND 50
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#define BT_8822B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70
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#define BT_8822B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55
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#define BT_8822B_1ANT_ANTDET_PSDTHRES_1ANT 35
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#define BT_8822B_1ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */
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#define BT_8822B_1ANT_ANTDET_ENABLE 0
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#define BT_8822B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 0
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#define BT_8822B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000
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* ********************************************/
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#define BT_INFO_8822B_1ANT_B_FTP BIT(7)
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#define BT_INFO_8822B_1ANT_B_A2DP BIT(6)
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#define BT_INFO_8822B_1ANT_B_HID BIT(5)
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#define BT_INFO_8822B_1ANT_B_SCO_BUSY BIT(4)
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#define BT_INFO_8822B_1ANT_B_ACL_BUSY BIT(3)
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#define BT_INFO_8822B_1ANT_B_INQ_PAGE BIT(2)
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#define BT_INFO_8822B_1ANT_B_SCO_ESCO BIT(1)
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#define BT_INFO_8822B_1ANT_B_CONNECTION BIT(0)
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#define BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT 2
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#define BT_8822B_1ANT_WIFI_NOISY_THRESH 150 /* max: 255 */
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#define BT_8822B_1ANT_DEFAULT_ISOLATION 15 /* unit: dB */
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enum bt_8822b_1ant_signal_state {
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BT_8822B_1ANT_SIG_STA_SET_TO_LOW = 0x0,
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BT_8822B_1ANT_SIG_STA_SET_BY_HW = 0x0,
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BT_8822B_1ANT_SIG_STA_SET_TO_HIGH = 0x1,
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BT_8822B_1ANT_SIG_STA_MAX
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BT_8822B_1ANT_GNT_SET_TO_LOW = 0x0,
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BT_8822B_1ANT_GNT_SET_TO_HIGH = 0x1,
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BT_8822B_1ANT_GNT_SET_BY_HW = 0x2,
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BT_8822B_1ANT_GNT_SET_MAX
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};
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enum bt_8822b_1ant_path_ctrl_owner {
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BT_8822B_1ANT_PCO_BTSIDE = 0x0,
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BT_8822B_1ANT_PCO_BTSIDE = 0x0,
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BT_8822B_1ANT_PCO_WLSIDE = 0x1,
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BT_8822B_1ANT_PCO_MAX
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};
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enum bt_8822b_1ant_gnt_ctrl_type {
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BT_8822B_1ANT_GNT_CTRL_BY_PTA = 0x0,
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BT_8822B_1ANT_GNT_CTRL_BY_SW = 0x1,
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BT_8822B_1ANT_GNT_CTRL_BY_PTA = 0x0,
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BT_8822B_1ANT_GNT_CTRL_BY_SW = 0x1,
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BT_8822B_1ANT_GNT_CTRL_MAX
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};
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enum bt_8822b_1ant_gnt_ctrl_block {
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BT_8822B_1ANT_GNT_BLOCK_RFC_BB = 0x0,
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BT_8822B_1ANT_GNT_BLOCK_RFC = 0x1,
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BT_8822B_1ANT_GNT_BLOCK_BB = 0x2,
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BT_8822B_1ANT_GNT_BLOCK_RFC_BB = 0x0,
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BT_8822B_1ANT_GNT_BLOCK_RFC = 0x1,
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BT_8822B_1ANT_GNT_BLOCK_BB = 0x2,
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BT_8822B_1ANT_GNT_BLOCK_MAX
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};
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enum bt_8822b_1ant_lte_coex_table_type {
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BT_8822B_1ANT_CTT_WL_VS_LTE = 0x0,
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BT_8822B_1ANT_CTT_BT_VS_LTE = 0x1,
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BT_8822B_1ANT_CTT_WL_VS_LTE = 0x0,
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BT_8822B_1ANT_CTT_BT_VS_LTE = 0x1,
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BT_8822B_1ANT_CTT_MAX
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};
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enum bt_8822b_1ant_lte_break_table_type {
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BT_8822B_1ANT_LBTT_WL_BREAK_LTE = 0x0,
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BT_8822B_1ANT_LBTT_BT_BREAK_LTE = 0x1,
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BT_8822B_1ANT_LBTT_LTE_BREAK_WL = 0x2,
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BT_8822B_1ANT_LBTT_LTE_BREAK_BT = 0x3,
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BT_8822B_1ANT_LBTT_WL_BREAK_LTE = 0x0,
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BT_8822B_1ANT_LBTT_BT_BREAK_LTE = 0x1,
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BT_8822B_1ANT_LBTT_LTE_BREAK_WL = 0x2,
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BT_8822B_1ANT_LBTT_LTE_BREAK_BT = 0x3,
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BT_8822B_1ANT_LBTT_MAX
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};
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enum bt_info_src_8822b_1ant {
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BT_INFO_SRC_8822B_1ANT_WIFI_FW = 0x0,
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BT_INFO_SRC_8822B_1ANT_BT_RSP = 0x1,
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BT_INFO_SRC_8822B_1ANT_BT_ACTIVE_SEND = 0x2,
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BT_INFO_SRC_8822B_1ANT_MAX
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BT_8822B_1ANT_INFO_SRC_WIFI_FW = 0x0,
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BT_8822B_1ANT_INFO_SRC_BT_RSP = 0x1,
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BT_8822B_1ANT_INFO_SRC_BT_ACT = 0x2,
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BT_8822B_1ANT_INFO_SRC_MAX
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};
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enum bt_8822b_1ant_bt_status {
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BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
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BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
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BT_8822B_1ANT_BT_STATUS_INQ_PAGE = 0x2,
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BT_8822B_1ANT_BT_STATUS_ACL_BUSY = 0x3,
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BT_8822B_1ANT_BT_STATUS_SCO_BUSY = 0x4,
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BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
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BT_8822B_1ANT_BT_STATUS_MAX
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BT_8822B_1ANT_BSTATUS_NCON_IDLE = 0x0,
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BT_8822B_1ANT_BSTATUS_CON_IDLE = 0x1,
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BT_8822B_1ANT_BSTATUS_INQ_PAGE = 0x2,
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BT_8822B_1ANT_BSTATUS_ACL_BUSY = 0x3,
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BT_8822B_1ANT_BSTATUS_SCO_BUSY = 0x4,
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BT_8822B_1ANT_BSTATUS_ACL_SCO_BUSY = 0x5,
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BT_8822B_1ANT_BSTATUS_MAX
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};
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enum bt_8822b_1ant_wifi_status {
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BT_8822B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
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BT_8822B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
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BT_8822B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
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BT_8822B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3,
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BT_8822B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
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BT_8822B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
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BT_8822B_1ANT_WIFI_STATUS_MAX
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BT_8822B_1ANT_WSTATUS_NCON_IDLE = 0x0,
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BT_8822B_1ANT_WSTATUS_NCON_SCAN = 0x1,
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BT_8822B_1ANT_WSTATUS_CON_SCAN = 0x2,
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BT_8822B_1ANT_WSTATUS_CON_SPECPKT = 0x3,
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BT_8822B_1ANT_WSTATUS_CON_IDLE = 0x4,
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BT_8822B_1ANT_WSTATUS_CON_BUSY = 0x5,
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BT_8822B_1ANT_WSTATUS_MAX
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};
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enum bt_8822b_1ant_coex_algo {
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BT_8822B_1ANT_COEX_ALGO_UNDEFINED = 0x0,
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BT_8822B_1ANT_COEX_ALGO_SCO = 0x1,
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BT_8822B_1ANT_COEX_ALGO_HID = 0x2,
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BT_8822B_1ANT_COEX_ALGO_A2DP = 0x3,
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BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
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BT_8822B_1ANT_COEX_ALGO_PANEDR = 0x5,
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BT_8822B_1ANT_COEX_ALGO_PANHS = 0x6,
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BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
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BT_8822B_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
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BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
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BT_8822B_1ANT_COEX_ALGO_HID_A2DP = 0xa,
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BT_8822B_1ANT_COEX_ALGO_NOPROFILEBUSY = 0xb,
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BT_8822B_1ANT_COEX_ALGO_A2DPSINK = 0xc,
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BT_8822B_1ANT_COEX_ALGO_MAX
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BT_8822B_1ANT_COEX_UNDEFINED = 0x0,
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BT_8822B_1ANT_COEX_SCO = 0x1,
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BT_8822B_1ANT_COEX_HID = 0x2,
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BT_8822B_1ANT_COEX_A2DP = 0x3,
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BT_8822B_1ANT_COEX_A2DP_PANHS = 0x4,
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BT_8822B_1ANT_COEX_PAN = 0x5,
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BT_8822B_1ANT_COEX_PANHS = 0x6,
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BT_8822B_1ANT_COEX_PAN_A2DP = 0x7,
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BT_8822B_1ANT_COEX_PAN_HID = 0x8,
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BT_8822B_1ANT_COEX_HID_A2DP_PAN = 0x9,
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BT_8822B_1ANT_COEX_HID_A2DP = 0xa,
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BT_8822B_1ANT_COEX_NOPROFILEBUSY = 0xb,
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BT_8822B_1ANT_COEX_A2DPSINK = 0xc,
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BT_8822B_1ANT_COEX_MAX
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};
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enum bt_8822b_1ant_ext_ant_switch_type {
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BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT = 0x0,
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BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SP3T = 0x1,
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BT_8822B_1ANT_EXT_ANT_SWITCH_MAX
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BT_8822B_1ANT_SWITCH_USE_SPDT = 0x0,
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BT_8822B_1ANT_SWITCH_USE_SP3T = 0x1,
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BT_8822B_1ANT_SWITCH_MAX
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};
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enum bt_8822b_1ant_ext_ant_switch_ctrl_type {
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BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0,
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BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1,
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BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2,
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BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3,
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BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4,
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BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_MAX
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BT_8822B_1ANT_CTRL_BY_BBSW = 0x0,
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BT_8822B_1ANT_CTRL_BY_PTA = 0x1,
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BT_8822B_1ANT_CTRL_BY_ANTDIV = 0x2,
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BT_8822B_1ANT_CTRL_BY_MAC = 0x3,
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BT_8822B_1ANT_CTRL_BY_BT = 0x4,
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BT_8822B_1ANT_CTRL_BY_FW = 0x5,
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BT_8822B_1ANT_CTRL_MAX
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};
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enum bt_8822b_1ant_ext_ant_switch_pos_type {
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BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT = 0x0,
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BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG = 0x1,
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BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA = 0x2,
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BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE = 0x3,
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BT_8822B_1ANT_EXT_ANT_SWITCH_TO_S0WLG_S1BT = 0x4,
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BT_8822B_1ANT_EXT_ANT_SWITCH_TO_MAX
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BT_8822B_1ANT_TO_BT = 0x0,
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BT_8822B_1ANT_TO_WLG = 0x1,
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BT_8822B_1ANT_TO_WLA = 0x2,
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BT_8822B_1ANT_TO_NOCARE = 0x3,
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BT_8822B_1ANT_TO_S0WLG_S1BT = 0x4,
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BT_8822B_1ANT_TO_MAX
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};
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enum bt_8822b_1ant_phase {
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BT_8822B_1ANT_PHASE_COEX_INIT = 0x0,
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BT_8822B_1ANT_PHASE_WLANONLY_INIT = 0x1,
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BT_8822B_1ANT_PHASE_WLAN_OFF = 0x2,
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BT_8822B_1ANT_PHASE_2G_RUNTIME = 0x3,
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BT_8822B_1ANT_PHASE_5G_RUNTIME = 0x4,
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BT_8822B_1ANT_PHASE_BTMPMODE = 0x5,
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BT_8822B_1ANT_PHASE_COEX_POWERON = 0x6,
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BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_WL = 0x7,
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BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_BT = 0x8,
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BT_8822B_1ANT_PHASE_MCC_DUALBAND_RUNTIME = 0x9,
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BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_S0WLS1BT = 0xa,
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BT_8822B_1ANT_PHASE_INIT = 0x0,
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BT_8822B_1ANT_PHASE_WONLY = 0x1,
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BT_8822B_1ANT_PHASE_WOFF = 0x2,
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BT_8822B_1ANT_PHASE_2G = 0x3,
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BT_8822B_1ANT_PHASE_5G = 0x4,
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BT_8822B_1ANT_PHASE_BTMP = 0x5,
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BT_8822B_1ANT_PHASE_POWERON = 0x6,
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BT_8822B_1ANT_PHASE_2G_WL = 0x7,
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BT_8822B_1ANT_PHASE_2G_BT = 0x8,
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BT_8822B_1ANT_PHASE_MCC = 0x9,
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BT_8822B_1ANT_PHASE_2G_WLBT = 0xa, /* GNT_BT/GNT_BT PTA */
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||||
BT_8822B_1ANT_PHASE_2G_FREERUN = 0xb, /* GNT_BT/GNT_BT SW Hi*/
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BT_8822B_1ANT_PHASE_MAX
|
||||
};
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||||
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||||
/*ADD SCOREBOARD TO FIX BT LPS 32K ISSUE WHILE WL BUSY*/
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||||
enum bt_8822b_1ant_Scoreboard {
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||||
BT_8822B_1ANT_SCOREBOARD_ACTIVE = BIT(0),
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||||
BT_8822B_1ANT_SCOREBOARD_ONOFF = BIT(1),
|
||||
BT_8822B_1ANT_SCOREBOARD_SCAN = BIT(2),
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||||
BT_8822B_1ANT_SCOREBOARD_UNDERTEST = BIT(3),
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||||
BT_8822B_1ANT_SCOREBOARD_RXGAIN = BIT(4),
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||||
BT_8822B_1ANT_SCOREBOARD_WLBUSY = BIT(6),
|
||||
BT_8822B_1ANT_SCOREBOARD_EXTFEM = BIT(8),
|
||||
BT_8822B_1ANT_SCOREBOARD_BTCQDDR = BIT(10)
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||||
enum bt_8822b_1ant_scoreboard {
|
||||
BT_8822B_1ANT_SCBD_ACTIVE = BIT(0),
|
||||
BT_8822B_1ANT_SCBD_ONOFF = BIT(1),
|
||||
BT_8822B_1ANT_SCBD_SCAN = BIT(2),
|
||||
BT_8822B_1ANT_SCBD_UNDERTEST = BIT(3),
|
||||
BT_8822B_1ANT_SCBD_RXGAIN = BIT(4),
|
||||
BT_8822B_1ANT_SCBD_WLBUSY = BIT(6),
|
||||
BT_8822B_1ANT_SCBD_EXTFEM = BIT(8),
|
||||
BT_8822B_1ANT_SCBD_CQDDR = BIT(10)
|
||||
};
|
||||
|
||||
enum bt_8822b_1ant_RUNREASON {
|
||||
BT_8822B_1ANT_RSN_2GSCANSTART = 0x0,
|
||||
BT_8822B_1ANT_RSN_5GSCANSTART = 0x1,
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||||
BT_8822B_1ANT_RSN_SCANFINISH = 0x2,
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BT_8822B_1ANT_RSN_2GSWITCHBAND = 0x3,
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BT_8822B_1ANT_RSN_5GSWITCHBAND = 0x4,
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BT_8822B_1ANT_RSN_2GCONSTART = 0x5,
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||||
BT_8822B_1ANT_RSN_5GCONSTART = 0x6,
|
||||
BT_8822B_1ANT_RSN_2GCONFINISH = 0x7,
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||||
BT_8822B_1ANT_RSN_5GCONFINISH = 0x8,
|
||||
BT_8822B_1ANT_RSN_2GMEDIA = 0x9,
|
||||
BT_8822B_1ANT_RSN_5GMEDIA = 0xa,
|
||||
BT_8822B_1ANT_RSN_MEDIADISCON = 0xb,
|
||||
BT_8822B_1ANT_RSN_2GSPECIALPKT = 0xc,
|
||||
BT_8822B_1ANT_RSN_5GSPECIALPKT = 0xd,
|
||||
BT_8822B_1ANT_RSN_BTINFO = 0xe,
|
||||
BT_8822B_1ANT_RSN_PERIODICAL = 0xf,
|
||||
BT_8822B_1ANT_RSN_PNP = 0x10,
|
||||
BT_8822B_1ANT_RSN_LPS = 0x11,
|
||||
BT_8822B_1ANT_RSN_MAX
|
||||
};
|
||||
|
||||
enum bt_8822b_1ant_WL_LINK_MODE {
|
||||
BT_8822B_1ANT_WLINK_2G1PORT = 0x0,
|
||||
BT_8822B_1ANT_WLINK_2GMPORT = 0x1,
|
||||
BT_8822B_1ANT_WLINK_25GMPORT = 0x2,
|
||||
BT_8822B_1ANT_WLINK_5G = 0x3,
|
||||
BT_8822B_1ANT_WLINK_2GGO = 0x4,
|
||||
BT_8822B_1ANT_WLINK_2GGC = 0x5,
|
||||
BT_8822B_1ANT_WLINK_BTMR = 0x6,
|
||||
BT_8822B_1ANT_WLINK_MAX
|
||||
};
|
||||
|
||||
struct coex_dm_8822b_1ant {
|
||||
/* hw setting */
|
||||
u32 pre_ant_pos_type;
|
||||
u32 cur_ant_pos_type;
|
||||
u32 cur_ant_pos_type;
|
||||
/* fw mechanism */
|
||||
boolean cur_ignore_wlan_act;
|
||||
boolean pre_ignore_wlan_act;
|
||||
u8 pre_ps_tdma;
|
||||
u8 cur_ps_tdma;
|
||||
u8 ps_tdma_para[5];
|
||||
u8 ps_tdma_du_adj_type;
|
||||
boolean auto_tdma_adjust;
|
||||
boolean pre_ps_tdma_on;
|
||||
boolean cur_ps_tdma_on;
|
||||
boolean pre_bt_auto_report;
|
||||
boolean cur_bt_auto_report;
|
||||
u8 pre_lps;
|
||||
u8 cur_lps;
|
||||
u8 pre_rpwm;
|
||||
u8 cur_rpwm;
|
||||
u8 pre_bt_dec_pwr_lvl;
|
||||
u8 cur_bt_dec_pwr_lvl;
|
||||
u8 pre_fw_dac_swing_lvl;
|
||||
u8 cur_fw_dac_swing_lvl;
|
||||
boolean cur_ignore_wlan_act;
|
||||
|
||||
u8 cur_ps_tdma;
|
||||
u8 ps_tdma_para[5];
|
||||
boolean auto_tdma_adjust;
|
||||
boolean cur_ps_tdma_on;
|
||||
|
||||
boolean cur_bt_auto_report;
|
||||
u8 cur_lps;
|
||||
u8 cur_rpwm;
|
||||
|
||||
u8 cur_bt_pwr_lvl;
|
||||
u8 cur_wl_pwr_lvl;
|
||||
|
||||
/* sw mechanism */
|
||||
boolean pre_low_penalty_ra;
|
||||
boolean cur_low_penalty_ra;
|
||||
u32 pre_val0x6c0;
|
||||
u32 cur_val0x6c0;
|
||||
u32 pre_val0x6c4;
|
||||
u32 cur_val0x6c4;
|
||||
u32 pre_val0x6c8;
|
||||
u32 cur_val0x6c8;
|
||||
u8 pre_val0x6cc;
|
||||
u8 cur_val0x6cc;
|
||||
boolean limited_dig;
|
||||
|
||||
u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */
|
||||
u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */
|
||||
u16 backup_retry_limit;
|
||||
u8 backup_ampdu_max_time;
|
||||
boolean cur_low_penalty_ra;
|
||||
|
||||
u32 cur_val0x6c0;
|
||||
u32 cur_val0x6c4;
|
||||
u32 cur_val0x6c8;
|
||||
u8 cur_val0x6cc;
|
||||
|
||||
/* algorithm related */
|
||||
u8 pre_algorithm;
|
||||
u8 cur_algorithm;
|
||||
u8 bt_status;
|
||||
u8 wifi_chnl_info[3];
|
||||
u8 cur_algorithm;
|
||||
u8 bt_status;
|
||||
u8 wifi_chnl_info[3];
|
||||
|
||||
u32 pre_ra_mask;
|
||||
u32 cur_ra_mask;
|
||||
u8 pre_arfr_type;
|
||||
u8 cur_arfr_type;
|
||||
u8 pre_retry_limit_type;
|
||||
u8 cur_retry_limit_type;
|
||||
u8 pre_ampdu_time_type;
|
||||
u8 cur_ampdu_time_type;
|
||||
u32 arp_cnt;
|
||||
u32 arp_cnt;
|
||||
|
||||
u32 pre_ext_ant_switch_status;
|
||||
u32 cur_ext_ant_switch_status;
|
||||
u32 cur_switch_status;
|
||||
|
||||
u8 error_condition;
|
||||
boolean pre_agc_table_en;
|
||||
boolean cur_agc_table_en;
|
||||
boolean cur_agc_table_en;
|
||||
u32 setting_tdma;
|
||||
};
|
||||
|
||||
struct coex_sta_8822b_1ant {
|
||||
boolean bt_disabled;
|
||||
boolean bt_link_exist;
|
||||
boolean sco_exist;
|
||||
boolean a2dp_exist;
|
||||
boolean hid_exist;
|
||||
boolean pan_exist;
|
||||
boolean msft_mr_exist;
|
||||
u8 num_of_profile;
|
||||
boolean bt_disabled;
|
||||
boolean bt_link_exist;
|
||||
boolean sco_exist;
|
||||
boolean a2dp_exist;
|
||||
boolean hid_exist;
|
||||
boolean pan_exist;
|
||||
boolean msft_mr_exist;
|
||||
u8 num_of_profile;
|
||||
|
||||
boolean under_lps;
|
||||
boolean under_ips;
|
||||
u32 specific_pkt_period_cnt;
|
||||
u32 high_priority_tx;
|
||||
u32 high_priority_rx;
|
||||
u32 low_priority_tx;
|
||||
u32 low_priority_rx;
|
||||
boolean is_hiPri_rx_overhead;
|
||||
s8 bt_rssi;
|
||||
u8 pre_bt_rssi_state;
|
||||
u8 pre_wifi_rssi_state[4];
|
||||
u8 bt_info_c2h[BT_INFO_SRC_8822B_1ANT_MAX][10];
|
||||
u32 bt_info_c2h_cnt[BT_INFO_SRC_8822B_1ANT_MAX];
|
||||
boolean bt_whck_test;
|
||||
boolean c2h_bt_inquiry_page;
|
||||
boolean c2h_bt_remote_name_req;
|
||||
boolean c2h_bt_page; /* Add for win8.1 page out issue */
|
||||
boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */
|
||||
boolean under_lps;
|
||||
boolean under_ips;
|
||||
u32 specific_pkt_period_cnt;
|
||||
u32 high_priority_tx;
|
||||
u32 high_priority_rx;
|
||||
u32 low_priority_tx;
|
||||
u32 low_priority_rx;
|
||||
boolean is_hi_pri_rx_overhead;
|
||||
s8 bt_rssi;
|
||||
u8 pre_bt_rssi_state;
|
||||
u8 pre_wifi_rssi_state[4];
|
||||
u8 bt_info_c2h[BT_8822B_1ANT_INFO_SRC_MAX][BTC_BTINFO_LENGTH_MAX];
|
||||
u32 bt_info_c2h_cnt[BT_8822B_1ANT_INFO_SRC_MAX];
|
||||
boolean bt_whck_test;
|
||||
boolean c2h_bt_inquiry_page;
|
||||
boolean c2h_bt_remote_name_req;
|
||||
boolean c2h_bt_page; /* Add for win8.1 page out issue */
|
||||
boolean wifi_high_pri_task1;
|
||||
boolean wifi_high_pri_task2;
|
||||
|
||||
u8 bt_info_ext;
|
||||
u8 bt_info_ext2;
|
||||
u32 pop_event_cnt;
|
||||
u8 scan_ap_num;
|
||||
u8 bt_retry_cnt;
|
||||
u8 bt_info_lb2;
|
||||
u8 bt_info_lb3;
|
||||
u8 bt_info_hb0;
|
||||
u8 bt_info_hb1;
|
||||
u8 bt_info_hb2;
|
||||
u8 bt_info_hb3;
|
||||
|
||||
u32 crc_ok_cck;
|
||||
u32 crc_ok_11g;
|
||||
u32 crc_ok_11n;
|
||||
u32 crc_ok_11n_vht;
|
||||
u32 pop_event_cnt;
|
||||
u8 scan_ap_num;
|
||||
u8 bt_retry_cnt;
|
||||
|
||||
u32 crc_err_cck;
|
||||
u32 crc_err_11g;
|
||||
u32 crc_err_11n;
|
||||
u32 crc_err_11n_vht;
|
||||
u32 crc_ok_cck;
|
||||
u32 crc_ok_11g;
|
||||
u32 crc_ok_11n;
|
||||
u32 crc_ok_11n_vht;
|
||||
|
||||
boolean cck_lock;
|
||||
boolean cck_lock_ever;
|
||||
boolean cck_lock_warn;
|
||||
u32 crc_err_cck;
|
||||
u32 crc_err_11g;
|
||||
u32 crc_err_11n;
|
||||
u32 crc_err_11n_vht;
|
||||
|
||||
u8 coex_table_type;
|
||||
boolean cck_lock;
|
||||
boolean cck_lock_ever;
|
||||
boolean cck_lock_warn;
|
||||
|
||||
boolean force_lps_ctrl;
|
||||
u8 coex_table_type;
|
||||
|
||||
boolean concurrent_rx_mode_on;
|
||||
boolean force_lps_ctrl;
|
||||
|
||||
u16 score_board;
|
||||
u8 isolation_btween_wb; /* 0~ 50 */
|
||||
boolean concurrent_rx_mode_on;
|
||||
|
||||
u8 a2dp_bit_pool;
|
||||
u8 cut_version;
|
||||
boolean acl_busy;
|
||||
boolean bt_create_connection;
|
||||
u16 score_board;
|
||||
u8 isolation_btween_wb; /* 0~ 50 */
|
||||
|
||||
u32 bt_coex_supported_feature;
|
||||
u32 bt_coex_supported_version;
|
||||
u8 a2dp_bit_pool;
|
||||
u8 cut_version;
|
||||
boolean acl_busy;
|
||||
boolean bt_create_connection;
|
||||
|
||||
u8 bt_ble_scan_type;
|
||||
u32 bt_ble_scan_para[3];
|
||||
u32 bt_coex_supported_feature;
|
||||
u32 bt_coex_supported_version;
|
||||
|
||||
boolean run_time_state;
|
||||
boolean freeze_coexrun_by_btinfo;
|
||||
u8 bt_ble_scan_type;
|
||||
u32 bt_ble_scan_para[3];
|
||||
|
||||
boolean is_A2DP_3M;
|
||||
boolean voice_over_HOGP;
|
||||
u8 bt_info;
|
||||
boolean is_autoslot;
|
||||
u8 forbidden_slot;
|
||||
u8 hid_busy_num;
|
||||
u8 hid_pair_cnt;
|
||||
boolean run_time_state;
|
||||
boolean freeze_coexrun_by_btinfo;
|
||||
|
||||
u32 cnt_RemoteNameReq;
|
||||
u32 cnt_setupLink;
|
||||
u32 cnt_ReInit;
|
||||
u32 cnt_IgnWlanAct;
|
||||
u32 cnt_Page;
|
||||
u32 cnt_RoleSwitch;
|
||||
boolean is_A2DP_3M;
|
||||
boolean voice_over_HOGP;
|
||||
u8 forbidden_slot;
|
||||
u8 hid_busy_num;
|
||||
u8 hid_pair_cnt;
|
||||
|
||||
u16 bt_reg_vendor_ac;
|
||||
u16 bt_reg_vendor_ae;
|
||||
u32 cnt_remote_name_req;
|
||||
u32 cnt_setup_link;
|
||||
u32 cnt_reinit;
|
||||
u32 cnt_ign_wlan_act;
|
||||
u32 cnt_page;
|
||||
u32 cnt_role_switch;
|
||||
|
||||
boolean is_setupLink;
|
||||
u8 wl_noisy_level;
|
||||
u32 gnt_error_cnt;
|
||||
u8 bt_afh_map[10];
|
||||
u8 bt_relink_downcount;
|
||||
boolean is_tdma_btautoslot;
|
||||
boolean is_tdma_btautoslot_hang;
|
||||
u16 bt_reg_vendor_ac;
|
||||
u16 bt_reg_vendor_ae;
|
||||
|
||||
u8 switch_band_notify_to;
|
||||
boolean is_rf_state_off;
|
||||
boolean is_setup_link;
|
||||
u8 wl_noisy_level;
|
||||
u32 gnt_error_cnt;
|
||||
u8 bt_afh_map[10];
|
||||
u8 bt_relink_downcount;
|
||||
boolean is_tdma_btautoslot;
|
||||
boolean is_tdma_btautoslot_hang;
|
||||
|
||||
boolean is_hid_low_pri_tx_overhead;
|
||||
boolean is_bt_multi_link;
|
||||
boolean is_bt_a2dp_sink;
|
||||
u8 switch_band_notify_to;
|
||||
boolean is_rf_state_off;
|
||||
|
||||
boolean is_set_ps_state_fail;
|
||||
u8 cnt_set_ps_state_fail;
|
||||
boolean is_hid_low_pri_tx_overhead;
|
||||
boolean is_bt_multi_link;
|
||||
boolean is_bt_a2dp_sink;
|
||||
|
||||
u8 wl_fw_dbg_info[10];
|
||||
u8 wl_rx_rate;
|
||||
u8 wl_rts_rx_rate;
|
||||
u8 wl_center_channel;
|
||||
boolean is_set_ps_state_fail;
|
||||
u8 cnt_set_ps_state_fail;
|
||||
|
||||
u16 score_board_WB;
|
||||
boolean is_hid_rcu;
|
||||
u16 legacy_forbidden_slot;
|
||||
u16 le_forbidden_slot;
|
||||
u8 bt_a2dp_vendor_id;
|
||||
u32 bt_a2dp_device_name;
|
||||
boolean is_ble_scan_en;
|
||||
u8 wl_fw_dbg_info[10];
|
||||
u8 wl_rx_rate;
|
||||
u8 wl_tx_rate;
|
||||
u8 wl_rts_rx_rate;
|
||||
u8 wl_center_channel;
|
||||
u8 wl_tx_macid;
|
||||
u8 wl_tx_retry_ratio;
|
||||
|
||||
boolean is_bt_opp_exist;
|
||||
boolean gl_wifi_busy;
|
||||
u16 score_board_WB;
|
||||
boolean is_hid_rcu;
|
||||
u8 bt_a2dp_vendor_id;
|
||||
u32 bt_a2dp_device_name;
|
||||
boolean is_ble_scan_en;
|
||||
|
||||
boolean is_mimo_ps;
|
||||
u8 connect_ap_period_cnt;
|
||||
boolean is_bt_reenable;
|
||||
u8 cnt_bt_reenable;
|
||||
boolean is_bt_opp_exist;
|
||||
boolean gl_wifi_busy;
|
||||
|
||||
boolean is_mimo_ps;
|
||||
u8 connect_ap_period_cnt;
|
||||
boolean is_bt_reenable;
|
||||
u8 cnt_bt_reenable;
|
||||
boolean is_wifi_linkscan_process;
|
||||
u8 wl_coex_mode;
|
||||
|
||||
u8 wl_pnp_wakeup_downcnt;
|
||||
u32 coex_run_cnt;
|
||||
boolean is_no_wl_5ms_extend;
|
||||
|
||||
u16 wl_0x42a_backup;
|
||||
u32 wl_0x430_backup;
|
||||
u32 wl_0x434_backup;
|
||||
u8 wl_0x455_backup;
|
||||
|
||||
boolean wl_tx_limit_en;
|
||||
boolean wl_ampdu_limit_en;
|
||||
boolean wl_rxagg_limit_en;
|
||||
u8 wl_rxagg_size;
|
||||
u8 coex_run_reason;
|
||||
};
|
||||
|
||||
struct rfe_type_8822b_1ant {
|
||||
|
||||
u8 rfe_module_type;
|
||||
boolean ext_ant_switch_exist;
|
||||
u8 ext_ant_switch_type;
|
||||
u8 rfe_module_type;
|
||||
boolean ext_switch_exist;
|
||||
u8 ext_switch_type;
|
||||
/* iF 0: ANTSW(rfe_sel9)=0, ANTSWB(rfe_sel8)=1 => Ant to BT/5G */
|
||||
u8 ext_ant_switch_ctrl_polarity;
|
||||
u8 ext_switch_polarity;
|
||||
};
|
||||
|
||||
|
||||
#define BT_8822B_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */
|
||||
#define BT_8822B_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */
|
||||
#define BT_8822B_1ANT_ANTDET_BUF_LEN 16
|
||||
|
||||
struct psdscan_sta_8822b_1ant {
|
||||
|
||||
u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */
|
||||
u32 ant_det_bt_tx_time;
|
||||
u32 ant_det_pre_psdscan_peak_val;
|
||||
boolean ant_det_is_ant_det_available;
|
||||
u32 ant_det_psd_scan_peak_val;
|
||||
boolean ant_det_is_btreply_available;
|
||||
u32 ant_det_psd_scan_peak_freq;
|
||||
|
||||
u8 ant_det_result;
|
||||
u8 ant_det_peak_val[BT_8822B_1ANT_ANTDET_BUF_LEN];
|
||||
u8 ant_det_peak_freq[BT_8822B_1ANT_ANTDET_BUF_LEN];
|
||||
u32 ant_det_try_count;
|
||||
u32 ant_det_fail_count;
|
||||
u32 ant_det_inteval_count;
|
||||
u32 ant_det_thres_offset;
|
||||
|
||||
u32 real_cent_freq;
|
||||
s32 real_offset;
|
||||
u32 real_span;
|
||||
|
||||
u32 psd_band_width; /* unit: Hz */
|
||||
u32 psd_point; /* 128/256/512/1024 */
|
||||
u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */
|
||||
u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */
|
||||
u32 psd_start_point;
|
||||
u32 psd_stop_point;
|
||||
u32 psd_max_value_point;
|
||||
u32 psd_max_value;
|
||||
u32 psd_start_base;
|
||||
u32 psd_avg_num; /* 1/8/16/32 */
|
||||
u32 psd_gen_count;
|
||||
boolean is_psd_running;
|
||||
boolean is_psd_show_max_only;
|
||||
boolean is_AntDet_running;
|
||||
struct wifi_link_info_8822b_1ant {
|
||||
u8 num_of_active_port;
|
||||
u32 port_connect_status;
|
||||
boolean is_all_under_5g;
|
||||
boolean is_mcc_25g;
|
||||
boolean is_p2p_connected;
|
||||
};
|
||||
|
||||
/* *******************************************
|
||||
* The following is interface which will notify coex module.
|
||||
* ******************************************* */
|
||||
void ex_halbtc8822b1ant_power_on_setting(IN struct btc_coexist *btcoexist);
|
||||
void ex_halbtc8822b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
|
||||
void ex_halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
|
||||
IN boolean wifi_only);
|
||||
void ex_halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist);
|
||||
void ex_halbtc8822b1ant_ips_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 type);
|
||||
void ex_halbtc8822b1ant_lps_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 type);
|
||||
void ex_halbtc8822b1ant_scan_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 type);
|
||||
void ex_halbtc8822b1ant_scan_notify_without_bt(IN struct btc_coexist *btcoexist,
|
||||
IN u8 type);
|
||||
void ex_halbtc8822b1ant_switchband_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 type);
|
||||
void ex_halbtc8822b1ant_switchband_notify_without_bt(IN struct btc_coexist
|
||||
*btcoexist,
|
||||
IN u8 type);
|
||||
void ex_halbtc8822b1ant_connect_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 type);
|
||||
void ex_halbtc8822b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 type);
|
||||
void ex_halbtc8822b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 type);
|
||||
void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 *tmp_buf, IN u8 length);
|
||||
void ex_halbtc8822b1ant_wl_fwdbginfo_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 *tmp_buf, IN u8 length);
|
||||
void ex_halbtc8822b1ant_rx_rate_change_notify(IN struct btc_coexist *btcoexist,
|
||||
IN BOOLEAN is_data_frame, IN u8 btc_rate_id);
|
||||
void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 type);
|
||||
void ex_halbtc8822b1ant_halt_notify(IN struct btc_coexist *btcoexist);
|
||||
void ex_halbtc8822b1ant_pnp_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 pnp_state);
|
||||
void ex_halbtc8822b1ant_ScoreBoardStatusNotify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 *tmp_buf, IN u8 length);
|
||||
void ex_halbtc8822b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist);
|
||||
void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist);
|
||||
void ex_halbtc8822b1ant_display_simple_coex_info(IN struct btc_coexist *btcoexist);
|
||||
|
||||
void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist);
|
||||
void ex_halbtc8822b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
|
||||
IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
|
||||
void ex_halbtc8822b1ant_antenna_isolation(IN struct btc_coexist *btcoexist,
|
||||
IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
|
||||
|
||||
void ex_halbtc8822b1ant_psd_scan(IN struct btc_coexist *btcoexist,
|
||||
IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
|
||||
void ex_halbtc8822b1ant_display_ant_detection(IN struct btc_coexist *btcoexist);
|
||||
|
||||
void ex_halbtc8822b1ant_dbg_control(IN struct btc_coexist *btcoexist,
|
||||
IN u8 op_code, IN u8 op_len, IN u8 *pdata);
|
||||
* ********************************************/
|
||||
void ex_halbtc8822b1ant_power_on_setting(struct btc_coexist *btc);
|
||||
void ex_halbtc8822b1ant_pre_load_firmware(struct btc_coexist *btc);
|
||||
void ex_halbtc8822b1ant_init_hw_config(struct btc_coexist *btc,
|
||||
boolean wifi_only);
|
||||
void ex_halbtc8822b1ant_init_coex_dm(struct btc_coexist *btc);
|
||||
void ex_halbtc8822b1ant_ips_notify(struct btc_coexist *btc, u8 type);
|
||||
void ex_halbtc8822b1ant_lps_notify(struct btc_coexist *btc, u8 type);
|
||||
void ex_halbtc8822b1ant_scan_notify(struct btc_coexist *btc, u8 type);
|
||||
void ex_halbtc8822b1ant_scan_notify_without_bt(struct btc_coexist *btc,
|
||||
u8 type);
|
||||
void ex_halbtc8822b1ant_switchband_notify(struct btc_coexist *btc,
|
||||
u8 type);
|
||||
void ex_halbtc8822b1ant_switchband_notify_without_bt(struct btc_coexist *btc,
|
||||
u8 type);
|
||||
void ex_halbtc8822b1ant_connect_notify(struct btc_coexist *btc, u8 type);
|
||||
void ex_halbtc8822b1ant_media_status_notify(struct btc_coexist *btc,
|
||||
u8 type);
|
||||
void ex_halbtc8822b1ant_specific_packet_notify(struct btc_coexist *btc,
|
||||
u8 type);
|
||||
void ex_halbtc8822b1ant_bt_info_notify(struct btc_coexist *btc,
|
||||
u8 *tmp_buf, u8 length);
|
||||
void ex_halbtc8822b1ant_wl_fwdbginfo_notify(struct btc_coexist *btc,
|
||||
u8 *tmp_buf, u8 length);
|
||||
void ex_halbtc8822b1ant_rx_rate_change_notify(struct btc_coexist *btc,
|
||||
BOOLEAN is_data_frame,
|
||||
u8 btc_rate_id);
|
||||
void ex_halbtc8822b1ant_tx_rate_change_notify(struct btc_coexist *btc,
|
||||
u8 tx_rate,
|
||||
u8 tx_retry_ratio, u8 macid);
|
||||
void ex_halbtc8822b1ant_rf_status_notify(struct btc_coexist *btc, u8 type);
|
||||
void ex_halbtc8822b1ant_halt_notify(struct btc_coexist *btc);
|
||||
void ex_halbtc8822b1ant_pnp_notify(struct btc_coexist *btc, u8 pnp_state);
|
||||
void ex_halbtc8822b1ant_score_board_status_notify(struct btc_coexist *btc,
|
||||
u8 *tmp_buf, u8 length);
|
||||
void ex_halbtc8822b1ant_coex_dm_reset(struct btc_coexist *btc);
|
||||
void ex_halbtc8822b1ant_periodical(struct btc_coexist *btc);
|
||||
void ex_halbtc8822b1ant_display_simple_coex_info(struct btc_coexist *btc);
|
||||
void ex_halbtc8822b1ant_display_coex_info(struct btc_coexist *btc);
|
||||
void ex_halbtc8822b1ant_dbg_control(struct btc_coexist *btc, u8 op_code,
|
||||
u8 op_len, u8 *pdata);
|
||||
|
||||
#else
|
||||
#define ex_halbtc8822b1ant_power_on_setting(btcoexist)
|
||||
#define ex_halbtc8822b1ant_pre_load_firmware(btcoexist)
|
||||
#define ex_halbtc8822b1ant_init_hw_config(btcoexist, wifi_only)
|
||||
#define ex_halbtc8822b1ant_init_coex_dm(btcoexist)
|
||||
#define ex_halbtc8822b1ant_ips_notify(btcoexist, type)
|
||||
#define ex_halbtc8822b1ant_lps_notify(btcoexist, type)
|
||||
#define ex_halbtc8822b1ant_scan_notify(btcoexist, type)
|
||||
#define ex_halbtc8822b1ant_scan_notify_without_bt(btcoexist, type)
|
||||
#define ex_halbtc8822b1ant_switchband_notify(btcoexist, type)
|
||||
#define ex_halbtc8822b1ant_switchband_notify_without_bt(btcoexist, type)
|
||||
#define ex_halbtc8822b1ant_connect_notify(btcoexist, type)
|
||||
#define ex_halbtc8822b1ant_media_status_notify(btcoexist, type)
|
||||
#define ex_halbtc8822b1ant_specific_packet_notify(btcoexist, type)
|
||||
#define ex_halbtc8822b1ant_bt_info_notify(btcoexist, tmp_buf, length)
|
||||
#define ex_halbtc8822b1ant_wl_fwdbginfo_notify(btcoexist, tmp_buf, length)
|
||||
#define ex_halbtc8822b1ant_rx_rate_change_notify(btcoexist, is_data_frame, btc_rate_id)
|
||||
#define ex_halbtc8822b1ant_rf_status_notify(btcoexist, type)
|
||||
#define ex_halbtc8822b1ant_halt_notify(btcoexist)
|
||||
#define ex_halbtc8822b1ant_pnp_notify(btcoexist, pnp_state)
|
||||
#define ex_halbtc8822b1ant_ScoreBoardStatusNotify(btcoexist, tmp_buf, length)
|
||||
#define ex_halbtc8822b1ant_coex_dm_reset(btcoexist)
|
||||
#define ex_halbtc8822b1ant_periodical(btcoexist)
|
||||
#define ex_halbtc8822b1ant_display_coex_info(btcoexist)
|
||||
#define ex_halbtc8822b1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds)
|
||||
#define ex_halbtc8822b1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds)
|
||||
#define ex_halbtc8822b1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds)
|
||||
#define ex_halbtc8822b1ant_display_ant_detection(btcoexist)
|
||||
#define ex_halbtc8822b1ant_dbg_control(btcoexist, op_code, op_len, pdata)
|
||||
#define ex_halbtc8822b1ant_power_on_setting(btc)
|
||||
#define ex_halbtc8822b1ant_pre_load_firmware(btc)
|
||||
#define ex_halbtc8822b1ant_init_hw_config(btc, wifi_only)
|
||||
#define ex_halbtc8822b1ant_init_coex_dm(btc)
|
||||
#define ex_halbtc8822b1ant_ips_notify(btc, type)
|
||||
#define ex_halbtc8822b1ant_lps_notify(btc, type)
|
||||
#define ex_halbtc8822b1ant_scan_notify(btc, type)
|
||||
#define ex_halbtc8822b1ant_scan_notify_without_bt(btc, type)
|
||||
#define ex_halbtc8822b1ant_switchband_notify(btc, type)
|
||||
#define ex_halbtc8822b1ant_switchband_notify_without_bt(btc, type)
|
||||
#define ex_halbtc8822b1ant_connect_notify(btc, type)
|
||||
#define ex_halbtc8822b1ant_media_status_notify(btc, type)
|
||||
#define ex_halbtc8822b1ant_specific_packet_notify(btc, type)
|
||||
#define ex_halbtc8822b1ant_bt_info_notify(btc, tmp_buf, length)
|
||||
#define ex_halbtc8822b1ant_wl_fwdbginfo_notify(btc, tmp_buf, length)
|
||||
#define ex_halbtc8822b1ant_rx_rate_change_notify(btc, is_data_frame, \
|
||||
btc_rate_id)
|
||||
#define ex_halbtc8822b1ant_tx_rate_change_notify(btcoexist, tx_rate, \
|
||||
tx_retry_ratio, macid)
|
||||
#define ex_halbtc8822b1ant_rf_status_notify(btc, type)
|
||||
#define ex_halbtc8822b1ant_halt_notify(btc)
|
||||
#define ex_halbtc8822b1ant_pnp_notify(btc, pnp_state)
|
||||
#define ex_halbtc8822b1ant_score_board_status_notify(btc, tmp_buf, length)
|
||||
#define ex_halbtc8822b1ant_coex_dm_reset(btc)
|
||||
#define ex_halbtc8822b1ant_periodical(btc)
|
||||
#define ex_halbtc8822b1ant_display_coex_info(btc)
|
||||
#define ex_halbtc8822b1ant_dbg_control(btc, op_code, op_len, pdata)
|
||||
#endif
|
||||
#else
|
||||
|
||||
void ex_halbtc8822b1ant_init_hw_config_without_bt(IN struct btc_coexist
|
||||
*btcoexist);
|
||||
void ex_halbtc8822b1ant_switch_band_without_bt(IN struct btc_coexist *btcoexist,
|
||||
IN boolean wifi_only_5g);
|
||||
|
||||
void
|
||||
ex_halbtc8822b1ant_init_hw_config_without_bt(struct btc_coexist *btc);
|
||||
void ex_halbtc8822b1ant_switch_band_without_bt(struct btc_coexist *btc,
|
||||
boolean wifi_only_5g);
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -19,554 +19,489 @@
|
||||
|
||||
/* *******************************************
|
||||
* The following is for 8822B 2Ant BT Co-exist definition
|
||||
* ******************************************* */
|
||||
#define BT_8822B_2ANT_COEX_DBG 0
|
||||
#define BT_AUTO_REPORT_ONLY_8822B_2ANT 1
|
||||
|
||||
|
||||
|
||||
|
||||
#define BT_INFO_8822B_2ANT_B_FTP BIT(7)
|
||||
#define BT_INFO_8822B_2ANT_B_A2DP BIT(6)
|
||||
#define BT_INFO_8822B_2ANT_B_HID BIT(5)
|
||||
#define BT_INFO_8822B_2ANT_B_SCO_BUSY BIT(4)
|
||||
#define BT_INFO_8822B_2ANT_B_ACL_BUSY BIT(3)
|
||||
#define BT_INFO_8822B_2ANT_B_INQ_PAGE BIT(2)
|
||||
#define BT_INFO_8822B_2ANT_B_SCO_ESCO BIT(1)
|
||||
#define BT_INFO_8822B_2ANT_B_CONNECTION BIT(0)
|
||||
|
||||
#define BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT 2
|
||||
* ********************************************/
|
||||
#define BT_INFO_8822B_2ANT_B_FTP BIT(7)
|
||||
#define BT_INFO_8822B_2ANT_B_A2DP BIT(6)
|
||||
#define BT_INFO_8822B_2ANT_B_HID BIT(5)
|
||||
#define BT_INFO_8822B_2ANT_B_SCO_BUSY BIT(4)
|
||||
#define BT_INFO_8822B_2ANT_B_ACL_BUSY BIT(3)
|
||||
#define BT_INFO_8822B_2ANT_B_INQ_PAGE BIT(2)
|
||||
#define BT_INFO_8822B_2ANT_B_SCO_ESCO BIT(1)
|
||||
#define BT_INFO_8822B_2ANT_B_CONNECTION BIT(0)
|
||||
|
||||
#define BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT 2
|
||||
|
||||
/* unit: % WiFi RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation.
|
||||
* (default = 42)
|
||||
*/
|
||||
#define BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 25
|
||||
#define BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 25
|
||||
/* unit: % BT RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation.
|
||||
* (default = 46)
|
||||
*/
|
||||
#define BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1 22
|
||||
#define BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1 22
|
||||
/* unit: % WiFi RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation.
|
||||
* (default = 42)
|
||||
*/
|
||||
#define BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES2 25
|
||||
#define BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES2 25
|
||||
/* unit: % BT RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation.
|
||||
* (default = 46)
|
||||
*/
|
||||
#define BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES2 22
|
||||
#define BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES2 22
|
||||
|
||||
#define BT_8822B_2ANT_DEFAULT_ISOLATION 25 /* unit: dB */
|
||||
#define BT_8822B_2ANT_WIFI_MAX_TX_POWER 15 /* unit: dBm */
|
||||
#define BT_8822B_2ANT_BT_MAX_TX_POWER 3 /* unit: dBm */
|
||||
#define BT_8822B_2ANT_WIFI_SIR_THRES1 -15 /* unit: dB */
|
||||
#define BT_8822B_2ANT_WIFI_SIR_THRES2 -30 /* unit: dB */
|
||||
#define BT_8822B_2ANT_BT_SIR_THRES1 -15 /* unit: dB */
|
||||
#define BT_8822B_2ANT_BT_SIR_THRES2 -30 /* unit: dB */
|
||||
|
||||
|
||||
/* for Antenna detection */
|
||||
#define BT_8822B_2ANT_ANTDET_PSDTHRES_BACKGROUND 50
|
||||
#define BT_8822B_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70
|
||||
#define BT_8822B_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 52
|
||||
#define BT_8822B_2ANT_ANTDET_PSDTHRES_1ANT 40
|
||||
#define BT_8822B_2ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */
|
||||
#define BT_8822B_2ANT_ANTDET_SWEEPPOINT_DELAY 60000
|
||||
#define BT_8822B_2ANT_ANTDET_ENABLE 0
|
||||
#define BT_8822B_2ANT_ANTDET_BTTXTIME 100
|
||||
#define BT_8822B_2ANT_ANTDET_BTTXCHANNEL 39
|
||||
#define BT_8822B_2ANT_ANTDET_PSD_SWWEEPCOUNT 50
|
||||
|
||||
|
||||
#define BT_8822B_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000
|
||||
#define BT_8822B_2ANT_DEFAULT_ISOLATION 25 /* unit: dB */
|
||||
#define BT_8822B_2ANT_WIFI_MAX_TX_POWER 15 /* unit: dBm */
|
||||
#define BT_8822B_2ANT_BT_MAX_TX_POWER 3 /* unit: dBm */
|
||||
#define BT_8822B_2ANT_WIFI_SIR_THRES1 -15 /* unit: dB */
|
||||
#define BT_8822B_2ANT_WIFI_SIR_THRES2 -30 /* unit: dB */
|
||||
#define BT_8822B_2ANT_BT_SIR_THRES1 -15 /* unit: dB */
|
||||
#define BT_8822B_2ANT_BT_SIR_THRES2 -30 /* unit: dB */
|
||||
|
||||
enum bt_8822b_2ant_signal_state {
|
||||
BT_8822B_2ANT_SIG_STA_SET_TO_LOW = 0x0,
|
||||
BT_8822B_2ANT_SIG_STA_SET_BY_HW = 0x0,
|
||||
BT_8822B_2ANT_SIG_STA_SET_TO_HIGH = 0x1,
|
||||
BT_8822B_2ANT_SIG_STA_MAX
|
||||
BT_8822B_2ANT_GNT_SET_TO_LOW = 0x0,
|
||||
BT_8822B_2ANT_GNT_SET_TO_HIGH = 0x1,
|
||||
BT_8822B_2ANT_GNT_SET_BY_HW = 0x2,
|
||||
BT_8822B_2ANT_GNT_SET_MAX
|
||||
};
|
||||
|
||||
enum bt_8822b_2ant_path_ctrl_owner {
|
||||
BT_8822B_2ANT_PCO_BTSIDE = 0x0,
|
||||
BT_8822B_2ANT_PCO_BTSIDE = 0x0,
|
||||
BT_8822B_2ANT_PCO_WLSIDE = 0x1,
|
||||
BT_8822B_2ANT_PCO_MAX
|
||||
};
|
||||
|
||||
enum bt_8822b_2ant_gnt_ctrl_type {
|
||||
BT_8822B_2ANT_GNT_TYPE_CTRL_BY_PTA = 0x0,
|
||||
BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW = 0x1,
|
||||
BT_8822B_2ANT_GNT_TYPE_MAX
|
||||
BT_8822B_2ANT_GNT_CTRL_BY_PTA = 0x0,
|
||||
BT_8822B_2ANT_GNT_CTRL_BY_SW = 0x1,
|
||||
BT_8822B_2ANT_GNT_CTRL_MAX
|
||||
};
|
||||
|
||||
enum bt_8822b_2ant_gnt_ctrl_block {
|
||||
BT_8822B_2ANT_GNT_BLOCK_RFC_BB = 0x0,
|
||||
BT_8822B_2ANT_GNT_BLOCK_RFC = 0x1,
|
||||
BT_8822B_2ANT_GNT_BLOCK_BB = 0x2,
|
||||
BT_8822B_2ANT_GNT_BLOCK_RFC_BB = 0x0,
|
||||
BT_8822B_2ANT_GNT_BLOCK_RFC = 0x1,
|
||||
BT_8822B_2ANT_GNT_BLOCK_BB = 0x2,
|
||||
BT_8822B_2ANT_GNT_BLOCK_MAX
|
||||
};
|
||||
|
||||
enum bt_8822b_2ant_lte_coex_table_type {
|
||||
BT_8822B_2ANT_CTT_WL_VS_LTE = 0x0,
|
||||
BT_8822B_2ANT_CTT_BT_VS_LTE = 0x1,
|
||||
BT_8822B_2ANT_CTT_WL_VS_LTE = 0x0,
|
||||
BT_8822B_2ANT_CTT_BT_VS_LTE = 0x1,
|
||||
BT_8822B_2ANT_CTT_MAX
|
||||
};
|
||||
|
||||
enum bt_8822b_2ant_lte_break_table_type {
|
||||
BT_8822B_2ANT_LBTT_WL_BREAK_LTE = 0x0,
|
||||
BT_8822B_2ANT_LBTT_BT_BREAK_LTE = 0x1,
|
||||
BT_8822B_2ANT_LBTT_LTE_BREAK_WL = 0x2,
|
||||
BT_8822B_2ANT_LBTT_LTE_BREAK_BT = 0x3,
|
||||
BT_8822B_2ANT_LBTT_WL_BREAK_LTE = 0x0,
|
||||
BT_8822B_2ANT_LBTT_BT_BREAK_LTE = 0x1,
|
||||
BT_8822B_2ANT_LBTT_LTE_BREAK_WL = 0x2,
|
||||
BT_8822B_2ANT_LBTT_LTE_BREAK_BT = 0x3,
|
||||
BT_8822B_2ANT_LBTT_MAX
|
||||
};
|
||||
|
||||
enum bt_info_src_8822b_2ant {
|
||||
BT_INFO_SRC_8822B_2ANT_WIFI_FW = 0x0,
|
||||
BT_INFO_SRC_8822B_2ANT_BT_RSP = 0x1,
|
||||
BT_INFO_SRC_8822B_2ANT_BT_ACTIVE_SEND = 0x2,
|
||||
BT_INFO_SRC_8822B_2ANT_MAX
|
||||
BT_8822B_2ANT_INFO_SRC_WIFI_FW = 0x0,
|
||||
BT_8822B_2ANT_INFO_SRC_BT_RSP = 0x1,
|
||||
BT_8822B_2ANT_INFO_SRC_BT_ACT = 0x2,
|
||||
BT_8822B_2ANT_INFO_SRC_MAX
|
||||
};
|
||||
|
||||
enum bt_8822b_2ant_bt_status {
|
||||
BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
|
||||
BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
|
||||
BT_8822B_2ANT_BT_STATUS_INQ_PAGE = 0x2,
|
||||
BT_8822B_2ANT_BT_STATUS_ACL_BUSY = 0x3,
|
||||
BT_8822B_2ANT_BT_STATUS_SCO_BUSY = 0x4,
|
||||
BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
|
||||
BT_8822B_2ANT_BT_STATUS_MAX
|
||||
BT_8822B_2ANT_BSTATUS_NCON_IDLE = 0x0,
|
||||
BT_8822B_2ANT_BSTATUS_CON_IDLE = 0x1,
|
||||
BT_8822B_2ANT_BSTATUS_INQ_PAGE = 0x2,
|
||||
BT_8822B_2ANT_BSTATUS_ACL_BUSY = 0x3,
|
||||
BT_8822B_2ANT_BSTATUS_SCO_BUSY = 0x4,
|
||||
BT_8822B_2ANT_BSTATUS_ACL_SCO_BUSY = 0x5,
|
||||
BT_8822B_2ANT_BSTATUS_MAX
|
||||
};
|
||||
|
||||
enum bt_8822b_2ant_coex_algo {
|
||||
BT_8822B_2ANT_COEX_ALGO_UNDEFINED = 0x0,
|
||||
BT_8822B_2ANT_COEX_ALGO_SCO = 0x1,
|
||||
BT_8822B_2ANT_COEX_ALGO_HID = 0x2,
|
||||
BT_8822B_2ANT_COEX_ALGO_A2DP = 0x3,
|
||||
BT_8822B_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
|
||||
BT_8822B_2ANT_COEX_ALGO_PANEDR = 0x5,
|
||||
BT_8822B_2ANT_COEX_ALGO_PANHS = 0x6,
|
||||
BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
|
||||
BT_8822B_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
|
||||
BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
|
||||
BT_8822B_2ANT_COEX_ALGO_HID_A2DP = 0xa,
|
||||
BT_8822B_2ANT_COEX_ALGO_NOPROFILEBUSY = 0xb,
|
||||
BT_8822B_2ANT_COEX_ALGO_A2DPSINK = 0xc,
|
||||
BT_8822B_2ANT_COEX_ALGO_MAX
|
||||
BT_8822B_2ANT_COEX_UNDEFINED = 0x0,
|
||||
BT_8822B_2ANT_COEX_SCO = 0x1,
|
||||
BT_8822B_2ANT_COEX_HID = 0x2,
|
||||
BT_8822B_2ANT_COEX_A2DP = 0x3,
|
||||
BT_8822B_2ANT_COEX_A2DP_PANHS = 0x4,
|
||||
BT_8822B_2ANT_COEX_PAN = 0x5,
|
||||
BT_8822B_2ANT_COEX_PANHS = 0x6,
|
||||
BT_8822B_2ANT_COEX_PAN_A2DP = 0x7,
|
||||
BT_8822B_2ANT_COEX_PAN_HID = 0x8,
|
||||
BT_8822B_2ANT_COEX_HID_A2DP_PAN = 0x9,
|
||||
BT_8822B_2ANT_COEX_HID_A2DP = 0xa,
|
||||
BT_8822B_2ANT_COEX_NOPROFILEBUSY = 0xb,
|
||||
BT_8822B_2ANT_COEX_A2DPSINK = 0xc,
|
||||
BT_8822B_2ANT_COEX_MAX
|
||||
};
|
||||
|
||||
enum bt_8822b_2ant_ext_ant_switch_type {
|
||||
BT_8822B_2ANT_EXT_ANT_SWITCH_USE_DPDT = 0x0,
|
||||
BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT = 0x1,
|
||||
BT_8822B_2ANT_EXT_ANT_SWITCH_NONE = 0x2,
|
||||
BT_8822B_2ANT_EXT_ANT_SWITCH_MAX
|
||||
BT_8822B_2ANT_SWITCH_USE_DPDT = 0x0,
|
||||
BT_8822B_2ANT_SWITCH_USE_SPDT = 0x1,
|
||||
BT_8822B_2ANT_SWITCH_NONE = 0x2,
|
||||
BT_8822B_2ANT_SWITCH_MAX
|
||||
};
|
||||
|
||||
enum bt_8822b_2ant_ext_ant_switch_ctrl_type {
|
||||
BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0,
|
||||
BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1,
|
||||
BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2,
|
||||
BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3,
|
||||
BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4,
|
||||
BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_MAX
|
||||
BT_8822B_2ANT_CTRL_BY_BBSW = 0x0,
|
||||
BT_8822B_2ANT_CTRL_BY_PTA = 0x1,
|
||||
BT_8822B_2ANT_CTRL_BY_ANTDIV = 0x2,
|
||||
BT_8822B_2ANT_CTRL_BY_MAC = 0x3,
|
||||
BT_8822B_2ANT_CTRL_BY_BT = 0x4,
|
||||
BT_8822B_2ANT_CTRL_BY_FW = 0x5,
|
||||
BT_8822B_2ANT_CTRL_MAX
|
||||
};
|
||||
|
||||
enum bt_8822b_2ant_ext_ant_switch_pos_type {
|
||||
BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT = 0x0,
|
||||
BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG = 0x1,
|
||||
BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLA = 0x2,
|
||||
BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE = 0x3,
|
||||
BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_MAX
|
||||
};
|
||||
|
||||
enum bt_8822b_2ant_ext_band_switch_pos_type {
|
||||
BT_8822B_2ANT_EXT_BAND_SWITCH_TO_WLG = 0x0,
|
||||
BT_8822B_2ANT_EXT_BAND_SWITCH_TO_WLA = 0x1,
|
||||
BT_8822B_2ANT_EXT_BAND_SWITCH_TO_MAX
|
||||
};
|
||||
|
||||
enum bt_8822b_2ant_int_block {
|
||||
BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG = 0x0,
|
||||
BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG = 0x1,
|
||||
BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG = 0x2,
|
||||
BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_MAX
|
||||
BT_8822B_2ANT_SWITCH_MAIN_TO_BT = 0x0,
|
||||
BT_8822B_2ANT_SWITCH_MAIN_TO_WLG = 0x1,
|
||||
BT_8822B_2ANT_SWITCH_MAIN_TO_WLA = 0x2,
|
||||
BT_8822B_2ANT_SWITCH_MAIN_TO_NOCARE = 0x3,
|
||||
BT_8822B_2ANT_SWITCH_MAIN_TO_MAX
|
||||
};
|
||||
|
||||
enum bt_8822b_2ant_phase {
|
||||
BT_8822B_2ANT_PHASE_COEX_INIT = 0x0,
|
||||
BT_8822B_2ANT_PHASE_WLANONLY_INIT = 0x1,
|
||||
BT_8822B_2ANT_PHASE_WLAN_OFF = 0x2,
|
||||
BT_8822B_2ANT_PHASE_2G_RUNTIME = 0x3,
|
||||
BT_8822B_2ANT_PHASE_5G_RUNTIME = 0x4,
|
||||
BT_8822B_2ANT_PHASE_BTMPMODE = 0x5,
|
||||
BT_8822B_2ANT_PHASE_ANTENNA_DET = 0x6,
|
||||
BT_8822B_2ANT_PHASE_COEX_POWERON = 0x7,
|
||||
BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT = 0x8,
|
||||
BT_8822B_2ANT_PHASE_2G_FREERUN = 0x9,
|
||||
BT_8822B_2ANT_PHASE_INIT = 0x0,
|
||||
BT_8822B_2ANT_PHASE_WONLY = 0x1,
|
||||
BT_8822B_2ANT_PHASE_WOFF = 0x2,
|
||||
BT_8822B_2ANT_PHASE_2G = 0x3,
|
||||
BT_8822B_2ANT_PHASE_5G = 0x4,
|
||||
BT_8822B_2ANT_PHASE_BTMP = 0x5,
|
||||
BT_8822B_2ANT_PHASE_ANTDET = 0x6,
|
||||
BT_8822B_2ANT_PHASE_POWERON = 0x7,
|
||||
BT_8822B_2ANT_PHASE_2G_CON = 0x8,
|
||||
BT_8822B_2ANT_PHASE_2G_FREERUN = 0x9,
|
||||
BT_8822B_2ANT_PHASE_MAX
|
||||
};
|
||||
|
||||
/*ADD SCOREBOARD TO FIX BT LPS 32K ISSUE WHILE WL BUSY*/
|
||||
|
||||
enum bt_8822b_2ant_Scoreboard {
|
||||
BT_8822B_2ANT_SCOREBOARD_ACTIVE = BIT(0),
|
||||
BT_8822B_2ANT_SCOREBOARD_ONOFF = BIT(1),
|
||||
BT_8822B_2ANT_SCOREBOARD_SCAN = BIT(2),
|
||||
BT_8822B_2ANT_SCOREBOARD_UNDERTEST = BIT(3),
|
||||
BT_8822B_2ANT_SCOREBOARD_RXGAIN = BIT(4),
|
||||
BT_8822B_2ANT_SCOREBOARD_WLBUSY = BIT(6),
|
||||
BT_8822B_2ANT_SCOREBOARD_EXTFEM = BIT(8),
|
||||
BT_8822B_2ANT_SCOREBOARD_BTCQDDR = BIT(10)
|
||||
enum bt_8822b_2ant_scoreboard {
|
||||
BT_8822B_2ANT_SCBD_ACTIVE = BIT(0),
|
||||
BT_8822B_2ANT_SCBD_ONOFF = BIT(1),
|
||||
BT_8822B_2ANT_SCBD_SCAN = BIT(2),
|
||||
BT_8822B_2ANT_SCBD_UNDERTEST = BIT(3),
|
||||
BT_8822B_2ANT_SCBD_RXGAIN = BIT(4),
|
||||
BT_8822B_2ANT_SCBD_WLBUSY = BIT(6),
|
||||
BT_8822B_2ANT_SCBD_EXTFEM = BIT(8),
|
||||
BT_8822B_2ANT_SCBD_CQDDR = BIT(10)
|
||||
};
|
||||
|
||||
enum bt_8822b_2ant_RUNREASON {
|
||||
BT_8822B_2ANT_RSN_2GSCANSTART = 0x0,
|
||||
BT_8822B_2ANT_RSN_5GSCANSTART = 0x1,
|
||||
BT_8822B_2ANT_RSN_SCANFINISH = 0x2,
|
||||
BT_8822B_2ANT_RSN_2GSWITCHBAND = 0x3,
|
||||
BT_8822B_2ANT_RSN_5GSWITCHBAND = 0x4,
|
||||
BT_8822B_2ANT_RSN_2GCONSTART = 0x5,
|
||||
BT_8822B_2ANT_RSN_5GCONSTART = 0x6,
|
||||
BT_8822B_2ANT_RSN_2GCONFINISH = 0x7,
|
||||
BT_8822B_2ANT_RSN_5GCONFINISH = 0x8,
|
||||
BT_8822B_2ANT_RSN_2GMEDIA = 0x9,
|
||||
BT_8822B_2ANT_RSN_5GMEDIA = 0xa,
|
||||
BT_8822B_2ANT_RSN_MEDIADISCON = 0xb,
|
||||
BT_8822B_2ANT_RSN_2GSPECIALPKT = 0xc,
|
||||
BT_8822B_2ANT_RSN_5GSPECIALPKT = 0xd,
|
||||
BT_8822B_2ANT_RSN_BTINFO = 0xe,
|
||||
BT_8822B_2ANT_RSN_PERIODICAL = 0xf,
|
||||
BT_8822B_2ANT_RSN_PNP = 0x10,
|
||||
BT_8822B_2ANT_RSN_LPS = 0x11,
|
||||
BT_8822B_2ANT_RSN_MAX
|
||||
};
|
||||
|
||||
|
||||
|
||||
enum bt_8822b_2ant_WL_LINK_MODE {
|
||||
BT_8822B_2ANT_WLINK_2G1PORT = 0x0,
|
||||
BT_8822B_2ANT_WLINK_2GMPORT = 0x1,
|
||||
BT_8822B_2ANT_WLINK_25GMPORT = 0x2,
|
||||
BT_8822B_2ANT_WLINK_5G = 0x3,
|
||||
BT_8822B_2ANT_WLINK_2GGO = 0x4,
|
||||
BT_8822B_2ANT_WLINK_2GGC = 0x5,
|
||||
BT_8822B_2ANT_WLINK_BTMR = 0x6,
|
||||
BT_8822B_2ANT_WLINK_MAX
|
||||
};
|
||||
|
||||
struct coex_dm_8822b_2ant {
|
||||
/* hw setting */
|
||||
u32 pre_ant_pos_type;
|
||||
u32 cur_ant_pos_type;
|
||||
u32 cur_ant_pos_type;
|
||||
/* fw mechanism */
|
||||
u8 pre_bt_dec_pwr_lvl;
|
||||
u8 cur_bt_dec_pwr_lvl;
|
||||
u8 pre_fw_dac_swing_lvl;
|
||||
u8 cur_fw_dac_swing_lvl;
|
||||
boolean cur_ignore_wlan_act;
|
||||
boolean pre_ignore_wlan_act;
|
||||
u8 pre_ps_tdma;
|
||||
u8 cur_ps_tdma;
|
||||
u8 ps_tdma_para[5];
|
||||
u8 ps_tdma_du_adj_type;
|
||||
boolean reset_tdma_adjust;
|
||||
boolean pre_ps_tdma_on;
|
||||
boolean cur_ps_tdma_on;
|
||||
boolean pre_bt_auto_report;
|
||||
boolean cur_bt_auto_report;
|
||||
|
||||
u8 cur_bt_pwr_lvl;
|
||||
u8 cur_wl_pwr_lvl;
|
||||
|
||||
boolean cur_ignore_wlan_act;
|
||||
|
||||
u8 cur_ps_tdma;
|
||||
u8 ps_tdma_para[5];
|
||||
boolean cur_ps_tdma_on;
|
||||
|
||||
boolean cur_bt_auto_report;
|
||||
|
||||
/* sw mechanism */
|
||||
boolean pre_rf_rx_lpf_shrink;
|
||||
boolean cur_rf_rx_lpf_shrink;
|
||||
u32 bt_rf_0x1e_backup;
|
||||
boolean pre_low_penalty_ra;
|
||||
boolean cur_low_penalty_ra;
|
||||
boolean pre_dac_swing_on;
|
||||
u32 pre_dac_swing_lvl;
|
||||
boolean cur_dac_swing_on;
|
||||
u32 cur_dac_swing_lvl;
|
||||
boolean pre_adc_back_off;
|
||||
boolean cur_adc_back_off;
|
||||
boolean pre_agc_table_en;
|
||||
boolean cur_agc_table_en;
|
||||
u32 pre_val0x6c0;
|
||||
u32 cur_val0x6c0;
|
||||
u32 pre_val0x6c4;
|
||||
u32 cur_val0x6c4;
|
||||
u32 pre_val0x6c8;
|
||||
u32 cur_val0x6c8;
|
||||
u8 pre_val0x6cc;
|
||||
u8 cur_val0x6cc;
|
||||
boolean limited_dig;
|
||||
boolean cur_low_penalty_ra;
|
||||
boolean cur_agc_table_en;
|
||||
|
||||
u32 cur_val0x6c0;
|
||||
u32 cur_val0x6c4;
|
||||
u32 cur_val0x6c8;
|
||||
u8 cur_val0x6cc;
|
||||
|
||||
/* algorithm related */
|
||||
u8 pre_algorithm;
|
||||
u8 cur_algorithm;
|
||||
u8 bt_status;
|
||||
u8 wifi_chnl_info[3];
|
||||
u8 cur_algorithm;
|
||||
u8 bt_status;
|
||||
u8 wifi_chnl_info[3];
|
||||
|
||||
boolean need_recover0x948;
|
||||
u32 backup0x948;
|
||||
u8 cur_lps;
|
||||
u8 cur_rpwm;
|
||||
|
||||
u8 pre_lps;
|
||||
u8 cur_lps;
|
||||
u8 pre_rpwm;
|
||||
u8 cur_rpwm;
|
||||
boolean is_switch_to_1dot5_ant;
|
||||
u32 arp_cnt;
|
||||
|
||||
boolean is_switch_to_1dot5_ant;
|
||||
u8 switch_thres_offset;
|
||||
u32 arp_cnt;
|
||||
|
||||
u32 pre_ext_ant_switch_status;
|
||||
u32 cur_ext_ant_switch_status;
|
||||
|
||||
u8 pre_ext_band_switch_status;
|
||||
u8 cur_ext_band_switch_status;
|
||||
|
||||
u8 pre_int_block_status;
|
||||
u8 cur_int_block_status;
|
||||
u32 cur_ext_ant_switch_status;
|
||||
u32 setting_tdma;
|
||||
};
|
||||
|
||||
|
||||
struct coex_sta_8822b_2ant {
|
||||
boolean bt_disabled;
|
||||
boolean bt_link_exist;
|
||||
boolean sco_exist;
|
||||
boolean a2dp_exist;
|
||||
boolean hid_exist;
|
||||
boolean pan_exist;
|
||||
boolean bt_disabled;
|
||||
boolean bt_link_exist;
|
||||
boolean sco_exist;
|
||||
boolean a2dp_exist;
|
||||
boolean hid_exist;
|
||||
boolean pan_exist;
|
||||
boolean msft_mr_exist;
|
||||
|
||||
boolean under_lps;
|
||||
boolean under_ips;
|
||||
u32 high_priority_tx;
|
||||
u32 high_priority_rx;
|
||||
u32 low_priority_tx;
|
||||
u32 low_priority_rx;
|
||||
boolean is_hiPri_rx_overhead;
|
||||
u8 bt_rssi;
|
||||
u8 pre_bt_rssi_state;
|
||||
u8 pre_wifi_rssi_state[4];
|
||||
u8 bt_info_c2h[BT_INFO_SRC_8822B_2ANT_MAX][10];
|
||||
u32 bt_info_c2h_cnt[BT_INFO_SRC_8822B_2ANT_MAX];
|
||||
boolean bt_whck_test;
|
||||
boolean c2h_bt_inquiry_page;
|
||||
boolean c2h_bt_remote_name_req;
|
||||
boolean under_lps;
|
||||
boolean under_ips;
|
||||
u32 high_priority_tx;
|
||||
u32 high_priority_rx;
|
||||
u32 low_priority_tx;
|
||||
u32 low_priority_rx;
|
||||
boolean is_hi_pri_rx_overhead;
|
||||
u8 bt_rssi;
|
||||
u8 pre_bt_rssi_state;
|
||||
u8 pre_wifi_rssi_state[4];
|
||||
u8 bt_info_c2h[BT_8822B_2ANT_INFO_SRC_MAX][BTC_BTINFO_LENGTH_MAX];
|
||||
u32 bt_info_c2h_cnt[BT_8822B_2ANT_INFO_SRC_MAX];
|
||||
boolean bt_whck_test;
|
||||
boolean c2h_bt_inquiry_page;
|
||||
boolean c2h_bt_remote_name_req;
|
||||
|
||||
u8 bt_info_ext;
|
||||
u8 bt_info_ext2;
|
||||
u32 pop_event_cnt;
|
||||
u8 scan_ap_num;
|
||||
u8 bt_retry_cnt;
|
||||
u8 bt_info_lb2;
|
||||
u8 bt_info_lb3;
|
||||
u8 bt_info_hb0;
|
||||
u8 bt_info_hb1;
|
||||
u8 bt_info_hb2;
|
||||
u8 bt_info_hb3;
|
||||
|
||||
u32 crc_ok_cck;
|
||||
u32 crc_ok_11g;
|
||||
u32 crc_ok_11n;
|
||||
u32 crc_ok_11n_vht;
|
||||
u32 pop_event_cnt;
|
||||
u8 scan_ap_num;
|
||||
u8 bt_retry_cnt;
|
||||
|
||||
u32 crc_err_cck;
|
||||
u32 crc_err_11g;
|
||||
u32 crc_err_11n;
|
||||
u32 crc_err_11n_vht;
|
||||
u32 crc_ok_cck;
|
||||
u32 crc_ok_11g;
|
||||
u32 crc_ok_11n;
|
||||
u32 crc_ok_11n_vht;
|
||||
|
||||
u32 acc_crc_ratio;
|
||||
u32 now_crc_ratio;
|
||||
u32 crc_err_cck;
|
||||
u32 crc_err_11g;
|
||||
u32 crc_err_11n;
|
||||
u32 crc_err_11n_vht;
|
||||
boolean cck_lock;
|
||||
boolean cck_lock_ever;
|
||||
boolean cck_lock_warn;
|
||||
|
||||
boolean cck_lock;
|
||||
boolean cck_lock_ever;
|
||||
boolean cck_lock_warn;
|
||||
u8 coex_table_type;
|
||||
boolean force_lps_ctrl;
|
||||
|
||||
u8 coex_table_type;
|
||||
boolean force_lps_ctrl;
|
||||
u8 dis_ver_info_cnt;
|
||||
|
||||
u8 dis_ver_info_cnt;
|
||||
u8 a2dp_bit_pool;
|
||||
u8 cut_version;
|
||||
|
||||
u8 a2dp_bit_pool;
|
||||
u8 cut_version;
|
||||
boolean concurrent_rx_mode_on;
|
||||
|
||||
boolean concurrent_rx_mode_on;
|
||||
u16 score_board;
|
||||
u8 isolation_btween_wb; /* 0~ 50 */
|
||||
u8 wifi_coex_thres;
|
||||
u8 bt_coex_thres;
|
||||
u8 wifi_coex_thres2;
|
||||
u8 bt_coex_thres2;
|
||||
|
||||
u16 score_board;
|
||||
u8 isolation_btween_wb; /* 0~ 50 */
|
||||
u8 wifi_coex_thres;
|
||||
u8 bt_coex_thres;
|
||||
u8 wifi_coex_thres2;
|
||||
u8 bt_coex_thres2;
|
||||
u8 num_of_profile;
|
||||
boolean acl_busy;
|
||||
boolean bt_create_connection;
|
||||
boolean wifi_high_pri_task1;
|
||||
boolean wifi_high_pri_task2;
|
||||
u32 specific_pkt_period_cnt;
|
||||
u32 bt_coex_supported_feature;
|
||||
u32 bt_coex_supported_version;
|
||||
|
||||
u8 num_of_profile;
|
||||
boolean acl_busy;
|
||||
boolean bt_create_connection;
|
||||
boolean wifi_is_high_pri_task;
|
||||
u32 specific_pkt_period_cnt;
|
||||
u32 bt_coex_supported_feature;
|
||||
u32 bt_coex_supported_version;
|
||||
u8 bt_ble_scan_type;
|
||||
u32 bt_ble_scan_para[3];
|
||||
|
||||
u8 bt_ble_scan_type;
|
||||
u32 bt_ble_scan_para[3];
|
||||
boolean run_time_state;
|
||||
boolean freeze_coexrun_by_btinfo;
|
||||
|
||||
boolean run_time_state;
|
||||
boolean freeze_coexrun_by_btinfo;
|
||||
boolean is_A2DP_3M;
|
||||
boolean voice_over_HOGP;
|
||||
boolean is_autoslot;
|
||||
u8 forbidden_slot;
|
||||
u8 hid_busy_num;
|
||||
u8 hid_pair_cnt;
|
||||
|
||||
boolean is_A2DP_3M;
|
||||
boolean voice_over_HOGP;
|
||||
u8 bt_info;
|
||||
boolean is_autoslot;
|
||||
u8 forbidden_slot;
|
||||
u8 hid_busy_num;
|
||||
u8 hid_pair_cnt;
|
||||
u32 cnt_remote_name_req;
|
||||
u32 cnt_setup_link;
|
||||
u32 cnt_reinit;
|
||||
u32 cnt_ign_wlan_act;
|
||||
u32 cnt_page;
|
||||
u32 cnt_role_switch;
|
||||
|
||||
u32 cnt_RemoteNameReq;
|
||||
u32 cnt_setupLink;
|
||||
u32 cnt_ReInit;
|
||||
u32 cnt_IgnWlanAct;
|
||||
u32 cnt_Page;
|
||||
u32 cnt_RoleSwitch;
|
||||
u16 bt_reg_vendor_ac;
|
||||
u16 bt_reg_vendor_ae;
|
||||
|
||||
u16 bt_reg_vendor_ac;
|
||||
u16 bt_reg_vendor_ae;
|
||||
boolean is_setup_link;
|
||||
u8 wl_noisy_level;
|
||||
u32 gnt_error_cnt;
|
||||
|
||||
boolean is_setupLink;
|
||||
u8 wl_noisy_level;
|
||||
u32 gnt_error_cnt;
|
||||
u8 bt_afh_map[10];
|
||||
u8 bt_relink_downcount;
|
||||
boolean is_tdma_btautoslot;
|
||||
boolean is_tdma_btautoslot_hang;
|
||||
|
||||
u8 bt_afh_map[10];
|
||||
u8 bt_relink_downcount;
|
||||
boolean is_tdma_btautoslot;
|
||||
boolean is_tdma_btautoslot_hang;
|
||||
boolean is_esco_mode;
|
||||
u8 switch_band_notify_to;
|
||||
boolean is_rf_state_off;
|
||||
|
||||
boolean is_eSCO_mode;
|
||||
u8 switch_band_notify_to;
|
||||
boolean is_rf_state_off;
|
||||
boolean is_hid_low_pri_tx_overhead;
|
||||
boolean is_bt_multi_link;
|
||||
boolean is_bt_a2dp_sink;
|
||||
|
||||
boolean is_hid_low_pri_tx_overhead;
|
||||
boolean is_bt_multi_link;
|
||||
boolean is_bt_a2dp_sink;
|
||||
boolean is_set_ps_state_fail;
|
||||
u8 cnt_set_ps_state_fail;
|
||||
|
||||
boolean is_set_ps_state_fail;
|
||||
u8 cnt_set_ps_state_fail;
|
||||
u8 wl_fw_dbg_info[10];
|
||||
u8 wl_rx_rate;
|
||||
u8 wl_tx_rate;
|
||||
u8 wl_rts_rx_rate;
|
||||
u8 wl_center_channel;
|
||||
u8 wl_tx_macid;
|
||||
u8 wl_tx_retry_ratio;
|
||||
|
||||
u8 wl_fw_dbg_info[10];
|
||||
u8 wl_rx_rate;
|
||||
u8 wl_rts_rx_rate;
|
||||
u8 wl_center_channel;
|
||||
boolean is_2g_freerun;
|
||||
|
||||
boolean is_2g_freerun;
|
||||
u16 score_board_WB;
|
||||
boolean is_hid_rcu;
|
||||
u8 bt_a2dp_vendor_id;
|
||||
u32 bt_a2dp_device_name;
|
||||
boolean is_ble_scan_en;
|
||||
|
||||
u16 score_board_WB;
|
||||
boolean is_hid_rcu;
|
||||
u16 legacy_forbidden_slot;
|
||||
u16 le_forbidden_slot;
|
||||
u8 bt_a2dp_vendor_id;
|
||||
u32 bt_a2dp_device_name;
|
||||
boolean is_ble_scan_en;
|
||||
boolean is_bt_opp_exist;
|
||||
boolean gl_wifi_busy;
|
||||
|
||||
boolean is_bt_opp_exist;
|
||||
boolean gl_wifi_busy;
|
||||
boolean is_mimo_ps;
|
||||
u8 connect_ap_period_cnt;
|
||||
boolean is_bt_reenable;
|
||||
u8 cnt_bt_reenable;
|
||||
boolean is_wifi_linkscan_process;
|
||||
u8 wl_coex_mode;
|
||||
|
||||
u8 wl_pnp_wakeup_downcnt;
|
||||
u32 coex_run_cnt;
|
||||
boolean is_no_wl_5ms_extend;
|
||||
|
||||
u16 wl_0x42a_backup;
|
||||
u32 wl_0x430_backup;
|
||||
u32 wl_0x434_backup;
|
||||
u8 wl_0x455_backup;
|
||||
|
||||
boolean wl_tx_limit_en;
|
||||
boolean wl_ampdu_limit_en;
|
||||
boolean wl_rxagg_limit_en;
|
||||
u8 wl_rxagg_size;
|
||||
u8 coex_run_reason;
|
||||
};
|
||||
|
||||
|
||||
#define BT_8822B_2ANT_EXT_BAND_SWITCH_USE_DPDT 0
|
||||
#define BT_8822B_2ANT_EXT_BAND_SWITCH_USE_SPDT 1
|
||||
|
||||
#define BT_8822B_2ANT_EXT_BAND_SWITCH_USE_DPDT 0
|
||||
#define BT_8822B_2ANT_EXT_BAND_SWITCH_USE_SPDT 1
|
||||
|
||||
struct rfe_type_8822b_2ant {
|
||||
|
||||
u8 rfe_module_type;
|
||||
boolean ext_ant_switch_exist;
|
||||
u8 ext_ant_switch_type; /* 0:DPDT, 1:SPDT */
|
||||
u8 rfe_module_type;
|
||||
boolean ext_switch_exist;
|
||||
u8 ext_switch_type; /* 0:DPDT, 1:SPDT */
|
||||
/* iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */
|
||||
u8 ext_ant_switch_ctrl_polarity;
|
||||
u8 ext_switch_polarity;
|
||||
|
||||
boolean ext_band_switch_exist;
|
||||
u8 ext_band_switch_type; /* 0:DPDT, 1:SPDT */
|
||||
u8 ext_band_switch_ctrl_polarity;
|
||||
boolean ext_band_switch_exist;
|
||||
u8 ext_band_switch_type; /* 0:DPDT, 1:SPDT */
|
||||
u8 ext_band_switch_ctrl_polarity;
|
||||
|
||||
/* If true: WLG at BTG, If false: WLG at WLAG */
|
||||
boolean wlg_Locate_at_btg;
|
||||
/* If TRUE: WLG at BTG, If FALSE: WLG at WLAG */
|
||||
boolean wlg_locate_at_btg;
|
||||
|
||||
boolean ext_ant_switch_diversity; /* If diversity on */
|
||||
boolean ext_ant_switch_diversity; /* If diversity on */
|
||||
};
|
||||
|
||||
#define BT_8822B_2ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */
|
||||
#define BT_8822B_2ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */
|
||||
#define BT_8822B_2ANT_ANTDET_BUF_LEN 16
|
||||
|
||||
struct psdscan_sta_8822b_2ant {
|
||||
|
||||
u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */
|
||||
u32 ant_det_bt_tx_time;
|
||||
u32 ant_det_pre_psdscan_peak_val;
|
||||
boolean ant_det_is_ant_det_available;
|
||||
u32 ant_det_psd_scan_peak_val;
|
||||
boolean ant_det_is_btreply_available;
|
||||
u32 ant_det_psd_scan_peak_freq;
|
||||
|
||||
u8 ant_det_result;
|
||||
u8 ant_det_peak_val[BT_8822B_2ANT_ANTDET_BUF_LEN];
|
||||
u8 ant_det_peak_freq[BT_8822B_2ANT_ANTDET_BUF_LEN];
|
||||
u32 ant_det_try_count;
|
||||
u32 ant_det_fail_count;
|
||||
u32 ant_det_inteval_count;
|
||||
u32 ant_det_thres_offset;
|
||||
|
||||
u32 real_cent_freq;
|
||||
s32 real_offset;
|
||||
u32 real_span;
|
||||
|
||||
u32 psd_band_width; /* unit: Hz */
|
||||
u32 psd_point; /* 128/256/512/1024 */
|
||||
u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */
|
||||
u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */
|
||||
u32 psd_start_point;
|
||||
u32 psd_stop_point;
|
||||
u32 psd_max_value_point;
|
||||
u32 psd_max_value;
|
||||
u32 psd_max_value2;
|
||||
/* filter loop_max_value that below BT_8822B_1ANT_ANTDET_PSDTHRES_1ANT,
|
||||
* and average the rest
|
||||
*/
|
||||
u32 psd_avg_value;
|
||||
/*max value in each loop */
|
||||
u32 psd_loop_max_value[BT_8822B_2ANT_ANTDET_PSD_SWWEEPCOUNT];
|
||||
u32 psd_start_base;
|
||||
u32 psd_avg_num; /* 1/8/16/32 */
|
||||
u32 psd_gen_count;
|
||||
boolean is_AntDet_running;
|
||||
boolean is_psd_show_max_only;
|
||||
struct wifi_link_info_8822b_2ant {
|
||||
u8 num_of_active_port;
|
||||
u32 port_connect_status;
|
||||
boolean is_all_under_5g;
|
||||
boolean is_mcc_25g;
|
||||
boolean is_p2p_connected;
|
||||
};
|
||||
|
||||
|
||||
/* *******************************************
|
||||
* The following is interface which will notify coex module.
|
||||
* ******************************************* */
|
||||
void ex_halbtc8822b2ant_power_on_setting(IN struct btc_coexist *btcoexist);
|
||||
void ex_halbtc8822b2ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
|
||||
void ex_halbtc8822b2ant_init_hw_config(IN struct btc_coexist *btcoexist,
|
||||
IN boolean wifi_only);
|
||||
void ex_halbtc8822b2ant_init_coex_dm(IN struct btc_coexist *btcoexist);
|
||||
void ex_halbtc8822b2ant_ips_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 type);
|
||||
void ex_halbtc8822b2ant_lps_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 type);
|
||||
void ex_halbtc8822b2ant_scan_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 type);
|
||||
void ex_halbtc8822b2ant_switchband_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 type);
|
||||
void ex_halbtc8822b2ant_connect_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 type);
|
||||
void ex_halbtc8822b2ant_media_status_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 type);
|
||||
void ex_halbtc8822b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 type);
|
||||
void ex_halbtc8822b2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 *tmp_buf, IN u8 length);
|
||||
void ex_halbtc8822b2ant_wl_fwdbginfo_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 *tmp_buf, IN u8 length);
|
||||
void ex_halbtc8822b2ant_rx_rate_change_notify(IN struct btc_coexist *btcoexist,
|
||||
IN BOOLEAN is_data_frame, IN u8 btc_rate_id);
|
||||
void ex_halbtc8822b2ant_rf_status_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 type);
|
||||
void ex_halbtc8822b2ant_halt_notify(IN struct btc_coexist *btcoexist);
|
||||
void ex_halbtc8822b2ant_pnp_notify(IN struct btc_coexist *btcoexist,
|
||||
IN u8 pnp_state);
|
||||
void ex_halbtc8822b2ant_periodical(IN struct btc_coexist *btcoexist);
|
||||
void ex_halbtc8822b2ant_display_simple_coex_info(IN struct btc_coexist *btcoexist);
|
||||
|
||||
void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist);
|
||||
void ex_halbtc8822b2ant_antenna_detection(IN struct btc_coexist *btcoexist,
|
||||
IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
|
||||
void ex_halbtc8822b2ant_display_ant_detection(IN struct btc_coexist *btcoexist);
|
||||
|
||||
|
||||
* ********************************************/
|
||||
void ex_halbtc8822b2ant_power_on_setting(struct btc_coexist *btc);
|
||||
void ex_halbtc8822b2ant_pre_load_firmware(struct btc_coexist *btc);
|
||||
void ex_halbtc8822b2ant_init_hw_config(struct btc_coexist *btc,
|
||||
boolean wifi_only);
|
||||
void ex_halbtc8822b2ant_init_coex_dm(struct btc_coexist *btc);
|
||||
void ex_halbtc8822b2ant_ips_notify(struct btc_coexist *btc, u8 type);
|
||||
void ex_halbtc8822b2ant_lps_notify(struct btc_coexist *btc, u8 type);
|
||||
void ex_halbtc8822b2ant_scan_notify(struct btc_coexist *btc, u8 type);
|
||||
void ex_halbtc8822b2ant_switchband_notify(struct btc_coexist *btc,
|
||||
u8 type);
|
||||
void ex_halbtc8822b2ant_connect_notify(struct btc_coexist *btc, u8 type);
|
||||
void ex_halbtc8822b2ant_media_status_notify(struct btc_coexist *btc,
|
||||
u8 type);
|
||||
void ex_halbtc8822b2ant_specific_packet_notify(struct btc_coexist *btc,
|
||||
u8 type);
|
||||
void ex_halbtc8822b2ant_bt_info_notify(struct btc_coexist *btc,
|
||||
u8 *tmp_buf, u8 length);
|
||||
void ex_halbtc8822b2ant_wl_fwdbginfo_notify(struct btc_coexist *btc,
|
||||
u8 *tmp_buf, u8 length);
|
||||
void ex_halbtc8822b2ant_rx_rate_change_notify(struct btc_coexist *btc,
|
||||
BOOLEAN is_data_frame,
|
||||
u8 btc_rate_id);
|
||||
void ex_halbtc8822b2ant_tx_rate_change_notify(struct btc_coexist *btc,
|
||||
u8 tx_rate,
|
||||
u8 tx_retry_ratio, u8 macid);
|
||||
void ex_halbtc8822b2ant_rf_status_notify(struct btc_coexist *btc,
|
||||
u8 type);
|
||||
void ex_halbtc8822b2ant_halt_notify(struct btc_coexist *btc);
|
||||
void ex_halbtc8822b2ant_pnp_notify(struct btc_coexist *btc, u8 pnp_state);
|
||||
void ex_halbtc8822b2ant_periodical(struct btc_coexist *btc);
|
||||
void ex_halbtc8822b2ant_display_simple_coex_info(struct btc_coexist *btc);
|
||||
void ex_halbtc8822b2ant_display_coex_info(struct btc_coexist *btc);
|
||||
#else
|
||||
#define ex_halbtc8822b2ant_power_on_setting(btcoexist)
|
||||
#define ex_halbtc8822b2ant_pre_load_firmware(btcoexist)
|
||||
#define ex_halbtc8822b2ant_init_hw_config(btcoexist, wifi_only)
|
||||
#define ex_halbtc8822b2ant_init_coex_dm(btcoexist)
|
||||
#define ex_halbtc8822b2ant_ips_notify(btcoexist, type)
|
||||
#define ex_halbtc8822b2ant_lps_notify(btcoexist, type)
|
||||
#define ex_halbtc8822b2ant_scan_notify(btcoexist, type)
|
||||
#define ex_halbtc8822b2ant_switchband_notify(btcoexist, type)
|
||||
#define ex_halbtc8822b2ant_connect_notify(btcoexist, type)
|
||||
#define ex_halbtc8822b2ant_media_status_notify(btcoexist, type)
|
||||
#define ex_halbtc8822b2ant_specific_packet_notify(btcoexist, type)
|
||||
#define ex_halbtc8822b2ant_bt_info_notify(btcoexist, tmp_buf, length)
|
||||
#define ex_halbtc8822b2ant_wl_fwdbginfo_notify(btcoexist, tmp_buf, length)
|
||||
#define ex_halbtc8822b2ant_rx_rate_change_notify(btcoexist, is_data_frame, btc_rate_id)
|
||||
#define ex_halbtc8822b2ant_rf_status_notify(btcoexist, type)
|
||||
#define ex_halbtc8822b2ant_halt_notify(btcoexist)
|
||||
#define ex_halbtc8822b2ant_pnp_notify(btcoexist, pnp_state)
|
||||
#define ex_halbtc8822b2ant_periodical(btcoexist)
|
||||
#define ex_halbtc8822b2ant_display_coex_info(btcoexist)
|
||||
#define ex_halbtc8822b2ant_display_ant_detection(btcoexist)
|
||||
#define ex_halbtc8822b2ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds)
|
||||
#define ex_halbtc8822b2ant_display_simple_coex_info(btcoexist)
|
||||
#define ex_halbtc8822b2ant_power_on_setting(btc)
|
||||
#define ex_halbtc8822b2ant_pre_load_firmware(btc)
|
||||
#define ex_halbtc8822b2ant_init_hw_config(btc, wifi_only)
|
||||
#define ex_halbtc8822b2ant_init_coex_dm(btc)
|
||||
#define ex_halbtc8822b2ant_ips_notify(btc, type)
|
||||
#define ex_halbtc8822b2ant_lps_notify(btc, type)
|
||||
#define ex_halbtc8822b2ant_scan_notify(btc, type)
|
||||
#define ex_halbtc8822b2ant_switchband_notify(btc, type)
|
||||
#define ex_halbtc8822b2ant_connect_notify(btc, type)
|
||||
#define ex_halbtc8822b2ant_media_status_notify(btc, type)
|
||||
#define ex_halbtc8822b2ant_specific_packet_notify(btc, type)
|
||||
#define ex_halbtc8822b2ant_bt_info_notify(btc, tmp_buf, length)
|
||||
#define ex_halbtc8822b2ant_wl_fwdbginfo_notify(btc, tmp_buf, length)
|
||||
#define ex_halbtc8822b2ant_rx_rate_change_notify(btc, is_data_frame, \
|
||||
btc_rate_id)
|
||||
#define ex_halbtc8822b2ant_tx_rate_change_notify(btcoexist, tx_rate, \
|
||||
tx_retry_ratio, macid)
|
||||
#define ex_halbtc8822b2ant_rf_status_notify(btc, type)
|
||||
#define ex_halbtc8822b2ant_halt_notify(btc)
|
||||
#define ex_halbtc8822b2ant_pnp_notify(btc, pnp_state)
|
||||
#define ex_halbtc8822b2ant_periodical(btc)
|
||||
#define ex_halbtc8822b2ant_display_coex_info(btc)
|
||||
#define ex_halbtc8822b2ant_display_simple_coex_info(btc)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -35,6 +35,9 @@ ex_hal8822b_wifi_only_hw_config(
|
||||
/*gnt_wl=1 , gnt_bt=0*/
|
||||
halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff, 0x7700);
|
||||
halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff, 0xc00f0038);
|
||||
|
||||
halwifionly_phy_set_bb_reg(pwifionlycfg, 0x6c0, 0xffffffff, 0xaaaaaaaa);
|
||||
halwifionly_phy_set_bb_reg(pwifionlycfg, 0x6c4, 0xffffffff, 0xaaaaaaaa);
|
||||
}
|
||||
|
||||
VOID
|
||||
@@ -55,6 +58,15 @@ ex_hal8822b_wifi_only_switchbandnotify(
|
||||
hal8822b_wifi_only_switch_antenna(pwifionlycfg, is_5g);
|
||||
}
|
||||
|
||||
VOID
|
||||
ex_hal8822b_wifi_only_connectnotify(
|
||||
IN struct wifi_only_cfg *pwifionlycfg,
|
||||
IN u1Byte is_5g
|
||||
)
|
||||
{
|
||||
hal8822b_wifi_only_switch_antenna(pwifionlycfg, is_5g);
|
||||
}
|
||||
|
||||
VOID
|
||||
hal8822b_wifi_only_switch_antenna(IN struct wifi_only_cfg *pwifionlycfg,
|
||||
IN u1Byte is_5g
|
||||
|
||||
@@ -30,6 +30,11 @@ ex_hal8822b_wifi_only_switchbandnotify(
|
||||
IN u1Byte is_5g
|
||||
);
|
||||
VOID
|
||||
ex_hal8822b_wifi_only_connectnotify(
|
||||
IN struct wifi_only_cfg *pwifionlycfg,
|
||||
IN u1Byte is_5g
|
||||
);
|
||||
VOID
|
||||
hal8822b_wifi_only_switch_antenna(IN struct wifi_only_cfg *pwifionlycfg,
|
||||
IN u1Byte is_5g
|
||||
);
|
||||
|
||||
@@ -133,6 +133,9 @@ do {\
|
||||
#define NORMAL_EXEC FALSE
|
||||
#define FORCE_EXEC TRUE
|
||||
|
||||
#define NM_EXCU FALSE
|
||||
#define FC_EXCU TRUE
|
||||
|
||||
#define BTC_RF_OFF 0x0
|
||||
#define BTC_RF_ON 0x1
|
||||
|
||||
@@ -214,6 +217,7 @@ typedef enum _BTC_CHIP_TYPE {
|
||||
/* following is for command line utility */
|
||||
#define CL_SPRINTF rsprintf
|
||||
#define CL_PRINTF DCMD_Printf
|
||||
#define CL_STRNCAT(dst, dst_size, src, src_size) rstrncat(dst, src, src_size)
|
||||
|
||||
struct btc_board_info {
|
||||
/* The following is some board information */
|
||||
@@ -234,6 +238,7 @@ struct btc_board_info {
|
||||
boolean ant_det_result_five_complete;
|
||||
u32 antdetval;
|
||||
u8 customerID;
|
||||
u8 customer_id;
|
||||
};
|
||||
|
||||
typedef enum _BTC_DBG_OPCODE {
|
||||
@@ -271,6 +276,7 @@ typedef enum _BTC_WIFI_ROLE {
|
||||
typedef enum _BTC_WIRELESS_FREQ {
|
||||
BTC_FREQ_2_4G = 0x0,
|
||||
BTC_FREQ_5G = 0x1,
|
||||
BTC_FREQ_25G = 0x2,
|
||||
BTC_FREQ_MAX
|
||||
} BTC_WIRELESS_FREQ, *PBTC_WIRELESS_FREQ;
|
||||
|
||||
@@ -293,6 +299,7 @@ typedef enum _BTC_WIFI_PNP {
|
||||
BTC_WIFI_PNP_WAKE_UP = 0x0,
|
||||
BTC_WIFI_PNP_SLEEP = 0x1,
|
||||
BTC_WIFI_PNP_SLEEP_KEEP_ANT = 0x2,
|
||||
BTC_WIFI_PNP_WOWLAN = 0x3,
|
||||
BTC_WIFI_PNP_MAX
|
||||
} BTC_WIFI_PNP, *PBTC_WIFI_PNP;
|
||||
|
||||
@@ -353,6 +360,7 @@ typedef enum _BTC_GET_TYPE {
|
||||
BTC_GET_BL_WIFI_FW_READY,
|
||||
BTC_GET_BL_WIFI_CONNECTED,
|
||||
BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED,
|
||||
BTC_GET_BL_WIFI_LINK_INFO,
|
||||
BTC_GET_BL_WIFI_BUSY,
|
||||
BTC_GET_BL_WIFI_SCAN,
|
||||
BTC_GET_BL_WIFI_LINK,
|
||||
@@ -366,6 +374,7 @@ typedef enum _BTC_GET_TYPE {
|
||||
BTC_GET_BL_WIFI_IS_IN_MP_MODE,
|
||||
BTC_GET_BL_IS_ASUS_8723B,
|
||||
BTC_GET_BL_RF4CE_CONNECTED,
|
||||
BTC_GET_BL_WIFI_LW_PWR_STATE,
|
||||
|
||||
/* type s4Byte */
|
||||
BTC_GET_S4_WIFI_RSSI,
|
||||
@@ -476,6 +485,7 @@ typedef enum _BTC_NOTIFY_TYPE_SCAN {
|
||||
BTC_SCAN_FINISH = 0x0,
|
||||
BTC_SCAN_START = 0x1,
|
||||
BTC_SCAN_START_2G = 0x2,
|
||||
BTC_SCAN_START_5G = 0x3,
|
||||
BTC_SCAN_MAX
|
||||
} BTC_NOTIFY_TYPE_SCAN, *PBTC_NOTIFY_TYPE_SCAN;
|
||||
typedef enum _BTC_NOTIFY_TYPE_SWITCHBAND {
|
||||
@@ -495,6 +505,7 @@ typedef enum _BTC_NOTIFY_TYPE_ASSOCIATE {
|
||||
typedef enum _BTC_NOTIFY_TYPE_MEDIA_STATUS {
|
||||
BTC_MEDIA_DISCONNECT = 0x0,
|
||||
BTC_MEDIA_CONNECT = 0x1,
|
||||
BTC_MEDIA_CONNECT_5G = 0x02,
|
||||
BTC_MEDIA_MAX
|
||||
} BTC_NOTIFY_TYPE_MEDIA_STATUS, *PBTC_NOTIFY_TYPE_MEDIA_STATUS;
|
||||
typedef enum _BTC_NOTIFY_TYPE_SPECIFIC_PACKET {
|
||||
@@ -523,6 +534,8 @@ typedef enum _BTC_BT_OFFON {
|
||||
BTC_BT_ON = 0x1,
|
||||
} BTC_BTOFFON, *PBTC_BT_OFFON;
|
||||
|
||||
#define BTC_5G_BAND 0x80
|
||||
|
||||
/*==================================================
|
||||
For following block is for coex offload
|
||||
==================================================*/
|
||||
@@ -632,6 +645,49 @@ typedef struct _BTC_OFFLOAD {
|
||||
extern BTC_OFFLOAD gl_coex_offload;
|
||||
/*==================================================*/
|
||||
|
||||
/* BTC_LINK_MODE same as WIFI_LINK_MODE */
|
||||
typedef enum _BTC_LINK_MODE{
|
||||
BTC_LINK_NONE=0,
|
||||
BTC_LINK_ONLY_GO,
|
||||
BTC_LINK_ONLY_GC,
|
||||
BTC_LINK_ONLY_STA,
|
||||
BTC_LINK_ONLY_AP,
|
||||
BTC_LINK_2G_MCC_GO_STA,
|
||||
BTC_LINK_5G_MCC_GO_STA,
|
||||
BTC_LINK_25G_MCC_GO_STA,
|
||||
BTC_LINK_2G_MCC_GC_STA,
|
||||
BTC_LINK_5G_MCC_GC_STA,
|
||||
BTC_LINK_25G_MCC_GC_STA,
|
||||
BTC_LINK_2G_SCC_GO_STA,
|
||||
BTC_LINK_5G_SCC_GO_STA,
|
||||
BTC_LINK_2G_SCC_GC_STA,
|
||||
BTC_LINK_5G_SCC_GC_STA,
|
||||
BTC_LINK_MAX=30
|
||||
}BTC_LINK_MODE, *PBTC_LINK_MODE;
|
||||
|
||||
|
||||
struct btc_wifi_link_info {
|
||||
BTC_LINK_MODE link_mode; /* LinkMode */
|
||||
u1Byte sta_center_channel; /* StaCenterChannel */
|
||||
u1Byte p2p_center_channel; /* P2PCenterChannel */
|
||||
BOOLEAN bany_client_join_go;
|
||||
BOOLEAN benable_noa;
|
||||
BOOLEAN bhotspot;
|
||||
};
|
||||
|
||||
typedef enum _BTC_MULTI_PORT_TDMA_MODE {
|
||||
BTC_MULTI_PORT_TDMA_MODE_NONE=0,
|
||||
BTC_MULTI_PORT_TDMA_MODE_2G_SCC_GO,
|
||||
BTC_MULTI_PORT_TDMA_MODE_2G_P2P_GO,
|
||||
BTC_MULTI_PORT_TDMA_MODE_2G_HOTSPOT_GO
|
||||
} BTC_MULTI_PORT_TDMA_MODE, *PBTC_MULTI_PORT_TDMA_MODE;
|
||||
|
||||
typedef struct btc_multi_port_tdma_info {
|
||||
BTC_MULTI_PORT_TDMA_MODE btc_multi_port_tdma_mode;
|
||||
u1Byte start_time_from_bcn;
|
||||
u1Byte bt_time;
|
||||
} BTC_MULTI_PORT_TDMA_INFO, *PBTC_MULTI_PORT_TDMA_INFO;
|
||||
|
||||
typedef u1Byte
|
||||
(*BFP_BTC_R1)(
|
||||
IN PVOID pBtcContext,
|
||||
@@ -783,6 +839,14 @@ typedef u4Byte
|
||||
IN PVOID pBtcContext
|
||||
);
|
||||
|
||||
typedef u4Byte
|
||||
(*BFP_BTC_SET_ATOMIC) (
|
||||
IN PVOID pBtcContext,
|
||||
IN pu4Byte target,
|
||||
IN u4Byte val
|
||||
);
|
||||
|
||||
|
||||
typedef VOID
|
||||
(*BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD)(
|
||||
IN PVOID pDM_Odm,
|
||||
@@ -913,6 +977,8 @@ struct btc_statistics {
|
||||
u32 cnt_stack_operation_notify;
|
||||
u32 cnt_dbg_ctrl;
|
||||
u32 cnt_rate_id_notify;
|
||||
u32 cnt_halt_notify;
|
||||
u32 cnt_pnp_notify;
|
||||
};
|
||||
|
||||
struct btc_coexist {
|
||||
@@ -922,6 +988,7 @@ struct btc_coexist {
|
||||
struct btc_bt_info bt_info; /*some bt info referenced by non-bt module*/
|
||||
struct btc_stack_info stack_info;
|
||||
struct btc_bt_link_info bt_link_info;
|
||||
struct btc_wifi_link_info wifi_link_info;
|
||||
|
||||
#ifdef CONFIG_RF4CE_COEXIST
|
||||
struct btc_rf4ce_info rf4ce_info;
|
||||
@@ -936,6 +1003,8 @@ struct btc_coexist {
|
||||
pu1Byte cli_buf;
|
||||
struct btc_statistics statistics;
|
||||
u1Byte pwrModeVal[10];
|
||||
BOOLEAN dbg_mode;
|
||||
BOOLEAN auto_report;
|
||||
|
||||
/* function pointers */
|
||||
/* io related */
|
||||
@@ -973,13 +1042,67 @@ struct btc_coexist {
|
||||
BFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE btc_get_bt_coex_supported_feature;
|
||||
BFP_BTC_GET_BT_COEX_SUPPORTED_VERSION btc_get_bt_coex_supported_version;
|
||||
BFP_BTC_GET_PHYDM_VERSION btc_get_bt_phydm_version;
|
||||
BFP_BTC_SET_ATOMIC btc_set_atomic;
|
||||
BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD btc_phydm_modify_RA_PCR_threshold;
|
||||
BTC_PHYDM_CMNINFOQUERY btc_phydm_query_PHY_counter;
|
||||
BTC_PHYDM_MODIFY_ANTDIV_HWSW btc_phydm_modify_ANTDIV_HwSw;
|
||||
BTC_PHYDM_MODIFY_ANTDIV_HWSW btc_phydm_modify_antdiv_hwsw;
|
||||
BFP_BTC_GET_ANT_DET_VAL_FROM_BT btc_get_ant_det_val_from_bt;
|
||||
BFP_BTC_GET_BLE_SCAN_TYPE_FROM_BT btc_get_ble_scan_type_from_bt;
|
||||
BFP_BTC_GET_BLE_SCAN_PARA_FROM_BT btc_get_ble_scan_para_from_bt;
|
||||
BFP_BTC_GET_BT_AFH_MAP_FROM_BT btc_get_bt_afh_map_from_bt;
|
||||
|
||||
union {
|
||||
#ifdef CONFIG_RTL8822B
|
||||
struct coex_dm_8822b_1ant coex_dm_8822b_1ant;
|
||||
struct coex_dm_8822b_2ant coex_dm_8822b_2ant;
|
||||
#endif /* 8822B */
|
||||
#ifdef CONFIG_RTL8821C
|
||||
struct coex_dm_8821c_1ant coex_dm_8821c_1ant;
|
||||
struct coex_dm_8821c_2ant coex_dm_8821c_2ant;
|
||||
#endif /* 8821C */
|
||||
#ifdef CONFIG_RTL8723D
|
||||
struct coex_dm_8723d_1ant coex_dm_8723d_1ant;
|
||||
struct coex_dm_8723d_2ant coex_dm_8723d_2ant;
|
||||
#endif /* 8723D */
|
||||
};
|
||||
|
||||
union {
|
||||
#ifdef CONFIG_RTL8822B
|
||||
struct coex_sta_8822b_1ant coex_sta_8822b_1ant;
|
||||
struct coex_sta_8822b_2ant coex_sta_8822b_2ant;
|
||||
#endif /* 8822B */
|
||||
#ifdef CONFIG_RTL8821C
|
||||
struct coex_sta_8821c_1ant coex_sta_8821c_1ant;
|
||||
struct coex_sta_8821c_2ant coex_sta_8821c_2ant;
|
||||
#endif /* 8821C */
|
||||
#ifdef CONFIG_RTL8723D
|
||||
struct coex_sta_8723d_1ant coex_sta_8723d_1ant;
|
||||
struct coex_sta_8723d_2ant coex_sta_8723d_2ant;
|
||||
#endif /* 8723D */
|
||||
};
|
||||
|
||||
union {
|
||||
#ifdef CONFIG_RTL8822B
|
||||
struct rfe_type_8822b_1ant rfe_type_8822b_1ant;
|
||||
struct rfe_type_8822b_2ant rfe_type_8822b_2ant;
|
||||
#endif /* 8822B */
|
||||
#ifdef CONFIG_RTL8821C
|
||||
struct rfe_type_8821c_1ant rfe_type_8821c_1ant;
|
||||
struct rfe_type_8821c_2ant rfe_type_8821c_2ant;
|
||||
#endif /* 8821C */
|
||||
};
|
||||
|
||||
union {
|
||||
#ifdef CONFIG_RTL8822B
|
||||
struct wifi_link_info_8822b_1ant wifi_link_info_8822b_1ant;
|
||||
struct wifi_link_info_8822b_2ant wifi_link_info_8822b_2ant;
|
||||
#endif /* 8822B */
|
||||
#ifdef CONFIG_RTL8821C
|
||||
struct wifi_link_info_8821c_1ant wifi_link_info_8821c_1ant;
|
||||
struct wifi_link_info_8821c_2ant wifi_link_info_8821c_2ant;
|
||||
#endif /* 8821C */
|
||||
};
|
||||
|
||||
};
|
||||
typedef struct btc_coexist *PBTC_COEXIST;
|
||||
|
||||
|
||||
@@ -22,6 +22,7 @@
|
||||
|
||||
#ifdef PLATFORM_LINUX
|
||||
#define rsprintf snprintf
|
||||
#define rstrncat(dst, src, src_size) strncat(dst, src, src_size)
|
||||
#elif defined(PLATFORM_WINDOWS)
|
||||
#define rsprintf sprintf_s
|
||||
#endif
|
||||
@@ -59,12 +60,14 @@ extern u4Byte GLBtcDbgType[];
|
||||
#define HS_SUPPORT 0
|
||||
#endif
|
||||
|
||||
#include "halbtcoutsrc.h"
|
||||
|
||||
/* for wifi only mode */
|
||||
#include "hal_btcoex_wifionly.h"
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
#define BTC_BTINFO_LENGTH_MAX 10
|
||||
|
||||
struct wifi_only_cfg;
|
||||
struct btc_coexist;
|
||||
|
||||
#ifdef CONFIG_RTL8192E
|
||||
#include "halbtc8192e1ant.h"
|
||||
@@ -108,6 +111,8 @@ extern u4Byte GLBtcDbgType[];
|
||||
#include "halbtc8821c2ant.h"
|
||||
#endif
|
||||
|
||||
#include "halbtcoutsrc.h"
|
||||
|
||||
#else /* CONFIG_BT_COEXIST */
|
||||
|
||||
#ifdef CONFIG_RTL8723B
|
||||
|
||||
@@ -13,7 +13,7 @@
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#if DEV_BUS_TYPE == RT_USB_INTERFACE
|
||||
#ifdef CONFIG_USB_HCI
|
||||
|
||||
#if defined(CONFIG_RTL8188E)
|
||||
#include "rtl8188e/HalEfuseMask8188E_USB.h"
|
||||
@@ -51,6 +51,10 @@
|
||||
#include "rtl8188f/HalEfuseMask8188F_USB.h"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTL8188GTV)
|
||||
#include "rtl8188gtv/HalEfuseMask8188GTV_USB.h"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTL8822B)
|
||||
#include "rtl8822b/HalEfuseMask8822B_USB.h"
|
||||
#endif
|
||||
@@ -58,8 +62,17 @@
|
||||
#if defined(CONFIG_RTL8821C)
|
||||
#include "rtl8821c/HalEfuseMask8821C_USB.h"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTL8710B)
|
||||
#include "rtl8710b/HalEfuseMask8710B_USB.h"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTL8192F)
|
||||
#include "rtl8192f/HalEfuseMask8192F_USB.h"
|
||||
#endif
|
||||
#endif /*CONFIG_USB_HCI*/
|
||||
|
||||
#elif DEV_BUS_TYPE == RT_PCI_INTERFACE
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
|
||||
#if defined(CONFIG_RTL8188E)
|
||||
#include "rtl8188e/HalEfuseMask8188E_PCIE.h"
|
||||
@@ -99,7 +112,11 @@
|
||||
#include "rtl8821c/HalEfuseMask8821C_PCIE.h"
|
||||
#endif
|
||||
|
||||
#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE
|
||||
#if defined(CONFIG_RTL8192F)
|
||||
#include "rtl8192f/HalEfuseMask8192F_PCIE.h"
|
||||
#endif
|
||||
#endif /*CONFIG_PCI_HCI*/
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
#if defined(CONFIG_RTL8723B)
|
||||
#include "rtl8723b/HalEfuseMask8723B_SDIO.h"
|
||||
#endif
|
||||
@@ -116,6 +133,10 @@
|
||||
#include "rtl8188f/HalEfuseMask8188F_SDIO.h"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTL8188GTV)
|
||||
#include "rtl8188gtv/HalEfuseMask8188GTV_SDIO.h"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTL8723D)
|
||||
#include "rtl8723d/HalEfuseMask8723D_SDIO.h"
|
||||
#endif
|
||||
@@ -135,4 +156,9 @@
|
||||
#if defined(CONFIG_RTL8822B)
|
||||
#include "rtl8822b/HalEfuseMask8822B_SDIO.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTL8192F)
|
||||
#include "rtl8192f/HalEfuseMask8192F_SDIO.h"
|
||||
#endif
|
||||
|
||||
#endif /*CONFIG_SDIO_HCI*/
|
||||
|
||||
300
hal/hal_btcoex.c
300
hal/hal_btcoex.c
@@ -71,13 +71,14 @@ const char *const GLBtcWifiBwString[] = {
|
||||
"11bg",
|
||||
"HT20",
|
||||
"HT40",
|
||||
"HT80",
|
||||
"HT160"
|
||||
"VHT80",
|
||||
"VHT160"
|
||||
};
|
||||
|
||||
const char *const GLBtcWifiFreqString[] = {
|
||||
"2.4G",
|
||||
"5G"
|
||||
"5G",
|
||||
"2.4G+5G"
|
||||
};
|
||||
|
||||
const char *const GLBtcIotPeerString[] = {
|
||||
@@ -615,6 +616,112 @@ u32 halbtcoutsrc_GetWifiLinkStatus(PBTC_COEXIST pBtCoexist)
|
||||
return retVal;
|
||||
}
|
||||
|
||||
struct btc_wifi_link_info halbtcoutsrc_getwifilinkinfo(PBTC_COEXIST pBtCoexist)
|
||||
{
|
||||
u8 n_assoc_iface = 0, i =0, mcc_en = _FALSE;
|
||||
PADAPTER adapter = NULL;
|
||||
PADAPTER iface = NULL;
|
||||
PADAPTER sta_iface = NULL, p2p_iface = NULL, ap_iface = NULL;
|
||||
BTC_LINK_MODE btc_link_moe = BTC_LINK_MAX;
|
||||
struct dvobj_priv *dvobj = NULL;
|
||||
struct mlme_ext_priv *mlmeext = NULL;
|
||||
struct btc_wifi_link_info wifi_link_info;
|
||||
|
||||
adapter = (PADAPTER)pBtCoexist->Adapter;
|
||||
dvobj = adapter_to_dvobj(adapter);
|
||||
n_assoc_iface = rtw_mi_get_assoc_if_num(adapter);
|
||||
|
||||
/* init value */
|
||||
wifi_link_info.link_mode = BTC_LINK_NONE;
|
||||
wifi_link_info.sta_center_channel = 0;
|
||||
wifi_link_info.p2p_center_channel = 0;
|
||||
wifi_link_info.bany_client_join_go = _FALSE;
|
||||
wifi_link_info.benable_noa = _FALSE;
|
||||
wifi_link_info.bhotspot = _FALSE;
|
||||
|
||||
for (i = 0; i < dvobj->iface_nums; i++) {
|
||||
iface = dvobj->padapters[i];
|
||||
if (!iface)
|
||||
continue;
|
||||
|
||||
mlmeext = &iface->mlmeextpriv;
|
||||
if (MLME_IS_GO(iface)) {
|
||||
wifi_link_info.link_mode = BTC_LINK_ONLY_GO;
|
||||
wifi_link_info.p2p_center_channel =
|
||||
rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
|
||||
p2p_iface = iface;
|
||||
if (rtw_linked_check(iface))
|
||||
wifi_link_info.bany_client_join_go = _TRUE;
|
||||
} else if (MLME_IS_GC(iface)) {
|
||||
wifi_link_info.link_mode = BTC_LINK_ONLY_GC;
|
||||
wifi_link_info.p2p_center_channel =
|
||||
rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
|
||||
p2p_iface = iface;
|
||||
} else if (MLME_IS_AP(iface)) {
|
||||
wifi_link_info.link_mode = BTC_LINK_ONLY_AP;
|
||||
ap_iface = iface;
|
||||
wifi_link_info.p2p_center_channel =
|
||||
rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
|
||||
} else if (MLME_IS_STA(iface) && rtw_linked_check(iface)) {
|
||||
wifi_link_info.link_mode = BTC_LINK_ONLY_STA;
|
||||
wifi_link_info.sta_center_channel =
|
||||
rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
|
||||
sta_iface = iface;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MCC_MODE
|
||||
if (MCC_EN(adapter)) {
|
||||
if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
|
||||
mcc_en = _TRUE;
|
||||
}
|
||||
#endif/* CONFIG_MCC_MODE */
|
||||
|
||||
if (n_assoc_iface == 0) {
|
||||
wifi_link_info.link_mode = BTC_LINK_NONE;
|
||||
} else if (n_assoc_iface == 1) {
|
||||
/* by pass */
|
||||
} else if (n_assoc_iface == 2) {
|
||||
if (sta_iface && p2p_iface) {
|
||||
u8 band_sta = sta_iface->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;
|
||||
u8 band_p2p = p2p_iface->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;
|
||||
if (band_sta == band_p2p) {
|
||||
switch (band_sta) {
|
||||
case BAND_ON_2_4G:
|
||||
if (MLME_IS_GO(p2p_iface))
|
||||
wifi_link_info.link_mode =
|
||||
mcc_en == _TRUE ? BTC_LINK_2G_MCC_GO_STA : BTC_LINK_2G_SCC_GO_STA;
|
||||
else if (MLME_IS_GC(p2p_iface))
|
||||
wifi_link_info.link_mode =
|
||||
mcc_en == _TRUE ? BTC_LINK_2G_MCC_GC_STA : BTC_LINK_2G_SCC_GC_STA;
|
||||
break;
|
||||
case BAND_ON_5G:
|
||||
if (MLME_IS_GO(p2p_iface))
|
||||
wifi_link_info.link_mode =
|
||||
mcc_en == _TRUE ? BTC_LINK_5G_MCC_GO_STA : BTC_LINK_5G_SCC_GO_STA;
|
||||
else if (MLME_IS_GC(p2p_iface))
|
||||
wifi_link_info.link_mode =
|
||||
mcc_en == _TRUE ? BTC_LINK_5G_MCC_GC_STA : BTC_LINK_5G_SCC_GC_STA;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
if (MLME_IS_GO(p2p_iface))
|
||||
wifi_link_info.link_mode = BTC_LINK_25G_MCC_GO_STA;
|
||||
else if (MLME_IS_GC(p2p_iface))
|
||||
wifi_link_info.link_mode = BTC_LINK_25G_MCC_GC_STA;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (pBtCoexist->board_info.btdm_ant_num == 1)
|
||||
RTW_ERR("%s do not support n_assoc_iface > 2 (ant_num == 1)", __func__);
|
||||
}
|
||||
|
||||
return wifi_link_info;
|
||||
}
|
||||
|
||||
|
||||
static void _btmpoper_timer_hdl(void *p)
|
||||
{
|
||||
if (GLBtcBtMpRptWait == _TRUE) {
|
||||
@@ -900,6 +1007,7 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
|
||||
PADAPTER padapter;
|
||||
PHAL_DATA_TYPE pHalData;
|
||||
struct mlme_ext_priv *mlmeext;
|
||||
struct btc_wifi_link_info *wifi_link_info;
|
||||
u8 bSoftApExist, bVwifiExist;
|
||||
u8 *pu8;
|
||||
s32 *pS4Tmp;
|
||||
@@ -923,6 +1031,7 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
|
||||
pU4Tmp = (u32 *)pOutBuf;
|
||||
pU1Tmp = (u8 *)pOutBuf;
|
||||
pU2Tmp = (u16*)pOutBuf;
|
||||
wifi_link_info = (struct btc_wifi_link_info *)pOutBuf;
|
||||
ret = _TRUE;
|
||||
|
||||
switch (getType) {
|
||||
@@ -1019,6 +1128,11 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
|
||||
#endif
|
||||
break;
|
||||
|
||||
case BTC_GET_BL_WIFI_LW_PWR_STATE:
|
||||
/* return false due to coex do not run during 32K */
|
||||
*pu8 = FALSE;
|
||||
break;
|
||||
|
||||
case BTC_GET_S4_WIFI_RSSI:
|
||||
*pS4Tmp = halbtcoutsrc_GetWifiRssi(padapter);
|
||||
break;
|
||||
@@ -1073,7 +1187,9 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
|
||||
case BTC_GET_U4_WIFI_LINK_STATUS:
|
||||
*pU4Tmp = halbtcoutsrc_GetWifiLinkStatus(pBtCoexist);
|
||||
break;
|
||||
|
||||
case BTC_GET_BL_WIFI_LINK_INFO:
|
||||
*wifi_link_info = halbtcoutsrc_getwifilinkinfo(pBtCoexist);
|
||||
break;
|
||||
case BTC_GET_U4_BT_PATCH_VER:
|
||||
*pU4Tmp = halbtcoutsrc_GetBtPatchVer(pBtCoexist);
|
||||
break;
|
||||
@@ -1668,13 +1784,101 @@ void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist)
|
||||
u8 wifiChnl = 0, wifiP2PChnl = 0, nScanAPNum = 0, FwPSState;
|
||||
u32 iqk_cnt_total = 0, iqk_cnt_ok = 0, iqk_cnt_fail = 0;
|
||||
u16 wifiBcnInterval = 0;
|
||||
PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
|
||||
struct btc_wifi_link_info wifi_link_info;
|
||||
|
||||
wifi_link_info = halbtcoutsrc_getwifilinkinfo(pBtCoexist);
|
||||
|
||||
switch (wifi_link_info.link_mode) {
|
||||
case BTC_LINK_NONE:
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
|
||||
"None", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
|
||||
wifiFreq = hal->current_channel > 14 ? BTC_FREQ_5G : BTC_FREQ_2_4G;
|
||||
break;
|
||||
case BTC_LINK_ONLY_GO:
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
|
||||
"ONLY_GO", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
|
||||
wifiFreq = hal->current_channel > 14 ? BTC_FREQ_5G : BTC_FREQ_2_4G;
|
||||
break;
|
||||
case BTC_LINK_ONLY_GC:
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
|
||||
"ONLY_GC", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
|
||||
wifiFreq = hal->current_channel > 14 ? BTC_FREQ_5G : BTC_FREQ_2_4G;
|
||||
break;
|
||||
case BTC_LINK_ONLY_STA:
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
|
||||
"ONLY_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
|
||||
wifiFreq = hal->current_channel > 14 ? BTC_FREQ_5G : BTC_FREQ_2_4G;
|
||||
break;
|
||||
case BTC_LINK_ONLY_AP:
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
|
||||
"ONLY_AP", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
|
||||
wifiFreq = hal->current_channel > 14 ? BTC_FREQ_5G : BTC_FREQ_2_4G;
|
||||
break;
|
||||
case BTC_LINK_2G_MCC_GO_STA:
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
|
||||
"24G_MCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
|
||||
wifiFreq = BTC_FREQ_2_4G;
|
||||
break;
|
||||
case BTC_LINK_5G_MCC_GO_STA:
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
|
||||
"5G_MCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
|
||||
wifiFreq = BTC_FREQ_5G;
|
||||
break;
|
||||
case BTC_LINK_25G_MCC_GO_STA:
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
|
||||
"2BANDS_MCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
|
||||
wifiFreq = BTC_FREQ_25G;
|
||||
break;
|
||||
case BTC_LINK_2G_MCC_GC_STA:
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
|
||||
"24G_MCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
|
||||
wifiFreq = BTC_FREQ_2_4G;
|
||||
break;
|
||||
case BTC_LINK_5G_MCC_GC_STA:
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
|
||||
"5G_MCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
|
||||
wifiFreq = BTC_FREQ_5G;
|
||||
break;
|
||||
case BTC_LINK_25G_MCC_GC_STA:
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
|
||||
"2BANDS_MCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
|
||||
wifiFreq = BTC_FREQ_25G;
|
||||
break;
|
||||
case BTC_LINK_2G_SCC_GO_STA:
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
|
||||
"24G_SCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
|
||||
wifiFreq = BTC_FREQ_2_4G;
|
||||
break;
|
||||
case BTC_LINK_5G_SCC_GO_STA:
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
|
||||
"5G_SCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
|
||||
wifiFreq = BTC_FREQ_5G;
|
||||
break;
|
||||
case BTC_LINK_2G_SCC_GC_STA:
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
|
||||
"24G_SCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
|
||||
wifiFreq = BTC_FREQ_2_4G;
|
||||
break;
|
||||
case BTC_LINK_5G_SCC_GC_STA:
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
|
||||
"5G_SCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
|
||||
wifiFreq = BTC_FREQ_5G;
|
||||
break;
|
||||
default:
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
|
||||
"UNKNOWN", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
|
||||
wifiFreq = hal->current_channel > 14 ? BTC_FREQ_5G : BTC_FREQ_2_4G;
|
||||
break;
|
||||
}
|
||||
|
||||
CL_PRINTF(cliBuf);
|
||||
|
||||
wifiLinkStatus = halbtcoutsrc_GetWifiLinkStatus(pBtCoexist);
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d (mcc+2band = %d)", "STA/vWifi/HS/p2pGo/p2pGc",
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", "STA/vWifi/HS/p2pGo/p2pGc",
|
||||
((wifiLinkStatus & WIFI_STA_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_AP_CONNECTED) ? 1 : 0),
|
||||
((wifiLinkStatus & WIFI_HS_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_P2P_GO_CONNECTED) ? 1 : 0),
|
||||
((wifiLinkStatus & WIFI_P2P_GC_CONNECTED) ? 1 : 0),
|
||||
halbtcoutsrc_IsDualBandConnected(padapter) ? 1 : 0);
|
||||
((wifiLinkStatus & WIFI_P2P_GC_CONNECTED) ? 1 : 0));
|
||||
CL_PRINTF(cliBuf);
|
||||
|
||||
pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
|
||||
@@ -1698,15 +1902,14 @@ void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist)
|
||||
}
|
||||
|
||||
pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi);
|
||||
pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_WIFI_DOT11_CHNL, &wifiChnl);
|
||||
pBtCoexist->btc_get(pBtCoexist, BTC_GET_U2_BEACON_PERIOD, &wifiBcnInterval);
|
||||
if ((wifiLinkStatus & WIFI_P2P_GO_CONNECTED) || (wifiLinkStatus & WIFI_P2P_GC_CONNECTED))
|
||||
pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_WIFI_P2P_CHNL, &wifiP2PChnl);
|
||||
wifiChnl = wifi_link_info.sta_center_channel;
|
||||
wifiP2PChnl = wifi_link_info.p2p_center_channel;
|
||||
|
||||
CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dBm/ %d/ %d/ %d", "RSSI/ STA_Chnl/ P2P_Chnl/ BI",
|
||||
wifiRssi-100, wifiChnl, wifiP2PChnl, wifiBcnInterval);
|
||||
CL_PRINTF(cliBuf);
|
||||
|
||||
pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifiFreq);
|
||||
pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
|
||||
pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
|
||||
pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
|
||||
@@ -2348,6 +2551,16 @@ u32 halbtcoutsrc_GetPhydmVersion(void *pBtcContext)
|
||||
#ifdef CONFIG_RTL8821C
|
||||
return RELEASE_VERSION_8821C;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8192F
|
||||
return RELEASE_VERSION_8192F;
|
||||
#endif
|
||||
}
|
||||
|
||||
u32 halbtcoutsrc_SetAtomic (void *btc_ctx, u32 *target, u32 val)
|
||||
{
|
||||
*target = val;
|
||||
return _SUCCESS;
|
||||
}
|
||||
|
||||
void halbtcoutsrc_phydm_modify_AntDiv_HwSw(void *pBtcContext, u8 is_hw)
|
||||
@@ -2535,6 +2748,7 @@ void EXhalbtcoutsrc_AntInfoSetting(void *padapter)
|
||||
}
|
||||
|
||||
pBtCoexist->board_info.customerID = RT_CID_DEFAULT;
|
||||
pBtCoexist->board_info.customer_id = RT_CID_DEFAULT;
|
||||
|
||||
/* set default antenna position to main port */
|
||||
pBtCoexist->board_info.btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
|
||||
@@ -2604,9 +2818,10 @@ u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter)
|
||||
pBtCoexist->btc_get_ble_scan_para_from_bt = halbtcoutsrc_GetBleScanParaFromBt;
|
||||
pBtCoexist->btc_get_bt_afh_map_from_bt = halbtcoutsrc_GetBtAFHMapFromBt;
|
||||
pBtCoexist->btc_get_bt_phydm_version = halbtcoutsrc_GetPhydmVersion;
|
||||
pBtCoexist->btc_set_atomic= halbtcoutsrc_SetAtomic;
|
||||
pBtCoexist->btc_phydm_modify_RA_PCR_threshold = halbtcoutsrc_phydm_modify_RA_PCR_threshold;
|
||||
pBtCoexist->btc_phydm_query_PHY_counter = halbtcoutsrc_phydm_query_PHY_counter;
|
||||
pBtCoexist->btc_phydm_modify_ANTDIV_HwSw = halbtcoutsrc_phydm_modify_AntDiv_HwSw;
|
||||
pBtCoexist->btc_phydm_modify_antdiv_hwsw = halbtcoutsrc_phydm_modify_AntDiv_HwSw;
|
||||
|
||||
pBtCoexist->cli_buf = &GLBtcDbgBuf[0];
|
||||
|
||||
@@ -2798,10 +3013,6 @@ void EXhalbtcoutsrc_init_hw_config(PBTC_COEXIST pBtCoexist, u8 bWifiOnly)
|
||||
ex_halbtc8822b1ant_init_hw_config(pBtCoexist, bWifiOnly);
|
||||
else if (pBtCoexist->board_info.btdm_ant_num == 2)
|
||||
ex_halbtc8822b2ant_init_hw_config(pBtCoexist, bWifiOnly);
|
||||
#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
|
||||
rtw_hal_set_default_port_id_cmd(pBtCoexist->Adapter, 0);
|
||||
rtw_hal_set_wifi_port_id_cmd(pBtCoexist->Adapter);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -2811,10 +3022,6 @@ void EXhalbtcoutsrc_init_hw_config(PBTC_COEXIST pBtCoexist, u8 bWifiOnly)
|
||||
ex_halbtc8821c2ant_init_hw_config(pBtCoexist, bWifiOnly);
|
||||
else if (pBtCoexist->board_info.btdm_ant_num == 1)
|
||||
ex_halbtc8821c1ant_init_hw_config(pBtCoexist, bWifiOnly);
|
||||
#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
|
||||
rtw_hal_set_default_port_id_cmd(pBtCoexist->Adapter, 0);
|
||||
rtw_hal_set_wifi_port_id_cmd(pBtCoexist->Adapter);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
}
|
||||
@@ -3293,7 +3500,9 @@ void EXhalbtcoutsrc_connect_notify(PBTC_COEXIST pBtCoexist, u8 assoType)
|
||||
|
||||
void EXhalbtcoutsrc_media_status_notify(PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS mediaStatus)
|
||||
{
|
||||
u8 mStatus;
|
||||
u8 mStatus = BTC_MEDIA_MAX;
|
||||
PADAPTER adapter = (PADAPTER)pBtCoexist->Adapter;
|
||||
HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
|
||||
|
||||
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
|
||||
return;
|
||||
@@ -3302,15 +3511,25 @@ void EXhalbtcoutsrc_media_status_notify(PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS
|
||||
if (pBtCoexist->manual_control)
|
||||
return;
|
||||
|
||||
if (RT_MEDIA_CONNECT == mediaStatus)
|
||||
mStatus = BTC_MEDIA_CONNECT;
|
||||
else
|
||||
if (RT_MEDIA_CONNECT == mediaStatus) {
|
||||
if (hal->current_band_type == BAND_ON_2_4G)
|
||||
mStatus = BTC_MEDIA_CONNECT;
|
||||
else if (hal->current_band_type == BAND_ON_5G)
|
||||
mStatus = BTC_MEDIA_CONNECT_5G;
|
||||
else {
|
||||
mStatus = BTC_MEDIA_CONNECT;
|
||||
RTW_ERR("%s unknow band type\n", __func__);
|
||||
}
|
||||
} else
|
||||
mStatus = BTC_MEDIA_DISCONNECT;
|
||||
|
||||
/* All notify is called in cmd thread, don't need to leave low power again
|
||||
* halbtcoutsrc_LeaveLowPower(pBtCoexist); */
|
||||
if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
|
||||
#ifdef CONFIG_RTL8821A
|
||||
/* compatible for 8821A */
|
||||
if (mStatus == BTC_MEDIA_CONNECT_5G)
|
||||
mStatus = BTC_MEDIA_CONNECT;
|
||||
if (pBtCoexist->board_info.btdm_ant_num == 2)
|
||||
ex_halbtc8821a2ant_media_status_notify(pBtCoexist, mStatus);
|
||||
else if (pBtCoexist->board_info.btdm_ant_num == 1)
|
||||
@@ -3354,6 +3573,9 @@ void EXhalbtcoutsrc_media_status_notify(PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS
|
||||
|
||||
#ifdef CONFIG_RTL8812A
|
||||
else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
|
||||
/* compatible for 8812A */
|
||||
if (mStatus == BTC_MEDIA_CONNECT_5G)
|
||||
mStatus = BTC_MEDIA_CONNECT;
|
||||
if (pBtCoexist->board_info.btdm_ant_num == 2)
|
||||
ex_halbtc8812a2ant_media_status_notify(pBtCoexist, mStatus);
|
||||
else if (pBtCoexist->board_info.btdm_ant_num == 1)
|
||||
@@ -3384,7 +3606,9 @@ void EXhalbtcoutsrc_media_status_notify(PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS
|
||||
|
||||
void EXhalbtcoutsrc_specific_packet_notify(PBTC_COEXIST pBtCoexist, u8 pktType)
|
||||
{
|
||||
u8 packetType;
|
||||
u8 packetType;
|
||||
PADAPTER adapter = (PADAPTER)pBtCoexist->Adapter;
|
||||
HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
|
||||
|
||||
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
|
||||
return;
|
||||
@@ -3403,10 +3627,17 @@ void EXhalbtcoutsrc_specific_packet_notify(PBTC_COEXIST pBtCoexist, u8 pktType)
|
||||
return;
|
||||
}
|
||||
|
||||
if (hal->current_band_type == BAND_ON_5G)
|
||||
packetType |= BTC_5G_BAND;
|
||||
|
||||
/* All notify is called in cmd thread, don't need to leave low power again
|
||||
* halbtcoutsrc_LeaveLowPower(pBtCoexist); */
|
||||
if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
|
||||
#ifdef CONFIG_RTL8821A
|
||||
/* compatible for 8821A */
|
||||
if (hal->current_band_type == BAND_ON_5G)
|
||||
packetType &= ~BTC_5G_BAND;
|
||||
|
||||
if (pBtCoexist->board_info.btdm_ant_num == 2)
|
||||
ex_halbtc8821a2ant_specific_packet_notify(pBtCoexist, packetType);
|
||||
else if (pBtCoexist->board_info.btdm_ant_num == 1)
|
||||
@@ -3450,6 +3681,10 @@ void EXhalbtcoutsrc_specific_packet_notify(PBTC_COEXIST pBtCoexist, u8 pktType)
|
||||
|
||||
#ifdef CONFIG_RTL8812A
|
||||
else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
|
||||
/* compatible for 8812A */
|
||||
if (hal->current_band_type == BAND_ON_5G)
|
||||
packetType &= ~BTC_5G_BAND;
|
||||
|
||||
if (pBtCoexist->board_info.btdm_ant_num == 2)
|
||||
ex_halbtc8812a2ant_specific_packet_notify(pBtCoexist, packetType);
|
||||
else if (pBtCoexist->board_info.btdm_ant_num == 1)
|
||||
@@ -3705,6 +3940,8 @@ void EXhalbtcoutsrc_halt_notify(PBTC_COEXIST pBtCoexist)
|
||||
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
|
||||
return;
|
||||
|
||||
pBtCoexist->statistics.cnt_halt_notify++;
|
||||
|
||||
if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
|
||||
#ifdef CONFIG_RTL8821A
|
||||
if (pBtCoexist->board_info.btdm_ant_num == 2)
|
||||
@@ -3792,6 +4029,8 @@ void EXhalbtcoutsrc_pnp_notify(PBTC_COEXIST pBtCoexist, u8 pnpState)
|
||||
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
|
||||
return;
|
||||
|
||||
pBtCoexist->statistics.cnt_pnp_notify++;
|
||||
|
||||
/* */
|
||||
/* currently only 1ant we have to do the notification, */
|
||||
/* once pnp is notified to sleep state, we have to leave LPS that we can sleep normally. */
|
||||
@@ -4292,15 +4531,6 @@ void EXhalbtcoutsrc_DisplayAntDetection(PBTC_COEXIST pBtCoexist)
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RTL8821C
|
||||
else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
|
||||
if (pBtCoexist->board_info.btdm_ant_num == 2)
|
||||
ex_halbtc8821c2ant_display_ant_detection(pBtCoexist);
|
||||
else if (pBtCoexist->board_info.btdm_ant_num == 1)
|
||||
ex_halbtc8821c1ant_display_ant_detection(pBtCoexist);
|
||||
}
|
||||
#endif
|
||||
|
||||
halbtcoutsrc_NormalLowPower(pBtCoexist);
|
||||
}
|
||||
|
||||
@@ -4910,7 +5140,7 @@ void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state)
|
||||
case BTCOEX_SUSPEND_STATE_RESUME:
|
||||
#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
|
||||
/* re-download FW after resume, inform WL FW port number */
|
||||
rtw_hal_set_wifi_port_id_cmd(GLBtCoexist.Adapter);
|
||||
rtw_hal_set_wifi_btc_port_id_cmd(GLBtCoexist.Adapter);
|
||||
#endif
|
||||
EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_WAKE_UP);
|
||||
break;
|
||||
|
||||
@@ -144,6 +144,26 @@ void hal_btcoex_wifionly_scan_notify(PADAPTER padapter)
|
||||
#endif
|
||||
}
|
||||
|
||||
void hal_btcoex_wifionly_connect_notify(PADAPTER padapter)
|
||||
{
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
|
||||
u8 is_5g = _FALSE;
|
||||
|
||||
if (pHalData->current_band_type == BAND_ON_5G)
|
||||
is_5g = _TRUE;
|
||||
|
||||
if (IS_HARDWARE_TYPE_8822B(padapter)) {
|
||||
#ifdef CONFIG_RTL8822B
|
||||
ex_hal8822b_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RTL8821C
|
||||
else if (IS_HARDWARE_TYPE_8821C(padapter))
|
||||
ex_hal8821c_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);
|
||||
#endif
|
||||
}
|
||||
|
||||
void hal_btcoex_wifionly_hw_config(PADAPTER padapter)
|
||||
{
|
||||
struct wifi_only_cfg *pwifionlycfg = &GLBtCoexistWifiOnly;
|
||||
|
||||
2960
hal/hal_com.c
2960
hal/hal_com.c
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
497
hal/hal_dm.c
497
hal/hal_dm.c
@@ -169,38 +169,123 @@ void record_ra_info(void *p_dm_void, u8 macid, struct cmn_sta_info *p_sta, u64 r
|
||||
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
|
||||
struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
|
||||
|
||||
rtw_macid_ctl_set_bw(macid_ctl, macid, p_sta->ra_info.ra_bw_mode);
|
||||
rtw_macid_ctl_set_vht_en(macid_ctl, macid, p_sta->ra_info.is_vht_enable);
|
||||
rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, ra_mask);
|
||||
rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, ra_mask >> 32);
|
||||
if (p_sta) {
|
||||
rtw_macid_ctl_set_bw(macid_ctl, macid, p_sta->ra_info.ra_bw_mode);
|
||||
rtw_macid_ctl_set_vht_en(macid_ctl, macid, p_sta->ra_info.is_vht_enable);
|
||||
rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, ra_mask);
|
||||
rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, ra_mask >> 32);
|
||||
|
||||
rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
|
||||
rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
|
||||
void rtw_phydm_fill_desc_dpt(void *dm, u8 *desc, u8 dpt_lv)
|
||||
{
|
||||
struct dm_struct *p_dm = (struct dm_struct *)dm;
|
||||
_adapter *adapter = p_dm->adapter;
|
||||
|
||||
switch (rtw_get_chip_type(adapter)) {
|
||||
/*
|
||||
#ifdef CONFIG_RTL8188F
|
||||
case RTL8188F:
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8723B
|
||||
case RTL8723B :
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8703B
|
||||
case RTL8703B :
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8812A
|
||||
case RTL8812 :
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8821A
|
||||
case RTL8821:
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8814A
|
||||
case RTL8814A :
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8192F
|
||||
case RTL8192F :
|
||||
break;
|
||||
#endif
|
||||
*/
|
||||
/*
|
||||
#ifdef CONFIG_RTL8192E
|
||||
case RTL8192E :
|
||||
SET_TX_DESC_TX_POWER_0_PSET_92E(desc, dpt_lv);
|
||||
break;
|
||||
#endif
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_RTL8821C
|
||||
case RTL8821C :
|
||||
SET_TX_DESC_TXPWR_OFSET_8821C(desc, dpt_lv);
|
||||
break;
|
||||
#endif
|
||||
|
||||
default :
|
||||
RTW_ERR("%s IC not support dynamic tx power\n", __func__);
|
||||
break;
|
||||
}
|
||||
}
|
||||
void rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id)
|
||||
{
|
||||
struct dm_struct *dm = adapter_to_phydm(adapter);
|
||||
|
||||
odm_set_dyntxpwr(dm, desc, mac_id);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTW_TX_2PATH_EN
|
||||
void rtw_phydm_tx_2path_en(_adapter *adapter)
|
||||
{
|
||||
struct dm_struct *dm = adapter_to_phydm(adapter);
|
||||
|
||||
phydm_tx_2path(dm);
|
||||
}
|
||||
#endif
|
||||
|
||||
void rtw_phydm_ops_func_init(struct dm_struct *p_phydm)
|
||||
{
|
||||
struct ra_table *p_ra_t = &p_phydm->dm_ra_table;
|
||||
|
||||
p_ra_t->record_ra_info = record_ra_info;
|
||||
#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
|
||||
p_phydm->fill_desc_dyntxpwr = rtw_phydm_fill_desc_dpt;
|
||||
#endif
|
||||
}
|
||||
void rtw_phydm_priv_init(_adapter *adapter)
|
||||
{
|
||||
PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
|
||||
struct dm_struct *phydm = &(hal->odmpriv);
|
||||
|
||||
phydm->adapter = adapter;
|
||||
odm_cmn_info_init(phydm, ODM_CMNINFO_PLATFORM, ODM_CE);
|
||||
}
|
||||
|
||||
void Init_ODM_ComInfo(_adapter *adapter)
|
||||
{
|
||||
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
|
||||
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
|
||||
struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
|
||||
struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
|
||||
struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
|
||||
int i;
|
||||
|
||||
_rtw_memset(pDM_Odm, 0, sizeof(*pDM_Odm));
|
||||
|
||||
pDM_Odm->adapter = adapter;
|
||||
|
||||
/*phydm_op_mode could be change for different scenarios: ex: SoftAP - PHYDM_BALANCE_MODE*/
|
||||
pHalData->phydm_op_mode = PHYDM_PERFORMANCE_MODE;/*Service one device*/
|
||||
|
||||
odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PLATFORM, ODM_CE);
|
||||
|
||||
rtw_odm_init_ic_type(adapter);
|
||||
|
||||
if (rtw_get_intf_type(adapter) == RTW_GSPI)
|
||||
@@ -250,7 +335,7 @@ void Init_ODM_ComInfo(_adapter *adapter)
|
||||
|
||||
#ifdef CONFIG_DFS_MASTER
|
||||
odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_DFS_REGION_DOMAIN, adapter->registrypriv.dfs_region_domain);
|
||||
odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->dfs_master_enabled));
|
||||
odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->radar_detect_enabled));
|
||||
#endif
|
||||
|
||||
odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA);
|
||||
@@ -259,6 +344,7 @@ void Init_ODM_ComInfo(_adapter *adapter)
|
||||
odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA);
|
||||
|
||||
odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->rfe_type);
|
||||
odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_X_CAP_SETTING, pHalData->crystal_cap);
|
||||
|
||||
odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0);
|
||||
|
||||
@@ -277,13 +363,12 @@ void Init_ODM_ComInfo(_adapter *adapter)
|
||||
/*Add by YuChen for adaptivity init*/
|
||||
odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVITY, &(adapter->registrypriv.adaptivity_en));
|
||||
phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, (adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE);
|
||||
phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_DCBACKOFF, adapter->registrypriv.adaptivity_dc_backoff);
|
||||
phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY, (adapter->registrypriv.adaptivity_dml != 0) ? TRUE : FALSE);
|
||||
phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_L2H_INI, adapter->registrypriv.adaptivity_th_l2h_ini);
|
||||
phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, adapter->registrypriv.adaptivity_th_edcca_hl_diff);
|
||||
|
||||
/*halrf info init*/
|
||||
halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_EEPROM_THERMAL_VALUE, pHalData->eeprom_thermal_meter);
|
||||
halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_PWT_TYPE, 0);
|
||||
|
||||
if (rtw_odm_adaptivity_needed(adapter) == _TRUE)
|
||||
rtw_odm_adaptivity_config_msg(RTW_DBGDUMP, adapter);
|
||||
@@ -365,6 +450,65 @@ static u32 edca_setting_dl_g_mode[HT_IOT_PEER_MAX] =
|
||||
/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP */
|
||||
{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};
|
||||
|
||||
|
||||
struct turbo_edca_setting{
|
||||
u32 edca_ul; /* uplink, tx */
|
||||
u32 edca_dl; /* downlink, rx */
|
||||
};
|
||||
|
||||
#define TURBO_EDCA_ENT(UL, DL) {UL, DL}
|
||||
|
||||
#if 0
|
||||
#define TURBO_EDCA_MODE_NUM 18
|
||||
static struct turbo_edca_setting rtw_turbo_edca[TURBO_EDCA_MODE_NUM] = {
|
||||
TURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 0 */
|
||||
TURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */
|
||||
TURBO_EDCA_ENT(0x4319, 0x4319), /* mode 2 */
|
||||
|
||||
TURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */
|
||||
TURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 4 */
|
||||
TURBO_EDCA_ENT(0x5e4319, 0x5e4319), /* mode 5 */
|
||||
|
||||
TURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 6 */
|
||||
TURBO_EDCA_ENT(0x6e431c, 0x6e431c), /* mode 7 */
|
||||
TURBO_EDCA_ENT(0x6e4319, 0x6e4319), /* mode 8 */
|
||||
|
||||
TURBO_EDCA_ENT(0x5ea42b, 0xa42b), /* mode 9 */
|
||||
TURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 10 */
|
||||
TURBO_EDCA_ENT(0x5e4319, 0x4319), /* mode 11 */
|
||||
|
||||
TURBO_EDCA_ENT(0x6ea42b, 0xa42b), /* mode 12 */
|
||||
TURBO_EDCA_ENT(0x6e431c, 0x431c), /* mode 13 */
|
||||
TURBO_EDCA_ENT(0x6e4319, 0x4319), /* mode 14 */
|
||||
|
||||
TURBO_EDCA_ENT(0x431c, 0x5e431c), /* mode 15 */
|
||||
|
||||
TURBO_EDCA_ENT(0xa42b, 0x5ea42b), /* mode 16 */
|
||||
|
||||
TURBO_EDCA_ENT(0x138642b, 0x431c), /* mode 17 */
|
||||
};
|
||||
#else
|
||||
#define TURBO_EDCA_MODE_NUM 8
|
||||
static struct turbo_edca_setting rtw_turbo_edca[TURBO_EDCA_MODE_NUM] = {
|
||||
/* { UL, DL } */
|
||||
TURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 0 */
|
||||
|
||||
TURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */
|
||||
|
||||
TURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 2 */
|
||||
|
||||
TURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */
|
||||
|
||||
TURBO_EDCA_ENT(0x5ea42b, 0x431c), /* mode 4 */
|
||||
|
||||
TURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 5 */
|
||||
|
||||
TURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 6 */
|
||||
|
||||
TURBO_EDCA_ENT(0x5e431c, 0xa42b), /* mode 7 */
|
||||
};
|
||||
#endif
|
||||
|
||||
void rtw_hal_turbo_edca(_adapter *adapter)
|
||||
{
|
||||
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
|
||||
@@ -394,7 +538,7 @@ void rtw_hal_turbo_edca(_adapter *adapter)
|
||||
u8 is_linked = _FALSE;
|
||||
u8 interface_type;
|
||||
|
||||
if (hal_data->dis_turboedca)
|
||||
if (hal_data->dis_turboedca == 1)
|
||||
return;
|
||||
|
||||
if (rtw_mi_check_status(adapter, MI_ASSOC))
|
||||
@@ -477,7 +621,7 @@ void rtw_hal_turbo_edca(_adapter *adapter)
|
||||
EDCA_BE_DL = edca_setting_DL[iot_peer];
|
||||
}
|
||||
|
||||
if ((ic_type == RTL8812) || (ic_type == RTL8821) || (ic_type == RTL8192E)) { /* add 8812AU/8812AE */
|
||||
if ((ic_type == RTL8812) || (ic_type == RTL8821) || (ic_type == RTL8192E) || (ic_type == RTL8192F)) { /* add 8812AU/8812AE */
|
||||
EDCA_BE_UL = 0x5ea42b;
|
||||
EDCA_BE_DL = 0x5ea42b;
|
||||
|
||||
@@ -491,16 +635,101 @@ void rtw_hal_turbo_edca(_adapter *adapter)
|
||||
EDCA_BE_DL = 0x6ea42b;
|
||||
}
|
||||
|
||||
if ((ic_type == RTL8822B)
|
||||
&& (interface_type == RTW_SDIO))
|
||||
EDCA_BE_DL = 0x00431c;
|
||||
|
||||
#ifdef CONFIG_RTW_TPT_MODE
|
||||
if ( dvobj->tpt_mode > 0 ) {
|
||||
EDCA_BE_UL = dvobj->edca_be_ul;
|
||||
EDCA_BE_DL = dvobj->edca_be_dl;
|
||||
}
|
||||
#endif /* CONFIG_RTW_TPT_MODE */
|
||||
|
||||
/* keep this condition at last check */
|
||||
if (hal_data->dis_turboedca == 2) {
|
||||
|
||||
if (hal_data->edca_param_mode < TURBO_EDCA_MODE_NUM) {
|
||||
|
||||
struct turbo_edca_setting param;
|
||||
|
||||
param = rtw_turbo_edca[hal_data->edca_param_mode];
|
||||
|
||||
EDCA_BE_UL = param.edca_ul;
|
||||
EDCA_BE_DL = param.edca_dl;
|
||||
|
||||
} else {
|
||||
|
||||
EDCA_BE_UL = hal_data->edca_param_mode;
|
||||
EDCA_BE_DL = hal_data->edca_param_mode;
|
||||
}
|
||||
}
|
||||
|
||||
if (traffic_index == DOWN_LINK)
|
||||
edca_param = EDCA_BE_DL;
|
||||
else
|
||||
edca_param = EDCA_BE_UL;
|
||||
|
||||
#ifdef CONFIG_EXTEND_LOWRATE_TXOP
|
||||
#define TXOP_CCK1M 0x01A6
|
||||
#define TXOP_CCK2M 0x00E6
|
||||
#define TXOP_CCK5M 0x006B
|
||||
#define TXOP_OFD6M 0x0066
|
||||
#define TXOP_MCS6M 0x0061
|
||||
{
|
||||
struct sta_info *psta;
|
||||
struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
|
||||
u8 mac_id, role, current_rate_id;
|
||||
|
||||
/* search all used & connect2AP macid */
|
||||
for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) {
|
||||
if (rtw_macid_is_used(macid_ctl, mac_id)) {
|
||||
role = GET_H2CCMD_MSRRPT_PARM_ROLE(&(macid_ctl->h2c_msr[mac_id]));
|
||||
if (role != H2C_MSR_ROLE_AP)
|
||||
continue;
|
||||
|
||||
psta = macid_ctl->sta[mac_id];
|
||||
current_rate_id = rtw_get_current_tx_rate(adapter, psta);
|
||||
/* Check init tx_rate==1M and set 0x508[31:16]==0x019B(unit 32us) if it is */
|
||||
switch (current_rate_id) {
|
||||
case DESC_RATE1M:
|
||||
edca_param &= 0x0000FFFF;
|
||||
edca_param |= (TXOP_CCK1M<<16);
|
||||
break;
|
||||
case DESC_RATE2M:
|
||||
edca_param &= 0x0000FFFF;
|
||||
edca_param |= (TXOP_CCK2M<<16);
|
||||
break;
|
||||
case DESC_RATE5_5M:
|
||||
edca_param &= 0x0000FFFF;
|
||||
edca_param |= (TXOP_CCK5M<<16);
|
||||
break;
|
||||
case DESC_RATE6M:
|
||||
edca_param &= 0x0000FFFF;
|
||||
edca_param |= (TXOP_OFD6M<<16);
|
||||
break;
|
||||
case DESC_RATEMCS0:
|
||||
edca_param &= 0x0000FFFF;
|
||||
edca_param |= (TXOP_MCS6M<<16);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_EXTEND_LOWRATE_TXOP */
|
||||
|
||||
#ifdef CONFIG_RTW_CUSTOMIZE_BEEDCA
|
||||
edca_param = CONFIG_RTW_CUSTOMIZE_BEEDCA;
|
||||
#endif
|
||||
rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
|
||||
|
||||
RTW_DBG("Turbo EDCA =0x%x\n", edca_param);
|
||||
if ( edca_param != hal_data->ac_param_be) {
|
||||
|
||||
rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
|
||||
|
||||
RTW_INFO("Turbo EDCA =0x%x\n", edca_param);
|
||||
}
|
||||
|
||||
hal_data->prv_traffic_idx = traffic_index;
|
||||
}
|
||||
@@ -625,8 +854,8 @@ void SetHalODMVar(
|
||||
break;
|
||||
case HAL_ODM_REGULATION:
|
||||
/* used to auto enable/disable adaptivity by SD7 */
|
||||
odm_cmn_info_init(podmpriv, ODM_CMNINFO_DOMAIN_CODE_2G, 0);
|
||||
odm_cmn_info_init(podmpriv, ODM_CMNINFO_DOMAIN_CODE_5G, 0);
|
||||
phydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_2G, 0);
|
||||
phydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_5G, 0);
|
||||
break;
|
||||
case HAL_ODM_INITIAL_GAIN: {
|
||||
u8 rx_gain = *((u8 *)(pValue1));
|
||||
@@ -914,15 +1143,22 @@ void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta)
|
||||
{
|
||||
struct ra_sta_info *ra_info;
|
||||
u8 curr_sgi = _FALSE;
|
||||
u32 tx_tp_mbips, rx_tp_mbips, bi_tp_mbips;
|
||||
|
||||
if (!psta)
|
||||
return;
|
||||
RTW_PRINT_SEL(sel, "====== mac_id : %d ======\n", psta->cmn.mac_id);
|
||||
RTW_PRINT_SEL(sel, "\n");
|
||||
RTW_PRINT_SEL(sel, "====== mac_id : %d [" MAC_FMT "] ======\n",
|
||||
psta->cmn.mac_id, MAC_ARG(psta->cmn.mac_addr));
|
||||
|
||||
if (is_client_associated_to_ap(psta->padapter))
|
||||
RTW_PRINT_SEL(sel, "BCN counts : %d (per-%d second), DTIM Period:%d\n",
|
||||
rtw_get_bcn_cnt(psta->padapter) / 2, 1, rtw_get_bcn_dtim_period(psta->padapter));
|
||||
|
||||
ra_info = &psta->cmn.ra_info;
|
||||
curr_sgi = (ra_info->curr_tx_rate & 0x80) ? _TRUE : _FALSE;
|
||||
curr_sgi = rtw_get_current_tx_sgi(adapter, psta);
|
||||
RTW_PRINT_SEL(sel, "tx_rate : %s(%s) rx_rate : %s, rx_rate_bmc : %s, rssi : %d %%\n"
|
||||
, HDATA_RATE((ra_info->curr_tx_rate & 0x7F)), (curr_sgi) ? "S" : "L"
|
||||
, HDATA_RATE(rtw_get_current_tx_rate(adapter, psta)), (curr_sgi) ? "S" : "L"
|
||||
, HDATA_RATE((psta->curr_rx_rate & 0x7F)), HDATA_RATE((psta->curr_rx_rate_bmc & 0x7F)), psta->cmn.rssi_stat.rssi
|
||||
);
|
||||
|
||||
@@ -945,14 +1181,51 @@ void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta)
|
||||
);
|
||||
}
|
||||
|
||||
RTW_PRINT_SEL(sel, "TP {Tx,Rx,Total} = { %d , %d , %d } Mbps\n",
|
||||
(psta->sta_stats.tx_tp_mbytes << 3), (psta->sta_stats.rx_tp_mbytes << 3),
|
||||
(psta->sta_stats.tx_tp_mbytes + psta->sta_stats.rx_tp_mbytes) << 3);
|
||||
_RTW_PRINT_SEL(sel, "RTW: [TP] ");
|
||||
tx_tp_mbips = psta->sta_stats.tx_tp_kbits >> 10;
|
||||
rx_tp_mbips = psta->sta_stats.rx_tp_kbits >> 10;
|
||||
bi_tp_mbips = tx_tp_mbips + rx_tp_mbips;
|
||||
|
||||
if (tx_tp_mbips)
|
||||
_RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips);
|
||||
else
|
||||
_RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.tx_tp_kbits);
|
||||
|
||||
if (rx_tp_mbips)
|
||||
_RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips);
|
||||
else
|
||||
_RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.rx_tp_kbits);
|
||||
|
||||
if (bi_tp_mbips)
|
||||
_RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips);
|
||||
else
|
||||
_RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.tx_tp_kbits + psta->sta_stats.rx_tp_kbits);
|
||||
|
||||
|
||||
_RTW_PRINT_SEL(sel, "RTW: [Smooth TP] ");
|
||||
tx_tp_mbips = psta->sta_stats.smooth_tx_tp_kbits >> 10;
|
||||
rx_tp_mbips = psta->sta_stats.smooth_rx_tp_kbits >> 10;
|
||||
bi_tp_mbips = tx_tp_mbips + rx_tp_mbips;
|
||||
if (tx_tp_mbips)
|
||||
_RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips);
|
||||
else
|
||||
_RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.smooth_tx_tp_kbits);
|
||||
|
||||
if (rx_tp_mbips)
|
||||
_RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips);
|
||||
else
|
||||
_RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.smooth_rx_tp_kbits);
|
||||
|
||||
if (bi_tp_mbips)
|
||||
_RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips);
|
||||
else
|
||||
_RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.smooth_tx_tp_kbits + psta->sta_stats.rx_tp_kbits);
|
||||
|
||||
#if 0
|
||||
RTW_PRINT_SEL(sel, "Moving-AVG TP {Tx,Rx,Total} = { %d , %d , %d } Mbps\n\n",
|
||||
(psta->cmn.tx_moving_average_tp << 3), (psta->cmn.rx_moving_average_tp << 3),
|
||||
(psta->cmn.tx_moving_average_tp + psta->cmn.rx_moving_average_tp) << 3);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
void dump_sta_info(void *sel, struct sta_info *psta)
|
||||
@@ -971,6 +1244,7 @@ void dump_sta_info(void *sel, struct sta_info *psta)
|
||||
RTW_PRINT_SEL(sel, "mac_id : %d\n", psta->cmn.mac_id);
|
||||
RTW_PRINT_SEL(sel, "wireless_mode : 0x%02x\n", psta->wireless_mode);
|
||||
RTW_PRINT_SEL(sel, "mimo_type : %d\n", psta->cmn.mimo_type);
|
||||
RTW_PRINT_SEL(sel, "static smps : %s\n", (psta->cmn.sm_ps == SM_PS_STATIC) ? "Y" : "N");
|
||||
RTW_PRINT_SEL(sel, "bw_mode : %s, ra_bw_mode : %s\n",
|
||||
ch_width_str(psta->cmn.bw_mode), ch_width_str(ra_info->ra_bw_mode));
|
||||
RTW_PRINT_SEL(sel, "rate_id : %d\n", ra_info->rate_id);
|
||||
@@ -982,8 +1256,8 @@ void dump_sta_info(void *sel, struct sta_info *psta)
|
||||
RTW_PRINT_SEL(sel, "is_noisy : %s\n", (ra_info->is_noisy) ? "Y" : "N");
|
||||
RTW_PRINT_SEL(sel, "txrx_state : %d\n", ra_info->txrx_state);/*0: uplink, 1:downlink, 2:bi-direction*/
|
||||
|
||||
curr_tx_sgi = (ra_info->curr_tx_rate & 0x80) ? _TRUE : _FALSE;
|
||||
curr_tx_rate = ra_info->curr_tx_rate & 0x7F;
|
||||
curr_tx_sgi = rtw_get_current_tx_sgi(psta->padapter, psta);
|
||||
curr_tx_rate = rtw_get_current_tx_rate(psta->padapter, psta);
|
||||
RTW_PRINT_SEL(sel, "curr_tx_rate : %s (%s)\n",
|
||||
HDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? "S" : "L");
|
||||
RTW_PRINT_SEL(sel, "curr_tx_bw : %s\n", ch_width_str(ra_info->curr_tx_bw));
|
||||
@@ -1010,15 +1284,8 @@ static void init_phydm_info(_adapter *adapter)
|
||||
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
|
||||
struct dm_struct *phydm = &(hal_data->odmpriv);
|
||||
|
||||
halrf_cmn_info_init(phydm, HALRF_CMNINFO_FW_VER,
|
||||
((hal_data->firmware_version << 16) | hal_data->firmware_sub_version));
|
||||
|
||||
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1))
|
||||
/*PHYDM API - thermal trim*/
|
||||
phydm_get_thermal_trim_offset(phydm);
|
||||
/*PHYDM API - power trim*/
|
||||
phydm_get_power_trim_offset(phydm);
|
||||
#endif
|
||||
odm_cmn_info_init(phydm, ODM_CMNINFO_FW_VER, hal_data->firmware_version);
|
||||
odm_cmn_info_init(phydm, ODM_CMNINFO_FW_SUB_VER, hal_data->firmware_sub_version);
|
||||
}
|
||||
void rtw_phydm_init(_adapter *adapter)
|
||||
{
|
||||
@@ -1027,9 +1294,13 @@ void rtw_phydm_init(_adapter *adapter)
|
||||
|
||||
init_phydm_info(adapter);
|
||||
odm_dm_init(phydm);
|
||||
#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
|
||||
phydm_pathb_q_matrix_rotate_en(phydm);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_LPS_PG
|
||||
/*
|
||||
static void _lps_pg_state_update(_adapter *adapter)
|
||||
{
|
||||
u8 is_in_lpspg = _FALSE;
|
||||
@@ -1046,44 +1317,90 @@ static void _lps_pg_state_update(_adapter *adapter)
|
||||
if (psta)
|
||||
psta->cmn.ra_info.disable_ra = (is_in_lpspg) ? _TRUE : _FALSE;
|
||||
}
|
||||
*/
|
||||
void rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg)
|
||||
{
|
||||
struct dm_struct *phydm = adapter_to_phydm(adapter);
|
||||
/*u8 rate_id;*/
|
||||
|
||||
if(sta == NULL) {
|
||||
RTW_ERR("%s sta is null\n", __func__);
|
||||
rtw_warn_on(1);
|
||||
return;
|
||||
}
|
||||
|
||||
if (in_lpspg) {
|
||||
sta->cmn.ra_info.disable_ra = _TRUE;
|
||||
sta->cmn.ra_info.disable_pt = _TRUE;
|
||||
/*TODO : DRV fix tx rate*/
|
||||
/*rate_id = phydm_get_rate_from_rssi_lv(phydm, sta->cmn.mac_id);*/
|
||||
} else {
|
||||
sta->cmn.ra_info.disable_ra = _FALSE;
|
||||
sta->cmn.ra_info.disable_pt = _FALSE;
|
||||
}
|
||||
|
||||
rtw_phydm_ra_registed(adapter, sta);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*#define DBG_PHYDM_STATE_CHK*/
|
||||
|
||||
|
||||
static u8 _rtw_phydm_rfk_condition_check(_adapter *adapter)
|
||||
static u8 _rtw_phydm_rfk_condition_check(_adapter *adapter, u8 is_scaning, u8 ifs_linked)
|
||||
{
|
||||
u8 rst = _FALSE;
|
||||
u8 rfk_allowed = _TRUE;
|
||||
|
||||
if (rtw_mi_stayin_union_ch_chk(adapter))
|
||||
rst = _TRUE;
|
||||
#ifdef CONFIG_SKIP_RFK_IN_DM
|
||||
rfk_allowed = _FALSE;
|
||||
if (0)
|
||||
RTW_ERR("[RFK-CHK] RF-K not allowed due to CONFIG_SKIP_RFK_IN_DM\n");
|
||||
return rfk_allowed;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MCC_MODE
|
||||
/*not in MCC State*/
|
||||
if (MCC_EN(adapter))
|
||||
if (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
|
||||
rst = _TRUE;
|
||||
if (MCC_EN(adapter) &&
|
||||
rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
|
||||
rfk_allowed = _FALSE;
|
||||
if (0)
|
||||
RTW_INFO("[RFK-CHK] RF-K not allowed due to doing MCC\n");
|
||||
return rfk_allowed;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
|
||||
|
||||
#endif
|
||||
|
||||
return rst;
|
||||
if (ifs_linked) {
|
||||
if (is_scaning) {
|
||||
rfk_allowed = _FALSE;
|
||||
RTW_DBG("[RFK-CHK] RF-K not allowed due to ifaces under site-survey\n");
|
||||
}
|
||||
else {
|
||||
rfk_allowed = rtw_mi_stayin_union_ch_chk(adapter) ? _TRUE : _FALSE;
|
||||
if (rfk_allowed == _FALSE)
|
||||
RTW_ERR("[RFK-CHK] RF-K not allowed due to ld_iface not stayin union ch\n");
|
||||
}
|
||||
}
|
||||
|
||||
return rfk_allowed;
|
||||
}
|
||||
|
||||
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
|
||||
static u8 _rtw_phydm_iqk_segment_chk(_adapter *adapter)
|
||||
static u8 _rtw_phydm_iqk_segment_chk(_adapter *adapter, u8 ifs_linked)
|
||||
{
|
||||
u8 rst = _FALSE;
|
||||
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
|
||||
u8 iqk_sgt = _FALSE;
|
||||
|
||||
#if 0
|
||||
if (dvobj->traffic_stat.cur_tx_tp > 2 || dvobj->traffic_stat.cur_rx_tp > 2)
|
||||
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
|
||||
if (ifs_linked && (dvobj->traffic_stat.cur_tx_tp > 2 || dvobj->traffic_stat.cur_rx_tp > 2))
|
||||
rst = _TRUE;
|
||||
#else
|
||||
rst = _TRUE;
|
||||
if (ifs_linked)
|
||||
iqk_sgt = _TRUE;
|
||||
#endif
|
||||
return rst;
|
||||
return iqk_sgt;
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -1164,16 +1481,46 @@ void rtw_dyn_soml_config(_adapter *adapter)
|
||||
}
|
||||
#endif
|
||||
|
||||
void rtw_phydm_watchdog(_adapter *adapter)
|
||||
|
||||
void rtw_phydm_read_efuse(_adapter *adapter)
|
||||
{
|
||||
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
|
||||
struct dm_struct *phydm = &(hal_data->odmpriv);
|
||||
|
||||
/*PHYDM API - thermal trim*/
|
||||
phydm_get_thermal_trim_offset(phydm);
|
||||
/*PHYDM API - power trim*/
|
||||
phydm_get_power_trim_offset(phydm);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_LPS_PWR_TRACKING
|
||||
void rtw_phydm_pwr_tracking_directly(_adapter *adapter)
|
||||
{
|
||||
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
|
||||
u8 rfk_forbidden = _TRUE;
|
||||
u8 is_linked = _FALSE;
|
||||
|
||||
if (rtw_mi_check_status(adapter, MI_ASSOC))
|
||||
is_linked = _TRUE;
|
||||
|
||||
rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, hal_data->bScanInProcess, is_linked) == _TRUE) ? _FALSE : _TRUE;
|
||||
halrf_cmn_info_set(&hal_data->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
|
||||
|
||||
odm_txpowertracking_direct_ce(&hal_data->odmpriv);
|
||||
}
|
||||
#endif
|
||||
|
||||
void rtw_phydm_watchdog(_adapter *adapter, bool in_lps)
|
||||
{
|
||||
u8 bLinked = _FALSE;
|
||||
u8 bsta_state = _FALSE;
|
||||
u8 bBtDisabled = _TRUE;
|
||||
u8 rfk_forbidden = _TRUE;
|
||||
u8 segment_iqk = _TRUE;
|
||||
u8 rfk_forbidden = _FALSE;
|
||||
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
|
||||
u8 segment_iqk = _FALSE;
|
||||
#endif
|
||||
u8 tx_unlinked_low_rate = 0xFF;
|
||||
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
|
||||
struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
|
||||
|
||||
if (!rtw_is_hw_init_completed(adapter)) {
|
||||
RTW_DBG("%s skip due to hw_init_completed == FALSE\n", __func__);
|
||||
@@ -1193,31 +1540,28 @@ void rtw_phydm_watchdog(_adapter *adapter)
|
||||
odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, bLinked);
|
||||
odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state);
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
bBtDisabled = rtw_btcoex_IsBtDisabled(adapter);
|
||||
#endif /* CONFIG_BT_COEXIST */
|
||||
#endif /* CONFIG_BT_COEXIST */
|
||||
odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED,
|
||||
(bBtDisabled == _TRUE) ? _FALSE : _TRUE);
|
||||
#ifdef CONFIG_LPS_PG
|
||||
_lps_pg_state_update(adapter);
|
||||
#endif
|
||||
|
||||
if (bLinked == _TRUE) {
|
||||
rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter) == _TRUE) ? _FALSE : _TRUE;
|
||||
halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
|
||||
rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, pHalData->bScanInProcess, bLinked) == _TRUE) ? _FALSE : _TRUE;
|
||||
halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
|
||||
|
||||
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
|
||||
segment_iqk = _rtw_phydm_iqk_segment_chk(adapter);
|
||||
halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_IQK_SEGMENT, segment_iqk);
|
||||
#endif
|
||||
} else {
|
||||
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
|
||||
segment_iqk = _rtw_phydm_iqk_segment_chk(adapter, bLinked);
|
||||
halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_IQK_SEGMENT, segment_iqk);
|
||||
#endif
|
||||
#ifdef DBG_PHYDM_STATE_CHK
|
||||
RTW_INFO("%s rfk_forbidden = %s, segment_iqk = %s\n",
|
||||
__func__, (rfk_forbidden) ? "Y" : "N", (segment_iqk) ? "Y" : "N");
|
||||
#endif
|
||||
|
||||
if (bLinked == _FALSE) {
|
||||
tx_unlinked_low_rate = _rtw_phydm_pwr_tracking_rate_check(adapter);
|
||||
halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RATE_INDEX, tx_unlinked_low_rate);
|
||||
}
|
||||
#ifdef DBG_PHYDM_STATE_CHK
|
||||
RTW_INFO("%s rfk_forbidden = %s, segment_iqk = %s\n",
|
||||
__func__, (rfk_forbidden) ? "Y" : "N", (segment_iqk) ? "Y" : "N");
|
||||
#endif
|
||||
|
||||
/*if (!rtw_mi_stayin_union_band_chk(adapter)) {
|
||||
#ifdef DBG_PHYDM_STATE_CHK
|
||||
@@ -1225,7 +1569,8 @@ void rtw_phydm_watchdog(_adapter *adapter)
|
||||
#endif
|
||||
goto _exit;
|
||||
}*/
|
||||
if (pwrctl->bpower_saving)
|
||||
|
||||
if (in_lps)
|
||||
phydm_watchdog_lps(&pHalData->odmpriv);
|
||||
else
|
||||
phydm_watchdog(&pHalData->odmpriv);
|
||||
|
||||
18
hal/hal_dm.h
18
hal/hal_dm.h
@@ -16,7 +16,9 @@
|
||||
#define __HAL_DM_H__
|
||||
|
||||
#define adapter_to_phydm(adapter) (&(GET_HAL_DATA(adapter)->odmpriv))
|
||||
#define dvobj_to_phydm(dvobj) adapter_to_phydm(dvobj_get_primary_adapter(dvobj))
|
||||
|
||||
void rtw_phydm_priv_init(_adapter *adapter);
|
||||
void Init_ODM_ComInfo(_adapter *adapter);
|
||||
void rtw_phydm_init(_adapter *adapter);
|
||||
|
||||
@@ -42,7 +44,7 @@ void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl,
|
||||
u8 period, u8 delay);
|
||||
void rtw_dyn_soml_config(_adapter *adapter);
|
||||
#endif
|
||||
void rtw_phydm_watchdog(_adapter *adapter);
|
||||
void rtw_phydm_watchdog(_adapter *adapter, bool in_lps);
|
||||
|
||||
void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter);
|
||||
void dump_sta_info(void *sel, struct sta_info *psta);
|
||||
@@ -84,5 +86,19 @@ u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt);
|
||||
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
|
||||
void rtw_phydm_iqk_trigger(_adapter *adapter);
|
||||
#endif
|
||||
void rtw_phydm_read_efuse(_adapter *adapter);
|
||||
|
||||
#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
|
||||
void rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id);
|
||||
#endif
|
||||
#ifdef CONFIG_RTW_TX_2PATH_EN
|
||||
void rtw_phydm_tx_2path_en(_adapter *adapter);
|
||||
#endif
|
||||
#ifdef CONFIG_LPS_PG
|
||||
void rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg);
|
||||
#endif
|
||||
#ifdef CONFIG_LPS_PWR_TRACKING
|
||||
void rtw_phydm_pwr_tracking_directly(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
#endif /* __HAL_DM_H__ */
|
||||
|
||||
593
hal/hal_halmac.c
593
hal/hal_halmac.c
@@ -1,6 +1,6 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2015 - 2017 Realtek Corporation.
|
||||
* Copyright(c) 2015 - 2018 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
@@ -18,6 +18,13 @@
|
||||
#include <hal_data.h> /* efuse, PHAL_DATA_TYPE and etc. */
|
||||
#include "hal_halmac.h" /* dvobj_to_halmac() and ect. */
|
||||
|
||||
/*
|
||||
* HALMAC take return value 0 for fail and 1 for success to replace
|
||||
* _FALSE/_TRUE after V1_04_09
|
||||
*/
|
||||
#define RTW_HALMAC_FAIL 0
|
||||
#define RTW_HALMAC_SUCCESS 1
|
||||
|
||||
#define DEFAULT_INDICATOR_TIMELMT 1000 /* ms */
|
||||
#define MSG_PREFIX "[HALMAC]"
|
||||
|
||||
@@ -183,15 +190,18 @@ static u8 _halmac_sdio_reg_read_n(void *p, u32 offset, u32 size, u8 *data)
|
||||
struct dvobj_priv *d = (struct dvobj_priv *)p;
|
||||
u8 *pbuf;
|
||||
u8 ret;
|
||||
u8 rst = _FALSE;
|
||||
u8 rst = RTW_HALMAC_FAIL;
|
||||
u32 sdio_read_size;
|
||||
|
||||
|
||||
if (!data)
|
||||
return rst;
|
||||
|
||||
sdio_read_size = RND4(size);
|
||||
sdio_read_size = rtw_sdio_cmd53_align_size(d, sdio_read_size);
|
||||
|
||||
pbuf = rtw_zmalloc(sdio_read_size);
|
||||
if ((!pbuf) || (!data))
|
||||
if (!pbuf)
|
||||
return rst;
|
||||
|
||||
ret = rtw_sdio_read_cmd53(d, offset, pbuf, sdio_read_size);
|
||||
@@ -201,7 +211,7 @@ static u8 _halmac_sdio_reg_read_n(void *p, u32 offset, u32 size, u8 *data)
|
||||
}
|
||||
|
||||
_rtw_memcpy(data, pbuf, size);
|
||||
rst = _TRUE;
|
||||
rst = RTW_HALMAC_SUCCESS;
|
||||
exit:
|
||||
rtw_mfree(pbuf, sdio_read_size);
|
||||
|
||||
@@ -376,7 +386,7 @@ static void _halmac_reg_write_32(void *p, u32 offset, u32 val)
|
||||
static u8 _halmac_mfree(void *p, void *buffer, u32 size)
|
||||
{
|
||||
rtw_mfree(buffer, size);
|
||||
return _TRUE;
|
||||
return RTW_HALMAC_SUCCESS;
|
||||
}
|
||||
|
||||
static void *_halmac_malloc(void *p, u32 size)
|
||||
@@ -387,13 +397,13 @@ static void *_halmac_malloc(void *p, u32 size)
|
||||
static u8 _halmac_memcpy(void *p, void *dest, void *src, u32 size)
|
||||
{
|
||||
_rtw_memcpy(dest, src, size);
|
||||
return _TRUE;
|
||||
return RTW_HALMAC_SUCCESS;
|
||||
}
|
||||
|
||||
static u8 _halmac_memset(void *p, void *addr, u8 value, u32 size)
|
||||
{
|
||||
_rtw_memset(addr, value, size);
|
||||
return _TRUE;
|
||||
return RTW_HALMAC_SUCCESS;
|
||||
}
|
||||
|
||||
static void _halmac_udelay(void *p, u32 us)
|
||||
@@ -410,13 +420,13 @@ static void _halmac_udelay(void *p, u32 us)
|
||||
static u8 _halmac_mutex_init(void *p, HALMAC_MUTEX *pMutex)
|
||||
{
|
||||
_rtw_mutex_init(pMutex);
|
||||
return _TRUE;
|
||||
return RTW_HALMAC_SUCCESS;
|
||||
}
|
||||
|
||||
static u8 _halmac_mutex_deinit(void *p, HALMAC_MUTEX *pMutex)
|
||||
{
|
||||
_rtw_mutex_free(pMutex);
|
||||
return _TRUE;
|
||||
return RTW_HALMAC_SUCCESS;
|
||||
}
|
||||
|
||||
static u8 _halmac_mutex_lock(void *p, HALMAC_MUTEX *pMutex)
|
||||
@@ -425,26 +435,70 @@ static u8 _halmac_mutex_lock(void *p, HALMAC_MUTEX *pMutex)
|
||||
|
||||
err = _enter_critical_mutex(pMutex, NULL);
|
||||
if (err)
|
||||
return _FALSE;
|
||||
return RTW_HALMAC_FAIL;
|
||||
|
||||
return _TRUE;
|
||||
return RTW_HALMAC_SUCCESS;
|
||||
}
|
||||
|
||||
static u8 _halmac_mutex_unlock(void *p, HALMAC_MUTEX *pMutex)
|
||||
{
|
||||
_exit_critical_mutex(pMutex, NULL);
|
||||
return RTW_HALMAC_SUCCESS;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SDIO_HCI
|
||||
#define DBG_MSG_FILTER
|
||||
#endif
|
||||
|
||||
#ifdef DBG_MSG_FILTER
|
||||
static u8 is_msg_allowed(uint drv_lv, u8 msg_lv)
|
||||
{
|
||||
switch (drv_lv) {
|
||||
case _DRV_NONE_:
|
||||
return _FALSE;
|
||||
|
||||
case _DRV_ALWAYS_:
|
||||
if (msg_lv > HALMAC_DBG_ALWAYS)
|
||||
return _FALSE;
|
||||
break;
|
||||
case _DRV_ERR_:
|
||||
if (msg_lv > HALMAC_DBG_ERR)
|
||||
return _FALSE;
|
||||
break;
|
||||
case _DRV_WARNING_:
|
||||
if (msg_lv > HALMAC_DBG_WARN)
|
||||
return _FALSE;
|
||||
break;
|
||||
case _DRV_INFO_:
|
||||
if (msg_lv >= HALMAC_DBG_TRACE)
|
||||
return _FALSE;
|
||||
break;
|
||||
}
|
||||
|
||||
return _TRUE;
|
||||
}
|
||||
#endif /* DBG_MSG_FILTER */
|
||||
|
||||
static u8 _halmac_msg_print(void *p, u32 msg_type, u8 msg_level, s8 *fmt, ...)
|
||||
{
|
||||
#define MSG_LEN 100
|
||||
va_list args;
|
||||
u8 str[MSG_LEN] = {0};
|
||||
#ifdef DBG_MSG_FILTER
|
||||
uint drv_level = _DRV_NONE_;
|
||||
#endif
|
||||
int err;
|
||||
u8 ret = _TRUE;
|
||||
u8 ret = RTW_HALMAC_SUCCESS;
|
||||
|
||||
|
||||
#ifdef DBG_MSG_FILTER
|
||||
#ifdef CONFIG_RTW_DEBUG
|
||||
drv_level = rtw_drv_log_level;
|
||||
#endif
|
||||
if (is_msg_allowed(drv_level, msg_level) == _FALSE)
|
||||
return ret;
|
||||
#endif
|
||||
|
||||
str[0] = '\n';
|
||||
va_start(args, fmt);
|
||||
err = vsnprintf(str, MSG_LEN, fmt, args);
|
||||
@@ -452,10 +506,10 @@ static u8 _halmac_msg_print(void *p, u32 msg_type, u8 msg_level, s8 *fmt, ...)
|
||||
|
||||
/* An output error is encountered */
|
||||
if (err < 0)
|
||||
return _FALSE;
|
||||
return RTW_HALMAC_FAIL;
|
||||
/* Output may be truncated due to size limit */
|
||||
if ((err == (MSG_LEN - 1)) && (str[MSG_LEN - 2] != '\n'))
|
||||
ret = _FALSE;
|
||||
ret = RTW_HALMAC_FAIL;
|
||||
|
||||
if (msg_level == HALMAC_DBG_ALWAYS)
|
||||
RTW_PRINT(MSG_PREFIX "%s", str);
|
||||
@@ -476,7 +530,7 @@ static u8 _halmac_buff_print(void *p, u32 msg_type, u8 msg_level, s8 *buf, u32 s
|
||||
else
|
||||
RTW_DBG_DUMP(MSG_PREFIX, buf, size);
|
||||
|
||||
return _TRUE;
|
||||
return RTW_HALMAC_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
@@ -515,6 +569,9 @@ static inline u8 is_valid_id_status(enum halmac_feature_id id, enum halmac_cmd_p
|
||||
break;
|
||||
case HALMAC_FEATURE_UPDATE_PACKET:
|
||||
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
|
||||
if (status != HALMAC_CMD_PROCESS_DONE)
|
||||
RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
|
||||
__FUNCTION__, id, status);
|
||||
break;
|
||||
case HALMAC_FEATURE_UPDATE_DATAPACK:
|
||||
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
|
||||
@@ -524,6 +581,11 @@ static inline u8 is_valid_id_status(enum halmac_feature_id id, enum halmac_cmd_p
|
||||
break;
|
||||
case HALMAC_FEATURE_CHANNEL_SWITCH:
|
||||
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
|
||||
if ((status != HALMAC_CMD_PROCESS_DONE) && (status != HALMAC_CMD_PROCESS_RCVD))
|
||||
RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
|
||||
__FUNCTION__, id, status);
|
||||
if (status == HALMAC_CMD_PROCESS_DONE)
|
||||
return _FALSE;
|
||||
break;
|
||||
case HALMAC_FEATURE_IQK:
|
||||
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
|
||||
@@ -621,7 +683,7 @@ static int wait_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id)
|
||||
|
||||
/*
|
||||
* Return:
|
||||
* Always return _TRUE, HALMAC don't care the return value.
|
||||
* Always return RTW_HALMAC_SUCCESS, HALMAC don't care the return value.
|
||||
*/
|
||||
static u8 _halmac_event_indication(void *p, enum halmac_feature_id feature_id, enum halmac_cmd_process_status process_status, u8 *buf, u32 size)
|
||||
{
|
||||
@@ -672,7 +734,7 @@ static u8 _halmac_event_indication(void *p, enum halmac_feature_id feature_id, e
|
||||
rtw_sctx_done(&sctx);
|
||||
|
||||
exit:
|
||||
return _TRUE;
|
||||
return RTW_HALMAC_SUCCESS;
|
||||
}
|
||||
|
||||
struct halmac_platform_api rtw_halmac_platform_api = {
|
||||
@@ -689,14 +751,14 @@ struct halmac_platform_api rtw_halmac_platform_api = {
|
||||
.SDIO_CMD53_WRITE_32 = _halmac_sdio_reg_write_32,
|
||||
.SDIO_CMD52_CIA_READ = _halmac_sdio_read_cia,
|
||||
#endif /* CONFIG_SDIO_HCI */
|
||||
#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCIE_HCI)
|
||||
#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
|
||||
.REG_READ_8 = _halmac_reg_read_8,
|
||||
.REG_READ_16 = _halmac_reg_read_16,
|
||||
.REG_READ_32 = _halmac_reg_read_32,
|
||||
.REG_WRITE_8 = _halmac_reg_write_8,
|
||||
.REG_WRITE_16 = _halmac_reg_write_16,
|
||||
.REG_WRITE_32 = _halmac_reg_write_32,
|
||||
#endif /* CONFIG_USB_HCI || CONFIG_PCIE_HCI */
|
||||
#endif /* CONFIG_USB_HCI || CONFIG_PCI_HCI */
|
||||
|
||||
/* Write data */
|
||||
#if 0
|
||||
@@ -983,7 +1045,7 @@ static int init_write_rsvd_page_size(struct dvobj_priv *d)
|
||||
#ifdef CONFIG_USB_HCI
|
||||
/* for USB do not exceed MAX_CMDBUF_SZ */
|
||||
size = 0x1000;
|
||||
#elif defined(CONFIG_PCIE_HCI)
|
||||
#elif defined(CONFIG_PCI_HCI)
|
||||
size = MAX_CMDBUF_SZ - TXDESC_OFFSET;
|
||||
#elif defined(CONFIG_SDIO_HCI)
|
||||
size = 0x7000; /* 28KB */
|
||||
@@ -1122,7 +1184,7 @@ int rtw_halmac_init_adapter(struct dvobj_priv *d, struct halmac_platform_api *pf
|
||||
intf = HALMAC_INTERFACE_SDIO;
|
||||
#elif defined(CONFIG_USB_HCI)
|
||||
intf = HALMAC_INTERFACE_USB;
|
||||
#elif defined(CONFIG_PCIE_HCI)
|
||||
#elif defined(CONFIG_PCI_HCI)
|
||||
intf = HALMAC_INTERFACE_PCIE;
|
||||
#else
|
||||
#warning "INTERFACE(CONFIG_XXX_HCI) not be defined!!"
|
||||
@@ -2323,6 +2385,164 @@ int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* rtw_halmac_set_rts_full_bw() - Send RTS to all covered channels
|
||||
* @d: struct dvobj_priv*
|
||||
* @enable: _TRUE(enable), _FALSE(disable)
|
||||
*
|
||||
* Hradware will duplicate RTS packet to all channels which are covered in used
|
||||
* bandwidth.
|
||||
*
|
||||
* Return 0 if process OK, otherwise -1.
|
||||
*/
|
||||
int rtw_halmac_set_rts_full_bw(struct dvobj_priv *d, u8 enable)
|
||||
{
|
||||
struct halmac_adapter *mac;
|
||||
struct halmac_api *api;
|
||||
enum halmac_ret_status status;
|
||||
u8 full;
|
||||
|
||||
|
||||
mac = dvobj_to_halmac(d);
|
||||
api = HALMAC_GET_API(mac);
|
||||
full = (enable == _TRUE) ? 1 : 0;
|
||||
|
||||
status = api->halmac_set_hw_value(mac, HALMAC_HW_RTS_FULL_BW, &full);
|
||||
if (HALMAC_RET_SUCCESS != status)
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef RTW_HALMAC_DBG_POWER_SWITCH
|
||||
static void _dump_mac_reg(struct dvobj_priv *d, u32 start, u32 end)
|
||||
{
|
||||
struct _ADAPTER *adapter;
|
||||
int i, j = 1;
|
||||
|
||||
|
||||
adapter = dvobj_get_primary_adapter(d);
|
||||
for (i = start; i < end; i += 4) {
|
||||
if (j % 4 == 1)
|
||||
RTW_PRINT("0x%04x", i);
|
||||
_RTW_PRINT(" 0x%08x ", rtw_read32(adapter, i));
|
||||
if ((j++) % 4 == 0)
|
||||
_RTW_PRINT("\n");
|
||||
}
|
||||
}
|
||||
|
||||
void dump_dbg_val(struct _ADAPTER *a, u32 reg)
|
||||
{
|
||||
u32 v32;
|
||||
|
||||
|
||||
rtw_write8(a, 0x3A, reg);
|
||||
v32 = rtw_read32(a, 0xC0);
|
||||
RTW_PRINT("0x3A = %02x, 0xC0 = 0x%08x\n",reg, v32);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
static void _dump_pcie_cfg_space(struct dvobj_priv *d)
|
||||
{
|
||||
struct _ADAPTER *padapter = dvobj_get_primary_adapter(d);
|
||||
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
|
||||
struct pci_dev *pdev = pdvobjpriv->ppcidev;
|
||||
struct pci_dev *bridge_pdev = pdev->bus->self;
|
||||
|
||||
u32 tmp[4] = { 0 };
|
||||
u32 i, j;
|
||||
|
||||
RTW_PRINT("\n***** PCI Device Configuration Space *****\n\n");
|
||||
|
||||
for(i = 0; i < 0x100; i += 0x10)
|
||||
{
|
||||
for (j = 0 ; j < 4 ; j++)
|
||||
pci_read_config_dword(pdev, i + j * 4, tmp+j);
|
||||
|
||||
RTW_PRINT("%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
|
||||
i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF,
|
||||
tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF,
|
||||
tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF,
|
||||
tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF);
|
||||
}
|
||||
|
||||
RTW_PRINT("\n***** PCI Host Device Configuration Space*****\n\n");
|
||||
|
||||
for(i = 0; i < 0x100; i += 0x10)
|
||||
{
|
||||
for (j = 0 ; j < 4 ; j++)
|
||||
pci_read_config_dword(bridge_pdev, i + j * 4, tmp+j);
|
||||
|
||||
RTW_PRINT("%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
|
||||
i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF,
|
||||
tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF,
|
||||
tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF,
|
||||
tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static void _dump_mac_reg_for_power_switch(struct dvobj_priv *d,
|
||||
const char* caller, char* desc)
|
||||
{
|
||||
struct _ADAPTER *a;
|
||||
u8 v8;
|
||||
|
||||
|
||||
RTW_PRINT("%s: %s\n", caller, desc);
|
||||
RTW_PRINT("======= MAC REG =======\n");
|
||||
/* page 0/1 */
|
||||
_dump_mac_reg(d, 0x0, 0x200);
|
||||
_dump_mac_reg(d, 0x300, 0x400); /* also dump page 3 */
|
||||
|
||||
/* dump debug register */
|
||||
a = dvobj_get_primary_adapter(d);
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
_dump_pcie_cfg_space(d);
|
||||
|
||||
v8 = rtw_read8(a, 0xF6) | 0x01;
|
||||
rtw_write8(a, 0xF6, v8);
|
||||
RTW_PRINT("0xF6 = %02x\n", v8);
|
||||
|
||||
dump_dbg_val(a, 0x63);
|
||||
dump_dbg_val(a, 0x64);
|
||||
dump_dbg_val(a, 0x68);
|
||||
dump_dbg_val(a, 0x69);
|
||||
dump_dbg_val(a, 0x6a);
|
||||
dump_dbg_val(a, 0x6b);
|
||||
dump_dbg_val(a, 0x71);
|
||||
dump_dbg_val(a, 0x72);
|
||||
#endif
|
||||
}
|
||||
|
||||
static enum halmac_ret_status _power_switch(struct halmac_adapter *halmac,
|
||||
struct halmac_api *api,
|
||||
enum halmac_mac_power pwr)
|
||||
{
|
||||
enum halmac_ret_status status;
|
||||
char desc[80] = {0};
|
||||
|
||||
|
||||
rtw_sprintf(desc, 80, "before calling power %s",
|
||||
(pwr==HALMAC_MAC_POWER_ON)?"on":"off");
|
||||
_dump_mac_reg_for_power_switch((struct dvobj_priv *)halmac->drv_adapter,
|
||||
__FUNCTION__, desc);
|
||||
|
||||
status = api->halmac_mac_power_switch(halmac, pwr);
|
||||
RTW_PRINT("%s: status=%d\n", __FUNCTION__, status);
|
||||
|
||||
rtw_sprintf(desc, 80, "after calling power %s",
|
||||
(pwr==HALMAC_MAC_POWER_ON)?"on":"off");
|
||||
_dump_mac_reg_for_power_switch((struct dvobj_priv *)halmac->drv_adapter,
|
||||
__FUNCTION__, desc);
|
||||
|
||||
return status;
|
||||
}
|
||||
#else /* !RTW_HALMAC_DBG_POWER_SWITCH */
|
||||
#define _power_switch(mac, api, pwr) (api)->halmac_mac_power_switch(mac, pwr)
|
||||
#endif /* !RTW_HALMAC_DBG_POWER_SWITCH */
|
||||
|
||||
/*
|
||||
* Description:
|
||||
* Power on device hardware.
|
||||
@@ -2340,7 +2560,13 @@ int rtw_halmac_poweron(struct dvobj_priv *d)
|
||||
struct halmac_api *api;
|
||||
enum halmac_ret_status status;
|
||||
int err = -1;
|
||||
#if defined(CONFIG_PCI_HCI) && defined(CONFIG_RTL8822B)
|
||||
struct _ADAPTER *a;
|
||||
u8 v8;
|
||||
u32 addr;
|
||||
|
||||
a = dvobj_get_primary_adapter(d);
|
||||
#endif
|
||||
|
||||
halmac = dvobj_to_halmac(d);
|
||||
if (!halmac)
|
||||
@@ -2358,14 +2584,48 @@ int rtw_halmac_poweron(struct dvobj_priv *d)
|
||||
goto out;
|
||||
#endif /* CONFIG_SDIO_HCI */
|
||||
|
||||
status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON);
|
||||
#if defined(CONFIG_PCI_HCI) && defined(CONFIG_RTL8822B)
|
||||
addr = 0x3F3;
|
||||
v8 = rtw_read8(a, addr);
|
||||
RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8);
|
||||
/* are we in pcie debug mode? */
|
||||
if (!(v8 & BIT(2))) {
|
||||
RTW_PRINT("%s: Enable pcie debug mode\n", __FUNCTION__);
|
||||
v8 |= BIT(2);
|
||||
v8 = rtw_write8(a, addr, v8);
|
||||
}
|
||||
#endif
|
||||
|
||||
status = _power_switch(halmac, api, HALMAC_MAC_POWER_ON);
|
||||
if (HALMAC_RET_PWR_UNCHANGE == status) {
|
||||
|
||||
#if defined(CONFIG_PCI_HCI) && defined(CONFIG_RTL8822B)
|
||||
addr = 0x3F3;
|
||||
v8 = rtw_read8(a, addr);
|
||||
RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8);
|
||||
|
||||
/* are we in pcie debug mode? */
|
||||
if (!(v8 & BIT(2))) {
|
||||
RTW_PRINT("%s: Enable pcie debug mode\n", __FUNCTION__);
|
||||
v8 |= BIT(2);
|
||||
v8 = rtw_write8(a, addr, v8);
|
||||
} else if (v8 & BIT(0)) {
|
||||
/* DMA stuck */
|
||||
addr = 0x1350;
|
||||
v8 = rtw_read8(a, addr);
|
||||
RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8);
|
||||
RTW_PRINT("%s: recover DMA stuck\n", __FUNCTION__);
|
||||
v8 |= BIT(6);
|
||||
v8 = rtw_write8(a, addr, v8);
|
||||
RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8);
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* Work around for warm reboot but device not power off,
|
||||
* but it would also fall into this case when auto power on is enabled.
|
||||
*/
|
||||
api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF);
|
||||
status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON);
|
||||
_power_switch(halmac, api, HALMAC_MAC_POWER_OFF);
|
||||
status = _power_switch(halmac, api, HALMAC_MAC_POWER_ON);
|
||||
RTW_WARN("%s: Power state abnormal, try to recover...%s\n",
|
||||
__FUNCTION__, (HALMAC_RET_SUCCESS == status)?"OK":"FAIL!");
|
||||
}
|
||||
@@ -2406,7 +2666,7 @@ int rtw_halmac_poweroff(struct dvobj_priv *d)
|
||||
|
||||
api = HALMAC_GET_API(halmac);
|
||||
|
||||
status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF);
|
||||
status = _power_switch(halmac, api, HALMAC_MAC_POWER_OFF);
|
||||
if ((HALMAC_RET_SUCCESS != status)
|
||||
&& (HALMAC_RET_PWR_UNCHANGE != status))
|
||||
goto out;
|
||||
@@ -2454,7 +2714,7 @@ void dump_trx_share_mode(void *sel, struct _ADAPTER *adapter)
|
||||
}
|
||||
#endif
|
||||
|
||||
static enum halmac_drv_rsvd_pg_num _rsvd_page_num_drv2halmac(u8 num)
|
||||
static enum halmac_drv_rsvd_pg_num _rsvd_page_num_drv2halmac(u16 num)
|
||||
{
|
||||
if (num <= 8)
|
||||
return HALMAC_RSVD_PG_NUM8;
|
||||
@@ -2466,18 +2726,20 @@ static enum halmac_drv_rsvd_pg_num _rsvd_page_num_drv2halmac(u8 num)
|
||||
return HALMAC_RSVD_PG_NUM32;
|
||||
if (num <= 64)
|
||||
return HALMAC_RSVD_PG_NUM64;
|
||||
if (num <= 128)
|
||||
return HALMAC_RSVD_PG_NUM128;
|
||||
|
||||
if (num > 128)
|
||||
if (num > 256)
|
||||
RTW_WARN("%s: Fail to allocate RSVD page(%d)!!"
|
||||
" The MAX RSVD page number is 128...\n",
|
||||
" The MAX RSVD page number is 256...\n",
|
||||
__FUNCTION__, num);
|
||||
|
||||
return HALMAC_RSVD_PG_NUM128;
|
||||
return HALMAC_RSVD_PG_NUM256;
|
||||
}
|
||||
|
||||
static u8 _rsvd_page_num_halmac2drv(enum halmac_drv_rsvd_pg_num rsvd_page_number)
|
||||
static u16 _rsvd_page_num_halmac2drv(enum halmac_drv_rsvd_pg_num rsvd_page_number)
|
||||
{
|
||||
u8 num = 0;
|
||||
u16 num = 0;
|
||||
|
||||
|
||||
switch (rsvd_page_number) {
|
||||
@@ -2504,6 +2766,10 @@ static u8 _rsvd_page_num_halmac2drv(enum halmac_drv_rsvd_pg_num rsvd_page_number
|
||||
case HALMAC_RSVD_PG_NUM128:
|
||||
num = 128;
|
||||
break;
|
||||
|
||||
case HALMAC_RSVD_PG_NUM256:
|
||||
num = 256;
|
||||
break;
|
||||
}
|
||||
|
||||
return num;
|
||||
@@ -2718,7 +2984,7 @@ static int _cfg_drv_rsvd_pg_num(struct dvobj_priv *d)
|
||||
struct halmac_api *api;
|
||||
enum halmac_drv_rsvd_pg_num rsvd_page_number;
|
||||
enum halmac_ret_status status;
|
||||
u8 drv_rsvd_num;
|
||||
u16 drv_rsvd_num;
|
||||
|
||||
|
||||
a = dvobj_get_primary_adapter(d);
|
||||
@@ -2926,6 +3192,13 @@ exit:
|
||||
return err;
|
||||
}
|
||||
|
||||
static void _init_trx_cfg_drv(struct dvobj_priv *d)
|
||||
{
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
rtw_hal_irp_reset(dvobj_get_primary_adapter(d));
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Description:
|
||||
* Downlaod Firmware Flow
|
||||
@@ -3027,6 +3300,7 @@ resume_tx:
|
||||
status = api->halmac_init_trx_cfg(mac, mode);
|
||||
if (HALMAC_RET_SUCCESS != status)
|
||||
return -1;
|
||||
_init_trx_cfg_drv(d);
|
||||
|
||||
/* 9. Config RX Aggregation */
|
||||
err = rtw_halmac_rx_agg_switch(d, _TRUE);
|
||||
@@ -3090,6 +3364,7 @@ static int init_mac_flow(struct dvobj_priv *d)
|
||||
status = api->halmac_init_mac_cfg(halmac, trx_mode);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
goto out;
|
||||
_init_trx_cfg_drv(d);
|
||||
|
||||
err = rtw_halmac_rx_agg_switch(d, _TRUE);
|
||||
if (err)
|
||||
@@ -3120,7 +3395,11 @@ static int _drv_enable_trx(struct dvobj_priv *d)
|
||||
|
||||
adapter = dvobj_get_primary_adapter(d);
|
||||
if (adapter->bup == _FALSE) {
|
||||
#ifdef CONFIG_NEW_NETDEV_HDL
|
||||
status = rtw_mi_start_drv_threads(adapter);
|
||||
#else
|
||||
status = rtw_start_drv_threads(adapter);
|
||||
#endif
|
||||
if (status == _FAIL) {
|
||||
RTW_ERR("%s: Start threads Failed!\n", __FUNCTION__);
|
||||
return -1;
|
||||
@@ -3395,7 +3674,7 @@ int rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout)
|
||||
if (empty == _FALSE) {
|
||||
#ifdef CONFIG_RTW_DEBUG
|
||||
u16 dbg_reg[] = {0x210, 0x230, 0x234, 0x238, 0x23C, 0x240,
|
||||
0x41A, 0x10FC, 0x10F8, 0x11F4, 0x11F8};
|
||||
0x418, 0x10FC, 0x10F8, 0x11F4, 0x11F8};
|
||||
u8 i;
|
||||
u32 val;
|
||||
|
||||
@@ -3612,6 +3891,7 @@ int rtw_halmac_phy_power_switch(struct dvobj_priv *d, u8 enable)
|
||||
struct halmac_adapter *halmac;
|
||||
struct halmac_api *api;
|
||||
enum halmac_ret_status status;
|
||||
u8 on;
|
||||
|
||||
|
||||
adapter = dvobj_get_primary_adapter(d);
|
||||
@@ -3619,8 +3899,9 @@ int rtw_halmac_phy_power_switch(struct dvobj_priv *d, u8 enable)
|
||||
if (!halmac)
|
||||
return -1;
|
||||
api = HALMAC_GET_API(halmac);
|
||||
on = (enable == _TRUE) ? 1 : 0;
|
||||
|
||||
status = api->halmac_set_hw_value(halmac, HALMAC_HW_EN_BB_RF, &enable);
|
||||
status = api->halmac_set_hw_value(halmac, HALMAC_HW_EN_BB_RF, &on);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return -1;
|
||||
|
||||
@@ -4141,7 +4422,7 @@ _exit:
|
||||
/*
|
||||
* rtw_halmac_rx_agg_switch() - Switch RX aggregation function and setting
|
||||
* @d struct dvobj_priv *
|
||||
* @enable 0/1 for disable/enable RX aggregation function
|
||||
* @enable _FALSE/_TRUE for disable/enable RX aggregation function
|
||||
*
|
||||
* This function could help to on/off bus RX aggregation function, and is only
|
||||
* useful for SDIO and USB interface. Although only "enable" flag is brough in,
|
||||
@@ -4291,6 +4572,7 @@ int rtw_halmac_p2pps(struct dvobj_priv *dvobj, struct hal_p2p_ps_para *pp2p_ps_p
|
||||
(&halmac_p2p_ps)->noa_sel = pp2p_ps_para->noa_sel;
|
||||
(&halmac_p2p_ps)->all_sta_sleep = pp2p_ps_para->all_sta_sleep;
|
||||
(&halmac_p2p_ps)->discovery = pp2p_ps_para->discovery;
|
||||
(&halmac_p2p_ps)->disable_close_rf = pp2p_ps_para->disable_close_rf;
|
||||
(&halmac_p2p_ps)->p2p_port_id = _hw_port_drv2halmac(pp2p_ps_para->p2p_port_id);
|
||||
(&halmac_p2p_ps)->p2p_group = pp2p_ps_para->p2p_group;
|
||||
(&halmac_p2p_ps)->p2p_macid = pp2p_ps_para->p2p_macid;
|
||||
@@ -4636,6 +4918,247 @@ void rtw_halmac_led_switch(struct dvobj_priv *d, u8 on)
|
||||
api->halmac_pinmux_wl_led_sw_ctrl(halmac, on);
|
||||
}
|
||||
|
||||
/**
|
||||
* rtw_halmac_bt_wake_cfg() - Configure BT wake host function
|
||||
* @d: struct dvobj_priv*
|
||||
* @enable: enable or disable BT wake host function
|
||||
* 0: disable
|
||||
* 1: enable
|
||||
*
|
||||
* Configure pinmux to allow BT to control BT wake host pin.
|
||||
*
|
||||
* Rteurn 0 for OK, otherwise fail.
|
||||
*/
|
||||
int rtw_halmac_bt_wake_cfg(struct dvobj_priv *d, u8 enable)
|
||||
{
|
||||
struct halmac_adapter *halmac;
|
||||
struct halmac_api *api;
|
||||
enum halmac_ret_status status;
|
||||
|
||||
|
||||
halmac = dvobj_to_halmac(d);
|
||||
api = HALMAC_GET_API(halmac);
|
||||
|
||||
if (enable) {
|
||||
status = api->halmac_pinmux_set_func(halmac,
|
||||
HALMAC_GPIO_FUNC_BT_HOST_WAKE1);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
RTW_ERR("%s: pinmux set BT_HOST_WAKE1 fail!(0x%x)\n",
|
||||
__FUNCTION__, status);
|
||||
return -1;
|
||||
}
|
||||
} else {
|
||||
status = api->halmac_pinmux_free_func(halmac,
|
||||
HALMAC_GPIO_FUNC_BT_HOST_WAKE1);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
RTW_ERR("%s: pinmux free BT_HOST_WAKE1 fail!(0x%x)\n",
|
||||
__FUNCTION__, status);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PNO_SUPPORT
|
||||
/**
|
||||
* _halmac_scanoffload() - Switch channel by firmware during scanning
|
||||
* @d: struct dvobj_priv*
|
||||
* @enable: 1: enable, 0: disable
|
||||
* @nlo: 1: nlo mode (no c2h event), 0: normal mode
|
||||
* @ssid: ssid of probe request
|
||||
* @ssid_len: ssid length
|
||||
*
|
||||
* Switch Channel and Send Porbe Request Offloaded by FW
|
||||
*
|
||||
* Rteurn 0 for OK, otherwise fail.
|
||||
*/
|
||||
static int _halmac_scanoffload(struct dvobj_priv *d, u32 enable, u8 nlo,
|
||||
u8 *ssid, u8 ssid_len)
|
||||
{
|
||||
struct _ADAPTER *adapter;
|
||||
struct halmac_adapter *mac;
|
||||
struct halmac_api *api;
|
||||
enum halmac_ret_status status;
|
||||
struct halmac_ch_info ch_info;
|
||||
struct halmac_ch_switch_option cs_option;
|
||||
struct mlme_ext_priv *pmlmeext;
|
||||
enum halmac_feature_id id_update, id_ch_sw;
|
||||
struct halmac_indicator *indicator, *tbl;
|
||||
|
||||
int err = 0;
|
||||
u8 probereq[64];
|
||||
u32 len = 0;
|
||||
int i = 0;
|
||||
struct pno_ssid pnossid;
|
||||
struct rf_ctl_t *rfctl = NULL;
|
||||
struct _RT_CHANNEL_INFO *ch_set;
|
||||
|
||||
|
||||
tbl = d->hmpriv.indicator;
|
||||
adapter = dvobj_get_primary_adapter(d);
|
||||
mac = dvobj_to_halmac(d);
|
||||
if (!mac)
|
||||
return -1;
|
||||
api = HALMAC_GET_API(mac);
|
||||
id_update = HALMAC_FEATURE_UPDATE_PACKET;
|
||||
id_ch_sw = HALMAC_FEATURE_CHANNEL_SWITCH;
|
||||
pmlmeext = &(adapter->mlmeextpriv);
|
||||
rfctl = adapter_to_rfctl(adapter);
|
||||
ch_set = rfctl->channel_set;
|
||||
|
||||
RTW_INFO("%s: %s scanoffload, mode: %s\n",
|
||||
__FUNCTION__, enable?"Enable":"Disable",
|
||||
nlo?"PNO/NLO":"Normal");
|
||||
|
||||
if (enable) {
|
||||
_rtw_memset(probereq, 0, sizeof(probereq));
|
||||
|
||||
_rtw_memset(&pnossid, 0, sizeof(pnossid));
|
||||
if (ssid) {
|
||||
if (ssid_len > sizeof(pnossid.SSID)) {
|
||||
RTW_ERR("%s: SSID length(%d) is too long(>%d)!!\n",
|
||||
__FUNCTION__, ssid_len, sizeof(pnossid.SSID));
|
||||
return -1;
|
||||
}
|
||||
|
||||
pnossid.SSID_len = ssid_len;
|
||||
_rtw_memcpy(pnossid.SSID, ssid, ssid_len);
|
||||
}
|
||||
|
||||
rtw_hal_construct_ProbeReq(adapter, probereq, &len, &pnossid);
|
||||
|
||||
if (!nlo) {
|
||||
err = init_halmac_event(d, id_update, NULL, 0);
|
||||
if (err)
|
||||
return -1;
|
||||
}
|
||||
|
||||
status = api->halmac_update_packet(mac, HALMAC_PACKET_PROBE_REQ,
|
||||
probereq, len);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
if (!nlo)
|
||||
free_halmac_event(d, id_update);
|
||||
RTW_ERR("%s: halmac_update_packet FAIL(%d)!!\n",
|
||||
__FUNCTION__, status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (!nlo) {
|
||||
err = wait_halmac_event(d, id_update);
|
||||
if (err)
|
||||
RTW_ERR("%s: wait update packet FAIL(%d)!!\n",
|
||||
__FUNCTION__, err);
|
||||
}
|
||||
|
||||
api->halmac_clear_ch_info(mac);
|
||||
|
||||
for (i = 0; i < rfctl->max_chan_nums && ch_set[i].ChannelNum != 0; i++) {
|
||||
_rtw_memset(&ch_info, 0, sizeof(ch_info));
|
||||
ch_info.extra_info = 0;
|
||||
ch_info.channel = ch_set[i].ChannelNum;
|
||||
ch_info.bw = HALMAC_BW_20;
|
||||
ch_info.pri_ch_idx = HALMAC_CH_IDX_1;
|
||||
ch_info.action_id = HALMAC_CS_ACTIVE_SCAN;
|
||||
ch_info.timeout = 1;
|
||||
status = api->halmac_add_ch_info(mac, &ch_info);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
RTW_ERR("%s: add_ch_info FAIL(%d)!!\n",
|
||||
__FUNCTION__, status);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
/* set channel switch option */
|
||||
_rtw_memset(&cs_option, 0, sizeof(cs_option));
|
||||
cs_option.dest_bw = HALMAC_BW_20;
|
||||
cs_option.periodic_option = HALMAC_CS_PERIODIC_2_PHASE;
|
||||
cs_option.dest_pri_ch_idx = HALMAC_CH_IDX_UNDEFINE;
|
||||
cs_option.tsf_low = 0;
|
||||
cs_option.switch_en = 1;
|
||||
cs_option.dest_ch_en = 1;
|
||||
cs_option.absolute_time_en = 0;
|
||||
cs_option.dest_ch = 1;
|
||||
|
||||
cs_option.normal_period = 5;
|
||||
cs_option.normal_period_sel = 0;
|
||||
cs_option.normal_cycle = 10;
|
||||
|
||||
cs_option.phase_2_period = 1;
|
||||
cs_option.phase_2_period_sel = 1;
|
||||
|
||||
/* nlo is for wow fw, 1: no c2h response */
|
||||
cs_option.nlo_en = nlo;
|
||||
|
||||
if (!nlo) {
|
||||
err = init_halmac_event(d, id_ch_sw, NULL, 0);
|
||||
if (err)
|
||||
return -1;
|
||||
}
|
||||
|
||||
status = api->halmac_ctrl_ch_switch(mac, &cs_option);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
if (!nlo)
|
||||
free_halmac_event(d, id_ch_sw);
|
||||
RTW_ERR("%s: halmac_ctrl_ch_switch FAIL(%d)!!\n",
|
||||
__FUNCTION__, status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (!nlo) {
|
||||
err = wait_halmac_event(d, id_ch_sw);
|
||||
if (err)
|
||||
RTW_ERR("%s: wait ctrl_ch_switch FAIL(%d)!!\n",
|
||||
__FUNCTION__, err);
|
||||
}
|
||||
} else {
|
||||
api->halmac_clear_ch_info(mac);
|
||||
|
||||
_rtw_memset(&cs_option, 0, sizeof(cs_option));
|
||||
cs_option.switch_en = 0;
|
||||
|
||||
if (!nlo) {
|
||||
err = init_halmac_event(d, id_ch_sw, NULL, 0);
|
||||
if (err)
|
||||
return -1;
|
||||
}
|
||||
|
||||
status = api->halmac_ctrl_ch_switch(mac, &cs_option);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
if (!nlo)
|
||||
free_halmac_event(d, id_ch_sw);
|
||||
RTW_ERR("%s: halmac_ctrl_ch_switch FAIL(%d)!!\n",
|
||||
__FUNCTION__, status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (!nlo) {
|
||||
err = wait_halmac_event(d, id_ch_sw);
|
||||
if (err)
|
||||
RTW_ERR("%s: wait ctrl_ch_switch FAIL(%d)!!\n",
|
||||
__FUNCTION__, err);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* rtw_halmac_pno_scanoffload() - Control firmware scan AP function for PNO
|
||||
* @d: struct dvobj_priv*
|
||||
* @enable: 1: enable, 0: disable
|
||||
*
|
||||
* Switch firmware scan AP function for PNO(prefer network offload) or
|
||||
* NLO(network list offload).
|
||||
*
|
||||
* Rteurn 0 for OK, otherwise fail.
|
||||
*/
|
||||
int rtw_halmac_pno_scanoffload(struct dvobj_priv *d, u32 enable)
|
||||
{
|
||||
return _halmac_scanoffload(d, enable, 1, NULL, 0);
|
||||
}
|
||||
#endif /* CONFIG_PNO_SUPPORT */
|
||||
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
|
||||
/*
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2015 - 2017 Realtek Corporation.
|
||||
* Copyright(c) 2015 - 2018 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
@@ -152,6 +152,7 @@ int rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct r
|
||||
int rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid);
|
||||
int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw);
|
||||
int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop);
|
||||
int rtw_halmac_set_rts_full_bw(struct dvobj_priv *d, u8 enable);
|
||||
|
||||
/* Functions */
|
||||
int rtw_halmac_poweron(struct dvobj_priv *);
|
||||
@@ -196,6 +197,10 @@ int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment);
|
||||
int rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para);
|
||||
int rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode);
|
||||
void rtw_halmac_led_switch(struct dvobj_priv *d, u8 on);
|
||||
int rtw_halmac_bt_wake_cfg(struct dvobj_priv *d, u8 enable);
|
||||
#ifdef CONFIG_PNO_SUPPORT
|
||||
int rtw_halmac_pno_scanoffload(struct dvobj_priv *d, u32 enable);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
int rtw_halmac_query_tx_page_num(struct dvobj_priv *);
|
||||
|
||||
@@ -333,6 +333,13 @@ u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr)
|
||||
|
||||
wvalue = (u16)(addr & 0x0000ffff);
|
||||
len = 1;
|
||||
|
||||
/* WLANON PAGE0_REG needs to add an offset 0x8000 */
|
||||
#if defined(CONFIG_RTL8710B)
|
||||
if(wvalue >= 0x0000 && wvalue < 0x0100)
|
||||
wvalue |= 0x8000;
|
||||
#endif
|
||||
|
||||
usbctrl_vendorreq(pintfhdl, request, wvalue, index,
|
||||
&data, len, requesttype);
|
||||
|
||||
@@ -356,6 +363,13 @@ u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr)
|
||||
|
||||
wvalue = (u16)(addr & 0x0000ffff);
|
||||
len = 2;
|
||||
|
||||
/* WLANON PAGE0_REG needs to add an offset 0x8000 */
|
||||
#if defined(CONFIG_RTL8710B)
|
||||
if(wvalue >= 0x0000 && wvalue < 0x0100)
|
||||
wvalue |= 0x8000;
|
||||
#endif
|
||||
|
||||
usbctrl_vendorreq(pintfhdl, request, wvalue, index,
|
||||
&data, len, requesttype);
|
||||
|
||||
@@ -380,6 +394,13 @@ u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr)
|
||||
|
||||
wvalue = (u16)(addr & 0x0000ffff);
|
||||
len = 4;
|
||||
|
||||
/* WLANON PAGE0_REG needs to add an offset 0x8000 */
|
||||
#if defined(CONFIG_RTL8710B)
|
||||
if(wvalue >= 0x0000 && wvalue < 0x0100)
|
||||
wvalue |= 0x8000;
|
||||
#endif
|
||||
|
||||
usbctrl_vendorreq(pintfhdl, request, wvalue, index,
|
||||
&data, len, requesttype);
|
||||
|
||||
@@ -404,8 +425,14 @@ int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
|
||||
|
||||
wvalue = (u16)(addr & 0x0000ffff);
|
||||
len = 1;
|
||||
|
||||
data = val;
|
||||
|
||||
/* WLANON PAGE0_REG needs to add an offset 0x8000 */
|
||||
#if defined(CONFIG_RTL8710B)
|
||||
if(wvalue >= 0x0000 && wvalue < 0x0100)
|
||||
wvalue |= 0x8000;
|
||||
#endif
|
||||
|
||||
ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index,
|
||||
&data, len, requesttype);
|
||||
|
||||
@@ -430,8 +457,14 @@ int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val)
|
||||
|
||||
wvalue = (u16)(addr & 0x0000ffff);
|
||||
len = 2;
|
||||
|
||||
data = val;
|
||||
|
||||
/* WLANON PAGE0_REG needs to add an offset 0x8000 */
|
||||
#if defined(CONFIG_RTL8710B)
|
||||
if(wvalue >= 0x0000 && wvalue < 0x0100)
|
||||
wvalue |= 0x8000;
|
||||
#endif
|
||||
|
||||
ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index,
|
||||
&data, len, requesttype);
|
||||
|
||||
@@ -458,6 +491,13 @@ int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val)
|
||||
wvalue = (u16)(addr & 0x0000ffff);
|
||||
len = 4;
|
||||
data = val;
|
||||
|
||||
/* WLANON PAGE0_REG needs to add an offset 0x8000 */
|
||||
#if defined(CONFIG_RTL8710B)
|
||||
if(wvalue >= 0x0000 && wvalue < 0x0100)
|
||||
wvalue |= 0x8000;
|
||||
#endif
|
||||
|
||||
ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index,
|
||||
&data, len, requesttype);
|
||||
|
||||
|
||||
185
hal/hal_intf.c
185
hal/hal_intf.c
@@ -28,9 +28,12 @@ const u32 _chip_type_to_odm_ic_type[] = {
|
||||
ODM_RTL8814A,
|
||||
ODM_RTL8703B,
|
||||
ODM_RTL8188F,
|
||||
ODM_RTL8188F,
|
||||
ODM_RTL8822B,
|
||||
ODM_RTL8723D,
|
||||
ODM_RTL8821C,
|
||||
ODM_RTL8710B,
|
||||
ODM_RTL8192F,
|
||||
0,
|
||||
};
|
||||
|
||||
@@ -75,12 +78,56 @@ void rtw_hal_read_chip_version(_adapter *padapter)
|
||||
rtw_odm_init_ic_type(padapter);
|
||||
}
|
||||
|
||||
static void rtw_init_wireless_mode(_adapter *padapter)
|
||||
{
|
||||
u8 proto_wireless_mode = 0;
|
||||
struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
|
||||
if(hal_spec->proto_cap & PROTO_CAP_11B)
|
||||
proto_wireless_mode |= WIRELESS_11B;
|
||||
|
||||
if(hal_spec->proto_cap & PROTO_CAP_11G)
|
||||
proto_wireless_mode |= WIRELESS_11G;
|
||||
#ifdef CONFIG_80211AC_VHT
|
||||
if(hal_spec->band_cap & BAND_CAP_5G)
|
||||
proto_wireless_mode |= WIRELESS_11A;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_80211N_HT
|
||||
if(hal_spec->proto_cap & PROTO_CAP_11N) {
|
||||
|
||||
if(hal_spec->band_cap & BAND_CAP_2G)
|
||||
proto_wireless_mode |= WIRELESS_11_24N;
|
||||
if(hal_spec->band_cap & BAND_CAP_5G)
|
||||
proto_wireless_mode |= WIRELESS_11_5N;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_80211AC_VHT
|
||||
if(hal_spec->proto_cap & PROTO_CAP_11AC)
|
||||
proto_wireless_mode |= WIRELESS_11AC;
|
||||
#endif
|
||||
padapter->registrypriv.wireless_mode &= proto_wireless_mode;
|
||||
}
|
||||
|
||||
void rtw_hal_def_value_init(_adapter *padapter)
|
||||
{
|
||||
if (is_primary_adapter(padapter)) {
|
||||
/*init fw_psmode_iface_id*/
|
||||
adapter_to_pwrctl(padapter)->fw_psmode_iface_id = 0xff;
|
||||
/*wireless_mode*/
|
||||
rtw_init_wireless_mode(padapter);
|
||||
padapter->hal_func.init_default_value(padapter);
|
||||
|
||||
rtw_init_hal_com_default_value(padapter);
|
||||
|
||||
#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
|
||||
adapter_to_dvobj(padapter)->dft.port_id = 0xFF;
|
||||
adapter_to_dvobj(padapter)->dft.mac_id = 0xFF;
|
||||
#endif
|
||||
#ifdef CONFIG_HW_P0_TSF_SYNC
|
||||
adapter_to_dvobj(padapter)->p0_tsf.sync_port = MAX_HW_PORT;
|
||||
adapter_to_dvobj(padapter)->p0_tsf.offset = 0;
|
||||
#endif
|
||||
|
||||
{
|
||||
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
|
||||
@@ -92,6 +139,7 @@ void rtw_hal_def_value_init(_adapter *padapter)
|
||||
dvobj->cam_ctl.sec_cap = hal_spec->sec_cap;
|
||||
dvobj->cam_ctl.num = rtw_min(hal_spec->sec_cam_ent_num, SEC_CAM_ENT_NUM_SW_LIMIT);
|
||||
}
|
||||
GET_HAL_DATA(padapter)->rx_tsf_addr_filter_config = 0;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -104,6 +152,7 @@ u8 rtw_hal_data_init(_adapter *padapter)
|
||||
RTW_INFO("cant not alloc memory for HAL DATA\n");
|
||||
return _FAIL;
|
||||
}
|
||||
rtw_phydm_priv_init(padapter);
|
||||
}
|
||||
return _SUCCESS;
|
||||
}
|
||||
@@ -237,6 +286,57 @@ void rtw_hal_init_opmode(_adapter *padapter)
|
||||
rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_DIRECTLY);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_NEW_NETDEV_HDL
|
||||
uint rtw_hal_iface_init(_adapter *adapter)
|
||||
{
|
||||
uint status = _SUCCESS;
|
||||
|
||||
rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter_mac_addr(adapter));
|
||||
#ifdef RTW_HALMAC
|
||||
rtw_hal_hw_port_enable(adapter);
|
||||
#endif
|
||||
rtw_sec_restore_wep_key(adapter);
|
||||
rtw_hal_init_opmode(adapter);
|
||||
rtw_hal_start_thread(adapter);
|
||||
return status;
|
||||
}
|
||||
uint rtw_hal_init(_adapter *padapter)
|
||||
{
|
||||
uint status = _SUCCESS;
|
||||
|
||||
status = padapter->hal_func.hal_init(padapter);
|
||||
|
||||
if (status == _SUCCESS) {
|
||||
rtw_set_hw_init_completed(padapter, _TRUE);
|
||||
if (padapter->registrypriv.notch_filter == 1)
|
||||
rtw_hal_notch_filter(padapter, 1);
|
||||
rtw_led_control(padapter, LED_CTL_POWER_ON);
|
||||
init_hw_mlme_ext(padapter);
|
||||
#ifdef CONFIG_RF_POWER_TRIM
|
||||
rtw_bb_rf_gain_offset(padapter);
|
||||
#endif /*CONFIG_RF_POWER_TRIM*/
|
||||
GET_PRIMARY_ADAPTER(padapter)->bup = _TRUE; /*temporary*/
|
||||
#ifdef CONFIG_MI_WITH_MBSSID_CAM
|
||||
rtw_mi_set_mbid_cam(padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_SUPPORT_MULTI_BCN
|
||||
rtw_ap_multi_bcn_cfg(padapter);
|
||||
#endif
|
||||
#if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)
|
||||
#ifdef CONFIG_DYNAMIC_SOML
|
||||
rtw_dyn_soml_config(padapter);
|
||||
#endif
|
||||
#endif
|
||||
#ifdef CONFIG_RTW_TX_2PATH_EN
|
||||
rtw_phydm_tx_2path_en(padapter);
|
||||
#endif
|
||||
} else {
|
||||
rtw_set_hw_init_completed(padapter, _FALSE);
|
||||
RTW_ERR("%s: hal_init fail\n", __func__);
|
||||
}
|
||||
return status;
|
||||
}
|
||||
#else
|
||||
uint rtw_hal_init(_adapter *padapter)
|
||||
{
|
||||
uint status = _SUCCESS;
|
||||
@@ -247,7 +347,7 @@ uint rtw_hal_init(_adapter *padapter)
|
||||
|
||||
if (status == _SUCCESS) {
|
||||
rtw_set_hw_init_completed(padapter, _TRUE);
|
||||
rtw_restore_mac_addr(padapter);
|
||||
rtw_mi_set_mac_addr(padapter);/*set mac addr of all ifaces*/
|
||||
#ifdef RTW_HALMAC
|
||||
rtw_restore_hw_port_cfg(padapter);
|
||||
#endif
|
||||
@@ -263,9 +363,13 @@ uint rtw_hal_init(_adapter *padapter)
|
||||
|
||||
rtw_hal_init_opmode(padapter);
|
||||
|
||||
#ifdef CONFIG_RF_POWER_TRIM
|
||||
#ifdef CONFIG_RF_POWER_TRIM
|
||||
rtw_bb_rf_gain_offset(padapter);
|
||||
#endif /*CONFIG_RF_POWER_TRIM*/
|
||||
#endif /*CONFIG_RF_POWER_TRIM*/
|
||||
|
||||
#ifdef CONFIG_SUPPORT_MULTI_BCN
|
||||
rtw_ap_multi_bcn_cfg(padapter);
|
||||
#endif
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)
|
||||
#ifdef CONFIG_DYNAMIC_SOML
|
||||
@@ -273,6 +377,9 @@ uint rtw_hal_init(_adapter *padapter)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTW_TX_2PATH_EN
|
||||
rtw_phydm_tx_2path_en(padapter);
|
||||
#endif
|
||||
} else {
|
||||
rtw_set_hw_init_completed(padapter, _FALSE);
|
||||
RTW_ERR("%s: fail\n", __func__);
|
||||
@@ -282,6 +389,7 @@ uint rtw_hal_init(_adapter *padapter)
|
||||
return status;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
uint rtw_hal_deinit(_adapter *padapter)
|
||||
{
|
||||
@@ -633,6 +741,23 @@ void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr,
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYSON_INDIRECT_ACCESS
|
||||
u32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask)
|
||||
{
|
||||
u32 data = 0;
|
||||
if (padapter->hal_func.read_syson_reg)
|
||||
data = padapter->hal_func.read_syson_reg(padapter, RegAddr, BitMask);
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
void rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
|
||||
{
|
||||
if (padapter->hal_func.write_syson_reg)
|
||||
padapter->hal_func.write_syson_reg(padapter, RegAddr, BitMask, Data);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI_HCI)
|
||||
s32 rtw_hal_interrupt_handler(_adapter *padapter)
|
||||
{
|
||||
@@ -640,6 +765,11 @@ s32 rtw_hal_interrupt_handler(_adapter *padapter)
|
||||
ret = padapter->hal_func.interrupt_handler(padapter);
|
||||
return ret;
|
||||
}
|
||||
|
||||
void rtw_hal_unmap_beacon_icf(_adapter *padapter)
|
||||
{
|
||||
padapter->hal_func.unmap_beacon_icf(padapter);
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
|
||||
void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf)
|
||||
@@ -1074,33 +1204,37 @@ static s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8
|
||||
{
|
||||
struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
|
||||
u16 reg_sleep;
|
||||
u32 *m = &bmp->m0;
|
||||
u32 m;
|
||||
u8 mid = 0;
|
||||
u32 val32;
|
||||
|
||||
do {
|
||||
if (*m == 0)
|
||||
goto move_next;
|
||||
|
||||
if (mid == 0)
|
||||
if (mid == 0) {
|
||||
m = bmp->m0;
|
||||
reg_sleep = macid_ctl->reg_sleep_m0;
|
||||
#if (MACID_NUM_SW_LIMIT > 32)
|
||||
else if (mid == 1)
|
||||
} else if (mid == 1) {
|
||||
m = bmp->m1;
|
||||
reg_sleep = macid_ctl->reg_sleep_m1;
|
||||
#endif
|
||||
#if (MACID_NUM_SW_LIMIT > 64)
|
||||
else if (mid == 2)
|
||||
} else if (mid == 2) {
|
||||
m = bmp->m2;
|
||||
reg_sleep = macid_ctl->reg_sleep_m2;
|
||||
#endif
|
||||
#if (MACID_NUM_SW_LIMIT > 96)
|
||||
else if (mid == 3)
|
||||
} else if (mid == 3) {
|
||||
m = bmp->m3;
|
||||
reg_sleep = macid_ctl->reg_sleep_m3;
|
||||
#endif
|
||||
else {
|
||||
} else {
|
||||
rtw_warn_on(1);
|
||||
break;
|
||||
}
|
||||
|
||||
if (m == 0)
|
||||
goto move_next;
|
||||
|
||||
if (!reg_sleep) {
|
||||
rtw_warn_on(1);
|
||||
break;
|
||||
@@ -1109,22 +1243,21 @@ static s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8
|
||||
val32 = rtw_read32(adapter, reg_sleep);
|
||||
RTW_INFO(ADPT_FMT" %s m%u=0x%08x, ori reg_0x%03x=0x%08x\n"
|
||||
, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
|
||||
, mid, *m, reg_sleep, val32);
|
||||
, mid, m, reg_sleep, val32);
|
||||
|
||||
if (sleep) {
|
||||
if ((val32 & *m) == *m)
|
||||
if ((val32 & m) == m)
|
||||
goto move_next;
|
||||
val32 |= *m;
|
||||
val32 |= m;
|
||||
} else {
|
||||
if ((val32 & *m) == 0)
|
||||
if ((val32 & m) == 0)
|
||||
goto move_next;
|
||||
val32 &= ~(*m);
|
||||
val32 &= ~m;
|
||||
}
|
||||
|
||||
rtw_write32(adapter, reg_sleep, val32);
|
||||
|
||||
move_next:
|
||||
m++;
|
||||
mid++;
|
||||
} while (mid * 32 < MACID_NUM_SW_LIMIT);
|
||||
|
||||
@@ -1204,11 +1337,13 @@ void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FW_CORRECT_BCN
|
||||
void rtw_hal_fw_correct_bcn(_adapter *padapter)
|
||||
{
|
||||
if (padapter->hal_func.fw_correct_bcn)
|
||||
padapter->hal_func.fw_correct_bcn(padapter);
|
||||
}
|
||||
#endif
|
||||
|
||||
void rtw_hal_set_tx_power_index(PADAPTER padapter, u32 powerindex, enum rf_path rfpath, u8 rate)
|
||||
{
|
||||
@@ -1501,20 +1636,18 @@ u8 rtw_hal_ops_check(_adapter *padapter)
|
||||
}
|
||||
#endif
|
||||
|
||||
if ((IS_HARDWARE_TYPE_8814A(padapter)
|
||||
|| IS_HARDWARE_TYPE_8822BU(padapter) || IS_HARDWARE_TYPE_8822BS(padapter))
|
||||
#ifdef CONFIG_FW_CORRECT_BCN
|
||||
if (IS_HARDWARE_TYPE_8814A(padapter)
|
||||
&& NULL == padapter->hal_func.fw_correct_bcn) {
|
||||
rtw_hal_error_msg("fw_correct_bcn");
|
||||
ret = _FAIL;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (IS_HARDWARE_TYPE_8822B(padapter) || IS_HARDWARE_TYPE_8821C(padapter)) {
|
||||
if (!padapter->hal_func.set_tx_power_index_handler) {
|
||||
rtw_hal_error_msg("set_tx_power_index_handler");
|
||||
ret = _FAIL;
|
||||
}
|
||||
if (!padapter->hal_func.set_tx_power_index_handler) {
|
||||
rtw_hal_error_msg("set_tx_power_index_handler");
|
||||
ret = _FAIL;
|
||||
}
|
||||
|
||||
if (!padapter->hal_func.get_tx_power_index_handler) {
|
||||
rtw_hal_error_msg("get_tx_power_index_handler");
|
||||
ret = _FAIL;
|
||||
|
||||
531
hal/hal_mcc.c
531
hal/hal_mcc.c
File diff suppressed because it is too large
Load Diff
208
hal/hal_mp.c
208
hal/hal_mp.c
@@ -42,9 +42,18 @@
|
||||
#ifdef CONFIG_RTL8723D
|
||||
#include <rtl8723d_hal.h>
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8710B
|
||||
#include <rtl8710b_hal.h>
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8188F
|
||||
#include <rtl8188f_hal.h>
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8188GTV
|
||||
#include <rtl8188gtv_hal.h>
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8192F
|
||||
#include <rtl8192f_hal.h>
|
||||
#endif
|
||||
#endif /* !RTW_HALMAC */
|
||||
|
||||
|
||||
@@ -145,7 +154,8 @@ void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
|
||||
u1Byte DataRate = 0xFF;
|
||||
|
||||
/* Do not modify CCK TX filter parameters for 8822B*/
|
||||
if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter))
|
||||
if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) ||
|
||||
IS_HARDWARE_TYPE_8723D(Adapter) || IS_HARDWARE_TYPE_8192F(Adapter))
|
||||
return;
|
||||
|
||||
DataRate = mpt_to_mgnt_rate(ulRateIdx);
|
||||
@@ -183,7 +193,7 @@ void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
|
||||
pHalData->RegForRecover[i].value);
|
||||
}
|
||||
}
|
||||
} else if (IS_HARDWARE_TYPE_8188F(Adapter)) {
|
||||
} else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
|
||||
/* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
|
||||
CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
|
||||
CCKSwingIndex = 20; /* default index */
|
||||
@@ -320,15 +330,17 @@ void hal_mpt_SetChannel(PADAPTER pAdapter)
|
||||
pHalData->bSwChnl = _TRUE;
|
||||
pHalData->bSetChnlBW = _TRUE;
|
||||
|
||||
if (bandwidth > 0) {
|
||||
if ((channel >= 3 && channel <= 11) || (channel >= 42 && channel <= 171))
|
||||
rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, pmp->prime_channel_offset);
|
||||
else
|
||||
rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
|
||||
} else
|
||||
rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
|
||||
#ifdef CONFIG_RTL8822B
|
||||
if (bandwidth == 2) {
|
||||
rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
|
||||
} else if (bandwidth == 1) {
|
||||
rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
|
||||
} else
|
||||
#endif
|
||||
rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
|
||||
|
||||
hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
|
||||
rtw_btcoex_wifionly_scan_notify(pAdapter);
|
||||
|
||||
}
|
||||
|
||||
@@ -347,15 +359,18 @@ void hal_mpt_SetBandwidth(PADAPTER pAdapter)
|
||||
pHalData->bSwChnl = _TRUE;
|
||||
pHalData->bSetChnlBW = _TRUE;
|
||||
|
||||
if (bandwidth > 0) {
|
||||
if ((channel >= 3 && channel <= 11) || (channel >= 42 && channel <= 171))
|
||||
rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, pmp->prime_channel_offset);
|
||||
else
|
||||
rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
|
||||
} else
|
||||
rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
|
||||
#ifdef CONFIG_RTL8822B
|
||||
if (bandwidth == 2) {
|
||||
rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
|
||||
} else if (bandwidth == 1) {
|
||||
rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
|
||||
} else
|
||||
#endif
|
||||
rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
|
||||
|
||||
hal_mpt_SwitchRfSetting(pAdapter);
|
||||
rtw_btcoex_wifionly_scan_notify(pAdapter);
|
||||
|
||||
}
|
||||
|
||||
void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
|
||||
@@ -430,7 +445,8 @@ mpt_SetTxPower(
|
||||
|
||||
if (IS_HARDWARE_TYPE_8814A(pAdapter))
|
||||
EndPath = RF_PATH_D;
|
||||
else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
|
||||
else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)
|
||||
|| IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
|
||||
EndPath = RF_PATH_A;
|
||||
|
||||
switch (Rate) {
|
||||
@@ -522,7 +538,9 @@ void hal_mpt_SetTxPower(PADAPTER pAdapter)
|
||||
IS_HARDWARE_TYPE_8723B(pAdapter) ||
|
||||
IS_HARDWARE_TYPE_8192E(pAdapter) ||
|
||||
IS_HARDWARE_TYPE_8703B(pAdapter) ||
|
||||
IS_HARDWARE_TYPE_8188F(pAdapter)) {
|
||||
IS_HARDWARE_TYPE_8188F(pAdapter) ||
|
||||
IS_HARDWARE_TYPE_8188GTV(pAdapter)
|
||||
) {
|
||||
u8 path = (pHalData->antenna_tx_path == ANTENNA_A) ? (RF_PATH_A) : (RF_PATH_B);
|
||||
|
||||
RTW_INFO("===> MPT_ProSetTxPower: Old\n");
|
||||
@@ -531,12 +549,14 @@ void hal_mpt_SetTxPower(PADAPTER pAdapter)
|
||||
mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
|
||||
|
||||
} else {
|
||||
RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n");
|
||||
|
||||
mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
|
||||
mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
|
||||
mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
|
||||
mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
|
||||
|
||||
if(IS_HARDWARE_TYPE_JAGUAR(pAdapter)||IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
|
||||
RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n");
|
||||
mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
|
||||
}
|
||||
}
|
||||
} else
|
||||
RTW_INFO("RFChipID < RF_CHIP_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
|
||||
@@ -556,7 +576,7 @@ void hal_mpt_SetDataRate(PADAPTER pAdapter)
|
||||
|
||||
hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
|
||||
#ifdef CONFIG_RTL8723B
|
||||
if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter)) {
|
||||
if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
|
||||
if (IS_CCK_RATE(DataRate)) {
|
||||
if (pMptCtx->mpt_rf_path == RF_PATH_A)
|
||||
phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0x6);
|
||||
@@ -618,7 +638,6 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter)
|
||||
R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
|
||||
R_ANTENNA_SELECT_CCK *p_cck_txrx;
|
||||
u8 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
|
||||
u8 HtStbcCap = pAdapter->registrypriv.stbc_cap;
|
||||
/*/PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);*/
|
||||
/*/PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
|
||||
|
||||
@@ -1425,6 +1444,65 @@ VOID mpt_SetRFPath_819X(PADAPTER pAdapter)
|
||||
}
|
||||
} /* MPT_ProSetRFPath */
|
||||
|
||||
#ifdef CONFIG_RTL8192F
|
||||
|
||||
void mpt_set_rfpath_8192f(PADAPTER pAdapter)
|
||||
{
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
|
||||
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
|
||||
|
||||
u16 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
|
||||
u8 NssforRate, odmNssforRate;
|
||||
u32 ulAntennaTx, ulAntennaRx;
|
||||
u8 RxAntToPhyDm;
|
||||
u8 TxAntToPhyDm;
|
||||
|
||||
ulAntennaTx = pHalData->antenna_tx_path;
|
||||
ulAntennaRx = pHalData->AntennaRxPath;
|
||||
NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
|
||||
|
||||
if (pHalData->rf_chip >= RF_TYPE_MAX)
|
||||
RTW_INFO("This RF chip ID is not supported\n");
|
||||
|
||||
switch (ulAntennaTx) {
|
||||
case ANTENNA_A:
|
||||
pMptCtx->mpt_rf_path = RF_PATH_A;
|
||||
TxAntToPhyDm = BB_PATH_A;
|
||||
break;
|
||||
case ANTENNA_B:
|
||||
pMptCtx->mpt_rf_path = RF_PATH_B;
|
||||
TxAntToPhyDm = BB_PATH_B;
|
||||
break;
|
||||
case ANTENNA_AB:
|
||||
pMptCtx->mpt_rf_path = RF_PATH_AB;
|
||||
TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
|
||||
break;
|
||||
default:
|
||||
pMptCtx->mpt_rf_path = RF_PATH_AB;
|
||||
TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
|
||||
break;
|
||||
}
|
||||
|
||||
switch (ulAntennaRx) {
|
||||
case ANTENNA_A:
|
||||
RxAntToPhyDm = BB_PATH_A;
|
||||
break;
|
||||
case ANTENNA_B:
|
||||
RxAntToPhyDm = BB_PATH_B;
|
||||
break;
|
||||
case ANTENNA_AB:
|
||||
RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
|
||||
break;
|
||||
default:
|
||||
RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
|
||||
break;
|
||||
}
|
||||
|
||||
config_phydm_trx_mode_8192f(GET_PDM_ODM(pAdapter), TxAntToPhyDm, RxAntToPhyDm, FALSE);
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void hal_mpt_SetAntenna(PADAPTER pAdapter)
|
||||
|
||||
@@ -1474,6 +1552,14 @@ void hal_mpt_SetAntenna(PADAPTER pAdapter)
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8192F
|
||||
if (IS_HARDWARE_TYPE_8192F(pAdapter)) {
|
||||
mpt_set_rfpath_8192f(pAdapter);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* else if (IS_HARDWARE_TYPE_8821B(pAdapter))
|
||||
mpt_SetRFPath_8821B(pAdapter);
|
||||
Prepare for 8822B
|
||||
@@ -1641,6 +1727,18 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
|
||||
phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF);
|
||||
phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/
|
||||
phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
|
||||
} else if (IS_HARDWARE_TYPE_8192F(pAdapter)) { /* USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
|
||||
#ifdef CONFIG_RTL8192F
|
||||
phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x1);
|
||||
phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x1);
|
||||
phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x1);
|
||||
phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x1);
|
||||
phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x1);
|
||||
phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x1);
|
||||
phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0xF);
|
||||
phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x1); /* RF LO disabled*/
|
||||
phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /* Tx mode*/
|
||||
#endif
|
||||
} else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
|
||||
if (pMptCtx->mpt_rf_path == RF_PATH_A) {
|
||||
phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
|
||||
@@ -1655,7 +1753,7 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
|
||||
phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
|
||||
phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
|
||||
}
|
||||
} else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
|
||||
} else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
|
||||
/*Set BB REG 88C: Prevent SingleTone Fail*/
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
|
||||
phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1);
|
||||
@@ -1709,11 +1807,11 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
|
||||
} else if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
|
||||
phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xF0F0, 0x707); /* 0xCB0[[15:12, 7:4] = 0x707*/
|
||||
|
||||
if (pHalData->external_pa_5g)
|
||||
if (pHalData->external_pa_5g)
|
||||
{
|
||||
phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
|
||||
}
|
||||
else if (pHalData->ExternalPA_2G)
|
||||
else if (pHalData->ExternalPA_2G)
|
||||
{
|
||||
phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
|
||||
}
|
||||
@@ -1752,6 +1850,18 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
|
||||
phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */
|
||||
/*/ RESTORE MAC REG 88C: Enable RF Functions*/
|
||||
phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0);
|
||||
} else if (IS_HARDWARE_TYPE_8192F(pAdapter)){
|
||||
#ifdef CONFIG_RTL8192F
|
||||
phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x0);
|
||||
phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x0);
|
||||
phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x0);
|
||||
phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x0);
|
||||
phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x0);
|
||||
phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x0);
|
||||
phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0x0);
|
||||
phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x0); /* RF LO disabled*/
|
||||
phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /* Rx mode*/
|
||||
#endif
|
||||
} else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
|
||||
if (pMptCtx->mpt_rf_path == RF_PATH_A) {
|
||||
phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
|
||||
@@ -1766,7 +1876,7 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
|
||||
phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
|
||||
phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
|
||||
}
|
||||
} else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
|
||||
} else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
|
||||
phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/
|
||||
phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/
|
||||
/*Set BB REG 88C: Prevent SingleTone Fail*/
|
||||
@@ -2056,55 +2166,61 @@ void mpt_ProSetPMacTx(PADAPTER Adapter)
|
||||
dbg_print("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
|
||||
PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);
|
||||
|
||||
PRINT_DATA("Src Address", Adapter->mac_addr, 6);
|
||||
PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, 6);
|
||||
PRINT_DATA("Src Address", Adapter->mac_addr, ETH_ALEN);
|
||||
PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, ETH_ALEN);
|
||||
#endif
|
||||
if (Adapter->mppriv.pktInterval != 0)
|
||||
PMacTxInfo.PacketPeriod = Adapter->mppriv.pktInterval;
|
||||
if (pmppriv->pktInterval != 0)
|
||||
PMacTxInfo.PacketPeriod = pmppriv->pktInterval;
|
||||
|
||||
if (pmppriv->tx.count != 0)
|
||||
PMacTxInfo.PacketCount = pmppriv->tx.count;
|
||||
|
||||
RTW_INFO("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
|
||||
RTW_INFO("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
|
||||
PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
|
||||
|
||||
if (PMacTxInfo.bEnPMacTx == FALSE) {
|
||||
pmppriv->mode = MP_ON;
|
||||
if (PMacTxInfo.Mode == CONTINUOUS_TX) {
|
||||
if (pMptCtx->HWTxmode == CONTINUOUS_TX) {
|
||||
phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
|
||||
if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
|
||||
if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
|
||||
mpt_StopCckContTx(Adapter);
|
||||
else
|
||||
mpt_StopOfdmContTx(Adapter);
|
||||
} else if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
|
||||
} else if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index)) {
|
||||
u4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord);
|
||||
phy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);
|
||||
phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/
|
||||
} else
|
||||
phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
|
||||
|
||||
if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
|
||||
if (pMptCtx->HWTxmode == OFDM_Single_Tone_TX) {
|
||||
/* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/
|
||||
if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
|
||||
if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
|
||||
mpt_StopCckContTx(Adapter);
|
||||
else
|
||||
mpt_StopOfdmContTx(Adapter);
|
||||
|
||||
mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);
|
||||
}
|
||||
|
||||
pMptCtx->HWTxmode = TEST_NONE;
|
||||
return;
|
||||
}
|
||||
|
||||
pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
|
||||
|
||||
if (PMacTxInfo.Mode == CONTINUOUS_TX) {
|
||||
pmppriv->mode = MP_CONTINUOUS_TX;
|
||||
pMptCtx->HWTxmode = CONTINUOUS_TX;
|
||||
PMacTxInfo.PacketCount = 1;
|
||||
|
||||
hal_mpt_SetTxPower(Adapter);
|
||||
|
||||
if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
|
||||
mpt_StartCckContTx(Adapter);
|
||||
else
|
||||
mpt_StartOfdmContTx(Adapter);
|
||||
} else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
|
||||
pmppriv->mode = MP_SINGLE_TONE_TX;
|
||||
/* Continuous TX -> HW TX -> RF Setting */
|
||||
pMptCtx->HWTxmode = OFDM_Single_Tone_TX;
|
||||
PMacTxInfo.PacketCount = 1;
|
||||
|
||||
if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
|
||||
@@ -2112,7 +2228,7 @@ void mpt_ProSetPMacTx(PADAPTER Adapter)
|
||||
else
|
||||
mpt_StartOfdmContTx(Adapter);
|
||||
} else if (PMacTxInfo.Mode == PACKETS_TX) {
|
||||
pmppriv->mode = MP_PACKET_TX;
|
||||
pMptCtx->HWTxmode = PACKETS_TX;
|
||||
if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)
|
||||
PMacTxInfo.PacketCount = 0xffff;
|
||||
}
|
||||
@@ -2228,6 +2344,16 @@ void mpt_ProSetPMacTx(PADAPTER Adapter)
|
||||
phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
|
||||
else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
|
||||
phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
|
||||
|
||||
} else if(IS_HARDWARE_TYPE_JAGUAR(Adapter)) {
|
||||
u4Byte offset = 0xb4c;
|
||||
|
||||
if(IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
|
||||
phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
|
||||
else if(IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
|
||||
phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
|
||||
else if(IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
|
||||
phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
|
||||
}
|
||||
|
||||
phy_set_bb_reg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/
|
||||
|
||||
@@ -28,13 +28,19 @@
|
||||
#include <osdep_service.h> /* __BIG_ENDIAN, __LITTLE_ENDIAN, _sema, _mutex */
|
||||
#endif
|
||||
|
||||
/*[Driver] provide the define of _TRUE, _FALSE, NULL, u8, u16, u32*/
|
||||
/*[Driver] provide the define of NULL, u8, u16, u32*/
|
||||
#ifndef NULL
|
||||
#define NULL ((void *)0)
|
||||
#endif
|
||||
|
||||
#define HALMAC_INLINE inline
|
||||
|
||||
/*
|
||||
* Ignore following typedef because Linux already have these
|
||||
* u8, u16, u32, s8, s16, s32
|
||||
* __le16, __le32, __be16, __be32
|
||||
*/
|
||||
|
||||
#define HALMAC_PLATFORM_LITTLE_ENDIAN 1
|
||||
#define HALMAC_PLATFORM_BIG_ENDIAN 0
|
||||
|
||||
|
||||
@@ -55,6 +55,7 @@
|
||||
#define EFUSE_SIZE_8822B 1024
|
||||
#define EEPROM_SIZE_8822B 768
|
||||
#define BT_EFUSE_SIZE_8822B 128
|
||||
#define PRTCT_EFUSE_SIZE_8822B 96
|
||||
|
||||
#define SEC_CAM_NUM_8822B 64
|
||||
|
||||
|
||||
@@ -37,7 +37,6 @@ cfg_drv_info_8822b(struct halmac_adapter *adapter,
|
||||
u8 value8;
|
||||
u32 value32;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
struct halmac_mac_rx_ignore_cfg cfg;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
PLTFM_MSG_TRACE("[TRACE]drv info = %d\n", drv_info);
|
||||
@@ -48,28 +47,24 @@ cfg_drv_info_8822b(struct halmac_adapter *adapter,
|
||||
phy_status_en = 0;
|
||||
sniffer_en = 0;
|
||||
plcp_hdr_en = 0;
|
||||
cfg.hdr_chk_en = _FALSE;
|
||||
break;
|
||||
case HALMAC_DRV_INFO_PHY_STATUS:
|
||||
drv_info_size = 4;
|
||||
phy_status_en = 1;
|
||||
sniffer_en = 0;
|
||||
plcp_hdr_en = 0;
|
||||
cfg.hdr_chk_en = _FALSE;
|
||||
break;
|
||||
case HALMAC_DRV_INFO_PHY_SNIFFER:
|
||||
drv_info_size = 5; /* phy status 4byte, sniffer info 1byte */
|
||||
phy_status_en = 1;
|
||||
sniffer_en = 1;
|
||||
plcp_hdr_en = 0;
|
||||
cfg.hdr_chk_en = _FALSE;
|
||||
break;
|
||||
case HALMAC_DRV_INFO_PHY_PLCP:
|
||||
drv_info_size = 6; /* phy status 4byte, plcp header 2byte */
|
||||
phy_status_en = 1;
|
||||
sniffer_en = 0;
|
||||
plcp_hdr_en = 1;
|
||||
cfg.hdr_chk_en = _FALSE;
|
||||
break;
|
||||
default:
|
||||
return HALMAC_RET_SW_CASE_NOT_SUPPORT;
|
||||
@@ -79,8 +74,6 @@ cfg_drv_info_8822b(struct halmac_adapter *adapter,
|
||||
HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE)
|
||||
drv_info_size = RX_DESC_DUMMY_SIZE_8822B >> 3;
|
||||
|
||||
api->halmac_set_hw_value(adapter, HALMAC_HW_RX_IGNORE, &cfg);
|
||||
|
||||
HALMAC_REG_W8(REG_RX_DRVINFO_SZ, drv_info_size);
|
||||
|
||||
value8 = HALMAC_REG_R8(REG_TRXFF_BNDY + 1);
|
||||
@@ -127,22 +120,6 @@ void
|
||||
cfg_rx_ignore_8822b(struct halmac_adapter *adapter,
|
||||
struct halmac_mac_rx_ignore_cfg *cfg)
|
||||
{
|
||||
u8 value8;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
value8 = HALMAC_REG_R8(REG_BBPSF_CTRL);
|
||||
|
||||
/*mac header check enable*/
|
||||
if (cfg->hdr_chk_en == _TRUE)
|
||||
value8 |= BIT_BBPSF_MHCHKEN | BIT_BBPSF_MPDUCHKEN;
|
||||
else
|
||||
value8 &= ~(BIT_BBPSF_MHCHKEN) & (~(BIT_BBPSF_MPDUCHKEN));
|
||||
|
||||
HALMAC_REG_W8(REG_BBPSF_CTRL, value8);
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
}
|
||||
|
||||
enum halmac_ret_status
|
||||
|
||||
@@ -50,6 +50,10 @@ get_hw_value_8822b(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
|
||||
case HALMAC_HW_FW_MAX_SIZE:
|
||||
*(u32 *)value = WLAN_FW_MAX_SIZE_8822B;
|
||||
break;
|
||||
case HALMAC_HW_SDIO_INT_LAT:
|
||||
break;
|
||||
case HALMAC_HW_SDIO_CLK_CNT:
|
||||
break;
|
||||
default:
|
||||
return HALMAC_RET_PARA_NOT_SUPPORT;
|
||||
}
|
||||
@@ -94,14 +98,16 @@ set_hw_value_8822b(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
|
||||
case HALMAC_HW_RXGCK_FIFO:
|
||||
break;
|
||||
case HALMAC_HW_RX_IGNORE:
|
||||
cfg_rx_ignore_8822b(adapter,
|
||||
(struct halmac_mac_rx_ignore_cfg *)value);
|
||||
break;
|
||||
case HALMAC_HW_LDO25_EN:
|
||||
cfg_ldo25_8822b(adapter, *(u8 *)value);
|
||||
break;
|
||||
case HALMAC_HW_PCIE_REF_AUTOK:
|
||||
break;
|
||||
case HALMAC_HW_SDIO_WT_EN:
|
||||
break;
|
||||
case HALMAC_HW_SDIO_CLK_MONITOR:
|
||||
break;
|
||||
default:
|
||||
return HALMAC_RET_PARA_NOT_SUPPORT;
|
||||
}
|
||||
@@ -122,8 +128,8 @@ set_hw_value_8822b(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
|
||||
enum halmac_ret_status
|
||||
fill_txdesc_check_sum_8822b(struct halmac_adapter *adapter, u8 *txdesc)
|
||||
{
|
||||
u16 chksum = 0;
|
||||
u16 *data = (u16 *)NULL;
|
||||
__le16 chksum = 0;
|
||||
__le16 *data;
|
||||
u32 i;
|
||||
|
||||
if (!txdesc) {
|
||||
@@ -131,12 +137,12 @@ fill_txdesc_check_sum_8822b(struct halmac_adapter *adapter, u8 *txdesc)
|
||||
return HALMAC_RET_NULL_POINTER;
|
||||
}
|
||||
|
||||
if (adapter->tx_desc_checksum != _TRUE)
|
||||
if (adapter->tx_desc_checksum != 1)
|
||||
PLTFM_MSG_TRACE("[TRACE]chksum disable");
|
||||
|
||||
SET_TX_DESC_TXDESC_CHECKSUM(txdesc, 0x0000);
|
||||
|
||||
data = (u16 *)(txdesc);
|
||||
data = (__le16 *)(txdesc);
|
||||
|
||||
/* HW clculates only 32byte */
|
||||
for (i = 0; i < 8; i++)
|
||||
@@ -144,9 +150,7 @@ fill_txdesc_check_sum_8822b(struct halmac_adapter *adapter, u8 *txdesc)
|
||||
|
||||
/* *(data + 2 * i) & *(data + (2 * i + 1) have endain issue*/
|
||||
/* Process eniadn issue after checksum calculation */
|
||||
chksum = rtk_le16_to_cpu(chksum);
|
||||
|
||||
SET_TX_DESC_TXDESC_CHECKSUM(txdesc, chksum);
|
||||
SET_TX_DESC_TXDESC_CHECKSUM(txdesc, rtk_le16_to_cpu(chksum));
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
@@ -159,7 +163,7 @@ cfg_ldo25_8822b(struct halmac_adapter *adapter, u8 enable)
|
||||
|
||||
value8 = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 3);
|
||||
|
||||
if (enable == _TRUE)
|
||||
if (enable == 1)
|
||||
HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 3, (u8)(value8 | BIT(7)));
|
||||
else
|
||||
HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 3, (u8)(value8 & ~BIT(7)));
|
||||
|
||||
@@ -314,7 +314,7 @@
|
||||
{HALMAC_SW_IO, HALMAC_GPIO15, HALMAC_GPIO_IN_OUT, \
|
||||
0x40, BIT(1) | BIT(0), 0}
|
||||
|
||||
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO0_8822B[] = {
|
||||
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO0_8822B[] = {
|
||||
GPIO0_BT_GPIO0_8822B,
|
||||
GPIO0_BT_ACT_8822B,
|
||||
GPIO0_WL_ACT_8822B,
|
||||
@@ -324,7 +324,7 @@ const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO0_8822B[] = {
|
||||
GPIO0_SW_IO_8822B
|
||||
};
|
||||
|
||||
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO1_8822B[] = {
|
||||
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO1_8822B[] = {
|
||||
GPIO1_BT_GPIO1_8822B,
|
||||
GPIO1_BT_3DD_SYNC_A_8822B,
|
||||
GPIO1_WL_CK_8822B,
|
||||
@@ -335,7 +335,7 @@ const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO1_8822B[] = {
|
||||
GPIO1_SW_IO_8822B
|
||||
};
|
||||
|
||||
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO2_8822B[] = {
|
||||
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO2_8822B[] = {
|
||||
GPIO2_BT_GPIO2_8822B,
|
||||
GPIO2_WL_STATE_8822B,
|
||||
GPIO2_BT_STATE_8822B,
|
||||
@@ -346,7 +346,7 @@ const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO2_8822B[] = {
|
||||
GPIO2_SW_IO_8822B
|
||||
};
|
||||
|
||||
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO3_8822B[] = {
|
||||
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO3_8822B[] = {
|
||||
GPIO3_BT_GPIO3_8822B,
|
||||
GPIO3_WL_PRI_8822B,
|
||||
GPIO3_BT_PRI_8822B,
|
||||
@@ -357,7 +357,7 @@ const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO3_8822B[] = {
|
||||
GPIO3_SW_IO_8822B
|
||||
};
|
||||
|
||||
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO4_8822B[] = {
|
||||
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO4_8822B[] = {
|
||||
GPIO4_BT_SPI_D0_8822B,
|
||||
GPIO4_WL_SPI_D0_8822B,
|
||||
GPIO4_SDIO_INT_8822B,
|
||||
@@ -369,7 +369,7 @@ const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO4_8822B[] = {
|
||||
GPIO4_SW_IO_8822B
|
||||
};
|
||||
|
||||
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO5_8822B[] = {
|
||||
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO5_8822B[] = {
|
||||
GPIO5_BT_SPI_D1_8822B,
|
||||
GPIO5_WL_SPI_D1_8822B,
|
||||
GPIO5_JTAG_TDI_8822B,
|
||||
@@ -380,7 +380,7 @@ const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO5_8822B[] = {
|
||||
GPIO5_SW_IO_8822B
|
||||
};
|
||||
|
||||
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO6_8822B[] = {
|
||||
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO6_8822B[] = {
|
||||
GPIO6_BT_SPI_D2_8822B,
|
||||
GPIO6_WL_SPI_D2_8822B,
|
||||
GPIO6_EEDO_8822B,
|
||||
@@ -394,7 +394,7 @@ const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO6_8822B[] = {
|
||||
GPIO6_SW_IO_8822B
|
||||
};
|
||||
|
||||
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO7_8822B[] = {
|
||||
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO7_8822B[] = {
|
||||
GPIO7_BT_SPI_D3_8822B,
|
||||
GPIO7_WL_SPI_D3_8822B,
|
||||
GPIO7_EEDI_8822B,
|
||||
@@ -407,45 +407,45 @@ const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO7_8822B[] = {
|
||||
GPIO7_SW_IO_8822B
|
||||
};
|
||||
|
||||
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO8_8822B[] = {
|
||||
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO8_8822B[] = {
|
||||
GPIO8_WL_EXT_WOL_8822B,
|
||||
GPIO8_WL_LED_8822B,
|
||||
GPIO8_SW_IO_8822B
|
||||
};
|
||||
|
||||
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO9_8822B[] = {
|
||||
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO9_8822B[] = {
|
||||
GPIO9_DIS_WL_N_8822B,
|
||||
GPIO9_WL_EXT_WOL_8822B,
|
||||
GPIO9_USCTS0_8822B,
|
||||
GPIO9_SW_IO_8822B
|
||||
};
|
||||
|
||||
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO10_8822B[] = {
|
||||
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO10_8822B[] = {
|
||||
GPIO10_SW_IO_8822B
|
||||
};
|
||||
|
||||
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO11_8822B[] = {
|
||||
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO11_8822B[] = {
|
||||
GPIO11_DIS_BT_N_8822B,
|
||||
GPIO11_USOUT0_8822B,
|
||||
GPIO11_SW_IO_8822B
|
||||
};
|
||||
|
||||
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO12_8822B[] = {
|
||||
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO12_8822B[] = {
|
||||
GPIO12_USIN0_8822B,
|
||||
GPIO12_SW_IO_8822B
|
||||
};
|
||||
|
||||
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO13_8822B[] = {
|
||||
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO13_8822B[] = {
|
||||
GPIO13_BT_WAKE_8822B,
|
||||
GPIO13_SW_IO_8822B
|
||||
};
|
||||
|
||||
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO14_8822B[] = {
|
||||
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO14_8822B[] = {
|
||||
GPIO14_UART_WAKE_8822B,
|
||||
GPIO14_SW_IO_8822B
|
||||
};
|
||||
|
||||
const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO15_8822B[] = {
|
||||
static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO15_8822B[] = {
|
||||
GPIO15_EXT_XTAL_8822B,
|
||||
GPIO15_SW_IO_8822B
|
||||
};
|
||||
@@ -498,6 +498,10 @@ pinmux_get_func_8822b(struct halmac_adapter *adapter,
|
||||
case HALMAC_GPIO_FUNC_SDIO_INT:
|
||||
*enable = (cur_func == HALMAC_SDIO_INT) ? 1 : 0;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
|
||||
case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
|
||||
*enable = (cur_func == HALMAC_GPIO13_14_WL_CTRL_EN) ? 1 : 0;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_0:
|
||||
case HALMAC_GPIO_FUNC_SW_IO_1:
|
||||
case HALMAC_GPIO_FUNC_SW_IO_2:
|
||||
@@ -630,9 +634,13 @@ pinmux_free_func_8822b(struct halmac_adapter *adapter,
|
||||
info->sw_io_12 = 0;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_13:
|
||||
case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
|
||||
info->bt_dev_wake = 0;
|
||||
info->sw_io_13 = 0;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_14:
|
||||
case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
|
||||
info->bt_host_wake = 0;
|
||||
info->sw_io_14 = 0;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_15:
|
||||
@@ -656,85 +664,87 @@ get_pinmux_list_8822b(struct halmac_adapter *adapter,
|
||||
{
|
||||
switch (gpio_func) {
|
||||
case HALMAC_GPIO_FUNC_SW_IO_0:
|
||||
*list = PIMUX_LIST_GPIO0_8822B;
|
||||
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO0_8822B);
|
||||
*list = PINMUX_LIST_GPIO0_8822B;
|
||||
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO0_8822B);
|
||||
*gpio_id = HALMAC_GPIO0;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_1:
|
||||
*list = PIMUX_LIST_GPIO1_8822B;
|
||||
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO1_8822B);
|
||||
*list = PINMUX_LIST_GPIO1_8822B;
|
||||
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO1_8822B);
|
||||
*gpio_id = HALMAC_GPIO1;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_2:
|
||||
*list = PIMUX_LIST_GPIO2_8822B;
|
||||
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO2_8822B);
|
||||
*list = PINMUX_LIST_GPIO2_8822B;
|
||||
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO2_8822B);
|
||||
*gpio_id = HALMAC_GPIO2;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_3:
|
||||
*list = PIMUX_LIST_GPIO3_8822B;
|
||||
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO3_8822B);
|
||||
*list = PINMUX_LIST_GPIO3_8822B;
|
||||
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO3_8822B);
|
||||
*gpio_id = HALMAC_GPIO3;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_4:
|
||||
case HALMAC_GPIO_FUNC_SDIO_INT:
|
||||
*list = PIMUX_LIST_GPIO4_8822B;
|
||||
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO4_8822B);
|
||||
*list = PINMUX_LIST_GPIO4_8822B;
|
||||
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO4_8822B);
|
||||
*gpio_id = HALMAC_GPIO4;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_5:
|
||||
*list = PIMUX_LIST_GPIO5_8822B;
|
||||
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO5_8822B);
|
||||
*list = PINMUX_LIST_GPIO5_8822B;
|
||||
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO5_8822B);
|
||||
*gpio_id = HALMAC_GPIO5;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_6:
|
||||
*list = PIMUX_LIST_GPIO6_8822B;
|
||||
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO6_8822B);
|
||||
*list = PINMUX_LIST_GPIO6_8822B;
|
||||
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO6_8822B);
|
||||
*gpio_id = HALMAC_GPIO6;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_7:
|
||||
*list = PIMUX_LIST_GPIO7_8822B;
|
||||
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO7_8822B);
|
||||
*list = PINMUX_LIST_GPIO7_8822B;
|
||||
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO7_8822B);
|
||||
*gpio_id = HALMAC_GPIO7;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_8:
|
||||
case HALMAC_GPIO_FUNC_WL_LED:
|
||||
*list = PIMUX_LIST_GPIO8_8822B;
|
||||
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO8_8822B);
|
||||
*list = PINMUX_LIST_GPIO8_8822B;
|
||||
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO8_8822B);
|
||||
*gpio_id = HALMAC_GPIO8;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_9:
|
||||
*list = PIMUX_LIST_GPIO9_8822B;
|
||||
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO9_8822B);
|
||||
*list = PINMUX_LIST_GPIO9_8822B;
|
||||
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO9_8822B);
|
||||
*gpio_id = HALMAC_GPIO9;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_10:
|
||||
*list = PIMUX_LIST_GPIO10_8822B;
|
||||
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO10_8822B);
|
||||
*list = PINMUX_LIST_GPIO10_8822B;
|
||||
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO10_8822B);
|
||||
*gpio_id = HALMAC_GPIO10;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_11:
|
||||
*list = PIMUX_LIST_GPIO11_8822B;
|
||||
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO11_8822B);
|
||||
*list = PINMUX_LIST_GPIO11_8822B;
|
||||
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO11_8822B);
|
||||
*gpio_id = HALMAC_GPIO11;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_12:
|
||||
*list = PIMUX_LIST_GPIO12_8822B;
|
||||
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO12_8822B);
|
||||
*list = PINMUX_LIST_GPIO12_8822B;
|
||||
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO12_8822B);
|
||||
*gpio_id = HALMAC_GPIO12;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_13:
|
||||
*list = PIMUX_LIST_GPIO13_8822B;
|
||||
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO13_8822B);
|
||||
case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
|
||||
*list = PINMUX_LIST_GPIO13_8822B;
|
||||
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO13_8822B);
|
||||
*gpio_id = HALMAC_GPIO13;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_14:
|
||||
*list = PIMUX_LIST_GPIO14_8822B;
|
||||
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO14_8822B);
|
||||
case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
|
||||
*list = PINMUX_LIST_GPIO14_8822B;
|
||||
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO14_8822B);
|
||||
*gpio_id = HALMAC_GPIO14;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_15:
|
||||
*list = PIMUX_LIST_GPIO15_8822B;
|
||||
*list_size = ARRAY_SIZE(PIMUX_LIST_GPIO15_8822B);
|
||||
*list = PINMUX_LIST_GPIO15_8822B;
|
||||
*list_size = ARRAY_SIZE(PINMUX_LIST_GPIO15_8822B);
|
||||
*gpio_id = HALMAC_GPIO15;
|
||||
break;
|
||||
default:
|
||||
@@ -786,10 +796,14 @@ chk_pinmux_valid_8822b(struct halmac_adapter *adapter,
|
||||
status = HALMAC_RET_PINMUX_USED;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_8:
|
||||
case HALMAC_GPIO_FUNC_WL_LED:
|
||||
if (info->sw_io_8 == 1 || info->wl_led == 1)
|
||||
status = HALMAC_RET_PINMUX_USED;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_WL_LED:
|
||||
if (info->sw_io_8 == 1 || info->wl_led == 1 ||
|
||||
info->bt_dev_wake == 1 || info->bt_host_wake == 1)
|
||||
status = HALMAC_RET_PINMUX_USED;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_9:
|
||||
if (info->sw_io_9 == 1)
|
||||
status = HALMAC_RET_PINMUX_USED;
|
||||
@@ -807,11 +821,21 @@ chk_pinmux_valid_8822b(struct halmac_adapter *adapter,
|
||||
status = HALMAC_RET_PINMUX_USED;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_13:
|
||||
if (info->sw_io_13 == 1)
|
||||
if (info->sw_io_13 == 1 || info->bt_dev_wake == 1)
|
||||
status = HALMAC_RET_PINMUX_USED;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
|
||||
if (info->sw_io_13 == 1 || info->bt_dev_wake == 1 ||
|
||||
info->wl_led == 1)
|
||||
status = HALMAC_RET_PINMUX_USED;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_14:
|
||||
if (info->sw_io_14 == 1)
|
||||
if (info->sw_io_14 == 1 || info->bt_host_wake == 1)
|
||||
status = HALMAC_RET_PINMUX_USED;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
|
||||
if (info->sw_io_14 == 1 || info->bt_host_wake == 1 ||
|
||||
info->wl_led == 1)
|
||||
status = HALMAC_RET_PINMUX_USED;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_15:
|
||||
|
||||
@@ -15,9 +15,16 @@
|
||||
|
||||
#include "halmac_init_8822b.h"
|
||||
#include "halmac_8822b_cfg.h"
|
||||
#if HALMAC_PCIE_SUPPORT
|
||||
#include "halmac_pcie_8822b.h"
|
||||
#endif
|
||||
#if HALMAC_SDIO_SUPPORT
|
||||
#include "halmac_sdio_8822b.h"
|
||||
#include "../halmac_sdio_88xx.h"
|
||||
#endif
|
||||
#if HALMAC_USB_SUPPORT
|
||||
#include "halmac_usb_8822b.h"
|
||||
#endif
|
||||
#include "halmac_gpio_8822b.h"
|
||||
#include "halmac_common_8822b.h"
|
||||
#include "halmac_cfg_wmac_8822b.h"
|
||||
@@ -26,6 +33,8 @@
|
||||
|
||||
#if HALMAC_8822B_SUPPORT
|
||||
|
||||
#define SYS_FUNC_EN 0xDC
|
||||
|
||||
#define RSVD_PG_DRV_NUM 16
|
||||
#define RSVD_PG_H2C_EXTRAINFO_NUM 24
|
||||
#define RSVD_PG_H2C_STATICINFO_NUM 8
|
||||
@@ -33,7 +42,8 @@
|
||||
#define RSVD_PG_CPU_INSTRUCTION_NUM 0
|
||||
#define RSVD_PG_FW_TXBUF_NUM 4
|
||||
#define RSVD_PG_CSIBUF_NUM 0
|
||||
#define RSVD_PG_DLLB_NUM 32
|
||||
#define RSVD_PG_DLLB_NUM (TX_FIFO_SIZE_8822B / 3 >> \
|
||||
TX_PAGE_SIZE_SHIFT_88XX)
|
||||
|
||||
#define MAC_TRX_ENABLE (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \
|
||||
BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \
|
||||
@@ -41,6 +51,29 @@
|
||||
|
||||
#define BLK_DESC_NUM 0x3
|
||||
|
||||
#define WLAN_SLOT_TIME 0x09
|
||||
#define WLAN_PIFS_TIME 0x19
|
||||
#define WLAN_SIFS_CCK_CONT_TX 0xA
|
||||
#define WLAN_SIFS_OFDM_CONT_TX 0xE
|
||||
#define WLAN_SIFS_CCK_TRX 0x10
|
||||
#define WLAN_SIFS_OFDM_TRX 0x10
|
||||
#define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */
|
||||
#define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */
|
||||
#define WLAN_RDG_NAV 0x05
|
||||
#define WLAN_TXOP_NAV 0x1B
|
||||
#define WLAN_CCK_RX_TSF 0x30
|
||||
#define WLAN_OFDM_RX_TSF 0x30
|
||||
#define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
|
||||
#define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
|
||||
#define WLAN_DRV_EARLY_INT 0x04
|
||||
#define WLAN_BCN_DMA_TIME 0x02
|
||||
|
||||
#define WLAN_RX_FILTER0 0x0FFFFFFF
|
||||
#define WLAN_RX_FILTER2 0xFFFF
|
||||
#define WLAN_RCR_CFG 0xE400220E
|
||||
#define WLAN_RXPKT_MAX_SZ 12288
|
||||
#define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9)
|
||||
|
||||
#define WLAN_AMPDU_MAX_TIME 0x70
|
||||
#define WLAN_RTS_LEN_TH 0xFF
|
||||
#define WLAN_RTS_TX_TIME_TH 0x08
|
||||
@@ -53,9 +86,26 @@
|
||||
#define WLAN_BAR_RETRY_LIMIT 0x01
|
||||
#define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
|
||||
|
||||
#define WLAN_TX_FUNC_CFG1 0x30
|
||||
#define WLAN_TX_FUNC_CFG2 0x30
|
||||
#define WLAN_MAC_OPT_NORM_FUNC1 0x98
|
||||
#define WLAN_MAC_OPT_LB_FUNC1 0x80
|
||||
#define WLAN_MAC_OPT_FUNC2 0x30810041
|
||||
|
||||
#define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \
|
||||
(WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
|
||||
(WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
|
||||
(WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
|
||||
|
||||
#define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
|
||||
(WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
|
||||
|
||||
#define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
|
||||
#define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
|
||||
|
||||
#if HALMAC_PLATFORM_WINDOWS
|
||||
/*SDIO RQPN Mapping for Windows, extra queue is not implemented in Driver code*/
|
||||
struct halmac_rqpn HALMAC_RQPN_SDIO_8822B[] = {
|
||||
static struct halmac_rqpn HALMAC_RQPN_SDIO_8822B[] = {
|
||||
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
|
||||
{HALMAC_TRX_MODE_NORMAL,
|
||||
HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
|
||||
@@ -78,7 +128,7 @@ struct halmac_rqpn HALMAC_RQPN_SDIO_8822B[] = {
|
||||
};
|
||||
#else
|
||||
/*SDIO RQPN Mapping*/
|
||||
struct halmac_rqpn HALMAC_RQPN_SDIO_8822B[] = {
|
||||
static struct halmac_rqpn HALMAC_RQPN_SDIO_8822B[] = {
|
||||
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
|
||||
{HALMAC_TRX_MODE_NORMAL,
|
||||
HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
|
||||
@@ -102,7 +152,7 @@ struct halmac_rqpn HALMAC_RQPN_SDIO_8822B[] = {
|
||||
#endif
|
||||
|
||||
/*PCIE RQPN Mapping*/
|
||||
struct halmac_rqpn HALMAC_RQPN_PCIE_8822B[] = {
|
||||
static struct halmac_rqpn HALMAC_RQPN_PCIE_8822B[] = {
|
||||
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
|
||||
{HALMAC_TRX_MODE_NORMAL,
|
||||
HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
|
||||
@@ -125,7 +175,7 @@ struct halmac_rqpn HALMAC_RQPN_PCIE_8822B[] = {
|
||||
};
|
||||
|
||||
/*USB 2 Bulkout RQPN Mapping*/
|
||||
struct halmac_rqpn HALMAC_RQPN_2BULKOUT_8822B[] = {
|
||||
static struct halmac_rqpn HALMAC_RQPN_2BULKOUT_8822B[] = {
|
||||
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
|
||||
{HALMAC_TRX_MODE_NORMAL,
|
||||
HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ,
|
||||
@@ -148,7 +198,7 @@ struct halmac_rqpn HALMAC_RQPN_2BULKOUT_8822B[] = {
|
||||
};
|
||||
|
||||
/*USB 3 Bulkout RQPN Mapping*/
|
||||
struct halmac_rqpn HALMAC_RQPN_3BULKOUT_8822B[] = {
|
||||
static struct halmac_rqpn HALMAC_RQPN_3BULKOUT_8822B[] = {
|
||||
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
|
||||
{HALMAC_TRX_MODE_NORMAL,
|
||||
HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
|
||||
@@ -171,7 +221,7 @@ struct halmac_rqpn HALMAC_RQPN_3BULKOUT_8822B[] = {
|
||||
};
|
||||
|
||||
/*USB 4 Bulkout RQPN Mapping*/
|
||||
struct halmac_rqpn HALMAC_RQPN_4BULKOUT_8822B[] = {
|
||||
static struct halmac_rqpn HALMAC_RQPN_4BULKOUT_8822B[] = {
|
||||
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
|
||||
{HALMAC_TRX_MODE_NORMAL,
|
||||
HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
|
||||
@@ -195,70 +245,70 @@ struct halmac_rqpn HALMAC_RQPN_4BULKOUT_8822B[] = {
|
||||
|
||||
#if HALMAC_PLATFORM_WINDOWS
|
||||
/*SDIO Page Number*/
|
||||
struct halmac_pg_num HALMAC_PG_NUM_SDIO_8822B[] = {
|
||||
static struct halmac_pg_num HALMAC_PG_NUM_SDIO_8822B[] = {
|
||||
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
|
||||
{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1},
|
||||
{HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 0, 1},
|
||||
{HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1},
|
||||
{HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1},
|
||||
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 640},
|
||||
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 640},
|
||||
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 1},
|
||||
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 1},
|
||||
};
|
||||
#else
|
||||
/*SDIO Page Number*/
|
||||
struct halmac_pg_num HALMAC_PG_NUM_SDIO_8822B[] = {
|
||||
static struct halmac_pg_num HALMAC_PG_NUM_SDIO_8822B[] = {
|
||||
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
|
||||
{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
|
||||
{HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 32, 1},
|
||||
{HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
|
||||
{HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
|
||||
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
|
||||
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
|
||||
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 1},
|
||||
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 1},
|
||||
};
|
||||
#endif
|
||||
|
||||
/*PCIE Page Number*/
|
||||
struct halmac_pg_num HALMAC_PG_NUM_PCIE_8822B[] = {
|
||||
static struct halmac_pg_num HALMAC_PG_NUM_PCIE_8822B[] = {
|
||||
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
|
||||
{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
|
||||
{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1},
|
||||
{HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
|
||||
{HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
|
||||
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
|
||||
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
|
||||
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 1},
|
||||
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 1},
|
||||
};
|
||||
|
||||
/*USB 2 Bulkout Page Number*/
|
||||
struct halmac_pg_num HALMAC_PG_NUM_2BULKOUT_8822B[] = {
|
||||
static struct halmac_pg_num HALMAC_PG_NUM_2BULKOUT_8822B[] = {
|
||||
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
|
||||
{HALMAC_TRX_MODE_NORMAL, 64, 64, 0, 0, 1},
|
||||
{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 0, 0, 1},
|
||||
{HALMAC_TRX_MODE_WMM, 64, 64, 0, 0, 1},
|
||||
{HALMAC_TRX_MODE_P2P, 64, 64, 0, 0, 1},
|
||||
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 0, 0, 1024},
|
||||
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 0, 0, 1024},
|
||||
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 0, 0, 1},
|
||||
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 0, 0, 1},
|
||||
};
|
||||
|
||||
/*USB 3 Bulkout Page Number*/
|
||||
struct halmac_pg_num HALMAC_PG_NUM_3BULKOUT_8822B[] = {
|
||||
static struct halmac_pg_num HALMAC_PG_NUM_3BULKOUT_8822B[] = {
|
||||
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
|
||||
{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1},
|
||||
{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 0, 1},
|
||||
{HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1},
|
||||
{HALMAC_TRX_MODE_WMM, 256, 256, 256, 0, 1},
|
||||
{HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1},
|
||||
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 1024},
|
||||
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 1024},
|
||||
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 1},
|
||||
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 1},
|
||||
};
|
||||
|
||||
/*USB 4 Bulkout Page Number*/
|
||||
struct halmac_pg_num HALMAC_PG_NUM_4BULKOUT_8822B[] = {
|
||||
static struct halmac_pg_num HALMAC_PG_NUM_4BULKOUT_8822B[] = {
|
||||
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
|
||||
{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
|
||||
{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1},
|
||||
{HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
|
||||
{HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
|
||||
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
|
||||
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
|
||||
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 1},
|
||||
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 1},
|
||||
};
|
||||
|
||||
static enum halmac_ret_status
|
||||
@@ -281,6 +331,7 @@ mount_api_8822b(struct halmac_adapter *adapter)
|
||||
adapter->hw_cfg_info.efuse_size = EFUSE_SIZE_8822B;
|
||||
adapter->hw_cfg_info.eeprom_size = EEPROM_SIZE_8822B;
|
||||
adapter->hw_cfg_info.bt_efuse_size = BT_EFUSE_SIZE_8822B;
|
||||
adapter->hw_cfg_info.prtct_efuse_size = PRTCT_EFUSE_SIZE_8822B;
|
||||
adapter->hw_cfg_info.cam_entry_num = SEC_CAM_NUM_8822B;
|
||||
adapter->hw_cfg_info.tx_fifo_size = TX_FIFO_SIZE_8822B;
|
||||
adapter->hw_cfg_info.rx_fifo_size = RX_FIFO_SIZE_8822B;
|
||||
@@ -290,6 +341,7 @@ mount_api_8822b(struct halmac_adapter *adapter)
|
||||
adapter->txff_alloc.rsvd_drv_pg_num = RSVD_PG_DRV_NUM;
|
||||
|
||||
api->halmac_init_trx_cfg = init_trx_cfg_8822b;
|
||||
api->halmac_init_system_cfg = init_system_cfg_8822b;
|
||||
api->halmac_init_protocol_cfg = init_protocol_cfg_8822b;
|
||||
api->halmac_init_h2c = init_h2c_8822b;
|
||||
api->halmac_pinmux_get_func = pinmux_get_func_8822b;
|
||||
@@ -300,8 +352,13 @@ mount_api_8822b(struct halmac_adapter *adapter)
|
||||
api->halmac_cfg_drv_info = cfg_drv_info_8822b;
|
||||
api->halmac_fill_txdesc_checksum = fill_txdesc_check_sum_8822b;
|
||||
api->halmac_init_low_pwr = init_low_pwr_8822b;
|
||||
api->halmac_pre_init_system_cfg = pre_init_system_cfg_8822b;
|
||||
|
||||
api->halmac_init_wmac_cfg = init_wmac_cfg_8822b;
|
||||
api->halmac_init_edca_cfg = init_edca_cfg_8822b;
|
||||
|
||||
if (adapter->intf == HALMAC_INTERFACE_SDIO) {
|
||||
#if HALMAC_SDIO_SUPPORT
|
||||
api->halmac_mac_power_switch = mac_pwr_switch_sdio_8822b;
|
||||
api->halmac_phy_cfg = phy_cfg_sdio_8822b;
|
||||
api->halmac_pcie_switch = pcie_switch_sdio_8822b;
|
||||
@@ -322,16 +379,22 @@ mount_api_8822b(struct halmac_adapter *adapter)
|
||||
if (!adapter->sdio_fs.macid_map)
|
||||
PLTFM_MSG_ERR("[ERR]allocate macid_map!!\n");
|
||||
}
|
||||
#endif
|
||||
} else if (adapter->intf == HALMAC_INTERFACE_USB) {
|
||||
#if HALMAC_USB_SUPPORT
|
||||
api->halmac_mac_power_switch = mac_pwr_switch_usb_8822b;
|
||||
api->halmac_phy_cfg = phy_cfg_usb_8822b;
|
||||
api->halmac_pcie_switch = pcie_switch_usb_8822b;
|
||||
api->halmac_interface_integration_tuning = intf_tun_usb_8822b;
|
||||
#endif
|
||||
} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
|
||||
#if HALMAC_PCIE_SUPPORT
|
||||
api->halmac_mac_power_switch = mac_pwr_switch_pcie_8822b;
|
||||
api->halmac_phy_cfg = phy_cfg_pcie_8822b;
|
||||
api->halmac_pcie_switch = pcie_switch_8822b;
|
||||
api->halmac_interface_integration_tuning = intf_tun_pcie_8822b;
|
||||
api->halmac_cfgspc_set_pcie = cfgspc_set_pcie_8822b;
|
||||
#endif
|
||||
} else {
|
||||
PLTFM_MSG_ERR("[ERR]Undefined IC\n");
|
||||
return HALMAC_RET_CHIP_NOT_SUPPORT;
|
||||
@@ -625,6 +688,40 @@ set_trx_fifo_info_8822b(struct halmac_adapter *adapter,
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* init_system_cfg_8822b() - init system config
|
||||
* @adapter : the adapter of halmac
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
init_system_cfg_8822b(struct halmac_adapter *adapter)
|
||||
{
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
u32 tmp = 0;
|
||||
u32 value32;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
value32 = HALMAC_REG_R32(REG_CPU_DMEM_CON) | BIT_WL_PLATFORM_RST;
|
||||
HALMAC_REG_W32(REG_CPU_DMEM_CON, value32);
|
||||
|
||||
HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, SYS_FUNC_EN);
|
||||
|
||||
/*disable boot-from-flash for driver's DL FW*/
|
||||
tmp = HALMAC_REG_R32(REG_MCUFW_CTRL);
|
||||
if (tmp & BIT_BOOT_FSPI_EN) {
|
||||
HALMAC_REG_W32(REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN));
|
||||
value32 = HALMAC_REG_R32(REG_GPIO_MUXCFG) & (~BIT_FSPI_EN);
|
||||
HALMAC_REG_W32(REG_GPIO_MUXCFG, value32);
|
||||
}
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* init_protocol_cfg_8822b() - config protocol register
|
||||
* @adapter : the adapter of halmac
|
||||
@@ -643,7 +740,7 @@ init_protocol_cfg_8822b(struct halmac_adapter *adapter)
|
||||
HALMAC_REG_W8_CLR(REG_SW_AMPDU_BURST_MODE_CTRL, BIT(6));
|
||||
|
||||
HALMAC_REG_W8(REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
|
||||
HALMAC_REG_W8(REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
|
||||
HALMAC_REG_W8_SET(REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
|
||||
|
||||
value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
|
||||
(WLAN_MAX_AGG_PKT_LIMIT << 16) |
|
||||
@@ -721,4 +818,158 @@ init_h2c_8822b(struct halmac_adapter *adapter)
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* init_edca_cfg_8822b() - init EDCA config
|
||||
* @adapter : the adapter of halmac
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
init_edca_cfg_8822b(struct halmac_adapter *adapter)
|
||||
{
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
/* Init SYNC_CLI_SEL : reg 0x5B4[6:4] = 0 */
|
||||
HALMAC_REG_W8_CLR(REG_TIMER0_SRC_SEL, BIT(4) | BIT(5) | BIT(6));
|
||||
|
||||
/* Clear TX pause */
|
||||
HALMAC_REG_W16(REG_TXPAUSE, 0x0000);
|
||||
|
||||
HALMAC_REG_W8(REG_SLOT, WLAN_SLOT_TIME);
|
||||
HALMAC_REG_W8(REG_PIFS, WLAN_PIFS_TIME);
|
||||
HALMAC_REG_W32(REG_SIFS, WLAN_SIFS_CFG);
|
||||
|
||||
HALMAC_REG_W16(REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
|
||||
HALMAC_REG_W16(REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
|
||||
|
||||
HALMAC_REG_W32(REG_RD_NAV_NXT, WLAN_NAV_CFG);
|
||||
HALMAC_REG_W16(REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
|
||||
|
||||
/* Set beacon cotnrol - enable TSF and other related functions */
|
||||
HALMAC_REG_W8(REG_BCN_CTRL, (u8)(HALMAC_REG_R8(REG_BCN_CTRL) |
|
||||
BIT_EN_BCN_FUNCTION));
|
||||
|
||||
/* Set send beacon related registers */
|
||||
HALMAC_REG_W32(REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
|
||||
HALMAC_REG_W8(REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
|
||||
HALMAC_REG_W8(REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
|
||||
|
||||
HALMAC_REG_W8_CLR(REG_TX_PTCL_CTRL + 1, BIT(4));
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* init_wmac_cfg_8822b() - init wmac config
|
||||
* @adapter : the adapter of halmac
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
init_wmac_cfg_8822b(struct halmac_adapter *adapter)
|
||||
{
|
||||
u8 value8;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
HALMAC_REG_W32(REG_RXFLTMAP0, WLAN_RX_FILTER0);
|
||||
HALMAC_REG_W16(REG_RXFLTMAP2, WLAN_RX_FILTER2);
|
||||
|
||||
HALMAC_REG_W32(REG_RCR, WLAN_RCR_CFG);
|
||||
|
||||
HALMAC_REG_W8(REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
|
||||
|
||||
HALMAC_REG_W8(REG_TCR + 2, WLAN_TX_FUNC_CFG2);
|
||||
HALMAC_REG_W8(REG_TCR + 1, WLAN_TX_FUNC_CFG1);
|
||||
|
||||
HALMAC_REG_W32(REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
|
||||
|
||||
if (adapter->hw_cfg_info.trx_mode == HALMAC_TRNSFER_NORMAL)
|
||||
value8 = WLAN_MAC_OPT_NORM_FUNC1;
|
||||
else
|
||||
value8 = WLAN_MAC_OPT_LB_FUNC1;
|
||||
|
||||
HALMAC_REG_W8(REG_WMAC_OPTION_FUNCTION + 4, value8);
|
||||
|
||||
status = api->halmac_init_low_pwr(adapter);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* pre_init_system_cfg_8822b() - pre-init system config
|
||||
* @adapter : the adapter of halmac
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
pre_init_system_cfg_8822b(struct halmac_adapter *adapter)
|
||||
{
|
||||
u32 value32;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
u8 enable_bb;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
HALMAC_REG_W8(REG_RSV_CTRL, 0);
|
||||
|
||||
if (adapter->intf == HALMAC_INTERFACE_SDIO) {
|
||||
#if HALMAC_SDIO_SUPPORT
|
||||
if (leave_sdio_suspend_88xx(adapter) != HALMAC_RET_SUCCESS)
|
||||
return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
|
||||
#endif
|
||||
} else if (adapter->intf == HALMAC_INTERFACE_USB) {
|
||||
#if HALMAC_USB_SUPPORT
|
||||
if (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20)
|
||||
HALMAC_REG_W8(0xFE5B, HALMAC_REG_R8(0xFE5B) | BIT(4));
|
||||
#endif
|
||||
} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
|
||||
#if HALMAC_PCIE_SUPPORT
|
||||
/* For PCIE power on fail issue */
|
||||
HALMAC_REG_W8(REG_HCI_OPT_CTRL + 1,
|
||||
HALMAC_REG_R8(REG_HCI_OPT_CTRL + 1) | BIT(0));
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Config PIN Mux */
|
||||
value32 = HALMAC_REG_R32(REG_PAD_CTRL1);
|
||||
value32 = value32 & (~(BIT(28) | BIT(29)));
|
||||
value32 = value32 | BIT(28) | BIT(29);
|
||||
HALMAC_REG_W32(REG_PAD_CTRL1, value32);
|
||||
|
||||
value32 = HALMAC_REG_R32(REG_LED_CFG);
|
||||
value32 = value32 & (~(BIT(25) | BIT(26)));
|
||||
HALMAC_REG_W32(REG_LED_CFG, value32);
|
||||
|
||||
value32 = HALMAC_REG_R32(REG_GPIO_MUXCFG);
|
||||
value32 = value32 & (~(BIT(2)));
|
||||
value32 = value32 | BIT(2);
|
||||
HALMAC_REG_W32(REG_GPIO_MUXCFG, value32);
|
||||
|
||||
enable_bb = 0;
|
||||
set_hw_value_88xx(adapter, HALMAC_HW_EN_BB_RF, &enable_bb);
|
||||
|
||||
if (HALMAC_REG_R8(REG_SYS_CFG1 + 2) & BIT(4)) {
|
||||
PLTFM_MSG_ERR("[ERR]test mode!!\n");
|
||||
return HALMAC_RET_WLAN_MODE_FAIL;
|
||||
}
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
#endif /* HALMAC_8822B_SUPPORT */
|
||||
|
||||
@@ -26,12 +26,24 @@ mount_api_8822b(struct halmac_adapter *adapter);
|
||||
enum halmac_ret_status
|
||||
init_trx_cfg_8822b(struct halmac_adapter *adapter, enum halmac_trx_mode mode);
|
||||
|
||||
enum halmac_ret_status
|
||||
init_system_cfg_8822b(struct halmac_adapter *adapter);
|
||||
|
||||
enum halmac_ret_status
|
||||
init_protocol_cfg_8822b(struct halmac_adapter *adapter);
|
||||
|
||||
enum halmac_ret_status
|
||||
init_h2c_8822b(struct halmac_adapter *adapter);
|
||||
|
||||
enum halmac_ret_status
|
||||
init_edca_cfg_8822b(struct halmac_adapter *adapter);
|
||||
|
||||
enum halmac_ret_status
|
||||
init_wmac_cfg_8822b(struct halmac_adapter *adapter);
|
||||
|
||||
enum halmac_ret_status
|
||||
pre_init_system_cfg_8822b(struct halmac_adapter *adapter);
|
||||
|
||||
#endif /* HALMAC_8822B_SUPPORT */
|
||||
|
||||
#endif/* _HALMAC_INIT_8822B_H_ */
|
||||
|
||||
@@ -1,214 +0,0 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "halmac_pcie_8822b.h"
|
||||
#include "halmac_pwr_seq_8822b.h"
|
||||
#include "../halmac_init_88xx.h"
|
||||
#include "../halmac_common_88xx.h"
|
||||
#include "../halmac_pcie_88xx.h"
|
||||
#include "../halmac_88xx_cfg.h"
|
||||
|
||||
#if HALMAC_8822B_SUPPORT
|
||||
|
||||
/**
|
||||
* mac_pwr_switch_pcie_8822b() - switch mac power
|
||||
* @adapter : the adapter of halmac
|
||||
* @pwr : power state
|
||||
* Author : KaiYuan Chang
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
mac_pwr_switch_pcie_8822b(struct halmac_adapter *adapter,
|
||||
enum halmac_mac_power pwr)
|
||||
{
|
||||
u8 value8;
|
||||
u8 rpwm;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
enum halmac_ret_status status;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
PLTFM_MSG_TRACE("[TRACE]pwr = %x\n", pwr);
|
||||
PLTFM_MSG_TRACE("[TRACE]8822B pwr seq ver = %s\n",
|
||||
HALMAC_8822B_PWR_SEQ_VER);
|
||||
|
||||
adapter->rpwm = HALMAC_REG_R8(REG_PCIE_HRPWM1_V1);
|
||||
|
||||
/* Check FW still exist or not */
|
||||
if (HALMAC_REG_R16(REG_MCUFW_CTRL) == 0xC078) {
|
||||
/* Leave 32K */
|
||||
rpwm = (u8)((adapter->rpwm ^ BIT(7)) & 0x80);
|
||||
HALMAC_REG_W8(REG_PCIE_HRPWM1_V1, rpwm);
|
||||
}
|
||||
|
||||
value8 = HALMAC_REG_R8(REG_CR);
|
||||
if (value8 == 0xEA)
|
||||
adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
|
||||
else
|
||||
adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
|
||||
|
||||
/* Check if power switch is needed */
|
||||
if (pwr == HALMAC_MAC_POWER_ON &&
|
||||
adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_ON) {
|
||||
PLTFM_MSG_WARN("[WARN]power state unchange!!\n");
|
||||
return HALMAC_RET_PWR_UNCHANGE;
|
||||
}
|
||||
|
||||
if (pwr == HALMAC_MAC_POWER_OFF) {
|
||||
status = trxdma_check_idle_88xx(adapter);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
if (pwr_seq_parser_88xx(adapter, card_dis_flow_8822b) !=
|
||||
HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]Handle power off cmd error\n");
|
||||
return HALMAC_RET_POWER_OFF_FAIL;
|
||||
}
|
||||
|
||||
adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
|
||||
adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
|
||||
init_adapter_dynamic_param_88xx(adapter);
|
||||
} else {
|
||||
if (pwr_seq_parser_88xx(adapter, card_en_flow_8822b) !=
|
||||
HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]Handle power on cmd error\n");
|
||||
return HALMAC_RET_POWER_ON_FAIL;
|
||||
}
|
||||
|
||||
adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
|
||||
}
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* halmac_pcie_switch_8822b() - pcie gen1/gen2 switch
|
||||
* @adapter : the adapter of halmac
|
||||
* @cfg : gen1/gen2 selection
|
||||
* Author : KaiYuan Chang
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
pcie_switch_8822b(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg)
|
||||
{
|
||||
u8 value8;
|
||||
u32 value32;
|
||||
u8 speed = 0;
|
||||
u32 cnt = 0;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
if (cfg == HALMAC_PCIE_GEN1) {
|
||||
value8 = dbi_r8_88xx(adapter, LINK_CTRL2_REG_OFFSET) & 0xF0;
|
||||
dbi_w8_88xx(adapter, LINK_CTRL2_REG_OFFSET, value8 | BIT(0));
|
||||
|
||||
value32 = dbi_r32_88xx(adapter, GEN2_CTRL_OFFSET);
|
||||
dbi_w32_88xx(adapter, GEN2_CTRL_OFFSET, value32 | BIT(17));
|
||||
|
||||
speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET) & 0x0F;
|
||||
cnt = 2000;
|
||||
|
||||
while ((speed != PCIE_GEN1_SPEED) && (cnt != 0)) {
|
||||
PLTFM_DELAY_US(50);
|
||||
speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET);
|
||||
speed &= 0x0F;
|
||||
cnt--;
|
||||
}
|
||||
|
||||
if (speed != PCIE_GEN1_SPEED) {
|
||||
PLTFM_MSG_ERR("[ERR]Speed change to GEN1 fail !\n");
|
||||
return HALMAC_RET_FAIL;
|
||||
}
|
||||
|
||||
} else if (cfg == HALMAC_PCIE_GEN2) {
|
||||
value8 = dbi_r8_88xx(adapter, LINK_CTRL2_REG_OFFSET) & 0xF0;
|
||||
dbi_w8_88xx(adapter, LINK_CTRL2_REG_OFFSET, value8 | BIT(1));
|
||||
|
||||
value32 = dbi_r32_88xx(adapter, GEN2_CTRL_OFFSET);
|
||||
dbi_w32_88xx(adapter, GEN2_CTRL_OFFSET, value32 | BIT(17));
|
||||
|
||||
speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET) & 0x0F;
|
||||
cnt = 2000;
|
||||
|
||||
while ((speed != PCIE_GEN2_SPEED) && (cnt != 0)) {
|
||||
PLTFM_DELAY_US(50);
|
||||
speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET);
|
||||
speed &= 0x0F;
|
||||
cnt--;
|
||||
}
|
||||
|
||||
if (speed != PCIE_GEN2_SPEED) {
|
||||
PLTFM_MSG_ERR("[ERR]Speed change to GEN1 fail !\n");
|
||||
return HALMAC_RET_FAIL;
|
||||
}
|
||||
|
||||
} else {
|
||||
PLTFM_MSG_ERR("[ERR]Error Speed !\n");
|
||||
return HALMAC_RET_FAIL;
|
||||
}
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* phy_cfg_pcie_8822b() - phy config
|
||||
* @adapter : the adapter of halmac
|
||||
* Author : KaiYuan Chang
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
phy_cfg_pcie_8822b(struct halmac_adapter *adapter,
|
||||
enum halmac_intf_phy_platform pltfm)
|
||||
{
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
status = parse_intf_phy_88xx(adapter, pcie_gen1_phy_param_8822b, pltfm,
|
||||
HAL_INTF_PHY_PCIE_GEN1);
|
||||
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
|
||||
status = parse_intf_phy_88xx(adapter, pcie_gen2_phy_param_8822b, pltfm,
|
||||
HAL_INTF_PHY_PCIE_GEN2);
|
||||
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* intf_tun_pcie_8822b() - pcie interface fine tuning
|
||||
* @adapter : the adapter of halmac
|
||||
* Author : Rick Liu
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
intf_tun_pcie_8822b(struct halmac_adapter *adapter)
|
||||
{
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
#endif /* HALMAC_8822B_SUPPORT*/
|
||||
@@ -1,42 +0,0 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _HALMAC_API_8822B_PCIE_H_
|
||||
#define _HALMAC_API_8822B_PCIE_H_
|
||||
|
||||
#include "../../halmac_api.h"
|
||||
|
||||
#if HALMAC_8822B_SUPPORT
|
||||
|
||||
extern struct halmac_intf_phy_para pcie_gen1_phy_param_8822b[];
|
||||
extern struct halmac_intf_phy_para pcie_gen2_phy_param_8822b[];
|
||||
|
||||
enum halmac_ret_status
|
||||
mac_pwr_switch_pcie_8822b(struct halmac_adapter *adapter,
|
||||
enum halmac_mac_power pwr);
|
||||
|
||||
enum halmac_ret_status
|
||||
pcie_switch_8822b(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg);
|
||||
|
||||
enum halmac_ret_status
|
||||
phy_cfg_pcie_8822b(struct halmac_adapter *adapter,
|
||||
enum halmac_intf_phy_platform pltfm);
|
||||
|
||||
enum halmac_ret_status
|
||||
intf_tun_pcie_8822b(struct halmac_adapter *adapter);
|
||||
|
||||
#endif /* HALMAC_8822B_SUPPORT*/
|
||||
|
||||
#endif/* _HALMAC_API_8822B_PCIE_H_ */
|
||||
@@ -14,6 +14,12 @@
|
||||
******************************************************************************/
|
||||
|
||||
#include "../../halmac_type.h"
|
||||
#if HALMAC_USB_SUPPORT
|
||||
#include "halmac_usb_8822b.h"
|
||||
#endif
|
||||
#if HALMAC_PCIE_SUPPORT
|
||||
#include "halmac_pcie_8822b.h"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* ============ip sel item list============
|
||||
@@ -39,7 +45,7 @@ struct halmac_intf_phy_para usb2_phy_param_8822b[] = {
|
||||
HALMAC_INTF_PHY_PLATFORM_ALL},
|
||||
};
|
||||
|
||||
struct halmac_intf_phy_para usb3_phy_8822b[] = {
|
||||
struct halmac_intf_phy_para usb3_phy_param_8822b[] = {
|
||||
/* {offset, value, ip sel, cut mask, platform mask} */
|
||||
{0x0001, 0xA841,
|
||||
HALMAC_IP_INTF_PHY,
|
||||
@@ -147,4 +153,4 @@ struct halmac_intf_phy_para pcie_gen2_phy_param_8822b[] = {
|
||||
HALMAC_INTF_PHY_PLATFORM_ALL},
|
||||
};
|
||||
|
||||
#endif /* HALMAC_8822B_SUPPORT*/
|
||||
#endif /* HALMAC_8822B_SUPPORT */
|
||||
|
||||
@@ -17,7 +17,7 @@
|
||||
|
||||
#if HALMAC_8822B_SUPPORT
|
||||
|
||||
struct halmac_wlan_pwr_cfg TRANS_CARDDIS_TO_CARDEMU_8822B[] = {
|
||||
static struct halmac_wlan_pwr_cfg TRANS_CARDDIS_TO_CARDEMU_8822B[] = {
|
||||
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
|
||||
{0x0086,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
@@ -56,7 +56,7 @@ struct halmac_wlan_pwr_cfg TRANS_CARDDIS_TO_CARDEMU_8822B[] = {
|
||||
HALMAC_PWR_CMD_END, 0, 0},
|
||||
};
|
||||
|
||||
struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_ACT_8822B[] = {
|
||||
static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_ACT_8822B[] = {
|
||||
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
|
||||
{0x0012,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
@@ -190,7 +190,7 @@ struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_ACT_8822B[] = {
|
||||
HALMAC_PWR_CMD_END, 0, 0},
|
||||
};
|
||||
|
||||
struct halmac_wlan_pwr_cfg TRANS_ACT_TO_CARDEMU_8822B[] = {
|
||||
static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_CARDEMU_8822B[] = {
|
||||
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
|
||||
{0x0003,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
@@ -264,7 +264,7 @@ struct halmac_wlan_pwr_cfg TRANS_ACT_TO_CARDEMU_8822B[] = {
|
||||
HALMAC_PWR_CMD_END, 0, 0},
|
||||
};
|
||||
|
||||
struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_CARDDIS_8822B[] = {
|
||||
static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_CARDDIS_8822B[] = {
|
||||
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
|
||||
{0x0005,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
@@ -281,11 +281,6 @@ struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_CARDDIS_8822B[] = {
|
||||
HALMAC_PWR_INTF_ALL_MSK,
|
||||
HALMAC_PWR_ADDR_MAC,
|
||||
HALMAC_PWR_CMD_WRITE, BIT(5), 0},
|
||||
{0x0005,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
|
||||
HALMAC_PWR_ADDR_MAC,
|
||||
HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
|
||||
{0x0005,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_PCI_MSK,
|
||||
@@ -340,7 +335,12 @@ struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_CARDDIS_8822B[] = {
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_ALL_MSK,
|
||||
HALMAC_PWR_ADDR_MAC,
|
||||
HALMAC_PWR_CMD_WRITE, BIT(7), 0},
|
||||
HALMAC_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
|
||||
{0x0005,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
|
||||
HALMAC_PWR_ADDR_MAC,
|
||||
HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
|
||||
{0x0086,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_SDIO_MSK,
|
||||
@@ -399,7 +399,7 @@ struct halmac_wlan_pwr_cfg *card_dis_flow_8822b[] = {
|
||||
|
||||
#if HALMAC_PLATFORM_TESTPROGRAM
|
||||
|
||||
struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_SUS_8822B[] = {
|
||||
static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_SUS_8822B[] = {
|
||||
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
|
||||
{0x0005,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
@@ -438,8 +438,18 @@ struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_SUS_8822B[] = {
|
||||
HALMAC_PWR_CMD_END, 0, 0},
|
||||
};
|
||||
|
||||
struct halmac_wlan_pwr_cfg TRANS_SUS_TO_CARDEMU_8822B[] = {
|
||||
static struct halmac_wlan_pwr_cfg TRANS_SUS_TO_CARDEMU_8822B[] = {
|
||||
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
|
||||
{0xFF0A,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_USB_MSK,
|
||||
HALMAC_PWR_ADDR_MAC,
|
||||
HALMAC_PWR_CMD_WRITE, 0xFF, 0},
|
||||
{0xFF0B,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_USB_MSK,
|
||||
HALMAC_PWR_ADDR_MAC,
|
||||
HALMAC_PWR_CMD_WRITE, 0xFF, 0},
|
||||
{0x0005,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_ALL_MSK,
|
||||
@@ -467,7 +477,7 @@ struct halmac_wlan_pwr_cfg TRANS_SUS_TO_CARDEMU_8822B[] = {
|
||||
HALMAC_PWR_CMD_END, 0, 0},
|
||||
};
|
||||
|
||||
struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_PDN_8822B[] = {
|
||||
static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_PDN_8822B[] = {
|
||||
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
|
||||
{0x0007,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
@@ -491,7 +501,7 @@ struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_PDN_8822B[] = {
|
||||
HALMAC_PWR_CMD_END, 0, 0},
|
||||
};
|
||||
|
||||
struct halmac_wlan_pwr_cfg TRANS_PDN_TO_CARDEMU_8822B[] = {
|
||||
static struct halmac_wlan_pwr_cfg TRANS_PDN_TO_CARDEMU_8822B[] = {
|
||||
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
|
||||
{0x0005,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
@@ -505,7 +515,7 @@ struct halmac_wlan_pwr_cfg TRANS_PDN_TO_CARDEMU_8822B[] = {
|
||||
HALMAC_PWR_CMD_END, 0, 0},
|
||||
};
|
||||
|
||||
struct halmac_wlan_pwr_cfg TRANS_ACT_TO_LPS_8822B[] = {
|
||||
static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_LPS_8822B[] = {
|
||||
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
|
||||
{0x0101,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
@@ -534,14 +544,34 @@ struct halmac_wlan_pwr_cfg TRANS_ACT_TO_LPS_8822B[] = {
|
||||
HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
|
||||
{0x0093,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_ALL_MSK,
|
||||
HALMAC_PWR_INTF_PCI_MSK,
|
||||
HALMAC_PWR_ADDR_MAC,
|
||||
HALMAC_PWR_CMD_WRITE, 0xFF, 0x42},
|
||||
HALMAC_PWR_CMD_WRITE, 0xFF, 0xDE},
|
||||
{0x0092,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_ALL_MSK,
|
||||
HALMAC_PWR_INTF_PCI_MSK,
|
||||
HALMAC_PWR_ADDR_MAC,
|
||||
HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
|
||||
HALMAC_PWR_CMD_WRITE, 0xFF, 0x60},
|
||||
{0x0093,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_USB_MSK,
|
||||
HALMAC_PWR_ADDR_MAC,
|
||||
HALMAC_PWR_CMD_WRITE, 0xFF, 0x9B},
|
||||
{0x0092,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_USB_MSK,
|
||||
HALMAC_PWR_ADDR_MAC,
|
||||
HALMAC_PWR_CMD_WRITE, 0xFF, 0x60},
|
||||
{0x0093,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_SDIO_MSK,
|
||||
HALMAC_PWR_ADDR_MAC,
|
||||
HALMAC_PWR_CMD_WRITE, 0xFF, 0xA},
|
||||
{0x0092,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_SDIO_MSK,
|
||||
HALMAC_PWR_ADDR_MAC,
|
||||
HALMAC_PWR_CMD_WRITE, 0xFF, 0x60},
|
||||
{0x0090,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_ALL_MSK,
|
||||
@@ -629,7 +659,7 @@ struct halmac_wlan_pwr_cfg TRANS_ACT_TO_LPS_8822B[] = {
|
||||
HALMAC_PWR_CMD_END, 0, 0},
|
||||
};
|
||||
|
||||
struct halmac_wlan_pwr_cfg TRANS_ACT_TO_DEEP_LPS_8822B[] = {
|
||||
static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_DEEP_LPS_8822B[] = {
|
||||
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
|
||||
{0x0101,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
@@ -658,14 +688,34 @@ struct halmac_wlan_pwr_cfg TRANS_ACT_TO_DEEP_LPS_8822B[] = {
|
||||
HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
|
||||
{0x0093,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_ALL_MSK,
|
||||
HALMAC_PWR_INTF_PCI_MSK,
|
||||
HALMAC_PWR_ADDR_MAC,
|
||||
HALMAC_PWR_CMD_WRITE, 0xFF, 0x40},
|
||||
HALMAC_PWR_CMD_WRITE, 0xFF, 0xDE},
|
||||
{0x0092,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_ALL_MSK,
|
||||
HALMAC_PWR_INTF_PCI_MSK,
|
||||
HALMAC_PWR_ADDR_MAC,
|
||||
HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
|
||||
HALMAC_PWR_CMD_WRITE, 0xFF, 0x60},
|
||||
{0x0093,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_USB_MSK,
|
||||
HALMAC_PWR_ADDR_MAC,
|
||||
HALMAC_PWR_CMD_WRITE, 0xFF, 0x9B},
|
||||
{0x0092,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_USB_MSK,
|
||||
HALMAC_PWR_ADDR_MAC,
|
||||
HALMAC_PWR_CMD_WRITE, 0xFF, 0x60},
|
||||
{0x0093,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_SDIO_MSK,
|
||||
HALMAC_PWR_ADDR_MAC,
|
||||
HALMAC_PWR_CMD_WRITE, 0xFF, 0xA},
|
||||
{0x0092,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_SDIO_MSK,
|
||||
HALMAC_PWR_ADDR_MAC,
|
||||
HALMAC_PWR_CMD_WRITE, 0xFF, 0x60},
|
||||
{0x0090,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
HALMAC_PWR_INTF_ALL_MSK,
|
||||
@@ -753,7 +803,7 @@ struct halmac_wlan_pwr_cfg TRANS_ACT_TO_DEEP_LPS_8822B[] = {
|
||||
HALMAC_PWR_CMD_END, 0, 0},
|
||||
};
|
||||
|
||||
struct halmac_wlan_pwr_cfg TRANS_LPS_TO_ACT_8822B[] = {
|
||||
static struct halmac_wlan_pwr_cfg TRANS_LPS_TO_ACT_8822B[] = {
|
||||
/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
|
||||
{0x0080,
|
||||
HALMAC_PWR_CUT_ALL_MSK,
|
||||
|
||||
@@ -21,7 +21,7 @@
|
||||
|
||||
#if HALMAC_8822B_SUPPORT
|
||||
|
||||
#define HALMAC_8822B_PWR_SEQ_VER "V24"
|
||||
#define HALMAC_8822B_PWR_SEQ_VER "V30"
|
||||
|
||||
extern struct halmac_wlan_pwr_cfg *card_en_flow_8822b[];
|
||||
extern struct halmac_wlan_pwr_cfg *card_dis_flow_8822b[];
|
||||
|
||||
@@ -1,868 +0,0 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "halmac_sdio_8822b.h"
|
||||
#include "halmac_pwr_seq_8822b.h"
|
||||
#include "../halmac_init_88xx.h"
|
||||
#include "../halmac_common_88xx.h"
|
||||
#include "../halmac_sdio_88xx.h"
|
||||
|
||||
#if HALMAC_8822B_SUPPORT
|
||||
|
||||
#define WLAN_ACQ_NUM_MAX 8
|
||||
|
||||
static enum halmac_ret_status
|
||||
chk_oqt_8822b(struct halmac_adapter *adapter, u32 tx_agg_num, u8 *buf,
|
||||
u8 macid_cnt);
|
||||
|
||||
static enum halmac_ret_status
|
||||
update_oqt_free_space_8822b(struct halmac_adapter *adapter);
|
||||
|
||||
static enum halmac_ret_status
|
||||
update_sdio_free_page_8822b(struct halmac_adapter *adapter);
|
||||
|
||||
static enum halmac_ret_status
|
||||
chk_qsel_8822b(struct halmac_adapter *adapter, u8 qsel_first, u8 *pkt,
|
||||
u8 *macid_cnt);
|
||||
|
||||
static enum halmac_ret_status
|
||||
chk_dma_mapping_8822b(struct halmac_adapter *adapter, u16 **cur_fs,
|
||||
u8 qsel_first);
|
||||
|
||||
static enum halmac_ret_status
|
||||
chk_rqd_page_num_8822b(struct halmac_adapter *adapter, u8 *buf, u32 *rqd_pg_num,
|
||||
u16 **cur_fs, u8 *macid_cnt, u32 tx_agg_num);
|
||||
|
||||
/**
|
||||
* mac_pwr_switch_sdio_8822b() - switch mac power
|
||||
* @adapter : the adapter of halmac
|
||||
* @pwr : power state
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
mac_pwr_switch_sdio_8822b(struct halmac_adapter *adapter,
|
||||
enum halmac_mac_power pwr)
|
||||
{
|
||||
u8 value8;
|
||||
u8 rpwm;
|
||||
u32 imr_backup;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
PLTFM_MSG_TRACE("[TRACE]8822B pwr seq ver = %s\n",
|
||||
HALMAC_8822B_PWR_SEQ_VER);
|
||||
|
||||
adapter->rpwm = HALMAC_REG_R8(REG_SDIO_HRPWM1);
|
||||
|
||||
/* Check FW still exist or not */
|
||||
if (HALMAC_REG_R16(REG_MCUFW_CTRL) == 0xC078) {
|
||||
/* Leave 32K */
|
||||
rpwm = (u8)((adapter->rpwm ^ BIT(7)) & 0x80);
|
||||
HALMAC_REG_W8(REG_SDIO_HRPWM1, rpwm);
|
||||
}
|
||||
|
||||
value8 = HALMAC_REG_R8(REG_CR);
|
||||
if (value8 == 0xEA)
|
||||
adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
|
||||
else
|
||||
adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
|
||||
|
||||
/*Check if power switch is needed*/
|
||||
if (pwr == HALMAC_MAC_POWER_ON &&
|
||||
adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_ON) {
|
||||
PLTFM_MSG_WARN("[WARN]power state unchange!!\n");
|
||||
return HALMAC_RET_PWR_UNCHANGE;
|
||||
}
|
||||
|
||||
imr_backup = HALMAC_REG_R32(REG_SDIO_HIMR);
|
||||
HALMAC_REG_W32(REG_SDIO_HIMR, 0);
|
||||
|
||||
if (pwr == HALMAC_MAC_POWER_OFF) {
|
||||
adapter->pwr_off_flow_flag = 1;
|
||||
if (pwr_seq_parser_88xx(adapter, card_dis_flow_8822b) !=
|
||||
HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]Handle power off cmd error\n");
|
||||
HALMAC_REG_W32(REG_SDIO_HIMR, imr_backup);
|
||||
return HALMAC_RET_POWER_OFF_FAIL;
|
||||
}
|
||||
|
||||
adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
|
||||
adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
|
||||
adapter->pwr_off_flow_flag = 0;
|
||||
init_adapter_dynamic_param_88xx(adapter);
|
||||
} else {
|
||||
if (pwr_seq_parser_88xx(adapter, card_en_flow_8822b) !=
|
||||
HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]Handle power on cmd error\n");
|
||||
HALMAC_REG_W32(REG_SDIO_HIMR, imr_backup);
|
||||
return HALMAC_RET_POWER_ON_FAIL;
|
||||
}
|
||||
|
||||
adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
|
||||
}
|
||||
|
||||
HALMAC_REG_W32(REG_SDIO_HIMR, imr_backup);
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* halmac_tx_allowed_sdio_88xx() - check tx status
|
||||
* @adapter : the adapter of halmac
|
||||
* @buf : tx packet, include txdesc
|
||||
* @size : tx packet size, include txdesc
|
||||
* Author : Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
tx_allowed_sdio_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size)
|
||||
{
|
||||
u16 *cur_fs = NULL;
|
||||
u32 cnt;
|
||||
u32 tx_agg_num;
|
||||
u32 rqd_pg_num = 0;
|
||||
u8 macid_cnt = 0;
|
||||
struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
if (!fs_info->macid_map) {
|
||||
PLTFM_MSG_ERR("[ERR]halmac allocate Macid_map Fail!!\n");
|
||||
return HALMAC_RET_MALLOC_FAIL;
|
||||
}
|
||||
|
||||
PLTFM_MEMSET(fs_info->macid_map, 0x00, fs_info->macid_map_size);
|
||||
|
||||
tx_agg_num = GET_TX_DESC_DMA_TXAGG_NUM(buf);
|
||||
tx_agg_num = (tx_agg_num == 0) ? 1 : tx_agg_num;
|
||||
|
||||
status = chk_rqd_page_num_8822b(adapter, buf, &rqd_pg_num, &cur_fs,
|
||||
&macid_cnt, tx_agg_num);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
|
||||
cnt = 10;
|
||||
do {
|
||||
if ((u32)(*cur_fs + fs_info->pubq_pg_num) > rqd_pg_num) {
|
||||
status = chk_oqt_8822b(adapter, tx_agg_num, buf,
|
||||
macid_cnt);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_WARN("[WARN]oqt buffer full!!\n");
|
||||
return status;
|
||||
}
|
||||
|
||||
if (*cur_fs >= rqd_pg_num) {
|
||||
*cur_fs -= (u16)rqd_pg_num;
|
||||
} else {
|
||||
fs_info->pubq_pg_num -=
|
||||
(u16)(rqd_pg_num - *cur_fs);
|
||||
*cur_fs = 0;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
update_sdio_free_page_8822b(adapter);
|
||||
|
||||
cnt--;
|
||||
if (cnt == 0)
|
||||
return HALMAC_RET_FREE_SPACE_NOT_ENOUGH;
|
||||
} while (1);
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* halmac_reg_read_8_sdio_88xx() - read 1byte register
|
||||
* @adapter : the adapter of halmac
|
||||
* @offset : register offset
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
u8
|
||||
reg_r8_sdio_8822b(struct halmac_adapter *adapter, u32 offset)
|
||||
{
|
||||
u8 value8;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
if ((offset & 0xFFFF0000) == 0) {
|
||||
value8 = (u8)r_indir_sdio_88xx(adapter, offset, HALMAC_IO_BYTE);
|
||||
} else {
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]convert offset\n");
|
||||
return status;
|
||||
}
|
||||
value8 = PLTFM_SDIO_CMD52_R(offset);
|
||||
}
|
||||
|
||||
return value8;
|
||||
}
|
||||
|
||||
/**
|
||||
* halmac_reg_write_8_sdio_88xx() - write 1byte register
|
||||
* @adapter : the adapter of halmac
|
||||
* @offset : register offset
|
||||
* @value : register value
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
reg_w8_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u8 value)
|
||||
{
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
if ((offset & 0xFFFF0000) == 0)
|
||||
offset |= WLAN_IOREG_OFFSET;
|
||||
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
|
||||
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]convert offset\n");
|
||||
return status;
|
||||
}
|
||||
|
||||
PLTFM_SDIO_CMD52_W(offset, value);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* halmac_reg_read_16_sdio_88xx() - read 2byte register
|
||||
* @adapter : the adapter of halmac
|
||||
* @offset : register offset
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
u16
|
||||
reg_r16_sdio_8822b(struct halmac_adapter *adapter, u32 offset)
|
||||
{
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
union {
|
||||
u16 word;
|
||||
u8 byte[2];
|
||||
} value16 = { 0x0000 };
|
||||
|
||||
if ((offset & 0xFFFF0000) == 0)
|
||||
return (u16)r_indir_sdio_88xx(adapter, offset, HALMAC_IO_WORD);
|
||||
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]convert offset\n");
|
||||
return status;
|
||||
}
|
||||
|
||||
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF ||
|
||||
((offset & (2 - 1)) != 0) ||
|
||||
adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_RW ||
|
||||
adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_R) {
|
||||
value16.byte[0] = PLTFM_SDIO_CMD52_R(offset);
|
||||
value16.byte[1] = PLTFM_SDIO_CMD52_R(offset + 1);
|
||||
value16.word = rtk_le16_to_cpu(value16.word);
|
||||
} else {
|
||||
value16.word = PLTFM_SDIO_CMD53_R16(offset);
|
||||
}
|
||||
|
||||
return value16.word;
|
||||
}
|
||||
|
||||
/**
|
||||
* halmac_reg_write_16_sdio_88xx() - write 2byte register
|
||||
* @adapter : the adapter of halmac
|
||||
* @offset : register offset
|
||||
* @value : register value
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
reg_w16_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u16 value)
|
||||
{
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF ||
|
||||
((offset & (2 - 1)) != 0) ||
|
||||
adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_RW ||
|
||||
adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_W) {
|
||||
if ((offset & 0xFFFF0000) == 0 && ((offset & (2 - 1)) == 0)) {
|
||||
status = w_indir_sdio_88xx(adapter, offset, value,
|
||||
HALMAC_IO_WORD);
|
||||
} else {
|
||||
if ((offset & 0xFFFF0000) == 0)
|
||||
offset |= WLAN_IOREG_OFFSET;
|
||||
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]convert offset\n");
|
||||
return status;
|
||||
}
|
||||
PLTFM_SDIO_CMD52_W(offset, (u8)(value & 0xFF));
|
||||
PLTFM_SDIO_CMD52_W(offset + 1,
|
||||
(u8)((value & 0xFF00) >> 8));
|
||||
}
|
||||
} else {
|
||||
if ((offset & 0xFFFF0000) == 0)
|
||||
offset |= WLAN_IOREG_OFFSET;
|
||||
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]convert offset\n");
|
||||
return status;
|
||||
}
|
||||
|
||||
PLTFM_SDIO_CMD53_W16(offset, value);
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* halmac_reg_read_32_sdio_88xx() - read 4byte register
|
||||
* @adapter : the adapter of halmac
|
||||
* @offset : register offset
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
u32
|
||||
reg_r32_sdio_8822b(struct halmac_adapter *adapter, u32 offset)
|
||||
{
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
union {
|
||||
u32 dword;
|
||||
u8 byte[4];
|
||||
} value32 = { 0x00000000 };
|
||||
|
||||
if ((offset & 0xFFFF0000) == 0)
|
||||
return r_indir_sdio_88xx(adapter, offset, HALMAC_IO_DWORD);
|
||||
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]convert offset\n");
|
||||
return status;
|
||||
}
|
||||
|
||||
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF ||
|
||||
(offset & (4 - 1)) != 0) {
|
||||
value32.byte[0] = PLTFM_SDIO_CMD52_R(offset);
|
||||
value32.byte[1] = PLTFM_SDIO_CMD52_R(offset + 1);
|
||||
value32.byte[2] = PLTFM_SDIO_CMD52_R(offset + 2);
|
||||
value32.byte[3] = PLTFM_SDIO_CMD52_R(offset + 3);
|
||||
value32.dword = rtk_le32_to_cpu(value32.dword);
|
||||
} else {
|
||||
value32.dword = PLTFM_SDIO_CMD53_R32(offset);
|
||||
}
|
||||
|
||||
return value32.dword;
|
||||
}
|
||||
|
||||
/**
|
||||
* halmac_reg_write_32_sdio_88xx() - write 4byte register
|
||||
* @adapter : the adapter of halmac
|
||||
* @offset : register offset
|
||||
* @value : register value
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
reg_w32_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u32 value)
|
||||
{
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF ||
|
||||
(offset & (4 - 1)) != 0) {
|
||||
if ((offset & 0xFFFF0000) == 0 && ((offset & (4 - 1)) == 0)) {
|
||||
status = w_indir_sdio_88xx(adapter, offset, value,
|
||||
HALMAC_IO_DWORD);
|
||||
} else {
|
||||
if ((offset & 0xFFFF0000) == 0)
|
||||
offset |= WLAN_IOREG_OFFSET;
|
||||
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]convert offset\n");
|
||||
return status;
|
||||
}
|
||||
PLTFM_SDIO_CMD52_W(offset, (u8)(value & 0xFF));
|
||||
PLTFM_SDIO_CMD52_W(offset + 1,
|
||||
(u8)((value >> 8) & 0xFF));
|
||||
PLTFM_SDIO_CMD52_W(offset + 2,
|
||||
(u8)((value >> 16) & 0xFF));
|
||||
PLTFM_SDIO_CMD52_W(offset + 3,
|
||||
(u8)((value >> 24) & 0xFF));
|
||||
}
|
||||
} else {
|
||||
if ((offset & 0xFFFF0000) == 0)
|
||||
offset |= WLAN_IOREG_OFFSET;
|
||||
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]convert offset\n");
|
||||
return status;
|
||||
}
|
||||
PLTFM_SDIO_CMD53_W32(offset, value);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static enum halmac_ret_status
|
||||
chk_oqt_8822b(struct halmac_adapter *adapter, u32 tx_agg_num, u8 *buf,
|
||||
u8 macid_cnt)
|
||||
{
|
||||
u32 cnt = 10;
|
||||
struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
|
||||
|
||||
/*S0, S1 are not allowed to use, 0x4E4[0] should be 0. Soar 20160323*/
|
||||
/*no need to check non_ac_oqt_number*/
|
||||
/*HI and MGQ blocked will cause protocal issue before H_OQT being full*/
|
||||
switch ((enum halmac_qsel)GET_TX_DESC_QSEL(buf)) {
|
||||
case HALMAC_QSEL_VO:
|
||||
case HALMAC_QSEL_VO_V2:
|
||||
case HALMAC_QSEL_VI:
|
||||
case HALMAC_QSEL_VI_V2:
|
||||
case HALMAC_QSEL_BE:
|
||||
case HALMAC_QSEL_BE_V2:
|
||||
case HALMAC_QSEL_BK:
|
||||
case HALMAC_QSEL_BK_V2:
|
||||
if (macid_cnt > WLAN_ACQ_NUM_MAX &&
|
||||
tx_agg_num > OQT_ENTRY_AC_8822B) {
|
||||
PLTFM_MSG_WARN("[WARN]txagg num %d > oqt entry\n",
|
||||
tx_agg_num);
|
||||
PLTFM_MSG_WARN("[WARN]macid cnt %d > acq max\n",
|
||||
macid_cnt);
|
||||
}
|
||||
|
||||
cnt = 10;
|
||||
do {
|
||||
if (fs_info->ac_empty >= macid_cnt) {
|
||||
fs_info->ac_empty -= macid_cnt;
|
||||
break;
|
||||
}
|
||||
|
||||
if (fs_info->ac_oqt_num >= tx_agg_num) {
|
||||
fs_info->ac_empty = 0;
|
||||
fs_info->ac_oqt_num -= (u8)tx_agg_num;
|
||||
break;
|
||||
}
|
||||
|
||||
update_oqt_free_space_8822b(adapter);
|
||||
|
||||
cnt--;
|
||||
if (cnt == 0)
|
||||
return HALMAC_RET_OQT_NOT_ENOUGH;
|
||||
} while (1);
|
||||
break;
|
||||
case HALMAC_QSEL_MGNT:
|
||||
case HALMAC_QSEL_HIGH:
|
||||
if (tx_agg_num > OQT_ENTRY_NOAC_8822B)
|
||||
PLTFM_MSG_WARN("[WARN]tx_agg_num %d > oqt entry\n",
|
||||
tx_agg_num, OQT_ENTRY_NOAC_8822B);
|
||||
|
||||
cnt = 10;
|
||||
do {
|
||||
if (fs_info->non_ac_oqt_num >= tx_agg_num) {
|
||||
fs_info->non_ac_oqt_num -= (u8)tx_agg_num;
|
||||
break;
|
||||
}
|
||||
|
||||
update_oqt_free_space_8822b(adapter);
|
||||
|
||||
cnt--;
|
||||
if (cnt == 0)
|
||||
return HALMAC_RET_OQT_NOT_ENOUGH;
|
||||
} while (1);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
static enum halmac_ret_status
|
||||
update_oqt_free_space_8822b(struct halmac_adapter *adapter)
|
||||
{
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
|
||||
u8 value;
|
||||
u32 oqt_free_page;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
oqt_free_page = HALMAC_REG_R32(REG_SDIO_OQT_FREE_TXPG_V1);
|
||||
fs_info->ac_oqt_num = (u8)BIT_GET_AC_OQT_FREEPG_V1(oqt_free_page);
|
||||
fs_info->non_ac_oqt_num = (u8)BIT_GET_NOAC_OQT_FREEPG_V1(oqt_free_page);
|
||||
fs_info->ac_empty = 0;
|
||||
if (fs_info->ac_oqt_num == OQT_ENTRY_AC_8822B) {
|
||||
value = HALMAC_REG_R8(REG_TXPKT_EMPTY);
|
||||
while (value > 0) {
|
||||
value = value & (value - 1);
|
||||
fs_info->ac_empty++;
|
||||
};
|
||||
} else {
|
||||
PLTFM_MSG_TRACE("[TRACE]free_space->ac_oqt_num %d != %d\n",
|
||||
fs_info->ac_oqt_num, OQT_ENTRY_AC_8822B);
|
||||
}
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
static enum halmac_ret_status
|
||||
update_sdio_free_page_8822b(struct halmac_adapter *adapter)
|
||||
{
|
||||
u32 free_page = 0;
|
||||
u32 free_page2 = 0;
|
||||
u32 free_page3 = 0;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
|
||||
u8 data[12] = {0};
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
HALMAC_REG_SDIO_RN(REG_SDIO_FREE_TXPG, 12, data);
|
||||
|
||||
free_page = rtk_le32_to_cpu(*(u32 *)(data + 0));
|
||||
free_page2 = rtk_le32_to_cpu(*(u32 *)(data + 4));
|
||||
free_page3 = rtk_le32_to_cpu(*(u32 *)(data + 8));
|
||||
|
||||
fs_info->hiq_pg_num = (u16)BIT_GET_HIQ_FREEPG_V1(free_page);
|
||||
fs_info->miq_pg_num = (u16)BIT_GET_MID_FREEPG_V1(free_page);
|
||||
fs_info->lowq_pg_num = (u16)BIT_GET_LOW_FREEPG_V1(free_page2);
|
||||
fs_info->pubq_pg_num = (u16)BIT_GET_PUB_FREEPG_V1(free_page2);
|
||||
fs_info->exq_pg_num = (u16)BIT_GET_EXQ_FREEPG_V1(free_page3);
|
||||
fs_info->ac_oqt_num = (u8)BIT_GET_AC_OQT_FREEPG_V1(free_page3);
|
||||
fs_info->non_ac_oqt_num = (u8)BIT_GET_NOAC_OQT_FREEPG_V1(free_page3);
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* phy_cfg_sdio_8822b() - phy config
|
||||
* @adapter : the adapter of halmac
|
||||
* Author : KaiYuan Chang
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
phy_cfg_sdio_8822b(struct halmac_adapter *adapter,
|
||||
enum halmac_intf_phy_platform pltfm)
|
||||
{
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* halmac_pcie_switch_8821c() - pcie gen1/gen2 switch
|
||||
* @adapter : the adapter of halmac
|
||||
* @cfg : gen1/gen2 selection
|
||||
* Author : KaiYuan Chang
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
pcie_switch_sdio_8822b(struct halmac_adapter *adapter,
|
||||
enum halmac_pcie_cfg cfg)
|
||||
{
|
||||
return HALMAC_RET_NOT_SUPPORT;
|
||||
}
|
||||
|
||||
/**
|
||||
* intf_tun_sdio_8822b() - sdio interface fine tuning
|
||||
* @adapter : the adapter of halmac
|
||||
* Author : Ivan
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
intf_tun_sdio_8822b(struct halmac_adapter *adapter)
|
||||
{
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* halmac_get_sdio_tx_addr_sdio_88xx() - get CMD53 addr for the TX packet
|
||||
* @adapter : the adapter of halmac
|
||||
* @buf : tx packet, include txdesc
|
||||
* @size : tx packet size
|
||||
* @cmd53_addr : cmd53 addr value
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
get_sdio_tx_addr_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size,
|
||||
u32 *cmd53_addr)
|
||||
{
|
||||
u32 len_unit4;
|
||||
enum halmac_qsel queue_sel;
|
||||
enum halmac_dma_mapping dma_mapping;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
if (!buf) {
|
||||
PLTFM_MSG_ERR("[ERR]buf is NULL!!\n");
|
||||
return HALMAC_RET_DATA_BUF_NULL;
|
||||
}
|
||||
|
||||
if (size == 0) {
|
||||
PLTFM_MSG_ERR("[ERR]size is 0!!\n");
|
||||
return HALMAC_RET_DATA_SIZE_INCORRECT;
|
||||
}
|
||||
|
||||
queue_sel = (enum halmac_qsel)GET_TX_DESC_QSEL(buf);
|
||||
|
||||
switch (queue_sel) {
|
||||
case HALMAC_QSEL_VO:
|
||||
case HALMAC_QSEL_VO_V2:
|
||||
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VO];
|
||||
break;
|
||||
case HALMAC_QSEL_VI:
|
||||
case HALMAC_QSEL_VI_V2:
|
||||
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VI];
|
||||
break;
|
||||
case HALMAC_QSEL_BE:
|
||||
case HALMAC_QSEL_BE_V2:
|
||||
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BE];
|
||||
break;
|
||||
case HALMAC_QSEL_BK:
|
||||
case HALMAC_QSEL_BK_V2:
|
||||
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BK];
|
||||
break;
|
||||
case HALMAC_QSEL_MGNT:
|
||||
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_MG];
|
||||
break;
|
||||
case HALMAC_QSEL_HIGH:
|
||||
case HALMAC_QSEL_BCN:
|
||||
case HALMAC_QSEL_CMD:
|
||||
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_HI];
|
||||
break;
|
||||
default:
|
||||
PLTFM_MSG_ERR("[ERR]Qsel is out of range\n");
|
||||
return HALMAC_RET_QSEL_INCORRECT;
|
||||
}
|
||||
|
||||
len_unit4 = (size >> 2) + ((size & (4 - 1)) ? 1 : 0);
|
||||
|
||||
switch (dma_mapping) {
|
||||
case HALMAC_DMA_MAPPING_HIGH:
|
||||
*cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_HIGH;
|
||||
break;
|
||||
case HALMAC_DMA_MAPPING_NORMAL:
|
||||
*cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL;
|
||||
break;
|
||||
case HALMAC_DMA_MAPPING_LOW:
|
||||
*cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_LOW;
|
||||
break;
|
||||
case HALMAC_DMA_MAPPING_EXTRA:
|
||||
*cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA;
|
||||
break;
|
||||
default:
|
||||
PLTFM_MSG_ERR("[ERR]DmaMapping is out of range\n");
|
||||
return HALMAC_RET_DMA_MAP_INCORRECT;
|
||||
}
|
||||
|
||||
*cmd53_addr = (*cmd53_addr << 13) |
|
||||
(len_unit4 & HALMAC_SDIO_4BYTE_LEN_MASK);
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
static enum halmac_ret_status
|
||||
chk_qsel_8822b(struct halmac_adapter *adapter, u8 qsel_first, u8 *pkt,
|
||||
u8 *macid_cnt)
|
||||
{
|
||||
u8 flag = 0;
|
||||
u8 qsel_now;
|
||||
u8 macid;
|
||||
struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
|
||||
|
||||
macid = (u8)GET_TX_DESC_MACID(pkt);
|
||||
qsel_now = (u8)GET_TX_DESC_QSEL(pkt);
|
||||
if (qsel_first == qsel_now) {
|
||||
if (*(fs_info->macid_map + macid) == 0) {
|
||||
*(fs_info->macid_map + macid) = 1;
|
||||
(*macid_cnt)++;
|
||||
}
|
||||
} else {
|
||||
switch ((enum halmac_qsel)qsel_now) {
|
||||
case HALMAC_QSEL_VO:
|
||||
if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VO_V2)
|
||||
flag = 1;
|
||||
break;
|
||||
case HALMAC_QSEL_VO_V2:
|
||||
if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VO)
|
||||
flag = 1;
|
||||
break;
|
||||
case HALMAC_QSEL_VI:
|
||||
if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VI_V2)
|
||||
flag = 1;
|
||||
break;
|
||||
case HALMAC_QSEL_VI_V2:
|
||||
if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VI)
|
||||
flag = 1;
|
||||
break;
|
||||
case HALMAC_QSEL_BE:
|
||||
if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BE_V2)
|
||||
flag = 1;
|
||||
break;
|
||||
case HALMAC_QSEL_BE_V2:
|
||||
if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BE)
|
||||
flag = 1;
|
||||
break;
|
||||
case HALMAC_QSEL_BK:
|
||||
if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BK_V2)
|
||||
flag = 1;
|
||||
break;
|
||||
case HALMAC_QSEL_BK_V2:
|
||||
if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BK)
|
||||
flag = 1;
|
||||
break;
|
||||
case HALMAC_QSEL_MGNT:
|
||||
case HALMAC_QSEL_HIGH:
|
||||
case HALMAC_QSEL_BCN:
|
||||
case HALMAC_QSEL_CMD:
|
||||
flag = 1;
|
||||
break;
|
||||
default:
|
||||
PLTFM_MSG_ERR("[ERR]Qsel is out of range\n");
|
||||
return HALMAC_RET_QSEL_INCORRECT;
|
||||
}
|
||||
if (flag == 1) {
|
||||
PLTFM_MSG_ERR("[ERR]Multi-Qsel is not allowed\n");
|
||||
PLTFM_MSG_ERR("[ERR]qsel = %d, %d\n",
|
||||
qsel_first, qsel_now);
|
||||
return HALMAC_RET_QSEL_INCORRECT;
|
||||
}
|
||||
if (*(fs_info->macid_map + macid + MACID_MAX_8822B) == 0) {
|
||||
*(fs_info->macid_map + macid + MACID_MAX_8822B) = 1;
|
||||
(*macid_cnt)++;
|
||||
}
|
||||
}
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
static enum halmac_ret_status
|
||||
chk_dma_mapping_8822b(struct halmac_adapter *adapter, u16 **cur_fs,
|
||||
u8 qsel_first)
|
||||
{
|
||||
enum halmac_dma_mapping dma_mapping;
|
||||
|
||||
switch ((enum halmac_qsel)qsel_first) {
|
||||
case HALMAC_QSEL_VO:
|
||||
case HALMAC_QSEL_VO_V2:
|
||||
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VO];
|
||||
break;
|
||||
case HALMAC_QSEL_VI:
|
||||
case HALMAC_QSEL_VI_V2:
|
||||
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VI];
|
||||
break;
|
||||
case HALMAC_QSEL_BE:
|
||||
case HALMAC_QSEL_BE_V2:
|
||||
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BE];
|
||||
break;
|
||||
case HALMAC_QSEL_BK:
|
||||
case HALMAC_QSEL_BK_V2:
|
||||
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BK];
|
||||
break;
|
||||
case HALMAC_QSEL_MGNT:
|
||||
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_MG];
|
||||
break;
|
||||
case HALMAC_QSEL_HIGH:
|
||||
dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_HI];
|
||||
break;
|
||||
case HALMAC_QSEL_BCN:
|
||||
case HALMAC_QSEL_CMD:
|
||||
return HALMAC_RET_SUCCESS;
|
||||
default:
|
||||
PLTFM_MSG_ERR("[ERR]Qsel is out of range: %d\n", qsel_first);
|
||||
return HALMAC_RET_QSEL_INCORRECT;
|
||||
}
|
||||
|
||||
switch (dma_mapping) {
|
||||
case HALMAC_DMA_MAPPING_HIGH:
|
||||
*cur_fs = &adapter->sdio_fs.hiq_pg_num;
|
||||
break;
|
||||
case HALMAC_DMA_MAPPING_NORMAL:
|
||||
*cur_fs = &adapter->sdio_fs.miq_pg_num;
|
||||
break;
|
||||
case HALMAC_DMA_MAPPING_LOW:
|
||||
*cur_fs = &adapter->sdio_fs.lowq_pg_num;
|
||||
break;
|
||||
case HALMAC_DMA_MAPPING_EXTRA:
|
||||
*cur_fs = &adapter->sdio_fs.exq_pg_num;
|
||||
break;
|
||||
default:
|
||||
PLTFM_MSG_ERR("[ERR]DmaMapping is out of range\n");
|
||||
return HALMAC_RET_DMA_MAP_INCORRECT;
|
||||
}
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
static enum halmac_ret_status
|
||||
chk_rqd_page_num_8822b(struct halmac_adapter *adapter, u8 *buf, u32 *rqd_pg_num,
|
||||
u16 **cur_fs, u8 *macid_cnt, u32 tx_agg_num)
|
||||
{
|
||||
u8 *pkt;
|
||||
u8 qsel_first;
|
||||
u32 i;
|
||||
u32 pkt_size;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
pkt = buf;
|
||||
|
||||
qsel_first = (u8)GET_TX_DESC_QSEL(pkt);
|
||||
|
||||
status = chk_dma_mapping_8822b(adapter, cur_fs, qsel_first);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
|
||||
for (i = 0; i < tx_agg_num; i++) {
|
||||
/*QSEL parser*/
|
||||
status = chk_qsel_8822b(adapter, qsel_first, pkt, macid_cnt);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
|
||||
/*Page number parser*/
|
||||
pkt_size = GET_TX_DESC_TXPKTSIZE(pkt) + GET_TX_DESC_OFFSET(pkt);
|
||||
*rqd_pg_num += (pkt_size >> TX_PAGE_SIZE_SHIFT_88XX) +
|
||||
((pkt_size & (TX_PAGE_SIZE_88XX - 1)) ? 1 : 0);
|
||||
|
||||
pkt += HALMAC_ALIGN(GET_TX_DESC_TXPKTSIZE(pkt) +
|
||||
(GET_TX_DESC_PKT_OFFSET(pkt) << 3) +
|
||||
TX_DESC_SIZE_88XX, 8);
|
||||
}
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
#endif /* HALMAC_8822B_SUPPORT*/
|
||||
@@ -1,66 +0,0 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _HALMAC_API_8822B_SDIO_H_
|
||||
#define _HALMAC_API_8822B_SDIO_H_
|
||||
|
||||
#include "../../halmac_api.h"
|
||||
#include "halmac_8822b_cfg.h"
|
||||
|
||||
#if HALMAC_8822B_SUPPORT
|
||||
|
||||
enum halmac_ret_status
|
||||
mac_pwr_switch_sdio_8822b(struct halmac_adapter *adapter,
|
||||
enum halmac_mac_power pwr);
|
||||
|
||||
enum halmac_ret_status
|
||||
tx_allowed_sdio_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size);
|
||||
|
||||
u8
|
||||
reg_r8_sdio_8822b(struct halmac_adapter *adapter, u32 offset);
|
||||
|
||||
enum halmac_ret_status
|
||||
reg_w8_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u8 value);
|
||||
|
||||
u16
|
||||
reg_r16_sdio_8822b(struct halmac_adapter *adapter, u32 offset);
|
||||
|
||||
enum halmac_ret_status
|
||||
reg_w16_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u16 value);
|
||||
|
||||
u32
|
||||
reg_r32_sdio_8822b(struct halmac_adapter *adapter, u32 offset);
|
||||
|
||||
enum halmac_ret_status
|
||||
reg_w32_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u32 value);
|
||||
|
||||
enum halmac_ret_status
|
||||
phy_cfg_sdio_8822b(struct halmac_adapter *adapter,
|
||||
enum halmac_intf_phy_platform pltfm);
|
||||
|
||||
enum halmac_ret_status
|
||||
pcie_switch_sdio_8822b(struct halmac_adapter *adapter,
|
||||
enum halmac_pcie_cfg cfg);
|
||||
|
||||
enum halmac_ret_status
|
||||
intf_tun_sdio_8822b(struct halmac_adapter *adapter);
|
||||
|
||||
enum halmac_ret_status
|
||||
get_sdio_tx_addr_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size,
|
||||
u32 *cmd53_addr);
|
||||
|
||||
#endif /* HALMAC_8822B_SUPPORT*/
|
||||
|
||||
#endif/* _HALMAC_API_8822B_SDIO_H_ */
|
||||
@@ -18,7 +18,7 @@
|
||||
#include "../halmac_init_88xx.h"
|
||||
#include "../halmac_common_88xx.h"
|
||||
|
||||
#if HALMAC_8822B_SUPPORT
|
||||
#if (HALMAC_8822B_SUPPORT && HALMAC_USB_SUPPORT)
|
||||
|
||||
/**
|
||||
* mac_pwr_switch_usb_8822b() - switch mac power
|
||||
@@ -118,7 +118,7 @@ phy_cfg_usb_8822b(struct halmac_adapter *adapter,
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
|
||||
status = parse_intf_phy_88xx(adapter, usb3_phy_8822b, pltfm,
|
||||
status = parse_intf_phy_88xx(adapter, usb3_phy_param_8822b, pltfm,
|
||||
HAL_INTF_PHY_USB3);
|
||||
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
@@ -156,4 +156,4 @@ intf_tun_usb_8822b(struct halmac_adapter *adapter)
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
#endif /* HALMAC_8822B_SUPPORT*/
|
||||
#endif /* HALMAC_8822B_SUPPORT */
|
||||
|
||||
@@ -18,10 +18,10 @@
|
||||
|
||||
#include "../../halmac_api.h"
|
||||
|
||||
#if HALMAC_8822B_SUPPORT
|
||||
#if (HALMAC_8822B_SUPPORT && HALMAC_USB_SUPPORT)
|
||||
|
||||
extern struct halmac_intf_phy_para usb2_phy_param_8822b[];
|
||||
extern struct halmac_intf_phy_para usb3_phy_8822b[];
|
||||
extern struct halmac_intf_phy_para usb3_phy_param_8822b[];
|
||||
|
||||
enum halmac_ret_status
|
||||
mac_pwr_switch_usb_8822b(struct halmac_adapter *adapter,
|
||||
|
||||
@@ -56,7 +56,7 @@ start_iqk_88xx(struct halmac_adapter *adapter, struct halmac_iqk_para *param)
|
||||
|
||||
hdr_info.sub_cmd_id = SUB_CMD_ID_IQK;
|
||||
hdr_info.content_size = 1;
|
||||
hdr_info.ack = _TRUE;
|
||||
hdr_info.ack = 1;
|
||||
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
|
||||
|
||||
adapter->halmac_state.iqk_state.seq_num = seq_num;
|
||||
@@ -116,16 +116,19 @@ ctrl_pwr_tracking_88xx(struct halmac_adapter *adapter,
|
||||
PWR_TRK_SET_TSSI_VALUE_A(h2c_buf, param->tssi_value);
|
||||
PWR_TRK_SET_OFFSET_VALUE_A(h2c_buf, param->pwr_tracking_offset_value);
|
||||
|
||||
param = &opt->pwr_tracking_para[HALMAC_RF_PATH_B];
|
||||
PWR_TRK_SET_ENABLE_B(h2c_buf, param->enable);
|
||||
PWR_TRK_SET_TX_PWR_INDEX_B(h2c_buf, param->tx_pwr_index);
|
||||
PWR_TRK_SET_TSSI_VALUE_B(h2c_buf, param->tssi_value);
|
||||
PWR_TRK_SET_OFFSET_VALUE_B(h2c_buf, param->pwr_tracking_offset_value);
|
||||
|
||||
param = &opt->pwr_tracking_para[HALMAC_RF_PATH_C];
|
||||
PWR_TRK_SET_ENABLE_C(h2c_buf, param->enable);
|
||||
PWR_TRK_SET_TX_PWR_INDEX_C(h2c_buf, param->tx_pwr_index);
|
||||
PWR_TRK_SET_TSSI_VALUE_C(h2c_buf, param->tssi_value);
|
||||
PWR_TRK_SET_OFFSET_VALUE_C(h2c_buf, param->pwr_tracking_offset_value);
|
||||
|
||||
param = &opt->pwr_tracking_para[HALMAC_RF_PATH_D];
|
||||
PWR_TRK_SET_ENABLE_D(h2c_buf, param->enable);
|
||||
PWR_TRK_SET_TX_PWR_INDEX_D(h2c_buf, param->tx_pwr_index);
|
||||
PWR_TRK_SET_TSSI_VALUE_D(h2c_buf, param->tssi_value);
|
||||
@@ -133,7 +136,7 @@ ctrl_pwr_tracking_88xx(struct halmac_adapter *adapter,
|
||||
|
||||
hdr_info.sub_cmd_id = SUB_CMD_ID_PWR_TRK;
|
||||
hdr_info.content_size = 20;
|
||||
hdr_info.ack = _TRUE;
|
||||
hdr_info.ack = 1;
|
||||
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
|
||||
|
||||
adapter->halmac_state.pwr_trk_state.seq_num = seq_num;
|
||||
@@ -243,7 +246,7 @@ psd_88xx(struct halmac_adapter *adapter, u16 start_psd, u16 end_psd)
|
||||
|
||||
hdr_info.sub_cmd_id = SUB_CMD_ID_PSD;
|
||||
hdr_info.content_size = 4;
|
||||
hdr_info.ack = _TRUE;
|
||||
hdr_info.ack = 1;
|
||||
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
|
||||
|
||||
status = send_h2c_pkt_88xx(adapter, h2c_buf);
|
||||
@@ -377,7 +380,7 @@ get_psd_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
|
||||
PLTFM_MEMCPY(state->data + seg_id * state->seg_size,
|
||||
buf + C2H_DATA_OFFSET_88XX, seg_size);
|
||||
|
||||
if (PSD_DATA_GET_END_SEGMENT(buf) == _FALSE)
|
||||
if (PSD_DATA_GET_END_SEGMENT(buf) == 0)
|
||||
return HALMAC_RET_SUCCESS;
|
||||
|
||||
proc_status = HALMAC_CMD_PROCESS_DONE;
|
||||
|
||||
@@ -15,10 +15,12 @@
|
||||
|
||||
#include "halmac_cfg_wmac_88xx.h"
|
||||
#include "halmac_88xx_cfg.h"
|
||||
#include "halmac_efuse_88xx.h"
|
||||
|
||||
#if HALMAC_88XX_SUPPORT
|
||||
|
||||
#define MAC_CLK_SPEED 80 /* 80M */
|
||||
#define EFUSE_PCB_INFO_OFFSET 0xCA
|
||||
|
||||
enum mac_clock_hw_def {
|
||||
MAC_CLK_HW_DEF_80M = 0,
|
||||
@@ -26,6 +28,9 @@ enum mac_clock_hw_def {
|
||||
MAC_CLK_HW_DEF_20M = 2,
|
||||
};
|
||||
|
||||
static enum halmac_ret_status
|
||||
board_rf_fine_tune_88xx(struct halmac_adapter *adapter);
|
||||
|
||||
/**
|
||||
* cfg_mac_addr_88xx() - config mac address
|
||||
* @adapter : the adapter of halmac
|
||||
@@ -39,8 +44,7 @@ enum halmac_ret_status
|
||||
cfg_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,
|
||||
union halmac_wlan_addr *addr)
|
||||
{
|
||||
u16 mac_addr_h;
|
||||
u32 mac_addr_l;
|
||||
u32 offset;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
@@ -50,37 +54,29 @@ cfg_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,
|
||||
return HALMAC_RET_PORT_NOT_SUPPORT;
|
||||
}
|
||||
|
||||
mac_addr_l = addr->addr_l_h.low;
|
||||
mac_addr_h = addr->addr_l_h.high;
|
||||
|
||||
mac_addr_l = rtk_le32_to_cpu(mac_addr_l);
|
||||
mac_addr_h = rtk_le16_to_cpu(mac_addr_h);
|
||||
|
||||
switch (port) {
|
||||
case HALMAC_PORTID0:
|
||||
HALMAC_REG_W32(REG_MACID, mac_addr_l);
|
||||
HALMAC_REG_W16(REG_MACID + 4, mac_addr_h);
|
||||
offset = REG_MACID;
|
||||
break;
|
||||
case HALMAC_PORTID1:
|
||||
HALMAC_REG_W32(REG_MACID1, mac_addr_l);
|
||||
HALMAC_REG_W16(REG_MACID1 + 4, mac_addr_h);
|
||||
offset = REG_MACID1;
|
||||
break;
|
||||
case HALMAC_PORTID2:
|
||||
HALMAC_REG_W32(REG_MACID2, mac_addr_l);
|
||||
HALMAC_REG_W16(REG_MACID2 + 4, mac_addr_h);
|
||||
offset = REG_MACID2;
|
||||
break;
|
||||
case HALMAC_PORTID3:
|
||||
HALMAC_REG_W32(REG_MACID3, mac_addr_l);
|
||||
HALMAC_REG_W16(REG_MACID3 + 4, mac_addr_h);
|
||||
offset = REG_MACID3;
|
||||
break;
|
||||
case HALMAC_PORTID4:
|
||||
HALMAC_REG_W32(REG_MACID4, mac_addr_l);
|
||||
HALMAC_REG_W16(REG_MACID4 + 4, mac_addr_h);
|
||||
offset = REG_MACID4;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
return HALMAC_RET_PORT_NOT_SUPPORT;
|
||||
}
|
||||
|
||||
HALMAC_REG_W32(offset, rtk_le32_to_cpu(addr->addr_l_h.low));
|
||||
HALMAC_REG_W16(offset + 4, rtk_le16_to_cpu(addr->addr_l_h.high));
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
@@ -99,8 +95,7 @@ enum halmac_ret_status
|
||||
cfg_bssid_88xx(struct halmac_adapter *adapter, u8 port,
|
||||
union halmac_wlan_addr *addr)
|
||||
{
|
||||
u16 bssid_addr_h;
|
||||
u32 bssid_addr_l;
|
||||
u32 offset;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
@@ -110,37 +105,29 @@ cfg_bssid_88xx(struct halmac_adapter *adapter, u8 port,
|
||||
return HALMAC_RET_PORT_NOT_SUPPORT;
|
||||
}
|
||||
|
||||
bssid_addr_l = addr->addr_l_h.low;
|
||||
bssid_addr_h = addr->addr_l_h.high;
|
||||
|
||||
bssid_addr_l = rtk_le32_to_cpu(bssid_addr_l);
|
||||
bssid_addr_h = rtk_le16_to_cpu(bssid_addr_h);
|
||||
|
||||
switch (port) {
|
||||
case HALMAC_PORTID0:
|
||||
HALMAC_REG_W32(REG_BSSID, bssid_addr_l);
|
||||
HALMAC_REG_W16(REG_BSSID + 4, bssid_addr_h);
|
||||
offset = REG_BSSID;
|
||||
break;
|
||||
case HALMAC_PORTID1:
|
||||
HALMAC_REG_W32(REG_BSSID1, bssid_addr_l);
|
||||
HALMAC_REG_W16(REG_BSSID1 + 4, bssid_addr_h);
|
||||
offset = REG_BSSID1;
|
||||
break;
|
||||
case HALMAC_PORTID2:
|
||||
HALMAC_REG_W32(REG_BSSID2, bssid_addr_l);
|
||||
HALMAC_REG_W16(REG_BSSID2 + 4, bssid_addr_h);
|
||||
offset = REG_BSSID2;
|
||||
break;
|
||||
case HALMAC_PORTID3:
|
||||
HALMAC_REG_W32(REG_BSSID3, bssid_addr_l);
|
||||
HALMAC_REG_W16(REG_BSSID3 + 4, bssid_addr_h);
|
||||
offset = REG_BSSID3;
|
||||
break;
|
||||
case HALMAC_PORTID4:
|
||||
HALMAC_REG_W32(REG_BSSID4, bssid_addr_l);
|
||||
HALMAC_REG_W16(REG_BSSID4 + 4, bssid_addr_h);
|
||||
offset = REG_BSSID4;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
return HALMAC_RET_PORT_NOT_SUPPORT;
|
||||
}
|
||||
|
||||
HALMAC_REG_W32(offset, rtk_le32_to_cpu(addr->addr_l_h.low));
|
||||
HALMAC_REG_W16(offset + 4, rtk_le16_to_cpu(addr->addr_l_h.high));
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
@@ -158,8 +145,7 @@ enum halmac_ret_status
|
||||
cfg_transmitter_addr_88xx(struct halmac_adapter *adapter, u8 port,
|
||||
union halmac_wlan_addr *addr)
|
||||
{
|
||||
u16 mac_addr_h;
|
||||
u32 mac_addr_l;
|
||||
u32 offset;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
@@ -169,37 +155,29 @@ cfg_transmitter_addr_88xx(struct halmac_adapter *adapter, u8 port,
|
||||
return HALMAC_RET_PORT_NOT_SUPPORT;
|
||||
}
|
||||
|
||||
mac_addr_l = addr->addr_l_h.low;
|
||||
mac_addr_h = addr->addr_l_h.high;
|
||||
|
||||
mac_addr_l = rtk_le32_to_cpu(mac_addr_l);
|
||||
mac_addr_h = rtk_le16_to_cpu(mac_addr_h);
|
||||
|
||||
switch (port) {
|
||||
case HALMAC_PORTID0:
|
||||
HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_0, mac_addr_l);
|
||||
HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_0 + 4, mac_addr_h);
|
||||
offset = REG_TRANSMIT_ADDRSS_0;
|
||||
break;
|
||||
case HALMAC_PORTID1:
|
||||
HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_1, mac_addr_l);
|
||||
HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_1 + 4, mac_addr_h);
|
||||
offset = REG_TRANSMIT_ADDRSS_1;
|
||||
break;
|
||||
case HALMAC_PORTID2:
|
||||
HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_2, mac_addr_l);
|
||||
HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_2 + 4, mac_addr_h);
|
||||
offset = REG_TRANSMIT_ADDRSS_2;
|
||||
break;
|
||||
case HALMAC_PORTID3:
|
||||
HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_3, mac_addr_l);
|
||||
HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_3 + 4, mac_addr_h);
|
||||
offset = REG_TRANSMIT_ADDRSS_3;
|
||||
break;
|
||||
case HALMAC_PORTID4:
|
||||
HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_4, mac_addr_l);
|
||||
HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_4 + 4, mac_addr_h);
|
||||
offset = REG_TRANSMIT_ADDRSS_4;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
return HALMAC_RET_PORT_NOT_SUPPORT;
|
||||
}
|
||||
|
||||
HALMAC_REG_W32(offset, rtk_le32_to_cpu(addr->addr_l_h.low));
|
||||
HALMAC_REG_W16(offset + 4, rtk_le16_to_cpu(addr->addr_l_h.high));
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
@@ -380,48 +358,43 @@ rw_bcn_ctrl_88xx(struct halmac_adapter *adapter, u8 port, u8 write_en,
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
if (write_en) {
|
||||
if (ctrl->dis_rx_bssid_fit == _TRUE)
|
||||
if (ctrl->dis_rx_bssid_fit == 1)
|
||||
ctrl_value |= BIT_DIS_RX_BSSID_FIT;
|
||||
|
||||
if (ctrl->en_txbcn_rpt == _TRUE)
|
||||
if (ctrl->en_txbcn_rpt == 1)
|
||||
ctrl_value |= BIT_P0_EN_TXBCN_RPT;
|
||||
|
||||
if (ctrl->dis_tsf_udt == _TRUE)
|
||||
if (ctrl->dis_tsf_udt == 1)
|
||||
ctrl_value |= BIT_DIS_TSF_UDT;
|
||||
|
||||
if (ctrl->en_bcn == _TRUE)
|
||||
if (ctrl->en_bcn == 1)
|
||||
ctrl_value |= BIT_EN_BCN_FUNCTION;
|
||||
|
||||
if (ctrl->en_rxbcn_rpt == _TRUE)
|
||||
if (ctrl->en_rxbcn_rpt == 1)
|
||||
ctrl_value |= BIT_P0_EN_RXBCN_RPT;
|
||||
|
||||
if (ctrl->en_p2p_ctwin == _TRUE)
|
||||
if (ctrl->en_p2p_ctwin == 1)
|
||||
ctrl_value |= BIT_EN_P2P_CTWINDOW;
|
||||
|
||||
if (ctrl->en_p2p_bcn_area == _TRUE)
|
||||
if (ctrl->en_p2p_bcn_area == 1)
|
||||
ctrl_value |= BIT_EN_P2P_BCNQ_AREA;
|
||||
|
||||
switch (port) {
|
||||
case HALMAC_PORTID0:
|
||||
HALMAC_REG_W8(REG_BCN_CTRL, ctrl_value);
|
||||
break;
|
||||
|
||||
case HALMAC_PORTID1:
|
||||
HALMAC_REG_W8(REG_BCN_CTRL_CLINT0, ctrl_value);
|
||||
break;
|
||||
|
||||
case HALMAC_PORTID2:
|
||||
HALMAC_REG_W8(REG_BCN_CTRL_CLINT1, ctrl_value);
|
||||
break;
|
||||
|
||||
case HALMAC_PORTID3:
|
||||
HALMAC_REG_W8(REG_BCN_CTRL_CLINT2, ctrl_value);
|
||||
break;
|
||||
|
||||
case HALMAC_PORTID4:
|
||||
HALMAC_REG_W8(REG_BCN_CTRL_CLINT3, ctrl_value);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
@@ -431,61 +404,56 @@ rw_bcn_ctrl_88xx(struct halmac_adapter *adapter, u8 port, u8 write_en,
|
||||
case HALMAC_PORTID0:
|
||||
ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL);
|
||||
break;
|
||||
|
||||
case HALMAC_PORTID1:
|
||||
ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT0);
|
||||
break;
|
||||
|
||||
case HALMAC_PORTID2:
|
||||
ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT1);
|
||||
break;
|
||||
|
||||
case HALMAC_PORTID3:
|
||||
ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT2);
|
||||
break;
|
||||
|
||||
case HALMAC_PORTID4:
|
||||
ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT3);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (ctrl_value & BIT_EN_P2P_BCNQ_AREA)
|
||||
ctrl->en_p2p_bcn_area = _TRUE;
|
||||
ctrl->en_p2p_bcn_area = 1;
|
||||
else
|
||||
ctrl->en_p2p_bcn_area = _FALSE;
|
||||
ctrl->en_p2p_bcn_area = 0;
|
||||
|
||||
if (ctrl_value & BIT_EN_P2P_CTWINDOW)
|
||||
ctrl->en_p2p_ctwin = _TRUE;
|
||||
ctrl->en_p2p_ctwin = 1;
|
||||
else
|
||||
ctrl->en_p2p_ctwin = _FALSE;
|
||||
ctrl->en_p2p_ctwin = 0;
|
||||
|
||||
if (ctrl_value & BIT_P0_EN_RXBCN_RPT)
|
||||
ctrl->en_rxbcn_rpt = _TRUE;
|
||||
ctrl->en_rxbcn_rpt = 1;
|
||||
else
|
||||
ctrl->en_rxbcn_rpt = _FALSE;
|
||||
ctrl->en_rxbcn_rpt = 0;
|
||||
|
||||
if (ctrl_value & BIT_EN_BCN_FUNCTION)
|
||||
ctrl->en_bcn = _TRUE;
|
||||
ctrl->en_bcn = 1;
|
||||
else
|
||||
ctrl->en_bcn = _FALSE;
|
||||
ctrl->en_bcn = 0;
|
||||
|
||||
if (ctrl_value & BIT_DIS_TSF_UDT)
|
||||
ctrl->dis_tsf_udt = _TRUE;
|
||||
ctrl->dis_tsf_udt = 1;
|
||||
else
|
||||
ctrl->dis_tsf_udt = _FALSE;
|
||||
ctrl->dis_tsf_udt = 0;
|
||||
|
||||
if (ctrl_value & BIT_P0_EN_TXBCN_RPT)
|
||||
ctrl->en_txbcn_rpt = _TRUE;
|
||||
ctrl->en_txbcn_rpt = 1;
|
||||
else
|
||||
ctrl->en_txbcn_rpt = _FALSE;
|
||||
ctrl->en_txbcn_rpt = 0;
|
||||
|
||||
if (ctrl_value & BIT_DIS_RX_BSSID_FIT)
|
||||
ctrl->dis_rx_bssid_fit = _TRUE;
|
||||
ctrl->dis_rx_bssid_fit = 1;
|
||||
else
|
||||
ctrl->dis_rx_bssid_fit = _FALSE;
|
||||
ctrl->dis_rx_bssid_fit = 0;
|
||||
}
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
@@ -505,20 +473,12 @@ enum halmac_ret_status
|
||||
cfg_multicast_addr_88xx(struct halmac_adapter *adapter,
|
||||
union halmac_wlan_addr *addr)
|
||||
{
|
||||
u16 addr_h;
|
||||
u32 addr_l;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
addr_l = addr->addr_l_h.low;
|
||||
addr_h = addr->addr_l_h.high;
|
||||
|
||||
addr_l = rtk_le32_to_cpu(addr_l);
|
||||
addr_h = rtk_le16_to_cpu(addr_h);
|
||||
|
||||
HALMAC_REG_W32(REG_MAR, addr_l);
|
||||
HALMAC_REG_W16(REG_MAR + 4, addr_h);
|
||||
HALMAC_REG_W32(REG_MAR, rtk_le32_to_cpu(addr->addr_l_h.low));
|
||||
HALMAC_REG_W16(REG_MAR + 4, rtk_le16_to_cpu(addr->addr_l_h.high));
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
@@ -628,10 +588,10 @@ cfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw)
|
||||
|
||||
switch (bw) {
|
||||
case HALMAC_BW_80:
|
||||
value32 = value32 | BIT(7);
|
||||
value32 |= BIT(8);
|
||||
break;
|
||||
case HALMAC_BW_40:
|
||||
value32 = value32 | BIT(8);
|
||||
value32 |= BIT(7);
|
||||
break;
|
||||
case HALMAC_BW_20:
|
||||
case HALMAC_BW_10:
|
||||
@@ -643,13 +603,7 @@ cfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw)
|
||||
|
||||
HALMAC_REG_W32(REG_WMAC_TRXPTCL_CTL, value32);
|
||||
|
||||
/* TODO:Move to change mac clk api later... */
|
||||
value32 = HALMAC_REG_R32(REG_AFE_CTRL1) & ~(BIT(20) | BIT(21));
|
||||
value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL);
|
||||
HALMAC_REG_W32(REG_AFE_CTRL1, value32);
|
||||
|
||||
HALMAC_REG_W8(REG_USTIME_TSF, MAC_CLK_SPEED);
|
||||
HALMAC_REG_W8(REG_USTIME_EDCA, MAC_CLK_SPEED);
|
||||
cfg_mac_clk_88xx(adapter);
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
@@ -657,13 +611,38 @@ cfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw)
|
||||
}
|
||||
|
||||
void
|
||||
enable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable)
|
||||
cfg_txfifo_lt_88xx(struct halmac_adapter *adapter,
|
||||
struct halmac_txfifo_lifetime_cfg *cfg)
|
||||
{
|
||||
u8 value8;
|
||||
u32 value32;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
if (cfg->enable == 1) {
|
||||
value8 = HALMAC_REG_R8(REG_LIFETIME_EN);
|
||||
value8 = value8 | BIT(0) | BIT(1) | BIT(2) | BIT(3);
|
||||
HALMAC_REG_W8(REG_LIFETIME_EN, value8);
|
||||
|
||||
value32 = (cfg->lifetime) >> 8;
|
||||
value32 = value32 + (value32 << 16);
|
||||
HALMAC_REG_W32(REG_PKT_LIFE_TIME, value32);
|
||||
} else {
|
||||
value8 = HALMAC_REG_R8(REG_LIFETIME_EN);
|
||||
value8 = value8 & (~(BIT(0) | BIT(1) | BIT(2) | BIT(3)));
|
||||
HALMAC_REG_W8(REG_LIFETIME_EN, value8);
|
||||
}
|
||||
}
|
||||
|
||||
enum halmac_ret_status
|
||||
enable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable)
|
||||
{
|
||||
u8 value8;
|
||||
u32 value32;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
if (enable == 1) {
|
||||
status = board_rf_fine_tune_88xx(adapter);
|
||||
value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN);
|
||||
value8 = value8 | BIT(0) | BIT(1);
|
||||
HALMAC_REG_W8(REG_SYS_FUNC_EN, value8);
|
||||
@@ -688,6 +667,59 @@ enable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable)
|
||||
value32 = value32 & (~(BIT(24) | BIT(25) | BIT(26)));
|
||||
HALMAC_REG_W32(REG_WLRF1, value32);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static enum halmac_ret_status
|
||||
board_rf_fine_tune_88xx(struct halmac_adapter *adapter)
|
||||
{
|
||||
u8 *map = NULL;
|
||||
u32 size = adapter->hw_cfg_info.eeprom_size;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
if (adapter->chip_id == HALMAC_CHIP_ID_8822B) {
|
||||
if (!adapter->efuse_map_valid || !adapter->efuse_map) {
|
||||
PLTFM_MSG_ERR("[ERR]efuse map invalid!!\n");
|
||||
return HALMAC_RET_EFUSE_R_FAIL;
|
||||
}
|
||||
|
||||
map = (u8 *)PLTFM_MALLOC(size);
|
||||
if (!map) {
|
||||
PLTFM_MSG_ERR("[ERR]malloc map\n");
|
||||
return HALMAC_RET_MALLOC_FAIL;
|
||||
}
|
||||
|
||||
PLTFM_MEMSET(map, 0xFF, size);
|
||||
|
||||
if (eeprom_parser_88xx(adapter, adapter->efuse_map, map) !=
|
||||
HALMAC_RET_SUCCESS) {
|
||||
PLTFM_FREE(map, size);
|
||||
return HALMAC_RET_EEPROM_PARSING_FAIL;
|
||||
}
|
||||
|
||||
/* Fine-tune XTAL voltage for 2L PCB board */
|
||||
if (*(map + EFUSE_PCB_INFO_OFFSET) == 0x0C)
|
||||
HALMAC_REG_W8_SET(REG_AFE_CTRL1 + 1, BIT(1));
|
||||
|
||||
PLTFM_FREE(map, size);
|
||||
}
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
void
|
||||
cfg_mac_clk_88xx(struct halmac_adapter *adapter)
|
||||
{
|
||||
u32 value32;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
value32 = HALMAC_REG_R32(REG_AFE_CTRL1) & ~(BIT(20) | BIT(21));
|
||||
value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL);
|
||||
HALMAC_REG_W32(REG_AFE_CTRL1, value32);
|
||||
|
||||
HALMAC_REG_W8(REG_USTIME_TSF, MAC_CLK_SPEED);
|
||||
HALMAC_REG_W8(REG_USTIME_EDCA, MAC_CLK_SPEED);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -753,11 +785,10 @@ config_security_88xx(struct halmac_adapter *adapter,
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
HALMAC_REG_W16(REG_CR, (u16)(HALMAC_REG_R16(REG_CR) | BIT_MAC_SEC_EN));
|
||||
HALMAC_REG_W16_SET(REG_CR, BIT_MAC_SEC_EN);
|
||||
|
||||
if (setting->compare_keyid == 1) {
|
||||
sec_cfg = HALMAC_REG_R8(REG_SECCFG + 1) | BIT(0);
|
||||
HALMAC_REG_W8(REG_SECCFG + 1, sec_cfg);
|
||||
HALMAC_REG_W8_SET(REG_SECCFG + 1, BIT(0));
|
||||
adapter->hw_cfg_info.chk_security_keyid = 1;
|
||||
} else {
|
||||
adapter->hw_cfg_info.chk_security_keyid = 0;
|
||||
@@ -784,7 +815,7 @@ config_security_88xx(struct halmac_adapter *adapter,
|
||||
if (setting->bip_enable == 1) {
|
||||
if (adapter->chip_id == HALMAC_CHIP_ID_8822B)
|
||||
return HALMAC_RET_BIP_NO_SUPPORT;
|
||||
#if HALMAC_8821C_SUPPORT
|
||||
#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
sec_cfg = HALMAC_REG_R8(REG_WSEC_OPTION + 2);
|
||||
|
||||
if (setting->tx_encryption == 1)
|
||||
@@ -1054,7 +1085,7 @@ rx_clk_gate_88xx(struct halmac_adapter *adapter, u8 enable)
|
||||
|
||||
value8 = HALMAC_REG_R8(REG_RCR + 2);
|
||||
|
||||
if (enable == _TRUE)
|
||||
if (enable == 1)
|
||||
HALMAC_REG_W8(REG_RCR + 2, value8 & ~(BIT(3)));
|
||||
else
|
||||
HALMAC_REG_W8(REG_RCR + 2, value8 | BIT(3));
|
||||
@@ -1154,15 +1185,26 @@ get_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,
|
||||
return HALMAC_RET_PORT_NOT_SUPPORT;
|
||||
}
|
||||
|
||||
mac_addr_l = rtk_le32_to_cpu(mac_addr_l);
|
||||
mac_addr_h = rtk_le16_to_cpu(mac_addr_h);
|
||||
|
||||
addr->addr_l_h.low = mac_addr_l;
|
||||
addr->addr_l_h.high = mac_addr_h;
|
||||
addr->addr_l_h.low = rtk_cpu_to_le32(mac_addr_l);
|
||||
addr->addr_l_h.high = rtk_cpu_to_le16(mac_addr_h);
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
void
|
||||
rts_full_bw_88xx(struct halmac_adapter *adapter, u8 enable)
|
||||
{
|
||||
u8 value8;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
value8 = HALMAC_REG_R8(REG_INIRTS_RATE_SEL);
|
||||
|
||||
if (enable == 1)
|
||||
HALMAC_REG_W8(REG_INIRTS_RATE_SEL, value8 | BIT(5));
|
||||
else
|
||||
HALMAC_REG_W8(REG_INIRTS_RATE_SEL, value8 & ~(BIT(5)));
|
||||
}
|
||||
|
||||
#endif /* HALMAC_88XX_SUPPORT */
|
||||
|
||||
@@ -68,6 +68,10 @@ enum halmac_ret_status
|
||||
cfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw);
|
||||
|
||||
void
|
||||
cfg_txfifo_lt_88xx(struct halmac_adapter *adapter,
|
||||
struct halmac_txfifo_lifetime_cfg *cfg);
|
||||
|
||||
enum halmac_ret_status
|
||||
enable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable);
|
||||
|
||||
enum halmac_ret_status
|
||||
@@ -118,6 +122,12 @@ enum halmac_ret_status
|
||||
get_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,
|
||||
union halmac_wlan_addr *addr);
|
||||
|
||||
void
|
||||
rts_full_bw_88xx(struct halmac_adapter *adapter, u8 enable);
|
||||
|
||||
void
|
||||
cfg_mac_clk_88xx(struct halmac_adapter *adapter);
|
||||
|
||||
#endif/* HALMAC_88XX_SUPPORT */
|
||||
|
||||
#endif/* _HALMAC_CFG_WMAC_88XX_H_ */
|
||||
|
||||
@@ -19,9 +19,15 @@
|
||||
#include "halmac_cfg_wmac_88xx.h"
|
||||
#include "halmac_efuse_88xx.h"
|
||||
#include "halmac_bb_rf_88xx.h"
|
||||
#if HALMAC_USB_SUPPORT
|
||||
#include "halmac_usb_88xx.h"
|
||||
#endif
|
||||
#if HALMAC_SDIO_SUPPORT
|
||||
#include "halmac_sdio_88xx.h"
|
||||
#endif
|
||||
#if HALMAC_PCIE_SUPPORT
|
||||
#include "halmac_pcie_88xx.h"
|
||||
#endif
|
||||
#include "halmac_mimo_88xx.h"
|
||||
|
||||
#if HALMAC_88XX_SUPPORT
|
||||
@@ -202,6 +208,14 @@ wlhdr_data_valid_88xx(struct halmac_adapter *adapter,
|
||||
static void
|
||||
dump_reg_88xx(struct halmac_adapter *adapter);
|
||||
|
||||
static u8
|
||||
packet_in_nlo_88xx(struct halmac_adapter *adapter,
|
||||
enum halmac_packet_id pkt_id);
|
||||
|
||||
static enum halmac_packet_id
|
||||
get_real_pkt_id_88xx(struct halmac_adapter *adapter,
|
||||
enum halmac_packet_id pkt_id);
|
||||
|
||||
/**
|
||||
* ofld_func_cfg_88xx() - config offload function
|
||||
* @adapter : the adapter of halmac
|
||||
@@ -301,7 +315,7 @@ dl_rsvd_page_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *buf,
|
||||
value8 = (u8)(value8 & ~(BIT(6)));
|
||||
HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8);
|
||||
|
||||
if (PLTFM_SEND_RSVD_PAGE(buf, size) == _FALSE) {
|
||||
if (PLTFM_SEND_RSVD_PAGE(buf, size) == 0) {
|
||||
PLTFM_MSG_ERR("[ERR]send rvsd pg(pltfm)!!\n");
|
||||
status = HALMAC_RET_DL_RSVD_PAGE_FAIL;
|
||||
goto DL_RSVD_PG_END;
|
||||
@@ -455,8 +469,9 @@ enum halmac_ret_status
|
||||
set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
|
||||
void *value)
|
||||
{
|
||||
enum halmac_ret_status status;
|
||||
struct halmac_tx_page_threshold_info *tx_th_info;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
struct halmac_tx_page_threshold_info *th_info = NULL;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
@@ -466,12 +481,14 @@ set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
|
||||
}
|
||||
|
||||
switch (hw_id) {
|
||||
#if HALMAC_USB_SUPPORT
|
||||
case HALMAC_HW_USB_MODE:
|
||||
status = set_usb_mode_88xx(adapter,
|
||||
*(enum halmac_usb_mode *)value);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
break;
|
||||
#endif
|
||||
case HALMAC_HW_BANDWIDTH:
|
||||
cfg_bw_88xx(adapter, *(enum halmac_bw *)value);
|
||||
break;
|
||||
@@ -482,12 +499,20 @@ set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
|
||||
cfg_pri_ch_idx_88xx(adapter, *(enum halmac_pri_ch_idx *)value);
|
||||
break;
|
||||
case HALMAC_HW_EN_BB_RF:
|
||||
enable_bb_rf_88xx(adapter, *(u8 *)value);
|
||||
status = enable_bb_rf_88xx(adapter, *(u8 *)value);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
break;
|
||||
#if HALMAC_SDIO_SUPPORT
|
||||
case HALMAC_HW_SDIO_TX_PAGE_THRESHOLD:
|
||||
tx_th_info = (struct halmac_tx_page_threshold_info *)value;
|
||||
cfg_sdio_tx_page_threshold_88xx(adapter, tx_th_info);
|
||||
if (adapter->intf == HALMAC_INTERFACE_SDIO) {
|
||||
th_info = (struct halmac_tx_page_threshold_info *)value;
|
||||
cfg_sdio_tx_page_threshold_88xx(adapter, th_info);
|
||||
} else {
|
||||
return HALMAC_RET_FAIL;
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
case HALMAC_HW_RX_SHIFT:
|
||||
rx_shift_88xx(adapter, *(u8 *)value);
|
||||
break;
|
||||
@@ -501,6 +526,15 @@ set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
|
||||
fast_edca_cfg_88xx(adapter,
|
||||
(struct halmac_fast_edca_cfg *)value);
|
||||
break;
|
||||
case HALMAC_HW_RTS_FULL_BW:
|
||||
rts_full_bw_88xx(adapter, *(u8 *)value);
|
||||
break;
|
||||
case HALMAC_HW_FREE_CNT_EN:
|
||||
HALMAC_REG_W8_SET(REG_MISC_CTRL, BIT_EN_FREECNT);
|
||||
break;
|
||||
case HALMAC_HW_TXFIFO_LIFETIME:
|
||||
cfg_txfifo_lt_88xx(adapter,
|
||||
(struct halmac_txfifo_lifetime_cfg *)value);
|
||||
default:
|
||||
return HALMAC_RET_PARA_NOT_SUPPORT;
|
||||
}
|
||||
@@ -531,8 +565,8 @@ set_h2c_pkt_hdr_88xx(struct halmac_adapter *adapter, u8 *hdr,
|
||||
(adapter->h2c_info.seq_num)++;
|
||||
PLTFM_MUTEX_UNLOCK(&adapter->h2c_seq_mutex);
|
||||
|
||||
if (info->ack == _TRUE)
|
||||
FW_OFFLOAD_H2C_SET_ACK(hdr, _TRUE);
|
||||
if (info->ack == 1)
|
||||
FW_OFFLOAD_H2C_SET_ACK(hdr, 1);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
@@ -554,7 +588,7 @@ send_h2c_pkt_88xx(struct halmac_adapter *adapter, u8 *pkt)
|
||||
|
||||
cnt = 100;
|
||||
do {
|
||||
if (PLTFM_SEND_H2C_PKT(pkt, H2C_PKT_SIZE_88XX) == _TRUE)
|
||||
if (PLTFM_SEND_H2C_PKT(pkt, H2C_PKT_SIZE_88XX) == 1)
|
||||
break;
|
||||
cnt--;
|
||||
if (cnt == 0) {
|
||||
@@ -578,8 +612,8 @@ get_h2c_buf_free_space_88xx(struct halmac_adapter *adapter)
|
||||
struct halmac_h2c_info *info = &adapter->h2c_info;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
hw_wptr = HALMAC_REG_R32(REG_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_WR_ADDR;
|
||||
fw_rptr = HALMAC_REG_R32(REG_H2C_PKT_READADDR) & BIT_MASK_H2C_READ_ADDR;
|
||||
hw_wptr = HALMAC_REG_R32(REG_H2C_PKT_WRITEADDR) & 0x3FFFF;
|
||||
fw_rptr = HALMAC_REG_R32(REG_H2C_PKT_READADDR) & 0x3FFFF;
|
||||
|
||||
if (hw_wptr >= fw_rptr)
|
||||
info->buf_fs = info->buf_size - (hw_wptr - fw_rptr);
|
||||
@@ -594,6 +628,9 @@ get_h2c_buf_free_space_88xx(struct halmac_adapter *adapter)
|
||||
* @adapter : the adapter of halmac
|
||||
* @buf : RX Packet pointer
|
||||
* @size : RX Packet size
|
||||
*
|
||||
* Note : Don't use any IO or DELAY in this API
|
||||
*
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
*
|
||||
* Used to process c2h packet info from RX path. After receiving the packet,
|
||||
@@ -607,7 +644,7 @@ get_c2h_info_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
|
||||
{
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
if (GET_RX_DESC_C2H(buf) == _TRUE) {
|
||||
if (GET_RX_DESC_C2H(buf) == 1) {
|
||||
PLTFM_MSG_TRACE("[TRACE]Parse c2h pkt\n");
|
||||
|
||||
status = parse_c2h_pkt_88xx(adapter, buf, size);
|
||||
@@ -623,7 +660,8 @@ get_c2h_info_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
|
||||
static enum halmac_ret_status
|
||||
parse_c2h_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
|
||||
{
|
||||
u8 cmd_id, sub_cmd_id;
|
||||
u8 cmd_id;
|
||||
u8 sub_cmd_id;
|
||||
u8 *c2h_pkt = buf + adapter->hw_cfg_info.rxdesc_size;
|
||||
u32 c2h_size = size - adapter->hw_cfg_info.rxdesc_size;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
@@ -732,7 +770,8 @@ _ENDFOUND:
|
||||
static enum halmac_ret_status
|
||||
get_h2c_ack_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
|
||||
{
|
||||
u8 cmd_id, sub_cmd_id;
|
||||
u8 cmd_id;
|
||||
u8 sub_cmd_id;
|
||||
u8 fw_rc;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
@@ -960,11 +999,10 @@ get_h2c_ack_ch_switch_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
|
||||
}
|
||||
|
||||
/**
|
||||
* mac_debug_88xx() - dump debug information
|
||||
* @adapter : the adapter of halmac
|
||||
* mac_debug_88xx_v1() - read some registers for debug
|
||||
* @adapter
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
mac_debug_88xx(struct halmac_adapter *adapter)
|
||||
@@ -1054,7 +1092,7 @@ dump_reg_88xx(struct halmac_adapter *adapter)
|
||||
* @info : cmd id, content
|
||||
* @full_fifo : parameter information
|
||||
*
|
||||
* If msk_en = _TRUE, the format of array is {reg_info, mask, value}.
|
||||
* If msk_en = 1, the format of array is {reg_info, mask, value}.
|
||||
* If msk_en =_FAUSE, the format of array is {reg_info, value}
|
||||
* The format of reg_info is
|
||||
* reg_info[31]=rf_reg, 0: MAC_BB reg, 1: RF reg
|
||||
@@ -1062,7 +1100,7 @@ dump_reg_88xx(struct halmac_adapter *adapter)
|
||||
* if rf_reg=0(MAC_BB reg), rf_path is meaningless.
|
||||
* ref_info[15:0]=offset
|
||||
*
|
||||
* Example: msk_en = _FALSE
|
||||
* Example: msk_en = 0
|
||||
* {0x8100000a, 0x00001122}
|
||||
* =>Set RF register, path_B, offset 0xA to 0x00001122
|
||||
* {0x00000824, 0x11224433}
|
||||
@@ -1124,7 +1162,7 @@ static enum halmac_ret_status
|
||||
proc_cfg_param_88xx(struct halmac_adapter *adapter,
|
||||
struct halmac_phy_parameter_info *param, u8 full_fifo)
|
||||
{
|
||||
u8 end_cmd = _FALSE;
|
||||
u8 end_cmd = 0;
|
||||
u32 rsvd_size;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
struct halmac_cfg_param_info *info = &adapter->cfg_param_info;
|
||||
@@ -1137,8 +1175,12 @@ proc_cfg_param_88xx(struct halmac_adapter *adapter,
|
||||
return status;
|
||||
|
||||
if (cnv_cfg_param_state_88xx(adapter, HALMAC_CMD_CNSTR_CNSTR) !=
|
||||
HALMAC_RET_SUCCESS)
|
||||
HALMAC_RET_SUCCESS) {
|
||||
PLTFM_FREE(info->buf, info->buf_size);
|
||||
info->buf = NULL;
|
||||
info->buf_wptr = NULL;
|
||||
return HALMAC_RET_ERROR_STATE;
|
||||
}
|
||||
|
||||
add_param_buf_88xx(adapter, param, info->buf_wptr, &end_cmd);
|
||||
if (param->cmd_id != HALMAC_PARAMETER_CMD_END) {
|
||||
@@ -1148,7 +1190,7 @@ proc_cfg_param_88xx(struct halmac_adapter *adapter,
|
||||
}
|
||||
|
||||
rsvd_size = info->avl_buf_size - adapter->hw_cfg_info.txdesc_size;
|
||||
if (rsvd_size > CFG_PARAM_H2C_INFO_SIZE && end_cmd == _FALSE)
|
||||
if (rsvd_size > CFG_PARAM_H2C_INFO_SIZE && end_cmd == 0)
|
||||
return HALMAC_RET_SUCCESS;
|
||||
|
||||
if (info->num == 0) {
|
||||
@@ -1166,10 +1208,16 @@ proc_cfg_param_88xx(struct halmac_adapter *adapter,
|
||||
}
|
||||
|
||||
status = send_cfg_param_h2c_88xx(adapter);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
if (info->buf) {
|
||||
PLTFM_FREE(info->buf, info->buf_size);
|
||||
info->buf = NULL;
|
||||
info->buf_wptr = NULL;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
if (end_cmd == _FALSE) {
|
||||
if (end_cmd == 0) {
|
||||
PLTFM_MSG_TRACE("[TRACE]send h2c-buf full\n");
|
||||
return HALMAC_RET_PARA_SENDING;
|
||||
}
|
||||
@@ -1197,7 +1245,7 @@ send_cfg_param_h2c_88xx(struct halmac_adapter *adapter)
|
||||
|
||||
*proc_status = HALMAC_CMD_PROCESS_SENDING;
|
||||
|
||||
if (info->full_fifo_mode == _TRUE)
|
||||
if (info->full_fifo_mode == 1)
|
||||
pg_addr = 0;
|
||||
else
|
||||
pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
|
||||
@@ -1214,7 +1262,7 @@ send_cfg_param_h2c_88xx(struct halmac_adapter *adapter)
|
||||
|
||||
hdr_info.sub_cmd_id = SUB_CMD_ID_CFG_PARAM;
|
||||
hdr_info.content_size = 4;
|
||||
hdr_info.ack = _TRUE;
|
||||
hdr_info.ack = 1;
|
||||
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
|
||||
|
||||
adapter->halmac_state.cfg_param_state.seq_num = seq_num;
|
||||
@@ -1276,7 +1324,7 @@ add_param_buf_88xx(struct halmac_adapter *adapter,
|
||||
struct halmac_cfg_param_info *info = &adapter->cfg_param_info;
|
||||
union halmac_parameter_content *content = ¶m->content;
|
||||
|
||||
*end_cmd = _FALSE;
|
||||
*end_cmd = 0;
|
||||
|
||||
PARAM_INFO_SET_LEN(buf, CFG_PARAM_H2C_INFO_SIZE);
|
||||
PARAM_INFO_SET_IO_CMD(buf, param->cmd_id);
|
||||
@@ -1311,7 +1359,7 @@ add_param_buf_88xx(struct halmac_adapter *adapter,
|
||||
PARAM_INFO_SET_DELAY_VAL(buf, content->DELAY_TIME.delay_time);
|
||||
break;
|
||||
case HALMAC_PARAMETER_CMD_END:
|
||||
*end_cmd = _TRUE;
|
||||
*end_cmd = 1;
|
||||
break;
|
||||
default:
|
||||
PLTFM_MSG_ERR("[ERR]cmd id!!\n");
|
||||
@@ -1330,7 +1378,7 @@ gen_cfg_param_h2c_88xx(struct halmac_adapter *adapter, u8 *buff)
|
||||
|
||||
CFG_PARAM_SET_NUM(buff, info->num);
|
||||
|
||||
if (info->full_fifo_mode == _TRUE) {
|
||||
if (info->full_fifo_mode == 1) {
|
||||
CFG_PARAM_SET_INIT_CASE(buff, 0x1);
|
||||
CFG_PARAM_SET_LOC(buff, 0);
|
||||
} else {
|
||||
@@ -1350,7 +1398,7 @@ malloc_cfg_param_buf_88xx(struct halmac_adapter *adapter, u8 full_fifo)
|
||||
if (info->buf)
|
||||
return HALMAC_RET_SUCCESS;
|
||||
|
||||
if (full_fifo == _TRUE)
|
||||
if (full_fifo == 1)
|
||||
info->buf_size = pltfm_info->malloc_size;
|
||||
else
|
||||
info->buf_size = CFG_PARAM_RSVDPG_SIZE;
|
||||
@@ -1420,6 +1468,11 @@ update_packet_88xx(struct halmac_adapter *adapter, enum halmac_packet_id pkt_id,
|
||||
return status;
|
||||
}
|
||||
|
||||
if (packet_in_nlo_88xx(adapter, pkt_id)) {
|
||||
*proc_status = HALMAC_CMD_PROCESS_DONE;
|
||||
adapter->nlo_flag = 1;
|
||||
}
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
@@ -1435,6 +1488,7 @@ send_h2c_update_packet_88xx(struct halmac_adapter *adapter,
|
||||
u16 pg_offset;
|
||||
struct halmac_h2c_header_info hdr_info;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
enum halmac_packet_id real_pkt_id;
|
||||
|
||||
status = dl_rsvd_page_88xx(adapter, pg_addr, pkt, size);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
@@ -1442,14 +1496,18 @@ send_h2c_update_packet_88xx(struct halmac_adapter *adapter,
|
||||
return status;
|
||||
}
|
||||
|
||||
real_pkt_id = get_real_pkt_id_88xx(adapter, pkt_id);
|
||||
pg_offset = pg_addr - adapter->txff_alloc.rsvd_boundary;
|
||||
UPDATE_PKT_SET_SIZE(h2c_buf, size + adapter->hw_cfg_info.txdesc_size);
|
||||
UPDATE_PKT_SET_ID(h2c_buf, pkt_id);
|
||||
UPDATE_PKT_SET_ID(h2c_buf, real_pkt_id);
|
||||
UPDATE_PKT_SET_LOC(h2c_buf, pg_offset);
|
||||
|
||||
hdr_info.sub_cmd_id = SUB_CMD_ID_UPDATE_PKT;
|
||||
hdr_info.content_size = 8;
|
||||
hdr_info.ack = _TRUE;
|
||||
if (packet_in_nlo_88xx(adapter, pkt_id))
|
||||
hdr_info.ack = 0;
|
||||
else
|
||||
hdr_info.ack = 1;
|
||||
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
|
||||
adapter->halmac_state.update_pkt_state.seq_num = seq_num;
|
||||
|
||||
@@ -1583,7 +1641,7 @@ dump_fifo_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel,
|
||||
return HALMAC_RET_NULL_POINTER;
|
||||
|
||||
tmp8 = HALMAC_REG_R8(REG_RCR + 2);
|
||||
enable = _FALSE;
|
||||
enable = 0;
|
||||
status = api->halmac_set_hw_value(adapter, HALMAC_HW_RX_CLK_GATE,
|
||||
&enable);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
@@ -1702,8 +1760,8 @@ set_h2c_header_88xx(struct halmac_adapter *adapter, u8 *hdr, u16 *seq, u8 ack)
|
||||
(adapter->h2c_info.seq_num)++;
|
||||
PLTFM_MUTEX_UNLOCK(&adapter->h2c_seq_mutex);
|
||||
|
||||
if (ack == _TRUE)
|
||||
H2C_CMD_HEADER_SET_ACK(hdr, _TRUE);
|
||||
if (ack == 1)
|
||||
H2C_CMD_HEADER_SET_ACK(hdr, 1);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
@@ -1898,7 +1956,7 @@ ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
if (opt->switch_en == _FALSE)
|
||||
if (opt->switch_en == 0)
|
||||
*proc_status = HALMAC_CMD_PROCESS_IDLE;
|
||||
|
||||
if ((*proc_status == HALMAC_CMD_PROCESS_SENDING) ||
|
||||
@@ -1908,7 +1966,7 @@ ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
|
||||
}
|
||||
|
||||
state = scan_cmd_cnstr_state_88xx(adapter);
|
||||
if (opt->switch_en == _TRUE) {
|
||||
if (opt->switch_en == 1) {
|
||||
if (state != HALMAC_CMD_CNSTR_CNSTR) {
|
||||
PLTFM_MSG_ERR("[ERR]state(en = 1)\n");
|
||||
return HALMAC_RET_ERROR_STATE;
|
||||
@@ -1946,6 +2004,9 @@ proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
if (opt->nlo_en == 1 && adapter->nlo_flag != 1)
|
||||
PLTFM_MSG_WARN("[WARN]probe req is NOT nlo pkt!!\n");
|
||||
|
||||
if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) !=
|
||||
HALMAC_RET_SUCCESS)
|
||||
return HALMAC_RET_ERROR_STATE;
|
||||
@@ -1981,7 +2042,10 @@ proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
|
||||
|
||||
hdr_info.sub_cmd_id = SUB_CMD_ID_CH_SWITCH;
|
||||
hdr_info.content_size = 20;
|
||||
hdr_info.ack = _TRUE;
|
||||
if (opt->nlo_en == 1)
|
||||
hdr_info.ack = 0;
|
||||
else
|
||||
hdr_info.ack = 1;
|
||||
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
|
||||
adapter->halmac_state.scan_state.seq_num = seq_num;
|
||||
|
||||
@@ -2004,6 +2068,8 @@ proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
|
||||
HALMAC_RET_SUCCESS)
|
||||
return HALMAC_RET_ERROR_STATE;
|
||||
|
||||
adapter->nlo_flag = 0;
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
@@ -2060,7 +2126,7 @@ chk_txdesc_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
if (GET_TX_DESC_BMC(buf) == _TRUE && GET_TX_DESC_AGG_EN(buf) == _TRUE)
|
||||
if (GET_TX_DESC_BMC(buf) == 1 && GET_TX_DESC_AGG_EN(buf) == 1)
|
||||
PLTFM_MSG_ERR("[ERR]txdesc - agg + bmc\n");
|
||||
|
||||
if (size < (GET_TX_DESC_TXPKTSIZE(buf) +
|
||||
@@ -2121,15 +2187,15 @@ wlhdr_valid_88xx(struct halmac_adapter *adapter, u8 *buf)
|
||||
|
||||
switch (wlhdr->type) {
|
||||
case WLHDR_TYPE_MGMT:
|
||||
if (wlhdr_mgmt_valid_88xx(adapter, wlhdr) != _TRUE)
|
||||
if (wlhdr_mgmt_valid_88xx(adapter, wlhdr) != 1)
|
||||
status = HALMAC_RET_WLHDR_FAIL;
|
||||
break;
|
||||
case WLHDR_TYPE_CTRL:
|
||||
if (wlhdr_ctrl_valid_88xx(adapter, wlhdr) != _TRUE)
|
||||
if (wlhdr_ctrl_valid_88xx(adapter, wlhdr) != 1)
|
||||
status = HALMAC_RET_WLHDR_FAIL;
|
||||
break;
|
||||
case WLHDR_TYPE_DATA:
|
||||
if (wlhdr_data_valid_88xx(adapter, wlhdr) != _TRUE)
|
||||
if (wlhdr_data_valid_88xx(adapter, wlhdr) != 1)
|
||||
status = HALMAC_RET_WLHDR_FAIL;
|
||||
break;
|
||||
default:
|
||||
@@ -2160,11 +2226,11 @@ wlhdr_mgmt_valid_88xx(struct halmac_adapter *adapter,
|
||||
case WLHDR_SUB_TYPE_DEAUTH:
|
||||
case WLHDR_SUB_TYPE_ACTION:
|
||||
case WLHDR_SUB_TYPE_ACTION_NOACK:
|
||||
state = _TRUE;
|
||||
state = 1;
|
||||
break;
|
||||
default:
|
||||
PLTFM_MSG_ERR("[ERR]mgmt invalid!!\n");
|
||||
state = _FALSE;
|
||||
state = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
@@ -2180,11 +2246,11 @@ wlhdr_ctrl_valid_88xx(struct halmac_adapter *adapter,
|
||||
switch (wlhdr->sub_type) {
|
||||
case WLHDR_SUB_TYPE_BF_RPT_POLL:
|
||||
case WLHDR_SUB_TYPE_NDPA:
|
||||
state = _TRUE;
|
||||
state = 1;
|
||||
break;
|
||||
default:
|
||||
PLTFM_MSG_ERR("[ERR]ctrl invalid!!\n");
|
||||
state = _FALSE;
|
||||
state = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
@@ -2202,11 +2268,11 @@ wlhdr_data_valid_88xx(struct halmac_adapter *adapter,
|
||||
case WLHDR_SUB_TYPE_NULL:
|
||||
case WLHDR_SUB_TYPE_QOS_DATA:
|
||||
case WLHDR_SUB_TYPE_QOS_NULL:
|
||||
state = _TRUE;
|
||||
state = 1;
|
||||
break;
|
||||
default:
|
||||
PLTFM_MSG_ERR("[ERR]data invalid!!\n");
|
||||
state = _FALSE;
|
||||
state = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
@@ -2214,7 +2280,7 @@ wlhdr_data_valid_88xx(struct halmac_adapter *adapter,
|
||||
}
|
||||
|
||||
/**
|
||||
* halmac_get_version() - get HALMAC version
|
||||
* get_version_88xx() - get HALMAC version
|
||||
* @ver : return version of major, prototype and minor information
|
||||
* Author : KaiYuan Chang / Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
@@ -2283,7 +2349,7 @@ proc_p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info)
|
||||
|
||||
hdr_info.sub_cmd_id = SUB_CMD_ID_P2PPS;
|
||||
hdr_info.content_size = 24;
|
||||
hdr_info.ack = _FALSE;
|
||||
hdr_info.ack = 0;
|
||||
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
|
||||
|
||||
status = send_h2c_pkt_88xx(adapter, h2c_buf);
|
||||
@@ -2424,6 +2490,9 @@ cfg_drv_rsvd_pg_num_88xx(struct halmac_adapter *adapter,
|
||||
case HALMAC_RSVD_PG_NUM128:
|
||||
adapter->txff_alloc.rsvd_drv_pg_num = 128;
|
||||
break;
|
||||
case HALMAC_RSVD_PG_NUM256:
|
||||
adapter->txff_alloc.rsvd_drv_pg_num = 256;
|
||||
break;
|
||||
}
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
@@ -2688,13 +2757,15 @@ parse_intf_phy_88xx(struct halmac_adapter *adapter,
|
||||
HALMAC_REG_W8((u32)offset, (u8)value);
|
||||
} else if (intf_phy == HAL_INTF_PHY_USB2 ||
|
||||
intf_phy == HAL_INTF_PHY_USB3) {
|
||||
#if HALMAC_USB_SUPPORT
|
||||
result = usbphy_write_88xx(adapter, (u8)offset,
|
||||
value, intf_phy);
|
||||
if (result != HALMAC_RET_SUCCESS)
|
||||
PLTFM_MSG_ERR("[ERR]usb phy!!\n");
|
||||
|
||||
#endif
|
||||
} else if (intf_phy == HAL_INTF_PHY_PCIE_GEN1 ||
|
||||
intf_phy == HAL_INTF_PHY_PCIE_GEN2) {
|
||||
#if HALMAC_PCIE_SUPPORT
|
||||
if (ip_sel == HALMAC_IP_INTF_PHY)
|
||||
result = mdio_write_88xx(adapter,
|
||||
(u8)offset,
|
||||
@@ -2705,7 +2776,7 @@ parse_intf_phy_88xx(struct halmac_adapter *adapter,
|
||||
(u8)value);
|
||||
if (result != HALMAC_RET_SUCCESS)
|
||||
PLTFM_MSG_ERR("[ERR]mdio/dbi!!\n");
|
||||
|
||||
#endif
|
||||
} else {
|
||||
PLTFM_MSG_ERR("[ERR]intf phy sel!!\n");
|
||||
}
|
||||
@@ -2855,4 +2926,41 @@ pwr_state_88xx(struct halmac_adapter *adapter, enum halmac_mac_power *state)
|
||||
*state = HALMAC_MAC_POWER_ON;
|
||||
}
|
||||
|
||||
static u8
|
||||
packet_in_nlo_88xx(struct halmac_adapter *adapter,
|
||||
enum halmac_packet_id pkt_id)
|
||||
{
|
||||
enum halmac_packet_id nlo_pkt = HALMAC_PACKET_PROBE_REQ_NLO;
|
||||
|
||||
if (pkt_id >= nlo_pkt)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
static enum halmac_packet_id
|
||||
get_real_pkt_id_88xx(struct halmac_adapter *adapter,
|
||||
enum halmac_packet_id pkt_id)
|
||||
{
|
||||
enum halmac_packet_id real_pkt_id;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
switch (pkt_id) {
|
||||
case HALMAC_PACKET_PROBE_REQ_NLO:
|
||||
real_pkt_id = HALMAC_PACKET_PROBE_REQ;
|
||||
break;
|
||||
case HALMAC_PACKET_SYNC_BCN_NLO:
|
||||
real_pkt_id = HALMAC_PACKET_SYNC_BCN;
|
||||
break;
|
||||
case HALMAC_PACKET_DISCOVERY_BCN_NLO:
|
||||
real_pkt_id = HALMAC_PACKET_DISCOVERY_BCN;
|
||||
break;
|
||||
default:
|
||||
real_pkt_id = pkt_id;
|
||||
}
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
return real_pkt_id;
|
||||
}
|
||||
|
||||
#endif /* HALMAC_88XX_SUPPORT */
|
||||
|
||||
@@ -22,7 +22,6 @@
|
||||
|
||||
#define RSVD_EFUSE_SIZE 16
|
||||
#define RSVD_CS_EFUSE_SIZE 24
|
||||
#define PROTECT_EFUSE_SIZE 96
|
||||
#define FEATURE_DUMP_PHY_EFUSE HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE
|
||||
#define FEATURE_DUMP_LOG_EFUSE HALMAC_FEATURE_DUMP_LOGICAL_EFUSE
|
||||
|
||||
@@ -37,9 +36,6 @@ static enum halmac_ret_status
|
||||
read_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
|
||||
u8 *map);
|
||||
|
||||
static enum halmac_ret_status
|
||||
eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map);
|
||||
|
||||
static enum halmac_ret_status
|
||||
read_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map);
|
||||
|
||||
@@ -98,6 +94,7 @@ dump_efuse_map_88xx(struct halmac_adapter *adapter,
|
||||
u8 *map = NULL;
|
||||
u8 *efuse_map;
|
||||
u32 efuse_size = adapter->hw_cfg_info.efuse_size;
|
||||
u32 prtct_efuse_size = adapter->hw_cfg_info.prtct_efuse_size;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
enum halmac_cmd_process_status *proc_status;
|
||||
|
||||
@@ -138,7 +135,7 @@ dump_efuse_map_88xx(struct halmac_adapter *adapter,
|
||||
return status;
|
||||
}
|
||||
|
||||
if (adapter->efuse_map_valid == _TRUE) {
|
||||
if (adapter->efuse_map_valid == 1) {
|
||||
*proc_status = HALMAC_CMD_PROCESS_DONE;
|
||||
efuse_map = adapter->efuse_map;
|
||||
|
||||
@@ -149,13 +146,17 @@ dump_efuse_map_88xx(struct halmac_adapter *adapter,
|
||||
}
|
||||
PLTFM_MEMSET(map, 0xFF, efuse_size);
|
||||
PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
|
||||
PLTFM_MEMCPY(map, efuse_map, efuse_size - PROTECT_EFUSE_SIZE);
|
||||
PLTFM_MEMCPY(map + efuse_size - PROTECT_EFUSE_SIZE +
|
||||
#if HALMAC_PLATFORM_WINDOWS
|
||||
PLTFM_MEMCPY(map, efuse_map, efuse_size);
|
||||
#else
|
||||
PLTFM_MEMCPY(map, efuse_map, efuse_size - prtct_efuse_size);
|
||||
PLTFM_MEMCPY(map + efuse_size - prtct_efuse_size +
|
||||
RSVD_CS_EFUSE_SIZE,
|
||||
efuse_map + efuse_size - PROTECT_EFUSE_SIZE +
|
||||
efuse_map + efuse_size - prtct_efuse_size +
|
||||
RSVD_CS_EFUSE_SIZE,
|
||||
PROTECT_EFUSE_SIZE - RSVD_EFUSE_SIZE -
|
||||
prtct_efuse_size - RSVD_EFUSE_SIZE -
|
||||
RSVD_CS_EFUSE_SIZE);
|
||||
#endif
|
||||
PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
|
||||
|
||||
PLTFM_EVENT_SIG(HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE,
|
||||
@@ -311,8 +312,9 @@ read_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value,
|
||||
enum halmac_efuse_bank bank)
|
||||
{
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
enum halmac_cmd_process_status *proc_status =
|
||||
&adapter->halmac_state.efuse_state.proc_status;
|
||||
enum halmac_cmd_process_status *proc_status;
|
||||
|
||||
proc_status = &adapter->halmac_state.efuse_state.proc_status;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
@@ -397,8 +399,8 @@ get_efuse_available_size_88xx(struct halmac_adapter *adapter, u32 *size)
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
|
||||
*size = adapter->hw_cfg_info.efuse_size - PROTECT_EFUSE_SIZE -
|
||||
adapter->efuse_end;
|
||||
*size = adapter->hw_cfg_info.efuse_size -
|
||||
adapter->hw_cfg_info.prtct_efuse_size - adapter->efuse_end;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
@@ -460,8 +462,9 @@ dump_log_efuse_map_88xx(struct halmac_adapter *adapter,
|
||||
u8 *map = NULL;
|
||||
u32 size = adapter->hw_cfg_info.eeprom_size;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
enum halmac_cmd_process_status *proc_status =
|
||||
&adapter->halmac_state.efuse_state.proc_status;
|
||||
enum halmac_cmd_process_status *proc_status;
|
||||
|
||||
proc_status = &adapter->halmac_state.efuse_state.proc_status;
|
||||
|
||||
if (cfg == HALMAC_EFUSE_R_FW &&
|
||||
halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
|
||||
@@ -498,7 +501,7 @@ dump_log_efuse_map_88xx(struct halmac_adapter *adapter,
|
||||
return status;
|
||||
}
|
||||
|
||||
if (adapter->efuse_map_valid == _TRUE) {
|
||||
if (adapter->efuse_map_valid == 1) {
|
||||
*proc_status = HALMAC_CMD_PROCESS_DONE;
|
||||
|
||||
map = (u8 *)PLTFM_MALLOC(size);
|
||||
@@ -889,7 +892,7 @@ read_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
/* Read efuse no need 2.5V LDO */
|
||||
enable = _FALSE;
|
||||
enable = 0;
|
||||
status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]dis ldo25\n");
|
||||
@@ -923,7 +926,8 @@ enum halmac_ret_status
|
||||
write_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
|
||||
{
|
||||
const u8 unlock_code = 0x69;
|
||||
u8 value_read = 0, enable;
|
||||
u8 value_read = 0;
|
||||
u8 enable;
|
||||
u32 value32;
|
||||
u32 tmp32;
|
||||
u32 cnt;
|
||||
@@ -931,13 +935,13 @@ write_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
|
||||
adapter->efuse_map_valid = _FALSE;
|
||||
adapter->efuse_map_valid = 0;
|
||||
PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
|
||||
|
||||
HALMAC_REG_W8(REG_PMC_DBG_CTRL2 + 3, unlock_code);
|
||||
|
||||
/* Enable 2.5V LDO */
|
||||
enable = _TRUE;
|
||||
enable = 1;
|
||||
status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]en ldo25\n");
|
||||
@@ -964,7 +968,7 @@ write_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
|
||||
HALMAC_REG_W8(REG_PMC_DBG_CTRL2 + 3, 0x00);
|
||||
|
||||
/* Disable 2.5V LDO */
|
||||
enable = _FALSE;
|
||||
enable = 0;
|
||||
status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]dis ldo25\n");
|
||||
@@ -984,7 +988,7 @@ write_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
static enum halmac_ret_status
|
||||
enum halmac_ret_status
|
||||
eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map)
|
||||
{
|
||||
u8 i;
|
||||
@@ -996,6 +1000,7 @@ eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map)
|
||||
u8 hdr2 = 0;
|
||||
u32 eeprom_idx;
|
||||
u32 efuse_idx = 0;
|
||||
u32 prtct_efuse_size = adapter->hw_cfg_info.prtct_efuse_size;
|
||||
struct halmac_hw_cfg_info *hw_info = &adapter->hw_cfg_info;
|
||||
|
||||
PLTFM_MEMSET(log_map, 0xFF, hw_info->eeprom_size);
|
||||
@@ -1022,7 +1027,7 @@ eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map)
|
||||
|
||||
efuse_idx++;
|
||||
|
||||
if (efuse_idx >= hw_info->efuse_size - PROTECT_EFUSE_SIZE - 1)
|
||||
if (efuse_idx >= hw_info->efuse_size - prtct_efuse_size - 1)
|
||||
return HALMAC_RET_EEPROM_PARSING_FAIL;
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
@@ -1050,7 +1055,7 @@ eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map)
|
||||
efuse_idx++;
|
||||
|
||||
if (efuse_idx > hw_info->efuse_size -
|
||||
PROTECT_EFUSE_SIZE - 1)
|
||||
prtct_efuse_size - 1)
|
||||
return HALMAC_RET_EEPROM_PARSING_FAIL;
|
||||
|
||||
value8 = *(phy_map + efuse_idx);
|
||||
@@ -1059,7 +1064,7 @@ eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map)
|
||||
efuse_idx++;
|
||||
|
||||
if (efuse_idx > hw_info->efuse_size -
|
||||
PROTECT_EFUSE_SIZE)
|
||||
prtct_efuse_size)
|
||||
return HALMAC_RET_EEPROM_PARSING_FAIL;
|
||||
}
|
||||
}
|
||||
@@ -1077,7 +1082,7 @@ read_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map)
|
||||
u32 efuse_size;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
if (adapter->efuse_map_valid == _FALSE) {
|
||||
if (adapter->efuse_map_valid == 0) {
|
||||
efuse_size = adapter->hw_cfg_info.efuse_size;
|
||||
|
||||
local_map = (u8 *)PLTFM_MALLOC(efuse_size);
|
||||
@@ -1104,7 +1109,7 @@ read_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map)
|
||||
|
||||
PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
|
||||
PLTFM_MEMCPY(adapter->efuse_map, local_map, efuse_size);
|
||||
adapter->efuse_map_valid = _TRUE;
|
||||
adapter->efuse_map_valid = 1;
|
||||
PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
|
||||
|
||||
PLTFM_FREE(local_map, efuse_size);
|
||||
@@ -1175,7 +1180,7 @@ dump_efuse_drv_88xx(struct halmac_adapter *adapter)
|
||||
}
|
||||
}
|
||||
|
||||
if (adapter->efuse_map_valid == _FALSE) {
|
||||
if (adapter->efuse_map_valid == 0) {
|
||||
map = (u8 *)PLTFM_MALLOC(efuse_size);
|
||||
if (!map) {
|
||||
PLTFM_MSG_ERR("[ERR]malloc map\n");
|
||||
@@ -1190,7 +1195,7 @@ dump_efuse_drv_88xx(struct halmac_adapter *adapter)
|
||||
|
||||
PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
|
||||
PLTFM_MEMCPY(adapter->efuse_map, map, efuse_size);
|
||||
adapter->efuse_map_valid = _TRUE;
|
||||
adapter->efuse_map_valid = 1;
|
||||
PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
|
||||
|
||||
PLTFM_FREE(map, efuse_size);
|
||||
@@ -1210,7 +1215,7 @@ dump_efuse_fw_88xx(struct halmac_adapter *adapter)
|
||||
|
||||
hdr_info.sub_cmd_id = SUB_CMD_ID_DUMP_PHYSICAL_EFUSE;
|
||||
hdr_info.content_size = 0;
|
||||
hdr_info.ack = _TRUE;
|
||||
hdr_info.ack = 1;
|
||||
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
|
||||
|
||||
adapter->halmac_state.efuse_state.seq_num = seq_num;
|
||||
@@ -1225,7 +1230,7 @@ dump_efuse_fw_88xx(struct halmac_adapter *adapter)
|
||||
}
|
||||
}
|
||||
|
||||
if (adapter->efuse_map_valid == _FALSE) {
|
||||
if (adapter->efuse_map_valid == 0) {
|
||||
status = send_h2c_pkt_88xx(adapter, h2c_buf);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]send h2c pkt\n");
|
||||
@@ -1249,6 +1254,7 @@ proc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
|
||||
u8 hdr2;
|
||||
u8 *map = NULL;
|
||||
u32 eeprom_size = adapter->hw_cfg_info.eeprom_size;
|
||||
u32 prtct_efuse_size = adapter->hw_cfg_info.prtct_efuse_size;
|
||||
u32 end;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
@@ -1289,7 +1295,7 @@ proc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
|
||||
|
||||
if (offset > 0x7f) {
|
||||
if (adapter->hw_cfg_info.efuse_size <=
|
||||
4 + PROTECT_EFUSE_SIZE + end) {
|
||||
4 + prtct_efuse_size + end) {
|
||||
PLTFM_FREE(map, eeprom_size);
|
||||
return HALMAC_RET_EFUSE_NOT_ENOUGH;
|
||||
}
|
||||
@@ -1319,7 +1325,7 @@ proc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
|
||||
}
|
||||
} else {
|
||||
if (adapter->hw_cfg_info.efuse_size <=
|
||||
3 + PROTECT_EFUSE_SIZE + end) {
|
||||
3 + prtct_efuse_size + end) {
|
||||
PLTFM_FREE(map, eeprom_size);
|
||||
return HALMAC_RET_EFUSE_NOT_ENOUGH;
|
||||
}
|
||||
@@ -1357,7 +1363,7 @@ read_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, u8 *map)
|
||||
return HALMAC_RET_NULL_POINTER;
|
||||
}
|
||||
|
||||
if (adapter->efuse_map_valid == _TRUE) {
|
||||
if (adapter->efuse_map_valid == 1) {
|
||||
PLTFM_MEMCPY(map, adapter->efuse_map + offset, size);
|
||||
} else {
|
||||
if (read_hw_efuse_88xx(adapter, offset, size, map) !=
|
||||
@@ -1485,7 +1491,8 @@ check_efuse_enough_88xx(struct halmac_adapter *adapter,
|
||||
}
|
||||
|
||||
if (adapter->hw_cfg_info.efuse_size <=
|
||||
(pg_num + PROTECT_EFUSE_SIZE + adapter->efuse_end))
|
||||
(pg_num + adapter->hw_cfg_info.prtct_efuse_size +
|
||||
adapter->efuse_end))
|
||||
return HALMAC_RET_EFUSE_NOT_ENOUGH;
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
@@ -1716,7 +1723,7 @@ get_efuse_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
|
||||
buf + C2H_DATA_OFFSET_88XX, seg_size);
|
||||
PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
|
||||
|
||||
if (EFUSE_DATA_GET_END_SEGMENT(buf) == _FALSE) {
|
||||
if (EFUSE_DATA_GET_END_SEGMENT(buf) == 0) {
|
||||
PLTFM_FREE(map, eeprom_size);
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
@@ -1728,7 +1735,7 @@ get_efuse_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
|
||||
state->proc_status = proc_status;
|
||||
|
||||
PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
|
||||
adapter->efuse_map_valid = _TRUE;
|
||||
adapter->efuse_map_valid = 1;
|
||||
PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
|
||||
|
||||
if (adapter->evnt.phy_efuse_map == 1) {
|
||||
@@ -1777,6 +1784,7 @@ get_dump_phy_efuse_status_88xx(struct halmac_adapter *adapter,
|
||||
{
|
||||
u8 *map = NULL;
|
||||
u32 efuse_size = adapter->hw_cfg_info.efuse_size;
|
||||
u32 prtct_efuse_size = adapter->hw_cfg_info.prtct_efuse_size;
|
||||
struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;
|
||||
|
||||
*proc_status = state->proc_status;
|
||||
@@ -1803,12 +1811,12 @@ get_dump_phy_efuse_status_88xx(struct halmac_adapter *adapter,
|
||||
PLTFM_MEMSET(map, 0xFF, efuse_size);
|
||||
PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
|
||||
PLTFM_MEMCPY(map, adapter->efuse_map,
|
||||
efuse_size - PROTECT_EFUSE_SIZE);
|
||||
PLTFM_MEMCPY(map + efuse_size - PROTECT_EFUSE_SIZE +
|
||||
efuse_size - prtct_efuse_size);
|
||||
PLTFM_MEMCPY(map + efuse_size - prtct_efuse_size +
|
||||
RSVD_CS_EFUSE_SIZE,
|
||||
adapter->efuse_map + efuse_size -
|
||||
PROTECT_EFUSE_SIZE + RSVD_CS_EFUSE_SIZE,
|
||||
PROTECT_EFUSE_SIZE - RSVD_EFUSE_SIZE -
|
||||
prtct_efuse_size + RSVD_CS_EFUSE_SIZE,
|
||||
prtct_efuse_size - RSVD_EFUSE_SIZE -
|
||||
RSVD_CS_EFUSE_SIZE);
|
||||
PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
|
||||
|
||||
@@ -1896,7 +1904,7 @@ get_h2c_ack_phy_efuse_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
|
||||
u32
|
||||
get_rsvd_efuse_size_88xx(struct halmac_adapter *adapter)
|
||||
{
|
||||
return PROTECT_EFUSE_SIZE;
|
||||
return adapter->hw_cfg_info.prtct_efuse_size;
|
||||
}
|
||||
|
||||
#endif /* HALMAC_88XX_SUPPORT */
|
||||
|
||||
@@ -24,6 +24,9 @@ enum halmac_ret_status
|
||||
dump_efuse_map_88xx(struct halmac_adapter *adapter,
|
||||
enum halmac_efuse_read_cfg cfg);
|
||||
|
||||
enum halmac_ret_status
|
||||
eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map);
|
||||
|
||||
enum halmac_ret_status
|
||||
dump_efuse_map_bt_88xx(struct halmac_adapter *adapter,
|
||||
enum halmac_efuse_bank bank, u32 size, u8 *map);
|
||||
|
||||
@@ -87,7 +87,7 @@ download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
|
||||
|
||||
hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH;
|
||||
hdr_info.content_size = 20;
|
||||
hdr_info.ack = _TRUE;
|
||||
hdr_info.ack = 1;
|
||||
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
|
||||
|
||||
rc = send_h2c_pkt_88xx(adapter, h2c_buf);
|
||||
@@ -131,7 +131,7 @@ download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
read_flash_88xx(struct halmac_adapter *adapter, u32 addr)
|
||||
read_flash_88xx(struct halmac_adapter *adapter, u32 addr, u32 length)
|
||||
{
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
enum halmac_ret_status status;
|
||||
@@ -168,13 +168,13 @@ read_flash_88xx(struct halmac_adapter *adapter, u32 addr)
|
||||
/* Construct H2C Content */
|
||||
DOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, 0x03);
|
||||
DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, h2c_info_addr - rsvd_pg_addr);
|
||||
DOWNLOAD_FLASH_SET_SIZE(h2c_buf, 4096);
|
||||
DOWNLOAD_FLASH_SET_SIZE(h2c_buf, length);
|
||||
DOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, addr);
|
||||
|
||||
/* Fill in H2C Header */
|
||||
hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH;
|
||||
hdr_info.content_size = 16;
|
||||
hdr_info.ack = _TRUE;
|
||||
hdr_info.ack = 1;
|
||||
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
|
||||
|
||||
/* Send H2C Cmd Packet */
|
||||
@@ -231,7 +231,7 @@ erase_flash_88xx(struct halmac_adapter *adapter, u8 erase_cmd, u32 addr)
|
||||
/* Fill in H2C Header */
|
||||
hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH;
|
||||
hdr_info.content_size = 16;
|
||||
hdr_info.ack = _TRUE;
|
||||
hdr_info.ack = 1;
|
||||
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
|
||||
|
||||
/* Send H2C Cmd Packet */
|
||||
@@ -286,7 +286,7 @@ check_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
|
||||
else
|
||||
pkt_size = size;
|
||||
|
||||
read_flash_88xx(adapter, addr);
|
||||
read_flash_88xx(adapter, addr, 4096);
|
||||
|
||||
cnt = 0;
|
||||
while (cnt < pkt_size) {
|
||||
|
||||
@@ -25,7 +25,7 @@ download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
|
||||
u32 rom_addr);
|
||||
|
||||
enum halmac_ret_status
|
||||
read_flash_88xx(struct halmac_adapter *adapter, u32 addr);
|
||||
read_flash_88xx(struct halmac_adapter *adapter, u32 addr, u32 length);
|
||||
|
||||
enum halmac_ret_status
|
||||
erase_flash_88xx(struct halmac_adapter *adapter, u8 erase_cmd, u32 addr);
|
||||
|
||||
@@ -243,14 +243,13 @@ start_dlfw_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
enum halmac_ret_status status;
|
||||
|
||||
dmem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_DMEM_SIZE));
|
||||
imem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_IMEM_SIZE));
|
||||
dmem_size =
|
||||
rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_DMEM_SIZE)));
|
||||
imem_size =
|
||||
rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_IMEM_SIZE)));
|
||||
if (0 != ((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4)))
|
||||
emem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_EMEM_SIZE));
|
||||
|
||||
dmem_size = rtk_le32_to_cpu(dmem_size);
|
||||
imem_size = rtk_le32_to_cpu(imem_size);
|
||||
emem_size = rtk_le32_to_cpu(emem_size);
|
||||
emem_size =
|
||||
rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_EMEM_SIZE)));
|
||||
|
||||
dmem_size += WLAN_FW_HDR_CHKSUM_SIZE;
|
||||
imem_size += WLAN_FW_HDR_CHKSUM_SIZE;
|
||||
@@ -268,15 +267,15 @@ start_dlfw_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
|
||||
HALMAC_REG_W16(REG_MCUFW_CTRL, value16);
|
||||
|
||||
cur_fw = fw_bin + WLAN_FW_HDR_SIZE;
|
||||
addr = *((u32 *)(fw_bin + WLAN_FW_HDR_DMEM_ADDR));
|
||||
addr = rtk_le32_to_cpu(addr) & ~BIT(31);
|
||||
addr = rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_DMEM_ADDR)));
|
||||
addr &= ~BIT(31);
|
||||
status = dlfw_to_mem_88xx(adapter, cur_fw, 0, addr, dmem_size);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
|
||||
cur_fw = fw_bin + WLAN_FW_HDR_SIZE + dmem_size;
|
||||
addr = *((u32 *)(fw_bin + WLAN_FW_HDR_IMEM_ADDR));
|
||||
addr = rtk_le32_to_cpu(addr) & ~BIT(31);
|
||||
addr = rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_IMEM_ADDR)));
|
||||
addr &= ~BIT(31);
|
||||
status = dlfw_to_mem_88xx(adapter, cur_fw, 0, addr, imem_size);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
@@ -285,8 +284,9 @@ DLFW_EMEM:
|
||||
if (emem_size) {
|
||||
cur_fw = fw_bin + WLAN_FW_HDR_SIZE +
|
||||
dmem_size + imem_size;
|
||||
addr = *((u32 *)(fw_bin + WLAN_FW_HDR_EMEM_ADDR));
|
||||
addr = rtk_le32_to_cpu(addr) & ~BIT(31);
|
||||
addr = rtk_le32_to_cpu(*((__le32 *)(fw_bin +
|
||||
WLAN_FW_HDR_EMEM_ADDR)));
|
||||
addr &= ~BIT(31);
|
||||
status = dlfw_to_mem_88xx(adapter, cur_fw, dl_addr << 7, addr,
|
||||
emem_size);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
@@ -308,15 +308,12 @@ chk_h2c_ver_88xx(struct halmac_adapter *adapter, u8 *fw_bin)
|
||||
u16 halmac_h2c_ver;
|
||||
u16 fw_h2c_ver;
|
||||
|
||||
fw_h2c_ver = *((u16 *)(fw_bin + WLAN_FW_HDR_H2C_FMT_VER));
|
||||
fw_h2c_ver = rtk_le16_to_cpu(fw_h2c_ver);
|
||||
fw_h2c_ver = rtk_le16_to_cpu(*((__le16 *)(fw_bin +
|
||||
WLAN_FW_HDR_H2C_FMT_VER)));
|
||||
halmac_h2c_ver = H2C_FORMAT_VERSION;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]halmac h2c ver = %x, fw h2c ver = %x!!\n",
|
||||
halmac_h2c_ver, fw_h2c_ver);
|
||||
|
||||
if (fw_h2c_ver != halmac_h2c_ver)
|
||||
PLTFM_MSG_WARN("[WARN]H2C/C2H ver is compatible!!\n");
|
||||
}
|
||||
|
||||
static enum halmac_ret_status
|
||||
@@ -332,14 +329,13 @@ chk_fw_size_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size)
|
||||
return HALMAC_RET_FW_SIZE_ERR;
|
||||
}
|
||||
|
||||
dmem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_DMEM_SIZE));
|
||||
imem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_IMEM_SIZE));
|
||||
dmem_size =
|
||||
rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_DMEM_SIZE)));
|
||||
imem_size =
|
||||
rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_IMEM_SIZE)));
|
||||
if (0 != ((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4)))
|
||||
emem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_EMEM_SIZE));
|
||||
|
||||
dmem_size = rtk_le32_to_cpu(dmem_size);
|
||||
imem_size = rtk_le32_to_cpu(imem_size);
|
||||
emem_size = rtk_le32_to_cpu(emem_size);
|
||||
emem_size =
|
||||
rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_EMEM_SIZE)));
|
||||
|
||||
dmem_size += WLAN_FW_HDR_CHKSUM_SIZE;
|
||||
imem_size += WLAN_FW_HDR_CHKSUM_SIZE;
|
||||
@@ -469,6 +465,28 @@ DL_FREE_FW_END:
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* reset_wifi_fw_88xx() - reset wifi fw
|
||||
* @adapter : the adapter of halmac
|
||||
* Author : LIN YONG-CHING
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
reset_wifi_fw_88xx(struct halmac_adapter *adapter)
|
||||
{
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
wlan_cpu_en_88xx(adapter, 0);
|
||||
pltfm_reset_88xx(adapter);
|
||||
init_ofld_feature_state_machine_88xx(adapter);
|
||||
wlan_cpu_en_88xx(adapter, 1);
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_fw_version_88xx() - get FW version
|
||||
* @adapter : the adapter of halmac
|
||||
@@ -507,18 +525,18 @@ update_fw_info_88xx(struct halmac_adapter *adapter, u8 *fw_bin)
|
||||
{
|
||||
struct halmac_fw_version *info = &adapter->fw_ver;
|
||||
|
||||
info->version = *((u16 *)(fw_bin + WLAN_FW_HDR_VERSION));
|
||||
info->version = rtk_le16_to_cpu(info->version);
|
||||
info->version =
|
||||
rtk_le16_to_cpu(*((__le16 *)(fw_bin + WLAN_FW_HDR_VERSION)));
|
||||
info->sub_version = *(fw_bin + WLAN_FW_HDR_SUBVERSION);
|
||||
info->sub_index = *(fw_bin + WLAN_FW_HDR_SUBINDEX);
|
||||
info->h2c_version = *((u16 *)(fw_bin + WLAN_FW_HDR_H2C_FMT_VER));
|
||||
info->h2c_version = rtk_le16_to_cpu(info->h2c_version);
|
||||
info->h2c_version = rtk_le16_to_cpu(*((__le16 *)(fw_bin +
|
||||
WLAN_FW_HDR_H2C_FMT_VER)));
|
||||
info->build_time.month = *(fw_bin + WLAN_FW_HDR_MONTH);
|
||||
info->build_time.date = *(fw_bin + WLAN_FW_HDR_DATE);
|
||||
info->build_time.hour = *(fw_bin + WLAN_FW_HDR_HOUR);
|
||||
info->build_time.min = *(fw_bin + WLAN_FW_HDR_MIN);
|
||||
info->build_time.year = *((u16 *)(fw_bin + WLAN_FW_HDR_YEAR));
|
||||
info->build_time.year = rtk_le16_to_cpu(info->build_time.year);
|
||||
info->build_time.year =
|
||||
rtk_le16_to_cpu(*((__le16 *)(fw_bin + WLAN_FW_HDR_YEAR)));
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]=== FW info ===\n");
|
||||
PLTFM_MSG_TRACE("[TRACE]ver : %X\n", info->version);
|
||||
@@ -560,7 +578,7 @@ dlfw_to_mem_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 src, u32 dest,
|
||||
status = send_fwpkt_88xx(adapter, (u16)(src >> 7),
|
||||
fw_bin + mem_offset, pkt_size);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]send fw pkt!!");
|
||||
PLTFM_MSG_ERR("[ERR]send fw pkt!!\n");
|
||||
return status;
|
||||
}
|
||||
|
||||
@@ -570,7 +588,7 @@ dlfw_to_mem_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 src, u32 dest,
|
||||
dest + mem_offset, pkt_size,
|
||||
first_part);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]iddma dlfw!!");
|
||||
PLTFM_MSG_ERR("[ERR]iddma dlfw!!\n");
|
||||
return status;
|
||||
}
|
||||
|
||||
@@ -581,7 +599,7 @@ dlfw_to_mem_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 src, u32 dest,
|
||||
|
||||
status = check_fw_chksum_88xx(adapter, dest);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]chk fw chksum!!");
|
||||
PLTFM_MSG_ERR("[ERR]chk fw chksum!!\n");
|
||||
return status;
|
||||
}
|
||||
|
||||
@@ -691,8 +709,29 @@ static enum halmac_ret_status
|
||||
send_fwpkt_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *fw_bin,
|
||||
u32 size)
|
||||
{
|
||||
u8 *fw_add_dum = NULL;
|
||||
enum halmac_ret_status status;
|
||||
|
||||
if (adapter->intf == HALMAC_INTERFACE_USB &&
|
||||
!((size + TX_DESC_SIZE_88XX) & (512 - 1))) {
|
||||
fw_add_dum = (u8 *)PLTFM_MALLOC(size + 1);
|
||||
if (!fw_add_dum) {
|
||||
PLTFM_MSG_ERR("[ERR]fw bin malloc!!\n");
|
||||
return HALMAC_RET_MALLOC_FAIL;
|
||||
}
|
||||
|
||||
PLTFM_MEMCPY(fw_add_dum, fw_bin, size);
|
||||
|
||||
status = dl_rsvd_page_88xx(adapter, pg_addr,
|
||||
fw_add_dum, size + 1);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
PLTFM_MSG_ERR("[ERR]dl rsvd page - dum!!\n");
|
||||
|
||||
PLTFM_FREE(fw_add_dum, size + 1);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
status = dl_rsvd_page_88xx(adapter, pg_addr, fw_bin, size);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
PLTFM_MSG_ERR("[ERR]dl rsvd page!!\n");
|
||||
@@ -803,7 +842,7 @@ check_fw_status_88xx(struct halmac_adapter *adapter, u8 *fw_status)
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
*fw_status = _TRUE;
|
||||
*fw_status = 1;
|
||||
|
||||
fw_dbg6 = HALMAC_REG_R32(REG_FW_DBG6);
|
||||
|
||||
@@ -818,7 +857,7 @@ check_fw_status_88xx(struct halmac_adapter *adapter, u8 *fw_status)
|
||||
if ((fw_dbg6 & FW_STATUS_CHK_FATAL) != 0) {
|
||||
PLTFM_MSG_ERR("[ERR]fw status(fatal):%X\n", fw_dbg6);
|
||||
fw_fatal_status_debug_88xx(adapter);
|
||||
*fw_status = _FALSE;
|
||||
*fw_status = 0;
|
||||
return status;
|
||||
}
|
||||
}
|
||||
@@ -837,7 +876,7 @@ check_fw_status_88xx(struct halmac_adapter *adapter, u8 *fw_status)
|
||||
cnt--;
|
||||
if (cnt == 0) {
|
||||
PLTFM_MSG_ERR("[ERR]fw pc\n");
|
||||
*fw_status = _FALSE;
|
||||
*fw_status = 0;
|
||||
return status;
|
||||
}
|
||||
PLTFM_DELAY_US(50);
|
||||
@@ -996,6 +1035,8 @@ enum halmac_ret_status
|
||||
send_general_info_88xx(struct halmac_adapter *adapter,
|
||||
struct halmac_general_info *info)
|
||||
{
|
||||
u8 h2cq_ele[4] = {0};
|
||||
u32 h2cq_addr;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
|
||||
@@ -1023,6 +1064,20 @@ send_general_info_88xx(struct halmac_adapter *adapter,
|
||||
return status;
|
||||
}
|
||||
|
||||
h2cq_addr = adapter->txff_alloc.rsvd_h2cq_addr;
|
||||
h2cq_addr <<= TX_PAGE_SIZE_SHIFT_88XX;
|
||||
status = dump_fifo_88xx(adapter, HAL_FIFO_SEL_TX,
|
||||
h2cq_addr, 4, h2cq_ele);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]dump h2cq!!\n");
|
||||
return status;
|
||||
}
|
||||
|
||||
if ((h2cq_ele[0] & 0x7F) != 0x01 || h2cq_ele[1] != 0xFF) {
|
||||
PLTFM_MSG_ERR("[ERR]h2cq compare!!\n");
|
||||
return HALMAC_RET_SEND_H2C_FAIL;
|
||||
}
|
||||
|
||||
if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_DONE)
|
||||
adapter->halmac_state.dlfw_state = HALMAC_GEN_INFO_SENT;
|
||||
|
||||
@@ -1048,7 +1103,7 @@ proc_send_general_info_88xx(struct halmac_adapter *adapter,
|
||||
|
||||
hdr_info.sub_cmd_id = SUB_CMD_ID_GENERAL_INFO;
|
||||
hdr_info.content_size = 4;
|
||||
hdr_info.ack = _FALSE;
|
||||
hdr_info.ack = 0;
|
||||
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
|
||||
|
||||
status = send_h2c_pkt_88xx(adapter, h2c_buf);
|
||||
@@ -1078,7 +1133,7 @@ proc_send_phydm_info_88xx(struct halmac_adapter *adapter,
|
||||
|
||||
hdr_info.sub_cmd_id = SUB_CMD_ID_PHYDM_INFO;
|
||||
hdr_info.content_size = 8;
|
||||
hdr_info.ack = _FALSE;
|
||||
hdr_info.ack = 0;
|
||||
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
|
||||
|
||||
status = send_h2c_pkt_88xx(adapter, h2c_buf);
|
||||
|
||||
@@ -22,8 +22,6 @@
|
||||
|
||||
#define HALMC_DDMA_POLLING_COUNT 1000
|
||||
|
||||
#endif /* HALMAC_88XX_SUPPORT */
|
||||
|
||||
enum halmac_ret_status
|
||||
download_firmware_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size);
|
||||
|
||||
@@ -31,6 +29,9 @@ enum halmac_ret_status
|
||||
free_download_firmware_88xx(struct halmac_adapter *adapter,
|
||||
enum halmac_dlfw_mem mem_sel, u8 *fw_bin, u32 size);
|
||||
|
||||
enum halmac_ret_status
|
||||
reset_wifi_fw_88xx(struct halmac_adapter *adapter);
|
||||
|
||||
enum halmac_ret_status
|
||||
get_fw_version_88xx(struct halmac_adapter *adapter,
|
||||
struct halmac_fw_version *ver);
|
||||
@@ -58,4 +59,6 @@ send_general_info_88xx(struct halmac_adapter *adapter,
|
||||
enum halmac_ret_status
|
||||
drv_fwctrl_88xx(struct halmac_adapter *adapter, u8 *payload, u32 size, u8 ack);
|
||||
|
||||
#endif /* HALMAC_88XX_SUPPORT */
|
||||
|
||||
#endif/* _HALMAC_FW_88XX_H_ */
|
||||
|
||||
@@ -273,6 +273,10 @@ pinmux_switch_88xx(struct halmac_adapter *adapter,
|
||||
case HALMAC_GPIO_FUNC_SDIO_INT:
|
||||
switch_func = HALMAC_SDIO_INT;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
|
||||
case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
|
||||
switch_func = HALMAC_GPIO13_14_WL_CTRL_EN;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_0:
|
||||
case HALMAC_GPIO_FUNC_SW_IO_1:
|
||||
case HALMAC_GPIO_FUNC_SW_IO_2:
|
||||
@@ -352,6 +356,12 @@ pinmux_record_88xx(struct halmac_adapter *adapter,
|
||||
case HALMAC_GPIO_FUNC_SDIO_INT:
|
||||
adapter->pinmux_info.sdio_int = val;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_BT_HOST_WAKE1:
|
||||
adapter->pinmux_info.bt_host_wake = val;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_BT_DEV_WAKE1:
|
||||
adapter->pinmux_info.bt_dev_wake = val;
|
||||
break;
|
||||
case HALMAC_GPIO_FUNC_SW_IO_0:
|
||||
adapter->pinmux_info.sw_io_0 = val;
|
||||
break;
|
||||
|
||||
@@ -21,9 +21,15 @@
|
||||
#include "halmac_efuse_88xx.h"
|
||||
#include "halmac_mimo_88xx.h"
|
||||
#include "halmac_bb_rf_88xx.h"
|
||||
#if HALMAC_SDIO_SUPPORT
|
||||
#include "halmac_sdio_88xx.h"
|
||||
#endif
|
||||
#if HALMAC_USB_SUPPORT
|
||||
#include "halmac_usb_88xx.h"
|
||||
#endif
|
||||
#if HALMAC_PCIE_SUPPORT
|
||||
#include "halmac_pcie_88xx.h"
|
||||
#endif
|
||||
#include "halmac_gpio_88xx.h"
|
||||
#include "halmac_flash_88xx.h"
|
||||
|
||||
@@ -39,6 +45,10 @@
|
||||
#include "halmac_8822c/halmac_init_8822c.h"
|
||||
#endif
|
||||
|
||||
#if HALMAC_8812F_SUPPORT
|
||||
#include "halmac_8812f/halmac_init_8812f.h"
|
||||
#endif
|
||||
|
||||
#if HALMAC_PLATFORM_TESTPROGRAM
|
||||
#include "halmisc_api_88xx.h"
|
||||
#endif
|
||||
@@ -49,48 +59,6 @@
|
||||
#define PLTFM_INFO_RSVD_PG_SIZE 16384
|
||||
#define DLFW_PKT_MAX_SIZE 8192 /* need multiple of 2 */
|
||||
|
||||
#define SYS_FUNC_EN 0xDC
|
||||
#define WLAN_SLOT_TIME 0x05
|
||||
#define WLAN_PIFS_TIME 0x19
|
||||
#define WLAN_SIFS_CCK_CONT_TX 0xA
|
||||
#define WLAN_SIFS_OFDM_CONT_TX 0xA
|
||||
#define WLAN_SIFS_CCK_TRX 0x10
|
||||
#define WLAN_SIFS_OFDM_TRX 0x10
|
||||
#define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */
|
||||
#define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */
|
||||
#define WLAN_RDG_NAV 0x05
|
||||
#define WLAN_TXOP_NAV 0x1B
|
||||
#define WLAN_CCK_RX_TSF 0x30
|
||||
#define WLAN_OFDM_RX_TSF 0x30
|
||||
#define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
|
||||
#define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
|
||||
#define WLAN_DRV_EARLY_INT 0x04
|
||||
#define WLAN_BCN_DMA_TIME 0x02
|
||||
#define WLAN_ACK_TO_CCK 0x40
|
||||
|
||||
#define WLAN_RX_FILTER0 0x0FFFFFFF
|
||||
#define WLAN_RX_FILTER2 0xFFFF
|
||||
#define WLAN_RCR_CFG 0xE400220E
|
||||
#define WLAN_RXPKT_MAX_SZ 12288
|
||||
#define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9)
|
||||
|
||||
#define WLAN_TX_FUNC_CFG1 0x30
|
||||
#define WLAN_TX_FUNC_CFG2 0x30
|
||||
#define WLAN_MAC_OPT_NORM_FUNC1 0x98
|
||||
#define WLAN_MAC_OPT_LB_FUNC1 0x80
|
||||
#define WLAN_MAC_OPT_FUNC2 0x30810041
|
||||
|
||||
#define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \
|
||||
(WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
|
||||
(WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
|
||||
(WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
|
||||
|
||||
#define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
|
||||
(WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
|
||||
|
||||
#define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
|
||||
#define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
|
||||
|
||||
static void
|
||||
init_state_machine_88xx(struct halmac_adapter *adapter);
|
||||
|
||||
@@ -109,7 +77,7 @@ init_adapter_param_88xx(struct halmac_adapter *adapter)
|
||||
adapter->api_registry.sdio_cmd53_4byte_en = 1;
|
||||
|
||||
adapter->efuse_map = (u8 *)NULL;
|
||||
adapter->efuse_map_valid = _FALSE;
|
||||
adapter->efuse_map_valid = 0;
|
||||
adapter->efuse_end = 0;
|
||||
|
||||
adapter->dlfw_pkt_size = DLFW_PKT_MAX_SIZE;
|
||||
@@ -119,7 +87,7 @@ init_adapter_param_88xx(struct halmac_adapter *adapter)
|
||||
adapter->cfg_param_info.buf = NULL;
|
||||
adapter->cfg_param_info.buf_wptr = NULL;
|
||||
adapter->cfg_param_info.num = 0;
|
||||
adapter->cfg_param_info.full_fifo_mode = _FALSE;
|
||||
adapter->cfg_param_info.full_fifo_mode = 0;
|
||||
adapter->cfg_param_info.buf_size = 0;
|
||||
adapter->cfg_param_info.avl_buf_size = 0;
|
||||
adapter->cfg_param_info.offset_accum = 0;
|
||||
@@ -134,7 +102,7 @@ init_adapter_param_88xx(struct halmac_adapter *adapter)
|
||||
adapter->ch_sw_info.ch_num = 0;
|
||||
|
||||
adapter->drv_info_size = 0;
|
||||
adapter->tx_desc_transfer = _FALSE;
|
||||
adapter->tx_desc_transfer = 0;
|
||||
|
||||
adapter->txff_alloc.tx_fifo_pg_num = 0;
|
||||
adapter->txff_alloc.acq_pg_num = 0;
|
||||
@@ -193,6 +161,13 @@ init_adapter_param_88xx(struct halmac_adapter *adapter)
|
||||
adapter->pcie_refautok_en = 1;
|
||||
adapter->pwr_off_flow_flag = 0;
|
||||
|
||||
adapter->rx_ignore_info.hdr_chk_mask = 1;
|
||||
adapter->rx_ignore_info.fcs_chk_mask = 1;
|
||||
adapter->rx_ignore_info.hdr_chk_en = 0;
|
||||
adapter->rx_ignore_info.fcs_chk_en = 0;
|
||||
adapter->rx_ignore_info.cck_rst_en = 0;
|
||||
adapter->rx_ignore_info.fcs_chk_thr = HALMAC_PSF_FCS_CHK_THR_28;
|
||||
|
||||
init_adapter_dynamic_param_88xx(adapter);
|
||||
init_state_machine_88xx(adapter);
|
||||
}
|
||||
@@ -223,6 +198,7 @@ mount_api_88xx(struct halmac_adapter *adapter)
|
||||
api->halmac_register_api = register_api_88xx;
|
||||
api->halmac_download_firmware = download_firmware_88xx;
|
||||
api->halmac_free_download_firmware = free_download_firmware_88xx;
|
||||
api->halmac_reset_wifi_fw = reset_wifi_fw_88xx;
|
||||
api->halmac_get_fw_version = get_fw_version_88xx;
|
||||
api->halmac_cfg_mac_addr = cfg_mac_addr_88xx;
|
||||
api->halmac_cfg_bssid = cfg_bssid_88xx;
|
||||
@@ -232,13 +208,9 @@ mount_api_88xx(struct halmac_adapter *adapter)
|
||||
api->halmac_cfg_bcn_space = cfg_bcn_space_88xx;
|
||||
api->halmac_rw_bcn_ctrl = rw_bcn_ctrl_88xx;
|
||||
api->halmac_cfg_multicast_addr = cfg_multicast_addr_88xx;
|
||||
api->halmac_pre_init_system_cfg = pre_init_system_cfg_88xx;
|
||||
api->halmac_init_system_cfg = init_system_cfg_88xx;
|
||||
api->halmac_init_edca_cfg = init_edca_cfg_88xx;
|
||||
api->halmac_cfg_operation_mode = cfg_operation_mode_88xx;
|
||||
api->halmac_cfg_ch_bw = cfg_ch_bw_88xx;
|
||||
api->halmac_cfg_bw = cfg_bw_88xx;
|
||||
api->halmac_init_wmac_cfg = init_wmac_cfg_88xx;
|
||||
api->halmac_init_mac_cfg = init_mac_cfg_88xx;
|
||||
api->halmac_dump_efuse_map = dump_efuse_map_88xx;
|
||||
api->halmac_dump_efuse_map_bt = dump_efuse_map_bt_88xx;
|
||||
@@ -315,15 +287,6 @@ mount_api_88xx(struct halmac_adapter *adapter)
|
||||
api->halmac_dl_drv_rsvd_page = dl_drv_rsvd_page_88xx;
|
||||
api->halmac_cfg_csi_rate = cfg_csi_rate_88xx;
|
||||
|
||||
api->halmac_sdio_cmd53_4byte = sdio_cmd53_4byte_88xx;
|
||||
api->halmac_sdio_hw_info = sdio_hw_info_88xx;
|
||||
|
||||
api->halmac_init_sdio_cfg = init_sdio_cfg_88xx;
|
||||
api->halmac_init_usb_cfg = init_usb_cfg_88xx;
|
||||
api->halmac_init_pcie_cfg = init_pcie_cfg_88xx;
|
||||
api->halmac_deinit_sdio_cfg = deinit_sdio_cfg_88xx;
|
||||
api->halmac_deinit_usb_cfg = deinit_usb_cfg_88xx;
|
||||
api->halmac_deinit_pcie_cfg = deinit_pcie_cfg_88xx;
|
||||
api->halmac_txfifo_is_empty = txfifo_is_empty_88xx;
|
||||
api->halmac_download_flash = download_flash_88xx;
|
||||
api->halmac_read_flash = read_flash_88xx;
|
||||
@@ -344,9 +307,11 @@ mount_api_88xx(struct halmac_adapter *adapter)
|
||||
api->halmac_enter_cpu_sleep_mode = enter_cpu_sleep_mode_88xx;
|
||||
api->halmac_get_cpu_mode = get_cpu_mode_88xx;
|
||||
api->halmac_drv_fwctrl = drv_fwctrl_88xx;
|
||||
api->halmac_en_ref_autok_pcie = en_ref_autok_88xx;
|
||||
|
||||
if (adapter->intf == HALMAC_INTERFACE_SDIO) {
|
||||
#if HALMAC_SDIO_SUPPORT
|
||||
api->halmac_init_sdio_cfg = init_sdio_cfg_88xx;
|
||||
api->halmac_deinit_sdio_cfg = deinit_sdio_cfg_88xx;
|
||||
api->halmac_cfg_rx_aggregation = cfg_sdio_rx_agg_88xx;
|
||||
api->halmac_init_interface_cfg = init_sdio_cfg_88xx;
|
||||
api->halmac_deinit_interface_cfg = deinit_sdio_cfg_88xx;
|
||||
@@ -355,7 +320,14 @@ mount_api_88xx(struct halmac_adapter *adapter)
|
||||
api->halmac_get_usb_bulkout_id = get_sdio_bulkout_id_88xx;
|
||||
api->halmac_reg_read_indirect_32 = sdio_indirect_reg_r32_88xx;
|
||||
api->halmac_reg_sdio_cmd53_read_n = sdio_reg_rn_88xx;
|
||||
api->halmac_sdio_cmd53_4byte = sdio_cmd53_4byte_88xx;
|
||||
api->halmac_sdio_hw_info = sdio_hw_info_88xx;
|
||||
|
||||
#endif
|
||||
} else if (adapter->intf == HALMAC_INTERFACE_USB) {
|
||||
#if HALMAC_USB_SUPPORT
|
||||
api->halmac_init_usb_cfg = init_usb_cfg_88xx;
|
||||
api->halmac_deinit_usb_cfg = deinit_usb_cfg_88xx;
|
||||
api->halmac_cfg_rx_aggregation = cfg_usb_rx_agg_88xx;
|
||||
api->halmac_init_interface_cfg = init_usb_cfg_88xx;
|
||||
api->halmac_deinit_interface_cfg = deinit_usb_cfg_88xx;
|
||||
@@ -372,7 +344,11 @@ mount_api_88xx(struct halmac_adapter *adapter)
|
||||
api->halmac_reg_write_32 = reg_w32_usb_88xx;
|
||||
api->halmac_reg_read_indirect_32 = usb_indirect_reg_r32_88xx;
|
||||
api->halmac_reg_sdio_cmd53_read_n = usb_reg_rn_88xx;
|
||||
#endif
|
||||
} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
|
||||
#if HALMAC_PCIE_SUPPORT
|
||||
api->halmac_init_pcie_cfg = init_pcie_cfg_88xx;
|
||||
api->halmac_deinit_pcie_cfg = deinit_pcie_cfg_88xx;
|
||||
api->halmac_cfg_rx_aggregation = cfg_pcie_rx_agg_88xx;
|
||||
api->halmac_init_interface_cfg = init_pcie_cfg_88xx;
|
||||
api->halmac_deinit_interface_cfg = deinit_pcie_cfg_88xx;
|
||||
@@ -389,6 +365,8 @@ mount_api_88xx(struct halmac_adapter *adapter)
|
||||
api->halmac_reg_write_32 = reg_w32_pcie_88xx;
|
||||
api->halmac_reg_read_indirect_32 = pcie_indirect_reg_r32_88xx;
|
||||
api->halmac_reg_sdio_cmd53_read_n = pcie_reg_rn_88xx;
|
||||
api->halmac_en_ref_autok_pcie = en_ref_autok_88xx;
|
||||
#endif
|
||||
} else {
|
||||
PLTFM_MSG_ERR("[ERR]Set halmac io function Error!!\n");
|
||||
}
|
||||
@@ -404,6 +382,10 @@ mount_api_88xx(struct halmac_adapter *adapter)
|
||||
} else if (adapter->chip_id == HALMAC_CHIP_ID_8822C) {
|
||||
#if HALMAC_8822C_SUPPORT
|
||||
mount_api_8822c(adapter);
|
||||
#endif
|
||||
} else if (adapter->chip_id == HALMAC_CHIP_ID_8812F) {
|
||||
#if HALMAC_8812F_SUPPORT
|
||||
mount_api_8812f(adapter);
|
||||
#endif
|
||||
} else {
|
||||
PLTFM_MSG_ERR("[ERR]Chip ID undefine!!\n");
|
||||
@@ -498,206 +480,6 @@ register_api_88xx(struct halmac_adapter *adapter,
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* pre_init_system_cfg_88xx() - pre-init system config
|
||||
* @adapter : the adapter of halmac
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
pre_init_system_cfg_88xx(struct halmac_adapter *adapter)
|
||||
{
|
||||
u32 value32;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
u8 enable_bb;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
HALMAC_REG_W8(REG_RSV_CTRL, 0);
|
||||
|
||||
if (adapter->intf == HALMAC_INTERFACE_SDIO) {
|
||||
if (leave_sdio_suspend_88xx(adapter) != HALMAC_RET_SUCCESS)
|
||||
return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
|
||||
} else if (adapter->intf == HALMAC_INTERFACE_USB) {
|
||||
if (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20)
|
||||
HALMAC_REG_W8(0xFE5B, HALMAC_REG_R8(0xFE5B) | BIT(4));
|
||||
} else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
|
||||
/* For PCIE power on fail issue */
|
||||
HALMAC_REG_W8(REG_HCI_OPT_CTRL + 1,
|
||||
HALMAC_REG_R8(REG_HCI_OPT_CTRL + 1) | BIT(0));
|
||||
}
|
||||
|
||||
/* Config PIN Mux */
|
||||
value32 = HALMAC_REG_R32(REG_PAD_CTRL1);
|
||||
value32 = value32 & (~(BIT(28) | BIT(29)));
|
||||
value32 = value32 | BIT(28) | BIT(29);
|
||||
HALMAC_REG_W32(REG_PAD_CTRL1, value32);
|
||||
|
||||
value32 = HALMAC_REG_R32(REG_LED_CFG);
|
||||
value32 = value32 & (~(BIT(25) | BIT(26)));
|
||||
HALMAC_REG_W32(REG_LED_CFG, value32);
|
||||
|
||||
value32 = HALMAC_REG_R32(REG_GPIO_MUXCFG);
|
||||
value32 = value32 & (~(BIT(2)));
|
||||
value32 = value32 | BIT(2);
|
||||
HALMAC_REG_W32(REG_GPIO_MUXCFG, value32);
|
||||
|
||||
enable_bb = _FALSE;
|
||||
set_hw_value_88xx(adapter, HALMAC_HW_EN_BB_RF, &enable_bb);
|
||||
|
||||
if (HALMAC_REG_R8(REG_SYS_CFG1 + 2) & BIT(4)) {
|
||||
PLTFM_MSG_ERR("[ERR]test mode!!\n");
|
||||
return HALMAC_RET_WLAN_MODE_FAIL;
|
||||
}
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* init_system_cfg_88xx() - init system config
|
||||
* @adapter : the adapter of halmac
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
init_system_cfg_88xx(struct halmac_adapter *adapter)
|
||||
{
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
u32 tmp = 0;
|
||||
u32 value32;
|
||||
enum halmac_ret_status status;
|
||||
u8 hwval;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
if (adapter->intf == HALMAC_INTERFACE_PCIE) {
|
||||
hwval = 1;
|
||||
status = api->halmac_set_hw_value(adapter,
|
||||
HALMAC_HW_PCIE_REF_AUTOK,
|
||||
&hwval);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
}
|
||||
|
||||
HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, SYS_FUNC_EN);
|
||||
|
||||
value32 = HALMAC_REG_R32(REG_SYS_SDIO_CTRL) | BIT_LTE_MUX_CTRL_PATH;
|
||||
HALMAC_REG_W32(REG_SYS_SDIO_CTRL, value32);
|
||||
|
||||
value32 = HALMAC_REG_R32(REG_CPU_DMEM_CON) | BIT_WL_PLATFORM_RST;
|
||||
#if HALMAC_8822C_SUPPORT
|
||||
if (adapter->chip_id != HALMAC_CHIP_ID_8822B &&
|
||||
adapter->chip_id != HALMAC_CHIP_ID_8821C)
|
||||
value32 |= BIT_DDMA_EN;
|
||||
#endif
|
||||
HALMAC_REG_W32(REG_CPU_DMEM_CON, value32);
|
||||
|
||||
/*disable boot-from-flash for driver's DL FW*/
|
||||
tmp = HALMAC_REG_R32(REG_MCUFW_CTRL);
|
||||
if (tmp & BIT_BOOT_FSPI_EN) {
|
||||
HALMAC_REG_W32(REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN));
|
||||
value32 = HALMAC_REG_R32(REG_GPIO_MUXCFG) & (~BIT_FSPI_EN);
|
||||
HALMAC_REG_W32(REG_GPIO_MUXCFG, value32);
|
||||
}
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* init_edca_cfg_88xx() - init EDCA config
|
||||
* @adapter : the adapter of halmac
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
init_edca_cfg_88xx(struct halmac_adapter *adapter)
|
||||
{
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
/* Clear TX pause */
|
||||
HALMAC_REG_W16(REG_TXPAUSE, 0x0000);
|
||||
|
||||
HALMAC_REG_W8(REG_SLOT, WLAN_SLOT_TIME);
|
||||
HALMAC_REG_W8(REG_PIFS, WLAN_PIFS_TIME);
|
||||
HALMAC_REG_W32(REG_SIFS, WLAN_SIFS_CFG);
|
||||
|
||||
HALMAC_REG_W16(REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
|
||||
HALMAC_REG_W16(REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
|
||||
|
||||
HALMAC_REG_W32(REG_RD_NAV_NXT, WLAN_NAV_CFG);
|
||||
HALMAC_REG_W16(REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
|
||||
|
||||
/* Set beacon cotnrol - enable TSF and other related functions */
|
||||
HALMAC_REG_W8(REG_BCN_CTRL, (u8)(HALMAC_REG_R8(REG_BCN_CTRL) |
|
||||
BIT_EN_BCN_FUNCTION));
|
||||
|
||||
/* Set send beacon related registers */
|
||||
HALMAC_REG_W32(REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
|
||||
HALMAC_REG_W8(REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
|
||||
HALMAC_REG_W8(REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* init_wmac_cfg_88xx() - init wmac config
|
||||
* @adapter : the adapter of halmac
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
init_wmac_cfg_88xx(struct halmac_adapter *adapter)
|
||||
{
|
||||
u8 value8;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
HALMAC_REG_W32(REG_RXFLTMAP0, WLAN_RX_FILTER0);
|
||||
HALMAC_REG_W16(REG_RXFLTMAP2, WLAN_RX_FILTER2);
|
||||
|
||||
HALMAC_REG_W32(REG_RCR, WLAN_RCR_CFG);
|
||||
|
||||
HALMAC_REG_W8(REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
|
||||
|
||||
HALMAC_REG_W8(REG_TCR + 2, WLAN_TX_FUNC_CFG2);
|
||||
HALMAC_REG_W8(REG_TCR + 1, WLAN_TX_FUNC_CFG1);
|
||||
|
||||
#if HALMAC_8821C_SUPPORT
|
||||
if (adapter->chip_id == HALMAC_CHIP_ID_8821C)
|
||||
HALMAC_REG_W8(REG_ACKTO_CCK, WLAN_ACK_TO_CCK);
|
||||
#endif
|
||||
HALMAC_REG_W32(REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
|
||||
|
||||
if (adapter->hw_cfg_info.trx_mode == HALMAC_TRNSFER_NORMAL)
|
||||
value8 = WLAN_MAC_OPT_NORM_FUNC1;
|
||||
else
|
||||
value8 = WLAN_MAC_OPT_LB_FUNC1;
|
||||
|
||||
HALMAC_REG_W8(REG_WMAC_OPTION_FUNCTION + 4, value8);
|
||||
|
||||
status = api->halmac_init_low_pwr(adapter);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* init_mac_cfg_88xx() - config page1~page7 register
|
||||
* @adapter : the adapter of halmac
|
||||
@@ -712,7 +494,7 @@ init_mac_cfg_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode)
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__, mode);
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
status = api->halmac_init_trx_cfg(adapter, mode);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
@@ -726,13 +508,13 @@ init_mac_cfg_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode)
|
||||
return status;
|
||||
}
|
||||
|
||||
status = init_edca_cfg_88xx(adapter);
|
||||
status = api->halmac_init_edca_cfg(adapter);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]init edca %x\n", status);
|
||||
return status;
|
||||
}
|
||||
|
||||
status = init_wmac_cfg_88xx(adapter);
|
||||
status = api->halmac_init_wmac_cfg(adapter);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]init wmac %x\n", status);
|
||||
return status;
|
||||
@@ -854,7 +636,7 @@ tx_desc_chksum_88xx(struct halmac_adapter *adapter, u8 enable)
|
||||
adapter->tx_desc_checksum = enable;
|
||||
|
||||
value16 = HALMAC_REG_R16(REG_TXDMA_OFFSET_CHK);
|
||||
if (enable == _TRUE)
|
||||
if (enable == 1)
|
||||
HALMAC_REG_W16(REG_TXDMA_OFFSET_CHK, value16 | BIT(13));
|
||||
else
|
||||
HALMAC_REG_W16(REG_TXDMA_OFFSET_CHK, value16 & ~BIT(13));
|
||||
@@ -875,9 +657,11 @@ verify_io_88xx(struct halmac_adapter *adapter)
|
||||
offset = REG_PAGE5_DUMMY;
|
||||
if (0 == (offset & 0xFFFF0000))
|
||||
offset |= WLAN_IOREG_OFFSET;
|
||||
|
||||
#if HALMAC_SDIO_SUPPORT
|
||||
ret_status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
|
||||
|
||||
#else
|
||||
return HALMAC_RET_WRONG_INTF;
|
||||
#endif
|
||||
/* Verify CMD52 R/W */
|
||||
wvalue8 = 0xab;
|
||||
PLTFM_SDIO_CMD52_W(offset, wvalue8);
|
||||
@@ -945,7 +729,8 @@ verify_send_rsvd_page_88xx(struct halmac_adapter *adapter)
|
||||
u8 *rsvd_buf = NULL;
|
||||
u8 *rsvd_page = NULL;
|
||||
u32 i;
|
||||
u32 pkt_size = 64, payload = 0xab;
|
||||
u32 pkt_size = 64;
|
||||
u32 payload = 0xab;
|
||||
enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;
|
||||
|
||||
rsvd_buf = (u8 *)PLTFM_MALLOC(pkt_size);
|
||||
@@ -1002,8 +787,12 @@ pg_num_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode,
|
||||
struct halmac_pg_num *tbl)
|
||||
{
|
||||
u8 flag;
|
||||
u16 hpq_num = 0, lpq_num = 0, npq_num = 0, gapq_num = 0;
|
||||
u16 expq_num = 0, pubq_num = 0;
|
||||
u16 hpq_num = 0;
|
||||
u16 lpq_num = 0;
|
||||
u16 npq_num = 0;
|
||||
u16 gapq_num = 0;
|
||||
u16 expq_num = 0;
|
||||
u16 pubq_num = 0;
|
||||
u32 i = 0;
|
||||
|
||||
flag = 0;
|
||||
|
||||
@@ -33,18 +33,6 @@ init_adapter_dynamic_param_88xx(struct halmac_adapter *adapter);
|
||||
enum halmac_ret_status
|
||||
mount_api_88xx(struct halmac_adapter *adapter);
|
||||
|
||||
enum halmac_ret_status
|
||||
pre_init_system_cfg_88xx(struct halmac_adapter *adapter);
|
||||
|
||||
enum halmac_ret_status
|
||||
init_system_cfg_88xx(struct halmac_adapter *adapter);
|
||||
|
||||
enum halmac_ret_status
|
||||
init_edca_cfg_88xx(struct halmac_adapter *adapter);
|
||||
|
||||
enum halmac_ret_status
|
||||
init_wmac_cfg_88xx(struct halmac_adapter *adapter);
|
||||
|
||||
enum halmac_ret_status
|
||||
init_mac_cfg_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode);
|
||||
|
||||
|
||||
@@ -22,6 +22,7 @@
|
||||
|
||||
#define TXBF_CTRL_CFG (BIT_R_ENABLE_NDPA | BIT_USE_NDPA_PARAMETER | \
|
||||
BIT_R_EN_NDPA_INT | BIT_DIS_NDP_BFEN)
|
||||
#define CSI_RATE_MAP 0x292911
|
||||
|
||||
static void
|
||||
cfg_mu_bfee_88xx(struct halmac_adapter *adapter,
|
||||
@@ -153,7 +154,7 @@ cfg_mu_bfer_88xx(struct halmac_adapter *adapter,
|
||||
u32 gid_valid[6] = {0};
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
if (param->mu_tx_en == _FALSE) {
|
||||
if (param->mu_tx_en == 0) {
|
||||
HALMAC_REG_W8(REG_MU_TX_CTL,
|
||||
HALMAC_REG_R8(REG_MU_TX_CTL) & ~(BIT(7)));
|
||||
return;
|
||||
@@ -211,7 +212,7 @@ cfg_mu_bfer_88xx(struct halmac_adapter *adapter,
|
||||
|
||||
/*To validate the sounding successful MU STA and enable MU TX*/
|
||||
for (i = 0; i < 6; i++) {
|
||||
if (param->sounding_sts[i] == _TRUE)
|
||||
if (param->sounding_sts[i] == 1)
|
||||
mu_tbl_valid |= BIT(i);
|
||||
}
|
||||
HALMAC_REG_W8(REG_MU_TX_CTL, mu_tbl_valid | BIT(7));
|
||||
@@ -252,6 +253,16 @@ cfg_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role,
|
||||
HALMAC_REG_W8(REG_SND_PTCL_CTRL + 3, 0x26);
|
||||
HALMAC_REG_W8_CLR(REG_RXFLTMAP1, BIT(4));
|
||||
HALMAC_REG_W8_CLR(REG_RXFLTMAP4, BIT(4));
|
||||
#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
if (adapter->chip_id == HALMAC_CHIP_ID_8822C)
|
||||
HALMAC_REG_W32(REG_CSI_RRSR,
|
||||
BIT_CSI_RRSC_BITMAP(CSI_RATE_MAP) |
|
||||
BIT_OFDM_LEN_TH(0));
|
||||
else if (adapter->chip_id == HALMAC_CHIP_ID_8812F)
|
||||
HALMAC_REG_W32(REG_CSI_RRSR,
|
||||
BIT_CSI_RRSC_BITMAP(CSI_RATE_MAP) |
|
||||
BIT_OFDM_LEN_TH(3));
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
return HALMAC_RET_INVALID_SOUNDING_SETTING;
|
||||
@@ -740,7 +751,7 @@ fw_snding_88xx(struct halmac_adapter *adapter,
|
||||
|
||||
hdr_info.sub_cmd_id = SUB_CMD_ID_FW_SNDING;
|
||||
hdr_info.content_size = 8;
|
||||
hdr_info.ack = _TRUE;
|
||||
hdr_info.ack = 1;
|
||||
set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
|
||||
adapter->halmac_state.fw_snding_state.seq_num = seq_num;
|
||||
|
||||
@@ -767,7 +778,7 @@ snding_pkt_chk_88xx(struct halmac_adapter *adapter, u8 *pkt)
|
||||
|
||||
if (GET_TX_DESC_NDPA(pkt) == 0) {
|
||||
PLTFM_MSG_ERR("[ERR]txdesc ndpa = 0\n");
|
||||
return _FALSE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
data_rate = (u8)GET_TX_DESC_DATARATE(pkt);
|
||||
@@ -775,21 +786,21 @@ snding_pkt_chk_88xx(struct halmac_adapter *adapter, u8 *pkt)
|
||||
data_rate <= HALMAC_VHT_NSS2_MCS9)) {
|
||||
if (!(data_rate >= HALMAC_MCS8 && data_rate <= HALMAC_MCS15)) {
|
||||
PLTFM_MSG_ERR("[ERR]txdesc rate\n");
|
||||
return _FALSE;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (GET_TX_DESC_NAVUSEHDR(pkt) == 0) {
|
||||
PLTFM_MSG_ERR("[ERR]txdesc navusehdr = 0\n");
|
||||
return _FALSE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (GET_TX_DESC_USE_RATE(pkt) == 0) {
|
||||
PLTFM_MSG_ERR("[ERR]txdesc userate = 0\n");
|
||||
return _FALSE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return _TRUE;
|
||||
return 1;
|
||||
}
|
||||
|
||||
static enum halmac_cmd_construct_state
|
||||
|
||||
@@ -1,543 +0,0 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "halmac_pcie_88xx.h"
|
||||
|
||||
#if HALMAC_88XX_SUPPORT
|
||||
|
||||
/**
|
||||
* init_pcie_cfg_88xx() - init PCIe
|
||||
* @adapter : the adapter of halmac
|
||||
* Author : KaiYuan Chang
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
init_pcie_cfg_88xx(struct halmac_adapter *adapter)
|
||||
{
|
||||
if (adapter->intf != HALMAC_INTERFACE_PCIE)
|
||||
return HALMAC_RET_WRONG_INTF;
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* deinit_pcie_cfg_88xx() - deinit PCIE
|
||||
* @adapter : the adapter of halmac
|
||||
* Author : KaiYuan Chang
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
deinit_pcie_cfg_88xx(struct halmac_adapter *adapter)
|
||||
{
|
||||
if (adapter->intf != HALMAC_INTERFACE_PCIE)
|
||||
return HALMAC_RET_WRONG_INTF;
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* cfg_pcie_rx_agg_88xx() - config rx aggregation
|
||||
* @adapter : the adapter of halmac
|
||||
* @halmac_rx_agg_mode
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
cfg_pcie_rx_agg_88xx(struct halmac_adapter *adapter,
|
||||
struct halmac_rxagg_cfg *cfg)
|
||||
{
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* reg_r8_pcie_88xx() - read 1byte register
|
||||
* @adapter : the adapter of halmac
|
||||
* @offset : register offset
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
u8
|
||||
reg_r8_pcie_88xx(struct halmac_adapter *adapter, u32 offset)
|
||||
{
|
||||
return PLTFM_REG_R8(offset);
|
||||
}
|
||||
|
||||
/**
|
||||
* reg_w8_pcie_88xx() - write 1byte register
|
||||
* @adapter : the adapter of halmac
|
||||
* @offset : register offset
|
||||
* @value : register value
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
reg_w8_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
|
||||
{
|
||||
PLTFM_REG_W8(offset, value);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* reg_r16_pcie_88xx() - read 2byte register
|
||||
* @adapter : the adapter of halmac
|
||||
* @offset : register offset
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
u16
|
||||
reg_r16_pcie_88xx(struct halmac_adapter *adapter, u32 offset)
|
||||
{
|
||||
return PLTFM_REG_R16(offset);
|
||||
}
|
||||
|
||||
/**
|
||||
* reg_w16_pcie_88xx() - write 2byte register
|
||||
* @adapter : the adapter of halmac
|
||||
* @offset : register offset
|
||||
* @value : register value
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
reg_w16_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u16 value)
|
||||
{
|
||||
PLTFM_REG_W16(offset, value);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* reg_r32_pcie_88xx() - read 4byte register
|
||||
* @adapter : the adapter of halmac
|
||||
* @offset : register offset
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
u32
|
||||
reg_r32_pcie_88xx(struct halmac_adapter *adapter, u32 offset)
|
||||
{
|
||||
return PLTFM_REG_R32(offset);
|
||||
}
|
||||
|
||||
/**
|
||||
* reg_w32_pcie_88xx() - write 4byte register
|
||||
* @adapter : the adapter of halmac
|
||||
* @offset : register offset
|
||||
* @value : register value
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
reg_w32_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u32 value)
|
||||
{
|
||||
PLTFM_REG_W32(offset, value);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* cfg_txagg_pcie_align_88xx() -config sdio bus tx agg alignment
|
||||
* @adapter : the adapter of halmac
|
||||
* @enable : function enable(1)/disable(0)
|
||||
* @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
|
||||
* Author : Soar Tu
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
cfg_txagg_pcie_align_88xx(struct halmac_adapter *adapter, u8 enable,
|
||||
u16 align_size)
|
||||
{
|
||||
return HALMAC_RET_NOT_SUPPORT;
|
||||
}
|
||||
|
||||
/**
|
||||
* tx_allowed_pcie_88xx() - check tx status
|
||||
* @adapter : the adapter of halmac
|
||||
* @buf : tx packet, include txdesc
|
||||
* @size : tx packet size, include txdesc
|
||||
* Author : Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
tx_allowed_pcie_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
|
||||
{
|
||||
return HALMAC_RET_NOT_SUPPORT;
|
||||
}
|
||||
|
||||
/**
|
||||
* pcie_indirect_reg_r32_88xx() - read MAC reg by SDIO reg
|
||||
* @adapter : the adapter of halmac
|
||||
* @offset : register offset
|
||||
* Author : Soar
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
u32
|
||||
pcie_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset)
|
||||
{
|
||||
return 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* pcie_reg_rn_88xx() - read n byte register
|
||||
* @adapter : the adapter of halmac
|
||||
* @offset : register offset
|
||||
* @size : register value size
|
||||
* @value : register value
|
||||
* Author : Soar
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
pcie_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
|
||||
u8 *value)
|
||||
{
|
||||
return HALMAC_RET_NOT_SUPPORT;
|
||||
}
|
||||
|
||||
/**
|
||||
* set_pcie_bulkout_num_88xx() - inform bulk-out num
|
||||
* @adapter : the adapter of halmac
|
||||
* @num : usb bulk-out number
|
||||
* Author : KaiYuan Chang
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
set_pcie_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num)
|
||||
{
|
||||
return HALMAC_RET_NOT_SUPPORT;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_pcie_tx_addr_88xx() - get CMD53 addr for the TX packet
|
||||
* @adapter : the adapter of halmac
|
||||
* @buf : tx packet, include txdesc
|
||||
* @size : tx packet size
|
||||
* @cmd53_addr : cmd53 addr value
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
get_pcie_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
|
||||
u32 *cmd53_addr)
|
||||
{
|
||||
return HALMAC_RET_NOT_SUPPORT;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_pcie_bulkout_id_88xx() - get bulk out id for the TX packet
|
||||
* @adapter : the adapter of halmac
|
||||
* @buf : tx packet, include txdesc
|
||||
* @size : tx packet size
|
||||
* @id : usb bulk-out id
|
||||
* Author : KaiYuan Chang
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
get_pcie_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
|
||||
u8 *id)
|
||||
{
|
||||
return HALMAC_RET_NOT_SUPPORT;
|
||||
}
|
||||
|
||||
enum halmac_ret_status
|
||||
mdio_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed)
|
||||
{
|
||||
u8 tmp_u1b = 0;
|
||||
u32 cnt = 0;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
u8 real_addr = 0;
|
||||
|
||||
HALMAC_REG_W16(REG_MDIO_V1, data);
|
||||
|
||||
real_addr = (addr & 0x1F);
|
||||
HALMAC_REG_W8(REG_PCIE_MIX_CFG, real_addr);
|
||||
|
||||
if (speed == HAL_INTF_PHY_PCIE_GEN1) {
|
||||
if (addr < 0x20)
|
||||
HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x00);
|
||||
else
|
||||
HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x01);
|
||||
} else if (speed == HAL_INTF_PHY_PCIE_GEN2) {
|
||||
if (addr < 0x20)
|
||||
HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x02);
|
||||
else
|
||||
HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x03);
|
||||
} else {
|
||||
PLTFM_MSG_ERR("[ERR]Error Speed !\n");
|
||||
}
|
||||
|
||||
HALMAC_REG_W8_SET(REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1);
|
||||
|
||||
tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1;
|
||||
cnt = 20;
|
||||
|
||||
while (tmp_u1b && (cnt != 0)) {
|
||||
PLTFM_DELAY_US(10);
|
||||
tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1;
|
||||
cnt--;
|
||||
}
|
||||
|
||||
if (tmp_u1b) {
|
||||
PLTFM_MSG_ERR("[ERR]MDIO write fail!\n");
|
||||
return HALMAC_RET_FAIL;
|
||||
}
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
u16
|
||||
mdio_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed)
|
||||
{
|
||||
u16 ret = 0;
|
||||
u8 tmp_u1b = 0;
|
||||
u32 cnt = 0;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
u8 real_addr = 0;
|
||||
|
||||
real_addr = (addr & 0x1F);
|
||||
HALMAC_REG_W8(REG_PCIE_MIX_CFG, real_addr);
|
||||
|
||||
if (speed == HAL_INTF_PHY_PCIE_GEN1) {
|
||||
if (addr < 0x20)
|
||||
HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x00);
|
||||
else
|
||||
HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x01);
|
||||
} else if (speed == HAL_INTF_PHY_PCIE_GEN2) {
|
||||
if (addr < 0x20)
|
||||
HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x02);
|
||||
else
|
||||
HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x03);
|
||||
} else {
|
||||
PLTFM_MSG_ERR("[ERR]Error Speed !\n");
|
||||
}
|
||||
|
||||
HALMAC_REG_W8_SET(REG_PCIE_MIX_CFG, BIT_MDIO_RFLAG_V1);
|
||||
|
||||
tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1;
|
||||
cnt = 20;
|
||||
while (tmp_u1b && (cnt != 0)) {
|
||||
PLTFM_DELAY_US(10);
|
||||
tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1;
|
||||
cnt--;
|
||||
}
|
||||
|
||||
if (tmp_u1b) {
|
||||
ret = 0xFFFF;
|
||||
PLTFM_MSG_ERR("[ERR]MDIO read fail!\n");
|
||||
} else {
|
||||
ret = HALMAC_REG_R16(REG_MDIO_V1 + 2);
|
||||
PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
enum halmac_ret_status
|
||||
dbi_w32_88xx(struct halmac_adapter *adapter, u16 addr, u32 data)
|
||||
{
|
||||
u8 tmp_u1b = 0;
|
||||
u32 cnt = 0;
|
||||
u16 write_addr = 0;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
HALMAC_REG_W32(REG_DBI_WDATA_V1, data);
|
||||
|
||||
write_addr = ((addr & 0x0ffc) | (0x000F << 12));
|
||||
HALMAC_REG_W16(REG_DBI_FLAG_V1, write_addr);
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]Addr-W = %x\n", write_addr);
|
||||
|
||||
HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x01);
|
||||
tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
|
||||
|
||||
cnt = 20;
|
||||
while (tmp_u1b && (cnt != 0)) {
|
||||
PLTFM_DELAY_US(10);
|
||||
tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
|
||||
cnt--;
|
||||
}
|
||||
|
||||
if (tmp_u1b) {
|
||||
PLTFM_MSG_ERR("[ERR]DBI write fail!\n");
|
||||
return HALMAC_RET_FAIL;
|
||||
}
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
u32
|
||||
dbi_r32_88xx(struct halmac_adapter *adapter, u16 addr)
|
||||
{
|
||||
u16 read_addr = addr & 0x0ffc;
|
||||
u8 tmp_u1b = 0;
|
||||
u32 cnt = 0;
|
||||
u32 ret = 0;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
HALMAC_REG_W16(REG_DBI_FLAG_V1, read_addr);
|
||||
|
||||
HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x2);
|
||||
tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
|
||||
|
||||
cnt = 20;
|
||||
while (tmp_u1b && (cnt != 0)) {
|
||||
PLTFM_DELAY_US(10);
|
||||
tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
|
||||
cnt--;
|
||||
}
|
||||
|
||||
if (tmp_u1b) {
|
||||
ret = 0xFFFF;
|
||||
PLTFM_MSG_ERR("[ERR]DBI read fail!\n");
|
||||
} else {
|
||||
ret = HALMAC_REG_R32(REG_DBI_RDATA_V1);
|
||||
PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
enum halmac_ret_status
|
||||
dbi_w8_88xx(struct halmac_adapter *adapter, u16 addr, u8 data)
|
||||
{
|
||||
u8 tmp_u1b = 0;
|
||||
u32 cnt = 0;
|
||||
u16 write_addr = 0;
|
||||
u16 remainder = addr & (4 - 1);
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
HALMAC_REG_W8(REG_DBI_WDATA_V1 + remainder, data);
|
||||
|
||||
write_addr = ((addr & 0x0ffc) | (BIT(0) << (remainder + 12)));
|
||||
|
||||
HALMAC_REG_W16(REG_DBI_FLAG_V1, write_addr);
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]Addr-W = %x\n", write_addr);
|
||||
|
||||
HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x01);
|
||||
|
||||
tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
|
||||
|
||||
cnt = 20;
|
||||
while (tmp_u1b && (cnt != 0)) {
|
||||
PLTFM_DELAY_US(10);
|
||||
tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
|
||||
cnt--;
|
||||
}
|
||||
|
||||
if (tmp_u1b) {
|
||||
PLTFM_MSG_ERR("[ERR]DBI write fail!\n");
|
||||
return HALMAC_RET_FAIL;
|
||||
}
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
u8
|
||||
dbi_r8_88xx(struct halmac_adapter *adapter, u16 addr)
|
||||
{
|
||||
u16 read_addr = addr & 0x0ffc;
|
||||
u8 tmp_u1b = 0;
|
||||
u32 cnt = 0;
|
||||
u8 ret = 0;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
HALMAC_REG_W16(REG_DBI_FLAG_V1, read_addr);
|
||||
HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x2);
|
||||
|
||||
tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
|
||||
|
||||
cnt = 20;
|
||||
while (tmp_u1b && (cnt != 0)) {
|
||||
PLTFM_DELAY_US(10);
|
||||
tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
|
||||
cnt--;
|
||||
}
|
||||
|
||||
if (tmp_u1b) {
|
||||
ret = 0xFF;
|
||||
PLTFM_MSG_ERR("[ERR]DBI read fail!\n");
|
||||
} else {
|
||||
ret = HALMAC_REG_R8(REG_DBI_RDATA_V1 + (addr & (4 - 1)));
|
||||
PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
enum halmac_ret_status
|
||||
trxdma_check_idle_88xx(struct halmac_adapter *adapter)
|
||||
{
|
||||
u32 cnt = 0;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
/* Stop Tx & Rx DMA */
|
||||
HALMAC_REG_W32_SET(REG_RXPKT_NUM, BIT(18));
|
||||
HALMAC_REG_W16_SET(REG_PCIE_CTRL, ~(BIT(15) | BIT(8)));
|
||||
|
||||
/* Stop FW */
|
||||
HALMAC_REG_W16_CLR(REG_SYS_FUNC_EN, BIT(10));
|
||||
|
||||
/* Check Tx DMA is idle */
|
||||
cnt = 20;
|
||||
while ((HALMAC_REG_R8(REG_SYS_CFG5) & BIT(2)) == BIT(2)) {
|
||||
PLTFM_DELAY_US(10);
|
||||
cnt--;
|
||||
if (cnt == 0) {
|
||||
PLTFM_MSG_ERR("[ERR]Chk tx idle\n");
|
||||
return HALMAC_RET_POWER_OFF_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check Rx DMA is idle */
|
||||
cnt = 20;
|
||||
while ((HALMAC_REG_R32(REG_RXPKT_NUM) & BIT(17)) != BIT(17)) {
|
||||
PLTFM_DELAY_US(10);
|
||||
cnt--;
|
||||
if (cnt == 0) {
|
||||
PLTFM_MSG_ERR("[ERR]Chk rx idle\n");
|
||||
return HALMAC_RET_POWER_OFF_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
void
|
||||
en_ref_autok_88xx(struct halmac_adapter *adapter, u8 en)
|
||||
{
|
||||
if (en == 1)
|
||||
adapter->pcie_refautok_en = 1;
|
||||
else
|
||||
adapter->pcie_refautok_en = 0;
|
||||
}
|
||||
|
||||
#endif /* HALMAC_88XX_SUPPORT */
|
||||
@@ -1,102 +0,0 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _HALMAC_PCIE_88XX_H_
|
||||
#define _HALMAC_PCIE_88XX_H_
|
||||
|
||||
#include "../halmac_api.h"
|
||||
|
||||
#if HALMAC_88XX_SUPPORT
|
||||
|
||||
enum halmac_ret_status
|
||||
init_pcie_cfg_88xx(struct halmac_adapter *adapter);
|
||||
|
||||
enum halmac_ret_status
|
||||
deinit_pcie_cfg_88xx(struct halmac_adapter *adapter);
|
||||
|
||||
enum halmac_ret_status
|
||||
cfg_pcie_rx_agg_88xx(struct halmac_adapter *adapter,
|
||||
struct halmac_rxagg_cfg *cfg);
|
||||
|
||||
u8
|
||||
reg_r8_pcie_88xx(struct halmac_adapter *adapter, u32 offset);
|
||||
|
||||
enum halmac_ret_status
|
||||
reg_w8_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
|
||||
|
||||
u16
|
||||
reg_r16_pcie_88xx(struct halmac_adapter *adapter, u32 offset);
|
||||
|
||||
enum halmac_ret_status
|
||||
reg_w16_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u16 value);
|
||||
|
||||
u32
|
||||
reg_r32_pcie_88xx(struct halmac_adapter *adapter, u32 offset);
|
||||
|
||||
enum halmac_ret_status
|
||||
reg_w32_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u32 value);
|
||||
|
||||
enum halmac_ret_status
|
||||
cfg_txagg_pcie_align_88xx(struct halmac_adapter *adapter, u8 enable,
|
||||
u16 align_size);
|
||||
|
||||
enum halmac_ret_status
|
||||
tx_allowed_pcie_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
|
||||
|
||||
u32
|
||||
pcie_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset);
|
||||
|
||||
enum halmac_ret_status
|
||||
pcie_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
|
||||
u8 *value);
|
||||
|
||||
enum halmac_ret_status
|
||||
set_pcie_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num);
|
||||
|
||||
enum halmac_ret_status
|
||||
get_pcie_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
|
||||
u32 *cmd53_addr);
|
||||
|
||||
enum halmac_ret_status
|
||||
get_pcie_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
|
||||
u8 *id);
|
||||
|
||||
enum halmac_ret_status
|
||||
mdio_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed);
|
||||
|
||||
u16
|
||||
mdio_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed);
|
||||
|
||||
enum halmac_ret_status
|
||||
dbi_w32_88xx(struct halmac_adapter *adapter, u16 addr, u32 data);
|
||||
|
||||
u32
|
||||
dbi_r32_88xx(struct halmac_adapter *adapter, u16 addr);
|
||||
|
||||
enum halmac_ret_status
|
||||
dbi_w8_88xx(struct halmac_adapter *adapter, u16 addr, u8 data);
|
||||
|
||||
u8
|
||||
dbi_r8_88xx(struct halmac_adapter *adapter, u16 addr);
|
||||
|
||||
enum halmac_ret_status
|
||||
trxdma_check_idle_88xx(struct halmac_adapter *adapter);
|
||||
|
||||
void
|
||||
en_ref_autok_88xx(struct halmac_adapter *dapter, u8 en);
|
||||
|
||||
#endif /* HALMAC_88XX_SUPPORT */
|
||||
|
||||
#endif/* _HALMAC_PCIE_88XX_H_ */
|
||||
@@ -1,892 +0,0 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "halmac_sdio_88xx.h"
|
||||
#include "halmac_88xx_cfg.h"
|
||||
|
||||
#if HALMAC_88XX_SUPPORT
|
||||
|
||||
/* define the SDIO Bus CLK threshold */
|
||||
/* for avoiding CMD53 fails that result from SDIO CLK sync to ana_clk fail */
|
||||
#define SDIO_CLK_HIGH_SPEED_TH 50 /* 50MHz */
|
||||
#define SDIO_CLK_SPEED_MAX 208 /* 208MHz */
|
||||
|
||||
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static u8
|
||||
r_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 offset);
|
||||
|
||||
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static u32
|
||||
r_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 offset);
|
||||
|
||||
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static u32
|
||||
r8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr);
|
||||
|
||||
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static u32
|
||||
r16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr);
|
||||
|
||||
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static u32
|
||||
r32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr);
|
||||
|
||||
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static enum halmac_ret_status
|
||||
w_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
|
||||
enum halmac_io_size size);
|
||||
|
||||
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static enum halmac_ret_status
|
||||
w_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
|
||||
enum halmac_io_size size);
|
||||
|
||||
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static enum halmac_ret_status
|
||||
w8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val);
|
||||
|
||||
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static enum halmac_ret_status
|
||||
w16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val);
|
||||
|
||||
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static enum halmac_ret_status
|
||||
w32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val);
|
||||
|
||||
/**
|
||||
* init_sdio_cfg_88xx() - init SDIO
|
||||
* @adapter : the adapter of halmac
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
init_sdio_cfg_88xx(struct halmac_adapter *adapter)
|
||||
{
|
||||
u32 value32;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
if (adapter->intf != HALMAC_INTERFACE_SDIO)
|
||||
return HALMAC_RET_WRONG_INTF;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
HALMAC_REG_R32(REG_SDIO_FREE_TXPG);
|
||||
|
||||
value32 = HALMAC_REG_R32(REG_SDIO_TX_CTRL) & 0xFFFF;
|
||||
value32 &= ~(BIT_CMD_ERR_STOP_INT_EN | BIT_EN_MASK_TIMER |
|
||||
BIT_EN_RXDMA_MASK_INT);
|
||||
HALMAC_REG_W32(REG_SDIO_TX_CTRL, value32);
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* deinit_sdio_cfg_88xx() - deinit SDIO
|
||||
* @adapter : the adapter of halmac
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
deinit_sdio_cfg_88xx(struct halmac_adapter *adapter)
|
||||
{
|
||||
if (adapter->intf != HALMAC_INTERFACE_SDIO)
|
||||
return HALMAC_RET_WRONG_INTF;
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* cfg_sdio_rx_agg_88xx() - config rx aggregation
|
||||
* @adapter : the adapter of halmac
|
||||
* @halmac_rx_agg_mode
|
||||
* Author : KaiYuan Chang/Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
cfg_sdio_rx_agg_88xx(struct halmac_adapter *adapter,
|
||||
struct halmac_rxagg_cfg *cfg)
|
||||
{
|
||||
u8 value8;
|
||||
u8 size;
|
||||
u8 timeout;
|
||||
u8 agg_enable;
|
||||
u32 value32;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
agg_enable = HALMAC_REG_R8(REG_TXDMA_PQ_MAP);
|
||||
|
||||
switch (cfg->mode) {
|
||||
case HALMAC_RX_AGG_MODE_NONE:
|
||||
agg_enable &= ~(BIT_RXDMA_AGG_EN);
|
||||
break;
|
||||
case HALMAC_RX_AGG_MODE_DMA:
|
||||
case HALMAC_RX_AGG_MODE_USB:
|
||||
agg_enable |= BIT_RXDMA_AGG_EN;
|
||||
break;
|
||||
default:
|
||||
PLTFM_MSG_ERR("[ERR]unsupported mode\n");
|
||||
agg_enable &= ~BIT_RXDMA_AGG_EN;
|
||||
break;
|
||||
}
|
||||
|
||||
if (cfg->threshold.drv_define == _FALSE) {
|
||||
size = 0xFF;
|
||||
timeout = 0x01;
|
||||
} else {
|
||||
size = cfg->threshold.size;
|
||||
timeout = cfg->threshold.timeout;
|
||||
}
|
||||
|
||||
value32 = HALMAC_REG_R32(REG_RXDMA_AGG_PG_TH);
|
||||
if (cfg->threshold.size_limit_en == _FALSE)
|
||||
HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 & ~BIT_EN_PRE_CALC);
|
||||
else
|
||||
HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 | BIT_EN_PRE_CALC);
|
||||
|
||||
HALMAC_REG_W8(REG_TXDMA_PQ_MAP, agg_enable);
|
||||
HALMAC_REG_W16(REG_RXDMA_AGG_PG_TH,
|
||||
(u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO_V1)));
|
||||
|
||||
value8 = HALMAC_REG_R8(REG_RXDMA_MODE);
|
||||
if (0 != (agg_enable & BIT_RXDMA_AGG_EN))
|
||||
HALMAC_REG_W8(REG_RXDMA_MODE, value8 | BIT_DMA_MODE);
|
||||
else
|
||||
HALMAC_REG_W8(REG_RXDMA_MODE, value8 & ~(BIT_DMA_MODE));
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* sdio_reg_rn_88xx() - read n byte register
|
||||
* @adapter : the adapter of halmac
|
||||
* @offset : register offset
|
||||
* @halmac_size : register value size
|
||||
* @value : register value
|
||||
* Author : Soar
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
sdio_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
|
||||
u8 *value)
|
||||
{
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
if (0 == (offset & 0xFFFF0000)) {
|
||||
PLTFM_MSG_ERR("[ERR]offset 0x%x\n", offset);
|
||||
return HALMAC_RET_FAIL;
|
||||
}
|
||||
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
|
||||
if (status != HALMAC_RET_SUCCESS) {
|
||||
PLTFM_MSG_ERR("[ERR]convert offset\n");
|
||||
return status;
|
||||
}
|
||||
|
||||
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
|
||||
PLTFM_MSG_ERR("[ERR]power off\n");
|
||||
return HALMAC_RET_FAIL;
|
||||
}
|
||||
|
||||
PLTFM_SDIO_CMD53_RN(offset, size, value);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* cfg_txagg_sdio_align_88xx() -config sdio bus tx agg alignment
|
||||
* @adapter : the adapter of halmac
|
||||
* @enable : function enable(1)/disable(0)
|
||||
* @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
|
||||
* Author : Soar Tu
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
cfg_txagg_sdio_align_88xx(struct halmac_adapter *adapter, u8 enable,
|
||||
u16 align_size)
|
||||
{
|
||||
u8 i;
|
||||
u8 flag = 0;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
if (adapter->chip_id == HALMAC_CHIP_ID_8822B)
|
||||
return HALMAC_RET_NOT_SUPPORT;
|
||||
|
||||
if ((align_size & 0xF000) != 0) {
|
||||
PLTFM_MSG_ERR("[ERR]out of range\n");
|
||||
return HALMAC_RET_FAIL;
|
||||
}
|
||||
|
||||
for (i = 3; i <= 11; i++) {
|
||||
if (align_size == 1 << i) {
|
||||
flag = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (flag == 0) {
|
||||
PLTFM_MSG_ERR("[ERR]not 2^3 ~ 2^11\n");
|
||||
return HALMAC_RET_FAIL;
|
||||
}
|
||||
|
||||
adapter->hw_cfg_info.tx_align_size = align_size;
|
||||
|
||||
if (enable)
|
||||
HALMAC_REG_W16(REG_RQPN_CTRL_2, 0x8000 | align_size);
|
||||
else
|
||||
HALMAC_REG_W16(REG_RQPN_CTRL_2, align_size);
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* sdio_indirect_reg_r32_88xx() - read MAC reg by SDIO reg
|
||||
* @adapter : the adapter of halmac
|
||||
* @offset : register offset
|
||||
* Author : Soar
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
u32
|
||||
sdio_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset)
|
||||
{
|
||||
return r_indir_sdio_88xx(adapter, offset, HALMAC_IO_DWORD);
|
||||
}
|
||||
|
||||
/**
|
||||
* set_sdio_bulkout_num_88xx() - inform bulk-out num
|
||||
* @adapter : the adapter of halmac
|
||||
* @bulkout_num : usb bulk-out number
|
||||
* Author : KaiYuan Chang
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
set_sdio_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num)
|
||||
{
|
||||
return HALMAC_RET_NOT_SUPPORT;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_sdio_bulkout_id_88xx() - get bulk out id for the TX packet
|
||||
* @adapter : the adapter of halmac
|
||||
* @halmac_buf : tx packet, include txdesc
|
||||
* @halmac_size : tx packet size
|
||||
* @bulkout_id : usb bulk-out id
|
||||
* Author : KaiYuan Chang
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
get_sdio_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
|
||||
u8 *id)
|
||||
{
|
||||
return HALMAC_RET_NOT_SUPPORT;
|
||||
}
|
||||
|
||||
/**
|
||||
* sdio_cmd53_4byte_88xx() - cmd53 only for 4byte len register IO
|
||||
* @adapter : the adapter of halmac
|
||||
* @enable : 1->CMD53 only use in 4byte reg, 0 : No limitation
|
||||
* Author : Ivan Lin/KaiYuan Chang
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
sdio_cmd53_4byte_88xx(struct halmac_adapter *adapter,
|
||||
enum halmac_sdio_cmd53_4byte_mode mode)
|
||||
{
|
||||
if (adapter->intf != HALMAC_INTERFACE_SDIO)
|
||||
return HALMAC_RET_WRONG_INTF;
|
||||
|
||||
if (adapter->api_registry.sdio_cmd53_4byte_en == 0)
|
||||
return HALMAC_RET_NOT_SUPPORT;
|
||||
|
||||
adapter->sdio_cmd53_4byte = mode;
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* sdio_hw_info_88xx() - info sdio hw info
|
||||
* @adapter : the adapter of halmac
|
||||
* @HALMAC_SDIO_CMD53_4BYTE_MODE :
|
||||
* clock_speed : sdio bus clock. Unit -> MHz
|
||||
* spec_ver : sdio spec version
|
||||
* Author : Ivan Lin
|
||||
* Return : enum halmac_ret_status
|
||||
* More details of status code can be found in prototype document
|
||||
*/
|
||||
enum halmac_ret_status
|
||||
sdio_hw_info_88xx(struct halmac_adapter *adapter,
|
||||
struct halmac_sdio_hw_info *info)
|
||||
{
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
if (adapter->intf != HALMAC_INTERFACE_SDIO)
|
||||
return HALMAC_RET_WRONG_INTF;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]SDIO clock:%d, spec:%d\n",
|
||||
info->clock_speed, info->spec_ver);
|
||||
|
||||
if (info->clock_speed > SDIO_CLK_SPEED_MAX)
|
||||
return HALMAC_RET_SDIO_CLOCK_ERR;
|
||||
|
||||
if (info->clock_speed > SDIO_CLK_HIGH_SPEED_TH)
|
||||
adapter->sdio_hw_info.io_hi_speed_flag = 1;
|
||||
|
||||
adapter->sdio_hw_info.io_indir_flag = info->io_indir_flag;
|
||||
if (info->clock_speed > SDIO_CLK_HIGH_SPEED_TH &&
|
||||
adapter->sdio_hw_info.io_indir_flag == 0)
|
||||
PLTFM_MSG_WARN("[WARN]SDIO clock:%d, indir access is better\n",
|
||||
info->clock_speed);
|
||||
|
||||
adapter->sdio_hw_info.clock_speed = info->clock_speed;
|
||||
adapter->sdio_hw_info.spec_ver = info->spec_ver;
|
||||
adapter->sdio_hw_info.block_size = info->block_size;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
void
|
||||
cfg_sdio_tx_page_threshold_88xx(struct halmac_adapter *adapter,
|
||||
struct halmac_tx_page_threshold_info *info)
|
||||
{
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
u32 threshold = info->threshold;
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
|
||||
|
||||
if (info->enable == 1) {
|
||||
threshold = BIT(31) | threshold;
|
||||
PLTFM_MSG_TRACE("[TRACE]enable\n");
|
||||
} else {
|
||||
threshold = ~(BIT(31)) & threshold;
|
||||
PLTFM_MSG_TRACE("[TRACE]disable\n");
|
||||
}
|
||||
|
||||
switch (info->dma_queue_sel) {
|
||||
case HALMAC_MAP2_HQ:
|
||||
HALMAC_REG_W32(REG_TQPNT1, threshold);
|
||||
break;
|
||||
case HALMAC_MAP2_NQ:
|
||||
HALMAC_REG_W32(REG_TQPNT2, threshold);
|
||||
break;
|
||||
case HALMAC_MAP2_LQ:
|
||||
HALMAC_REG_W32(REG_TQPNT3, threshold);
|
||||
break;
|
||||
case HALMAC_MAP2_EXQ:
|
||||
HALMAC_REG_W32(REG_TQPNT4, threshold);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
}
|
||||
|
||||
enum halmac_ret_status
|
||||
cnv_to_sdio_bus_offset_88xx(struct halmac_adapter *adapter, u32 *offset)
|
||||
{
|
||||
switch ((*offset) & 0xFFFF0000) {
|
||||
case WLAN_IOREG_OFFSET:
|
||||
*offset &= HALMAC_WLAN_MAC_REG_MSK;
|
||||
*offset |= HALMAC_SDIO_CMD_ADDR_MAC_REG << 13;
|
||||
break;
|
||||
case SDIO_LOCAL_OFFSET:
|
||||
*offset &= HALMAC_SDIO_LOCAL_MSK;
|
||||
*offset |= HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13;
|
||||
break;
|
||||
default:
|
||||
*offset = 0xFFFFFFFF;
|
||||
PLTFM_MSG_ERR("[ERR]base address!!\n");
|
||||
return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL;
|
||||
}
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
enum halmac_ret_status
|
||||
leave_sdio_suspend_88xx(struct halmac_adapter *adapter)
|
||||
{
|
||||
u8 value8;
|
||||
u32 cnt;
|
||||
struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
value8 = HALMAC_REG_R8(REG_SDIO_HSUS_CTRL);
|
||||
HALMAC_REG_W8(REG_SDIO_HSUS_CTRL, value8 & ~(BIT(0)));
|
||||
|
||||
cnt = 10000;
|
||||
while (!(HALMAC_REG_R8(REG_SDIO_HSUS_CTRL) & 0x02)) {
|
||||
cnt--;
|
||||
if (cnt == 0)
|
||||
return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
|
||||
}
|
||||
|
||||
value8 = HALMAC_REG_R8(REG_HCI_OPT_CTRL + 2);
|
||||
if (adapter->sdio_hw_info.spec_ver == HALMAC_SDIO_SPEC_VER_3_00)
|
||||
HALMAC_REG_W8(REG_HCI_OPT_CTRL + 2, value8 | BIT(2));
|
||||
else
|
||||
HALMAC_REG_W8(REG_HCI_OPT_CTRL + 2, value8 & ~(BIT(2)));
|
||||
|
||||
return HALMAC_RET_SUCCESS;
|
||||
}
|
||||
|
||||
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static u8
|
||||
r_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 offset)
|
||||
{
|
||||
u8 value8, tmp, cnt = 50;
|
||||
u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
|
||||
u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, ®_cfg);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
|
||||
PLTFM_SDIO_CMD52_W(reg_cfg, (u8)offset);
|
||||
PLTFM_SDIO_CMD52_W(reg_cfg + 1, (u8)(offset >> 8));
|
||||
PLTFM_SDIO_CMD52_W(reg_cfg + 2, (u8)(BIT(3) | BIT(4)));
|
||||
|
||||
do {
|
||||
tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
|
||||
cnt--;
|
||||
} while (((tmp & BIT(4)) == 0) && (cnt > 0));
|
||||
|
||||
if (((cnt & BIT(4)) == 0) && cnt == 0)
|
||||
PLTFM_MSG_ERR("[ERR]sdio indirect CMD52 read\n");
|
||||
|
||||
value8 = PLTFM_SDIO_CMD52_R(reg_data);
|
||||
|
||||
return value8;
|
||||
}
|
||||
|
||||
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static u32
|
||||
r_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 offset)
|
||||
{
|
||||
u8 tmp, cnt = 50;
|
||||
u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
|
||||
u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
union {
|
||||
u32 dword;
|
||||
u8 byte[4];
|
||||
} value32 = { 0x00000000 };
|
||||
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, ®_cfg);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
|
||||
PLTFM_SDIO_CMD53_W32(reg_cfg, offset | BIT(19) | BIT(20));
|
||||
|
||||
do {
|
||||
tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
|
||||
cnt--;
|
||||
} while (((tmp & BIT(4)) == 0) && (cnt > 0));
|
||||
|
||||
if (((cnt & BIT(4)) == 0) && cnt == 0)
|
||||
PLTFM_MSG_ERR("[ERR]sdio indirect CMD53 read\n");
|
||||
|
||||
value32.dword = PLTFM_SDIO_CMD53_R32(reg_data);
|
||||
|
||||
return value32.dword;
|
||||
}
|
||||
|
||||
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static u32
|
||||
r8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr)
|
||||
{
|
||||
union {
|
||||
u32 dword;
|
||||
u8 byte[4];
|
||||
} val = { 0x00000000 };
|
||||
|
||||
if (adapter->pwr_off_flow_flag == 1 ||
|
||||
adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
|
||||
val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
|
||||
val.dword = rtk_le32_to_cpu(val.dword);
|
||||
} else {
|
||||
val.dword = r_indir_cmd53_88xx(adapter, adr);
|
||||
}
|
||||
|
||||
return val.dword;
|
||||
}
|
||||
|
||||
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static u32
|
||||
r16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr)
|
||||
{
|
||||
u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
union {
|
||||
u32 dword;
|
||||
u8 byte[4];
|
||||
} val = { 0x00000000 };
|
||||
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
|
||||
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
|
||||
if (0 != (adr & (2 - 1))) {
|
||||
val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
|
||||
val.byte[1] = r_indir_cmd52_88xx(adapter, adr + 1);
|
||||
} else {
|
||||
val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
|
||||
val.byte[1] = PLTFM_SDIO_CMD52_R(reg_data + 1);
|
||||
}
|
||||
val.dword = rtk_le32_to_cpu(val.dword);
|
||||
} else {
|
||||
if (0 != (adr & (2 - 1))) {
|
||||
val.byte[0] = (u8)r_indir_cmd53_88xx(adapter, adr);
|
||||
val.byte[1] = (u8)r_indir_cmd53_88xx(adapter, adr + 1);
|
||||
val.dword = rtk_le32_to_cpu(val.dword);
|
||||
} else {
|
||||
val.dword = r_indir_cmd53_88xx(adapter, adr);
|
||||
}
|
||||
}
|
||||
return val.dword;
|
||||
}
|
||||
|
||||
/*only for r_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static u32
|
||||
r32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr)
|
||||
{
|
||||
u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
union {
|
||||
u32 dword;
|
||||
u8 byte[4];
|
||||
} val = { 0x00000000 };
|
||||
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
|
||||
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
|
||||
if (0 != (adr & (4 - 1))) {
|
||||
val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
|
||||
val.byte[1] = r_indir_cmd52_88xx(adapter, adr + 1);
|
||||
val.byte[2] = r_indir_cmd52_88xx(adapter, adr + 2);
|
||||
val.byte[3] = r_indir_cmd52_88xx(adapter, adr + 3);
|
||||
} else {
|
||||
val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
|
||||
val.byte[1] = PLTFM_SDIO_CMD52_R(reg_data + 1);
|
||||
val.byte[2] = PLTFM_SDIO_CMD52_R(reg_data + 2);
|
||||
val.byte[3] = PLTFM_SDIO_CMD52_R(reg_data + 3);
|
||||
}
|
||||
val.dword = rtk_le32_to_cpu(val.dword);
|
||||
} else {
|
||||
if (0 != (adr & (4 - 1))) {
|
||||
val.byte[0] = (u8)r_indir_cmd53_88xx(adapter, adr);
|
||||
val.byte[1] = (u8)r_indir_cmd53_88xx(adapter, adr + 1);
|
||||
val.byte[2] = (u8)r_indir_cmd53_88xx(adapter, adr + 2);
|
||||
val.byte[3] = (u8)r_indir_cmd53_88xx(adapter, adr + 3);
|
||||
val.dword = rtk_le32_to_cpu(val.dword);
|
||||
} else {
|
||||
val.dword = r_indir_cmd53_88xx(adapter, adr);
|
||||
}
|
||||
}
|
||||
return val.dword;
|
||||
}
|
||||
|
||||
u32
|
||||
r_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr,
|
||||
enum halmac_io_size size)
|
||||
{
|
||||
u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
union {
|
||||
u32 dword;
|
||||
u8 byte[4];
|
||||
} val = { 0x00000000 };
|
||||
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
|
||||
PLTFM_MUTEX_LOCK(&adapter->sdio_indir_mutex);
|
||||
|
||||
switch (size) {
|
||||
case HALMAC_IO_BYTE:
|
||||
val.dword = r8_indir_sdio_88xx(adapter, adr);
|
||||
break;
|
||||
case HALMAC_IO_WORD:
|
||||
val.dword = r16_indir_sdio_88xx(adapter, adr);
|
||||
break;
|
||||
case HALMAC_IO_DWORD:
|
||||
val.dword = r32_indir_sdio_88xx(adapter, adr);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
PLTFM_MUTEX_UNLOCK(&adapter->sdio_indir_mutex);
|
||||
|
||||
return val.dword;
|
||||
}
|
||||
|
||||
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static enum halmac_ret_status
|
||||
w_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
|
||||
enum halmac_io_size size)
|
||||
{
|
||||
u8 tmp, cnt = 50;
|
||||
u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
|
||||
u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, ®_cfg);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
|
||||
PLTFM_SDIO_CMD52_W(reg_cfg, (u8)adr);
|
||||
PLTFM_SDIO_CMD52_W(reg_cfg + 1, (u8)(adr >> 8));
|
||||
switch (size) {
|
||||
case HALMAC_IO_BYTE:
|
||||
PLTFM_SDIO_CMD52_W(reg_data, (u8)val);
|
||||
PLTFM_SDIO_CMD52_W(reg_cfg + 2, (u8)(BIT(2) | BIT(4)));
|
||||
break;
|
||||
case HALMAC_IO_WORD:
|
||||
PLTFM_SDIO_CMD52_W(reg_data, (u8)val);
|
||||
PLTFM_SDIO_CMD52_W(reg_data + 1, (u8)(val >> 8));
|
||||
PLTFM_SDIO_CMD52_W(reg_cfg + 2,
|
||||
(u8)(BIT(0) | BIT(2) | BIT(4)));
|
||||
break;
|
||||
case HALMAC_IO_DWORD:
|
||||
PLTFM_SDIO_CMD52_W(reg_data, (u8)val);
|
||||
PLTFM_SDIO_CMD52_W(reg_data + 1, (u8)(val >> 8));
|
||||
PLTFM_SDIO_CMD52_W(reg_data + 2, (u8)(val >> 16));
|
||||
PLTFM_SDIO_CMD52_W(reg_data + 3, (u8)(val >> 24));
|
||||
PLTFM_SDIO_CMD52_W(reg_cfg + 2,
|
||||
(u8)(BIT(1) | BIT(2) | BIT(4)));
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
do {
|
||||
tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
|
||||
cnt--;
|
||||
} while (((tmp & BIT(4)) == 0) && (cnt > 0));
|
||||
|
||||
if (((cnt & BIT(4)) == 0) && cnt == 0)
|
||||
PLTFM_MSG_ERR("[ERR]sdio indirect CMD52 write\n");
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static enum halmac_ret_status
|
||||
w_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
|
||||
enum halmac_io_size size)
|
||||
{
|
||||
u8 tmp, cnt = 50;
|
||||
u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
|
||||
u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
|
||||
u32 value32 = 0;
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, ®_cfg);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
|
||||
switch (size) {
|
||||
case HALMAC_IO_BYTE:
|
||||
value32 = adr | BIT(18) | BIT(20);
|
||||
break;
|
||||
case HALMAC_IO_WORD:
|
||||
value32 = adr | BIT(16) | BIT(18) | BIT(20);
|
||||
break;
|
||||
case HALMAC_IO_DWORD:
|
||||
value32 = adr | BIT(17) | BIT(18) | BIT(20);
|
||||
break;
|
||||
default:
|
||||
return HALMAC_RET_FAIL;
|
||||
}
|
||||
|
||||
PLTFM_SDIO_CMD53_W32(reg_data, val);
|
||||
PLTFM_SDIO_CMD53_W32(reg_cfg, value32);
|
||||
|
||||
do {
|
||||
tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
|
||||
cnt--;
|
||||
} while (((tmp & BIT(4)) == 0) && (cnt > 0));
|
||||
|
||||
if (((cnt & BIT(4)) == 0) && cnt == 0)
|
||||
PLTFM_MSG_ERR("[ERR]sdio indirect CMD53 read\n");
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static enum halmac_ret_status
|
||||
w8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val)
|
||||
{
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
if (adapter->pwr_off_flow_flag == 1 ||
|
||||
adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF)
|
||||
status = w_indir_cmd52_88xx(adapter, adr, val, HALMAC_IO_BYTE);
|
||||
else
|
||||
status = w_indir_cmd53_88xx(adapter, adr, val, HALMAC_IO_BYTE);
|
||||
return status;
|
||||
}
|
||||
|
||||
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static enum halmac_ret_status
|
||||
w16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val)
|
||||
{
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
|
||||
if (0 != (adr & (2 - 1))) {
|
||||
status = w_indir_cmd52_88xx(adapter, adr, val,
|
||||
HALMAC_IO_BYTE);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
status = w_indir_cmd52_88xx(adapter, adr + 1, val >> 8,
|
||||
HALMAC_IO_BYTE);
|
||||
} else {
|
||||
status = w_indir_cmd52_88xx(adapter, adr, val,
|
||||
HALMAC_IO_WORD);
|
||||
}
|
||||
} else {
|
||||
if (0 != (adr & (2 - 1))) {
|
||||
status = w_indir_cmd53_88xx(adapter, adr, val,
|
||||
HALMAC_IO_BYTE);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
status = w_indir_cmd53_88xx(adapter, adr + 1, val >> 8,
|
||||
HALMAC_IO_BYTE);
|
||||
} else {
|
||||
status = w_indir_cmd53_88xx(adapter, adr, val,
|
||||
HALMAC_IO_WORD);
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/*only for w_indir_sdio_88xx !!, Soar 20171222*/
|
||||
static enum halmac_ret_status
|
||||
w32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val)
|
||||
{
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
|
||||
if (0 != (adr & (4 - 1))) {
|
||||
status = w_indir_cmd52_88xx(adapter, adr, val,
|
||||
HALMAC_IO_BYTE);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
status = w_indir_cmd52_88xx(adapter, adr + 1, val >> 8,
|
||||
HALMAC_IO_BYTE);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
status = w_indir_cmd52_88xx(adapter, adr + 2, val >> 16,
|
||||
HALMAC_IO_BYTE);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
status = w_indir_cmd52_88xx(adapter, adr + 3, val >> 24,
|
||||
HALMAC_IO_BYTE);
|
||||
} else {
|
||||
status = w_indir_cmd52_88xx(adapter, adr, val,
|
||||
HALMAC_IO_DWORD);
|
||||
}
|
||||
} else {
|
||||
if (0 != (adr & (4 - 1))) {
|
||||
status = w_indir_cmd53_88xx(adapter, adr, val,
|
||||
HALMAC_IO_BYTE);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
status = w_indir_cmd53_88xx(adapter, adr + 1, val >> 8,
|
||||
HALMAC_IO_BYTE);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
status = w_indir_cmd53_88xx(adapter, adr + 2, val >> 16,
|
||||
HALMAC_IO_BYTE);
|
||||
if (status != HALMAC_RET_SUCCESS)
|
||||
return status;
|
||||
status = w_indir_cmd53_88xx(adapter, adr + 3, val >> 24,
|
||||
HALMAC_IO_BYTE);
|
||||
} else {
|
||||
status = w_indir_cmd53_88xx(adapter, adr, val,
|
||||
HALMAC_IO_DWORD);
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
enum halmac_ret_status
|
||||
w_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
|
||||
enum halmac_io_size size)
|
||||
{
|
||||
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
||||
|
||||
PLTFM_MUTEX_LOCK(&adapter->sdio_indir_mutex);
|
||||
|
||||
switch (size) {
|
||||
case HALMAC_IO_BYTE:
|
||||
status = w8_indir_sdio_88xx(adapter, adr, val);
|
||||
break;
|
||||
case HALMAC_IO_WORD:
|
||||
status = w16_indir_sdio_88xx(adapter, adr, val);
|
||||
break;
|
||||
case HALMAC_IO_DWORD:
|
||||
status = w32_indir_sdio_88xx(adapter, adr, val);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
PLTFM_MUTEX_UNLOCK(&adapter->sdio_indir_mutex);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
#endif /* HALMAC_88XX_SUPPORT */
|
||||
@@ -1,79 +0,0 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _HALMAC_SDIO_88XX_H_
|
||||
#define _HALMAC_SDIO_88XX_H_
|
||||
|
||||
#include "../halmac_api.h"
|
||||
|
||||
#if HALMAC_88XX_SUPPORT
|
||||
|
||||
enum halmac_ret_status
|
||||
init_sdio_cfg_88xx(struct halmac_adapter *adapter);
|
||||
|
||||
enum halmac_ret_status
|
||||
deinit_sdio_cfg_88xx(struct halmac_adapter *adapter);
|
||||
|
||||
enum halmac_ret_status
|
||||
cfg_sdio_rx_agg_88xx(struct halmac_adapter *adapter,
|
||||
struct halmac_rxagg_cfg *cfg);
|
||||
|
||||
enum halmac_ret_status
|
||||
cfg_txagg_sdio_align_88xx(struct halmac_adapter *adapter, u8 enable,
|
||||
u16 align_size);
|
||||
|
||||
u32
|
||||
sdio_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset);
|
||||
|
||||
enum halmac_ret_status
|
||||
sdio_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
|
||||
u8 *value);
|
||||
|
||||
enum halmac_ret_status
|
||||
set_sdio_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num);
|
||||
|
||||
enum halmac_ret_status
|
||||
get_sdio_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
|
||||
u8 *id);
|
||||
|
||||
enum halmac_ret_status
|
||||
sdio_cmd53_4byte_88xx(struct halmac_adapter *adapter,
|
||||
enum halmac_sdio_cmd53_4byte_mode mode);
|
||||
|
||||
enum halmac_ret_status
|
||||
sdio_hw_info_88xx(struct halmac_adapter *adapter,
|
||||
struct halmac_sdio_hw_info *info);
|
||||
|
||||
void
|
||||
cfg_sdio_tx_page_threshold_88xx(struct halmac_adapter *adapter,
|
||||
struct halmac_tx_page_threshold_info *info);
|
||||
|
||||
enum halmac_ret_status
|
||||
cnv_to_sdio_bus_offset_88xx(struct halmac_adapter *adapter, u32 *offset);
|
||||
|
||||
enum halmac_ret_status
|
||||
leave_sdio_suspend_88xx(struct halmac_adapter *adapter);
|
||||
|
||||
u32
|
||||
r_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr,
|
||||
enum halmac_io_size size);
|
||||
|
||||
enum halmac_ret_status
|
||||
w_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
|
||||
enum halmac_io_size size);
|
||||
|
||||
#endif /* HALMAC_88XX_SUPPORT */
|
||||
|
||||
#endif/* _HALMAC_SDIO_88XX_H_ */
|
||||
@@ -15,7 +15,7 @@
|
||||
|
||||
#include "halmac_usb_88xx.h"
|
||||
|
||||
#if HALMAC_88XX_SUPPORT
|
||||
#if (HALMAC_88XX_SUPPORT && HALMAC_USB_SUPPORT)
|
||||
|
||||
enum usb_burst_size {
|
||||
USB_BURST_SIZE_3_0 = 0x0,
|
||||
@@ -53,8 +53,7 @@ init_usb_cfg_88xx(struct halmac_adapter *adapter)
|
||||
}
|
||||
|
||||
HALMAC_REG_W8(REG_RXDMA_MODE, value8);
|
||||
HALMAC_REG_W16(REG_TXDMA_OFFSET_CHK,
|
||||
HALMAC_REG_R16(REG_TXDMA_OFFSET_CHK) | BIT_DROP_DATA_EN);
|
||||
HALMAC_REG_W16_SET(REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN);
|
||||
|
||||
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
||||
|
||||
@@ -117,7 +116,7 @@ cfg_usb_rx_agg_88xx(struct halmac_adapter *adapter,
|
||||
break;
|
||||
}
|
||||
|
||||
if (cfg->threshold.drv_define == _FALSE) {
|
||||
if (cfg->threshold.drv_define == 0) {
|
||||
if (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20) {
|
||||
/* usb3.0 */
|
||||
size = 0x5;
|
||||
@@ -133,7 +132,7 @@ cfg_usb_rx_agg_88xx(struct halmac_adapter *adapter,
|
||||
}
|
||||
|
||||
value32 = HALMAC_REG_R32(REG_RXDMA_AGG_PG_TH);
|
||||
if (cfg->threshold.size_limit_en == _FALSE)
|
||||
if (cfg->threshold.size_limit_en == 0)
|
||||
HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 & ~BIT_EN_PRE_CALC);
|
||||
else
|
||||
HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 | BIT_EN_PRE_CALC);
|
||||
@@ -159,11 +158,7 @@ cfg_usb_rx_agg_88xx(struct halmac_adapter *adapter,
|
||||
u8
|
||||
reg_r8_usb_88xx(struct halmac_adapter *adapter, u32 offset)
|
||||
{
|
||||
u8 value8;
|
||||
|
||||
value8 = PLTFM_REG_R8(offset);
|
||||
|
||||
return value8;
|
||||
return PLTFM_REG_R8(offset);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -194,11 +189,7 @@ reg_w8_usb_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
|
||||
u16
|
||||
reg_r16_usb_88xx(struct halmac_adapter *adapter, u32 offset)
|
||||
{
|
||||
u16 value16;
|
||||
|
||||
value16 = PLTFM_REG_R16(offset);
|
||||
|
||||
return value16;
|
||||
return PLTFM_REG_R16(offset);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -229,11 +220,7 @@ reg_w16_usb_88xx(struct halmac_adapter *adapter, u32 offset, u16 value)
|
||||
u32
|
||||
reg_r32_usb_88xx(struct halmac_adapter *adapter, u32 offset)
|
||||
{
|
||||
u32 value32;
|
||||
|
||||
value32 = PLTFM_REG_R32(offset);
|
||||
|
||||
return value32;
|
||||
return PLTFM_REG_R32(offset);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -442,9 +429,9 @@ set_usb_mode_88xx(struct halmac_adapter *adapter, enum halmac_usb_mode mode)
|
||||
cur_mode = (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20) ?
|
||||
HALMAC_USB_MODE_U3 : HALMAC_USB_MODE_U2;
|
||||
|
||||
/*check if HW supports usb2_usb3 switch*/
|
||||
/* check if HW supports usb2_usb3 switch */
|
||||
usb_tmp = HALMAC_REG_R32(REG_PAD_CTRL2);
|
||||
if (_FALSE == (BIT_GET_USB23_SW_MODE_V1(usb_tmp) |
|
||||
if (0 == (BIT_GET_USB23_SW_MODE_V1(usb_tmp) |
|
||||
(usb_tmp & BIT_USB3_USB2_TRANSITION))) {
|
||||
PLTFM_MSG_ERR("[ERR]u2/u3 switch\n");
|
||||
return HALMAC_RET_USB2_3_SWITCH_UNSUPPORT;
|
||||
@@ -512,7 +499,7 @@ usbphy_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed)
|
||||
HALMAC_REG_W8(0xff0c, addr | BIT(6));
|
||||
value = (u16)(HALMAC_REG_R32(0xff0c) >> 8);
|
||||
} else if (speed == HAL_INTF_PHY_USB2) {
|
||||
if (addr >= 0xE0 && addr <= 0xFF)
|
||||
if (addr >= 0xE0)
|
||||
addr -= 0x20;
|
||||
if (addr >= 0xC0 && addr <= 0xDF) {
|
||||
HALMAC_REG_W8(0xfe40, addr);
|
||||
|
||||
@@ -18,7 +18,7 @@
|
||||
|
||||
#include "../halmac_api.h"
|
||||
|
||||
#if HALMAC_88XX_SUPPORT
|
||||
#if (HALMAC_88XX_SUPPORT && HALMAC_USB_SUPPORT)
|
||||
|
||||
enum halmac_ret_status
|
||||
init_usb_cfg_88xx(struct halmac_adapter *adapter);
|
||||
|
||||
@@ -41,10 +41,13 @@
|
||||
#endif
|
||||
#if HALMAC_88XX_V1_SUPPORT
|
||||
#include "halmac_88xx_v1/halmac_init_88xx_v1.h"
|
||||
#if defined(HALMAC_DATA_CPU_EN)
|
||||
#include "halmac_88xxd_v1/halmac_init_88xxd_v1.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
/* Remove halmac_*/
|
||||
|
||||
enum chip_id_hw_def {
|
||||
CHIP_ID_HW_DEF_8723A = 0x01,
|
||||
CHIP_ID_HW_DEF_8188E = 0x02,
|
||||
@@ -63,6 +66,7 @@ enum chip_id_hw_def {
|
||||
CHIP_ID_HW_DEF_8723D = 0x0F,
|
||||
CHIP_ID_HW_DEF_8814B = 0x11,
|
||||
CHIP_ID_HW_DEF_8822C = 0x13,
|
||||
CHIP_ID_HW_DEF_8812F = 0x14,
|
||||
CHIP_ID_HW_DEF_UNDEFINE = 0x7F,
|
||||
CHIP_ID_HW_DEF_PS = 0xEA,
|
||||
};
|
||||
@@ -84,7 +88,7 @@ pltfm_reg_w8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
|
||||
u32 offset, u8 data);
|
||||
|
||||
static u8
|
||||
pltfm_reg_r_indir_sdio(VOID *drv_adapter, struct halmac_platform_api *pltfm_api,
|
||||
pltfm_reg_r_indir_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
|
||||
u32 offset);
|
||||
|
||||
static enum halmac_ret_status
|
||||
@@ -170,7 +174,8 @@ halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api,
|
||||
#if HALMAC_88XX_SUPPORT
|
||||
if (adapter->chip_id == HALMAC_CHIP_ID_8822B ||
|
||||
adapter->chip_id == HALMAC_CHIP_ID_8821C ||
|
||||
adapter->chip_id == HALMAC_CHIP_ID_8822C) {
|
||||
adapter->chip_id == HALMAC_CHIP_ID_8822C ||
|
||||
adapter->chip_id == HALMAC_CHIP_ID_8812F) {
|
||||
init_adapter_param_88xx(adapter);
|
||||
status = mount_api_88xx(adapter);
|
||||
}
|
||||
@@ -181,6 +186,12 @@ halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api,
|
||||
init_adapter_param_88xx_v1(adapter);
|
||||
status = mount_api_88xx_v1(adapter);
|
||||
}
|
||||
#if defined(HALMAC_DATA_CPU_EN)
|
||||
if (adapter->chip_id == HALMAC_CHIP_ID_8814B) {
|
||||
init_adapter_param_88xxd_v1(adapter);
|
||||
status = mount_api_88xxd_v1(adapter);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#else
|
||||
@@ -213,6 +224,13 @@ halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api,
|
||||
}
|
||||
#endif
|
||||
|
||||
#if HALMAC_8812F_SUPPORT
|
||||
if (adapter->chip_id == HALMAC_CHIP_ID_8812F) {
|
||||
init_adapter_param_win8812f(adapter);
|
||||
status = mount_api_win8812f(adapter);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
*halmac_api = (struct halmac_api *)adapter->halmac_api;
|
||||
|
||||
@@ -496,6 +514,8 @@ get_chip_info(void *drv_adapter, struct halmac_platform_api *pltfm_api,
|
||||
adapter->chip_id = HALMAC_CHIP_ID_8197F;
|
||||
} else if (chip_id == CHIP_ID_HW_DEF_8822C) {
|
||||
adapter->chip_id = HALMAC_CHIP_ID_8822C;
|
||||
} else if (chip_id == CHIP_ID_HW_DEF_8812F) {
|
||||
adapter->chip_id = HALMAC_CHIP_ID_8812F;
|
||||
} else {
|
||||
adapter->chip_id = HALMAC_CHIP_ID_UNDEFINE;
|
||||
PLTFM_MSG_ERR("[ERR]Chip id is undefined\n");
|
||||
@@ -544,7 +564,7 @@ pltfm_reg_w8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
|
||||
}
|
||||
|
||||
static u8
|
||||
pltfm_reg_r_indir_sdio(VOID *drv_adapter, struct halmac_platform_api *pltfm_api,
|
||||
pltfm_reg_r_indir_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
|
||||
u32 offset)
|
||||
{
|
||||
u8 value8, tmp, cnt = 50;
|
||||
|
||||
@@ -19,13 +19,14 @@
|
||||
#define HALMAC_SVN_VER "11692M"
|
||||
|
||||
#define HALMAC_MAJOR_VER 0x0001
|
||||
#define HALMAC_PROTOTYPE_VER 0x0004
|
||||
#define HALMAC_MINOR_VER 0x0008
|
||||
#define HALMAC_PATCH_VER 0x0003
|
||||
#define HALMAC_PROTOTYPE_VER 0x0005
|
||||
#define HALMAC_MINOR_VER 0x0014
|
||||
#define HALMAC_PATCH_VER 0x0015
|
||||
|
||||
#define HALMAC_88XX_SUPPORT (HALMAC_8821C_SUPPORT || \
|
||||
HALMAC_8822B_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define HALMAC_88XX_V1_SUPPORT HALMAC_8814B_SUPPORT
|
||||
|
||||
|
||||
25505
hal/halmac/halmac_bit2.h
25505
hal/halmac/halmac_bit2.h
File diff suppressed because it is too large
Load Diff
@@ -17026,17 +17026,19 @@
|
||||
(BIT_CLEAR_R_WMAC_MASK_LA_MAC_8197F(x) | \
|
||||
BIT_R_WMAC_MASK_LA_MAC_8197F(v))
|
||||
|
||||
#define BIT_SHIFT_DUMP_OK_ADDR_8197F 16
|
||||
#define BIT_MASK_DUMP_OK_ADDR_8197F 0xffff
|
||||
#define BIT_DUMP_OK_ADDR_8197F(x) \
|
||||
(((x) & BIT_MASK_DUMP_OK_ADDR_8197F) << BIT_SHIFT_DUMP_OK_ADDR_8197F)
|
||||
#define BITS_DUMP_OK_ADDR_8197F \
|
||||
(BIT_MASK_DUMP_OK_ADDR_8197F << BIT_SHIFT_DUMP_OK_ADDR_8197F)
|
||||
#define BIT_CLEAR_DUMP_OK_ADDR_8197F(x) ((x) & (~BITS_DUMP_OK_ADDR_8197F))
|
||||
#define BIT_GET_DUMP_OK_ADDR_8197F(x) \
|
||||
(((x) >> BIT_SHIFT_DUMP_OK_ADDR_8197F) & BIT_MASK_DUMP_OK_ADDR_8197F)
|
||||
#define BIT_SET_DUMP_OK_ADDR_8197F(x, v) \
|
||||
(BIT_CLEAR_DUMP_OK_ADDR_8197F(x) | BIT_DUMP_OK_ADDR_8197F(v))
|
||||
#define BIT_SHIFT_DUMP_OK_ADDR_V1_8197F 15
|
||||
#define BIT_MASK_DUMP_OK_ADDR_V1_8197F 0x1ffff
|
||||
#define BIT_DUMP_OK_ADDR_V1_8197F(x) \
|
||||
(((x) & BIT_MASK_DUMP_OK_ADDR_V1_8197F) \
|
||||
<< BIT_SHIFT_DUMP_OK_ADDR_V1_8197F)
|
||||
#define BITS_DUMP_OK_ADDR_V1_8197F \
|
||||
(BIT_MASK_DUMP_OK_ADDR_V1_8197F << BIT_SHIFT_DUMP_OK_ADDR_V1_8197F)
|
||||
#define BIT_CLEAR_DUMP_OK_ADDR_V1_8197F(x) ((x) & (~BITS_DUMP_OK_ADDR_V1_8197F))
|
||||
#define BIT_GET_DUMP_OK_ADDR_V1_8197F(x) \
|
||||
(((x) >> BIT_SHIFT_DUMP_OK_ADDR_V1_8197F) & \
|
||||
BIT_MASK_DUMP_OK_ADDR_V1_8197F)
|
||||
#define BIT_SET_DUMP_OK_ADDR_V1_8197F(x, v) \
|
||||
(BIT_CLEAR_DUMP_OK_ADDR_V1_8197F(x) | BIT_DUMP_OK_ADDR_V1_8197F(v))
|
||||
|
||||
#define BIT_SHIFT_R_TRIG_TIME_SEL_8197F 8
|
||||
#define BIT_MASK_R_TRIG_TIME_SEL_8197F 0x7f
|
||||
@@ -17290,4 +17292,77 @@
|
||||
|
||||
/* 2 REG_RTS_ADDRESS_1_8197F */
|
||||
|
||||
/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8197F */
|
||||
#define BIT_LTECOEX_ACCESS_START_V1_8197F BIT(31)
|
||||
#define BIT_LTECOEX_WRITE_MODE_V1_8197F BIT(30)
|
||||
#define BIT_LTECOEX_READY_BIT_V1_8197F BIT(29)
|
||||
|
||||
#define BIT_SHIFT_WRITE_BYTE_EN_V1_8197F 16
|
||||
#define BIT_MASK_WRITE_BYTE_EN_V1_8197F 0xf
|
||||
#define BIT_WRITE_BYTE_EN_V1_8197F(x) \
|
||||
(((x) & BIT_MASK_WRITE_BYTE_EN_V1_8197F) \
|
||||
<< BIT_SHIFT_WRITE_BYTE_EN_V1_8197F)
|
||||
#define BITS_WRITE_BYTE_EN_V1_8197F \
|
||||
(BIT_MASK_WRITE_BYTE_EN_V1_8197F << BIT_SHIFT_WRITE_BYTE_EN_V1_8197F)
|
||||
#define BIT_CLEAR_WRITE_BYTE_EN_V1_8197F(x) \
|
||||
((x) & (~BITS_WRITE_BYTE_EN_V1_8197F))
|
||||
#define BIT_GET_WRITE_BYTE_EN_V1_8197F(x) \
|
||||
(((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8197F) & \
|
||||
BIT_MASK_WRITE_BYTE_EN_V1_8197F)
|
||||
#define BIT_SET_WRITE_BYTE_EN_V1_8197F(x, v) \
|
||||
(BIT_CLEAR_WRITE_BYTE_EN_V1_8197F(x) | BIT_WRITE_BYTE_EN_V1_8197F(v))
|
||||
|
||||
#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8197F 0
|
||||
#define BIT_MASK_LTECOEX_REG_ADDR_V1_8197F 0xffff
|
||||
#define BIT_LTECOEX_REG_ADDR_V1_8197F(x) \
|
||||
(((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8197F) \
|
||||
<< BIT_SHIFT_LTECOEX_REG_ADDR_V1_8197F)
|
||||
#define BITS_LTECOEX_REG_ADDR_V1_8197F \
|
||||
(BIT_MASK_LTECOEX_REG_ADDR_V1_8197F \
|
||||
<< BIT_SHIFT_LTECOEX_REG_ADDR_V1_8197F)
|
||||
#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8197F(x) \
|
||||
((x) & (~BITS_LTECOEX_REG_ADDR_V1_8197F))
|
||||
#define BIT_GET_LTECOEX_REG_ADDR_V1_8197F(x) \
|
||||
(((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8197F) & \
|
||||
BIT_MASK_LTECOEX_REG_ADDR_V1_8197F)
|
||||
#define BIT_SET_LTECOEX_REG_ADDR_V1_8197F(x, v) \
|
||||
(BIT_CLEAR_LTECOEX_REG_ADDR_V1_8197F(x) | \
|
||||
BIT_LTECOEX_REG_ADDR_V1_8197F(v))
|
||||
|
||||
/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8197F */
|
||||
|
||||
#define BIT_SHIFT_LTECOEX_W_DATA_V1_8197F 0
|
||||
#define BIT_MASK_LTECOEX_W_DATA_V1_8197F 0xffffffffL
|
||||
#define BIT_LTECOEX_W_DATA_V1_8197F(x) \
|
||||
(((x) & BIT_MASK_LTECOEX_W_DATA_V1_8197F) \
|
||||
<< BIT_SHIFT_LTECOEX_W_DATA_V1_8197F)
|
||||
#define BITS_LTECOEX_W_DATA_V1_8197F \
|
||||
(BIT_MASK_LTECOEX_W_DATA_V1_8197F << BIT_SHIFT_LTECOEX_W_DATA_V1_8197F)
|
||||
#define BIT_CLEAR_LTECOEX_W_DATA_V1_8197F(x) \
|
||||
((x) & (~BITS_LTECOEX_W_DATA_V1_8197F))
|
||||
#define BIT_GET_LTECOEX_W_DATA_V1_8197F(x) \
|
||||
(((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8197F) & \
|
||||
BIT_MASK_LTECOEX_W_DATA_V1_8197F)
|
||||
#define BIT_SET_LTECOEX_W_DATA_V1_8197F(x, v) \
|
||||
(BIT_CLEAR_LTECOEX_W_DATA_V1_8197F(x) | BIT_LTECOEX_W_DATA_V1_8197F(v))
|
||||
|
||||
/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8197F */
|
||||
|
||||
#define BIT_SHIFT_LTECOEX_R_DATA_V1_8197F 0
|
||||
#define BIT_MASK_LTECOEX_R_DATA_V1_8197F 0xffffffffL
|
||||
#define BIT_LTECOEX_R_DATA_V1_8197F(x) \
|
||||
(((x) & BIT_MASK_LTECOEX_R_DATA_V1_8197F) \
|
||||
<< BIT_SHIFT_LTECOEX_R_DATA_V1_8197F)
|
||||
#define BITS_LTECOEX_R_DATA_V1_8197F \
|
||||
(BIT_MASK_LTECOEX_R_DATA_V1_8197F << BIT_SHIFT_LTECOEX_R_DATA_V1_8197F)
|
||||
#define BIT_CLEAR_LTECOEX_R_DATA_V1_8197F(x) \
|
||||
((x) & (~BITS_LTECOEX_R_DATA_V1_8197F))
|
||||
#define BIT_GET_LTECOEX_R_DATA_V1_8197F(x) \
|
||||
(((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8197F) & \
|
||||
BIT_MASK_LTECOEX_R_DATA_V1_8197F)
|
||||
#define BIT_SET_LTECOEX_R_DATA_V1_8197F(x, v) \
|
||||
(BIT_CLEAR_LTECOEX_R_DATA_V1_8197F(x) | BIT_LTECOEX_R_DATA_V1_8197F(v))
|
||||
|
||||
/* 2 REG_NOT_VALID_8197F */
|
||||
|
||||
#endif
|
||||
|
||||
@@ -16159,8 +16159,6 @@
|
||||
(BIT_CLEAR_MU_SCORETABLE_OFFSET_8814B(x) | \
|
||||
BIT_MU_SCORETABLE_OFFSET_8814B(v))
|
||||
|
||||
/* 2 REG_USEREG_SETTING_8814B */
|
||||
|
||||
/* 2 REG_BF0_TIME_SETTING_8814B */
|
||||
#define BIT_BF0_TIMER_SET_8814B BIT(31)
|
||||
#define BIT_BF0_TIMER_CLR_8814B BIT(30)
|
||||
@@ -19948,7 +19946,43 @@
|
||||
|
||||
/* 2 REG_RSVD_8814B */
|
||||
|
||||
/* 2 REG_RSVD_8814B */
|
||||
/* 2 REG_SCHEDULER_COUNTER_8814B */
|
||||
|
||||
#define BIT_SHIFT__SCHEDULER_COUNTER_8814B 16
|
||||
#define BIT_MASK__SCHEDULER_COUNTER_8814B 0xffff
|
||||
#define BIT__SCHEDULER_COUNTER_8814B(x) \
|
||||
(((x) & BIT_MASK__SCHEDULER_COUNTER_8814B) \
|
||||
<< BIT_SHIFT__SCHEDULER_COUNTER_8814B)
|
||||
#define BITS__SCHEDULER_COUNTER_8814B \
|
||||
(BIT_MASK__SCHEDULER_COUNTER_8814B \
|
||||
<< BIT_SHIFT__SCHEDULER_COUNTER_8814B)
|
||||
#define BIT_CLEAR__SCHEDULER_COUNTER_8814B(x) \
|
||||
((x) & (~BITS__SCHEDULER_COUNTER_8814B))
|
||||
#define BIT_GET__SCHEDULER_COUNTER_8814B(x) \
|
||||
(((x) >> BIT_SHIFT__SCHEDULER_COUNTER_8814B) & \
|
||||
BIT_MASK__SCHEDULER_COUNTER_8814B)
|
||||
#define BIT_SET__SCHEDULER_COUNTER_8814B(x, v) \
|
||||
(BIT_CLEAR__SCHEDULER_COUNTER_8814B(x) | \
|
||||
BIT__SCHEDULER_COUNTER_8814B(v))
|
||||
|
||||
#define BIT__SCHEDULER_COUNTER_RST_8814B BIT(8)
|
||||
|
||||
#define BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B 0
|
||||
#define BIT_MASK_SCHEDULER_COUNTER_SEL_8814B 0xff
|
||||
#define BIT_SCHEDULER_COUNTER_SEL_8814B(x) \
|
||||
(((x) & BIT_MASK_SCHEDULER_COUNTER_SEL_8814B) \
|
||||
<< BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B)
|
||||
#define BITS_SCHEDULER_COUNTER_SEL_8814B \
|
||||
(BIT_MASK_SCHEDULER_COUNTER_SEL_8814B \
|
||||
<< BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B)
|
||||
#define BIT_CLEAR_SCHEDULER_COUNTER_SEL_8814B(x) \
|
||||
((x) & (~BITS_SCHEDULER_COUNTER_SEL_8814B))
|
||||
#define BIT_GET_SCHEDULER_COUNTER_SEL_8814B(x) \
|
||||
(((x) >> BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B) & \
|
||||
BIT_MASK_SCHEDULER_COUNTER_SEL_8814B)
|
||||
#define BIT_SET_SCHEDULER_COUNTER_SEL_8814B(x, v) \
|
||||
(BIT_CLEAR_SCHEDULER_COUNTER_SEL_8814B(x) | \
|
||||
BIT_SCHEDULER_COUNTER_SEL_8814B(v))
|
||||
|
||||
/* 2 REG_RSVD_8814B */
|
||||
|
||||
@@ -23204,6 +23238,11 @@
|
||||
#define BIT_CLI0_PWR_ST_V1_8814B BIT(0)
|
||||
|
||||
/* 2 REG_GENERAL_OPTION_8814B */
|
||||
#define BIT_FIX_MSDU_TAIL_WR_8814B BIT(12)
|
||||
#define BIT_FIX_MSDU_SHIFT_8814B BIT(11)
|
||||
#define BIT_RXFIFO_GNT_CUT_8814B BIT(8)
|
||||
#define BIT_WMAC_FIX_FIRST_MPDU_WITH_PHYSTS_8814B BIT(5)
|
||||
#define BIT_DUMMY_RXD_FCS_ERROR_MASK_EN_8814B BIT(4)
|
||||
#define BIT_PATTERN_MATCH_FIX_EN_8814B BIT(3)
|
||||
#define BIT_TXSERV_FIELD_SEL_8814B BIT(2)
|
||||
#define BIT_RXVHT_LEN_SEL_8814B BIT(1)
|
||||
|
||||
@@ -260,6 +260,18 @@
|
||||
#define BIT_RF_EN_8822C BIT(0)
|
||||
|
||||
/* 2 REG_AFE_LDO_CTRL_8822C */
|
||||
#define BIT_R_SYM_WLPON_EMEM1_EN_8822C BIT(31)
|
||||
#define BIT_R_SYM_WLPON_EMEM0_EN_8822C BIT(30)
|
||||
#define BIT_R_SYM_WLPOFF_P4EN_8822C BIT(28)
|
||||
#define BIT_R_SYM_WLPOFF_P3EN_8822C BIT(27)
|
||||
#define BIT_R_SYM_WLPOFF_P2EN_8822C BIT(26)
|
||||
#define BIT_R_SYM_WLPOFF_P1EN_8822C BIT(25)
|
||||
#define BIT_R_SYM_WLPOFF_EN_8822C BIT(24)
|
||||
#define BIT_R_SYM_WLPON_P3EN_8822C BIT(21)
|
||||
#define BIT_R_SYM_WLPON_P2EN_8822C BIT(20)
|
||||
#define BIT_R_SYM_WLPON_P1EN_8822C BIT(19)
|
||||
#define BIT_R_SYM_WLPON_EN_8822C BIT(18)
|
||||
#define BIT_R_SYM_LDOV12D_STBY_8822C BIT(16)
|
||||
#define BIT_R_SYM_WLBBOFF1_P4_EN_8822C BIT(9)
|
||||
#define BIT_R_SYM_WLBBOFF1_P3_EN_8822C BIT(8)
|
||||
#define BIT_R_SYM_WLBBOFF1_P2_EN_8822C BIT(7)
|
||||
@@ -12144,34 +12156,8 @@
|
||||
#define BIT_SET_BCNQ_PKT_INFO_8822C(x, v) \
|
||||
(BIT_CLEAR_BCNQ_PKT_INFO_8822C(x) | BIT_BCNQ_PKT_INFO_8822C(v))
|
||||
|
||||
/* 2 REG_USEREG_SETTING_8822C */
|
||||
#define BIT_NDPA_USEREG_8822C BIT(21)
|
||||
|
||||
#define BIT_SHIFT_RETRY_USEREG_8822C 19
|
||||
#define BIT_MASK_RETRY_USEREG_8822C 0x3
|
||||
#define BIT_RETRY_USEREG_8822C(x) \
|
||||
(((x) & BIT_MASK_RETRY_USEREG_8822C) << BIT_SHIFT_RETRY_USEREG_8822C)
|
||||
#define BITS_RETRY_USEREG_8822C \
|
||||
(BIT_MASK_RETRY_USEREG_8822C << BIT_SHIFT_RETRY_USEREG_8822C)
|
||||
#define BIT_CLEAR_RETRY_USEREG_8822C(x) ((x) & (~BITS_RETRY_USEREG_8822C))
|
||||
#define BIT_GET_RETRY_USEREG_8822C(x) \
|
||||
(((x) >> BIT_SHIFT_RETRY_USEREG_8822C) & BIT_MASK_RETRY_USEREG_8822C)
|
||||
#define BIT_SET_RETRY_USEREG_8822C(x, v) \
|
||||
(BIT_CLEAR_RETRY_USEREG_8822C(x) | BIT_RETRY_USEREG_8822C(v))
|
||||
|
||||
#define BIT_SHIFT_TRYPKT_USEREG_8822C 17
|
||||
#define BIT_MASK_TRYPKT_USEREG_8822C 0x3
|
||||
#define BIT_TRYPKT_USEREG_8822C(x) \
|
||||
(((x) & BIT_MASK_TRYPKT_USEREG_8822C) << BIT_SHIFT_TRYPKT_USEREG_8822C)
|
||||
#define BITS_TRYPKT_USEREG_8822C \
|
||||
(BIT_MASK_TRYPKT_USEREG_8822C << BIT_SHIFT_TRYPKT_USEREG_8822C)
|
||||
#define BIT_CLEAR_TRYPKT_USEREG_8822C(x) ((x) & (~BITS_TRYPKT_USEREG_8822C))
|
||||
#define BIT_GET_TRYPKT_USEREG_8822C(x) \
|
||||
(((x) >> BIT_SHIFT_TRYPKT_USEREG_8822C) & BIT_MASK_TRYPKT_USEREG_8822C)
|
||||
#define BIT_SET_TRYPKT_USEREG_8822C(x, v) \
|
||||
(BIT_CLEAR_TRYPKT_USEREG_8822C(x) | BIT_TRYPKT_USEREG_8822C(v))
|
||||
|
||||
#define BIT_CTLPKT_USEREG_8822C BIT(16)
|
||||
/* 2 REG_LOOPBACK_OPTION_8822C */
|
||||
#define BIT_LOOPACK_FAST_EDCA_EN_8822C BIT(24)
|
||||
|
||||
/* 2 REG_AESIV_SETTING_8822C */
|
||||
|
||||
@@ -13531,6 +13517,10 @@
|
||||
/* 2 REG_NOT_VALID_8822C */
|
||||
|
||||
/* 2 REG_CCA_TXEN_CNT_8822C */
|
||||
#define BIT_ENABLE_STOP_UPDATE_NAV_8822C BIT(21)
|
||||
#define BIT_ENABLE_GEN_RANDON_SLOT_TX_8822C BIT(20)
|
||||
#define BIT_ENABLE_RANDOM_SHIFT_TX_8822C BIT(19)
|
||||
#define BIT_ENABLE_EDCA_REF_FUNCTION_8822C BIT(18)
|
||||
#define BIT_CCA_TXEN_CNT_SWITCH_8822C BIT(17)
|
||||
#define BIT_CCA_TXEN_CNT_EN_8822C BIT(16)
|
||||
|
||||
@@ -15814,7 +15804,43 @@
|
||||
|
||||
/* 2 REG_RSVD_8822C */
|
||||
|
||||
/* 2 REG_RSVD_8822C */
|
||||
/* 2 REG_SCHEDULER_COUNTER_8822C */
|
||||
|
||||
#define BIT_SHIFT__SCHEDULER_COUNTER_8822C 16
|
||||
#define BIT_MASK__SCHEDULER_COUNTER_8822C 0xffff
|
||||
#define BIT__SCHEDULER_COUNTER_8822C(x) \
|
||||
(((x) & BIT_MASK__SCHEDULER_COUNTER_8822C) \
|
||||
<< BIT_SHIFT__SCHEDULER_COUNTER_8822C)
|
||||
#define BITS__SCHEDULER_COUNTER_8822C \
|
||||
(BIT_MASK__SCHEDULER_COUNTER_8822C \
|
||||
<< BIT_SHIFT__SCHEDULER_COUNTER_8822C)
|
||||
#define BIT_CLEAR__SCHEDULER_COUNTER_8822C(x) \
|
||||
((x) & (~BITS__SCHEDULER_COUNTER_8822C))
|
||||
#define BIT_GET__SCHEDULER_COUNTER_8822C(x) \
|
||||
(((x) >> BIT_SHIFT__SCHEDULER_COUNTER_8822C) & \
|
||||
BIT_MASK__SCHEDULER_COUNTER_8822C)
|
||||
#define BIT_SET__SCHEDULER_COUNTER_8822C(x, v) \
|
||||
(BIT_CLEAR__SCHEDULER_COUNTER_8822C(x) | \
|
||||
BIT__SCHEDULER_COUNTER_8822C(v))
|
||||
|
||||
#define BIT__SCHEDULER_COUNTER_RST_8822C BIT(8)
|
||||
|
||||
#define BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C 0
|
||||
#define BIT_MASK_SCHEDULER_COUNTER_SEL_8822C 0xff
|
||||
#define BIT_SCHEDULER_COUNTER_SEL_8822C(x) \
|
||||
(((x) & BIT_MASK_SCHEDULER_COUNTER_SEL_8822C) \
|
||||
<< BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C)
|
||||
#define BITS_SCHEDULER_COUNTER_SEL_8822C \
|
||||
(BIT_MASK_SCHEDULER_COUNTER_SEL_8822C \
|
||||
<< BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C)
|
||||
#define BIT_CLEAR_SCHEDULER_COUNTER_SEL_8822C(x) \
|
||||
((x) & (~BITS_SCHEDULER_COUNTER_SEL_8822C))
|
||||
#define BIT_GET_SCHEDULER_COUNTER_SEL_8822C(x) \
|
||||
(((x) >> BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C) & \
|
||||
BIT_MASK_SCHEDULER_COUNTER_SEL_8822C)
|
||||
#define BIT_SET_SCHEDULER_COUNTER_SEL_8822C(x, v) \
|
||||
(BIT_CLEAR_SCHEDULER_COUNTER_SEL_8822C(x) | \
|
||||
BIT_SCHEDULER_COUNTER_SEL_8822C(v))
|
||||
|
||||
/* 2 REG_RSVD_8822C */
|
||||
|
||||
@@ -18568,6 +18594,11 @@
|
||||
#define BIT_CLI0_PWR_ST_V1_8822C BIT(0)
|
||||
|
||||
/* 2 REG_GENERAL_OPTION_8822C */
|
||||
#define BIT_WMAC_RXRST_NDP_TIMEOUT_8822C BIT(11)
|
||||
#define BIT_WMAC_NDP_STANDBY_WAIT_RXEND_8822C BIT(10)
|
||||
#define BIT_DUMMY_FCS_READY_MASK_EN_8822C BIT(9)
|
||||
#define BIT_RXFIFO_GNT_CUT_8822C BIT(8)
|
||||
#define BIT_DUMMY_RXD_FCS_ERROR_MASK_EN_V1_8822C BIT(7)
|
||||
#define BIT_WMAC_EXT_DBG_SEL_V1_8822C BIT(6)
|
||||
#define BIT_WMAC_FIX_FIRST_MPDU_WITH_PHYSTS_8822C BIT(5)
|
||||
#define BIT_RX_DMA_BYPASS_CHECK_DATABYPASS_CHECK_DATA_8822C BIT(4)
|
||||
@@ -21264,6 +21295,9 @@
|
||||
|
||||
#define BIT_CMD11_SEQ_EN_8822C BIT(0)
|
||||
|
||||
/* 2 REG_SDIO_CTRL_8822C */
|
||||
#define BIT_SIG_OUT_PH_8822C BIT(0)
|
||||
|
||||
/* 2 REG_SDIO_DRIVING_8822C */
|
||||
|
||||
#define BIT_SHIFT_SDIO_DRV_TYPE_D_8822C 12
|
||||
|
||||
@@ -16,7 +16,7 @@
|
||||
#ifndef _HALMAC_FW_INFO_H_
|
||||
#define _HALMAC_FW_INFO_H_
|
||||
|
||||
#define H2C_FORMAT_VERSION 11
|
||||
#define H2C_FORMAT_VERSION 12
|
||||
|
||||
/* FW bin information */
|
||||
#define WLAN_FW_HDR_SIZE 64
|
||||
@@ -69,6 +69,9 @@ enum halmac_packet_id {
|
||||
HALMAC_PACKET_PROBE_REQ = 0x00,
|
||||
HALMAC_PACKET_SYNC_BCN = 0x01,
|
||||
HALMAC_PACKET_DISCOVERY_BCN = 0x02,
|
||||
HALMAC_PACKET_PROBE_REQ_NLO = 0xF0,
|
||||
HALMAC_PACKET_SYNC_BCN_NLO = 0xF1,
|
||||
HALMAC_PACKET_DISCOVERY_BCN_NLO = 0xF2,
|
||||
HALMAC_PACKET_UNDEFINE = 0x7FFFFFFF,
|
||||
};
|
||||
|
||||
|
||||
@@ -20,15 +20,16 @@
|
||||
#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03
|
||||
#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01
|
||||
#define C2H_SUB_CMD_ID_CFG_PARAM_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_UPDATE_PKT_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_IQK_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_PWR_TRK_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_PSD_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_FW_MEM_DUMP_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_PSD_DATA 0X04
|
||||
#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
|
||||
#define C2H_SUB_CMD_ID_IQK_DATA 0X06
|
||||
@@ -50,16 +51,20 @@
|
||||
#define C2H_SUB_CMD_ID_FW_FWCTRL_RPT 0X1F
|
||||
#define C2H_SUB_CMD_ID_H2C_LOOPBACK_ACK 0X20
|
||||
#define C2H_SUB_CMD_ID_FWCMD_LOOPBACK_ACK 0X21
|
||||
#define C2H_SUB_CMD_ID_SCAN_CH_NOTIFY 0X22
|
||||
#define C2H_SUB_CMD_ID_FW_TBTT_RPT 0X23
|
||||
#define C2H_SUB_CMD_ID_BCN_OFFLOAD 0X24
|
||||
#define H2C_SUB_CMD_ID_CFG_PARAM_ACK SUB_CMD_ID_CFG_PARAM
|
||||
#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH
|
||||
#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX
|
||||
#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE
|
||||
#define H2C_SUB_CMD_ID_UPDATE_PKT_ACK SUB_CMD_ID_UPDATE_PKT
|
||||
#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK
|
||||
#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK
|
||||
#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH
|
||||
#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK
|
||||
#define H2C_SUB_CMD_ID_PWR_TRK_ACK SUB_CMD_ID_PWR_TRK
|
||||
#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD
|
||||
#define H2C_SUB_CMD_ID_FW_MEM_DUMP_ACK SUB_CMD_ID_FW_MEM_DUMP
|
||||
#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT
|
||||
#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG
|
||||
#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING
|
||||
@@ -67,15 +72,16 @@
|
||||
#define H2C_SUB_CMD_ID_H2C_LOOPBACK_ACK SUB_CMD_ID_H2C_LOOPBACK
|
||||
#define H2C_SUB_CMD_ID_FWCMD_LOOPBACK_ACK SUB_CMD_ID_FWCMD_LOOPBACK
|
||||
#define H2C_CMD_ID_CFG_PARAM_ACK 0XFF
|
||||
#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF
|
||||
#define H2C_CMD_ID_BT_COEX_ACK 0XFF
|
||||
#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF
|
||||
#define H2C_CMD_ID_UPDATE_PKT_ACK 0XFF
|
||||
#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF
|
||||
#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF
|
||||
#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF
|
||||
#define H2C_CMD_ID_IQK_ACK 0XFF
|
||||
#define H2C_CMD_ID_PWR_TRK_ACK 0XFF
|
||||
#define H2C_CMD_ID_PSD_ACK 0XFF
|
||||
#define H2C_CMD_ID_FW_MEM_DUMP_ACK 0XFF
|
||||
#define H2C_CMD_ID_CCX_RPT 0XFF
|
||||
#define H2C_CMD_ID_FW_DBG_MSG 0XFF
|
||||
#define H2C_CMD_ID_FW_SNDING_ACK 0XFF
|
||||
@@ -124,6 +130,46 @@
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
|
||||
#define SCAN_STATUS_RPT_SET_H2C_SEQ_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
|
||||
#define SCAN_STATUS_RPT_GET_TSF_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_0(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_0_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
|
||||
#define SCAN_STATUS_RPT_GET_TSF_1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_1(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_1_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)
|
||||
#define SCAN_STATUS_RPT_GET_TSF_2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_2(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_2_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)
|
||||
#define SCAN_STATUS_RPT_GET_TSF_3(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 24, 8)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_3(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_3_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value)
|
||||
#define SCAN_STATUS_RPT_GET_TSF_4(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 0, 8)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_4(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 8, value)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_4_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 8, value)
|
||||
#define SCAN_STATUS_RPT_GET_TSF_5(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 8, 8)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_5(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 8, 8, value)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_5_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 8, 8, value)
|
||||
#define SCAN_STATUS_RPT_GET_TSF_6(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 16, 8)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_6(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 16, 8, value)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_6_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 16, 8, value)
|
||||
#define SCAN_STATUS_RPT_GET_TSF_7(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 24, 8)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_7(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 24, 8, value)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_7_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 24, 8, value)
|
||||
#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_pkt) \
|
||||
GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
|
||||
#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(c2h_pkt, value) \
|
||||
@@ -158,6 +204,46 @@
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 0, 32, value)
|
||||
#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 0, 32, value)
|
||||
#define CH_SWITCH_ACK_GET_TSF_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8)
|
||||
#define CH_SWITCH_ACK_SET_TSF_0(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value)
|
||||
#define CH_SWITCH_ACK_SET_TSF_0_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value)
|
||||
#define CH_SWITCH_ACK_GET_TSF_1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8)
|
||||
#define CH_SWITCH_ACK_SET_TSF_1(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value)
|
||||
#define CH_SWITCH_ACK_SET_TSF_1_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value)
|
||||
#define CH_SWITCH_ACK_GET_TSF_2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
|
||||
#define CH_SWITCH_ACK_SET_TSF_2(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
|
||||
#define CH_SWITCH_ACK_SET_TSF_2_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
|
||||
#define CH_SWITCH_ACK_GET_TSF_3(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
|
||||
#define CH_SWITCH_ACK_SET_TSF_3(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
|
||||
#define CH_SWITCH_ACK_SET_TSF_3_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
|
||||
#define CH_SWITCH_ACK_GET_TSF_4(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X10, 0, 8)
|
||||
#define CH_SWITCH_ACK_SET_TSF_4(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 0, 8, value)
|
||||
#define CH_SWITCH_ACK_SET_TSF_4_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 0, 8, value)
|
||||
#define CH_SWITCH_ACK_GET_TSF_5(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X10, 8, 8)
|
||||
#define CH_SWITCH_ACK_SET_TSF_5(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 8, 8, value)
|
||||
#define CH_SWITCH_ACK_SET_TSF_5_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 8, 8, value)
|
||||
#define CH_SWITCH_ACK_GET_TSF_6(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X10, 16, 8)
|
||||
#define CH_SWITCH_ACK_SET_TSF_6(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 16, 8, value)
|
||||
#define CH_SWITCH_ACK_SET_TSF_6_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 16, 8, value)
|
||||
#define CH_SWITCH_ACK_GET_TSF_7(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X10, 24, 8)
|
||||
#define CH_SWITCH_ACK_SET_TSF_7(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 24, 8, value)
|
||||
#define CH_SWITCH_ACK_SET_TSF_7_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 24, 8, value)
|
||||
#define BT_COEX_ACK_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 0, 8)
|
||||
#define BT_COEX_ACK_SET_DATA_START(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 8, value)
|
||||
@@ -503,4 +589,76 @@
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 8, value)
|
||||
#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_CH_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_CH_NUM(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
|
||||
#define SCAN_CH_NOTIFY_SET_CH_NUM_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_NOTIFY_ID(c2h_pkt) \
|
||||
GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_NOTIFY_ID(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
|
||||
#define SCAN_CH_NOTIFY_SET_NOTIFY_ID_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_STATUS(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_STATUS(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
|
||||
#define SCAN_CH_NOTIFY_SET_STATUS_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_TSF_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_0(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_0_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_TSF_1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_1(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_1_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_TSF_2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_2(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_2_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_TSF_3(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 24, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_3(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_3_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_TSF_4(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_4(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_4_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_TSF_5(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_5(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_5_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_TSF_6(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_6(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_6_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_TSF_7(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_7(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_7_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
|
||||
#define FW_TBTT_RPT_GET_PORT_NUMBER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
|
||||
#define FW_TBTT_RPT_SET_PORT_NUMBER(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
|
||||
#define FW_TBTT_RPT_SET_PORT_NUMBER_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
|
||||
#define BCN_OFFLOAD_GET_SUPPORT_VER(c2h_pkt) \
|
||||
GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
|
||||
#define BCN_OFFLOAD_SET_SUPPORT_VER(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
|
||||
#define BCN_OFFLOAD_SET_SUPPORT_VER_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
|
||||
#define BCN_OFFLOAD_GET_STATUS(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
|
||||
#define BCN_OFFLOAD_SET_STATUS(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
|
||||
#define BCN_OFFLOAD_SET_STATUS_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
|
||||
#endif
|
||||
|
||||
@@ -20,15 +20,16 @@
|
||||
#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03
|
||||
#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01
|
||||
#define C2H_SUB_CMD_ID_CFG_PARAM_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_UPDATE_PKT_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_IQK_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_PWR_TRK_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_PSD_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_FW_MEM_DUMP_ACK 0X01
|
||||
#define C2H_SUB_CMD_ID_PSD_DATA 0X04
|
||||
#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
|
||||
#define C2H_SUB_CMD_ID_IQK_DATA 0X06
|
||||
@@ -50,16 +51,20 @@
|
||||
#define C2H_SUB_CMD_ID_FW_FWCTRL_RPT 0X1F
|
||||
#define C2H_SUB_CMD_ID_H2C_LOOPBACK_ACK 0X20
|
||||
#define C2H_SUB_CMD_ID_FWCMD_LOOPBACK_ACK 0X21
|
||||
#define C2H_SUB_CMD_ID_SCAN_CH_NOTIFY 0X22
|
||||
#define C2H_SUB_CMD_ID_FW_TBTT_RPT 0X23
|
||||
#define C2H_SUB_CMD_ID_BCN_OFFLOAD 0X24
|
||||
#define H2C_SUB_CMD_ID_CFG_PARAM_ACK SUB_CMD_ID_CFG_PARAM
|
||||
#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH
|
||||
#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX
|
||||
#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE
|
||||
#define H2C_SUB_CMD_ID_UPDATE_PKT_ACK SUB_CMD_ID_UPDATE_PKT
|
||||
#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK
|
||||
#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK
|
||||
#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH
|
||||
#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK
|
||||
#define H2C_SUB_CMD_ID_PWR_TRK_ACK SUB_CMD_ID_PWR_TRK
|
||||
#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD
|
||||
#define H2C_SUB_CMD_ID_FW_MEM_DUMP_ACK SUB_CMD_ID_FW_MEM_DUMP
|
||||
#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT
|
||||
#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG
|
||||
#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING
|
||||
@@ -67,15 +72,16 @@
|
||||
#define H2C_SUB_CMD_ID_H2C_LOOPBACK_ACK SUB_CMD_ID_H2C_LOOPBACK
|
||||
#define H2C_SUB_CMD_ID_FWCMD_LOOPBACK_ACK SUB_CMD_ID_FWCMD_LOOPBACK
|
||||
#define H2C_CMD_ID_CFG_PARAM_ACK 0XFF
|
||||
#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF
|
||||
#define H2C_CMD_ID_BT_COEX_ACK 0XFF
|
||||
#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF
|
||||
#define H2C_CMD_ID_UPDATE_PKT_ACK 0XFF
|
||||
#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF
|
||||
#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF
|
||||
#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF
|
||||
#define H2C_CMD_ID_IQK_ACK 0XFF
|
||||
#define H2C_CMD_ID_PWR_TRK_ACK 0XFF
|
||||
#define H2C_CMD_ID_PSD_ACK 0XFF
|
||||
#define H2C_CMD_ID_FW_MEM_DUMP_ACK 0XFF
|
||||
#define H2C_CMD_ID_CCX_RPT 0XFF
|
||||
#define H2C_CMD_ID_FW_DBG_MSG 0XFF
|
||||
#define H2C_CMD_ID_FW_SNDING_ACK 0XFF
|
||||
@@ -110,6 +116,36 @@
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
|
||||
#define SCAN_STATUS_RPT_SET_H2C_SEQ(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
|
||||
#define SCAN_STATUS_RPT_GET_TSF_0(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_0(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
|
||||
#define SCAN_STATUS_RPT_GET_TSF_1(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_1(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)
|
||||
#define SCAN_STATUS_RPT_GET_TSF_2(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_2(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)
|
||||
#define SCAN_STATUS_RPT_GET_TSF_3(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_3(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value)
|
||||
#define SCAN_STATUS_RPT_GET_TSF_4(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 8)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_4(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 8, value)
|
||||
#define SCAN_STATUS_RPT_GET_TSF_5(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 8, 8)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_5(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 8, 8, value)
|
||||
#define SCAN_STATUS_RPT_GET_TSF_6(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 16, 8)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_6(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 16, 8, value)
|
||||
#define SCAN_STATUS_RPT_GET_TSF_7(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 24, 8)
|
||||
#define SCAN_STATUS_RPT_SET_TSF_7(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 24, 8, value)
|
||||
#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
|
||||
#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(c2h_pkt, value) \
|
||||
@@ -133,6 +169,30 @@
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 0, 32)
|
||||
#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 0, 32, value)
|
||||
#define CH_SWITCH_ACK_GET_TSF_0(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8)
|
||||
#define CH_SWITCH_ACK_SET_TSF_0(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value)
|
||||
#define CH_SWITCH_ACK_GET_TSF_1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8)
|
||||
#define CH_SWITCH_ACK_SET_TSF_1(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value)
|
||||
#define CH_SWITCH_ACK_GET_TSF_2(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
|
||||
#define CH_SWITCH_ACK_SET_TSF_2(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
|
||||
#define CH_SWITCH_ACK_GET_TSF_3(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
|
||||
#define CH_SWITCH_ACK_SET_TSF_3(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
|
||||
#define CH_SWITCH_ACK_GET_TSF_4(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 0, 8)
|
||||
#define CH_SWITCH_ACK_SET_TSF_4(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 0, 8, value)
|
||||
#define CH_SWITCH_ACK_GET_TSF_5(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 8, 8)
|
||||
#define CH_SWITCH_ACK_SET_TSF_5(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 8, 8, value)
|
||||
#define CH_SWITCH_ACK_GET_TSF_6(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 16, 8)
|
||||
#define CH_SWITCH_ACK_SET_TSF_6(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 16, 8, value)
|
||||
#define CH_SWITCH_ACK_GET_TSF_7(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 24, 8)
|
||||
#define CH_SWITCH_ACK_SET_TSF_7(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 24, 8, value)
|
||||
#define BT_COEX_ACK_GET_DATA_START(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 8)
|
||||
#define BT_COEX_ACK_SET_DATA_START(c2h_pkt, value) \
|
||||
@@ -368,4 +428,55 @@
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 8)
|
||||
#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_CH_NUM(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_CH_NUM(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_NOTIFY_ID(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_NOTIFY_ID(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_STATUS(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_STATUS(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_TSF_0(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_0(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_TSF_1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_1(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_TSF_2(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_2(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_TSF_3(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_3(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_TSF_4(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_4(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_TSF_5(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_5(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_TSF_6(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_6(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
|
||||
#define SCAN_CH_NOTIFY_GET_TSF_7(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
|
||||
#define SCAN_CH_NOTIFY_SET_TSF_7(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
|
||||
#define FW_TBTT_RPT_GET_PORT_NUMBER(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
|
||||
#define FW_TBTT_RPT_SET_PORT_NUMBER(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
|
||||
#define BCN_OFFLOAD_GET_SUPPORT_VER(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
|
||||
#define BCN_OFFLOAD_SET_SUPPORT_VER(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
|
||||
#define BCN_OFFLOAD_GET_STATUS(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
|
||||
#define BCN_OFFLOAD_SET_STATUS(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
|
||||
#endif
|
||||
|
||||
@@ -16,6 +16,7 @@
|
||||
#ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_
|
||||
#define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_
|
||||
#define CMD_ID_FW_OFFLOAD_H2C 0XFF
|
||||
#define CMD_ID_FW_ACCESS_TEST 0XFF
|
||||
#define CMD_ID_CH_SWITCH 0XFF
|
||||
#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF
|
||||
#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF
|
||||
@@ -28,19 +29,21 @@
|
||||
#define CMD_ID_IQK 0XFF
|
||||
#define CMD_ID_PWR_TRK 0XFF
|
||||
#define CMD_ID_PSD 0XFF
|
||||
#define CMD_ID_PHYDM_INFO 0XFF
|
||||
#define CMD_ID_FW_SNDING 0XFF
|
||||
#define CMD_ID_FW_FWCTRL 0XFF
|
||||
#define CMD_ID_H2C_LOOPBACK 0XFF
|
||||
#define CMD_ID_FWCMD_LOOPBACK 0XFF
|
||||
#define CMD_ID_UPDATE_SCAN_PKT 0XFF
|
||||
#define CMD_ID_BCN_OFFLOAD 0XFF
|
||||
#define CMD_ID_P2PPS 0XFF
|
||||
#define CMD_ID_BT_COEX 0XFF
|
||||
#define CMD_ID_NAN_CTRL 0XFF
|
||||
#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF
|
||||
#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF
|
||||
#define CMD_ID_FW_ACCESS_TEST 0XFF
|
||||
#define CMD_ID_PHYDM_INFO 0XFF
|
||||
#define CMD_ID_FW_SNDING 0XFF
|
||||
#define CMD_ID_H2C_LOOPBACK 0XFF
|
||||
#define CMD_ID_FWCMD_LOOPBACK 0XFF
|
||||
#define CMD_ID_FW_FWCTRL 0XFF
|
||||
#define CATEGORY_H2C_CMD_HEADER 0X00
|
||||
#define CATEGORY_FW_OFFLOAD_H2C 0X01
|
||||
#define CATEGORY_FW_ACCESS_TEST 0X01
|
||||
#define CATEGORY_CH_SWITCH 0X01
|
||||
#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01
|
||||
#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01
|
||||
@@ -53,17 +56,19 @@
|
||||
#define CATEGORY_IQK 0X01
|
||||
#define CATEGORY_PWR_TRK 0X01
|
||||
#define CATEGORY_PSD 0X01
|
||||
#define CATEGORY_PHYDM_INFO 0X01
|
||||
#define CATEGORY_FW_SNDING 0X01
|
||||
#define CATEGORY_FW_FWCTRL 0X01
|
||||
#define CATEGORY_H2C_LOOPBACK 0X01
|
||||
#define CATEGORY_FWCMD_LOOPBACK 0X01
|
||||
#define CATEGORY_UPDATE_SCAN_PKT 0X01
|
||||
#define CATEGORY_BCN_OFFLOAD 0X01
|
||||
#define CATEGORY_P2PPS 0X01
|
||||
#define CATEGORY_BT_COEX 0X01
|
||||
#define CATEGORY_NAN_CTRL 0X01
|
||||
#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01
|
||||
#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01
|
||||
#define CATEGORY_FW_ACCESS_TEST 0X01
|
||||
#define CATEGORY_PHYDM_INFO 0X01
|
||||
#define CATEGORY_FW_SNDING 0X01
|
||||
#define CATEGORY_H2C_LOOPBACK 0X01
|
||||
#define CATEGORY_FWCMD_LOOPBACK 0X01
|
||||
#define CATEGORY_FW_FWCTRL 0X01
|
||||
#define SUB_CMD_ID_FW_ACCESS_TEST 0X00
|
||||
#define SUB_CMD_ID_CH_SWITCH 0X02
|
||||
#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
|
||||
#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05
|
||||
@@ -76,17 +81,18 @@
|
||||
#define SUB_CMD_ID_IQK 0X0E
|
||||
#define SUB_CMD_ID_PWR_TRK 0X0F
|
||||
#define SUB_CMD_ID_PSD 0X10
|
||||
#define SUB_CMD_ID_PHYDM_INFO 0X11
|
||||
#define SUB_CMD_ID_FW_SNDING 0X12
|
||||
#define SUB_CMD_ID_FW_FWCTRL 0X13
|
||||
#define SUB_CMD_ID_H2C_LOOPBACK 0X14
|
||||
#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15
|
||||
#define SUB_CMD_ID_UPDATE_SCAN_PKT 0X16
|
||||
#define SUB_CMD_ID_BCN_OFFLOAD 0X17
|
||||
#define SUB_CMD_ID_P2PPS 0X24
|
||||
#define SUB_CMD_ID_BT_COEX 0X60
|
||||
#define SUB_CMD_ID_NAN_CTRL 0XB2
|
||||
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
|
||||
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
|
||||
#define SUB_CMD_ID_FW_ACCESS_TEST 0X00
|
||||
#define SUB_CMD_ID_PHYDM_INFO 0X11
|
||||
#define SUB_CMD_ID_FW_SNDING 0X12
|
||||
#define SUB_CMD_ID_H2C_LOOPBACK 0X14
|
||||
#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15
|
||||
#define SUB_CMD_ID_FW_FWCTRL 0X13
|
||||
#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 7)
|
||||
#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 7, value)
|
||||
@@ -142,6 +148,114 @@
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 16, value)
|
||||
#define FW_OFFLOAD_H2C_SET_SEQ_NUM_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 16, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_TXFF_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_RXFF_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_FWFF_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PHYFF_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 4, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 5, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_CAM_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 6, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 6, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 6, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 7, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 7, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 7, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 9, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 16, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE0_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 17, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 17, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE1_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 17, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 18, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 18, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE2_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 18, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 19, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 19, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE3_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 19, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 20, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 20, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE4_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 20, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 21, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 21, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE5_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 21, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 22, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 22, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE6_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 22, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 23, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 23, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE7_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 23, 1, value)
|
||||
#define CH_SWITCH_GET_START(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
|
||||
#define CH_SWITCH_SET_START(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
|
||||
@@ -162,6 +276,11 @@
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 2, value)
|
||||
#define CH_SWITCH_SET_PERIODIC_OPT_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 2, value)
|
||||
#define CH_SWITCH_GET_SCAN_MODE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 5, 1)
|
||||
#define CH_SWITCH_SET_SCAN_MODE(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value)
|
||||
#define CH_SWITCH_SET_SCAN_MODE_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value)
|
||||
#define CH_SWITCH_GET_INFO_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
|
||||
#define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
|
||||
@@ -480,6 +599,171 @@
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 16, value)
|
||||
#define PSD_SET_END_PSD_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 16, value)
|
||||
#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
|
||||
#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
|
||||
#define PHYDM_INFO_SET_REF_TYPE_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
|
||||
#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
|
||||
#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
|
||||
#define PHYDM_INFO_SET_RF_TYPE_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
|
||||
#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
|
||||
#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define PHYDM_INFO_SET_CUT_VER_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 24, 4)
|
||||
#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 4, value)
|
||||
#define PHYDM_INFO_SET_RX_ANT_STATUS_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 4, value)
|
||||
#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 28, 4)
|
||||
#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 28, 4, value)
|
||||
#define PHYDM_INFO_SET_TX_ANT_STATUS_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 28, 4, value)
|
||||
#define FW_SNDING_GET_SU0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
|
||||
#define FW_SNDING_SET_SU0(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
|
||||
#define FW_SNDING_SET_SU0_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
|
||||
#define FW_SNDING_GET_SU1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
|
||||
#define FW_SNDING_SET_SU1(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
|
||||
#define FW_SNDING_SET_SU1_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
|
||||
#define FW_SNDING_GET_MU(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
|
||||
#define FW_SNDING_SET_MU(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
|
||||
#define FW_SNDING_SET_MU_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
|
||||
#define FW_SNDING_GET_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
|
||||
#define FW_SNDING_SET_PERIOD(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
|
||||
#define FW_SNDING_SET_PERIOD_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
|
||||
#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
|
||||
#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define FW_SNDING_SET_NDPA0_HEAD_PG_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
|
||||
#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
|
||||
#define FW_SNDING_SET_NDPA1_HEAD_PG_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
|
||||
#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0XC, 0, 8)
|
||||
#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 0, 8, value)
|
||||
#define FW_SNDING_SET_MU_NDPA_HEAD_PG_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 0, 8, value)
|
||||
#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 8, 8)
|
||||
#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 8, 8, value)
|
||||
#define FW_SNDING_SET_RPT0_HEAD_PG_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 8, 8, value)
|
||||
#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 16, 8)
|
||||
#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 16, 8, value)
|
||||
#define FW_SNDING_SET_RPT1_HEAD_PG_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 16, 8, value)
|
||||
#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 24, 8)
|
||||
#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 24, 8, value)
|
||||
#define FW_SNDING_SET_RPT2_HEAD_PG_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 24, 8, value)
|
||||
#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
|
||||
#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
|
||||
#define FW_FWCTRL_SET_SEQ_NUM_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
|
||||
#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1)
|
||||
#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value)
|
||||
#define FW_FWCTRL_SET_MORE_CONTENT_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value)
|
||||
#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 9, 7)
|
||||
#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 7, value)
|
||||
#define FW_FWCTRL_SET_CONTENT_IDX_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 7, value)
|
||||
#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
|
||||
#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define FW_FWCTRL_SET_CLASS_ID_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define FW_FWCTRL_GET_LENGTH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
|
||||
#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
|
||||
#define FW_FWCTRL_SET_LENGTH_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
|
||||
#define FW_FWCTRL_GET_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32)
|
||||
#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value)
|
||||
#define FW_FWCTRL_SET_CONTENT_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value)
|
||||
#define UPDATE_SCAN_PKT_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)
|
||||
#define UPDATE_SCAN_PKT_SET_SIZE(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)
|
||||
#define UPDATE_SCAN_PKT_SET_SIZE_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)
|
||||
#define UPDATE_SCAN_PKT_GET_INDEX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
|
||||
#define UPDATE_SCAN_PKT_SET_INDEX(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define UPDATE_SCAN_PKT_SET_INDEX_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define UPDATE_SCAN_PKT_GET_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
|
||||
#define UPDATE_SCAN_PKT_SET_LOC(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
|
||||
#define UPDATE_SCAN_PKT_SET_LOC_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
|
||||
#define BCN_OFFLOAD_GET_REQUEST_VERSION(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
|
||||
#define BCN_OFFLOAD_SET_REQUEST_VERSION(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
|
||||
#define BCN_OFFLOAD_SET_REQUEST_VERSION_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
|
||||
#define BCN_OFFLOAD_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
|
||||
#define BCN_OFFLOAD_SET_ENABLE(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
|
||||
#define BCN_OFFLOAD_SET_ENABLE_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
|
||||
#define BCN_OFFLOAD_GET_MORE_RULE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
|
||||
#define BCN_OFFLOAD_SET_MORE_RULE(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
|
||||
#define BCN_OFFLOAD_SET_MORE_RULE_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
|
||||
#define BCN_OFFLOAD_GET_C2H_PERIODIC_REPORT(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)
|
||||
#define BCN_OFFLOAD_SET_C2H_PERIODIC_REPORT(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)
|
||||
#define BCN_OFFLOAD_SET_C2H_PERIODIC_REPORT_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)
|
||||
#define BCN_OFFLOAD_GET_REPORT_PERIOD(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
|
||||
#define BCN_OFFLOAD_SET_REPORT_PERIOD(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
|
||||
#define BCN_OFFLOAD_SET_REPORT_PERIOD_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
|
||||
#define BCN_OFFLOAD_GET_RULE_LENGTH(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
|
||||
#define BCN_OFFLOAD_SET_RULE_LENGTH(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define BCN_OFFLOAD_SET_RULE_LENGTH_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define BCN_OFFLOAD_GET_RULE_CONTENT(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)
|
||||
#define BCN_OFFLOAD_SET_RULE_CONTENT(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
|
||||
#define BCN_OFFLOAD_SET_RULE_CONTENT_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
|
||||
#define P2PPS_GET_OFFLOAD_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
|
||||
#define P2PPS_SET_OFFLOAD_EN(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
|
||||
@@ -768,222 +1052,4 @@
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 16, 16, value)
|
||||
#define NAN_CHANNEL_PLAN_1_SET_DURATION_5_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 16, 16, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_TXFF_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_RXFF_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_FWFF_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PHYFF_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 4, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 5, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_CAM_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 6, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 6, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 6, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 7, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 7, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 7, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 9, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 16, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE0_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 17, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 17, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE1_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 17, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 18, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 18, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE2_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 18, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 19, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 19, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE3_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 19, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 20, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 20, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE4_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 20, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 21, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 21, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE5_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 21, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 22, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 22, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE6_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 22, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 23, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 23, 1, value)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE7_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 23, 1, value)
|
||||
#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
|
||||
#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
|
||||
#define PHYDM_INFO_SET_REF_TYPE_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
|
||||
#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
|
||||
#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
|
||||
#define PHYDM_INFO_SET_RF_TYPE_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
|
||||
#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
|
||||
#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define PHYDM_INFO_SET_CUT_VER_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 24, 4)
|
||||
#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 4, value)
|
||||
#define PHYDM_INFO_SET_RX_ANT_STATUS_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 4, value)
|
||||
#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 28, 4)
|
||||
#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 28, 4, value)
|
||||
#define PHYDM_INFO_SET_TX_ANT_STATUS_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 28, 4, value)
|
||||
#define FW_SNDING_GET_SU0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
|
||||
#define FW_SNDING_SET_SU0(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
|
||||
#define FW_SNDING_SET_SU0_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
|
||||
#define FW_SNDING_GET_SU1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
|
||||
#define FW_SNDING_SET_SU1(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
|
||||
#define FW_SNDING_SET_SU1_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
|
||||
#define FW_SNDING_GET_MU(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
|
||||
#define FW_SNDING_SET_MU(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
|
||||
#define FW_SNDING_SET_MU_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
|
||||
#define FW_SNDING_GET_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
|
||||
#define FW_SNDING_SET_PERIOD(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
|
||||
#define FW_SNDING_SET_PERIOD_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
|
||||
#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
|
||||
#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define FW_SNDING_SET_NDPA0_HEAD_PG_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
|
||||
#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
|
||||
#define FW_SNDING_SET_NDPA1_HEAD_PG_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
|
||||
#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0XC, 0, 8)
|
||||
#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 0, 8, value)
|
||||
#define FW_SNDING_SET_MU_NDPA_HEAD_PG_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 0, 8, value)
|
||||
#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 8, 8)
|
||||
#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 8, 8, value)
|
||||
#define FW_SNDING_SET_RPT0_HEAD_PG_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 8, 8, value)
|
||||
#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 16, 8)
|
||||
#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 16, 8, value)
|
||||
#define FW_SNDING_SET_RPT1_HEAD_PG_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 16, 8, value)
|
||||
#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 24, 8)
|
||||
#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 24, 8, value)
|
||||
#define FW_SNDING_SET_RPT2_HEAD_PG_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 24, 8, value)
|
||||
#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
|
||||
#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
|
||||
#define FW_FWCTRL_SET_SEQ_NUM_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
|
||||
#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1)
|
||||
#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value)
|
||||
#define FW_FWCTRL_SET_MORE_CONTENT_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value)
|
||||
#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 9, 7)
|
||||
#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 7, value)
|
||||
#define FW_FWCTRL_SET_CONTENT_IDX_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 7, value)
|
||||
#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
|
||||
#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define FW_FWCTRL_SET_CLASS_ID_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define FW_FWCTRL_GET_LENGTH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
|
||||
#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
|
||||
#define FW_FWCTRL_SET_LENGTH_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
|
||||
#define FW_FWCTRL_GET_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32)
|
||||
#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value)
|
||||
#define FW_FWCTRL_SET_CONTENT_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value)
|
||||
#endif
|
||||
|
||||
@@ -16,6 +16,7 @@
|
||||
#ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_
|
||||
#define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_
|
||||
#define CMD_ID_FW_OFFLOAD_H2C 0XFF
|
||||
#define CMD_ID_FW_ACCESS_TEST 0XFF
|
||||
#define CMD_ID_CH_SWITCH 0XFF
|
||||
#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF
|
||||
#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF
|
||||
@@ -28,19 +29,21 @@
|
||||
#define CMD_ID_IQK 0XFF
|
||||
#define CMD_ID_PWR_TRK 0XFF
|
||||
#define CMD_ID_PSD 0XFF
|
||||
#define CMD_ID_PHYDM_INFO 0XFF
|
||||
#define CMD_ID_FW_SNDING 0XFF
|
||||
#define CMD_ID_FW_FWCTRL 0XFF
|
||||
#define CMD_ID_H2C_LOOPBACK 0XFF
|
||||
#define CMD_ID_FWCMD_LOOPBACK 0XFF
|
||||
#define CMD_ID_UPDATE_SCAN_PKT 0XFF
|
||||
#define CMD_ID_BCN_OFFLOAD 0XFF
|
||||
#define CMD_ID_P2PPS 0XFF
|
||||
#define CMD_ID_BT_COEX 0XFF
|
||||
#define CMD_ID_NAN_CTRL 0XFF
|
||||
#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF
|
||||
#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF
|
||||
#define CMD_ID_FW_ACCESS_TEST 0XFF
|
||||
#define CMD_ID_PHYDM_INFO 0XFF
|
||||
#define CMD_ID_FW_SNDING 0XFF
|
||||
#define CMD_ID_H2C_LOOPBACK 0XFF
|
||||
#define CMD_ID_FWCMD_LOOPBACK 0XFF
|
||||
#define CMD_ID_FW_FWCTRL 0XFF
|
||||
#define CATEGORY_H2C_CMD_HEADER 0X00
|
||||
#define CATEGORY_FW_OFFLOAD_H2C 0X01
|
||||
#define CATEGORY_FW_ACCESS_TEST 0X01
|
||||
#define CATEGORY_CH_SWITCH 0X01
|
||||
#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01
|
||||
#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01
|
||||
@@ -53,17 +56,19 @@
|
||||
#define CATEGORY_IQK 0X01
|
||||
#define CATEGORY_PWR_TRK 0X01
|
||||
#define CATEGORY_PSD 0X01
|
||||
#define CATEGORY_PHYDM_INFO 0X01
|
||||
#define CATEGORY_FW_SNDING 0X01
|
||||
#define CATEGORY_FW_FWCTRL 0X01
|
||||
#define CATEGORY_H2C_LOOPBACK 0X01
|
||||
#define CATEGORY_FWCMD_LOOPBACK 0X01
|
||||
#define CATEGORY_UPDATE_SCAN_PKT 0X01
|
||||
#define CATEGORY_BCN_OFFLOAD 0X01
|
||||
#define CATEGORY_P2PPS 0X01
|
||||
#define CATEGORY_BT_COEX 0X01
|
||||
#define CATEGORY_NAN_CTRL 0X01
|
||||
#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01
|
||||
#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01
|
||||
#define CATEGORY_FW_ACCESS_TEST 0X01
|
||||
#define CATEGORY_PHYDM_INFO 0X01
|
||||
#define CATEGORY_FW_SNDING 0X01
|
||||
#define CATEGORY_H2C_LOOPBACK 0X01
|
||||
#define CATEGORY_FWCMD_LOOPBACK 0X01
|
||||
#define CATEGORY_FW_FWCTRL 0X01
|
||||
#define SUB_CMD_ID_FW_ACCESS_TEST 0X00
|
||||
#define SUB_CMD_ID_CH_SWITCH 0X02
|
||||
#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
|
||||
#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05
|
||||
@@ -76,17 +81,18 @@
|
||||
#define SUB_CMD_ID_IQK 0X0E
|
||||
#define SUB_CMD_ID_PWR_TRK 0X0F
|
||||
#define SUB_CMD_ID_PSD 0X10
|
||||
#define SUB_CMD_ID_P2PPS 0X24
|
||||
#define SUB_CMD_ID_BT_COEX 0X60
|
||||
#define SUB_CMD_ID_NAN_CTRL 0XB2
|
||||
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
|
||||
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
|
||||
#define SUB_CMD_ID_FW_ACCESS_TEST 0X00
|
||||
#define SUB_CMD_ID_PHYDM_INFO 0X11
|
||||
#define SUB_CMD_ID_FW_SNDING 0X12
|
||||
#define SUB_CMD_ID_FW_FWCTRL 0X13
|
||||
#define SUB_CMD_ID_H2C_LOOPBACK 0X14
|
||||
#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15
|
||||
#define SUB_CMD_ID_UPDATE_SCAN_PKT 0X16
|
||||
#define SUB_CMD_ID_BCN_OFFLOAD 0X17
|
||||
#define SUB_CMD_ID_P2PPS 0X24
|
||||
#define SUB_CMD_ID_BT_COEX 0X60
|
||||
#define SUB_CMD_ID_NAN_CTRL 0XB2
|
||||
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
|
||||
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
|
||||
#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 7)
|
||||
#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value) \
|
||||
@@ -125,6 +131,78 @@
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 16)
|
||||
#define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 16, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 6, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 6, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 7, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 7, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 17, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 17, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 18, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 18, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 19, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 19, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 20, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 20, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 21, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 21, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 22, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 22, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 23, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 23, 1, value)
|
||||
#define CH_SWITCH_GET_START(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
|
||||
#define CH_SWITCH_SET_START(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
|
||||
@@ -139,6 +217,9 @@
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 2)
|
||||
#define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 2, value)
|
||||
#define CH_SWITCH_GET_SCAN_MODE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1)
|
||||
#define CH_SWITCH_SET_SCAN_MODE(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value)
|
||||
#define CH_SWITCH_GET_INFO_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
|
||||
#define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
|
||||
@@ -356,6 +437,117 @@
|
||||
#define PSD_GET_END_PSD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 16)
|
||||
#define PSD_SET_END_PSD(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 16, value)
|
||||
#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
|
||||
#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
|
||||
#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
|
||||
#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
|
||||
#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
|
||||
#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 4)
|
||||
#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 4, value)
|
||||
#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 28, 4)
|
||||
#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 28, 4, value)
|
||||
#define FW_SNDING_GET_SU0(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
|
||||
#define FW_SNDING_SET_SU0(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
|
||||
#define FW_SNDING_GET_SU1(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
|
||||
#define FW_SNDING_SET_SU1(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
|
||||
#define FW_SNDING_GET_MU(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
|
||||
#define FW_SNDING_SET_MU(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
|
||||
#define FW_SNDING_GET_PERIOD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
|
||||
#define FW_SNDING_SET_PERIOD(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
|
||||
#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
|
||||
#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
|
||||
#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
|
||||
#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 0, 8)
|
||||
#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 0, 8, value)
|
||||
#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 8, 8)
|
||||
#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 8, 8, value)
|
||||
#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 16, 8)
|
||||
#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 16, 8, value)
|
||||
#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 24, 8)
|
||||
#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 24, 8, value)
|
||||
#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
|
||||
#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
|
||||
#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1)
|
||||
#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value)
|
||||
#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 7)
|
||||
#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 7, value)
|
||||
#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
|
||||
#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define FW_FWCTRL_GET_LENGTH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
|
||||
#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
|
||||
#define FW_FWCTRL_GET_CONTENT(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32)
|
||||
#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value)
|
||||
#define UPDATE_SCAN_PKT_GET_SIZE(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)
|
||||
#define UPDATE_SCAN_PKT_SET_SIZE(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)
|
||||
#define UPDATE_SCAN_PKT_GET_INDEX(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
|
||||
#define UPDATE_SCAN_PKT_SET_INDEX(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define UPDATE_SCAN_PKT_GET_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
|
||||
#define UPDATE_SCAN_PKT_SET_LOC(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
|
||||
#define BCN_OFFLOAD_GET_REQUEST_VERSION(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
|
||||
#define BCN_OFFLOAD_SET_REQUEST_VERSION(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
|
||||
#define BCN_OFFLOAD_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
|
||||
#define BCN_OFFLOAD_SET_ENABLE(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
|
||||
#define BCN_OFFLOAD_GET_MORE_RULE(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
|
||||
#define BCN_OFFLOAD_SET_MORE_RULE(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
|
||||
#define BCN_OFFLOAD_GET_C2H_PERIODIC_REPORT(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)
|
||||
#define BCN_OFFLOAD_SET_C2H_PERIODIC_REPORT(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)
|
||||
#define BCN_OFFLOAD_GET_REPORT_PERIOD(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
|
||||
#define BCN_OFFLOAD_SET_REPORT_PERIOD(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
|
||||
#define BCN_OFFLOAD_GET_RULE_LENGTH(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
|
||||
#define BCN_OFFLOAD_SET_RULE_LENGTH(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define BCN_OFFLOAD_GET_RULE_CONTENT(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
|
||||
#define BCN_OFFLOAD_SET_RULE_CONTENT(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
|
||||
#define P2PPS_GET_OFFLOAD_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
|
||||
#define P2PPS_SET_OFFLOAD_EN(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
|
||||
@@ -546,149 +738,4 @@
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 16, 16)
|
||||
#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 16, 16, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 6, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 6, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 7, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 7, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 17, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 17, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 18, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 18, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 19, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 19, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 20, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 20, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 21, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 21, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 22, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 22, 1, value)
|
||||
#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 23, 1)
|
||||
#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 23, 1, value)
|
||||
#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
|
||||
#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
|
||||
#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
|
||||
#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
|
||||
#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
|
||||
#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 4)
|
||||
#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 4, value)
|
||||
#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 28, 4)
|
||||
#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 28, 4, value)
|
||||
#define FW_SNDING_GET_SU0(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
|
||||
#define FW_SNDING_SET_SU0(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
|
||||
#define FW_SNDING_GET_SU1(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
|
||||
#define FW_SNDING_SET_SU1(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
|
||||
#define FW_SNDING_GET_MU(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
|
||||
#define FW_SNDING_SET_MU(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
|
||||
#define FW_SNDING_GET_PERIOD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
|
||||
#define FW_SNDING_SET_PERIOD(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
|
||||
#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
|
||||
#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
|
||||
#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
|
||||
#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 0, 8)
|
||||
#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 0, 8, value)
|
||||
#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 8, 8)
|
||||
#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 8, 8, value)
|
||||
#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 16, 8)
|
||||
#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 16, 8, value)
|
||||
#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 24, 8)
|
||||
#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 24, 8, value)
|
||||
#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
|
||||
#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
|
||||
#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1)
|
||||
#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value)
|
||||
#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 7)
|
||||
#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 7, value)
|
||||
#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
|
||||
#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
|
||||
#define FW_FWCTRL_GET_LENGTH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
|
||||
#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
|
||||
#define FW_FWCTRL_GET_CONTENT(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32)
|
||||
#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value)
|
||||
#endif
|
||||
|
||||
@@ -71,6 +71,23 @@
|
||||
#define HALMAC_WLPHY_RFE_CTRL2GPIO 25
|
||||
#define HALMAC_EXT_XTAL 26
|
||||
#define HALMAC_SW_IO 27
|
||||
#define HALMAC_BT_SDIO_INT 28
|
||||
#define HALMAC_BT_JTAG 29
|
||||
#define HALMAC_WL_JTAG 30
|
||||
#define HALMAC_BT_RF 31
|
||||
#define HALMAC_WLPHY_RFE_CTRL2GPIO_2 32
|
||||
#define HALMAC_MAILBOX_3W 33
|
||||
#define HALMAC_MAILBOX_1W 34
|
||||
#define HALMAC_SW_DPDT_SEL 35
|
||||
#define HALMAC_BT_DPDT_SEL 36
|
||||
#define HALMAC_WL_DPDT_SEL 37
|
||||
#define HALMAC_BT_PAPE_SEL 38
|
||||
#define HALMAC_SW_PAPE_SEL 39
|
||||
#define HALMAC_WLBT_PAPE_SEL 40
|
||||
#define HALMAC_SW_LNAON_SET 41
|
||||
#define HALMAC_BT_LNAON_SEL 42
|
||||
#define HALMAC_WLBT_LNAON_SEL 43
|
||||
#define HALMAC_SWR_CTRL_EN 44
|
||||
|
||||
struct halmac_gpio_pimux_list {
|
||||
u16 func;
|
||||
|
||||
@@ -16,7 +16,7 @@
|
||||
#ifndef __HALMAC__HW_CFG_H__
|
||||
#define __HALMAC__HW_CFG_H__
|
||||
|
||||
#include <drv_conf.h> /* CONFIG_[IC] */
|
||||
#include <drv_conf.h> /* CONFIG_[IC], CONFIG_[INTF]_HCI */
|
||||
|
||||
#ifdef CONFIG_RTL8723A
|
||||
#define HALMAC_8723A_SUPPORT 1
|
||||
@@ -138,6 +138,24 @@
|
||||
#define HALMAC_8198F_SUPPORT 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8192F
|
||||
#define HALMAC_8192F_SUPPORT 1
|
||||
#else
|
||||
#define HALMAC_8192F_SUPPORT 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8197G
|
||||
#define HALMAC_8197G_SUPPORT 1
|
||||
#else
|
||||
#define HALMAC_8197G_SUPPORT 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8812F
|
||||
#define HALMAC_8812F_SUPPORT 1
|
||||
#else
|
||||
#define HALMAC_8812F_SUPPORT 0
|
||||
#endif
|
||||
|
||||
|
||||
/* Halmac support IC version */
|
||||
|
||||
@@ -165,6 +183,24 @@
|
||||
#define HALMAC_8822C_SUPPORT 0
|
||||
#endif
|
||||
|
||||
|
||||
/* Interface support */
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
#define HALMAC_SDIO_SUPPORT 1
|
||||
#else
|
||||
#define HALMAC_SDIO_SUPPORT 0
|
||||
#endif
|
||||
#ifdef CONFIG_USB_HCI
|
||||
#define HALMAC_USB_SUPPORT 1
|
||||
#else
|
||||
#define HALMAC_USB_SUPPORT 0
|
||||
#endif
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define HALMAC_PCIE_SUPPORT 1
|
||||
#else
|
||||
#define HALMAC_PCIE_SUPPORT 0
|
||||
#endif
|
||||
|
||||
#endif /* __HALMAC__HW_CFG_H__ */
|
||||
|
||||
|
||||
|
||||
@@ -27,6 +27,7 @@
|
||||
#define CMD_ID_C2H_RA_PARA_RPT 0X0E
|
||||
#define CMD_ID_C2H_CUR_CHANNEL 0X10
|
||||
#define CMD_ID_C2H_GPIO_WAKEUP 0X14
|
||||
#define CMD_ID_C2H_DROPID_RPT 0X2D
|
||||
#define C2H_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
|
||||
#define C2H_SET_CMD_ID(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
|
||||
@@ -609,4 +610,41 @@
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
|
||||
#define C2H_GPIO_WAKEUP_SET_TRIGGER_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
|
||||
#define C2H_DROPID_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
|
||||
#define C2H_DROPID_RPT_SET_CMD_ID(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
|
||||
#define C2H_DROPID_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
|
||||
#define C2H_DROPID_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
|
||||
#define C2H_DROPID_RPT_SET_SEQ(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
|
||||
#define C2H_DROPID_RPT_SET_SEQ_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
|
||||
#define C2H_DROPID_RPT_GET_DROPIDBIT(c2h_pkt) \
|
||||
GET_C2H_FIELD(c2h_pkt + 0X00, 16, 4)
|
||||
#define C2H_DROPID_RPT_SET_DROPIDBIT(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 4, value)
|
||||
#define C2H_DROPID_RPT_SET_DROPIDBIT_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 4, value)
|
||||
#define C2H_DROPID_RPT_GET_CURDROPID(c2h_pkt) \
|
||||
GET_C2H_FIELD(c2h_pkt + 0X00, 20, 2)
|
||||
#define C2H_DROPID_RPT_SET_CURDROPID(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 20, 2, value)
|
||||
#define C2H_DROPID_RPT_SET_CURDROPID_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 20, 2, value)
|
||||
#define C2H_DROPID_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
|
||||
#define C2H_DROPID_RPT_SET_MACID(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
|
||||
#define C2H_DROPID_RPT_SET_MACID_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
|
||||
#define C2H_DROPID_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
|
||||
#define C2H_DROPID_RPT_SET_LEN(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
|
||||
#define C2H_DROPID_RPT_SET_LEN_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
|
||||
#define C2H_DROPID_RPT_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
|
||||
#define C2H_DROPID_RPT_SET_TRIGGER(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
|
||||
#define C2H_DROPID_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value) \
|
||||
SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
|
||||
#endif
|
||||
|
||||
@@ -27,6 +27,7 @@
|
||||
#define CMD_ID_C2H_RA_PARA_RPT 0X0E
|
||||
#define CMD_ID_C2H_CUR_CHANNEL 0X10
|
||||
#define CMD_ID_C2H_GPIO_WAKEUP 0X14
|
||||
#define CMD_ID_C2H_DROPID_RPT 0X2D
|
||||
#define C2H_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
|
||||
#define C2H_SET_CMD_ID(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
|
||||
@@ -405,4 +406,29 @@
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
|
||||
#define C2H_GPIO_WAKEUP_SET_TRIGGER(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
|
||||
#define C2H_DROPID_RPT_GET_CMD_ID(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
|
||||
#define C2H_DROPID_RPT_SET_CMD_ID(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
|
||||
#define C2H_DROPID_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
|
||||
#define C2H_DROPID_RPT_SET_SEQ(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
|
||||
#define C2H_DROPID_RPT_GET_DROPIDBIT(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 4)
|
||||
#define C2H_DROPID_RPT_SET_DROPIDBIT(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 4, value)
|
||||
#define C2H_DROPID_RPT_GET_CURDROPID(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 20, 2)
|
||||
#define C2H_DROPID_RPT_SET_CURDROPID(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 20, 2, value)
|
||||
#define C2H_DROPID_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
|
||||
#define C2H_DROPID_RPT_SET_MACID(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
|
||||
#define C2H_DROPID_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
|
||||
#define C2H_DROPID_RPT_SET_LEN(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
|
||||
#define C2H_DROPID_RPT_GET_TRIGGER(c2h_pkt) \
|
||||
LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
|
||||
#define C2H_DROPID_RPT_SET_TRIGGER(c2h_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
|
||||
#endif
|
||||
|
||||
@@ -675,66 +675,30 @@
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
|
||||
#define SET_PWR_MODE_SET_PWR_STATE_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
|
||||
#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X04, 16, 1)
|
||||
#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 1, value)
|
||||
#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 1, value)
|
||||
#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X04, 17, 1)
|
||||
#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 17, 1, value)
|
||||
#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 17, 1, value)
|
||||
#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X04, 18, 1)
|
||||
#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 18, 1, value)
|
||||
#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 18, 1, value)
|
||||
#define SET_PWR_MODE_GET_PROTECT_BCN(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X04, 19, 1)
|
||||
#define SET_PWR_MODE_SET_PROTECT_BCN(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 19, 1, value)
|
||||
#define SET_PWR_MODE_SET_PROTECT_BCN_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 19, 1, value)
|
||||
#define SET_PWR_MODE_GET_SILENCE_PERIOD(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X04, 20, 1)
|
||||
#define SET_PWR_MODE_SET_SILENCE_PERIOD(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 20, 1, value)
|
||||
#define SET_PWR_MODE_SET_SILENCE_PERIOD_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 20, 1, value)
|
||||
#define SET_PWR_MODE_GET_FAST_BT_CONNECT(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X04, 21, 1)
|
||||
#define SET_PWR_MODE_SET_FAST_BT_CONNECT(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 21, 1, value)
|
||||
#define SET_PWR_MODE_SET_FAST_BT_CONNECT_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 21, 1, value)
|
||||
#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X04, 22, 1)
|
||||
#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 22, 1, value)
|
||||
#define SET_PWR_MODE_SET_TWO_ANTENNA_EN_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 22, 1, value)
|
||||
#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X04, 24, 1)
|
||||
#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 1, value)
|
||||
#define SET_PWR_MODE_SET_ADOPT_USER_SETTING_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 1, value)
|
||||
#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X04, 25, 3)
|
||||
#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 25, 3, value)
|
||||
#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 25, 3, value)
|
||||
#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X04, 28, 4)
|
||||
#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 28, 4, value)
|
||||
#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 28, 4, value)
|
||||
#define SET_PWR_MODE_GET_RSVD_NOUSED(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)
|
||||
#define SET_PWR_MODE_SET_RSVD_NOUSED(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)
|
||||
#define SET_PWR_MODE_SET_RSVD_NOUSED_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)
|
||||
#define SET_PWR_MODE_GET_BCN_RECEIVING_TIME(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X04, 24, 5)
|
||||
#define SET_PWR_MODE_SET_BCN_RECEIVING_TIME(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 5, value)
|
||||
#define SET_PWR_MODE_SET_BCN_RECEIVING_TIME_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 5, value)
|
||||
#define SET_PWR_MODE_GET_BCN_LISTEN_INTERVAL(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X04, 29, 2)
|
||||
#define SET_PWR_MODE_SET_BCN_LISTEN_INTERVAL(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 29, 2, value)
|
||||
#define SET_PWR_MODE_SET_BCN_LISTEN_INTERVAL_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 29, 2, value)
|
||||
#define SET_PWR_MODE_GET_ADOPT_BCN_RECEIVING_TIME(h2c_pkt) \
|
||||
GET_H2C_FIELD(h2c_pkt + 0X04, 31, 1)
|
||||
#define SET_PWR_MODE_SET_ADOPT_BCN_RECEIVING_TIME(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 31, 1, value)
|
||||
#define SET_PWR_MODE_SET_ADOPT_BCN_RECEIVING_TIME_NO_CLR(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 31, 1, value)
|
||||
#define PS_TUNING_PARA_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
|
||||
#define PS_TUNING_PARA_SET_CMD_ID(h2c_pkt, value) \
|
||||
SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
|
||||
|
||||
@@ -485,46 +485,22 @@
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
|
||||
#define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
|
||||
#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 1)
|
||||
#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 1, value)
|
||||
#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 17, 1)
|
||||
#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 17, 1, value)
|
||||
#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 18, 1)
|
||||
#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 18, 1, value)
|
||||
#define SET_PWR_MODE_GET_PROTECT_BCN(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 19, 1)
|
||||
#define SET_PWR_MODE_SET_PROTECT_BCN(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 19, 1, value)
|
||||
#define SET_PWR_MODE_GET_SILENCE_PERIOD(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 20, 1)
|
||||
#define SET_PWR_MODE_SET_SILENCE_PERIOD(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 20, 1, value)
|
||||
#define SET_PWR_MODE_GET_FAST_BT_CONNECT(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 21, 1)
|
||||
#define SET_PWR_MODE_SET_FAST_BT_CONNECT(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 21, 1, value)
|
||||
#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 22, 1)
|
||||
#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 22, 1, value)
|
||||
#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 1)
|
||||
#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 1, value)
|
||||
#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 25, 3)
|
||||
#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 25, 3, value)
|
||||
#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 28, 4)
|
||||
#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 28, 4, value)
|
||||
#define SET_PWR_MODE_GET_RSVD_NOUSED(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)
|
||||
#define SET_PWR_MODE_SET_RSVD_NOUSED(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)
|
||||
#define SET_PWR_MODE_GET_BCN_RECEIVING_TIME(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 5)
|
||||
#define SET_PWR_MODE_SET_BCN_RECEIVING_TIME(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 5, value)
|
||||
#define SET_PWR_MODE_GET_BCN_LISTEN_INTERVAL(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 29, 2)
|
||||
#define SET_PWR_MODE_SET_BCN_LISTEN_INTERVAL(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 29, 2, value)
|
||||
#define SET_PWR_MODE_GET_ADOPT_BCN_RECEIVING_TIME(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 31, 1)
|
||||
#define SET_PWR_MODE_SET_ADOPT_BCN_RECEIVING_TIME(h2c_pkt, value) \
|
||||
SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 31, 1, value)
|
||||
#define PS_TUNING_PARA_GET_CMD_ID(h2c_pkt) \
|
||||
LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
|
||||
#define PS_TUNING_PARA_SET_CMD_ID(h2c_pkt, value) \
|
||||
|
||||
@@ -17,13 +17,37 @@
|
||||
#define __HALMAC_PCIE_REG_H__
|
||||
|
||||
/* PCIE PHY register */
|
||||
#define RAC_CTRL_PPR 0x00
|
||||
#define RAC_SET_PPR 0x20
|
||||
#define RAC_TRG_PPR 0x21
|
||||
#define RAC_CTRL_PPR 0x00
|
||||
#define RAC_SET_PPR 0x20
|
||||
#define RAC_TRG_PPR 0x21
|
||||
#define RAC_CTRL_PPR_V1 0x30
|
||||
#define RAC_SET_PPR_V1 0x31
|
||||
|
||||
/* PCIE CFG register */
|
||||
#define PCIE_L1_BACKDOOR 0x719
|
||||
#define PCIE_L1SS_CTRL 0x718
|
||||
#define PCIE_L1_CTRL 0x719
|
||||
#define PCIE_ASPM_CTRL 0x70F
|
||||
#define PCIE_CLK_CTRL 0x725
|
||||
#define PCIE_L1SS_CAP 0x160
|
||||
#define PCIE_L1SS_SUP 0x164
|
||||
#define PCIE_L1SS_STS 0x168
|
||||
|
||||
/* PCIE CFG bit */
|
||||
#define PCIE_BIT_WAKE BIT(2)
|
||||
#define PCIE_BIT_L1 BIT(3)
|
||||
#define PCIE_BIT_CLK BIT(4)
|
||||
#define PCIE_BIT_L0S BIT(7)
|
||||
#define PCIE_BIT_L1SS BIT(5)
|
||||
#define PCIE_BIT_L1SSSUP BIT(4)
|
||||
|
||||
/* PCIE ASPM mask*/
|
||||
#define SHFT_L1DLY 3
|
||||
#define SHFT_L0SDLY 0
|
||||
#define PCIE_ASPMDLY_MASK 0x07
|
||||
#define PCIE_L1SS_MASK 0x0F
|
||||
|
||||
/* PCIE Capability */
|
||||
#define PCIE_L1SS_ID 0x001E
|
||||
|
||||
/* PCIE MAC register */
|
||||
#define LINK_CTRL2_REG_OFFSET 0xA0
|
||||
|
||||
@@ -20,26 +20,21 @@
|
||||
|
||||
#define HALMAC_PWR_POLLING_CNT 20000
|
||||
|
||||
/*
|
||||
* The value of cmd : 4 bits
|
||||
*/
|
||||
/* The value of cmd : 4 bits */
|
||||
|
||||
/*
|
||||
* offset : the read register offset
|
||||
/* offset : the read register offset
|
||||
* msk : the mask of the read value
|
||||
* value : N/A, left by 0
|
||||
* Note : dirver shall implement this function by read & msk
|
||||
*/
|
||||
#define HALMAC_PWR_CMD_READ 0x00
|
||||
/*
|
||||
* offset: the read register offset
|
||||
/* offset: the read register offset
|
||||
* msk: the mask of the write bits
|
||||
* value: write value
|
||||
* Note: driver shall implement this cmd by read & msk after write
|
||||
*/
|
||||
#define HALMAC_PWR_CMD_WRITE 0x01
|
||||
/*
|
||||
* offset: the read register offset
|
||||
/* offset: the read register offset
|
||||
* msk: the mask of the polled value
|
||||
* value: the value to be polled, masked by the msd field.
|
||||
* Note: driver shall implement this cmd by
|
||||
@@ -49,22 +44,18 @@
|
||||
* } while(not timeout);
|
||||
*/
|
||||
#define HALMAC_PWR_CMD_POLLING 0x02
|
||||
/*
|
||||
* offset: the value to delay
|
||||
/* offset: the value to delay
|
||||
* msk: N/A
|
||||
* value: the unit of delay, 0: us, 1: ms
|
||||
*/
|
||||
#define HALMAC_PWR_CMD_DELAY 0x03
|
||||
/*
|
||||
* offset: N/A
|
||||
/* offset: N/A
|
||||
* msk: N/A
|
||||
* value: N/A
|
||||
*/
|
||||
#define HALMAC_PWR_CMD_END 0x04
|
||||
|
||||
/*
|
||||
* The value of base : 4 bits
|
||||
*/
|
||||
/* The value of base : 4 bits */
|
||||
|
||||
/* define the base address of each block */
|
||||
#define HALMAC_PWR_ADDR_MAC 0x00
|
||||
@@ -72,17 +63,13 @@
|
||||
#define HALMAC_PWR_ADDR_PCIE 0x02
|
||||
#define HALMAC_PWR_ADDR_SDIO 0x03
|
||||
|
||||
/*
|
||||
* The value of interface_msk : 4 bits
|
||||
*/
|
||||
/* The value of interface_msk : 4 bits */
|
||||
#define HALMAC_PWR_INTF_SDIO_MSK BIT(0)
|
||||
#define HALMAC_PWR_INTF_USB_MSK BIT(1)
|
||||
#define HALMAC_PWR_INTF_PCI_MSK BIT(2)
|
||||
#define HALMAC_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
|
||||
|
||||
/*
|
||||
* The value of cut_msk : 8 bits
|
||||
*/
|
||||
/* The value of cut_msk : 8 bits */
|
||||
#define HALMAC_PWR_CUT_TESTCHIP_MSK BIT(0)
|
||||
#define HALMAC_PWR_CUT_A_MSK BIT(1)
|
||||
#define HALMAC_PWR_CUT_B_MSK BIT(2)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -696,5 +696,8 @@
|
||||
#define REG_SEC_OPT_V2_8197F 0x07EC
|
||||
#define REG_RTS_ADDRESS_0_8197F 0x07F0
|
||||
#define REG_RTS_ADDRESS_1_8197F 0x07F8
|
||||
#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8197F 0x1700
|
||||
#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8197F 0x1704
|
||||
#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8197F 0x1708
|
||||
|
||||
#endif
|
||||
|
||||
@@ -628,7 +628,6 @@
|
||||
#define REG_DUMMY_PAGE4_V1_8814B 0x04FC
|
||||
#define REG_DUMMY_PAGE4_1_8814B 0x04FE
|
||||
#define REG_MU_OFFSET_8814B 0x1400
|
||||
#define REG_USEREG_SETTING_8814B 0x1420
|
||||
#define REG_BF0_TIME_SETTING_8814B 0x1428
|
||||
#define REG_BF1_TIME_SETTING_8814B 0x142C
|
||||
#define REG_BF_TIMEOUT_EN_8814B 0x1430
|
||||
@@ -796,6 +795,7 @@
|
||||
#define REG_TIMER_COMPARE_8814B 0x15C0
|
||||
#define REG_TIMER_COMPARE_VALUE_LOW_8814B 0x15C4
|
||||
#define REG_TIMER_COMPARE_VALUE_HIGH_8814B 0x15C8
|
||||
#define REG_SCHEDULER_COUNTER_8814B 0x15D0
|
||||
#define REG_WMAC_CR_8814B 0x0600
|
||||
#define REG_WMAC_FWPKT_CR_8814B 0x0601
|
||||
#define REG_FW_STS_FILTER_8814B 0x0602
|
||||
|
||||
@@ -440,7 +440,7 @@
|
||||
#define REG_Q6_Q7_INFO_8822C 0x140C
|
||||
#define REG_MGQ_HIQ_INFO_8822C 0x1410
|
||||
#define REG_CMDQ_BCNQ_INFO_8822C 0x1414
|
||||
#define REG_USEREG_SETTING_8822C 0x1420
|
||||
#define REG_LOOPBACK_OPTION_8822C 0x1420
|
||||
#define REG_AESIV_SETTING_8822C 0x1424
|
||||
#define REG_BF0_TIME_SETTING_8822C 0x1428
|
||||
#define REG_BF1_TIME_SETTING_8822C 0x142C
|
||||
@@ -620,6 +620,7 @@
|
||||
#define REG_P2PPS_HW_AUTO_PAUSE_CTRL_8822C 0x156C
|
||||
#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8822C 0x1570
|
||||
#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8822C 0x1574
|
||||
#define REG_SCHEDULER_COUNTER_8822C 0x15D0
|
||||
#define REG_WMAC_CR_8822C 0x0600
|
||||
#define REG_WMAC_FWPKT_CR_8822C 0x0601
|
||||
#define REG_FW_STS_FILTER_8822C 0x0602
|
||||
@@ -837,6 +838,7 @@
|
||||
#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822C 0x1708
|
||||
#define REG_SDIO_TX_CTRL_8822C 0x10250000
|
||||
#define REG_SDIO_CMD11_VOL_SWITCH_8822C 0x10250004
|
||||
#define REG_SDIO_CTRL_8822C 0x10250005
|
||||
#define REG_SDIO_DRIVING_8822C 0x10250006
|
||||
#define REG_SDIO_MONITOR_8822C 0x10250008
|
||||
#define REG_SDIO_MONITOR_2_8822C 0x1025000C
|
||||
|
||||
@@ -16,7 +16,8 @@
|
||||
#ifndef _HALMAC_RX_BD_NIC_H_
|
||||
#define _HALMAC_RX_BD_NIC_H_
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||\
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXBD_DW0*/
|
||||
|
||||
|
||||
@@ -16,13 +16,21 @@
|
||||
#ifndef _HALMAC_RX_DESC_AP_H_
|
||||
#define _HALMAC_RX_DESC_AP_H_
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*RXDESC_WORD0*/
|
||||
|
||||
#define GET_RX_DESC_EOR(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \
|
||||
30)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_PHYPKTIDC(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \
|
||||
28)
|
||||
@@ -39,7 +47,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_SWDEC(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \
|
||||
@@ -81,7 +89,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_TY_PE(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x3, \
|
||||
@@ -99,7 +108,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_MF(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
|
||||
@@ -114,7 +123,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_PAM(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
|
||||
@@ -131,7 +141,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_CHK_VLD(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
|
||||
@@ -149,7 +160,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
|
||||
@@ -161,7 +172,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_CHKERR(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
|
||||
@@ -184,7 +196,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_PAGGR(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
|
||||
@@ -201,7 +214,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_RXID_MATCH(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
|
||||
@@ -219,7 +233,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_AMSDU(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
|
||||
@@ -228,7 +242,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_MACID_VLD(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
|
||||
@@ -238,7 +253,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_TID(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0xf, 8)
|
||||
@@ -246,7 +261,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_MACID(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x7f, \
|
||||
@@ -269,7 +285,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_PPDU_CNT(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x3, \
|
||||
@@ -279,7 +296,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_C2H(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
|
||||
@@ -287,7 +304,7 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8198F_SUPPORT)
|
||||
#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_HWRSVD_V1(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x7, \
|
||||
@@ -296,7 +313,7 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_HWRSVD(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0xf, \
|
||||
@@ -304,7 +321,7 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8198F_SUPPORT)
|
||||
#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_RXMAGPKT(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
|
||||
@@ -314,7 +331,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_WLANHD_IV_LEN(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x3f, \
|
||||
@@ -330,7 +347,7 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822C_SUPPORT)
|
||||
#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_RX_STATISTICS(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
|
||||
@@ -339,7 +356,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_RX_IS_QOS(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
|
||||
@@ -357,7 +375,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_FRAG(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0xf, \
|
||||
@@ -378,7 +396,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_PATTERN_MATCH(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \
|
||||
@@ -395,7 +414,7 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \
|
||||
@@ -408,7 +427,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_DMA_AGG_NUM(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0xff, \
|
||||
@@ -417,7 +436,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_BSSID_FIT_1_0(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x3, \
|
||||
@@ -438,7 +458,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_HTC(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \
|
||||
@@ -456,7 +476,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_BSSID_FIT_4_2(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x7, 7)
|
||||
@@ -472,7 +493,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_RX_RATE(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x7f, \
|
||||
@@ -481,7 +502,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*RXDESC_WORD4*/
|
||||
|
||||
@@ -516,17 +538,33 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_MACID_RPT_BUFF(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \
|
||||
17)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, \
|
||||
16)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_SWPS_RPT_V1(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, \
|
||||
16)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814B_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_MACID_V1(rxdesc) \
|
||||
@@ -535,8 +573,20 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_FC_POWER_V1(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, \
|
||||
15)
|
||||
#define GET_RX_DESC_TXRPTMID_CTL_MASK_V1(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, \
|
||||
14)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_RX_SCRAMBLER(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \
|
||||
@@ -546,6 +596,14 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_SNIF_INFO(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x3f, \
|
||||
8)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_FC_POWER(rxdesc) \
|
||||
@@ -568,7 +626,7 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_PATTERN_IDX(rxdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \
|
||||
@@ -593,7 +651,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*RXDESC_WORD5*/
|
||||
|
||||
|
||||
@@ -608,4 +608,172 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
/*RXDESC_WORD0*/
|
||||
|
||||
#define GET_RX_DESC_EOR_8192F(rxdesc) GET_RX_DESC_EOR(rxdesc)
|
||||
#define GET_RX_DESC_SWDEC_8192F(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
|
||||
#define GET_RX_DESC_PHYST_8192F(rxdesc) GET_RX_DESC_PHYST(rxdesc)
|
||||
#define GET_RX_DESC_SHIFT_8192F(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
|
||||
#define GET_RX_DESC_QOS_8192F(rxdesc) GET_RX_DESC_QOS(rxdesc)
|
||||
#define GET_RX_DESC_SECURITY_8192F(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
|
||||
#define GET_RX_DESC_DRV_INFO_SIZE_8192F(rxdesc) \
|
||||
GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
|
||||
#define GET_RX_DESC_ICV_ERR_8192F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
|
||||
#define GET_RX_DESC_CRC32_8192F(rxdesc) GET_RX_DESC_CRC32(rxdesc)
|
||||
#define GET_RX_DESC_PKT_LEN_8192F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
|
||||
|
||||
/*RXDESC_WORD1*/
|
||||
|
||||
#define GET_RX_DESC_BC_8192F(rxdesc) GET_RX_DESC_BC(rxdesc)
|
||||
#define GET_RX_DESC_MC_8192F(rxdesc) GET_RX_DESC_MC(rxdesc)
|
||||
#define GET_RX_DESC_TY_PE_8192F(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
|
||||
#define GET_RX_DESC_MF_8192F(rxdesc) GET_RX_DESC_MF(rxdesc)
|
||||
#define GET_RX_DESC_MD_8192F(rxdesc) GET_RX_DESC_MD(rxdesc)
|
||||
#define GET_RX_DESC_PWR_8192F(rxdesc) GET_RX_DESC_PWR(rxdesc)
|
||||
#define GET_RX_DESC_PAM_8192F(rxdesc) GET_RX_DESC_PAM(rxdesc)
|
||||
#define GET_RX_DESC_CHK_VLD_8192F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
|
||||
#define GET_RX_DESC_RX_IS_TCP_UDP_8192F(rxdesc) \
|
||||
GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
|
||||
#define GET_RX_DESC_RX_IPV_8192F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
|
||||
#define GET_RX_DESC_CHKERR_8192F(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
|
||||
#define GET_RX_DESC_PAGGR_8192F(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
|
||||
#define GET_RX_DESC_RXID_MATCH_8192F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
|
||||
#define GET_RX_DESC_AMSDU_8192F(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
|
||||
#define GET_RX_DESC_MACID_VLD_8192F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
|
||||
#define GET_RX_DESC_TID_8192F(rxdesc) GET_RX_DESC_TID(rxdesc)
|
||||
#define GET_RX_DESC_MACID_8192F(rxdesc) GET_RX_DESC_MACID(rxdesc)
|
||||
|
||||
/*RXDESC_WORD2*/
|
||||
|
||||
#define GET_RX_DESC_FCS_OK_8192F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
|
||||
#define GET_RX_DESC_PPDU_CNT_8192F(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
|
||||
#define GET_RX_DESC_C2H_8192F(rxdesc) GET_RX_DESC_C2H(rxdesc)
|
||||
#define GET_RX_DESC_HWRSVD_8192F(rxdesc) GET_RX_DESC_HWRSVD_V1(rxdesc)
|
||||
#define GET_RX_DESC_RXMAGPKT_8192F(rxdesc) GET_RX_DESC_RXMAGPKT(rxdesc)
|
||||
#define GET_RX_DESC_WLANHD_IV_LEN_8192F(rxdesc) \
|
||||
GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
|
||||
#define GET_RX_DESC_RX_IS_QOS_8192F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
|
||||
#define GET_RX_DESC_FRAG_8192F(rxdesc) GET_RX_DESC_FRAG(rxdesc)
|
||||
#define GET_RX_DESC_SEQ_8192F(rxdesc) GET_RX_DESC_SEQ(rxdesc)
|
||||
|
||||
/*RXDESC_WORD3*/
|
||||
|
||||
#define GET_RX_DESC_MAGIC_WAKE_8192F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
|
||||
#define GET_RX_DESC_UNICAST_WAKE_8192F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
|
||||
#define GET_RX_DESC_PATTERN_MATCH_8192F(rxdesc) \
|
||||
GET_RX_DESC_PATTERN_MATCH(rxdesc)
|
||||
#define GET_RX_DESC_DMA_AGG_NUM_8192F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
|
||||
#define GET_RX_DESC_BSSID_FIT_1_0_8192F(rxdesc) \
|
||||
GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
|
||||
#define GET_RX_DESC_EOSP_8192F(rxdesc) GET_RX_DESC_EOSP(rxdesc)
|
||||
#define GET_RX_DESC_HTC_8192F(rxdesc) GET_RX_DESC_HTC(rxdesc)
|
||||
#define GET_RX_DESC_RX_RATE_8192F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
|
||||
|
||||
/*RXDESC_WORD4*/
|
||||
|
||||
#define GET_RX_DESC_A1_FIT_8192F(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
|
||||
#define GET_RX_DESC_MACID_RPT_BUFF_8192F(rxdesc) \
|
||||
GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
|
||||
#define GET_RX_DESC_SWPS_RPT_8192F(rxdesc) GET_RX_DESC_SWPS_RPT_V1(rxdesc)
|
||||
#define GET_RX_DESC_FC_POWER_8192F(rxdesc) GET_RX_DESC_FC_POWER_V1(rxdesc)
|
||||
#define GET_RX_DESC_TXRPTMID_CTL_MASK_8192F(rxdesc) \
|
||||
GET_RX_DESC_TXRPTMID_CTL_MASK_V1(rxdesc)
|
||||
#define GET_RX_DESC_SNIF_INFO_8192F(rxdesc) GET_RX_DESC_SNIF_INFO(rxdesc)
|
||||
#define GET_RX_DESC_PATTERN_IDX_8192F(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)
|
||||
|
||||
/*RXDESC_WORD5*/
|
||||
|
||||
#define GET_RX_DESC_TSFL_8192F(rxdesc) GET_RX_DESC_TSFL(rxdesc)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*RXDESC_WORD0*/
|
||||
|
||||
#define GET_RX_DESC_EOR_8812F(rxdesc) GET_RX_DESC_EOR(rxdesc)
|
||||
#define GET_RX_DESC_PHYPKTIDC_8812F(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
|
||||
#define GET_RX_DESC_SWDEC_8812F(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
|
||||
#define GET_RX_DESC_PHYST_8812F(rxdesc) GET_RX_DESC_PHYST(rxdesc)
|
||||
#define GET_RX_DESC_SHIFT_8812F(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
|
||||
#define GET_RX_DESC_QOS_8812F(rxdesc) GET_RX_DESC_QOS(rxdesc)
|
||||
#define GET_RX_DESC_SECURITY_8812F(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
|
||||
#define GET_RX_DESC_DRV_INFO_SIZE_8812F(rxdesc) \
|
||||
GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
|
||||
#define GET_RX_DESC_ICV_ERR_8812F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
|
||||
#define GET_RX_DESC_CRC32_8812F(rxdesc) GET_RX_DESC_CRC32(rxdesc)
|
||||
#define GET_RX_DESC_PKT_LEN_8812F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
|
||||
|
||||
/*RXDESC_WORD1*/
|
||||
|
||||
#define GET_RX_DESC_BC_8812F(rxdesc) GET_RX_DESC_BC(rxdesc)
|
||||
#define GET_RX_DESC_MC_8812F(rxdesc) GET_RX_DESC_MC(rxdesc)
|
||||
#define GET_RX_DESC_TY_PE_8812F(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
|
||||
#define GET_RX_DESC_MF_8812F(rxdesc) GET_RX_DESC_MF(rxdesc)
|
||||
#define GET_RX_DESC_MD_8812F(rxdesc) GET_RX_DESC_MD(rxdesc)
|
||||
#define GET_RX_DESC_PWR_8812F(rxdesc) GET_RX_DESC_PWR(rxdesc)
|
||||
#define GET_RX_DESC_PAM_8812F(rxdesc) GET_RX_DESC_PAM(rxdesc)
|
||||
#define GET_RX_DESC_CHK_VLD_8812F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
|
||||
#define GET_RX_DESC_RX_IS_TCP_UDP_8812F(rxdesc) \
|
||||
GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
|
||||
#define GET_RX_DESC_RX_IPV_8812F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
|
||||
#define GET_RX_DESC_CHKERR_8812F(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
|
||||
#define GET_RX_DESC_PAGGR_8812F(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
|
||||
#define GET_RX_DESC_RXID_MATCH_8812F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
|
||||
#define GET_RX_DESC_AMSDU_8812F(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
|
||||
#define GET_RX_DESC_MACID_VLD_8812F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
|
||||
#define GET_RX_DESC_TID_8812F(rxdesc) GET_RX_DESC_TID(rxdesc)
|
||||
#define GET_RX_DESC_MACID_8812F(rxdesc) GET_RX_DESC_MACID(rxdesc)
|
||||
|
||||
/*RXDESC_WORD2*/
|
||||
|
||||
#define GET_RX_DESC_FCS_OK_8812F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
|
||||
#define GET_RX_DESC_PPDU_CNT_8812F(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
|
||||
#define GET_RX_DESC_C2H_8812F(rxdesc) GET_RX_DESC_C2H(rxdesc)
|
||||
#define GET_RX_DESC_HWRSVD_8812F(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)
|
||||
#define GET_RX_DESC_WLANHD_IV_LEN_8812F(rxdesc) \
|
||||
GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
|
||||
#define GET_RX_DESC_RX_STATISTICS_8812F(rxdesc) \
|
||||
GET_RX_DESC_RX_STATISTICS(rxdesc)
|
||||
#define GET_RX_DESC_RX_IS_QOS_8812F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
|
||||
#define GET_RX_DESC_FRAG_8812F(rxdesc) GET_RX_DESC_FRAG(rxdesc)
|
||||
#define GET_RX_DESC_SEQ_8812F(rxdesc) GET_RX_DESC_SEQ(rxdesc)
|
||||
|
||||
/*RXDESC_WORD3*/
|
||||
|
||||
#define GET_RX_DESC_MAGIC_WAKE_8812F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
|
||||
#define GET_RX_DESC_UNICAST_WAKE_8812F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
|
||||
#define GET_RX_DESC_PATTERN_MATCH_8812F(rxdesc) \
|
||||
GET_RX_DESC_PATTERN_MATCH(rxdesc)
|
||||
#define GET_RX_DESC_RXPAYLOAD_MATCH_8812F(rxdesc) \
|
||||
GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)
|
||||
#define GET_RX_DESC_RXPAYLOAD_ID_8812F(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)
|
||||
#define GET_RX_DESC_DMA_AGG_NUM_8812F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
|
||||
#define GET_RX_DESC_BSSID_FIT_1_0_8812F(rxdesc) \
|
||||
GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
|
||||
#define GET_RX_DESC_EOSP_8812F(rxdesc) GET_RX_DESC_EOSP(rxdesc)
|
||||
#define GET_RX_DESC_HTC_8812F(rxdesc) GET_RX_DESC_HTC(rxdesc)
|
||||
#define GET_RX_DESC_BSSID_FIT_4_2_8812F(rxdesc) \
|
||||
GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
|
||||
#define GET_RX_DESC_RX_RATE_8812F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
|
||||
|
||||
/*RXDESC_WORD4*/
|
||||
|
||||
#define GET_RX_DESC_A1_FIT_8812F(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
|
||||
#define GET_RX_DESC_MACID_RPT_BUFF_8812F(rxdesc) \
|
||||
GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
|
||||
#define GET_RX_DESC_RX_PRE_NDP_VLD_8812F(rxdesc) \
|
||||
GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
|
||||
#define GET_RX_DESC_RX_SCRAMBLER_8812F(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
|
||||
#define GET_RX_DESC_RX_EOF_8812F(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
|
||||
#define GET_RX_DESC_PATTERN_IDX_8812F(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)
|
||||
|
||||
/*RXDESC_WORD5*/
|
||||
|
||||
#define GET_RX_DESC_TSFL_8812F(rxdesc) GET_RX_DESC_TSFL(rxdesc)
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -16,11 +16,19 @@
|
||||
#ifndef _HALMAC_RX_DESC_NIC_H_
|
||||
#define _HALMAC_RX_DESC_NIC_H_
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*RXDESC_WORD0*/
|
||||
|
||||
#define GET_RX_DESC_EOR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 30, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_PHYPKTIDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 28, 1)
|
||||
|
||||
#endif
|
||||
@@ -33,7 +41,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_SWDEC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 27, 1)
|
||||
#define GET_RX_DESC_PHYST(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 26, 1)
|
||||
@@ -53,7 +61,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_TY_PE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 28, 2)
|
||||
|
||||
@@ -67,7 +76,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_MF(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 27, 1)
|
||||
#define GET_RX_DESC_MD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 26, 1)
|
||||
@@ -76,7 +85,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_PAM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 24, 1)
|
||||
|
||||
@@ -89,7 +99,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_CHK_VLD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 23, 1)
|
||||
|
||||
@@ -104,7 +115,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 22, 1)
|
||||
#define GET_RX_DESC_RX_IPV(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 21, 1)
|
||||
@@ -112,7 +123,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_CHKERR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 20, 1)
|
||||
|
||||
@@ -128,7 +140,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_PAGGR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 15, 1)
|
||||
|
||||
@@ -141,7 +154,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_RXID_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 14, 1)
|
||||
|
||||
@@ -155,14 +169,15 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_AMSDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 13, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_MACID_VLD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 12, 1)
|
||||
|
||||
@@ -170,14 +185,15 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_TID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 8, 4)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_MACID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 0, 7)
|
||||
|
||||
@@ -194,7 +210,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_PPDU_CNT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 29, 2)
|
||||
|
||||
@@ -202,26 +219,26 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_C2H(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 28, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8198F_SUPPORT)
|
||||
#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_HWRSVD_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 25, 3)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_HWRSVD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 24, 4)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8198F_SUPPORT)
|
||||
#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_RXMAGPKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 24, 1)
|
||||
|
||||
@@ -229,7 +246,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_WLANHD_IV_LEN(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 18, 6)
|
||||
|
||||
@@ -241,14 +258,15 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822C_SUPPORT)
|
||||
#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_RX_STATISTICS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 17, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_RX_IS_QOS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 16, 1)
|
||||
|
||||
@@ -262,7 +280,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_FRAG(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 12, 4)
|
||||
#define GET_RX_DESC_SEQ(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 0, 12)
|
||||
@@ -275,7 +293,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_PATTERN_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 29, 1)
|
||||
|
||||
@@ -288,7 +307,7 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) \
|
||||
LE_BITS_TO_4BYTE(rxdesc + 0x0C, 28, 1)
|
||||
@@ -298,14 +317,15 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_DMA_AGG_NUM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 16, 8)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_BSSID_FIT_1_0(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 12, 2)
|
||||
#define GET_RX_DESC_EOSP(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 11, 1)
|
||||
@@ -320,7 +340,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_HTC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 10, 1)
|
||||
|
||||
@@ -335,7 +355,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_BSSID_FIT_4_2(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 7, 3)
|
||||
|
||||
@@ -349,14 +370,15 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_RX_RATE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 0, 7)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*RXDESC_WORD4*/
|
||||
|
||||
@@ -383,29 +405,58 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_MACID_RPT_BUFF(rxdesc) \
|
||||
LE_BITS_TO_4BYTE(rxdesc + 0x10, 17, 7)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) \
|
||||
LE_BITS_TO_4BYTE(rxdesc + 0x10, 16, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_SWPS_RPT_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 16, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814B_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_MACID_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 15, 8)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_FC_POWER_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 15, 1)
|
||||
#define GET_RX_DESC_TXRPTMID_CTL_MASK_V1(rxdesc) \
|
||||
LE_BITS_TO_4BYTE(rxdesc + 0x10, 14, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_RX_SCRAMBLER(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 9, 7)
|
||||
#define GET_RX_DESC_RX_EOF(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 8, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_SNIF_INFO(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 8, 6)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_FC_POWER(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 7, 1)
|
||||
@@ -426,7 +477,7 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define GET_RX_DESC_PATTERN_IDX(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 8)
|
||||
|
||||
@@ -445,7 +496,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*RXDESC_WORD5*/
|
||||
|
||||
|
||||
@@ -16,7 +16,8 @@
|
||||
#ifndef _HALMAC_TX_BD_NIC_H_
|
||||
#define _HALMAC_TX_BD_NIC_H_
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||\
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXBD_DW0*/
|
||||
|
||||
|
||||
@@ -16,7 +16,8 @@
|
||||
#ifndef _HALMAC_TX_DESC_AP_H_
|
||||
#define _HALMAC_TX_DESC_AP_H_
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXDESC_WORD0*/
|
||||
|
||||
@@ -47,7 +48,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_GF(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
|
||||
@@ -76,7 +78,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_NO_ACM(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
|
||||
@@ -105,7 +108,7 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
|
||||
@@ -120,7 +123,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
|
||||
@@ -131,6 +135,13 @@
|
||||
#define GET_TX_DESC_AMSDU_PAD_EN(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \
|
||||
27)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_LS(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
|
||||
value, 0x1, 26)
|
||||
@@ -140,6 +151,13 @@
|
||||
#define GET_TX_DESC_LS(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \
|
||||
26)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_HTC(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
|
||||
value, 0x1, 25)
|
||||
@@ -177,7 +195,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_OFFSET(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
|
||||
@@ -244,8 +262,23 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_KEYID_SEL(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
|
||||
value, 0x1, 30)
|
||||
#define SET_TX_DESC_KEYID_SEL_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 30)
|
||||
#define GET_TX_DESC_KEYID_SEL(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
|
||||
30)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_MOREDATA(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
|
||||
@@ -283,7 +316,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_PKT_OFFSET(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
|
||||
@@ -312,7 +346,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_SEC_TYPE(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
|
||||
@@ -359,7 +394,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_PIFS(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
|
||||
@@ -407,7 +443,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_QSEL(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
|
||||
@@ -435,7 +471,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_MACID(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
|
||||
@@ -464,7 +501,7 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXDESC_WORD2*/
|
||||
|
||||
@@ -495,7 +532,7 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_FTM_EN(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
|
||||
@@ -538,7 +575,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_G_ID(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
|
||||
@@ -581,7 +619,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_BT_NULL(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
|
||||
@@ -655,7 +694,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_NULL_1(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
|
||||
@@ -706,7 +746,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_TRI_FRAME(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
|
||||
@@ -720,7 +761,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_P_AID(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
|
||||
@@ -749,7 +791,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXDESC_WORD3*/
|
||||
|
||||
@@ -807,7 +850,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_NAVUSEHDR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
|
||||
@@ -872,7 +916,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_DISDATAFB(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
|
||||
@@ -932,7 +977,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_WHEADER_LEN(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
|
||||
@@ -961,7 +1007,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXDESC_WORD4*/
|
||||
|
||||
@@ -1060,7 +1107,7 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822C_SUPPORT)
|
||||
#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANTSEL_EN_V1(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
|
||||
@@ -1089,7 +1136,7 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822C_SUPPORT)
|
||||
#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
|
||||
@@ -1103,8 +1150,23 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_TXPWR_OFSET_TYPE_V1(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
|
||||
value, 0x7, 28)
|
||||
#define SET_TX_DESC_TXPWR_OFSET_TYPE_V1_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword5, value, 0x7, 28)
|
||||
#define GET_TX_DESC_TXPWR_OFSET_TYPE_V1(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x7, \
|
||||
28)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_TX_ANT(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
|
||||
@@ -1132,8 +1194,23 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_DROP_ID_V1(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
|
||||
value, 0x3, 22)
|
||||
#define SET_TX_DESC_DROP_ID_V1_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 22)
|
||||
#define GET_TX_DESC_DROP_ID_V1(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, \
|
||||
22)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_PORT_ID(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
|
||||
@@ -1147,8 +1224,22 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_PORT_ID_V1(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
|
||||
value, 0x1, 21)
|
||||
#define SET_TX_DESC_PORT_ID_V1_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 21)
|
||||
#define GET_TX_DESC_PORT_ID_V1(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \
|
||||
21)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_MULTIPLE_PORT(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
|
||||
@@ -1163,7 +1254,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
|
||||
@@ -1177,7 +1269,8 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_RTS_SC(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
|
||||
@@ -1191,7 +1284,8 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
|
||||
@@ -1206,7 +1300,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_RTS_SHORT(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
|
||||
@@ -1270,7 +1365,7 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXDESC_WORD6*/
|
||||
|
||||
@@ -1300,8 +1395,22 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANT_MAPC_V2(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
|
||||
value, 0x3, 30)
|
||||
#define SET_TX_DESC_ANT_MAPC_V2_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 30)
|
||||
#define GET_TX_DESC_ANT_MAPC_V2(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
|
||||
30)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANT_MAPD(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
|
||||
@@ -1329,8 +1438,22 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANT_MAPB_V2(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
|
||||
value, 0x3, 28)
|
||||
#define SET_TX_DESC_ANT_MAPB_V2_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 28)
|
||||
#define GET_TX_DESC_ANT_MAPB_V2(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
|
||||
28)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANT_MAPC(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
|
||||
@@ -1358,8 +1481,22 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANT_MAPA_V2(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
|
||||
value, 0x3, 26)
|
||||
#define SET_TX_DESC_ANT_MAPA_V2_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 26)
|
||||
#define GET_TX_DESC_ANT_MAPA_V2(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
|
||||
26)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANT_MAPB(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
|
||||
@@ -1387,8 +1524,22 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANTSEL_D_V1(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
|
||||
value, 0x3, 24)
|
||||
#define SET_TX_DESC_ANTSEL_D_V1_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 24)
|
||||
#define GET_TX_DESC_ANTSEL_D_V1(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
|
||||
24)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANT_MAPA(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
|
||||
@@ -1399,6 +1550,26 @@
|
||||
#define GET_TX_DESC_ANT_MAPA(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
|
||||
22)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANTSEL_C_V2(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
|
||||
value, 0x3, 22)
|
||||
#define SET_TX_DESC_ANTSEL_C_V2_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 22)
|
||||
#define GET_TX_DESC_ANTSEL_C_V2(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
|
||||
22)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANTSEL_C(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
|
||||
value, 0x3, 20)
|
||||
@@ -1425,8 +1596,22 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANTSEL_B_V2(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
|
||||
value, 0x7, 19)
|
||||
#define SET_TX_DESC_ANTSEL_B_V2_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword6, value, 0x7, 19)
|
||||
#define GET_TX_DESC_ANTSEL_B_V2(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x7, \
|
||||
19)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANTSEL_B(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
|
||||
@@ -1463,8 +1648,23 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANTSEL_A_V2(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
|
||||
value, 0x7, 16)
|
||||
#define SET_TX_DESC_ANTSEL_A_V2_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword6, value, 0x7, 16)
|
||||
#define GET_TX_DESC_ANTSEL_A_V2(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x7, \
|
||||
16)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_MBSSID(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
|
||||
@@ -1479,7 +1679,7 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_SW_DEFINE(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
|
||||
@@ -1493,7 +1693,7 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8198F_SUPPORT)
|
||||
#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_SWPS_SEQ(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
|
||||
@@ -1508,7 +1708,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXDESC_WORD7*/
|
||||
|
||||
@@ -1521,6 +1722,13 @@
|
||||
#define GET_TX_DESC_DMA_TXAGG_NUM(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xff, \
|
||||
24)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
|
||||
value, 0xff, 24)
|
||||
@@ -1530,6 +1738,36 @@
|
||||
#define GET_TX_DESC_FINAL_DATA_RATE(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xff, \
|
||||
24)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANT_MAPD_V2(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
|
||||
value, 0x3, 22)
|
||||
#define SET_TX_DESC_ANT_MAPD_V2_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword7, value, 0x3, 22)
|
||||
#define GET_TX_DESC_ANT_MAPD_V2(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x3, \
|
||||
22)
|
||||
#define SET_TX_DESC_ANTSEL_EN_V2(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
|
||||
value, 0x1, 21)
|
||||
#define SET_TX_DESC_ANTSEL_EN_V2_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1, 21)
|
||||
#define GET_TX_DESC_ANTSEL_EN_V2(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1, \
|
||||
21)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_NTX_MAP(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
|
||||
value, 0xf, 20)
|
||||
@@ -1565,8 +1803,23 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_MBSSID_EX_V1(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
|
||||
value, 0x1, 16)
|
||||
#define SET_TX_DESC_MBSSID_EX_V1_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1, 16)
|
||||
#define GET_TX_DESC_MBSSID_EX_V1(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1, \
|
||||
16)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
|
||||
@@ -1596,6 +1849,12 @@
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, \
|
||||
0xffff, 0)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXDESC_WORD8*/
|
||||
|
||||
#define SET_TX_DESC_TXWIFI_CP(txdesc, value) \
|
||||
@@ -1670,6 +1929,13 @@
|
||||
#define GET_TX_DESC_SMH_EN(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \
|
||||
24)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_TAILPAGE_L(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
|
||||
value, 0xff, 24)
|
||||
@@ -1697,6 +1963,13 @@
|
||||
#define GET_TX_DESC_NEXTHEADPAGE_L(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xff, \
|
||||
16)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_EN_HWSEQ(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
|
||||
value, 0x1, 15)
|
||||
@@ -1706,6 +1979,12 @@
|
||||
#define GET_TX_DESC_EN_HWSEQ(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \
|
||||
15)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_EN_HWEXSEQ(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
|
||||
value, 0x1, 14)
|
||||
@@ -1715,6 +1994,27 @@
|
||||
#define GET_TX_DESC_EN_HWEXSEQ(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \
|
||||
14)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_EN_HWSEQ_MODE(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
|
||||
value, 0x3, 14)
|
||||
#define SET_TX_DESC_EN_HWSEQ_MODE_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 14)
|
||||
#define GET_TX_DESC_EN_HWSEQ_MODE(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, \
|
||||
14)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_DATA_RC(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
|
||||
value, 0x3f, 8)
|
||||
@@ -1742,6 +2042,12 @@
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3f, \
|
||||
0)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXDESC_WORD9*/
|
||||
|
||||
#define SET_TX_DESC_TAILPAGE_H(txdesc, value) \
|
||||
@@ -1762,6 +2068,27 @@
|
||||
#define GET_TX_DESC_NEXTHEADPAGE_H(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xf, \
|
||||
24)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_FINAL_DATA_RATE_V1(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
|
||||
value, 0xff, 24)
|
||||
#define SET_TX_DESC_FINAL_DATA_RATE_V1_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword9, value, 0xff, 24)
|
||||
#define GET_TX_DESC_FINAL_DATA_RATE_V1(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xff, \
|
||||
24)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_SW_SEQ(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
|
||||
value, 0xfff, 12)
|
||||
@@ -1771,6 +2098,13 @@
|
||||
#define GET_TX_DESC_SW_SEQ(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, \
|
||||
0xfff, 12)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_TXBF_PATH(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
|
||||
value, 0x1, 11)
|
||||
@@ -1780,6 +2114,13 @@
|
||||
#define GET_TX_DESC_TXBF_PATH(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, \
|
||||
11)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_PADDING_LEN(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
|
||||
value, 0x7ff, 0)
|
||||
@@ -1801,10 +2142,34 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
#if (HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*WORD10*/
|
||||
|
||||
#define SET_TX_DESC_HT_DATA_SND(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
|
||||
value, 0x1, 31)
|
||||
#define SET_TX_DESC_HT_DATA_SND_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 31)
|
||||
#define GET_TX_DESC_HT_DATA_SND(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
|
||||
31)
|
||||
#define SET_TX_DESC_SHCUT_CAM(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
|
||||
value, 0x3f, 16)
|
||||
#define SET_TX_DESC_SHCUT_CAM_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword10, value, 0x3f, 16)
|
||||
#define GET_TX_DESC_SHCUT_CAM(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, \
|
||||
0x3f, 16)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_MU_DATARATE(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
|
||||
value, 0xff, 8)
|
||||
@@ -1823,6 +2188,35 @@
|
||||
#define GET_TX_DESC_MU_RC(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0xf, \
|
||||
4)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_NDPA_RATE_SEL(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
|
||||
value, 0x1, 3)
|
||||
#define SET_TX_DESC_NDPA_RATE_SEL_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 3)
|
||||
#define GET_TX_DESC_NDPA_RATE_SEL(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
|
||||
3)
|
||||
#define SET_TX_DESC_HW_NDPA_EN(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
|
||||
value, 0x1, 2)
|
||||
#define SET_TX_DESC_HW_NDPA_EN_NO_CLR(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_NO_CLR( \
|
||||
((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 2)
|
||||
#define GET_TX_DESC_HW_NDPA_EN(txdesc) \
|
||||
HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
|
||||
2)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_SND_PKT_SEL(txdesc, value) \
|
||||
HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
|
||||
value, 0x3, 0)
|
||||
|
||||
@@ -2382,4 +2382,727 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
/*TXDESC_WORD0*/
|
||||
|
||||
#define SET_TX_DESC_GF_8192F(txdesc, value) SET_TX_DESC_GF(txdesc, value)
|
||||
#define GET_TX_DESC_GF_8192F(txdesc) GET_TX_DESC_GF(txdesc)
|
||||
#define SET_TX_DESC_NO_ACM_8192F(txdesc, value) \
|
||||
SET_TX_DESC_NO_ACM(txdesc, value)
|
||||
#define GET_TX_DESC_NO_ACM_8192F(txdesc) GET_TX_DESC_NO_ACM(txdesc)
|
||||
#define SET_TX_DESC_AMSDU_PAD_EN_8192F(txdesc, value) \
|
||||
SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)
|
||||
#define GET_TX_DESC_AMSDU_PAD_EN_8192F(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)
|
||||
#define SET_TX_DESC_HTC_8192F(txdesc, value) SET_TX_DESC_HTC(txdesc, value)
|
||||
#define GET_TX_DESC_HTC_8192F(txdesc) GET_TX_DESC_HTC(txdesc)
|
||||
#define SET_TX_DESC_BMC_8192F(txdesc, value) SET_TX_DESC_BMC(txdesc, value)
|
||||
#define GET_TX_DESC_BMC_8192F(txdesc) GET_TX_DESC_BMC(txdesc)
|
||||
#define SET_TX_DESC_OFFSET_8192F(txdesc, value) \
|
||||
SET_TX_DESC_OFFSET(txdesc, value)
|
||||
#define GET_TX_DESC_OFFSET_8192F(txdesc) GET_TX_DESC_OFFSET(txdesc)
|
||||
#define SET_TX_DESC_TXPKTSIZE_8192F(txdesc, value) \
|
||||
SET_TX_DESC_TXPKTSIZE(txdesc, value)
|
||||
#define GET_TX_DESC_TXPKTSIZE_8192F(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
|
||||
|
||||
/*WORD1*/
|
||||
|
||||
#define SET_TX_DESC_KEYID_SEL_8192F(txdesc, value) \
|
||||
SET_TX_DESC_KEYID_SEL(txdesc, value)
|
||||
#define GET_TX_DESC_KEYID_SEL_8192F(txdesc) GET_TX_DESC_KEYID_SEL(txdesc)
|
||||
#define SET_TX_DESC_MOREDATA_8192F(txdesc, value) \
|
||||
SET_TX_DESC_MOREDATA(txdesc, value)
|
||||
#define GET_TX_DESC_MOREDATA_8192F(txdesc) GET_TX_DESC_MOREDATA(txdesc)
|
||||
#define SET_TX_DESC_PKT_OFFSET_8192F(txdesc, value) \
|
||||
SET_TX_DESC_PKT_OFFSET(txdesc, value)
|
||||
#define GET_TX_DESC_PKT_OFFSET_8192F(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)
|
||||
#define SET_TX_DESC_SEC_TYPE_8192F(txdesc, value) \
|
||||
SET_TX_DESC_SEC_TYPE(txdesc, value)
|
||||
#define GET_TX_DESC_SEC_TYPE_8192F(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)
|
||||
#define SET_TX_DESC_EN_DESC_ID_8192F(txdesc, value) \
|
||||
SET_TX_DESC_EN_DESC_ID(txdesc, value)
|
||||
#define GET_TX_DESC_EN_DESC_ID_8192F(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)
|
||||
#define SET_TX_DESC_RATE_ID_8192F(txdesc, value) \
|
||||
SET_TX_DESC_RATE_ID(txdesc, value)
|
||||
#define GET_TX_DESC_RATE_ID_8192F(txdesc) GET_TX_DESC_RATE_ID(txdesc)
|
||||
#define SET_TX_DESC_PIFS_8192F(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)
|
||||
#define GET_TX_DESC_PIFS_8192F(txdesc) GET_TX_DESC_PIFS(txdesc)
|
||||
#define SET_TX_DESC_LSIG_TXOP_EN_8192F(txdesc, value) \
|
||||
SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)
|
||||
#define GET_TX_DESC_LSIG_TXOP_EN_8192F(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)
|
||||
#define SET_TX_DESC_RD_NAV_EXT_8192F(txdesc, value) \
|
||||
SET_TX_DESC_RD_NAV_EXT(txdesc, value)
|
||||
#define GET_TX_DESC_RD_NAV_EXT_8192F(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)
|
||||
#define SET_TX_DESC_QSEL_8192F(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
|
||||
#define GET_TX_DESC_QSEL_8192F(txdesc) GET_TX_DESC_QSEL(txdesc)
|
||||
#define SET_TX_DESC_MACID_8192F(txdesc, value) SET_TX_DESC_MACID(txdesc, value)
|
||||
#define GET_TX_DESC_MACID_8192F(txdesc) GET_TX_DESC_MACID(txdesc)
|
||||
|
||||
/*TXDESC_WORD2*/
|
||||
|
||||
#define SET_TX_DESC_FTM_EN_8192F(txdesc, value) \
|
||||
SET_TX_DESC_FTM_EN(txdesc, value)
|
||||
#define GET_TX_DESC_FTM_EN_8192F(txdesc) GET_TX_DESC_FTM_EN(txdesc)
|
||||
#define SET_TX_DESC_G_ID_8192F(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)
|
||||
#define GET_TX_DESC_G_ID_8192F(txdesc) GET_TX_DESC_G_ID(txdesc)
|
||||
#define SET_TX_DESC_BT_NULL_8192F(txdesc, value) \
|
||||
SET_TX_DESC_BT_NULL(txdesc, value)
|
||||
#define GET_TX_DESC_BT_NULL_8192F(txdesc) GET_TX_DESC_BT_NULL(txdesc)
|
||||
#define SET_TX_DESC_AMPDU_DENSITY_8192F(txdesc, value) \
|
||||
SET_TX_DESC_AMPDU_DENSITY(txdesc, value)
|
||||
#define GET_TX_DESC_AMPDU_DENSITY_8192F(txdesc) \
|
||||
GET_TX_DESC_AMPDU_DENSITY(txdesc)
|
||||
#define SET_TX_DESC_SPE_RPT_8192F(txdesc, value) \
|
||||
SET_TX_DESC_SPE_RPT(txdesc, value)
|
||||
#define GET_TX_DESC_SPE_RPT_8192F(txdesc) GET_TX_DESC_SPE_RPT(txdesc)
|
||||
#define SET_TX_DESC_RAW_8192F(txdesc, value) SET_TX_DESC_RAW(txdesc, value)
|
||||
#define GET_TX_DESC_RAW_8192F(txdesc) GET_TX_DESC_RAW(txdesc)
|
||||
#define SET_TX_DESC_MOREFRAG_8192F(txdesc, value) \
|
||||
SET_TX_DESC_MOREFRAG(txdesc, value)
|
||||
#define GET_TX_DESC_MOREFRAG_8192F(txdesc) GET_TX_DESC_MOREFRAG(txdesc)
|
||||
#define SET_TX_DESC_BK_8192F(txdesc, value) SET_TX_DESC_BK(txdesc, value)
|
||||
#define GET_TX_DESC_BK_8192F(txdesc) GET_TX_DESC_BK(txdesc)
|
||||
#define SET_TX_DESC_NULL_1_8192F(txdesc, value) \
|
||||
SET_TX_DESC_NULL_1(txdesc, value)
|
||||
#define GET_TX_DESC_NULL_1_8192F(txdesc) GET_TX_DESC_NULL_1(txdesc)
|
||||
#define SET_TX_DESC_NULL_0_8192F(txdesc, value) \
|
||||
SET_TX_DESC_NULL_0(txdesc, value)
|
||||
#define GET_TX_DESC_NULL_0_8192F(txdesc) GET_TX_DESC_NULL_0(txdesc)
|
||||
#define SET_TX_DESC_RDG_EN_8192F(txdesc, value) \
|
||||
SET_TX_DESC_RDG_EN(txdesc, value)
|
||||
#define GET_TX_DESC_RDG_EN_8192F(txdesc) GET_TX_DESC_RDG_EN(txdesc)
|
||||
#define SET_TX_DESC_AGG_EN_8192F(txdesc, value) \
|
||||
SET_TX_DESC_AGG_EN(txdesc, value)
|
||||
#define GET_TX_DESC_AGG_EN_8192F(txdesc) GET_TX_DESC_AGG_EN(txdesc)
|
||||
#define SET_TX_DESC_CCA_RTS_8192F(txdesc, value) \
|
||||
SET_TX_DESC_CCA_RTS(txdesc, value)
|
||||
#define GET_TX_DESC_CCA_RTS_8192F(txdesc) GET_TX_DESC_CCA_RTS(txdesc)
|
||||
#define SET_TX_DESC_TRI_FRAME_8192F(txdesc, value) \
|
||||
SET_TX_DESC_TRI_FRAME(txdesc, value)
|
||||
#define GET_TX_DESC_TRI_FRAME_8192F(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)
|
||||
#define SET_TX_DESC_P_AID_8192F(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)
|
||||
#define GET_TX_DESC_P_AID_8192F(txdesc) GET_TX_DESC_P_AID(txdesc)
|
||||
|
||||
/*TXDESC_WORD3*/
|
||||
|
||||
#define SET_TX_DESC_AMPDU_MAX_TIME_8192F(txdesc, value) \
|
||||
SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)
|
||||
#define GET_TX_DESC_AMPDU_MAX_TIME_8192F(txdesc) \
|
||||
GET_TX_DESC_AMPDU_MAX_TIME(txdesc)
|
||||
#define SET_TX_DESC_NDPA_8192F(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)
|
||||
#define GET_TX_DESC_NDPA_8192F(txdesc) GET_TX_DESC_NDPA(txdesc)
|
||||
#define SET_TX_DESC_MAX_AGG_NUM_8192F(txdesc, value) \
|
||||
SET_TX_DESC_MAX_AGG_NUM(txdesc, value)
|
||||
#define GET_TX_DESC_MAX_AGG_NUM_8192F(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)
|
||||
#define SET_TX_DESC_USE_MAX_TIME_EN_8192F(txdesc, value) \
|
||||
SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)
|
||||
#define GET_TX_DESC_USE_MAX_TIME_EN_8192F(txdesc) \
|
||||
GET_TX_DESC_USE_MAX_TIME_EN(txdesc)
|
||||
#define SET_TX_DESC_NAVUSEHDR_8192F(txdesc, value) \
|
||||
SET_TX_DESC_NAVUSEHDR(txdesc, value)
|
||||
#define GET_TX_DESC_NAVUSEHDR_8192F(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)
|
||||
#define SET_TX_DESC_CHK_EN_8192F(txdesc, value) \
|
||||
SET_TX_DESC_CHK_EN(txdesc, value)
|
||||
#define GET_TX_DESC_CHK_EN_8192F(txdesc) GET_TX_DESC_CHK_EN(txdesc)
|
||||
#define SET_TX_DESC_HW_RTS_EN_8192F(txdesc, value) \
|
||||
SET_TX_DESC_HW_RTS_EN(txdesc, value)
|
||||
#define GET_TX_DESC_HW_RTS_EN_8192F(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)
|
||||
#define SET_TX_DESC_RTSEN_8192F(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)
|
||||
#define GET_TX_DESC_RTSEN_8192F(txdesc) GET_TX_DESC_RTSEN(txdesc)
|
||||
#define SET_TX_DESC_CTS2SELF_8192F(txdesc, value) \
|
||||
SET_TX_DESC_CTS2SELF(txdesc, value)
|
||||
#define GET_TX_DESC_CTS2SELF_8192F(txdesc) GET_TX_DESC_CTS2SELF(txdesc)
|
||||
#define SET_TX_DESC_DISDATAFB_8192F(txdesc, value) \
|
||||
SET_TX_DESC_DISDATAFB(txdesc, value)
|
||||
#define GET_TX_DESC_DISDATAFB_8192F(txdesc) GET_TX_DESC_DISDATAFB(txdesc)
|
||||
#define SET_TX_DESC_DISRTSFB_8192F(txdesc, value) \
|
||||
SET_TX_DESC_DISRTSFB(txdesc, value)
|
||||
#define GET_TX_DESC_DISRTSFB_8192F(txdesc) GET_TX_DESC_DISRTSFB(txdesc)
|
||||
#define SET_TX_DESC_USE_RATE_8192F(txdesc, value) \
|
||||
SET_TX_DESC_USE_RATE(txdesc, value)
|
||||
#define GET_TX_DESC_USE_RATE_8192F(txdesc) GET_TX_DESC_USE_RATE(txdesc)
|
||||
#define SET_TX_DESC_HW_SSN_SEL_8192F(txdesc, value) \
|
||||
SET_TX_DESC_HW_SSN_SEL(txdesc, value)
|
||||
#define GET_TX_DESC_HW_SSN_SEL_8192F(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)
|
||||
#define SET_TX_DESC_WHEADER_LEN_8192F(txdesc, value) \
|
||||
SET_TX_DESC_WHEADER_LEN(txdesc, value)
|
||||
#define GET_TX_DESC_WHEADER_LEN_8192F(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)
|
||||
|
||||
/*TXDESC_WORD4*/
|
||||
|
||||
#define SET_TX_DESC_PCTS_MASK_IDX_8192F(txdesc, value) \
|
||||
SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)
|
||||
#define GET_TX_DESC_PCTS_MASK_IDX_8192F(txdesc) \
|
||||
GET_TX_DESC_PCTS_MASK_IDX(txdesc)
|
||||
#define SET_TX_DESC_PCTS_EN_8192F(txdesc, value) \
|
||||
SET_TX_DESC_PCTS_EN(txdesc, value)
|
||||
#define GET_TX_DESC_PCTS_EN_8192F(txdesc) GET_TX_DESC_PCTS_EN(txdesc)
|
||||
#define SET_TX_DESC_RTSRATE_8192F(txdesc, value) \
|
||||
SET_TX_DESC_RTSRATE(txdesc, value)
|
||||
#define GET_TX_DESC_RTSRATE_8192F(txdesc) GET_TX_DESC_RTSRATE(txdesc)
|
||||
#define SET_TX_DESC_RTS_DATA_RTY_LMT_8192F(txdesc, value) \
|
||||
SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)
|
||||
#define GET_TX_DESC_RTS_DATA_RTY_LMT_8192F(txdesc) \
|
||||
GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)
|
||||
#define SET_TX_DESC_RTY_LMT_EN_8192F(txdesc, value) \
|
||||
SET_TX_DESC_RTY_LMT_EN(txdesc, value)
|
||||
#define GET_TX_DESC_RTY_LMT_EN_8192F(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)
|
||||
#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8192F(txdesc, value) \
|
||||
SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)
|
||||
#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8192F(txdesc) \
|
||||
GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)
|
||||
#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8192F(txdesc, value) \
|
||||
SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)
|
||||
#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8192F(txdesc) \
|
||||
GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)
|
||||
#define SET_TX_DESC_TRY_RATE_8192F(txdesc, value) \
|
||||
SET_TX_DESC_TRY_RATE(txdesc, value)
|
||||
#define GET_TX_DESC_TRY_RATE_8192F(txdesc) GET_TX_DESC_TRY_RATE(txdesc)
|
||||
#define SET_TX_DESC_DATARATE_8192F(txdesc, value) \
|
||||
SET_TX_DESC_DATARATE(txdesc, value)
|
||||
#define GET_TX_DESC_DATARATE_8192F(txdesc) GET_TX_DESC_DATARATE(txdesc)
|
||||
|
||||
/*TXDESC_WORD5*/
|
||||
|
||||
#define SET_TX_DESC_POLLUTED_8192F(txdesc, value) \
|
||||
SET_TX_DESC_POLLUTED(txdesc, value)
|
||||
#define GET_TX_DESC_POLLUTED_8192F(txdesc) GET_TX_DESC_POLLUTED(txdesc)
|
||||
#define SET_TX_DESC_TXPWR_OFSET_TYPE_8192F(txdesc, value) \
|
||||
SET_TX_DESC_TXPWR_OFSET_TYPE_V1(txdesc, value)
|
||||
#define GET_TX_DESC_TXPWR_OFSET_TYPE_8192F(txdesc) \
|
||||
GET_TX_DESC_TXPWR_OFSET_TYPE_V1(txdesc)
|
||||
#define SET_TX_DESC_TX_ANT_8192F(txdesc, value) \
|
||||
SET_TX_DESC_TX_ANT(txdesc, value)
|
||||
#define GET_TX_DESC_TX_ANT_8192F(txdesc) GET_TX_DESC_TX_ANT(txdesc)
|
||||
#define SET_TX_DESC_DROP_ID_8192F(txdesc, value) \
|
||||
SET_TX_DESC_DROP_ID_V1(txdesc, value)
|
||||
#define GET_TX_DESC_DROP_ID_8192F(txdesc) GET_TX_DESC_DROP_ID_V1(txdesc)
|
||||
#define SET_TX_DESC_PORT_ID_8192F(txdesc, value) \
|
||||
SET_TX_DESC_PORT_ID_V1(txdesc, value)
|
||||
#define GET_TX_DESC_PORT_ID_8192F(txdesc) GET_TX_DESC_PORT_ID_V1(txdesc)
|
||||
#define SET_TX_DESC_RTS_SC_8192F(txdesc, value) \
|
||||
SET_TX_DESC_RTS_SC(txdesc, value)
|
||||
#define GET_TX_DESC_RTS_SC_8192F(txdesc) GET_TX_DESC_RTS_SC(txdesc)
|
||||
#define SET_TX_DESC_RTS_SHORT_8192F(txdesc, value) \
|
||||
SET_TX_DESC_RTS_SHORT(txdesc, value)
|
||||
#define GET_TX_DESC_RTS_SHORT_8192F(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)
|
||||
#define SET_TX_DESC_VCS_STBC_8192F(txdesc, value) \
|
||||
SET_TX_DESC_VCS_STBC(txdesc, value)
|
||||
#define GET_TX_DESC_VCS_STBC_8192F(txdesc) GET_TX_DESC_VCS_STBC(txdesc)
|
||||
#define SET_TX_DESC_DATA_STBC_8192F(txdesc, value) \
|
||||
SET_TX_DESC_DATA_STBC(txdesc, value)
|
||||
#define GET_TX_DESC_DATA_STBC_8192F(txdesc) GET_TX_DESC_DATA_STBC(txdesc)
|
||||
#define SET_TX_DESC_DATA_LDPC_8192F(txdesc, value) \
|
||||
SET_TX_DESC_DATA_LDPC(txdesc, value)
|
||||
#define GET_TX_DESC_DATA_LDPC_8192F(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)
|
||||
#define SET_TX_DESC_DATA_BW_8192F(txdesc, value) \
|
||||
SET_TX_DESC_DATA_BW(txdesc, value)
|
||||
#define GET_TX_DESC_DATA_BW_8192F(txdesc) GET_TX_DESC_DATA_BW(txdesc)
|
||||
#define SET_TX_DESC_DATA_SHORT_8192F(txdesc, value) \
|
||||
SET_TX_DESC_DATA_SHORT(txdesc, value)
|
||||
#define GET_TX_DESC_DATA_SHORT_8192F(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)
|
||||
#define SET_TX_DESC_DATA_SC_8192F(txdesc, value) \
|
||||
SET_TX_DESC_DATA_SC(txdesc, value)
|
||||
#define GET_TX_DESC_DATA_SC_8192F(txdesc) GET_TX_DESC_DATA_SC(txdesc)
|
||||
|
||||
/*TXDESC_WORD6*/
|
||||
|
||||
#define SET_TX_DESC_ANT_MAPC_8192F(txdesc, value) \
|
||||
SET_TX_DESC_ANT_MAPC_V2(txdesc, value)
|
||||
#define GET_TX_DESC_ANT_MAPC_8192F(txdesc) GET_TX_DESC_ANT_MAPC_V2(txdesc)
|
||||
#define SET_TX_DESC_ANT_MAPB_8192F(txdesc, value) \
|
||||
SET_TX_DESC_ANT_MAPB_V2(txdesc, value)
|
||||
#define GET_TX_DESC_ANT_MAPB_8192F(txdesc) GET_TX_DESC_ANT_MAPB_V2(txdesc)
|
||||
#define SET_TX_DESC_ANT_MAPA_8192F(txdesc, value) \
|
||||
SET_TX_DESC_ANT_MAPA_V2(txdesc, value)
|
||||
#define GET_TX_DESC_ANT_MAPA_8192F(txdesc) GET_TX_DESC_ANT_MAPA_V2(txdesc)
|
||||
#define SET_TX_DESC_ANTSEL_D_8192F(txdesc, value) \
|
||||
SET_TX_DESC_ANTSEL_D_V1(txdesc, value)
|
||||
#define GET_TX_DESC_ANTSEL_D_8192F(txdesc) GET_TX_DESC_ANTSEL_D_V1(txdesc)
|
||||
#define SET_TX_DESC_ANTSEL_C_8192F(txdesc, value) \
|
||||
SET_TX_DESC_ANTSEL_C_V2(txdesc, value)
|
||||
#define GET_TX_DESC_ANTSEL_C_8192F(txdesc) GET_TX_DESC_ANTSEL_C_V2(txdesc)
|
||||
#define SET_TX_DESC_ANTSEL_B_8192F(txdesc, value) \
|
||||
SET_TX_DESC_ANTSEL_B_V2(txdesc, value)
|
||||
#define GET_TX_DESC_ANTSEL_B_8192F(txdesc) GET_TX_DESC_ANTSEL_B_V2(txdesc)
|
||||
#define SET_TX_DESC_ANTSEL_A_8192F(txdesc, value) \
|
||||
SET_TX_DESC_ANTSEL_A_V2(txdesc, value)
|
||||
#define GET_TX_DESC_ANTSEL_A_8192F(txdesc) GET_TX_DESC_ANTSEL_A_V2(txdesc)
|
||||
#define SET_TX_DESC_MBSSID_8192F(txdesc, value) \
|
||||
SET_TX_DESC_MBSSID(txdesc, value)
|
||||
#define GET_TX_DESC_MBSSID_8192F(txdesc) GET_TX_DESC_MBSSID(txdesc)
|
||||
#define SET_TX_DESC_SWPS_SEQ_8192F(txdesc, value) \
|
||||
SET_TX_DESC_SWPS_SEQ(txdesc, value)
|
||||
#define GET_TX_DESC_SWPS_SEQ_8192F(txdesc) GET_TX_DESC_SWPS_SEQ(txdesc)
|
||||
|
||||
/*TXDESC_WORD7*/
|
||||
|
||||
#define SET_TX_DESC_DMA_TXAGG_NUM_8192F(txdesc, value) \
|
||||
SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)
|
||||
#define GET_TX_DESC_DMA_TXAGG_NUM_8192F(txdesc) \
|
||||
GET_TX_DESC_DMA_TXAGG_NUM(txdesc)
|
||||
#define SET_TX_DESC_ANT_MAPD_8192F(txdesc, value) \
|
||||
SET_TX_DESC_ANT_MAPD_V2(txdesc, value)
|
||||
#define GET_TX_DESC_ANT_MAPD_8192F(txdesc) GET_TX_DESC_ANT_MAPD_V2(txdesc)
|
||||
#define SET_TX_DESC_ANTSEL_EN_8192F(txdesc, value) \
|
||||
SET_TX_DESC_ANTSEL_EN_V2(txdesc, value)
|
||||
#define GET_TX_DESC_ANTSEL_EN_8192F(txdesc) GET_TX_DESC_ANTSEL_EN_V2(txdesc)
|
||||
#define SET_TX_DESC_MBSSID_EX_8192F(txdesc, value) \
|
||||
SET_TX_DESC_MBSSID_EX_V1(txdesc, value)
|
||||
#define GET_TX_DESC_MBSSID_EX_8192F(txdesc) GET_TX_DESC_MBSSID_EX_V1(txdesc)
|
||||
#define SET_TX_DESC_TX_BUFF_SIZE_8192F(txdesc, value) \
|
||||
SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)
|
||||
#define GET_TX_DESC_TX_BUFF_SIZE_8192F(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)
|
||||
#define SET_TX_DESC_TXDESC_CHECKSUM_8192F(txdesc, value) \
|
||||
SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)
|
||||
#define GET_TX_DESC_TXDESC_CHECKSUM_8192F(txdesc) \
|
||||
GET_TX_DESC_TXDESC_CHECKSUM(txdesc)
|
||||
#define SET_TX_DESC_TIMESTAMP_8192F(txdesc, value) \
|
||||
SET_TX_DESC_TIMESTAMP(txdesc, value)
|
||||
#define GET_TX_DESC_TIMESTAMP_8192F(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)
|
||||
|
||||
/*TXDESC_WORD8*/
|
||||
|
||||
#define SET_TX_DESC_TAILPAGE_L_8192F(txdesc, value) \
|
||||
SET_TX_DESC_TAILPAGE_L(txdesc, value)
|
||||
#define GET_TX_DESC_TAILPAGE_L_8192F(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)
|
||||
#define SET_TX_DESC_SDIO_DMASEQ_8192F(txdesc, value) \
|
||||
SET_TX_DESC_SDIO_DMASEQ(txdesc, value)
|
||||
#define GET_TX_DESC_SDIO_DMASEQ_8192F(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)
|
||||
#define SET_TX_DESC_NEXTHEADPAGE_L_8192F(txdesc, value) \
|
||||
SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)
|
||||
#define GET_TX_DESC_NEXTHEADPAGE_L_8192F(txdesc) \
|
||||
GET_TX_DESC_NEXTHEADPAGE_L(txdesc)
|
||||
#define SET_TX_DESC_EN_HWSEQ_8192F(txdesc, value) \
|
||||
SET_TX_DESC_EN_HWSEQ(txdesc, value)
|
||||
#define GET_TX_DESC_EN_HWSEQ_8192F(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)
|
||||
#define SET_TX_DESC_DATA_RC_8192F(txdesc, value) \
|
||||
SET_TX_DESC_DATA_RC(txdesc, value)
|
||||
#define GET_TX_DESC_DATA_RC_8192F(txdesc) GET_TX_DESC_DATA_RC(txdesc)
|
||||
#define SET_TX_DESC_BAR_RTY_TH_8192F(txdesc, value) \
|
||||
SET_TX_DESC_BAR_RTY_TH(txdesc, value)
|
||||
#define GET_TX_DESC_BAR_RTY_TH_8192F(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)
|
||||
#define SET_TX_DESC_RTS_RC_8192F(txdesc, value) \
|
||||
SET_TX_DESC_RTS_RC(txdesc, value)
|
||||
#define GET_TX_DESC_RTS_RC_8192F(txdesc) GET_TX_DESC_RTS_RC(txdesc)
|
||||
|
||||
/*TXDESC_WORD9*/
|
||||
|
||||
#define SET_TX_DESC_FINAL_DATA_RATE_8192F(txdesc, value) \
|
||||
SET_TX_DESC_FINAL_DATA_RATE_V1(txdesc, value)
|
||||
#define GET_TX_DESC_FINAL_DATA_RATE_8192F(txdesc) \
|
||||
GET_TX_DESC_FINAL_DATA_RATE_V1(txdesc)
|
||||
#define SET_TX_DESC_SW_SEQ_8192F(txdesc, value) \
|
||||
SET_TX_DESC_SW_SEQ(txdesc, value)
|
||||
#define GET_TX_DESC_SW_SEQ_8192F(txdesc) GET_TX_DESC_SW_SEQ(txdesc)
|
||||
#define SET_TX_DESC_PADDING_LEN_8192F(txdesc, value) \
|
||||
SET_TX_DESC_PADDING_LEN(txdesc, value)
|
||||
#define GET_TX_DESC_PADDING_LEN_8192F(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)
|
||||
#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8192F(txdesc, value) \
|
||||
SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)
|
||||
#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8192F(txdesc) \
|
||||
GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)
|
||||
|
||||
/*WORD10*/
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXDESC_WORD0*/
|
||||
|
||||
#define SET_TX_DESC_DISQSELSEQ_8812F(txdesc, value) \
|
||||
SET_TX_DESC_DISQSELSEQ(txdesc, value)
|
||||
#define GET_TX_DESC_DISQSELSEQ_8812F(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)
|
||||
#define SET_TX_DESC_GF_8812F(txdesc, value) SET_TX_DESC_GF(txdesc, value)
|
||||
#define GET_TX_DESC_GF_8812F(txdesc) GET_TX_DESC_GF(txdesc)
|
||||
#define SET_TX_DESC_NO_ACM_8812F(txdesc, value) \
|
||||
SET_TX_DESC_NO_ACM(txdesc, value)
|
||||
#define GET_TX_DESC_NO_ACM_8812F(txdesc) GET_TX_DESC_NO_ACM(txdesc)
|
||||
#define SET_TX_DESC_BCNPKT_TSF_CTRL_8812F(txdesc, value) \
|
||||
SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)
|
||||
#define GET_TX_DESC_BCNPKT_TSF_CTRL_8812F(txdesc) \
|
||||
GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)
|
||||
#define SET_TX_DESC_AMSDU_PAD_EN_8812F(txdesc, value) \
|
||||
SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)
|
||||
#define GET_TX_DESC_AMSDU_PAD_EN_8812F(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)
|
||||
#define SET_TX_DESC_LS_8812F(txdesc, value) SET_TX_DESC_LS(txdesc, value)
|
||||
#define GET_TX_DESC_LS_8812F(txdesc) GET_TX_DESC_LS(txdesc)
|
||||
#define SET_TX_DESC_HTC_8812F(txdesc, value) SET_TX_DESC_HTC(txdesc, value)
|
||||
#define GET_TX_DESC_HTC_8812F(txdesc) GET_TX_DESC_HTC(txdesc)
|
||||
#define SET_TX_DESC_BMC_8812F(txdesc, value) SET_TX_DESC_BMC(txdesc, value)
|
||||
#define GET_TX_DESC_BMC_8812F(txdesc) GET_TX_DESC_BMC(txdesc)
|
||||
#define SET_TX_DESC_OFFSET_8812F(txdesc, value) \
|
||||
SET_TX_DESC_OFFSET(txdesc, value)
|
||||
#define GET_TX_DESC_OFFSET_8812F(txdesc) GET_TX_DESC_OFFSET(txdesc)
|
||||
#define SET_TX_DESC_TXPKTSIZE_8812F(txdesc, value) \
|
||||
SET_TX_DESC_TXPKTSIZE(txdesc, value)
|
||||
#define GET_TX_DESC_TXPKTSIZE_8812F(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
|
||||
|
||||
/*WORD1*/
|
||||
|
||||
#define SET_TX_DESC_MOREDATA_8812F(txdesc, value) \
|
||||
SET_TX_DESC_MOREDATA(txdesc, value)
|
||||
#define GET_TX_DESC_MOREDATA_8812F(txdesc) GET_TX_DESC_MOREDATA(txdesc)
|
||||
#define SET_TX_DESC_PKT_OFFSET_8812F(txdesc, value) \
|
||||
SET_TX_DESC_PKT_OFFSET(txdesc, value)
|
||||
#define GET_TX_DESC_PKT_OFFSET_8812F(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)
|
||||
#define SET_TX_DESC_SEC_TYPE_8812F(txdesc, value) \
|
||||
SET_TX_DESC_SEC_TYPE(txdesc, value)
|
||||
#define GET_TX_DESC_SEC_TYPE_8812F(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)
|
||||
#define SET_TX_DESC_EN_DESC_ID_8812F(txdesc, value) \
|
||||
SET_TX_DESC_EN_DESC_ID(txdesc, value)
|
||||
#define GET_TX_DESC_EN_DESC_ID_8812F(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)
|
||||
#define SET_TX_DESC_RATE_ID_8812F(txdesc, value) \
|
||||
SET_TX_DESC_RATE_ID(txdesc, value)
|
||||
#define GET_TX_DESC_RATE_ID_8812F(txdesc) GET_TX_DESC_RATE_ID(txdesc)
|
||||
#define SET_TX_DESC_PIFS_8812F(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)
|
||||
#define GET_TX_DESC_PIFS_8812F(txdesc) GET_TX_DESC_PIFS(txdesc)
|
||||
#define SET_TX_DESC_LSIG_TXOP_EN_8812F(txdesc, value) \
|
||||
SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)
|
||||
#define GET_TX_DESC_LSIG_TXOP_EN_8812F(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)
|
||||
#define SET_TX_DESC_RD_NAV_EXT_8812F(txdesc, value) \
|
||||
SET_TX_DESC_RD_NAV_EXT(txdesc, value)
|
||||
#define GET_TX_DESC_RD_NAV_EXT_8812F(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)
|
||||
#define SET_TX_DESC_QSEL_8812F(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
|
||||
#define GET_TX_DESC_QSEL_8812F(txdesc) GET_TX_DESC_QSEL(txdesc)
|
||||
#define SET_TX_DESC_MACID_8812F(txdesc, value) SET_TX_DESC_MACID(txdesc, value)
|
||||
#define GET_TX_DESC_MACID_8812F(txdesc) GET_TX_DESC_MACID(txdesc)
|
||||
|
||||
/*TXDESC_WORD2*/
|
||||
|
||||
#define SET_TX_DESC_HW_AES_IV_8812F(txdesc, value) \
|
||||
SET_TX_DESC_HW_AES_IV(txdesc, value)
|
||||
#define GET_TX_DESC_HW_AES_IV_8812F(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)
|
||||
#define SET_TX_DESC_FTM_EN_8812F(txdesc, value) \
|
||||
SET_TX_DESC_FTM_EN(txdesc, value)
|
||||
#define GET_TX_DESC_FTM_EN_8812F(txdesc) GET_TX_DESC_FTM_EN(txdesc)
|
||||
#define SET_TX_DESC_G_ID_8812F(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)
|
||||
#define GET_TX_DESC_G_ID_8812F(txdesc) GET_TX_DESC_G_ID(txdesc)
|
||||
#define SET_TX_DESC_BT_NULL_8812F(txdesc, value) \
|
||||
SET_TX_DESC_BT_NULL(txdesc, value)
|
||||
#define GET_TX_DESC_BT_NULL_8812F(txdesc) GET_TX_DESC_BT_NULL(txdesc)
|
||||
#define SET_TX_DESC_AMPDU_DENSITY_8812F(txdesc, value) \
|
||||
SET_TX_DESC_AMPDU_DENSITY(txdesc, value)
|
||||
#define GET_TX_DESC_AMPDU_DENSITY_8812F(txdesc) \
|
||||
GET_TX_DESC_AMPDU_DENSITY(txdesc)
|
||||
#define SET_TX_DESC_SPE_RPT_8812F(txdesc, value) \
|
||||
SET_TX_DESC_SPE_RPT(txdesc, value)
|
||||
#define GET_TX_DESC_SPE_RPT_8812F(txdesc) GET_TX_DESC_SPE_RPT(txdesc)
|
||||
#define SET_TX_DESC_RAW_8812F(txdesc, value) SET_TX_DESC_RAW(txdesc, value)
|
||||
#define GET_TX_DESC_RAW_8812F(txdesc) GET_TX_DESC_RAW(txdesc)
|
||||
#define SET_TX_DESC_MOREFRAG_8812F(txdesc, value) \
|
||||
SET_TX_DESC_MOREFRAG(txdesc, value)
|
||||
#define GET_TX_DESC_MOREFRAG_8812F(txdesc) GET_TX_DESC_MOREFRAG(txdesc)
|
||||
#define SET_TX_DESC_BK_8812F(txdesc, value) SET_TX_DESC_BK(txdesc, value)
|
||||
#define GET_TX_DESC_BK_8812F(txdesc) GET_TX_DESC_BK(txdesc)
|
||||
#define SET_TX_DESC_NULL_1_8812F(txdesc, value) \
|
||||
SET_TX_DESC_NULL_1(txdesc, value)
|
||||
#define GET_TX_DESC_NULL_1_8812F(txdesc) GET_TX_DESC_NULL_1(txdesc)
|
||||
#define SET_TX_DESC_NULL_0_8812F(txdesc, value) \
|
||||
SET_TX_DESC_NULL_0(txdesc, value)
|
||||
#define GET_TX_DESC_NULL_0_8812F(txdesc) GET_TX_DESC_NULL_0(txdesc)
|
||||
#define SET_TX_DESC_RDG_EN_8812F(txdesc, value) \
|
||||
SET_TX_DESC_RDG_EN(txdesc, value)
|
||||
#define GET_TX_DESC_RDG_EN_8812F(txdesc) GET_TX_DESC_RDG_EN(txdesc)
|
||||
#define SET_TX_DESC_AGG_EN_8812F(txdesc, value) \
|
||||
SET_TX_DESC_AGG_EN(txdesc, value)
|
||||
#define GET_TX_DESC_AGG_EN_8812F(txdesc) GET_TX_DESC_AGG_EN(txdesc)
|
||||
#define SET_TX_DESC_CCA_RTS_8812F(txdesc, value) \
|
||||
SET_TX_DESC_CCA_RTS(txdesc, value)
|
||||
#define GET_TX_DESC_CCA_RTS_8812F(txdesc) GET_TX_DESC_CCA_RTS(txdesc)
|
||||
#define SET_TX_DESC_TRI_FRAME_8812F(txdesc, value) \
|
||||
SET_TX_DESC_TRI_FRAME(txdesc, value)
|
||||
#define GET_TX_DESC_TRI_FRAME_8812F(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)
|
||||
#define SET_TX_DESC_P_AID_8812F(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)
|
||||
#define GET_TX_DESC_P_AID_8812F(txdesc) GET_TX_DESC_P_AID(txdesc)
|
||||
|
||||
/*TXDESC_WORD3*/
|
||||
|
||||
#define SET_TX_DESC_AMPDU_MAX_TIME_8812F(txdesc, value) \
|
||||
SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)
|
||||
#define GET_TX_DESC_AMPDU_MAX_TIME_8812F(txdesc) \
|
||||
GET_TX_DESC_AMPDU_MAX_TIME(txdesc)
|
||||
#define SET_TX_DESC_NDPA_8812F(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)
|
||||
#define GET_TX_DESC_NDPA_8812F(txdesc) GET_TX_DESC_NDPA(txdesc)
|
||||
#define SET_TX_DESC_MAX_AGG_NUM_8812F(txdesc, value) \
|
||||
SET_TX_DESC_MAX_AGG_NUM(txdesc, value)
|
||||
#define GET_TX_DESC_MAX_AGG_NUM_8812F(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)
|
||||
#define SET_TX_DESC_USE_MAX_TIME_EN_8812F(txdesc, value) \
|
||||
SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)
|
||||
#define GET_TX_DESC_USE_MAX_TIME_EN_8812F(txdesc) \
|
||||
GET_TX_DESC_USE_MAX_TIME_EN(txdesc)
|
||||
#define SET_TX_DESC_NAVUSEHDR_8812F(txdesc, value) \
|
||||
SET_TX_DESC_NAVUSEHDR(txdesc, value)
|
||||
#define GET_TX_DESC_NAVUSEHDR_8812F(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)
|
||||
#define SET_TX_DESC_CHK_EN_8812F(txdesc, value) \
|
||||
SET_TX_DESC_CHK_EN(txdesc, value)
|
||||
#define GET_TX_DESC_CHK_EN_8812F(txdesc) GET_TX_DESC_CHK_EN(txdesc)
|
||||
#define SET_TX_DESC_HW_RTS_EN_8812F(txdesc, value) \
|
||||
SET_TX_DESC_HW_RTS_EN(txdesc, value)
|
||||
#define GET_TX_DESC_HW_RTS_EN_8812F(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)
|
||||
#define SET_TX_DESC_RTSEN_8812F(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)
|
||||
#define GET_TX_DESC_RTSEN_8812F(txdesc) GET_TX_DESC_RTSEN(txdesc)
|
||||
#define SET_TX_DESC_CTS2SELF_8812F(txdesc, value) \
|
||||
SET_TX_DESC_CTS2SELF(txdesc, value)
|
||||
#define GET_TX_DESC_CTS2SELF_8812F(txdesc) GET_TX_DESC_CTS2SELF(txdesc)
|
||||
#define SET_TX_DESC_DISDATAFB_8812F(txdesc, value) \
|
||||
SET_TX_DESC_DISDATAFB(txdesc, value)
|
||||
#define GET_TX_DESC_DISDATAFB_8812F(txdesc) GET_TX_DESC_DISDATAFB(txdesc)
|
||||
#define SET_TX_DESC_DISRTSFB_8812F(txdesc, value) \
|
||||
SET_TX_DESC_DISRTSFB(txdesc, value)
|
||||
#define GET_TX_DESC_DISRTSFB_8812F(txdesc) GET_TX_DESC_DISRTSFB(txdesc)
|
||||
#define SET_TX_DESC_USE_RATE_8812F(txdesc, value) \
|
||||
SET_TX_DESC_USE_RATE(txdesc, value)
|
||||
#define GET_TX_DESC_USE_RATE_8812F(txdesc) GET_TX_DESC_USE_RATE(txdesc)
|
||||
#define SET_TX_DESC_HW_SSN_SEL_8812F(txdesc, value) \
|
||||
SET_TX_DESC_HW_SSN_SEL(txdesc, value)
|
||||
#define GET_TX_DESC_HW_SSN_SEL_8812F(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)
|
||||
#define SET_TX_DESC_WHEADER_LEN_8812F(txdesc, value) \
|
||||
SET_TX_DESC_WHEADER_LEN(txdesc, value)
|
||||
#define GET_TX_DESC_WHEADER_LEN_8812F(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)
|
||||
|
||||
/*TXDESC_WORD4*/
|
||||
|
||||
#define SET_TX_DESC_PCTS_MASK_IDX_8812F(txdesc, value) \
|
||||
SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)
|
||||
#define GET_TX_DESC_PCTS_MASK_IDX_8812F(txdesc) \
|
||||
GET_TX_DESC_PCTS_MASK_IDX(txdesc)
|
||||
#define SET_TX_DESC_PCTS_EN_8812F(txdesc, value) \
|
||||
SET_TX_DESC_PCTS_EN(txdesc, value)
|
||||
#define GET_TX_DESC_PCTS_EN_8812F(txdesc) GET_TX_DESC_PCTS_EN(txdesc)
|
||||
#define SET_TX_DESC_RTSRATE_8812F(txdesc, value) \
|
||||
SET_TX_DESC_RTSRATE(txdesc, value)
|
||||
#define GET_TX_DESC_RTSRATE_8812F(txdesc) GET_TX_DESC_RTSRATE(txdesc)
|
||||
#define SET_TX_DESC_RTS_DATA_RTY_LMT_8812F(txdesc, value) \
|
||||
SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)
|
||||
#define GET_TX_DESC_RTS_DATA_RTY_LMT_8812F(txdesc) \
|
||||
GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)
|
||||
#define SET_TX_DESC_RTY_LMT_EN_8812F(txdesc, value) \
|
||||
SET_TX_DESC_RTY_LMT_EN(txdesc, value)
|
||||
#define GET_TX_DESC_RTY_LMT_EN_8812F(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)
|
||||
#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8812F(txdesc, value) \
|
||||
SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)
|
||||
#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8812F(txdesc) \
|
||||
GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)
|
||||
#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8812F(txdesc, value) \
|
||||
SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)
|
||||
#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8812F(txdesc) \
|
||||
GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)
|
||||
#define SET_TX_DESC_TRY_RATE_8812F(txdesc, value) \
|
||||
SET_TX_DESC_TRY_RATE(txdesc, value)
|
||||
#define GET_TX_DESC_TRY_RATE_8812F(txdesc) GET_TX_DESC_TRY_RATE(txdesc)
|
||||
#define SET_TX_DESC_DATARATE_8812F(txdesc, value) \
|
||||
SET_TX_DESC_DATARATE(txdesc, value)
|
||||
#define GET_TX_DESC_DATARATE_8812F(txdesc) GET_TX_DESC_DATARATE(txdesc)
|
||||
|
||||
/*TXDESC_WORD5*/
|
||||
|
||||
#define SET_TX_DESC_POLLUTED_8812F(txdesc, value) \
|
||||
SET_TX_DESC_POLLUTED(txdesc, value)
|
||||
#define GET_TX_DESC_POLLUTED_8812F(txdesc) GET_TX_DESC_POLLUTED(txdesc)
|
||||
#define SET_TX_DESC_ANTSEL_EN_8812F(txdesc, value) \
|
||||
SET_TX_DESC_ANTSEL_EN_V1(txdesc, value)
|
||||
#define GET_TX_DESC_ANTSEL_EN_8812F(txdesc) GET_TX_DESC_ANTSEL_EN_V1(txdesc)
|
||||
#define SET_TX_DESC_TXPWR_OFSET_TYPE_8812F(txdesc, value) \
|
||||
SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value)
|
||||
#define GET_TX_DESC_TXPWR_OFSET_TYPE_8812F(txdesc) \
|
||||
GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc)
|
||||
#define SET_TX_DESC_TX_ANT_8812F(txdesc, value) \
|
||||
SET_TX_DESC_TX_ANT(txdesc, value)
|
||||
#define GET_TX_DESC_TX_ANT_8812F(txdesc) GET_TX_DESC_TX_ANT(txdesc)
|
||||
#define SET_TX_DESC_PORT_ID_8812F(txdesc, value) \
|
||||
SET_TX_DESC_PORT_ID(txdesc, value)
|
||||
#define GET_TX_DESC_PORT_ID_8812F(txdesc) GET_TX_DESC_PORT_ID(txdesc)
|
||||
#define SET_TX_DESC_MULTIPLE_PORT_8812F(txdesc, value) \
|
||||
SET_TX_DESC_MULTIPLE_PORT(txdesc, value)
|
||||
#define GET_TX_DESC_MULTIPLE_PORT_8812F(txdesc) \
|
||||
GET_TX_DESC_MULTIPLE_PORT(txdesc)
|
||||
#define SET_TX_DESC_SIGNALING_TAPKT_EN_8812F(txdesc, value) \
|
||||
SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)
|
||||
#define GET_TX_DESC_SIGNALING_TAPKT_EN_8812F(txdesc) \
|
||||
GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)
|
||||
#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8812F(txdesc, value) \
|
||||
SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value)
|
||||
#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8812F(txdesc) \
|
||||
GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc)
|
||||
#define SET_TX_DESC_RTS_SHORT_8812F(txdesc, value) \
|
||||
SET_TX_DESC_RTS_SHORT(txdesc, value)
|
||||
#define GET_TX_DESC_RTS_SHORT_8812F(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)
|
||||
#define SET_TX_DESC_VCS_STBC_8812F(txdesc, value) \
|
||||
SET_TX_DESC_VCS_STBC(txdesc, value)
|
||||
#define GET_TX_DESC_VCS_STBC_8812F(txdesc) GET_TX_DESC_VCS_STBC(txdesc)
|
||||
#define SET_TX_DESC_DATA_STBC_8812F(txdesc, value) \
|
||||
SET_TX_DESC_DATA_STBC(txdesc, value)
|
||||
#define GET_TX_DESC_DATA_STBC_8812F(txdesc) GET_TX_DESC_DATA_STBC(txdesc)
|
||||
#define SET_TX_DESC_DATA_LDPC_8812F(txdesc, value) \
|
||||
SET_TX_DESC_DATA_LDPC(txdesc, value)
|
||||
#define GET_TX_DESC_DATA_LDPC_8812F(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)
|
||||
#define SET_TX_DESC_DATA_BW_8812F(txdesc, value) \
|
||||
SET_TX_DESC_DATA_BW(txdesc, value)
|
||||
#define GET_TX_DESC_DATA_BW_8812F(txdesc) GET_TX_DESC_DATA_BW(txdesc)
|
||||
#define SET_TX_DESC_DATA_SHORT_8812F(txdesc, value) \
|
||||
SET_TX_DESC_DATA_SHORT(txdesc, value)
|
||||
#define GET_TX_DESC_DATA_SHORT_8812F(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)
|
||||
#define SET_TX_DESC_DATA_SC_8812F(txdesc, value) \
|
||||
SET_TX_DESC_DATA_SC(txdesc, value)
|
||||
#define GET_TX_DESC_DATA_SC_8812F(txdesc) GET_TX_DESC_DATA_SC(txdesc)
|
||||
|
||||
/*TXDESC_WORD6*/
|
||||
|
||||
#define SET_TX_DESC_ANTSEL_D_8812F(txdesc, value) \
|
||||
SET_TX_DESC_ANTSEL_D(txdesc, value)
|
||||
#define GET_TX_DESC_ANTSEL_D_8812F(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)
|
||||
#define SET_TX_DESC_ANT_MAPD_8812F(txdesc, value) \
|
||||
SET_TX_DESC_ANT_MAPD(txdesc, value)
|
||||
#define GET_TX_DESC_ANT_MAPD_8812F(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)
|
||||
#define SET_TX_DESC_ANT_MAPC_8812F(txdesc, value) \
|
||||
SET_TX_DESC_ANT_MAPC(txdesc, value)
|
||||
#define GET_TX_DESC_ANT_MAPC_8812F(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)
|
||||
#define SET_TX_DESC_ANT_MAPB_8812F(txdesc, value) \
|
||||
SET_TX_DESC_ANT_MAPB(txdesc, value)
|
||||
#define GET_TX_DESC_ANT_MAPB_8812F(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)
|
||||
#define SET_TX_DESC_ANT_MAPA_8812F(txdesc, value) \
|
||||
SET_TX_DESC_ANT_MAPA(txdesc, value)
|
||||
#define GET_TX_DESC_ANT_MAPA_8812F(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)
|
||||
#define SET_TX_DESC_ANTSEL_C_8812F(txdesc, value) \
|
||||
SET_TX_DESC_ANTSEL_C(txdesc, value)
|
||||
#define GET_TX_DESC_ANTSEL_C_8812F(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)
|
||||
#define SET_TX_DESC_ANTSEL_B_8812F(txdesc, value) \
|
||||
SET_TX_DESC_ANTSEL_B(txdesc, value)
|
||||
#define GET_TX_DESC_ANTSEL_B_8812F(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)
|
||||
#define SET_TX_DESC_ANTSEL_A_8812F(txdesc, value) \
|
||||
SET_TX_DESC_ANTSEL_A(txdesc, value)
|
||||
#define GET_TX_DESC_ANTSEL_A_8812F(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)
|
||||
#define SET_TX_DESC_MBSSID_8812F(txdesc, value) \
|
||||
SET_TX_DESC_MBSSID(txdesc, value)
|
||||
#define GET_TX_DESC_MBSSID_8812F(txdesc) GET_TX_DESC_MBSSID(txdesc)
|
||||
#define SET_TX_DESC_SW_DEFINE_8812F(txdesc, value) \
|
||||
SET_TX_DESC_SW_DEFINE(txdesc, value)
|
||||
#define GET_TX_DESC_SW_DEFINE_8812F(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)
|
||||
|
||||
/*TXDESC_WORD7*/
|
||||
|
||||
#define SET_TX_DESC_DMA_TXAGG_NUM_8812F(txdesc, value) \
|
||||
SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)
|
||||
#define GET_TX_DESC_DMA_TXAGG_NUM_8812F(txdesc) \
|
||||
GET_TX_DESC_DMA_TXAGG_NUM(txdesc)
|
||||
#define SET_TX_DESC_FINAL_DATA_RATE_8812F(txdesc, value) \
|
||||
SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)
|
||||
#define GET_TX_DESC_FINAL_DATA_RATE_8812F(txdesc) \
|
||||
GET_TX_DESC_FINAL_DATA_RATE(txdesc)
|
||||
#define SET_TX_DESC_NTX_MAP_8812F(txdesc, value) \
|
||||
SET_TX_DESC_NTX_MAP(txdesc, value)
|
||||
#define GET_TX_DESC_NTX_MAP_8812F(txdesc) GET_TX_DESC_NTX_MAP(txdesc)
|
||||
#define SET_TX_DESC_TX_BUFF_SIZE_8812F(txdesc, value) \
|
||||
SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)
|
||||
#define GET_TX_DESC_TX_BUFF_SIZE_8812F(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)
|
||||
#define SET_TX_DESC_TXDESC_CHECKSUM_8812F(txdesc, value) \
|
||||
SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)
|
||||
#define GET_TX_DESC_TXDESC_CHECKSUM_8812F(txdesc) \
|
||||
GET_TX_DESC_TXDESC_CHECKSUM(txdesc)
|
||||
#define SET_TX_DESC_TIMESTAMP_8812F(txdesc, value) \
|
||||
SET_TX_DESC_TIMESTAMP(txdesc, value)
|
||||
#define GET_TX_DESC_TIMESTAMP_8812F(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)
|
||||
|
||||
/*TXDESC_WORD8*/
|
||||
|
||||
#define SET_TX_DESC_TXWIFI_CP_8812F(txdesc, value) \
|
||||
SET_TX_DESC_TXWIFI_CP(txdesc, value)
|
||||
#define GET_TX_DESC_TXWIFI_CP_8812F(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)
|
||||
#define SET_TX_DESC_MAC_CP_8812F(txdesc, value) \
|
||||
SET_TX_DESC_MAC_CP(txdesc, value)
|
||||
#define GET_TX_DESC_MAC_CP_8812F(txdesc) GET_TX_DESC_MAC_CP(txdesc)
|
||||
#define SET_TX_DESC_STW_PKTRE_DIS_8812F(txdesc, value) \
|
||||
SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)
|
||||
#define GET_TX_DESC_STW_PKTRE_DIS_8812F(txdesc) \
|
||||
GET_TX_DESC_STW_PKTRE_DIS(txdesc)
|
||||
#define SET_TX_DESC_STW_RB_DIS_8812F(txdesc, value) \
|
||||
SET_TX_DESC_STW_RB_DIS(txdesc, value)
|
||||
#define GET_TX_DESC_STW_RB_DIS_8812F(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)
|
||||
#define SET_TX_DESC_STW_RATE_DIS_8812F(txdesc, value) \
|
||||
SET_TX_DESC_STW_RATE_DIS(txdesc, value)
|
||||
#define GET_TX_DESC_STW_RATE_DIS_8812F(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)
|
||||
#define SET_TX_DESC_STW_ANT_DIS_8812F(txdesc, value) \
|
||||
SET_TX_DESC_STW_ANT_DIS(txdesc, value)
|
||||
#define GET_TX_DESC_STW_ANT_DIS_8812F(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)
|
||||
#define SET_TX_DESC_STW_EN_8812F(txdesc, value) \
|
||||
SET_TX_DESC_STW_EN(txdesc, value)
|
||||
#define GET_TX_DESC_STW_EN_8812F(txdesc) GET_TX_DESC_STW_EN(txdesc)
|
||||
#define SET_TX_DESC_SMH_EN_8812F(txdesc, value) \
|
||||
SET_TX_DESC_SMH_EN(txdesc, value)
|
||||
#define GET_TX_DESC_SMH_EN_8812F(txdesc) GET_TX_DESC_SMH_EN(txdesc)
|
||||
#define SET_TX_DESC_TAILPAGE_L_8812F(txdesc, value) \
|
||||
SET_TX_DESC_TAILPAGE_L(txdesc, value)
|
||||
#define GET_TX_DESC_TAILPAGE_L_8812F(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)
|
||||
#define SET_TX_DESC_SDIO_DMASEQ_8812F(txdesc, value) \
|
||||
SET_TX_DESC_SDIO_DMASEQ(txdesc, value)
|
||||
#define GET_TX_DESC_SDIO_DMASEQ_8812F(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)
|
||||
#define SET_TX_DESC_NEXTHEADPAGE_L_8812F(txdesc, value) \
|
||||
SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)
|
||||
#define GET_TX_DESC_NEXTHEADPAGE_L_8812F(txdesc) \
|
||||
GET_TX_DESC_NEXTHEADPAGE_L(txdesc)
|
||||
#define SET_TX_DESC_EN_HWSEQ_MODE_8812F(txdesc, value) \
|
||||
SET_TX_DESC_EN_HWSEQ_MODE(txdesc, value)
|
||||
#define GET_TX_DESC_EN_HWSEQ_MODE_8812F(txdesc) \
|
||||
GET_TX_DESC_EN_HWSEQ_MODE(txdesc)
|
||||
#define SET_TX_DESC_DATA_RC_8812F(txdesc, value) \
|
||||
SET_TX_DESC_DATA_RC(txdesc, value)
|
||||
#define GET_TX_DESC_DATA_RC_8812F(txdesc) GET_TX_DESC_DATA_RC(txdesc)
|
||||
#define SET_TX_DESC_BAR_RTY_TH_8812F(txdesc, value) \
|
||||
SET_TX_DESC_BAR_RTY_TH(txdesc, value)
|
||||
#define GET_TX_DESC_BAR_RTY_TH_8812F(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)
|
||||
#define SET_TX_DESC_RTS_RC_8812F(txdesc, value) \
|
||||
SET_TX_DESC_RTS_RC(txdesc, value)
|
||||
#define GET_TX_DESC_RTS_RC_8812F(txdesc) GET_TX_DESC_RTS_RC(txdesc)
|
||||
|
||||
/*TXDESC_WORD9*/
|
||||
|
||||
#define SET_TX_DESC_TAILPAGE_H_8812F(txdesc, value) \
|
||||
SET_TX_DESC_TAILPAGE_H(txdesc, value)
|
||||
#define GET_TX_DESC_TAILPAGE_H_8812F(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)
|
||||
#define SET_TX_DESC_NEXTHEADPAGE_H_8812F(txdesc, value) \
|
||||
SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)
|
||||
#define GET_TX_DESC_NEXTHEADPAGE_H_8812F(txdesc) \
|
||||
GET_TX_DESC_NEXTHEADPAGE_H(txdesc)
|
||||
#define SET_TX_DESC_SW_SEQ_8812F(txdesc, value) \
|
||||
SET_TX_DESC_SW_SEQ(txdesc, value)
|
||||
#define GET_TX_DESC_SW_SEQ_8812F(txdesc) GET_TX_DESC_SW_SEQ(txdesc)
|
||||
#define SET_TX_DESC_TXBF_PATH_8812F(txdesc, value) \
|
||||
SET_TX_DESC_TXBF_PATH(txdesc, value)
|
||||
#define GET_TX_DESC_TXBF_PATH_8812F(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)
|
||||
#define SET_TX_DESC_PADDING_LEN_8812F(txdesc, value) \
|
||||
SET_TX_DESC_PADDING_LEN(txdesc, value)
|
||||
#define GET_TX_DESC_PADDING_LEN_8812F(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)
|
||||
#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8812F(txdesc, value) \
|
||||
SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)
|
||||
#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8812F(txdesc) \
|
||||
GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)
|
||||
|
||||
/*WORD10*/
|
||||
|
||||
#define SET_TX_DESC_HT_DATA_SND_8812F(txdesc, value) \
|
||||
SET_TX_DESC_HT_DATA_SND(txdesc, value)
|
||||
#define GET_TX_DESC_HT_DATA_SND_8812F(txdesc) GET_TX_DESC_HT_DATA_SND(txdesc)
|
||||
#define SET_TX_DESC_SHCUT_CAM_8812F(txdesc, value) \
|
||||
SET_TX_DESC_SHCUT_CAM(txdesc, value)
|
||||
#define GET_TX_DESC_SHCUT_CAM_8812F(txdesc) GET_TX_DESC_SHCUT_CAM(txdesc)
|
||||
#define SET_TX_DESC_MU_DATARATE_8812F(txdesc, value) \
|
||||
SET_TX_DESC_MU_DATARATE(txdesc, value)
|
||||
#define GET_TX_DESC_MU_DATARATE_8812F(txdesc) GET_TX_DESC_MU_DATARATE(txdesc)
|
||||
#define SET_TX_DESC_MU_RC_8812F(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value)
|
||||
#define GET_TX_DESC_MU_RC_8812F(txdesc) GET_TX_DESC_MU_RC(txdesc)
|
||||
#define SET_TX_DESC_NDPA_RATE_SEL_8812F(txdesc, value) \
|
||||
SET_TX_DESC_NDPA_RATE_SEL(txdesc, value)
|
||||
#define GET_TX_DESC_NDPA_RATE_SEL_8812F(txdesc) \
|
||||
GET_TX_DESC_NDPA_RATE_SEL(txdesc)
|
||||
#define SET_TX_DESC_HW_NDPA_EN_8812F(txdesc, value) \
|
||||
SET_TX_DESC_HW_NDPA_EN(txdesc, value)
|
||||
#define GET_TX_DESC_HW_NDPA_EN_8812F(txdesc) GET_TX_DESC_HW_NDPA_EN(txdesc)
|
||||
#define SET_TX_DESC_SND_PKT_SEL_8812F(txdesc, value) \
|
||||
SET_TX_DESC_SND_PKT_SEL(txdesc, value)
|
||||
#define GET_TX_DESC_SND_PKT_SEL_8812F(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc)
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -16,7 +16,8 @@
|
||||
#ifndef _HALMAC_TX_DESC_NIC_H_
|
||||
#define _HALMAC_TX_DESC_NIC_H_
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXDESC_WORD0*/
|
||||
|
||||
@@ -35,7 +36,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_GF(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value)
|
||||
@@ -52,7 +54,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_NO_ACM(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value)
|
||||
@@ -69,7 +72,7 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 28, 1, value)
|
||||
@@ -79,14 +82,29 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 27, 1, value)
|
||||
#define GET_TX_DESC_AMSDU_PAD_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 27, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_LS(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 26, 1, value)
|
||||
#define GET_TX_DESC_LS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 26, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_HTC(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 25, 1, value)
|
||||
#define GET_TX_DESC_HTC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 25, 1)
|
||||
@@ -106,7 +124,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_OFFSET(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 16, 8, value)
|
||||
@@ -143,8 +161,17 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_KEYID_SEL(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value)
|
||||
#define GET_TX_DESC_KEYID_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_MOREDATA(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value)
|
||||
@@ -164,7 +191,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_PKT_OFFSET(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 24, 5, value)
|
||||
@@ -181,7 +209,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_SEC_TYPE(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 22, 2, value)
|
||||
@@ -204,7 +233,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_PIFS(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 15, 1, value)
|
||||
@@ -228,7 +258,7 @@
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_QSEL(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 8, 5, value)
|
||||
@@ -245,7 +275,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_MACID(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 7, value)
|
||||
@@ -262,7 +293,7 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXDESC_WORD2*/
|
||||
|
||||
@@ -281,7 +312,7 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
|
||||
HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_FTM_EN(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 30, 1, value)
|
||||
@@ -306,7 +337,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_G_ID(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 6, value)
|
||||
@@ -332,7 +364,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_BT_NULL(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 23, 1, value)
|
||||
@@ -365,7 +398,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_NULL_1(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 15, 1, value)
|
||||
@@ -386,7 +420,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_TRI_FRAME(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 9, 1, value)
|
||||
@@ -395,7 +430,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_P_AID(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 9, value)
|
||||
@@ -413,7 +449,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXDESC_WORD3*/
|
||||
|
||||
@@ -443,7 +480,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_NAVUSEHDR(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 15, 1, value)
|
||||
@@ -472,7 +510,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_DISDATAFB(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 10, 1, value)
|
||||
@@ -501,7 +540,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_WHEADER_LEN(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value)
|
||||
@@ -518,7 +558,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXDESC_WORD4*/
|
||||
|
||||
@@ -561,7 +602,7 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822C_SUPPORT)
|
||||
#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANTSEL_EN_V1(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 30, 1, value)
|
||||
@@ -578,7 +619,7 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822C_SUPPORT)
|
||||
#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 2, value)
|
||||
@@ -587,8 +628,18 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_TXPWR_OFSET_TYPE_V1(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 3, value)
|
||||
#define GET_TX_DESC_TXPWR_OFSET_TYPE_V1(txdesc) \
|
||||
LE_BITS_TO_4BYTE(txdesc + 0x14, 28, 3)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8192F_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_TX_ANT(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 4, value)
|
||||
@@ -604,8 +655,17 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_DROP_ID_V1(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 22, 2, value)
|
||||
#define GET_TX_DESC_DROP_ID_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 22, 2)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_PORT_ID(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 21, 3, value)
|
||||
@@ -613,8 +673,16 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_PORT_ID_V1(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 21, 1, value)
|
||||
#define GET_TX_DESC_PORT_ID_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 21, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_MULTIPLE_PORT(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 18, 3, value)
|
||||
@@ -623,7 +691,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 17, 1, value)
|
||||
@@ -632,7 +701,8 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_RTS_SC(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 13, 4, value)
|
||||
@@ -640,7 +710,8 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 13, 4, value)
|
||||
@@ -650,7 +721,8 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_RTS_SHORT(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 12, 1, value)
|
||||
@@ -677,7 +749,7 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXDESC_WORD6*/
|
||||
|
||||
@@ -695,8 +767,16 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANT_MAPC_V2(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 30, 2, value)
|
||||
#define GET_TX_DESC_ANT_MAPC_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 30, 2)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANT_MAPD(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 2, value)
|
||||
@@ -712,8 +792,16 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANT_MAPB_V2(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 2, value)
|
||||
#define GET_TX_DESC_ANT_MAPB_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 2)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANT_MAPC(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 2, value)
|
||||
@@ -729,8 +817,16 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANT_MAPA_V2(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 2, value)
|
||||
#define GET_TX_DESC_ANT_MAPA_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 2)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANT_MAPB(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 2, value)
|
||||
@@ -746,12 +842,34 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANTSEL_D_V1(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 2, value)
|
||||
#define GET_TX_DESC_ANTSEL_D_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 2)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANT_MAPA(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 22, 2, value)
|
||||
#define GET_TX_DESC_ANT_MAPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 22, 2)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANTSEL_C_V2(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 22, 2, value)
|
||||
#define GET_TX_DESC_ANTSEL_C_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 22, 2)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANTSEL_C(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 20, 2, value)
|
||||
#define GET_TX_DESC_ANTSEL_C(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 20, 2)
|
||||
@@ -766,8 +884,16 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANTSEL_B_V2(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 19, 3, value)
|
||||
#define GET_TX_DESC_ANTSEL_B_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 19, 3)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANTSEL_B(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 18, 2, value)
|
||||
@@ -786,8 +912,17 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANTSEL_A_V2(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 3, value)
|
||||
#define GET_TX_DESC_ANTSEL_A_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 3)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_MBSSID(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 12, 4, value)
|
||||
@@ -796,7 +931,7 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_SW_DEFINE(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 12, value)
|
||||
@@ -804,7 +939,7 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8198F_SUPPORT)
|
||||
#if (HALMAC_8198F_SUPPORT || HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_SWPS_SEQ(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 12, value)
|
||||
@@ -813,17 +948,43 @@
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXDESC_WORD7*/
|
||||
|
||||
#define SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 24, 8, value)
|
||||
#define GET_TX_DESC_DMA_TXAGG_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 24, 8)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 24, 8, value)
|
||||
#define GET_TX_DESC_FINAL_DATA_RATE(txdesc) \
|
||||
LE_BITS_TO_4BYTE(txdesc + 0x1C, 24, 8)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_ANT_MAPD_V2(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 22, 2, value)
|
||||
#define GET_TX_DESC_ANT_MAPD_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 22, 2)
|
||||
#define SET_TX_DESC_ANTSEL_EN_V2(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 21, 1, value)
|
||||
#define GET_TX_DESC_ANTSEL_EN_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 21, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_NTX_MAP(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 20, 4, value)
|
||||
#define GET_TX_DESC_NTX_MAP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 20, 4)
|
||||
@@ -841,8 +1002,17 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_MBSSID_EX_V1(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 16, 1, value)
|
||||
#define GET_TX_DESC_MBSSID_EX_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 16, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value)
|
||||
@@ -855,6 +1025,12 @@
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value)
|
||||
#define GET_TX_DESC_TIMESTAMP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXDESC_WORD8*/
|
||||
|
||||
#define SET_TX_DESC_TXWIFI_CP(txdesc, value) \
|
||||
@@ -881,6 +1057,13 @@
|
||||
#define SET_TX_DESC_SMH_EN(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 1, value)
|
||||
#define GET_TX_DESC_SMH_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_TAILPAGE_L(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 8, value)
|
||||
#define GET_TX_DESC_TAILPAGE_L(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 8)
|
||||
@@ -891,12 +1074,40 @@
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 8, value)
|
||||
#define GET_TX_DESC_NEXTHEADPAGE_L(txdesc) \
|
||||
LE_BITS_TO_4BYTE(txdesc + 0x20, 16, 8)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_EN_HWSEQ(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 15, 1, value)
|
||||
#define GET_TX_DESC_EN_HWSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 15, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_EN_HWEXSEQ(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 14, 1, value)
|
||||
#define GET_TX_DESC_EN_HWEXSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 14, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_EN_HWSEQ_MODE(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 14, 2, value)
|
||||
#define GET_TX_DESC_EN_HWSEQ_MODE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 14, 2)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_DATA_RC(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 8, 6, value)
|
||||
#define GET_TX_DESC_DATA_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 8, 6)
|
||||
@@ -907,6 +1118,12 @@
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 0, 6, value)
|
||||
#define GET_TX_DESC_RTS_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 0, 6)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*TXDESC_WORD9*/
|
||||
|
||||
#define SET_TX_DESC_TAILPAGE_H(txdesc, value) \
|
||||
@@ -916,12 +1133,42 @@
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 24, 4, value)
|
||||
#define GET_TX_DESC_NEXTHEADPAGE_H(txdesc) \
|
||||
LE_BITS_TO_4BYTE(txdesc + 0x24, 24, 4)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8192F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_FINAL_DATA_RATE_V1(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 24, 8, value)
|
||||
#define GET_TX_DESC_FINAL_DATA_RATE_V1(txdesc) \
|
||||
LE_BITS_TO_4BYTE(txdesc + 0x24, 24, 8)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_SW_SEQ(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 12, 12, value)
|
||||
#define GET_TX_DESC_SW_SEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 12, 12)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_TXBF_PATH(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 11, 1, value)
|
||||
#define GET_TX_DESC_TXBF_PATH(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 11, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
|
||||
HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_PADDING_LEN(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 11, value)
|
||||
#define GET_TX_DESC_PADDING_LEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 0, 11)
|
||||
@@ -932,16 +1179,45 @@
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
|
||||
#if (HALMAC_8812F_SUPPORT)
|
||||
|
||||
/*WORD10*/
|
||||
|
||||
#define SET_TX_DESC_HT_DATA_SND(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 31, 1, value)
|
||||
#define GET_TX_DESC_HT_DATA_SND(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 31, 1)
|
||||
#define SET_TX_DESC_SHCUT_CAM(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 16, 6, value)
|
||||
#define GET_TX_DESC_SHCUT_CAM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 16, 6)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_MU_DATARATE(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 8, 8, value)
|
||||
#define GET_TX_DESC_MU_DATARATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 8, 8)
|
||||
#define SET_TX_DESC_MU_RC(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 4, 4, value)
|
||||
#define GET_TX_DESC_MU_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 4, 4)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_NDPA_RATE_SEL(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 3, 1, value)
|
||||
#define GET_TX_DESC_NDPA_RATE_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 3, 1)
|
||||
#define SET_TX_DESC_HW_NDPA_EN(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 2, 1, value)
|
||||
#define GET_TX_DESC_HW_NDPA_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 2, 1)
|
||||
|
||||
#endif
|
||||
|
||||
#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \
|
||||
HALMAC_8812F_SUPPORT)
|
||||
|
||||
#define SET_TX_DESC_SND_PKT_SEL(txdesc, value) \
|
||||
SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 0, 2, value)
|
||||
#define GET_TX_DESC_SND_PKT_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 0, 2)
|
||||
|
||||
@@ -48,6 +48,18 @@
|
||||
#define HALMAC_MSG_LEVEL_NO_LOG 0
|
||||
#endif
|
||||
|
||||
#ifndef HALMAC_SDIO_SUPPORT
|
||||
#define HALMAC_SDIO_SUPPORT 1
|
||||
#endif
|
||||
|
||||
#ifndef HALMAC_USB_SUPPORT
|
||||
#define HALMAC_USB_SUPPORT 1
|
||||
#endif
|
||||
|
||||
#ifndef HALMAC_PCIE_SUPPORT
|
||||
#define HALMAC_PCIE_SUPPORT 1
|
||||
#endif
|
||||
|
||||
#ifndef HALMAC_MSG_LEVEL
|
||||
#define HALMAC_MSG_LEVEL HALMAC_MSG_LEVEL_TRACE
|
||||
#endif
|
||||
@@ -176,18 +188,36 @@
|
||||
api->halmac_reg_sdio_cmd53_read_n(adapter, offset, size, data)
|
||||
|
||||
#define HALMAC_REG_W8_CLR(offset, mask) \
|
||||
HALMAC_REG_W8(offset, HALMAC_REG_R8(offset) & ~(mask))
|
||||
do { \
|
||||
u32 __offset = (u32)offset; \
|
||||
HALMAC_REG_W8(__offset, HALMAC_REG_R8(__offset) & ~(mask)); \
|
||||
} while (0)
|
||||
#define HALMAC_REG_W16_CLR(offset, mask) \
|
||||
HALMAC_REG_W16(offset, HALMAC_REG_R16(offset) & ~(mask))
|
||||
do { \
|
||||
u32 __offset = (u32)offset; \
|
||||
HALMAC_REG_W16(__offset, HALMAC_REG_R16(__offset) & ~(mask)); \
|
||||
} while (0)
|
||||
#define HALMAC_REG_W32_CLR(offset, mask) \
|
||||
HALMAC_REG_W32(offset, HALMAC_REG_R32(offset) & ~(mask))
|
||||
do { \
|
||||
u32 __offset = (u32)offset; \
|
||||
HALMAC_REG_W32(__offset, HALMAC_REG_R32(__offset) & ~(mask)); \
|
||||
} while (0)
|
||||
|
||||
#define HALMAC_REG_W8_SET(offset, mask) \
|
||||
HALMAC_REG_W8(offset, HALMAC_REG_R8(offset) | (mask))
|
||||
do { \
|
||||
u32 __offset = (u32)offset; \
|
||||
HALMAC_REG_W8(__offset, HALMAC_REG_R8(__offset) | mask); \
|
||||
} while (0)
|
||||
#define HALMAC_REG_W16_SET(offset, mask) \
|
||||
HALMAC_REG_W16(offset, HALMAC_REG_R16(offset) | (mask))
|
||||
do { \
|
||||
u32 __offset = (u32)offset; \
|
||||
HALMAC_REG_W16(__offset, HALMAC_REG_R16(__offset) | mask); \
|
||||
} while (0)
|
||||
#define HALMAC_REG_W32_SET(offset, mask) \
|
||||
HALMAC_REG_W32(offset, HALMAC_REG_R32(offset) | (mask))
|
||||
do { \
|
||||
u32 __offset = (u32)offset; \
|
||||
HALMAC_REG_W32(__offset, HALMAC_REG_R32(__offset) | mask); \
|
||||
} while (0)
|
||||
|
||||
/* Swap Little-endian <-> Big-endia*/
|
||||
#define SWAP32(x) \
|
||||
@@ -479,6 +509,8 @@ enum halmac_ret_status {
|
||||
HALMAC_RET_TXDESC_SET_FAIL = 0x73,
|
||||
HALMAC_RET_WLHDR_FAIL = 0x74,
|
||||
HALMAC_RET_WLAN_MODE_FAIL = 0x75,
|
||||
HALMAC_RET_SDIO_SEQ_FAIL = 0x72,
|
||||
HALMAC_RET_INIT_XTAL_AAC_FAIL = 0x76,
|
||||
};
|
||||
|
||||
enum halmac_chip_id {
|
||||
@@ -487,6 +519,7 @@ enum halmac_chip_id {
|
||||
HALMAC_CHIP_ID_8814B = 2,
|
||||
HALMAC_CHIP_ID_8197F = 3,
|
||||
HALMAC_CHIP_ID_8822C = 4,
|
||||
HALMAC_CHIP_ID_8812F = 5,
|
||||
HALMAC_CHIP_ID_UNDEFINE = 0x7F,
|
||||
};
|
||||
|
||||
@@ -858,6 +891,7 @@ struct halmac_hw_cfg_info {
|
||||
u8 acq_num;
|
||||
u8 trx_mode;
|
||||
u8 usb_txagg_num;
|
||||
u32 prtct_efuse_size;
|
||||
};
|
||||
|
||||
struct halmac_sdio_free_space {
|
||||
@@ -948,6 +982,7 @@ struct halmac_ch_switch_option {
|
||||
u8 normal_cycle;
|
||||
u8 phase_2_period;
|
||||
u8 phase_2_period_sel;
|
||||
u8 nlo_en;
|
||||
};
|
||||
|
||||
struct halmac_p2pps {
|
||||
@@ -1027,6 +1062,11 @@ struct halmac_fast_edca_cfg {
|
||||
u8 queue_to; /* unit : 32us*/
|
||||
};
|
||||
|
||||
struct halmac_txfifo_lifetime_cfg {
|
||||
u8 enable;
|
||||
u32 lifetime;
|
||||
};
|
||||
|
||||
enum halmac_data_rate {
|
||||
HALMAC_CCK1,
|
||||
HALMAC_CCK2,
|
||||
@@ -1199,6 +1239,7 @@ enum halmac_drv_rsvd_pg_num {
|
||||
HALMAC_RSVD_PG_NUM32, /* 4K */
|
||||
HALMAC_RSVD_PG_NUM64, /* 8K */
|
||||
HALMAC_RSVD_PG_NUM128, /* 16K */
|
||||
HALMAC_RSVD_PG_NUM256, /* 32K */
|
||||
};
|
||||
|
||||
enum halmac_pcie_cfg {
|
||||
@@ -1232,11 +1273,11 @@ union halmac_wlan_addr {
|
||||
u8 addr[6];
|
||||
struct {
|
||||
union {
|
||||
u32 low;
|
||||
__le32 low;
|
||||
u8 low_byte[4];
|
||||
};
|
||||
union {
|
||||
u16 high;
|
||||
__le16 high;
|
||||
u8 high_byte[2];
|
||||
};
|
||||
} addr_l_h;
|
||||
@@ -1268,9 +1309,6 @@ struct halmac_platform_api {
|
||||
/* send pBuf to h2c queue, the tx_desc is not included in pBuf */
|
||||
/* driver need to fill tx_desc with qsel = h2c */
|
||||
u8 (*SEND_H2C_PKT)(void *drv_adapter, u8 *buf, u32 size);
|
||||
/* send pBuf to fw cmd queue, the tx_desc is not included in pBuf */
|
||||
/*driver need to fill tx_desc with qsel = h2c */
|
||||
u8 (*SEND_FWCMD)(void *drv_adapter, u8 *buf, u32 size);
|
||||
|
||||
u8 (*RTL_FREE)(void *drv_adapter, void *buf, u32 size);
|
||||
void* (*RTL_MALLOC)(void *drv_adapter, u32 size);
|
||||
@@ -1518,6 +1556,8 @@ enum halmac_api_id {
|
||||
HALMAC_API_GET_CPU_MODE = 0x9A,
|
||||
HALMAC_API_DRV_FWCTRL = 0x9B,
|
||||
HALMAC_API_EN_REF_AUTOK = 0x9C,
|
||||
HALMAC_API_RESET_WIFI_FW = 0x9D,
|
||||
HALMAC_API_CFGSPC_SET_PCIE = 0x9E,
|
||||
HALMAC_API_MAX
|
||||
};
|
||||
|
||||
@@ -1556,6 +1596,12 @@ enum halmac_sdio_tx_format {
|
||||
HALMAC_SDIO_DUMMY_AUTO_MODE = 3,
|
||||
};
|
||||
|
||||
enum halmac_sdio_clk_monitor {
|
||||
HALMAC_MONITOR_5US = 1,
|
||||
HALMAC_MONITOR_50US = 2,
|
||||
HALMAC_MONITOR_9MS = 3,
|
||||
};
|
||||
|
||||
enum halmac_hw_id {
|
||||
/* Get HW value */
|
||||
HALMAC_HW_RQPN_MAPPING = 0x00,
|
||||
@@ -1584,13 +1630,13 @@ enum halmac_hw_id {
|
||||
HALMAC_HW_TX_PAGE_SIZE = 0x17,
|
||||
HALMAC_HW_USB_TXAGG_DESC_NUM = 0x18,
|
||||
HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 0x19,
|
||||
HALMAC_HW_HIOE_INST_START = 0x1A,
|
||||
HALMAC_HW_HIOE_INST_END = 0x1B,
|
||||
HALMAC_HW_AC_OQT_SIZE = 0x1C,
|
||||
HALMAC_HW_NON_AC_OQT_SIZE = 0x1D,
|
||||
HALMAC_HW_AC_QUEUE_NUM = 0x1E,
|
||||
HALMAC_HW_RQPN_CH_MAPPING = 0x1F,
|
||||
HALMAC_HW_PWR_STATE = 0x20,
|
||||
HALMAC_HW_SDIO_INT_LAT = 0x21,
|
||||
HALMAC_HW_SDIO_CLK_CNT = 0x22,
|
||||
/* Set HW value */
|
||||
HALMAC_HW_USB_MODE = 0x60,
|
||||
HALMAC_HW_SEQ_EN = 0x61,
|
||||
@@ -1609,6 +1655,11 @@ enum halmac_hw_id {
|
||||
HALMAC_HW_FAST_EDCA = 0x6E,
|
||||
HALMAC_HW_LDO25_EN = 0x6F,
|
||||
HALMAC_HW_PCIE_REF_AUTOK = 0x70,
|
||||
HALMAC_HW_RTS_FULL_BW = 0x71,
|
||||
HALMAC_HW_FREE_CNT_EN = 0x72,
|
||||
HALMAC_HW_SDIO_WT_EN = 0x73,
|
||||
HALMAC_HW_SDIO_CLK_MONITOR = 0x74,
|
||||
HALMAC_HW_TXFIFO_LIFETIME = 0x75,
|
||||
HALMAC_HW_ID_UNDEFINE = 0x7F,
|
||||
};
|
||||
|
||||
@@ -1646,6 +1697,8 @@ enum halmac_gpio_func {
|
||||
HALMAC_GPIO_FUNC_SW_IO_13 = 15,
|
||||
HALMAC_GPIO_FUNC_SW_IO_14 = 16,
|
||||
HALMAC_GPIO_FUNC_SW_IO_15 = 17,
|
||||
HALMAC_GPIO_FUNC_BT_HOST_WAKE1 = 18,
|
||||
HALMAC_GPIO_FUNC_BT_DEV_WAKE1 = 19,
|
||||
HALMAC_GPIO_FUNC_UNDEFINE = 0X7F,
|
||||
};
|
||||
|
||||
@@ -1668,6 +1721,68 @@ enum halmac_psf_fcs_chk_thr {
|
||||
HALMAC_PSF_FCS_CHK_THR_28 = 7,
|
||||
};
|
||||
|
||||
enum halmac_func_ctrl {
|
||||
HALMAC_DISABLE = 0,
|
||||
HALMAC_ENABLE = 1,
|
||||
HALMAC_DEFAULT = 0xFE,
|
||||
HALMAC_IGNORE = 0xFF
|
||||
};
|
||||
|
||||
enum halmac_pcie_clkdly {
|
||||
HALMAC_CLKDLY_0 = 0,
|
||||
HALMAC_CLKDLY_5US = 1,
|
||||
HALMAC_CLKDLY_6US = 2,
|
||||
HALMAC_CLKDLY_11US = 3,
|
||||
HALMAC_CLKDLY_15US = 4,
|
||||
HALMAC_CLKDLY_19US = 5,
|
||||
HALMAC_CLKDLY_25US = 6,
|
||||
HALMAC_CLKDLY_30US = 7,
|
||||
HALMAC_CLKDLY_38US = 8,
|
||||
HALMAC_CLKDLY_50US = 9,
|
||||
HALMAC_CLKDLY_64US = 10,
|
||||
HALMAC_CLKDLY_100US = 11,
|
||||
HALMAC_CLKDLY_128US = 12,
|
||||
HALMAC_CLKDLY_150US = 13,
|
||||
HALMAC_CLKDLY_192US = 14,
|
||||
HALMAC_CLKDLY_200US = 15,
|
||||
HALMAC_CLKDLY_R_ERR = 0xFD,
|
||||
HALMAC_CLKDLY_DEF = 0xFE,
|
||||
HALMAC_CLKDLY_IGNORE = 0xFF
|
||||
};
|
||||
|
||||
enum halmac_pcie_l1dly {
|
||||
HALMAC_L1DLY_16US = 0,
|
||||
HALMAC_L1DLY_32US = 1,
|
||||
HALMAC_L1DLY_64US = 2,
|
||||
HALMAC_L1DLY_INFI = 3,
|
||||
HALMAC_L1DLY_R_ERR = 0xFD,
|
||||
HALMAC_L1DLY_DEF = 0xFE,
|
||||
HALMAC_L1DLY_IGNORE = 0xFF
|
||||
};
|
||||
|
||||
enum halmac_pcie_l0sdly {
|
||||
HALMAC_L0SDLY_1US = 0,
|
||||
HALMAC_L0SDLY_3US = 1,
|
||||
HALMAC_L0SDLY_5US = 2,
|
||||
HALMAC_L0SDLY_7US = 3,
|
||||
HALMAC_L0SDLY_R_ERR = 0xFD,
|
||||
HALMAC_L0SDLY_DEF = 0xFE,
|
||||
HALMAC_L0SDLY_IGNORE = 0xFF
|
||||
};
|
||||
|
||||
struct halmac_pcie_cfgspc_param {
|
||||
u8 write;
|
||||
u8 read;
|
||||
enum halmac_func_ctrl l0s_ctrl;
|
||||
enum halmac_func_ctrl l1_ctrl;
|
||||
enum halmac_func_ctrl l1ss_ctrl;
|
||||
enum halmac_func_ctrl wake_ctrl;
|
||||
enum halmac_func_ctrl crq_ctrl;
|
||||
enum halmac_pcie_clkdly clkdly_ctrl;
|
||||
enum halmac_pcie_l0sdly l0sdly_ctrl;
|
||||
enum halmac_pcie_l1dly l1dly_ctrl;
|
||||
};
|
||||
|
||||
struct halmac_txff_allocation {
|
||||
u16 tx_fifo_pg_num;
|
||||
u16 rsvd_pg_num;
|
||||
@@ -1828,6 +1943,16 @@ struct halmac_edca_para {
|
||||
struct halmac_mac_rx_ignore_cfg {
|
||||
u8 hdr_chk_en;
|
||||
u8 fcs_chk_en;
|
||||
u8 cck_rst_en;
|
||||
enum halmac_psf_fcs_chk_thr fcs_chk_thr;
|
||||
};
|
||||
|
||||
struct halmac_rx_ignore_info {
|
||||
u8 hdr_chk_mask;
|
||||
u8 fcs_chk_mask;
|
||||
u8 hdr_chk_en;
|
||||
u8 fcs_chk_en;
|
||||
u8 cck_rst_en;
|
||||
enum halmac_psf_fcs_chk_thr fcs_chk_thr;
|
||||
};
|
||||
|
||||
@@ -1835,7 +1960,9 @@ struct halmac_pinmux_info {
|
||||
/* byte0 */
|
||||
u8 wl_led:1;
|
||||
u8 sdio_int:1;
|
||||
u8 rsvd1:6;
|
||||
u8 bt_host_wake:1;
|
||||
u8 bt_dev_wake:1;
|
||||
u8 rsvd1:4;
|
||||
/* byte1 */
|
||||
u8 sw_io_0:1;
|
||||
u8 sw_io_1:1;
|
||||
@@ -1885,9 +2012,9 @@ struct halmac_h2c_info {
|
||||
struct halmac_adapter {
|
||||
enum halmac_dma_mapping pq_map[HALMAC_PQ_MAP_NUM];
|
||||
enum halmac_dma_ch ch_map[HALMAC_PQ_MAP_NUM];
|
||||
HALMAC_MUTEX h2c_seq_mutex;
|
||||
HALMAC_MUTEX efuse_mutex;
|
||||
HALMAC_MUTEX sdio_indir_mutex; /*Protect sdio indirect access */
|
||||
HALMAC_MUTEX h2c_seq_mutex; /* protect h2c seq num */
|
||||
HALMAC_MUTEX efuse_mutex; /*protect adapter efuse map */
|
||||
HALMAC_MUTEX sdio_indir_mutex; /*protect sdio indirect access */
|
||||
struct halmac_cfg_param_info cfg_param_info;
|
||||
struct halmac_ch_sw_info ch_sw_info;
|
||||
struct halmac_event_trigger evnt;
|
||||
@@ -1922,7 +2049,8 @@ struct halmac_adapter {
|
||||
u8 efuse_auto_check_en;
|
||||
u8 pcie_refautok_en;
|
||||
u8 pwr_off_flow_flag;
|
||||
|
||||
u8 nlo_flag;
|
||||
struct halmac_rx_ignore_info rx_ignore_info;
|
||||
#if HALMAC_PLATFORM_TESTPROGRAM
|
||||
struct halmisc_adapter *halmisc_adapter;
|
||||
#endif
|
||||
@@ -1943,6 +2071,8 @@ struct halmac_api {
|
||||
enum halmac_dlfw_mem mem_sel,
|
||||
u8 *fw_bin, u32 size);
|
||||
enum halmac_ret_status
|
||||
(*halmac_reset_wifi_fw)(struct halmac_adapter *adapter);
|
||||
enum halmac_ret_status
|
||||
(*halmac_get_fw_version)(struct halmac_adapter *adapter,
|
||||
struct halmac_fw_version *ver);
|
||||
enum halmac_ret_status
|
||||
@@ -2238,12 +2368,14 @@ struct halmac_api {
|
||||
enum halmac_ret_status
|
||||
(*halmac_cfg_csi_rate)(struct halmac_adapter *adapter, u8 rssi,
|
||||
u8 cur_rate, u8 fixrate_en, u8 *new_rate);
|
||||
#if HALMAC_SDIO_SUPPORT
|
||||
enum halmac_ret_status
|
||||
(*halmac_sdio_cmd53_4byte)(struct halmac_adapter *adapter,
|
||||
enum halmac_sdio_cmd53_4byte_mode mode);
|
||||
enum halmac_ret_status
|
||||
(*halmac_sdio_hw_info)(struct halmac_adapter *adapter,
|
||||
struct halmac_sdio_hw_info *info);
|
||||
#endif
|
||||
enum halmac_ret_status
|
||||
(*halmac_cfg_transmitter_addr)(struct halmac_adapter *adapter, u8 port,
|
||||
union halmac_wlan_addr *addr);
|
||||
@@ -2266,7 +2398,8 @@ struct halmac_api {
|
||||
(*halmac_download_flash)(struct halmac_adapter *adapter, u8 *fw_bin,
|
||||
u32 size, u32 rom_addr);
|
||||
enum halmac_ret_status
|
||||
(*halmac_read_flash)(struct halmac_adapter *adapter, u32 addr);
|
||||
(*halmac_read_flash)(struct halmac_adapter *adapter, u32 addr,
|
||||
u32 length);
|
||||
enum halmac_ret_status
|
||||
(*halmac_erase_flash)(struct halmac_adapter *adapter, u8 erase_cmd,
|
||||
u32 addr);
|
||||
@@ -2332,8 +2465,13 @@ struct halmac_api {
|
||||
enum halmac_ret_status
|
||||
(*halmac_write_efuse)(struct halmac_adapter *adapter, u32 offset,
|
||||
u8 value);
|
||||
VOID
|
||||
#if HALMAC_PCIE_SUPPORT
|
||||
enum halmac_ret_status
|
||||
(*halmac_cfgspc_set_pcie)(struct halmac_adapter *adapter,
|
||||
struct halmac_pcie_cfgspc_param *param);
|
||||
void
|
||||
(*halmac_en_ref_autok_pcie)(struct halmac_adapter *adapter, u8 en);
|
||||
#endif
|
||||
#if HALMAC_PLATFORM_TESTPROGRAM
|
||||
struct halmisc_api *halmisc_api;
|
||||
#endif
|
||||
|
||||
@@ -1,118 +1,188 @@
|
||||
|
||||
_PHYDM_FILES :=\
|
||||
phydm/phydm.o \
|
||||
phydm/phydm_dig.o\
|
||||
phydm/phydm_antdiv.o\
|
||||
phydm/phydm_soml.o\
|
||||
phydm/phydm_smt_ant.o\
|
||||
phydm/phydm_pathdiv.o\
|
||||
phydm/phydm_rainfo.o\
|
||||
phydm/phydm_dynamictxpower.o\
|
||||
phydm/phydm_adaptivity.o\
|
||||
phydm/phydm_debug.o\
|
||||
phydm/phydm_interface.o\
|
||||
phydm/phydm_phystatus.o\
|
||||
phydm/phydm_hwconfig.o\
|
||||
phydm/phydm_dfs.o\
|
||||
phydm/phydm_cfotracking.o\
|
||||
phydm/phydm_adc_sampling.o\
|
||||
phydm/phydm_ccx.o\
|
||||
phydm/phydm_primary_cca.o\
|
||||
phydm/phydm_cck_pd.o\
|
||||
phydm/phydm_rssi_monitor.o\
|
||||
phydm/phydm_auto_dbg.o\
|
||||
phydm/phydm_math_lib.o\
|
||||
phydm/phydm_noisemonitor.o\
|
||||
phydm/phydm_api.o\
|
||||
phydm/phydm_pow_train.o\
|
||||
phydm/txbf/phydm_hal_txbf_api.o\
|
||||
EdcaTurboCheck.o\
|
||||
phydm/halrf/halrf.o\
|
||||
phydm/halrf/halphyrf_ap.o\
|
||||
phydm/halrf/halrf_powertracking_ap.o\
|
||||
phydm/halrf/halrf_powertracking.o\
|
||||
phydm/halrf/halrf_kfree.o
|
||||
|
||||
ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
|
||||
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
|
||||
_PHYDM_FILES += \
|
||||
phydm/rtl8188e/halhwimg8188e_bb.o\
|
||||
phydm/rtl8188e/halhwimg8188e_mac.o\
|
||||
phydm/rtl8188e/halhwimg8188e_rf.o\
|
||||
phydm/rtl8188e/phydm_regconfig8188e.o\
|
||||
phydm/rtl8188e/hal8188erateadaptive.o\
|
||||
phydm/rtl8188e/phydm_rtl8188e.o\
|
||||
phydm/halrf/rtl8188e/halrf_8188e_ap.o
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_RTL_8812_SUPPORT),y)
|
||||
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
|
||||
_PHYDM_FILES += ./phydm/halrf/rtl8812a/halrf_8812a_ap.o
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_WLAN_HAL_8881A),y)
|
||||
_PHYDM_FILES += phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.o
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
|
||||
_PHYDM_FILES += \
|
||||
phydm/halrf/rtl8192e/halrf_8192e_ap.o\
|
||||
phydm/rtl8192e/phydm_rtl8192e.o
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
|
||||
rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_8814a_ap.o
|
||||
rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_iqk_8814a.o
|
||||
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
|
||||
rtl8192cd-objs += \
|
||||
phydm/rtl8814a/halhwimg8814a_bb.o\
|
||||
phydm/rtl8814a/halhwimg8814a_mac.o\
|
||||
phydm/rtl8814a/halhwimg8814a_rf.o\
|
||||
phydm/rtl8814a/phydm_regconfig8814a.o\
|
||||
phydm/rtl8814a/phydm_rtl8814a.o
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_WLAN_HAL_8822BE),y)
|
||||
_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_8822b.o
|
||||
_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_iqk_8822b.o
|
||||
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
|
||||
_PHYDM_FILES += \
|
||||
phydm/rtl8822b/halhwimg8822b_bb.o\
|
||||
phydm/rtl8822b/halhwimg8822b_mac.o\
|
||||
phydm/rtl8822b/halhwimg8822b_rf.o\
|
||||
phydm/rtl8822b/phydm_regconfig8822b.o\
|
||||
phydm/rtl8822b/phydm_hal_api8822b.o\
|
||||
phydm/rtl8822b/phydm_rtl8822b.o
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_WLAN_HAL_8821CE),y)
|
||||
_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_8821c.o
|
||||
_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_iqk_8821c.o
|
||||
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
|
||||
_PHYDM_FILES += \
|
||||
phydm/rtl8821c/halhwimg8821c_bb.o\
|
||||
phydm/rtl8821c/halhwimg8821c_mac.o\
|
||||
phydm/rtl8821c/halhwimg8821c_rf.o\
|
||||
phydm/rtl8821c/phydm_regconfig8821c.o\
|
||||
phydm/rtl8821c/phydm_hal_api8821c.o
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_WLAN_HAL_8197F),y)
|
||||
_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_8197f.o
|
||||
_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_iqk_8197f.o
|
||||
_PHYDM_FILES += efuse_97f/efuse.o
|
||||
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
|
||||
_PHYDM_FILES += \
|
||||
phydm/rtl8197f/halhwimg8197f_bb.o\
|
||||
phydm/rtl8197f/halhwimg8197f_mac.o\
|
||||
phydm/rtl8197f/halhwimg8197f_rf.o\
|
||||
phydm/rtl8197f/phydm_hal_api8197f.o\
|
||||
phydm/rtl8197f/phydm_regconfig8197f.o\
|
||||
phydm/rtl8197f/phydm_rtl8197f.o
|
||||
endif
|
||||
endif
|
||||
|
||||
_PHYDM_FILES :=\
|
||||
phydm/phydm.o \
|
||||
phydm/phydm_dig.o\
|
||||
phydm/phydm_antdiv.o\
|
||||
phydm/phydm_soml.o\
|
||||
phydm/phydm_smt_ant.o\
|
||||
phydm/phydm_pathdiv.o\
|
||||
phydm/phydm_rainfo.o\
|
||||
phydm/phydm_dynamictxpower.o\
|
||||
phydm/phydm_adaptivity.o\
|
||||
phydm/phydm_debug.o\
|
||||
phydm/phydm_interface.o\
|
||||
phydm/phydm_phystatus.o\
|
||||
phydm/phydm_hwconfig.o\
|
||||
phydm/phydm_dfs.o\
|
||||
phydm/phydm_cfotracking.o\
|
||||
phydm/phydm_adc_sampling.o\
|
||||
phydm/phydm_ccx.o\
|
||||
phydm/phydm_primary_cca.o\
|
||||
phydm/phydm_cck_pd.o\
|
||||
phydm/phydm_rssi_monitor.o\
|
||||
phydm/phydm_auto_dbg.o\
|
||||
phydm/phydm_math_lib.o\
|
||||
phydm/phydm_noisemonitor.o\
|
||||
phydm/phydm_api.o\
|
||||
phydm/phydm_pow_train.o\
|
||||
phydm/phydm_lna_sat.o\
|
||||
phydm/phydm_pmac_tx_setting.o\
|
||||
phydm/phydm_mp.o\
|
||||
phydm/txbf/phydm_hal_txbf_api.o\
|
||||
EdcaTurboCheck.o\
|
||||
phydm/halrf/halrf.o\
|
||||
phydm/halrf/halrf_debug.o\
|
||||
phydm/halrf/halphyrf_ap.o\
|
||||
phydm/halrf/halrf_powertracking_ap.o\
|
||||
phydm/halrf/halrf_powertracking.o\
|
||||
phydm/halrf/halrf_kfree.o
|
||||
|
||||
ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
|
||||
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
|
||||
_PHYDM_FILES += \
|
||||
phydm/rtl8188e/halhwimg8188e_bb.o\
|
||||
phydm/rtl8188e/halhwimg8188e_mac.o\
|
||||
phydm/rtl8188e/halhwimg8188e_rf.o\
|
||||
phydm/rtl8188e/phydm_regconfig8188e.o\
|
||||
phydm/rtl8188e/hal8188erateadaptive.o\
|
||||
phydm/rtl8188e/phydm_rtl8188e.o\
|
||||
phydm/halrf/rtl8188e/halrf_8188e_ap.o
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_RTL_8812_SUPPORT),y)
|
||||
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
|
||||
_PHYDM_FILES += ./phydm/halrf/rtl8812a/halrf_8812a_ap.o
|
||||
endif
|
||||
_PHYDM_FILES += phydm/rtl8812a/phydm_rtl8812a.o
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_WLAN_HAL_8881A),y)
|
||||
_PHYDM_FILES += phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.o
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
|
||||
_PHYDM_FILES += \
|
||||
phydm/halrf/rtl8192e/halrf_8192e_ap.o\
|
||||
phydm/rtl8192e/phydm_rtl8192e.o
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
|
||||
rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_8814a_ap.o
|
||||
rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_iqk_8814a.o
|
||||
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
|
||||
rtl8192cd-objs += \
|
||||
phydm/rtl8814a/halhwimg8814a_bb.o\
|
||||
phydm/rtl8814a/halhwimg8814a_mac.o\
|
||||
phydm/rtl8814a/halhwimg8814a_rf.o\
|
||||
phydm/rtl8814a/phydm_regconfig8814a.o\
|
||||
phydm/rtl8814a/phydm_rtl8814a.o
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_WLAN_HAL_8822BE),y)
|
||||
_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_8822b.o
|
||||
_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_iqk_8822b.o
|
||||
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
|
||||
_PHYDM_FILES += \
|
||||
phydm/rtl8822b/halhwimg8822b_bb.o\
|
||||
phydm/rtl8822b/halhwimg8822b_mac.o\
|
||||
phydm/rtl8822b/halhwimg8822b_rf.o\
|
||||
phydm/rtl8822b/phydm_regconfig8822b.o\
|
||||
phydm/rtl8822b/phydm_hal_api8822b.o\
|
||||
phydm/rtl8822b/phydm_rtl8822b.o
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_WLAN_HAL_8822CE),y)
|
||||
_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_8822c.o
|
||||
_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_iqk_8822c.o
|
||||
_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_dpk_8822c.o
|
||||
_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_rfk_init_8822c.o
|
||||
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
|
||||
_PHYDM_FILES += \
|
||||
phydm/rtl8822c/halhwimg8822c_bb.o\
|
||||
phydm/rtl8822c/halhwimg8822c_mac.o\
|
||||
phydm/rtl8822c/halhwimg8822c_rf.o\
|
||||
phydm/rtl8822c/phydm_regconfig8822c.o\
|
||||
phydm/rtl8822c/phydm_hal_api8822c.o
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_WLAN_HAL_8821CE),y)
|
||||
_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_8821c.o
|
||||
_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_iqk_8821c.o
|
||||
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
|
||||
_PHYDM_FILES += \
|
||||
phydm/rtl8821c/halhwimg8821c_bb.o\
|
||||
phydm/rtl8821c/halhwimg8821c_mac.o\
|
||||
phydm/rtl8821c/halhwimg8821c_rf.o\
|
||||
phydm/rtl8821c/phydm_regconfig8821c.o\
|
||||
phydm/rtl8821c/phydm_hal_api8821c.o
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_WLAN_HAL_8197F),y)
|
||||
_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_8197f.o
|
||||
_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_iqk_8197f.o
|
||||
_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_dpk_8197f.o
|
||||
_PHYDM_FILES += efuse_97f/efuse.o
|
||||
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
|
||||
_PHYDM_FILES += \
|
||||
phydm/rtl8197f/halhwimg8197f_bb.o\
|
||||
phydm/rtl8197f/halhwimg8197f_mac.o\
|
||||
phydm/rtl8197f/halhwimg8197f_rf.o\
|
||||
phydm/rtl8197f/phydm_hal_api8197f.o\
|
||||
phydm/rtl8197f/phydm_regconfig8197f.o\
|
||||
phydm/rtl8197f/phydm_rtl8197f.o
|
||||
endif
|
||||
endif
|
||||
|
||||
|
||||
ifeq ($(CONFIG_WLAN_HAL_8192FE),y)
|
||||
_PHYDM_FILES += phydm/halrf/rtl8192f/halrf_8192f.o
|
||||
_PHYDM_FILES += phydm/halrf/rtl8192f/halrf_dpk_8192f.o
|
||||
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
|
||||
_PHYDM_FILES += \
|
||||
phydm/rtl8192f/halhwimg8192f_bb.o\
|
||||
phydm/rtl8192f/halhwimg8192f_mac.o\
|
||||
phydm/rtl8192f/halhwimg8192f_rf.o\
|
||||
phydm/rtl8192f/phydm_hal_api8192f.o\
|
||||
phydm/rtl8192f/phydm_regconfig8192f.o\
|
||||
phydm/rtl8192f/phydm_rtl8192f.o
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_WLAN_HAL_8198F),y)
|
||||
_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_8198f.o
|
||||
_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_iqk_8198f.o
|
||||
_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_dpk_8198f.o
|
||||
_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_rfk_init_8198f.o
|
||||
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
|
||||
_PHYDM_FILES += \
|
||||
phydm/rtl8198f/phydm_hal_api8198f.o\
|
||||
phydm/rtl8198f/halhwimg8198f_bb.o\
|
||||
phydm/rtl8198f/halhwimg8198f_mac.o\
|
||||
phydm/rtl8198f/halhwimg8198f_rf.o\
|
||||
phydm/rtl8198f/phydm_regconfig8198f.o \
|
||||
phydm/halrf/rtl8198f/halrf_8198f.o
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_WLAN_HAL_8814BE),y)
|
||||
_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_8814b.o
|
||||
_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_iqk_8814b.o
|
||||
_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_rfk_init_8814b.o
|
||||
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
|
||||
_PHYDM_FILES += \
|
||||
phydm/rtl8814b/phydm_hal_api8814b.o\
|
||||
phydm/rtl8814b/halhwimg8814b_bb.o\
|
||||
phydm/rtl8814b/halhwimg8814b_mac.o\
|
||||
phydm/rtl8814b/halhwimg8814b_rf.o\
|
||||
phydm/rtl8814b/phydm_regconfig8814b.o \
|
||||
phydm/halrf/rtl8814b/halrf_8814b.o
|
||||
endif
|
||||
endif
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -16,76 +16,76 @@
|
||||
#ifndef __INC_HW_IMG_H
|
||||
#define __INC_HW_IMG_H
|
||||
|
||||
/*
|
||||
/*@
|
||||
* 2011/03/15 MH Add for different IC HW image file selection. code size consideration.
|
||||
* */
|
||||
#if RT_PLATFORM == PLATFORM_LINUX
|
||||
|
||||
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
|
||||
/* For 92C */
|
||||
/* @For 92C */
|
||||
#define RTL8192CE_HWIMG_SUPPORT 1
|
||||
#define RTL8192CE_TEST_HWIMG_SUPPORT 0
|
||||
#define RTL8192CU_HWIMG_SUPPORT 0
|
||||
#define RTL8192CU_TEST_HWIMG_SUPPORT 0
|
||||
|
||||
/* For 92D */
|
||||
/* @For 92D */
|
||||
#define RTL8192DE_HWIMG_SUPPORT 1
|
||||
#define RTL8192DE_TEST_HWIMG_SUPPORT 0
|
||||
#define RTL8192DU_HWIMG_SUPPORT 0
|
||||
#define RTL8192DU_TEST_HWIMG_SUPPORT 0
|
||||
|
||||
/* For 8723 */
|
||||
/* @For 8723 */
|
||||
#define RTL8723E_HWIMG_SUPPORT 1
|
||||
#define RTL8723U_HWIMG_SUPPORT 0
|
||||
#define RTL8723S_HWIMG_SUPPORT 0
|
||||
|
||||
/* For 88E */
|
||||
/* @For 88E */
|
||||
#define RTL8188EE_HWIMG_SUPPORT 0
|
||||
#define RTL8188EU_HWIMG_SUPPORT 0
|
||||
#define RTL8188ES_HWIMG_SUPPORT 0
|
||||
|
||||
#elif (DEV_BUS_TYPE == RT_USB_INTERFACE)
|
||||
/* For 92C */
|
||||
/* @For 92C */
|
||||
#define RTL8192CE_HWIMG_SUPPORT 0
|
||||
#define RTL8192CE_TEST_HWIMG_SUPPORT 0
|
||||
#define RTL8192CU_HWIMG_SUPPORT 1
|
||||
#define RTL8192CU_TEST_HWIMG_SUPPORT 0
|
||||
|
||||
/* For 92D */
|
||||
/* @For 92D */
|
||||
#define RTL8192DE_HWIMG_SUPPORT 0
|
||||
#define RTL8192DE_TEST_HWIMG_SUPPORT 0
|
||||
#define RTL8192DU_HWIMG_SUPPORT 1
|
||||
#define RTL8192DU_TEST_HWIMG_SUPPORT 0
|
||||
|
||||
/* For 8723 */
|
||||
/* @For 8723 */
|
||||
#define RTL8723E_HWIMG_SUPPORT 0
|
||||
#define RTL8723U_HWIMG_SUPPORT 1
|
||||
#define RTL8723S_HWIMG_SUPPORT 0
|
||||
|
||||
/* For 88E */
|
||||
/* @For 88E */
|
||||
#define RTL8188EE_HWIMG_SUPPORT 0
|
||||
#define RTL8188EU_HWIMG_SUPPORT 0
|
||||
#define RTL8188ES_HWIMG_SUPPORT 0
|
||||
|
||||
#elif (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
|
||||
/* For 92C */
|
||||
/* @For 92C */
|
||||
#define RTL8192CE_HWIMG_SUPPORT 0
|
||||
#define RTL8192CE_TEST_HWIMG_SUPPORT 0
|
||||
#define RTL8192CU_HWIMG_SUPPORT 1
|
||||
#define RTL8192CU_TEST_HWIMG_SUPPORT 0
|
||||
|
||||
/* For 92D */
|
||||
/* @For 92D */
|
||||
#define RTL8192DE_HWIMG_SUPPORT 0
|
||||
#define RTL8192DE_TEST_HWIMG_SUPPORT 0
|
||||
#define RTL8192DU_HWIMG_SUPPORT 1
|
||||
#define RTL8192DU_TEST_HWIMG_SUPPORT 0
|
||||
|
||||
/* For 8723 */
|
||||
/* @For 8723 */
|
||||
#define RTL8723E_HWIMG_SUPPORT 0
|
||||
#define RTL8723U_HWIMG_SUPPORT 0
|
||||
#define RTL8723S_HWIMG_SUPPORT 1
|
||||
|
||||
/* For 88E */
|
||||
/* @For 88E */
|
||||
#define RTL8188EE_HWIMG_SUPPORT 0
|
||||
#define RTL8188EU_HWIMG_SUPPORT 0
|
||||
#define RTL8188ES_HWIMG_SUPPORT 0
|
||||
@@ -93,40 +93,40 @@
|
||||
|
||||
#else /* PLATFORM_WINDOWS & MacOSX */
|
||||
|
||||
/* For 92C */
|
||||
/* @For 92C */
|
||||
#define RTL8192CE_HWIMG_SUPPORT 1
|
||||
#define RTL8192CE_TEST_HWIMG_SUPPORT 1
|
||||
#define RTL8192CU_HWIMG_SUPPORT 1
|
||||
#define RTL8192CU_TEST_HWIMG_SUPPORT 1
|
||||
|
||||
/* For 92D */
|
||||
/* @For 92D */
|
||||
#define RTL8192DE_HWIMG_SUPPORT 1
|
||||
#define RTL8192DE_TEST_HWIMG_SUPPORT 1
|
||||
#define RTL8192DU_HWIMG_SUPPORT 1
|
||||
#define RTL8192DU_TEST_HWIMG_SUPPORT 1
|
||||
|
||||
#if defined(UNDER_CE)
|
||||
/* For 8723 */
|
||||
/* @For 8723 */
|
||||
#define RTL8723E_HWIMG_SUPPORT 0
|
||||
#define RTL8723U_HWIMG_SUPPORT 0
|
||||
#define RTL8723S_HWIMG_SUPPORT 1
|
||||
|
||||
/* For 88E */
|
||||
/* @For 88E */
|
||||
#define RTL8188EE_HWIMG_SUPPORT 0
|
||||
#define RTL8188EU_HWIMG_SUPPORT 0
|
||||
#define RTL8188ES_HWIMG_SUPPORT 0
|
||||
|
||||
#else
|
||||
|
||||
/* For 8723 */
|
||||
/* @For 8723 */
|
||||
#define RTL8723E_HWIMG_SUPPORT 1
|
||||
/* #define RTL_8723E_TEST_HWIMG_SUPPORT 1 */
|
||||
/* @#define RTL_8723E_TEST_HWIMG_SUPPORT 1 */
|
||||
#define RTL8723U_HWIMG_SUPPORT 1
|
||||
/* #define RTL_8723U_TEST_HWIMG_SUPPORT 1 */
|
||||
/* @#define RTL_8723U_TEST_HWIMG_SUPPORT 1 */
|
||||
#define RTL8723S_HWIMG_SUPPORT 1
|
||||
/* #define RTL_8723S_TEST_HWIMG_SUPPORT 1 */
|
||||
/* @#define RTL_8723S_TEST_HWIMG_SUPPORT 1 */
|
||||
|
||||
/* For 88E */
|
||||
/* @For 88E */
|
||||
#define RTL8188EE_HWIMG_SUPPORT 1
|
||||
#define RTL8188EU_HWIMG_SUPPORT 1
|
||||
#define RTL8188ES_HWIMG_SUPPORT 1
|
||||
@@ -134,4 +134,4 @@
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __INC_HW_IMG_H */
|
||||
#endif /* @__INC_HW_IMG_H */
|
||||
|
||||
@@ -74,6 +74,15 @@ void configure_txpower_track(
|
||||
configure_txpower_track_8822b(config);
|
||||
#endif
|
||||
|
||||
#if RTL8192F_SUPPORT
|
||||
if (dm->support_ic_type == ODM_RTL8192F)
|
||||
configure_txpower_track_8192f(config);
|
||||
#endif
|
||||
|
||||
#if RTL8198F_SUPPORT
|
||||
if (dm->support_ic_type == ODM_RTL8198F)
|
||||
configure_txpower_track_8198f(config);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
@@ -95,7 +104,7 @@ odm_txpowertracking_callback_thermal_meter_92e(
|
||||
struct rtl8192cd_priv *priv = dm->priv;
|
||||
|
||||
rf_mimo_mode = dm->rf_type;
|
||||
/* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK,"%s:%d rf_mimo_mode:%d\n", __FUNCTION__, __LINE__, rf_mimo_mode); */
|
||||
/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK,"%s:%d rf_mimo_mode:%d\n", __FUNCTION__, __LINE__, rf_mimo_mode); */
|
||||
|
||||
#ifdef MP_TEST
|
||||
if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
|
||||
@@ -109,7 +118,7 @@ odm_txpowertracking_callback_thermal_meter_92e(
|
||||
}
|
||||
|
||||
thermal_value = (unsigned char)odm_get_rf_reg(dm, RF_PATH_A, ODM_RF_T_METER_92E, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
|
||||
|
||||
|
||||
switch (rf_mimo_mode) {
|
||||
@@ -129,7 +138,7 @@ odm_txpowertracking_callback_thermal_meter_92e(
|
||||
for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) {
|
||||
if (ele_D == (ofdm_swing_table_92e[i] >> 22)) {
|
||||
OFDM_index[0] = (unsigned char)i;
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@@ -140,7 +149,7 @@ odm_txpowertracking_callback_thermal_meter_92e(
|
||||
for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) {
|
||||
if (ele_D == (ofdm_swing_table_92e[i] >> 22)) {
|
||||
OFDM_index[1] = (unsigned char)i;
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@@ -162,7 +171,7 @@ odm_txpowertracking_callback_thermal_meter_92e(
|
||||
|
||||
if (thermal_value_avg_count) {
|
||||
thermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count);
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -174,8 +183,8 @@ odm_txpowertracking_callback_thermal_meter_92e(
|
||||
}
|
||||
|
||||
if (thermal_value != priv->pshare->thermal_value) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n");
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
|
||||
|
||||
delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
|
||||
delta_IQK = RTL_ABS(thermal_value, priv->pshare->thermal_value_iqk);
|
||||
@@ -184,32 +193,32 @@ odm_txpowertracking_callback_thermal_meter_92e(
|
||||
|
||||
#ifdef _TRACKING_TABLE_FILE
|
||||
if (priv->pshare->rf_ft_var.pwr_track_file) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
|
||||
|
||||
if (is_decrease) {
|
||||
for (i = 0; i < rf; i++) {
|
||||
OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0);
|
||||
OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_92E- 1)) ? (OFDM_TABLE_SIZE_92E - 1) : OFDM_index[i]);
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
|
||||
CCK_index = priv->pshare->CCK_index0 + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1);
|
||||
CCK_index = ((CCK_index > (CCK_TABLE_SIZE_92E - 1)) ? (CCK_TABLE_SIZE_92E - 1) : CCK_index);
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1));
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1));
|
||||
}
|
||||
} else {
|
||||
for (i = 0; i < rf; i++) {
|
||||
OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0);
|
||||
OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ? OFDM_min_index : OFDM_index[i]);
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
|
||||
CCK_index = priv->pshare->CCK_index0 - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1);
|
||||
CCK_index = ((CCK_index < 0) ? 0 : CCK_index);
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1));
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1));
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* CFG_TRACKING_TABLE_FILE */
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]);
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]);
|
||||
|
||||
/* Adujst OFDM Ant_A according to IQK result */
|
||||
ele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] & 0xFFC00000) >> 22;
|
||||
@@ -275,8 +284,8 @@ odm_txpowertracking_callback_thermal_meter_92e(
|
||||
|
||||
}
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0xc80 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD));
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0xc88 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD));
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xc80 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD));
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xc88 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD));
|
||||
|
||||
if ((delta_IQK > 3) && (!iqk_info->rfk_forbidden)) {
|
||||
priv->pshare->thermal_value_iqk = thermal_value;
|
||||
@@ -305,37 +314,40 @@ odm_txpowertracking_callback_thermal_meter_92e(
|
||||
priv->pshare->OFDM_index[i] = OFDM_index[i];
|
||||
priv->pshare->CCK_index = CCK_index;
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
|
||||
#if (RTL8197F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\
|
||||
RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter_jaguar_series3(
|
||||
void *dm_void
|
||||
)
|
||||
{
|
||||
#if 1
|
||||
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
||||
u8 thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase;
|
||||
u8 thermal_value_avg_count = 0, p = 0, i = 0;
|
||||
u32 thermal_value_avg = 0;
|
||||
struct rtl8192cd_priv *priv = dm->priv;
|
||||
struct txpwrtrack_cfg c;
|
||||
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
|
||||
struct dm_iqk_info *iqk_info = &dm->IQK_info;
|
||||
/*4 1. The following TWO tables decide the final index of OFDM/CCK swing table.*/
|
||||
u8 *delta_swing_table_idx_tup_a = NULL, *delta_swing_table_idx_tdown_a = NULL;
|
||||
u8 *delta_swing_table_idx_tup_b = NULL, *delta_swing_table_idx_tdown_b = NULL;
|
||||
u8 *delta_swing_table_idx_tup_cck_a = NULL, *delta_swing_table_idx_tdown_cck_a = NULL;
|
||||
u8 *delta_swing_table_idx_tup_cck_b = NULL, *delta_swing_table_idx_tdown_cck_b = NULL;
|
||||
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
||||
u8 thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase;
|
||||
u8 thermal_value_avg_count = 0, p = 0, i = 0;
|
||||
u32 thermal_value_avg = 0;
|
||||
struct rtl8192cd_priv *priv = dm->priv;
|
||||
struct txpwrtrack_cfg c;
|
||||
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
|
||||
struct dm_iqk_info *iqk_info = &dm->IQK_info;
|
||||
struct _hal_rf_ *rf = &dm->rf_table;
|
||||
/*The following tables decide the final index of OFDM/CCK swing table.*/
|
||||
u8 *pwrtrk_tab_up_a = NULL, *pwrtrk_tab_down_a = NULL;
|
||||
u8 *pwrtrk_tab_up_b = NULL, *pwrtrk_tab_down_b = NULL;
|
||||
u8 *pwrtrk_tab_up_cck_a = NULL, *pwrtrk_tab_down_cck_a = NULL;
|
||||
u8 *pwrtrk_tab_up_cck_b = NULL, *pwrtrk_tab_down_cck_b = NULL;
|
||||
/*for 8814 add by Yu Chen*/
|
||||
u8 *delta_swing_table_idx_tup_c = NULL, *delta_swing_table_idx_tdown_c = NULL;
|
||||
u8 *delta_swing_table_idx_tup_d = NULL, *delta_swing_table_idx_tdown_d = NULL;
|
||||
u8 *delta_swing_table_idx_tup_cck_c = NULL, *delta_swing_table_idx_tdown_cck_c = NULL;
|
||||
u8 *delta_swing_table_idx_tup_cck_d = NULL, *delta_swing_table_idx_tdown_cck_d = NULL;
|
||||
u8 *pwrtrk_tab_up_c = NULL, *pwrtrk_tab_down_c = NULL;
|
||||
u8 *pwrtrk_tab_up_d = NULL, *pwrtrk_tab_down_d = NULL;
|
||||
u8 *pwrtrk_tab_up_cck_c = NULL, *pwrtrk_tab_down_cck_c = NULL;
|
||||
u8 *pwrtrk_tab_up_cck_d = NULL, *pwrtrk_tab_down_cck_d = NULL;
|
||||
s8 thermal_value_temp = 0;
|
||||
|
||||
#ifdef MP_TEST
|
||||
if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
|
||||
@@ -350,22 +362,47 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series3(
|
||||
|
||||
configure_txpower_track(dm, &c);
|
||||
|
||||
(*c.get_delta_all_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
|
||||
(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b,
|
||||
(u8 **)&delta_swing_table_idx_tup_cck_a, (u8 **)&delta_swing_table_idx_tdown_cck_a,
|
||||
(u8 **)&delta_swing_table_idx_tup_cck_b, (u8 **)&delta_swing_table_idx_tdown_cck_b);
|
||||
(*c.get_delta_all_swing_table)(dm,
|
||||
(u8 **)&pwrtrk_tab_up_a, (u8 **)&pwrtrk_tab_down_a,
|
||||
(u8 **)&pwrtrk_tab_up_b, (u8 **)&pwrtrk_tab_down_b,
|
||||
(u8 **)&pwrtrk_tab_up_cck_a, (u8 **)&pwrtrk_tab_down_cck_a,
|
||||
(u8 **)&pwrtrk_tab_up_cck_b, (u8 **)&pwrtrk_tab_down_cck_b);
|
||||
|
||||
thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /*0x42: RF Reg[15:10] 88E*/
|
||||
if (GET_CHIP_VER(priv) == VERSION_8198F) {
|
||||
(*c.get_delta_all_swing_table_ex)(dm,
|
||||
(u8 **)&pwrtrk_tab_up_c, (u8 **)&pwrtrk_tab_down_c,
|
||||
(u8 **)&pwrtrk_tab_up_d, (u8 **)&pwrtrk_tab_down_d,
|
||||
(u8 **)&pwrtrk_tab_up_cck_c, (u8 **)&pwrtrk_tab_down_cck_c,
|
||||
(u8 **)&pwrtrk_tab_up_cck_d, (u8 **)&pwrtrk_tab_down_cck_d);
|
||||
}
|
||||
/*0x42: RF Reg[15:10] 88E*/
|
||||
thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);
|
||||
#ifdef THER_TRIM
|
||||
if (GET_CHIP_VER(priv) == VERSION_8197F) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"orig thermal_value=%d, ther_trim_val=%d\n", thermal_value, priv->pshare->rf_ft_var.ther_trim_val);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"orig thermal_value=%d, ther_trim_val=%d\n", thermal_value, priv->pshare->rf_ft_var.ther_trim_val);
|
||||
|
||||
thermal_value += priv->pshare->rf_ft_var.ther_trim_val;
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"after thermal trim, thermal_value=%d\n", thermal_value);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"after thermal trim, thermal_value=%d\n", thermal_value);
|
||||
}
|
||||
|
||||
if (GET_CHIP_VER(priv) == VERSION_8198F) {
|
||||
thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
|
||||
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"thermal_value_temp(%d) = ther_value(%d) + ther_trim_ther(%d)\n",
|
||||
thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));
|
||||
|
||||
if (thermal_value_temp > 63)
|
||||
thermal_value = 63;
|
||||
else if (thermal_value_temp < 0)
|
||||
thermal_value = 0;
|
||||
else
|
||||
thermal_value = thermal_value_temp;
|
||||
}
|
||||
#endif
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"Readback Thermal Meter = 0x%x(%d) EEPROMthermalmeter 0x%x(%d)\n"
|
||||
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\n\n\nCurrent Thermal = 0x%x(%d) EEPROMthermalmeter 0x%x(%d)\n"
|
||||
, thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther);
|
||||
|
||||
/* Initialize */
|
||||
@@ -393,12 +430,12 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series3(
|
||||
}
|
||||
|
||||
if (thermal_value_avg_count) {/*Calculate Average thermal_value after average enough times*/
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"thermal_value_avg=0x%x(%d) thermal_value_avg_count = %d\n"
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"thermal_value_avg=0x%x(%d) thermal_value_avg_count = %d\n"
|
||||
, thermal_value_avg, thermal_value_avg, thermal_value_avg_count);
|
||||
|
||||
thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X(%d), EEPROMthermalmeter = 0x%X(%d)\n", thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X(%d), EEPROMthermalmeter = 0x%X(%d)\n", thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther);
|
||||
}
|
||||
|
||||
/*4 Calculate delta, delta_LCK, delta_IQK.*/
|
||||
@@ -408,136 +445,153 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series3(
|
||||
is_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1);
|
||||
|
||||
if (delta > 29) { /* power track table index(thermal diff.) upper bound*/
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta(%d) > 29, set delta to 29\n", delta);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta(%d) > 29, set delta to 29\n", delta);
|
||||
delta = 29;
|
||||
}
|
||||
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
|
||||
|
||||
/*4 if necessary, do LCK.*/
|
||||
if ((delta_LCK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
|
||||
if ((delta_LCK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
|
||||
dm->rf_calibrate_info.thermal_value_lck = thermal_value;
|
||||
#if (RTL8822B_SUPPORT != 1)
|
||||
if (!(dm->support_ic_type & ODM_RTL8822B)) {
|
||||
if (c.phy_lc_calibrate)
|
||||
(*c.phy_lc_calibrate)(dm);
|
||||
}
|
||||
if (c.phy_lc_calibrate)
|
||||
(*c.phy_lc_calibrate)(dm);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
if ((delta_IQK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
|
||||
dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
|
||||
if (c.do_iqk)
|
||||
(*c.do_iqk)(dm, true, 0, 0);
|
||||
}
|
||||
|
||||
if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/
|
||||
if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/
|
||||
return;
|
||||
|
||||
/*4 Do Power Tracking*/
|
||||
|
||||
if (thermal_value != dm->rf_calibrate_info.thermal_value) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"\n\n******** START POWER TRACKING ********\n");
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n",
|
||||
thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******** START POWER TRACKING ********\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n",
|
||||
thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
|
||||
|
||||
#ifdef _TRACKING_TABLE_FILE
|
||||
if (priv->pshare->rf_ft_var.pwr_track_file) {
|
||||
if (is_increase) { /*thermal is higher than base*/
|
||||
if (is_increase) { /*thermal is higher than base*/
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
switch (p) {
|
||||
case RF_PATH_B:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_b[%d] = %d delta_swing_table_idx_tup_cck_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta], delta, delta_swing_table_idx_tup_cck_b[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta];
|
||||
cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_b[delta];
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_b[%d] = %d pwrtrk_tab_up_cck_b[%d] = %d\n", delta, pwrtrk_tab_up_b[delta], delta, pwrtrk_tab_up_cck_b[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_b[delta];
|
||||
cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_b[delta];
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
|
||||
break;
|
||||
|
||||
case RF_PATH_C:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_c[%d] = %d delta_swing_table_idx_tup_cck_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta], delta, delta_swing_table_idx_tup_cck_c[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta];
|
||||
cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_c[delta];
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_c[%d] = %d pwrtrk_tab_up_cck_c[%d] = %d\n", delta, pwrtrk_tab_up_c[delta], delta, pwrtrk_tab_up_cck_c[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_c[delta];
|
||||
cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_c[delta];
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
|
||||
break;
|
||||
|
||||
case RF_PATH_D:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_d[%d] = %d delta_swing_table_idx_tup_cck_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta], delta, delta_swing_table_idx_tup_cck_d[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta];
|
||||
cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_d[delta];
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_d[%d] = %d pwrtrk_tab_up_cck_d[%d] = %d\n", delta, pwrtrk_tab_up_d[delta], delta, pwrtrk_tab_up_cck_d[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_d[delta];
|
||||
cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_d[delta];
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
|
||||
break;
|
||||
default:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_a[%d] = %d delta_swing_table_idx_tup_cck_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta], delta, delta_swing_table_idx_tup_cck_a[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta];
|
||||
cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_a[delta];
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_a[%d] = %d pwrtrk_tab_up_cck_a[%d] = %d\n", delta, pwrtrk_tab_up_a[delta], delta, pwrtrk_tab_up_cck_a[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_a[delta];
|
||||
cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_a[delta];
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else { /* thermal is lower than base*/
|
||||
} else { /* thermal is lower than base*/
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
switch (p) {
|
||||
case RF_PATH_B:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_b[%d] = %d delta_swing_table_idx_tdown_cck_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta], delta, delta_swing_table_idx_tdown_cck_b[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta];
|
||||
cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_b[delta];
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_b[%d] = %d pwrtrk_tab_down_cck_b[%d] = %d\n", delta, pwrtrk_tab_down_b[delta], delta, pwrtrk_tab_down_cck_b[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_b[delta];
|
||||
cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_b[delta];
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
|
||||
break;
|
||||
|
||||
case RF_PATH_C:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_c[%d] = %d delta_swing_table_idx_tdown_cck_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta], delta, delta_swing_table_idx_tdown_cck_c[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta];
|
||||
cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_c[delta];
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_c[%d] = %d pwrtrk_tab_down_cck_c[%d] = %d\n", delta, pwrtrk_tab_down_c[delta], delta, pwrtrk_tab_down_cck_c[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_c[delta];
|
||||
cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_c[delta];
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
|
||||
break;
|
||||
|
||||
case RF_PATH_D:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_d[%d] = %d delta_swing_table_idx_tdown_cck_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta], delta, delta_swing_table_idx_tdown_cck_d[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta];
|
||||
cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_d[delta];
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_d[%d] = %d pwrtrk_tab_down_cck_d[%d] = %d\n", delta, pwrtrk_tab_down_d[delta], delta, pwrtrk_tab_down_cck_d[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_d[delta];
|
||||
cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_d[delta];
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
|
||||
break;
|
||||
|
||||
default:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_a[%d] = %d delta_swing_table_idx_tdown_cck_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta], delta, delta_swing_table_idx_tdown_cck_a[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta];
|
||||
cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_a[delta];
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_a[%d] = %d pwrtrk_tab_down_cck_a[%d] = %d\n", delta, pwrtrk_tab_down_a[delta], delta, pwrtrk_tab_down_cck_a[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_a[delta];
|
||||
cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_a[delta];
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (is_increase) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> increse power --->\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> increse power --->\n");
|
||||
if (GET_CHIP_VER(priv) == VERSION_8197F) {
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
|
||||
//} else if (GET_CHIP_VER(priv) == VERSION_8192F) {
|
||||
// for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
// (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
|
||||
} else if (GET_CHIP_VER(priv) == VERSION_8822B) {
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
|
||||
} else if (GET_CHIP_VER(priv) == VERSION_8821C) {
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
|
||||
} else if (GET_CHIP_VER(priv) == VERSION_8198F) {
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
|
||||
}
|
||||
} else {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> decrese power --->\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power --->\n");
|
||||
if (GET_CHIP_VER(priv) == VERSION_8197F) {
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
|
||||
//} else if (GET_CHIP_VER(priv) == VERSION_8192F) {
|
||||
// for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
// (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
|
||||
} else if (GET_CHIP_VER(priv) == VERSION_8822B) {
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
|
||||
} else if (GET_CHIP_VER(priv) == VERSION_8821C) {
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
|
||||
} else if (GET_CHIP_VER(priv) == VERSION_8198F) {
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** END:%s() ********\n\n", __func__);
|
||||
if (GET_CHIP_VER(priv) != VERSION_8198F) {
|
||||
if ((delta_IQK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
|
||||
dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
|
||||
if (!(dm->support_ic_type & ODM_RTL8197F)) {
|
||||
if (c.do_iqk)
|
||||
(*c.do_iqk)(dm, false, thermal_value, 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n\n", __func__);
|
||||
/*update thermal meter value*/
|
||||
dm->rf_calibrate_info.thermal_value = thermal_value;
|
||||
|
||||
@@ -597,7 +651,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2(
|
||||
(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
|
||||
|
||||
thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
|
||||
|
||||
/* Initialize */
|
||||
if (!dm->rf_calibrate_info.thermal_value)
|
||||
@@ -614,16 +668,16 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2(
|
||||
/* 4 Query OFDM BB swing default setting Bit[31:21] */
|
||||
for (p = RF_PATH_A ; p < c.rf_path_count ; p++) {
|
||||
ele_D = odm_get_bb_reg(dm, bb_swing_reg[p], 0xffe00000);
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[p], odm_get_bb_reg(dm, bb_swing_reg[p], MASKDWORD), ele_D);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[p], odm_get_bb_reg(dm, bb_swing_reg[p], MASKDWORD), ele_D);
|
||||
|
||||
for (bb_swing_idx = 0; bb_swing_idx < TXSCALE_TABLE_SIZE; bb_swing_idx++) {/* 4 */
|
||||
if (ele_D == tx_scaling_table_jaguar[bb_swing_idx]) {
|
||||
dm->rf_calibrate_info.OFDM_index[p] = (u8)bb_swing_idx;
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"OFDM_index[%d]=%d\n", p, dm->rf_calibrate_info.OFDM_index[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"OFDM_index[%d]=%d\n", p, dm->rf_calibrate_info.OFDM_index[p]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "kfree_offset[%d]=%d\n", p, cali_info->kfree_offset[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "kfree_offset[%d]=%d\n", p, cali_info->kfree_offset[p]);
|
||||
|
||||
}
|
||||
|
||||
@@ -642,7 +696,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2(
|
||||
|
||||
if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */
|
||||
thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\n", thermal_value, priv->pmib->dot11RFEntry.ther);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\n", thermal_value, priv->pmib->dot11RFEntry.ther);
|
||||
}
|
||||
|
||||
/* 4 Calculate delta, delta_LCK, delta_IQK. */
|
||||
@@ -654,7 +708,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2(
|
||||
/* 4 if necessary, do LCK. */
|
||||
if (!(dm->support_ic_type & ODM_RTL8821)) {
|
||||
if ((delta_LCK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
|
||||
dm->rf_calibrate_info.thermal_value_lck = thermal_value;
|
||||
|
||||
/*Use RTLCK, so close power tracking driver LCK*/
|
||||
@@ -669,7 +723,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2(
|
||||
|
||||
if ((delta_IQK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
|
||||
panic_printk("%s(%d)\n", __FUNCTION__, __LINE__);
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
|
||||
dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
|
||||
if (c.do_iqk)
|
||||
(*c.do_iqk)(dm, true, 0, 0);
|
||||
@@ -681,12 +735,12 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2(
|
||||
/* 4 Do Power Tracking */
|
||||
|
||||
if (is_tssi_enable == true) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter PURE TSSI MODE**********\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter PURE TSSI MODE**********\n");
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0);
|
||||
} else if (thermal_value != dm->rf_calibrate_info.thermal_value) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"\n******** START POWER TRACKING ********\n");
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\n******** START POWER TRACKING ********\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
|
||||
|
||||
#ifdef _TRACKING_TABLE_FILE
|
||||
if (priv->pshare->rf_ft_var.pwr_track_file) {
|
||||
@@ -694,27 +748,27 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2(
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
switch (p) {
|
||||
case RF_PATH_B:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /* Record delta swing for mix mode power tracking */
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
|
||||
case RF_PATH_C:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /* Record delta swing for mix mode power tracking */
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
|
||||
case RF_PATH_D:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /* Record delta swing for mix mode power tracking */
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
|
||||
default:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /* Record delta swing for mix mode power tracking */
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@@ -722,45 +776,45 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series2(
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
switch (p) {
|
||||
case RF_PATH_B:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /* Record delta swing for mix mode power tracking */
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
|
||||
case RF_PATH_C:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /* Record delta swing for mix mode power tracking */
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
|
||||
case RF_PATH_D:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /* Record delta swing for mix mode power tracking */
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
|
||||
default:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
|
||||
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /* Record delta swing for mix mode power tracking */
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (is_increase) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> increse power --->\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> increse power --->\n");
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
|
||||
} else {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> decrese power --->\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power --->\n");
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
|
||||
/* update thermal meter value */
|
||||
dm->rf_calibrate_info.thermal_value = thermal_value;
|
||||
|
||||
@@ -811,17 +865,17 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series(
|
||||
|
||||
|
||||
thermal_value = (unsigned char)phy_query_rf_reg(priv, RF_PATH_A, 0x42, 0xfc00, 1); /* 0x42: RF Reg[15:10] 88E */
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
|
||||
|
||||
|
||||
/* 4 Query OFDM BB swing default setting Bit[31:21] */
|
||||
for (rf_path = 0 ; rf_path < max_rf_path ; rf_path++) {
|
||||
ele_D = phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000);
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], MASKDWORD), ele_D);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], MASKDWORD), ele_D);
|
||||
for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */
|
||||
if (ele_D == ofdm_swing_table_8812[i]) {
|
||||
OFDM_index[rf_path] = (unsigned char)i;
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "OFDM_index[%d]=%d\n", rf_path, OFDM_index[rf_path]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "OFDM_index[%d]=%d\n", rf_path, OFDM_index[rf_path]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@@ -829,22 +883,22 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series(
|
||||
#if 0
|
||||
/* Query OFDM path A default setting Bit[31:21] */
|
||||
ele_D = phy_query_bb_reg(priv, 0xc1c, 0xffe00000);
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0xc1c:0x%x ([31:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xc1c, MASKDWORD), ele_D);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xc1c:0x%x ([31:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xc1c, MASKDWORD), ele_D);
|
||||
for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */
|
||||
if (ele_D == ofdm_swing_table_8812[i]) {
|
||||
OFDM_index[0] = (unsigned char)i;
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "OFDM_index[0]=%d\n", OFDM_index[0]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "OFDM_index[0]=%d\n", OFDM_index[0]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* Query OFDM path B default setting */
|
||||
if (rf == 2) {
|
||||
ele_D = phy_query_bb_reg(priv, 0xe1c, 0xffe00000);
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0xe1c:0x%x ([32:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xe1c, MASKDWORD), ele_D);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xe1c:0x%x ([32:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xe1c, MASKDWORD), ele_D);
|
||||
for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {
|
||||
if (ele_D == ofdm_swing_table_8812[i]) {
|
||||
OFDM_index[1] = (unsigned char)i;
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "OFDM_index[1]=%d\n", OFDM_index[1]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "OFDM_index[1]=%d\n", OFDM_index[1]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@@ -883,8 +937,8 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series(
|
||||
return;
|
||||
|
||||
if (thermal_value != priv->pshare->thermal_value) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n");
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
|
||||
delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
|
||||
delta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck);
|
||||
is_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0);
|
||||
@@ -893,11 +947,11 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series(
|
||||
#ifdef _TRACKING_TABLE_FILE
|
||||
if (priv->pshare->rf_ft_var.pwr_track_file) {
|
||||
for (rf_path = 0; rf_path < max_rf_path; rf_path++) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
|
||||
if (is_decrease) {
|
||||
OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] + get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0);
|
||||
OFDM_index[rf_path] = ((OFDM_index[rf_path] > (OFDM_TABLE_SIZE_8812 - 1)) ? (OFDM_TABLE_SIZE_8812 - 1) : OFDM_index[rf_path]);
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
|
||||
#if 0/* RTL8881A_SUPPORT */
|
||||
if (dm->support_ic_type == ODM_RTL8881A) {
|
||||
if (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) {
|
||||
@@ -932,7 +986,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series(
|
||||
#else
|
||||
OFDM_index[rf_path] = ((OFDM_index[rf_path] < OFDM_min_index) ? OFDM_min_index : OFDM_index[rf_path]);
|
||||
#endif
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -940,7 +994,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series(
|
||||
/* 4 Set new BB swing index */
|
||||
for (rf_path = 0; rf_path < max_rf_path; rf_path++) {
|
||||
phy_set_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000, ofdm_swing_table_8812[(unsigned int)OFDM_index[rf_path]]);
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000), OFDM_index[rf_path]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000), OFDM_index[rf_path]);
|
||||
}
|
||||
|
||||
}
|
||||
@@ -959,7 +1013,7 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series(
|
||||
RTL_W8(0x522, 0x0);
|
||||
priv->pshare->thermal_value_lck = thermal_value;
|
||||
}
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
|
||||
|
||||
/* update thermal meter value */
|
||||
priv->pshare->thermal_value = thermal_value;
|
||||
@@ -980,9 +1034,9 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
|
||||
struct dm_iqk_info *iqk_info = &dm->IQK_info;
|
||||
|
||||
#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
|
||||
if (dm->support_ic_type == ODM_RTL8197F || dm->support_ic_type == ODM_RTL8822B
|
||||
|| dm->support_ic_type == ODM_RTL8821C) {
|
||||
#if (RTL8197F_SUPPORT == 1 ||RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
|
||||
if (dm->support_ic_type == ODM_RTL8197F || dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8822B
|
||||
|| dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8198F) {
|
||||
odm_txpowertracking_callback_thermal_meter_jaguar_series3(dm);
|
||||
return;
|
||||
}
|
||||
@@ -1064,7 +1118,7 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "===>odm_txpowertracking_callback_thermal_meter_8188e, dm->bb_swing_idx_cck_base: %d, dm->bb_swing_idx_ofdm_base: %d\n", cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "===>odm_txpowertracking_callback_thermal_meter_8188e, dm->bb_swing_idx_cck_base: %d, dm->bb_swing_idx_ofdm_base: %d\n", cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base);
|
||||
/*
|
||||
if (!dm->rf_calibrate_info.tm_trigger) {
|
||||
odm_set_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, BIT(17) | BIT(16), 0x3);
|
||||
@@ -1088,7 +1142,7 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
}
|
||||
|
||||
if (dm->rf_calibrate_info.is_reloadtxpowerindex)
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "reload ofdm index for band switch\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "reload ofdm index for band switch\n");
|
||||
|
||||
/* 4 4. Calculate average thermal meter */
|
||||
|
||||
@@ -1110,7 +1164,7 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
|
||||
thermal_value = (u8)(thermal_value_avg / (thermal_value_avg_count + 4));
|
||||
cali_info->thermal_value_delta = thermal_value - priv->pmib->dot11RFEntry.ther;
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value);
|
||||
}
|
||||
|
||||
/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
|
||||
@@ -1161,8 +1215,8 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
cali_info->bb_swing_idx_cck = dm->rf_calibrate_info.CCK_index;
|
||||
cali_info->bb_swing_idx_ofdm[RF_PATH_A] = dm->rf_calibrate_info.OFDM_index[RF_PATH_A];
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, dm->rf_calibrate_info.power_index_offset);
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "The 'OFDM' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base, dm->rf_calibrate_info.power_index_offset);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, dm->rf_calibrate_info.power_index_offset);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "The 'OFDM' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base, dm->rf_calibrate_info.power_index_offset);
|
||||
|
||||
/* 4 7.1 Handle boundary conditions of index. */
|
||||
|
||||
@@ -1179,12 +1233,12 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
else if (dm->rf_calibrate_info.CCK_index < 0)
|
||||
dm->rf_calibrate_info.CCK_index = 0;
|
||||
} else {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"The thermal meter is unchanged or TxPowerTracking OFF: thermal_value: %d, dm->rf_calibrate_info.thermal_value: %d)\n", thermal_value, dm->rf_calibrate_info.thermal_value);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"The thermal meter is unchanged or TxPowerTracking OFF: thermal_value: %d, dm->rf_calibrate_info.thermal_value: %d)\n", thermal_value, dm->rf_calibrate_info.thermal_value);
|
||||
dm->rf_calibrate_info.power_index_offset = 0;
|
||||
}
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.CCK_index, cali_info->bb_swing_idx_cck_base);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.CCK_index, cali_info->bb_swing_idx_cck_base);
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.OFDM_index[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.OFDM_index[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base);
|
||||
|
||||
if (dm->rf_calibrate_info.power_index_offset != 0 && dm->rf_calibrate_info.txpowertrack_control) {
|
||||
/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
|
||||
@@ -1196,20 +1250,20 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
/* */
|
||||
/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
|
||||
if (thermal_value > dm->rf_calibrate_info.thermal_value) {
|
||||
/* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK, */
|
||||
/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK, */
|
||||
/* "Temperature Increasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */
|
||||
/* dm->rf_calibrate_info.power_index_offset, delta, thermal_value, hal_data->eeprom_thermal_meter, dm->rf_calibrate_info.thermal_value); */
|
||||
} else if (thermal_value < dm->rf_calibrate_info.thermal_value) { /* Low temperature */
|
||||
/* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK, */
|
||||
/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK, */
|
||||
/* "Temperature Decreasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */
|
||||
/* dm->rf_calibrate_info.power_index_offset, delta, thermal_value, hal_data->eeprom_thermal_meter, dm->rf_calibrate_info.thermal_value); */
|
||||
}
|
||||
if (thermal_value > dm->priv->pmib->dot11RFEntry.ther)
|
||||
{
|
||||
/* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK,"Temperature(%d) hugher than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */
|
||||
/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK,"Temperature(%d) hugher than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, TXAGC, 0, 0);
|
||||
} else {
|
||||
/* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK,"Temperature(%d) lower than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */
|
||||
/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK,"Temperature(%d) lower than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, RF_PATH_A, indexforchannel);
|
||||
if (is2T)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, RF_PATH_B, indexforchannel);
|
||||
@@ -1221,7 +1275,7 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
|
||||
}
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n");
|
||||
|
||||
dm->rf_calibrate_info.tx_powercount = 0;
|
||||
}
|
||||
|
||||
@@ -13,8 +13,8 @@
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __HAL_PHY_RF_H__
|
||||
#define __HAL_PHY_RF_H__
|
||||
#ifndef __HALPHYRF_H__
|
||||
#define __HALPHYRF_H__
|
||||
|
||||
#include "halrf/halrf_powertracking_ap.h"
|
||||
#include "halrf/halrf_kfree.h"
|
||||
@@ -31,6 +31,22 @@
|
||||
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8195B_SUPPORT == 1)
|
||||
// #include "halrf/rtl8195b/halrf.h"
|
||||
#include "halrf/rtl8195b/halrf_iqk_8195b.h"
|
||||
#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
|
||||
#include "halrf/rtl8195b/halrf_dpk_8195b.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8198F_SUPPORT == 1)
|
||||
#include "halrf/rtl8198f/halrf_iqk_8198f.h"
|
||||
#include "halrf/rtl8198f/halrf_dpk_8198f.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8814B_SUPPORT == 1)
|
||||
#include "halrf/rtl8814b/halrf_iqk_8814b.h"
|
||||
#endif
|
||||
|
||||
enum pwrtrack_method {
|
||||
BBSWING,
|
||||
TXAGC,
|
||||
@@ -45,7 +61,7 @@ typedef void (*func_lck)(void *);
|
||||
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
|
||||
typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
|
||||
typedef void (*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
|
||||
|
||||
typedef void (*func_all_swing_ex)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
|
||||
|
||||
struct txpwrtrack_cfg {
|
||||
u8 swing_table_size_cck;
|
||||
@@ -60,7 +76,8 @@ struct txpwrtrack_cfg {
|
||||
func_lck phy_lc_calibrate;
|
||||
func_swing get_delta_swing_table;
|
||||
func_swing8814only get_delta_swing_table8814only;
|
||||
func_all_swing get_delta_all_swing_table;
|
||||
func_all_swing get_delta_all_swing_table;
|
||||
func_all_swing_ex get_delta_all_swing_table_ex;
|
||||
};
|
||||
|
||||
void
|
||||
@@ -119,4 +136,4 @@ odm_get_right_chnl_place_for_iqk(
|
||||
void phydm_rf_init(void *dm_void);
|
||||
void phydm_rf_watchdog(void *dm_void);
|
||||
|
||||
#endif /* #ifndef __HAL_PHY_RF_H__ */
|
||||
#endif /*#ifndef __HALPHYRF_H__*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -23,25 +23,35 @@
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __HAL_PHY_RF_H__
|
||||
#define __HAL_PHY_RF_H__
|
||||
#ifndef __HALPHYRF_H__
|
||||
#define __HALPHYRF_H__
|
||||
|
||||
#include "halrf/halrf_kfree.h"
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
#include "halrf/rtl8814a/halrf_iqk_8814a.h"
|
||||
#include "halrf/rtl8814a/halrf_iqk_8814a.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#include "halrf/rtl8822b/halrf_iqk_8822b.h"
|
||||
#include "halrf/rtl8822b/halrf_iqk_8822b.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8821C_SUPPORT == 1)
|
||||
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
|
||||
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8195B_SUPPORT == 1)
|
||||
/* #include "halrf/rtl8195b/halrf.h" */
|
||||
#include "halrf/rtl8195b/halrf_iqk_8195b.h"
|
||||
#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
|
||||
#include "halrf/rtl8195b/halrf_dpk_8195b.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8814B_SUPPORT == 1)
|
||||
#include "halrf/rtl8814b/halrf_iqk_8814b.h"
|
||||
#endif
|
||||
|
||||
#include "halrf/halrf_powertracking_ce.h"
|
||||
|
||||
|
||||
enum spur_cal_method {
|
||||
PLL_RESET,
|
||||
AFE_PHASE_SEL
|
||||
@@ -56,69 +66,49 @@ enum pwrtrack_method {
|
||||
MIX_5G_TSSI_2G_MODE
|
||||
};
|
||||
|
||||
typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
|
||||
typedef void(*func_iqk)(void *, u8, u8, u8);
|
||||
typedef void (*func_lck)(void *);
|
||||
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
|
||||
typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
|
||||
typedef void(*func_swing_xtal)(void *, s8 **, s8 **);
|
||||
typedef void(*func_set_xtal)(void *);
|
||||
typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
|
||||
typedef void (*func_iqk)(void *, u8, u8, u8);
|
||||
typedef void (*func_lck)(void *);
|
||||
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
|
||||
typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
|
||||
typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
|
||||
typedef void (*func_set_xtal)(void *);
|
||||
|
||||
struct txpwrtrack_cfg {
|
||||
u8 swing_table_size_cck;
|
||||
u8 swing_table_size_ofdm;
|
||||
u8 threshold_iqk;
|
||||
u8 threshold_dpk;
|
||||
u8 average_thermal_num;
|
||||
u8 rf_path_count;
|
||||
u32 thermal_reg_addr;
|
||||
func_set_pwr odm_tx_pwr_track_set_pwr;
|
||||
func_iqk do_iqk;
|
||||
func_lck phy_lc_calibrate;
|
||||
func_swing get_delta_swing_table;
|
||||
func_swing8814only get_delta_swing_table8814only;
|
||||
func_swing_xtal get_delta_swing_xtal_table;
|
||||
func_set_xtal odm_txxtaltrack_set_xtal;
|
||||
u8 swing_table_size_cck;
|
||||
u8 swing_table_size_ofdm;
|
||||
u8 threshold_iqk;
|
||||
u8 threshold_dpk;
|
||||
u8 average_thermal_num;
|
||||
u8 rf_path_count;
|
||||
u32 thermal_reg_addr;
|
||||
func_set_pwr odm_tx_pwr_track_set_pwr;
|
||||
func_iqk do_iqk;
|
||||
func_lck phy_lc_calibrate;
|
||||
func_swing get_delta_swing_table;
|
||||
func_swing8814only get_delta_swing_table8814only;
|
||||
func_swing_xtal get_delta_swing_xtal_table;
|
||||
func_set_xtal odm_txxtaltrack_set_xtal;
|
||||
};
|
||||
|
||||
void
|
||||
configure_txpower_track(
|
||||
void *dm_void,
|
||||
struct txpwrtrack_cfg *config
|
||||
);
|
||||
void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config);
|
||||
|
||||
void odm_clear_txpowertracking_state(void *dm_void);
|
||||
|
||||
void
|
||||
odm_clear_txpowertracking_state(
|
||||
void *dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
void *dm_void
|
||||
void odm_txpowertracking_callback_thermal_meter(void *dm_void);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
void *dm
|
||||
void odm_txpowertracking_callback_thermal_meter(void *dm);
|
||||
#else
|
||||
void *adapter
|
||||
void odm_txpowertracking_callback_thermal_meter(void *adapter);
|
||||
#endif
|
||||
);
|
||||
|
||||
#define ODM_TARGET_CHNL_NUM_2G_5G 59
|
||||
|
||||
void odm_reset_iqk_result(void *dm_void);
|
||||
u8 odm_get_right_chnl_place_for_iqk(u8 chnl);
|
||||
|
||||
#define ODM_TARGET_CHNL_NUM_2G_5G 59
|
||||
void phydm_rf_init(void *dm_void);
|
||||
void phydm_rf_watchdog(void *dm_void);
|
||||
|
||||
|
||||
void
|
||||
odm_reset_iqk_result(
|
||||
void *dm_void
|
||||
);
|
||||
u8
|
||||
odm_get_right_chnl_place_for_iqk(
|
||||
u8 chnl
|
||||
);
|
||||
|
||||
void phydm_rf_init(void *dm_void);
|
||||
void phydm_rf_watchdog(void *dm_void);
|
||||
|
||||
#endif /* #ifndef __HAL_PHY_RF_H__ */
|
||||
#endif /*__HALPHYRF_H__*/
|
||||
|
||||
528
hal/phydm/halrf/halphyrf_iot.c
Normal file
528
hal/phydm/halrf/halphyrf_iot.c
Normal file
@@ -0,0 +1,528 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
|
||||
do {\
|
||||
for (_offset = 0; _offset < _size; _offset++) { \
|
||||
if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
|
||||
if (_offset != 0)\
|
||||
_offset--;\
|
||||
break;\
|
||||
} \
|
||||
} \
|
||||
if (_offset >= _size)\
|
||||
_offset = _size-1;\
|
||||
} while (0)
|
||||
|
||||
void configure_txpower_track(
|
||||
void *dm_void,
|
||||
struct txpwrtrack_cfg *config
|
||||
)
|
||||
{
|
||||
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
||||
#if RTL8195B_SUPPORT
|
||||
if (dm->support_ic_type == ODM_RTL8195B)
|
||||
configure_txpower_track_8195b(config);
|
||||
#endif
|
||||
|
||||
#if RTL8721D_SUPPORT
|
||||
if (dm->support_ic_type == ODM_RTL8721D)
|
||||
configure_txpower_track_8721d(config);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/* **********************************************************************
|
||||
* <20121113, Kordan> This function should be called when tx_agc changed.
|
||||
* Otherwise the previous compensation is gone, because we record the
|
||||
* delta of temperature between two TxPowerTracking watch dogs.
|
||||
*
|
||||
* NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
|
||||
* need to call this function.
|
||||
* ********************************************************************** */
|
||||
void
|
||||
odm_clear_txpowertracking_state(
|
||||
void *dm_void
|
||||
)
|
||||
{
|
||||
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
||||
struct _hal_rf_ *rf = &dm->rf_table;
|
||||
u8 p = 0;
|
||||
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
|
||||
|
||||
cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
|
||||
cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
|
||||
dm->rf_calibrate_info.CCK_index = 0;
|
||||
|
||||
for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
|
||||
cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
|
||||
cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
|
||||
cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
|
||||
|
||||
cali_info->power_index_offset[p] = 0;
|
||||
cali_info->delta_power_index[p] = 0;
|
||||
cali_info->delta_power_index_last[p] = 0;
|
||||
|
||||
cali_info->absolute_ofdm_swing_idx[p] = 0;
|
||||
cali_info->remnant_ofdm_swing_idx[p] = 0;
|
||||
cali_info->kfree_offset[p] = 0;
|
||||
}
|
||||
|
||||
cali_info->modify_tx_agc_flag_path_a = false;
|
||||
cali_info->modify_tx_agc_flag_path_b = false;
|
||||
cali_info->modify_tx_agc_flag_path_c = false;
|
||||
cali_info->modify_tx_agc_flag_path_d = false;
|
||||
cali_info->remnant_cck_swing_idx = 0;
|
||||
cali_info->thermal_value = rf->eeprom_thermal;
|
||||
cali_info->modify_tx_agc_value_cck = 0;
|
||||
cali_info->modify_tx_agc_value_ofdm = 0;
|
||||
}
|
||||
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter(
|
||||
void *dm_void
|
||||
)
|
||||
{
|
||||
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
||||
struct _hal_rf_ *rf = &dm->rf_table;
|
||||
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
|
||||
struct dm_iqk_info *iqk_info = &dm->IQK_info;
|
||||
|
||||
u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
|
||||
u8 thermal_value_avg_count = 0;
|
||||
u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
|
||||
|
||||
u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
|
||||
u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */
|
||||
u8 power_tracking_type = rf->pwt_type;
|
||||
u8 xtal_offset_eanble = 0;
|
||||
s8 thermal_value_temp = 0;
|
||||
|
||||
struct txpwrtrack_cfg c = {0};
|
||||
|
||||
/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
|
||||
u8 *delta_swing_table_idx_tup_a = NULL;
|
||||
u8 *delta_swing_table_idx_tdown_a = NULL;
|
||||
u8 *delta_swing_table_idx_tup_b = NULL;
|
||||
u8 *delta_swing_table_idx_tdown_b = NULL;
|
||||
/*for Xtal Offset by James.Tung*/
|
||||
s8 *delta_swing_table_xtal_up = NULL;
|
||||
s8 *delta_swing_table_xtal_down = NULL;
|
||||
|
||||
/* 4 2. Initialization ( 7 steps in total ) */
|
||||
|
||||
configure_txpower_track(dm, &c);
|
||||
|
||||
(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
|
||||
(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
|
||||
|
||||
/*for Xtal Offset*/
|
||||
if (dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8721D))
|
||||
(*c.get_delta_swing_xtal_table)(dm,
|
||||
(s8 **)&delta_swing_table_xtal_up,
|
||||
(s8 **)&delta_swing_table_xtal_down);
|
||||
|
||||
cali_info->txpowertracking_callback_cnt++; /*cosa add for debug*/
|
||||
cali_info->is_txpowertracking_init = true;
|
||||
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
|
||||
cali_info->bb_swing_idx_cck_base,
|
||||
cali_info->bb_swing_idx_ofdm_base[RF_PATH_A],
|
||||
cali_info->default_ofdm_index);
|
||||
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"cali_info->txpowertrack_control = %d, hal_data->eeprom_thermal_meter %d\n",
|
||||
cali_info->txpowertrack_control, rf->eeprom_thermal);
|
||||
|
||||
if (dm->support_ic_type == ODM_RTL8721D)
|
||||
thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A,
|
||||
c.thermal_reg_addr, 0x7e0);
|
||||
/* 0x42: RF Reg[10:5] 8721D */
|
||||
else
|
||||
thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A,
|
||||
c.thermal_reg_addr, 0xfc00);
|
||||
/* 0x42: RF Reg[15:10] 88E */
|
||||
|
||||
thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
|
||||
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"thermal_value_temp(%d) = thermal_value(%d) + power_trim_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));
|
||||
|
||||
if (thermal_value_temp > 63)
|
||||
thermal_value = 63;
|
||||
else if (thermal_value_temp < 0)
|
||||
thermal_value = 0;
|
||||
else
|
||||
thermal_value = thermal_value_temp;
|
||||
|
||||
if (!cali_info->txpowertrack_control)
|
||||
return;
|
||||
|
||||
if (rf->eeprom_thermal == 0xff) {
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", rf->eeprom_thermal);
|
||||
return;
|
||||
}
|
||||
#if 0
|
||||
/*4 3. Initialize ThermalValues of rf_calibrate_info*/
|
||||
//if (cali_info->is_reloadtxpowerindex)
|
||||
// RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "reload ofdm index for band switch\n");
|
||||
#endif
|
||||
/*4 4. Calculate average thermal meter*/
|
||||
|
||||
cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] = thermal_value;
|
||||
cali_info->thermal_value_avg_index++;
|
||||
if (cali_info->thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/
|
||||
cali_info->thermal_value_avg_index = 0;
|
||||
|
||||
for (i = 0; i < c.average_thermal_num; i++) {
|
||||
if (cali_info->thermal_value_avg[i]) {
|
||||
thermal_value_avg += cali_info->thermal_value_avg[i];
|
||||
thermal_value_avg_count++;
|
||||
}
|
||||
}
|
||||
|
||||
if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */
|
||||
thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
|
||||
cali_info->thermal_value_delta = thermal_value - rf->eeprom_thermal;
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, rf->eeprom_thermal);
|
||||
}
|
||||
|
||||
/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
|
||||
/* "delta" here is used to determine whether thermal value changes or not. */
|
||||
delta = (thermal_value > cali_info->thermal_value) ? (thermal_value - cali_info->thermal_value) : (cali_info->thermal_value - thermal_value);
|
||||
delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
|
||||
delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
|
||||
|
||||
/*4 6. If necessary, do LCK.*/
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
|
||||
|
||||
/* Wait sacn to do LCK by RF Jenyu*/
|
||||
if ((!*dm->is_scan_in_process) && !iqk_info->rfk_forbidden &&
|
||||
(!*dm->is_tdma)) {
|
||||
/* Delta temperature is equal to or larger than 20 centigrade.*/
|
||||
if (delta_LCK >= c.threshold_iqk) {
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
|
||||
cali_info->thermal_value_lck = thermal_value;
|
||||
|
||||
/*Use RTLCK, so close power tracking driver LCK*/
|
||||
(*c.phy_lc_calibrate)(dm);
|
||||
}
|
||||
}
|
||||
|
||||
/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
|
||||
if (delta > 0 && cali_info->txpowertrack_control) {
|
||||
/* "delta" here is used to record the absolute value of difference. */
|
||||
delta = thermal_value > rf->eeprom_thermal ? (thermal_value - rf->eeprom_thermal) : (rf->eeprom_thermal - thermal_value);
|
||||
|
||||
if (delta >= TXPWR_TRACK_TABLE_SIZE)
|
||||
delta = TXPWR_TRACK_TABLE_SIZE - 1;
|
||||
|
||||
/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
|
||||
if (thermal_value > rf->eeprom_thermal) {
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
|
||||
switch (p) {
|
||||
case RF_PATH_B:
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
|
||||
|
||||
cali_info->delta_power_index[p] =
|
||||
delta_swing_table_idx_tup_b
|
||||
[delta];
|
||||
cali_info->absolute_ofdm_swing_idx[p] =
|
||||
delta_swing_table_idx_tup_b
|
||||
[delta];
|
||||
/*Record delta swing for mix mode*/
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
|
||||
default:
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
|
||||
|
||||
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
|
||||
cali_info->absolute_ofdm_swing_idx[p] =
|
||||
delta_swing_table_idx_tup_a[delta];
|
||||
/*Record delta swing*/
|
||||
/*for mix mode power tracking*/
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* JJ ADD 20161014 */
|
||||
if (dm->support_ic_type &
|
||||
(ODM_RTL8195B | ODM_RTL8721D)) {
|
||||
/*Save xtal_offset from Xtal table*/
|
||||
cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]);
|
||||
cali_info->xtal_offset = delta_swing_table_xtal_up[delta];
|
||||
xtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset);
|
||||
}
|
||||
|
||||
} else {
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
|
||||
|
||||
switch (p) {
|
||||
case RF_PATH_B:
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
|
||||
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
|
||||
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
|
||||
default:
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
|
||||
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
|
||||
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* JJ ADD 20161014 */
|
||||
|
||||
if (dm->support_ic_type &
|
||||
(ODM_RTL8195B | ODM_RTL8721D)) {
|
||||
/*Save xtal_offset from Xtal table*/
|
||||
cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]);
|
||||
cali_info->xtal_offset = delta_swing_table_xtal_down[delta];
|
||||
xtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset);
|
||||
}
|
||||
}
|
||||
#if 0
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p);
|
||||
|
||||
if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/
|
||||
cali_info->power_index_offset[p] = 0;
|
||||
else
|
||||
cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/
|
||||
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]);
|
||||
|
||||
cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];
|
||||
cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p];
|
||||
|
||||
cali_info->bb_swing_idx_cck = cali_info->CCK_index;
|
||||
cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p];
|
||||
|
||||
/*************Print BB Swing base and index Offset*************/
|
||||
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]);
|
||||
|
||||
/*4 7.1 Handle boundary conditions of index.*/
|
||||
|
||||
if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
|
||||
cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
|
||||
else if (cali_info->OFDM_index[p] <= OFDM_min_index)
|
||||
cali_info->OFDM_index[p] = OFDM_min_index;
|
||||
}
|
||||
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"\n\n========================================================================================================\n");
|
||||
|
||||
if (cali_info->CCK_index > c.swing_table_size_cck - 1)
|
||||
cali_info->CCK_index = c.swing_table_size_cck - 1;
|
||||
else if (cali_info->CCK_index <= 0)
|
||||
cali_info->CCK_index = 0;
|
||||
#endif
|
||||
} else {
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n",
|
||||
cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value);
|
||||
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
cali_info->power_index_offset[p] = 0;
|
||||
}
|
||||
#if 0
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
|
||||
cali_info->CCK_index, cali_info->bb_swing_idx_cck_base); /*Print Swing base & current*/
|
||||
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
|
||||
cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]);
|
||||
}
|
||||
#endif
|
||||
if (thermal_value > rf->eeprom_thermal) {
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"Temperature(%d) higher than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
|
||||
|
||||
if (dm->support_ic_type == ODM_RTL8188E ||
|
||||
dm->support_ic_type == ODM_RTL8192E ||
|
||||
dm->support_ic_type == ODM_RTL8821 ||
|
||||
dm->support_ic_type == ODM_RTL8812 ||
|
||||
dm->support_ic_type == ODM_RTL8723B ||
|
||||
dm->support_ic_type == ODM_RTL8814A ||
|
||||
dm->support_ic_type == ODM_RTL8703B ||
|
||||
dm->support_ic_type == ODM_RTL8188F ||
|
||||
dm->support_ic_type == ODM_RTL8822B ||
|
||||
dm->support_ic_type == ODM_RTL8723D ||
|
||||
dm->support_ic_type == ODM_RTL8821C ||
|
||||
dm->support_ic_type == ODM_RTL8710B ||
|
||||
dm->support_ic_type == ODM_RTL8192F ||
|
||||
dm->support_ic_type == ODM_RTL8195B ||
|
||||
dm->support_ic_type == ODM_RTL8721D){
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
|
||||
} else {
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
|
||||
}
|
||||
} else {
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"Temperature(%d) lower than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
|
||||
|
||||
if (dm->support_ic_type == ODM_RTL8188E ||
|
||||
dm->support_ic_type == ODM_RTL8192E ||
|
||||
dm->support_ic_type == ODM_RTL8821 ||
|
||||
dm->support_ic_type == ODM_RTL8812 ||
|
||||
dm->support_ic_type == ODM_RTL8723B ||
|
||||
dm->support_ic_type == ODM_RTL8814A ||
|
||||
dm->support_ic_type == ODM_RTL8703B ||
|
||||
dm->support_ic_type == ODM_RTL8188F ||
|
||||
dm->support_ic_type == ODM_RTL8822B ||
|
||||
dm->support_ic_type == ODM_RTL8723D ||
|
||||
dm->support_ic_type == ODM_RTL8821C ||
|
||||
dm->support_ic_type == ODM_RTL8710B ||
|
||||
dm->support_ic_type == ODM_RTL8192F ||
|
||||
dm->support_ic_type == ODM_RTL8195B ||
|
||||
dm->support_ic_type == ODM_RTL8721D) {
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel);
|
||||
} else {
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
|
||||
}
|
||||
|
||||
cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];
|
||||
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"cali_info->thermal_value = %d thermal_value= %d\n", cali_info->thermal_value, thermal_value);
|
||||
|
||||
cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
|
||||
}
|
||||
|
||||
/* JJ ADD 20161014 */
|
||||
if (dm->support_ic_type == (ODM_RTL8195B | ODM_RTL8721D)) {
|
||||
if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (rf->eeprom_thermal != 0xff)) {
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
|
||||
|
||||
if (thermal_value > rf->eeprom_thermal) {
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"Temperature(%d) higher than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
|
||||
(*c.odm_txxtaltrack_set_xtal)(dm);
|
||||
} else {
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"Temperature(%d) lower than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
|
||||
(*c.odm_txxtaltrack_set_xtal)(dm);
|
||||
}
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* Wait sacn to do IQK by RF Jenyu*/
|
||||
if ((!*dm->is_scan_in_process) && (!iqk_info->rfk_forbidden)) {
|
||||
/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
|
||||
if (delta_IQK >= c.threshold_iqk) {
|
||||
cali_info->thermal_value_iqk = thermal_value;
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
|
||||
if (!cali_info->is_iqk_in_progress)
|
||||
(*c.do_iqk)(dm, delta_IQK, thermal_value, 8);
|
||||
}
|
||||
}
|
||||
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n");
|
||||
|
||||
cali_info->tx_powercount = 0;
|
||||
}
|
||||
|
||||
/* 3============================================================
|
||||
* 3 IQ Calibration
|
||||
* 3============================================================
|
||||
*/
|
||||
|
||||
void
|
||||
odm_reset_iqk_result(
|
||||
void *dm_void
|
||||
)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
odm_iq_calibrate(
|
||||
struct dm_struct *dm
|
||||
)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void phydm_rf_init(void *dm_void)
|
||||
{
|
||||
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
||||
|
||||
odm_txpowertracking_init(dm);
|
||||
|
||||
odm_clear_txpowertracking_state(dm);
|
||||
}
|
||||
|
||||
void phydm_rf_watchdog(void *dm_void)
|
||||
{
|
||||
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
||||
|
||||
odm_txpowertracking_check(dm);
|
||||
}
|
||||
124
hal/phydm/halrf/halphyrf_iot.h
Normal file
124
hal/phydm/halrf/halphyrf_iot.h
Normal file
@@ -0,0 +1,124 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __HALPHYRF_H__
|
||||
#define __HALPHYRF_H__
|
||||
|
||||
#include "halrf/halrf_kfree.h"
|
||||
|
||||
#if (RTL8821C_SUPPORT == 1)
|
||||
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8195B_SUPPORT == 1)
|
||||
// #include "halrf/rtl8195b/halrf.h"
|
||||
#include "halrf/rtl8195b/halrf_iqk_8195b.h"
|
||||
#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
|
||||
#include "halrf/rtl8195b/halrf_dpk_8195b.h"
|
||||
#endif
|
||||
|
||||
#include "halrf/halrf_powertracking_iot.h"
|
||||
|
||||
|
||||
enum spur_cal_method {
|
||||
PLL_RESET,
|
||||
AFE_PHASE_SEL
|
||||
};
|
||||
|
||||
enum pwrtrack_method {
|
||||
BBSWING,
|
||||
TXAGC,
|
||||
MIX_MODE,
|
||||
TSSI_MODE,
|
||||
MIX_2G_TSSI_5G_MODE,
|
||||
MIX_5G_TSSI_2G_MODE
|
||||
};
|
||||
|
||||
typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
|
||||
typedef void(*func_iqk)(void *, u8, u8, u8);
|
||||
typedef void (*func_lck)(void *);
|
||||
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
|
||||
typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
|
||||
typedef void(*func_swing_xtal)(void *, s8 **, s8 **);
|
||||
typedef void(*func_set_xtal)(void *);
|
||||
|
||||
struct txpwrtrack_cfg {
|
||||
u8 swing_table_size_cck;
|
||||
u8 swing_table_size_ofdm;
|
||||
u8 threshold_iqk;
|
||||
u8 threshold_dpk;
|
||||
u8 average_thermal_num;
|
||||
u8 rf_path_count;
|
||||
u32 thermal_reg_addr;
|
||||
func_set_pwr odm_tx_pwr_track_set_pwr;
|
||||
func_iqk do_iqk;
|
||||
func_lck phy_lc_calibrate;
|
||||
func_swing get_delta_swing_table;
|
||||
func_swing8814only get_delta_swing_table8814only;
|
||||
func_swing_xtal get_delta_swing_xtal_table;
|
||||
func_set_xtal odm_txxtaltrack_set_xtal;
|
||||
};
|
||||
|
||||
void
|
||||
configure_txpower_track(
|
||||
void *dm_void,
|
||||
struct txpwrtrack_cfg *config
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
odm_clear_txpowertracking_state(
|
||||
void *dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
void *dm_void
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
void *dm
|
||||
#else
|
||||
void *adapter
|
||||
#endif
|
||||
);
|
||||
|
||||
|
||||
|
||||
#define ODM_TARGET_CHNL_NUM_2G_5G 59
|
||||
|
||||
|
||||
void
|
||||
odm_reset_iqk_result(
|
||||
void *dm_void
|
||||
);
|
||||
u8
|
||||
odm_get_right_chnl_place_for_iqk(
|
||||
u8 chnl
|
||||
);
|
||||
|
||||
void phydm_rf_init(void *dm_void);
|
||||
void phydm_rf_watchdog(void *dm_void);
|
||||
|
||||
#endif /*#ifndef __HALPHYRF_H__*/
|
||||
@@ -94,6 +94,16 @@ void configure_txpower_track(
|
||||
configure_txpower_track_8821c(config);
|
||||
#endif
|
||||
|
||||
#if RTL8192F_SUPPORT
|
||||
if (dm->support_ic_type == ODM_RTL8192F)
|
||||
configure_txpower_track_8192f(config);
|
||||
#endif
|
||||
|
||||
#if RTL8822C_SUPPORT
|
||||
if (dm->support_ic_type == ODM_RTL8822C)
|
||||
configure_txpower_track_8822c(config);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/* **********************************************************************
|
||||
@@ -166,7 +176,7 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
|
||||
s8 diff_DPK[4] = {0};
|
||||
u8 thermal_value_avg_count = 0;
|
||||
u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
|
||||
u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4, regc88, rege14, reg848,reg838, reg86c;
|
||||
|
||||
u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
|
||||
u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */
|
||||
@@ -201,7 +211,7 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
(*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
|
||||
(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
|
||||
/* JJ ADD 20161014 */
|
||||
if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) /*for Xtal Offset*/
|
||||
if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F)) /*for Xtal Offset*/
|
||||
(*c.get_delta_swing_xtal_table)(dm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down);
|
||||
|
||||
|
||||
@@ -220,17 +230,17 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
cali_info->rega24 = 0x090e1317;
|
||||
#endif
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
|
||||
cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"cali_info->txpowertrack_control=%d, hal_data->eeprom_thermal_meter %d\n", cali_info->txpowertrack_control, hal_data->eeprom_thermal_meter);
|
||||
thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
|
||||
|
||||
thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"thermal_value_temp(%d) = thermal_value(%d) + power_time_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));
|
||||
|
||||
if (thermal_value_temp > 63)
|
||||
@@ -242,34 +252,46 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
|
||||
/*add log by zhao he, check c80/c94/c14/ca0 value*/
|
||||
if (dm->support_ic_type == ODM_RTL8723D) {
|
||||
regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD);
|
||||
regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD);
|
||||
regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD);
|
||||
regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF);
|
||||
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
|
||||
regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
|
||||
regcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD);
|
||||
regcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD);
|
||||
regab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF);
|
||||
RF_DBG(dm, DBG_RF_IQK, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
|
||||
}
|
||||
|
||||
/* JJ ADD 20161014 */
|
||||
if (dm->support_ic_type == ODM_RTL8710B) {
|
||||
regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD);
|
||||
regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD);
|
||||
regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD);
|
||||
regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF);
|
||||
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
|
||||
regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
|
||||
regcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD);
|
||||
regcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD);
|
||||
regab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF);
|
||||
RF_DBG(dm, DBG_RF_IQK, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
|
||||
}
|
||||
/* Winnita add 20171205 */
|
||||
if (dm->support_ic_type == ODM_RTL8192F) {
|
||||
regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
|
||||
regc88 = odm_get_bb_reg(dm, R_0xc88, MASKDWORD);
|
||||
regab4 = odm_get_bb_reg(dm, R_0xab4, MASKDWORD);
|
||||
rege14 = odm_get_bb_reg(dm, R_0xe14, MASKDWORD);
|
||||
reg848 = odm_get_bb_reg(dm, R_0x848, MASKDWORD);
|
||||
reg838 = odm_get_bb_reg(dm, R_0x838, MASKDWORD);
|
||||
reg86c = odm_get_bb_reg(dm, R_0x86c, MASKDWORD);
|
||||
RF_DBG(dm, DBG_RF_IQK, "0xc80 = 0x%x 0xc88 = 0x%x 0xab4 = 0x%x 0xe14 = 0x%x\n", regc80, regc88, regab4, rege14);
|
||||
RF_DBG(dm, DBG_RF_IQK, "0x848 = 0x%x 0x838 = 0x%x 0x86c = 0x%x\n", reg848, reg838, reg86c);
|
||||
}
|
||||
|
||||
if (!cali_info->txpowertrack_control)
|
||||
return;
|
||||
|
||||
if (hal_data->eeprom_thermal_meter == 0xff) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", hal_data->eeprom_thermal_meter);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", hal_data->eeprom_thermal_meter);
|
||||
return;
|
||||
}
|
||||
|
||||
/*4 3. Initialize ThermalValues of rf_calibrate_info*/
|
||||
|
||||
if (cali_info->is_reloadtxpowerindex)
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "reload ofdm index for band switch\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "reload ofdm index for band switch\n");
|
||||
|
||||
/*4 4. Calculate average thermal meter*/
|
||||
|
||||
@@ -288,7 +310,7 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */
|
||||
thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
|
||||
cali_info->thermal_value_delta = thermal_value - hal_data->eeprom_thermal_meter;
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, hal_data->eeprom_thermal_meter);
|
||||
}
|
||||
|
||||
@@ -302,7 +324,7 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
if (cali_info->thermal_value_iqk == 0xff) { /*no PG, use thermal value for IQK*/
|
||||
cali_info->thermal_value_iqk = thermal_value;
|
||||
delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no PG, use thermal_value for IQK\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no PG, use thermal_value for IQK\n");
|
||||
}
|
||||
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
@@ -312,7 +334,7 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
|
||||
if (!(dm->support_ic_type & ODM_RTL8821)) { /*no PG, do LCK at initial status*/
|
||||
if (cali_info->thermal_value_lck == 0xff) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no PG, do LCK\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no PG, do LCK\n");
|
||||
cali_info->thermal_value_lck = thermal_value;
|
||||
|
||||
/*Use RTLCK, so close power tracking driver LCK*/
|
||||
@@ -324,13 +346,13 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
|
||||
}
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
|
||||
|
||||
/* Wait sacn to do LCK by RF Jenyu*/
|
||||
if( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
|
||||
/* Delta temperature is equal to or larger than 20 centigrade.*/
|
||||
if (delta_LCK >= c.threshold_iqk) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
|
||||
cali_info->thermal_value_lck = thermal_value;
|
||||
|
||||
/*Use RTLCK, so close power tracking driver LCK*/
|
||||
@@ -366,51 +388,51 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
|
||||
switch (p) {
|
||||
case RF_PATH_B:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
|
||||
|
||||
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta];
|
||||
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
|
||||
case RF_PATH_C:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]);
|
||||
|
||||
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta];
|
||||
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
|
||||
case RF_PATH_D:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]);
|
||||
|
||||
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta];
|
||||
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
|
||||
default:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
|
||||
|
||||
cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
|
||||
cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* JJ ADD 20161014 */
|
||||
if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
|
||||
if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F)) {
|
||||
/*Save xtal_offset from Xtal table*/
|
||||
cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]);
|
||||
cali_info->xtal_offset = delta_swing_table_xtal_up[delta];
|
||||
|
||||
@@ -426,47 +448,47 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
|
||||
switch (p) {
|
||||
case RF_PATH_B:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
|
||||
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
|
||||
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
|
||||
case RF_PATH_C:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]);
|
||||
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta];
|
||||
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
|
||||
case RF_PATH_D:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]);
|
||||
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta];
|
||||
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
|
||||
default:
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
|
||||
cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
|
||||
cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* JJ ADD 20161014 */
|
||||
if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
|
||||
if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F)) {
|
||||
/*Save xtal_offset from Xtal table*/
|
||||
cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]);
|
||||
cali_info->xtal_offset = delta_swing_table_xtal_down[delta];
|
||||
|
||||
@@ -479,7 +501,7 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
}
|
||||
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p);
|
||||
|
||||
if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/
|
||||
@@ -487,7 +509,7 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
else
|
||||
cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]);
|
||||
|
||||
cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];
|
||||
@@ -498,9 +520,9 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
|
||||
/*************Print BB Swing base and index Offset*************/
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]);
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]);
|
||||
|
||||
/*4 7.1 Handle boundary conditions of index.*/
|
||||
@@ -511,7 +533,7 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
cali_info->OFDM_index[p] = OFDM_min_index;
|
||||
}
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"\n\n========================================================================================================\n");
|
||||
|
||||
if (cali_info->CCK_index > c.swing_table_size_cck - 1)
|
||||
@@ -519,7 +541,7 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
else if (cali_info->CCK_index <= 0)
|
||||
cali_info->CCK_index = 0;
|
||||
} else {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n",
|
||||
cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value);
|
||||
|
||||
@@ -527,33 +549,33 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
cali_info->power_index_offset[p] = 0;
|
||||
}
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
|
||||
cali_info->CCK_index, cali_info->bb_swing_idx_cck_base); /*Print Swing base & current*/
|
||||
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
|
||||
cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]);
|
||||
}
|
||||
|
||||
if ((dm->support_ic_type & ODM_RTL8814A)) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "power_tracking_type=%d\n", power_tracking_type);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "power_tracking_type=%d\n", power_tracking_type);
|
||||
|
||||
if (power_tracking_type == 0) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
|
||||
} else if (power_tracking_type == 1) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n");
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_2G_TSSI_5G_MODE, p, 0);
|
||||
} else if (power_tracking_type == 2) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n");
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_5G_TSSI_2G_MODE, p, 0);
|
||||
} else if (power_tracking_type == 3) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI MODE**********\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI MODE**********\n");
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0);
|
||||
}
|
||||
@@ -574,13 +596,13 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
|
||||
if (thermal_value > cali_info->thermal_value) {
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
|
||||
p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);
|
||||
}
|
||||
} else if (thermal_value < cali_info->thermal_value) { /*Low temperature*/
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
|
||||
p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);
|
||||
}
|
||||
@@ -592,36 +614,37 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
if (thermal_value > dm->priv->pmib->dot11RFEntry.ther)
|
||||
#endif
|
||||
{
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
|
||||
|
||||
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
|
||||
dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
|
||||
dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
|
||||
dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
|
||||
dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B ||
|
||||
dm->support_ic_type == ODM_RTL8192F) {
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
|
||||
} else {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
|
||||
}
|
||||
} else {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
|
||||
|
||||
if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
|
||||
dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
|
||||
dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
|
||||
dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
|
||||
dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B ||
|
||||
dm->support_ic_type == ODM_RTL8192F) {
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel);
|
||||
} else {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
|
||||
}
|
||||
@@ -632,7 +655,7 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
for (p = RF_PATH_A; p < c.rf_path_count; p++)
|
||||
cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"cali_info->thermal_value = %d thermal_value= %d\n", cali_info->thermal_value, thermal_value);
|
||||
|
||||
cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
|
||||
@@ -640,27 +663,28 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
}
|
||||
|
||||
|
||||
if (dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
|
||||
if (dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D ||
|
||||
dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
|
||||
|
||||
if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (thermal_value > hal_data->eeprom_thermal_meter) {
|
||||
#else
|
||||
if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
|
||||
#endif
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
|
||||
(*c.odm_txxtaltrack_set_xtal)(dm);
|
||||
} else {
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
|
||||
"Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
|
||||
(*c.odm_txxtaltrack_set_xtal)(dm);
|
||||
}
|
||||
}
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
|
||||
}
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
@@ -671,7 +695,7 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
|
||||
if (delta_IQK >= c.threshold_iqk) {
|
||||
cali_info->thermal_value_iqk = thermal_value;
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
|
||||
if (!cali_info->is_iqk_in_progress)
|
||||
(*c.do_iqk)(dm, delta_IQK, thermal_value, 8);
|
||||
}
|
||||
@@ -679,42 +703,42 @@ odm_txpowertracking_callback_thermal_meter(
|
||||
}
|
||||
if (cali_info->dpk_thermal[RF_PATH_A] != 0) {
|
||||
if (diff_DPK[RF_PATH_A] >= c.threshold_dpk) {
|
||||
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk));
|
||||
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
|
||||
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk));
|
||||
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
|
||||
} else if ((diff_DPK[RF_PATH_A] <= -1 * c.threshold_dpk)) {
|
||||
s32 value = 0x20 + (diff_DPK[RF_PATH_A] / c.threshold_dpk);
|
||||
|
||||
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
|
||||
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
|
||||
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
|
||||
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
|
||||
} else {
|
||||
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
|
||||
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
|
||||
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
|
||||
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
|
||||
}
|
||||
}
|
||||
if (cali_info->dpk_thermal[RF_PATH_B] != 0) {
|
||||
if (diff_DPK[RF_PATH_B] >= c.threshold_dpk) {
|
||||
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk));
|
||||
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
|
||||
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk));
|
||||
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
|
||||
} else if ((diff_DPK[RF_PATH_B] <= -1 * c.threshold_dpk)) {
|
||||
s32 value = 0x20 + (diff_DPK[RF_PATH_B] / c.threshold_dpk);
|
||||
|
||||
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
|
||||
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
|
||||
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
|
||||
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
|
||||
} else {
|
||||
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
|
||||
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
|
||||
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
|
||||
odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n");
|
||||
RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n");
|
||||
|
||||
cali_info->tx_powercount = 0;
|
||||
}
|
||||
@@ -760,7 +784,7 @@ odm_iq_calibrate(
|
||||
void *adapter = dm->adapter;
|
||||
struct dm_iqk_info *iqk_info = &dm->IQK_info;
|
||||
|
||||
RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("=>%s\n" , __FUNCTION__));
|
||||
RF_DBG(dm, DBG_RF_IQK, "=>%s\n",__FUNCTION__);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
if (*dm->is_fcs_mode_enable)
|
||||
@@ -768,8 +792,8 @@ odm_iq_calibrate(
|
||||
#endif
|
||||
|
||||
if ((dm->is_linked) && (!iqk_info->rfk_forbidden)) {
|
||||
RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("interval=%d ch=%d prech=%d scan=%s\n", dm->linked_interval,
|
||||
*dm->channel, dm->pre_channel, *dm->is_scan_in_process == TRUE ? "TRUE":"FALSE"));
|
||||
RF_DBG(dm, DBG_RF_IQK, "interval=%d ch=%d prech=%d scan=%s\n", dm->linked_interval,
|
||||
*dm->channel, dm->pre_channel, *dm->is_scan_in_process == TRUE ? "TRUE":"FALSE");
|
||||
|
||||
if (*dm->channel != dm->pre_channel) {
|
||||
dm->pre_channel = *dm->channel;
|
||||
@@ -780,12 +804,12 @@ odm_iq_calibrate(
|
||||
dm->linked_interval++;
|
||||
|
||||
if (dm->linked_interval == 2)
|
||||
PHY_IQCalibrate((PADAPTER)adapter, false);
|
||||
PHY_IQCalibrate(adapter, false);
|
||||
} else
|
||||
dm->linked_interval = 0;
|
||||
|
||||
RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("<=%s interval=%d ch=%d prech=%d scan=%s\n", __FUNCTION__, dm->linked_interval,
|
||||
*dm->channel, dm->pre_channel, *dm->is_scan_in_process == TRUE?"TRUE":"FALSE"));
|
||||
RF_DBG(dm, DBG_RF_IQK, "<=%s interval=%d ch=%d prech=%d scan=%s\n", __FUNCTION__, dm->linked_interval,
|
||||
*dm->channel, dm->pre_channel, *dm->is_scan_in_process == TRUE?"TRUE":"FALSE");
|
||||
}
|
||||
|
||||
void phydm_rf_init(struct dm_struct *dm)
|
||||
|
||||
@@ -13,43 +13,33 @@
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __HAL_PHY_RF_H__
|
||||
#define __HAL_PHY_RF_H__
|
||||
#ifndef __HALPHYRF_H__
|
||||
#define __HALPHYRF_H__
|
||||
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
#if RT_PLATFORM == PLATFORM_MACOSX
|
||||
#include "rtl8814a/halrf_iqk_8814a.h"
|
||||
#else
|
||||
#include "halrf/rtl8814a/halrf_iqk_8814a.h"
|
||||
#endif
|
||||
#include "halrf/rtl8814a/halrf_iqk_8814a.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#if RT_PLATFORM == PLATFORM_MACOSX
|
||||
#include "rtl8822b/halrf_iqk_8822b.h"
|
||||
#include "../../MAC/Halmac_type.h"
|
||||
#else
|
||||
#include "halrf/rtl8822b/halrf_iqk_8822b.h"
|
||||
#include "../mac/Halmac_type.h"
|
||||
#endif
|
||||
#include "halrf/rtl8822b/halrf_iqk_8822b.h"
|
||||
#include "../mac/Halmac_type.h"
|
||||
#endif
|
||||
|
||||
#if RT_PLATFORM == PLATFORM_MACOSX
|
||||
#include "halrf_powertracking_win.h"
|
||||
#include "halrf_kfree.h"
|
||||
#include "halrf_txgapcal.h"
|
||||
#else
|
||||
#include "halrf/halrf_powertracking_win.h"
|
||||
#include "halrf/halrf_kfree.h"
|
||||
#include "halrf/halrf_txgapcal.h"
|
||||
#endif
|
||||
|
||||
#include "halrf/halrf_powertracking_win.h"
|
||||
#include "halrf/halrf_kfree.h"
|
||||
#include "halrf/halrf_txgapcal.h"
|
||||
#if (RTL8821C_SUPPORT == 1)
|
||||
#if RT_PLATFORM == PLATFORM_MACOSX
|
||||
#include "rtl8821c/halrf_iqk_8821c.h"
|
||||
#else
|
||||
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
|
||||
#endif
|
||||
#include "halrf/rtl8821c/halrf_iqk_8821c.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8195B_SUPPORT == 1)
|
||||
// #include "halrf/rtl8195b/halrf.h"
|
||||
#include "halrf/rtl8195b/halrf_iqk_8195b.h"
|
||||
#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
|
||||
#include "halrf/rtl8195b/halrf_dpk_8195b.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8814B_SUPPORT == 1)
|
||||
#include "halrf/rtl8814b/halrf_iqk_8814b.h"
|
||||
#endif
|
||||
|
||||
enum spur_cal_method {
|
||||
@@ -132,4 +122,4 @@ void odm_iq_calibrate(struct dm_struct *dm);
|
||||
void phydm_rf_init(struct dm_struct *dm);
|
||||
void phydm_rf_watchdog(struct dm_struct *dm);
|
||||
|
||||
#endif /* #ifndef __HAL_PHY_RF_H__ */
|
||||
#endif /*#ifndef __HALPHYRF_H__*/
|
||||
|
||||
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Reference in New Issue
Block a user